Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 14:50:12.893863 lava-dispatcher, installed at version: 2024.03
2 14:50:12.894057 start: 0 validate
3 14:50:12.894193 Start time: 2024-06-04 14:50:12.894184+00:00 (UTC)
4 14:50:12.894316 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:50:12.894448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:50:13.152772 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:50:13.152939 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:50:13.410165 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:50:13.410376 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:50:13.667117 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:50:13.667311 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:50:13.923901 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:50:13.924080 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:50:14.182391 validate duration: 1.29
16 14:50:14.182672 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:50:14.182778 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:50:14.182894 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:50:14.183018 Not decompressing ramdisk as can be used compressed.
20 14:50:14.183103 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:50:14.183168 saving as /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/ramdisk/initrd.cpio.gz
22 14:50:14.183239 total size: 5628169 (5 MB)
23 14:50:14.184286 progress 0 % (0 MB)
24 14:50:14.185973 progress 5 % (0 MB)
25 14:50:14.187551 progress 10 % (0 MB)
26 14:50:14.188971 progress 15 % (0 MB)
27 14:50:14.190775 progress 20 % (1 MB)
28 14:50:14.192549 progress 25 % (1 MB)
29 14:50:14.194277 progress 30 % (1 MB)
30 14:50:14.195957 progress 35 % (1 MB)
31 14:50:14.197497 progress 40 % (2 MB)
32 14:50:14.199050 progress 45 % (2 MB)
33 14:50:14.200492 progress 50 % (2 MB)
34 14:50:14.202073 progress 55 % (2 MB)
35 14:50:14.203601 progress 60 % (3 MB)
36 14:50:14.205206 progress 65 % (3 MB)
37 14:50:14.207027 progress 70 % (3 MB)
38 14:50:14.208573 progress 75 % (4 MB)
39 14:50:14.210209 progress 80 % (4 MB)
40 14:50:14.211739 progress 85 % (4 MB)
41 14:50:14.213494 progress 90 % (4 MB)
42 14:50:14.215168 progress 95 % (5 MB)
43 14:50:14.216737 progress 100 % (5 MB)
44 14:50:14.216950 5 MB downloaded in 0.03 s (159.20 MB/s)
45 14:50:14.217135 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:50:14.217415 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:50:14.217503 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:50:14.217588 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:50:14.217732 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:50:14.217813 saving as /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/kernel/Image
52 14:50:14.217876 total size: 54682112 (52 MB)
53 14:50:14.217939 No compression specified
54 14:50:14.219088 progress 0 % (0 MB)
55 14:50:14.234221 progress 5 % (2 MB)
56 14:50:14.248666 progress 10 % (5 MB)
57 14:50:14.263577 progress 15 % (7 MB)
58 14:50:14.277845 progress 20 % (10 MB)
59 14:50:14.292171 progress 25 % (13 MB)
60 14:50:14.306503 progress 30 % (15 MB)
61 14:50:14.320884 progress 35 % (18 MB)
62 14:50:14.335092 progress 40 % (20 MB)
63 14:50:14.349244 progress 45 % (23 MB)
64 14:50:14.363583 progress 50 % (26 MB)
65 14:50:14.377720 progress 55 % (28 MB)
66 14:50:14.391968 progress 60 % (31 MB)
67 14:50:14.406329 progress 65 % (33 MB)
68 14:50:14.420961 progress 70 % (36 MB)
69 14:50:14.435343 progress 75 % (39 MB)
70 14:50:14.450056 progress 80 % (41 MB)
71 14:50:14.464697 progress 85 % (44 MB)
72 14:50:14.479023 progress 90 % (46 MB)
73 14:50:14.493428 progress 95 % (49 MB)
74 14:50:14.507641 progress 100 % (52 MB)
75 14:50:14.507901 52 MB downloaded in 0.29 s (179.81 MB/s)
76 14:50:14.508084 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:50:14.508431 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:50:14.508520 start: 1.3 download-retry (timeout 00:10:00) [common]
80 14:50:14.508608 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 14:50:14.508750 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:50:14.508821 saving as /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/dtb/mt8192-asurada-spherion-r0.dtb
83 14:50:14.508884 total size: 47258 (0 MB)
84 14:50:14.508948 No compression specified
85 14:50:14.510091 progress 69 % (0 MB)
86 14:50:14.510399 progress 100 % (0 MB)
87 14:50:14.510566 0 MB downloaded in 0.00 s (26.85 MB/s)
88 14:50:14.510696 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:50:14.510927 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:50:14.511015 start: 1.4 download-retry (timeout 00:10:00) [common]
92 14:50:14.511100 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 14:50:14.511220 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:50:14.511290 saving as /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/nfsrootfs/full.rootfs.tar
95 14:50:14.511352 total size: 120894716 (115 MB)
96 14:50:14.511415 Using unxz to decompress xz
97 14:50:14.515627 progress 0 % (0 MB)
98 14:50:14.883611 progress 5 % (5 MB)
99 14:50:15.262178 progress 10 % (11 MB)
100 14:50:15.622453 progress 15 % (17 MB)
101 14:50:15.955391 progress 20 % (23 MB)
102 14:50:16.257484 progress 25 % (28 MB)
103 14:50:16.624656 progress 30 % (34 MB)
104 14:50:16.972767 progress 35 % (40 MB)
105 14:50:17.147591 progress 40 % (46 MB)
106 14:50:17.331905 progress 45 % (51 MB)
107 14:50:17.660810 progress 50 % (57 MB)
108 14:50:18.052916 progress 55 % (63 MB)
109 14:50:18.416941 progress 60 % (69 MB)
110 14:50:18.769921 progress 65 % (74 MB)
111 14:50:19.121208 progress 70 % (80 MB)
112 14:50:19.480993 progress 75 % (86 MB)
113 14:50:19.825020 progress 80 % (92 MB)
114 14:50:20.168256 progress 85 % (98 MB)
115 14:50:20.528420 progress 90 % (103 MB)
116 14:50:20.861750 progress 95 % (109 MB)
117 14:50:21.224233 progress 100 % (115 MB)
118 14:50:21.229684 115 MB downloaded in 6.72 s (17.16 MB/s)
119 14:50:21.229992 end: 1.4.1 http-download (duration 00:00:07) [common]
121 14:50:21.230415 end: 1.4 download-retry (duration 00:00:07) [common]
122 14:50:21.230539 start: 1.5 download-retry (timeout 00:09:53) [common]
123 14:50:21.230656 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 14:50:21.230839 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:50:21.230938 saving as /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/modules/modules.tar
126 14:50:21.231030 total size: 8608920 (8 MB)
127 14:50:21.231123 Using unxz to decompress xz
128 14:50:21.235908 progress 0 % (0 MB)
129 14:50:21.255605 progress 5 % (0 MB)
130 14:50:21.283649 progress 10 % (0 MB)
131 14:50:21.314673 progress 15 % (1 MB)
132 14:50:21.339322 progress 20 % (1 MB)
133 14:50:21.364028 progress 25 % (2 MB)
134 14:50:21.388407 progress 30 % (2 MB)
135 14:50:21.413431 progress 35 % (2 MB)
136 14:50:21.440798 progress 40 % (3 MB)
137 14:50:21.464197 progress 45 % (3 MB)
138 14:50:21.489607 progress 50 % (4 MB)
139 14:50:21.516147 progress 55 % (4 MB)
140 14:50:21.541673 progress 60 % (4 MB)
141 14:50:21.566531 progress 65 % (5 MB)
142 14:50:21.593165 progress 70 % (5 MB)
143 14:50:21.620969 progress 75 % (6 MB)
144 14:50:21.649059 progress 80 % (6 MB)
145 14:50:21.674874 progress 85 % (7 MB)
146 14:50:21.700963 progress 90 % (7 MB)
147 14:50:21.727249 progress 95 % (7 MB)
148 14:50:21.753322 progress 100 % (8 MB)
149 14:50:21.758977 8 MB downloaded in 0.53 s (15.55 MB/s)
150 14:50:21.759233 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:50:21.759519 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:50:21.759615 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 14:50:21.759712 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 14:50:25.308299 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba
156 14:50:25.308496 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 14:50:25.308603 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 14:50:25.308772 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4
159 14:50:25.308902 makedir: /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin
160 14:50:25.309003 makedir: /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/tests
161 14:50:25.309101 makedir: /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/results
162 14:50:25.309201 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-add-keys
163 14:50:25.309345 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-add-sources
164 14:50:25.309476 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-background-process-start
165 14:50:25.309604 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-background-process-stop
166 14:50:25.309732 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-common-functions
167 14:50:25.309857 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-echo-ipv4
168 14:50:25.309981 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-install-packages
169 14:50:25.310104 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-installed-packages
170 14:50:25.310227 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-os-build
171 14:50:25.310350 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-probe-channel
172 14:50:25.310474 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-probe-ip
173 14:50:25.310597 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-target-ip
174 14:50:25.310718 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-target-mac
175 14:50:25.310839 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-target-storage
176 14:50:25.310963 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-case
177 14:50:25.311094 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-event
178 14:50:25.311222 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-feedback
179 14:50:25.311345 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-raise
180 14:50:25.311469 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-reference
181 14:50:25.311593 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-runner
182 14:50:25.311716 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-set
183 14:50:25.311839 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-test-shell
184 14:50:25.311963 Updating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-add-keys (debian)
185 14:50:25.312114 Updating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-add-sources (debian)
186 14:50:25.312252 Updating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-install-packages (debian)
187 14:50:25.312517 Updating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-installed-packages (debian)
188 14:50:25.312658 Updating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/bin/lava-os-build (debian)
189 14:50:25.312779 Creating /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/environment
190 14:50:25.312879 LAVA metadata
191 14:50:25.312946 - LAVA_JOB_ID=14167012
192 14:50:25.313009 - LAVA_DISPATCHER_IP=192.168.201.1
193 14:50:25.313110 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 14:50:25.313176 skipped lava-vland-overlay
195 14:50:25.313249 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 14:50:25.313328 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 14:50:25.313388 skipped lava-multinode-overlay
198 14:50:25.313459 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 14:50:25.313538 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 14:50:25.313613 Loading test definitions
201 14:50:25.313704 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 14:50:25.313785 Using /lava-14167012 at stage 0
203 14:50:25.314061 uuid=14167012_1.6.2.3.1 testdef=None
204 14:50:25.314148 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 14:50:25.314231 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 14:50:25.314683 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 14:50:25.314907 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 14:50:25.315469 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 14:50:25.315700 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 14:50:25.316245 runner path: /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/0/tests/0_timesync-off test_uuid 14167012_1.6.2.3.1
213 14:50:25.316410 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 14:50:25.316644 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 14:50:25.316716 Using /lava-14167012 at stage 0
217 14:50:25.316819 Fetching tests from https://github.com/kernelci/test-definitions.git
218 14:50:25.316906 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/0/tests/1_kselftest-tpm2'
219 14:50:27.356048 Running '/usr/bin/git checkout kernelci.org
220 14:50:27.506779 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 14:50:27.507544 uuid=14167012_1.6.2.3.5 testdef=None
222 14:50:27.507703 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 14:50:27.507957 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 14:50:27.508734 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 14:50:27.508979 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 14:50:27.510012 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 14:50:27.510263 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 14:50:27.511221 runner path: /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/0/tests/1_kselftest-tpm2 test_uuid 14167012_1.6.2.3.5
232 14:50:27.511316 BOARD='mt8192-asurada-spherion-r0'
233 14:50:27.511382 BRANCH='cip'
234 14:50:27.511443 SKIPFILE='/dev/null'
235 14:50:27.511502 SKIP_INSTALL='True'
236 14:50:27.511585 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 14:50:27.511649 TST_CASENAME=''
238 14:50:27.511707 TST_CMDFILES='tpm2'
239 14:50:27.511852 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 14:50:27.512067 Creating lava-test-runner.conf files
242 14:50:27.512133 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167012/lava-overlay-5j48cel4/lava-14167012/0 for stage 0
243 14:50:27.512226 - 0_timesync-off
244 14:50:27.512296 - 1_kselftest-tpm2
245 14:50:27.512404 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 14:50:27.512497 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 14:50:35.304926 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 14:50:35.305123 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 14:50:35.305245 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 14:50:35.305347 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 14:50:35.305441 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 14:50:35.479946 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 14:50:35.480344 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 14:50:35.480468 extracting modules file /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba
255 14:50:35.709639 extracting modules file /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167012/extract-overlay-ramdisk-if8kdf0c/ramdisk
256 14:50:35.934762 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 14:50:35.934934 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 14:50:35.935038 [common] Applying overlay to NFS
259 14:50:35.935112 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167012/compress-overlay-7wjrg313/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba
260 14:50:36.890249 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 14:50:36.890416 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 14:50:36.890518 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 14:50:36.890606 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 14:50:36.890690 Building ramdisk /var/lib/lava/dispatcher/tmp/14167012/extract-overlay-ramdisk-if8kdf0c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167012/extract-overlay-ramdisk-if8kdf0c/ramdisk
265 14:50:37.201325 >> 130335 blocks
266 14:50:39.360934 rename /var/lib/lava/dispatcher/tmp/14167012/extract-overlay-ramdisk-if8kdf0c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/ramdisk/ramdisk.cpio.gz
267 14:50:39.361369 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 14:50:39.361516 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 14:50:39.361624 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 14:50:39.361739 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/kernel/Image']
271 14:50:52.831804 Returned 0 in 13 seconds
272 14:50:52.932866 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/kernel/image.itb
273 14:50:53.327118 output: FIT description: Kernel Image image with one or more FDT blobs
274 14:50:53.327480 output: Created: Tue Jun 4 15:50:53 2024
275 14:50:53.327557 output: Image 0 (kernel-1)
276 14:50:53.327626 output: Description:
277 14:50:53.327690 output: Created: Tue Jun 4 15:50:53 2024
278 14:50:53.327761 output: Type: Kernel Image
279 14:50:53.327823 output: Compression: lzma compressed
280 14:50:53.327882 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
281 14:50:53.327938 output: Architecture: AArch64
282 14:50:53.327996 output: OS: Linux
283 14:50:53.328050 output: Load Address: 0x00000000
284 14:50:53.328106 output: Entry Point: 0x00000000
285 14:50:53.328168 output: Hash algo: crc32
286 14:50:53.328247 output: Hash value: 88dcd836
287 14:50:53.328302 output: Image 1 (fdt-1)
288 14:50:53.328362 output: Description: mt8192-asurada-spherion-r0
289 14:50:53.328431 output: Created: Tue Jun 4 15:50:53 2024
290 14:50:53.328485 output: Type: Flat Device Tree
291 14:50:53.328538 output: Compression: uncompressed
292 14:50:53.328589 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 14:50:53.328642 output: Architecture: AArch64
294 14:50:53.328694 output: Hash algo: crc32
295 14:50:53.328745 output: Hash value: 0f8e4d2e
296 14:50:53.328796 output: Image 2 (ramdisk-1)
297 14:50:53.328848 output: Description: unavailable
298 14:50:53.328900 output: Created: Tue Jun 4 15:50:53 2024
299 14:50:53.328952 output: Type: RAMDisk Image
300 14:50:53.329003 output: Compression: Unknown Compression
301 14:50:53.329064 output: Data Size: 18732471 Bytes = 18293.43 KiB = 17.86 MiB
302 14:50:53.329118 output: Architecture: AArch64
303 14:50:53.329169 output: OS: Linux
304 14:50:53.329220 output: Load Address: unavailable
305 14:50:53.329281 output: Entry Point: unavailable
306 14:50:53.329333 output: Hash algo: crc32
307 14:50:53.329394 output: Hash value: 51f26391
308 14:50:53.329447 output: Default Configuration: 'conf-1'
309 14:50:53.329499 output: Configuration 0 (conf-1)
310 14:50:53.329550 output: Description: mt8192-asurada-spherion-r0
311 14:50:53.329602 output: Kernel: kernel-1
312 14:50:53.329654 output: Init Ramdisk: ramdisk-1
313 14:50:53.329705 output: FDT: fdt-1
314 14:50:53.329757 output: Loadables: kernel-1
315 14:50:53.329808 output:
316 14:50:53.330014 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 14:50:53.330115 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 14:50:53.330222 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 14:50:53.330315 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 14:50:53.330390 No LXC device requested
321 14:50:53.330466 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 14:50:53.330551 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 14:50:53.330628 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 14:50:53.330693 Checking files for TFTP limit of 4294967296 bytes.
325 14:50:53.331189 end: 1 tftp-deploy (duration 00:00:39) [common]
326 14:50:53.331296 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 14:50:53.331385 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 14:50:53.331508 substitutions:
329 14:50:53.331573 - {DTB}: 14167012/tftp-deploy-q261glni/dtb/mt8192-asurada-spherion-r0.dtb
330 14:50:53.331635 - {INITRD}: 14167012/tftp-deploy-q261glni/ramdisk/ramdisk.cpio.gz
331 14:50:53.331692 - {KERNEL}: 14167012/tftp-deploy-q261glni/kernel/Image
332 14:50:53.331749 - {LAVA_MAC}: None
333 14:50:53.331804 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba
334 14:50:53.331859 - {NFS_SERVER_IP}: 192.168.201.1
335 14:50:53.331912 - {PRESEED_CONFIG}: None
336 14:50:53.331966 - {PRESEED_LOCAL}: None
337 14:50:53.332019 - {RAMDISK}: 14167012/tftp-deploy-q261glni/ramdisk/ramdisk.cpio.gz
338 14:50:53.332083 - {ROOT_PART}: None
339 14:50:53.332144 - {ROOT}: None
340 14:50:53.332197 - {SERVER_IP}: 192.168.201.1
341 14:50:53.332249 - {TEE}: None
342 14:50:53.332301 Parsed boot commands:
343 14:50:53.332378 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 14:50:53.332569 Parsed boot commands: tftpboot 192.168.201.1 14167012/tftp-deploy-q261glni/kernel/image.itb 14167012/tftp-deploy-q261glni/kernel/cmdline
345 14:50:53.332654 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 14:50:53.332734 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 14:50:53.332823 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 14:50:53.332906 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 14:50:53.332992 Not connected, no need to disconnect.
350 14:50:53.333066 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 14:50:53.333147 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 14:50:53.333215 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 14:50:53.336949 Setting prompt string to ['lava-test: # ']
354 14:50:53.337315 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 14:50:53.337427 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 14:50:53.337519 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 14:50:53.337611 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 14:50:53.337909 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 14:50:58.488831 >> Command sent successfully.
360 14:50:58.494778 Returned 0 in 5 seconds
361 14:50:58.595640 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 14:50:58.597377 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 14:50:58.598077 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 14:50:58.598643 Setting prompt string to 'Starting depthcharge on Spherion...'
366 14:50:58.599087 Changing prompt to 'Starting depthcharge on Spherion...'
367 14:50:58.599718 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 14:50:58.601973 [Enter `^Ec?' for help]
369 14:50:58.765358
370 14:50:58.765927
371 14:50:58.766395 F0: 102B 0000
372 14:50:58.766825
373 14:50:58.767245 F3: 1001 0000 [0200]
374 14:50:58.768289
375 14:50:58.768798 F3: 1001 0000
376 14:50:58.769239
377 14:50:58.769649 F7: 102D 0000
378 14:50:58.770147
379 14:50:58.772156 F1: 0000 0000
380 14:50:58.772630
381 14:50:58.773082 V0: 0000 0000 [0001]
382 14:50:58.773489
383 14:50:58.775285 00: 0007 8000
384 14:50:58.775741
385 14:50:58.776175 01: 0000 0000
386 14:50:58.776650
387 14:50:58.778568 BP: 0C00 0209 [0000]
388 14:50:58.778998
389 14:50:58.779461 G0: 1182 0000
390 14:50:58.779872
391 14:50:58.782068 EC: 0000 0021 [4000]
392 14:50:58.782502
393 14:50:58.782937 S7: 0000 0000 [0000]
394 14:50:58.783368
395 14:50:58.785668 CC: 0000 0000 [0001]
396 14:50:58.786091
397 14:50:58.786423 T0: 0000 0040 [010F]
398 14:50:58.786733
399 14:50:58.787068 Jump to BL
400 14:50:58.787463
401 14:50:58.812170
402 14:50:58.812635
403 14:50:58.819573 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 14:50:58.823266 ARM64: Exception handlers installed.
405 14:50:58.827186 ARM64: Testing exception
406 14:50:58.830120 ARM64: Done test exception
407 14:50:58.836907 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 14:50:58.847816 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 14:50:58.854657 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 14:50:58.864583 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 14:50:58.871101 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 14:50:58.877729 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 14:50:58.889907 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 14:50:58.895903 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 14:50:58.915540 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 14:50:58.918389 WDT: Last reset was cold boot
417 14:50:58.921531 SPI1(PAD0) initialized at 2873684 Hz
418 14:50:58.924869 SPI5(PAD0) initialized at 992727 Hz
419 14:50:58.928135 VBOOT: Loading verstage.
420 14:50:58.934794 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 14:50:58.938006 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 14:50:58.941661 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 14:50:58.945137 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 14:50:58.952675 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 14:50:58.959078 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 14:50:58.970195 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 14:50:58.970629
428 14:50:58.970968
429 14:50:58.980608 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 14:50:58.984043 ARM64: Exception handlers installed.
431 14:50:58.987110 ARM64: Testing exception
432 14:50:58.987541 ARM64: Done test exception
433 14:50:58.993815 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 14:50:58.997185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 14:50:59.011106 Probing TPM: . done!
436 14:50:59.011536 TPM ready after 0 ms
437 14:50:59.018093 Connected to device vid:did:rid of 1ae0:0028:00
438 14:50:59.024643 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 14:50:59.083605 Initialized TPM device CR50 revision 0
440 14:50:59.095454 tlcl_send_startup: Startup return code is 0
441 14:50:59.095909 TPM: setup succeeded
442 14:50:59.106739 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 14:50:59.115854 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 14:50:59.128926 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 14:50:59.137171 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 14:50:59.140281 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 14:50:59.144015 in-header: 03 07 00 00 08 00 00 00
448 14:50:59.147695 in-data: aa e4 47 04 13 02 00 00
449 14:50:59.151028 Chrome EC: UHEPI supported
450 14:50:59.157973 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 14:50:59.162239 in-header: 03 95 00 00 08 00 00 00
452 14:50:59.165744 in-data: 18 20 20 08 00 00 00 00
453 14:50:59.166297 Phase 1
454 14:50:59.169677 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 14:50:59.176938 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 14:50:59.180302 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 14:50:59.184074 Recovery requested (1009000e)
458 14:50:59.192868 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 14:50:59.198310 tlcl_extend: response is 0
460 14:50:59.207798 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 14:50:59.213051 tlcl_extend: response is 0
462 14:50:59.220133 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 14:50:59.239691 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 14:50:59.246572 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 14:50:59.247006
466 14:50:59.247344
467 14:50:59.256731 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 14:50:59.259509 ARM64: Exception handlers installed.
469 14:50:59.263185 ARM64: Testing exception
470 14:50:59.263616 ARM64: Done test exception
471 14:50:59.285355 pmic_efuse_setting: Set efuses in 11 msecs
472 14:50:59.289006 pmwrap_interface_init: Select PMIF_VLD_RDY
473 14:50:59.295636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 14:50:59.299157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 14:50:59.302651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 14:50:59.310016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 14:50:59.313865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 14:50:59.320303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 14:50:59.323836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 14:50:59.327868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 14:50:59.331363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 14:50:59.339272 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 14:50:59.343200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 14:50:59.346433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 14:50:59.349765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 14:50:59.357876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 14:50:59.364994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 14:50:59.368744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 14:50:59.375966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 14:50:59.379767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 14:50:59.386415 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 14:50:59.389896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 14:50:59.397807 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 14:50:59.401694 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 14:50:59.408559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 14:50:59.412287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 14:50:59.419437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 14:50:59.423459 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 14:50:59.430486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 14:50:59.434501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 14:50:59.438748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 14:50:59.445587 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 14:50:59.449024 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 14:50:59.452559 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 14:50:59.460217 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 14:50:59.463784 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 14:50:59.467519 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 14:50:59.474918 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 14:50:59.478714 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 14:50:59.485919 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 14:50:59.489667 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 14:50:59.493361 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 14:50:59.497276 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 14:50:59.500949 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 14:50:59.507879 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 14:50:59.511463 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 14:50:59.515538 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 14:50:59.519048 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 14:50:59.522812 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 14:50:59.526712 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 14:50:59.530771 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 14:50:59.537764 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 14:50:59.541159 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 14:50:59.549102 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 14:50:59.556567 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 14:50:59.559972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 14:50:59.571167 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 14:50:59.579025 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 14:50:59.582883 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 14:50:59.585972 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 14:50:59.589479 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 14:50:59.598195 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
533 14:50:59.605098 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 14:50:59.608728 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 14:50:59.612143 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 14:50:59.623105 [RTC]rtc_get_frequency_meter,154: input=15, output=757
537 14:50:59.632954 [RTC]rtc_get_frequency_meter,154: input=23, output=943
538 14:50:59.642199 [RTC]rtc_get_frequency_meter,154: input=19, output=853
539 14:50:59.651547 [RTC]rtc_get_frequency_meter,154: input=17, output=802
540 14:50:59.660779 [RTC]rtc_get_frequency_meter,154: input=16, output=782
541 14:50:59.670841 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 14:50:59.680465 [RTC]rtc_get_frequency_meter,154: input=17, output=805
543 14:50:59.683388 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 14:50:59.691088 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 14:50:59.694751 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 14:50:59.698457 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 14:50:59.702273 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 14:50:59.706281 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 14:50:59.710070 ADC[4]: Raw value=906942 ID=7
550 14:50:59.710501 ADC[3]: Raw value=213441 ID=1
551 14:50:59.714015 RAM Code: 0x71
552 14:50:59.716870 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 14:50:59.720793 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 14:50:59.732512 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 14:50:59.735435 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 14:50:59.739187 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 14:50:59.743349 in-header: 03 07 00 00 08 00 00 00
558 14:50:59.747188 in-data: aa e4 47 04 13 02 00 00
559 14:50:59.750710 Chrome EC: UHEPI supported
560 14:50:59.758113 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 14:50:59.761984 in-header: 03 95 00 00 08 00 00 00
562 14:50:59.765218 in-data: 18 20 20 08 00 00 00 00
563 14:50:59.765741 MRC: failed to locate region type 0.
564 14:50:59.773082 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 14:50:59.777000 DRAM-K: Running full calibration
566 14:50:59.784441 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 14:50:59.784871 header.status = 0x0
568 14:50:59.788324 header.version = 0x6 (expected: 0x6)
569 14:50:59.792072 header.size = 0xd00 (expected: 0xd00)
570 14:50:59.792637 header.flags = 0x0
571 14:50:59.799241 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 14:50:59.817467 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 14:50:59.824894 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 14:50:59.828490 dram_init: ddr_geometry: 2
575 14:50:59.828930 [EMI] MDL number = 2
576 14:50:59.831788 [EMI] Get MDL freq = 0
577 14:50:59.832225 dram_init: ddr_type: 0
578 14:50:59.835736 is_discrete_lpddr4: 1
579 14:50:59.839523 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 14:50:59.840050
581 14:50:59.840433
582 14:50:59.840759 [Bian_co] ETT version 0.0.0.1
583 14:50:59.846326 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 14:50:59.846852
585 14:50:59.849175 dramc_set_vcore_voltage set vcore to 650000
586 14:50:59.853355 Read voltage for 800, 4
587 14:50:59.853779 Vio18 = 0
588 14:50:59.854116 Vcore = 650000
589 14:50:59.854430 Vdram = 0
590 14:50:59.857258 Vddq = 0
591 14:50:59.857797 Vmddr = 0
592 14:50:59.861104 dram_init: config_dvfs: 1
593 14:50:59.864765 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 14:50:59.868706 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 14:50:59.872163 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
596 14:50:59.875557 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
597 14:50:59.879501 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 14:50:59.886425 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 14:50:59.886979 MEM_TYPE=3, freq_sel=18
600 14:50:59.889506 sv_algorithm_assistance_LP4_1600
601 14:50:59.893063 ============ PULL DRAM RESETB DOWN ============
602 14:50:59.900571 ========== PULL DRAM RESETB DOWN end =========
603 14:50:59.903965 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 14:50:59.907319 ===================================
605 14:50:59.907751 LPDDR4 DRAM CONFIGURATION
606 14:50:59.910962 ===================================
607 14:50:59.914985 EX_ROW_EN[0] = 0x0
608 14:50:59.915507 EX_ROW_EN[1] = 0x0
609 14:50:59.918815 LP4Y_EN = 0x0
610 14:50:59.919348 WORK_FSP = 0x0
611 14:50:59.922360 WL = 0x2
612 14:50:59.922892 RL = 0x2
613 14:50:59.925485 BL = 0x2
614 14:50:59.925991 RPST = 0x0
615 14:50:59.928923 RD_PRE = 0x0
616 14:50:59.929425 WR_PRE = 0x1
617 14:50:59.932209 WR_PST = 0x0
618 14:50:59.932717 DBI_WR = 0x0
619 14:50:59.935344 DBI_RD = 0x0
620 14:50:59.935766 OTF = 0x1
621 14:50:59.939661 ===================================
622 14:50:59.942297 ===================================
623 14:50:59.945598 ANA top config
624 14:50:59.949379 ===================================
625 14:50:59.949808 DLL_ASYNC_EN = 0
626 14:50:59.952643 ALL_SLAVE_EN = 1
627 14:50:59.955854 NEW_RANK_MODE = 1
628 14:50:59.959272 DLL_IDLE_MODE = 1
629 14:50:59.959804 LP45_APHY_COMB_EN = 1
630 14:50:59.962664 TX_ODT_DIS = 1
631 14:50:59.965597 NEW_8X_MODE = 1
632 14:50:59.969436 ===================================
633 14:50:59.973217 ===================================
634 14:50:59.976142 data_rate = 1600
635 14:50:59.979948 CKR = 1
636 14:50:59.980419 DQ_P2S_RATIO = 8
637 14:50:59.983282 ===================================
638 14:50:59.986697 CA_P2S_RATIO = 8
639 14:50:59.989692 DQ_CA_OPEN = 0
640 14:50:59.992896 DQ_SEMI_OPEN = 0
641 14:50:59.996070 CA_SEMI_OPEN = 0
642 14:50:59.996526 CA_FULL_RATE = 0
643 14:50:59.999384 DQ_CKDIV4_EN = 1
644 14:51:00.002932 CA_CKDIV4_EN = 1
645 14:51:00.006591 CA_PREDIV_EN = 0
646 14:51:00.009948 PH8_DLY = 0
647 14:51:00.012912 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 14:51:00.013344 DQ_AAMCK_DIV = 4
649 14:51:00.016424 CA_AAMCK_DIV = 4
650 14:51:00.019717 CA_ADMCK_DIV = 4
651 14:51:00.022920 DQ_TRACK_CA_EN = 0
652 14:51:00.026671 CA_PICK = 800
653 14:51:00.030189 CA_MCKIO = 800
654 14:51:00.030783 MCKIO_SEMI = 0
655 14:51:00.033736 PLL_FREQ = 3068
656 14:51:00.037421 DQ_UI_PI_RATIO = 32
657 14:51:00.040858 CA_UI_PI_RATIO = 0
658 14:51:00.045491 ===================================
659 14:51:00.045924 ===================================
660 14:51:00.048814 memory_type:LPDDR4
661 14:51:00.052829 GP_NUM : 10
662 14:51:00.053260 SRAM_EN : 1
663 14:51:00.055972 MD32_EN : 0
664 14:51:00.059816 ===================================
665 14:51:00.060244 [ANA_INIT] >>>>>>>>>>>>>>
666 14:51:00.064099 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 14:51:00.067596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 14:51:00.070836 ===================================
669 14:51:00.074323 data_rate = 1600,PCW = 0X7600
670 14:51:00.077768 ===================================
671 14:51:00.080756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 14:51:00.083832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 14:51:00.091109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 14:51:00.094162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 14:51:00.097339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 14:51:00.100870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 14:51:00.104004 [ANA_INIT] flow start
678 14:51:00.107755 [ANA_INIT] PLL >>>>>>>>
679 14:51:00.108335 [ANA_INIT] PLL <<<<<<<<
680 14:51:00.110878 [ANA_INIT] MIDPI >>>>>>>>
681 14:51:00.114377 [ANA_INIT] MIDPI <<<<<<<<
682 14:51:00.117403 [ANA_INIT] DLL >>>>>>>>
683 14:51:00.117881 [ANA_INIT] flow end
684 14:51:00.120680 ============ LP4 DIFF to SE enter ============
685 14:51:00.127334 ============ LP4 DIFF to SE exit ============
686 14:51:00.127907 [ANA_INIT] <<<<<<<<<<<<<
687 14:51:00.130718 [Flow] Enable top DCM control >>>>>
688 14:51:00.134705 [Flow] Enable top DCM control <<<<<
689 14:51:00.137527 Enable DLL master slave shuffle
690 14:51:00.144462 ==============================================================
691 14:51:00.145057 Gating Mode config
692 14:51:00.150802 ==============================================================
693 14:51:00.154403 Config description:
694 14:51:00.161449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 14:51:00.167615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 14:51:00.174445 SELPH_MODE 0: By rank 1: By Phase
697 14:51:00.177953 ==============================================================
698 14:51:00.180901 GAT_TRACK_EN = 1
699 14:51:00.184422 RX_GATING_MODE = 2
700 14:51:00.187943 RX_GATING_TRACK_MODE = 2
701 14:51:00.190608 SELPH_MODE = 1
702 14:51:00.194426 PICG_EARLY_EN = 1
703 14:51:00.197362 VALID_LAT_VALUE = 1
704 14:51:00.204254 ==============================================================
705 14:51:00.207565 Enter into Gating configuration >>>>
706 14:51:00.210941 Exit from Gating configuration <<<<
707 14:51:00.214147 Enter into DVFS_PRE_config >>>>>
708 14:51:00.224199 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 14:51:00.227582 Exit from DVFS_PRE_config <<<<<
710 14:51:00.231346 Enter into PICG configuration >>>>
711 14:51:00.234399 Exit from PICG configuration <<<<
712 14:51:00.234873 [RX_INPUT] configuration >>>>>
713 14:51:00.237328 [RX_INPUT] configuration <<<<<
714 14:51:00.244238 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 14:51:00.247792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 14:51:00.254726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 14:51:00.261349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 14:51:00.267495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 14:51:00.274375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 14:51:00.276917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 14:51:00.280537 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 14:51:00.283818 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 14:51:00.290706 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 14:51:00.293868 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 14:51:00.297597 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 14:51:00.300690 ===================================
727 14:51:00.304000 LPDDR4 DRAM CONFIGURATION
728 14:51:00.307592 ===================================
729 14:51:00.310651 EX_ROW_EN[0] = 0x0
730 14:51:00.310861 EX_ROW_EN[1] = 0x0
731 14:51:00.314341 LP4Y_EN = 0x0
732 14:51:00.314572 WORK_FSP = 0x0
733 14:51:00.316964 WL = 0x2
734 14:51:00.317111 RL = 0x2
735 14:51:00.320306 BL = 0x2
736 14:51:00.320474 RPST = 0x0
737 14:51:00.323792 RD_PRE = 0x0
738 14:51:00.323948 WR_PRE = 0x1
739 14:51:00.326908 WR_PST = 0x0
740 14:51:00.327085 DBI_WR = 0x0
741 14:51:00.330520 DBI_RD = 0x0
742 14:51:00.330821 OTF = 0x1
743 14:51:00.334000 ===================================
744 14:51:00.341130 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 14:51:00.344189 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 14:51:00.348108 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 14:51:00.350533 ===================================
748 14:51:00.353923 LPDDR4 DRAM CONFIGURATION
749 14:51:00.357445 ===================================
750 14:51:00.360994 EX_ROW_EN[0] = 0x10
751 14:51:00.361468 EX_ROW_EN[1] = 0x0
752 14:51:00.363733 LP4Y_EN = 0x0
753 14:51:00.364164 WORK_FSP = 0x0
754 14:51:00.366981 WL = 0x2
755 14:51:00.367064 RL = 0x2
756 14:51:00.370273 BL = 0x2
757 14:51:00.370356 RPST = 0x0
758 14:51:00.373781 RD_PRE = 0x0
759 14:51:00.373865 WR_PRE = 0x1
760 14:51:00.376988 WR_PST = 0x0
761 14:51:00.377097 DBI_WR = 0x0
762 14:51:00.380941 DBI_RD = 0x0
763 14:51:00.381449 OTF = 0x1
764 14:51:00.384455 ===================================
765 14:51:00.390749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 14:51:00.395564 nWR fixed to 40
767 14:51:00.398250 [ModeRegInit_LP4] CH0 RK0
768 14:51:00.398720 [ModeRegInit_LP4] CH0 RK1
769 14:51:00.401741 [ModeRegInit_LP4] CH1 RK0
770 14:51:00.404966 [ModeRegInit_LP4] CH1 RK1
771 14:51:00.405438 match AC timing 13
772 14:51:00.411808 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 14:51:00.415589 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 14:51:00.418616 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 14:51:00.425314 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 14:51:00.428400 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 14:51:00.428901 [EMI DOE] emi_dcm 0
778 14:51:00.435023 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 14:51:00.435496 ==
780 14:51:00.438356 Dram Type= 6, Freq= 0, CH_0, rank 0
781 14:51:00.442068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 14:51:00.442499 ==
783 14:51:00.448863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 14:51:00.452017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 14:51:00.462619 [CA 0] Center 36 (6~67) winsize 62
786 14:51:00.465658 [CA 1] Center 36 (6~67) winsize 62
787 14:51:00.469379 [CA 2] Center 34 (4~65) winsize 62
788 14:51:00.472332 [CA 3] Center 34 (4~64) winsize 61
789 14:51:00.476008 [CA 4] Center 33 (2~64) winsize 63
790 14:51:00.478913 [CA 5] Center 32 (2~62) winsize 61
791 14:51:00.479339
792 14:51:00.482234 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 14:51:00.482664
794 14:51:00.485777 [CATrainingPosCal] consider 1 rank data
795 14:51:00.489017 u2DelayCellTimex100 = 270/100 ps
796 14:51:00.492061 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
797 14:51:00.498785 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
798 14:51:00.502258 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
799 14:51:00.505415 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
800 14:51:00.508763 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
801 14:51:00.512621 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
802 14:51:00.513055
803 14:51:00.515972 CA PerBit enable=1, Macro0, CA PI delay=32
804 14:51:00.516437
805 14:51:00.519109 [CBTSetCACLKResult] CA Dly = 32
806 14:51:00.519534 CS Dly: 4 (0~35)
807 14:51:00.522258 ==
808 14:51:00.525588 Dram Type= 6, Freq= 0, CH_0, rank 1
809 14:51:00.528755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 14:51:00.529190 ==
811 14:51:00.532378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 14:51:00.538780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 14:51:00.548934 [CA 0] Center 36 (6~67) winsize 62
814 14:51:00.552155 [CA 1] Center 36 (6~67) winsize 62
815 14:51:00.555767 [CA 2] Center 34 (4~65) winsize 62
816 14:51:00.559120 [CA 3] Center 33 (3~64) winsize 62
817 14:51:00.562464 [CA 4] Center 33 (3~63) winsize 61
818 14:51:00.566084 [CA 5] Center 32 (2~63) winsize 62
819 14:51:00.566674
820 14:51:00.568898 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 14:51:00.569327
822 14:51:00.571971 [CATrainingPosCal] consider 2 rank data
823 14:51:00.575708 u2DelayCellTimex100 = 270/100 ps
824 14:51:00.578941 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
825 14:51:00.581973 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
826 14:51:00.588707 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
827 14:51:00.592626 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
828 14:51:00.595328 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
829 14:51:00.598963 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
830 14:51:00.599391
831 14:51:00.602692 CA PerBit enable=1, Macro0, CA PI delay=32
832 14:51:00.603123
833 14:51:00.605582 [CBTSetCACLKResult] CA Dly = 32
834 14:51:00.606009 CS Dly: 4 (0~36)
835 14:51:00.606352
836 14:51:00.609207 ----->DramcWriteLeveling(PI) begin...
837 14:51:00.612412 ==
838 14:51:00.612844 Dram Type= 6, Freq= 0, CH_0, rank 0
839 14:51:00.619831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 14:51:00.620263 ==
841 14:51:00.620653 Write leveling (Byte 0): 32 => 32
842 14:51:00.623928 Write leveling (Byte 1): 31 => 31
843 14:51:00.627572 DramcWriteLeveling(PI) end<-----
844 14:51:00.628000
845 14:51:00.628337 ==
846 14:51:00.630881 Dram Type= 6, Freq= 0, CH_0, rank 0
847 14:51:00.634560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 14:51:00.634988 ==
849 14:51:00.637864 [Gating] SW mode calibration
850 14:51:00.644663 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 14:51:00.651462 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 14:51:00.654600 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 14:51:00.657905 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 14:51:00.664328 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
855 14:51:00.668325 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 14:51:00.671217 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 14:51:00.677455 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:51:00.681163 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:51:00.685107 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:51:00.691374 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 14:51:00.694608 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 14:51:00.698441 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 14:51:00.701472 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 14:51:00.708773 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 14:51:00.711807 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 14:51:00.714891 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 14:51:00.721522 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 14:51:00.724645 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 14:51:00.727905 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 14:51:00.734291 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 14:51:00.737400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 14:51:00.741120 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 14:51:00.748097 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 14:51:00.751063 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 14:51:00.754671 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 14:51:00.761260 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 14:51:00.765018 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 14:51:00.767527 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
879 14:51:00.774277 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
880 14:51:00.777480 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 14:51:00.781291 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 14:51:00.788326 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 14:51:00.791407 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 14:51:00.794887 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 14:51:00.798307 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
886 14:51:00.804400 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 0) (1 0)
887 14:51:00.807957 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
888 14:51:00.811243 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 14:51:00.817949 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 14:51:00.821254 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 14:51:00.824715 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 14:51:00.831355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 14:51:00.834308 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
894 14:51:00.837980 0 11 8 | B1->B0 | 2d2d 3a3a | 0 1 | (0 0) (0 0)
895 14:51:00.844223 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
896 14:51:00.847924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 14:51:00.851161 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 14:51:00.858533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 14:51:00.861610 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 14:51:00.864551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 14:51:00.871061 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 14:51:00.874868 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 14:51:00.877746 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 14:51:00.884614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 14:51:00.887501 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 14:51:00.891243 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 14:51:00.897544 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 14:51:00.901068 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 14:51:00.904223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 14:51:00.907763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 14:51:00.914437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 14:51:00.917787 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 14:51:00.921636 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 14:51:00.927633 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 14:51:00.931487 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 14:51:00.934497 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 14:51:00.941455 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 14:51:00.945053 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 14:51:00.948179 Total UI for P1: 0, mck2ui 16
920 14:51:00.951999 best dqsien dly found for B0: ( 0, 14, 6)
921 14:51:00.954817 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
922 14:51:00.958229 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 14:51:00.961364 Total UI for P1: 0, mck2ui 16
924 14:51:00.965251 best dqsien dly found for B1: ( 0, 14, 10)
925 14:51:00.969132 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 14:51:00.972230 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 14:51:00.972804
928 14:51:00.978977 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 14:51:00.982478 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 14:51:00.982902 [Gating] SW calibration Done
931 14:51:00.985506 ==
932 14:51:00.989182 Dram Type= 6, Freq= 0, CH_0, rank 0
933 14:51:00.992437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 14:51:00.992930 ==
935 14:51:00.993272 RX Vref Scan: 0
936 14:51:00.993589
937 14:51:00.995745 RX Vref 0 -> 0, step: 1
938 14:51:00.996167
939 14:51:00.999064 RX Delay -130 -> 252, step: 16
940 14:51:01.001817 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 14:51:01.005963 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 14:51:01.012456 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 14:51:01.015346 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 14:51:01.019227 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 14:51:01.022247 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 14:51:01.025697 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 14:51:01.028986 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 14:51:01.035409 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 14:51:01.038321 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 14:51:01.041986 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 14:51:01.045009 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 14:51:01.048512 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 14:51:01.055633 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 14:51:01.058610 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 14:51:01.062178 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 14:51:01.062261 ==
957 14:51:01.065330 Dram Type= 6, Freq= 0, CH_0, rank 0
958 14:51:01.068284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 14:51:01.071992 ==
960 14:51:01.072080 DQS Delay:
961 14:51:01.072150 DQS0 = 0, DQS1 = 0
962 14:51:01.075506 DQM Delay:
963 14:51:01.075681 DQM0 = 89, DQM1 = 82
964 14:51:01.075766 DQ Delay:
965 14:51:01.078929 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 14:51:01.082233 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 14:51:01.085933 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
968 14:51:01.089031 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 14:51:01.089214
970 14:51:01.089326
971 14:51:01.092634 ==
972 14:51:01.095370 Dram Type= 6, Freq= 0, CH_0, rank 0
973 14:51:01.099120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 14:51:01.099324 ==
975 14:51:01.099452
976 14:51:01.099559
977 14:51:01.102392 TX Vref Scan disable
978 14:51:01.102551 == TX Byte 0 ==
979 14:51:01.106255 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 14:51:01.112195 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 14:51:01.112513 == TX Byte 1 ==
982 14:51:01.115467 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 14:51:01.122632 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 14:51:01.123032 ==
985 14:51:01.126120 Dram Type= 6, Freq= 0, CH_0, rank 0
986 14:51:01.129356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 14:51:01.129757 ==
988 14:51:01.142161 TX Vref=22, minBit 10, minWin=27, winSum=448
989 14:51:01.146081 TX Vref=24, minBit 10, minWin=27, winSum=453
990 14:51:01.148954 TX Vref=26, minBit 9, minWin=27, winSum=455
991 14:51:01.152436 TX Vref=28, minBit 8, minWin=28, winSum=458
992 14:51:01.155580 TX Vref=30, minBit 0, minWin=28, winSum=456
993 14:51:01.162331 TX Vref=32, minBit 5, minWin=28, winSum=455
994 14:51:01.165548 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
995 14:51:01.166021
996 14:51:01.169352 Final TX Range 1 Vref 28
997 14:51:01.169880
998 14:51:01.170270 ==
999 14:51:01.172274 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 14:51:01.175574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 14:51:01.176000 ==
1002 14:51:01.179046
1003 14:51:01.179468
1004 14:51:01.179802 TX Vref Scan disable
1005 14:51:01.182414 == TX Byte 0 ==
1006 14:51:01.185554 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 14:51:01.189619 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 14:51:01.192284 == TX Byte 1 ==
1009 14:51:01.195787 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 14:51:01.199075 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 14:51:01.202700
1012 14:51:01.203221 [DATLAT]
1013 14:51:01.203561 Freq=800, CH0 RK0
1014 14:51:01.203883
1015 14:51:01.206084 DATLAT Default: 0xa
1016 14:51:01.206597 0, 0xFFFF, sum = 0
1017 14:51:01.209036 1, 0xFFFF, sum = 0
1018 14:51:01.209559 2, 0xFFFF, sum = 0
1019 14:51:01.212336 3, 0xFFFF, sum = 0
1020 14:51:01.212905 4, 0xFFFF, sum = 0
1021 14:51:01.215976 5, 0xFFFF, sum = 0
1022 14:51:01.216546 6, 0xFFFF, sum = 0
1023 14:51:01.218935 7, 0xFFFF, sum = 0
1024 14:51:01.223019 8, 0xFFFF, sum = 0
1025 14:51:01.223577 9, 0x0, sum = 1
1026 14:51:01.223937 10, 0x0, sum = 2
1027 14:51:01.225708 11, 0x0, sum = 3
1028 14:51:01.226127 12, 0x0, sum = 4
1029 14:51:01.229353 best_step = 10
1030 14:51:01.229810
1031 14:51:01.230155 ==
1032 14:51:01.232647 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 14:51:01.235692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 14:51:01.236120 ==
1035 14:51:01.239024 RX Vref Scan: 1
1036 14:51:01.239435
1037 14:51:01.239762 Set Vref Range= 32 -> 127
1038 14:51:01.240204
1039 14:51:01.242225 RX Vref 32 -> 127, step: 1
1040 14:51:01.242638
1041 14:51:01.245969 RX Delay -79 -> 252, step: 8
1042 14:51:01.246487
1043 14:51:01.249356 Set Vref, RX VrefLevel [Byte0]: 32
1044 14:51:01.252561 [Byte1]: 32
1045 14:51:01.252978
1046 14:51:01.255817 Set Vref, RX VrefLevel [Byte0]: 33
1047 14:51:01.259000 [Byte1]: 33
1048 14:51:01.262377
1049 14:51:01.262893 Set Vref, RX VrefLevel [Byte0]: 34
1050 14:51:01.266214 [Byte1]: 34
1051 14:51:01.270176
1052 14:51:01.270591 Set Vref, RX VrefLevel [Byte0]: 35
1053 14:51:01.273493 [Byte1]: 35
1054 14:51:01.278494
1055 14:51:01.279054 Set Vref, RX VrefLevel [Byte0]: 36
1056 14:51:01.281440 [Byte1]: 36
1057 14:51:01.285815
1058 14:51:01.286276 Set Vref, RX VrefLevel [Byte0]: 37
1059 14:51:01.288675 [Byte1]: 37
1060 14:51:01.293705
1061 14:51:01.294123 Set Vref, RX VrefLevel [Byte0]: 38
1062 14:51:01.296773 [Byte1]: 38
1063 14:51:01.300543
1064 14:51:01.300997 Set Vref, RX VrefLevel [Byte0]: 39
1065 14:51:01.304090 [Byte1]: 39
1066 14:51:01.308422
1067 14:51:01.308929 Set Vref, RX VrefLevel [Byte0]: 40
1068 14:51:01.311567 [Byte1]: 40
1069 14:51:01.315079
1070 14:51:01.315977 Set Vref, RX VrefLevel [Byte0]: 41
1071 14:51:01.318481 [Byte1]: 41
1072 14:51:01.322795
1073 14:51:01.323207 Set Vref, RX VrefLevel [Byte0]: 42
1074 14:51:01.326076 [Byte1]: 42
1075 14:51:01.330715
1076 14:51:01.331263 Set Vref, RX VrefLevel [Byte0]: 43
1077 14:51:01.334238 [Byte1]: 43
1078 14:51:01.338032
1079 14:51:01.338564 Set Vref, RX VrefLevel [Byte0]: 44
1080 14:51:01.341956 [Byte1]: 44
1081 14:51:01.345541
1082 14:51:01.346055 Set Vref, RX VrefLevel [Byte0]: 45
1083 14:51:01.349108 [Byte1]: 45
1084 14:51:01.352900
1085 14:51:01.353345 Set Vref, RX VrefLevel [Byte0]: 46
1086 14:51:01.356021 [Byte1]: 46
1087 14:51:01.360743
1088 14:51:01.361287 Set Vref, RX VrefLevel [Byte0]: 47
1089 14:51:01.364049 [Byte1]: 47
1090 14:51:01.367912
1091 14:51:01.368322 Set Vref, RX VrefLevel [Byte0]: 48
1092 14:51:01.371581 [Byte1]: 48
1093 14:51:01.375763
1094 14:51:01.376447 Set Vref, RX VrefLevel [Byte0]: 49
1095 14:51:01.378855 [Byte1]: 49
1096 14:51:01.383296
1097 14:51:01.383716 Set Vref, RX VrefLevel [Byte0]: 50
1098 14:51:01.386249 [Byte1]: 50
1099 14:51:01.390801
1100 14:51:01.391221 Set Vref, RX VrefLevel [Byte0]: 51
1101 14:51:01.394138 [Byte1]: 51
1102 14:51:01.398630
1103 14:51:01.399306 Set Vref, RX VrefLevel [Byte0]: 52
1104 14:51:01.401521 [Byte1]: 52
1105 14:51:01.406015
1106 14:51:01.406405 Set Vref, RX VrefLevel [Byte0]: 53
1107 14:51:01.409472 [Byte1]: 53
1108 14:51:01.413483
1109 14:51:01.413895 Set Vref, RX VrefLevel [Byte0]: 54
1110 14:51:01.416865 [Byte1]: 54
1111 14:51:01.421271
1112 14:51:01.421701 Set Vref, RX VrefLevel [Byte0]: 55
1113 14:51:01.424564 [Byte1]: 55
1114 14:51:01.428562
1115 14:51:01.429088 Set Vref, RX VrefLevel [Byte0]: 56
1116 14:51:01.432234 [Byte1]: 56
1117 14:51:01.436444
1118 14:51:01.436888 Set Vref, RX VrefLevel [Byte0]: 57
1119 14:51:01.439181 [Byte1]: 57
1120 14:51:01.443773
1121 14:51:01.444183 Set Vref, RX VrefLevel [Byte0]: 58
1122 14:51:01.447295 [Byte1]: 58
1123 14:51:01.451538
1124 14:51:01.451956 Set Vref, RX VrefLevel [Byte0]: 59
1125 14:51:01.454540 [Byte1]: 59
1126 14:51:01.459089
1127 14:51:01.459599 Set Vref, RX VrefLevel [Byte0]: 60
1128 14:51:01.462172 [Byte1]: 60
1129 14:51:01.466458
1130 14:51:01.466971 Set Vref, RX VrefLevel [Byte0]: 61
1131 14:51:01.469739 [Byte1]: 61
1132 14:51:01.473490
1133 14:51:01.473961 Set Vref, RX VrefLevel [Byte0]: 62
1134 14:51:01.477266 [Byte1]: 62
1135 14:51:01.481396
1136 14:51:01.481860 Set Vref, RX VrefLevel [Byte0]: 63
1137 14:51:01.484434 [Byte1]: 63
1138 14:51:01.488733
1139 14:51:01.489144 Set Vref, RX VrefLevel [Byte0]: 64
1140 14:51:01.492153 [Byte1]: 64
1141 14:51:01.496544
1142 14:51:01.496961 Set Vref, RX VrefLevel [Byte0]: 65
1143 14:51:01.500009 [Byte1]: 65
1144 14:51:01.504448
1145 14:51:01.505079 Set Vref, RX VrefLevel [Byte0]: 66
1146 14:51:01.507272 [Byte1]: 66
1147 14:51:01.511451
1148 14:51:01.511862 Set Vref, RX VrefLevel [Byte0]: 67
1149 14:51:01.515084 [Byte1]: 67
1150 14:51:01.519304
1151 14:51:01.519716 Set Vref, RX VrefLevel [Byte0]: 68
1152 14:51:01.522468 [Byte1]: 68
1153 14:51:01.526898
1154 14:51:01.527409 Set Vref, RX VrefLevel [Byte0]: 69
1155 14:51:01.529928 [Byte1]: 69
1156 14:51:01.534310
1157 14:51:01.534824 Set Vref, RX VrefLevel [Byte0]: 70
1158 14:51:01.537936 [Byte1]: 70
1159 14:51:01.541741
1160 14:51:01.542260 Set Vref, RX VrefLevel [Byte0]: 71
1161 14:51:01.545037 [Byte1]: 71
1162 14:51:01.549479
1163 14:51:01.550163 Set Vref, RX VrefLevel [Byte0]: 72
1164 14:51:01.552488 [Byte1]: 72
1165 14:51:01.557092
1166 14:51:01.557613 Set Vref, RX VrefLevel [Byte0]: 73
1167 14:51:01.560279 [Byte1]: 73
1168 14:51:01.564197
1169 14:51:01.564675 Set Vref, RX VrefLevel [Byte0]: 74
1170 14:51:01.568084 [Byte1]: 74
1171 14:51:01.572410
1172 14:51:01.572829 Set Vref, RX VrefLevel [Byte0]: 75
1173 14:51:01.574969 [Byte1]: 75
1174 14:51:01.579892
1175 14:51:01.580437 Set Vref, RX VrefLevel [Byte0]: 76
1176 14:51:01.583305 [Byte1]: 76
1177 14:51:01.586998
1178 14:51:01.587415 Set Vref, RX VrefLevel [Byte0]: 77
1179 14:51:01.590041 [Byte1]: 77
1180 14:51:01.595271
1181 14:51:01.595785 Set Vref, RX VrefLevel [Byte0]: 78
1182 14:51:01.598010 [Byte1]: 78
1183 14:51:01.602247
1184 14:51:01.602818 Final RX Vref Byte 0 = 60 to rank0
1185 14:51:01.605422 Final RX Vref Byte 1 = 60 to rank0
1186 14:51:01.609213 Final RX Vref Byte 0 = 60 to rank1
1187 14:51:01.612089 Final RX Vref Byte 1 = 60 to rank1==
1188 14:51:01.615728 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 14:51:01.622332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 14:51:01.622767 ==
1191 14:51:01.623140 DQS Delay:
1192 14:51:01.623449 DQS0 = 0, DQS1 = 0
1193 14:51:01.625832 DQM Delay:
1194 14:51:01.626340 DQM0 = 92, DQM1 = 86
1195 14:51:01.629177 DQ Delay:
1196 14:51:01.632137 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1197 14:51:01.635184 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1198 14:51:01.638675 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1199 14:51:01.642191 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1200 14:51:01.642743
1201 14:51:01.643164
1202 14:51:01.648942 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1203 14:51:01.652245 CH0 RK0: MR19=606, MR18=4A41
1204 14:51:01.659087 CH0_RK0: MR19=0x606, MR18=0x4A41, DQSOSC=391, MR23=63, INC=96, DEC=64
1205 14:51:01.659513
1206 14:51:01.662687 ----->DramcWriteLeveling(PI) begin...
1207 14:51:01.663256 ==
1208 14:51:01.665698 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 14:51:01.669377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 14:51:01.669795 ==
1211 14:51:01.672411 Write leveling (Byte 0): 33 => 33
1212 14:51:01.675854 Write leveling (Byte 1): 30 => 30
1213 14:51:01.679117 DramcWriteLeveling(PI) end<-----
1214 14:51:01.679540
1215 14:51:01.679869 ==
1216 14:51:01.682870 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 14:51:01.725944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 14:51:01.726100 ==
1219 14:51:01.726165 [Gating] SW mode calibration
1220 14:51:01.726450 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 14:51:01.727007 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 14:51:01.727095 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 14:51:01.727487 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 14:51:01.727761 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 14:51:01.728021 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 14:51:01.728103 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 14:51:01.728170 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 14:51:01.770574 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 14:51:01.770752 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 14:51:01.771067 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 14:51:01.771177 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 14:51:01.771281 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 14:51:01.771357 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 14:51:01.771422 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 14:51:01.771502 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 14:51:01.771568 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 14:51:01.771633 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 14:51:01.774436 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 14:51:01.781154 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1240 14:51:01.784563 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1241 14:51:01.788038 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 14:51:01.794181 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 14:51:01.797754 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 14:51:01.801132 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 14:51:01.807776 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 14:51:01.811261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 14:51:01.814829 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 14:51:01.821348 0 9 8 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (0 0)
1249 14:51:01.824258 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 14:51:01.828131 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 14:51:01.831258 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 14:51:01.838232 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 14:51:01.841408 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 14:51:01.844582 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 14:51:01.851650 0 10 4 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
1256 14:51:01.854303 0 10 8 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1257 14:51:01.858745 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 14:51:01.862328 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 14:51:01.869850 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 14:51:01.873745 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 14:51:01.876336 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 14:51:01.880216 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 14:51:01.886773 0 11 4 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1264 14:51:01.890659 0 11 8 | B1->B0 | 3c3c 3737 | 0 1 | (0 0) (0 0)
1265 14:51:01.894127 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 14:51:01.897509 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 14:51:01.903922 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 14:51:01.907731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 14:51:01.910699 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 14:51:01.917572 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 14:51:01.921012 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 14:51:01.924241 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1273 14:51:01.930665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 14:51:01.933865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 14:51:01.937459 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 14:51:01.943826 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 14:51:01.946595 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 14:51:01.950300 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 14:51:01.957318 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 14:51:01.960487 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 14:51:01.963788 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 14:51:01.970255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 14:51:01.973652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 14:51:01.977269 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 14:51:01.984500 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 14:51:01.986896 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 14:51:01.990622 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 14:51:01.997481 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1289 14:51:01.997896 Total UI for P1: 0, mck2ui 16
1290 14:51:02.000533 best dqsien dly found for B1: ( 0, 14, 6)
1291 14:51:02.008057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1292 14:51:02.010989 Total UI for P1: 0, mck2ui 16
1293 14:51:02.014760 best dqsien dly found for B0: ( 0, 14, 8)
1294 14:51:02.017214 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1295 14:51:02.020076 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1296 14:51:02.020157
1297 14:51:02.023983 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 14:51:02.027065 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1299 14:51:02.030384 [Gating] SW calibration Done
1300 14:51:02.030465 ==
1301 14:51:02.033995 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 14:51:02.037206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 14:51:02.037294 ==
1304 14:51:02.040634 RX Vref Scan: 0
1305 14:51:02.040799
1306 14:51:02.040879 RX Vref 0 -> 0, step: 1
1307 14:51:02.040949
1308 14:51:02.043787 RX Delay -130 -> 252, step: 16
1309 14:51:02.050128 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1310 14:51:02.054735 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1311 14:51:02.057712 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1312 14:51:02.060940 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1313 14:51:02.064419 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1314 14:51:02.067831 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1315 14:51:02.074655 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1316 14:51:02.078203 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1317 14:51:02.081249 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1318 14:51:02.084813 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1319 14:51:02.087438 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1320 14:51:02.094059 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1321 14:51:02.097704 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1322 14:51:02.100618 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1323 14:51:02.103952 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1324 14:51:02.107807 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1325 14:51:02.110691 ==
1326 14:51:02.114248 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 14:51:02.117995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 14:51:02.118514 ==
1329 14:51:02.118845 DQS Delay:
1330 14:51:02.120944 DQS0 = 0, DQS1 = 0
1331 14:51:02.121361 DQM Delay:
1332 14:51:02.124518 DQM0 = 93, DQM1 = 83
1333 14:51:02.124938 DQ Delay:
1334 14:51:02.127489 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1335 14:51:02.131168 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1336 14:51:02.134436 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1337 14:51:02.137578 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1338 14:51:02.138159
1339 14:51:02.138495
1340 14:51:02.138912 ==
1341 14:51:02.140884 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 14:51:02.144449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 14:51:02.144870 ==
1344 14:51:02.145197
1345 14:51:02.145502
1346 14:51:02.147679 TX Vref Scan disable
1347 14:51:02.150991 == TX Byte 0 ==
1348 14:51:02.154470 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1349 14:51:02.157487 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1350 14:51:02.161016 == TX Byte 1 ==
1351 14:51:02.164717 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1352 14:51:02.167510 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1353 14:51:02.167933 ==
1354 14:51:02.171197 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 14:51:02.174602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 14:51:02.175021 ==
1357 14:51:02.189191 TX Vref=22, minBit 10, minWin=27, winSum=451
1358 14:51:02.192410 TX Vref=24, minBit 8, minWin=27, winSum=452
1359 14:51:02.196325 TX Vref=26, minBit 5, minWin=28, winSum=457
1360 14:51:02.199509 TX Vref=28, minBit 5, minWin=28, winSum=456
1361 14:51:02.202501 TX Vref=30, minBit 5, minWin=28, winSum=458
1362 14:51:02.206396 TX Vref=32, minBit 4, minWin=28, winSum=454
1363 14:51:02.212783 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
1364 14:51:02.213244
1365 14:51:02.216055 Final TX Range 1 Vref 30
1366 14:51:02.216507
1367 14:51:02.216839 ==
1368 14:51:02.219218 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 14:51:02.222504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 14:51:02.222805 ==
1371 14:51:02.223040
1372 14:51:02.223260
1373 14:51:02.225880 TX Vref Scan disable
1374 14:51:02.228958 == TX Byte 0 ==
1375 14:51:02.232617 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1376 14:51:02.236014 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1377 14:51:02.239116 == TX Byte 1 ==
1378 14:51:02.242665 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1379 14:51:02.246068 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1380 14:51:02.246387
1381 14:51:02.249353 [DATLAT]
1382 14:51:02.249650 Freq=800, CH0 RK1
1383 14:51:02.249889
1384 14:51:02.253162 DATLAT Default: 0xa
1385 14:51:02.253458 0, 0xFFFF, sum = 0
1386 14:51:02.255885 1, 0xFFFF, sum = 0
1387 14:51:02.255967 2, 0xFFFF, sum = 0
1388 14:51:02.259001 3, 0xFFFF, sum = 0
1389 14:51:02.259083 4, 0xFFFF, sum = 0
1390 14:51:02.262881 5, 0xFFFF, sum = 0
1391 14:51:02.262964 6, 0xFFFF, sum = 0
1392 14:51:02.266267 7, 0xFFFF, sum = 0
1393 14:51:02.266355 8, 0xFFFF, sum = 0
1394 14:51:02.269508 9, 0x0, sum = 1
1395 14:51:02.269596 10, 0x0, sum = 2
1396 14:51:02.273360 11, 0x0, sum = 3
1397 14:51:02.273902 12, 0x0, sum = 4
1398 14:51:02.276669 best_step = 10
1399 14:51:02.277084
1400 14:51:02.277412 ==
1401 14:51:02.279696 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 14:51:02.283125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 14:51:02.283551 ==
1404 14:51:02.283880 RX Vref Scan: 0
1405 14:51:02.286599
1406 14:51:02.287016 RX Vref 0 -> 0, step: 1
1407 14:51:02.287347
1408 14:51:02.289807 RX Delay -79 -> 252, step: 8
1409 14:51:02.292893 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1410 14:51:02.299825 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1411 14:51:02.303440 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1412 14:51:02.307096 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1413 14:51:02.309845 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1414 14:51:02.313365 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1415 14:51:02.319882 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1416 14:51:02.323322 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1417 14:51:02.326474 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1418 14:51:02.329915 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1419 14:51:02.333498 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1420 14:51:02.336640 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1421 14:51:02.343201 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1422 14:51:02.346647 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1423 14:51:02.349798 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1424 14:51:02.353253 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1425 14:51:02.353346 ==
1426 14:51:02.356457 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 14:51:02.363052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 14:51:02.363134 ==
1429 14:51:02.363198 DQS Delay:
1430 14:51:02.366464 DQS0 = 0, DQS1 = 0
1431 14:51:02.366550 DQM Delay:
1432 14:51:02.366618 DQM0 = 92, DQM1 = 83
1433 14:51:02.369833 DQ Delay:
1434 14:51:02.373099 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1435 14:51:02.376130 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1436 14:51:02.379457 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1437 14:51:02.383699 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1438 14:51:02.384111
1439 14:51:02.384486
1440 14:51:02.390103 [DQSOSCAuto] RK1, (LSB)MR18= 0x4010, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1441 14:51:02.393439 CH0 RK1: MR19=606, MR18=4010
1442 14:51:02.400503 CH0_RK1: MR19=0x606, MR18=0x4010, DQSOSC=393, MR23=63, INC=95, DEC=63
1443 14:51:02.403656 [RxdqsGatingPostProcess] freq 800
1444 14:51:02.406816 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 14:51:02.410378 Pre-setting of DQS Precalculation
1446 14:51:02.416510 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 14:51:02.416591 ==
1448 14:51:02.420241 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 14:51:02.423355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 14:51:02.423441 ==
1451 14:51:02.430368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 14:51:02.433904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 14:51:02.444615 [CA 0] Center 36 (6~67) winsize 62
1454 14:51:02.447801 [CA 1] Center 36 (6~67) winsize 62
1455 14:51:02.451421 [CA 2] Center 35 (5~66) winsize 62
1456 14:51:02.454404 [CA 3] Center 34 (4~65) winsize 62
1457 14:51:02.457815 [CA 4] Center 35 (5~65) winsize 61
1458 14:51:02.461256 [CA 5] Center 34 (4~65) winsize 62
1459 14:51:02.461811
1460 14:51:02.464924 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1461 14:51:02.465479
1462 14:51:02.467810 [CATrainingPosCal] consider 1 rank data
1463 14:51:02.471473 u2DelayCellTimex100 = 270/100 ps
1464 14:51:02.474383 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 14:51:02.478073 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 14:51:02.481431 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1467 14:51:02.488119 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 14:51:02.491301 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 14:51:02.494380 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 14:51:02.494812
1471 14:51:02.497655 CA PerBit enable=1, Macro0, CA PI delay=34
1472 14:51:02.498072
1473 14:51:02.500997 [CBTSetCACLKResult] CA Dly = 34
1474 14:51:02.501411 CS Dly: 6 (0~37)
1475 14:51:02.501739 ==
1476 14:51:02.505151 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 14:51:02.512646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 14:51:02.513068 ==
1479 14:51:02.514392 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 14:51:02.521042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 14:51:02.531077 [CA 0] Center 36 (6~67) winsize 62
1482 14:51:02.534366 [CA 1] Center 36 (6~67) winsize 62
1483 14:51:02.537873 [CA 2] Center 35 (4~66) winsize 63
1484 14:51:02.541702 [CA 3] Center 34 (4~65) winsize 62
1485 14:51:02.545531 [CA 4] Center 34 (4~65) winsize 62
1486 14:51:02.549295 [CA 5] Center 34 (4~65) winsize 62
1487 14:51:02.549812
1488 14:51:02.553076 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1489 14:51:02.553631
1490 14:51:02.556563 [CATrainingPosCal] consider 2 rank data
1491 14:51:02.556999 u2DelayCellTimex100 = 270/100 ps
1492 14:51:02.559931 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 14:51:02.566574 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 14:51:02.570188 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1495 14:51:02.573475 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 14:51:02.576395 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 14:51:02.579971 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 14:51:02.580427
1499 14:51:02.583224 CA PerBit enable=1, Macro0, CA PI delay=34
1500 14:51:02.583646
1501 14:51:02.587106 [CBTSetCACLKResult] CA Dly = 34
1502 14:51:02.587624 CS Dly: 7 (0~39)
1503 14:51:02.589937
1504 14:51:02.593369 ----->DramcWriteLeveling(PI) begin...
1505 14:51:02.593808 ==
1506 14:51:02.596817 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 14:51:02.599840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 14:51:02.600257 ==
1509 14:51:02.603025 Write leveling (Byte 0): 27 => 27
1510 14:51:02.606579 Write leveling (Byte 1): 31 => 31
1511 14:51:02.610182 DramcWriteLeveling(PI) end<-----
1512 14:51:02.610600
1513 14:51:02.610930 ==
1514 14:51:02.613324 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 14:51:02.616634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 14:51:02.617053 ==
1517 14:51:02.620107 [Gating] SW mode calibration
1518 14:51:02.626447 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 14:51:02.633417 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 14:51:02.636691 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 14:51:02.639849 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 14:51:02.643642 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 14:51:02.649956 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 14:51:02.653277 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 14:51:02.656838 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 14:51:02.663618 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 14:51:02.666743 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 14:51:02.670330 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 14:51:02.676450 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 14:51:02.680179 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 14:51:02.683212 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 14:51:02.690112 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 14:51:02.693370 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 14:51:02.697006 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 14:51:02.703999 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 14:51:02.706993 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 14:51:02.709964 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 14:51:02.716921 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1539 14:51:02.719792 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 14:51:02.723868 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 14:51:02.727125 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 14:51:02.733750 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 14:51:02.736607 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 14:51:02.740163 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 14:51:02.746688 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1546 14:51:02.750026 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1547 14:51:02.753627 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 14:51:02.760285 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 14:51:02.763301 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 14:51:02.767069 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 14:51:02.773506 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 14:51:02.776949 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1553 14:51:02.780379 0 10 4 | B1->B0 | 3030 2727 | 0 0 | (1 1) (1 0)
1554 14:51:02.787067 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
1555 14:51:02.790208 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 14:51:02.793565 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 14:51:02.800414 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 14:51:02.803524 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 14:51:02.806712 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 14:51:02.813600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 14:51:02.816637 0 11 4 | B1->B0 | 2e2e 3939 | 1 0 | (0 0) (0 0)
1562 14:51:02.820719 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1563 14:51:02.823289 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 14:51:02.830073 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 14:51:02.833404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 14:51:02.836814 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 14:51:02.843732 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 14:51:02.847597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 14:51:02.850699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1570 14:51:02.856989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 14:51:02.860311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 14:51:02.863732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 14:51:02.870535 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 14:51:02.873443 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 14:51:02.877294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 14:51:02.884167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 14:51:02.887601 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 14:51:02.890669 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 14:51:02.893900 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 14:51:02.900206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 14:51:02.903458 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 14:51:02.907001 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 14:51:02.913776 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 14:51:02.916700 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1585 14:51:02.920568 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 14:51:02.927339 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 14:51:02.930494 Total UI for P1: 0, mck2ui 16
1588 14:51:02.933410 best dqsien dly found for B0: ( 0, 14, 2)
1589 14:51:02.933826 Total UI for P1: 0, mck2ui 16
1590 14:51:02.940527 best dqsien dly found for B1: ( 0, 14, 4)
1591 14:51:02.943550 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1592 14:51:02.947106 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1593 14:51:02.947525
1594 14:51:02.950610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1595 14:51:02.953576 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1596 14:51:02.957163 [Gating] SW calibration Done
1597 14:51:02.957627 ==
1598 14:51:02.960569 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 14:51:02.963358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 14:51:02.963842 ==
1601 14:51:02.967396 RX Vref Scan: 0
1602 14:51:02.967812
1603 14:51:02.968219 RX Vref 0 -> 0, step: 1
1604 14:51:02.968582
1605 14:51:02.970302 RX Delay -130 -> 252, step: 16
1606 14:51:02.973619 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1607 14:51:02.980594 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1608 14:51:02.983584 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1609 14:51:02.987473 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1610 14:51:02.990131 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1611 14:51:02.993686 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1612 14:51:03.000548 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1613 14:51:03.003837 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1614 14:51:03.007159 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1615 14:51:03.010162 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1616 14:51:03.014165 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1617 14:51:03.020256 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1618 14:51:03.023519 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1619 14:51:03.027091 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1620 14:51:03.030394 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1621 14:51:03.034040 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1622 14:51:03.034475 ==
1623 14:51:03.037079 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 14:51:03.043858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 14:51:03.044483 ==
1626 14:51:03.045028 DQS Delay:
1627 14:51:03.047414 DQS0 = 0, DQS1 = 0
1628 14:51:03.047824 DQM Delay:
1629 14:51:03.048155 DQM0 = 93, DQM1 = 89
1630 14:51:03.050706 DQ Delay:
1631 14:51:03.053678 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1632 14:51:03.057319 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1633 14:51:03.060762 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1634 14:51:03.063569 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1635 14:51:03.064295
1636 14:51:03.064968
1637 14:51:03.065661 ==
1638 14:51:03.067227 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 14:51:03.070337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 14:51:03.070419 ==
1641 14:51:03.070482
1642 14:51:03.070541
1643 14:51:03.073396 TX Vref Scan disable
1644 14:51:03.073476 == TX Byte 0 ==
1645 14:51:03.080308 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1646 14:51:03.083503 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1647 14:51:03.083611 == TX Byte 1 ==
1648 14:51:03.090426 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1649 14:51:03.093422 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1650 14:51:03.093503 ==
1651 14:51:03.097020 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 14:51:03.101016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 14:51:03.101094 ==
1654 14:51:03.114600 TX Vref=22, minBit 1, minWin=26, winSum=436
1655 14:51:03.117738 TX Vref=24, minBit 0, minWin=26, winSum=440
1656 14:51:03.121658 TX Vref=26, minBit 1, minWin=27, winSum=443
1657 14:51:03.124439 TX Vref=28, minBit 1, minWin=27, winSum=445
1658 14:51:03.127928 TX Vref=30, minBit 1, minWin=27, winSum=446
1659 14:51:03.131637 TX Vref=32, minBit 2, minWin=26, winSum=444
1660 14:51:03.138013 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 30
1661 14:51:03.138151
1662 14:51:03.141034 Final TX Range 1 Vref 30
1663 14:51:03.141116
1664 14:51:03.141180 ==
1665 14:51:03.144346 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 14:51:03.147633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 14:51:03.147716 ==
1668 14:51:03.147780
1669 14:51:03.150839
1670 14:51:03.150921 TX Vref Scan disable
1671 14:51:03.154388 == TX Byte 0 ==
1672 14:51:03.157769 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1673 14:51:03.161460 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1674 14:51:03.164195 == TX Byte 1 ==
1675 14:51:03.167781 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1676 14:51:03.171156 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1677 14:51:03.174236
1678 14:51:03.174372 [DATLAT]
1679 14:51:03.174471 Freq=800, CH1 RK0
1680 14:51:03.174560
1681 14:51:03.178072 DATLAT Default: 0xa
1682 14:51:03.178208 0, 0xFFFF, sum = 0
1683 14:51:03.181344 1, 0xFFFF, sum = 0
1684 14:51:03.181475 2, 0xFFFF, sum = 0
1685 14:51:03.184546 3, 0xFFFF, sum = 0
1686 14:51:03.184702 4, 0xFFFF, sum = 0
1687 14:51:03.188234 5, 0xFFFF, sum = 0
1688 14:51:03.188460 6, 0xFFFF, sum = 0
1689 14:51:03.191341 7, 0xFFFF, sum = 0
1690 14:51:03.194373 8, 0xFFFF, sum = 0
1691 14:51:03.194671 9, 0x0, sum = 1
1692 14:51:03.194925 10, 0x0, sum = 2
1693 14:51:03.198164 11, 0x0, sum = 3
1694 14:51:03.198403 12, 0x0, sum = 4
1695 14:51:03.201238 best_step = 10
1696 14:51:03.201530
1697 14:51:03.201769 ==
1698 14:51:03.204926 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 14:51:03.208109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 14:51:03.208588 ==
1701 14:51:03.211756 RX Vref Scan: 1
1702 14:51:03.212384
1703 14:51:03.212737 Set Vref Range= 32 -> 127
1704 14:51:03.213045
1705 14:51:03.215057 RX Vref 32 -> 127, step: 1
1706 14:51:03.215575
1707 14:51:03.218257 RX Delay -63 -> 252, step: 8
1708 14:51:03.218808
1709 14:51:03.221346 Set Vref, RX VrefLevel [Byte0]: 32
1710 14:51:03.225296 [Byte1]: 32
1711 14:51:03.225802
1712 14:51:03.228190 Set Vref, RX VrefLevel [Byte0]: 33
1713 14:51:03.231663 [Byte1]: 33
1714 14:51:03.234788
1715 14:51:03.235213 Set Vref, RX VrefLevel [Byte0]: 34
1716 14:51:03.238464 [Byte1]: 34
1717 14:51:03.242627
1718 14:51:03.243084 Set Vref, RX VrefLevel [Byte0]: 35
1719 14:51:03.245743 [Byte1]: 35
1720 14:51:03.250458
1721 14:51:03.251306 Set Vref, RX VrefLevel [Byte0]: 36
1722 14:51:03.253038 [Byte1]: 36
1723 14:51:03.257659
1724 14:51:03.258120 Set Vref, RX VrefLevel [Byte0]: 37
1725 14:51:03.261114 [Byte1]: 37
1726 14:51:03.264946
1727 14:51:03.265492 Set Vref, RX VrefLevel [Byte0]: 38
1728 14:51:03.268379 [Byte1]: 38
1729 14:51:03.272583
1730 14:51:03.273108 Set Vref, RX VrefLevel [Byte0]: 39
1731 14:51:03.275963 [Byte1]: 39
1732 14:51:03.279907
1733 14:51:03.280473 Set Vref, RX VrefLevel [Byte0]: 40
1734 14:51:03.283894 [Byte1]: 40
1735 14:51:03.288093
1736 14:51:03.288678 Set Vref, RX VrefLevel [Byte0]: 41
1737 14:51:03.291410 [Byte1]: 41
1738 14:51:03.294863
1739 14:51:03.295372 Set Vref, RX VrefLevel [Byte0]: 42
1740 14:51:03.298401 [Byte1]: 42
1741 14:51:03.302612
1742 14:51:03.303086 Set Vref, RX VrefLevel [Byte0]: 43
1743 14:51:03.305529 [Byte1]: 43
1744 14:51:03.310090
1745 14:51:03.310552 Set Vref, RX VrefLevel [Byte0]: 44
1746 14:51:03.312939 [Byte1]: 44
1747 14:51:03.317352
1748 14:51:03.317760 Set Vref, RX VrefLevel [Byte0]: 45
1749 14:51:03.321350 [Byte1]: 45
1750 14:51:03.324891
1751 14:51:03.325313 Set Vref, RX VrefLevel [Byte0]: 46
1752 14:51:03.328004 [Byte1]: 46
1753 14:51:03.332426
1754 14:51:03.332969 Set Vref, RX VrefLevel [Byte0]: 47
1755 14:51:03.335921 [Byte1]: 47
1756 14:51:03.339892
1757 14:51:03.340559 Set Vref, RX VrefLevel [Byte0]: 48
1758 14:51:03.342810 [Byte1]: 48
1759 14:51:03.347301
1760 14:51:03.347713 Set Vref, RX VrefLevel [Byte0]: 49
1761 14:51:03.350406 [Byte1]: 49
1762 14:51:03.354660
1763 14:51:03.358172 Set Vref, RX VrefLevel [Byte0]: 50
1764 14:51:03.361513 [Byte1]: 50
1765 14:51:03.361944
1766 14:51:03.364415 Set Vref, RX VrefLevel [Byte0]: 51
1767 14:51:03.368262 [Byte1]: 51
1768 14:51:03.368814
1769 14:51:03.371333 Set Vref, RX VrefLevel [Byte0]: 52
1770 14:51:03.374464 [Byte1]: 52
1771 14:51:03.375000
1772 14:51:03.378259 Set Vref, RX VrefLevel [Byte0]: 53
1773 14:51:03.381233 [Byte1]: 53
1774 14:51:03.384712
1775 14:51:03.385126 Set Vref, RX VrefLevel [Byte0]: 54
1776 14:51:03.388158 [Byte1]: 54
1777 14:51:03.392297
1778 14:51:03.392927 Set Vref, RX VrefLevel [Byte0]: 55
1779 14:51:03.395536 [Byte1]: 55
1780 14:51:03.399941
1781 14:51:03.400399 Set Vref, RX VrefLevel [Byte0]: 56
1782 14:51:03.403313 [Byte1]: 56
1783 14:51:03.407698
1784 14:51:03.408227 Set Vref, RX VrefLevel [Byte0]: 57
1785 14:51:03.410684 [Byte1]: 57
1786 14:51:03.415133
1787 14:51:03.415541 Set Vref, RX VrefLevel [Byte0]: 58
1788 14:51:03.418731 [Byte1]: 58
1789 14:51:03.422716
1790 14:51:03.423229 Set Vref, RX VrefLevel [Byte0]: 59
1791 14:51:03.425481 [Byte1]: 59
1792 14:51:03.429965
1793 14:51:03.430426 Set Vref, RX VrefLevel [Byte0]: 60
1794 14:51:03.433333 [Byte1]: 60
1795 14:51:03.437574
1796 14:51:03.437987 Set Vref, RX VrefLevel [Byte0]: 61
1797 14:51:03.440889 [Byte1]: 61
1798 14:51:03.444884
1799 14:51:03.445296 Set Vref, RX VrefLevel [Byte0]: 62
1800 14:51:03.448041 [Byte1]: 62
1801 14:51:03.451988
1802 14:51:03.452069 Set Vref, RX VrefLevel [Byte0]: 63
1803 14:51:03.455065 [Byte1]: 63
1804 14:51:03.459496
1805 14:51:03.459583 Set Vref, RX VrefLevel [Byte0]: 64
1806 14:51:03.462680 [Byte1]: 64
1807 14:51:03.466987
1808 14:51:03.467091 Set Vref, RX VrefLevel [Byte0]: 65
1809 14:51:03.470682 [Byte1]: 65
1810 14:51:03.474850
1811 14:51:03.474959 Set Vref, RX VrefLevel [Byte0]: 66
1812 14:51:03.477946 [Byte1]: 66
1813 14:51:03.482264
1814 14:51:03.482357 Set Vref, RX VrefLevel [Byte0]: 67
1815 14:51:03.485064 [Byte1]: 67
1816 14:51:03.489194
1817 14:51:03.489299 Set Vref, RX VrefLevel [Byte0]: 68
1818 14:51:03.492970 [Byte1]: 68
1819 14:51:03.496677
1820 14:51:03.496758 Set Vref, RX VrefLevel [Byte0]: 69
1821 14:51:03.500166 [Byte1]: 69
1822 14:51:03.504755
1823 14:51:03.504863 Set Vref, RX VrefLevel [Byte0]: 70
1824 14:51:03.507780 [Byte1]: 70
1825 14:51:03.511719
1826 14:51:03.511799 Final RX Vref Byte 0 = 54 to rank0
1827 14:51:03.515638 Final RX Vref Byte 1 = 59 to rank0
1828 14:51:03.518776 Final RX Vref Byte 0 = 54 to rank1
1829 14:51:03.522163 Final RX Vref Byte 1 = 59 to rank1==
1830 14:51:03.525446 Dram Type= 6, Freq= 0, CH_1, rank 0
1831 14:51:03.531875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 14:51:03.531957 ==
1833 14:51:03.532021 DQS Delay:
1834 14:51:03.532080 DQS0 = 0, DQS1 = 0
1835 14:51:03.535590 DQM Delay:
1836 14:51:03.535670 DQM0 = 94, DQM1 = 89
1837 14:51:03.538664 DQ Delay:
1838 14:51:03.541934 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1839 14:51:03.542040 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1840 14:51:03.545267 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1841 14:51:03.552068 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1842 14:51:03.552149
1843 14:51:03.552213
1844 14:51:03.558558 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1845 14:51:03.562094 CH1 RK0: MR19=606, MR18=2D49
1846 14:51:03.568936 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1847 14:51:03.569017
1848 14:51:03.571796 ----->DramcWriteLeveling(PI) begin...
1849 14:51:03.571878 ==
1850 14:51:03.575520 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 14:51:03.578571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 14:51:03.578657 ==
1853 14:51:03.582367 Write leveling (Byte 0): 26 => 26
1854 14:51:03.585685 Write leveling (Byte 1): 27 => 27
1855 14:51:03.588624 DramcWriteLeveling(PI) end<-----
1856 14:51:03.588705
1857 14:51:03.588768 ==
1858 14:51:03.591886 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 14:51:03.595358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 14:51:03.595439 ==
1861 14:51:03.598706 [Gating] SW mode calibration
1862 14:51:03.605339 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1863 14:51:03.611982 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1864 14:51:03.615482 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1865 14:51:03.618625 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1866 14:51:03.625285 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 14:51:03.628346 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 14:51:03.632249 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 14:51:03.639160 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 14:51:03.642120 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 14:51:03.645402 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 14:51:03.652204 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 14:51:03.655500 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 14:51:03.659101 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 14:51:03.662216 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 14:51:03.669023 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 14:51:03.672195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 14:51:03.675452 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 14:51:03.681862 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 14:51:03.685496 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1881 14:51:03.688582 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1882 14:51:03.695480 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 14:51:03.699250 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 14:51:03.702085 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 14:51:03.708754 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 14:51:03.712324 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 14:51:03.715978 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 14:51:03.722487 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 14:51:03.725699 0 9 4 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1890 14:51:03.729191 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1891 14:51:03.735730 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 14:51:03.739483 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 14:51:03.742329 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 14:51:03.745580 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 14:51:03.752380 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 14:51:03.756015 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1897 14:51:03.758950 0 10 4 | B1->B0 | 2a2a 3030 | 0 1 | (0 0) (0 0)
1898 14:51:03.765718 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1899 14:51:03.769105 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 14:51:03.772828 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 14:51:03.779265 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 14:51:03.782937 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 14:51:03.785888 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 14:51:03.792558 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1905 14:51:03.795484 0 11 4 | B1->B0 | 3b3b 3131 | 0 0 | (0 0) (1 1)
1906 14:51:03.799139 0 11 8 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
1907 14:51:03.805476 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 14:51:03.809087 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 14:51:03.812827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 14:51:03.818857 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 14:51:03.822429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 14:51:03.826080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 14:51:03.829213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1914 14:51:03.835958 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1915 14:51:03.839124 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 14:51:03.842613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 14:51:03.849193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 14:51:03.852532 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 14:51:03.856231 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 14:51:03.862915 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 14:51:03.865904 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 14:51:03.869370 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 14:51:03.875954 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 14:51:03.879734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 14:51:03.882990 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 14:51:03.886149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 14:51:03.893111 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 14:51:03.896068 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 14:51:03.899904 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1930 14:51:03.906230 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 14:51:03.909731 Total UI for P1: 0, mck2ui 16
1932 14:51:03.913266 best dqsien dly found for B0: ( 0, 14, 4)
1933 14:51:03.915815 Total UI for P1: 0, mck2ui 16
1934 14:51:03.919635 best dqsien dly found for B1: ( 0, 14, 4)
1935 14:51:03.923058 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1936 14:51:03.926068 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1937 14:51:03.926149
1938 14:51:03.929542 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1939 14:51:03.933181 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1940 14:51:03.936125 [Gating] SW calibration Done
1941 14:51:03.936231 ==
1942 14:51:03.939678 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 14:51:03.943118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 14:51:03.943231 ==
1945 14:51:03.946378 RX Vref Scan: 0
1946 14:51:03.946459
1947 14:51:03.946522 RX Vref 0 -> 0, step: 1
1948 14:51:03.946581
1949 14:51:03.949839 RX Delay -130 -> 252, step: 16
1950 14:51:03.952629 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1951 14:51:03.959480 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1952 14:51:03.963123 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1953 14:51:03.966272 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1954 14:51:03.969944 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1955 14:51:03.972892 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1956 14:51:03.979680 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1957 14:51:03.983000 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1958 14:51:03.986297 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1959 14:51:03.989739 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1960 14:51:03.992727 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1961 14:51:03.999797 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1962 14:51:04.002814 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1963 14:51:04.006598 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1964 14:51:04.009933 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1965 14:51:04.012863 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1966 14:51:04.016220 ==
1967 14:51:04.016327 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 14:51:04.022869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 14:51:04.022950 ==
1970 14:51:04.023014 DQS Delay:
1971 14:51:04.026473 DQS0 = 0, DQS1 = 0
1972 14:51:04.026579 DQM Delay:
1973 14:51:04.026672 DQM0 = 91, DQM1 = 87
1974 14:51:04.029699 DQ Delay:
1975 14:51:04.033258 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1976 14:51:04.036796 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1977 14:51:04.040000 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1978 14:51:04.043281 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1979 14:51:04.043361
1980 14:51:04.043429
1981 14:51:04.043496 ==
1982 14:51:04.046457 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 14:51:04.049558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 14:51:04.049638 ==
1985 14:51:04.049703
1986 14:51:04.049760
1987 14:51:04.052877 TX Vref Scan disable
1988 14:51:04.056514 == TX Byte 0 ==
1989 14:51:04.059550 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1990 14:51:04.063225 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1991 14:51:04.066494 == TX Byte 1 ==
1992 14:51:04.069650 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1993 14:51:04.073134 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1994 14:51:04.073216 ==
1995 14:51:04.076467 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 14:51:04.080130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 14:51:04.080273 ==
1998 14:51:04.093912 TX Vref=22, minBit 1, minWin=26, winSum=435
1999 14:51:04.098053 TX Vref=24, minBit 1, minWin=26, winSum=443
2000 14:51:04.100971 TX Vref=26, minBit 1, minWin=26, winSum=445
2001 14:51:04.104072 TX Vref=28, minBit 2, minWin=27, winSum=450
2002 14:51:04.107726 TX Vref=30, minBit 0, minWin=27, winSum=444
2003 14:51:04.110736 TX Vref=32, minBit 0, minWin=27, winSum=445
2004 14:51:04.117445 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
2005 14:51:04.117527
2006 14:51:04.121097 Final TX Range 1 Vref 28
2007 14:51:04.121169
2008 14:51:04.121229 ==
2009 14:51:04.124649 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 14:51:04.127512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 14:51:04.127584 ==
2012 14:51:04.127644
2013 14:51:04.127699
2014 14:51:04.131015 TX Vref Scan disable
2015 14:51:04.134517 == TX Byte 0 ==
2016 14:51:04.137649 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2017 14:51:04.140787 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2018 14:51:04.144286 == TX Byte 1 ==
2019 14:51:04.147357 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2020 14:51:04.150594 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2021 14:51:04.150700
2022 14:51:04.153826 [DATLAT]
2023 14:51:04.153907 Freq=800, CH1 RK1
2024 14:51:04.153971
2025 14:51:04.157917 DATLAT Default: 0xa
2026 14:51:04.158022 0, 0xFFFF, sum = 0
2027 14:51:04.160930 1, 0xFFFF, sum = 0
2028 14:51:04.161009 2, 0xFFFF, sum = 0
2029 14:51:04.164035 3, 0xFFFF, sum = 0
2030 14:51:04.164106 4, 0xFFFF, sum = 0
2031 14:51:04.167579 5, 0xFFFF, sum = 0
2032 14:51:04.167662 6, 0xFFFF, sum = 0
2033 14:51:04.170765 7, 0xFFFF, sum = 0
2034 14:51:04.170847 8, 0xFFFF, sum = 0
2035 14:51:04.174313 9, 0x0, sum = 1
2036 14:51:04.174395 10, 0x0, sum = 2
2037 14:51:04.177804 11, 0x0, sum = 3
2038 14:51:04.177885 12, 0x0, sum = 4
2039 14:51:04.180808 best_step = 10
2040 14:51:04.180888
2041 14:51:04.180951 ==
2042 14:51:04.184807 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 14:51:04.187806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 14:51:04.187912 ==
2045 14:51:04.191329 RX Vref Scan: 0
2046 14:51:04.191435
2047 14:51:04.191528 RX Vref 0 -> 0, step: 1
2048 14:51:04.191661
2049 14:51:04.194275 RX Delay -79 -> 252, step: 8
2050 14:51:04.201100 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2051 14:51:04.204120 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2052 14:51:04.207896 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2053 14:51:04.211190 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2054 14:51:04.214255 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2055 14:51:04.217880 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2056 14:51:04.224080 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2057 14:51:04.227973 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2058 14:51:04.231212 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2059 14:51:04.234577 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2060 14:51:04.237571 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2061 14:51:04.240697 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2062 14:51:04.247495 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2063 14:51:04.251369 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2064 14:51:04.254242 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2065 14:51:04.257257 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2066 14:51:04.257339 ==
2067 14:51:04.260923 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 14:51:04.267339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 14:51:04.267425 ==
2070 14:51:04.267513 DQS Delay:
2071 14:51:04.271169 DQS0 = 0, DQS1 = 0
2072 14:51:04.271240 DQM Delay:
2073 14:51:04.271299 DQM0 = 97, DQM1 = 91
2074 14:51:04.274335 DQ Delay:
2075 14:51:04.278025 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2076 14:51:04.280867 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2077 14:51:04.283971 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2078 14:51:04.287812 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2079 14:51:04.287892
2080 14:51:04.287955
2081 14:51:04.294655 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2082 14:51:04.297639 CH1 RK1: MR19=606, MR18=440E
2083 14:51:04.304719 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2084 14:51:04.307928 [RxdqsGatingPostProcess] freq 800
2085 14:51:04.310775 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2086 14:51:04.314497 Pre-setting of DQS Precalculation
2087 14:51:04.320714 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2088 14:51:04.327322 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2089 14:51:04.334261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2090 14:51:04.334348
2091 14:51:04.334416
2092 14:51:04.337757 [Calibration Summary] 1600 Mbps
2093 14:51:04.337849 CH 0, Rank 0
2094 14:51:04.341230 SW Impedance : PASS
2095 14:51:04.344277 DUTY Scan : NO K
2096 14:51:04.344396 ZQ Calibration : PASS
2097 14:51:04.347932 Jitter Meter : NO K
2098 14:51:04.350921 CBT Training : PASS
2099 14:51:04.351030 Write leveling : PASS
2100 14:51:04.354763 RX DQS gating : PASS
2101 14:51:04.357742 RX DQ/DQS(RDDQC) : PASS
2102 14:51:04.357875 TX DQ/DQS : PASS
2103 14:51:04.360825 RX DATLAT : PASS
2104 14:51:04.361005 RX DQ/DQS(Engine): PASS
2105 14:51:04.364150 TX OE : NO K
2106 14:51:04.364362 All Pass.
2107 14:51:04.364533
2108 14:51:04.367669 CH 0, Rank 1
2109 14:51:04.367857 SW Impedance : PASS
2110 14:51:04.371354 DUTY Scan : NO K
2111 14:51:04.374602 ZQ Calibration : PASS
2112 14:51:04.374798 Jitter Meter : NO K
2113 14:51:04.377563 CBT Training : PASS
2114 14:51:04.380914 Write leveling : PASS
2115 14:51:04.381150 RX DQS gating : PASS
2116 14:51:04.384825 RX DQ/DQS(RDDQC) : PASS
2117 14:51:04.388129 TX DQ/DQS : PASS
2118 14:51:04.388710 RX DATLAT : PASS
2119 14:51:04.391330 RX DQ/DQS(Engine): PASS
2120 14:51:04.394629 TX OE : NO K
2121 14:51:04.395072 All Pass.
2122 14:51:04.395455
2123 14:51:04.395806 CH 1, Rank 0
2124 14:51:04.397988 SW Impedance : PASS
2125 14:51:04.401172 DUTY Scan : NO K
2126 14:51:04.401680 ZQ Calibration : PASS
2127 14:51:04.404691 Jitter Meter : NO K
2128 14:51:04.405224 CBT Training : PASS
2129 14:51:04.408458 Write leveling : PASS
2130 14:51:04.411423 RX DQS gating : PASS
2131 14:51:04.411834 RX DQ/DQS(RDDQC) : PASS
2132 14:51:04.414985 TX DQ/DQS : PASS
2133 14:51:04.418386 RX DATLAT : PASS
2134 14:51:04.418894 RX DQ/DQS(Engine): PASS
2135 14:51:04.421464 TX OE : NO K
2136 14:51:04.421880 All Pass.
2137 14:51:04.422234
2138 14:51:04.425079 CH 1, Rank 1
2139 14:51:04.425492 SW Impedance : PASS
2140 14:51:04.428323 DUTY Scan : NO K
2141 14:51:04.431529 ZQ Calibration : PASS
2142 14:51:04.431944 Jitter Meter : NO K
2143 14:51:04.434984 CBT Training : PASS
2144 14:51:04.438206 Write leveling : PASS
2145 14:51:04.438658 RX DQS gating : PASS
2146 14:51:04.441927 RX DQ/DQS(RDDQC) : PASS
2147 14:51:04.442431 TX DQ/DQS : PASS
2148 14:51:04.445245 RX DATLAT : PASS
2149 14:51:04.449148 RX DQ/DQS(Engine): PASS
2150 14:51:04.449575 TX OE : NO K
2151 14:51:04.452077 All Pass.
2152 14:51:04.452461
2153 14:51:04.452764 DramC Write-DBI off
2154 14:51:04.455640 PER_BANK_REFRESH: Hybrid Mode
2155 14:51:04.456055 TX_TRACKING: ON
2156 14:51:04.458840 [GetDramInforAfterCalByMRR] Vendor 6.
2157 14:51:04.465323 [GetDramInforAfterCalByMRR] Revision 606.
2158 14:51:04.468466 [GetDramInforAfterCalByMRR] Revision 2 0.
2159 14:51:04.468911 MR0 0x3b3b
2160 14:51:04.469336 MR8 0x5151
2161 14:51:04.472324 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 14:51:04.472865
2163 14:51:04.475419 MR0 0x3b3b
2164 14:51:04.475874 MR8 0x5151
2165 14:51:04.478652 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 14:51:04.479029
2167 14:51:04.488899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2168 14:51:04.491643 [FAST_K] Save calibration result to emmc
2169 14:51:04.495301 [FAST_K] Save calibration result to emmc
2170 14:51:04.498751 dram_init: config_dvfs: 1
2171 14:51:04.501794 dramc_set_vcore_voltage set vcore to 662500
2172 14:51:04.505220 Read voltage for 1200, 2
2173 14:51:04.505633 Vio18 = 0
2174 14:51:04.505960 Vcore = 662500
2175 14:51:04.508232 Vdram = 0
2176 14:51:04.508684 Vddq = 0
2177 14:51:04.509039 Vmddr = 0
2178 14:51:04.514958 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2179 14:51:04.518552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2180 14:51:04.522726 MEM_TYPE=3, freq_sel=15
2181 14:51:04.525346 sv_algorithm_assistance_LP4_1600
2182 14:51:04.528325 ============ PULL DRAM RESETB DOWN ============
2183 14:51:04.531782 ========== PULL DRAM RESETB DOWN end =========
2184 14:51:04.538733 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 14:51:04.542158 ===================================
2186 14:51:04.542575 LPDDR4 DRAM CONFIGURATION
2187 14:51:04.545247 ===================================
2188 14:51:04.548293 EX_ROW_EN[0] = 0x0
2189 14:51:04.552018 EX_ROW_EN[1] = 0x0
2190 14:51:04.552625 LP4Y_EN = 0x0
2191 14:51:04.555631 WORK_FSP = 0x0
2192 14:51:04.556201 WL = 0x4
2193 14:51:04.558974 RL = 0x4
2194 14:51:04.559383 BL = 0x2
2195 14:51:04.562123 RPST = 0x0
2196 14:51:04.562533 RD_PRE = 0x0
2197 14:51:04.565461 WR_PRE = 0x1
2198 14:51:04.566053 WR_PST = 0x0
2199 14:51:04.568716 DBI_WR = 0x0
2200 14:51:04.569126 DBI_RD = 0x0
2201 14:51:04.571968 OTF = 0x1
2202 14:51:04.575114 ===================================
2203 14:51:04.579134 ===================================
2204 14:51:04.579550 ANA top config
2205 14:51:04.582300 ===================================
2206 14:51:04.585639 DLL_ASYNC_EN = 0
2207 14:51:04.588287 ALL_SLAVE_EN = 0
2208 14:51:04.588904 NEW_RANK_MODE = 1
2209 14:51:04.592120 DLL_IDLE_MODE = 1
2210 14:51:04.595084 LP45_APHY_COMB_EN = 1
2211 14:51:04.598801 TX_ODT_DIS = 1
2212 14:51:04.601945 NEW_8X_MODE = 1
2213 14:51:04.604817 ===================================
2214 14:51:04.608647 ===================================
2215 14:51:04.609124 data_rate = 2400
2216 14:51:04.611487 CKR = 1
2217 14:51:04.615265 DQ_P2S_RATIO = 8
2218 14:51:04.618543 ===================================
2219 14:51:04.621499 CA_P2S_RATIO = 8
2220 14:51:04.625155 DQ_CA_OPEN = 0
2221 14:51:04.628610 DQ_SEMI_OPEN = 0
2222 14:51:04.629117 CA_SEMI_OPEN = 0
2223 14:51:04.631885 CA_FULL_RATE = 0
2224 14:51:04.635086 DQ_CKDIV4_EN = 0
2225 14:51:04.638409 CA_CKDIV4_EN = 0
2226 14:51:04.641843 CA_PREDIV_EN = 0
2227 14:51:04.645491 PH8_DLY = 17
2228 14:51:04.645910 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2229 14:51:04.648434 DQ_AAMCK_DIV = 4
2230 14:51:04.651548 CA_AAMCK_DIV = 4
2231 14:51:04.655078 CA_ADMCK_DIV = 4
2232 14:51:04.658482 DQ_TRACK_CA_EN = 0
2233 14:51:04.661814 CA_PICK = 1200
2234 14:51:04.665171 CA_MCKIO = 1200
2235 14:51:04.665593 MCKIO_SEMI = 0
2236 14:51:04.668419 PLL_FREQ = 2366
2237 14:51:04.671686 DQ_UI_PI_RATIO = 32
2238 14:51:04.675113 CA_UI_PI_RATIO = 0
2239 14:51:04.678287 ===================================
2240 14:51:04.681483 ===================================
2241 14:51:04.684682 memory_type:LPDDR4
2242 14:51:04.685103 GP_NUM : 10
2243 14:51:04.688647 SRAM_EN : 1
2244 14:51:04.689064 MD32_EN : 0
2245 14:51:04.691642 ===================================
2246 14:51:04.695201 [ANA_INIT] >>>>>>>>>>>>>>
2247 14:51:04.698419 <<<<<< [CONFIGURE PHASE]: ANA_TX
2248 14:51:04.701995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2249 14:51:04.704917 ===================================
2250 14:51:04.708408 data_rate = 2400,PCW = 0X5b00
2251 14:51:04.711972 ===================================
2252 14:51:04.715035 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2253 14:51:04.722133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 14:51:04.724800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 14:51:04.732039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2256 14:51:04.735317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2257 14:51:04.738790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2258 14:51:04.739214 [ANA_INIT] flow start
2259 14:51:04.742370 [ANA_INIT] PLL >>>>>>>>
2260 14:51:04.744892 [ANA_INIT] PLL <<<<<<<<
2261 14:51:04.745315 [ANA_INIT] MIDPI >>>>>>>>
2262 14:51:04.748447 [ANA_INIT] MIDPI <<<<<<<<
2263 14:51:04.751653 [ANA_INIT] DLL >>>>>>>>
2264 14:51:04.752075 [ANA_INIT] DLL <<<<<<<<
2265 14:51:04.755412 [ANA_INIT] flow end
2266 14:51:04.758937 ============ LP4 DIFF to SE enter ============
2267 14:51:04.761910 ============ LP4 DIFF to SE exit ============
2268 14:51:04.765315 [ANA_INIT] <<<<<<<<<<<<<
2269 14:51:04.768662 [Flow] Enable top DCM control >>>>>
2270 14:51:04.771661 [Flow] Enable top DCM control <<<<<
2271 14:51:04.774893 Enable DLL master slave shuffle
2272 14:51:04.782234 ==============================================================
2273 14:51:04.782737 Gating Mode config
2274 14:51:04.788454 ==============================================================
2275 14:51:04.788905 Config description:
2276 14:51:04.798860 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2277 14:51:04.804799 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2278 14:51:04.811597 SELPH_MODE 0: By rank 1: By Phase
2279 14:51:04.815279 ==============================================================
2280 14:51:04.818436 GAT_TRACK_EN = 1
2281 14:51:04.821530 RX_GATING_MODE = 2
2282 14:51:04.824803 RX_GATING_TRACK_MODE = 2
2283 14:51:04.828421 SELPH_MODE = 1
2284 14:51:04.831601 PICG_EARLY_EN = 1
2285 14:51:04.835492 VALID_LAT_VALUE = 1
2286 14:51:04.838397 ==============================================================
2287 14:51:04.844923 Enter into Gating configuration >>>>
2288 14:51:04.845344 Exit from Gating configuration <<<<
2289 14:51:04.848407 Enter into DVFS_PRE_config >>>>>
2290 14:51:04.861484 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2291 14:51:04.865309 Exit from DVFS_PRE_config <<<<<
2292 14:51:04.868662 Enter into PICG configuration >>>>
2293 14:51:04.869086 Exit from PICG configuration <<<<
2294 14:51:04.871709 [RX_INPUT] configuration >>>>>
2295 14:51:04.875214 [RX_INPUT] configuration <<<<<
2296 14:51:04.882000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2297 14:51:04.885327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2298 14:51:04.891817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 14:51:04.898267 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 14:51:04.905046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 14:51:04.911814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 14:51:04.914939 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2303 14:51:04.918365 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2304 14:51:04.921829 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2305 14:51:04.928660 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2306 14:51:04.931864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2307 14:51:04.934880 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 14:51:04.938912 ===================================
2309 14:51:04.942071 LPDDR4 DRAM CONFIGURATION
2310 14:51:04.945115 ===================================
2311 14:51:04.945534 EX_ROW_EN[0] = 0x0
2312 14:51:04.948921 EX_ROW_EN[1] = 0x0
2313 14:51:04.952095 LP4Y_EN = 0x0
2314 14:51:04.952538 WORK_FSP = 0x0
2315 14:51:04.955476 WL = 0x4
2316 14:51:04.955887 RL = 0x4
2317 14:51:04.958934 BL = 0x2
2318 14:51:04.959388 RPST = 0x0
2319 14:51:04.962458 RD_PRE = 0x0
2320 14:51:04.962868 WR_PRE = 0x1
2321 14:51:04.965310 WR_PST = 0x0
2322 14:51:04.965766 DBI_WR = 0x0
2323 14:51:04.968676 DBI_RD = 0x0
2324 14:51:04.969087 OTF = 0x1
2325 14:51:04.971971 ===================================
2326 14:51:04.975498 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2327 14:51:04.982033 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2328 14:51:04.985212 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 14:51:04.988567 ===================================
2330 14:51:04.991799 LPDDR4 DRAM CONFIGURATION
2331 14:51:04.995371 ===================================
2332 14:51:04.995448 EX_ROW_EN[0] = 0x10
2333 14:51:04.998134 EX_ROW_EN[1] = 0x0
2334 14:51:04.998215 LP4Y_EN = 0x0
2335 14:51:05.001416 WORK_FSP = 0x0
2336 14:51:05.001570 WL = 0x4
2337 14:51:05.005055 RL = 0x4
2338 14:51:05.008239 BL = 0x2
2339 14:51:05.008354 RPST = 0x0
2340 14:51:05.011722 RD_PRE = 0x0
2341 14:51:05.011831 WR_PRE = 0x1
2342 14:51:05.015348 WR_PST = 0x0
2343 14:51:05.015455 DBI_WR = 0x0
2344 14:51:05.018423 DBI_RD = 0x0
2345 14:51:05.018504 OTF = 0x1
2346 14:51:05.021813 ===================================
2347 14:51:05.028440 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2348 14:51:05.028545 ==
2349 14:51:05.031535 Dram Type= 6, Freq= 0, CH_0, rank 0
2350 14:51:05.035281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2351 14:51:05.035383 ==
2352 14:51:05.038588 [Duty_Offset_Calibration]
2353 14:51:05.038687 B0:2 B1:1 CA:1
2354 14:51:05.038776
2355 14:51:05.041776 [DutyScan_Calibration_Flow] k_type=0
2356 14:51:05.052881
2357 14:51:05.052954 ==CLK 0==
2358 14:51:05.055926 Final CLK duty delay cell = 0
2359 14:51:05.059558 [0] MAX Duty = 5187%(X100), DQS PI = 24
2360 14:51:05.062709 [0] MIN Duty = 4875%(X100), DQS PI = 0
2361 14:51:05.062780 [0] AVG Duty = 5031%(X100)
2362 14:51:05.066314
2363 14:51:05.066394 CH0 CLK Duty spec in!! Max-Min= 312%
2364 14:51:05.072672 [DutyScan_Calibration_Flow] ====Done====
2365 14:51:05.072754
2366 14:51:05.076022 [DutyScan_Calibration_Flow] k_type=1
2367 14:51:05.091295
2368 14:51:05.091400 ==DQS 0 ==
2369 14:51:05.094837 Final DQS duty delay cell = -4
2370 14:51:05.098158 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2371 14:51:05.101335 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2372 14:51:05.104710 [-4] AVG Duty = 4953%(X100)
2373 14:51:05.104810
2374 14:51:05.104899 ==DQS 1 ==
2375 14:51:05.107934 Final DQS duty delay cell = 0
2376 14:51:05.111260 [0] MAX Duty = 5156%(X100), DQS PI = 62
2377 14:51:05.114737 [0] MIN Duty = 5000%(X100), DQS PI = 34
2378 14:51:05.117687 [0] AVG Duty = 5078%(X100)
2379 14:51:05.117794
2380 14:51:05.121122 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2381 14:51:05.121195
2382 14:51:05.124570 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2383 14:51:05.127889 [DutyScan_Calibration_Flow] ====Done====
2384 14:51:05.127962
2385 14:51:05.131447 [DutyScan_Calibration_Flow] k_type=3
2386 14:51:05.148059
2387 14:51:05.148165 ==DQM 0 ==
2388 14:51:05.151857 Final DQM duty delay cell = 0
2389 14:51:05.154982 [0] MAX Duty = 5156%(X100), DQS PI = 30
2390 14:51:05.158088 [0] MIN Duty = 4906%(X100), DQS PI = 52
2391 14:51:05.161622 [0] AVG Duty = 5031%(X100)
2392 14:51:05.161702
2393 14:51:05.161765 ==DQM 1 ==
2394 14:51:05.164742 Final DQM duty delay cell = 0
2395 14:51:05.168288 [0] MAX Duty = 5093%(X100), DQS PI = 0
2396 14:51:05.171477 [0] MIN Duty = 5031%(X100), DQS PI = 14
2397 14:51:05.174679 [0] AVG Duty = 5062%(X100)
2398 14:51:05.174759
2399 14:51:05.178539 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2400 14:51:05.178619
2401 14:51:05.181679 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2402 14:51:05.184985 [DutyScan_Calibration_Flow] ====Done====
2403 14:51:05.185071
2404 14:51:05.188318 [DutyScan_Calibration_Flow] k_type=2
2405 14:51:05.204493
2406 14:51:05.204574 ==DQ 0 ==
2407 14:51:05.207958 Final DQ duty delay cell = 0
2408 14:51:05.210989 [0] MAX Duty = 5031%(X100), DQS PI = 24
2409 14:51:05.214511 [0] MIN Duty = 4875%(X100), DQS PI = 0
2410 14:51:05.214620 [0] AVG Duty = 4953%(X100)
2411 14:51:05.214713
2412 14:51:05.218206 ==DQ 1 ==
2413 14:51:05.221472 Final DQ duty delay cell = 0
2414 14:51:05.224607 [0] MAX Duty = 5093%(X100), DQS PI = 24
2415 14:51:05.227620 [0] MIN Duty = 4907%(X100), DQS PI = 36
2416 14:51:05.227696 [0] AVG Duty = 5000%(X100)
2417 14:51:05.227758
2418 14:51:05.231182 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2419 14:51:05.231255
2420 14:51:05.234979 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2421 14:51:05.241279 [DutyScan_Calibration_Flow] ====Done====
2422 14:51:05.241353 ==
2423 14:51:05.244250 Dram Type= 6, Freq= 0, CH_1, rank 0
2424 14:51:05.247836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2425 14:51:05.247912 ==
2426 14:51:05.251029 [Duty_Offset_Calibration]
2427 14:51:05.251130 B0:1 B1:0 CA:0
2428 14:51:05.251219
2429 14:51:05.254282 [DutyScan_Calibration_Flow] k_type=0
2430 14:51:05.263403
2431 14:51:05.263475 ==CLK 0==
2432 14:51:05.267424 Final CLK duty delay cell = -4
2433 14:51:05.270333 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2434 14:51:05.274160 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2435 14:51:05.277168 [-4] AVG Duty = 4969%(X100)
2436 14:51:05.277274
2437 14:51:05.280030 CH1 CLK Duty spec in!! Max-Min= 124%
2438 14:51:05.283796 [DutyScan_Calibration_Flow] ====Done====
2439 14:51:05.283871
2440 14:51:05.286984 [DutyScan_Calibration_Flow] k_type=1
2441 14:51:05.303292
2442 14:51:05.303400 ==DQS 0 ==
2443 14:51:05.306458 Final DQS duty delay cell = 0
2444 14:51:05.310419 [0] MAX Duty = 5062%(X100), DQS PI = 12
2445 14:51:05.313374 [0] MIN Duty = 4844%(X100), DQS PI = 0
2446 14:51:05.313456 [0] AVG Duty = 4953%(X100)
2447 14:51:05.317060
2448 14:51:05.317140 ==DQS 1 ==
2449 14:51:05.320270 Final DQS duty delay cell = 0
2450 14:51:05.323440 [0] MAX Duty = 5187%(X100), DQS PI = 18
2451 14:51:05.327137 [0] MIN Duty = 4969%(X100), DQS PI = 8
2452 14:51:05.327212 [0] AVG Duty = 5078%(X100)
2453 14:51:05.327274
2454 14:51:05.333690 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2455 14:51:05.333767
2456 14:51:05.336890 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2457 14:51:05.340050 [DutyScan_Calibration_Flow] ====Done====
2458 14:51:05.340121
2459 14:51:05.343441 [DutyScan_Calibration_Flow] k_type=3
2460 14:51:05.360065
2461 14:51:05.360145 ==DQM 0 ==
2462 14:51:05.363535 Final DQM duty delay cell = 0
2463 14:51:05.366653 [0] MAX Duty = 5156%(X100), DQS PI = 8
2464 14:51:05.370032 [0] MIN Duty = 5000%(X100), DQS PI = 48
2465 14:51:05.370114 [0] AVG Duty = 5078%(X100)
2466 14:51:05.370177
2467 14:51:05.373726 ==DQM 1 ==
2468 14:51:05.376859 Final DQM duty delay cell = 0
2469 14:51:05.380103 [0] MAX Duty = 5031%(X100), DQS PI = 16
2470 14:51:05.383731 [0] MIN Duty = 4907%(X100), DQS PI = 36
2471 14:51:05.383812 [0] AVG Duty = 4969%(X100)
2472 14:51:05.383876
2473 14:51:05.390228 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2474 14:51:05.390334
2475 14:51:05.393855 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2476 14:51:05.396697 [DutyScan_Calibration_Flow] ====Done====
2477 14:51:05.396802
2478 14:51:05.400040 [DutyScan_Calibration_Flow] k_type=2
2479 14:51:05.415668
2480 14:51:05.415775 ==DQ 0 ==
2481 14:51:05.419449 Final DQ duty delay cell = -4
2482 14:51:05.422334 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2483 14:51:05.426110 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2484 14:51:05.429363 [-4] AVG Duty = 5000%(X100)
2485 14:51:05.429444
2486 14:51:05.429507 ==DQ 1 ==
2487 14:51:05.432756 Final DQ duty delay cell = 0
2488 14:51:05.436225 [0] MAX Duty = 5125%(X100), DQS PI = 20
2489 14:51:05.439031 [0] MIN Duty = 4969%(X100), DQS PI = 12
2490 14:51:05.439106 [0] AVG Duty = 5047%(X100)
2491 14:51:05.439172
2492 14:51:05.446219 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2493 14:51:05.446290
2494 14:51:05.449693 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2495 14:51:05.452825 [DutyScan_Calibration_Flow] ====Done====
2496 14:51:05.456186 nWR fixed to 30
2497 14:51:05.456268 [ModeRegInit_LP4] CH0 RK0
2498 14:51:05.459460 [ModeRegInit_LP4] CH0 RK1
2499 14:51:05.462345 [ModeRegInit_LP4] CH1 RK0
2500 14:51:05.466034 [ModeRegInit_LP4] CH1 RK1
2501 14:51:05.466168 match AC timing 7
2502 14:51:05.469350 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2503 14:51:05.476250 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2504 14:51:05.479252 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2505 14:51:05.482826 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2506 14:51:05.489440 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2507 14:51:05.489515 ==
2508 14:51:05.493035 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 14:51:05.496203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 14:51:05.496288 ==
2511 14:51:05.502282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2512 14:51:05.509073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2513 14:51:05.515937 [CA 0] Center 39 (8~70) winsize 63
2514 14:51:05.519845 [CA 1] Center 39 (8~70) winsize 63
2515 14:51:05.522992 [CA 2] Center 35 (5~66) winsize 62
2516 14:51:05.526057 [CA 3] Center 34 (4~65) winsize 62
2517 14:51:05.529731 [CA 4] Center 33 (3~64) winsize 62
2518 14:51:05.533120 [CA 5] Center 32 (3~62) winsize 60
2519 14:51:05.533226
2520 14:51:05.536432 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2521 14:51:05.536513
2522 14:51:05.539831 [CATrainingPosCal] consider 1 rank data
2523 14:51:05.543396 u2DelayCellTimex100 = 270/100 ps
2524 14:51:05.546318 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2525 14:51:05.549734 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2526 14:51:05.556220 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2527 14:51:05.559801 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2528 14:51:05.562925 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2529 14:51:05.566057 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2530 14:51:05.566137
2531 14:51:05.569057 CA PerBit enable=1, Macro0, CA PI delay=32
2532 14:51:05.569138
2533 14:51:05.572741 [CBTSetCACLKResult] CA Dly = 32
2534 14:51:05.572822 CS Dly: 6 (0~37)
2535 14:51:05.576293 ==
2536 14:51:05.576383 Dram Type= 6, Freq= 0, CH_0, rank 1
2537 14:51:05.582537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 14:51:05.582618 ==
2539 14:51:05.586252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 14:51:05.592643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2541 14:51:05.601865 [CA 0] Center 38 (8~69) winsize 62
2542 14:51:05.605405 [CA 1] Center 38 (8~69) winsize 62
2543 14:51:05.608295 [CA 2] Center 35 (5~66) winsize 62
2544 14:51:05.612191 [CA 3] Center 34 (4~65) winsize 62
2545 14:51:05.615575 [CA 4] Center 33 (3~64) winsize 62
2546 14:51:05.618777 [CA 5] Center 32 (2~62) winsize 61
2547 14:51:05.618940
2548 14:51:05.621924 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2549 14:51:05.622101
2550 14:51:05.625082 [CATrainingPosCal] consider 2 rank data
2551 14:51:05.628890 u2DelayCellTimex100 = 270/100 ps
2552 14:51:05.632337 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2553 14:51:05.635051 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2554 14:51:05.642066 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2555 14:51:05.645418 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2556 14:51:05.649120 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2557 14:51:05.652304 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2558 14:51:05.652860
2559 14:51:05.655458 CA PerBit enable=1, Macro0, CA PI delay=32
2560 14:51:05.655973
2561 14:51:05.659117 [CBTSetCACLKResult] CA Dly = 32
2562 14:51:05.659637 CS Dly: 6 (0~38)
2563 14:51:05.659969
2564 14:51:05.662278 ----->DramcWriteLeveling(PI) begin...
2565 14:51:05.665992 ==
2566 14:51:05.669365 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 14:51:05.672366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 14:51:05.672795 ==
2569 14:51:05.675454 Write leveling (Byte 0): 32 => 32
2570 14:51:05.679394 Write leveling (Byte 1): 27 => 27
2571 14:51:05.682924 DramcWriteLeveling(PI) end<-----
2572 14:51:05.683479
2573 14:51:05.683839 ==
2574 14:51:05.685848 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 14:51:05.689111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 14:51:05.689574 ==
2577 14:51:05.692951 [Gating] SW mode calibration
2578 14:51:05.699279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2579 14:51:05.702422 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2580 14:51:05.709042 0 15 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
2581 14:51:05.712299 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2582 14:51:05.715760 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 14:51:05.722301 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 14:51:05.725618 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 14:51:05.729260 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 14:51:05.735697 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2587 14:51:05.739338 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2588 14:51:05.742691 1 0 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
2589 14:51:05.748920 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 14:51:05.752922 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 14:51:05.755792 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 14:51:05.762311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 14:51:05.765820 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 14:51:05.768915 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2595 14:51:05.775528 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2596 14:51:05.778839 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2597 14:51:05.782640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 14:51:05.785613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 14:51:05.792897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 14:51:05.795551 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 14:51:05.799159 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 14:51:05.805688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 14:51:05.809420 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2604 14:51:05.812730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2605 14:51:05.819471 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 14:51:05.822292 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 14:51:05.825927 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 14:51:05.832228 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 14:51:05.835482 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 14:51:05.838821 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 14:51:05.845461 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 14:51:05.849024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 14:51:05.851879 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 14:51:05.858642 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 14:51:05.861911 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 14:51:05.865440 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 14:51:05.868892 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 14:51:05.875702 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 14:51:05.878585 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 14:51:05.882294 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 14:51:05.885364 Total UI for P1: 0, mck2ui 16
2622 14:51:05.888918 best dqsien dly found for B0: ( 1, 3, 28)
2623 14:51:05.892053 Total UI for P1: 0, mck2ui 16
2624 14:51:05.895366 best dqsien dly found for B1: ( 1, 3, 30)
2625 14:51:05.898884 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2626 14:51:05.901884 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2627 14:51:05.905744
2628 14:51:05.908735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2629 14:51:05.911962 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2630 14:51:05.915289 [Gating] SW calibration Done
2631 14:51:05.915397 ==
2632 14:51:05.919044 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 14:51:05.922063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 14:51:05.922167 ==
2635 14:51:05.922272 RX Vref Scan: 0
2636 14:51:05.922363
2637 14:51:05.925924 RX Vref 0 -> 0, step: 1
2638 14:51:05.926037
2639 14:51:05.928997 RX Delay -40 -> 252, step: 8
2640 14:51:05.932068 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2641 14:51:05.935726 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2642 14:51:05.941829 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2643 14:51:05.945534 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2644 14:51:05.949123 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2645 14:51:05.952082 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2646 14:51:05.955647 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2647 14:51:05.959002 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2648 14:51:05.965625 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2649 14:51:05.969263 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2650 14:51:05.972588 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2651 14:51:05.975745 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2652 14:51:05.978940 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2653 14:51:05.985623 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2654 14:51:05.989094 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2655 14:51:05.992261 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2656 14:51:05.992412 ==
2657 14:51:05.995779 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 14:51:05.999021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 14:51:06.001781 ==
2660 14:51:06.001903 DQS Delay:
2661 14:51:06.001999 DQS0 = 0, DQS1 = 0
2662 14:51:06.005854 DQM Delay:
2663 14:51:06.005975 DQM0 = 121, DQM1 = 113
2664 14:51:06.008925 DQ Delay:
2665 14:51:06.012774 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2666 14:51:06.015609 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2667 14:51:06.019150 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2668 14:51:06.022323 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2669 14:51:06.022741
2670 14:51:06.023064
2671 14:51:06.023367 ==
2672 14:51:06.026276 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 14:51:06.029160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 14:51:06.029578 ==
2675 14:51:06.029907
2676 14:51:06.030209
2677 14:51:06.032566 TX Vref Scan disable
2678 14:51:06.036276 == TX Byte 0 ==
2679 14:51:06.039380 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2680 14:51:06.042409 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2681 14:51:06.045996 == TX Byte 1 ==
2682 14:51:06.049309 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2683 14:51:06.052787 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2684 14:51:06.053206 ==
2685 14:51:06.056047 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 14:51:06.059199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 14:51:06.062741 ==
2688 14:51:06.072855 TX Vref=22, minBit 0, minWin=25, winSum=405
2689 14:51:06.076228 TX Vref=24, minBit 0, minWin=25, winSum=411
2690 14:51:06.079561 TX Vref=26, minBit 1, minWin=25, winSum=415
2691 14:51:06.082863 TX Vref=28, minBit 13, minWin=25, winSum=424
2692 14:51:06.086087 TX Vref=30, minBit 13, minWin=25, winSum=422
2693 14:51:06.092996 TX Vref=32, minBit 13, minWin=25, winSum=419
2694 14:51:06.096191 [TxChooseVref] Worse bit 13, Min win 25, Win sum 424, Final Vref 28
2695 14:51:06.096653
2696 14:51:06.099654 Final TX Range 1 Vref 28
2697 14:51:06.100075
2698 14:51:06.100457 ==
2699 14:51:06.103057 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 14:51:06.105951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 14:51:06.109537 ==
2702 14:51:06.109956
2703 14:51:06.110283
2704 14:51:06.110589 TX Vref Scan disable
2705 14:51:06.112990 == TX Byte 0 ==
2706 14:51:06.116382 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2707 14:51:06.119502 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2708 14:51:06.122816 == TX Byte 1 ==
2709 14:51:06.126032 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2710 14:51:06.129713 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2711 14:51:06.133475
2712 14:51:06.133888 [DATLAT]
2713 14:51:06.134214 Freq=1200, CH0 RK0
2714 14:51:06.134517
2715 14:51:06.136326 DATLAT Default: 0xd
2716 14:51:06.136768 0, 0xFFFF, sum = 0
2717 14:51:06.139409 1, 0xFFFF, sum = 0
2718 14:51:06.139826 2, 0xFFFF, sum = 0
2719 14:51:06.143316 3, 0xFFFF, sum = 0
2720 14:51:06.143731 4, 0xFFFF, sum = 0
2721 14:51:06.146195 5, 0xFFFF, sum = 0
2722 14:51:06.149958 6, 0xFFFF, sum = 0
2723 14:51:06.150529 7, 0xFFFF, sum = 0
2724 14:51:06.153057 8, 0xFFFF, sum = 0
2725 14:51:06.153478 9, 0xFFFF, sum = 0
2726 14:51:06.157034 10, 0xFFFF, sum = 0
2727 14:51:06.157468 11, 0xFFFF, sum = 0
2728 14:51:06.159656 12, 0x0, sum = 1
2729 14:51:06.160101 13, 0x0, sum = 2
2730 14:51:06.162904 14, 0x0, sum = 3
2731 14:51:06.163337 15, 0x0, sum = 4
2732 14:51:06.163794 best_step = 13
2733 14:51:06.164367
2734 14:51:06.166624 ==
2735 14:51:06.169448 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 14:51:06.173115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 14:51:06.173546 ==
2738 14:51:06.173974 RX Vref Scan: 1
2739 14:51:06.174382
2740 14:51:06.176695 Set Vref Range= 32 -> 127
2741 14:51:06.177120
2742 14:51:06.179617 RX Vref 32 -> 127, step: 1
2743 14:51:06.180252
2744 14:51:06.183474 RX Delay -13 -> 252, step: 4
2745 14:51:06.183946
2746 14:51:06.186517 Set Vref, RX VrefLevel [Byte0]: 32
2747 14:51:06.189926 [Byte1]: 32
2748 14:51:06.190383
2749 14:51:06.193324 Set Vref, RX VrefLevel [Byte0]: 33
2750 14:51:06.196198 [Byte1]: 33
2751 14:51:06.196742
2752 14:51:06.200078 Set Vref, RX VrefLevel [Byte0]: 34
2753 14:51:06.203113 [Byte1]: 34
2754 14:51:06.207363
2755 14:51:06.207657 Set Vref, RX VrefLevel [Byte0]: 35
2756 14:51:06.210644 [Byte1]: 35
2757 14:51:06.214979
2758 14:51:06.215197 Set Vref, RX VrefLevel [Byte0]: 36
2759 14:51:06.218062 [Byte1]: 36
2760 14:51:06.223170
2761 14:51:06.223324 Set Vref, RX VrefLevel [Byte0]: 37
2762 14:51:06.226280 [Byte1]: 37
2763 14:51:06.230418
2764 14:51:06.230549 Set Vref, RX VrefLevel [Byte0]: 38
2765 14:51:06.233782 [Byte1]: 38
2766 14:51:06.238105
2767 14:51:06.238221 Set Vref, RX VrefLevel [Byte0]: 39
2768 14:51:06.241681 [Byte1]: 39
2769 14:51:06.246367
2770 14:51:06.246474 Set Vref, RX VrefLevel [Byte0]: 40
2771 14:51:06.249610 [Byte1]: 40
2772 14:51:06.254266
2773 14:51:06.254447 Set Vref, RX VrefLevel [Byte0]: 41
2774 14:51:06.257754 [Byte1]: 41
2775 14:51:06.262059
2776 14:51:06.262163 Set Vref, RX VrefLevel [Byte0]: 42
2777 14:51:06.265409 [Byte1]: 42
2778 14:51:06.270273
2779 14:51:06.270443 Set Vref, RX VrefLevel [Byte0]: 43
2780 14:51:06.273607 [Byte1]: 43
2781 14:51:06.278203
2782 14:51:06.278380 Set Vref, RX VrefLevel [Byte0]: 44
2783 14:51:06.281147 [Byte1]: 44
2784 14:51:06.286305
2785 14:51:06.286506 Set Vref, RX VrefLevel [Byte0]: 45
2786 14:51:06.289216 [Byte1]: 45
2787 14:51:06.293544
2788 14:51:06.293757 Set Vref, RX VrefLevel [Byte0]: 46
2789 14:51:06.297175 [Byte1]: 46
2790 14:51:06.302286
2791 14:51:06.302539 Set Vref, RX VrefLevel [Byte0]: 47
2792 14:51:06.305313 [Byte1]: 47
2793 14:51:06.309549
2794 14:51:06.309781 Set Vref, RX VrefLevel [Byte0]: 48
2795 14:51:06.313204 [Byte1]: 48
2796 14:51:06.317850
2797 14:51:06.318222 Set Vref, RX VrefLevel [Byte0]: 49
2798 14:51:06.324254 [Byte1]: 49
2799 14:51:06.324743
2800 14:51:06.327954 Set Vref, RX VrefLevel [Byte0]: 50
2801 14:51:06.331067 [Byte1]: 50
2802 14:51:06.331635
2803 14:51:06.334105 Set Vref, RX VrefLevel [Byte0]: 51
2804 14:51:06.337816 [Byte1]: 51
2805 14:51:06.341287
2806 14:51:06.341846 Set Vref, RX VrefLevel [Byte0]: 52
2807 14:51:06.344951 [Byte1]: 52
2808 14:51:06.349278
2809 14:51:06.349765 Set Vref, RX VrefLevel [Byte0]: 53
2810 14:51:06.352453 [Byte1]: 53
2811 14:51:06.357212
2812 14:51:06.357776 Set Vref, RX VrefLevel [Byte0]: 54
2813 14:51:06.360819 [Byte1]: 54
2814 14:51:06.364980
2815 14:51:06.365441 Set Vref, RX VrefLevel [Byte0]: 55
2816 14:51:06.368220 [Byte1]: 55
2817 14:51:06.373021
2818 14:51:06.373616 Set Vref, RX VrefLevel [Byte0]: 56
2819 14:51:06.376020 [Byte1]: 56
2820 14:51:06.381141
2821 14:51:06.381712 Set Vref, RX VrefLevel [Byte0]: 57
2822 14:51:06.384011 [Byte1]: 57
2823 14:51:06.389059
2824 14:51:06.389652 Set Vref, RX VrefLevel [Byte0]: 58
2825 14:51:06.392281 [Byte1]: 58
2826 14:51:06.396527
2827 14:51:06.396992 Set Vref, RX VrefLevel [Byte0]: 59
2828 14:51:06.400333 [Byte1]: 59
2829 14:51:06.404422
2830 14:51:06.404885 Set Vref, RX VrefLevel [Byte0]: 60
2831 14:51:06.407403 [Byte1]: 60
2832 14:51:06.412690
2833 14:51:06.413256 Set Vref, RX VrefLevel [Byte0]: 61
2834 14:51:06.415498 [Byte1]: 61
2835 14:51:06.420942
2836 14:51:06.421506 Set Vref, RX VrefLevel [Byte0]: 62
2837 14:51:06.424075 [Byte1]: 62
2838 14:51:06.428127
2839 14:51:06.428631 Set Vref, RX VrefLevel [Byte0]: 63
2840 14:51:06.431839 [Byte1]: 63
2841 14:51:06.436203
2842 14:51:06.436826 Set Vref, RX VrefLevel [Byte0]: 64
2843 14:51:06.439517 [Byte1]: 64
2844 14:51:06.444094
2845 14:51:06.444719 Set Vref, RX VrefLevel [Byte0]: 65
2846 14:51:06.447395 [Byte1]: 65
2847 14:51:06.452383
2848 14:51:06.452956 Set Vref, RX VrefLevel [Byte0]: 66
2849 14:51:06.454928 [Byte1]: 66
2850 14:51:06.459801
2851 14:51:06.460413 Set Vref, RX VrefLevel [Byte0]: 67
2852 14:51:06.463299 [Byte1]: 67
2853 14:51:06.467725
2854 14:51:06.468286 Set Vref, RX VrefLevel [Byte0]: 68
2855 14:51:06.471727 [Byte1]: 68
2856 14:51:06.475754
2857 14:51:06.476222 Set Vref, RX VrefLevel [Byte0]: 69
2858 14:51:06.478909 [Byte1]: 69
2859 14:51:06.483422
2860 14:51:06.483984 Final RX Vref Byte 0 = 56 to rank0
2861 14:51:06.486896 Final RX Vref Byte 1 = 47 to rank0
2862 14:51:06.490428 Final RX Vref Byte 0 = 56 to rank1
2863 14:51:06.493390 Final RX Vref Byte 1 = 47 to rank1==
2864 14:51:06.496901 Dram Type= 6, Freq= 0, CH_0, rank 0
2865 14:51:06.503666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 14:51:06.504247 ==
2867 14:51:06.504682 DQS Delay:
2868 14:51:06.505027 DQS0 = 0, DQS1 = 0
2869 14:51:06.506759 DQM Delay:
2870 14:51:06.507224 DQM0 = 120, DQM1 = 110
2871 14:51:06.510495 DQ Delay:
2872 14:51:06.513792 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2873 14:51:06.516896 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2874 14:51:06.519858 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
2875 14:51:06.523321 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2876 14:51:06.523938
2877 14:51:06.524415
2878 14:51:06.530261 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2879 14:51:06.534028 CH0 RK0: MR19=404, MR18=160F
2880 14:51:06.540068 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2881 14:51:06.540701
2882 14:51:06.543847 ----->DramcWriteLeveling(PI) begin...
2883 14:51:06.544473 ==
2884 14:51:06.546710 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 14:51:06.550604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 14:51:06.553231 ==
2887 14:51:06.553694 Write leveling (Byte 0): 34 => 34
2888 14:51:06.557265 Write leveling (Byte 1): 28 => 28
2889 14:51:06.560752 DramcWriteLeveling(PI) end<-----
2890 14:51:06.561385
2891 14:51:06.561761 ==
2892 14:51:06.563354 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 14:51:06.570280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 14:51:06.570838 ==
2895 14:51:06.571207 [Gating] SW mode calibration
2896 14:51:06.580453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2897 14:51:06.583825 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2898 14:51:06.587449 0 15 0 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
2899 14:51:06.593601 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 14:51:06.596940 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 14:51:06.600207 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 14:51:06.607388 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 14:51:06.610259 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 14:51:06.614234 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2905 14:51:06.620561 0 15 28 | B1->B0 | 3232 3131 | 1 1 | (1 0) (0 0)
2906 14:51:06.623886 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 14:51:06.627257 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 14:51:06.634509 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 14:51:06.637766 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 14:51:06.640515 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 14:51:06.643574 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 14:51:06.650685 1 0 24 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
2913 14:51:06.654297 1 0 28 | B1->B0 | 3d3d 3b3a | 0 1 | (1 1) (0 0)
2914 14:51:06.657217 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2915 14:51:06.663952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 14:51:06.667828 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 14:51:06.670682 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 14:51:06.677148 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 14:51:06.681317 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 14:51:06.683800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 14:51:06.690843 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2922 14:51:06.693934 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2923 14:51:06.697485 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 14:51:06.704247 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 14:51:06.707182 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 14:51:06.710791 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 14:51:06.717697 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 14:51:06.720769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 14:51:06.724736 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 14:51:06.727665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 14:51:06.734428 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 14:51:06.737179 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 14:51:06.741116 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 14:51:06.747460 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 14:51:06.750917 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 14:51:06.754189 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 14:51:06.760758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2938 14:51:06.764082 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2939 14:51:06.768132 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 14:51:06.771012 Total UI for P1: 0, mck2ui 16
2941 14:51:06.774166 best dqsien dly found for B0: ( 1, 3, 30)
2942 14:51:06.778003 Total UI for P1: 0, mck2ui 16
2943 14:51:06.781288 best dqsien dly found for B1: ( 1, 3, 30)
2944 14:51:06.784645 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2945 14:51:06.787828 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2946 14:51:06.788438
2947 14:51:06.791304 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2948 14:51:06.797841 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2949 14:51:06.798609 [Gating] SW calibration Done
2950 14:51:06.799003 ==
2951 14:51:06.800961 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 14:51:06.807864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 14:51:06.808331 ==
2954 14:51:06.808906 RX Vref Scan: 0
2955 14:51:06.809283
2956 14:51:06.811506 RX Vref 0 -> 0, step: 1
2957 14:51:06.811967
2958 14:51:06.814529 RX Delay -40 -> 252, step: 8
2959 14:51:06.818057 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2960 14:51:06.821131 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2961 14:51:06.825303 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2962 14:51:06.828158 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2963 14:51:06.835002 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2964 14:51:06.837752 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2965 14:51:06.841153 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2966 14:51:06.845263 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2967 14:51:06.848098 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2968 14:51:06.854909 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2969 14:51:06.857768 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2970 14:51:06.861727 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2971 14:51:06.864958 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2972 14:51:06.868390 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2973 14:51:06.874706 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2974 14:51:06.877848 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2975 14:51:06.878314 ==
2976 14:51:06.881401 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 14:51:06.885065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 14:51:06.885632 ==
2979 14:51:06.885999 DQS Delay:
2980 14:51:06.888519 DQS0 = 0, DQS1 = 0
2981 14:51:06.889085 DQM Delay:
2982 14:51:06.891918 DQM0 = 122, DQM1 = 112
2983 14:51:06.892520 DQ Delay:
2984 14:51:06.895152 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2985 14:51:06.898487 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2986 14:51:06.901491 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2987 14:51:06.904604 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2988 14:51:06.908700
2989 14:51:06.909234
2990 14:51:06.909682 ==
2991 14:51:06.911549 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 14:51:06.915044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 14:51:06.915619 ==
2994 14:51:06.915990
2995 14:51:06.916324
2996 14:51:06.917890 TX Vref Scan disable
2997 14:51:06.918355 == TX Byte 0 ==
2998 14:51:06.924655 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2999 14:51:06.928123 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3000 14:51:06.928636 == TX Byte 1 ==
3001 14:51:06.934868 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3002 14:51:06.938254 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3003 14:51:06.938676 ==
3004 14:51:06.941468 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 14:51:06.945163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 14:51:06.945585 ==
3007 14:51:06.957545 TX Vref=22, minBit 2, minWin=25, winSum=414
3008 14:51:06.961554 TX Vref=24, minBit 3, minWin=25, winSum=414
3009 14:51:06.964430 TX Vref=26, minBit 13, minWin=25, winSum=421
3010 14:51:06.967943 TX Vref=28, minBit 2, minWin=26, winSum=422
3011 14:51:06.971571 TX Vref=30, minBit 5, minWin=25, winSum=424
3012 14:51:06.977897 TX Vref=32, minBit 12, minWin=25, winSum=422
3013 14:51:06.981257 [TxChooseVref] Worse bit 2, Min win 26, Win sum 422, Final Vref 28
3014 14:51:06.981785
3015 14:51:06.984603 Final TX Range 1 Vref 28
3016 14:51:06.985023
3017 14:51:06.985352 ==
3018 14:51:06.987723 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 14:51:06.991382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 14:51:06.991907 ==
3021 14:51:06.994138
3022 14:51:06.994558
3023 14:51:06.994886 TX Vref Scan disable
3024 14:51:06.997555 == TX Byte 0 ==
3025 14:51:07.000896 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3026 14:51:07.004817 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3027 14:51:07.007761 == TX Byte 1 ==
3028 14:51:07.010981 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3029 14:51:07.014741 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3030 14:51:07.017765
3031 14:51:07.018288 [DATLAT]
3032 14:51:07.018624 Freq=1200, CH0 RK1
3033 14:51:07.018940
3034 14:51:07.020706 DATLAT Default: 0xd
3035 14:51:07.021130 0, 0xFFFF, sum = 0
3036 14:51:07.024569 1, 0xFFFF, sum = 0
3037 14:51:07.024995 2, 0xFFFF, sum = 0
3038 14:51:07.027386 3, 0xFFFF, sum = 0
3039 14:51:07.027814 4, 0xFFFF, sum = 0
3040 14:51:07.031627 5, 0xFFFF, sum = 0
3041 14:51:07.034112 6, 0xFFFF, sum = 0
3042 14:51:07.034545 7, 0xFFFF, sum = 0
3043 14:51:07.037902 8, 0xFFFF, sum = 0
3044 14:51:07.038380 9, 0xFFFF, sum = 0
3045 14:51:07.041155 10, 0xFFFF, sum = 0
3046 14:51:07.041580 11, 0xFFFF, sum = 0
3047 14:51:07.044404 12, 0x0, sum = 1
3048 14:51:07.044832 13, 0x0, sum = 2
3049 14:51:07.048329 14, 0x0, sum = 3
3050 14:51:07.048785 15, 0x0, sum = 4
3051 14:51:07.049122 best_step = 13
3052 14:51:07.049441
3053 14:51:07.051126 ==
3054 14:51:07.054943 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 14:51:07.057920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 14:51:07.058598 ==
3057 14:51:07.059043 RX Vref Scan: 0
3058 14:51:07.059366
3059 14:51:07.061996 RX Vref 0 -> 0, step: 1
3060 14:51:07.062530
3061 14:51:07.064395 RX Delay -13 -> 252, step: 4
3062 14:51:07.068307 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3063 14:51:07.070948 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3064 14:51:07.077702 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3065 14:51:07.081348 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3066 14:51:07.084441 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3067 14:51:07.088002 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3068 14:51:07.091553 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3069 14:51:07.097948 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3070 14:51:07.101270 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3071 14:51:07.104803 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3072 14:51:07.107756 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3073 14:51:07.111373 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3074 14:51:07.118089 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3075 14:51:07.121070 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3076 14:51:07.124475 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3077 14:51:07.127651 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3078 14:51:07.128147 ==
3079 14:51:07.131212 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 14:51:07.138232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 14:51:07.138648 ==
3082 14:51:07.138975 DQS Delay:
3083 14:51:07.139323 DQS0 = 0, DQS1 = 0
3084 14:51:07.141112 DQM Delay:
3085 14:51:07.141527 DQM0 = 121, DQM1 = 109
3086 14:51:07.144183 DQ Delay:
3087 14:51:07.147801 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3088 14:51:07.151240 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3089 14:51:07.154207 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3090 14:51:07.158328 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3091 14:51:07.158848
3092 14:51:07.159178
3093 14:51:07.168256 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3094 14:51:07.168829 CH0 RK1: MR19=403, MR18=10F2
3095 14:51:07.174988 CH0_RK1: MR19=0x403, MR18=0x10F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3096 14:51:07.177714 [RxdqsGatingPostProcess] freq 1200
3097 14:51:07.184424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3098 14:51:07.187664 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 14:51:07.191417 best DQS1 dly(2T, 0.5T) = (0, 11)
3100 14:51:07.191930 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 14:51:07.194351 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3102 14:51:07.197956 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 14:51:07.201605 best DQS1 dly(2T, 0.5T) = (0, 11)
3104 14:51:07.204804 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 14:51:07.207979 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3106 14:51:07.211071 Pre-setting of DQS Precalculation
3107 14:51:07.218087 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3108 14:51:07.218577 ==
3109 14:51:07.221141 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 14:51:07.224977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 14:51:07.225552 ==
3112 14:51:07.231617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3113 14:51:07.234507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3114 14:51:07.244853 [CA 0] Center 37 (7~68) winsize 62
3115 14:51:07.247636 [CA 1] Center 37 (7~68) winsize 62
3116 14:51:07.251650 [CA 2] Center 35 (5~65) winsize 61
3117 14:51:07.254828 [CA 3] Center 34 (4~64) winsize 61
3118 14:51:07.257867 [CA 4] Center 34 (4~64) winsize 61
3119 14:51:07.261438 [CA 5] Center 33 (3~63) winsize 61
3120 14:51:07.262001
3121 14:51:07.264328 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3122 14:51:07.264809
3123 14:51:07.267343 [CATrainingPosCal] consider 1 rank data
3124 14:51:07.271050 u2DelayCellTimex100 = 270/100 ps
3125 14:51:07.275078 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3126 14:51:07.277932 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3127 14:51:07.284289 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3128 14:51:07.288052 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3129 14:51:07.291112 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3130 14:51:07.294568 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3131 14:51:07.295140
3132 14:51:07.298209 CA PerBit enable=1, Macro0, CA PI delay=33
3133 14:51:07.298769
3134 14:51:07.301102 [CBTSetCACLKResult] CA Dly = 33
3135 14:51:07.301562 CS Dly: 7 (0~38)
3136 14:51:07.301921 ==
3137 14:51:07.304208 Dram Type= 6, Freq= 0, CH_1, rank 1
3138 14:51:07.311599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 14:51:07.312166 ==
3140 14:51:07.314467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3141 14:51:07.321054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3142 14:51:07.330178 [CA 0] Center 37 (7~68) winsize 62
3143 14:51:07.333254 [CA 1] Center 38 (8~68) winsize 61
3144 14:51:07.336561 [CA 2] Center 35 (5~66) winsize 62
3145 14:51:07.339933 [CA 3] Center 34 (4~65) winsize 62
3146 14:51:07.343136 [CA 4] Center 34 (4~65) winsize 62
3147 14:51:07.346267 [CA 5] Center 34 (4~64) winsize 61
3148 14:51:07.346720
3149 14:51:07.349866 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3150 14:51:07.350460
3151 14:51:07.358155 [CATrainingPosCal] consider 2 rank data
3152 14:51:07.358623 u2DelayCellTimex100 = 270/100 ps
3153 14:51:07.360015 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 14:51:07.363041 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3155 14:51:07.369767 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3156 14:51:07.372641 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 14:51:07.376757 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 14:51:07.379785 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3159 14:51:07.379941
3160 14:51:07.383214 CA PerBit enable=1, Macro0, CA PI delay=33
3161 14:51:07.383348
3162 14:51:07.386389 [CBTSetCACLKResult] CA Dly = 33
3163 14:51:07.386535 CS Dly: 8 (0~40)
3164 14:51:07.386630
3165 14:51:07.389887 ----->DramcWriteLeveling(PI) begin...
3166 14:51:07.390047 ==
3167 14:51:07.392962 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 14:51:07.399635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 14:51:07.399744 ==
3170 14:51:07.403192 Write leveling (Byte 0): 25 => 25
3171 14:51:07.406417 Write leveling (Byte 1): 28 => 28
3172 14:51:07.406539 DramcWriteLeveling(PI) end<-----
3173 14:51:07.409432
3174 14:51:07.409513 ==
3175 14:51:07.413149 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 14:51:07.416211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 14:51:07.416317 ==
3178 14:51:07.419588 [Gating] SW mode calibration
3179 14:51:07.426286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3180 14:51:07.429398 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3181 14:51:07.436466 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 14:51:07.439832 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 14:51:07.442771 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 14:51:07.449333 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 14:51:07.453183 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 14:51:07.456305 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 14:51:07.463059 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
3188 14:51:07.466001 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3189 14:51:07.469441 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 14:51:07.476263 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 14:51:07.480168 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 14:51:07.483414 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 14:51:07.486173 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 14:51:07.493102 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 14:51:07.496687 1 0 24 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
3196 14:51:07.499625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 14:51:07.506933 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 14:51:07.509704 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 14:51:07.512787 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 14:51:07.519736 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 14:51:07.523217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 14:51:07.526291 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 14:51:07.533262 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3204 14:51:07.537111 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3205 14:51:07.539378 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 14:51:07.546771 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 14:51:07.550227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 14:51:07.553543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 14:51:07.559750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 14:51:07.563120 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 14:51:07.566472 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 14:51:07.573234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 14:51:07.576856 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 14:51:07.579696 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 14:51:07.583159 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 14:51:07.589944 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 14:51:07.593291 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 14:51:07.596688 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 14:51:07.603916 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3220 14:51:07.606861 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3221 14:51:07.610473 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 14:51:07.613098 Total UI for P1: 0, mck2ui 16
3223 14:51:07.616613 best dqsien dly found for B0: ( 1, 3, 26)
3224 14:51:07.620052 Total UI for P1: 0, mck2ui 16
3225 14:51:07.623193 best dqsien dly found for B1: ( 1, 3, 28)
3226 14:51:07.626652 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3227 14:51:07.630291 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3228 14:51:07.630568
3229 14:51:07.636930 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3230 14:51:07.639812 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3231 14:51:07.640077 [Gating] SW calibration Done
3232 14:51:07.643854 ==
3233 14:51:07.646602 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 14:51:07.649669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 14:51:07.649869 ==
3236 14:51:07.650020 RX Vref Scan: 0
3237 14:51:07.650162
3238 14:51:07.653214 RX Vref 0 -> 0, step: 1
3239 14:51:07.653377
3240 14:51:07.656728 RX Delay -40 -> 252, step: 8
3241 14:51:07.659901 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3242 14:51:07.663512 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3243 14:51:07.670198 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3244 14:51:07.673463 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3245 14:51:07.676480 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3246 14:51:07.680051 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3247 14:51:07.683081 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3248 14:51:07.687040 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3249 14:51:07.693397 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3250 14:51:07.696529 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3251 14:51:07.699802 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3252 14:51:07.703582 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3253 14:51:07.706237 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3254 14:51:07.713347 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3255 14:51:07.717246 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3256 14:51:07.720079 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3257 14:51:07.720597 ==
3258 14:51:07.723828 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 14:51:07.727075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 14:51:07.729942 ==
3261 14:51:07.730406 DQS Delay:
3262 14:51:07.730770 DQS0 = 0, DQS1 = 0
3263 14:51:07.733958 DQM Delay:
3264 14:51:07.734486 DQM0 = 119, DQM1 = 116
3265 14:51:07.738134 DQ Delay:
3266 14:51:07.740512 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3267 14:51:07.743371 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3268 14:51:07.746750 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3269 14:51:07.750002 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3270 14:51:07.750422
3271 14:51:07.750803
3272 14:51:07.751118 ==
3273 14:51:07.753509 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 14:51:07.756949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 14:51:07.757418 ==
3276 14:51:07.757750
3277 14:51:07.758058
3278 14:51:07.759892 TX Vref Scan disable
3279 14:51:07.763544 == TX Byte 0 ==
3280 14:51:07.767368 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3281 14:51:07.770382 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3282 14:51:07.773780 == TX Byte 1 ==
3283 14:51:07.777000 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3284 14:51:07.780702 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3285 14:51:07.781218 ==
3286 14:51:07.783860 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 14:51:07.787609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 14:51:07.790690 ==
3289 14:51:07.800558 TX Vref=22, minBit 9, minWin=24, winSum=411
3290 14:51:07.803554 TX Vref=24, minBit 1, minWin=25, winSum=416
3291 14:51:07.806889 TX Vref=26, minBit 9, minWin=25, winSum=425
3292 14:51:07.810296 TX Vref=28, minBit 1, minWin=26, winSum=425
3293 14:51:07.813354 TX Vref=30, minBit 2, minWin=26, winSum=431
3294 14:51:07.816876 TX Vref=32, minBit 9, minWin=26, winSum=431
3295 14:51:07.823916 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3296 14:51:07.824522
3297 14:51:07.827019 Final TX Range 1 Vref 30
3298 14:51:07.827573
3299 14:51:07.827937 ==
3300 14:51:07.830337 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 14:51:07.834035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 14:51:07.834679 ==
3303 14:51:07.835057
3304 14:51:07.836809
3305 14:51:07.837269 TX Vref Scan disable
3306 14:51:07.840907 == TX Byte 0 ==
3307 14:51:07.843871 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3308 14:51:07.846686 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3309 14:51:07.851161 == TX Byte 1 ==
3310 14:51:07.853593 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 14:51:07.857084 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 14:51:07.857656
3313 14:51:07.860560 [DATLAT]
3314 14:51:07.861104 Freq=1200, CH1 RK0
3315 14:51:07.861478
3316 14:51:07.864103 DATLAT Default: 0xd
3317 14:51:07.864654 0, 0xFFFF, sum = 0
3318 14:51:07.867404 1, 0xFFFF, sum = 0
3319 14:51:07.867961 2, 0xFFFF, sum = 0
3320 14:51:07.869973 3, 0xFFFF, sum = 0
3321 14:51:07.870560 4, 0xFFFF, sum = 0
3322 14:51:07.873960 5, 0xFFFF, sum = 0
3323 14:51:07.874569 6, 0xFFFF, sum = 0
3324 14:51:07.877724 7, 0xFFFF, sum = 0
3325 14:51:07.878288 8, 0xFFFF, sum = 0
3326 14:51:07.880336 9, 0xFFFF, sum = 0
3327 14:51:07.883680 10, 0xFFFF, sum = 0
3328 14:51:07.884220 11, 0xFFFF, sum = 0
3329 14:51:07.886930 12, 0x0, sum = 1
3330 14:51:07.887399 13, 0x0, sum = 2
3331 14:51:07.887771 14, 0x0, sum = 3
3332 14:51:07.890719 15, 0x0, sum = 4
3333 14:51:07.891284 best_step = 13
3334 14:51:07.891770
3335 14:51:07.894259 ==
3336 14:51:07.894820 Dram Type= 6, Freq= 0, CH_1, rank 0
3337 14:51:07.900591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3338 14:51:07.901156 ==
3339 14:51:07.901528 RX Vref Scan: 1
3340 14:51:07.901874
3341 14:51:07.903692 Set Vref Range= 32 -> 127
3342 14:51:07.904247
3343 14:51:07.907375 RX Vref 32 -> 127, step: 1
3344 14:51:07.907927
3345 14:51:07.910185 RX Delay -5 -> 252, step: 4
3346 14:51:07.910769
3347 14:51:07.913894 Set Vref, RX VrefLevel [Byte0]: 32
3348 14:51:07.916758 [Byte1]: 32
3349 14:51:07.917226
3350 14:51:07.920294 Set Vref, RX VrefLevel [Byte0]: 33
3351 14:51:07.923670 [Byte1]: 33
3352 14:51:07.924136
3353 14:51:07.927172 Set Vref, RX VrefLevel [Byte0]: 34
3354 14:51:07.929968 [Byte1]: 34
3355 14:51:07.934292
3356 14:51:07.934929 Set Vref, RX VrefLevel [Byte0]: 35
3357 14:51:07.937340 [Byte1]: 35
3358 14:51:07.941895
3359 14:51:07.942456 Set Vref, RX VrefLevel [Byte0]: 36
3360 14:51:07.945435 [Byte1]: 36
3361 14:51:07.949642
3362 14:51:07.950123 Set Vref, RX VrefLevel [Byte0]: 37
3363 14:51:07.952685 [Byte1]: 37
3364 14:51:07.957709
3365 14:51:07.958124 Set Vref, RX VrefLevel [Byte0]: 38
3366 14:51:07.960730 [Byte1]: 38
3367 14:51:07.966194
3368 14:51:07.966489 Set Vref, RX VrefLevel [Byte0]: 39
3369 14:51:07.969110 [Byte1]: 39
3370 14:51:07.973453
3371 14:51:07.973748 Set Vref, RX VrefLevel [Byte0]: 40
3372 14:51:07.976671 [Byte1]: 40
3373 14:51:07.981422
3374 14:51:07.981818 Set Vref, RX VrefLevel [Byte0]: 41
3375 14:51:07.984059 [Byte1]: 41
3376 14:51:07.989122
3377 14:51:07.989536 Set Vref, RX VrefLevel [Byte0]: 42
3378 14:51:07.992658 [Byte1]: 42
3379 14:51:07.997266
3380 14:51:07.997679 Set Vref, RX VrefLevel [Byte0]: 43
3381 14:51:08.000488 [Byte1]: 43
3382 14:51:08.004660
3383 14:51:08.005075 Set Vref, RX VrefLevel [Byte0]: 44
3384 14:51:08.007835 [Byte1]: 44
3385 14:51:08.012696
3386 14:51:08.013111 Set Vref, RX VrefLevel [Byte0]: 45
3387 14:51:08.015742 [Byte1]: 45
3388 14:51:08.020299
3389 14:51:08.020893 Set Vref, RX VrefLevel [Byte0]: 46
3390 14:51:08.023530 [Byte1]: 46
3391 14:51:08.028508
3392 14:51:08.029010 Set Vref, RX VrefLevel [Byte0]: 47
3393 14:51:08.031299 [Byte1]: 47
3394 14:51:08.035911
3395 14:51:08.036483 Set Vref, RX VrefLevel [Byte0]: 48
3396 14:51:08.039519 [Byte1]: 48
3397 14:51:08.044054
3398 14:51:08.044559 Set Vref, RX VrefLevel [Byte0]: 49
3399 14:51:08.047588 [Byte1]: 49
3400 14:51:08.051643
3401 14:51:08.052101 Set Vref, RX VrefLevel [Byte0]: 50
3402 14:51:08.055300 [Byte1]: 50
3403 14:51:08.059926
3404 14:51:08.060702 Set Vref, RX VrefLevel [Byte0]: 51
3405 14:51:08.062854 [Byte1]: 51
3406 14:51:08.067879
3407 14:51:08.068479 Set Vref, RX VrefLevel [Byte0]: 52
3408 14:51:08.070951 [Byte1]: 52
3409 14:51:08.075398
3410 14:51:08.075952 Set Vref, RX VrefLevel [Byte0]: 53
3411 14:51:08.078652 [Byte1]: 53
3412 14:51:08.083462
3413 14:51:08.084012 Set Vref, RX VrefLevel [Byte0]: 54
3414 14:51:08.086971 [Byte1]: 54
3415 14:51:08.091175
3416 14:51:08.091729 Set Vref, RX VrefLevel [Byte0]: 55
3417 14:51:08.094577 [Byte1]: 55
3418 14:51:08.099335
3419 14:51:08.099884 Set Vref, RX VrefLevel [Byte0]: 56
3420 14:51:08.102306 [Byte1]: 56
3421 14:51:08.107102
3422 14:51:08.107655 Set Vref, RX VrefLevel [Byte0]: 57
3423 14:51:08.109734 [Byte1]: 57
3424 14:51:08.115079
3425 14:51:08.115626 Set Vref, RX VrefLevel [Byte0]: 58
3426 14:51:08.117918 [Byte1]: 58
3427 14:51:08.122590
3428 14:51:08.123081 Set Vref, RX VrefLevel [Byte0]: 59
3429 14:51:08.125729 [Byte1]: 59
3430 14:51:08.131400
3431 14:51:08.131964 Set Vref, RX VrefLevel [Byte0]: 60
3432 14:51:08.134088 [Byte1]: 60
3433 14:51:08.138271
3434 14:51:08.138848 Set Vref, RX VrefLevel [Byte0]: 61
3435 14:51:08.141729 [Byte1]: 61
3436 14:51:08.146164
3437 14:51:08.146725 Set Vref, RX VrefLevel [Byte0]: 62
3438 14:51:08.149106 [Byte1]: 62
3439 14:51:08.153383
3440 14:51:08.153839 Set Vref, RX VrefLevel [Byte0]: 63
3441 14:51:08.157166 [Byte1]: 63
3442 14:51:08.161645
3443 14:51:08.162302 Set Vref, RX VrefLevel [Byte0]: 64
3444 14:51:08.164862 [Byte1]: 64
3445 14:51:08.169572
3446 14:51:08.170074 Set Vref, RX VrefLevel [Byte0]: 65
3447 14:51:08.172695 [Byte1]: 65
3448 14:51:08.177491
3449 14:51:08.177899 Set Vref, RX VrefLevel [Byte0]: 66
3450 14:51:08.180863 [Byte1]: 66
3451 14:51:08.184883
3452 14:51:08.185293 Set Vref, RX VrefLevel [Byte0]: 67
3453 14:51:08.188871 [Byte1]: 67
3454 14:51:08.193059
3455 14:51:08.193562 Set Vref, RX VrefLevel [Byte0]: 68
3456 14:51:08.196160 [Byte1]: 68
3457 14:51:08.200823
3458 14:51:08.203736 Final RX Vref Byte 0 = 53 to rank0
3459 14:51:08.204147 Final RX Vref Byte 1 = 52 to rank0
3460 14:51:08.207560 Final RX Vref Byte 0 = 53 to rank1
3461 14:51:08.210845 Final RX Vref Byte 1 = 52 to rank1==
3462 14:51:08.213638 Dram Type= 6, Freq= 0, CH_1, rank 0
3463 14:51:08.220681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 14:51:08.221090 ==
3465 14:51:08.221413 DQS Delay:
3466 14:51:08.224135 DQS0 = 0, DQS1 = 0
3467 14:51:08.224570 DQM Delay:
3468 14:51:08.224894 DQM0 = 120, DQM1 = 117
3469 14:51:08.227236 DQ Delay:
3470 14:51:08.230957 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3471 14:51:08.234301 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3472 14:51:08.237211 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3473 14:51:08.240856 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3474 14:51:08.241433
3475 14:51:08.241765
3476 14:51:08.250848 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3477 14:51:08.251365 CH1 RK0: MR19=304, MR18=FF12
3478 14:51:08.257350 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3479 14:51:08.257808
3480 14:51:08.260953 ----->DramcWriteLeveling(PI) begin...
3481 14:51:08.261524 ==
3482 14:51:08.264421 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 14:51:08.270794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 14:51:08.271348 ==
3485 14:51:08.274180 Write leveling (Byte 0): 27 => 27
3486 14:51:08.274734 Write leveling (Byte 1): 28 => 28
3487 14:51:08.277602 DramcWriteLeveling(PI) end<-----
3488 14:51:08.278150
3489 14:51:08.278511 ==
3490 14:51:08.280592 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 14:51:08.287161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 14:51:08.287621 ==
3493 14:51:08.290948 [Gating] SW mode calibration
3494 14:51:08.297256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3495 14:51:08.300859 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3496 14:51:08.307864 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 14:51:08.311044 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 14:51:08.314278 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 14:51:08.317930 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 14:51:08.324608 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 14:51:08.327984 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 14:51:08.330692 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 0) (0 0)
3503 14:51:08.337879 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 14:51:08.341097 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 14:51:08.343766 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 14:51:08.350742 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 14:51:08.354532 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 14:51:08.357782 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 14:51:08.364629 1 0 20 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3510 14:51:08.367563 1 0 24 | B1->B0 | 4242 2424 | 1 0 | (0 0) (0 0)
3511 14:51:08.370808 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 14:51:08.377166 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 14:51:08.380902 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 14:51:08.384506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 14:51:08.391284 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 14:51:08.394521 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 14:51:08.397751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3518 14:51:08.404414 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3519 14:51:08.407875 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3520 14:51:08.410640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 14:51:08.417068 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 14:51:08.420682 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 14:51:08.424497 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 14:51:08.427453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 14:51:08.434203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 14:51:08.437134 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 14:51:08.441209 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 14:51:08.447195 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 14:51:08.450505 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 14:51:08.454016 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 14:51:08.460464 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 14:51:08.464065 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 14:51:08.466991 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 14:51:08.474215 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3535 14:51:08.477195 Total UI for P1: 0, mck2ui 16
3536 14:51:08.480718 best dqsien dly found for B1: ( 1, 3, 22)
3537 14:51:08.483870 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3538 14:51:08.487523 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 14:51:08.490875 Total UI for P1: 0, mck2ui 16
3540 14:51:08.493716 best dqsien dly found for B0: ( 1, 3, 26)
3541 14:51:08.497424 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3542 14:51:08.500608 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3543 14:51:08.501164
3544 14:51:08.507102 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3545 14:51:08.510073 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3546 14:51:08.514090 [Gating] SW calibration Done
3547 14:51:08.514546 ==
3548 14:51:08.516925 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 14:51:08.520676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 14:51:08.521237 ==
3551 14:51:08.521604 RX Vref Scan: 0
3552 14:51:08.521946
3553 14:51:08.523811 RX Vref 0 -> 0, step: 1
3554 14:51:08.524280
3555 14:51:08.527155 RX Delay -40 -> 252, step: 8
3556 14:51:08.530028 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3557 14:51:08.533730 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3558 14:51:08.540527 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3559 14:51:08.543396 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3560 14:51:08.546729 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3561 14:51:08.550243 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3562 14:51:08.553222 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3563 14:51:08.560021 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3564 14:51:08.563518 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3565 14:51:08.566573 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3566 14:51:08.570271 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3567 14:51:08.573545 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3568 14:51:08.580140 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3569 14:51:08.583623 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3570 14:51:08.586851 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3571 14:51:08.589987 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3572 14:51:08.590546 ==
3573 14:51:08.593910 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 14:51:08.600221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 14:51:08.600827 ==
3576 14:51:08.601196 DQS Delay:
3577 14:51:08.601537 DQS0 = 0, DQS1 = 0
3578 14:51:08.603073 DQM Delay:
3579 14:51:08.603537 DQM0 = 119, DQM1 = 117
3580 14:51:08.606276 DQ Delay:
3581 14:51:08.609712 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3582 14:51:08.613278 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3583 14:51:08.616562 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3584 14:51:08.619843 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3585 14:51:08.620427
3586 14:51:08.621015
3587 14:51:08.621371 ==
3588 14:51:08.623666 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 14:51:08.626621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 14:51:08.629600 ==
3591 14:51:08.630060
3592 14:51:08.630420
3593 14:51:08.630752 TX Vref Scan disable
3594 14:51:08.633053 == TX Byte 0 ==
3595 14:51:08.636094 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3596 14:51:08.639488 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3597 14:51:08.643032 == TX Byte 1 ==
3598 14:51:08.646019 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3599 14:51:08.649766 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3600 14:51:08.652767 ==
3601 14:51:08.653331 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 14:51:08.659323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 14:51:08.659852 ==
3604 14:51:08.670611 TX Vref=22, minBit 1, minWin=25, winSum=417
3605 14:51:08.673667 TX Vref=24, minBit 1, minWin=26, winSum=426
3606 14:51:08.677339 TX Vref=26, minBit 10, minWin=25, winSum=427
3607 14:51:08.680696 TX Vref=28, minBit 9, minWin=26, winSum=434
3608 14:51:08.683737 TX Vref=30, minBit 9, minWin=26, winSum=433
3609 14:51:08.690494 TX Vref=32, minBit 9, minWin=26, winSum=432
3610 14:51:08.693701 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3611 14:51:08.694172
3612 14:51:08.696808 Final TX Range 1 Vref 28
3613 14:51:08.697275
3614 14:51:08.697637 ==
3615 14:51:08.700381 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 14:51:08.703789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 14:51:08.704252 ==
3618 14:51:08.704743
3619 14:51:08.706835
3620 14:51:08.707273 TX Vref Scan disable
3621 14:51:08.710037 == TX Byte 0 ==
3622 14:51:08.713800 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3623 14:51:08.716895 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3624 14:51:08.720673 == TX Byte 1 ==
3625 14:51:08.724202 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3626 14:51:08.726907 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3627 14:51:08.730469
3628 14:51:08.731025 [DATLAT]
3629 14:51:08.731390 Freq=1200, CH1 RK1
3630 14:51:08.731725
3631 14:51:08.733210 DATLAT Default: 0xd
3632 14:51:08.733667 0, 0xFFFF, sum = 0
3633 14:51:08.736878 1, 0xFFFF, sum = 0
3634 14:51:08.737486 2, 0xFFFF, sum = 0
3635 14:51:08.739826 3, 0xFFFF, sum = 0
3636 14:51:08.740252 4, 0xFFFF, sum = 0
3637 14:51:08.743457 5, 0xFFFF, sum = 0
3638 14:51:08.746763 6, 0xFFFF, sum = 0
3639 14:51:08.747190 7, 0xFFFF, sum = 0
3640 14:51:08.750088 8, 0xFFFF, sum = 0
3641 14:51:08.750677 9, 0xFFFF, sum = 0
3642 14:51:08.753217 10, 0xFFFF, sum = 0
3643 14:51:08.753646 11, 0xFFFF, sum = 0
3644 14:51:08.756992 12, 0x0, sum = 1
3645 14:51:08.757532 13, 0x0, sum = 2
3646 14:51:08.759773 14, 0x0, sum = 3
3647 14:51:08.760197 15, 0x0, sum = 4
3648 14:51:08.760573 best_step = 13
3649 14:51:08.763685
3650 14:51:08.764206 ==
3651 14:51:08.766592 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 14:51:08.770113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 14:51:08.770535 ==
3654 14:51:08.770867 RX Vref Scan: 0
3655 14:51:08.771179
3656 14:51:08.773458 RX Vref 0 -> 0, step: 1
3657 14:51:08.773982
3658 14:51:08.776873 RX Delay -5 -> 252, step: 4
3659 14:51:08.780227 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3660 14:51:08.786550 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3661 14:51:08.789895 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3662 14:51:08.793370 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3663 14:51:08.796710 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3664 14:51:08.800186 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3665 14:51:08.806362 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3666 14:51:08.809854 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3667 14:51:08.813122 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3668 14:51:08.816120 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3669 14:51:08.820149 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3670 14:51:08.826809 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3671 14:51:08.829859 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3672 14:51:08.832941 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3673 14:51:08.836564 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3674 14:51:08.840186 iDelay=195, Bit 15, Center 126 (63 ~ 190) 128
3675 14:51:08.843312 ==
3676 14:51:08.843878 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 14:51:08.849350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 14:51:08.849905 ==
3679 14:51:08.850278 DQS Delay:
3680 14:51:08.853037 DQS0 = 0, DQS1 = 0
3681 14:51:08.853500 DQM Delay:
3682 14:51:08.856274 DQM0 = 120, DQM1 = 117
3683 14:51:08.856777 DQ Delay:
3684 14:51:08.859245 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3685 14:51:08.862815 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3686 14:51:08.866406 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3687 14:51:08.869365 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3688 14:51:08.869821
3689 14:51:08.870158
3690 14:51:08.879380 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3691 14:51:08.882770 CH1 RK1: MR19=403, MR18=11EF
3692 14:51:08.886195 CH1_RK1: MR19=0x403, MR18=0x11EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3693 14:51:08.889377 [RxdqsGatingPostProcess] freq 1200
3694 14:51:08.896215 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3695 14:51:08.899610 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 14:51:08.902571 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 14:51:08.905988 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 14:51:08.909268 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 14:51:08.912478 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 14:51:08.915541 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 14:51:08.918904 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 14:51:08.922460 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 14:51:08.926393 Pre-setting of DQS Precalculation
3704 14:51:08.929131 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3705 14:51:08.936282 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3706 14:51:08.942218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3707 14:51:08.942773
3708 14:51:08.943136
3709 14:51:08.946252 [Calibration Summary] 2400 Mbps
3710 14:51:08.949135 CH 0, Rank 0
3711 14:51:08.949600 SW Impedance : PASS
3712 14:51:08.952727 DUTY Scan : NO K
3713 14:51:08.955743 ZQ Calibration : PASS
3714 14:51:08.956161 Jitter Meter : NO K
3715 14:51:08.959140 CBT Training : PASS
3716 14:51:08.962721 Write leveling : PASS
3717 14:51:08.963245 RX DQS gating : PASS
3718 14:51:08.965505 RX DQ/DQS(RDDQC) : PASS
3719 14:51:08.965926 TX DQ/DQS : PASS
3720 14:51:08.969480 RX DATLAT : PASS
3721 14:51:08.972636 RX DQ/DQS(Engine): PASS
3722 14:51:08.973166 TX OE : NO K
3723 14:51:08.976052 All Pass.
3724 14:51:08.976613
3725 14:51:08.976949 CH 0, Rank 1
3726 14:51:08.979165 SW Impedance : PASS
3727 14:51:08.979591 DUTY Scan : NO K
3728 14:51:08.982988 ZQ Calibration : PASS
3729 14:51:08.985592 Jitter Meter : NO K
3730 14:51:08.986032 CBT Training : PASS
3731 14:51:08.989249 Write leveling : PASS
3732 14:51:08.992862 RX DQS gating : PASS
3733 14:51:08.993392 RX DQ/DQS(RDDQC) : PASS
3734 14:51:08.996010 TX DQ/DQS : PASS
3735 14:51:08.999176 RX DATLAT : PASS
3736 14:51:08.999596 RX DQ/DQS(Engine): PASS
3737 14:51:09.002473 TX OE : NO K
3738 14:51:09.002894 All Pass.
3739 14:51:09.003226
3740 14:51:09.005799 CH 1, Rank 0
3741 14:51:09.006340 SW Impedance : PASS
3742 14:51:09.009222 DUTY Scan : NO K
3743 14:51:09.012214 ZQ Calibration : PASS
3744 14:51:09.012673 Jitter Meter : NO K
3745 14:51:09.015492 CBT Training : PASS
3746 14:51:09.018999 Write leveling : PASS
3747 14:51:09.019417 RX DQS gating : PASS
3748 14:51:09.022088 RX DQ/DQS(RDDQC) : PASS
3749 14:51:09.022680 TX DQ/DQS : PASS
3750 14:51:09.025610 RX DATLAT : PASS
3751 14:51:09.028657 RX DQ/DQS(Engine): PASS
3752 14:51:09.029077 TX OE : NO K
3753 14:51:09.032255 All Pass.
3754 14:51:09.032846
3755 14:51:09.033196 CH 1, Rank 1
3756 14:51:09.035472 SW Impedance : PASS
3757 14:51:09.035890 DUTY Scan : NO K
3758 14:51:09.038726 ZQ Calibration : PASS
3759 14:51:09.041829 Jitter Meter : NO K
3760 14:51:09.042262 CBT Training : PASS
3761 14:51:09.046007 Write leveling : PASS
3762 14:51:09.049206 RX DQS gating : PASS
3763 14:51:09.049731 RX DQ/DQS(RDDQC) : PASS
3764 14:51:09.051816 TX DQ/DQS : PASS
3765 14:51:09.055707 RX DATLAT : PASS
3766 14:51:09.056236 RX DQ/DQS(Engine): PASS
3767 14:51:09.059015 TX OE : NO K
3768 14:51:09.059542 All Pass.
3769 14:51:09.059882
3770 14:51:09.062027 DramC Write-DBI off
3771 14:51:09.065616 PER_BANK_REFRESH: Hybrid Mode
3772 14:51:09.066144 TX_TRACKING: ON
3773 14:51:09.075403 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3774 14:51:09.078422 [FAST_K] Save calibration result to emmc
3775 14:51:09.081956 dramc_set_vcore_voltage set vcore to 650000
3776 14:51:09.085997 Read voltage for 600, 5
3777 14:51:09.086516 Vio18 = 0
3778 14:51:09.086852 Vcore = 650000
3779 14:51:09.088891 Vdram = 0
3780 14:51:09.089306 Vddq = 0
3781 14:51:09.089638 Vmddr = 0
3782 14:51:09.095751 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3783 14:51:09.098490 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3784 14:51:09.101599 MEM_TYPE=3, freq_sel=19
3785 14:51:09.105776 sv_algorithm_assistance_LP4_1600
3786 14:51:09.108902 ============ PULL DRAM RESETB DOWN ============
3787 14:51:09.111978 ========== PULL DRAM RESETB DOWN end =========
3788 14:51:09.118645 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3789 14:51:09.122338 ===================================
3790 14:51:09.122965 LPDDR4 DRAM CONFIGURATION
3791 14:51:09.125143 ===================================
3792 14:51:09.128585 EX_ROW_EN[0] = 0x0
3793 14:51:09.131646 EX_ROW_EN[1] = 0x0
3794 14:51:09.132067 LP4Y_EN = 0x0
3795 14:51:09.135386 WORK_FSP = 0x0
3796 14:51:09.135909 WL = 0x2
3797 14:51:09.138285 RL = 0x2
3798 14:51:09.138761 BL = 0x2
3799 14:51:09.141633 RPST = 0x0
3800 14:51:09.142049 RD_PRE = 0x0
3801 14:51:09.144828 WR_PRE = 0x1
3802 14:51:09.145261 WR_PST = 0x0
3803 14:51:09.148904 DBI_WR = 0x0
3804 14:51:09.149428 DBI_RD = 0x0
3805 14:51:09.151900 OTF = 0x1
3806 14:51:09.155413 ===================================
3807 14:51:09.158699 ===================================
3808 14:51:09.159223 ANA top config
3809 14:51:09.162539 ===================================
3810 14:51:09.165070 DLL_ASYNC_EN = 0
3811 14:51:09.168370 ALL_SLAVE_EN = 1
3812 14:51:09.171498 NEW_RANK_MODE = 1
3813 14:51:09.172020 DLL_IDLE_MODE = 1
3814 14:51:09.174955 LP45_APHY_COMB_EN = 1
3815 14:51:09.178410 TX_ODT_DIS = 1
3816 14:51:09.181498 NEW_8X_MODE = 1
3817 14:51:09.185142 ===================================
3818 14:51:09.188072 ===================================
3819 14:51:09.191667 data_rate = 1200
3820 14:51:09.192182 CKR = 1
3821 14:51:09.195275 DQ_P2S_RATIO = 8
3822 14:51:09.198532 ===================================
3823 14:51:09.202283 CA_P2S_RATIO = 8
3824 14:51:09.204997 DQ_CA_OPEN = 0
3825 14:51:09.207998 DQ_SEMI_OPEN = 0
3826 14:51:09.211671 CA_SEMI_OPEN = 0
3827 14:51:09.212157 CA_FULL_RATE = 0
3828 14:51:09.214865 DQ_CKDIV4_EN = 1
3829 14:51:09.217627 CA_CKDIV4_EN = 1
3830 14:51:09.221601 CA_PREDIV_EN = 0
3831 14:51:09.224416 PH8_DLY = 0
3832 14:51:09.227980 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3833 14:51:09.228541 DQ_AAMCK_DIV = 4
3834 14:51:09.231106 CA_AAMCK_DIV = 4
3835 14:51:09.234633 CA_ADMCK_DIV = 4
3836 14:51:09.237597 DQ_TRACK_CA_EN = 0
3837 14:51:09.241512 CA_PICK = 600
3838 14:51:09.244549 CA_MCKIO = 600
3839 14:51:09.245014 MCKIO_SEMI = 0
3840 14:51:09.247603 PLL_FREQ = 2288
3841 14:51:09.251736 DQ_UI_PI_RATIO = 32
3842 14:51:09.254478 CA_UI_PI_RATIO = 0
3843 14:51:09.257633 ===================================
3844 14:51:09.261190 ===================================
3845 14:51:09.264799 memory_type:LPDDR4
3846 14:51:09.265315 GP_NUM : 10
3847 14:51:09.267752 SRAM_EN : 1
3848 14:51:09.270841 MD32_EN : 0
3849 14:51:09.275065 ===================================
3850 14:51:09.275582 [ANA_INIT] >>>>>>>>>>>>>>
3851 14:51:09.277575 <<<<<< [CONFIGURE PHASE]: ANA_TX
3852 14:51:09.281321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3853 14:51:09.285011 ===================================
3854 14:51:09.287998 data_rate = 1200,PCW = 0X5800
3855 14:51:09.291217 ===================================
3856 14:51:09.294487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3857 14:51:09.301102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 14:51:09.304055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 14:51:09.311059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3860 14:51:09.314217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3861 14:51:09.317142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3862 14:51:09.317680 [ANA_INIT] flow start
3863 14:51:09.320697 [ANA_INIT] PLL >>>>>>>>
3864 14:51:09.323770 [ANA_INIT] PLL <<<<<<<<
3865 14:51:09.327800 [ANA_INIT] MIDPI >>>>>>>>
3866 14:51:09.328315 [ANA_INIT] MIDPI <<<<<<<<
3867 14:51:09.330633 [ANA_INIT] DLL >>>>>>>>
3868 14:51:09.334416 [ANA_INIT] flow end
3869 14:51:09.337411 ============ LP4 DIFF to SE enter ============
3870 14:51:09.340459 ============ LP4 DIFF to SE exit ============
3871 14:51:09.344177 [ANA_INIT] <<<<<<<<<<<<<
3872 14:51:09.347652 [Flow] Enable top DCM control >>>>>
3873 14:51:09.350434 [Flow] Enable top DCM control <<<<<
3874 14:51:09.354130 Enable DLL master slave shuffle
3875 14:51:09.357437 ==============================================================
3876 14:51:09.360703 Gating Mode config
3877 14:51:09.364170 ==============================================================
3878 14:51:09.367437 Config description:
3879 14:51:09.377039 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3880 14:51:09.383854 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3881 14:51:09.387404 SELPH_MODE 0: By rank 1: By Phase
3882 14:51:09.394007 ==============================================================
3883 14:51:09.397669 GAT_TRACK_EN = 1
3884 14:51:09.400377 RX_GATING_MODE = 2
3885 14:51:09.403693 RX_GATING_TRACK_MODE = 2
3886 14:51:09.407608 SELPH_MODE = 1
3887 14:51:09.410940 PICG_EARLY_EN = 1
3888 14:51:09.411501 VALID_LAT_VALUE = 1
3889 14:51:09.417536 ==============================================================
3890 14:51:09.420542 Enter into Gating configuration >>>>
3891 14:51:09.424189 Exit from Gating configuration <<<<
3892 14:51:09.427764 Enter into DVFS_PRE_config >>>>>
3893 14:51:09.437365 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3894 14:51:09.440726 Exit from DVFS_PRE_config <<<<<
3895 14:51:09.443811 Enter into PICG configuration >>>>
3896 14:51:09.447243 Exit from PICG configuration <<<<
3897 14:51:09.450540 [RX_INPUT] configuration >>>>>
3898 14:51:09.453759 [RX_INPUT] configuration <<<<<
3899 14:51:09.456663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3900 14:51:09.464208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3901 14:51:09.470542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 14:51:09.477227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 14:51:09.484147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 14:51:09.490766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 14:51:09.494041 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3906 14:51:09.497013 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3907 14:51:09.500856 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3908 14:51:09.503752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3909 14:51:09.510760 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3910 14:51:09.513521 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 14:51:09.517084 ===================================
3912 14:51:09.520795 LPDDR4 DRAM CONFIGURATION
3913 14:51:09.523534 ===================================
3914 14:51:09.524100 EX_ROW_EN[0] = 0x0
3915 14:51:09.527064 EX_ROW_EN[1] = 0x0
3916 14:51:09.527632 LP4Y_EN = 0x0
3917 14:51:09.530327 WORK_FSP = 0x0
3918 14:51:09.530788 WL = 0x2
3919 14:51:09.533610 RL = 0x2
3920 14:51:09.534176 BL = 0x2
3921 14:51:09.537048 RPST = 0x0
3922 14:51:09.540236 RD_PRE = 0x0
3923 14:51:09.540726 WR_PRE = 0x1
3924 14:51:09.543810 WR_PST = 0x0
3925 14:51:09.544272 DBI_WR = 0x0
3926 14:51:09.547217 DBI_RD = 0x0
3927 14:51:09.547779 OTF = 0x1
3928 14:51:09.550034 ===================================
3929 14:51:09.553708 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3930 14:51:09.557049 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3931 14:51:09.563584 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 14:51:09.566563 ===================================
3933 14:51:09.570370 LPDDR4 DRAM CONFIGURATION
3934 14:51:09.573171 ===================================
3935 14:51:09.573642 EX_ROW_EN[0] = 0x10
3936 14:51:09.577306 EX_ROW_EN[1] = 0x0
3937 14:51:09.577873 LP4Y_EN = 0x0
3938 14:51:09.580273 WORK_FSP = 0x0
3939 14:51:09.580781 WL = 0x2
3940 14:51:09.583660 RL = 0x2
3941 14:51:09.584223 BL = 0x2
3942 14:51:09.586850 RPST = 0x0
3943 14:51:09.587427 RD_PRE = 0x0
3944 14:51:09.590178 WR_PRE = 0x1
3945 14:51:09.590647 WR_PST = 0x0
3946 14:51:09.593853 DBI_WR = 0x0
3947 14:51:09.594416 DBI_RD = 0x0
3948 14:51:09.596885 OTF = 0x1
3949 14:51:09.600186 ===================================
3950 14:51:09.606817 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3951 14:51:09.610555 nWR fixed to 30
3952 14:51:09.613468 [ModeRegInit_LP4] CH0 RK0
3953 14:51:09.613933 [ModeRegInit_LP4] CH0 RK1
3954 14:51:09.617296 [ModeRegInit_LP4] CH1 RK0
3955 14:51:09.620334 [ModeRegInit_LP4] CH1 RK1
3956 14:51:09.620828 match AC timing 17
3957 14:51:09.627099 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3958 14:51:09.630516 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 14:51:09.633236 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3960 14:51:09.640071 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3961 14:51:09.643873 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3962 14:51:09.644488 ==
3963 14:51:09.647087 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 14:51:09.650646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 14:51:09.651212 ==
3966 14:51:09.657384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 14:51:09.663552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3968 14:51:09.667151 [CA 0] Center 35 (5~66) winsize 62
3969 14:51:09.670225 [CA 1] Center 36 (5~67) winsize 63
3970 14:51:09.673186 [CA 2] Center 33 (3~64) winsize 62
3971 14:51:09.676815 [CA 3] Center 33 (2~64) winsize 63
3972 14:51:09.680331 [CA 4] Center 33 (2~64) winsize 63
3973 14:51:09.683689 [CA 5] Center 32 (2~63) winsize 62
3974 14:51:09.684150
3975 14:51:09.686880 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3976 14:51:09.687342
3977 14:51:09.690053 [CATrainingPosCal] consider 1 rank data
3978 14:51:09.693427 u2DelayCellTimex100 = 270/100 ps
3979 14:51:09.697029 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3980 14:51:09.700170 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3981 14:51:09.703893 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3982 14:51:09.707151 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3983 14:51:09.710595 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3984 14:51:09.713342 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3985 14:51:09.713870
3986 14:51:09.720519 CA PerBit enable=1, Macro0, CA PI delay=32
3987 14:51:09.720999
3988 14:51:09.721480 [CBTSetCACLKResult] CA Dly = 32
3989 14:51:09.723646 CS Dly: 4 (0~35)
3990 14:51:09.724124 ==
3991 14:51:09.726555 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 14:51:09.730219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 14:51:09.730797 ==
3994 14:51:09.737059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 14:51:09.743633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 14:51:09.747081 [CA 0] Center 35 (5~66) winsize 62
3997 14:51:09.749900 [CA 1] Center 35 (5~66) winsize 62
3998 14:51:09.753578 [CA 2] Center 34 (3~65) winsize 63
3999 14:51:09.756916 [CA 3] Center 33 (3~64) winsize 62
4000 14:51:09.759889 [CA 4] Center 33 (2~64) winsize 63
4001 14:51:09.763200 [CA 5] Center 32 (2~63) winsize 62
4002 14:51:09.763728
4003 14:51:09.766533 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 14:51:09.766990
4005 14:51:09.769785 [CATrainingPosCal] consider 2 rank data
4006 14:51:09.772833 u2DelayCellTimex100 = 270/100 ps
4007 14:51:09.776605 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4008 14:51:09.779675 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4009 14:51:09.783169 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4010 14:51:09.786256 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4011 14:51:09.789971 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4012 14:51:09.796834 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4013 14:51:09.797363
4014 14:51:09.799892 CA PerBit enable=1, Macro0, CA PI delay=32
4015 14:51:09.800469
4016 14:51:09.802897 [CBTSetCACLKResult] CA Dly = 32
4017 14:51:09.803332 CS Dly: 5 (0~37)
4018 14:51:09.803767
4019 14:51:09.805923 ----->DramcWriteLeveling(PI) begin...
4020 14:51:09.806365 ==
4021 14:51:09.809194 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 14:51:09.815927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 14:51:09.816397 ==
4024 14:51:09.819681 Write leveling (Byte 0): 35 => 35
4025 14:51:09.820119 Write leveling (Byte 1): 32 => 32
4026 14:51:09.822786 DramcWriteLeveling(PI) end<-----
4027 14:51:09.823219
4028 14:51:09.823652 ==
4029 14:51:09.825607 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 14:51:09.832763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 14:51:09.833302 ==
4032 14:51:09.835649 [Gating] SW mode calibration
4033 14:51:09.842146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 14:51:09.845588 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4035 14:51:09.852264 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 14:51:09.855779 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 14:51:09.859134 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 14:51:09.865731 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4039 14:51:09.868962 0 9 16 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
4040 14:51:09.872414 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 14:51:09.879357 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 14:51:09.883038 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 14:51:09.885791 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 14:51:09.889231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 14:51:09.896165 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 14:51:09.898963 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
4047 14:51:09.902130 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
4048 14:51:09.909042 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 14:51:09.912720 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 14:51:09.915383 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 14:51:09.922577 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 14:51:09.925548 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 14:51:09.928941 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 14:51:09.935807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 14:51:09.939219 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 14:51:09.941878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 14:51:09.948991 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 14:51:09.952503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 14:51:09.955561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 14:51:09.962154 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 14:51:09.965242 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 14:51:09.968897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 14:51:09.975430 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 14:51:09.979021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 14:51:09.982477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 14:51:09.988704 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 14:51:09.991972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 14:51:09.995749 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 14:51:10.001789 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 14:51:10.005283 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 14:51:10.008580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4072 14:51:10.011933 Total UI for P1: 0, mck2ui 16
4073 14:51:10.015596 best dqsien dly found for B0: ( 0, 13, 12)
4074 14:51:10.018596 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 14:51:10.021618 Total UI for P1: 0, mck2ui 16
4076 14:51:10.024877 best dqsien dly found for B1: ( 0, 13, 16)
4077 14:51:10.031770 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4078 14:51:10.035580 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4079 14:51:10.036114
4080 14:51:10.038721 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 14:51:10.042094 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4082 14:51:10.045050 [Gating] SW calibration Done
4083 14:51:10.045513 ==
4084 14:51:10.048935 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 14:51:10.051956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 14:51:10.052455 ==
4087 14:51:10.055000 RX Vref Scan: 0
4088 14:51:10.055563
4089 14:51:10.055932 RX Vref 0 -> 0, step: 1
4090 14:51:10.056273
4091 14:51:10.058994 RX Delay -230 -> 252, step: 16
4092 14:51:10.061689 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4093 14:51:10.068988 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4094 14:51:10.072284 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4095 14:51:10.075593 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4096 14:51:10.079009 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4097 14:51:10.082133 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4098 14:51:10.088979 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4099 14:51:10.092403 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4100 14:51:10.095470 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4101 14:51:10.098474 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4102 14:51:10.105525 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4103 14:51:10.108316 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4104 14:51:10.112499 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4105 14:51:10.115435 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4106 14:51:10.121646 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4107 14:51:10.124953 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4108 14:51:10.125416 ==
4109 14:51:10.128875 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 14:51:10.131914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 14:51:10.132413 ==
4112 14:51:10.132794 DQS Delay:
4113 14:51:10.135431 DQS0 = 0, DQS1 = 0
4114 14:51:10.136005 DQM Delay:
4115 14:51:10.138056 DQM0 = 50, DQM1 = 44
4116 14:51:10.138674 DQ Delay:
4117 14:51:10.142203 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4118 14:51:10.145524 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4119 14:51:10.148409 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4120 14:51:10.152085 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4121 14:51:10.152592
4122 14:51:10.152928
4123 14:51:10.153283 ==
4124 14:51:10.155111 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 14:51:10.159231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 14:51:10.161988 ==
4127 14:51:10.162514
4128 14:51:10.162847
4129 14:51:10.163157 TX Vref Scan disable
4130 14:51:10.165527 == TX Byte 0 ==
4131 14:51:10.168544 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4132 14:51:10.171991 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4133 14:51:10.174686 == TX Byte 1 ==
4134 14:51:10.178158 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 14:51:10.182019 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 14:51:10.185009 ==
4137 14:51:10.188255 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 14:51:10.192206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 14:51:10.192782 ==
4140 14:51:10.193118
4141 14:51:10.193430
4142 14:51:10.194775 TX Vref Scan disable
4143 14:51:10.195195 == TX Byte 0 ==
4144 14:51:10.201497 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4145 14:51:10.204311 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4146 14:51:10.208109 == TX Byte 1 ==
4147 14:51:10.211226 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4148 14:51:10.214638 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4149 14:51:10.215103
4150 14:51:10.215462 [DATLAT]
4151 14:51:10.217599 Freq=600, CH0 RK0
4152 14:51:10.218066
4153 14:51:10.218430 DATLAT Default: 0x9
4154 14:51:10.221728 0, 0xFFFF, sum = 0
4155 14:51:10.224464 1, 0xFFFF, sum = 0
4156 14:51:10.224936 2, 0xFFFF, sum = 0
4157 14:51:10.228410 3, 0xFFFF, sum = 0
4158 14:51:10.228997 4, 0xFFFF, sum = 0
4159 14:51:10.231602 5, 0xFFFF, sum = 0
4160 14:51:10.232185 6, 0xFFFF, sum = 0
4161 14:51:10.234264 7, 0xFFFF, sum = 0
4162 14:51:10.234758 8, 0x0, sum = 1
4163 14:51:10.237688 9, 0x0, sum = 2
4164 14:51:10.238160 10, 0x0, sum = 3
4165 14:51:10.238596 11, 0x0, sum = 4
4166 14:51:10.241460 best_step = 9
4167 14:51:10.241923
4168 14:51:10.242287 ==
4169 14:51:10.245001 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 14:51:10.248732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 14:51:10.249340 ==
4172 14:51:10.251193 RX Vref Scan: 1
4173 14:51:10.251658
4174 14:51:10.252022 RX Vref 0 -> 0, step: 1
4175 14:51:10.254638
4176 14:51:10.255099 RX Delay -163 -> 252, step: 8
4177 14:51:10.255464
4178 14:51:10.257271 Set Vref, RX VrefLevel [Byte0]: 56
4179 14:51:10.260917 [Byte1]: 47
4180 14:51:10.265913
4181 14:51:10.266474 Final RX Vref Byte 0 = 56 to rank0
4182 14:51:10.268320 Final RX Vref Byte 1 = 47 to rank0
4183 14:51:10.271876 Final RX Vref Byte 0 = 56 to rank1
4184 14:51:10.275132 Final RX Vref Byte 1 = 47 to rank1==
4185 14:51:10.278407 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 14:51:10.285075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 14:51:10.285502 ==
4188 14:51:10.285837 DQS Delay:
4189 14:51:10.286146 DQS0 = 0, DQS1 = 0
4190 14:51:10.288299 DQM Delay:
4191 14:51:10.288773 DQM0 = 53, DQM1 = 46
4192 14:51:10.291822 DQ Delay:
4193 14:51:10.295518 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4194 14:51:10.298420 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =56
4195 14:51:10.298987 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4196 14:51:10.305065 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4197 14:51:10.305497
4198 14:51:10.305842
4199 14:51:10.311936 [DQSOSCAuto] RK0, (LSB)MR18= 0x7367, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4200 14:51:10.314904 CH0 RK0: MR19=808, MR18=7367
4201 14:51:10.321687 CH0_RK0: MR19=0x808, MR18=0x7367, DQSOSC=388, MR23=63, INC=174, DEC=116
4202 14:51:10.322177
4203 14:51:10.325029 ----->DramcWriteLeveling(PI) begin...
4204 14:51:10.325746 ==
4205 14:51:10.327979 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 14:51:10.331828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 14:51:10.332549 ==
4208 14:51:10.334916 Write leveling (Byte 0): 34 => 34
4209 14:51:10.338084 Write leveling (Byte 1): 30 => 30
4210 14:51:10.341667 DramcWriteLeveling(PI) end<-----
4211 14:51:10.342110
4212 14:51:10.342442 ==
4213 14:51:10.344524 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 14:51:10.348032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 14:51:10.348490 ==
4216 14:51:10.351742 [Gating] SW mode calibration
4217 14:51:10.358215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 14:51:10.364875 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 14:51:10.368171 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 14:51:10.374596 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 14:51:10.377866 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 14:51:10.380828 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 14:51:10.387768 0 9 16 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
4224 14:51:10.391835 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 14:51:10.394547 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 14:51:10.401027 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 14:51:10.404549 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 14:51:10.408013 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 14:51:10.411368 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 14:51:10.417439 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4231 14:51:10.421176 0 10 16 | B1->B0 | 4040 4242 | 0 0 | (0 0) (0 0)
4232 14:51:10.424382 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 14:51:10.430896 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 14:51:10.434284 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 14:51:10.438030 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 14:51:10.444280 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 14:51:10.447807 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 14:51:10.451386 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4239 14:51:10.457740 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4240 14:51:10.460704 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 14:51:10.464176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 14:51:10.470823 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 14:51:10.474111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 14:51:10.477746 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 14:51:10.484494 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 14:51:10.487509 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 14:51:10.490790 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 14:51:10.497724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 14:51:10.500565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 14:51:10.504420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 14:51:10.511291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 14:51:10.514278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 14:51:10.517361 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 14:51:10.524194 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4255 14:51:10.527468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 14:51:10.530611 Total UI for P1: 0, mck2ui 16
4257 14:51:10.534043 best dqsien dly found for B0: ( 0, 13, 12)
4258 14:51:10.537545 Total UI for P1: 0, mck2ui 16
4259 14:51:10.540675 best dqsien dly found for B1: ( 0, 13, 14)
4260 14:51:10.544113 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4261 14:51:10.547086 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4262 14:51:10.547554
4263 14:51:10.550671 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4264 14:51:10.553818 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4265 14:51:10.557031 [Gating] SW calibration Done
4266 14:51:10.557495 ==
4267 14:51:10.560460 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 14:51:10.563925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 14:51:10.567542 ==
4270 14:51:10.568102 RX Vref Scan: 0
4271 14:51:10.568576
4272 14:51:10.570616 RX Vref 0 -> 0, step: 1
4273 14:51:10.571183
4274 14:51:10.573686 RX Delay -230 -> 252, step: 16
4275 14:51:10.577393 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4276 14:51:10.580542 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4277 14:51:10.584220 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4278 14:51:10.586559 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4279 14:51:10.593392 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4280 14:51:10.597229 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4281 14:51:10.600296 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4282 14:51:10.603430 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4283 14:51:10.610137 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4284 14:51:10.613493 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4285 14:51:10.616465 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4286 14:51:10.619930 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4287 14:51:10.626561 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4288 14:51:10.630290 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4289 14:51:10.633042 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4290 14:51:10.636187 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4291 14:51:10.636788 ==
4292 14:51:10.639575 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 14:51:10.646142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 14:51:10.646611 ==
4295 14:51:10.646977 DQS Delay:
4296 14:51:10.649630 DQS0 = 0, DQS1 = 0
4297 14:51:10.650182 DQM Delay:
4298 14:51:10.650546 DQM0 = 56, DQM1 = 43
4299 14:51:10.652638 DQ Delay:
4300 14:51:10.656162 DQ0 =57, DQ1 =57, DQ2 =49, DQ3 =49
4301 14:51:10.660077 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4302 14:51:10.662607 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4303 14:51:10.666336 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4304 14:51:10.666891
4305 14:51:10.667255
4306 14:51:10.667689 ==
4307 14:51:10.669243 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 14:51:10.672618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 14:51:10.673186 ==
4310 14:51:10.673558
4311 14:51:10.673901
4312 14:51:10.675906 TX Vref Scan disable
4313 14:51:10.679153 == TX Byte 0 ==
4314 14:51:10.682670 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4315 14:51:10.685766 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4316 14:51:10.689497 == TX Byte 1 ==
4317 14:51:10.692999 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4318 14:51:10.696145 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4319 14:51:10.696769 ==
4320 14:51:10.700073 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 14:51:10.702731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 14:51:10.703222 ==
4323 14:51:10.705910
4324 14:51:10.706367
4325 14:51:10.706728 TX Vref Scan disable
4326 14:51:10.709486 == TX Byte 0 ==
4327 14:51:10.713328 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4328 14:51:10.716381 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4329 14:51:10.719497 == TX Byte 1 ==
4330 14:51:10.723099 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4331 14:51:10.729829 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4332 14:51:10.730411
4333 14:51:10.730780 [DATLAT]
4334 14:51:10.731118 Freq=600, CH0 RK1
4335 14:51:10.731448
4336 14:51:10.733030 DATLAT Default: 0x9
4337 14:51:10.733496 0, 0xFFFF, sum = 0
4338 14:51:10.736203 1, 0xFFFF, sum = 0
4339 14:51:10.736719 2, 0xFFFF, sum = 0
4340 14:51:10.739598 3, 0xFFFF, sum = 0
4341 14:51:10.740071 4, 0xFFFF, sum = 0
4342 14:51:10.742810 5, 0xFFFF, sum = 0
4343 14:51:10.746229 6, 0xFFFF, sum = 0
4344 14:51:10.746656 7, 0xFFFF, sum = 0
4345 14:51:10.746995 8, 0x0, sum = 1
4346 14:51:10.749939 9, 0x0, sum = 2
4347 14:51:10.750473 10, 0x0, sum = 3
4348 14:51:10.752837 11, 0x0, sum = 4
4349 14:51:10.753263 best_step = 9
4350 14:51:10.753591
4351 14:51:10.753897 ==
4352 14:51:10.756436 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 14:51:10.763547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 14:51:10.764071 ==
4355 14:51:10.764529 RX Vref Scan: 0
4356 14:51:10.764855
4357 14:51:10.765784 RX Vref 0 -> 0, step: 1
4358 14:51:10.766203
4359 14:51:10.769536 RX Delay -163 -> 252, step: 8
4360 14:51:10.772558 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4361 14:51:10.779313 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4362 14:51:10.782682 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4363 14:51:10.785743 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4364 14:51:10.789360 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4365 14:51:10.792432 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4366 14:51:10.796203 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4367 14:51:10.803082 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4368 14:51:10.805867 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4369 14:51:10.809050 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4370 14:51:10.813199 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4371 14:51:10.819226 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4372 14:51:10.822338 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4373 14:51:10.825534 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4374 14:51:10.829374 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4375 14:51:10.832429 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4376 14:51:10.836117 ==
4377 14:51:10.839234 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 14:51:10.842571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 14:51:10.842999 ==
4380 14:51:10.843329 DQS Delay:
4381 14:51:10.845740 DQS0 = 0, DQS1 = 0
4382 14:51:10.846158 DQM Delay:
4383 14:51:10.849568 DQM0 = 54, DQM1 = 46
4384 14:51:10.850076 DQ Delay:
4385 14:51:10.852293 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4386 14:51:10.856015 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4387 14:51:10.859275 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4388 14:51:10.862767 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4389 14:51:10.863273
4390 14:51:10.863605
4391 14:51:10.869270 [DQSOSCAuto] RK1, (LSB)MR18= 0x6123, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4392 14:51:10.872200 CH0 RK1: MR19=808, MR18=6123
4393 14:51:10.879318 CH0_RK1: MR19=0x808, MR18=0x6123, DQSOSC=391, MR23=63, INC=171, DEC=114
4394 14:51:10.882512 [RxdqsGatingPostProcess] freq 600
4395 14:51:10.888911 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4396 14:51:10.889421 Pre-setting of DQS Precalculation
4397 14:51:10.895286 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4398 14:51:10.895796 ==
4399 14:51:10.898657 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 14:51:10.903046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 14:51:10.903558 ==
4402 14:51:10.909009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 14:51:10.915637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4404 14:51:10.918576 [CA 0] Center 36 (5~67) winsize 63
4405 14:51:10.922253 [CA 1] Center 36 (5~67) winsize 63
4406 14:51:10.925234 [CA 2] Center 35 (4~66) winsize 63
4407 14:51:10.929047 [CA 3] Center 34 (4~65) winsize 62
4408 14:51:10.932105 [CA 4] Center 34 (4~65) winsize 62
4409 14:51:10.935020 [CA 5] Center 34 (3~65) winsize 63
4410 14:51:10.935438
4411 14:51:10.938791 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4412 14:51:10.939302
4413 14:51:10.942259 [CATrainingPosCal] consider 1 rank data
4414 14:51:10.945142 u2DelayCellTimex100 = 270/100 ps
4415 14:51:10.948653 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4416 14:51:10.951905 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4417 14:51:10.955034 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4418 14:51:10.958649 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 14:51:10.961967 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 14:51:10.965182 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4421 14:51:10.968609
4422 14:51:10.971564 CA PerBit enable=1, Macro0, CA PI delay=34
4423 14:51:10.971985
4424 14:51:10.975325 [CBTSetCACLKResult] CA Dly = 34
4425 14:51:10.975843 CS Dly: 5 (0~36)
4426 14:51:10.976177 ==
4427 14:51:10.978876 Dram Type= 6, Freq= 0, CH_1, rank 1
4428 14:51:10.981870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 14:51:10.982386 ==
4430 14:51:10.988149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 14:51:10.995215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4432 14:51:10.998539 [CA 0] Center 36 (5~67) winsize 63
4433 14:51:11.001847 [CA 1] Center 36 (6~67) winsize 62
4434 14:51:11.005303 [CA 2] Center 35 (4~66) winsize 63
4435 14:51:11.008843 [CA 3] Center 35 (4~66) winsize 63
4436 14:51:11.011984 [CA 4] Center 35 (4~66) winsize 63
4437 14:51:11.014915 [CA 5] Center 34 (4~65) winsize 62
4438 14:51:11.015337
4439 14:51:11.018600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4440 14:51:11.019017
4441 14:51:11.021933 [CATrainingPosCal] consider 2 rank data
4442 14:51:11.025483 u2DelayCellTimex100 = 270/100 ps
4443 14:51:11.028451 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4444 14:51:11.031801 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4445 14:51:11.034720 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4446 14:51:11.038424 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 14:51:11.041534 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4448 14:51:11.047978 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 14:51:11.048433
4450 14:51:11.051459 CA PerBit enable=1, Macro0, CA PI delay=34
4451 14:51:11.051974
4452 14:51:11.055152 [CBTSetCACLKResult] CA Dly = 34
4453 14:51:11.055570 CS Dly: 6 (0~38)
4454 14:51:11.055930
4455 14:51:11.058249 ----->DramcWriteLeveling(PI) begin...
4456 14:51:11.058667 ==
4457 14:51:11.061262 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 14:51:11.067895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 14:51:11.068314 ==
4460 14:51:11.071369 Write leveling (Byte 0): 28 => 28
4461 14:51:11.071783 Write leveling (Byte 1): 31 => 31
4462 14:51:11.074721 DramcWriteLeveling(PI) end<-----
4463 14:51:11.075279
4464 14:51:11.075833 ==
4465 14:51:11.077613 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 14:51:11.084846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 14:51:11.085274 ==
4468 14:51:11.087697 [Gating] SW mode calibration
4469 14:51:11.094818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4470 14:51:11.098240 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4471 14:51:11.104741 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 14:51:11.107646 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 14:51:11.111267 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 14:51:11.117423 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4475 14:51:11.121473 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 14:51:11.124793 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 14:51:11.131193 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 14:51:11.134212 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 14:51:11.137835 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 14:51:11.144185 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 14:51:11.147842 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4482 14:51:11.151436 0 10 12 | B1->B0 | 3636 3838 | 0 0 | (1 1) (1 1)
4483 14:51:11.154124 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 14:51:11.160646 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 14:51:11.164244 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 14:51:11.167223 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 14:51:11.174242 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 14:51:11.177654 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 14:51:11.180669 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 14:51:11.187568 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4491 14:51:11.190635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 14:51:11.194070 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 14:51:11.201095 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 14:51:11.204001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 14:51:11.207659 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 14:51:11.214203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 14:51:11.217301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 14:51:11.220834 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 14:51:11.227498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 14:51:11.230698 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 14:51:11.234311 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 14:51:11.240427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 14:51:11.244149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 14:51:11.247112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 14:51:11.254011 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 14:51:11.256970 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4507 14:51:11.260704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 14:51:11.263896 Total UI for P1: 0, mck2ui 16
4509 14:51:11.266984 best dqsien dly found for B0: ( 0, 13, 12)
4510 14:51:11.270523 Total UI for P1: 0, mck2ui 16
4511 14:51:11.273657 best dqsien dly found for B1: ( 0, 13, 12)
4512 14:51:11.277457 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4513 14:51:11.280767 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4514 14:51:11.281325
4515 14:51:11.283571 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4516 14:51:11.290157 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4517 14:51:11.290575 [Gating] SW calibration Done
4518 14:51:11.293844 ==
4519 14:51:11.294263 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 14:51:11.300619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 14:51:11.301138 ==
4522 14:51:11.301475 RX Vref Scan: 0
4523 14:51:11.301787
4524 14:51:11.303603 RX Vref 0 -> 0, step: 1
4525 14:51:11.304023
4526 14:51:11.306881 RX Delay -230 -> 252, step: 16
4527 14:51:11.310602 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4528 14:51:11.314108 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4529 14:51:11.320437 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4530 14:51:11.323872 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4531 14:51:11.327067 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4532 14:51:11.330584 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4533 14:51:11.334224 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4534 14:51:11.340154 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4535 14:51:11.343930 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4536 14:51:11.346520 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4537 14:51:11.350574 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4538 14:51:11.357278 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4539 14:51:11.360068 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4540 14:51:11.363897 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4541 14:51:11.367001 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4542 14:51:11.370336 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4543 14:51:11.370986 ==
4544 14:51:11.373445 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 14:51:11.380982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 14:51:11.381406 ==
4547 14:51:11.381824 DQS Delay:
4548 14:51:11.383217 DQS0 = 0, DQS1 = 0
4549 14:51:11.383949 DQM Delay:
4550 14:51:11.386422 DQM0 = 51, DQM1 = 49
4551 14:51:11.386874 DQ Delay:
4552 14:51:11.390034 DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =41
4553 14:51:11.393543 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4554 14:51:11.396275 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4555 14:51:11.400045 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =57
4556 14:51:11.400497
4557 14:51:11.400827
4558 14:51:11.401139 ==
4559 14:51:11.403611 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 14:51:11.406354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 14:51:11.406779 ==
4562 14:51:11.407117
4563 14:51:11.407430
4564 14:51:11.410093 TX Vref Scan disable
4565 14:51:11.413010 == TX Byte 0 ==
4566 14:51:11.416458 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4567 14:51:11.419888 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4568 14:51:11.423272 == TX Byte 1 ==
4569 14:51:11.426489 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4570 14:51:11.429460 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4571 14:51:11.429876 ==
4572 14:51:11.433644 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 14:51:11.436734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 14:51:11.439692 ==
4575 14:51:11.440227
4576 14:51:11.440602
4577 14:51:11.440906 TX Vref Scan disable
4578 14:51:11.443944 == TX Byte 0 ==
4579 14:51:11.447030 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 14:51:11.453651 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 14:51:11.454153 == TX Byte 1 ==
4582 14:51:11.456938 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4583 14:51:11.464036 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4584 14:51:11.464662
4585 14:51:11.465028 [DATLAT]
4586 14:51:11.465359 Freq=600, CH1 RK0
4587 14:51:11.465682
4588 14:51:11.466769 DATLAT Default: 0x9
4589 14:51:11.470160 0, 0xFFFF, sum = 0
4590 14:51:11.470621 1, 0xFFFF, sum = 0
4591 14:51:11.473714 2, 0xFFFF, sum = 0
4592 14:51:11.474277 3, 0xFFFF, sum = 0
4593 14:51:11.476688 4, 0xFFFF, sum = 0
4594 14:51:11.477231 5, 0xFFFF, sum = 0
4595 14:51:11.480731 6, 0xFFFF, sum = 0
4596 14:51:11.481444 7, 0xFFFF, sum = 0
4597 14:51:11.483117 8, 0x0, sum = 1
4598 14:51:11.483575 9, 0x0, sum = 2
4599 14:51:11.483944 10, 0x0, sum = 3
4600 14:51:11.487187 11, 0x0, sum = 4
4601 14:51:11.487745 best_step = 9
4602 14:51:11.488107
4603 14:51:11.489918 ==
4604 14:51:11.490370 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 14:51:11.496167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 14:51:11.496776 ==
4607 14:51:11.497139 RX Vref Scan: 1
4608 14:51:11.497471
4609 14:51:11.500085 RX Vref 0 -> 0, step: 1
4610 14:51:11.500722
4611 14:51:11.503277 RX Delay -163 -> 252, step: 8
4612 14:51:11.503839
4613 14:51:11.506457 Set Vref, RX VrefLevel [Byte0]: 53
4614 14:51:11.509566 [Byte1]: 52
4615 14:51:11.510021
4616 14:51:11.513300 Final RX Vref Byte 0 = 53 to rank0
4617 14:51:11.516267 Final RX Vref Byte 1 = 52 to rank0
4618 14:51:11.519435 Final RX Vref Byte 0 = 53 to rank1
4619 14:51:11.522803 Final RX Vref Byte 1 = 52 to rank1==
4620 14:51:11.526145 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 14:51:11.529777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 14:51:11.530193 ==
4623 14:51:11.532959 DQS Delay:
4624 14:51:11.533368 DQS0 = 0, DQS1 = 0
4625 14:51:11.536044 DQM Delay:
4626 14:51:11.536497 DQM0 = 48, DQM1 = 45
4627 14:51:11.536827 DQ Delay:
4628 14:51:11.539260 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4629 14:51:11.542876 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4630 14:51:11.546395 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4631 14:51:11.549213 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4632 14:51:11.549731
4633 14:51:11.550064
4634 14:51:11.559547 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4635 14:51:11.562587 CH1 RK0: MR19=808, MR18=4C72
4636 14:51:11.569396 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4637 14:51:11.569811
4638 14:51:11.572447 ----->DramcWriteLeveling(PI) begin...
4639 14:51:11.572891 ==
4640 14:51:11.576227 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 14:51:11.579063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 14:51:11.579480 ==
4643 14:51:11.582567 Write leveling (Byte 0): 29 => 29
4644 14:51:11.586220 Write leveling (Byte 1): 30 => 30
4645 14:51:11.589444 DramcWriteLeveling(PI) end<-----
4646 14:51:11.589854
4647 14:51:11.590175 ==
4648 14:51:11.592388 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 14:51:11.596267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 14:51:11.596714 ==
4651 14:51:11.599307 [Gating] SW mode calibration
4652 14:51:11.606081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4653 14:51:11.612976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4654 14:51:11.615733 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 14:51:11.619234 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 14:51:11.626046 0 9 8 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)
4657 14:51:11.629204 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 0)
4658 14:51:11.632387 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 14:51:11.639105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 14:51:11.642481 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 14:51:11.645922 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 14:51:11.652503 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 14:51:11.655762 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 14:51:11.659099 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4665 14:51:11.665463 0 10 12 | B1->B0 | 3939 3939 | 0 1 | (0 0) (0 0)
4666 14:51:11.669017 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 14:51:11.672666 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 14:51:11.675958 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 14:51:11.682912 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 14:51:11.685700 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 14:51:11.688993 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 14:51:11.695971 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 14:51:11.698927 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 14:51:11.702352 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 14:51:11.708634 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 14:51:11.712444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 14:51:11.715644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 14:51:11.722348 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 14:51:11.726035 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 14:51:11.728653 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 14:51:11.735992 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 14:51:11.738619 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 14:51:11.741958 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 14:51:11.748683 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 14:51:11.751770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 14:51:11.755623 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 14:51:11.762227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 14:51:11.765235 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 14:51:11.768668 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4690 14:51:11.775304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 14:51:11.775869 Total UI for P1: 0, mck2ui 16
4692 14:51:11.782128 best dqsien dly found for B0: ( 0, 13, 14)
4693 14:51:11.782684 Total UI for P1: 0, mck2ui 16
4694 14:51:11.788330 best dqsien dly found for B1: ( 0, 13, 12)
4695 14:51:11.792071 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4696 14:51:11.795471 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4697 14:51:11.796026
4698 14:51:11.798920 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4699 14:51:11.801520 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4700 14:51:11.805259 [Gating] SW calibration Done
4701 14:51:11.805722 ==
4702 14:51:11.808738 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 14:51:11.812037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 14:51:11.812622 ==
4705 14:51:11.815789 RX Vref Scan: 0
4706 14:51:11.816376
4707 14:51:11.816743 RX Vref 0 -> 0, step: 1
4708 14:51:11.817081
4709 14:51:11.818448 RX Delay -230 -> 252, step: 16
4710 14:51:11.825302 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4711 14:51:11.828450 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4712 14:51:11.831827 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4713 14:51:11.835090 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4714 14:51:11.838261 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4715 14:51:11.844706 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4716 14:51:11.847990 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4717 14:51:11.851601 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4718 14:51:11.855210 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4719 14:51:11.858139 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4720 14:51:11.865183 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4721 14:51:11.868326 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4722 14:51:11.871352 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4723 14:51:11.874830 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4724 14:51:11.881706 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4725 14:51:11.884775 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4726 14:51:11.885206 ==
4727 14:51:11.888421 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 14:51:11.891888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 14:51:11.892429 ==
4730 14:51:11.894566 DQS Delay:
4731 14:51:11.895038 DQS0 = 0, DQS1 = 0
4732 14:51:11.897956 DQM Delay:
4733 14:51:11.898377 DQM0 = 50, DQM1 = 48
4734 14:51:11.898804 DQ Delay:
4735 14:51:11.901565 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4736 14:51:11.904802 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4737 14:51:11.908385 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4738 14:51:11.911159 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4739 14:51:11.911573
4740 14:51:11.911934
4741 14:51:11.912263 ==
4742 14:51:11.914837 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 14:51:11.921101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 14:51:11.921660 ==
4745 14:51:11.922026
4746 14:51:11.922359
4747 14:51:11.925114 TX Vref Scan disable
4748 14:51:11.925673 == TX Byte 0 ==
4749 14:51:11.927935 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4750 14:51:11.935207 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4751 14:51:11.935774 == TX Byte 1 ==
4752 14:51:11.937748 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4753 14:51:11.944796 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4754 14:51:11.945267 ==
4755 14:51:11.947896 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 14:51:11.951561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 14:51:11.952187 ==
4758 14:51:11.952752
4759 14:51:11.953084
4760 14:51:11.954372 TX Vref Scan disable
4761 14:51:11.957786 == TX Byte 0 ==
4762 14:51:11.961231 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 14:51:11.964291 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 14:51:11.968009 == TX Byte 1 ==
4765 14:51:11.971418 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4766 14:51:11.974536 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4767 14:51:11.974985
4768 14:51:11.977940 [DATLAT]
4769 14:51:11.978421 Freq=600, CH1 RK1
4770 14:51:11.978804
4771 14:51:11.981069 DATLAT Default: 0x9
4772 14:51:11.981505 0, 0xFFFF, sum = 0
4773 14:51:11.984719 1, 0xFFFF, sum = 0
4774 14:51:11.985149 2, 0xFFFF, sum = 0
4775 14:51:11.987523 3, 0xFFFF, sum = 0
4776 14:51:11.987945 4, 0xFFFF, sum = 0
4777 14:51:11.990775 5, 0xFFFF, sum = 0
4778 14:51:11.991195 6, 0xFFFF, sum = 0
4779 14:51:11.994217 7, 0xFFFF, sum = 0
4780 14:51:11.994636 8, 0x0, sum = 1
4781 14:51:11.997416 9, 0x0, sum = 2
4782 14:51:11.997839 10, 0x0, sum = 3
4783 14:51:12.000977 11, 0x0, sum = 4
4784 14:51:12.001397 best_step = 9
4785 14:51:12.001728
4786 14:51:12.002030 ==
4787 14:51:12.004526 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 14:51:12.007654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 14:51:12.008071 ==
4790 14:51:12.011017 RX Vref Scan: 0
4791 14:51:12.011428
4792 14:51:12.013916 RX Vref 0 -> 0, step: 1
4793 14:51:12.014329
4794 14:51:12.014654 RX Delay -163 -> 252, step: 8
4795 14:51:12.022018 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4796 14:51:12.025448 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4797 14:51:12.028946 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4798 14:51:12.031945 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4799 14:51:12.035977 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4800 14:51:12.042517 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4801 14:51:12.045778 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4802 14:51:12.048826 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4803 14:51:12.052387 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4804 14:51:12.055768 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4805 14:51:12.062106 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4806 14:51:12.065871 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4807 14:51:12.069241 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4808 14:51:12.072239 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4809 14:51:12.079066 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4810 14:51:12.082760 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4811 14:51:12.083283 ==
4812 14:51:12.085678 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 14:51:12.088699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 14:51:12.089117 ==
4815 14:51:12.089441 DQS Delay:
4816 14:51:12.092369 DQS0 = 0, DQS1 = 0
4817 14:51:12.092786 DQM Delay:
4818 14:51:12.095921 DQM0 = 49, DQM1 = 45
4819 14:51:12.096494 DQ Delay:
4820 14:51:12.099025 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4821 14:51:12.102534 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4822 14:51:12.105429 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4823 14:51:12.109140 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4824 14:51:12.109555
4825 14:51:12.109881
4826 14:51:12.118780 [DQSOSCAuto] RK1, (LSB)MR18= 0x661b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4827 14:51:12.119290 CH1 RK1: MR19=808, MR18=661B
4828 14:51:12.125882 CH1_RK1: MR19=0x808, MR18=0x661B, DQSOSC=390, MR23=63, INC=172, DEC=114
4829 14:51:12.128966 [RxdqsGatingPostProcess] freq 600
4830 14:51:12.136113 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4831 14:51:12.138539 Pre-setting of DQS Precalculation
4832 14:51:12.142909 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4833 14:51:12.148920 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4834 14:51:12.158589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4835 14:51:12.159190
4836 14:51:12.159691
4837 14:51:12.161598 [Calibration Summary] 1200 Mbps
4838 14:51:12.162017 CH 0, Rank 0
4839 14:51:12.165548 SW Impedance : PASS
4840 14:51:12.166062 DUTY Scan : NO K
4841 14:51:12.168431 ZQ Calibration : PASS
4842 14:51:12.168852 Jitter Meter : NO K
4843 14:51:12.171821 CBT Training : PASS
4844 14:51:12.174900 Write leveling : PASS
4845 14:51:12.175320 RX DQS gating : PASS
4846 14:51:12.178220 RX DQ/DQS(RDDQC) : PASS
4847 14:51:12.181692 TX DQ/DQS : PASS
4848 14:51:12.182112 RX DATLAT : PASS
4849 14:51:12.185215 RX DQ/DQS(Engine): PASS
4850 14:51:12.188181 TX OE : NO K
4851 14:51:12.188625 All Pass.
4852 14:51:12.188957
4853 14:51:12.189262 CH 0, Rank 1
4854 14:51:12.191593 SW Impedance : PASS
4855 14:51:12.195466 DUTY Scan : NO K
4856 14:51:12.195990 ZQ Calibration : PASS
4857 14:51:12.198591 Jitter Meter : NO K
4858 14:51:12.201727 CBT Training : PASS
4859 14:51:12.202246 Write leveling : PASS
4860 14:51:12.205095 RX DQS gating : PASS
4861 14:51:12.208334 RX DQ/DQS(RDDQC) : PASS
4862 14:51:12.208776 TX DQ/DQS : PASS
4863 14:51:12.212001 RX DATLAT : PASS
4864 14:51:12.212580 RX DQ/DQS(Engine): PASS
4865 14:51:12.215027 TX OE : NO K
4866 14:51:12.215547 All Pass.
4867 14:51:12.215880
4868 14:51:12.218522 CH 1, Rank 0
4869 14:51:12.218936 SW Impedance : PASS
4870 14:51:12.221310 DUTY Scan : NO K
4871 14:51:12.225260 ZQ Calibration : PASS
4872 14:51:12.225836 Jitter Meter : NO K
4873 14:51:12.228656 CBT Training : PASS
4874 14:51:12.231370 Write leveling : PASS
4875 14:51:12.231785 RX DQS gating : PASS
4876 14:51:12.235155 RX DQ/DQS(RDDQC) : PASS
4877 14:51:12.238083 TX DQ/DQS : PASS
4878 14:51:12.238568 RX DATLAT : PASS
4879 14:51:12.241946 RX DQ/DQS(Engine): PASS
4880 14:51:12.244957 TX OE : NO K
4881 14:51:12.245533 All Pass.
4882 14:51:12.245900
4883 14:51:12.246290 CH 1, Rank 1
4884 14:51:12.248649 SW Impedance : PASS
4885 14:51:12.251942 DUTY Scan : NO K
4886 14:51:12.252578 ZQ Calibration : PASS
4887 14:51:12.254841 Jitter Meter : NO K
4888 14:51:12.258221 CBT Training : PASS
4889 14:51:12.258757 Write leveling : PASS
4890 14:51:12.261708 RX DQS gating : PASS
4891 14:51:12.262124 RX DQ/DQS(RDDQC) : PASS
4892 14:51:12.264842 TX DQ/DQS : PASS
4893 14:51:12.268204 RX DATLAT : PASS
4894 14:51:12.268715 RX DQ/DQS(Engine): PASS
4895 14:51:12.271678 TX OE : NO K
4896 14:51:12.272192 All Pass.
4897 14:51:12.272582
4898 14:51:12.275136 DramC Write-DBI off
4899 14:51:12.277854 PER_BANK_REFRESH: Hybrid Mode
4900 14:51:12.278330 TX_TRACKING: ON
4901 14:51:12.288145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4902 14:51:12.291511 [FAST_K] Save calibration result to emmc
4903 14:51:12.294790 dramc_set_vcore_voltage set vcore to 662500
4904 14:51:12.298082 Read voltage for 933, 3
4905 14:51:12.298567 Vio18 = 0
4906 14:51:12.298896 Vcore = 662500
4907 14:51:12.301231 Vdram = 0
4908 14:51:12.301759 Vddq = 0
4909 14:51:12.302092 Vmddr = 0
4910 14:51:12.307979 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4911 14:51:12.311658 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4912 14:51:12.314372 MEM_TYPE=3, freq_sel=17
4913 14:51:12.317711 sv_algorithm_assistance_LP4_1600
4914 14:51:12.321331 ============ PULL DRAM RESETB DOWN ============
4915 14:51:12.327960 ========== PULL DRAM RESETB DOWN end =========
4916 14:51:12.331016 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4917 14:51:12.334921 ===================================
4918 14:51:12.337699 LPDDR4 DRAM CONFIGURATION
4919 14:51:12.341464 ===================================
4920 14:51:12.341985 EX_ROW_EN[0] = 0x0
4921 14:51:12.344503 EX_ROW_EN[1] = 0x0
4922 14:51:12.345016 LP4Y_EN = 0x0
4923 14:51:12.348212 WORK_FSP = 0x0
4924 14:51:12.348679 WL = 0x3
4925 14:51:12.351430 RL = 0x3
4926 14:51:12.351953 BL = 0x2
4927 14:51:12.354163 RPST = 0x0
4928 14:51:12.354575 RD_PRE = 0x0
4929 14:51:12.357934 WR_PRE = 0x1
4930 14:51:12.358347 WR_PST = 0x0
4931 14:51:12.361205 DBI_WR = 0x0
4932 14:51:12.364473 DBI_RD = 0x0
4933 14:51:12.364915 OTF = 0x1
4934 14:51:12.367347 ===================================
4935 14:51:12.371124 ===================================
4936 14:51:12.371646 ANA top config
4937 14:51:12.374042 ===================================
4938 14:51:12.377542 DLL_ASYNC_EN = 0
4939 14:51:12.381004 ALL_SLAVE_EN = 1
4940 14:51:12.384317 NEW_RANK_MODE = 1
4941 14:51:12.387830 DLL_IDLE_MODE = 1
4942 14:51:12.388398 LP45_APHY_COMB_EN = 1
4943 14:51:12.391290 TX_ODT_DIS = 1
4944 14:51:12.394001 NEW_8X_MODE = 1
4945 14:51:12.397763 ===================================
4946 14:51:12.400899 ===================================
4947 14:51:12.404375 data_rate = 1866
4948 14:51:12.407422 CKR = 1
4949 14:51:12.407839 DQ_P2S_RATIO = 8
4950 14:51:12.410714 ===================================
4951 14:51:12.414404 CA_P2S_RATIO = 8
4952 14:51:12.417756 DQ_CA_OPEN = 0
4953 14:51:12.420762 DQ_SEMI_OPEN = 0
4954 14:51:12.424045 CA_SEMI_OPEN = 0
4955 14:51:12.427773 CA_FULL_RATE = 0
4956 14:51:12.428383 DQ_CKDIV4_EN = 1
4957 14:51:12.430315 CA_CKDIV4_EN = 1
4958 14:51:12.434369 CA_PREDIV_EN = 0
4959 14:51:12.437400 PH8_DLY = 0
4960 14:51:12.440862 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4961 14:51:12.444225 DQ_AAMCK_DIV = 4
4962 14:51:12.444689 CA_AAMCK_DIV = 4
4963 14:51:12.447254 CA_ADMCK_DIV = 4
4964 14:51:12.450815 DQ_TRACK_CA_EN = 0
4965 14:51:12.453794 CA_PICK = 933
4966 14:51:12.457477 CA_MCKIO = 933
4967 14:51:12.460765 MCKIO_SEMI = 0
4968 14:51:12.464016 PLL_FREQ = 3732
4969 14:51:12.464480 DQ_UI_PI_RATIO = 32
4970 14:51:12.467199 CA_UI_PI_RATIO = 0
4971 14:51:12.470841 ===================================
4972 14:51:12.473979 ===================================
4973 14:51:12.477681 memory_type:LPDDR4
4974 14:51:12.480460 GP_NUM : 10
4975 14:51:12.480875 SRAM_EN : 1
4976 14:51:12.484021 MD32_EN : 0
4977 14:51:12.487799 ===================================
4978 14:51:12.488209 [ANA_INIT] >>>>>>>>>>>>>>
4979 14:51:12.490637 <<<<<< [CONFIGURE PHASE]: ANA_TX
4980 14:51:12.493753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4981 14:51:12.497497 ===================================
4982 14:51:12.501012 data_rate = 1866,PCW = 0X8f00
4983 14:51:12.503915 ===================================
4984 14:51:12.507335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4985 14:51:12.514180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 14:51:12.516914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 14:51:12.523998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4988 14:51:12.527538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4989 14:51:12.530623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4990 14:51:12.533753 [ANA_INIT] flow start
4991 14:51:12.534230 [ANA_INIT] PLL >>>>>>>>
4992 14:51:12.537208 [ANA_INIT] PLL <<<<<<<<
4993 14:51:12.540224 [ANA_INIT] MIDPI >>>>>>>>
4994 14:51:12.540670 [ANA_INIT] MIDPI <<<<<<<<
4995 14:51:12.543846 [ANA_INIT] DLL >>>>>>>>
4996 14:51:12.546632 [ANA_INIT] flow end
4997 14:51:12.550128 ============ LP4 DIFF to SE enter ============
4998 14:51:12.553666 ============ LP4 DIFF to SE exit ============
4999 14:51:12.556862 [ANA_INIT] <<<<<<<<<<<<<
5000 14:51:12.560601 [Flow] Enable top DCM control >>>>>
5001 14:51:12.563683 [Flow] Enable top DCM control <<<<<
5002 14:51:12.567756 Enable DLL master slave shuffle
5003 14:51:12.570459 ==============================================================
5004 14:51:12.573833 Gating Mode config
5005 14:51:12.580218 ==============================================================
5006 14:51:12.580774 Config description:
5007 14:51:12.589933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5008 14:51:12.597029 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5009 14:51:12.600005 SELPH_MODE 0: By rank 1: By Phase
5010 14:51:12.606708 ==============================================================
5011 14:51:12.610357 GAT_TRACK_EN = 1
5012 14:51:12.613973 RX_GATING_MODE = 2
5013 14:51:12.616931 RX_GATING_TRACK_MODE = 2
5014 14:51:12.620043 SELPH_MODE = 1
5015 14:51:12.623391 PICG_EARLY_EN = 1
5016 14:51:12.626768 VALID_LAT_VALUE = 1
5017 14:51:12.630074 ==============================================================
5018 14:51:12.633203 Enter into Gating configuration >>>>
5019 14:51:12.636609 Exit from Gating configuration <<<<
5020 14:51:12.640145 Enter into DVFS_PRE_config >>>>>
5021 14:51:12.653229 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5022 14:51:12.653777 Exit from DVFS_PRE_config <<<<<
5023 14:51:12.656690 Enter into PICG configuration >>>>
5024 14:51:12.660070 Exit from PICG configuration <<<<
5025 14:51:12.663739 [RX_INPUT] configuration >>>>>
5026 14:51:12.667360 [RX_INPUT] configuration <<<<<
5027 14:51:12.673502 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5028 14:51:12.676723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5029 14:51:12.683669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 14:51:12.689538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 14:51:12.696290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 14:51:12.702983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 14:51:12.706323 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5034 14:51:12.709910 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5035 14:51:12.712946 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5036 14:51:12.719848 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5037 14:51:12.722908 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5038 14:51:12.726597 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 14:51:12.729506 ===================================
5040 14:51:12.733319 LPDDR4 DRAM CONFIGURATION
5041 14:51:12.736320 ===================================
5042 14:51:12.736765 EX_ROW_EN[0] = 0x0
5043 14:51:12.740025 EX_ROW_EN[1] = 0x0
5044 14:51:12.743152 LP4Y_EN = 0x0
5045 14:51:12.743665 WORK_FSP = 0x0
5046 14:51:12.746027 WL = 0x3
5047 14:51:12.746441 RL = 0x3
5048 14:51:12.749449 BL = 0x2
5049 14:51:12.749879 RPST = 0x0
5050 14:51:12.753663 RD_PRE = 0x0
5051 14:51:12.754173 WR_PRE = 0x1
5052 14:51:12.756236 WR_PST = 0x0
5053 14:51:12.756728 DBI_WR = 0x0
5054 14:51:12.759755 DBI_RD = 0x0
5055 14:51:12.760169 OTF = 0x1
5056 14:51:12.762949 ===================================
5057 14:51:12.765959 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5058 14:51:12.772535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5059 14:51:12.776397 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 14:51:12.779855 ===================================
5061 14:51:12.782976 LPDDR4 DRAM CONFIGURATION
5062 14:51:12.786177 ===================================
5063 14:51:12.786594 EX_ROW_EN[0] = 0x10
5064 14:51:12.789293 EX_ROW_EN[1] = 0x0
5065 14:51:12.789710 LP4Y_EN = 0x0
5066 14:51:12.793071 WORK_FSP = 0x0
5067 14:51:12.793484 WL = 0x3
5068 14:51:12.795921 RL = 0x3
5069 14:51:12.796215 BL = 0x2
5070 14:51:12.799461 RPST = 0x0
5071 14:51:12.802760 RD_PRE = 0x0
5072 14:51:12.802984 WR_PRE = 0x1
5073 14:51:12.806299 WR_PST = 0x0
5074 14:51:12.806480 DBI_WR = 0x0
5075 14:51:12.809454 DBI_RD = 0x0
5076 14:51:12.809631 OTF = 0x1
5077 14:51:12.812842 ===================================
5078 14:51:12.819416 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5079 14:51:12.823051 nWR fixed to 30
5080 14:51:12.826507 [ModeRegInit_LP4] CH0 RK0
5081 14:51:12.826611 [ModeRegInit_LP4] CH0 RK1
5082 14:51:12.829271 [ModeRegInit_LP4] CH1 RK0
5083 14:51:12.832943 [ModeRegInit_LP4] CH1 RK1
5084 14:51:12.833035 match AC timing 9
5085 14:51:12.839556 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5086 14:51:12.842954 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5087 14:51:12.846442 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5088 14:51:12.852875 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5089 14:51:12.856520 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5090 14:51:12.856613 ==
5091 14:51:12.859428 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 14:51:12.862540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 14:51:12.862648 ==
5094 14:51:12.869481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 14:51:12.875634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5096 14:51:12.879170 [CA 0] Center 37 (6~68) winsize 63
5097 14:51:12.882556 [CA 1] Center 37 (7~68) winsize 62
5098 14:51:12.885948 [CA 2] Center 34 (4~65) winsize 62
5099 14:51:12.889142 [CA 3] Center 34 (3~65) winsize 63
5100 14:51:12.892217 [CA 4] Center 33 (2~64) winsize 63
5101 14:51:12.896217 [CA 5] Center 32 (2~62) winsize 61
5102 14:51:12.896336
5103 14:51:12.899139 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5104 14:51:12.899220
5105 14:51:12.902319 [CATrainingPosCal] consider 1 rank data
5106 14:51:12.906093 u2DelayCellTimex100 = 270/100 ps
5107 14:51:12.908882 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5108 14:51:12.912225 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5109 14:51:12.915792 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5110 14:51:12.918763 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5111 14:51:12.921922 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5112 14:51:12.929151 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5113 14:51:12.929246
5114 14:51:12.932641 CA PerBit enable=1, Macro0, CA PI delay=32
5115 14:51:12.932724
5116 14:51:12.935533 [CBTSetCACLKResult] CA Dly = 32
5117 14:51:12.935635 CS Dly: 5 (0~36)
5118 14:51:12.935701 ==
5119 14:51:12.938775 Dram Type= 6, Freq= 0, CH_0, rank 1
5120 14:51:12.942447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 14:51:12.945541 ==
5122 14:51:12.949166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5123 14:51:12.955635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5124 14:51:12.958742 [CA 0] Center 37 (7~68) winsize 62
5125 14:51:12.962388 [CA 1] Center 37 (6~68) winsize 63
5126 14:51:12.965733 [CA 2] Center 34 (4~65) winsize 62
5127 14:51:12.968941 [CA 3] Center 34 (3~65) winsize 63
5128 14:51:12.971850 [CA 4] Center 33 (3~63) winsize 61
5129 14:51:12.975759 [CA 5] Center 32 (2~62) winsize 61
5130 14:51:12.975849
5131 14:51:12.978411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5132 14:51:12.978495
5133 14:51:12.982160 [CATrainingPosCal] consider 2 rank data
5134 14:51:12.985192 u2DelayCellTimex100 = 270/100 ps
5135 14:51:12.988538 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5136 14:51:12.992095 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5137 14:51:12.995163 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5138 14:51:12.999005 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5139 14:51:13.005050 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5140 14:51:13.008346 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5141 14:51:13.008460
5142 14:51:13.012169 CA PerBit enable=1, Macro0, CA PI delay=32
5143 14:51:13.012250
5144 14:51:13.015522 [CBTSetCACLKResult] CA Dly = 32
5145 14:51:13.015683 CS Dly: 5 (0~37)
5146 14:51:13.015755
5147 14:51:13.018713 ----->DramcWriteLeveling(PI) begin...
5148 14:51:13.018874 ==
5149 14:51:13.022016 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 14:51:13.028627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 14:51:13.028787 ==
5152 14:51:13.032027 Write leveling (Byte 0): 30 => 30
5153 14:51:13.035217 Write leveling (Byte 1): 28 => 28
5154 14:51:13.035367 DramcWriteLeveling(PI) end<-----
5155 14:51:13.035442
5156 14:51:13.038347 ==
5157 14:51:13.042441 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 14:51:13.045314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 14:51:13.045486 ==
5160 14:51:13.048490 [Gating] SW mode calibration
5161 14:51:13.055264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5162 14:51:13.058859 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5163 14:51:13.065727 0 14 0 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
5164 14:51:13.068686 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 14:51:13.071894 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 14:51:13.078465 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 14:51:13.082595 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 14:51:13.085188 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 14:51:13.091796 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 14:51:13.095624 0 14 28 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5171 14:51:13.098363 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
5172 14:51:13.105283 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 14:51:13.108513 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 14:51:13.111816 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 14:51:13.118634 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 14:51:13.121745 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 14:51:13.125440 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5178 14:51:13.132408 0 15 28 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
5179 14:51:13.135092 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5180 14:51:13.138183 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 14:51:13.144792 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 14:51:13.148662 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 14:51:13.152091 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 14:51:13.158292 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 14:51:13.161600 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5186 14:51:13.165281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 14:51:13.168807 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5188 14:51:13.175229 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 14:51:13.178300 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 14:51:13.182168 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 14:51:13.188737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 14:51:13.192029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 14:51:13.195880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 14:51:13.201923 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 14:51:13.204805 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 14:51:13.208558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 14:51:13.215271 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 14:51:13.218104 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 14:51:13.221504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 14:51:13.228495 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 14:51:13.231931 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5202 14:51:13.234831 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5203 14:51:13.238140 Total UI for P1: 0, mck2ui 16
5204 14:51:13.241992 best dqsien dly found for B0: ( 1, 2, 24)
5205 14:51:13.248442 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5206 14:51:13.251145 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 14:51:13.255081 Total UI for P1: 0, mck2ui 16
5208 14:51:13.258051 best dqsien dly found for B1: ( 1, 2, 30)
5209 14:51:13.261548 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5210 14:51:13.264622 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5211 14:51:13.265223
5212 14:51:13.268271 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5213 14:51:13.271358 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5214 14:51:13.274924 [Gating] SW calibration Done
5215 14:51:13.275476 ==
5216 14:51:13.277928 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 14:51:13.280962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 14:51:13.284807 ==
5219 14:51:13.285268 RX Vref Scan: 0
5220 14:51:13.285626
5221 14:51:13.287844 RX Vref 0 -> 0, step: 1
5222 14:51:13.288304
5223 14:51:13.288703 RX Delay -80 -> 252, step: 8
5224 14:51:13.295080 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5225 14:51:13.298384 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5226 14:51:13.301109 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5227 14:51:13.304772 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5228 14:51:13.307892 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5229 14:51:13.314324 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5230 14:51:13.318525 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5231 14:51:13.321277 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5232 14:51:13.324672 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5233 14:51:13.328200 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5234 14:51:13.331220 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5235 14:51:13.337973 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5236 14:51:13.341522 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5237 14:51:13.344584 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5238 14:51:13.348281 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5239 14:51:13.351269 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5240 14:51:13.351722 ==
5241 14:51:13.355148 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 14:51:13.361228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 14:51:13.361690 ==
5244 14:51:13.362053 DQS Delay:
5245 14:51:13.364749 DQS0 = 0, DQS1 = 0
5246 14:51:13.365208 DQM Delay:
5247 14:51:13.368290 DQM0 = 105, DQM1 = 95
5248 14:51:13.368881 DQ Delay:
5249 14:51:13.371473 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5250 14:51:13.374677 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5251 14:51:13.377806 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5252 14:51:13.381292 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5253 14:51:13.381672
5254 14:51:13.382013
5255 14:51:13.382323 ==
5256 14:51:13.384517 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 14:51:13.388551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 14:51:13.389065 ==
5259 14:51:13.389399
5260 14:51:13.391806
5261 14:51:13.392334 TX Vref Scan disable
5262 14:51:13.394535 == TX Byte 0 ==
5263 14:51:13.398552 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5264 14:51:13.401104 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5265 14:51:13.405316 == TX Byte 1 ==
5266 14:51:13.408401 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5267 14:51:13.411553 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5268 14:51:13.412074 ==
5269 14:51:13.415003 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 14:51:13.421568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 14:51:13.422070 ==
5272 14:51:13.422401
5273 14:51:13.422705
5274 14:51:13.422995 TX Vref Scan disable
5275 14:51:13.424877 == TX Byte 0 ==
5276 14:51:13.428885 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5277 14:51:13.435392 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5278 14:51:13.436104 == TX Byte 1 ==
5279 14:51:13.438586 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5280 14:51:13.444969 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5281 14:51:13.445687
5282 14:51:13.446330 [DATLAT]
5283 14:51:13.446915 Freq=933, CH0 RK0
5284 14:51:13.447430
5285 14:51:13.448426 DATLAT Default: 0xd
5286 14:51:13.448993 0, 0xFFFF, sum = 0
5287 14:51:13.452071 1, 0xFFFF, sum = 0
5288 14:51:13.452632 2, 0xFFFF, sum = 0
5289 14:51:13.455142 3, 0xFFFF, sum = 0
5290 14:51:13.458160 4, 0xFFFF, sum = 0
5291 14:51:13.458887 5, 0xFFFF, sum = 0
5292 14:51:13.461472 6, 0xFFFF, sum = 0
5293 14:51:13.462015 7, 0xFFFF, sum = 0
5294 14:51:13.465469 8, 0xFFFF, sum = 0
5295 14:51:13.466134 9, 0xFFFF, sum = 0
5296 14:51:13.468025 10, 0x0, sum = 1
5297 14:51:13.468622 11, 0x0, sum = 2
5298 14:51:13.471565 12, 0x0, sum = 3
5299 14:51:13.472135 13, 0x0, sum = 4
5300 14:51:13.472695 best_step = 11
5301 14:51:13.473279
5302 14:51:13.474753 ==
5303 14:51:13.478121 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 14:51:13.481504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 14:51:13.481921 ==
5306 14:51:13.482247 RX Vref Scan: 1
5307 14:51:13.482547
5308 14:51:13.484776 RX Vref 0 -> 0, step: 1
5309 14:51:13.485325
5310 14:51:13.488325 RX Delay -53 -> 252, step: 4
5311 14:51:13.488883
5312 14:51:13.491530 Set Vref, RX VrefLevel [Byte0]: 56
5313 14:51:13.494536 [Byte1]: 47
5314 14:51:13.494908
5315 14:51:13.498607 Final RX Vref Byte 0 = 56 to rank0
5316 14:51:13.501663 Final RX Vref Byte 1 = 47 to rank0
5317 14:51:13.504991 Final RX Vref Byte 0 = 56 to rank1
5318 14:51:13.508417 Final RX Vref Byte 1 = 47 to rank1==
5319 14:51:13.511258 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 14:51:13.515149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 14:51:13.518213 ==
5322 14:51:13.518632 DQS Delay:
5323 14:51:13.518893 DQS0 = 0, DQS1 = 0
5324 14:51:13.521353 DQM Delay:
5325 14:51:13.521676 DQM0 = 104, DQM1 = 95
5326 14:51:13.524984 DQ Delay:
5327 14:51:13.528029 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5328 14:51:13.531569 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =110
5329 14:51:13.535118 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =90
5330 14:51:13.538233 DQ12 =100, DQ13 =98, DQ14 =108, DQ15 =102
5331 14:51:13.538562
5332 14:51:13.538817
5333 14:51:13.544563 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5334 14:51:13.548158 CH0 RK0: MR19=505, MR18=2D25
5335 14:51:13.554708 CH0_RK0: MR19=0x505, MR18=0x2D25, DQSOSC=407, MR23=63, INC=65, DEC=43
5336 14:51:13.555149
5337 14:51:13.557706 ----->DramcWriteLeveling(PI) begin...
5338 14:51:13.558136 ==
5339 14:51:13.561342 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 14:51:13.564555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 14:51:13.564968 ==
5342 14:51:13.568245 Write leveling (Byte 0): 34 => 34
5343 14:51:13.571236 Write leveling (Byte 1): 30 => 30
5344 14:51:13.574452 DramcWriteLeveling(PI) end<-----
5345 14:51:13.574863
5346 14:51:13.575183 ==
5347 14:51:13.578184 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 14:51:13.580948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 14:51:13.581364 ==
5350 14:51:13.584488 [Gating] SW mode calibration
5351 14:51:13.591462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 14:51:13.598400 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5353 14:51:13.600932 0 14 0 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
5354 14:51:13.607931 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 14:51:13.611407 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 14:51:13.614349 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 14:51:13.621278 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 14:51:13.624119 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 14:51:13.627652 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 14:51:13.634360 0 14 28 | B1->B0 | 2626 2929 | 0 1 | (0 0) (1 0)
5361 14:51:13.637230 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5362 14:51:13.640653 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 14:51:13.647816 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 14:51:13.650875 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 14:51:13.654026 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 14:51:13.657994 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 14:51:13.664544 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5368 14:51:13.667550 0 15 28 | B1->B0 | 3d3d 3c3c | 0 0 | (0 0) (0 0)
5369 14:51:13.670965 1 0 0 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
5370 14:51:13.677689 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 14:51:13.681155 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 14:51:13.684369 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 14:51:13.691062 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 14:51:13.694244 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 14:51:13.697195 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 14:51:13.704680 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 14:51:13.708014 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 14:51:13.710847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 14:51:13.717400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 14:51:13.720997 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 14:51:13.724404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 14:51:13.730640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 14:51:13.734496 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 14:51:13.737582 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 14:51:13.744447 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 14:51:13.747497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 14:51:13.750473 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 14:51:13.757721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 14:51:13.760705 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 14:51:13.764304 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 14:51:13.767353 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 14:51:13.774065 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5393 14:51:13.777608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5394 14:51:13.780680 Total UI for P1: 0, mck2ui 16
5395 14:51:13.784291 best dqsien dly found for B1: ( 1, 2, 28)
5396 14:51:13.787695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 14:51:13.790777 Total UI for P1: 0, mck2ui 16
5398 14:51:13.794183 best dqsien dly found for B0: ( 1, 2, 30)
5399 14:51:13.797451 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5400 14:51:13.803907 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5401 14:51:13.804492
5402 14:51:13.807565 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5403 14:51:13.810352 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5404 14:51:13.813574 [Gating] SW calibration Done
5405 14:51:13.814127 ==
5406 14:51:13.817059 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 14:51:13.820235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 14:51:13.820677 ==
5409 14:51:13.821004 RX Vref Scan: 0
5410 14:51:13.823476
5411 14:51:13.823948 RX Vref 0 -> 0, step: 1
5412 14:51:13.824283
5413 14:51:13.827215 RX Delay -80 -> 252, step: 8
5414 14:51:13.830694 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5415 14:51:13.833572 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5416 14:51:13.840356 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5417 14:51:13.844519 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5418 14:51:13.847713 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5419 14:51:13.850692 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5420 14:51:13.853386 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5421 14:51:13.860554 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5422 14:51:13.864372 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5423 14:51:13.867362 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5424 14:51:13.870763 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5425 14:51:13.873938 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5426 14:51:13.876818 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5427 14:51:13.880499 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5428 14:51:13.887334 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5429 14:51:13.890087 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5430 14:51:13.890646 ==
5431 14:51:13.893724 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 14:51:13.897048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 14:51:13.897512 ==
5434 14:51:13.900207 DQS Delay:
5435 14:51:13.900689 DQS0 = 0, DQS1 = 0
5436 14:51:13.901050 DQM Delay:
5437 14:51:13.903343 DQM0 = 105, DQM1 = 93
5438 14:51:13.903819 DQ Delay:
5439 14:51:13.907327 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5440 14:51:13.909938 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5441 14:51:13.913511 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5442 14:51:13.920596 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5443 14:51:13.921156
5444 14:51:13.921535
5445 14:51:13.921916 ==
5446 14:51:13.922956 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 14:51:13.926464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 14:51:13.926926 ==
5449 14:51:13.927289
5450 14:51:13.927619
5451 14:51:13.929900 TX Vref Scan disable
5452 14:51:13.930370 == TX Byte 0 ==
5453 14:51:13.936307 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5454 14:51:13.940251 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5455 14:51:13.940722 == TX Byte 1 ==
5456 14:51:13.946698 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5457 14:51:13.950007 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5458 14:51:13.950445 ==
5459 14:51:13.953655 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 14:51:13.956395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 14:51:13.956887 ==
5462 14:51:13.957333
5463 14:51:13.957653
5464 14:51:13.959929 TX Vref Scan disable
5465 14:51:13.963221 == TX Byte 0 ==
5466 14:51:13.966430 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5467 14:51:13.969443 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5468 14:51:13.973263 == TX Byte 1 ==
5469 14:51:13.976430 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5470 14:51:13.980079 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5471 14:51:13.980658
5472 14:51:13.983118 [DATLAT]
5473 14:51:13.983594 Freq=933, CH0 RK1
5474 14:51:13.983935
5475 14:51:13.987052 DATLAT Default: 0xb
5476 14:51:13.987570 0, 0xFFFF, sum = 0
5477 14:51:13.989659 1, 0xFFFF, sum = 0
5478 14:51:13.990085 2, 0xFFFF, sum = 0
5479 14:51:13.993130 3, 0xFFFF, sum = 0
5480 14:51:13.993552 4, 0xFFFF, sum = 0
5481 14:51:13.996150 5, 0xFFFF, sum = 0
5482 14:51:13.996608 6, 0xFFFF, sum = 0
5483 14:51:14.000040 7, 0xFFFF, sum = 0
5484 14:51:14.000614 8, 0xFFFF, sum = 0
5485 14:51:14.002982 9, 0xFFFF, sum = 0
5486 14:51:14.003502 10, 0x0, sum = 1
5487 14:51:14.006556 11, 0x0, sum = 2
5488 14:51:14.007073 12, 0x0, sum = 3
5489 14:51:14.009433 13, 0x0, sum = 4
5490 14:51:14.009896 best_step = 11
5491 14:51:14.010267
5492 14:51:14.010572 ==
5493 14:51:14.012872 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 14:51:14.019688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 14:51:14.020227 ==
5496 14:51:14.020693 RX Vref Scan: 0
5497 14:51:14.021083
5498 14:51:14.022969 RX Vref 0 -> 0, step: 1
5499 14:51:14.023438
5500 14:51:14.026265 RX Delay -53 -> 252, step: 4
5501 14:51:14.029264 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5502 14:51:14.036094 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5503 14:51:14.039545 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5504 14:51:14.042395 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5505 14:51:14.045850 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5506 14:51:14.049219 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5507 14:51:14.052807 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5508 14:51:14.059516 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5509 14:51:14.062870 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5510 14:51:14.066299 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5511 14:51:14.069311 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5512 14:51:14.072835 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5513 14:51:14.079178 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5514 14:51:14.082886 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5515 14:51:14.086202 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5516 14:51:14.089320 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5517 14:51:14.089800 ==
5518 14:51:14.092473 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 14:51:14.099238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 14:51:14.099663 ==
5521 14:51:14.099995 DQS Delay:
5522 14:51:14.100307 DQS0 = 0, DQS1 = 0
5523 14:51:14.102783 DQM Delay:
5524 14:51:14.103304 DQM0 = 104, DQM1 = 94
5525 14:51:14.106281 DQ Delay:
5526 14:51:14.109112 DQ0 =100, DQ1 =104, DQ2 =102, DQ3 =100
5527 14:51:14.112582 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5528 14:51:14.115430 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =86
5529 14:51:14.119222 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5530 14:51:14.119775
5531 14:51:14.120143
5532 14:51:14.125799 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5533 14:51:14.129386 CH0 RK1: MR19=505, MR18=2A03
5534 14:51:14.136148 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5535 14:51:14.139152 [RxdqsGatingPostProcess] freq 933
5536 14:51:14.146097 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5537 14:51:14.146653 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 14:51:14.148992 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 14:51:14.152541 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 14:51:14.155980 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 14:51:14.159046 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 14:51:14.162268 best DQS1 dly(2T, 0.5T) = (0, 10)
5543 14:51:14.165874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 14:51:14.168596 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5545 14:51:14.172307 Pre-setting of DQS Precalculation
5546 14:51:14.178792 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5547 14:51:14.179395 ==
5548 14:51:14.182102 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 14:51:14.185533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 14:51:14.186047 ==
5551 14:51:14.192454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 14:51:14.195551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5553 14:51:14.199589 [CA 0] Center 36 (6~67) winsize 62
5554 14:51:14.202906 [CA 1] Center 37 (6~68) winsize 63
5555 14:51:14.206211 [CA 2] Center 34 (4~65) winsize 62
5556 14:51:14.209193 [CA 3] Center 34 (4~65) winsize 62
5557 14:51:14.212555 [CA 4] Center 34 (4~65) winsize 62
5558 14:51:14.216239 [CA 5] Center 33 (3~64) winsize 62
5559 14:51:14.216741
5560 14:51:14.219804 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5561 14:51:14.220385
5562 14:51:14.222611 [CATrainingPosCal] consider 1 rank data
5563 14:51:14.226294 u2DelayCellTimex100 = 270/100 ps
5564 14:51:14.229580 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 14:51:14.235609 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5566 14:51:14.238920 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 14:51:14.242889 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 14:51:14.246197 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 14:51:14.248938 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 14:51:14.249359
5571 14:51:14.252651 CA PerBit enable=1, Macro0, CA PI delay=33
5572 14:51:14.253072
5573 14:51:14.255558 [CBTSetCACLKResult] CA Dly = 33
5574 14:51:14.255972 CS Dly: 6 (0~37)
5575 14:51:14.259247 ==
5576 14:51:14.262156 Dram Type= 6, Freq= 0, CH_1, rank 1
5577 14:51:14.266135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 14:51:14.266646 ==
5579 14:51:14.269164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 14:51:14.275646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5581 14:51:14.279682 [CA 0] Center 36 (6~67) winsize 62
5582 14:51:14.282962 [CA 1] Center 37 (7~68) winsize 62
5583 14:51:14.286547 [CA 2] Center 35 (5~66) winsize 62
5584 14:51:14.289293 [CA 3] Center 34 (4~65) winsize 62
5585 14:51:14.292517 [CA 4] Center 34 (4~65) winsize 62
5586 14:51:14.295816 [CA 5] Center 34 (4~64) winsize 61
5587 14:51:14.296540
5588 14:51:14.299430 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5589 14:51:14.299888
5590 14:51:14.302587 [CATrainingPosCal] consider 2 rank data
5591 14:51:14.306565 u2DelayCellTimex100 = 270/100 ps
5592 14:51:14.309369 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5593 14:51:14.316083 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5594 14:51:14.319335 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5595 14:51:14.322676 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5596 14:51:14.325904 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5597 14:51:14.328953 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5598 14:51:14.329414
5599 14:51:14.333048 CA PerBit enable=1, Macro0, CA PI delay=34
5600 14:51:14.333603
5601 14:51:14.336184 [CBTSetCACLKResult] CA Dly = 34
5602 14:51:14.336783 CS Dly: 7 (0~40)
5603 14:51:14.339423
5604 14:51:14.342366 ----->DramcWriteLeveling(PI) begin...
5605 14:51:14.342862 ==
5606 14:51:14.345694 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 14:51:14.349331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 14:51:14.349867 ==
5609 14:51:14.352227 Write leveling (Byte 0): 24 => 24
5610 14:51:14.355615 Write leveling (Byte 1): 28 => 28
5611 14:51:14.358815 DramcWriteLeveling(PI) end<-----
5612 14:51:14.359444
5613 14:51:14.359790 ==
5614 14:51:14.362094 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 14:51:14.365474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 14:51:14.365895 ==
5617 14:51:14.368849 [Gating] SW mode calibration
5618 14:51:14.375827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5619 14:51:14.381777 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5620 14:51:14.384938 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 14:51:14.388410 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 14:51:14.395313 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 14:51:14.398554 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 14:51:14.402091 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 14:51:14.408364 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 14:51:14.411749 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5627 14:51:14.414731 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5628 14:51:14.418625 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 14:51:14.424835 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 14:51:14.428359 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 14:51:14.431876 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 14:51:14.438080 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 14:51:14.441854 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 14:51:14.445321 0 15 24 | B1->B0 | 2929 2e2e | 0 1 | (0 0) (0 0)
5635 14:51:14.451573 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5636 14:51:14.454652 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 14:51:14.458377 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 14:51:14.465155 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 14:51:14.468086 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 14:51:14.471826 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 14:51:14.478242 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5642 14:51:14.481948 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 14:51:14.484918 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5644 14:51:14.491385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 14:51:14.494578 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 14:51:14.498117 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 14:51:14.504474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 14:51:14.507732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 14:51:14.511178 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 14:51:14.517973 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 14:51:14.521293 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 14:51:14.524024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 14:51:14.530943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 14:51:14.534138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 14:51:14.537901 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 14:51:14.544548 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 14:51:14.547724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 14:51:14.550991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5659 14:51:14.557864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5660 14:51:14.561160 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 14:51:14.564269 Total UI for P1: 0, mck2ui 16
5662 14:51:14.567309 best dqsien dly found for B0: ( 1, 2, 28)
5663 14:51:14.570996 Total UI for P1: 0, mck2ui 16
5664 14:51:14.573930 best dqsien dly found for B1: ( 1, 2, 26)
5665 14:51:14.577676 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5666 14:51:14.580766 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5667 14:51:14.580848
5668 14:51:14.583993 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5669 14:51:14.587680 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5670 14:51:14.591016 [Gating] SW calibration Done
5671 14:51:14.591098 ==
5672 14:51:14.593888 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 14:51:14.597774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 14:51:14.597856 ==
5675 14:51:14.600849 RX Vref Scan: 0
5676 14:51:14.600930
5677 14:51:14.603978 RX Vref 0 -> 0, step: 1
5678 14:51:14.604058
5679 14:51:14.604121 RX Delay -80 -> 252, step: 8
5680 14:51:14.611068 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5681 14:51:14.614388 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5682 14:51:14.617545 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5683 14:51:14.621052 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5684 14:51:14.623895 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5685 14:51:14.627534 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5686 14:51:14.633810 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5687 14:51:14.637543 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5688 14:51:14.640812 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5689 14:51:14.644177 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5690 14:51:14.647385 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5691 14:51:14.650505 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5692 14:51:14.657685 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5693 14:51:14.661270 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5694 14:51:14.664170 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5695 14:51:14.667858 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5696 14:51:14.667962 ==
5697 14:51:14.670986 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 14:51:14.673876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 14:51:14.677329 ==
5700 14:51:14.677429 DQS Delay:
5701 14:51:14.677535 DQS0 = 0, DQS1 = 0
5702 14:51:14.680829 DQM Delay:
5703 14:51:14.680928 DQM0 = 102, DQM1 = 99
5704 14:51:14.683881 DQ Delay:
5705 14:51:14.687186 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5706 14:51:14.690827 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5707 14:51:14.693701 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5708 14:51:14.697005 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5709 14:51:14.697118
5710 14:51:14.697204
5711 14:51:14.697289 ==
5712 14:51:14.700703 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 14:51:14.703956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 14:51:14.704053 ==
5715 14:51:14.704152
5716 14:51:14.704235
5717 14:51:14.707498 TX Vref Scan disable
5718 14:51:14.710713 == TX Byte 0 ==
5719 14:51:14.713770 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5720 14:51:14.717404 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5721 14:51:14.720497 == TX Byte 1 ==
5722 14:51:14.723306 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5723 14:51:14.726940 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5724 14:51:14.727070 ==
5725 14:51:14.730401 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 14:51:14.736563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 14:51:14.736651 ==
5728 14:51:14.736715
5729 14:51:14.736799
5730 14:51:14.736871 TX Vref Scan disable
5731 14:51:14.740857 == TX Byte 0 ==
5732 14:51:14.743889 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5733 14:51:14.750575 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5734 14:51:14.750662 == TX Byte 1 ==
5735 14:51:14.754016 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5736 14:51:14.760975 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5737 14:51:14.761114
5738 14:51:14.761194 [DATLAT]
5739 14:51:14.761316 Freq=933, CH1 RK0
5740 14:51:14.761406
5741 14:51:14.763918 DATLAT Default: 0xd
5742 14:51:14.764004 0, 0xFFFF, sum = 0
5743 14:51:14.767337 1, 0xFFFF, sum = 0
5744 14:51:14.767445 2, 0xFFFF, sum = 0
5745 14:51:14.770474 3, 0xFFFF, sum = 0
5746 14:51:14.774035 4, 0xFFFF, sum = 0
5747 14:51:14.774118 5, 0xFFFF, sum = 0
5748 14:51:14.777435 6, 0xFFFF, sum = 0
5749 14:51:14.777518 7, 0xFFFF, sum = 0
5750 14:51:14.780717 8, 0xFFFF, sum = 0
5751 14:51:14.780801 9, 0xFFFF, sum = 0
5752 14:51:14.784183 10, 0x0, sum = 1
5753 14:51:14.784266 11, 0x0, sum = 2
5754 14:51:14.787189 12, 0x0, sum = 3
5755 14:51:14.787271 13, 0x0, sum = 4
5756 14:51:14.787337 best_step = 11
5757 14:51:14.787397
5758 14:51:14.790758 ==
5759 14:51:14.793619 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 14:51:14.797374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 14:51:14.797457 ==
5762 14:51:14.797531 RX Vref Scan: 1
5763 14:51:14.797595
5764 14:51:14.800351 RX Vref 0 -> 0, step: 1
5765 14:51:14.800458
5766 14:51:14.804041 RX Delay -45 -> 252, step: 4
5767 14:51:14.804155
5768 14:51:14.806930 Set Vref, RX VrefLevel [Byte0]: 53
5769 14:51:14.810632 [Byte1]: 52
5770 14:51:14.810713
5771 14:51:14.813746 Final RX Vref Byte 0 = 53 to rank0
5772 14:51:14.817009 Final RX Vref Byte 1 = 52 to rank0
5773 14:51:14.820763 Final RX Vref Byte 0 = 53 to rank1
5774 14:51:14.823724 Final RX Vref Byte 1 = 52 to rank1==
5775 14:51:14.826906 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 14:51:14.830603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 14:51:14.830686 ==
5778 14:51:14.833668 DQS Delay:
5779 14:51:14.833750 DQS0 = 0, DQS1 = 0
5780 14:51:14.837033 DQM Delay:
5781 14:51:14.837116 DQM0 = 102, DQM1 = 99
5782 14:51:14.837182 DQ Delay:
5783 14:51:14.840844 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5784 14:51:14.843815 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5785 14:51:14.846935 DQ8 =88, DQ9 =92, DQ10 =100, DQ11 =94
5786 14:51:14.853555 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5787 14:51:14.853637
5788 14:51:14.853701
5789 14:51:14.860309 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5790 14:51:14.863583 CH1 RK0: MR19=505, MR18=152D
5791 14:51:14.870562 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5792 14:51:14.870675
5793 14:51:14.873915 ----->DramcWriteLeveling(PI) begin...
5794 14:51:14.874023 ==
5795 14:51:14.877134 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 14:51:14.880056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 14:51:14.880139 ==
5798 14:51:14.883518 Write leveling (Byte 0): 27 => 27
5799 14:51:14.886741 Write leveling (Byte 1): 28 => 28
5800 14:51:14.890256 DramcWriteLeveling(PI) end<-----
5801 14:51:14.890339
5802 14:51:14.890404 ==
5803 14:51:14.893893 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 14:51:14.896811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 14:51:14.896901 ==
5806 14:51:14.900043 [Gating] SW mode calibration
5807 14:51:14.906710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5808 14:51:14.913696 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5809 14:51:14.916830 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 14:51:14.923581 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 14:51:14.926499 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 14:51:14.930199 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 14:51:14.936933 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 14:51:14.939914 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5815 14:51:14.943464 0 14 24 | B1->B0 | 2e2e 3232 | 1 0 | (1 1) (0 1)
5816 14:51:14.950075 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 0)
5817 14:51:14.953318 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 14:51:14.956606 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 14:51:14.963193 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 14:51:14.966677 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 14:51:14.970405 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 14:51:14.973668 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 14:51:14.980211 0 15 24 | B1->B0 | 3535 2b2b | 0 0 | (0 0) (0 0)
5824 14:51:14.982959 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
5825 14:51:14.986358 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 14:51:14.993256 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 14:51:14.996129 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 14:51:14.999972 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 14:51:15.006596 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 14:51:15.009837 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5831 14:51:15.013018 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5832 14:51:15.019564 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5833 14:51:15.023004 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 14:51:15.026240 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 14:51:15.032746 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 14:51:15.036321 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 14:51:15.040063 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 14:51:15.046062 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 14:51:15.049571 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 14:51:15.053066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 14:51:15.060156 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 14:51:15.062907 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 14:51:15.066445 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 14:51:15.072825 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 14:51:15.076453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 14:51:15.079559 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5847 14:51:15.085878 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5848 14:51:15.089399 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5849 14:51:15.092553 Total UI for P1: 0, mck2ui 16
5850 14:51:15.095701 best dqsien dly found for B1: ( 1, 2, 22)
5851 14:51:15.099434 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 14:51:15.102375 Total UI for P1: 0, mck2ui 16
5853 14:51:15.106320 best dqsien dly found for B0: ( 1, 2, 28)
5854 14:51:15.109338 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5855 14:51:15.112893 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5856 14:51:15.112974
5857 14:51:15.116066 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5858 14:51:15.122670 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5859 14:51:15.122754 [Gating] SW calibration Done
5860 14:51:15.122818 ==
5861 14:51:15.125931 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 14:51:15.132323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 14:51:15.132414 ==
5864 14:51:15.132477 RX Vref Scan: 0
5865 14:51:15.132537
5866 14:51:15.135625 RX Vref 0 -> 0, step: 1
5867 14:51:15.135705
5868 14:51:15.139302 RX Delay -80 -> 252, step: 8
5869 14:51:15.142626 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5870 14:51:15.146023 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5871 14:51:15.149478 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5872 14:51:15.152267 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5873 14:51:15.159147 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5874 14:51:15.162976 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5875 14:51:15.165671 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5876 14:51:15.168907 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5877 14:51:15.172638 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5878 14:51:15.175612 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5879 14:51:15.182042 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5880 14:51:15.185690 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5881 14:51:15.188520 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5882 14:51:15.192446 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5883 14:51:15.195375 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5884 14:51:15.201997 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5885 14:51:15.202078 ==
5886 14:51:15.205325 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 14:51:15.208664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 14:51:15.208746 ==
5889 14:51:15.208810 DQS Delay:
5890 14:51:15.212194 DQS0 = 0, DQS1 = 0
5891 14:51:15.212300 DQM Delay:
5892 14:51:15.215199 DQM0 = 101, DQM1 = 98
5893 14:51:15.215279 DQ Delay:
5894 14:51:15.219165 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5895 14:51:15.222207 DQ4 =95, DQ5 =115, DQ6 =107, DQ7 =99
5896 14:51:15.225125 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5897 14:51:15.228967 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5898 14:51:15.229048
5899 14:51:15.229111
5900 14:51:15.229168 ==
5901 14:51:15.232095 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 14:51:15.238729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 14:51:15.238811 ==
5904 14:51:15.238874
5905 14:51:15.238932
5906 14:51:15.238988 TX Vref Scan disable
5907 14:51:15.241700 == TX Byte 0 ==
5908 14:51:15.245577 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5909 14:51:15.248928 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5910 14:51:15.252263 == TX Byte 1 ==
5911 14:51:15.255629 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 14:51:15.262054 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 14:51:15.262136 ==
5914 14:51:15.265345 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 14:51:15.268493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 14:51:15.268574 ==
5917 14:51:15.268636
5918 14:51:15.268695
5919 14:51:15.271830 TX Vref Scan disable
5920 14:51:15.271938 == TX Byte 0 ==
5921 14:51:15.278443 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5922 14:51:15.281449 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5923 14:51:15.281530 == TX Byte 1 ==
5924 14:51:15.288691 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 14:51:15.291506 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 14:51:15.291590
5927 14:51:15.291653 [DATLAT]
5928 14:51:15.295158 Freq=933, CH1 RK1
5929 14:51:15.295238
5930 14:51:15.295301 DATLAT Default: 0xb
5931 14:51:15.298329 0, 0xFFFF, sum = 0
5932 14:51:15.298412 1, 0xFFFF, sum = 0
5933 14:51:15.301923 2, 0xFFFF, sum = 0
5934 14:51:15.302004 3, 0xFFFF, sum = 0
5935 14:51:15.304900 4, 0xFFFF, sum = 0
5936 14:51:15.304982 5, 0xFFFF, sum = 0
5937 14:51:15.308621 6, 0xFFFF, sum = 0
5938 14:51:15.311481 7, 0xFFFF, sum = 0
5939 14:51:15.311563 8, 0xFFFF, sum = 0
5940 14:51:15.314902 9, 0xFFFF, sum = 0
5941 14:51:15.314983 10, 0x0, sum = 1
5942 14:51:15.318058 11, 0x0, sum = 2
5943 14:51:15.318140 12, 0x0, sum = 3
5944 14:51:15.318205 13, 0x0, sum = 4
5945 14:51:15.321696 best_step = 11
5946 14:51:15.321776
5947 14:51:15.321837 ==
5948 14:51:15.324688 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 14:51:15.328531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 14:51:15.328612 ==
5951 14:51:15.331515 RX Vref Scan: 0
5952 14:51:15.331595
5953 14:51:15.331658 RX Vref 0 -> 0, step: 1
5954 14:51:15.331717
5955 14:51:15.334752 RX Delay -45 -> 252, step: 4
5956 14:51:15.341978 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5957 14:51:15.346052 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5958 14:51:15.349033 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5959 14:51:15.352045 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5960 14:51:15.355677 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5961 14:51:15.362351 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5962 14:51:15.365563 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5963 14:51:15.369178 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5964 14:51:15.372260 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5965 14:51:15.375407 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5966 14:51:15.379069 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5967 14:51:15.385460 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5968 14:51:15.388619 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5969 14:51:15.392123 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5970 14:51:15.395294 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5971 14:51:15.402370 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5972 14:51:15.402451 ==
5973 14:51:15.405311 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 14:51:15.408871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 14:51:15.408952 ==
5976 14:51:15.409015 DQS Delay:
5977 14:51:15.411951 DQS0 = 0, DQS1 = 0
5978 14:51:15.412070 DQM Delay:
5979 14:51:15.415532 DQM0 = 104, DQM1 = 100
5980 14:51:15.415638 DQ Delay:
5981 14:51:15.418725 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5982 14:51:15.421700 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5983 14:51:15.425549 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =92
5984 14:51:15.428211 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5985 14:51:15.428316
5986 14:51:15.428428
5987 14:51:15.438360 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5988 14:51:15.441317 CH1 RK1: MR19=504, MR18=2BFD
5989 14:51:15.445072 CH1_RK1: MR19=0x504, MR18=0x2BFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5990 14:51:15.448432 [RxdqsGatingPostProcess] freq 933
5991 14:51:15.454916 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5992 14:51:15.457977 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 14:51:15.461572 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 14:51:15.465014 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 14:51:15.468121 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 14:51:15.471240 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 14:51:15.474565 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 14:51:15.477720 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 14:51:15.481395 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 14:51:15.484716 Pre-setting of DQS Precalculation
6001 14:51:15.487623 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6002 14:51:15.494705 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6003 14:51:15.501327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6004 14:51:15.501407
6005 14:51:15.504223
6006 14:51:15.504303 [Calibration Summary] 1866 Mbps
6007 14:51:15.507708 CH 0, Rank 0
6008 14:51:15.507788 SW Impedance : PASS
6009 14:51:15.511219 DUTY Scan : NO K
6010 14:51:15.514356 ZQ Calibration : PASS
6011 14:51:15.514436 Jitter Meter : NO K
6012 14:51:15.517499 CBT Training : PASS
6013 14:51:15.520835 Write leveling : PASS
6014 14:51:15.520915 RX DQS gating : PASS
6015 14:51:15.524024 RX DQ/DQS(RDDQC) : PASS
6016 14:51:15.527533 TX DQ/DQS : PASS
6017 14:51:15.527614 RX DATLAT : PASS
6018 14:51:15.530987 RX DQ/DQS(Engine): PASS
6019 14:51:15.534439 TX OE : NO K
6020 14:51:15.534520 All Pass.
6021 14:51:15.534583
6022 14:51:15.534642 CH 0, Rank 1
6023 14:51:15.537198 SW Impedance : PASS
6024 14:51:15.540706 DUTY Scan : NO K
6025 14:51:15.540786 ZQ Calibration : PASS
6026 14:51:15.544532 Jitter Meter : NO K
6027 14:51:15.547639 CBT Training : PASS
6028 14:51:15.547719 Write leveling : PASS
6029 14:51:15.550509 RX DQS gating : PASS
6030 14:51:15.554295 RX DQ/DQS(RDDQC) : PASS
6031 14:51:15.554380 TX DQ/DQS : PASS
6032 14:51:15.557416 RX DATLAT : PASS
6033 14:51:15.557497 RX DQ/DQS(Engine): PASS
6034 14:51:15.561042 TX OE : NO K
6035 14:51:15.561132 All Pass.
6036 14:51:15.561209
6037 14:51:15.564455 CH 1, Rank 0
6038 14:51:15.564575 SW Impedance : PASS
6039 14:51:15.567548 DUTY Scan : NO K
6040 14:51:15.570445 ZQ Calibration : PASS
6041 14:51:15.570525 Jitter Meter : NO K
6042 14:51:15.574220 CBT Training : PASS
6043 14:51:15.577424 Write leveling : PASS
6044 14:51:15.577505 RX DQS gating : PASS
6045 14:51:15.580796 RX DQ/DQS(RDDQC) : PASS
6046 14:51:15.584272 TX DQ/DQS : PASS
6047 14:51:15.584399 RX DATLAT : PASS
6048 14:51:15.587141 RX DQ/DQS(Engine): PASS
6049 14:51:15.590254 TX OE : NO K
6050 14:51:15.590335 All Pass.
6051 14:51:15.590398
6052 14:51:15.590457 CH 1, Rank 1
6053 14:51:15.594066 SW Impedance : PASS
6054 14:51:15.597174 DUTY Scan : NO K
6055 14:51:15.597255 ZQ Calibration : PASS
6056 14:51:15.600371 Jitter Meter : NO K
6057 14:51:15.604092 CBT Training : PASS
6058 14:51:15.604191 Write leveling : PASS
6059 14:51:15.607453 RX DQS gating : PASS
6060 14:51:15.607533 RX DQ/DQS(RDDQC) : PASS
6061 14:51:15.610720 TX DQ/DQS : PASS
6062 14:51:15.613984 RX DATLAT : PASS
6063 14:51:15.614091 RX DQ/DQS(Engine): PASS
6064 14:51:15.617128 TX OE : NO K
6065 14:51:15.617209 All Pass.
6066 14:51:15.617271
6067 14:51:15.620544 DramC Write-DBI off
6068 14:51:15.623318 PER_BANK_REFRESH: Hybrid Mode
6069 14:51:15.623417 TX_TRACKING: ON
6070 14:51:15.633617 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6071 14:51:15.636697 [FAST_K] Save calibration result to emmc
6072 14:51:15.640169 dramc_set_vcore_voltage set vcore to 650000
6073 14:51:15.643628 Read voltage for 400, 6
6074 14:51:15.643712 Vio18 = 0
6075 14:51:15.647136 Vcore = 650000
6076 14:51:15.647220 Vdram = 0
6077 14:51:15.647283 Vddq = 0
6078 14:51:15.647341 Vmddr = 0
6079 14:51:15.653525 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6080 14:51:15.657338 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6081 14:51:15.660131 MEM_TYPE=3, freq_sel=20
6082 14:51:15.663234 sv_algorithm_assistance_LP4_800
6083 14:51:15.666951 ============ PULL DRAM RESETB DOWN ============
6084 14:51:15.673824 ========== PULL DRAM RESETB DOWN end =========
6085 14:51:15.676694 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6086 14:51:15.680301 ===================================
6087 14:51:15.683441 LPDDR4 DRAM CONFIGURATION
6088 14:51:15.687089 ===================================
6089 14:51:15.687171 EX_ROW_EN[0] = 0x0
6090 14:51:15.689821 EX_ROW_EN[1] = 0x0
6091 14:51:15.689901 LP4Y_EN = 0x0
6092 14:51:15.693258 WORK_FSP = 0x0
6093 14:51:15.693338 WL = 0x2
6094 14:51:15.696679 RL = 0x2
6095 14:51:15.696760 BL = 0x2
6096 14:51:15.699709 RPST = 0x0
6097 14:51:15.699789 RD_PRE = 0x0
6098 14:51:15.703688 WR_PRE = 0x1
6099 14:51:15.703769 WR_PST = 0x0
6100 14:51:15.706511 DBI_WR = 0x0
6101 14:51:15.710189 DBI_RD = 0x0
6102 14:51:15.710270 OTF = 0x1
6103 14:51:15.713190 ===================================
6104 14:51:15.716806 ===================================
6105 14:51:15.716887 ANA top config
6106 14:51:15.719856 ===================================
6107 14:51:15.723406 DLL_ASYNC_EN = 0
6108 14:51:15.726422 ALL_SLAVE_EN = 1
6109 14:51:15.729808 NEW_RANK_MODE = 1
6110 14:51:15.733123 DLL_IDLE_MODE = 1
6111 14:51:15.733204 LP45_APHY_COMB_EN = 1
6112 14:51:15.736299 TX_ODT_DIS = 1
6113 14:51:15.739951 NEW_8X_MODE = 1
6114 14:51:15.743263 ===================================
6115 14:51:15.746700 ===================================
6116 14:51:15.749817 data_rate = 800
6117 14:51:15.753479 CKR = 1
6118 14:51:15.753565 DQ_P2S_RATIO = 4
6119 14:51:15.756757 ===================================
6120 14:51:15.760083 CA_P2S_RATIO = 4
6121 14:51:15.763151 DQ_CA_OPEN = 0
6122 14:51:15.766246 DQ_SEMI_OPEN = 1
6123 14:51:15.769930 CA_SEMI_OPEN = 1
6124 14:51:15.772828 CA_FULL_RATE = 0
6125 14:51:15.772910 DQ_CKDIV4_EN = 0
6126 14:51:15.776352 CA_CKDIV4_EN = 1
6127 14:51:15.779629 CA_PREDIV_EN = 0
6128 14:51:15.782666 PH8_DLY = 0
6129 14:51:15.786542 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6130 14:51:15.789396 DQ_AAMCK_DIV = 0
6131 14:51:15.789476 CA_AAMCK_DIV = 0
6132 14:51:15.793274 CA_ADMCK_DIV = 4
6133 14:51:15.796704 DQ_TRACK_CA_EN = 0
6134 14:51:15.799473 CA_PICK = 800
6135 14:51:15.802875 CA_MCKIO = 400
6136 14:51:15.806005 MCKIO_SEMI = 400
6137 14:51:15.809622 PLL_FREQ = 3016
6138 14:51:15.809702 DQ_UI_PI_RATIO = 32
6139 14:51:15.812828 CA_UI_PI_RATIO = 32
6140 14:51:15.816619 ===================================
6141 14:51:15.819642 ===================================
6142 14:51:15.823063 memory_type:LPDDR4
6143 14:51:15.825949 GP_NUM : 10
6144 14:51:15.826029 SRAM_EN : 1
6145 14:51:15.829678 MD32_EN : 0
6146 14:51:15.833044 ===================================
6147 14:51:15.835917 [ANA_INIT] >>>>>>>>>>>>>>
6148 14:51:15.835997 <<<<<< [CONFIGURE PHASE]: ANA_TX
6149 14:51:15.839667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6150 14:51:15.842754 ===================================
6151 14:51:15.846047 data_rate = 800,PCW = 0X7400
6152 14:51:15.849240 ===================================
6153 14:51:15.852901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6154 14:51:15.859573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 14:51:15.869435 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 14:51:15.876123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6157 14:51:15.879727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6158 14:51:15.882950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6159 14:51:15.883031 [ANA_INIT] flow start
6160 14:51:15.886226 [ANA_INIT] PLL >>>>>>>>
6161 14:51:15.889245 [ANA_INIT] PLL <<<<<<<<
6162 14:51:15.889326 [ANA_INIT] MIDPI >>>>>>>>
6163 14:51:15.892823 [ANA_INIT] MIDPI <<<<<<<<
6164 14:51:15.896067 [ANA_INIT] DLL >>>>>>>>
6165 14:51:15.896147 [ANA_INIT] flow end
6166 14:51:15.902724 ============ LP4 DIFF to SE enter ============
6167 14:51:15.906104 ============ LP4 DIFF to SE exit ============
6168 14:51:15.909747 [ANA_INIT] <<<<<<<<<<<<<
6169 14:51:15.912726 [Flow] Enable top DCM control >>>>>
6170 14:51:15.915666 [Flow] Enable top DCM control <<<<<
6171 14:51:15.915747 Enable DLL master slave shuffle
6172 14:51:15.922446 ==============================================================
6173 14:51:15.926305 Gating Mode config
6174 14:51:15.929137 ==============================================================
6175 14:51:15.932981 Config description:
6176 14:51:15.942319 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6177 14:51:15.949165 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6178 14:51:15.952624 SELPH_MODE 0: By rank 1: By Phase
6179 14:51:15.959435 ==============================================================
6180 14:51:15.962252 GAT_TRACK_EN = 0
6181 14:51:15.965610 RX_GATING_MODE = 2
6182 14:51:15.968923 RX_GATING_TRACK_MODE = 2
6183 14:51:15.971863 SELPH_MODE = 1
6184 14:51:15.975858 PICG_EARLY_EN = 1
6185 14:51:15.975940 VALID_LAT_VALUE = 1
6186 14:51:15.982006 ==============================================================
6187 14:51:15.985547 Enter into Gating configuration >>>>
6188 14:51:15.988586 Exit from Gating configuration <<<<
6189 14:51:15.992024 Enter into DVFS_PRE_config >>>>>
6190 14:51:16.002111 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6191 14:51:16.006020 Exit from DVFS_PRE_config <<<<<
6192 14:51:16.009193 Enter into PICG configuration >>>>
6193 14:51:16.012228 Exit from PICG configuration <<<<
6194 14:51:16.015200 [RX_INPUT] configuration >>>>>
6195 14:51:16.018954 [RX_INPUT] configuration <<<<<
6196 14:51:16.022179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6197 14:51:16.028883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6198 14:51:16.035574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 14:51:16.042282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 14:51:16.048751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 14:51:16.052279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 14:51:16.059211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6203 14:51:16.062256 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6204 14:51:16.065283 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6205 14:51:16.069018 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6206 14:51:16.075706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6207 14:51:16.078582 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 14:51:16.081863 ===================================
6209 14:51:16.085365 LPDDR4 DRAM CONFIGURATION
6210 14:51:16.088587 ===================================
6211 14:51:16.088667 EX_ROW_EN[0] = 0x0
6212 14:51:16.092068 EX_ROW_EN[1] = 0x0
6213 14:51:16.092154 LP4Y_EN = 0x0
6214 14:51:16.095710 WORK_FSP = 0x0
6215 14:51:16.095795 WL = 0x2
6216 14:51:16.098678 RL = 0x2
6217 14:51:16.098763 BL = 0x2
6218 14:51:16.101737 RPST = 0x0
6219 14:51:16.101827 RD_PRE = 0x0
6220 14:51:16.105701 WR_PRE = 0x1
6221 14:51:16.105786 WR_PST = 0x0
6222 14:51:16.109113 DBI_WR = 0x0
6223 14:51:16.109198 DBI_RD = 0x0
6224 14:51:16.112070 OTF = 0x1
6225 14:51:16.115360 ===================================
6226 14:51:16.118782 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6227 14:51:16.121992 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6228 14:51:16.128714 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 14:51:16.132723 ===================================
6230 14:51:16.135323 LPDDR4 DRAM CONFIGURATION
6231 14:51:16.135408 ===================================
6232 14:51:16.138449 EX_ROW_EN[0] = 0x10
6233 14:51:16.142025 EX_ROW_EN[1] = 0x0
6234 14:51:16.142110 LP4Y_EN = 0x0
6235 14:51:16.145389 WORK_FSP = 0x0
6236 14:51:16.145475 WL = 0x2
6237 14:51:16.148693 RL = 0x2
6238 14:51:16.148778 BL = 0x2
6239 14:51:16.151738 RPST = 0x0
6240 14:51:16.151823 RD_PRE = 0x0
6241 14:51:16.155169 WR_PRE = 0x1
6242 14:51:16.155254 WR_PST = 0x0
6243 14:51:16.158606 DBI_WR = 0x0
6244 14:51:16.158690 DBI_RD = 0x0
6245 14:51:16.161773 OTF = 0x1
6246 14:51:16.165489 ===================================
6247 14:51:16.171467 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6248 14:51:16.175294 nWR fixed to 30
6249 14:51:16.178381 [ModeRegInit_LP4] CH0 RK0
6250 14:51:16.178466 [ModeRegInit_LP4] CH0 RK1
6251 14:51:16.181869 [ModeRegInit_LP4] CH1 RK0
6252 14:51:16.185014 [ModeRegInit_LP4] CH1 RK1
6253 14:51:16.185098 match AC timing 19
6254 14:51:16.191779 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6255 14:51:16.195424 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6256 14:51:16.198461 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6257 14:51:16.205137 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6258 14:51:16.208658 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6259 14:51:16.208748 ==
6260 14:51:16.211683 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 14:51:16.215068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 14:51:16.215154 ==
6263 14:51:16.221915 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 14:51:16.228603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6265 14:51:16.231555 [CA 0] Center 36 (8~64) winsize 57
6266 14:51:16.234707 [CA 1] Center 36 (8~64) winsize 57
6267 14:51:16.234791 [CA 2] Center 36 (8~64) winsize 57
6268 14:51:16.238533 [CA 3] Center 36 (8~64) winsize 57
6269 14:51:16.241388 [CA 4] Center 36 (8~64) winsize 57
6270 14:51:16.245079 [CA 5] Center 36 (8~64) winsize 57
6271 14:51:16.245163
6272 14:51:16.248474 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6273 14:51:16.251345
6274 14:51:16.254831 [CATrainingPosCal] consider 1 rank data
6275 14:51:16.254916 u2DelayCellTimex100 = 270/100 ps
6276 14:51:16.261527 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 14:51:16.265090 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 14:51:16.267789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 14:51:16.271662 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 14:51:16.274556 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 14:51:16.278025 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 14:51:16.278111
6283 14:51:16.281584 CA PerBit enable=1, Macro0, CA PI delay=36
6284 14:51:16.281669
6285 14:51:16.285147 [CBTSetCACLKResult] CA Dly = 36
6286 14:51:16.287927 CS Dly: 1 (0~32)
6287 14:51:16.288012 ==
6288 14:51:16.291822 Dram Type= 6, Freq= 0, CH_0, rank 1
6289 14:51:16.294880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 14:51:16.294966 ==
6291 14:51:16.301567 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 14:51:16.304612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 14:51:16.308291 [CA 0] Center 36 (8~64) winsize 57
6294 14:51:16.311392 [CA 1] Center 36 (8~64) winsize 57
6295 14:51:16.314627 [CA 2] Center 36 (8~64) winsize 57
6296 14:51:16.318022 [CA 3] Center 36 (8~64) winsize 57
6297 14:51:16.321594 [CA 4] Center 36 (8~64) winsize 57
6298 14:51:16.325001 [CA 5] Center 36 (8~64) winsize 57
6299 14:51:16.325088
6300 14:51:16.327964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 14:51:16.328049
6302 14:51:16.331256 [CATrainingPosCal] consider 2 rank data
6303 14:51:16.335018 u2DelayCellTimex100 = 270/100 ps
6304 14:51:16.338407 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 14:51:16.341553 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 14:51:16.344450 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 14:51:16.348122 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 14:51:16.354401 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 14:51:16.358025 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 14:51:16.358113
6311 14:51:16.361123 CA PerBit enable=1, Macro0, CA PI delay=36
6312 14:51:16.361209
6313 14:51:16.364732 [CBTSetCACLKResult] CA Dly = 36
6314 14:51:16.364817 CS Dly: 1 (0~32)
6315 14:51:16.364903
6316 14:51:16.368215 ----->DramcWriteLeveling(PI) begin...
6317 14:51:16.368326 ==
6318 14:51:16.371273 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 14:51:16.377754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 14:51:16.377840 ==
6321 14:51:16.381567 Write leveling (Byte 0): 40 => 8
6322 14:51:16.381641 Write leveling (Byte 1): 40 => 8
6323 14:51:16.384505 DramcWriteLeveling(PI) end<-----
6324 14:51:16.384584
6325 14:51:16.384648 ==
6326 14:51:16.388138 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 14:51:16.394492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 14:51:16.394573 ==
6329 14:51:16.398354 [Gating] SW mode calibration
6330 14:51:16.405024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6331 14:51:16.408140 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6332 14:51:16.414939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 14:51:16.417787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 14:51:16.420996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 14:51:16.428029 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 14:51:16.431436 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 14:51:16.434403 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 14:51:16.437608 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 14:51:16.444746 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 14:51:16.447552 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 14:51:16.451249 Total UI for P1: 0, mck2ui 16
6342 14:51:16.454480 best dqsien dly found for B0: ( 0, 14, 24)
6343 14:51:16.457567 Total UI for P1: 0, mck2ui 16
6344 14:51:16.461290 best dqsien dly found for B1: ( 0, 14, 24)
6345 14:51:16.464250 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6346 14:51:16.467781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6347 14:51:16.467862
6348 14:51:16.471282 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 14:51:16.478122 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 14:51:16.478203 [Gating] SW calibration Done
6351 14:51:16.478267 ==
6352 14:51:16.481061 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 14:51:16.488002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 14:51:16.488083 ==
6355 14:51:16.488147 RX Vref Scan: 0
6356 14:51:16.488207
6357 14:51:16.491193 RX Vref 0 -> 0, step: 1
6358 14:51:16.491273
6359 14:51:16.494182 RX Delay -410 -> 252, step: 16
6360 14:51:16.497609 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6361 14:51:16.501092 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6362 14:51:16.507574 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6363 14:51:16.510889 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6364 14:51:16.514388 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6365 14:51:16.517599 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6366 14:51:16.520735 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6367 14:51:16.527316 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6368 14:51:16.530552 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6369 14:51:16.534100 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6370 14:51:16.537259 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6371 14:51:16.544083 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6372 14:51:16.547542 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6373 14:51:16.550622 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6374 14:51:16.557616 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6375 14:51:16.560792 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6376 14:51:16.560873 ==
6377 14:51:16.563734 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 14:51:16.567483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 14:51:16.567564 ==
6380 14:51:16.570904 DQS Delay:
6381 14:51:16.570983 DQS0 = 27, DQS1 = 35
6382 14:51:16.571047 DQM Delay:
6383 14:51:16.573967 DQM0 = 15, DQM1 = 15
6384 14:51:16.574047 DQ Delay:
6385 14:51:16.577502 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =8
6386 14:51:16.580465 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6387 14:51:16.584047 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6388 14:51:16.587319 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =16
6389 14:51:16.587399
6390 14:51:16.587461
6391 14:51:16.587518 ==
6392 14:51:16.590160 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 14:51:16.594081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 14:51:16.597006 ==
6395 14:51:16.597134
6396 14:51:16.597215
6397 14:51:16.597273 TX Vref Scan disable
6398 14:51:16.600247 == TX Byte 0 ==
6399 14:51:16.603637 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 14:51:16.607562 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 14:51:16.610543 == TX Byte 1 ==
6402 14:51:16.613525 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 14:51:16.616929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 14:51:16.617010 ==
6405 14:51:16.620028 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 14:51:16.627034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 14:51:16.627115 ==
6408 14:51:16.627177
6409 14:51:16.627234
6410 14:51:16.627290 TX Vref Scan disable
6411 14:51:16.630035 == TX Byte 0 ==
6412 14:51:16.633880 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 14:51:16.637009 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 14:51:16.640194 == TX Byte 1 ==
6415 14:51:16.643513 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 14:51:16.647167 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 14:51:16.647247
6418 14:51:16.650254 [DATLAT]
6419 14:51:16.650333 Freq=400, CH0 RK0
6420 14:51:16.650397
6421 14:51:16.653347 DATLAT Default: 0xf
6422 14:51:16.653432 0, 0xFFFF, sum = 0
6423 14:51:16.656706 1, 0xFFFF, sum = 0
6424 14:51:16.656787 2, 0xFFFF, sum = 0
6425 14:51:16.659887 3, 0xFFFF, sum = 0
6426 14:51:16.659967 4, 0xFFFF, sum = 0
6427 14:51:16.663313 5, 0xFFFF, sum = 0
6428 14:51:16.663393 6, 0xFFFF, sum = 0
6429 14:51:16.666470 7, 0xFFFF, sum = 0
6430 14:51:16.666565 8, 0xFFFF, sum = 0
6431 14:51:16.669871 9, 0xFFFF, sum = 0
6432 14:51:16.669953 10, 0xFFFF, sum = 0
6433 14:51:16.673519 11, 0xFFFF, sum = 0
6434 14:51:16.676763 12, 0xFFFF, sum = 0
6435 14:51:16.676844 13, 0x0, sum = 1
6436 14:51:16.676908 14, 0x0, sum = 2
6437 14:51:16.680156 15, 0x0, sum = 3
6438 14:51:16.680238 16, 0x0, sum = 4
6439 14:51:16.683270 best_step = 14
6440 14:51:16.683350
6441 14:51:16.683414 ==
6442 14:51:16.686520 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 14:51:16.689964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 14:51:16.690045 ==
6445 14:51:16.693149 RX Vref Scan: 1
6446 14:51:16.693229
6447 14:51:16.693293 RX Vref 0 -> 0, step: 1
6448 14:51:16.693351
6449 14:51:16.696732 RX Delay -311 -> 252, step: 8
6450 14:51:16.696826
6451 14:51:16.699837 Set Vref, RX VrefLevel [Byte0]: 56
6452 14:51:16.702898 [Byte1]: 47
6453 14:51:16.707997
6454 14:51:16.708077 Final RX Vref Byte 0 = 56 to rank0
6455 14:51:16.711704 Final RX Vref Byte 1 = 47 to rank0
6456 14:51:16.714619 Final RX Vref Byte 0 = 56 to rank1
6457 14:51:16.718028 Final RX Vref Byte 1 = 47 to rank1==
6458 14:51:16.721769 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 14:51:16.728493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 14:51:16.728576 ==
6461 14:51:16.728642 DQS Delay:
6462 14:51:16.728702 DQS0 = 28, DQS1 = 36
6463 14:51:16.731413 DQM Delay:
6464 14:51:16.731495 DQM0 = 10, DQM1 = 12
6465 14:51:16.734690 DQ Delay:
6466 14:51:16.738253 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6467 14:51:16.738335 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6468 14:51:16.741217 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6469 14:51:16.745193 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6470 14:51:16.745275
6471 14:51:16.745339
6472 14:51:16.754876 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6473 14:51:16.757841 CH0 RK0: MR19=C0C, MR18=C8B6
6474 14:51:16.764712 CH0_RK0: MR19=0xC0C, MR18=0xC8B6, DQSOSC=385, MR23=63, INC=398, DEC=265
6475 14:51:16.764793 ==
6476 14:51:16.768430 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 14:51:16.771226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 14:51:16.771307 ==
6479 14:51:16.775021 [Gating] SW mode calibration
6480 14:51:16.781286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6481 14:51:16.784654 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6482 14:51:16.791621 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 14:51:16.794910 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 14:51:16.798148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 14:51:16.804599 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 14:51:16.807863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 14:51:16.811254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 14:51:16.817658 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 14:51:16.821064 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 14:51:16.824646 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 14:51:16.828048 Total UI for P1: 0, mck2ui 16
6492 14:51:16.831157 best dqsien dly found for B0: ( 0, 14, 24)
6493 14:51:16.834403 Total UI for P1: 0, mck2ui 16
6494 14:51:16.838074 best dqsien dly found for B1: ( 0, 14, 24)
6495 14:51:16.841030 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6496 14:51:16.844905 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6497 14:51:16.844986
6498 14:51:16.851553 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 14:51:16.854418 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 14:51:16.857808 [Gating] SW calibration Done
6501 14:51:16.857890 ==
6502 14:51:16.861762 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 14:51:16.864607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 14:51:16.864689 ==
6505 14:51:16.864752 RX Vref Scan: 0
6506 14:51:16.864812
6507 14:51:16.867860 RX Vref 0 -> 0, step: 1
6508 14:51:16.867940
6509 14:51:16.871473 RX Delay -410 -> 252, step: 16
6510 14:51:16.874297 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6511 14:51:16.877891 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6512 14:51:16.884644 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6513 14:51:16.887715 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6514 14:51:16.891402 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6515 14:51:16.894254 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6516 14:51:16.901173 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6517 14:51:16.904121 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6518 14:51:16.907696 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6519 14:51:16.910886 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6520 14:51:16.917709 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6521 14:51:16.921228 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6522 14:51:16.924652 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6523 14:51:16.930862 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6524 14:51:16.934278 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6525 14:51:16.937216 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6526 14:51:16.937297 ==
6527 14:51:16.940744 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 14:51:16.944199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 14:51:16.944280 ==
6530 14:51:16.947413 DQS Delay:
6531 14:51:16.947493 DQS0 = 27, DQS1 = 35
6532 14:51:16.950979 DQM Delay:
6533 14:51:16.951060 DQM0 = 12, DQM1 = 12
6534 14:51:16.954433 DQ Delay:
6535 14:51:16.954514 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6536 14:51:16.957396 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6537 14:51:16.960736 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6538 14:51:16.964281 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6539 14:51:16.964400
6540 14:51:16.964466
6541 14:51:16.964526 ==
6542 14:51:16.967635 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 14:51:16.974311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 14:51:16.974393 ==
6545 14:51:16.974456
6546 14:51:16.974515
6547 14:51:16.974572 TX Vref Scan disable
6548 14:51:16.977661 == TX Byte 0 ==
6549 14:51:16.981235 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6550 14:51:16.984255 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6551 14:51:16.987420 == TX Byte 1 ==
6552 14:51:16.991085 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6553 14:51:16.994143 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6554 14:51:16.994224 ==
6555 14:51:16.997332 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 14:51:17.003954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 14:51:17.004036 ==
6558 14:51:17.004098
6559 14:51:17.004157
6560 14:51:17.004213 TX Vref Scan disable
6561 14:51:17.007460 == TX Byte 0 ==
6562 14:51:17.010906 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6563 14:51:17.013911 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6564 14:51:17.017039 == TX Byte 1 ==
6565 14:51:17.020539 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6566 14:51:17.023761 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6567 14:51:17.023841
6568 14:51:17.027274 [DATLAT]
6569 14:51:17.027354 Freq=400, CH0 RK1
6570 14:51:17.027418
6571 14:51:17.030483 DATLAT Default: 0xe
6572 14:51:17.030564 0, 0xFFFF, sum = 0
6573 14:51:17.034066 1, 0xFFFF, sum = 0
6574 14:51:17.034148 2, 0xFFFF, sum = 0
6575 14:51:17.037039 3, 0xFFFF, sum = 0
6576 14:51:17.037120 4, 0xFFFF, sum = 0
6577 14:51:17.040658 5, 0xFFFF, sum = 0
6578 14:51:17.040739 6, 0xFFFF, sum = 0
6579 14:51:17.043873 7, 0xFFFF, sum = 0
6580 14:51:17.043954 8, 0xFFFF, sum = 0
6581 14:51:17.046920 9, 0xFFFF, sum = 0
6582 14:51:17.050489 10, 0xFFFF, sum = 0
6583 14:51:17.050574 11, 0xFFFF, sum = 0
6584 14:51:17.053523 12, 0xFFFF, sum = 0
6585 14:51:17.053605 13, 0x0, sum = 1
6586 14:51:17.057074 14, 0x0, sum = 2
6587 14:51:17.057155 15, 0x0, sum = 3
6588 14:51:17.060040 16, 0x0, sum = 4
6589 14:51:17.060121 best_step = 14
6590 14:51:17.060184
6591 14:51:17.060243 ==
6592 14:51:17.063358 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 14:51:17.066712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 14:51:17.066793 ==
6595 14:51:17.070044 RX Vref Scan: 0
6596 14:51:17.070124
6597 14:51:17.073316 RX Vref 0 -> 0, step: 1
6598 14:51:17.073397
6599 14:51:17.073460 RX Delay -311 -> 252, step: 8
6600 14:51:17.081865 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6601 14:51:17.085349 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6602 14:51:17.088410 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6603 14:51:17.092211 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6604 14:51:17.098572 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6605 14:51:17.101794 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6606 14:51:17.105342 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6607 14:51:17.108288 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6608 14:51:17.114992 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6609 14:51:17.118657 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6610 14:51:17.121984 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6611 14:51:17.125049 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6612 14:51:17.131852 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6613 14:51:17.134779 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6614 14:51:17.138444 iDelay=217, Bit 14, Center -16 (-231 ~ 200) 432
6615 14:51:17.145227 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6616 14:51:17.145307 ==
6617 14:51:17.148276 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 14:51:17.151770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 14:51:17.151850 ==
6620 14:51:17.151914 DQS Delay:
6621 14:51:17.155060 DQS0 = 24, DQS1 = 36
6622 14:51:17.155139 DQM Delay:
6623 14:51:17.158581 DQM0 = 8, DQM1 = 13
6624 14:51:17.158661 DQ Delay:
6625 14:51:17.161807 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6626 14:51:17.164705 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6627 14:51:17.168418 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6628 14:51:17.171363 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6629 14:51:17.171444
6630 14:51:17.171506
6631 14:51:17.178582 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6632 14:51:17.181700 CH0 RK1: MR19=C0C, MR18=BA5B
6633 14:51:17.188257 CH0_RK1: MR19=0xC0C, MR18=0xBA5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6634 14:51:17.191037 [RxdqsGatingPostProcess] freq 400
6635 14:51:17.198049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6636 14:51:17.198129 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 14:51:17.201421 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 14:51:17.205019 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 14:51:17.208240 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 14:51:17.211143 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 14:51:17.214949 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 14:51:17.218098 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 14:51:17.221437 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 14:51:17.224849 Pre-setting of DQS Precalculation
6645 14:51:17.228045 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6646 14:51:17.231505 ==
6647 14:51:17.234612 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 14:51:17.237906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 14:51:17.237987 ==
6650 14:51:17.241366 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 14:51:17.248041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 14:51:17.251306 [CA 0] Center 36 (8~64) winsize 57
6653 14:51:17.254762 [CA 1] Center 36 (8~64) winsize 57
6654 14:51:17.257657 [CA 2] Center 36 (8~64) winsize 57
6655 14:51:17.261547 [CA 3] Center 36 (8~64) winsize 57
6656 14:51:17.264707 [CA 4] Center 36 (8~64) winsize 57
6657 14:51:17.268144 [CA 5] Center 36 (8~64) winsize 57
6658 14:51:17.268224
6659 14:51:17.271123 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 14:51:17.271203
6661 14:51:17.274972 [CATrainingPosCal] consider 1 rank data
6662 14:51:17.277995 u2DelayCellTimex100 = 270/100 ps
6663 14:51:17.281543 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 14:51:17.284827 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 14:51:17.288125 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 14:51:17.291121 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 14:51:17.294503 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 14:51:17.300982 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 14:51:17.301063
6670 14:51:17.304537 CA PerBit enable=1, Macro0, CA PI delay=36
6671 14:51:17.304617
6672 14:51:17.308073 [CBTSetCACLKResult] CA Dly = 36
6673 14:51:17.308153 CS Dly: 1 (0~32)
6674 14:51:17.308217 ==
6675 14:51:17.311239 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 14:51:17.315069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 14:51:17.315150 ==
6678 14:51:17.321230 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 14:51:17.327764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6680 14:51:17.331272 [CA 0] Center 36 (8~64) winsize 57
6681 14:51:17.334605 [CA 1] Center 36 (8~64) winsize 57
6682 14:51:17.337877 [CA 2] Center 36 (8~64) winsize 57
6683 14:51:17.340933 [CA 3] Center 36 (8~64) winsize 57
6684 14:51:17.344545 [CA 4] Center 36 (8~64) winsize 57
6685 14:51:17.347905 [CA 5] Center 36 (8~64) winsize 57
6686 14:51:17.347986
6687 14:51:17.350873 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6688 14:51:17.350955
6689 14:51:17.354385 [CATrainingPosCal] consider 2 rank data
6690 14:51:17.358044 u2DelayCellTimex100 = 270/100 ps
6691 14:51:17.360991 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 14:51:17.364544 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 14:51:17.367560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 14:51:17.370808 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 14:51:17.374086 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 14:51:17.377687 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 14:51:17.377767
6698 14:51:17.380754 CA PerBit enable=1, Macro0, CA PI delay=36
6699 14:51:17.384472
6700 14:51:17.384552 [CBTSetCACLKResult] CA Dly = 36
6701 14:51:17.387200 CS Dly: 1 (0~32)
6702 14:51:17.387280
6703 14:51:17.390787 ----->DramcWriteLeveling(PI) begin...
6704 14:51:17.390868 ==
6705 14:51:17.393842 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 14:51:17.397610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 14:51:17.397690 ==
6708 14:51:17.400465 Write leveling (Byte 0): 40 => 8
6709 14:51:17.403975 Write leveling (Byte 1): 40 => 8
6710 14:51:17.407434 DramcWriteLeveling(PI) end<-----
6711 14:51:17.407514
6712 14:51:17.407579 ==
6713 14:51:17.410515 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 14:51:17.413944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 14:51:17.414024 ==
6716 14:51:17.417775 [Gating] SW mode calibration
6717 14:51:17.423994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6718 14:51:17.430454 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6719 14:51:17.434206 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 14:51:17.440461 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 14:51:17.444054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 14:51:17.447527 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 14:51:17.454179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 14:51:17.456900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 14:51:17.460486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 14:51:17.467035 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 14:51:17.470597 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 14:51:17.473842 Total UI for P1: 0, mck2ui 16
6729 14:51:17.476993 best dqsien dly found for B0: ( 0, 14, 24)
6730 14:51:17.480178 Total UI for P1: 0, mck2ui 16
6731 14:51:17.483476 best dqsien dly found for B1: ( 0, 14, 24)
6732 14:51:17.487276 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6733 14:51:17.490307 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6734 14:51:17.490387
6735 14:51:17.493850 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 14:51:17.496973 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 14:51:17.500185 [Gating] SW calibration Done
6738 14:51:17.500265 ==
6739 14:51:17.503705 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 14:51:17.506880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 14:51:17.506962 ==
6742 14:51:17.510437 RX Vref Scan: 0
6743 14:51:17.510518
6744 14:51:17.513695 RX Vref 0 -> 0, step: 1
6745 14:51:17.513776
6746 14:51:17.513839 RX Delay -410 -> 252, step: 16
6747 14:51:17.520916 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6748 14:51:17.524038 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6749 14:51:17.527074 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6750 14:51:17.533777 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6751 14:51:17.536914 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6752 14:51:17.540680 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6753 14:51:17.543494 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6754 14:51:17.546744 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6755 14:51:17.553632 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6756 14:51:17.556494 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6757 14:51:17.560143 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6758 14:51:17.566741 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6759 14:51:17.569879 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6760 14:51:17.573502 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6761 14:51:17.576780 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6762 14:51:17.583438 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6763 14:51:17.583523 ==
6764 14:51:17.586921 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 14:51:17.590026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 14:51:17.590110 ==
6767 14:51:17.590175 DQS Delay:
6768 14:51:17.593823 DQS0 = 27, DQS1 = 27
6769 14:51:17.593905 DQM Delay:
6770 14:51:17.596680 DQM0 = 11, DQM1 = 8
6771 14:51:17.596762 DQ Delay:
6772 14:51:17.600253 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6773 14:51:17.603424 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6774 14:51:17.606350 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6775 14:51:17.609538 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6776 14:51:17.609620
6777 14:51:17.609684
6778 14:51:17.609743 ==
6779 14:51:17.613319 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 14:51:17.616651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 14:51:17.616734 ==
6782 14:51:17.616800
6783 14:51:17.616860
6784 14:51:17.620074 TX Vref Scan disable
6785 14:51:17.620157 == TX Byte 0 ==
6786 14:51:17.626203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 14:51:17.629860 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 14:51:17.629943 == TX Byte 1 ==
6789 14:51:17.636562 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 14:51:17.639490 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 14:51:17.639599 ==
6792 14:51:17.642741 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 14:51:17.645733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 14:51:17.645839 ==
6795 14:51:17.646001
6796 14:51:17.646151
6797 14:51:17.649469 TX Vref Scan disable
6798 14:51:17.649554 == TX Byte 0 ==
6799 14:51:17.656332 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 14:51:17.659371 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 14:51:17.659453 == TX Byte 1 ==
6802 14:51:17.665932 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 14:51:17.669176 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 14:51:17.669260
6805 14:51:17.669323 [DATLAT]
6806 14:51:17.672192 Freq=400, CH1 RK0
6807 14:51:17.672275
6808 14:51:17.672351 DATLAT Default: 0xf
6809 14:51:17.676445 0, 0xFFFF, sum = 0
6810 14:51:17.676527 1, 0xFFFF, sum = 0
6811 14:51:17.679130 2, 0xFFFF, sum = 0
6812 14:51:17.679212 3, 0xFFFF, sum = 0
6813 14:51:17.682490 4, 0xFFFF, sum = 0
6814 14:51:17.686074 5, 0xFFFF, sum = 0
6815 14:51:17.686157 6, 0xFFFF, sum = 0
6816 14:51:17.689315 7, 0xFFFF, sum = 0
6817 14:51:17.689396 8, 0xFFFF, sum = 0
6818 14:51:17.692760 9, 0xFFFF, sum = 0
6819 14:51:17.692842 10, 0xFFFF, sum = 0
6820 14:51:17.696026 11, 0xFFFF, sum = 0
6821 14:51:17.696108 12, 0xFFFF, sum = 0
6822 14:51:17.699414 13, 0x0, sum = 1
6823 14:51:17.699495 14, 0x0, sum = 2
6824 14:51:17.702408 15, 0x0, sum = 3
6825 14:51:17.702497 16, 0x0, sum = 4
6826 14:51:17.706045 best_step = 14
6827 14:51:17.706125
6828 14:51:17.706188 ==
6829 14:51:17.709235 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 14:51:17.712198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 14:51:17.712279 ==
6832 14:51:17.712350 RX Vref Scan: 1
6833 14:51:17.712443
6834 14:51:17.716004 RX Vref 0 -> 0, step: 1
6835 14:51:17.716084
6836 14:51:17.718948 RX Delay -295 -> 252, step: 8
6837 14:51:17.719028
6838 14:51:17.722074 Set Vref, RX VrefLevel [Byte0]: 53
6839 14:51:17.725823 [Byte1]: 52
6840 14:51:17.729504
6841 14:51:17.729586 Final RX Vref Byte 0 = 53 to rank0
6842 14:51:17.732754 Final RX Vref Byte 1 = 52 to rank0
6843 14:51:17.736495 Final RX Vref Byte 0 = 53 to rank1
6844 14:51:17.739408 Final RX Vref Byte 1 = 52 to rank1==
6845 14:51:17.742792 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 14:51:17.749714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 14:51:17.749808 ==
6848 14:51:17.749874 DQS Delay:
6849 14:51:17.752628 DQS0 = 32, DQS1 = 32
6850 14:51:17.752711 DQM Delay:
6851 14:51:17.752777 DQM0 = 13, DQM1 = 11
6852 14:51:17.755926 DQ Delay:
6853 14:51:17.759456 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6854 14:51:17.762789 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6855 14:51:17.762872 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6856 14:51:17.765960 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6857 14:51:17.769244
6858 14:51:17.769326
6859 14:51:17.775572 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6860 14:51:17.779217 CH1 RK0: MR19=C0C, MR18=90C9
6861 14:51:17.785677 CH1_RK0: MR19=0xC0C, MR18=0x90C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6862 14:51:17.785766 ==
6863 14:51:17.789241 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 14:51:17.792279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 14:51:17.792400 ==
6866 14:51:17.795739 [Gating] SW mode calibration
6867 14:51:17.802722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6868 14:51:17.809282 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6869 14:51:17.812279 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 14:51:17.815618 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 14:51:17.822046 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 14:51:17.825526 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 14:51:17.829174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 14:51:17.835900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 14:51:17.838861 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 14:51:17.842095 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 14:51:17.846067 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 14:51:17.849206 Total UI for P1: 0, mck2ui 16
6879 14:51:17.852277 best dqsien dly found for B0: ( 0, 14, 24)
6880 14:51:17.856120 Total UI for P1: 0, mck2ui 16
6881 14:51:17.858835 best dqsien dly found for B1: ( 0, 14, 24)
6882 14:51:17.862065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6883 14:51:17.865473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6884 14:51:17.869046
6885 14:51:17.872773 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 14:51:17.875541 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 14:51:17.879369 [Gating] SW calibration Done
6888 14:51:17.879452 ==
6889 14:51:17.882298 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 14:51:17.885195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 14:51:17.885282 ==
6892 14:51:17.888831 RX Vref Scan: 0
6893 14:51:17.888913
6894 14:51:17.888978 RX Vref 0 -> 0, step: 1
6895 14:51:17.889038
6896 14:51:17.892034 RX Delay -410 -> 252, step: 16
6897 14:51:17.895487 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6898 14:51:17.902301 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6899 14:51:17.905405 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6900 14:51:17.908377 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6901 14:51:17.912053 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6902 14:51:17.919020 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6903 14:51:17.922022 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6904 14:51:17.925792 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6905 14:51:17.928751 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6906 14:51:17.935693 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6907 14:51:17.938806 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6908 14:51:17.941701 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6909 14:51:17.945229 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6910 14:51:17.951741 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6911 14:51:17.955462 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6912 14:51:17.958405 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6913 14:51:17.958488 ==
6914 14:51:17.962222 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 14:51:17.968756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 14:51:17.968840 ==
6917 14:51:17.968905 DQS Delay:
6918 14:51:17.972243 DQS0 = 35, DQS1 = 35
6919 14:51:17.972326 DQM Delay:
6920 14:51:17.972435 DQM0 = 17, DQM1 = 14
6921 14:51:17.975268 DQ Delay:
6922 14:51:17.978472 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6923 14:51:17.981551 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6924 14:51:17.981633 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6925 14:51:17.988614 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6926 14:51:17.988696
6927 14:51:17.988760
6928 14:51:17.988820 ==
6929 14:51:17.991620 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 14:51:17.994763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 14:51:17.994846 ==
6932 14:51:17.994911
6933 14:51:17.994971
6934 14:51:17.998264 TX Vref Scan disable
6935 14:51:17.998347 == TX Byte 0 ==
6936 14:51:18.001847 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6937 14:51:18.008497 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6938 14:51:18.008580 == TX Byte 1 ==
6939 14:51:18.011164 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6940 14:51:18.018060 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6941 14:51:18.018143 ==
6942 14:51:18.021324 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 14:51:18.024977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 14:51:18.025060 ==
6945 14:51:18.025125
6946 14:51:18.025184
6947 14:51:18.028319 TX Vref Scan disable
6948 14:51:18.028437 == TX Byte 0 ==
6949 14:51:18.034722 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6950 14:51:18.038321 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6951 14:51:18.038404 == TX Byte 1 ==
6952 14:51:18.041758 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6953 14:51:18.047749 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6954 14:51:18.047833
6955 14:51:18.047899 [DATLAT]
6956 14:51:18.051511 Freq=400, CH1 RK1
6957 14:51:18.051593
6958 14:51:18.051658 DATLAT Default: 0xe
6959 14:51:18.054457 0, 0xFFFF, sum = 0
6960 14:51:18.054539 1, 0xFFFF, sum = 0
6961 14:51:18.057768 2, 0xFFFF, sum = 0
6962 14:51:18.057853 3, 0xFFFF, sum = 0
6963 14:51:18.061501 4, 0xFFFF, sum = 0
6964 14:51:18.061586 5, 0xFFFF, sum = 0
6965 14:51:18.064532 6, 0xFFFF, sum = 0
6966 14:51:18.064615 7, 0xFFFF, sum = 0
6967 14:51:18.067561 8, 0xFFFF, sum = 0
6968 14:51:18.067645 9, 0xFFFF, sum = 0
6969 14:51:18.071154 10, 0xFFFF, sum = 0
6970 14:51:18.071237 11, 0xFFFF, sum = 0
6971 14:51:18.074432 12, 0xFFFF, sum = 0
6972 14:51:18.074515 13, 0x0, sum = 1
6973 14:51:18.077887 14, 0x0, sum = 2
6974 14:51:18.077970 15, 0x0, sum = 3
6975 14:51:18.081510 16, 0x0, sum = 4
6976 14:51:18.081593 best_step = 14
6977 14:51:18.081658
6978 14:51:18.081718 ==
6979 14:51:18.084726 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 14:51:18.091472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 14:51:18.091559 ==
6982 14:51:18.091635 RX Vref Scan: 0
6983 14:51:18.091697
6984 14:51:18.094232 RX Vref 0 -> 0, step: 1
6985 14:51:18.094314
6986 14:51:18.097695 RX Delay -311 -> 252, step: 8
6987 14:51:18.104416 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6988 14:51:18.107690 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6989 14:51:18.111154 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6990 14:51:18.114408 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6991 14:51:18.121163 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6992 14:51:18.124317 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6993 14:51:18.127262 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6994 14:51:18.130880 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6995 14:51:18.137505 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6996 14:51:18.140776 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6997 14:51:18.144146 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6998 14:51:18.147526 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6999 14:51:18.154170 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7000 14:51:18.157374 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7001 14:51:18.160784 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7002 14:51:18.164186 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7003 14:51:18.167443 ==
7004 14:51:18.167525 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 14:51:18.174288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 14:51:18.174373 ==
7007 14:51:18.174437 DQS Delay:
7008 14:51:18.177713 DQS0 = 28, DQS1 = 36
7009 14:51:18.177795 DQM Delay:
7010 14:51:18.180966 DQM0 = 10, DQM1 = 15
7011 14:51:18.181047 DQ Delay:
7012 14:51:18.183837 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7013 14:51:18.187160 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7014 14:51:18.190736 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7015 14:51:18.194010 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7016 14:51:18.194090
7017 14:51:18.194153
7018 14:51:18.200474 [DQSOSCAuto] RK1, (LSB)MR18= 0xc555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7019 14:51:18.204166 CH1 RK1: MR19=C0C, MR18=C555
7020 14:51:18.210692 CH1_RK1: MR19=0xC0C, MR18=0xC555, DQSOSC=385, MR23=63, INC=398, DEC=265
7021 14:51:18.213610 [RxdqsGatingPostProcess] freq 400
7022 14:51:18.217379 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7023 14:51:18.220570 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 14:51:18.223566 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 14:51:18.227306 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 14:51:18.230549 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 14:51:18.234082 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 14:51:18.237026 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 14:51:18.240438 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 14:51:18.243740 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 14:51:18.247017 Pre-setting of DQS Precalculation
7032 14:51:18.250380 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7033 14:51:18.260009 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7034 14:51:18.266698 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7035 14:51:18.266780
7036 14:51:18.266844
7037 14:51:18.270390 [Calibration Summary] 800 Mbps
7038 14:51:18.270471 CH 0, Rank 0
7039 14:51:18.273716 SW Impedance : PASS
7040 14:51:18.273839 DUTY Scan : NO K
7041 14:51:18.276897 ZQ Calibration : PASS
7042 14:51:18.280150 Jitter Meter : NO K
7043 14:51:18.280230 CBT Training : PASS
7044 14:51:18.283700 Write leveling : PASS
7045 14:51:18.286738 RX DQS gating : PASS
7046 14:51:18.286820 RX DQ/DQS(RDDQC) : PASS
7047 14:51:18.290429 TX DQ/DQS : PASS
7048 14:51:18.293647 RX DATLAT : PASS
7049 14:51:18.293729 RX DQ/DQS(Engine): PASS
7050 14:51:18.296960 TX OE : NO K
7051 14:51:18.297043 All Pass.
7052 14:51:18.297108
7053 14:51:18.299859 CH 0, Rank 1
7054 14:51:18.299939 SW Impedance : PASS
7055 14:51:18.303463 DUTY Scan : NO K
7056 14:51:18.303543 ZQ Calibration : PASS
7057 14:51:18.306624 Jitter Meter : NO K
7058 14:51:18.310164 CBT Training : PASS
7059 14:51:18.310245 Write leveling : NO K
7060 14:51:18.313520 RX DQS gating : PASS
7061 14:51:18.317335 RX DQ/DQS(RDDQC) : PASS
7062 14:51:18.317417 TX DQ/DQS : PASS
7063 14:51:18.320274 RX DATLAT : PASS
7064 14:51:18.323524 RX DQ/DQS(Engine): PASS
7065 14:51:18.323604 TX OE : NO K
7066 14:51:18.327096 All Pass.
7067 14:51:18.327176
7068 14:51:18.327239 CH 1, Rank 0
7069 14:51:18.330126 SW Impedance : PASS
7070 14:51:18.330207 DUTY Scan : NO K
7071 14:51:18.333494 ZQ Calibration : PASS
7072 14:51:18.336886 Jitter Meter : NO K
7073 14:51:18.336966 CBT Training : PASS
7074 14:51:18.339999 Write leveling : PASS
7075 14:51:18.340078 RX DQS gating : PASS
7076 14:51:18.343703 RX DQ/DQS(RDDQC) : PASS
7077 14:51:18.346696 TX DQ/DQS : PASS
7078 14:51:18.346778 RX DATLAT : PASS
7079 14:51:18.350323 RX DQ/DQS(Engine): PASS
7080 14:51:18.353383 TX OE : NO K
7081 14:51:18.353465 All Pass.
7082 14:51:18.353528
7083 14:51:18.353586 CH 1, Rank 1
7084 14:51:18.356475 SW Impedance : PASS
7085 14:51:18.360153 DUTY Scan : NO K
7086 14:51:18.360234 ZQ Calibration : PASS
7087 14:51:18.363259 Jitter Meter : NO K
7088 14:51:18.366929 CBT Training : PASS
7089 14:51:18.367011 Write leveling : NO K
7090 14:51:18.370238 RX DQS gating : PASS
7091 14:51:18.373668 RX DQ/DQS(RDDQC) : PASS
7092 14:51:18.373750 TX DQ/DQS : PASS
7093 14:51:18.376607 RX DATLAT : PASS
7094 14:51:18.380102 RX DQ/DQS(Engine): PASS
7095 14:51:18.380184 TX OE : NO K
7096 14:51:18.380250 All Pass.
7097 14:51:18.383422
7098 14:51:18.383504 DramC Write-DBI off
7099 14:51:18.386835 PER_BANK_REFRESH: Hybrid Mode
7100 14:51:18.386918 TX_TRACKING: ON
7101 14:51:18.396505 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7102 14:51:18.400052 [FAST_K] Save calibration result to emmc
7103 14:51:18.403076 dramc_set_vcore_voltage set vcore to 725000
7104 14:51:18.406503 Read voltage for 1600, 0
7105 14:51:18.406583 Vio18 = 0
7106 14:51:18.409709 Vcore = 725000
7107 14:51:18.409790 Vdram = 0
7108 14:51:18.409853 Vddq = 0
7109 14:51:18.409912 Vmddr = 0
7110 14:51:18.417344 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7111 14:51:18.423349 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7112 14:51:18.423430 MEM_TYPE=3, freq_sel=13
7113 14:51:18.426332 sv_algorithm_assistance_LP4_3733
7114 14:51:18.429852 ============ PULL DRAM RESETB DOWN ============
7115 14:51:18.436222 ========== PULL DRAM RESETB DOWN end =========
7116 14:51:18.439919 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7117 14:51:18.443250 ===================================
7118 14:51:18.446449 LPDDR4 DRAM CONFIGURATION
7119 14:51:18.449953 ===================================
7120 14:51:18.450041 EX_ROW_EN[0] = 0x0
7121 14:51:18.452792 EX_ROW_EN[1] = 0x0
7122 14:51:18.456748 LP4Y_EN = 0x0
7123 14:51:18.456839 WORK_FSP = 0x1
7124 14:51:18.459574 WL = 0x5
7125 14:51:18.459655 RL = 0x5
7126 14:51:18.463008 BL = 0x2
7127 14:51:18.463091 RPST = 0x0
7128 14:51:18.465947 RD_PRE = 0x0
7129 14:51:18.466036 WR_PRE = 0x1
7130 14:51:18.469300 WR_PST = 0x1
7131 14:51:18.469406 DBI_WR = 0x0
7132 14:51:18.472940 DBI_RD = 0x0
7133 14:51:18.473020 OTF = 0x1
7134 14:51:18.476041 ===================================
7135 14:51:18.479657 ===================================
7136 14:51:18.482765 ANA top config
7137 14:51:18.485813 ===================================
7138 14:51:18.485895 DLL_ASYNC_EN = 0
7139 14:51:18.489617 ALL_SLAVE_EN = 0
7140 14:51:18.492865 NEW_RANK_MODE = 1
7141 14:51:18.496137 DLL_IDLE_MODE = 1
7142 14:51:18.499243 LP45_APHY_COMB_EN = 1
7143 14:51:18.499325 TX_ODT_DIS = 0
7144 14:51:18.502663 NEW_8X_MODE = 1
7145 14:51:18.505818 ===================================
7146 14:51:18.509438 ===================================
7147 14:51:18.512494 data_rate = 3200
7148 14:51:18.515749 CKR = 1
7149 14:51:18.519640 DQ_P2S_RATIO = 8
7150 14:51:18.522700 ===================================
7151 14:51:18.522781 CA_P2S_RATIO = 8
7152 14:51:18.525989 DQ_CA_OPEN = 0
7153 14:51:18.528923 DQ_SEMI_OPEN = 0
7154 14:51:18.532335 CA_SEMI_OPEN = 0
7155 14:51:18.535716 CA_FULL_RATE = 0
7156 14:51:18.539315 DQ_CKDIV4_EN = 0
7157 14:51:18.539396 CA_CKDIV4_EN = 0
7158 14:51:18.543006 CA_PREDIV_EN = 0
7159 14:51:18.545447 PH8_DLY = 12
7160 14:51:18.549234 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7161 14:51:18.552101 DQ_AAMCK_DIV = 4
7162 14:51:18.555916 CA_AAMCK_DIV = 4
7163 14:51:18.556020 CA_ADMCK_DIV = 4
7164 14:51:18.559257 DQ_TRACK_CA_EN = 0
7165 14:51:18.562579 CA_PICK = 1600
7166 14:51:18.565569 CA_MCKIO = 1600
7167 14:51:18.569136 MCKIO_SEMI = 0
7168 14:51:18.572445 PLL_FREQ = 3068
7169 14:51:18.575579 DQ_UI_PI_RATIO = 32
7170 14:51:18.575659 CA_UI_PI_RATIO = 0
7171 14:51:18.579157 ===================================
7172 14:51:18.582281 ===================================
7173 14:51:18.585847 memory_type:LPDDR4
7174 14:51:18.589020 GP_NUM : 10
7175 14:51:18.589101 SRAM_EN : 1
7176 14:51:18.592192 MD32_EN : 0
7177 14:51:18.595772 ===================================
7178 14:51:18.599012 [ANA_INIT] >>>>>>>>>>>>>>
7179 14:51:18.602473 <<<<<< [CONFIGURE PHASE]: ANA_TX
7180 14:51:18.605986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7181 14:51:18.609095 ===================================
7182 14:51:18.609176 data_rate = 3200,PCW = 0X7600
7183 14:51:18.612248 ===================================
7184 14:51:18.615231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7185 14:51:18.622153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 14:51:18.629093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 14:51:18.631914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7188 14:51:18.635856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7189 14:51:18.638691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7190 14:51:18.642296 [ANA_INIT] flow start
7191 14:51:18.645313 [ANA_INIT] PLL >>>>>>>>
7192 14:51:18.645394 [ANA_INIT] PLL <<<<<<<<
7193 14:51:18.648664 [ANA_INIT] MIDPI >>>>>>>>
7194 14:51:18.651916 [ANA_INIT] MIDPI <<<<<<<<
7195 14:51:18.651998 [ANA_INIT] DLL >>>>>>>>
7196 14:51:18.655320 [ANA_INIT] DLL <<<<<<<<
7197 14:51:18.658515 [ANA_INIT] flow end
7198 14:51:18.662541 ============ LP4 DIFF to SE enter ============
7199 14:51:18.665302 ============ LP4 DIFF to SE exit ============
7200 14:51:18.668353 [ANA_INIT] <<<<<<<<<<<<<
7201 14:51:18.672184 [Flow] Enable top DCM control >>>>>
7202 14:51:18.675461 [Flow] Enable top DCM control <<<<<
7203 14:51:18.678790 Enable DLL master slave shuffle
7204 14:51:18.682066 ==============================================================
7205 14:51:18.685586 Gating Mode config
7206 14:51:18.691616 ==============================================================
7207 14:51:18.691745 Config description:
7208 14:51:18.701462 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7209 14:51:18.708318 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7210 14:51:18.711900 SELPH_MODE 0: By rank 1: By Phase
7211 14:51:18.718237 ==============================================================
7212 14:51:18.721596 GAT_TRACK_EN = 1
7213 14:51:18.724917 RX_GATING_MODE = 2
7214 14:51:18.728196 RX_GATING_TRACK_MODE = 2
7215 14:51:18.731905 SELPH_MODE = 1
7216 14:51:18.735000 PICG_EARLY_EN = 1
7217 14:51:18.738716 VALID_LAT_VALUE = 1
7218 14:51:18.741903 ==============================================================
7219 14:51:18.744803 Enter into Gating configuration >>>>
7220 14:51:18.748372 Exit from Gating configuration <<<<
7221 14:51:18.751609 Enter into DVFS_PRE_config >>>>>
7222 14:51:18.761798 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7223 14:51:18.764963 Exit from DVFS_PRE_config <<<<<
7224 14:51:18.768675 Enter into PICG configuration >>>>
7225 14:51:18.771519 Exit from PICG configuration <<<<
7226 14:51:18.775092 [RX_INPUT] configuration >>>>>
7227 14:51:18.778572 [RX_INPUT] configuration <<<<<
7228 14:51:18.785735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7229 14:51:18.788280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7230 14:51:18.794982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 14:51:18.801810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 14:51:18.808567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 14:51:18.815124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 14:51:18.818301 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7235 14:51:18.821513 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7236 14:51:18.825166 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7237 14:51:18.831891 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7238 14:51:18.834658 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7239 14:51:18.837942 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 14:51:18.841588 ===================================
7241 14:51:18.845089 LPDDR4 DRAM CONFIGURATION
7242 14:51:18.848111 ===================================
7243 14:51:18.848197 EX_ROW_EN[0] = 0x0
7244 14:51:18.851225 EX_ROW_EN[1] = 0x0
7245 14:51:18.851310 LP4Y_EN = 0x0
7246 14:51:18.854981 WORK_FSP = 0x1
7247 14:51:18.858102 WL = 0x5
7248 14:51:18.858187 RL = 0x5
7249 14:51:18.861386 BL = 0x2
7250 14:51:18.861470 RPST = 0x0
7251 14:51:18.864446 RD_PRE = 0x0
7252 14:51:18.864526 WR_PRE = 0x1
7253 14:51:18.868233 WR_PST = 0x1
7254 14:51:18.868313 DBI_WR = 0x0
7255 14:51:18.871304 DBI_RD = 0x0
7256 14:51:18.871387 OTF = 0x1
7257 14:51:18.874439 ===================================
7258 14:51:18.877834 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7259 14:51:18.884549 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7260 14:51:18.888269 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 14:51:18.891181 ===================================
7262 14:51:18.894701 LPDDR4 DRAM CONFIGURATION
7263 14:51:18.897804 ===================================
7264 14:51:18.897890 EX_ROW_EN[0] = 0x10
7265 14:51:18.901429 EX_ROW_EN[1] = 0x0
7266 14:51:18.901514 LP4Y_EN = 0x0
7267 14:51:18.904735 WORK_FSP = 0x1
7268 14:51:18.904820 WL = 0x5
7269 14:51:18.907878 RL = 0x5
7270 14:51:18.907962 BL = 0x2
7271 14:51:18.910997 RPST = 0x0
7272 14:51:18.914667 RD_PRE = 0x0
7273 14:51:18.914752 WR_PRE = 0x1
7274 14:51:18.917772 WR_PST = 0x1
7275 14:51:18.917857 DBI_WR = 0x0
7276 14:51:18.921326 DBI_RD = 0x0
7277 14:51:18.921410 OTF = 0x1
7278 14:51:18.924266 ===================================
7279 14:51:18.931380 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7280 14:51:18.931462 ==
7281 14:51:18.934450 Dram Type= 6, Freq= 0, CH_0, rank 0
7282 14:51:18.938071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 14:51:18.938157 ==
7284 14:51:18.941620 [Duty_Offset_Calibration]
7285 14:51:18.941705 B0:2 B1:1 CA:1
7286 14:51:18.944472
7287 14:51:18.947474 [DutyScan_Calibration_Flow] k_type=0
7288 14:51:18.955870
7289 14:51:18.955958 ==CLK 0==
7290 14:51:18.958944 Final CLK duty delay cell = 0
7291 14:51:18.962802 [0] MAX Duty = 5156%(X100), DQS PI = 22
7292 14:51:18.965585 [0] MIN Duty = 4907%(X100), DQS PI = 0
7293 14:51:18.965667 [0] AVG Duty = 5031%(X100)
7294 14:51:18.969259
7295 14:51:18.972254 CH0 CLK Duty spec in!! Max-Min= 249%
7296 14:51:18.975822 [DutyScan_Calibration_Flow] ====Done====
7297 14:51:18.975904
7298 14:51:18.979029 [DutyScan_Calibration_Flow] k_type=1
7299 14:51:18.994953
7300 14:51:18.995035 ==DQS 0 ==
7301 14:51:18.998692 Final DQS duty delay cell = -4
7302 14:51:19.001462 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7303 14:51:19.005193 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7304 14:51:19.008392 [-4] AVG Duty = 4891%(X100)
7305 14:51:19.008476
7306 14:51:19.008539 ==DQS 1 ==
7307 14:51:19.011982 Final DQS duty delay cell = 0
7308 14:51:19.014872 [0] MAX Duty = 5187%(X100), DQS PI = 20
7309 14:51:19.018494 [0] MIN Duty = 5031%(X100), DQS PI = 50
7310 14:51:19.021741 [0] AVG Duty = 5109%(X100)
7311 14:51:19.021823
7312 14:51:19.025179 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7313 14:51:19.025261
7314 14:51:19.028316 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7315 14:51:19.032149 [DutyScan_Calibration_Flow] ====Done====
7316 14:51:19.032261
7317 14:51:19.034589 [DutyScan_Calibration_Flow] k_type=3
7318 14:51:19.051782
7319 14:51:19.051874 ==DQM 0 ==
7320 14:51:19.054814 Final DQM duty delay cell = 0
7321 14:51:19.058399 [0] MAX Duty = 5187%(X100), DQS PI = 26
7322 14:51:19.061438 [0] MIN Duty = 4907%(X100), DQS PI = 56
7323 14:51:19.065295 [0] AVG Duty = 5047%(X100)
7324 14:51:19.065385
7325 14:51:19.065452 ==DQM 1 ==
7326 14:51:19.068516 Final DQM duty delay cell = -4
7327 14:51:19.071848 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7328 14:51:19.074731 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7329 14:51:19.078375 [-4] AVG Duty = 4875%(X100)
7330 14:51:19.078457
7331 14:51:19.081538 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7332 14:51:19.081620
7333 14:51:19.084774 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7334 14:51:19.088612 [DutyScan_Calibration_Flow] ====Done====
7335 14:51:19.088693
7336 14:51:19.091645 [DutyScan_Calibration_Flow] k_type=2
7337 14:51:19.108819
7338 14:51:19.108902 ==DQ 0 ==
7339 14:51:19.112754 Final DQ duty delay cell = 0
7340 14:51:19.115845 [0] MAX Duty = 5062%(X100), DQS PI = 24
7341 14:51:19.118660 [0] MIN Duty = 4907%(X100), DQS PI = 0
7342 14:51:19.118742 [0] AVG Duty = 4984%(X100)
7343 14:51:19.122465
7344 14:51:19.122546 ==DQ 1 ==
7345 14:51:19.125529 Final DQ duty delay cell = 0
7346 14:51:19.129222 [0] MAX Duty = 5125%(X100), DQS PI = 6
7347 14:51:19.132453 [0] MIN Duty = 4907%(X100), DQS PI = 34
7348 14:51:19.132536 [0] AVG Duty = 5016%(X100)
7349 14:51:19.132601
7350 14:51:19.135275 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7351 14:51:19.139019
7352 14:51:19.142333 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7353 14:51:19.145649 [DutyScan_Calibration_Flow] ====Done====
7354 14:51:19.145735 ==
7355 14:51:19.148633 Dram Type= 6, Freq= 0, CH_1, rank 0
7356 14:51:19.152304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7357 14:51:19.152411 ==
7358 14:51:19.155647 [Duty_Offset_Calibration]
7359 14:51:19.155729 B0:1 B1:0 CA:0
7360 14:51:19.155793
7361 14:51:19.158852 [DutyScan_Calibration_Flow] k_type=0
7362 14:51:19.168376
7363 14:51:19.168464 ==CLK 0==
7364 14:51:19.171992 Final CLK duty delay cell = -4
7365 14:51:19.175184 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7366 14:51:19.178077 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7367 14:51:19.181551 [-4] AVG Duty = 4937%(X100)
7368 14:51:19.181632
7369 14:51:19.184927 CH1 CLK Duty spec in!! Max-Min= 125%
7370 14:51:19.188477 [DutyScan_Calibration_Flow] ====Done====
7371 14:51:19.188558
7372 14:51:19.191428 [DutyScan_Calibration_Flow] k_type=1
7373 14:51:19.208021
7374 14:51:19.208104 ==DQS 0 ==
7375 14:51:19.213054 Final DQS duty delay cell = 0
7376 14:51:19.215131 [0] MAX Duty = 5094%(X100), DQS PI = 20
7377 14:51:19.218221 [0] MIN Duty = 4844%(X100), DQS PI = 44
7378 14:51:19.221948 [0] AVG Duty = 4969%(X100)
7379 14:51:19.222030
7380 14:51:19.222094 ==DQS 1 ==
7381 14:51:19.225077 Final DQS duty delay cell = 0
7382 14:51:19.228697 [0] MAX Duty = 5249%(X100), DQS PI = 16
7383 14:51:19.231624 [0] MIN Duty = 4969%(X100), DQS PI = 6
7384 14:51:19.234749 [0] AVG Duty = 5109%(X100)
7385 14:51:19.234830
7386 14:51:19.238653 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7387 14:51:19.238734
7388 14:51:19.241593 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7389 14:51:19.245221 [DutyScan_Calibration_Flow] ====Done====
7390 14:51:19.245302
7391 14:51:19.247983 [DutyScan_Calibration_Flow] k_type=3
7392 14:51:19.265467
7393 14:51:19.265549 ==DQM 0 ==
7394 14:51:19.269153 Final DQM duty delay cell = 0
7395 14:51:19.271942 [0] MAX Duty = 5218%(X100), DQS PI = 18
7396 14:51:19.275422 [0] MIN Duty = 4969%(X100), DQS PI = 48
7397 14:51:19.275503 [0] AVG Duty = 5093%(X100)
7398 14:51:19.278836
7399 14:51:19.278917 ==DQM 1 ==
7400 14:51:19.282438 Final DQM duty delay cell = 0
7401 14:51:19.285423 [0] MAX Duty = 5093%(X100), DQS PI = 16
7402 14:51:19.288670 [0] MIN Duty = 4938%(X100), DQS PI = 8
7403 14:51:19.288753 [0] AVG Duty = 5015%(X100)
7404 14:51:19.288817
7405 14:51:19.295110 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7406 14:51:19.295191
7407 14:51:19.298712 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7408 14:51:19.302949 [DutyScan_Calibration_Flow] ====Done====
7409 14:51:19.303030
7410 14:51:19.305095 [DutyScan_Calibration_Flow] k_type=2
7411 14:51:19.321150
7412 14:51:19.321234 ==DQ 0 ==
7413 14:51:19.324654 Final DQ duty delay cell = -4
7414 14:51:19.327956 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7415 14:51:19.331087 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7416 14:51:19.334830 [-4] AVG Duty = 4937%(X100)
7417 14:51:19.334910
7418 14:51:19.334973 ==DQ 1 ==
7419 14:51:19.338013 Final DQ duty delay cell = 0
7420 14:51:19.341437 [0] MAX Duty = 5125%(X100), DQS PI = 20
7421 14:51:19.344589 [0] MIN Duty = 4938%(X100), DQS PI = 8
7422 14:51:19.344671 [0] AVG Duty = 5031%(X100)
7423 14:51:19.347849
7424 14:51:19.351275 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7425 14:51:19.351356
7426 14:51:19.354837 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7427 14:51:19.357718 [DutyScan_Calibration_Flow] ====Done====
7428 14:51:19.361419 nWR fixed to 30
7429 14:51:19.361501 [ModeRegInit_LP4] CH0 RK0
7430 14:51:19.364707 [ModeRegInit_LP4] CH0 RK1
7431 14:51:19.367721 [ModeRegInit_LP4] CH1 RK0
7432 14:51:19.371601 [ModeRegInit_LP4] CH1 RK1
7433 14:51:19.371683 match AC timing 5
7434 14:51:19.374634 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7435 14:51:19.381310 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7436 14:51:19.384873 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7437 14:51:19.391247 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7438 14:51:19.394467 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7439 14:51:19.394548 [MiockJmeterHQA]
7440 14:51:19.394612
7441 14:51:19.397811 [DramcMiockJmeter] u1RxGatingPI = 0
7442 14:51:19.401481 0 : 4252, 4027
7443 14:51:19.401563 4 : 4363, 4137
7444 14:51:19.401629 8 : 4253, 4027
7445 14:51:19.404754 12 : 4368, 4140
7446 14:51:19.404836 16 : 4257, 4029
7447 14:51:19.408197 20 : 4255, 4029
7448 14:51:19.408281 24 : 4252, 4027
7449 14:51:19.411118 28 : 4371, 4139
7450 14:51:19.411200 32 : 4368, 4140
7451 14:51:19.414475 36 : 4363, 4137
7452 14:51:19.414558 40 : 4253, 4027
7453 14:51:19.414623 44 : 4252, 4027
7454 14:51:19.417666 48 : 4360, 4138
7455 14:51:19.417749 52 : 4252, 4027
7456 14:51:19.421149 56 : 4360, 4137
7457 14:51:19.421232 60 : 4255, 4029
7458 14:51:19.425128 64 : 4363, 4140
7459 14:51:19.425211 68 : 4250, 4027
7460 14:51:19.427848 72 : 4250, 4027
7461 14:51:19.427930 76 : 4360, 4137
7462 14:51:19.427996 80 : 4250, 4027
7463 14:51:19.431677 84 : 4361, 4137
7464 14:51:19.431760 88 : 4363, 131
7465 14:51:19.434972 92 : 4249, 0
7466 14:51:19.435055 96 : 4252, 0
7467 14:51:19.435120 100 : 4252, 0
7468 14:51:19.437685 104 : 4363, 0
7469 14:51:19.437768 108 : 4252, 0
7470 14:51:19.441280 112 : 4252, 0
7471 14:51:19.441363 116 : 4360, 0
7472 14:51:19.441429 120 : 4360, 0
7473 14:51:19.444872 124 : 4250, 0
7474 14:51:19.444955 128 : 4252, 0
7475 14:51:19.445020 132 : 4255, 0
7476 14:51:19.448044 136 : 4252, 0
7477 14:51:19.448126 140 : 4250, 0
7478 14:51:19.451003 144 : 4250, 0
7479 14:51:19.451122 148 : 4252, 0
7480 14:51:19.451215 152 : 4361, 0
7481 14:51:19.454274 156 : 4361, 0
7482 14:51:19.454357 160 : 4250, 0
7483 14:51:19.457748 164 : 4252, 0
7484 14:51:19.457830 168 : 4360, 0
7485 14:51:19.457895 172 : 4250, 0
7486 14:51:19.461323 176 : 4257, 0
7487 14:51:19.461405 180 : 4250, 0
7488 14:51:19.464505 184 : 4361, 0
7489 14:51:19.464588 188 : 4250, 0
7490 14:51:19.464653 192 : 4360, 0
7491 14:51:19.467991 196 : 4250, 0
7492 14:51:19.468074 200 : 4250, 0
7493 14:51:19.471232 204 : 4361, 1145
7494 14:51:19.471315 208 : 4249, 3999
7495 14:51:19.471380 212 : 4361, 4138
7496 14:51:19.474374 216 : 4363, 4139
7497 14:51:19.474456 220 : 4360, 4137
7498 14:51:19.477474 224 : 4249, 4027
7499 14:51:19.477557 228 : 4363, 4140
7500 14:51:19.481034 232 : 4253, 4029
7501 14:51:19.481117 236 : 4250, 4027
7502 14:51:19.484645 240 : 4253, 4029
7503 14:51:19.484728 244 : 4253, 4029
7504 14:51:19.487658 248 : 4252, 4029
7505 14:51:19.487741 252 : 4360, 4137
7506 14:51:19.490747 256 : 4253, 4027
7507 14:51:19.490829 260 : 4250, 4027
7508 14:51:19.494257 264 : 4255, 4029
7509 14:51:19.494340 268 : 4363, 4139
7510 14:51:19.494404 272 : 4360, 4137
7511 14:51:19.497694 276 : 4249, 4027
7512 14:51:19.497777 280 : 4364, 4140
7513 14:51:19.500799 284 : 4253, 4029
7514 14:51:19.500882 288 : 4250, 4027
7515 14:51:19.503860 292 : 4252, 4027
7516 14:51:19.503942 296 : 4253, 4029
7517 14:51:19.507768 300 : 4250, 4027
7518 14:51:19.507850 304 : 4360, 4137
7519 14:51:19.510727 308 : 4255, 3972
7520 14:51:19.510813 312 : 4252, 2026
7521 14:51:19.510913
7522 14:51:19.514166 MIOCK jitter meter ch=0
7523 14:51:19.514247
7524 14:51:19.517322 1T = (312-88) = 224 dly cells
7525 14:51:19.523895 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7526 14:51:19.523977 ==
7527 14:51:19.527023 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 14:51:19.530609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 14:51:19.530692 ==
7530 14:51:19.534012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 14:51:19.540913 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 14:51:19.543973 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 14:51:19.550293 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 14:51:19.558707 [CA 0] Center 42 (12~73) winsize 62
7535 14:51:19.562121 [CA 1] Center 42 (12~73) winsize 62
7536 14:51:19.565287 [CA 2] Center 38 (8~68) winsize 61
7537 14:51:19.568752 [CA 3] Center 37 (8~67) winsize 60
7538 14:51:19.571972 [CA 4] Center 36 (6~66) winsize 61
7539 14:51:19.575326 [CA 5] Center 35 (6~64) winsize 59
7540 14:51:19.575408
7541 14:51:19.578807 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7542 14:51:19.578889
7543 14:51:19.582018 [CATrainingPosCal] consider 1 rank data
7544 14:51:19.585597 u2DelayCellTimex100 = 290/100 ps
7545 14:51:19.592284 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7546 14:51:19.595169 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7547 14:51:19.598609 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7548 14:51:19.602021 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7549 14:51:19.605266 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7550 14:51:19.608849 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7551 14:51:19.608932
7552 14:51:19.612087 CA PerBit enable=1, Macro0, CA PI delay=35
7553 14:51:19.612194
7554 14:51:19.615345 [CBTSetCACLKResult] CA Dly = 35
7555 14:51:19.618490 CS Dly: 9 (0~40)
7556 14:51:19.622203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 14:51:19.625292 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 14:51:19.625372 ==
7559 14:51:19.629010 Dram Type= 6, Freq= 0, CH_0, rank 1
7560 14:51:19.632065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 14:51:19.634915 ==
7562 14:51:19.638761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 14:51:19.642006 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 14:51:19.648360 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 14:51:19.652206 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 14:51:19.662359 [CA 0] Center 43 (13~73) winsize 61
7567 14:51:19.665846 [CA 1] Center 43 (13~73) winsize 61
7568 14:51:19.669182 [CA 2] Center 38 (8~68) winsize 61
7569 14:51:19.672102 [CA 3] Center 38 (8~68) winsize 61
7570 14:51:19.675612 [CA 4] Center 36 (6~66) winsize 61
7571 14:51:19.679187 [CA 5] Center 35 (6~65) winsize 60
7572 14:51:19.679282
7573 14:51:19.682072 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7574 14:51:19.682156
7575 14:51:19.685714 [CATrainingPosCal] consider 2 rank data
7576 14:51:19.688937 u2DelayCellTimex100 = 290/100 ps
7577 14:51:19.692462 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7578 14:51:19.698990 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7579 14:51:19.702531 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7580 14:51:19.705378 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7581 14:51:19.708689 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7582 14:51:19.712208 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7583 14:51:19.712298
7584 14:51:19.715375 CA PerBit enable=1, Macro0, CA PI delay=35
7585 14:51:19.715461
7586 14:51:19.718819 [CBTSetCACLKResult] CA Dly = 35
7587 14:51:19.722580 CS Dly: 9 (0~41)
7588 14:51:19.725664 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 14:51:19.728527 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 14:51:19.728609
7591 14:51:19.732354 ----->DramcWriteLeveling(PI) begin...
7592 14:51:19.732440 ==
7593 14:51:19.735384 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 14:51:19.739080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 14:51:19.741916 ==
7596 14:51:19.741998 Write leveling (Byte 0): 35 => 35
7597 14:51:19.745434 Write leveling (Byte 1): 29 => 29
7598 14:51:19.749008 DramcWriteLeveling(PI) end<-----
7599 14:51:19.749091
7600 14:51:19.749155 ==
7601 14:51:19.751911 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 14:51:19.758862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 14:51:19.758974 ==
7604 14:51:19.759073 [Gating] SW mode calibration
7605 14:51:19.768615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7606 14:51:19.771882 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7607 14:51:19.774978 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7608 14:51:19.781972 1 4 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7609 14:51:19.785607 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7610 14:51:19.788538 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7611 14:51:19.795686 1 4 16 | B1->B0 | 2322 3535 | 1 1 | (0 0) (1 1)
7612 14:51:19.798505 1 4 20 | B1->B0 | 3333 3939 | 0 0 | (0 0) (0 0)
7613 14:51:19.802428 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7614 14:51:19.808540 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7615 14:51:19.811723 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 14:51:19.815239 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7617 14:51:19.822647 1 5 8 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
7618 14:51:19.825334 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7619 14:51:19.828624 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7620 14:51:19.835054 1 5 20 | B1->B0 | 2929 2626 | 0 0 | (0 1) (0 0)
7621 14:51:19.838681 1 5 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
7622 14:51:19.841890 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7623 14:51:19.848683 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 14:51:19.852517 1 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7625 14:51:19.855124 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7626 14:51:19.861793 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7627 14:51:19.865519 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7628 14:51:19.868543 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 14:51:19.871950 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 14:51:19.878504 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 14:51:19.882089 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 14:51:19.884968 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 14:51:19.891847 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 14:51:19.895317 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 14:51:19.898501 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 14:51:19.904958 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 14:51:19.908118 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 14:51:19.911772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 14:51:19.918277 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 14:51:19.921896 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 14:51:19.924880 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 14:51:19.931845 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 14:51:19.934904 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 14:51:19.938146 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 14:51:19.945391 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 14:51:19.948209 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 14:51:19.951580 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 14:51:19.958842 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 14:51:19.961860 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 14:51:19.965287 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 14:51:19.971790 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7652 14:51:19.971873 Total UI for P1: 0, mck2ui 16
7653 14:51:19.978177 best dqsien dly found for B0: ( 1, 9, 12)
7654 14:51:19.981700 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 14:51:19.984935 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 14:51:19.988292 Total UI for P1: 0, mck2ui 16
7657 14:51:19.991568 best dqsien dly found for B1: ( 1, 9, 20)
7658 14:51:19.995217 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7659 14:51:19.998266 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7660 14:51:19.998347
7661 14:51:20.001483 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7662 14:51:20.008510 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7663 14:51:20.008594 [Gating] SW calibration Done
7664 14:51:20.011599 ==
7665 14:51:20.011681 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 14:51:20.018300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 14:51:20.018387 ==
7668 14:51:20.018452 RX Vref Scan: 0
7669 14:51:20.018513
7670 14:51:20.021281 RX Vref 0 -> 0, step: 1
7671 14:51:20.021363
7672 14:51:20.024896 RX Delay 0 -> 252, step: 8
7673 14:51:20.028558 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7674 14:51:20.031333 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7675 14:51:20.034778 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7676 14:51:20.041287 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7677 14:51:20.044813 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7678 14:51:20.048126 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7679 14:51:20.051038 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7680 14:51:20.054689 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7681 14:51:20.058084 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7682 14:51:20.064717 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7683 14:51:20.068010 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7684 14:51:20.071038 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7685 14:51:20.074453 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7686 14:51:20.081192 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7687 14:51:20.084569 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7688 14:51:20.087685 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7689 14:51:20.087767 ==
7690 14:51:20.090952 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 14:51:20.094770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 14:51:20.094854 ==
7693 14:51:20.097634 DQS Delay:
7694 14:51:20.097716 DQS0 = 0, DQS1 = 0
7695 14:51:20.100927 DQM Delay:
7696 14:51:20.101008 DQM0 = 137, DQM1 = 129
7697 14:51:20.101073 DQ Delay:
7698 14:51:20.107429 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7699 14:51:20.111276 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7700 14:51:20.114039 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7701 14:51:20.117740 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
7702 14:51:20.117823
7703 14:51:20.117887
7704 14:51:20.117947 ==
7705 14:51:20.120791 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 14:51:20.124582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 14:51:20.124664 ==
7708 14:51:20.124728
7709 14:51:20.124787
7710 14:51:20.127540 TX Vref Scan disable
7711 14:51:20.130815 == TX Byte 0 ==
7712 14:51:20.134491 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7713 14:51:20.137462 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7714 14:51:20.141024 == TX Byte 1 ==
7715 14:51:20.144246 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7716 14:51:20.147645 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7717 14:51:20.147744 ==
7718 14:51:20.150558 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 14:51:20.157328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 14:51:20.157423 ==
7721 14:51:20.167929
7722 14:51:20.171504 TX Vref early break, caculate TX vref
7723 14:51:20.175180 TX Vref=16, minBit 4, minWin=22, winSum=379
7724 14:51:20.178374 TX Vref=18, minBit 3, minWin=23, winSum=390
7725 14:51:20.181252 TX Vref=20, minBit 0, minWin=24, winSum=400
7726 14:51:20.184823 TX Vref=22, minBit 0, minWin=24, winSum=406
7727 14:51:20.187908 TX Vref=24, minBit 7, minWin=25, winSum=416
7728 14:51:20.194567 TX Vref=26, minBit 1, minWin=25, winSum=424
7729 14:51:20.197949 TX Vref=28, minBit 1, minWin=25, winSum=425
7730 14:51:20.201025 TX Vref=30, minBit 7, minWin=24, winSum=416
7731 14:51:20.204440 TX Vref=32, minBit 6, minWin=23, winSum=400
7732 14:51:20.210994 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
7733 14:51:20.211094
7734 14:51:20.214990 Final TX Range 0 Vref 28
7735 14:51:20.215085
7736 14:51:20.215150 ==
7737 14:51:20.218021 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 14:51:20.221136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 14:51:20.221225 ==
7740 14:51:20.221290
7741 14:51:20.221349
7742 14:51:20.224125 TX Vref Scan disable
7743 14:51:20.227808 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7744 14:51:20.230644 == TX Byte 0 ==
7745 14:51:20.234409 u2DelayCellOfst[0]=10 cells (3 PI)
7746 14:51:20.237730 u2DelayCellOfst[1]=13 cells (4 PI)
7747 14:51:20.240875 u2DelayCellOfst[2]=10 cells (3 PI)
7748 14:51:20.244661 u2DelayCellOfst[3]=10 cells (3 PI)
7749 14:51:20.247873 u2DelayCellOfst[4]=6 cells (2 PI)
7750 14:51:20.251221 u2DelayCellOfst[5]=0 cells (0 PI)
7751 14:51:20.251308 u2DelayCellOfst[6]=16 cells (5 PI)
7752 14:51:20.254260 u2DelayCellOfst[7]=16 cells (5 PI)
7753 14:51:20.260850 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7754 14:51:20.263985 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7755 14:51:20.264077 == TX Byte 1 ==
7756 14:51:20.267709 u2DelayCellOfst[8]=0 cells (0 PI)
7757 14:51:20.270662 u2DelayCellOfst[9]=3 cells (1 PI)
7758 14:51:20.274296 u2DelayCellOfst[10]=6 cells (2 PI)
7759 14:51:20.277651 u2DelayCellOfst[11]=6 cells (2 PI)
7760 14:51:20.280861 u2DelayCellOfst[12]=10 cells (3 PI)
7761 14:51:20.284701 u2DelayCellOfst[13]=13 cells (4 PI)
7762 14:51:20.287574 u2DelayCellOfst[14]=13 cells (4 PI)
7763 14:51:20.291145 u2DelayCellOfst[15]=10 cells (3 PI)
7764 14:51:20.294190 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7765 14:51:20.297501 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7766 14:51:20.300350 DramC Write-DBI on
7767 14:51:20.300439 ==
7768 14:51:20.304195 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 14:51:20.307290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 14:51:20.307374 ==
7771 14:51:20.307439
7772 14:51:20.307499
7773 14:51:20.310359 TX Vref Scan disable
7774 14:51:20.313949 == TX Byte 0 ==
7775 14:51:20.317453 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7776 14:51:20.320841 == TX Byte 1 ==
7777 14:51:20.324223 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7778 14:51:20.324305 DramC Write-DBI off
7779 14:51:20.324377
7780 14:51:20.327247 [DATLAT]
7781 14:51:20.327328 Freq=1600, CH0 RK0
7782 14:51:20.327393
7783 14:51:20.330594 DATLAT Default: 0xf
7784 14:51:20.330675 0, 0xFFFF, sum = 0
7785 14:51:20.333857 1, 0xFFFF, sum = 0
7786 14:51:20.333941 2, 0xFFFF, sum = 0
7787 14:51:20.337225 3, 0xFFFF, sum = 0
7788 14:51:20.337308 4, 0xFFFF, sum = 0
7789 14:51:20.340291 5, 0xFFFF, sum = 0
7790 14:51:20.340416 6, 0xFFFF, sum = 0
7791 14:51:20.344126 7, 0xFFFF, sum = 0
7792 14:51:20.344210 8, 0xFFFF, sum = 0
7793 14:51:20.346909 9, 0xFFFF, sum = 0
7794 14:51:20.350752 10, 0xFFFF, sum = 0
7795 14:51:20.350842 11, 0xFFFF, sum = 0
7796 14:51:20.353982 12, 0xFFFF, sum = 0
7797 14:51:20.354072 13, 0xFFFF, sum = 0
7798 14:51:20.356941 14, 0x0, sum = 1
7799 14:51:20.357028 15, 0x0, sum = 2
7800 14:51:20.360845 16, 0x0, sum = 3
7801 14:51:20.360935 17, 0x0, sum = 4
7802 14:51:20.361002 best_step = 15
7803 14:51:20.363866
7804 14:51:20.363950 ==
7805 14:51:20.367286 Dram Type= 6, Freq= 0, CH_0, rank 0
7806 14:51:20.370497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7807 14:51:20.370586 ==
7808 14:51:20.370652 RX Vref Scan: 1
7809 14:51:20.370713
7810 14:51:20.373458 Set Vref Range= 24 -> 127
7811 14:51:20.373574
7812 14:51:20.377194 RX Vref 24 -> 127, step: 1
7813 14:51:20.377283
7814 14:51:20.380759 RX Delay 19 -> 252, step: 4
7815 14:51:20.380846
7816 14:51:20.383615 Set Vref, RX VrefLevel [Byte0]: 24
7817 14:51:20.386836 [Byte1]: 24
7818 14:51:20.386921
7819 14:51:20.390674 Set Vref, RX VrefLevel [Byte0]: 25
7820 14:51:20.393705 [Byte1]: 25
7821 14:51:20.393787
7822 14:51:20.396970 Set Vref, RX VrefLevel [Byte0]: 26
7823 14:51:20.400659 [Byte1]: 26
7824 14:51:20.403739
7825 14:51:20.403819 Set Vref, RX VrefLevel [Byte0]: 27
7826 14:51:20.406814 [Byte1]: 27
7827 14:51:20.411918
7828 14:51:20.411999 Set Vref, RX VrefLevel [Byte0]: 28
7829 14:51:20.415029 [Byte1]: 28
7830 14:51:20.419213
7831 14:51:20.419293 Set Vref, RX VrefLevel [Byte0]: 29
7832 14:51:20.422165 [Byte1]: 29
7833 14:51:20.426649
7834 14:51:20.426729 Set Vref, RX VrefLevel [Byte0]: 30
7835 14:51:20.430144 [Byte1]: 30
7836 14:51:20.433821
7837 14:51:20.433914 Set Vref, RX VrefLevel [Byte0]: 31
7838 14:51:20.437754 [Byte1]: 31
7839 14:51:20.441671
7840 14:51:20.441765 Set Vref, RX VrefLevel [Byte0]: 32
7841 14:51:20.445027 [Byte1]: 32
7842 14:51:20.449351
7843 14:51:20.449448 Set Vref, RX VrefLevel [Byte0]: 33
7844 14:51:20.452348 [Byte1]: 33
7845 14:51:20.457123
7846 14:51:20.457232 Set Vref, RX VrefLevel [Byte0]: 34
7847 14:51:20.460218 [Byte1]: 34
7848 14:51:20.464503
7849 14:51:20.464604 Set Vref, RX VrefLevel [Byte0]: 35
7850 14:51:20.467596 [Byte1]: 35
7851 14:51:20.471626
7852 14:51:20.471730 Set Vref, RX VrefLevel [Byte0]: 36
7853 14:51:20.475136 [Byte1]: 36
7854 14:51:20.479525
7855 14:51:20.479627 Set Vref, RX VrefLevel [Byte0]: 37
7856 14:51:20.482958 [Byte1]: 37
7857 14:51:20.487143
7858 14:51:20.487245 Set Vref, RX VrefLevel [Byte0]: 38
7859 14:51:20.490390 [Byte1]: 38
7860 14:51:20.494815
7861 14:51:20.494898 Set Vref, RX VrefLevel [Byte0]: 39
7862 14:51:20.498283 [Byte1]: 39
7863 14:51:20.502499
7864 14:51:20.502580 Set Vref, RX VrefLevel [Byte0]: 40
7865 14:51:20.505503 [Byte1]: 40
7866 14:51:20.509975
7867 14:51:20.510056 Set Vref, RX VrefLevel [Byte0]: 41
7868 14:51:20.513604 [Byte1]: 41
7869 14:51:20.517263
7870 14:51:20.520806 Set Vref, RX VrefLevel [Byte0]: 42
7871 14:51:20.523734 [Byte1]: 42
7872 14:51:20.523816
7873 14:51:20.527009 Set Vref, RX VrefLevel [Byte0]: 43
7874 14:51:20.530650 [Byte1]: 43
7875 14:51:20.530731
7876 14:51:20.533899 Set Vref, RX VrefLevel [Byte0]: 44
7877 14:51:20.536728 [Byte1]: 44
7878 14:51:20.536813
7879 14:51:20.540305 Set Vref, RX VrefLevel [Byte0]: 45
7880 14:51:20.543496 [Byte1]: 45
7881 14:51:20.548059
7882 14:51:20.548141 Set Vref, RX VrefLevel [Byte0]: 46
7883 14:51:20.550856 [Byte1]: 46
7884 14:51:20.555031
7885 14:51:20.555112 Set Vref, RX VrefLevel [Byte0]: 47
7886 14:51:20.558571 [Byte1]: 47
7887 14:51:20.562813
7888 14:51:20.562893 Set Vref, RX VrefLevel [Byte0]: 48
7889 14:51:20.566283 [Byte1]: 48
7890 14:51:20.570565
7891 14:51:20.570646 Set Vref, RX VrefLevel [Byte0]: 49
7892 14:51:20.573797 [Byte1]: 49
7893 14:51:20.578431
7894 14:51:20.578512 Set Vref, RX VrefLevel [Byte0]: 50
7895 14:51:20.581362 [Byte1]: 50
7896 14:51:20.585597
7897 14:51:20.585677 Set Vref, RX VrefLevel [Byte0]: 51
7898 14:51:20.588893 [Byte1]: 51
7899 14:51:20.592928
7900 14:51:20.593009 Set Vref, RX VrefLevel [Byte0]: 52
7901 14:51:20.596345 [Byte1]: 52
7902 14:51:20.601197
7903 14:51:20.601281 Set Vref, RX VrefLevel [Byte0]: 53
7904 14:51:20.604269 [Byte1]: 53
7905 14:51:20.608122
7906 14:51:20.608203 Set Vref, RX VrefLevel [Byte0]: 54
7907 14:51:20.611328 [Byte1]: 54
7908 14:51:20.615678
7909 14:51:20.615759 Set Vref, RX VrefLevel [Byte0]: 55
7910 14:51:20.619537 [Byte1]: 55
7911 14:51:20.623576
7912 14:51:20.623656 Set Vref, RX VrefLevel [Byte0]: 56
7913 14:51:20.626669 [Byte1]: 56
7914 14:51:20.630859
7915 14:51:20.630949 Set Vref, RX VrefLevel [Byte0]: 57
7916 14:51:20.634493 [Byte1]: 57
7917 14:51:20.638850
7918 14:51:20.638932 Set Vref, RX VrefLevel [Byte0]: 58
7919 14:51:20.642153 [Byte1]: 58
7920 14:51:20.646538
7921 14:51:20.646619 Set Vref, RX VrefLevel [Byte0]: 59
7922 14:51:20.649693 [Byte1]: 59
7923 14:51:20.654013
7924 14:51:20.654097 Set Vref, RX VrefLevel [Byte0]: 60
7925 14:51:20.657515 [Byte1]: 60
7926 14:51:20.661179
7927 14:51:20.661341 Set Vref, RX VrefLevel [Byte0]: 61
7928 14:51:20.664810 [Byte1]: 61
7929 14:51:20.669092
7930 14:51:20.669245 Set Vref, RX VrefLevel [Byte0]: 62
7931 14:51:20.671918 [Byte1]: 62
7932 14:51:20.676246
7933 14:51:20.676405 Set Vref, RX VrefLevel [Byte0]: 63
7934 14:51:20.680088 [Byte1]: 63
7935 14:51:20.684151
7936 14:51:20.684305 Set Vref, RX VrefLevel [Byte0]: 64
7937 14:51:20.687357 [Byte1]: 64
7938 14:51:20.691533
7939 14:51:20.691682 Set Vref, RX VrefLevel [Byte0]: 65
7940 14:51:20.694550 [Byte1]: 65
7941 14:51:20.699368
7942 14:51:20.699450 Set Vref, RX VrefLevel [Byte0]: 66
7943 14:51:20.702684 [Byte1]: 66
7944 14:51:20.706948
7945 14:51:20.707028 Set Vref, RX VrefLevel [Byte0]: 67
7946 14:51:20.710100 [Byte1]: 67
7947 14:51:20.714409
7948 14:51:20.714489 Set Vref, RX VrefLevel [Byte0]: 68
7949 14:51:20.717854 [Byte1]: 68
7950 14:51:20.722120
7951 14:51:20.722199 Set Vref, RX VrefLevel [Byte0]: 69
7952 14:51:20.725312 [Byte1]: 69
7953 14:51:20.729631
7954 14:51:20.729711 Set Vref, RX VrefLevel [Byte0]: 70
7955 14:51:20.733042 [Byte1]: 70
7956 14:51:20.737035
7957 14:51:20.737114 Set Vref, RX VrefLevel [Byte0]: 71
7958 14:51:20.740152 [Byte1]: 71
7959 14:51:20.744756
7960 14:51:20.744836 Set Vref, RX VrefLevel [Byte0]: 72
7961 14:51:20.747841 [Byte1]: 72
7962 14:51:20.752127
7963 14:51:20.752207 Set Vref, RX VrefLevel [Byte0]: 73
7964 14:51:20.755653 [Byte1]: 73
7965 14:51:20.760052
7966 14:51:20.760134 Set Vref, RX VrefLevel [Byte0]: 74
7967 14:51:20.763141 [Byte1]: 74
7968 14:51:20.767443
7969 14:51:20.767523 Set Vref, RX VrefLevel [Byte0]: 75
7970 14:51:20.771366 [Byte1]: 75
7971 14:51:20.774761
7972 14:51:20.774841 Final RX Vref Byte 0 = 55 to rank0
7973 14:51:20.778375 Final RX Vref Byte 1 = 59 to rank0
7974 14:51:20.781148 Final RX Vref Byte 0 = 55 to rank1
7975 14:51:20.785150 Final RX Vref Byte 1 = 59 to rank1==
7976 14:51:20.787847 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 14:51:20.795005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 14:51:20.795086 ==
7979 14:51:20.795150 DQS Delay:
7980 14:51:20.795208 DQS0 = 0, DQS1 = 0
7981 14:51:20.798028 DQM Delay:
7982 14:51:20.798108 DQM0 = 134, DQM1 = 127
7983 14:51:20.801892 DQ Delay:
7984 14:51:20.804850 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =132
7985 14:51:20.808227 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7986 14:51:20.811587 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7987 14:51:20.814371 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7988 14:51:20.814464
7989 14:51:20.814555
7990 14:51:20.814640
7991 14:51:20.818353 [DramC_TX_OE_Calibration] TA2
7992 14:51:20.821380 Original DQ_B0 (3 6) =30, OEN = 27
7993 14:51:20.824316 Original DQ_B1 (3 6) =30, OEN = 27
7994 14:51:20.828283 24, 0x0, End_B0=24 End_B1=24
7995 14:51:20.828376 25, 0x0, End_B0=25 End_B1=25
7996 14:51:20.831337 26, 0x0, End_B0=26 End_B1=26
7997 14:51:20.834674 27, 0x0, End_B0=27 End_B1=27
7998 14:51:20.837877 28, 0x0, End_B0=28 End_B1=28
7999 14:51:20.841578 29, 0x0, End_B0=29 End_B1=29
8000 14:51:20.841661 30, 0x0, End_B0=30 End_B1=30
8001 14:51:20.844451 31, 0x4545, End_B0=30 End_B1=30
8002 14:51:20.847798 Byte0 end_step=30 best_step=27
8003 14:51:20.851030 Byte1 end_step=30 best_step=27
8004 14:51:20.854743 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 14:51:20.857636 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 14:51:20.857719
8007 14:51:20.857782
8008 14:51:20.864290 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8009 14:51:20.867461 CH0 RK0: MR19=303, MR18=2521
8010 14:51:20.874504 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8011 14:51:20.874614
8012 14:51:20.877483 ----->DramcWriteLeveling(PI) begin...
8013 14:51:20.877568 ==
8014 14:51:20.880800 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 14:51:20.884222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 14:51:20.884307 ==
8017 14:51:20.887588 Write leveling (Byte 0): 36 => 36
8018 14:51:20.891155 Write leveling (Byte 1): 28 => 28
8019 14:51:20.894072 DramcWriteLeveling(PI) end<-----
8020 14:51:20.894155
8021 14:51:20.894219 ==
8022 14:51:20.897448 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 14:51:20.901007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 14:51:20.901089 ==
8025 14:51:20.904237 [Gating] SW mode calibration
8026 14:51:20.910863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 14:51:20.917439 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 14:51:20.920520 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8029 14:51:20.927400 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8030 14:51:20.930332 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8031 14:51:20.934160 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8032 14:51:20.940716 1 4 16 | B1->B0 | 2e2e 3837 | 1 1 | (1 1) (1 1)
8033 14:51:20.943785 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8034 14:51:20.947030 1 4 24 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (0 0)
8035 14:51:20.953920 1 4 28 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
8036 14:51:20.957090 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8037 14:51:20.960703 1 5 4 | B1->B0 | 3434 3b3b | 1 1 | (1 1) (0 0)
8038 14:51:20.963890 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 14:51:20.970216 1 5 12 | B1->B0 | 3434 3938 | 1 1 | (1 0) (0 1)
8040 14:51:20.973746 1 5 16 | B1->B0 | 2f2f 2d2c | 0 1 | (0 0) (0 0)
8041 14:51:20.977161 1 5 20 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8042 14:51:20.983652 1 5 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8043 14:51:20.987386 1 5 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8044 14:51:20.990400 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8045 14:51:20.997061 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8046 14:51:21.000728 1 6 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8047 14:51:21.003846 1 6 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8048 14:51:21.010071 1 6 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (1 1)
8049 14:51:21.013709 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8050 14:51:21.017352 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 14:51:21.023905 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 14:51:21.026839 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 14:51:21.030127 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 14:51:21.036870 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 14:51:21.040555 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8056 14:51:21.043553 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8057 14:51:21.050310 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 14:51:21.053231 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 14:51:21.056687 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 14:51:21.063626 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 14:51:21.066647 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 14:51:21.070352 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 14:51:21.076763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 14:51:21.080224 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 14:51:21.083247 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 14:51:21.090059 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 14:51:21.092939 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 14:51:21.096625 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 14:51:21.103230 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 14:51:21.106423 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 14:51:21.109801 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8072 14:51:21.113045 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8073 14:51:21.119898 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 14:51:21.123632 Total UI for P1: 0, mck2ui 16
8075 14:51:21.126326 best dqsien dly found for B0: ( 1, 9, 14)
8076 14:51:21.129896 Total UI for P1: 0, mck2ui 16
8077 14:51:21.133188 best dqsien dly found for B1: ( 1, 9, 14)
8078 14:51:21.136316 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8079 14:51:21.139883 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8080 14:51:21.139967
8081 14:51:21.142988 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8082 14:51:21.146540 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 14:51:21.150137 [Gating] SW calibration Done
8084 14:51:21.150220 ==
8085 14:51:21.153025 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 14:51:21.156247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 14:51:21.156376 ==
8088 14:51:21.159729 RX Vref Scan: 0
8089 14:51:21.159810
8090 14:51:21.162792 RX Vref 0 -> 0, step: 1
8091 14:51:21.162878
8092 14:51:21.162943 RX Delay 0 -> 252, step: 8
8093 14:51:21.169323 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8094 14:51:21.172892 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8095 14:51:21.175946 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8096 14:51:21.179257 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8097 14:51:21.183007 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8098 14:51:21.188986 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8099 14:51:21.192601 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8100 14:51:21.195662 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8101 14:51:21.199571 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8102 14:51:21.202441 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8103 14:51:21.209213 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8104 14:51:21.212476 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8105 14:51:21.215913 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8106 14:51:21.218878 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8107 14:51:21.222520 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8108 14:51:21.229486 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8109 14:51:21.229571 ==
8110 14:51:21.232319 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 14:51:21.235612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 14:51:21.235697 ==
8113 14:51:21.235783 DQS Delay:
8114 14:51:21.238954 DQS0 = 0, DQS1 = 0
8115 14:51:21.239061 DQM Delay:
8116 14:51:21.242520 DQM0 = 136, DQM1 = 128
8117 14:51:21.242603 DQ Delay:
8118 14:51:21.245609 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8119 14:51:21.249067 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8120 14:51:21.252231 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8121 14:51:21.255614 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8122 14:51:21.259037
8123 14:51:21.259121
8124 14:51:21.259205 ==
8125 14:51:21.262599 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 14:51:21.265587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 14:51:21.265671 ==
8128 14:51:21.265757
8129 14:51:21.265836
8130 14:51:21.269151 TX Vref Scan disable
8131 14:51:21.269235 == TX Byte 0 ==
8132 14:51:21.275460 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8133 14:51:21.278874 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8134 14:51:21.278958 == TX Byte 1 ==
8135 14:51:21.285688 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8136 14:51:21.289043 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8137 14:51:21.289128 ==
8138 14:51:21.292163 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 14:51:21.295700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 14:51:21.295785 ==
8141 14:51:21.308825
8142 14:51:21.311639 TX Vref early break, caculate TX vref
8143 14:51:21.315038 TX Vref=16, minBit 3, minWin=22, winSum=388
8144 14:51:21.318990 TX Vref=18, minBit 1, minWin=23, winSum=397
8145 14:51:21.321911 TX Vref=20, minBit 1, minWin=24, winSum=406
8146 14:51:21.325500 TX Vref=22, minBit 0, minWin=25, winSum=412
8147 14:51:21.328734 TX Vref=24, minBit 0, minWin=25, winSum=420
8148 14:51:21.335129 TX Vref=26, minBit 1, minWin=26, winSum=431
8149 14:51:21.338750 TX Vref=28, minBit 3, minWin=25, winSum=423
8150 14:51:21.341740 TX Vref=30, minBit 0, minWin=25, winSum=415
8151 14:51:21.345161 TX Vref=32, minBit 4, minWin=24, winSum=408
8152 14:51:21.351852 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 26
8153 14:51:21.351948
8154 14:51:21.355440 Final TX Range 0 Vref 26
8155 14:51:21.355522
8156 14:51:21.355585 ==
8157 14:51:21.358474 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 14:51:21.362027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 14:51:21.362109 ==
8160 14:51:21.362172
8161 14:51:21.362231
8162 14:51:21.364989 TX Vref Scan disable
8163 14:51:21.368448 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8164 14:51:21.371989 == TX Byte 0 ==
8165 14:51:21.374979 u2DelayCellOfst[0]=10 cells (3 PI)
8166 14:51:21.377995 u2DelayCellOfst[1]=13 cells (4 PI)
8167 14:51:21.381640 u2DelayCellOfst[2]=10 cells (3 PI)
8168 14:51:21.385196 u2DelayCellOfst[3]=6 cells (2 PI)
8169 14:51:21.388178 u2DelayCellOfst[4]=6 cells (2 PI)
8170 14:51:21.388259 u2DelayCellOfst[5]=0 cells (0 PI)
8171 14:51:21.391594 u2DelayCellOfst[6]=16 cells (5 PI)
8172 14:51:21.395568 u2DelayCellOfst[7]=16 cells (5 PI)
8173 14:51:21.401610 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8174 14:51:21.405185 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8175 14:51:21.405267 == TX Byte 1 ==
8176 14:51:21.408207 u2DelayCellOfst[8]=0 cells (0 PI)
8177 14:51:21.411445 u2DelayCellOfst[9]=0 cells (0 PI)
8178 14:51:21.414754 u2DelayCellOfst[10]=6 cells (2 PI)
8179 14:51:21.418364 u2DelayCellOfst[11]=6 cells (2 PI)
8180 14:51:21.421334 u2DelayCellOfst[12]=10 cells (3 PI)
8181 14:51:21.424864 u2DelayCellOfst[13]=10 cells (3 PI)
8182 14:51:21.428289 u2DelayCellOfst[14]=16 cells (5 PI)
8183 14:51:21.431402 u2DelayCellOfst[15]=10 cells (3 PI)
8184 14:51:21.434995 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8185 14:51:21.438083 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8186 14:51:21.441137 DramC Write-DBI on
8187 14:51:21.441218 ==
8188 14:51:21.444915 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 14:51:21.448328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 14:51:21.448457 ==
8191 14:51:21.448553
8192 14:51:21.448645
8193 14:51:21.451432 TX Vref Scan disable
8194 14:51:21.454491 == TX Byte 0 ==
8195 14:51:21.458307 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8196 14:51:21.461129 == TX Byte 1 ==
8197 14:51:21.464590 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8198 14:51:21.464699 DramC Write-DBI off
8199 14:51:21.464790
8200 14:51:21.467877 [DATLAT]
8201 14:51:21.467983 Freq=1600, CH0 RK1
8202 14:51:21.468075
8203 14:51:21.471526 DATLAT Default: 0xf
8204 14:51:21.471611 0, 0xFFFF, sum = 0
8205 14:51:21.474305 1, 0xFFFF, sum = 0
8206 14:51:21.474392 2, 0xFFFF, sum = 0
8207 14:51:21.477967 3, 0xFFFF, sum = 0
8208 14:51:21.478050 4, 0xFFFF, sum = 0
8209 14:51:21.481360 5, 0xFFFF, sum = 0
8210 14:51:21.481442 6, 0xFFFF, sum = 0
8211 14:51:21.484371 7, 0xFFFF, sum = 0
8212 14:51:21.487700 8, 0xFFFF, sum = 0
8213 14:51:21.487808 9, 0xFFFF, sum = 0
8214 14:51:21.491003 10, 0xFFFF, sum = 0
8215 14:51:21.491085 11, 0xFFFF, sum = 0
8216 14:51:21.494448 12, 0xFFFF, sum = 0
8217 14:51:21.494530 13, 0xFFFF, sum = 0
8218 14:51:21.497696 14, 0x0, sum = 1
8219 14:51:21.497827 15, 0x0, sum = 2
8220 14:51:21.500860 16, 0x0, sum = 3
8221 14:51:21.500941 17, 0x0, sum = 4
8222 14:51:21.504285 best_step = 15
8223 14:51:21.504417
8224 14:51:21.504481 ==
8225 14:51:21.507886 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 14:51:21.510967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 14:51:21.511047 ==
8228 14:51:21.511110 RX Vref Scan: 0
8229 14:51:21.513960
8230 14:51:21.514040 RX Vref 0 -> 0, step: 1
8231 14:51:21.514103
8232 14:51:21.517686 RX Delay 19 -> 252, step: 4
8233 14:51:21.520686 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8234 14:51:21.527609 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8235 14:51:21.530652 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8236 14:51:21.534115 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8237 14:51:21.537373 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8238 14:51:21.540817 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8239 14:51:21.547127 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8240 14:51:21.550712 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8241 14:51:21.553770 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8242 14:51:21.557489 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8243 14:51:21.560555 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8244 14:51:21.567304 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8245 14:51:21.570588 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8246 14:51:21.573819 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8247 14:51:21.576988 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8248 14:51:21.580577 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8249 14:51:21.583449 ==
8250 14:51:21.587185 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 14:51:21.590504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 14:51:21.590585 ==
8253 14:51:21.590648 DQS Delay:
8254 14:51:21.593941 DQS0 = 0, DQS1 = 0
8255 14:51:21.594021 DQM Delay:
8256 14:51:21.597277 DQM0 = 134, DQM1 = 127
8257 14:51:21.597357 DQ Delay:
8258 14:51:21.600823 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8259 14:51:21.603849 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8260 14:51:21.607130 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =120
8261 14:51:21.610859 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8262 14:51:21.610939
8263 14:51:21.611002
8264 14:51:21.611060
8265 14:51:21.614053 [DramC_TX_OE_Calibration] TA2
8266 14:51:21.617137 Original DQ_B0 (3 6) =30, OEN = 27
8267 14:51:21.620880 Original DQ_B1 (3 6) =30, OEN = 27
8268 14:51:21.623725 24, 0x0, End_B0=24 End_B1=24
8269 14:51:21.627526 25, 0x0, End_B0=25 End_B1=25
8270 14:51:21.627608 26, 0x0, End_B0=26 End_B1=26
8271 14:51:21.630722 27, 0x0, End_B0=27 End_B1=27
8272 14:51:21.633984 28, 0x0, End_B0=28 End_B1=28
8273 14:51:21.637116 29, 0x0, End_B0=29 End_B1=29
8274 14:51:21.637197 30, 0x0, End_B0=30 End_B1=30
8275 14:51:21.640637 31, 0x4545, End_B0=30 End_B1=30
8276 14:51:21.643638 Byte0 end_step=30 best_step=27
8277 14:51:21.647342 Byte1 end_step=30 best_step=27
8278 14:51:21.650679 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 14:51:21.653805 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 14:51:21.653886
8281 14:51:21.653949
8282 14:51:21.660322 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8283 14:51:21.663776 CH0 RK1: MR19=303, MR18=2109
8284 14:51:21.670248 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8285 14:51:21.673818 [RxdqsGatingPostProcess] freq 1600
8286 14:51:21.677166 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 14:51:21.680227 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 14:51:21.683970 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 14:51:21.686990 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 14:51:21.690263 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 14:51:21.693648 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 14:51:21.697301 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 14:51:21.700504 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 14:51:21.703915 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 14:51:21.707260 Pre-setting of DQS Precalculation
8296 14:51:21.710210 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 14:51:21.710290 ==
8298 14:51:21.713909 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 14:51:21.717597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 14:51:21.720528 ==
8301 14:51:21.723819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 14:51:21.727313 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 14:51:21.733742 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 14:51:21.737429 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 14:51:21.747513 [CA 0] Center 41 (11~71) winsize 61
8306 14:51:21.750822 [CA 1] Center 41 (12~71) winsize 60
8307 14:51:21.753845 [CA 2] Center 38 (9~68) winsize 60
8308 14:51:21.757434 [CA 3] Center 37 (8~66) winsize 59
8309 14:51:21.760350 [CA 4] Center 37 (8~67) winsize 60
8310 14:51:21.764095 [CA 5] Center 36 (7~66) winsize 60
8311 14:51:21.764176
8312 14:51:21.767009 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 14:51:21.767090
8314 14:51:21.770472 [CATrainingPosCal] consider 1 rank data
8315 14:51:21.773791 u2DelayCellTimex100 = 290/100 ps
8316 14:51:21.777363 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8317 14:51:21.783595 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8318 14:51:21.786949 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8319 14:51:21.790451 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 14:51:21.793629 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8321 14:51:21.796724 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8322 14:51:21.796805
8323 14:51:21.799971 CA PerBit enable=1, Macro0, CA PI delay=36
8324 14:51:21.800051
8325 14:51:21.803658 [CBTSetCACLKResult] CA Dly = 36
8326 14:51:21.806639 CS Dly: 10 (0~41)
8327 14:51:21.810161 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 14:51:21.813551 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 14:51:21.813632 ==
8330 14:51:21.816534 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 14:51:21.823523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 14:51:21.823613 ==
8333 14:51:21.826798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 14:51:21.829859 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 14:51:21.836629 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 14:51:21.843198 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 14:51:21.850692 [CA 0] Center 42 (12~72) winsize 61
8338 14:51:21.853782 [CA 1] Center 41 (12~71) winsize 60
8339 14:51:21.857107 [CA 2] Center 38 (9~68) winsize 60
8340 14:51:21.860822 [CA 3] Center 38 (9~67) winsize 59
8341 14:51:21.863766 [CA 4] Center 38 (8~68) winsize 61
8342 14:51:21.867719 [CA 5] Center 37 (8~67) winsize 60
8343 14:51:21.867799
8344 14:51:21.870517 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8345 14:51:21.870597
8346 14:51:21.874295 [CATrainingPosCal] consider 2 rank data
8347 14:51:21.877286 u2DelayCellTimex100 = 290/100 ps
8348 14:51:21.880282 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8349 14:51:21.887300 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8350 14:51:21.890627 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8351 14:51:21.893666 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8352 14:51:21.897184 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 14:51:21.900182 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8354 14:51:21.900287
8355 14:51:21.903652 CA PerBit enable=1, Macro0, CA PI delay=37
8356 14:51:21.903732
8357 14:51:21.907113 [CBTSetCACLKResult] CA Dly = 37
8358 14:51:21.910380 CS Dly: 11 (0~44)
8359 14:51:21.913799 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 14:51:21.917137 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 14:51:21.917217
8362 14:51:21.920328 ----->DramcWriteLeveling(PI) begin...
8363 14:51:21.920419 ==
8364 14:51:21.923706 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 14:51:21.926963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 14:51:21.930246 ==
8367 14:51:21.930352 Write leveling (Byte 0): 25 => 25
8368 14:51:21.933696 Write leveling (Byte 1): 27 => 27
8369 14:51:21.937120 DramcWriteLeveling(PI) end<-----
8370 14:51:21.937224
8371 14:51:21.937318 ==
8372 14:51:21.940094 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 14:51:21.946787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 14:51:21.946866 ==
8375 14:51:21.946929 [Gating] SW mode calibration
8376 14:51:21.957203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 14:51:21.960173 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 14:51:21.963903 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 14:51:21.970711 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 14:51:21.973738 1 4 8 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
8381 14:51:21.977275 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8382 14:51:21.983317 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 14:51:21.987016 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 14:51:21.990063 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 14:51:21.996679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 14:51:21.999920 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 14:51:22.003573 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 14:51:22.010129 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8389 14:51:22.013349 1 5 12 | B1->B0 | 2c2c 2424 | 0 0 | (0 1) (1 0)
8390 14:51:22.016379 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8391 14:51:22.023451 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 14:51:22.026344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 14:51:22.030312 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 14:51:22.036540 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 14:51:22.039996 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 14:51:22.043051 1 6 8 | B1->B0 | 2727 3838 | 0 1 | (0 0) (1 1)
8397 14:51:22.049781 1 6 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
8398 14:51:22.052895 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 14:51:22.056031 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 14:51:22.062789 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 14:51:22.066240 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 14:51:22.070065 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 14:51:22.076558 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 14:51:22.080243 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 14:51:22.082539 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 14:51:22.089694 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 14:51:22.092777 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 14:51:22.096451 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 14:51:22.102695 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 14:51:22.106448 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 14:51:22.109580 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 14:51:22.115810 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 14:51:22.119583 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 14:51:22.122617 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 14:51:22.129436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 14:51:22.132441 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 14:51:22.136236 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 14:51:22.142496 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 14:51:22.146028 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 14:51:22.149061 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 14:51:22.156069 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 14:51:22.159093 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8423 14:51:22.162691 Total UI for P1: 0, mck2ui 16
8424 14:51:22.165848 best dqsien dly found for B0: ( 1, 9, 10)
8425 14:51:22.169582 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 14:51:22.172534 Total UI for P1: 0, mck2ui 16
8427 14:51:22.175721 best dqsien dly found for B1: ( 1, 9, 12)
8428 14:51:22.178958 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8429 14:51:22.182105 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8430 14:51:22.182188
8431 14:51:22.185468 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 14:51:22.191963 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8433 14:51:22.192043 [Gating] SW calibration Done
8434 14:51:22.192105 ==
8435 14:51:22.195952 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 14:51:22.201772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 14:51:22.201853 ==
8438 14:51:22.201916 RX Vref Scan: 0
8439 14:51:22.201975
8440 14:51:22.205284 RX Vref 0 -> 0, step: 1
8441 14:51:22.205365
8442 14:51:22.208562 RX Delay 0 -> 252, step: 8
8443 14:51:22.211870 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8444 14:51:22.215394 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8445 14:51:22.219012 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8446 14:51:22.225539 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8447 14:51:22.228585 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8448 14:51:22.232103 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8449 14:51:22.235675 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8450 14:51:22.238610 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8451 14:51:22.242011 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8452 14:51:22.248745 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8453 14:51:22.251740 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8454 14:51:22.255337 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8455 14:51:22.258609 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8456 14:51:22.265343 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8457 14:51:22.268779 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8458 14:51:22.271813 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8459 14:51:22.271893 ==
8460 14:51:22.274866 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 14:51:22.278741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 14:51:22.278822 ==
8463 14:51:22.281751 DQS Delay:
8464 14:51:22.281830 DQS0 = 0, DQS1 = 0
8465 14:51:22.285512 DQM Delay:
8466 14:51:22.285591 DQM0 = 136, DQM1 = 132
8467 14:51:22.285653 DQ Delay:
8468 14:51:22.288569 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8469 14:51:22.294934 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8470 14:51:22.298496 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8471 14:51:22.301737 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8472 14:51:22.301818
8473 14:51:22.301880
8474 14:51:22.301937 ==
8475 14:51:22.305087 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 14:51:22.308561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 14:51:22.308641 ==
8478 14:51:22.308703
8479 14:51:22.308761
8480 14:51:22.311689 TX Vref Scan disable
8481 14:51:22.314757 == TX Byte 0 ==
8482 14:51:22.318464 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8483 14:51:22.321728 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 14:51:22.324707 == TX Byte 1 ==
8485 14:51:22.328292 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8486 14:51:22.331970 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8487 14:51:22.332049 ==
8488 14:51:22.335071 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 14:51:22.338327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 14:51:22.341443 ==
8491 14:51:22.352463
8492 14:51:22.355616 TX Vref early break, caculate TX vref
8493 14:51:22.358714 TX Vref=16, minBit 0, minWin=22, winSum=376
8494 14:51:22.362386 TX Vref=18, minBit 1, minWin=23, winSum=386
8495 14:51:22.366118 TX Vref=20, minBit 1, minWin=24, winSum=400
8496 14:51:22.369001 TX Vref=22, minBit 1, minWin=24, winSum=410
8497 14:51:22.372410 TX Vref=24, minBit 1, minWin=25, winSum=418
8498 14:51:22.378540 TX Vref=26, minBit 0, minWin=25, winSum=424
8499 14:51:22.382403 TX Vref=28, minBit 0, minWin=25, winSum=427
8500 14:51:22.385494 TX Vref=30, minBit 2, minWin=25, winSum=423
8501 14:51:22.388978 TX Vref=32, minBit 6, minWin=24, winSum=412
8502 14:51:22.392237 TX Vref=34, minBit 6, minWin=23, winSum=402
8503 14:51:22.398876 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8504 14:51:22.398956
8505 14:51:22.402506 Final TX Range 0 Vref 28
8506 14:51:22.402586
8507 14:51:22.402649 ==
8508 14:51:22.405603 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 14:51:22.409075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 14:51:22.409155 ==
8511 14:51:22.409218
8512 14:51:22.409278
8513 14:51:22.412332 TX Vref Scan disable
8514 14:51:22.418942 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8515 14:51:22.419023 == TX Byte 0 ==
8516 14:51:22.422225 u2DelayCellOfst[0]=16 cells (5 PI)
8517 14:51:22.425578 u2DelayCellOfst[1]=10 cells (3 PI)
8518 14:51:22.428759 u2DelayCellOfst[2]=0 cells (0 PI)
8519 14:51:22.432166 u2DelayCellOfst[3]=3 cells (1 PI)
8520 14:51:22.435416 u2DelayCellOfst[4]=6 cells (2 PI)
8521 14:51:22.438454 u2DelayCellOfst[5]=16 cells (5 PI)
8522 14:51:22.438535 u2DelayCellOfst[6]=16 cells (5 PI)
8523 14:51:22.442350 u2DelayCellOfst[7]=6 cells (2 PI)
8524 14:51:22.449037 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8525 14:51:22.452354 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8526 14:51:22.452464 == TX Byte 1 ==
8527 14:51:22.455120 u2DelayCellOfst[8]=0 cells (0 PI)
8528 14:51:22.458575 u2DelayCellOfst[9]=3 cells (1 PI)
8529 14:51:22.462226 u2DelayCellOfst[10]=13 cells (4 PI)
8530 14:51:22.465498 u2DelayCellOfst[11]=3 cells (1 PI)
8531 14:51:22.468478 u2DelayCellOfst[12]=16 cells (5 PI)
8532 14:51:22.471989 u2DelayCellOfst[13]=16 cells (5 PI)
8533 14:51:22.475631 u2DelayCellOfst[14]=16 cells (5 PI)
8534 14:51:22.478123 u2DelayCellOfst[15]=16 cells (5 PI)
8535 14:51:22.481836 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8536 14:51:22.488121 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8537 14:51:22.488205 DramC Write-DBI on
8538 14:51:22.488268 ==
8539 14:51:22.491728 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 14:51:22.495286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 14:51:22.495368 ==
8542 14:51:22.498443
8543 14:51:22.498524
8544 14:51:22.498588 TX Vref Scan disable
8545 14:51:22.501363 == TX Byte 0 ==
8546 14:51:22.505015 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8547 14:51:22.508598 == TX Byte 1 ==
8548 14:51:22.511761 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8549 14:51:22.511843 DramC Write-DBI off
8550 14:51:22.514882
8551 14:51:22.514963 [DATLAT]
8552 14:51:22.515027 Freq=1600, CH1 RK0
8553 14:51:22.515088
8554 14:51:22.518410 DATLAT Default: 0xf
8555 14:51:22.518490 0, 0xFFFF, sum = 0
8556 14:51:22.521644 1, 0xFFFF, sum = 0
8557 14:51:22.521726 2, 0xFFFF, sum = 0
8558 14:51:22.525215 3, 0xFFFF, sum = 0
8559 14:51:22.525298 4, 0xFFFF, sum = 0
8560 14:51:22.528065 5, 0xFFFF, sum = 0
8561 14:51:22.531373 6, 0xFFFF, sum = 0
8562 14:51:22.531456 7, 0xFFFF, sum = 0
8563 14:51:22.534632 8, 0xFFFF, sum = 0
8564 14:51:22.534715 9, 0xFFFF, sum = 0
8565 14:51:22.538125 10, 0xFFFF, sum = 0
8566 14:51:22.538207 11, 0xFFFF, sum = 0
8567 14:51:22.541414 12, 0xFFFF, sum = 0
8568 14:51:22.541496 13, 0xFFFF, sum = 0
8569 14:51:22.544416 14, 0x0, sum = 1
8570 14:51:22.544498 15, 0x0, sum = 2
8571 14:51:22.548186 16, 0x0, sum = 3
8572 14:51:22.548268 17, 0x0, sum = 4
8573 14:51:22.551467 best_step = 15
8574 14:51:22.551548
8575 14:51:22.551612 ==
8576 14:51:22.554669 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 14:51:22.558476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 14:51:22.558558 ==
8579 14:51:22.561334 RX Vref Scan: 1
8580 14:51:22.561415
8581 14:51:22.561479 Set Vref Range= 24 -> 127
8582 14:51:22.561540
8583 14:51:22.564620 RX Vref 24 -> 127, step: 1
8584 14:51:22.564701
8585 14:51:22.568144 RX Delay 27 -> 252, step: 4
8586 14:51:22.568225
8587 14:51:22.571020 Set Vref, RX VrefLevel [Byte0]: 24
8588 14:51:22.574593 [Byte1]: 24
8589 14:51:22.574674
8590 14:51:22.577779 Set Vref, RX VrefLevel [Byte0]: 25
8591 14:51:22.581282 [Byte1]: 25
8592 14:51:22.581363
8593 14:51:22.584732 Set Vref, RX VrefLevel [Byte0]: 26
8594 14:51:22.587531 [Byte1]: 26
8595 14:51:22.591624
8596 14:51:22.591704 Set Vref, RX VrefLevel [Byte0]: 27
8597 14:51:22.594973 [Byte1]: 27
8598 14:51:22.599293
8599 14:51:22.599373 Set Vref, RX VrefLevel [Byte0]: 28
8600 14:51:22.602280 [Byte1]: 28
8601 14:51:22.606595
8602 14:51:22.606676 Set Vref, RX VrefLevel [Byte0]: 29
8603 14:51:22.610490 [Byte1]: 29
8604 14:51:22.614212
8605 14:51:22.614292 Set Vref, RX VrefLevel [Byte0]: 30
8606 14:51:22.617619 [Byte1]: 30
8607 14:51:22.621700
8608 14:51:22.621772 Set Vref, RX VrefLevel [Byte0]: 31
8609 14:51:22.624885 [Byte1]: 31
8610 14:51:22.629614
8611 14:51:22.629695 Set Vref, RX VrefLevel [Byte0]: 32
8612 14:51:22.632873 [Byte1]: 32
8613 14:51:22.636721
8614 14:51:22.636801 Set Vref, RX VrefLevel [Byte0]: 33
8615 14:51:22.640127 [Byte1]: 33
8616 14:51:22.644528
8617 14:51:22.644624 Set Vref, RX VrefLevel [Byte0]: 34
8618 14:51:22.647712 [Byte1]: 34
8619 14:51:22.651940
8620 14:51:22.652021 Set Vref, RX VrefLevel [Byte0]: 35
8621 14:51:22.655160 [Byte1]: 35
8622 14:51:22.659473
8623 14:51:22.659555 Set Vref, RX VrefLevel [Byte0]: 36
8624 14:51:22.662939 [Byte1]: 36
8625 14:51:22.666887
8626 14:51:22.666966 Set Vref, RX VrefLevel [Byte0]: 37
8627 14:51:22.670222 [Byte1]: 37
8628 14:51:22.674608
8629 14:51:22.674687 Set Vref, RX VrefLevel [Byte0]: 38
8630 14:51:22.677799 [Byte1]: 38
8631 14:51:22.682089
8632 14:51:22.682170 Set Vref, RX VrefLevel [Byte0]: 39
8633 14:51:22.685585 [Byte1]: 39
8634 14:51:22.689478
8635 14:51:22.689557 Set Vref, RX VrefLevel [Byte0]: 40
8636 14:51:22.693199 [Byte1]: 40
8637 14:51:22.697599
8638 14:51:22.697679 Set Vref, RX VrefLevel [Byte0]: 41
8639 14:51:22.700624 [Byte1]: 41
8640 14:51:22.704812
8641 14:51:22.704891 Set Vref, RX VrefLevel [Byte0]: 42
8642 14:51:22.707819 [Byte1]: 42
8643 14:51:22.712191
8644 14:51:22.712271 Set Vref, RX VrefLevel [Byte0]: 43
8645 14:51:22.715850 [Byte1]: 43
8646 14:51:22.719731
8647 14:51:22.719811 Set Vref, RX VrefLevel [Byte0]: 44
8648 14:51:22.723199 [Byte1]: 44
8649 14:51:22.727339
8650 14:51:22.727445 Set Vref, RX VrefLevel [Byte0]: 45
8651 14:51:22.730321 [Byte1]: 45
8652 14:51:22.734805
8653 14:51:22.734885 Set Vref, RX VrefLevel [Byte0]: 46
8654 14:51:22.738645 [Byte1]: 46
8655 14:51:22.742225
8656 14:51:22.742305 Set Vref, RX VrefLevel [Byte0]: 47
8657 14:51:22.745781 [Byte1]: 47
8658 14:51:22.750009
8659 14:51:22.750089 Set Vref, RX VrefLevel [Byte0]: 48
8660 14:51:22.753211 [Byte1]: 48
8661 14:51:22.757407
8662 14:51:22.757488 Set Vref, RX VrefLevel [Byte0]: 49
8663 14:51:22.760766 [Byte1]: 49
8664 14:51:22.764831
8665 14:51:22.764912 Set Vref, RX VrefLevel [Byte0]: 50
8666 14:51:22.768020 [Byte1]: 50
8667 14:51:22.772336
8668 14:51:22.772456 Set Vref, RX VrefLevel [Byte0]: 51
8669 14:51:22.775956 [Byte1]: 51
8670 14:51:22.780123
8671 14:51:22.780230 Set Vref, RX VrefLevel [Byte0]: 52
8672 14:51:22.783344 [Byte1]: 52
8673 14:51:22.787466
8674 14:51:22.787546 Set Vref, RX VrefLevel [Byte0]: 53
8675 14:51:22.790986 [Byte1]: 53
8676 14:51:22.795223
8677 14:51:22.795303 Set Vref, RX VrefLevel [Byte0]: 54
8678 14:51:22.798613 [Byte1]: 54
8679 14:51:22.802927
8680 14:51:22.803007 Set Vref, RX VrefLevel [Byte0]: 55
8681 14:51:22.806124 [Byte1]: 55
8682 14:51:22.810395
8683 14:51:22.810475 Set Vref, RX VrefLevel [Byte0]: 56
8684 14:51:22.813258 [Byte1]: 56
8685 14:51:22.817336
8686 14:51:22.817415 Set Vref, RX VrefLevel [Byte0]: 57
8687 14:51:22.821218 [Byte1]: 57
8688 14:51:22.825422
8689 14:51:22.825502 Set Vref, RX VrefLevel [Byte0]: 58
8690 14:51:22.828434 [Byte1]: 58
8691 14:51:22.832919
8692 14:51:22.833000 Set Vref, RX VrefLevel [Byte0]: 59
8693 14:51:22.835999 [Byte1]: 59
8694 14:51:22.840537
8695 14:51:22.840618 Set Vref, RX VrefLevel [Byte0]: 60
8696 14:51:22.843804 [Byte1]: 60
8697 14:51:22.847798
8698 14:51:22.847883 Set Vref, RX VrefLevel [Byte0]: 61
8699 14:51:22.850931 [Byte1]: 61
8700 14:51:22.855445
8701 14:51:22.855525 Set Vref, RX VrefLevel [Byte0]: 62
8702 14:51:22.859036 [Byte1]: 62
8703 14:51:22.862569
8704 14:51:22.862649 Set Vref, RX VrefLevel [Byte0]: 63
8705 14:51:22.865908 [Byte1]: 63
8706 14:51:22.870551
8707 14:51:22.870657 Set Vref, RX VrefLevel [Byte0]: 64
8708 14:51:22.873785 [Byte1]: 64
8709 14:51:22.877813
8710 14:51:22.877893 Set Vref, RX VrefLevel [Byte0]: 65
8711 14:51:22.881326 [Byte1]: 65
8712 14:51:22.885437
8713 14:51:22.885519 Set Vref, RX VrefLevel [Byte0]: 66
8714 14:51:22.888752 [Byte1]: 66
8715 14:51:22.892918
8716 14:51:22.893003 Set Vref, RX VrefLevel [Byte0]: 67
8717 14:51:22.896179 [Byte1]: 67
8718 14:51:22.900265
8719 14:51:22.900399 Set Vref, RX VrefLevel [Byte0]: 68
8720 14:51:22.904017 [Byte1]: 68
8721 14:51:22.908722
8722 14:51:22.908803 Set Vref, RX VrefLevel [Byte0]: 69
8723 14:51:22.911566 [Byte1]: 69
8724 14:51:22.915250
8725 14:51:22.915331 Set Vref, RX VrefLevel [Byte0]: 70
8726 14:51:22.919009 [Byte1]: 70
8727 14:51:22.923342
8728 14:51:22.923422 Set Vref, RX VrefLevel [Byte0]: 71
8729 14:51:22.926401 [Byte1]: 71
8730 14:51:22.930403
8731 14:51:22.930484 Set Vref, RX VrefLevel [Byte0]: 72
8732 14:51:22.934347 [Byte1]: 72
8733 14:51:22.938594
8734 14:51:22.938674 Set Vref, RX VrefLevel [Byte0]: 73
8735 14:51:22.941695 [Byte1]: 73
8736 14:51:22.945867
8737 14:51:22.945947 Set Vref, RX VrefLevel [Byte0]: 74
8738 14:51:22.949023 [Byte1]: 74
8739 14:51:22.952991
8740 14:51:22.953071 Set Vref, RX VrefLevel [Byte0]: 75
8741 14:51:22.956224 [Byte1]: 75
8742 14:51:22.960633
8743 14:51:22.960713 Final RX Vref Byte 0 = 58 to rank0
8744 14:51:22.964037 Final RX Vref Byte 1 = 57 to rank0
8745 14:51:22.967413 Final RX Vref Byte 0 = 58 to rank1
8746 14:51:22.970804 Final RX Vref Byte 1 = 57 to rank1==
8747 14:51:22.974366 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 14:51:22.977557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 14:51:22.981097 ==
8750 14:51:22.981177 DQS Delay:
8751 14:51:22.981241 DQS0 = 0, DQS1 = 0
8752 14:51:22.984209 DQM Delay:
8753 14:51:22.984289 DQM0 = 134, DQM1 = 131
8754 14:51:22.987407 DQ Delay:
8755 14:51:22.990769 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8756 14:51:22.993772 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8757 14:51:22.997191 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8758 14:51:23.000544 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8759 14:51:23.000625
8760 14:51:23.000687
8761 14:51:23.000749
8762 14:51:23.004290 [DramC_TX_OE_Calibration] TA2
8763 14:51:23.007228 Original DQ_B0 (3 6) =30, OEN = 27
8764 14:51:23.010543 Original DQ_B1 (3 6) =30, OEN = 27
8765 14:51:23.013743 24, 0x0, End_B0=24 End_B1=24
8766 14:51:23.013824 25, 0x0, End_B0=25 End_B1=25
8767 14:51:23.017112 26, 0x0, End_B0=26 End_B1=26
8768 14:51:23.020288 27, 0x0, End_B0=27 End_B1=27
8769 14:51:23.023743 28, 0x0, End_B0=28 End_B1=28
8770 14:51:23.027013 29, 0x0, End_B0=29 End_B1=29
8771 14:51:23.027095 30, 0x0, End_B0=30 End_B1=30
8772 14:51:23.030120 31, 0x4141, End_B0=30 End_B1=30
8773 14:51:23.034067 Byte0 end_step=30 best_step=27
8774 14:51:23.037117 Byte1 end_step=30 best_step=27
8775 14:51:23.040266 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 14:51:23.043971 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 14:51:23.044051
8778 14:51:23.044113
8779 14:51:23.050004 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8780 14:51:23.053877 CH1 RK0: MR19=303, MR18=1523
8781 14:51:23.060114 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8782 14:51:23.060195
8783 14:51:23.063760 ----->DramcWriteLeveling(PI) begin...
8784 14:51:23.063842 ==
8785 14:51:23.066797 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 14:51:23.070057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 14:51:23.070137 ==
8788 14:51:23.073000 Write leveling (Byte 0): 27 => 27
8789 14:51:23.076688 Write leveling (Byte 1): 29 => 29
8790 14:51:23.079942 DramcWriteLeveling(PI) end<-----
8791 14:51:23.080022
8792 14:51:23.080085 ==
8793 14:51:23.083429 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 14:51:23.086588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 14:51:23.086669 ==
8796 14:51:23.090325 [Gating] SW mode calibration
8797 14:51:23.096281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 14:51:23.103457 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 14:51:23.106461 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 14:51:23.113577 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 14:51:23.116743 1 4 8 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
8802 14:51:23.120200 1 4 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8803 14:51:23.126270 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 14:51:23.129806 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 14:51:23.133217 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 14:51:23.136212 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 14:51:23.143138 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 14:51:23.146515 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8809 14:51:23.149851 1 5 8 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 1)
8810 14:51:23.156552 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8811 14:51:23.159639 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 14:51:23.163438 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 14:51:23.170239 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 14:51:23.173267 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 14:51:23.176288 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 14:51:23.183215 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 14:51:23.186317 1 6 8 | B1->B0 | 4040 2424 | 0 0 | (0 0) (0 0)
8818 14:51:23.189890 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8819 14:51:23.196216 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 14:51:23.199870 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 14:51:23.202746 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 14:51:23.209455 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 14:51:23.213092 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 14:51:23.216315 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 14:51:23.222902 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8826 14:51:23.226431 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8827 14:51:23.229819 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8828 14:51:23.236566 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 14:51:23.239710 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 14:51:23.242892 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 14:51:23.245993 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 14:51:23.253308 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 14:51:23.256002 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 14:51:23.259909 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 14:51:23.265899 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 14:51:23.269284 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 14:51:23.273027 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 14:51:23.279329 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 14:51:23.282880 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 14:51:23.286191 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8841 14:51:23.292921 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 14:51:23.296088 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8843 14:51:23.299764 Total UI for P1: 0, mck2ui 16
8844 14:51:23.302643 best dqsien dly found for B1: ( 1, 9, 6)
8845 14:51:23.306183 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 14:51:23.309397 Total UI for P1: 0, mck2ui 16
8847 14:51:23.312411 best dqsien dly found for B0: ( 1, 9, 10)
8848 14:51:23.315708 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8849 14:51:23.319100 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8850 14:51:23.319181
8851 14:51:23.325919 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 14:51:23.329527 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8853 14:51:23.329608 [Gating] SW calibration Done
8854 14:51:23.332558 ==
8855 14:51:23.336094 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 14:51:23.339604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 14:51:23.339685 ==
8858 14:51:23.339748 RX Vref Scan: 0
8859 14:51:23.339807
8860 14:51:23.342793 RX Vref 0 -> 0, step: 1
8861 14:51:23.342873
8862 14:51:23.345838 RX Delay 0 -> 252, step: 8
8863 14:51:23.349345 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8864 14:51:23.352375 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8865 14:51:23.356067 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8866 14:51:23.362644 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8867 14:51:23.365887 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8868 14:51:23.369314 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8869 14:51:23.372308 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8870 14:51:23.376024 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8871 14:51:23.382581 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8872 14:51:23.385442 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8873 14:51:23.389186 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8874 14:51:23.392316 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8875 14:51:23.395568 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8876 14:51:23.402110 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8877 14:51:23.405840 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8878 14:51:23.409150 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8879 14:51:23.409281 ==
8880 14:51:23.412108 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 14:51:23.415564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 14:51:23.419089 ==
8883 14:51:23.419169 DQS Delay:
8884 14:51:23.419233 DQS0 = 0, DQS1 = 0
8885 14:51:23.422291 DQM Delay:
8886 14:51:23.422371 DQM0 = 135, DQM1 = 133
8887 14:51:23.425672 DQ Delay:
8888 14:51:23.428835 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8889 14:51:23.432501 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8890 14:51:23.435376 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8891 14:51:23.438843 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8892 14:51:23.438924
8893 14:51:23.438987
8894 14:51:23.439044 ==
8895 14:51:23.442312 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 14:51:23.445891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 14:51:23.445971 ==
8898 14:51:23.446034
8899 14:51:23.448761
8900 14:51:23.448841 TX Vref Scan disable
8901 14:51:23.451919 == TX Byte 0 ==
8902 14:51:23.455520 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8903 14:51:23.458706 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8904 14:51:23.462342 == TX Byte 1 ==
8905 14:51:23.465461 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8906 14:51:23.468574 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8907 14:51:23.468654 ==
8908 14:51:23.472038 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 14:51:23.478173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 14:51:23.478255 ==
8911 14:51:23.490501
8912 14:51:23.493264 TX Vref early break, caculate TX vref
8913 14:51:23.497222 TX Vref=16, minBit 1, minWin=23, winSum=382
8914 14:51:23.500203 TX Vref=18, minBit 10, minWin=23, winSum=390
8915 14:51:23.503396 TX Vref=20, minBit 1, minWin=24, winSum=399
8916 14:51:23.506864 TX Vref=22, minBit 6, minWin=24, winSum=409
8917 14:51:23.510088 TX Vref=24, minBit 0, minWin=25, winSum=415
8918 14:51:23.516907 TX Vref=26, minBit 0, minWin=25, winSum=421
8919 14:51:23.520461 TX Vref=28, minBit 0, minWin=25, winSum=424
8920 14:51:23.523299 TX Vref=30, minBit 1, minWin=25, winSum=421
8921 14:51:23.526919 TX Vref=32, minBit 0, minWin=24, winSum=412
8922 14:51:23.530192 TX Vref=34, minBit 0, minWin=24, winSum=401
8923 14:51:23.537063 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8924 14:51:23.537145
8925 14:51:23.540320 Final TX Range 0 Vref 28
8926 14:51:23.540441
8927 14:51:23.540506 ==
8928 14:51:23.543922 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 14:51:23.547116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 14:51:23.547198 ==
8931 14:51:23.547263
8932 14:51:23.547322
8933 14:51:23.550145 TX Vref Scan disable
8934 14:51:23.556804 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8935 14:51:23.556900 == TX Byte 0 ==
8936 14:51:23.560761 u2DelayCellOfst[0]=16 cells (5 PI)
8937 14:51:23.563560 u2DelayCellOfst[1]=10 cells (3 PI)
8938 14:51:23.566939 u2DelayCellOfst[2]=0 cells (0 PI)
8939 14:51:23.570288 u2DelayCellOfst[3]=6 cells (2 PI)
8940 14:51:23.573469 u2DelayCellOfst[4]=10 cells (3 PI)
8941 14:51:23.576641 u2DelayCellOfst[5]=16 cells (5 PI)
8942 14:51:23.576725 u2DelayCellOfst[6]=16 cells (5 PI)
8943 14:51:23.580670 u2DelayCellOfst[7]=6 cells (2 PI)
8944 14:51:23.586741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8945 14:51:23.589979 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8946 14:51:23.590068 == TX Byte 1 ==
8947 14:51:23.593412 u2DelayCellOfst[8]=0 cells (0 PI)
8948 14:51:23.597371 u2DelayCellOfst[9]=3 cells (1 PI)
8949 14:51:23.600065 u2DelayCellOfst[10]=10 cells (3 PI)
8950 14:51:23.603558 u2DelayCellOfst[11]=3 cells (1 PI)
8951 14:51:23.606811 u2DelayCellOfst[12]=13 cells (4 PI)
8952 14:51:23.610456 u2DelayCellOfst[13]=13 cells (4 PI)
8953 14:51:23.613672 u2DelayCellOfst[14]=16 cells (5 PI)
8954 14:51:23.616349 u2DelayCellOfst[15]=16 cells (5 PI)
8955 14:51:23.620219 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8956 14:51:23.623218 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8957 14:51:23.626692 DramC Write-DBI on
8958 14:51:23.626776 ==
8959 14:51:23.629843 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 14:51:23.632969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 14:51:23.633052 ==
8962 14:51:23.633116
8963 14:51:23.636119
8964 14:51:23.636201 TX Vref Scan disable
8965 14:51:23.639992 == TX Byte 0 ==
8966 14:51:23.642869 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8967 14:51:23.646519 == TX Byte 1 ==
8968 14:51:23.649766 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8969 14:51:23.649849 DramC Write-DBI off
8970 14:51:23.653381
8971 14:51:23.653464 [DATLAT]
8972 14:51:23.653529 Freq=1600, CH1 RK1
8973 14:51:23.653589
8974 14:51:23.656244 DATLAT Default: 0xf
8975 14:51:23.656327 0, 0xFFFF, sum = 0
8976 14:51:23.659225 1, 0xFFFF, sum = 0
8977 14:51:23.659308 2, 0xFFFF, sum = 0
8978 14:51:23.662786 3, 0xFFFF, sum = 0
8979 14:51:23.665872 4, 0xFFFF, sum = 0
8980 14:51:23.665961 5, 0xFFFF, sum = 0
8981 14:51:23.669735 6, 0xFFFF, sum = 0
8982 14:51:23.669819 7, 0xFFFF, sum = 0
8983 14:51:23.672786 8, 0xFFFF, sum = 0
8984 14:51:23.672871 9, 0xFFFF, sum = 0
8985 14:51:23.676082 10, 0xFFFF, sum = 0
8986 14:51:23.676165 11, 0xFFFF, sum = 0
8987 14:51:23.679217 12, 0xFFFF, sum = 0
8988 14:51:23.679300 13, 0xFFFF, sum = 0
8989 14:51:23.682801 14, 0x0, sum = 1
8990 14:51:23.682885 15, 0x0, sum = 2
8991 14:51:23.685909 16, 0x0, sum = 3
8992 14:51:23.685993 17, 0x0, sum = 4
8993 14:51:23.689911 best_step = 15
8994 14:51:23.689992
8995 14:51:23.690056 ==
8996 14:51:23.692557 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 14:51:23.695697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 14:51:23.695780 ==
8999 14:51:23.698947 RX Vref Scan: 0
9000 14:51:23.699029
9001 14:51:23.699094 RX Vref 0 -> 0, step: 1
9002 14:51:23.699154
9003 14:51:23.702541 RX Delay 19 -> 252, step: 4
9004 14:51:23.705778 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9005 14:51:23.712647 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9006 14:51:23.715641 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9007 14:51:23.719128 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9008 14:51:23.722400 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9009 14:51:23.725590 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9010 14:51:23.729165 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9011 14:51:23.735881 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9012 14:51:23.738833 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9013 14:51:23.742562 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9014 14:51:23.745659 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9015 14:51:23.752472 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9016 14:51:23.755721 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9017 14:51:23.759296 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9018 14:51:23.762181 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9019 14:51:23.765910 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9020 14:51:23.765998 ==
9021 14:51:23.768915 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 14:51:23.775850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 14:51:23.775939 ==
9024 14:51:23.776004 DQS Delay:
9025 14:51:23.778719 DQS0 = 0, DQS1 = 0
9026 14:51:23.778802 DQM Delay:
9027 14:51:23.782472 DQM0 = 134, DQM1 = 130
9028 14:51:23.782556 DQ Delay:
9029 14:51:23.785432 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9030 14:51:23.789101 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9031 14:51:23.791997 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9032 14:51:23.795819 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9033 14:51:23.795904
9034 14:51:23.795967
9035 14:51:23.796027
9036 14:51:23.798534 [DramC_TX_OE_Calibration] TA2
9037 14:51:23.802203 Original DQ_B0 (3 6) =30, OEN = 27
9038 14:51:23.805454 Original DQ_B1 (3 6) =30, OEN = 27
9039 14:51:23.809166 24, 0x0, End_B0=24 End_B1=24
9040 14:51:23.812712 25, 0x0, End_B0=25 End_B1=25
9041 14:51:23.812799 26, 0x0, End_B0=26 End_B1=26
9042 14:51:23.815939 27, 0x0, End_B0=27 End_B1=27
9043 14:51:23.819029 28, 0x0, End_B0=28 End_B1=28
9044 14:51:23.821955 29, 0x0, End_B0=29 End_B1=29
9045 14:51:23.822069 30, 0x0, End_B0=30 End_B1=30
9046 14:51:23.825502 31, 0x4141, End_B0=30 End_B1=30
9047 14:51:23.828991 Byte0 end_step=30 best_step=27
9048 14:51:23.832093 Byte1 end_step=30 best_step=27
9049 14:51:23.835433 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 14:51:23.838767 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 14:51:23.838850
9052 14:51:23.838914
9053 14:51:23.845726 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9054 14:51:23.848623 CH1 RK1: MR19=303, MR18=2106
9055 14:51:23.855583 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9056 14:51:23.858610 [RxdqsGatingPostProcess] freq 1600
9057 14:51:23.862468 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 14:51:23.865349 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 14:51:23.869063 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 14:51:23.872204 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 14:51:23.875774 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 14:51:23.878919 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 14:51:23.882270 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 14:51:23.885207 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 14:51:23.889026 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 14:51:23.892451 Pre-setting of DQS Precalculation
9067 14:51:23.895457 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 14:51:23.902267 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 14:51:23.908792 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 14:51:23.912126
9071 14:51:23.912214
9072 14:51:23.912278 [Calibration Summary] 3200 Mbps
9073 14:51:23.915474 CH 0, Rank 0
9074 14:51:23.915562 SW Impedance : PASS
9075 14:51:23.918499 DUTY Scan : NO K
9076 14:51:23.921823 ZQ Calibration : PASS
9077 14:51:23.921982 Jitter Meter : NO K
9078 14:51:23.925476 CBT Training : PASS
9079 14:51:23.928720 Write leveling : PASS
9080 14:51:23.928827 RX DQS gating : PASS
9081 14:51:23.932153 RX DQ/DQS(RDDQC) : PASS
9082 14:51:23.935202 TX DQ/DQS : PASS
9083 14:51:23.935294 RX DATLAT : PASS
9084 14:51:23.938901 RX DQ/DQS(Engine): PASS
9085 14:51:23.942125 TX OE : PASS
9086 14:51:23.942231 All Pass.
9087 14:51:23.942297
9088 14:51:23.942358 CH 0, Rank 1
9089 14:51:23.945607 SW Impedance : PASS
9090 14:51:23.948944 DUTY Scan : NO K
9091 14:51:23.949033 ZQ Calibration : PASS
9092 14:51:23.952068 Jitter Meter : NO K
9093 14:51:23.952167 CBT Training : PASS
9094 14:51:23.955133 Write leveling : PASS
9095 14:51:23.958313 RX DQS gating : PASS
9096 14:51:23.958403 RX DQ/DQS(RDDQC) : PASS
9097 14:51:23.961741 TX DQ/DQS : PASS
9098 14:51:23.965597 RX DATLAT : PASS
9099 14:51:23.965685 RX DQ/DQS(Engine): PASS
9100 14:51:23.968818 TX OE : PASS
9101 14:51:23.968903 All Pass.
9102 14:51:23.968968
9103 14:51:23.972269 CH 1, Rank 0
9104 14:51:23.972378 SW Impedance : PASS
9105 14:51:23.975580 DUTY Scan : NO K
9106 14:51:23.978926 ZQ Calibration : PASS
9107 14:51:23.979014 Jitter Meter : NO K
9108 14:51:23.981825 CBT Training : PASS
9109 14:51:23.985597 Write leveling : PASS
9110 14:51:23.985684 RX DQS gating : PASS
9111 14:51:23.988712 RX DQ/DQS(RDDQC) : PASS
9112 14:51:23.991838 TX DQ/DQS : PASS
9113 14:51:23.991924 RX DATLAT : PASS
9114 14:51:23.995615 RX DQ/DQS(Engine): PASS
9115 14:51:23.995701 TX OE : PASS
9116 14:51:23.998766 All Pass.
9117 14:51:23.998852
9118 14:51:23.998916 CH 1, Rank 1
9119 14:51:24.002280 SW Impedance : PASS
9120 14:51:24.002367 DUTY Scan : NO K
9121 14:51:24.005254 ZQ Calibration : PASS
9122 14:51:24.008453 Jitter Meter : NO K
9123 14:51:24.008540 CBT Training : PASS
9124 14:51:24.012098 Write leveling : PASS
9125 14:51:24.015402 RX DQS gating : PASS
9126 14:51:24.015488 RX DQ/DQS(RDDQC) : PASS
9127 14:51:24.018392 TX DQ/DQS : PASS
9128 14:51:24.022240 RX DATLAT : PASS
9129 14:51:24.022327 RX DQ/DQS(Engine): PASS
9130 14:51:24.025164 TX OE : PASS
9131 14:51:24.025248 All Pass.
9132 14:51:24.025313
9133 14:51:24.028239 DramC Write-DBI on
9134 14:51:24.031953 PER_BANK_REFRESH: Hybrid Mode
9135 14:51:24.032044 TX_TRACKING: ON
9136 14:51:24.041619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 14:51:24.048560 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 14:51:24.055375 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 14:51:24.058225 [FAST_K] Save calibration result to emmc
9140 14:51:24.061713 sync common calibartion params.
9141 14:51:24.064886 sync cbt_mode0:1, 1:1
9142 14:51:24.068663 dram_init: ddr_geometry: 2
9143 14:51:24.068755 dram_init: ddr_geometry: 2
9144 14:51:24.071757 dram_init: ddr_geometry: 2
9145 14:51:24.074780 0:dram_rank_size:100000000
9146 14:51:24.078267 1:dram_rank_size:100000000
9147 14:51:24.081727 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 14:51:24.084776 DFS_SHUFFLE_HW_MODE: ON
9149 14:51:24.088232 dramc_set_vcore_voltage set vcore to 725000
9150 14:51:24.091779 Read voltage for 1600, 0
9151 14:51:24.091868 Vio18 = 0
9152 14:51:24.091933 Vcore = 725000
9153 14:51:24.095321 Vdram = 0
9154 14:51:24.095410 Vddq = 0
9155 14:51:24.095474 Vmddr = 0
9156 14:51:24.098219 switch to 3200 Mbps bootup
9157 14:51:24.101875 [DramcRunTimeConfig]
9158 14:51:24.101961 PHYPLL
9159 14:51:24.102026 DPM_CONTROL_AFTERK: ON
9160 14:51:24.104693 PER_BANK_REFRESH: ON
9161 14:51:24.108549 REFRESH_OVERHEAD_REDUCTION: ON
9162 14:51:24.108640 CMD_PICG_NEW_MODE: OFF
9163 14:51:24.111442 XRTWTW_NEW_MODE: ON
9164 14:51:24.114514 XRTRTR_NEW_MODE: ON
9165 14:51:24.114599 TX_TRACKING: ON
9166 14:51:24.117665 RDSEL_TRACKING: OFF
9167 14:51:24.117749 DQS Precalculation for DVFS: ON
9168 14:51:24.121375 RX_TRACKING: OFF
9169 14:51:24.121460 HW_GATING DBG: ON
9170 14:51:24.124678 ZQCS_ENABLE_LP4: ON
9171 14:51:24.124763 RX_PICG_NEW_MODE: ON
9172 14:51:24.127773 TX_PICG_NEW_MODE: ON
9173 14:51:24.131498 ENABLE_RX_DCM_DPHY: ON
9174 14:51:24.134418 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 14:51:24.134503 DUMMY_READ_FOR_TRACKING: OFF
9176 14:51:24.138143 !!! SPM_CONTROL_AFTERK: OFF
9177 14:51:24.141412 !!! SPM could not control APHY
9178 14:51:24.144417 IMPEDANCE_TRACKING: ON
9179 14:51:24.144511 TEMP_SENSOR: ON
9180 14:51:24.148187 HW_SAVE_FOR_SR: OFF
9181 14:51:24.148299 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 14:51:24.154701 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 14:51:24.154794 Read ODT Tracking: ON
9184 14:51:24.157710 Refresh Rate DeBounce: ON
9185 14:51:24.161317 DFS_NO_QUEUE_FLUSH: ON
9186 14:51:24.161417 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 14:51:24.164315 ENABLE_DFS_RUNTIME_MRW: OFF
9188 14:51:24.167844 DDR_RESERVE_NEW_MODE: ON
9189 14:51:24.167931 MR_CBT_SWITCH_FREQ: ON
9190 14:51:24.170853 =========================
9191 14:51:24.190397 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 14:51:24.193791 dram_init: ddr_geometry: 2
9193 14:51:24.211906 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 14:51:24.215326 dram_init: dram init end (result: 0)
9195 14:51:24.222264 DRAM-K: Full calibration passed in 24434 msecs
9196 14:51:24.225728 MRC: failed to locate region type 0.
9197 14:51:24.225834 DRAM rank0 size:0x100000000,
9198 14:51:24.228785 DRAM rank1 size=0x100000000
9199 14:51:24.238855 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 14:51:24.245428 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 14:51:24.252107 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 14:51:24.259061 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 14:51:24.261851 DRAM rank0 size:0x100000000,
9204 14:51:24.265575 DRAM rank1 size=0x100000000
9205 14:51:24.265667 CBMEM:
9206 14:51:24.268750 IMD: root @ 0xfffff000 254 entries.
9207 14:51:24.271808 IMD: root @ 0xffffec00 62 entries.
9208 14:51:24.275107 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 14:51:24.278523 WARNING: RO_VPD is uninitialized or empty.
9210 14:51:24.284900 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 14:51:24.292114 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 14:51:24.305058 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9213 14:51:24.316005 BS: romstage times (exec / console): total (unknown) / 23974 ms
9214 14:51:24.316133
9215 14:51:24.316203
9216 14:51:24.326309 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 14:51:24.329741 ARM64: Exception handlers installed.
9218 14:51:24.332807 ARM64: Testing exception
9219 14:51:24.335948 ARM64: Done test exception
9220 14:51:24.336035 Enumerating buses...
9221 14:51:24.339417 Show all devs... Before device enumeration.
9222 14:51:24.342727 Root Device: enabled 1
9223 14:51:24.346313 CPU_CLUSTER: 0: enabled 1
9224 14:51:24.346402 CPU: 00: enabled 1
9225 14:51:24.349493 Compare with tree...
9226 14:51:24.349579 Root Device: enabled 1
9227 14:51:24.352803 CPU_CLUSTER: 0: enabled 1
9228 14:51:24.356307 CPU: 00: enabled 1
9229 14:51:24.356432 Root Device scanning...
9230 14:51:24.359391 scan_static_bus for Root Device
9231 14:51:24.362533 CPU_CLUSTER: 0 enabled
9232 14:51:24.366183 scan_static_bus for Root Device done
9233 14:51:24.369294 scan_bus: bus Root Device finished in 8 msecs
9234 14:51:24.369392 done
9235 14:51:24.376183 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 14:51:24.379117 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 14:51:24.386301 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 14:51:24.389216 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 14:51:24.392586 Allocating resources...
9240 14:51:24.395916 Reading resources...
9241 14:51:24.398980 Root Device read_resources bus 0 link: 0
9242 14:51:24.399068 DRAM rank0 size:0x100000000,
9243 14:51:24.402883 DRAM rank1 size=0x100000000
9244 14:51:24.406122 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 14:51:24.409468 CPU: 00 missing read_resources
9246 14:51:24.412379 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 14:51:24.419693 Root Device read_resources bus 0 link: 0 done
9248 14:51:24.419795 Done reading resources.
9249 14:51:24.426040 Show resources in subtree (Root Device)...After reading.
9250 14:51:24.429376 Root Device child on link 0 CPU_CLUSTER: 0
9251 14:51:24.432313 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 14:51:24.442752 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 14:51:24.442867 CPU: 00
9254 14:51:24.445545 Root Device assign_resources, bus 0 link: 0
9255 14:51:24.448962 CPU_CLUSTER: 0 missing set_resources
9256 14:51:24.452271 Root Device assign_resources, bus 0 link: 0 done
9257 14:51:24.455642 Done setting resources.
9258 14:51:24.462413 Show resources in subtree (Root Device)...After assigning values.
9259 14:51:24.465821 Root Device child on link 0 CPU_CLUSTER: 0
9260 14:51:24.469121 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 14:51:24.478801 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 14:51:24.479077 CPU: 00
9263 14:51:24.482321 Done allocating resources.
9264 14:51:24.485893 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 14:51:24.489097 Enabling resources...
9266 14:51:24.489185 done.
9267 14:51:24.495654 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 14:51:24.495749 Initializing devices...
9269 14:51:24.499029 Root Device init
9270 14:51:24.499112 init hardware done!
9271 14:51:24.502353 0x00000018: ctrlr->caps
9272 14:51:24.505891 52.000 MHz: ctrlr->f_max
9273 14:51:24.505977 0.400 MHz: ctrlr->f_min
9274 14:51:24.509016 0x40ff8080: ctrlr->voltages
9275 14:51:24.509102 sclk: 390625
9276 14:51:24.512285 Bus Width = 1
9277 14:51:24.512403 sclk: 390625
9278 14:51:24.515334 Bus Width = 1
9279 14:51:24.515419 Early init status = 3
9280 14:51:24.521980 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 14:51:24.525447 in-header: 03 fc 00 00 01 00 00 00
9282 14:51:24.528495 in-data: 00
9283 14:51:24.532107 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9284 14:51:24.536571 in-header: 03 fd 00 00 00 00 00 00
9285 14:51:24.540313 in-data:
9286 14:51:24.543359 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9287 14:51:24.547653 in-header: 03 fc 00 00 01 00 00 00
9288 14:51:24.551201 in-data: 00
9289 14:51:24.554439 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9290 14:51:24.559789 in-header: 03 fd 00 00 00 00 00 00
9291 14:51:24.563414 in-data:
9292 14:51:24.566254 [SSUSB] Setting up USB HOST controller...
9293 14:51:24.569921 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9294 14:51:24.573015 [SSUSB] phy power-on done.
9295 14:51:24.576918 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9296 14:51:24.582943 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9297 14:51:24.586665 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9298 14:51:24.593138 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9299 14:51:24.599983 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9300 14:51:24.606557 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9301 14:51:24.612676 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9302 14:51:24.619474 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9303 14:51:24.623184 SPM: binary array size = 0x9dc
9304 14:51:24.626425 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9305 14:51:24.632992 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9306 14:51:24.639459 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9307 14:51:24.643034 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9308 14:51:24.649704 configure_display: Starting display init
9309 14:51:24.683269 anx7625_power_on_init: Init interface.
9310 14:51:24.686806 anx7625_disable_pd_protocol: Disabled PD feature.
9311 14:51:24.689740 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9312 14:51:24.717541 anx7625_start_dp_work: Secure OCM version=00
9313 14:51:24.720561 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9314 14:51:24.735681 sp_tx_get_edid_block: EDID Block = 1
9315 14:51:24.838045 Extracted contents:
9316 14:51:24.841836 header: 00 ff ff ff ff ff ff 00
9317 14:51:24.844908 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9318 14:51:24.847839 version: 01 04
9319 14:51:24.851378 basic params: 95 1f 11 78 0a
9320 14:51:24.854718 chroma info: 76 90 94 55 54 90 27 21 50 54
9321 14:51:24.858269 established: 00 00 00
9322 14:51:24.865019 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9323 14:51:24.867984 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9324 14:51:24.875103 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 14:51:24.881713 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9326 14:51:24.888670 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9327 14:51:24.891607 extensions: 00
9328 14:51:24.891703 checksum: fb
9329 14:51:24.891768
9330 14:51:24.895159 Manufacturer: IVO Model 57d Serial Number 0
9331 14:51:24.897925 Made week 0 of 2020
9332 14:51:24.898010 EDID version: 1.4
9333 14:51:24.901556 Digital display
9334 14:51:24.904987 6 bits per primary color channel
9335 14:51:24.905078 DisplayPort interface
9336 14:51:24.908027 Maximum image size: 31 cm x 17 cm
9337 14:51:24.908111 Gamma: 220%
9338 14:51:24.911613 Check DPMS levels
9339 14:51:24.914875 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9340 14:51:24.918459 First detailed timing is preferred timing
9341 14:51:24.921307 Established timings supported:
9342 14:51:24.925028 Standard timings supported:
9343 14:51:24.925118 Detailed timings
9344 14:51:24.930983 Hex of detail: 383680a07038204018303c0035ae10000019
9345 14:51:24.934460 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9346 14:51:24.941327 0780 0798 07c8 0820 hborder 0
9347 14:51:24.944629 0438 043b 0447 0458 vborder 0
9348 14:51:24.947997 -hsync -vsync
9349 14:51:24.948086 Did detailed timing
9350 14:51:24.951537 Hex of detail: 000000000000000000000000000000000000
9351 14:51:24.954576 Manufacturer-specified data, tag 0
9352 14:51:24.961142 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9353 14:51:24.961261 ASCII string: InfoVision
9354 14:51:24.967325 Hex of detail: 000000fe00523134304e574635205248200a
9355 14:51:24.971307 ASCII string: R140NWF5 RH
9356 14:51:24.971470 Checksum
9357 14:51:24.974086 Checksum: 0xfb (valid)
9358 14:51:24.977877 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9359 14:51:24.980582 DSI data_rate: 832800000 bps
9360 14:51:24.984473 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9361 14:51:24.991190 anx7625_parse_edid: pixelclock(138800).
9362 14:51:24.994313 hactive(1920), hsync(48), hfp(24), hbp(88)
9363 14:51:24.997391 vactive(1080), vsync(12), vfp(3), vbp(17)
9364 14:51:25.000933 anx7625_dsi_config: config dsi.
9365 14:51:25.007146 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9366 14:51:25.020396 anx7625_dsi_config: success to config DSI
9367 14:51:25.023519 anx7625_dp_start: MIPI phy setup OK.
9368 14:51:25.026733 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9369 14:51:25.030321 mtk_ddp_mode_set invalid vrefresh 60
9370 14:51:25.033259 main_disp_path_setup
9371 14:51:25.033350 ovl_layer_smi_id_en
9372 14:51:25.036882 ovl_layer_smi_id_en
9373 14:51:25.036970 ccorr_config
9374 14:51:25.037034 aal_config
9375 14:51:25.039974 gamma_config
9376 14:51:25.040057 postmask_config
9377 14:51:25.043518 dither_config
9378 14:51:25.046540 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9379 14:51:25.053385 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9380 14:51:25.056649 Root Device init finished in 555 msecs
9381 14:51:25.059895 CPU_CLUSTER: 0 init
9382 14:51:25.066839 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9383 14:51:25.069917 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9384 14:51:25.073502 APU_MBOX 0x190000b0 = 0x10001
9385 14:51:25.076835 APU_MBOX 0x190001b0 = 0x10001
9386 14:51:25.079880 APU_MBOX 0x190005b0 = 0x10001
9387 14:51:25.083711 APU_MBOX 0x190006b0 = 0x10001
9388 14:51:25.086881 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9389 14:51:25.099279 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9390 14:51:25.112037 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9391 14:51:25.118442 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9392 14:51:25.130337 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9393 14:51:25.139474 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9394 14:51:25.142105 CPU_CLUSTER: 0 init finished in 81 msecs
9395 14:51:25.145549 Devices initialized
9396 14:51:25.148977 Show all devs... After init.
9397 14:51:25.149077 Root Device: enabled 1
9398 14:51:25.152088 CPU_CLUSTER: 0: enabled 1
9399 14:51:25.155651 CPU: 00: enabled 1
9400 14:51:25.158738 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9401 14:51:25.162020 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9402 14:51:25.165456 ELOG: NV offset 0x57f000 size 0x1000
9403 14:51:25.172013 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9404 14:51:25.179219 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9405 14:51:25.182355 ELOG: Event(17) added with size 13 at 2024-06-04 14:46:43 UTC
9406 14:51:25.185447 out: cmd=0x121: 03 db 21 01 00 00 00 00
9407 14:51:25.189647 in-header: 03 f5 00 00 2c 00 00 00
9408 14:51:25.202505 in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9409 14:51:25.209189 ELOG: Event(A1) added with size 10 at 2024-06-04 14:46:43 UTC
9410 14:51:25.215530 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9411 14:51:25.222249 ELOG: Event(A0) added with size 9 at 2024-06-04 14:46:43 UTC
9412 14:51:25.226075 elog_add_boot_reason: Logged dev mode boot
9413 14:51:25.229059 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9414 14:51:25.232330 Finalize devices...
9415 14:51:25.232426 Devices finalized
9416 14:51:25.238976 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9417 14:51:25.242760 Writing coreboot table at 0xffe64000
9418 14:51:25.245921 0. 000000000010a000-0000000000113fff: RAMSTAGE
9419 14:51:25.249083 1. 0000000040000000-00000000400fffff: RAM
9420 14:51:25.255798 2. 0000000040100000-000000004032afff: RAMSTAGE
9421 14:51:25.259108 3. 000000004032b000-00000000545fffff: RAM
9422 14:51:25.262172 4. 0000000054600000-000000005465ffff: BL31
9423 14:51:25.265919 5. 0000000054660000-00000000ffe63fff: RAM
9424 14:51:25.272157 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9425 14:51:25.275592 7. 0000000100000000-000000023fffffff: RAM
9426 14:51:25.275690 Passing 5 GPIOs to payload:
9427 14:51:25.282269 NAME | PORT | POLARITY | VALUE
9428 14:51:25.285455 EC in RW | 0x000000aa | low | undefined
9429 14:51:25.292260 EC interrupt | 0x00000005 | low | undefined
9430 14:51:25.295990 TPM interrupt | 0x000000ab | high | undefined
9431 14:51:25.298734 SD card detect | 0x00000011 | high | undefined
9432 14:51:25.305782 speaker enable | 0x00000093 | high | undefined
9433 14:51:25.308900 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9434 14:51:25.311881 in-header: 03 f9 00 00 02 00 00 00
9435 14:51:25.311969 in-data: 02 00
9436 14:51:25.315678 ADC[4]: Raw value=904726 ID=7
9437 14:51:25.318752 ADC[3]: Raw value=213441 ID=1
9438 14:51:25.318838 RAM Code: 0x71
9439 14:51:25.322059 ADC[6]: Raw value=75332 ID=0
9440 14:51:25.325146 ADC[5]: Raw value=212703 ID=1
9441 14:51:25.325232 SKU Code: 0x1
9442 14:51:25.331819 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b33e
9443 14:51:25.334865 coreboot table: 964 bytes.
9444 14:51:25.338841 IMD ROOT 0. 0xfffff000 0x00001000
9445 14:51:25.341951 IMD SMALL 1. 0xffffe000 0x00001000
9446 14:51:25.345578 RO MCACHE 2. 0xffffc000 0x00001104
9447 14:51:25.348294 CONSOLE 3. 0xfff7c000 0x00080000
9448 14:51:25.352158 FMAP 4. 0xfff7b000 0x00000452
9449 14:51:25.355067 TIME STAMP 5. 0xfff7a000 0x00000910
9450 14:51:25.358175 VBOOT WORK 6. 0xfff66000 0x00014000
9451 14:51:25.361751 RAMOOPS 7. 0xffe66000 0x00100000
9452 14:51:25.364977 COREBOOT 8. 0xffe64000 0x00002000
9453 14:51:25.365090 IMD small region:
9454 14:51:25.367969 IMD ROOT 0. 0xffffec00 0x00000400
9455 14:51:25.371650 VPD 1. 0xffffeb80 0x0000006c
9456 14:51:25.374744 MMC STATUS 2. 0xffffeb60 0x00000004
9457 14:51:25.381741 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9458 14:51:25.384815 Probing TPM: done!
9459 14:51:25.388009 Connected to device vid:did:rid of 1ae0:0028:00
9460 14:51:25.398245 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9461 14:51:25.402398 Initialized TPM device CR50 revision 0
9462 14:51:25.404829 Checking cr50 for pending updates
9463 14:51:25.408678 Reading cr50 TPM mode
9464 14:51:25.417297 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9465 14:51:25.423826 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9466 14:51:25.463994 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9467 14:51:25.467736 Checking segment from ROM address 0x40100000
9468 14:51:25.470923 Checking segment from ROM address 0x4010001c
9469 14:51:25.477870 Loading segment from ROM address 0x40100000
9470 14:51:25.477978 code (compression=0)
9471 14:51:25.484623 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9472 14:51:25.494337 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9473 14:51:25.494465 it's not compressed!
9474 14:51:25.501045 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9475 14:51:25.504611 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9476 14:51:25.524661 Loading segment from ROM address 0x4010001c
9477 14:51:25.524799 Entry Point 0x80000000
9478 14:51:25.527773 Loaded segments
9479 14:51:25.531281 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9480 14:51:25.537645 Jumping to boot code at 0x80000000(0xffe64000)
9481 14:51:25.544323 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9482 14:51:25.550903 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9483 14:51:25.558953 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9484 14:51:25.562227 Checking segment from ROM address 0x40100000
9485 14:51:25.565541 Checking segment from ROM address 0x4010001c
9486 14:51:25.572492 Loading segment from ROM address 0x40100000
9487 14:51:25.572606 code (compression=1)
9488 14:51:25.578984 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9489 14:51:25.588802 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9490 14:51:25.588935 using LZMA
9491 14:51:25.597373 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9492 14:51:25.604047 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9493 14:51:25.607593 Loading segment from ROM address 0x4010001c
9494 14:51:25.607693 Entry Point 0x54601000
9495 14:51:25.611083 Loaded segments
9496 14:51:25.614053 NOTICE: MT8192 bl31_setup
9497 14:51:25.620711 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9498 14:51:25.624516 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9499 14:51:25.628205 WARNING: region 0:
9500 14:51:25.631097 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 14:51:25.631182 WARNING: region 1:
9502 14:51:25.637866 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9503 14:51:25.641043 WARNING: region 2:
9504 14:51:25.644469 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9505 14:51:25.648202 WARNING: region 3:
9506 14:51:25.651235 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 14:51:25.654371 WARNING: region 4:
9508 14:51:25.661065 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 14:51:25.661182 WARNING: region 5:
9510 14:51:25.664561 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 14:51:25.667863 WARNING: region 6:
9512 14:51:25.671138 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 14:51:25.671227 WARNING: region 7:
9514 14:51:25.677808 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 14:51:25.684272 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9516 14:51:25.687897 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9517 14:51:25.691025 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9518 14:51:25.698283 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9519 14:51:25.701309 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9520 14:51:25.704470 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9521 14:51:25.710944 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9522 14:51:25.714302 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9523 14:51:25.720920 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9524 14:51:25.724591 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9525 14:51:25.727575 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9526 14:51:25.734391 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9527 14:51:25.738298 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9528 14:51:25.741118 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9529 14:51:25.747736 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9530 14:51:25.751122 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9531 14:51:25.754747 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9532 14:51:25.761529 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9533 14:51:25.764462 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9534 14:51:25.768116 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9535 14:51:25.774537 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9536 14:51:25.777718 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9537 14:51:25.784549 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9538 14:51:25.787657 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9539 14:51:25.791224 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9540 14:51:25.797735 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9541 14:51:25.801219 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9542 14:51:25.808051 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9543 14:51:25.811064 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9544 14:51:25.814765 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9545 14:51:25.821058 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9546 14:51:25.824369 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9547 14:51:25.827919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9548 14:51:25.834604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9549 14:51:25.837937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9550 14:51:25.841499 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9551 14:51:25.844513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9552 14:51:25.851298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9553 14:51:25.854765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9554 14:51:25.857763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9555 14:51:25.861126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9556 14:51:25.868065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9557 14:51:25.871295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9558 14:51:25.874877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9559 14:51:25.878324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9560 14:51:25.884971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9561 14:51:25.888031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9562 14:51:25.891246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9563 14:51:25.898213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9564 14:51:25.901893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9565 14:51:25.904935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9566 14:51:25.911500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9567 14:51:25.915048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9568 14:51:25.921214 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9569 14:51:25.925040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9570 14:51:25.931494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9571 14:51:25.934486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9572 14:51:25.938153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9573 14:51:25.944742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9574 14:51:25.948091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9575 14:51:25.954473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9576 14:51:25.958059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9577 14:51:25.964362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9578 14:51:25.967973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9579 14:51:25.974398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9580 14:51:25.977961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9581 14:51:25.980976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9582 14:51:25.987945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9583 14:51:25.991079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9584 14:51:25.997815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9585 14:51:26.001340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9586 14:51:26.008111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9587 14:51:26.011382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9588 14:51:26.014314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9589 14:51:26.021256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9590 14:51:26.024964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9591 14:51:26.031709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9592 14:51:26.034465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9593 14:51:26.041284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9594 14:51:26.044319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9595 14:51:26.047817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9596 14:51:26.054817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9597 14:51:26.057865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9598 14:51:26.064418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9599 14:51:26.068287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9600 14:51:26.074682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9601 14:51:26.077947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9602 14:51:26.081558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9603 14:51:26.088069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9604 14:51:26.091531 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9605 14:51:26.098353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9606 14:51:26.101533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9607 14:51:26.108002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9608 14:51:26.111537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9609 14:51:26.114880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9610 14:51:26.121858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9611 14:51:26.125014 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9612 14:51:26.128032 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9613 14:51:26.134791 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9614 14:51:26.138023 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9615 14:51:26.141270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9616 14:51:26.148406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9617 14:51:26.151634 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9618 14:51:26.154861 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9619 14:51:26.161513 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9620 14:51:26.165076 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9621 14:51:26.168334 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9622 14:51:26.175258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9623 14:51:26.178042 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9624 14:51:26.184779 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9625 14:51:26.188379 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9626 14:51:26.191885 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9627 14:51:26.198271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9628 14:51:26.202129 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9629 14:51:26.208383 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9630 14:51:26.212135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9631 14:51:26.215028 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9632 14:51:26.218672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9633 14:51:26.225467 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9634 14:51:26.228266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9635 14:51:26.232027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9636 14:51:26.235270 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9637 14:51:26.241822 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9638 14:51:26.245053 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9639 14:51:26.248757 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9640 14:51:26.255308 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9641 14:51:26.258506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9642 14:51:26.264968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9643 14:51:26.268297 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9644 14:51:26.271950 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9645 14:51:26.278388 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9646 14:51:26.282205 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9647 14:51:26.285083 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9648 14:51:26.291602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9649 14:51:26.295386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9650 14:51:26.302649 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9651 14:51:26.305634 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9652 14:51:26.308868 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9653 14:51:26.315203 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9654 14:51:26.318634 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9655 14:51:26.325611 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9656 14:51:26.328323 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9657 14:51:26.332122 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9658 14:51:26.338448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9659 14:51:26.342219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9660 14:51:26.345134 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9661 14:51:26.352252 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9662 14:51:26.355431 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9663 14:51:26.362678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9664 14:51:26.365620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9665 14:51:26.368627 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9666 14:51:26.375379 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9667 14:51:26.379060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9668 14:51:26.382148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9669 14:51:26.388556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9670 14:51:26.391917 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9671 14:51:26.398916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9672 14:51:26.402068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9673 14:51:26.405881 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9674 14:51:26.412315 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9675 14:51:26.415629 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9676 14:51:26.422060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9677 14:51:26.425521 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9678 14:51:26.428761 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9679 14:51:26.435442 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9680 14:51:26.438725 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9681 14:51:26.445284 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9682 14:51:26.448450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9683 14:51:26.452152 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9684 14:51:26.458478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9685 14:51:26.461616 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9686 14:51:26.468152 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9687 14:51:26.472080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9688 14:51:26.475198 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9689 14:51:26.481829 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9690 14:51:26.484918 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9691 14:51:26.491725 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9692 14:51:26.494763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9693 14:51:26.498224 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9694 14:51:26.504615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9695 14:51:26.508373 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9696 14:51:26.511325 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9697 14:51:26.517933 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9698 14:51:26.521449 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9699 14:51:26.528292 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9700 14:51:26.531093 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9701 14:51:26.534529 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9702 14:51:26.541336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9703 14:51:26.544947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9704 14:51:26.551003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9705 14:51:26.554461 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9706 14:51:26.561132 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9707 14:51:26.564316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9708 14:51:26.568019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9709 14:51:26.574463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9710 14:51:26.578047 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9711 14:51:26.584283 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9712 14:51:26.587996 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9713 14:51:26.591000 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9714 14:51:26.597680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9715 14:51:26.600901 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9716 14:51:26.607304 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9717 14:51:26.610848 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9718 14:51:26.617438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9719 14:51:26.620642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9720 14:51:26.624251 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9721 14:51:26.631018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9722 14:51:26.633952 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9723 14:51:26.640749 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9724 14:51:26.644180 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9725 14:51:26.650607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9726 14:51:26.654412 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9727 14:51:26.657384 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9728 14:51:26.664038 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9729 14:51:26.666993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9730 14:51:26.674010 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9731 14:51:26.677405 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9732 14:51:26.680354 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9733 14:51:26.687204 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9734 14:51:26.690299 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9735 14:51:26.696980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9736 14:51:26.700651 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9737 14:51:26.703776 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9738 14:51:26.710529 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9739 14:51:26.713429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9740 14:51:26.720493 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9741 14:51:26.723586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9742 14:51:26.730628 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9743 14:51:26.733847 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9744 14:51:26.737404 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9745 14:51:26.740597 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9746 14:51:26.746709 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9747 14:51:26.750423 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9748 14:51:26.753414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9749 14:51:26.756950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9750 14:51:26.763213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9751 14:51:26.766952 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9752 14:51:26.773800 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9753 14:51:26.776799 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9754 14:51:26.779977 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9755 14:51:26.787099 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9756 14:51:26.790394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9757 14:51:26.793996 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9758 14:51:26.800178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9759 14:51:26.803145 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9760 14:51:26.807033 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9761 14:51:26.813342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9762 14:51:26.816877 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9763 14:51:26.820119 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9764 14:51:26.826793 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9765 14:51:26.830256 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9766 14:51:26.836302 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9767 14:51:26.840251 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9768 14:51:26.843317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9769 14:51:26.849709 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9770 14:51:26.853095 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9771 14:51:26.859480 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9772 14:51:26.862939 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9773 14:51:26.866117 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9774 14:51:26.872746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9775 14:51:26.876765 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9776 14:51:26.879445 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9777 14:51:26.886032 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9778 14:51:26.889339 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9779 14:51:26.893083 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9780 14:51:26.899600 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9781 14:51:26.903009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9782 14:51:26.909382 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9783 14:51:26.913065 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9784 14:51:26.916271 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9785 14:51:26.919917 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9786 14:51:26.925935 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9787 14:51:26.929617 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9788 14:51:26.932827 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9789 14:51:26.936288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9790 14:51:26.939859 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9791 14:51:26.946313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9792 14:51:26.949330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9793 14:51:26.953003 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9794 14:51:26.956019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9795 14:51:26.962785 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9796 14:51:26.966039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9797 14:51:26.969610 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9798 14:51:26.976000 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9799 14:51:26.979843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9800 14:51:26.986354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9801 14:51:26.989029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9802 14:51:26.996156 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9803 14:51:26.999111 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9804 14:51:27.002307 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9805 14:51:27.009306 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9806 14:51:27.012670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9807 14:51:27.019137 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9808 14:51:27.022107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9809 14:51:27.025806 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9810 14:51:27.032288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9811 14:51:27.035370 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9812 14:51:27.042173 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9813 14:51:27.045423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9814 14:51:27.049019 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9815 14:51:27.055337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9816 14:51:27.058912 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9817 14:51:27.065158 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9818 14:51:27.068823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9819 14:51:27.075073 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9820 14:51:27.078923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9821 14:51:27.081977 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9822 14:51:27.088694 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9823 14:51:27.092398 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9824 14:51:27.098332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9825 14:51:27.101961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9826 14:51:27.105555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9827 14:51:27.112042 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9828 14:51:27.114863 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9829 14:51:27.122101 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9830 14:51:27.125456 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9831 14:51:27.128188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9832 14:51:27.134977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9833 14:51:27.138226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9834 14:51:27.144926 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9835 14:51:27.148531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9836 14:51:27.151573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9837 14:51:27.158160 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9838 14:51:27.161707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9839 14:51:27.168313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9840 14:51:27.171393 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9841 14:51:27.178319 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9842 14:51:27.181452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9843 14:51:27.184708 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9844 14:51:27.191475 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9845 14:51:27.194939 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9846 14:51:27.201956 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9847 14:51:27.204782 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9848 14:51:27.207999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9849 14:51:27.214716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9850 14:51:27.218434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9851 14:51:27.224975 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9852 14:51:27.228074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9853 14:51:27.231608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9854 14:51:27.238184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9855 14:51:27.241330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9856 14:51:27.248421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9857 14:51:27.251572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9858 14:51:27.258220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9859 14:51:27.261040 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9860 14:51:27.264257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9861 14:51:27.270957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9862 14:51:27.274197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9863 14:51:27.280870 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9864 14:51:27.284093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9865 14:51:27.287362 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9866 14:51:27.294168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9867 14:51:27.297468 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9868 14:51:27.303894 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9869 14:51:27.307645 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9870 14:51:27.314276 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9871 14:51:27.317576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9872 14:51:27.320881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9873 14:51:27.327304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9874 14:51:27.330962 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9875 14:51:27.337439 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9876 14:51:27.340483 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9877 14:51:27.347239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9878 14:51:27.350855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9879 14:51:27.353991 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9880 14:51:27.360865 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9881 14:51:27.363970 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9882 14:51:27.370253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9883 14:51:27.374187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9884 14:51:27.380917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9885 14:51:27.384888 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9886 14:51:27.387060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9887 14:51:27.393796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9888 14:51:27.396714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9889 14:51:27.403383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9890 14:51:27.406993 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9891 14:51:27.413407 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9892 14:51:27.416906 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9893 14:51:27.423548 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9894 14:51:27.426619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9895 14:51:27.429752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9896 14:51:27.436755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9897 14:51:27.440306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9898 14:51:27.447213 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9899 14:51:27.450265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9900 14:51:27.453228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9901 14:51:27.460071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9902 14:51:27.463238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9903 14:51:27.470052 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9904 14:51:27.473593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9905 14:51:27.480467 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9906 14:51:27.483312 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9907 14:51:27.490277 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9908 14:51:27.493260 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9909 14:51:27.497101 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9910 14:51:27.503544 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9911 14:51:27.506493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9912 14:51:27.513121 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9913 14:51:27.516711 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9914 14:51:27.523679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9915 14:51:27.526408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9916 14:51:27.529820 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9917 14:51:27.536828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9918 14:51:27.540173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9919 14:51:27.546905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9920 14:51:27.549845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9921 14:51:27.557130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9922 14:51:27.560259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9923 14:51:27.566742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9924 14:51:27.569629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9925 14:51:27.573473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9926 14:51:27.579784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9927 14:51:27.583082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9928 14:51:27.589721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9929 14:51:27.593067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9930 14:51:27.599959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9931 14:51:27.602990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9932 14:51:27.609865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9933 14:51:27.613012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9934 14:51:27.619936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9935 14:51:27.623173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9936 14:51:27.629674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9937 14:51:27.632895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9938 14:51:27.639531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9939 14:51:27.642614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9940 14:51:27.649327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9941 14:51:27.652806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9942 14:51:27.659386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9943 14:51:27.662448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9944 14:51:27.668942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9945 14:51:27.672518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9946 14:51:27.679028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9947 14:51:27.682821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9948 14:51:27.689209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9949 14:51:27.692600 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9950 14:51:27.695718 INFO: [APUAPC] vio 0
9951 14:51:27.698753 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9952 14:51:27.705579 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9953 14:51:27.709404 INFO: [APUAPC] D0_APC_0: 0x400510
9954 14:51:27.712626 INFO: [APUAPC] D0_APC_1: 0x0
9955 14:51:27.712732 INFO: [APUAPC] D0_APC_2: 0x1540
9956 14:51:27.715517 INFO: [APUAPC] D0_APC_3: 0x0
9957 14:51:27.718881 INFO: [APUAPC] D1_APC_0: 0xffffffff
9958 14:51:27.722458 INFO: [APUAPC] D1_APC_1: 0xffffffff
9959 14:51:27.725873 INFO: [APUAPC] D1_APC_2: 0x3fffff
9960 14:51:27.729319 INFO: [APUAPC] D1_APC_3: 0x0
9961 14:51:27.732020 INFO: [APUAPC] D2_APC_0: 0xffffffff
9962 14:51:27.735702 INFO: [APUAPC] D2_APC_1: 0xffffffff
9963 14:51:27.738800 INFO: [APUAPC] D2_APC_2: 0x3fffff
9964 14:51:27.742404 INFO: [APUAPC] D2_APC_3: 0x0
9965 14:51:27.745527 INFO: [APUAPC] D3_APC_0: 0xffffffff
9966 14:51:27.748771 INFO: [APUAPC] D3_APC_1: 0xffffffff
9967 14:51:27.752054 INFO: [APUAPC] D3_APC_2: 0x3fffff
9968 14:51:27.755698 INFO: [APUAPC] D3_APC_3: 0x0
9969 14:51:27.758863 INFO: [APUAPC] D4_APC_0: 0xffffffff
9970 14:51:27.762305 INFO: [APUAPC] D4_APC_1: 0xffffffff
9971 14:51:27.765517 INFO: [APUAPC] D4_APC_2: 0x3fffff
9972 14:51:27.769240 INFO: [APUAPC] D4_APC_3: 0x0
9973 14:51:27.772310 INFO: [APUAPC] D5_APC_0: 0xffffffff
9974 14:51:27.775437 INFO: [APUAPC] D5_APC_1: 0xffffffff
9975 14:51:27.778928 INFO: [APUAPC] D5_APC_2: 0x3fffff
9976 14:51:27.782069 INFO: [APUAPC] D5_APC_3: 0x0
9977 14:51:27.785636 INFO: [APUAPC] D6_APC_0: 0xffffffff
9978 14:51:27.788883 INFO: [APUAPC] D6_APC_1: 0xffffffff
9979 14:51:27.792728 INFO: [APUAPC] D6_APC_2: 0x3fffff
9980 14:51:27.795764 INFO: [APUAPC] D6_APC_3: 0x0
9981 14:51:27.798739 INFO: [APUAPC] D7_APC_0: 0xffffffff
9982 14:51:27.802321 INFO: [APUAPC] D7_APC_1: 0xffffffff
9983 14:51:27.805277 INFO: [APUAPC] D7_APC_2: 0x3fffff
9984 14:51:27.808668 INFO: [APUAPC] D7_APC_3: 0x0
9985 14:51:27.812162 INFO: [APUAPC] D8_APC_0: 0xffffffff
9986 14:51:27.815395 INFO: [APUAPC] D8_APC_1: 0xffffffff
9987 14:51:27.818321 INFO: [APUAPC] D8_APC_2: 0x3fffff
9988 14:51:27.821809 INFO: [APUAPC] D8_APC_3: 0x0
9989 14:51:27.824992 INFO: [APUAPC] D9_APC_0: 0xffffffff
9990 14:51:27.828746 INFO: [APUAPC] D9_APC_1: 0xffffffff
9991 14:51:27.832462 INFO: [APUAPC] D9_APC_2: 0x3fffff
9992 14:51:27.835337 INFO: [APUAPC] D9_APC_3: 0x0
9993 14:51:27.838429 INFO: [APUAPC] D10_APC_0: 0xffffffff
9994 14:51:27.841859 INFO: [APUAPC] D10_APC_1: 0xffffffff
9995 14:51:27.844976 INFO: [APUAPC] D10_APC_2: 0x3fffff
9996 14:51:27.848358 INFO: [APUAPC] D10_APC_3: 0x0
9997 14:51:27.851880 INFO: [APUAPC] D11_APC_0: 0xffffffff
9998 14:51:27.855157 INFO: [APUAPC] D11_APC_1: 0xffffffff
9999 14:51:27.858489 INFO: [APUAPC] D11_APC_2: 0x3fffff
10000 14:51:27.861527 INFO: [APUAPC] D11_APC_3: 0x0
10001 14:51:27.865194 INFO: [APUAPC] D12_APC_0: 0xffffffff
10002 14:51:27.868253 INFO: [APUAPC] D12_APC_1: 0xffffffff
10003 14:51:27.871426 INFO: [APUAPC] D12_APC_2: 0x3fffff
10004 14:51:27.874884 INFO: [APUAPC] D12_APC_3: 0x0
10005 14:51:27.877964 INFO: [APUAPC] D13_APC_0: 0xffffffff
10006 14:51:27.881843 INFO: [APUAPC] D13_APC_1: 0xffffffff
10007 14:51:27.884722 INFO: [APUAPC] D13_APC_2: 0x3fffff
10008 14:51:27.887815 INFO: [APUAPC] D13_APC_3: 0x0
10009 14:51:27.891602 INFO: [APUAPC] D14_APC_0: 0xffffffff
10010 14:51:27.895030 INFO: [APUAPC] D14_APC_1: 0xffffffff
10011 14:51:27.898250 INFO: [APUAPC] D14_APC_2: 0x3fffff
10012 14:51:27.901788 INFO: [APUAPC] D14_APC_3: 0x0
10013 14:51:27.904678 INFO: [APUAPC] D15_APC_0: 0xffffffff
10014 14:51:27.908054 INFO: [APUAPC] D15_APC_1: 0xffffffff
10015 14:51:27.911815 INFO: [APUAPC] D15_APC_2: 0x3fffff
10016 14:51:27.914800 INFO: [APUAPC] D15_APC_3: 0x0
10017 14:51:27.917984 INFO: [APUAPC] APC_CON: 0x4
10018 14:51:27.921354 INFO: [NOCDAPC] D0_APC_0: 0x0
10019 14:51:27.921445 INFO: [NOCDAPC] D0_APC_1: 0x0
10020 14:51:27.924560 INFO: [NOCDAPC] D1_APC_0: 0x0
10021 14:51:27.927670 INFO: [NOCDAPC] D1_APC_1: 0xfff
10022 14:51:27.931361 INFO: [NOCDAPC] D2_APC_0: 0x0
10023 14:51:27.934659 INFO: [NOCDAPC] D2_APC_1: 0xfff
10024 14:51:27.937799 INFO: [NOCDAPC] D3_APC_0: 0x0
10025 14:51:27.941309 INFO: [NOCDAPC] D3_APC_1: 0xfff
10026 14:51:27.944809 INFO: [NOCDAPC] D4_APC_0: 0x0
10027 14:51:27.947610 INFO: [NOCDAPC] D4_APC_1: 0xfff
10028 14:51:27.951138 INFO: [NOCDAPC] D5_APC_0: 0x0
10029 14:51:27.951248 INFO: [NOCDAPC] D5_APC_1: 0xfff
10030 14:51:27.954317 INFO: [NOCDAPC] D6_APC_0: 0x0
10031 14:51:27.958227 INFO: [NOCDAPC] D6_APC_1: 0xfff
10032 14:51:27.961060 INFO: [NOCDAPC] D7_APC_0: 0x0
10033 14:51:27.964240 INFO: [NOCDAPC] D7_APC_1: 0xfff
10034 14:51:27.967874 INFO: [NOCDAPC] D8_APC_0: 0x0
10035 14:51:27.970887 INFO: [NOCDAPC] D8_APC_1: 0xfff
10036 14:51:27.974560 INFO: [NOCDAPC] D9_APC_0: 0x0
10037 14:51:27.977453 INFO: [NOCDAPC] D9_APC_1: 0xfff
10038 14:51:27.981326 INFO: [NOCDAPC] D10_APC_0: 0x0
10039 14:51:27.984326 INFO: [NOCDAPC] D10_APC_1: 0xfff
10040 14:51:27.988002 INFO: [NOCDAPC] D11_APC_0: 0x0
10041 14:51:27.988118 INFO: [NOCDAPC] D11_APC_1: 0xfff
10042 14:51:27.991153 INFO: [NOCDAPC] D12_APC_0: 0x0
10043 14:51:27.994393 INFO: [NOCDAPC] D12_APC_1: 0xfff
10044 14:51:27.998004 INFO: [NOCDAPC] D13_APC_0: 0x0
10045 14:51:28.001204 INFO: [NOCDAPC] D13_APC_1: 0xfff
10046 14:51:28.004751 INFO: [NOCDAPC] D14_APC_0: 0x0
10047 14:51:28.007441 INFO: [NOCDAPC] D14_APC_1: 0xfff
10048 14:51:28.011350 INFO: [NOCDAPC] D15_APC_0: 0x0
10049 14:51:28.014452 INFO: [NOCDAPC] D15_APC_1: 0xfff
10050 14:51:28.017515 INFO: [NOCDAPC] APC_CON: 0x4
10051 14:51:28.021004 INFO: [APUAPC] set_apusys_apc done
10052 14:51:28.024062 INFO: [DEVAPC] devapc_init done
10053 14:51:28.027510 INFO: GICv3 without legacy support detected.
10054 14:51:28.030829 INFO: ARM GICv3 driver initialized in EL3
10055 14:51:28.034268 INFO: Maximum SPI INTID supported: 639
10056 14:51:28.041234 INFO: BL31: Initializing runtime services
10057 14:51:28.044325 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10058 14:51:28.047415 INFO: SPM: enable CPC mode
10059 14:51:28.053891 INFO: mcdi ready for mcusys-off-idle and system suspend
10060 14:51:28.057295 INFO: BL31: Preparing for EL3 exit to normal world
10061 14:51:28.060676 INFO: Entry point address = 0x80000000
10062 14:51:28.063870 INFO: SPSR = 0x8
10063 14:51:28.068902
10064 14:51:28.069005
10065 14:51:28.069088
10066 14:51:28.072549 Starting depthcharge on Spherion...
10067 14:51:28.072628
10068 14:51:28.072694 Wipe memory regions:
10069 14:51:28.072754
10070 14:51:28.073594 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10071 14:51:28.073724 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10072 14:51:28.073836 Setting prompt string to ['asurada:']
10073 14:51:28.073961 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10074 14:51:28.075953 [0x00000040000000, 0x00000054600000)
10075 14:51:28.197855
10076 14:51:28.198053 [0x00000054660000, 0x00000080000000)
10077 14:51:28.458422
10078 14:51:28.458593 [0x000000821a7280, 0x000000ffe64000)
10079 14:51:29.201916
10080 14:51:29.202102 [0x00000100000000, 0x00000240000000)
10081 14:51:31.088196
10082 14:51:31.090952 Initializing XHCI USB controller at 0x11200000.
10083 14:51:32.129558
10084 14:51:32.132831 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10085 14:51:32.132927
10086 14:51:32.133013
10087 14:51:32.133321 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 14:51:32.233699 asurada: tftpboot 192.168.201.1 14167012/tftp-deploy-q261glni/kernel/image.itb 14167012/tftp-deploy-q261glni/kernel/cmdline
10090 14:51:32.233879 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 14:51:32.233982 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 14:51:32.237849 tftpboot 192.168.201.1 14167012/tftp-deploy-q261glni/kernel/image.ittp-deploy-q261glni/kernel/cmdline
10093 14:51:32.237937
10094 14:51:32.238020 Waiting for link
10095 14:51:32.398796
10096 14:51:32.398947 R8152: Initializing
10097 14:51:32.399045
10098 14:51:32.401820 Version 9 (ocp_data = 6010)
10099 14:51:32.401906
10100 14:51:32.404937 R8152: Done initializing
10101 14:51:32.405019
10102 14:51:32.405083 Adding net device
10103 14:51:34.278392
10104 14:51:34.278528 done.
10105 14:51:34.278597
10106 14:51:34.278657 MAC: 00:e0:4c:78:7a:aa
10107 14:51:34.278718
10108 14:51:34.281168 Sending DHCP discover... done.
10109 14:51:34.281256
10110 14:51:34.284359 Waiting for reply... done.
10111 14:51:34.284452
10112 14:51:34.287708 Sending DHCP request... done.
10113 14:51:34.287818
10114 14:51:34.287909 Waiting for reply... done.
10115 14:51:34.287996
10116 14:51:34.290905 My ip is 192.168.201.12
10117 14:51:34.291028
10118 14:51:34.294375 The DHCP server ip is 192.168.201.1
10119 14:51:34.294462
10120 14:51:34.297612 TFTP server IP predefined by user: 192.168.201.1
10121 14:51:34.297698
10122 14:51:34.304531 Bootfile predefined by user: 14167012/tftp-deploy-q261glni/kernel/image.itb
10123 14:51:34.304624
10124 14:51:34.308016 Sending tftp read request... done.
10125 14:51:34.308150
10126 14:51:34.311015 Waiting for the transfer...
10127 14:51:34.311126
10128 14:51:34.574552 00000000 ################################################################
10129 14:51:34.574754
10130 14:51:34.832908 00080000 ################################################################
10131 14:51:34.833088
10132 14:51:35.096192 00100000 ################################################################
10133 14:51:35.096437
10134 14:51:35.382720 00180000 ################################################################
10135 14:51:35.382910
10136 14:51:35.651884 00200000 ################################################################
10137 14:51:35.652087
10138 14:51:35.927549 00280000 ################################################################
10139 14:51:35.927749
10140 14:51:36.198546 00300000 ################################################################
10141 14:51:36.198696
10142 14:51:36.460143 00380000 ################################################################
10143 14:51:36.460292
10144 14:51:36.728759 00400000 ################################################################
10145 14:51:36.728953
10146 14:51:37.018092 00480000 ################################################################
10147 14:51:37.018273
10148 14:51:37.311233 00500000 ################################################################
10149 14:51:37.311385
10150 14:51:37.592307 00580000 ################################################################
10151 14:51:37.592492
10152 14:51:37.880873 00600000 ################################################################
10153 14:51:37.881047
10154 14:51:38.177396 00680000 ################################################################
10155 14:51:38.177534
10156 14:51:38.469410 00700000 ################################################################
10157 14:51:38.469544
10158 14:51:38.741290 00780000 ################################################################
10159 14:51:38.741431
10160 14:51:39.007273 00800000 ################################################################
10161 14:51:39.007443
10162 14:51:39.268101 00880000 ################################################################
10163 14:51:39.268248
10164 14:51:39.557362 00900000 ################################################################
10165 14:51:39.557533
10166 14:51:39.815078 00980000 ################################################################
10167 14:51:39.815246
10168 14:51:40.069956 00a00000 ################################################################
10169 14:51:40.070124
10170 14:51:40.357416 00a80000 ################################################################
10171 14:51:40.357582
10172 14:51:40.612871 00b00000 ################################################################
10173 14:51:40.613034
10174 14:51:40.886365 00b80000 ################################################################
10175 14:51:40.886531
10176 14:51:41.141682 00c00000 ################################################################
10177 14:51:41.141817
10178 14:51:41.402295 00c80000 ################################################################
10179 14:51:41.402462
10180 14:51:41.662485 00d00000 ################################################################
10181 14:51:41.662655
10182 14:51:41.932007 00d80000 ################################################################
10183 14:51:41.932175
10184 14:51:42.191128 00e00000 ################################################################
10185 14:51:42.191296
10186 14:51:42.455433 00e80000 ################################################################
10187 14:51:42.455601
10188 14:51:42.742176 00f00000 ################################################################
10189 14:51:42.742340
10190 14:51:43.017253 00f80000 ################################################################
10191 14:51:43.017387
10192 14:51:43.284247 01000000 ################################################################
10193 14:51:43.284432
10194 14:51:43.576690 01080000 ################################################################
10195 14:51:43.576888
10196 14:51:43.870162 01100000 ################################################################
10197 14:51:43.870336
10198 14:51:44.141797 01180000 ################################################################
10199 14:51:44.141994
10200 14:51:44.438430 01200000 ################################################################
10201 14:51:44.438605
10202 14:51:44.731604 01280000 ################################################################
10203 14:51:44.731779
10204 14:51:45.016149 01300000 ################################################################
10205 14:51:45.016345
10206 14:51:45.290105 01380000 ################################################################
10207 14:51:45.290253
10208 14:51:45.562688 01400000 ################################################################
10209 14:51:45.562850
10210 14:51:45.832772 01480000 ################################################################
10211 14:51:45.832960
10212 14:51:46.114112 01500000 ################################################################
10213 14:51:46.114263
10214 14:51:46.400611 01580000 ################################################################
10215 14:51:46.400765
10216 14:51:46.684027 01600000 ################################################################
10217 14:51:46.684180
10218 14:51:46.951182 01680000 ################################################################
10219 14:51:46.951322
10220 14:51:47.200039 01700000 ################################################################
10221 14:51:47.200240
10222 14:51:47.459383 01780000 ################################################################
10223 14:51:47.459541
10224 14:51:47.724190 01800000 ################################################################
10225 14:51:47.724336
10226 14:51:47.989988 01880000 ################################################################
10227 14:51:47.990139
10228 14:51:48.249391 01900000 ################################################################
10229 14:51:48.249548
10230 14:51:48.492150 01980000 ################################################################
10231 14:51:48.492354
10232 14:51:48.735411 01a00000 ################################################################
10233 14:51:48.735567
10234 14:51:48.987531 01a80000 ################################################################
10235 14:51:48.987687
10236 14:51:49.247090 01b00000 ################################################################
10237 14:51:49.247240
10238 14:51:49.493327 01b80000 ################################################################
10239 14:51:49.493504
10240 14:51:49.743904 01c00000 ################################################################
10241 14:51:49.744057
10242 14:51:49.995556 01c80000 ################################################################
10243 14:51:49.995733
10244 14:51:50.247158 01d00000 ################################################################
10245 14:51:50.247304
10246 14:51:50.495534 01d80000 ################################################################
10247 14:51:50.495710
10248 14:51:50.687656 01e00000 ################################################ done.
10249 14:51:50.687809
10250 14:51:50.690948 The bootfile was 31842382 bytes long.
10251 14:51:50.691066
10252 14:51:50.694133 Sending tftp read request... done.
10253 14:51:50.694228
10254 14:51:50.694296 Waiting for the transfer...
10255 14:51:50.694357
10256 14:51:50.697684 00000000 # done.
10257 14:51:50.697802
10258 14:51:50.704361 Command line loaded dynamically from TFTP file: 14167012/tftp-deploy-q261glni/kernel/cmdline
10259 14:51:50.704479
10260 14:51:50.727400 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10261 14:51:50.727529
10262 14:51:50.727598 Loading FIT.
10263 14:51:50.727659
10264 14:51:50.730452 Image ramdisk-1 has 18732471 bytes.
10265 14:51:50.730561
10266 14:51:50.733719 Image fdt-1 has 47258 bytes.
10267 14:51:50.733832
10268 14:51:50.737552 Image kernel-1 has 13060619 bytes.
10269 14:51:50.737642
10270 14:51:50.747021 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10271 14:51:50.747132
10272 14:51:50.763999 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10273 14:51:50.764151
10274 14:51:50.770344 Choosing best match conf-1 for compat google,spherion-rev2.
10275 14:51:50.770441
10276 14:51:50.778143 Connected to device vid:did:rid of 1ae0:0028:00
10277 14:51:50.786528
10278 14:51:50.789565 tpm_get_response: command 0x17b, return code 0x0
10279 14:51:50.789659
10280 14:51:50.792764 ec_init: CrosEC protocol v3 supported (256, 248)
10281 14:51:50.797028
10282 14:51:50.800148 tpm_cleanup: add release locality here.
10283 14:51:50.800231
10284 14:51:50.800314 Shutting down all USB controllers.
10285 14:51:50.803271
10286 14:51:50.803354 Removing current net device
10287 14:51:50.803419
10288 14:51:50.810311 Exiting depthcharge with code 4 at timestamp: 51994622
10289 14:51:50.810397
10290 14:51:50.813700 LZMA decompressing kernel-1 to 0x821a6718
10291 14:51:50.813783
10292 14:51:50.816656 LZMA decompressing kernel-1 to 0x40000000
10293 14:51:52.429300
10294 14:51:52.429455 jumping to kernel
10295 14:51:52.429937 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10296 14:51:52.430036 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10297 14:51:52.430112 Setting prompt string to ['Linux version [0-9]']
10298 14:51:52.430179 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10299 14:51:52.430245 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10300 14:51:52.512472
10301 14:51:52.515417 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10302 14:51:52.519341 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10303 14:51:52.519448 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10304 14:51:52.519521 Setting prompt string to []
10305 14:51:52.519596 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10306 14:51:52.519669 Using line separator: #'\n'#
10307 14:51:52.519728 No login prompt set.
10308 14:51:52.519790 Parsing kernel messages
10309 14:51:52.519845 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10310 14:51:52.519945 [login-action] Waiting for messages, (timeout 00:04:01)
10311 14:51:52.520010 Waiting using forced prompt support (timeout 00:02:00)
10312 14:51:52.538593 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10313 14:51:52.542392 [ 0.000000] random: crng init done
10314 14:51:52.548549 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 14:51:52.552209 [ 0.000000] efi: UEFI not found.
10316 14:51:52.558521 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 14:51:52.565055 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 14:51:52.575614 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 14:51:52.585055 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 14:51:52.591788 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 14:51:52.598575 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 14:51:52.605400 [ 0.000000] NUMA: No NUMA configuration found
10323 14:51:52.611548 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 14:51:52.615206 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10325 14:51:52.618192 [ 0.000000] Zone ranges:
10326 14:51:52.624821 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 14:51:52.628523 [ 0.000000] DMA32 empty
10328 14:51:52.635060 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 14:51:52.638566 [ 0.000000] Movable zone start for each node
10330 14:51:52.641731 [ 0.000000] Early memory node ranges
10331 14:51:52.648678 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 14:51:52.654900 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 14:51:52.661822 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 14:51:52.665253 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 14:51:52.671830 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 14:51:52.678298 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 14:51:52.735894 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 14:51:52.742369 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 14:51:52.749365 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 14:51:52.752115 [ 0.000000] psci: probing for conduit method from DT.
10341 14:51:52.759376 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 14:51:52.762346 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 14:51:52.769296 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 14:51:52.772617 [ 0.000000] psci: SMC Calling Convention v1.2
10345 14:51:52.779215 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10346 14:51:52.782480 [ 0.000000] Detected VIPT I-cache on CPU0
10347 14:51:52.789248 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 14:51:52.796017 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 14:51:52.802872 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 14:51:52.809033 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 14:51:52.815824 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 14:51:52.822451 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 14:51:52.829278 [ 0.000000] alternatives: applying boot alternatives
10354 14:51:52.832543 [ 0.000000] Fallback order for Node 0: 0
10355 14:51:52.838704 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 14:51:52.842608 [ 0.000000] Policy zone: Normal
10357 14:51:52.865204 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10358 14:51:52.879219 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 14:51:52.888780 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 14:51:52.899178 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 14:51:52.905629 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 14:51:52.908833 <6>[ 0.000000] software IO TLB: area num 8.
10363 14:51:52.965237 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 14:51:53.114374 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10365 14:51:53.121205 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 14:51:53.127806 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 14:51:53.131034 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 14:51:53.137546 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 14:51:53.144070 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 14:51:53.147358 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 14:51:53.158005 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 14:51:53.164165 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 14:51:53.167588 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 14:51:53.175240 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 14:51:53.178980 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 14:51:53.185568 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 14:51:53.188602 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 14:51:53.192161 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 14:51:53.201880 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 14:51:53.212088 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 14:51:53.225262 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 14:51:53.231703 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 14:51:53.240591 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 14:51:53.253968 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 14:51:53.260860 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 14:51:53.267497 <6>[ 0.009230] Console: colour dummy device 80x25
10387 14:51:53.277197 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 14:51:53.284166 <6>[ 0.024464] pid_max: default: 32768 minimum: 301
10389 14:51:53.287425 <6>[ 0.029335] LSM: Security Framework initializing
10390 14:51:53.293731 <6>[ 0.034271] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 14:51:53.303939 <6>[ 0.042133] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 14:51:53.313959 <6>[ 0.051550] cblist_init_generic: Setting adjustable number of callback queues.
10393 14:51:53.317117 <6>[ 0.059039] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 14:51:53.326968 <6>[ 0.065418] cblist_init_generic: Setting adjustable number of callback queues.
10395 14:51:53.334001 <6>[ 0.072845] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 14:51:53.337003 <6>[ 0.079243] rcu: Hierarchical SRCU implementation.
10397 14:51:53.344113 <6>[ 0.084266] rcu: Max phase no-delay instances is 1000.
10398 14:51:53.350504 <6>[ 0.091298] EFI services will not be available.
10399 14:51:53.353794 <6>[ 0.096284] smp: Bringing up secondary CPUs ...
10400 14:51:53.361914 <6>[ 0.101333] Detected VIPT I-cache on CPU1
10401 14:51:53.368519 <6>[ 0.101405] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 14:51:53.375318 <6>[ 0.101436] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 14:51:53.378764 <6>[ 0.101772] Detected VIPT I-cache on CPU2
10404 14:51:53.384999 <6>[ 0.101823] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 14:51:53.391876 <6>[ 0.101841] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 14:51:53.398614 <6>[ 0.102099] Detected VIPT I-cache on CPU3
10407 14:51:53.404952 <6>[ 0.102147] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 14:51:53.411758 <6>[ 0.102161] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 14:51:53.414802 <6>[ 0.102468] CPU features: detected: Spectre-v4
10410 14:51:53.421631 <6>[ 0.102474] CPU features: detected: Spectre-BHB
10411 14:51:53.424783 <6>[ 0.102479] Detected PIPT I-cache on CPU4
10412 14:51:53.431404 <6>[ 0.102534] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 14:51:53.437708 <6>[ 0.102550] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 14:51:53.444561 <6>[ 0.102846] Detected PIPT I-cache on CPU5
10415 14:51:53.451364 <6>[ 0.102910] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 14:51:53.458262 <6>[ 0.102926] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 14:51:53.460955 <6>[ 0.103207] Detected PIPT I-cache on CPU6
10418 14:51:53.467839 <6>[ 0.103272] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 14:51:53.474618 <6>[ 0.103288] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 14:51:53.481178 <6>[ 0.103585] Detected PIPT I-cache on CPU7
10421 14:51:53.487809 <6>[ 0.103649] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 14:51:53.494418 <6>[ 0.103665] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 14:51:53.498189 <6>[ 0.103713] smp: Brought up 1 node, 8 CPUs
10424 14:51:53.505087 <6>[ 0.245170] SMP: Total of 8 processors activated.
10425 14:51:53.507913 <6>[ 0.250090] CPU features: detected: 32-bit EL0 Support
10426 14:51:53.517927 <6>[ 0.255487] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 14:51:53.524728 <6>[ 0.264288] CPU features: detected: Common not Private translations
10428 14:51:53.527866 <6>[ 0.270763] CPU features: detected: CRC32 instructions
10429 14:51:53.534617 <6>[ 0.276115] CPU features: detected: RCpc load-acquire (LDAPR)
10430 14:51:53.541031 <6>[ 0.282075] CPU features: detected: LSE atomic instructions
10431 14:51:53.547862 <6>[ 0.287857] CPU features: detected: Privileged Access Never
10432 14:51:53.550956 <6>[ 0.293636] CPU features: detected: RAS Extension Support
10433 14:51:53.561256 <6>[ 0.299280] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 14:51:53.564086 <6>[ 0.306500] CPU: All CPU(s) started at EL2
10435 14:51:53.570306 <6>[ 0.310816] alternatives: applying system-wide alternatives
10436 14:51:53.579528 <6>[ 0.321662] devtmpfs: initialized
10437 14:51:53.592136 <6>[ 0.330649] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 14:51:53.602148 <6>[ 0.340612] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 14:51:53.608471 <6>[ 0.348553] pinctrl core: initialized pinctrl subsystem
10440 14:51:53.611566 <6>[ 0.355200] DMI not present or invalid.
10441 14:51:53.618690 <6>[ 0.359611] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 14:51:53.628713 <6>[ 0.366470] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 14:51:53.634853 <6>[ 0.374061] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 14:51:53.644977 <6>[ 0.382273] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 14:51:53.648229 <6>[ 0.390513] audit: initializing netlink subsys (disabled)
10446 14:51:53.658214 <5>[ 0.396206] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10447 14:51:53.665101 <6>[ 0.396911] thermal_sys: Registered thermal governor 'step_wise'
10448 14:51:53.671303 <6>[ 0.404171] thermal_sys: Registered thermal governor 'power_allocator'
10449 14:51:53.675001 <6>[ 0.410427] cpuidle: using governor menu
10450 14:51:53.678033 <6>[ 0.421384] NET: Registered PF_QIPCRTR protocol family
10451 14:51:53.688371 <6>[ 0.426868] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 14:51:53.691376 <6>[ 0.433971] ASID allocator initialised with 32768 entries
10453 14:51:53.698737 <6>[ 0.440550] Serial: AMBA PL011 UART driver
10454 14:51:53.707288 <4>[ 0.449307] Trying to register duplicate clock ID: 134
10455 14:51:53.767289 <6>[ 0.512428] KASLR enabled
10456 14:51:53.781733 <6>[ 0.520181] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 14:51:53.788092 <6>[ 0.527191] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 14:51:53.794729 <6>[ 0.533680] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 14:51:53.801324 <6>[ 0.540687] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 14:51:53.808252 <6>[ 0.547173] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 14:51:53.815047 <6>[ 0.554176] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 14:51:53.821184 <6>[ 0.560664] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 14:51:53.828022 <6>[ 0.567666] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 14:51:53.831177 <6>[ 0.575122] ACPI: Interpreter disabled.
10465 14:51:53.839564 <6>[ 0.581562] iommu: Default domain type: Translated
10466 14:51:53.846055 <6>[ 0.586709] iommu: DMA domain TLB invalidation policy: strict mode
10467 14:51:53.849391 <5>[ 0.593371] SCSI subsystem initialized
10468 14:51:53.856295 <6>[ 0.597619] usbcore: registered new interface driver usbfs
10469 14:51:53.862655 <6>[ 0.603351] usbcore: registered new interface driver hub
10470 14:51:53.866449 <6>[ 0.608901] usbcore: registered new device driver usb
10471 14:51:53.873054 <6>[ 0.615015] pps_core: LinuxPPS API ver. 1 registered
10472 14:51:53.882996 <6>[ 0.620210] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 14:51:53.886168 <6>[ 0.629553] PTP clock support registered
10474 14:51:53.889408 <6>[ 0.633793] EDAC MC: Ver: 3.0.0
10475 14:51:53.896706 <6>[ 0.638976] FPGA manager framework
10476 14:51:53.903400 <6>[ 0.642654] Advanced Linux Sound Architecture Driver Initialized.
10477 14:51:53.906910 <6>[ 0.649435] vgaarb: loaded
10478 14:51:53.913378 <6>[ 0.652585] clocksource: Switched to clocksource arch_sys_counter
10479 14:51:53.916831 <5>[ 0.659031] VFS: Disk quotas dquot_6.6.0
10480 14:51:53.923666 <6>[ 0.663216] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 14:51:53.926566 <6>[ 0.670411] pnp: PnP ACPI: disabled
10482 14:51:53.935268 <6>[ 0.677086] NET: Registered PF_INET protocol family
10483 14:51:53.944831 <6>[ 0.682671] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 14:51:53.956256 <6>[ 0.694986] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 14:51:53.966481 <6>[ 0.703799] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 14:51:53.972898 <6>[ 0.711770] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 14:51:53.979684 <6>[ 0.720470] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 14:51:53.991661 <6>[ 0.730216] TCP: Hash tables configured (established 65536 bind 65536)
10489 14:51:53.998267 <6>[ 0.737083] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 14:51:54.004791 <6>[ 0.744283] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 14:51:54.011500 <6>[ 0.751986] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 14:51:54.017792 <6>[ 0.758137] RPC: Registered named UNIX socket transport module.
10493 14:51:54.021385 <6>[ 0.764292] RPC: Registered udp transport module.
10494 14:51:54.027781 <6>[ 0.769226] RPC: Registered tcp transport module.
10495 14:51:54.034736 <6>[ 0.774160] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 14:51:54.037805 <6>[ 0.780825] PCI: CLS 0 bytes, default 64
10497 14:51:54.040958 <6>[ 0.785192] Unpacking initramfs...
10498 14:51:54.050976 <6>[ 0.788905] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 14:51:54.057772 <6>[ 0.797534] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 14:51:54.064108 <6>[ 0.806346] kvm [1]: IPA Size Limit: 40 bits
10501 14:51:54.067604 <6>[ 0.810874] kvm [1]: GICv3: no GICV resource entry
10502 14:51:54.074263 <6>[ 0.815894] kvm [1]: disabling GICv2 emulation
10503 14:51:54.081062 <6>[ 0.820587] kvm [1]: GIC system register CPU interface enabled
10504 14:51:54.083966 <6>[ 0.826755] kvm [1]: vgic interrupt IRQ18
10505 14:51:54.090788 <6>[ 0.832632] kvm [1]: VHE mode initialized successfully
10506 14:51:54.097215 <5>[ 0.839057] Initialise system trusted keyrings
10507 14:51:54.104084 <6>[ 0.843847] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 14:51:54.111937 <6>[ 0.853811] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 14:51:54.118783 <5>[ 0.860182] NFS: Registering the id_resolver key type
10510 14:51:54.121986 <5>[ 0.865487] Key type id_resolver registered
10511 14:51:54.128897 <5>[ 0.869901] Key type id_legacy registered
10512 14:51:54.135388 <6>[ 0.874186] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 14:51:54.141702 <6>[ 0.881109] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 14:51:54.148538 <6>[ 0.888822] 9p: Installing v9fs 9p2000 file system support
10515 14:51:54.185175 <5>[ 0.926970] Key type asymmetric registered
10516 14:51:54.188245 <5>[ 0.931299] Asymmetric key parser 'x509' registered
10517 14:51:54.198159 <6>[ 0.936435] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 14:51:54.201268 <6>[ 0.944049] io scheduler mq-deadline registered
10519 14:51:54.204846 <6>[ 0.948810] io scheduler kyber registered
10520 14:51:54.224121 <6>[ 0.965860] EINJ: ACPI disabled.
10521 14:51:54.256868 <4>[ 0.991985] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 14:51:54.266312 <4>[ 1.002618] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 14:51:54.281514 <6>[ 1.023418] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 14:51:54.289217 <6>[ 1.031372] printk: console [ttyS0] disabled
10525 14:51:54.317358 <6>[ 1.055999] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 14:51:54.324073 <6>[ 1.065471] printk: console [ttyS0] enabled
10527 14:51:54.327381 <6>[ 1.065471] printk: console [ttyS0] enabled
10528 14:51:54.334050 <6>[ 1.074367] printk: bootconsole [mtk8250] disabled
10529 14:51:54.337629 <6>[ 1.074367] printk: bootconsole [mtk8250] disabled
10530 14:51:54.344219 <6>[ 1.085421] SuperH (H)SCI(F) driver initialized
10531 14:51:54.346974 <6>[ 1.090697] msm_serial: driver initialized
10532 14:51:54.361235 <6>[ 1.099610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10533 14:51:54.370581 <6>[ 1.108161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10534 14:51:54.377273 <6>[ 1.116703] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10535 14:51:54.387831 <6>[ 1.125330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10536 14:51:54.394190 <6>[ 1.134037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10537 14:51:54.404048 <6>[ 1.142751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10538 14:51:54.413998 <6>[ 1.151291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10539 14:51:54.420947 <6>[ 1.160093] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10540 14:51:54.430780 <6>[ 1.168636] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10541 14:51:54.441971 <6>[ 1.184279] loop: module loaded
10542 14:51:54.448749 <6>[ 1.190251] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10543 14:51:54.472001 <4>[ 1.213631] mtk-pmic-keys: Failed to locate of_node [id: -1]
10544 14:51:54.478499 <6>[ 1.220314] megasas: 07.719.03.00-rc1
10545 14:51:54.488055 <6>[ 1.229869] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10546 14:51:54.495012 <6>[ 1.235985] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10547 14:51:54.510882 <6>[ 1.252562] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 14:51:54.566866 <6>[ 1.302104] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10549 14:51:54.834244 <6>[ 1.576300] Freeing initrd memory: 18288K
10550 14:51:54.846263 <6>[ 1.588062] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10551 14:51:54.856795 <6>[ 1.598963] tun: Universal TUN/TAP device driver, 1.6
10552 14:51:54.860074 <6>[ 1.605029] thunder_xcv, ver 1.0
10553 14:51:54.863666 <6>[ 1.608527] thunder_bgx, ver 1.0
10554 14:51:54.867012 <6>[ 1.612026] nicpf, ver 1.0
10555 14:51:54.876998 <6>[ 1.616025] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10556 14:51:54.880670 <6>[ 1.623502] hns3: Copyright (c) 2017 Huawei Corporation.
10557 14:51:54.883741 <6>[ 1.629093] hclge is initializing
10558 14:51:54.890582 <6>[ 1.632674] e1000: Intel(R) PRO/1000 Network Driver
10559 14:51:54.897443 <6>[ 1.637803] e1000: Copyright (c) 1999-2006 Intel Corporation.
10560 14:51:54.900567 <6>[ 1.643815] e1000e: Intel(R) PRO/1000 Network Driver
10561 14:51:54.907144 <6>[ 1.649031] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10562 14:51:54.913866 <6>[ 1.655218] igb: Intel(R) Gigabit Ethernet Network Driver
10563 14:51:54.920573 <6>[ 1.660869] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 14:51:54.927083 <6>[ 1.666708] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 14:51:54.933620 <6>[ 1.673227] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 14:51:54.937203 <6>[ 1.679710] sky2: driver version 1.30
10567 14:51:54.943528 <6>[ 1.684649] usbcore: registered new device driver r8152-cfgselector
10568 14:51:54.950696 <6>[ 1.691184] usbcore: registered new interface driver r8152
10569 14:51:54.953884 <6>[ 1.696996] VFIO - User Level meta-driver version: 0.3
10570 14:51:54.962980 <6>[ 1.705204] usbcore: registered new interface driver usb-storage
10571 14:51:54.970124 <6>[ 1.711643] usbcore: registered new device driver onboard-usb-hub
10572 14:51:54.978512 <6>[ 1.720778] mt6397-rtc mt6359-rtc: registered as rtc0
10573 14:51:54.988718 <6>[ 1.726237] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:47:13 UTC (1717512433)
10574 14:51:54.992310 <6>[ 1.735797] i2c_dev: i2c /dev entries driver
10575 14:51:55.008673 <6>[ 1.747595] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10576 14:51:55.016018 <4>[ 1.756311] cpu cpu0: supply cpu not found, using dummy regulator
10577 14:51:55.022386 <4>[ 1.762737] cpu cpu1: supply cpu not found, using dummy regulator
10578 14:51:55.029159 <4>[ 1.769137] cpu cpu2: supply cpu not found, using dummy regulator
10579 14:51:55.035655 <4>[ 1.775539] cpu cpu3: supply cpu not found, using dummy regulator
10580 14:51:55.042505 <4>[ 1.781938] cpu cpu4: supply cpu not found, using dummy regulator
10581 14:51:55.049314 <4>[ 1.788357] cpu cpu5: supply cpu not found, using dummy regulator
10582 14:51:55.055743 <4>[ 1.794755] cpu cpu6: supply cpu not found, using dummy regulator
10583 14:51:55.059021 <4>[ 1.801149] cpu cpu7: supply cpu not found, using dummy regulator
10584 14:51:55.080922 <6>[ 1.822785] cpu cpu0: EM: created perf domain
10585 14:51:55.084040 <6>[ 1.827709] cpu cpu4: EM: created perf domain
10586 14:51:55.091103 <6>[ 1.833293] sdhci: Secure Digital Host Controller Interface driver
10587 14:51:55.097873 <6>[ 1.839725] sdhci: Copyright(c) Pierre Ossman
10588 14:51:55.104677 <6>[ 1.844681] Synopsys Designware Multimedia Card Interface Driver
10589 14:51:55.111068 <6>[ 1.851317] sdhci-pltfm: SDHCI platform and OF driver helper
10590 14:51:55.114243 <6>[ 1.851377] mmc0: CQHCI version 5.10
10591 14:51:55.121189 <6>[ 1.861556] ledtrig-cpu: registered to indicate activity on CPUs
10592 14:51:55.127570 <6>[ 1.868635] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10593 14:51:55.134473 <6>[ 1.875689] usbcore: registered new interface driver usbhid
10594 14:51:55.137486 <6>[ 1.881510] usbhid: USB HID core driver
10595 14:51:55.144603 <6>[ 1.885705] spi_master spi0: will run message pump with realtime priority
10596 14:51:55.186035 <6>[ 1.921755] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10597 14:51:55.205333 <6>[ 1.937179] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10598 14:51:55.212486 <6>[ 1.952167] cros-ec-spi spi0.0: Chrome EC device registered
10599 14:51:55.215631 <6>[ 1.958199] mmc0: Command Queue Engine enabled
10600 14:51:55.222401 <6>[ 1.962961] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10601 14:51:55.229085 <6>[ 1.970681] mmcblk0: mmc0:0001 DA4128 116 GiB
10602 14:51:55.239540 <6>[ 1.981402] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 14:51:55.246859 <6>[ 1.988800] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 14:51:55.253081 <6>[ 1.995012] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 14:51:55.263336 <6>[ 1.998760] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10606 14:51:55.270294 <6>[ 2.001039] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 14:51:55.273283 <6>[ 2.010485] NET: Registered PF_PACKET protocol family
10608 14:51:55.280049 <6>[ 2.021486] 9pnet: Installing 9P2000 support
10609 14:51:55.283113 <5>[ 2.026066] Key type dns_resolver registered
10610 14:51:55.290047 <6>[ 2.031162] registered taskstats version 1
10611 14:51:55.293069 <5>[ 2.035553] Loading compiled-in X.509 certificates
10612 14:51:55.322666 <4>[ 2.058331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 14:51:55.332858 <4>[ 2.069076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 14:51:55.347339 <6>[ 2.089372] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10615 14:51:55.354474 <6>[ 2.096375] xhci-mtk 11200000.usb: xHCI Host Controller
10616 14:51:55.360771 <6>[ 2.101885] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10617 14:51:55.371116 <6>[ 2.109750] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 14:51:55.377694 <6>[ 2.119198] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10619 14:51:55.384461 <6>[ 2.125301] xhci-mtk 11200000.usb: xHCI Host Controller
10620 14:51:55.390709 <6>[ 2.130787] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10621 14:51:55.397716 <6>[ 2.138527] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10622 14:51:55.404703 <6>[ 2.146370] hub 1-0:1.0: USB hub found
10623 14:51:55.407691 <6>[ 2.150399] hub 1-0:1.0: 1 port detected
10624 14:51:55.414442 <6>[ 2.154727] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10625 14:51:55.421273 <6>[ 2.163492] hub 2-0:1.0: USB hub found
10626 14:51:55.425026 <6>[ 2.167524] hub 2-0:1.0: 1 port detected
10627 14:51:55.432467 <6>[ 2.174908] mtk-msdc 11f70000.mmc: Got CD GPIO
10628 14:51:55.450886 <6>[ 2.189348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10629 14:51:55.457303 <6>[ 2.197373] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10630 14:51:55.467129 <4>[ 2.205318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10631 14:51:55.477405 <6>[ 2.214865] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10632 14:51:55.483667 <6>[ 2.222942] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10633 14:51:55.490860 <6>[ 2.230957] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10634 14:51:55.501116 <6>[ 2.238876] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10635 14:51:55.507187 <6>[ 2.246693] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10636 14:51:55.517256 <6>[ 2.254510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10637 14:51:55.527401 <6>[ 2.264916] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10638 14:51:55.533732 <6>[ 2.273296] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10639 14:51:55.543483 <6>[ 2.281637] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10640 14:51:55.550177 <6>[ 2.289975] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10641 14:51:55.560462 <6>[ 2.298313] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10642 14:51:55.566674 <6>[ 2.306651] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10643 14:51:55.576699 <6>[ 2.314989] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10644 14:51:55.583448 <6>[ 2.323327] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10645 14:51:55.593789 <6>[ 2.331665] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10646 14:51:55.599916 <6>[ 2.340003] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10647 14:51:55.610041 <6>[ 2.348340] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10648 14:51:55.616622 <6>[ 2.356679] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10649 14:51:55.626607 <6>[ 2.365018] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10650 14:51:55.633096 <6>[ 2.373356] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10651 14:51:55.642814 <6>[ 2.381694] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10652 14:51:55.649549 <6>[ 2.390430] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10653 14:51:55.656527 <6>[ 2.397600] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10654 14:51:55.662843 <6>[ 2.404368] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10655 14:51:55.669606 <6>[ 2.411141] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10656 14:51:55.676268 <6>[ 2.418072] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10657 14:51:55.686211 <6>[ 2.424939] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10658 14:51:55.695715 <6>[ 2.434078] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10659 14:51:55.706240 <6>[ 2.443199] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10660 14:51:55.716059 <6>[ 2.452493] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10661 14:51:55.723077 <6>[ 2.461960] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10662 14:51:55.732410 <6>[ 2.471428] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10663 14:51:55.742439 <6>[ 2.480547] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10664 14:51:55.752644 <6>[ 2.490013] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10665 14:51:55.762419 <6>[ 2.499132] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10666 14:51:55.772145 <6>[ 2.508450] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10667 14:51:55.781959 <6>[ 2.518610] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10668 14:51:55.792199 <6>[ 2.530204] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10669 14:51:55.798939 <6>[ 2.539898] Trying to probe devices needed for running init ...
10670 14:51:55.814119 <6>[ 2.552889] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 14:51:55.841630 <6>[ 2.583660] hub 2-1:1.0: USB hub found
10672 14:51:55.844491 <6>[ 2.588083] hub 2-1:1.0: 3 ports detected
10673 14:51:55.853002 <6>[ 2.594760] hub 2-1:1.0: USB hub found
10674 14:51:55.855531 <6>[ 2.599253] hub 2-1:1.0: 3 ports detected
10675 14:51:55.965950 <6>[ 2.704886] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10676 14:51:56.120381 <6>[ 2.862766] hub 1-1:1.0: USB hub found
10677 14:51:56.123915 <6>[ 2.867279] hub 1-1:1.0: 4 ports detected
10678 14:51:56.134218 <6>[ 2.876202] hub 1-1:1.0: USB hub found
10679 14:51:56.137412 <6>[ 2.880747] hub 1-1:1.0: 4 ports detected
10680 14:51:56.206051 <6>[ 2.944940] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10681 14:51:56.314535 <6>[ 3.053274] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10682 14:51:56.346410 <4>[ 3.085092] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10683 14:51:56.355976 <4>[ 3.094175] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10684 14:51:56.395978 <6>[ 3.138009] r8152 2-1.3:1.0 eth0: v1.12.13
10685 14:51:56.465808 <6>[ 3.204909] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10686 14:51:56.598747 <6>[ 3.340914] hub 1-1.4:1.0: USB hub found
10687 14:51:56.602030 <6>[ 3.345593] hub 1-1.4:1.0: 2 ports detected
10688 14:51:56.611521 <6>[ 3.353715] hub 1-1.4:1.0: USB hub found
10689 14:51:56.614958 <6>[ 3.358217] hub 1-1.4:1.0: 2 ports detected
10690 14:51:56.913589 <6>[ 3.652879] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 14:51:57.105419 <6>[ 3.844697] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 14:51:58.143873 <6>[ 4.886505] r8152 2-1.3:1.0 eth0: carrier on
10693 14:51:58.186423 <5>[ 4.912685] Sending DHCP requests ., OK
10694 14:51:58.192778 <6>[ 4.932907] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10695 14:51:58.196497 <6>[ 4.941195] IP-Config: Complete:
10696 14:51:58.209750 <6>[ 4.944692] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10697 14:51:58.216582 <6>[ 4.955430] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10698 14:51:58.223044 <6>[ 4.964049] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10699 14:51:58.229561 <6>[ 4.964058] nameserver0=192.168.201.1
10700 14:51:58.232938 <6>[ 4.976199] clk: Disabling unused clocks
10701 14:51:58.236080 <6>[ 4.981585] ALSA device list:
10702 14:51:58.239261 <6>[ 4.984876] No soundcards found.
10703 14:51:58.249975 <6>[ 4.992396] Freeing unused kernel memory: 8512K
10704 14:51:58.252955 <6>[ 4.997421] Run /init as init process
10705 14:51:58.263168 Loading, please wait...
10706 14:51:58.290654 Starting systemd-udevd version 252.22-1~deb12u1
10707 14:51:58.546863 <6>[ 5.285533] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10708 14:51:58.556348 <6>[ 5.293902] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10709 14:51:58.563051 <6>[ 5.302808] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10710 14:51:58.581107 <6>[ 5.320130] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10711 14:51:58.603705 <3>[ 5.343064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 14:51:58.607255 <6>[ 5.344747] remoteproc remoteproc0: scp is available
10713 14:51:58.617132 <4>[ 5.345096] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10714 14:51:58.623649 <3>[ 5.351184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 14:51:58.630591 <6>[ 5.356473] remoteproc remoteproc0: powering up scp
10716 14:51:58.637061 <3>[ 5.363694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 14:51:58.643968 <4>[ 5.368804] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10718 14:51:58.653631 <6>[ 5.371853] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10719 14:51:58.660400 <3>[ 5.377142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 14:51:58.667414 <6>[ 5.385029] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10721 14:51:58.673323 <3>[ 5.392317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 14:51:58.684068 <6>[ 5.392317] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10723 14:51:58.687108 <6>[ 5.393380] mc: Linux media interface: v0.10
10724 14:51:58.697288 <4>[ 5.418350] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10725 14:51:58.701080 <4>[ 5.418350] Fallback method does not support PEC.
10726 14:51:58.708017 <6>[ 5.419687] videodev: Linux video capture interface: v2.00
10727 14:51:58.714499 <3>[ 5.422576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 14:51:58.721841 <3>[ 5.422595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 14:51:58.731780 <3>[ 5.422602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 14:51:58.738286 <3>[ 5.423708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 14:51:58.745024 <6>[ 5.430070] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10732 14:51:58.751443 <6>[ 5.430080] pci_bus 0000:00: root bus resource [bus 00-ff]
10733 14:51:58.758402 <6>[ 5.430087] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10734 14:51:58.767916 <6>[ 5.430093] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10735 14:51:58.774652 <6>[ 5.430138] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10736 14:51:58.781639 <6>[ 5.430161] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10737 14:51:58.787974 <6>[ 5.430240] pci 0000:00:00.0: supports D1 D2
10738 14:51:58.795018 <6>[ 5.430243] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10739 14:51:58.800894 <6>[ 5.432076] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10740 14:51:58.811284 <3>[ 5.435231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 14:51:58.817679 <3>[ 5.447544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10742 14:51:58.824498 <6>[ 5.449091] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10743 14:51:58.834610 <3>[ 5.454578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 14:51:58.840877 <3>[ 5.454581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 14:51:58.850676 <3>[ 5.454633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 14:51:58.857343 <6>[ 5.462707] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10747 14:51:58.867543 <3>[ 5.468158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10748 14:51:58.874485 <3>[ 5.470745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 14:51:58.884019 <6>[ 5.473006] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10750 14:51:58.894348 <6>[ 5.473460] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10751 14:51:58.900547 <6>[ 5.478918] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10752 14:51:58.910128 <6>[ 5.485246] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10753 14:51:58.917109 <3>[ 5.486951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 14:51:58.927226 <6>[ 5.494737] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10755 14:51:58.933521 <3>[ 5.499551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 14:51:58.936848 <6>[ 5.506956] pci 0000:01:00.0: supports D1 D2
10757 14:51:58.946894 <3>[ 5.516601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 14:51:58.953745 <6>[ 5.522856] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10759 14:51:58.956515 <6>[ 5.523612] Bluetooth: Core ver 2.22
10760 14:51:58.963206 <6>[ 5.523735] NET: Registered PF_BLUETOOTH protocol family
10761 14:51:58.970066 <6>[ 5.523738] Bluetooth: HCI device and connection manager initialized
10762 14:51:58.973290 <6>[ 5.523766] Bluetooth: HCI socket layer initialized
10763 14:51:58.980056 <6>[ 5.523773] Bluetooth: L2CAP socket layer initialized
10764 14:51:58.983153 <6>[ 5.523786] Bluetooth: SCO socket layer initialized
10765 14:51:58.993572 <3>[ 5.530360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 14:51:58.999786 <6>[ 5.530393] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10767 14:51:59.009746 <6>[ 5.530396] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10768 14:51:59.016363 <6>[ 5.530405] remoteproc remoteproc0: remote processor scp is now up
10769 14:51:59.023112 <6>[ 5.548711] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10770 14:51:59.029375 <6>[ 5.551517] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10771 14:51:59.036318 <6>[ 5.558066] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10772 14:51:59.046441 <6>[ 5.558272] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10773 14:51:59.053018 <6>[ 5.558277] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10774 14:51:59.059094 <6>[ 5.558303] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10775 14:51:59.069448 <6>[ 5.558315] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10776 14:51:59.076132 <6>[ 5.558328] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10777 14:51:59.082834 <6>[ 5.558340] pci 0000:00:00.0: PCI bridge to [bus 01]
10778 14:51:59.089025 <6>[ 5.558345] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10779 14:51:59.095577 <6>[ 5.558478] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10780 14:51:59.102307 <6>[ 5.559000] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10781 14:51:59.108869 <6>[ 5.559225] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10782 14:51:59.122501 <6>[ 5.569420] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10783 14:51:59.129172 <5>[ 5.576378] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10784 14:51:59.135790 <6>[ 5.577154] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10785 14:51:59.143544 <6>[ 5.581906] usbcore: registered new interface driver uvcvideo
10786 14:51:59.148998 <6>[ 5.582291] usbcore: registered new interface driver btusb
10787 14:51:59.155361 <6>[ 5.582516] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10788 14:51:59.165389 <4>[ 5.583222] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10789 14:51:59.171808 <3>[ 5.583238] Bluetooth: hci0: Failed to load firmware file (-2)
10790 14:51:59.178770 <3>[ 5.583244] Bluetooth: hci0: Failed to set up firmware (-2)
10791 14:51:59.188791 <4>[ 5.583249] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10792 14:51:59.194862 <5>[ 5.602907] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10793 14:51:59.204870 <5>[ 5.943707] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10794 14:51:59.214963 <4>[ 5.952264] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10795 14:51:59.217933 <6>[ 5.961150] cfg80211: failed to load regulatory.db
10796 14:51:59.259041 <6>[ 5.998138] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10797 14:51:59.265425 <6>[ 6.005637] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10798 14:51:59.289971 <6>[ 6.032353] mt7921e 0000:01:00.0: ASIC revision: 79610010
10799 14:51:59.393607 <6>[ 6.132463] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10800 14:51:59.396697 <6>[ 6.132463]
10801 14:51:59.400008 Begin: Loading essential drivers ... done.
10802 14:51:59.403095 Begin: Running /scripts/init-premount ... done.
10803 14:51:59.409640 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10804 14:51:59.419966 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10805 14:51:59.422868 Device /sys/class/net/eth0 found
10806 14:51:59.422973 done.
10807 14:51:59.438277 Begin: Waiting up to 180 secs for any network device to become available ... done.
10808 14:51:59.494353 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10809 14:51:59.501282 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10810 14:51:59.507405 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10811 14:51:59.514335 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10812 14:51:59.520949 host : mt8192-asurada-spherion-r0-cbg-0
10813 14:51:59.527923 domain : lava-rack
10814 14:51:59.530997 rootserver: 192.168.201.1 rootpath:
10815 14:51:59.531074 filename :
10816 14:51:59.663242 <6>[ 6.402454] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10817 14:51:59.701529 done.
10818 14:51:59.708115 Begin: Running /scripts/nfs-bottom ... done.
10819 14:51:59.723135 Begin: Running /scripts/init-bottom ... done.
10820 14:52:01.019781 <6>[ 7.762436] NET: Registered PF_INET6 protocol family
10821 14:52:01.027435 <6>[ 7.770212] Segment Routing with IPv6
10822 14:52:01.030465 <6>[ 7.774218] In-situ OAM (IOAM) with IPv6
10823 14:52:01.195765 <30>[ 7.911946] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10824 14:52:01.201945 <30>[ 7.945121] systemd[1]: Detected architecture arm64.
10825 14:52:01.209469
10826 14:52:01.212450 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10827 14:52:01.212552
10828 14:52:01.234475 <30>[ 7.977363] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10829 14:52:02.188271 <30>[ 8.927822] systemd[1]: Queued start job for default target graphical.target.
10830 14:52:02.235012 <30>[ 8.974053] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10831 14:52:02.241109 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10832 14:52:02.262920 <30>[ 9.002776] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10833 14:52:02.273243 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10834 14:52:02.290898 <30>[ 9.030732] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10835 14:52:02.301414 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10836 14:52:02.318527 <30>[ 9.058364] systemd[1]: Created slice user.slice - User and Session Slice.
10837 14:52:02.325254 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10838 14:52:02.349589 <30>[ 9.085755] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10839 14:52:02.359187 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10840 14:52:02.377006 <30>[ 9.113153] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10841 14:52:02.383233 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10842 14:52:02.411303 <30>[ 9.141094] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10843 14:52:02.421479 <30>[ 9.160916] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10844 14:52:02.427677 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10845 14:52:02.446114 <30>[ 9.185312] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10846 14:52:02.452263 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10847 14:52:02.473312 <30>[ 9.212958] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10848 14:52:02.483310 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10849 14:52:02.498042 <30>[ 9.240990] systemd[1]: Reached target paths.target - Path Units.
10850 14:52:02.507779 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10851 14:52:02.525875 <30>[ 9.265339] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10852 14:52:02.532082 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10853 14:52:02.546075 <30>[ 9.288876] systemd[1]: Reached target slices.target - Slice Units.
10854 14:52:02.555840 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10855 14:52:02.570082 <30>[ 9.312924] systemd[1]: Reached target swap.target - Swaps.
10856 14:52:02.576495 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10857 14:52:02.597893 <30>[ 9.337392] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10858 14:52:02.607817 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10859 14:52:02.626253 <30>[ 9.365795] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10860 14:52:02.636187 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10861 14:52:02.656139 <30>[ 9.395797] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10862 14:52:02.666196 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10863 14:52:02.682626 <30>[ 9.422198] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10864 14:52:02.692650 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10865 14:52:02.710302 <30>[ 9.449697] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10866 14:52:02.716921 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10867 14:52:02.734609 <30>[ 9.474171] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10868 14:52:02.744400 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10869 14:52:02.764316 <30>[ 9.503513] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10870 14:52:02.773425 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10871 14:52:02.789971 <30>[ 9.529359] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10872 14:52:02.799967 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10873 14:52:02.857515 <30>[ 9.597061] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10874 14:52:02.864185 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10875 14:52:02.886854 <30>[ 9.626217] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10876 14:52:02.893278 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10877 14:52:02.918957 <30>[ 9.658551] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10878 14:52:02.925520 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10879 14:52:02.952439 <30>[ 9.685464] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10880 14:52:02.990202 <30>[ 9.729812] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10881 14:52:03.000047 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10882 14:52:03.027509 <30>[ 9.766743] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10883 14:52:03.033777 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10884 14:52:03.058910 <30>[ 9.798782] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10885 14:52:03.065422 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10886 14:52:03.095698 <30>[ 9.835149] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10887 14:52:03.101983 <6>[ 9.836454] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10888 14:52:03.112079 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10889 14:52:03.139090 <30>[ 9.878699] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10890 14:52:03.149064 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10891 14:52:03.198099 <30>[ 9.937734] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10892 14:52:03.204742 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10893 14:52:03.231053 <30>[ 9.970986] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10894 14:52:03.237564 Startin<6>[ 9.980028] fuse: init (API version 7.37)
10895 14:52:03.244545 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10896 14:52:03.290240 <30>[ 10.029736] systemd[1]: Starting systemd-journald.service - Journal Service...
10897 14:52:03.297046 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10898 14:52:03.329465 <30>[ 10.068804] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10899 14:52:03.335667 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10900 14:52:03.361411 <30>[ 10.097339] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10901 14:52:03.367368 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10902 14:52:03.395556 <30>[ 10.135189] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10903 14:52:03.405311 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10904 14:52:03.442926 <3>[ 10.182468] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 14:52:03.466859 <30>[ 10.205526] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10906 14:52:03.476699 Startin<3>[ 10.214565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 14:52:03.483051 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10908 14:52:03.506344 <30>[ 10.246017] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10909 14:52:03.513244 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10910 14:52:03.528360 <3>[ 10.267525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 14:52:03.538602 <30>[ 10.277226] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10912 14:52:03.544850 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10913 14:52:03.560962 <3>[ 10.300704] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 14:52:03.571191 <30>[ 10.310465] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10915 14:52:03.577644 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10916 14:52:03.592199 <3>[ 10.331893] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 14:52:03.606623 <30>[ 10.346402] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10918 14:52:03.624212 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static D<3>[ 10.362451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 14:52:03.624367 evice Nodes.
10920 14:52:03.642658 <30>[ 10.382427] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10921 14:52:03.649883 <30>[ 10.390713] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10922 14:52:03.659945 <3>[ 10.396811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 14:52:03.669651 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10924 14:52:03.684168 <30>[ 10.426668] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10925 14:52:03.694288 <3>[ 10.432352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 14:52:03.704233 <30>[ 10.434948] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10927 14:52:03.710525 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10928 14:52:03.726647 <3>[ 10.466639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 14:52:03.738001 <30>[ 10.477928] systemd[1]: modprobe@drm.service: Deactivated successfully.
10930 14:52:03.745081 <30>[ 10.485896] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10931 14:52:03.752447 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10932 14:52:03.762203 <3>[ 10.500868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 14:52:03.773118 <30>[ 10.512918] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10934 14:52:03.783587 <30>[ 10.521975] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10935 14:52:03.797367 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 10.535192] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 14:52:03.800796 fi_psto…m - Load Kernel Module efi_pstore.
10937 14:52:03.819697 <30>[ 10.559099] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10938 14:52:03.826832 <30>[ 10.567249] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10939 14:52:03.837481 <3>[ 10.572531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 14:52:03.843641 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10941 14:52:03.860295 <30>[ 10.603047] systemd[1]: modprobe@loop.service: Deactivated successfully.
10942 14:52:03.871457 <30>[ 10.611115] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10943 14:52:03.881436 <3>[ 10.611579] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 14:52:03.887681 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10945 14:52:03.907818 <30>[ 10.646548] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10946 14:52:03.921101 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Ker<3>[ 10.660623] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 14:52:03.931278 <3>[ 10.661482] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10948 14:52:03.948153 <4>[ 10.678984] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10949 14:52:03.954830 <3>[ 10.693760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 14:52:03.964705 <3>[ 10.694613] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10951 14:52:03.964820 nel Modules.
10952 14:52:03.988600 <30>[ 10.724832] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10953 14:52:03.995016 <3>[ 10.727514] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 14:52:04.005343 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10955 14:52:04.023588 <30>[ 10.762722] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10956 14:52:04.033698 <3>[ 10.768856] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 14:52:04.040543 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10958 14:52:04.058433 <30>[ 10.798004] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10959 14:52:04.068561 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10960 14:52:04.087176 <30>[ 10.826413] systemd[1]: Reached target network-pre.target - Preparation for Network.
10961 14:52:04.093674 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10962 14:52:04.157986 <30>[ 10.897327] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10963 14:52:04.163934 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10964 14:52:04.189593 <30>[ 10.929341] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10965 14:52:04.199256 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10966 14:52:04.220384 <30>[ 10.957208] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10967 14:52:04.238214 <30>[ 10.970866] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10968 14:52:04.252100 <30>[ 10.992131] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10969 14:52:04.258788 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10970 14:52:04.283150 <30>[ 11.019912] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10971 14:52:04.334237 <30>[ 11.073851] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10972 14:52:04.340320 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10973 14:52:04.370094 <30>[ 11.109804] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10974 14:52:04.376591 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10975 14:52:04.408618 <30>[ 11.148167] systemd[1]: Started systemd-journald.service - Journal Service.
10976 14:52:04.415176 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10977 14:52:04.438374 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10978 14:52:04.461883 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10979 14:52:04.482788 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10980 14:52:04.502803 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10981 14:52:04.526545 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10982 14:52:04.578735 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10983 14:52:04.600795 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10984 14:52:04.634275 <46>[ 11.373931] systemd-journald[306]: Received client request to flush runtime journal.
10985 14:52:05.736764 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10986 14:52:05.753785 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10987 14:52:05.776901 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10988 14:52:06.037932 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10989 14:52:06.062119 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10990 14:52:06.092843 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10991 14:52:06.225400 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10992 14:52:06.288376 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10993 14:52:06.366576 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10994 14:52:06.645718 <6>[ 13.389114] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10995 14:52:06.680322 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10996 14:52:06.733461 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10997 14:52:06.797239 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10998 14:52:06.873040 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10999 14:52:06.894342 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11000 14:52:06.914801 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11001 14:52:06.966346 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11002 14:52:06.989187 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11003 14:52:07.055041 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11004 14:52:07.079348 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11005 14:52:07.108265 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11006 14:52:07.141632 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11007 14:52:07.173355 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11008 14:52:07.230660 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11009 14:52:07.252147 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11010 14:52:07.269034 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11011 14:52:07.285417 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11012 14:52:07.306936 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11013 14:52:07.327702 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11014 14:52:07.345324 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11015 14:52:07.368247 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11016 14:52:07.388131 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11017 14:52:07.405588 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11018 14:52:07.423267 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11019 14:52:07.441095 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11020 14:52:07.458360 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11021 14:52:07.503416 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11022 14:52:07.542495 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11023 14:52:07.648288 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11024 14:52:07.678380 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11025 14:52:07.786184 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11026 14:52:07.858450 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11027 14:52:07.885303 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11028 14:52:07.902469 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11029 14:52:07.919516 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11030 14:52:07.963527 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11031 14:52:07.982560 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11032 14:52:08.003251 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11033 14:52:08.022151 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11034 14:52:08.086875 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11035 14:52:08.124246 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11036 14:52:08.206311
11037 14:52:08.209542 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11038 14:52:08.209634
11039 14:52:08.212686 debian-bookworm-arm64 login: root (automatic login)
11040 14:52:08.212760
11041 14:52:08.482293 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11042 14:52:08.482430
11043 14:52:08.489135 The programs included with the Debian GNU/Linux system are free software;
11044 14:52:08.495812 the exact distribution terms for each program are described in the
11045 14:52:08.499093 individual files in /usr/share/doc/*/copyright.
11046 14:52:08.499170
11047 14:52:08.505594 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11048 14:52:08.509181 permitted by applicable law.
11049 14:52:09.468868 Matched prompt #10: / #
11051 14:52:09.469204 Setting prompt string to ['/ #']
11052 14:52:09.469313 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11054 14:52:09.469565 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11055 14:52:09.469699 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
11056 14:52:09.469770 Setting prompt string to ['/ #']
11057 14:52:09.469879 Forcing a shell prompt, looking for ['/ #']
11059 14:52:09.520115 / #
11060 14:52:09.520265 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11061 14:52:09.520378 Waiting using forced prompt support (timeout 00:02:30)
11062 14:52:09.524923
11063 14:52:09.525219 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11064 14:52:09.525312 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
11066 14:52:09.625667 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba'
11067 14:52:09.630898 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167012/extract-nfsrootfs-1qs7mtba'
11069 14:52:09.731434 / # export NFS_SERVER_IP='192.168.201.1'
11070 14:52:09.736660 export NFS_SERVER_IP='192.168.201.1'
11071 14:52:09.736953 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11072 14:52:09.737057 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
11073 14:52:09.737149 end: 2 depthcharge-action (duration 00:01:16) [common]
11074 14:52:09.737240 start: 3 lava-test-retry (timeout 00:08:04) [common]
11075 14:52:09.737326 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
11076 14:52:09.737404 Using namespace: common
11078 14:52:09.837734 / # #
11079 14:52:09.837872 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11080 14:52:09.842954 #
11081 14:52:09.843223 Using /lava-14167012
11083 14:52:09.943527 / # export SHELL=/bin/bash
11084 14:52:09.948739 export SHELL=/bin/bash
11086 14:52:10.049261 / # . /lava-14167012/environment
11087 14:52:10.054711 . /lava-14167012/environment
11089 14:52:10.159972 / # /lava-14167012/bin/lava-test-runner /lava-14167012/0
11090 14:52:10.160108 Test shell timeout: 10s (minimum of the action and connection timeout)
11091 14:52:10.165137 /lava-14167012/bin/lava-test-runner /lava-14167012/0
11092 14:52:10.384730 + export TESTRUN_ID=0_timesync-off
11093 14:52:10.387608 + TESTRUN_ID=0_timesync-off
11094 14:52:10.390823 + cd /lava-14167012/0/tests/0_timesync-off
11095 14:52:10.393920 ++ cat uuid
11096 14:52:10.397148 + UUID=14167012_1.6.2.3.1
11097 14:52:10.397226 + set +x
11098 14:52:10.404234 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14167012_1.6.2.3.1>
11099 14:52:10.404548 Received signal: <STARTRUN> 0_timesync-off 14167012_1.6.2.3.1
11100 14:52:10.404628 Starting test lava.0_timesync-off (14167012_1.6.2.3.1)
11101 14:52:10.404716 Skipping test definition patterns.
11102 14:52:10.407282 + systemctl stop systemd-timesyncd
11103 14:52:10.479499 + set +x
11104 14:52:10.483338 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14167012_1.6.2.3.1>
11105 14:52:10.483594 Received signal: <ENDRUN> 0_timesync-off 14167012_1.6.2.3.1
11106 14:52:10.483678 Ending use of test pattern.
11107 14:52:10.483740 Ending test lava.0_timesync-off (14167012_1.6.2.3.1), duration 0.08
11109 14:52:10.531384 + export TESTRUN_ID=1_kselftest-tpm2
11110 14:52:10.534696 + TESTRUN_ID=1_kselftest-tpm2
11111 14:52:10.541040 + cd /lava-14167012/0/tests/1_kselftest-tpm2
11112 14:52:10.541125 ++ cat uuid
11113 14:52:10.544023 + UUID=14167012_1.6.2.3.5
11114 14:52:10.544106 + set +x
11115 14:52:10.547345 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14167012_1.6.2.3.5>
11116 14:52:10.547600 Received signal: <STARTRUN> 1_kselftest-tpm2 14167012_1.6.2.3.5
11117 14:52:10.547674 Starting test lava.1_kselftest-tpm2 (14167012_1.6.2.3.5)
11118 14:52:10.547753 Skipping test definition patterns.
11119 14:52:10.551321 + cd ./automated/linux/kselftest/
11120 14:52:10.577262 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11121 14:52:10.599529 INFO: install_deps skipped
11122 14:52:11.085722 --2024-06-04 14:47:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11123 14:52:11.097034 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11124 14:52:11.221811 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11125 14:52:11.346217 HTTP request sent, awaiting response... 200 OK
11126 14:52:11.349345 Length: 1647736 (1.6M) [application/octet-stream]
11127 14:52:11.352527 Saving to: 'kselftest_armhf.tar.gz'
11128 14:52:11.352610
11129 14:52:11.352730
11130 14:52:11.594821 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11131 14:52:11.843477 kselftest_armhf.tar 2%[ ] 47.81K 197KB/s
11132 14:52:12.264758 kselftest_armhf.tar 13%[=> ] 217.50K 446KB/s
11133 14:52:12.270977 kselftest_armhf.tar 51%[=========> ] 820.82K 911KB/s
11134 14:52:12.278027 kselftest_armhf.tar 100%[===================>] 1.57M 1.73MB/s in 0.9s
11135 14:52:12.278116
11136 14:52:12.423417 2024-06-04 14:47:30 (1.73 MB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736]
11137 14:52:12.423615
11138 14:52:16.237252 skiplist:
11139 14:52:16.240624 ========================================
11140 14:52:16.243653 ========================================
11141 14:52:16.283442 tpm2:test_smoke.sh
11142 14:52:16.287282 tpm2:test_space.sh
11143 14:52:16.302116 ============== Tests to run ===============
11144 14:52:16.302233 tpm2:test_smoke.sh
11145 14:52:16.305828 tpm2:test_space.sh
11146 14:52:16.308838 ===========End Tests to run ===============
11147 14:52:16.308923 shardfile-tpm2 pass
11148 14:52:16.405258 <12>[ 23.149698] kselftest: Running tests in tpm2
11149 14:52:16.413672 TAP version 13
11150 14:52:16.426678 1..2
11151 14:52:16.451220 # selftests: tpm2: test_smoke.sh
11152 14:52:18.221805 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11153 14:52:18.228230 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11154 14:52:18.235441 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11155 14:52:18.238636 # Traceback (most recent call last):
11156 14:52:18.248310 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11157 14:52:18.248473 # if self.tpm:
11158 14:52:18.251706 # ^^^^^^^^
11159 14:52:18.255529 # AttributeError: 'Client' object has no attribute 'tpm'
11160 14:52:18.261656 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11161 14:52:18.268424 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11162 14:52:18.272001 # Traceback (most recent call last):
11163 14:52:18.281539 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11164 14:52:18.281692 # if self.tpm:
11165 14:52:18.285200 # ^^^^^^^^
11166 14:52:18.288748 # AttributeError: 'Client' object has no attribute 'tpm'
11167 14:52:18.295185 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11168 14:52:18.301663 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11169 14:52:18.305093 # Traceback (most recent call last):
11170 14:52:18.315520 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11171 14:52:18.318575 # if self.tpm:
11172 14:52:18.318670 # ^^^^^^^^
11173 14:52:18.325277 # AttributeError: 'Client' object has no attribute 'tpm'
11174 14:52:18.332061 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11175 14:52:18.338383 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11176 14:52:18.341955 # Traceback (most recent call last):
11177 14:52:18.351673 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11178 14:52:18.351825 # if self.tpm:
11179 14:52:18.355306 # ^^^^^^^^
11180 14:52:18.358398 # AttributeError: 'Client' object has no attribute 'tpm'
11181 14:52:18.365244 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11182 14:52:18.371832 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11183 14:52:18.375495 # Traceback (most recent call last):
11184 14:52:18.385503 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11185 14:52:18.388834 # if self.tpm:
11186 14:52:18.388944 # ^^^^^^^^
11187 14:52:18.395418 # AttributeError: 'Client' object has no attribute 'tpm'
11188 14:52:18.401776 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11189 14:52:18.404993 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11190 14:52:18.408743 # Traceback (most recent call last):
11191 14:52:18.418484 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11192 14:52:18.421641 # if self.tpm:
11193 14:52:18.421740 # ^^^^^^^^
11194 14:52:18.428540 # AttributeError: 'Client' object has no attribute 'tpm'
11195 14:52:18.435193 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11196 14:52:18.441661 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11197 14:52:18.445085 # Traceback (most recent call last):
11198 14:52:18.454802 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11199 14:52:18.454925 # if self.tpm:
11200 14:52:18.458634 # ^^^^^^^^
11201 14:52:18.465023 # AttributeError: 'Client' object has no attribute 'tpm'
11202 14:52:18.471634 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11203 14:52:18.478452 # Exception ignored in: <function Client.__del__ at 0xffffabddccc0>
11204 14:52:18.487007 # Traceback (most recent call last):
11205 14:52:18.493347 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11206 14:52:18.496328 # if self.tpm:
11207 14:52:18.496456 # ^^^^^^^^
11208 14:52:18.499474 # AttributeError: 'Client' object has no attribute 'tpm'
11209 14:52:18.499572 #
11210 14:52:18.505771 # ======================================================================
11211 14:52:18.512646 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11212 14:52:18.519209 # ----------------------------------------------------------------------
11213 14:52:18.523130 # Traceback (most recent call last):
11214 14:52:18.532288 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11215 14:52:18.539237 # self.root_key = self.client.create_root_key()
11216 14:52:18.542333 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11217 14:52:18.553033 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11218 14:52:18.559103 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11219 14:52:18.562590 # ^^^^^^^^^^^^^^^^^^
11220 14:52:18.572865 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11221 14:52:18.576099 # raise ProtocolError(cc, rc)
11222 14:52:18.583226 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11223 14:52:18.583336 #
11224 14:52:18.589674 # ======================================================================
11225 14:52:18.596004 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11226 14:52:18.602802 # ----------------------------------------------------------------------
11227 14:52:18.606111 # Traceback (most recent call last):
11228 14:52:18.615738 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11229 14:52:18.619500 # self.client = tpm2.Client()
11230 14:52:18.622870 # ^^^^^^^^^^^^^
11231 14:52:18.632902 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11232 14:52:18.636055 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11233 14:52:18.642804 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11234 14:52:18.645970 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11235 14:52:18.646066 #
11236 14:52:18.652749 # ======================================================================
11237 14:52:18.659628 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11238 14:52:18.666088 # ----------------------------------------------------------------------
11239 14:52:18.669300 # Traceback (most recent call last):
11240 14:52:18.679224 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11241 14:52:18.682514 # self.client = tpm2.Client()
11242 14:52:18.686247 # ^^^^^^^^^^^^^
11243 14:52:18.695737 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11244 14:52:18.699729 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11245 14:52:18.705901 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11246 14:52:18.709024 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11247 14:52:18.709122 #
11248 14:52:18.715625 # ======================================================================
11249 14:52:18.722590 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11250 14:52:18.729091 # ----------------------------------------------------------------------
11251 14:52:18.732742 # Traceback (most recent call last):
11252 14:52:18.742928 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11253 14:52:18.746077 # self.client = tpm2.Client()
11254 14:52:18.749994 # ^^^^^^^^^^^^^
11255 14:52:18.760213 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11256 14:52:18.763768 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11257 14:52:18.772024 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11258 14:52:18.775067 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11259 14:52:18.775164 #
11260 14:52:18.782438 # ======================================================================
11261 14:52:18.789423 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11262 14:52:18.797866 # ----------------------------------------------------------------------
11263 14:52:18.798027 # Traceback (most recent call last):
11264 14:52:18.808573 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11265 14:52:18.814155 # self.client = tpm2.Client()
11266 14:52:18.814265 # ^^^^^^^^^^^^^
11267 14:52:18.824457 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11268 14:52:18.831533 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11269 14:52:18.834610 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11270 14:52:18.841267 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11271 14:52:18.841371 #
11272 14:52:18.848132 # ======================================================================
11273 14:52:18.851125 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11274 14:52:18.857645 # ----------------------------------------------------------------------
11275 14:52:18.861574 # Traceback (most recent call last):
11276 14:52:18.871014 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11277 14:52:18.874875 # self.client = tpm2.Client()
11278 14:52:18.878271 # ^^^^^^^^^^^^^
11279 14:52:18.888273 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11280 14:52:18.894391 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11281 14:52:18.897871 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11282 14:52:18.904659 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11283 14:52:18.904784 #
11284 14:52:18.911409 # ======================================================================
11285 14:52:18.917697 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11286 14:52:18.920848 # ----------------------------------------------------------------------
11287 14:52:18.924714 # Traceback (most recent call last):
11288 14:52:18.937971 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11289 14:52:18.938143 # self.client = tpm2.Client()
11290 14:52:18.940990 # ^^^^^^^^^^^^^
11291 14:52:18.951101 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11292 14:52:18.957447 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11293 14:52:18.961304 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11294 14:52:18.968003 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11295 14:52:18.968137 #
11296 14:52:18.974661 # ======================================================================
11297 14:52:18.980968 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11298 14:52:18.987924 # ----------------------------------------------------------------------
11299 14:52:18.991162 # Traceback (most recent call last):
11300 14:52:19.001184 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11301 14:52:19.004795 # self.client = tpm2.Client()
11302 14:52:19.007877 # ^^^^^^^^^^^^^
11303 14:52:19.018109 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11304 14:52:19.021334 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11305 14:52:19.027949 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11306 14:52:19.031039 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11307 14:52:19.031139 #
11308 14:52:19.037898 # ======================================================================
11309 14:52:19.047950 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11310 14:52:19.055067 # ----------------------------------------------------------------------
11311 14:52:19.058066 # Traceback (most recent call last):
11312 14:52:19.068209 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11313 14:52:19.071412 # self.client = tpm2.Client()
11314 14:52:19.071540 # ^^^^^^^^^^^^^
11315 14:52:19.081670 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11316 14:52:19.088205 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11317 14:52:19.091165 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11318 14:52:19.098181 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11319 14:52:19.098313 #
11320 14:52:19.104654 # ----------------------------------------------------------------------
11321 14:52:19.107973 # Ran 9 tests in 0.047s
11322 14:52:19.108077 #
11323 14:52:19.108166 # FAILED (errors=9)
11324 14:52:19.114806 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11325 14:52:19.121197 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11326 14:52:19.121312 #
11327 14:52:19.128065 # ----------------------------------------------------------------------
11328 14:52:19.131233 # Ran 2 tests in 0.024s
11329 14:52:19.131353 #
11330 14:52:19.131449 # OK
11331 14:52:19.134744 ok 1 selftests: tpm2: test_smoke.sh
11332 14:52:19.138206 # selftests: tpm2: test_space.sh
11333 14:52:19.144472 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11334 14:52:19.150970 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11335 14:52:19.154353 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11336 14:52:19.161027 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11337 14:52:19.161152 #
11338 14:52:19.167992 # ======================================================================
11339 14:52:19.174949 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11340 14:52:19.181119 # ----------------------------------------------------------------------
11341 14:52:19.184797 # Traceback (most recent call last):
11342 14:52:19.194605 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11343 14:52:19.198404 # root1 = space1.create_root_key()
11344 14:52:19.201668 # ^^^^^^^^^^^^^^^^^^^^^^^^
11345 14:52:19.214643 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11346 14:52:19.218204 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11347 14:52:19.224716 # ^^^^^^^^^^^^^^^^^^
11348 14:52:19.234507 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11349 14:52:19.238341 # raise ProtocolError(cc, rc)
11350 14:52:19.241486 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11351 14:52:19.241573 #
11352 14:52:19.248220 # ======================================================================
11353 14:52:19.255152 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11354 14:52:19.261497 # ----------------------------------------------------------------------
11355 14:52:19.264433 # Traceback (most recent call last):
11356 14:52:19.274836 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11357 14:52:19.277701 # space1.create_root_key()
11358 14:52:19.287851 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11359 14:52:19.294984 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11360 14:52:19.297713 # ^^^^^^^^^^^^^^^^^^
11361 14:52:19.308135 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11362 14:52:19.311104 # raise ProtocolError(cc, rc)
11363 14:52:19.317970 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11364 14:52:19.318102 #
11365 14:52:19.324231 # ======================================================================
11366 14:52:19.331120 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11367 14:52:19.337991 # ----------------------------------------------------------------------
11368 14:52:19.341244 # Traceback (most recent call last):
11369 14:52:19.351125 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11370 14:52:19.354315 # root1 = space1.create_root_key()
11371 14:52:19.357949 # ^^^^^^^^^^^^^^^^^^^^^^^^
11372 14:52:19.367976 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11373 14:52:19.374595 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11374 14:52:19.378094 # ^^^^^^^^^^^^^^^^^^
11375 14:52:19.387986 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11376 14:52:19.391133 # raise ProtocolError(cc, rc)
11377 14:52:19.398023 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11378 14:52:19.398148 #
11379 14:52:19.404631 # ======================================================================
11380 14:52:19.411276 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11381 14:52:19.417744 # ----------------------------------------------------------------------
11382 14:52:19.421337 # Traceback (most recent call last):
11383 14:52:19.431322 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11384 14:52:19.434499 # root1 = space1.create_root_key()
11385 14:52:19.438258 # ^^^^^^^^^^^^^^^^^^^^^^^^
11386 14:52:19.451571 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11387 14:52:19.454471 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11388 14:52:19.461470 # ^^^^^^^^^^^^^^^^^^
11389 14:52:19.471124 # File "/lava-14167012/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11390 14:52:19.475112 # raise ProtocolError(cc, rc)
11391 14:52:19.478230 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11392 14:52:19.478337 #
11393 14:52:19.484805 # ----------------------------------------------------------------------
11394 14:52:19.488225 # Ran 4 tests in 0.087s
11395 14:52:19.488389 #
11396 14:52:19.491447 # FAILED (errors=4)
11397 14:52:19.494655 not ok 2 selftests: tpm2: test_space.sh # exit=1
11398 14:52:19.678032 tpm2_test_smoke_sh pass
11399 14:52:19.681737 tpm2_test_space_sh fail
11400 14:52:19.748080 + ../../utils/send-to-lava.sh ./output/result.txt
11401 14:52:19.807101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11402 14:52:19.807509 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11404 14:52:19.846911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11405 14:52:19.847240 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11407 14:52:19.886638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11408 14:52:19.887014 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11410 14:52:19.889831 + set +x
11411 14:52:19.892931 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14167012_1.6.2.3.5>
11412 14:52:19.893221 Received signal: <ENDRUN> 1_kselftest-tpm2 14167012_1.6.2.3.5
11413 14:52:19.893328 Ending use of test pattern.
11414 14:52:19.893429 Ending test lava.1_kselftest-tpm2 (14167012_1.6.2.3.5), duration 9.35
11416 14:52:19.896545 <LAVA_TEST_RUNNER EXIT>
11417 14:52:19.896827 ok: lava_test_shell seems to have completed
11418 14:52:19.896996 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11419 14:52:19.897139 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11420 14:52:19.897260 end: 3 lava-test-retry (duration 00:00:10) [common]
11421 14:52:19.897397 start: 4 finalize (timeout 00:07:54) [common]
11422 14:52:19.897523 start: 4.1 power-off (timeout 00:00:30) [common]
11423 14:52:19.897839 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11424 14:52:19.974960 >> Command sent successfully.
11425 14:52:19.977918 Returned 0 in 0 seconds
11426 14:52:20.078325 end: 4.1 power-off (duration 00:00:00) [common]
11428 14:52:20.078682 start: 4.2 read-feedback (timeout 00:07:54) [common]
11429 14:52:20.078953 Listened to connection for namespace 'common' for up to 1s
11430 14:52:21.079873 Finalising connection for namespace 'common'
11431 14:52:21.080050 Disconnecting from shell: Finalise
11432 14:52:21.080130 / #
11433 14:52:21.180476 end: 4.2 read-feedback (duration 00:00:01) [common]
11434 14:52:21.180682 end: 4 finalize (duration 00:00:01) [common]
11435 14:52:21.180827 Cleaning after the job
11436 14:52:21.180958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/ramdisk
11437 14:52:21.183196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/kernel
11438 14:52:21.194443 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/dtb
11439 14:52:21.194734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/nfsrootfs
11440 14:52:21.263125 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167012/tftp-deploy-q261glni/modules
11441 14:52:21.269085 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167012
11442 14:52:21.842070 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167012
11443 14:52:21.842251 Job finished correctly