Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 20
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 14:43:47.876459 lava-dispatcher, installed at version: 2024.03
2 14:43:47.876706 start: 0 validate
3 14:43:47.876840 Start time: 2024-06-04 14:43:47.876832+00:00 (UTC)
4 14:43:47.876964 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:43:47.877090 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:43:48.141567 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:43:48.141752 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:43:59.402597 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:43:59.402859 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:43:59.660714 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:59.660893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:44:00.171916 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:44:00.172097 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:44:03.183520 validate duration: 15.31
16 14:44:03.183779 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:44:03.183876 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:44:03.183964 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:44:03.184088 Not decompressing ramdisk as can be used compressed.
20 14:44:03.184175 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 14:44:03.184240 saving as /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/ramdisk/initrd.cpio.gz
22 14:44:03.184306 total size: 5628151 (5 MB)
23 14:44:03.456650 progress 0 % (0 MB)
24 14:44:03.458214 progress 5 % (0 MB)
25 14:44:03.459744 progress 10 % (0 MB)
26 14:44:03.461229 progress 15 % (0 MB)
27 14:44:03.462758 progress 20 % (1 MB)
28 14:44:03.464112 progress 25 % (1 MB)
29 14:44:03.465705 progress 30 % (1 MB)
30 14:44:03.467244 progress 35 % (1 MB)
31 14:44:03.468672 progress 40 % (2 MB)
32 14:44:03.470166 progress 45 % (2 MB)
33 14:44:03.471560 progress 50 % (2 MB)
34 14:44:03.473141 progress 55 % (2 MB)
35 14:44:03.474691 progress 60 % (3 MB)
36 14:44:03.476130 progress 65 % (3 MB)
37 14:44:03.477758 progress 70 % (3 MB)
38 14:44:03.479150 progress 75 % (4 MB)
39 14:44:03.480781 progress 80 % (4 MB)
40 14:44:03.482108 progress 85 % (4 MB)
41 14:44:03.483619 progress 90 % (4 MB)
42 14:44:03.485200 progress 95 % (5 MB)
43 14:44:03.486622 progress 100 % (5 MB)
44 14:44:03.486838 5 MB downloaded in 0.30 s (17.74 MB/s)
45 14:44:03.486980 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:44:03.487211 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:44:03.487346 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:44:03.487472 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:44:03.487600 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:44:03.487672 saving as /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/kernel/Image
52 14:44:03.487734 total size: 54682112 (52 MB)
53 14:44:03.487796 No compression specified
54 14:44:03.488909 progress 0 % (0 MB)
55 14:44:03.503087 progress 5 % (2 MB)
56 14:44:03.516873 progress 10 % (5 MB)
57 14:44:03.530737 progress 15 % (7 MB)
58 14:44:03.544273 progress 20 % (10 MB)
59 14:44:03.557993 progress 25 % (13 MB)
60 14:44:03.571504 progress 30 % (15 MB)
61 14:44:03.585720 progress 35 % (18 MB)
62 14:44:03.600282 progress 40 % (20 MB)
63 14:44:03.616181 progress 45 % (23 MB)
64 14:44:03.630828 progress 50 % (26 MB)
65 14:44:03.644540 progress 55 % (28 MB)
66 14:44:03.658366 progress 60 % (31 MB)
67 14:44:03.671901 progress 65 % (33 MB)
68 14:44:03.685691 progress 70 % (36 MB)
69 14:44:03.699406 progress 75 % (39 MB)
70 14:44:03.713224 progress 80 % (41 MB)
71 14:44:03.726827 progress 85 % (44 MB)
72 14:44:03.740405 progress 90 % (46 MB)
73 14:44:03.754029 progress 95 % (49 MB)
74 14:44:03.767303 progress 100 % (52 MB)
75 14:44:03.767542 52 MB downloaded in 0.28 s (186.38 MB/s)
76 14:44:03.767694 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:44:03.767936 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:44:03.768025 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:44:03.768110 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:44:03.768242 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:44:03.768312 saving as /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/dtb/mt8192-asurada-spherion-r0.dtb
83 14:44:03.768374 total size: 47258 (0 MB)
84 14:44:03.768436 No compression specified
85 14:44:03.769556 progress 69 % (0 MB)
86 14:44:03.769828 progress 100 % (0 MB)
87 14:44:03.769989 0 MB downloaded in 0.00 s (27.95 MB/s)
88 14:44:03.770112 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:44:03.770336 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:44:03.770421 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:44:03.770504 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:44:03.770612 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 14:44:03.770680 saving as /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/nfsrootfs/full.rootfs.tar
95 14:44:03.770740 total size: 69067788 (65 MB)
96 14:44:03.770802 Using unxz to decompress xz
97 14:44:03.774329 progress 0 % (0 MB)
98 14:44:03.966403 progress 5 % (3 MB)
99 14:44:04.168626 progress 10 % (6 MB)
100 14:44:04.371333 progress 15 % (9 MB)
101 14:44:04.534887 progress 20 % (13 MB)
102 14:44:04.714636 progress 25 % (16 MB)
103 14:44:04.916911 progress 30 % (19 MB)
104 14:44:05.034681 progress 35 % (23 MB)
105 14:44:05.131053 progress 40 % (26 MB)
106 14:44:05.331889 progress 45 % (29 MB)
107 14:44:05.541584 progress 50 % (32 MB)
108 14:44:05.749435 progress 55 % (36 MB)
109 14:44:05.969230 progress 60 % (39 MB)
110 14:44:06.161490 progress 65 % (42 MB)
111 14:44:06.360172 progress 70 % (46 MB)
112 14:44:06.555000 progress 75 % (49 MB)
113 14:44:06.770392 progress 80 % (52 MB)
114 14:44:06.948151 progress 85 % (56 MB)
115 14:44:07.140647 progress 90 % (59 MB)
116 14:44:07.344143 progress 95 % (62 MB)
117 14:44:07.546845 progress 100 % (65 MB)
118 14:44:07.552993 65 MB downloaded in 3.78 s (17.42 MB/s)
119 14:44:07.553245 end: 1.4.1 http-download (duration 00:00:04) [common]
121 14:44:07.553519 end: 1.4 download-retry (duration 00:00:04) [common]
122 14:44:07.553615 start: 1.5 download-retry (timeout 00:09:56) [common]
123 14:44:07.553706 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 14:44:07.553860 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:44:07.553936 saving as /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/modules/modules.tar
126 14:44:07.553999 total size: 8608920 (8 MB)
127 14:44:07.554065 Using unxz to decompress xz
128 14:44:07.557705 progress 0 % (0 MB)
129 14:44:07.576616 progress 5 % (0 MB)
130 14:44:07.603981 progress 10 % (0 MB)
131 14:44:07.634067 progress 15 % (1 MB)
132 14:44:07.657655 progress 20 % (1 MB)
133 14:44:07.681044 progress 25 % (2 MB)
134 14:44:07.709021 progress 30 % (2 MB)
135 14:44:07.733433 progress 35 % (2 MB)
136 14:44:07.760054 progress 40 % (3 MB)
137 14:44:07.782648 progress 45 % (3 MB)
138 14:44:07.808275 progress 50 % (4 MB)
139 14:44:07.834384 progress 55 % (4 MB)
140 14:44:07.858807 progress 60 % (4 MB)
141 14:44:07.882788 progress 65 % (5 MB)
142 14:44:07.907838 progress 70 % (5 MB)
143 14:44:07.933737 progress 75 % (6 MB)
144 14:44:07.959594 progress 80 % (6 MB)
145 14:44:07.983823 progress 85 % (7 MB)
146 14:44:08.009291 progress 90 % (7 MB)
147 14:44:08.034800 progress 95 % (7 MB)
148 14:44:08.059840 progress 100 % (8 MB)
149 14:44:08.065490 8 MB downloaded in 0.51 s (16.05 MB/s)
150 14:44:08.065742 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:44:08.066021 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:44:08.066117 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 14:44:08.066213 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 14:44:09.522882 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih
156 14:44:09.523080 end: 1.6.1 extract-nfsrootfs (duration 00:00:01) [common]
157 14:44:09.523185 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 14:44:09.523357 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l
159 14:44:09.523486 makedir: /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin
160 14:44:09.523587 makedir: /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/tests
161 14:44:09.523687 makedir: /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/results
162 14:44:09.523787 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-add-keys
163 14:44:09.523921 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-add-sources
164 14:44:09.524061 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-background-process-start
165 14:44:09.524184 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-background-process-stop
166 14:44:09.524304 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-common-functions
167 14:44:09.524424 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-echo-ipv4
168 14:44:09.524542 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-install-packages
169 14:44:09.524671 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-installed-packages
170 14:44:09.524790 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-os-build
171 14:44:09.524910 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-probe-channel
172 14:44:09.525027 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-probe-ip
173 14:44:09.525143 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-target-ip
174 14:44:09.525259 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-target-mac
175 14:44:09.525375 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-target-storage
176 14:44:09.525493 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-case
177 14:44:09.525611 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-event
178 14:44:09.525731 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-feedback
179 14:44:09.525847 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-raise
180 14:44:09.525964 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-reference
181 14:44:09.526081 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-runner
182 14:44:09.526198 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-set
183 14:44:09.526314 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-test-shell
184 14:44:09.526432 Updating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-install-packages (oe)
185 14:44:09.526575 Updating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/bin/lava-installed-packages (oe)
186 14:44:09.526698 Creating /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/environment
187 14:44:09.526791 LAVA metadata
188 14:44:09.526857 - LAVA_JOB_ID=14166994
189 14:44:09.526925 - LAVA_DISPATCHER_IP=192.168.201.1
190 14:44:09.527023 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 14:44:09.527090 skipped lava-vland-overlay
192 14:44:09.527164 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 14:44:09.527242 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 14:44:09.527303 skipped lava-multinode-overlay
195 14:44:09.527375 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 14:44:09.527453 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 14:44:09.527526 Loading test definitions
198 14:44:09.527614 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 14:44:09.527685 Using /lava-14166994 at stage 0
200 14:44:09.527969 uuid=14166994_1.6.2.3.1 testdef=None
201 14:44:09.528058 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 14:44:09.528142 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 14:44:09.528621 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 14:44:09.528840 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 14:44:09.529424 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 14:44:09.529653 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 14:44:09.530217 runner path: /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/0/tests/0_lc-compliance test_uuid 14166994_1.6.2.3.1
210 14:44:09.530371 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 14:44:09.530576 Creating lava-test-runner.conf files
213 14:44:09.530640 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14166994/lava-overlay-yjdna_5l/lava-14166994/0 for stage 0
214 14:44:09.530726 - 0_lc-compliance
215 14:44:09.530820 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 14:44:09.530904 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 14:44:09.536460 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 14:44:09.536569 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 14:44:09.536655 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 14:44:09.536737 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 14:44:09.536820 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 14:44:09.695812 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 14:44:09.696187 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 14:44:09.696302 extracting modules file /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih
225 14:44:09.897013 extracting modules file /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166994/extract-overlay-ramdisk-z9cayq0o/ramdisk
226 14:44:10.111893 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 14:44:10.112060 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 14:44:10.112154 [common] Applying overlay to NFS
229 14:44:10.112224 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166994/compress-overlay-goxvg07n/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih
230 14:44:10.118503 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 14:44:10.118617 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 14:44:10.118706 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 14:44:10.118795 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 14:44:10.118874 Building ramdisk /var/lib/lava/dispatcher/tmp/14166994/extract-overlay-ramdisk-z9cayq0o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14166994/extract-overlay-ramdisk-z9cayq0o/ramdisk
235 14:44:10.449439 >> 130335 blocks
236 14:44:12.440367 rename /var/lib/lava/dispatcher/tmp/14166994/extract-overlay-ramdisk-z9cayq0o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/ramdisk/ramdisk.cpio.gz
237 14:44:12.440847 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 14:44:12.440967 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 14:44:12.441071 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 14:44:12.441173 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/kernel/Image']
241 14:44:25.759886 Returned 0 in 13 seconds
242 14:44:25.860462 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/kernel/image.itb
243 14:44:26.202655 output: FIT description: Kernel Image image with one or more FDT blobs
244 14:44:26.203022 output: Created: Tue Jun 4 15:44:26 2024
245 14:44:26.203098 output: Image 0 (kernel-1)
246 14:44:26.203163 output: Description:
247 14:44:26.203227 output: Created: Tue Jun 4 15:44:26 2024
248 14:44:26.203288 output: Type: Kernel Image
249 14:44:26.203348 output: Compression: lzma compressed
250 14:44:26.203410 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
251 14:44:26.203472 output: Architecture: AArch64
252 14:44:26.203528 output: OS: Linux
253 14:44:26.203588 output: Load Address: 0x00000000
254 14:44:26.203648 output: Entry Point: 0x00000000
255 14:44:26.203706 output: Hash algo: crc32
256 14:44:26.203765 output: Hash value: 88dcd836
257 14:44:26.203825 output: Image 1 (fdt-1)
258 14:44:26.203882 output: Description: mt8192-asurada-spherion-r0
259 14:44:26.203940 output: Created: Tue Jun 4 15:44:26 2024
260 14:44:26.203997 output: Type: Flat Device Tree
261 14:44:26.204052 output: Compression: uncompressed
262 14:44:26.204107 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 14:44:26.204162 output: Architecture: AArch64
264 14:44:26.204216 output: Hash algo: crc32
265 14:44:26.204270 output: Hash value: 0f8e4d2e
266 14:44:26.204325 output: Image 2 (ramdisk-1)
267 14:44:26.204379 output: Description: unavailable
268 14:44:26.204433 output: Created: Tue Jun 4 15:44:26 2024
269 14:44:26.204492 output: Type: RAMDisk Image
270 14:44:26.204555 output: Compression: Unknown Compression
271 14:44:26.204612 output: Data Size: 18735895 Bytes = 18296.77 KiB = 17.87 MiB
272 14:44:26.204667 output: Architecture: AArch64
273 14:44:26.204722 output: OS: Linux
274 14:44:26.204776 output: Load Address: unavailable
275 14:44:26.204830 output: Entry Point: unavailable
276 14:44:26.204884 output: Hash algo: crc32
277 14:44:26.204939 output: Hash value: dadf1870
278 14:44:26.204993 output: Default Configuration: 'conf-1'
279 14:44:26.205047 output: Configuration 0 (conf-1)
280 14:44:26.205101 output: Description: mt8192-asurada-spherion-r0
281 14:44:26.205156 output: Kernel: kernel-1
282 14:44:26.205209 output: Init Ramdisk: ramdisk-1
283 14:44:26.205263 output: FDT: fdt-1
284 14:44:26.205316 output: Loadables: kernel-1
285 14:44:26.205370 output:
286 14:44:26.205560 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 14:44:26.205656 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 14:44:26.205776 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 14:44:26.205873 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 14:44:26.205953 No LXC device requested
291 14:44:26.206032 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 14:44:26.206116 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 14:44:26.206199 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 14:44:26.206266 Checking files for TFTP limit of 4294967296 bytes.
295 14:44:26.206746 end: 1 tftp-deploy (duration 00:00:23) [common]
296 14:44:26.206848 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 14:44:26.206954 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 14:44:26.207081 substitutions:
299 14:44:26.207150 - {DTB}: 14166994/tftp-deploy-rqbtyl8_/dtb/mt8192-asurada-spherion-r0.dtb
300 14:44:26.207216 - {INITRD}: 14166994/tftp-deploy-rqbtyl8_/ramdisk/ramdisk.cpio.gz
301 14:44:26.207278 - {KERNEL}: 14166994/tftp-deploy-rqbtyl8_/kernel/Image
302 14:44:26.207338 - {LAVA_MAC}: None
303 14:44:26.207396 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih
304 14:44:26.207454 - {NFS_SERVER_IP}: 192.168.201.1
305 14:44:26.207510 - {PRESEED_CONFIG}: None
306 14:44:26.207566 - {PRESEED_LOCAL}: None
307 14:44:26.207622 - {RAMDISK}: 14166994/tftp-deploy-rqbtyl8_/ramdisk/ramdisk.cpio.gz
308 14:44:26.207677 - {ROOT_PART}: None
309 14:44:26.207732 - {ROOT}: None
310 14:44:26.207787 - {SERVER_IP}: 192.168.201.1
311 14:44:26.207842 - {TEE}: None
312 14:44:26.207896 Parsed boot commands:
313 14:44:26.207951 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 14:44:26.208125 Parsed boot commands: tftpboot 192.168.201.1 14166994/tftp-deploy-rqbtyl8_/kernel/image.itb 14166994/tftp-deploy-rqbtyl8_/kernel/cmdline
315 14:44:26.208212 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 14:44:26.208297 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 14:44:26.208390 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 14:44:26.208473 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 14:44:26.208544 Not connected, no need to disconnect.
320 14:44:26.208669 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 14:44:26.208754 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 14:44:26.208825 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 14:44:26.212023 Setting prompt string to ['lava-test: # ']
324 14:44:26.212358 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 14:44:26.212465 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 14:44:26.212592 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 14:44:26.212734 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 14:44:26.212943 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
329 14:44:39.712582 Returned 0 in 13 seconds
330 14:44:39.813317 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 14:44:39.813650 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 14:44:39.813753 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 14:44:39.813848 Setting prompt string to 'Starting depthcharge on Spherion...'
335 14:44:39.813918 Changing prompt to 'Starting depthcharge on Spherion...'
336 14:44:39.813988 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 14:44:39.814393 [Enter `^Ec?' for help]
338 14:44:39.814476
339 14:44:39.814546
340 14:44:39.814612 F0: 102B 0000
341 14:44:39.814677
342 14:44:39.814737 F3: 1001 0000 [0200]
343 14:44:39.814802
344 14:44:39.814861 F3: 1001 0000
345 14:44:39.814929
346 14:44:39.814988 F7: 102D 0000
347 14:44:39.815045
348 14:44:39.815102 F1: 0000 0000
349 14:44:39.815159
350 14:44:39.815214 V0: 0000 0000 [0001]
351 14:44:39.815271
352 14:44:39.815327 00: 0007 8000
353 14:44:39.815386
354 14:44:39.815442 01: 0000 0000
355 14:44:39.815499
356 14:44:39.815555 BP: 0C00 0209 [0000]
357 14:44:39.815610
358 14:44:39.815665 G0: 1182 0000
359 14:44:39.815721
360 14:44:39.815777 EC: 0000 0021 [4000]
361 14:44:39.815833
362 14:44:39.815889 S7: 0000 0000 [0000]
363 14:44:39.815945
364 14:44:39.816000 CC: 0000 0000 [0001]
365 14:44:39.816056
366 14:44:39.816111 T0: 0000 0040 [010F]
367 14:44:39.816167
368 14:44:39.816222 Jump to BL
369 14:44:39.816277
370 14:44:39.816332
371 14:44:39.816387
372 14:44:39.816442 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 14:44:39.816502 ARM64: Exception handlers installed.
374 14:44:39.816571 ARM64: Testing exception
375 14:44:39.816629 ARM64: Done test exception
376 14:44:39.816685 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 14:44:39.816742 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 14:44:39.816799 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 14:44:39.816856 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 14:44:39.816913 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 14:44:39.816969 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 14:44:39.817025 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 14:44:39.817081 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 14:44:39.817138 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 14:44:39.817194 WDT: Last reset was cold boot
386 14:44:39.817250 SPI1(PAD0) initialized at 2873684 Hz
387 14:44:39.817306 SPI5(PAD0) initialized at 992727 Hz
388 14:44:39.817362 VBOOT: Loading verstage.
389 14:44:39.817417 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 14:44:39.817474 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 14:44:39.817530 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 14:44:39.817586 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 14:44:39.817643 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 14:44:39.817699 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 14:44:39.817755 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
396 14:44:39.817811
397 14:44:39.817866
398 14:44:39.817922 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 14:44:39.817979 ARM64: Exception handlers installed.
400 14:44:39.818034 ARM64: Testing exception
401 14:44:39.818090 ARM64: Done test exception
402 14:44:39.818146 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 14:44:39.818202 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 14:44:39.818258 Probing TPM: . done!
405 14:44:39.818313 TPM ready after 0 ms
406 14:44:39.818368 Connected to device vid:did:rid of 1ae0:0028:00
407 14:44:39.818424 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
408 14:44:39.818481 Initialized TPM device CR50 revision 0
409 14:44:39.818537 tlcl_send_startup: Startup return code is 0
410 14:44:39.818592 TPM: setup succeeded
411 14:44:39.818648 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 14:44:39.818703 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 14:44:39.818759 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 14:44:39.818815 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 14:44:39.818870 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 14:44:39.818969 in-header: 03 07 00 00 08 00 00 00
417 14:44:39.819047 in-data: aa e4 47 04 13 02 00 00
418 14:44:39.819119 Chrome EC: UHEPI supported
419 14:44:39.819208 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 14:44:39.819270 in-header: 03 a9 00 00 08 00 00 00
421 14:44:39.819328 in-data: 84 60 60 08 00 00 00 00
422 14:44:39.819384 Phase 1
423 14:44:39.819440 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 14:44:39.819497 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 14:44:39.819554 VB2:vb2_check_recovery() Recovery was requested manually
426 14:44:39.819611 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 14:44:39.819667 Recovery requested (1009000e)
428 14:44:39.819723 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 14:44:39.819779 tlcl_extend: response is 0
430 14:44:39.819835 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 14:44:39.819892 tlcl_extend: response is 0
432 14:44:39.819949 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 14:44:39.820005 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 14:44:39.820062 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 14:44:39.820118
436 14:44:39.820174
437 14:44:39.820229 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 14:44:39.820285 ARM64: Exception handlers installed.
439 14:44:39.820341 ARM64: Testing exception
440 14:44:39.820397 ARM64: Done test exception
441 14:44:39.820452 pmic_efuse_setting: Set efuses in 11 msecs
442 14:44:39.820507 pmwrap_interface_init: Select PMIF_VLD_RDY
443 14:44:39.820590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 14:44:39.820662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 14:44:39.820915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 14:44:39.820981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 14:44:39.821039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 14:44:39.821094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 14:44:39.821151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 14:44:39.821207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 14:44:39.821263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 14:44:39.821318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 14:44:39.821375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 14:44:39.821430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 14:44:39.821486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 14:44:39.821542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 14:44:39.821598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 14:44:39.821654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 14:44:39.821709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 14:44:39.821765 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 14:44:39.821821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 14:44:39.821877 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 14:44:39.821933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 14:44:39.821988 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 14:44:39.822044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 14:44:39.822099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 14:44:39.822155 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 14:44:39.822211 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 14:44:39.822267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 14:44:39.822322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 14:44:39.822378 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 14:44:39.822434 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 14:44:39.822489 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 14:44:39.822545 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 14:44:39.822600 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 14:44:39.822656 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 14:44:39.822711 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 14:44:39.822767 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 14:44:39.822822 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 14:44:39.822878 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 14:44:39.822934 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 14:44:39.822990 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 14:44:39.823045 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 14:44:39.823141 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 14:44:39.823197 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 14:44:39.823252 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 14:44:39.823332 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 14:44:39.823392 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 14:44:39.823448 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 14:44:39.823504 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 14:44:39.823560 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 14:44:39.823616 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 14:44:39.823671 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 14:44:39.823727 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 14:44:39.823783 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 14:44:39.823839 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 14:44:39.823895 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 14:44:39.823951 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 14:44:39.824007 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 14:44:39.824063 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 14:44:39.824119 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 14:44:39.824174 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa
503 14:44:39.824231 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 14:44:39.824287 [RTC]rtc_osc_init,62: osc32con val = 0xde70
505 14:44:39.824342 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 14:44:39.824398 [RTC]rtc_get_frequency_meter,154: input=15, output=772
507 14:44:39.824453 [RTC]rtc_get_frequency_meter,154: input=23, output=955
508 14:44:39.824509 [RTC]rtc_get_frequency_meter,154: input=19, output=864
509 14:44:39.824597 [RTC]rtc_get_frequency_meter,154: input=17, output=817
510 14:44:39.824669 [RTC]rtc_get_frequency_meter,154: input=16, output=793
511 14:44:39.824724 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
512 14:44:39.824780 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
513 14:44:39.824836 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
514 14:44:39.824891 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
515 14:44:39.825153 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
516 14:44:39.825234 ADC[4]: Raw value=902876 ID=7
517 14:44:39.825291 ADC[3]: Raw value=213179 ID=1
518 14:44:39.825347 RAM Code: 0x71
519 14:44:39.825402 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
520 14:44:39.825458 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
521 14:44:39.825515 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
522 14:44:39.825572 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
523 14:44:39.825628 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
524 14:44:39.825685 in-header: 03 07 00 00 08 00 00 00
525 14:44:39.825741 in-data: aa e4 47 04 13 02 00 00
526 14:44:39.825796 Chrome EC: UHEPI supported
527 14:44:39.825852 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
528 14:44:39.825908 in-header: 03 a9 00 00 08 00 00 00
529 14:44:39.825964 in-data: 84 60 60 08 00 00 00 00
530 14:44:39.826020 MRC: failed to locate region type 0.
531 14:44:39.826075 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
532 14:44:39.826131 DRAM-K: Running full calibration
533 14:44:39.826194 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
534 14:44:39.826265 header.status = 0x0
535 14:44:39.826322 header.version = 0x6 (expected: 0x6)
536 14:44:39.826378 header.size = 0xd00 (expected: 0xd00)
537 14:44:39.826435 header.flags = 0x0
538 14:44:39.826490 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
539 14:44:39.826547 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
540 14:44:39.826604 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
541 14:44:39.826677 dram_init: ddr_geometry: 2
542 14:44:39.826748 [EMI] MDL number = 2
543 14:44:39.826803 [EMI] Get MDL freq = 0
544 14:44:39.826859 dram_init: ddr_type: 0
545 14:44:39.826914 is_discrete_lpddr4: 1
546 14:44:39.826969 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
547 14:44:39.827041
548 14:44:39.827130
549 14:44:39.827217 [Bian_co] ETT version 0.0.0.1
550 14:44:39.827287 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
551 14:44:39.827344
552 14:44:39.827399 dramc_set_vcore_voltage set vcore to 650000
553 14:44:39.827454 Read voltage for 800, 4
554 14:44:39.827510 Vio18 = 0
555 14:44:39.827565 Vcore = 650000
556 14:44:39.827620 Vdram = 0
557 14:44:39.827675 Vddq = 0
558 14:44:39.827730 Vmddr = 0
559 14:44:39.827785 dram_init: config_dvfs: 1
560 14:44:39.827839 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
561 14:44:39.827895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
562 14:44:39.827950 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
563 14:44:39.828005 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
564 14:44:39.828064 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
565 14:44:39.828120 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
566 14:44:39.828176 MEM_TYPE=3, freq_sel=18
567 14:44:39.828231 sv_algorithm_assistance_LP4_1600
568 14:44:39.828286 ============ PULL DRAM RESETB DOWN ============
569 14:44:39.828342 ========== PULL DRAM RESETB DOWN end =========
570 14:44:39.828399 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
571 14:44:39.828455 ===================================
572 14:44:39.828509 LPDDR4 DRAM CONFIGURATION
573 14:44:39.828603 ===================================
574 14:44:39.828659 EX_ROW_EN[0] = 0x0
575 14:44:39.828715 EX_ROW_EN[1] = 0x0
576 14:44:39.828770 LP4Y_EN = 0x0
577 14:44:39.828824 WORK_FSP = 0x0
578 14:44:39.828884 WL = 0x2
579 14:44:39.828939 RL = 0x2
580 14:44:39.828994 BL = 0x2
581 14:44:39.829050 RPST = 0x0
582 14:44:39.829105 RD_PRE = 0x0
583 14:44:39.829159 WR_PRE = 0x1
584 14:44:39.829214 WR_PST = 0x0
585 14:44:39.829269 DBI_WR = 0x0
586 14:44:39.829324 DBI_RD = 0x0
587 14:44:39.829378 OTF = 0x1
588 14:44:39.829434 ===================================
589 14:44:39.829490 ===================================
590 14:44:39.829545 ANA top config
591 14:44:39.829600 ===================================
592 14:44:39.829656 DLL_ASYNC_EN = 0
593 14:44:39.829711 ALL_SLAVE_EN = 1
594 14:44:39.829767 NEW_RANK_MODE = 1
595 14:44:39.829824 DLL_IDLE_MODE = 1
596 14:44:39.829880 LP45_APHY_COMB_EN = 1
597 14:44:39.829935 TX_ODT_DIS = 1
598 14:44:39.829990 NEW_8X_MODE = 1
599 14:44:39.830046 ===================================
600 14:44:39.830101 ===================================
601 14:44:39.830155 data_rate = 1600
602 14:44:39.830210 CKR = 1
603 14:44:39.830267 DQ_P2S_RATIO = 8
604 14:44:39.830344 ===================================
605 14:44:39.830402 CA_P2S_RATIO = 8
606 14:44:39.830457 DQ_CA_OPEN = 0
607 14:44:39.830513 DQ_SEMI_OPEN = 0
608 14:44:39.830567 CA_SEMI_OPEN = 0
609 14:44:39.830622 CA_FULL_RATE = 0
610 14:44:39.830677 DQ_CKDIV4_EN = 1
611 14:44:39.830732 CA_CKDIV4_EN = 1
612 14:44:39.830788 CA_PREDIV_EN = 0
613 14:44:39.830843 PH8_DLY = 0
614 14:44:39.830899 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
615 14:44:39.830954 DQ_AAMCK_DIV = 4
616 14:44:39.831010 CA_AAMCK_DIV = 4
617 14:44:39.831066 CA_ADMCK_DIV = 4
618 14:44:39.831121 DQ_TRACK_CA_EN = 0
619 14:44:39.831176 CA_PICK = 800
620 14:44:39.831231 CA_MCKIO = 800
621 14:44:39.831286 MCKIO_SEMI = 0
622 14:44:39.831342 PLL_FREQ = 3068
623 14:44:39.831397 DQ_UI_PI_RATIO = 32
624 14:44:39.831452 CA_UI_PI_RATIO = 0
625 14:44:39.831507 ===================================
626 14:44:39.831562 ===================================
627 14:44:39.831617 memory_type:LPDDR4
628 14:44:39.831673 GP_NUM : 10
629 14:44:39.831727 SRAM_EN : 1
630 14:44:39.831783 MD32_EN : 0
631 14:44:39.831838 ===================================
632 14:44:39.831894 [ANA_INIT] >>>>>>>>>>>>>>
633 14:44:39.831949 <<<<<< [CONFIGURE PHASE]: ANA_TX
634 14:44:39.832007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
635 14:44:39.832062 ===================================
636 14:44:39.832324 data_rate = 1600,PCW = 0X7600
637 14:44:39.832387 ===================================
638 14:44:39.832445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
639 14:44:39.832502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
640 14:44:39.832582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 14:44:39.832655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
642 14:44:39.832711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
643 14:44:39.832767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
644 14:44:39.832824 [ANA_INIT] flow start
645 14:44:39.832879 [ANA_INIT] PLL >>>>>>>>
646 14:44:39.832935 [ANA_INIT] PLL <<<<<<<<
647 14:44:39.832990 [ANA_INIT] MIDPI >>>>>>>>
648 14:44:39.833045 [ANA_INIT] MIDPI <<<<<<<<
649 14:44:39.833100 [ANA_INIT] DLL >>>>>>>>
650 14:44:39.833172 [ANA_INIT] flow end
651 14:44:39.833241 ============ LP4 DIFF to SE enter ============
652 14:44:39.833297 ============ LP4 DIFF to SE exit ============
653 14:44:39.833354 [ANA_INIT] <<<<<<<<<<<<<
654 14:44:39.833409 [Flow] Enable top DCM control >>>>>
655 14:44:39.833464 [Flow] Enable top DCM control <<<<<
656 14:44:39.833519 Enable DLL master slave shuffle
657 14:44:39.833575 ==============================================================
658 14:44:39.833665 Gating Mode config
659 14:44:39.833721 ==============================================================
660 14:44:39.833776 Config description:
661 14:44:39.833832 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
662 14:44:39.833888 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
663 14:44:39.833944 SELPH_MODE 0: By rank 1: By Phase
664 14:44:39.834000 ==============================================================
665 14:44:39.834056 GAT_TRACK_EN = 1
666 14:44:39.834112 RX_GATING_MODE = 2
667 14:44:39.834168 RX_GATING_TRACK_MODE = 2
668 14:44:39.834223 SELPH_MODE = 1
669 14:44:39.834278 PICG_EARLY_EN = 1
670 14:44:39.834334 VALID_LAT_VALUE = 1
671 14:44:39.834418 ==============================================================
672 14:44:39.834512 Enter into Gating configuration >>>>
673 14:44:39.834605 Exit from Gating configuration <<<<
674 14:44:39.834667 Enter into DVFS_PRE_config >>>>>
675 14:44:39.834725 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
676 14:44:39.834786 Exit from DVFS_PRE_config <<<<<
677 14:44:39.834843 Enter into PICG configuration >>>>
678 14:44:39.834899 Exit from PICG configuration <<<<
679 14:44:39.834955 [RX_INPUT] configuration >>>>>
680 14:44:39.835012 [RX_INPUT] configuration <<<<<
681 14:44:39.835068 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
682 14:44:39.835123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
683 14:44:39.835179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
684 14:44:39.835234 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
685 14:44:39.835290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
686 14:44:39.835345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
687 14:44:39.835400 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
688 14:44:39.835455 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
689 14:44:39.835510 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
690 14:44:39.835565 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
691 14:44:39.835621 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
692 14:44:39.835675 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
693 14:44:39.835730 ===================================
694 14:44:39.835786 LPDDR4 DRAM CONFIGURATION
695 14:44:39.835874 ===================================
696 14:44:39.835930 EX_ROW_EN[0] = 0x0
697 14:44:39.835986 EX_ROW_EN[1] = 0x0
698 14:44:39.836041 LP4Y_EN = 0x0
699 14:44:39.836096 WORK_FSP = 0x0
700 14:44:39.836151 WL = 0x2
701 14:44:39.836206 RL = 0x2
702 14:44:39.836261 BL = 0x2
703 14:44:39.836316 RPST = 0x0
704 14:44:39.836371 RD_PRE = 0x0
705 14:44:39.836426 WR_PRE = 0x1
706 14:44:39.836481 WR_PST = 0x0
707 14:44:39.836535 DBI_WR = 0x0
708 14:44:39.836630 DBI_RD = 0x0
709 14:44:39.836686 OTF = 0x1
710 14:44:39.836741 ===================================
711 14:44:39.836797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
712 14:44:39.836852 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
713 14:44:39.836908 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
714 14:44:39.836963 ===================================
715 14:44:39.837019 LPDDR4 DRAM CONFIGURATION
716 14:44:39.837075 ===================================
717 14:44:39.837130 EX_ROW_EN[0] = 0x10
718 14:44:39.837185 EX_ROW_EN[1] = 0x0
719 14:44:39.837240 LP4Y_EN = 0x0
720 14:44:39.837295 WORK_FSP = 0x0
721 14:44:39.837350 WL = 0x2
722 14:44:39.837405 RL = 0x2
723 14:44:39.837460 BL = 0x2
724 14:44:39.837515 RPST = 0x0
725 14:44:39.837569 RD_PRE = 0x0
726 14:44:39.837625 WR_PRE = 0x1
727 14:44:39.837680 WR_PST = 0x0
728 14:44:39.837734 DBI_WR = 0x0
729 14:44:39.837789 DBI_RD = 0x0
730 14:44:39.837844 OTF = 0x1
731 14:44:39.837899 ===================================
732 14:44:39.837955 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
733 14:44:39.838011 nWR fixed to 40
734 14:44:39.838067 [ModeRegInit_LP4] CH0 RK0
735 14:44:39.838122 [ModeRegInit_LP4] CH0 RK1
736 14:44:39.838190 [ModeRegInit_LP4] CH1 RK0
737 14:44:39.838289 [ModeRegInit_LP4] CH1 RK1
738 14:44:39.838368 match AC timing 13
739 14:44:39.838426 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
740 14:44:39.838484 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
741 14:44:39.838541 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
742 14:44:39.838598 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
743 14:44:39.838855 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
744 14:44:39.838923 [EMI DOE] emi_dcm 0
745 14:44:39.838982 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
746 14:44:39.839073 ==
747 14:44:39.839148 Dram Type= 6, Freq= 0, CH_0, rank 0
748 14:44:39.839220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
749 14:44:39.839294 ==
750 14:44:39.839352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
751 14:44:39.839424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
752 14:44:39.839481 [CA 0] Center 38 (7~69) winsize 63
753 14:44:39.839537 [CA 1] Center 38 (7~69) winsize 63
754 14:44:39.839593 [CA 2] Center 35 (5~66) winsize 62
755 14:44:39.839649 [CA 3] Center 35 (5~66) winsize 62
756 14:44:39.839705 [CA 4] Center 34 (4~65) winsize 62
757 14:44:39.839760 [CA 5] Center 33 (3~64) winsize 62
758 14:44:39.839815
759 14:44:39.839871 [CmdBusTrainingLP45] Vref(ca) range 1: 32
760 14:44:39.839926
761 14:44:39.839982 [CATrainingPosCal] consider 1 rank data
762 14:44:39.840037 u2DelayCellTimex100 = 270/100 ps
763 14:44:39.840092 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
764 14:44:39.840148 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
765 14:44:39.840204 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
766 14:44:39.840260 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
767 14:44:39.840316 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
768 14:44:39.840372 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
769 14:44:39.840427
770 14:44:39.840482 CA PerBit enable=1, Macro0, CA PI delay=33
771 14:44:39.840538
772 14:44:39.840639 [CBTSetCACLKResult] CA Dly = 33
773 14:44:39.840696 CS Dly: 5 (0~36)
774 14:44:39.840751 ==
775 14:44:39.840807 Dram Type= 6, Freq= 0, CH_0, rank 1
776 14:44:39.840871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 14:44:39.840936 ==
778 14:44:39.840992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
779 14:44:39.841049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
780 14:44:39.841106 [CA 0] Center 38 (7~69) winsize 63
781 14:44:39.841194 [CA 1] Center 38 (7~69) winsize 63
782 14:44:39.841250 [CA 2] Center 36 (6~67) winsize 62
783 14:44:39.841306 [CA 3] Center 35 (5~66) winsize 62
784 14:44:39.841361 [CA 4] Center 35 (4~66) winsize 63
785 14:44:39.841417 [CA 5] Center 34 (4~65) winsize 62
786 14:44:39.841473
787 14:44:39.841569 [CmdBusTrainingLP45] Vref(ca) range 1: 32
788 14:44:39.841657
789 14:44:39.841717 [CATrainingPosCal] consider 2 rank data
790 14:44:39.841774 u2DelayCellTimex100 = 270/100 ps
791 14:44:39.841831 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
792 14:44:39.841888 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
793 14:44:39.841944 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
794 14:44:39.841999 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
795 14:44:39.842055 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
796 14:44:39.842110 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
797 14:44:39.842166
798 14:44:39.842221 CA PerBit enable=1, Macro0, CA PI delay=34
799 14:44:39.842277
800 14:44:39.842364 [CBTSetCACLKResult] CA Dly = 34
801 14:44:39.842420 CS Dly: 6 (0~38)
802 14:44:39.842475
803 14:44:39.842530 ----->DramcWriteLeveling(PI) begin...
804 14:44:39.842587 ==
805 14:44:39.842643 Dram Type= 6, Freq= 0, CH_0, rank 0
806 14:44:39.842702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 14:44:39.842759 ==
808 14:44:39.842814 Write leveling (Byte 0): 31 => 31
809 14:44:39.842870 Write leveling (Byte 1): 30 => 30
810 14:44:39.842926 DramcWriteLeveling(PI) end<-----
811 14:44:39.842982
812 14:44:39.843037 ==
813 14:44:39.843092 Dram Type= 6, Freq= 0, CH_0, rank 0
814 14:44:39.843147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
815 14:44:39.843204 ==
816 14:44:39.843260 [Gating] SW mode calibration
817 14:44:39.843315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
818 14:44:39.843371 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
819 14:44:39.843427 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
820 14:44:39.843482 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
821 14:44:39.843538 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
822 14:44:39.843594 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:44:39.843649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:44:39.843705 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:44:39.843760 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:44:39.843816 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 14:44:39.843871 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 14:44:39.843927 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 14:44:39.843982 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 14:44:39.844037 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 14:44:39.844093 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 14:44:39.844148 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 14:44:39.844203 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 14:44:39.844259 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 14:44:39.844314 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 14:44:39.844368 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 14:44:39.844424 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
838 14:44:39.844479 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 14:44:39.844534 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 14:44:39.844629 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 14:44:39.844685 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 14:44:39.844741 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 14:44:39.844796 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 14:44:39.844852 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
845 14:44:39.844907 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
846 14:44:39.844963 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
847 14:44:39.845018 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 14:44:39.845073 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 14:44:39.845128 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 14:44:39.845183 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 14:44:39.845434 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 14:44:39.845499 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
853 14:44:39.845557 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
854 14:44:39.845614 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 14:44:39.845670 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 14:44:39.845727 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 14:44:39.845782 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:44:39.845838 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:44:39.845894 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:44:39.845950 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
861 14:44:39.846005 0 11 8 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
862 14:44:39.846061 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
863 14:44:39.846116 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 14:44:39.846172 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 14:44:39.846227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 14:44:39.846283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 14:44:39.846338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
868 14:44:39.846394 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
869 14:44:39.846449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
870 14:44:39.846504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 14:44:39.846559 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 14:44:39.846614 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 14:44:39.846669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 14:44:39.846724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 14:44:39.846780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 14:44:39.846835 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 14:44:39.846890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 14:44:39.846945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 14:44:39.847001 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 14:44:39.847056 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 14:44:39.847112 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 14:44:39.847167 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 14:44:39.847222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 14:44:39.847277 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
885 14:44:39.847333 Total UI for P1: 0, mck2ui 16
886 14:44:39.847389 best dqsien dly found for B0: ( 0, 14, 2)
887 14:44:39.847444 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 14:44:39.847500 Total UI for P1: 0, mck2ui 16
889 14:44:39.847555 best dqsien dly found for B1: ( 0, 14, 4)
890 14:44:39.847611 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
891 14:44:39.847666 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
892 14:44:39.847722
893 14:44:39.847777 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
894 14:44:39.847833 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
895 14:44:39.847888 [Gating] SW calibration Done
896 14:44:39.847944 ==
897 14:44:39.848000 Dram Type= 6, Freq= 0, CH_0, rank 0
898 14:44:39.848055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 14:44:39.848111 ==
900 14:44:39.848167 RX Vref Scan: 0
901 14:44:39.848222
902 14:44:39.848276 RX Vref 0 -> 0, step: 1
903 14:44:39.848331
904 14:44:39.848386 RX Delay -130 -> 252, step: 16
905 14:44:39.848441 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
906 14:44:39.848497 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
907 14:44:39.848559 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
908 14:44:39.848651 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
909 14:44:39.848706 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 14:44:39.848761 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
911 14:44:39.848817 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
912 14:44:39.848872 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
913 14:44:39.848927 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
914 14:44:39.848982 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
915 14:44:39.849037 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
916 14:44:39.849093 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
917 14:44:39.849148 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
918 14:44:39.849211 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
919 14:44:39.849287 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
920 14:44:39.849343 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
921 14:44:39.849399 ==
922 14:44:39.849454 Dram Type= 6, Freq= 0, CH_0, rank 0
923 14:44:39.849510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 14:44:39.849566 ==
925 14:44:39.849622 DQS Delay:
926 14:44:39.849677 DQS0 = 0, DQS1 = 0
927 14:44:39.849732 DQM Delay:
928 14:44:39.849787 DQM0 = 89, DQM1 = 78
929 14:44:39.849843 DQ Delay:
930 14:44:39.849897 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
931 14:44:39.849953 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
932 14:44:39.850008 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
933 14:44:39.850064 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
934 14:44:39.850119
935 14:44:39.850174
936 14:44:39.850229 ==
937 14:44:39.850284 Dram Type= 6, Freq= 0, CH_0, rank 0
938 14:44:39.850339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 14:44:39.850401 ==
940 14:44:39.850456
941 14:44:39.850511
942 14:44:39.850566 TX Vref Scan disable
943 14:44:39.850622 == TX Byte 0 ==
944 14:44:39.850677 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
945 14:44:39.850732 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
946 14:44:39.850788 == TX Byte 1 ==
947 14:44:39.850843 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
948 14:44:39.850898 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
949 14:44:39.850953 ==
950 14:44:39.851008 Dram Type= 6, Freq= 0, CH_0, rank 0
951 14:44:39.851062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 14:44:39.851117 ==
953 14:44:39.851172 TX Vref=22, minBit 6, minWin=27, winSum=440
954 14:44:39.851231 TX Vref=24, minBit 7, minWin=27, winSum=445
955 14:44:39.851287 TX Vref=26, minBit 8, minWin=27, winSum=447
956 14:44:39.851343 TX Vref=28, minBit 12, minWin=27, winSum=454
957 14:44:39.851398 TX Vref=30, minBit 6, minWin=28, winSum=458
958 14:44:39.851453 TX Vref=32, minBit 5, minWin=28, winSum=458
959 14:44:39.851701 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 30
960 14:44:39.851766
961 14:44:39.851822 Final TX Range 1 Vref 30
962 14:44:39.851878
963 14:44:39.851932 ==
964 14:44:39.851987 Dram Type= 6, Freq= 0, CH_0, rank 0
965 14:44:39.852043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 14:44:39.852099 ==
967 14:44:39.852154
968 14:44:39.852209
969 14:44:39.852264 TX Vref Scan disable
970 14:44:39.852319 == TX Byte 0 ==
971 14:44:39.852374 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
972 14:44:39.852429 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
973 14:44:39.852485 == TX Byte 1 ==
974 14:44:39.852540 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
975 14:44:39.852642 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
976 14:44:39.852697
977 14:44:39.852753 [DATLAT]
978 14:44:39.852807 Freq=800, CH0 RK0
979 14:44:39.852862
980 14:44:39.852917 DATLAT Default: 0xa
981 14:44:39.852972 0, 0xFFFF, sum = 0
982 14:44:39.853027 1, 0xFFFF, sum = 0
983 14:44:39.853084 2, 0xFFFF, sum = 0
984 14:44:39.853139 3, 0xFFFF, sum = 0
985 14:44:39.853198 4, 0xFFFF, sum = 0
986 14:44:39.853254 5, 0xFFFF, sum = 0
987 14:44:39.853310 6, 0xFFFF, sum = 0
988 14:44:39.853368 7, 0xFFFF, sum = 0
989 14:44:39.853462 8, 0xFFFF, sum = 0
990 14:44:39.853562 9, 0x0, sum = 1
991 14:44:39.853626 10, 0x0, sum = 2
992 14:44:39.853684 11, 0x0, sum = 3
993 14:44:39.853741 12, 0x0, sum = 4
994 14:44:39.853798 best_step = 10
995 14:44:39.853854
996 14:44:39.853909 ==
997 14:44:39.853965 Dram Type= 6, Freq= 0, CH_0, rank 0
998 14:44:39.854020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
999 14:44:39.854076 ==
1000 14:44:39.854131 RX Vref Scan: 1
1001 14:44:39.854186
1002 14:44:39.854241 Set Vref Range= 32 -> 127
1003 14:44:39.854296
1004 14:44:39.854351 RX Vref 32 -> 127, step: 1
1005 14:44:39.854405
1006 14:44:39.854460 RX Delay -95 -> 252, step: 8
1007 14:44:39.854515
1008 14:44:39.854570 Set Vref, RX VrefLevel [Byte0]: 32
1009 14:44:39.854626 [Byte1]: 32
1010 14:44:39.854681
1011 14:44:39.854735 Set Vref, RX VrefLevel [Byte0]: 33
1012 14:44:39.854790 [Byte1]: 33
1013 14:44:39.854846
1014 14:44:39.854900 Set Vref, RX VrefLevel [Byte0]: 34
1015 14:44:39.854955 [Byte1]: 34
1016 14:44:39.855010
1017 14:44:39.855065 Set Vref, RX VrefLevel [Byte0]: 35
1018 14:44:39.855121 [Byte1]: 35
1019 14:44:39.855177
1020 14:44:39.855232 Set Vref, RX VrefLevel [Byte0]: 36
1021 14:44:39.855287 [Byte1]: 36
1022 14:44:39.855342
1023 14:44:39.855396 Set Vref, RX VrefLevel [Byte0]: 37
1024 14:44:39.855452 [Byte1]: 37
1025 14:44:39.855514
1026 14:44:39.855571 Set Vref, RX VrefLevel [Byte0]: 38
1027 14:44:39.855632 [Byte1]: 38
1028 14:44:39.855688
1029 14:44:39.855743 Set Vref, RX VrefLevel [Byte0]: 39
1030 14:44:39.855820 [Byte1]: 39
1031 14:44:39.855876
1032 14:44:39.855945 Set Vref, RX VrefLevel [Byte0]: 40
1033 14:44:39.856000 [Byte1]: 40
1034 14:44:39.856054
1035 14:44:39.856107 Set Vref, RX VrefLevel [Byte0]: 41
1036 14:44:39.856162 [Byte1]: 41
1037 14:44:39.856216
1038 14:44:39.856285 Set Vref, RX VrefLevel [Byte0]: 42
1039 14:44:39.856373 [Byte1]: 42
1040 14:44:39.856489
1041 14:44:39.856599 Set Vref, RX VrefLevel [Byte0]: 43
1042 14:44:39.856658 [Byte1]: 43
1043 14:44:39.856745
1044 14:44:39.856800 Set Vref, RX VrefLevel [Byte0]: 44
1045 14:44:39.856874 [Byte1]: 44
1046 14:44:39.856944
1047 14:44:39.856999 Set Vref, RX VrefLevel [Byte0]: 45
1048 14:44:39.857054 [Byte1]: 45
1049 14:44:39.857108
1050 14:44:39.857163 Set Vref, RX VrefLevel [Byte0]: 46
1051 14:44:39.857217 [Byte1]: 46
1052 14:44:39.857276
1053 14:44:39.857330 Set Vref, RX VrefLevel [Byte0]: 47
1054 14:44:39.857385 [Byte1]: 47
1055 14:44:39.857440
1056 14:44:39.857494 Set Vref, RX VrefLevel [Byte0]: 48
1057 14:44:39.857549 [Byte1]: 48
1058 14:44:39.857603
1059 14:44:39.857658 Set Vref, RX VrefLevel [Byte0]: 49
1060 14:44:39.857712 [Byte1]: 49
1061 14:44:39.857766
1062 14:44:39.857820 Set Vref, RX VrefLevel [Byte0]: 50
1063 14:44:39.857874 [Byte1]: 50
1064 14:44:39.857928
1065 14:44:39.857982 Set Vref, RX VrefLevel [Byte0]: 51
1066 14:44:39.858036 [Byte1]: 51
1067 14:44:39.858090
1068 14:44:39.858144 Set Vref, RX VrefLevel [Byte0]: 52
1069 14:44:39.858198 [Byte1]: 52
1070 14:44:39.858252
1071 14:44:39.858318 Set Vref, RX VrefLevel [Byte0]: 53
1072 14:44:39.858376 [Byte1]: 53
1073 14:44:39.858431
1074 14:44:39.858485 Set Vref, RX VrefLevel [Byte0]: 54
1075 14:44:39.858540 [Byte1]: 54
1076 14:44:39.858595
1077 14:44:39.858650 Set Vref, RX VrefLevel [Byte0]: 55
1078 14:44:39.858704 [Byte1]: 55
1079 14:44:39.858759
1080 14:44:39.858813 Set Vref, RX VrefLevel [Byte0]: 56
1081 14:44:39.858867 [Byte1]: 56
1082 14:44:39.858921
1083 14:44:39.858975 Set Vref, RX VrefLevel [Byte0]: 57
1084 14:44:39.859029 [Byte1]: 57
1085 14:44:39.859084
1086 14:44:39.859138 Set Vref, RX VrefLevel [Byte0]: 58
1087 14:44:39.859192 [Byte1]: 58
1088 14:44:39.859246
1089 14:44:39.859300 Set Vref, RX VrefLevel [Byte0]: 59
1090 14:44:39.859357 [Byte1]: 59
1091 14:44:39.859411
1092 14:44:39.859465 Set Vref, RX VrefLevel [Byte0]: 60
1093 14:44:39.859519 [Byte1]: 60
1094 14:44:39.859573
1095 14:44:39.859627 Set Vref, RX VrefLevel [Byte0]: 61
1096 14:44:39.859681 [Byte1]: 61
1097 14:44:39.859754
1098 14:44:39.859823 Set Vref, RX VrefLevel [Byte0]: 62
1099 14:44:39.859877 [Byte1]: 62
1100 14:44:39.859932
1101 14:44:39.859986 Set Vref, RX VrefLevel [Byte0]: 63
1102 14:44:39.860040 [Byte1]: 63
1103 14:44:39.860094
1104 14:44:39.860148 Set Vref, RX VrefLevel [Byte0]: 64
1105 14:44:39.860203 [Byte1]: 64
1106 14:44:39.860257
1107 14:44:39.860311 Set Vref, RX VrefLevel [Byte0]: 65
1108 14:44:39.860365 [Byte1]: 65
1109 14:44:39.860418
1110 14:44:39.860472 Set Vref, RX VrefLevel [Byte0]: 66
1111 14:44:39.860526 [Byte1]: 66
1112 14:44:39.860604
1113 14:44:39.860673 Set Vref, RX VrefLevel [Byte0]: 67
1114 14:44:39.860727 [Byte1]: 67
1115 14:44:39.860781
1116 14:44:39.860835 Set Vref, RX VrefLevel [Byte0]: 68
1117 14:44:39.860889 [Byte1]: 68
1118 14:44:39.860944
1119 14:44:39.860998 Set Vref, RX VrefLevel [Byte0]: 69
1120 14:44:39.861052 [Byte1]: 69
1121 14:44:39.861107
1122 14:44:39.861161 Set Vref, RX VrefLevel [Byte0]: 70
1123 14:44:39.861215 [Byte1]: 70
1124 14:44:39.861269
1125 14:44:39.861323 Set Vref, RX VrefLevel [Byte0]: 71
1126 14:44:39.861377 [Byte1]: 71
1127 14:44:39.861432
1128 14:44:39.861485 Set Vref, RX VrefLevel [Byte0]: 72
1129 14:44:39.861539 [Byte1]: 72
1130 14:44:39.861593
1131 14:44:39.861647 Set Vref, RX VrefLevel [Byte0]: 73
1132 14:44:39.861901 [Byte1]: 73
1133 14:44:39.861965
1134 14:44:39.862022 Set Vref, RX VrefLevel [Byte0]: 74
1135 14:44:39.862078 [Byte1]: 74
1136 14:44:39.862133
1137 14:44:39.862188 Set Vref, RX VrefLevel [Byte0]: 75
1138 14:44:39.862243 [Byte1]: 75
1139 14:44:39.862298
1140 14:44:39.862353 Set Vref, RX VrefLevel [Byte0]: 76
1141 14:44:39.862407 [Byte1]: 76
1142 14:44:39.862462
1143 14:44:39.862517 Set Vref, RX VrefLevel [Byte0]: 77
1144 14:44:39.862571 [Byte1]: 77
1145 14:44:39.862626
1146 14:44:39.862681 Final RX Vref Byte 0 = 62 to rank0
1147 14:44:39.862737 Final RX Vref Byte 1 = 61 to rank0
1148 14:44:39.862793 Final RX Vref Byte 0 = 62 to rank1
1149 14:44:39.862848 Final RX Vref Byte 1 = 61 to rank1==
1150 14:44:39.862903 Dram Type= 6, Freq= 0, CH_0, rank 0
1151 14:44:39.862958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 14:44:39.863014 ==
1153 14:44:39.863069 DQS Delay:
1154 14:44:39.863124 DQS0 = 0, DQS1 = 0
1155 14:44:39.863178 DQM Delay:
1156 14:44:39.863232 DQM0 = 93, DQM1 = 82
1157 14:44:39.863319 DQ Delay:
1158 14:44:39.863392 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1159 14:44:39.863460 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1160 14:44:39.863514 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1161 14:44:39.863568 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1162 14:44:39.863622
1163 14:44:39.863674
1164 14:44:39.863728 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1165 14:44:39.863783 CH0 RK0: MR19=606, MR18=3D38
1166 14:44:39.863837 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1167 14:44:39.863891
1168 14:44:39.863944 ----->DramcWriteLeveling(PI) begin...
1169 14:44:39.863998 ==
1170 14:44:39.864052 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 14:44:39.864105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 14:44:39.864160 ==
1173 14:44:39.864214 Write leveling (Byte 0): 33 => 33
1174 14:44:39.864268 Write leveling (Byte 1): 28 => 28
1175 14:44:39.864323 DramcWriteLeveling(PI) end<-----
1176 14:44:39.864377
1177 14:44:39.864431 ==
1178 14:44:39.864485 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 14:44:39.864540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 14:44:39.864638 ==
1181 14:44:39.864693 [Gating] SW mode calibration
1182 14:44:39.864747 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1183 14:44:39.864803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1184 14:44:39.864858 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1185 14:44:39.864913 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1186 14:44:39.864968 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 14:44:39.865023 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 14:44:39.865078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 14:44:39.865132 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 14:44:39.865186 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 14:44:39.865241 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 14:44:39.865296 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 14:44:39.865351 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 14:44:39.865405 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 14:44:39.865459 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 14:44:39.865514 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 14:44:39.865569 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 14:44:39.865624 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 14:44:39.865678 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 14:44:39.865732 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 14:44:39.865787 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1202 14:44:39.865842 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 14:44:39.865896 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 14:44:39.865950 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 14:44:39.866004 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 14:44:39.866059 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 14:44:39.866114 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 14:44:39.866168 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 14:44:39.866222 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1210 14:44:39.866277 0 9 8 | B1->B0 | 2c2c 3333 | 1 0 | (1 1) (0 0)
1211 14:44:39.866331 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 14:44:39.866386 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 14:44:39.866440 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 14:44:39.866495 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 14:44:39.866549 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 14:44:39.866603 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1217 14:44:39.866691 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1218 14:44:39.866746 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1219 14:44:39.866800 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 14:44:39.866883 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 14:44:39.866941 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 14:44:39.867013 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 14:44:39.867084 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 14:44:39.867171 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 14:44:39.867224 0 11 4 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
1226 14:44:39.867278 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1227 14:44:39.867332 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 14:44:39.867386 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 14:44:39.867439 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 14:44:39.867493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 14:44:39.867546 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 14:44:39.867600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 14:44:39.867653 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1234 14:44:39.867900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 14:44:39.867963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 14:44:39.868019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 14:44:39.868074 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 14:44:39.868129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 14:44:39.868184 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 14:44:39.868239 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 14:44:39.868293 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 14:44:39.868348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 14:44:39.868402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 14:44:39.868457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 14:44:39.868511 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 14:44:39.868603 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 14:44:39.868659 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 14:44:39.868714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 14:44:39.868769 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 14:44:39.868823 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 14:44:39.868877 Total UI for P1: 0, mck2ui 16
1252 14:44:39.868933 best dqsien dly found for B0: ( 0, 14, 6)
1253 14:44:39.868988 Total UI for P1: 0, mck2ui 16
1254 14:44:39.869043 best dqsien dly found for B1: ( 0, 14, 6)
1255 14:44:39.869097 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1256 14:44:39.869152 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1257 14:44:39.869206
1258 14:44:39.869260 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1259 14:44:39.869314 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1260 14:44:39.869368 [Gating] SW calibration Done
1261 14:44:39.869423 ==
1262 14:44:39.869476 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 14:44:39.869530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 14:44:39.869585 ==
1265 14:44:39.869639 RX Vref Scan: 0
1266 14:44:39.869693
1267 14:44:39.869747 RX Vref 0 -> 0, step: 1
1268 14:44:39.869801
1269 14:44:39.869855 RX Delay -130 -> 252, step: 16
1270 14:44:39.869909 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1271 14:44:39.869963 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1272 14:44:39.870018 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1273 14:44:39.870072 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1274 14:44:39.870126 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1275 14:44:39.870180 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1276 14:44:39.870235 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1277 14:44:39.870289 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1278 14:44:39.870344 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1279 14:44:39.870398 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1280 14:44:39.870452 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1281 14:44:39.870507 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1282 14:44:39.870561 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1283 14:44:39.870615 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1284 14:44:39.870669 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1285 14:44:39.870723 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1286 14:44:39.870777 ==
1287 14:44:39.870831 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 14:44:39.870885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 14:44:39.870940 ==
1290 14:44:39.870994 DQS Delay:
1291 14:44:39.871048 DQS0 = 0, DQS1 = 0
1292 14:44:39.871102 DQM Delay:
1293 14:44:39.871156 DQM0 = 87, DQM1 = 80
1294 14:44:39.871210 DQ Delay:
1295 14:44:39.871264 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1296 14:44:39.871319 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1297 14:44:39.871373 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1298 14:44:39.871427 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1299 14:44:39.871481
1300 14:44:39.871534
1301 14:44:39.871587 ==
1302 14:44:39.871641 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 14:44:39.871695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 14:44:39.871749 ==
1305 14:44:39.871803
1306 14:44:39.871857
1307 14:44:39.871911 TX Vref Scan disable
1308 14:44:39.871965 == TX Byte 0 ==
1309 14:44:39.872019 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1310 14:44:39.872074 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1311 14:44:39.872129 == TX Byte 1 ==
1312 14:44:39.872183 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1313 14:44:39.872237 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1314 14:44:39.872291 ==
1315 14:44:39.872345 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 14:44:39.872400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 14:44:39.872454 ==
1318 14:44:39.872508 TX Vref=22, minBit 1, minWin=27, winSum=444
1319 14:44:39.872590 TX Vref=24, minBit 8, minWin=27, winSum=449
1320 14:44:39.872660 TX Vref=26, minBit 10, minWin=27, winSum=453
1321 14:44:39.872714 TX Vref=28, minBit 8, minWin=27, winSum=454
1322 14:44:39.872769 TX Vref=30, minBit 8, minWin=27, winSum=457
1323 14:44:39.872823 TX Vref=32, minBit 6, minWin=28, winSum=459
1324 14:44:39.872878 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 32
1325 14:44:39.872932
1326 14:44:39.872986 Final TX Range 1 Vref 32
1327 14:44:39.873041
1328 14:44:39.873094 ==
1329 14:44:39.873148 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 14:44:39.873202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 14:44:39.873280 ==
1332 14:44:39.873336
1333 14:44:39.873388
1334 14:44:39.873440 TX Vref Scan disable
1335 14:44:39.873492 == TX Byte 0 ==
1336 14:44:39.873545 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1337 14:44:39.873597 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1338 14:44:39.873649 == TX Byte 1 ==
1339 14:44:39.873701 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1340 14:44:39.873754 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1341 14:44:39.873806
1342 14:44:39.873858 [DATLAT]
1343 14:44:39.873910 Freq=800, CH0 RK1
1344 14:44:39.873962
1345 14:44:39.874014 DATLAT Default: 0xa
1346 14:44:39.874066 0, 0xFFFF, sum = 0
1347 14:44:39.874120 1, 0xFFFF, sum = 0
1348 14:44:39.874173 2, 0xFFFF, sum = 0
1349 14:44:39.874225 3, 0xFFFF, sum = 0
1350 14:44:39.874278 4, 0xFFFF, sum = 0
1351 14:44:39.874331 5, 0xFFFF, sum = 0
1352 14:44:39.874384 6, 0xFFFF, sum = 0
1353 14:44:39.874437 7, 0xFFFF, sum = 0
1354 14:44:39.874490 8, 0xFFFF, sum = 0
1355 14:44:39.874543 9, 0x0, sum = 1
1356 14:44:39.874596 10, 0x0, sum = 2
1357 14:44:39.874649 11, 0x0, sum = 3
1358 14:44:39.874702 12, 0x0, sum = 4
1359 14:44:39.874755 best_step = 10
1360 14:44:39.874808
1361 14:44:39.874859 ==
1362 14:44:39.874911 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 14:44:39.874964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 14:44:39.875017 ==
1365 14:44:39.875068 RX Vref Scan: 0
1366 14:44:39.875120
1367 14:44:39.875172 RX Vref 0 -> 0, step: 1
1368 14:44:39.875223
1369 14:44:39.875275 RX Delay -95 -> 252, step: 8
1370 14:44:39.875521 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1371 14:44:39.875581 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1372 14:44:39.875635 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1373 14:44:39.875688 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1374 14:44:39.875741 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1375 14:44:39.875795 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1376 14:44:39.875848 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1377 14:44:39.875900 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1378 14:44:39.875953 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1379 14:44:39.876006 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1380 14:44:39.876058 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1381 14:44:39.876111 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1382 14:44:39.876163 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1383 14:44:39.876216 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1384 14:44:39.876268 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1385 14:44:39.876321 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1386 14:44:39.876373 ==
1387 14:44:39.876426 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 14:44:39.876479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 14:44:39.876531 ==
1390 14:44:39.876622 DQS Delay:
1391 14:44:39.876675 DQS0 = 0, DQS1 = 0
1392 14:44:39.876727 DQM Delay:
1393 14:44:39.876779 DQM0 = 90, DQM1 = 80
1394 14:44:39.876831 DQ Delay:
1395 14:44:39.876883 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1396 14:44:39.876936 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1397 14:44:39.876988 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1398 14:44:39.877041 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1399 14:44:39.877093
1400 14:44:39.877144
1401 14:44:39.877196 [DQSOSCAuto] RK1, (LSB)MR18= 0x401b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1402 14:44:39.877250 CH0 RK1: MR19=606, MR18=401B
1403 14:44:39.877302 CH0_RK1: MR19=0x606, MR18=0x401B, DQSOSC=393, MR23=63, INC=95, DEC=63
1404 14:44:39.877355 [RxdqsGatingPostProcess] freq 800
1405 14:44:39.877407 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1406 14:44:39.877460 Pre-setting of DQS Precalculation
1407 14:44:39.877512 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1408 14:44:39.877564 ==
1409 14:44:39.877617 Dram Type= 6, Freq= 0, CH_1, rank 0
1410 14:44:39.877669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 14:44:39.877721 ==
1412 14:44:39.877773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 14:44:39.877827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 14:44:39.877880 [CA 0] Center 36 (6~67) winsize 62
1415 14:44:39.877932 [CA 1] Center 37 (6~68) winsize 63
1416 14:44:39.877984 [CA 2] Center 35 (5~65) winsize 61
1417 14:44:39.878036 [CA 3] Center 34 (4~65) winsize 62
1418 14:44:39.878088 [CA 4] Center 34 (4~65) winsize 62
1419 14:44:39.878140 [CA 5] Center 34 (3~65) winsize 63
1420 14:44:39.878192
1421 14:44:39.878244 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1422 14:44:39.878296
1423 14:44:39.878349 [CATrainingPosCal] consider 1 rank data
1424 14:44:39.878401 u2DelayCellTimex100 = 270/100 ps
1425 14:44:39.878453 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 14:44:39.878506 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1427 14:44:39.878559 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 14:44:39.878611 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 14:44:39.878663 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 14:44:39.878715 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1431 14:44:39.878767
1432 14:44:39.878819 CA PerBit enable=1, Macro0, CA PI delay=34
1433 14:44:39.878872
1434 14:44:39.878923 [CBTSetCACLKResult] CA Dly = 34
1435 14:44:39.878975 CS Dly: 5 (0~36)
1436 14:44:39.879028 ==
1437 14:44:39.879080 Dram Type= 6, Freq= 0, CH_1, rank 1
1438 14:44:39.879133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 14:44:39.879185 ==
1440 14:44:39.879238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 14:44:39.879290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 14:44:39.879343 [CA 0] Center 36 (6~67) winsize 62
1443 14:44:39.879395 [CA 1] Center 37 (6~68) winsize 63
1444 14:44:39.879448 [CA 2] Center 35 (5~66) winsize 62
1445 14:44:39.879499 [CA 3] Center 34 (4~65) winsize 62
1446 14:44:39.879551 [CA 4] Center 34 (4~65) winsize 62
1447 14:44:39.879603 [CA 5] Center 34 (4~65) winsize 62
1448 14:44:39.879655
1449 14:44:39.879707 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1450 14:44:39.879759
1451 14:44:39.879810 [CATrainingPosCal] consider 2 rank data
1452 14:44:39.879863 u2DelayCellTimex100 = 270/100 ps
1453 14:44:39.879915 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 14:44:39.879968 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1455 14:44:39.880020 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1456 14:44:39.880072 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 14:44:39.880124 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 14:44:39.880176 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 14:44:39.880228
1460 14:44:39.880280 CA PerBit enable=1, Macro0, CA PI delay=34
1461 14:44:39.880332
1462 14:44:39.880384 [CBTSetCACLKResult] CA Dly = 34
1463 14:44:39.880436 CS Dly: 5 (0~37)
1464 14:44:39.880487
1465 14:44:39.880539 ----->DramcWriteLeveling(PI) begin...
1466 14:44:39.880634 ==
1467 14:44:39.880687 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 14:44:39.880739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 14:44:39.880792 ==
1470 14:44:39.880844 Write leveling (Byte 0): 26 => 26
1471 14:44:39.880895 Write leveling (Byte 1): 31 => 31
1472 14:44:39.880948 DramcWriteLeveling(PI) end<-----
1473 14:44:39.881000
1474 14:44:39.881052 ==
1475 14:44:39.881104 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 14:44:39.881157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 14:44:39.881210 ==
1478 14:44:39.881262 [Gating] SW mode calibration
1479 14:44:39.881314 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1480 14:44:39.881367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1481 14:44:39.881420 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1482 14:44:39.881473 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 14:44:39.881526 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 14:44:39.881578 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 14:44:39.881630 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 14:44:39.881682 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 14:44:39.881932 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 14:44:39.881996 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 14:44:39.882050 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 14:44:39.882105 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 14:44:39.882158 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 14:44:39.882211 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 14:44:39.882264 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 14:44:39.882317 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 14:44:39.882369 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 14:44:39.882422 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1497 14:44:39.882474 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1498 14:44:39.882544 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1499 14:44:39.882611 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 14:44:39.882664 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 14:44:39.882716 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 14:44:39.882769 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 14:44:39.882821 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 14:44:39.882874 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 14:44:39.882926 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 14:44:39.882979 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1507 14:44:39.883032 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 14:44:39.883107 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 14:44:39.883205 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 14:44:39.883257 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 14:44:39.883341 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 14:44:39.883393 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 14:44:39.883446 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1514 14:44:39.883498 0 10 4 | B1->B0 | 2f2f 2d2d | 1 1 | (0 0) (1 0)
1515 14:44:39.883550 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1516 14:44:39.883603 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 14:44:39.883655 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 14:44:39.883708 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 14:44:39.883760 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 14:44:39.883813 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 14:44:39.883865 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1522 14:44:39.883949 0 11 4 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
1523 14:44:39.884003 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
1524 14:44:39.884055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 14:44:39.884108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 14:44:39.884161 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 14:44:39.884212 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 14:44:39.884265 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 14:44:39.884317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1530 14:44:39.884370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1531 14:44:39.884423 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 14:44:39.884475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 14:44:39.884551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 14:44:39.884620 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 14:44:39.884673 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 14:44:39.884726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 14:44:39.884811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 14:44:39.884900 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 14:44:39.884981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 14:44:39.885038 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 14:44:39.885092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 14:44:39.885145 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 14:44:39.885198 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 14:44:39.885251 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 14:44:39.885303 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 14:44:39.885356 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1547 14:44:39.885414 Total UI for P1: 0, mck2ui 16
1548 14:44:39.885467 best dqsien dly found for B0: ( 0, 14, 2)
1549 14:44:39.885538 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 14:44:39.885605 Total UI for P1: 0, mck2ui 16
1551 14:44:39.885658 best dqsien dly found for B1: ( 0, 14, 4)
1552 14:44:39.885711 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1553 14:44:39.885764 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1554 14:44:39.885817
1555 14:44:39.885868 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1556 14:44:39.885921 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1557 14:44:39.885974 [Gating] SW calibration Done
1558 14:44:39.886027 ==
1559 14:44:39.886080 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 14:44:39.886133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 14:44:39.886186 ==
1562 14:44:39.886238 RX Vref Scan: 0
1563 14:44:39.886290
1564 14:44:39.886342 RX Vref 0 -> 0, step: 1
1565 14:44:39.886394
1566 14:44:39.886446 RX Delay -130 -> 252, step: 16
1567 14:44:39.886498 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1568 14:44:39.886550 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1569 14:44:39.886603 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1570 14:44:39.886655 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1571 14:44:39.886708 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1572 14:44:39.886760 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1573 14:44:39.886812 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1574 14:44:39.886864 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1575 14:44:39.886919 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1576 14:44:39.886973 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1577 14:44:39.887225 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1578 14:44:39.887285 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1579 14:44:39.887339 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1580 14:44:39.887392 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1581 14:44:39.887445 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1582 14:44:39.887497 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1583 14:44:39.887582 ==
1584 14:44:39.887635 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 14:44:39.887687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 14:44:39.887740 ==
1587 14:44:39.887793 DQS Delay:
1588 14:44:39.887845 DQS0 = 0, DQS1 = 0
1589 14:44:39.887897 DQM Delay:
1590 14:44:39.887950 DQM0 = 86, DQM1 = 80
1591 14:44:39.888002 DQ Delay:
1592 14:44:39.888054 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1593 14:44:39.888107 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1594 14:44:39.888159 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1595 14:44:39.888211 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1596 14:44:39.888264
1597 14:44:39.888316
1598 14:44:39.888368 ==
1599 14:44:39.888421 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 14:44:39.888473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 14:44:39.888525 ==
1602 14:44:39.888616
1603 14:44:39.888668
1604 14:44:39.888720 TX Vref Scan disable
1605 14:44:39.888773 == TX Byte 0 ==
1606 14:44:39.888826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1607 14:44:39.888879 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1608 14:44:39.888931 == TX Byte 1 ==
1609 14:44:39.888983 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1610 14:44:39.889035 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1611 14:44:39.889088 ==
1612 14:44:39.889140 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 14:44:39.889193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 14:44:39.889279 ==
1615 14:44:39.889331 TX Vref=22, minBit 15, minWin=27, winSum=453
1616 14:44:39.889384 TX Vref=24, minBit 13, minWin=27, winSum=452
1617 14:44:39.889437 TX Vref=26, minBit 15, minWin=27, winSum=455
1618 14:44:39.889489 TX Vref=28, minBit 15, minWin=27, winSum=455
1619 14:44:39.889542 TX Vref=30, minBit 8, minWin=28, winSum=458
1620 14:44:39.889595 TX Vref=32, minBit 12, minWin=27, winSum=456
1621 14:44:39.889648 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1622 14:44:39.889701
1623 14:44:39.889753 Final TX Range 1 Vref 30
1624 14:44:39.889806
1625 14:44:39.889858 ==
1626 14:44:39.889910 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 14:44:39.889963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 14:44:39.890015 ==
1629 14:44:39.890067
1630 14:44:39.890119
1631 14:44:39.890170 TX Vref Scan disable
1632 14:44:39.890222 == TX Byte 0 ==
1633 14:44:39.890274 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1634 14:44:39.890327 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1635 14:44:39.890379 == TX Byte 1 ==
1636 14:44:39.890431 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1637 14:44:39.890484 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1638 14:44:39.890536
1639 14:44:39.890589 [DATLAT]
1640 14:44:39.890641 Freq=800, CH1 RK0
1641 14:44:39.890694
1642 14:44:39.890746 DATLAT Default: 0xa
1643 14:44:39.890798 0, 0xFFFF, sum = 0
1644 14:44:39.890852 1, 0xFFFF, sum = 0
1645 14:44:39.890905 2, 0xFFFF, sum = 0
1646 14:44:39.890958 3, 0xFFFF, sum = 0
1647 14:44:39.891012 4, 0xFFFF, sum = 0
1648 14:44:39.891064 5, 0xFFFF, sum = 0
1649 14:44:39.891117 6, 0xFFFF, sum = 0
1650 14:44:39.891170 7, 0xFFFF, sum = 0
1651 14:44:39.891223 8, 0xFFFF, sum = 0
1652 14:44:39.891276 9, 0x0, sum = 1
1653 14:44:39.891329 10, 0x0, sum = 2
1654 14:44:39.891382 11, 0x0, sum = 3
1655 14:44:39.891435 12, 0x0, sum = 4
1656 14:44:39.891488 best_step = 10
1657 14:44:39.891540
1658 14:44:39.891591 ==
1659 14:44:39.891643 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 14:44:39.891695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 14:44:39.891748 ==
1662 14:44:39.891801 RX Vref Scan: 1
1663 14:44:39.891852
1664 14:44:39.891904 Set Vref Range= 32 -> 127
1665 14:44:39.891956
1666 14:44:39.892008 RX Vref 32 -> 127, step: 1
1667 14:44:39.892061
1668 14:44:39.892113 RX Delay -95 -> 252, step: 8
1669 14:44:39.892164
1670 14:44:39.892216 Set Vref, RX VrefLevel [Byte0]: 32
1671 14:44:39.892269 [Byte1]: 32
1672 14:44:39.892322
1673 14:44:39.892373 Set Vref, RX VrefLevel [Byte0]: 33
1674 14:44:39.892425 [Byte1]: 33
1675 14:44:39.892477
1676 14:44:39.892529 Set Vref, RX VrefLevel [Byte0]: 34
1677 14:44:39.892617 [Byte1]: 34
1678 14:44:39.892669
1679 14:44:39.892721 Set Vref, RX VrefLevel [Byte0]: 35
1680 14:44:39.892774 [Byte1]: 35
1681 14:44:39.892826
1682 14:44:39.892877 Set Vref, RX VrefLevel [Byte0]: 36
1683 14:44:39.892930 [Byte1]: 36
1684 14:44:39.892983
1685 14:44:39.893036 Set Vref, RX VrefLevel [Byte0]: 37
1686 14:44:39.893087 [Byte1]: 37
1687 14:44:39.893140
1688 14:44:39.893192 Set Vref, RX VrefLevel [Byte0]: 38
1689 14:44:39.893244 [Byte1]: 38
1690 14:44:39.893324
1691 14:44:39.893381 Set Vref, RX VrefLevel [Byte0]: 39
1692 14:44:39.893435 [Byte1]: 39
1693 14:44:39.893488
1694 14:44:39.893539 Set Vref, RX VrefLevel [Byte0]: 40
1695 14:44:39.893591 [Byte1]: 40
1696 14:44:39.893643
1697 14:44:39.893696 Set Vref, RX VrefLevel [Byte0]: 41
1698 14:44:39.893748 [Byte1]: 41
1699 14:44:39.893800
1700 14:44:39.893852 Set Vref, RX VrefLevel [Byte0]: 42
1701 14:44:39.893904 [Byte1]: 42
1702 14:44:39.893957
1703 14:44:39.894008 Set Vref, RX VrefLevel [Byte0]: 43
1704 14:44:39.894061 [Byte1]: 43
1705 14:44:39.894114
1706 14:44:39.894166 Set Vref, RX VrefLevel [Byte0]: 44
1707 14:44:39.894217 [Byte1]: 44
1708 14:44:39.894269
1709 14:44:39.894322 Set Vref, RX VrefLevel [Byte0]: 45
1710 14:44:39.894374 [Byte1]: 45
1711 14:44:39.894426
1712 14:44:39.894477 Set Vref, RX VrefLevel [Byte0]: 46
1713 14:44:39.894529 [Byte1]: 46
1714 14:44:39.894581
1715 14:44:39.894633 Set Vref, RX VrefLevel [Byte0]: 47
1716 14:44:39.894685 [Byte1]: 47
1717 14:44:39.894737
1718 14:44:39.894789 Set Vref, RX VrefLevel [Byte0]: 48
1719 14:44:39.894841 [Byte1]: 48
1720 14:44:39.894893
1721 14:44:39.894945 Set Vref, RX VrefLevel [Byte0]: 49
1722 14:44:39.894997 [Byte1]: 49
1723 14:44:39.895049
1724 14:44:39.895101 Set Vref, RX VrefLevel [Byte0]: 50
1725 14:44:39.895153 [Byte1]: 50
1726 14:44:39.895206
1727 14:44:39.895259 Set Vref, RX VrefLevel [Byte0]: 51
1728 14:44:39.895340 [Byte1]: 51
1729 14:44:39.895434
1730 14:44:39.895512 Set Vref, RX VrefLevel [Byte0]: 52
1731 14:44:39.895568 [Byte1]: 52
1732 14:44:39.895621
1733 14:44:39.895706 Set Vref, RX VrefLevel [Byte0]: 53
1734 14:44:39.895759 [Byte1]: 53
1735 14:44:39.895812
1736 14:44:39.895864 Set Vref, RX VrefLevel [Byte0]: 54
1737 14:44:39.895917 [Byte1]: 54
1738 14:44:39.895970
1739 14:44:39.896023 Set Vref, RX VrefLevel [Byte0]: 55
1740 14:44:39.896272 [Byte1]: 55
1741 14:44:39.896332
1742 14:44:39.896386 Set Vref, RX VrefLevel [Byte0]: 56
1743 14:44:39.896439 [Byte1]: 56
1744 14:44:39.896492
1745 14:44:39.896569 Set Vref, RX VrefLevel [Byte0]: 57
1746 14:44:39.896637 [Byte1]: 57
1747 14:44:39.896690
1748 14:44:39.896742 Set Vref, RX VrefLevel [Byte0]: 58
1749 14:44:39.896795 [Byte1]: 58
1750 14:44:39.896847
1751 14:44:39.896900 Set Vref, RX VrefLevel [Byte0]: 59
1752 14:44:39.896953 [Byte1]: 59
1753 14:44:39.897005
1754 14:44:39.897057 Set Vref, RX VrefLevel [Byte0]: 60
1755 14:44:39.897110 [Byte1]: 60
1756 14:44:39.897162
1757 14:44:39.897214 Set Vref, RX VrefLevel [Byte0]: 61
1758 14:44:39.897266 [Byte1]: 61
1759 14:44:39.897318
1760 14:44:39.897370 Set Vref, RX VrefLevel [Byte0]: 62
1761 14:44:39.897422 [Byte1]: 62
1762 14:44:39.897474
1763 14:44:39.897526 Set Vref, RX VrefLevel [Byte0]: 63
1764 14:44:39.897578 [Byte1]: 63
1765 14:44:39.897630
1766 14:44:39.897682 Set Vref, RX VrefLevel [Byte0]: 64
1767 14:44:39.897734 [Byte1]: 64
1768 14:44:39.897787
1769 14:44:39.897839 Set Vref, RX VrefLevel [Byte0]: 65
1770 14:44:39.897891 [Byte1]: 65
1771 14:44:39.897943
1772 14:44:39.897995 Set Vref, RX VrefLevel [Byte0]: 66
1773 14:44:39.898048 [Byte1]: 66
1774 14:44:39.898100
1775 14:44:39.898151 Set Vref, RX VrefLevel [Byte0]: 67
1776 14:44:39.898203 [Byte1]: 67
1777 14:44:39.898255
1778 14:44:39.898307 Set Vref, RX VrefLevel [Byte0]: 68
1779 14:44:39.898359 [Byte1]: 68
1780 14:44:39.898411
1781 14:44:39.898463 Set Vref, RX VrefLevel [Byte0]: 69
1782 14:44:39.898516 [Byte1]: 69
1783 14:44:39.898568
1784 14:44:39.898620 Set Vref, RX VrefLevel [Byte0]: 70
1785 14:44:39.898672 [Byte1]: 70
1786 14:44:39.898724
1787 14:44:39.898776 Set Vref, RX VrefLevel [Byte0]: 71
1788 14:44:39.898828 [Byte1]: 71
1789 14:44:39.898880
1790 14:44:39.898932 Set Vref, RX VrefLevel [Byte0]: 72
1791 14:44:39.898984 [Byte1]: 72
1792 14:44:39.899035
1793 14:44:39.899087 Set Vref, RX VrefLevel [Byte0]: 73
1794 14:44:39.899139 [Byte1]: 73
1795 14:44:39.899208
1796 14:44:39.899300 Set Vref, RX VrefLevel [Byte0]: 74
1797 14:44:39.899357 [Byte1]: 74
1798 14:44:39.899410
1799 14:44:39.899462 Set Vref, RX VrefLevel [Byte0]: 75
1800 14:44:39.899514 [Byte1]: 75
1801 14:44:39.899566
1802 14:44:39.899619 Set Vref, RX VrefLevel [Byte0]: 76
1803 14:44:39.899671 [Byte1]: 76
1804 14:44:39.899722
1805 14:44:39.899774 Set Vref, RX VrefLevel [Byte0]: 77
1806 14:44:39.899827 [Byte1]: 77
1807 14:44:39.899879
1808 14:44:39.899931 Final RX Vref Byte 0 = 53 to rank0
1809 14:44:39.899984 Final RX Vref Byte 1 = 63 to rank0
1810 14:44:39.900039 Final RX Vref Byte 0 = 53 to rank1
1811 14:44:39.900092 Final RX Vref Byte 1 = 63 to rank1==
1812 14:44:39.900145 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 14:44:39.900198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 14:44:39.900251 ==
1815 14:44:39.900302 DQS Delay:
1816 14:44:39.900354 DQS0 = 0, DQS1 = 0
1817 14:44:39.900406 DQM Delay:
1818 14:44:39.900458 DQM0 = 91, DQM1 = 83
1819 14:44:39.900510 DQ Delay:
1820 14:44:39.900584 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =84
1821 14:44:39.900651 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =88
1822 14:44:39.900703 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1823 14:44:39.900756 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1824 14:44:39.900808
1825 14:44:39.900860
1826 14:44:39.900912 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1827 14:44:39.900966 CH1 RK0: MR19=606, MR18=2D4A
1828 14:44:39.901050 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1829 14:44:39.901103
1830 14:44:39.901155 ----->DramcWriteLeveling(PI) begin...
1831 14:44:39.901209 ==
1832 14:44:39.901261 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 14:44:39.901313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 14:44:39.901365 ==
1835 14:44:39.901417 Write leveling (Byte 0): 26 => 26
1836 14:44:39.901470 Write leveling (Byte 1): 31 => 31
1837 14:44:39.901522 DramcWriteLeveling(PI) end<-----
1838 14:44:39.901574
1839 14:44:39.901626 ==
1840 14:44:39.901678 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 14:44:39.901731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 14:44:39.901784 ==
1843 14:44:39.901836 [Gating] SW mode calibration
1844 14:44:39.901888 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 14:44:39.901941 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 14:44:39.901994 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 14:44:39.902046 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1848 14:44:39.902099 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1849 14:44:39.902151 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 14:44:39.902205 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 14:44:39.902257 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 14:44:39.902310 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 14:44:39.902362 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 14:44:39.902415 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 14:44:39.902467 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 14:44:39.902519 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 14:44:39.902571 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 14:44:39.902624 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 14:44:39.902676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 14:44:39.902728 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 14:44:39.902780 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 14:44:39.902833 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 14:44:39.902885 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1864 14:44:39.902937 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 14:44:39.902990 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 14:44:39.903042 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 14:44:39.903094 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 14:44:39.903146 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 14:44:39.903198 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 14:44:39.903453 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 14:44:39.903516 0 9 4 | B1->B0 | 2727 2424 | 1 1 | (0 0) (1 1)
1872 14:44:39.903571 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 14:44:39.903624 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 14:44:39.903677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 14:44:39.903730 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 14:44:39.903798 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 14:44:39.903867 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 14:44:39.903919 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1879 14:44:39.903972 0 10 4 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 1)
1880 14:44:39.904024 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1881 14:44:39.904109 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 14:44:39.904162 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 14:44:39.904215 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 14:44:39.904268 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 14:44:39.904320 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 14:44:39.904373 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 14:44:39.904426 0 11 4 | B1->B0 | 3838 3535 | 0 0 | (0 0) (1 1)
1888 14:44:39.904478 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1889 14:44:39.904530 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 14:44:39.904619 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 14:44:39.904672 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 14:44:39.904725 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 14:44:39.904777 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 14:44:39.904829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 14:44:39.904881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1896 14:44:39.904934 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1897 14:44:39.904986 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 14:44:39.905039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 14:44:39.905092 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 14:44:39.905144 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 14:44:39.905196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 14:44:39.905249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 14:44:39.905302 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 14:44:39.905354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 14:44:39.905407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 14:44:39.905459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 14:44:39.905512 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 14:44:39.905563 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 14:44:39.905616 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 14:44:39.905668 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 14:44:39.905720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1912 14:44:39.905773 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 14:44:39.905825 Total UI for P1: 0, mck2ui 16
1914 14:44:39.905879 best dqsien dly found for B0: ( 0, 14, 4)
1915 14:44:39.905931 Total UI for P1: 0, mck2ui 16
1916 14:44:39.905984 best dqsien dly found for B1: ( 0, 14, 4)
1917 14:44:39.906038 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1918 14:44:39.906090 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1919 14:44:39.906143
1920 14:44:39.906194 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1921 14:44:39.906247 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1922 14:44:39.906299 [Gating] SW calibration Done
1923 14:44:39.906352 ==
1924 14:44:39.906404 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 14:44:39.906457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 14:44:39.906510 ==
1927 14:44:39.906562 RX Vref Scan: 0
1928 14:44:39.906614
1929 14:44:39.906665 RX Vref 0 -> 0, step: 1
1930 14:44:39.906718
1931 14:44:39.906769 RX Delay -130 -> 252, step: 16
1932 14:44:39.906822 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1933 14:44:39.906874 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1934 14:44:39.906927 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1935 14:44:39.906979 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1936 14:44:39.907032 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1937 14:44:39.907083 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1938 14:44:39.907136 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1939 14:44:39.907188 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1940 14:44:39.907241 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1941 14:44:39.907293 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1942 14:44:39.907345 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1943 14:44:39.907397 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1944 14:44:39.907449 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1945 14:44:39.907502 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1946 14:44:39.907554 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1947 14:44:39.907606 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1948 14:44:39.907658 ==
1949 14:44:39.907710 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 14:44:39.907763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 14:44:39.907815 ==
1952 14:44:39.907868 DQS Delay:
1953 14:44:39.907924 DQS0 = 0, DQS1 = 0
1954 14:44:39.907976 DQM Delay:
1955 14:44:39.908028 DQM0 = 91, DQM1 = 79
1956 14:44:40.022281 DQ Delay:
1957 14:44:40.022417 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1958 14:44:40.022483 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1959 14:44:40.022544 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
1960 14:44:40.022603 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1961 14:44:40.022660
1962 14:44:40.022716
1963 14:44:40.022770 ==
1964 14:44:40.022825 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 14:44:40.022880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 14:44:40.022935 ==
1967 14:44:40.022989
1968 14:44:40.023042
1969 14:44:40.023095 TX Vref Scan disable
1970 14:44:40.023149 == TX Byte 0 ==
1971 14:44:40.023203 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1972 14:44:40.023257 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1973 14:44:40.023310 == TX Byte 1 ==
1974 14:44:40.023362 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1975 14:44:40.023627 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1976 14:44:40.023689 ==
1977 14:44:40.023743 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 14:44:40.023798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 14:44:40.023852 ==
1980 14:44:40.023906 TX Vref=22, minBit 12, minWin=27, winSum=452
1981 14:44:40.023960 TX Vref=24, minBit 8, minWin=27, winSum=450
1982 14:44:40.024047 TX Vref=26, minBit 13, minWin=27, winSum=456
1983 14:44:40.024100 TX Vref=28, minBit 8, minWin=28, winSum=458
1984 14:44:40.024154 TX Vref=30, minBit 8, minWin=28, winSum=460
1985 14:44:40.024207 TX Vref=32, minBit 8, minWin=28, winSum=458
1986 14:44:40.024260 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1987 14:44:40.024314
1988 14:44:40.024366 Final TX Range 1 Vref 30
1989 14:44:40.024419
1990 14:44:40.024471 ==
1991 14:44:40.024524 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 14:44:40.024621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 14:44:40.024675 ==
1994 14:44:40.024728
1995 14:44:40.024780
1996 14:44:40.024833 TX Vref Scan disable
1997 14:44:40.024885 == TX Byte 0 ==
1998 14:44:40.024938 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1999 14:44:40.024991 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2000 14:44:40.025044 == TX Byte 1 ==
2001 14:44:40.025097 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2002 14:44:40.025150 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2003 14:44:40.025203
2004 14:44:40.025255 [DATLAT]
2005 14:44:40.025307 Freq=800, CH1 RK1
2006 14:44:40.025359
2007 14:44:40.025411 DATLAT Default: 0xa
2008 14:44:40.025463 0, 0xFFFF, sum = 0
2009 14:44:40.025517 1, 0xFFFF, sum = 0
2010 14:44:40.025571 2, 0xFFFF, sum = 0
2011 14:44:40.025625 3, 0xFFFF, sum = 0
2012 14:44:40.025679 4, 0xFFFF, sum = 0
2013 14:44:40.025733 5, 0xFFFF, sum = 0
2014 14:44:40.025786 6, 0xFFFF, sum = 0
2015 14:44:40.025839 7, 0xFFFF, sum = 0
2016 14:44:40.025893 8, 0xFFFF, sum = 0
2017 14:44:40.025945 9, 0x0, sum = 1
2018 14:44:40.025999 10, 0x0, sum = 2
2019 14:44:40.026052 11, 0x0, sum = 3
2020 14:44:40.026105 12, 0x0, sum = 4
2021 14:44:40.026158 best_step = 10
2022 14:44:40.026210
2023 14:44:40.026262 ==
2024 14:44:40.026315 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 14:44:40.026386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 14:44:40.026455 ==
2027 14:44:40.026528 RX Vref Scan: 0
2028 14:44:40.026584
2029 14:44:40.026637 RX Vref 0 -> 0, step: 1
2030 14:44:40.026689
2031 14:44:40.026741 RX Delay -95 -> 252, step: 8
2032 14:44:40.026794 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2033 14:44:40.026847 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2034 14:44:40.026899 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2035 14:44:40.026952 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2036 14:44:40.027004 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2037 14:44:40.027057 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2038 14:44:40.027109 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2039 14:44:40.027162 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2040 14:44:40.027215 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2041 14:44:40.027267 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2042 14:44:40.027319 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2043 14:44:40.027371 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2044 14:44:40.027431 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2045 14:44:40.027484 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2046 14:44:40.027537 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2047 14:44:40.027590 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2048 14:44:40.027642 ==
2049 14:44:40.027694 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 14:44:40.027747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 14:44:40.027800 ==
2052 14:44:40.027855 DQS Delay:
2053 14:44:40.027910 DQS0 = 0, DQS1 = 0
2054 14:44:40.027965 DQM Delay:
2055 14:44:40.028018 DQM0 = 92, DQM1 = 83
2056 14:44:40.028073 DQ Delay:
2057 14:44:40.028127 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2058 14:44:40.028182 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2059 14:44:40.028236 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2060 14:44:40.028290 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2061 14:44:40.028345
2062 14:44:40.028399
2063 14:44:40.028453 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2064 14:44:40.028508 CH1 RK1: MR19=606, MR18=3B10
2065 14:44:40.028591 CH1_RK1: MR19=0x606, MR18=0x3B10, DQSOSC=394, MR23=63, INC=95, DEC=63
2066 14:44:40.028663 [RxdqsGatingPostProcess] freq 800
2067 14:44:40.028717 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2068 14:44:40.028772 Pre-setting of DQS Precalculation
2069 14:44:40.028827 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2070 14:44:40.028883 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2071 14:44:40.028938 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2072 14:44:40.028993
2073 14:44:40.029048
2074 14:44:40.029102 [Calibration Summary] 1600 Mbps
2075 14:44:40.029157 CH 0, Rank 0
2076 14:44:40.029211 SW Impedance : PASS
2077 14:44:40.029266 DUTY Scan : NO K
2078 14:44:40.029321 ZQ Calibration : PASS
2079 14:44:40.029393 Jitter Meter : NO K
2080 14:44:40.029461 CBT Training : PASS
2081 14:44:40.029516 Write leveling : PASS
2082 14:44:40.029601 RX DQS gating : PASS
2083 14:44:40.029656 RX DQ/DQS(RDDQC) : PASS
2084 14:44:40.029709 TX DQ/DQS : PASS
2085 14:44:40.029764 RX DATLAT : PASS
2086 14:44:40.029818 RX DQ/DQS(Engine): PASS
2087 14:44:40.029873 TX OE : NO K
2088 14:44:40.029928 All Pass.
2089 14:44:40.029982
2090 14:44:40.030036 CH 0, Rank 1
2091 14:44:40.030090 SW Impedance : PASS
2092 14:44:40.030176 DUTY Scan : NO K
2093 14:44:40.030230 ZQ Calibration : PASS
2094 14:44:40.030284 Jitter Meter : NO K
2095 14:44:40.030339 CBT Training : PASS
2096 14:44:40.030393 Write leveling : PASS
2097 14:44:40.030448 RX DQS gating : PASS
2098 14:44:40.030502 RX DQ/DQS(RDDQC) : PASS
2099 14:44:40.030556 TX DQ/DQS : PASS
2100 14:44:40.030610 RX DATLAT : PASS
2101 14:44:40.030665 RX DQ/DQS(Engine): PASS
2102 14:44:40.030719 TX OE : NO K
2103 14:44:40.030774 All Pass.
2104 14:44:40.030828
2105 14:44:40.030882 CH 1, Rank 0
2106 14:44:40.030936 SW Impedance : PASS
2107 14:44:40.030991 DUTY Scan : NO K
2108 14:44:40.031045 ZQ Calibration : PASS
2109 14:44:40.031099 Jitter Meter : NO K
2110 14:44:40.031152 CBT Training : PASS
2111 14:44:40.031207 Write leveling : PASS
2112 14:44:40.031262 RX DQS gating : PASS
2113 14:44:40.031316 RX DQ/DQS(RDDQC) : PASS
2114 14:44:40.031387 TX DQ/DQS : PASS
2115 14:44:40.031459 RX DATLAT : PASS
2116 14:44:40.031514 RX DQ/DQS(Engine): PASS
2117 14:44:40.031568 TX OE : NO K
2118 14:44:40.031623 All Pass.
2119 14:44:40.031677
2120 14:44:40.031731 CH 1, Rank 1
2121 14:44:40.031786 SW Impedance : PASS
2122 14:44:40.031840 DUTY Scan : NO K
2123 14:44:40.031894 ZQ Calibration : PASS
2124 14:44:40.032147 Jitter Meter : NO K
2125 14:44:40.032209 CBT Training : PASS
2126 14:44:40.032265 Write leveling : PASS
2127 14:44:40.032320 RX DQS gating : PASS
2128 14:44:40.032392 RX DQ/DQS(RDDQC) : PASS
2129 14:44:40.032448 TX DQ/DQS : PASS
2130 14:44:40.032504 RX DATLAT : PASS
2131 14:44:40.032566 RX DQ/DQS(Engine): PASS
2132 14:44:40.032637 TX OE : NO K
2133 14:44:40.032692 All Pass.
2134 14:44:40.032747
2135 14:44:40.032801 DramC Write-DBI off
2136 14:44:40.032856 PER_BANK_REFRESH: Hybrid Mode
2137 14:44:40.032911 TX_TRACKING: ON
2138 14:44:40.032965 [GetDramInforAfterCalByMRR] Vendor 6.
2139 14:44:40.033053 [GetDramInforAfterCalByMRR] Revision 606.
2140 14:44:40.033107 [GetDramInforAfterCalByMRR] Revision 2 0.
2141 14:44:40.033162 MR0 0x3b3b
2142 14:44:40.033217 MR8 0x5151
2143 14:44:40.033285 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2144 14:44:40.033375
2145 14:44:40.033439 MR0 0x3b3b
2146 14:44:40.033526 MR8 0x5151
2147 14:44:40.033609 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 14:44:40.033665
2149 14:44:40.033720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2150 14:44:40.033777 [FAST_K] Save calibration result to emmc
2151 14:44:40.033832 [FAST_K] Save calibration result to emmc
2152 14:44:40.033887 dram_init: config_dvfs: 1
2153 14:44:40.033942 dramc_set_vcore_voltage set vcore to 662500
2154 14:44:40.033996 Read voltage for 1200, 2
2155 14:44:40.034052 Vio18 = 0
2156 14:44:40.034107 Vcore = 662500
2157 14:44:40.034161 Vdram = 0
2158 14:44:40.034215 Vddq = 0
2159 14:44:40.034269 Vmddr = 0
2160 14:44:40.034324 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2161 14:44:40.034379 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2162 14:44:40.034435 MEM_TYPE=3, freq_sel=15
2163 14:44:40.034488 sv_algorithm_assistance_LP4_1600
2164 14:44:40.034543 ============ PULL DRAM RESETB DOWN ============
2165 14:44:40.034597 ========== PULL DRAM RESETB DOWN end =========
2166 14:44:40.034651 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 14:44:40.034705 ===================================
2168 14:44:40.034760 LPDDR4 DRAM CONFIGURATION
2169 14:44:40.034813 ===================================
2170 14:44:40.034867 EX_ROW_EN[0] = 0x0
2171 14:44:40.034921 EX_ROW_EN[1] = 0x0
2172 14:44:40.034974 LP4Y_EN = 0x0
2173 14:44:40.035029 WORK_FSP = 0x0
2174 14:44:40.035083 WL = 0x4
2175 14:44:40.035138 RL = 0x4
2176 14:44:40.035192 BL = 0x2
2177 14:44:40.035247 RPST = 0x0
2178 14:44:40.035302 RD_PRE = 0x0
2179 14:44:40.035373 WR_PRE = 0x1
2180 14:44:40.035443 WR_PST = 0x0
2181 14:44:40.035497 DBI_WR = 0x0
2182 14:44:40.035551 DBI_RD = 0x0
2183 14:44:40.035622 OTF = 0x1
2184 14:44:40.035693 ===================================
2185 14:44:40.035748 ===================================
2186 14:44:40.035802 ANA top config
2187 14:44:40.035856 ===================================
2188 14:44:40.035911 DLL_ASYNC_EN = 0
2189 14:44:40.035965 ALL_SLAVE_EN = 0
2190 14:44:40.036019 NEW_RANK_MODE = 1
2191 14:44:40.036074 DLL_IDLE_MODE = 1
2192 14:44:40.036128 LP45_APHY_COMB_EN = 1
2193 14:44:40.036183 TX_ODT_DIS = 1
2194 14:44:40.036237 NEW_8X_MODE = 1
2195 14:44:40.036292 ===================================
2196 14:44:40.036347 ===================================
2197 14:44:40.036401 data_rate = 2400
2198 14:44:40.036456 CKR = 1
2199 14:44:40.036510 DQ_P2S_RATIO = 8
2200 14:44:40.036589 ===================================
2201 14:44:40.036661 CA_P2S_RATIO = 8
2202 14:44:40.036747 DQ_CA_OPEN = 0
2203 14:44:40.036801 DQ_SEMI_OPEN = 0
2204 14:44:40.036855 CA_SEMI_OPEN = 0
2205 14:44:40.036909 CA_FULL_RATE = 0
2206 14:44:40.036964 DQ_CKDIV4_EN = 0
2207 14:44:40.037019 CA_CKDIV4_EN = 0
2208 14:44:40.037073 CA_PREDIV_EN = 0
2209 14:44:40.037127 PH8_DLY = 17
2210 14:44:40.037182 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2211 14:44:40.037236 DQ_AAMCK_DIV = 4
2212 14:44:40.037291 CA_AAMCK_DIV = 4
2213 14:44:40.037372 CA_ADMCK_DIV = 4
2214 14:44:40.037443 DQ_TRACK_CA_EN = 0
2215 14:44:40.037497 CA_PICK = 1200
2216 14:44:40.037552 CA_MCKIO = 1200
2217 14:44:40.037606 MCKIO_SEMI = 0
2218 14:44:40.037661 PLL_FREQ = 2366
2219 14:44:40.037715 DQ_UI_PI_RATIO = 32
2220 14:44:40.037769 CA_UI_PI_RATIO = 0
2221 14:44:40.037823 ===================================
2222 14:44:40.037878 ===================================
2223 14:44:40.037933 memory_type:LPDDR4
2224 14:44:40.037987 GP_NUM : 10
2225 14:44:40.038042 SRAM_EN : 1
2226 14:44:40.038096 MD32_EN : 0
2227 14:44:40.038151 ===================================
2228 14:44:40.038205 [ANA_INIT] >>>>>>>>>>>>>>
2229 14:44:40.038261 <<<<<< [CONFIGURE PHASE]: ANA_TX
2230 14:44:40.038316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2231 14:44:40.038370 ===================================
2232 14:44:40.038425 data_rate = 2400,PCW = 0X5b00
2233 14:44:40.038479 ===================================
2234 14:44:40.038534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2235 14:44:40.038589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 14:44:40.038644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 14:44:40.038698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2238 14:44:40.038753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2239 14:44:40.038807 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2240 14:44:40.038862 [ANA_INIT] flow start
2241 14:44:40.038941 [ANA_INIT] PLL >>>>>>>>
2242 14:44:40.039010 [ANA_INIT] PLL <<<<<<<<
2243 14:44:40.039064 [ANA_INIT] MIDPI >>>>>>>>
2244 14:44:40.039118 [ANA_INIT] MIDPI <<<<<<<<
2245 14:44:40.039171 [ANA_INIT] DLL >>>>>>>>
2246 14:44:40.039226 [ANA_INIT] DLL <<<<<<<<
2247 14:44:40.039279 [ANA_INIT] flow end
2248 14:44:40.039334 ============ LP4 DIFF to SE enter ============
2249 14:44:40.039389 ============ LP4 DIFF to SE exit ============
2250 14:44:40.039444 [ANA_INIT] <<<<<<<<<<<<<
2251 14:44:40.039498 [Flow] Enable top DCM control >>>>>
2252 14:44:40.039553 [Flow] Enable top DCM control <<<<<
2253 14:44:40.039607 Enable DLL master slave shuffle
2254 14:44:40.039704 ==============================================================
2255 14:44:40.039758 Gating Mode config
2256 14:44:40.040032 ==============================================================
2257 14:44:40.040099 Config description:
2258 14:44:40.040172 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2259 14:44:40.040229 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2260 14:44:40.040285 SELPH_MODE 0: By rank 1: By Phase
2261 14:44:40.040340 ==============================================================
2262 14:44:40.040396 GAT_TRACK_EN = 1
2263 14:44:40.040450 RX_GATING_MODE = 2
2264 14:44:40.040504 RX_GATING_TRACK_MODE = 2
2265 14:44:40.040582 SELPH_MODE = 1
2266 14:44:40.040652 PICG_EARLY_EN = 1
2267 14:44:40.040707 VALID_LAT_VALUE = 1
2268 14:44:40.040762 ==============================================================
2269 14:44:40.040817 Enter into Gating configuration >>>>
2270 14:44:40.040871 Exit from Gating configuration <<<<
2271 14:44:40.040926 Enter into DVFS_PRE_config >>>>>
2272 14:44:40.040981 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2273 14:44:40.041037 Exit from DVFS_PRE_config <<<<<
2274 14:44:40.041091 Enter into PICG configuration >>>>
2275 14:44:40.041159 Exit from PICG configuration <<<<
2276 14:44:40.041219 [RX_INPUT] configuration >>>>>
2277 14:44:40.041273 [RX_INPUT] configuration <<<<<
2278 14:44:40.041327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2279 14:44:40.041422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2280 14:44:40.041520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 14:44:40.041601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 14:44:40.041703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 14:44:40.041758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 14:44:40.041811 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2285 14:44:40.041865 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2286 14:44:40.041918 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2287 14:44:40.041973 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2288 14:44:40.042026 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2289 14:44:40.042097 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 14:44:40.042167 ===================================
2291 14:44:40.042222 LPDDR4 DRAM CONFIGURATION
2292 14:44:40.042277 ===================================
2293 14:44:40.042332 EX_ROW_EN[0] = 0x0
2294 14:44:40.042386 EX_ROW_EN[1] = 0x0
2295 14:44:40.042441 LP4Y_EN = 0x0
2296 14:44:40.042495 WORK_FSP = 0x0
2297 14:44:40.042549 WL = 0x4
2298 14:44:40.042603 RL = 0x4
2299 14:44:40.042658 BL = 0x2
2300 14:44:40.042712 RPST = 0x0
2301 14:44:40.042766 RD_PRE = 0x0
2302 14:44:40.042820 WR_PRE = 0x1
2303 14:44:40.042874 WR_PST = 0x0
2304 14:44:40.042928 DBI_WR = 0x0
2305 14:44:40.042982 DBI_RD = 0x0
2306 14:44:40.043036 OTF = 0x1
2307 14:44:40.043090 ===================================
2308 14:44:40.043144 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2309 14:44:40.043199 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2310 14:44:40.043253 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 14:44:40.043307 ===================================
2312 14:44:40.043400 LPDDR4 DRAM CONFIGURATION
2313 14:44:40.043454 ===================================
2314 14:44:40.043508 EX_ROW_EN[0] = 0x10
2315 14:44:40.043562 EX_ROW_EN[1] = 0x0
2316 14:44:40.043616 LP4Y_EN = 0x0
2317 14:44:40.043670 WORK_FSP = 0x0
2318 14:44:40.043724 WL = 0x4
2319 14:44:40.043778 RL = 0x4
2320 14:44:40.043832 BL = 0x2
2321 14:44:40.043886 RPST = 0x0
2322 14:44:40.043940 RD_PRE = 0x0
2323 14:44:40.043994 WR_PRE = 0x1
2324 14:44:40.044047 WR_PST = 0x0
2325 14:44:40.044102 DBI_WR = 0x0
2326 14:44:40.044156 DBI_RD = 0x0
2327 14:44:40.044210 OTF = 0x1
2328 14:44:40.044265 ===================================
2329 14:44:40.044320 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2330 14:44:40.044375 ==
2331 14:44:40.044428 Dram Type= 6, Freq= 0, CH_0, rank 0
2332 14:44:40.044481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2333 14:44:40.044535 ==
2334 14:44:40.044628 [Duty_Offset_Calibration]
2335 14:44:40.044680 B0:2 B1:0 CA:1
2336 14:44:40.044733
2337 14:44:40.044786 [DutyScan_Calibration_Flow] k_type=0
2338 14:44:40.044838
2339 14:44:40.044890 ==CLK 0==
2340 14:44:40.044943 Final CLK duty delay cell = -4
2341 14:44:40.044996 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2342 14:44:40.045048 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2343 14:44:40.045100 [-4] AVG Duty = 4953%(X100)
2344 14:44:40.045153
2345 14:44:40.045222 CH0 CLK Duty spec in!! Max-Min= 156%
2346 14:44:40.045322 [DutyScan_Calibration_Flow] ====Done====
2347 14:44:40.045392
2348 14:44:40.045445 [DutyScan_Calibration_Flow] k_type=1
2349 14:44:40.045498
2350 14:44:40.045551 ==DQS 0 ==
2351 14:44:40.045605 Final DQS duty delay cell = 0
2352 14:44:40.045672 [0] MAX Duty = 5187%(X100), DQS PI = 30
2353 14:44:40.045725 [0] MIN Duty = 4938%(X100), DQS PI = 0
2354 14:44:40.045776 [0] AVG Duty = 5062%(X100)
2355 14:44:40.045828
2356 14:44:40.045880 ==DQS 1 ==
2357 14:44:40.045932 Final DQS duty delay cell = -4
2358 14:44:40.045984 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2359 14:44:40.046036 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2360 14:44:40.046089 [-4] AVG Duty = 5015%(X100)
2361 14:44:40.046141
2362 14:44:40.046193 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2363 14:44:40.046245
2364 14:44:40.046297 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2365 14:44:40.046349 [DutyScan_Calibration_Flow] ====Done====
2366 14:44:40.046402
2367 14:44:40.046454 [DutyScan_Calibration_Flow] k_type=3
2368 14:44:40.046506
2369 14:44:40.046558 ==DQM 0 ==
2370 14:44:40.046611 Final DQM duty delay cell = 0
2371 14:44:40.046664 [0] MAX Duty = 5062%(X100), DQS PI = 24
2372 14:44:40.046716 [0] MIN Duty = 4813%(X100), DQS PI = 0
2373 14:44:40.046769 [0] AVG Duty = 4937%(X100)
2374 14:44:40.046822
2375 14:44:40.046875 ==DQM 1 ==
2376 14:44:40.046927 Final DQM duty delay cell = 0
2377 14:44:40.046980 [0] MAX Duty = 5187%(X100), DQS PI = 48
2378 14:44:40.047032 [0] MIN Duty = 5000%(X100), DQS PI = 12
2379 14:44:40.047084 [0] AVG Duty = 5093%(X100)
2380 14:44:40.047135
2381 14:44:40.047419 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2382 14:44:40.047510
2383 14:44:40.047564 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2384 14:44:40.047618 [DutyScan_Calibration_Flow] ====Done====
2385 14:44:40.047671
2386 14:44:40.047724 [DutyScan_Calibration_Flow] k_type=2
2387 14:44:40.047775
2388 14:44:40.047827 ==DQ 0 ==
2389 14:44:40.047880 Final DQ duty delay cell = -4
2390 14:44:40.047933 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2391 14:44:40.047986 [-4] MIN Duty = 4844%(X100), DQS PI = 16
2392 14:44:40.048039 [-4] AVG Duty = 4937%(X100)
2393 14:44:40.048092
2394 14:44:40.048143 ==DQ 1 ==
2395 14:44:40.048196 Final DQ duty delay cell = 4
2396 14:44:40.048248 [4] MAX Duty = 5093%(X100), DQS PI = 6
2397 14:44:40.048300 [4] MIN Duty = 5031%(X100), DQS PI = 0
2398 14:44:40.048353 [4] AVG Duty = 5062%(X100)
2399 14:44:40.048405
2400 14:44:40.048457 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2401 14:44:40.048510
2402 14:44:40.048588 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2403 14:44:40.048688 [DutyScan_Calibration_Flow] ====Done====
2404 14:44:40.048741 ==
2405 14:44:40.048793 Dram Type= 6, Freq= 0, CH_1, rank 0
2406 14:44:40.048863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2407 14:44:40.048932 ==
2408 14:44:40.048984 [Duty_Offset_Calibration]
2409 14:44:40.049035 B0:0 B1:-1 CA:2
2410 14:44:40.049087
2411 14:44:40.049139 [DutyScan_Calibration_Flow] k_type=0
2412 14:44:40.049192
2413 14:44:40.049244 ==CLK 0==
2414 14:44:40.049296 Final CLK duty delay cell = 0
2415 14:44:40.049349 [0] MAX Duty = 5156%(X100), DQS PI = 16
2416 14:44:40.049419 [0] MIN Duty = 4938%(X100), DQS PI = 44
2417 14:44:40.049519 [0] AVG Duty = 5047%(X100)
2418 14:44:40.049601
2419 14:44:40.049653 CH1 CLK Duty spec in!! Max-Min= 218%
2420 14:44:40.049706 [DutyScan_Calibration_Flow] ====Done====
2421 14:44:40.049758
2422 14:44:40.049810 [DutyScan_Calibration_Flow] k_type=1
2423 14:44:40.049862
2424 14:44:40.049915 ==DQS 0 ==
2425 14:44:40.049967 Final DQS duty delay cell = 0
2426 14:44:40.050020 [0] MAX Duty = 5093%(X100), DQS PI = 24
2427 14:44:40.050072 [0] MIN Duty = 4969%(X100), DQS PI = 0
2428 14:44:40.050124 [0] AVG Duty = 5031%(X100)
2429 14:44:40.050176
2430 14:44:40.050228 ==DQS 1 ==
2431 14:44:40.050280 Final DQS duty delay cell = 0
2432 14:44:40.050333 [0] MAX Duty = 5156%(X100), DQS PI = 0
2433 14:44:40.050386 [0] MIN Duty = 4844%(X100), DQS PI = 36
2434 14:44:40.050438 [0] AVG Duty = 5000%(X100)
2435 14:44:40.050490
2436 14:44:40.050542 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2437 14:44:40.050595
2438 14:44:40.050647 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2439 14:44:40.050700 [DutyScan_Calibration_Flow] ====Done====
2440 14:44:40.050752
2441 14:44:40.050804 [DutyScan_Calibration_Flow] k_type=3
2442 14:44:40.050856
2443 14:44:40.050908 ==DQM 0 ==
2444 14:44:40.050960 Final DQM duty delay cell = 4
2445 14:44:40.051046 [4] MAX Duty = 5093%(X100), DQS PI = 22
2446 14:44:40.051099 [4] MIN Duty = 4907%(X100), DQS PI = 44
2447 14:44:40.051152 [4] AVG Duty = 5000%(X100)
2448 14:44:40.051204
2449 14:44:40.051255 ==DQM 1 ==
2450 14:44:40.051331 Final DQM duty delay cell = -4
2451 14:44:40.051419 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2452 14:44:40.051472 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2453 14:44:40.051525 [-4] AVG Duty = 4875%(X100)
2454 14:44:40.051577
2455 14:44:40.051629 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2456 14:44:40.051681
2457 14:44:40.051734 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2458 14:44:40.051787 [DutyScan_Calibration_Flow] ====Done====
2459 14:44:40.051840
2460 14:44:40.051908 [DutyScan_Calibration_Flow] k_type=2
2461 14:44:40.051975
2462 14:44:40.052028 ==DQ 0 ==
2463 14:44:40.052095 Final DQ duty delay cell = 0
2464 14:44:40.052224 [0] MAX Duty = 5062%(X100), DQS PI = 20
2465 14:44:40.052306 [0] MIN Duty = 4938%(X100), DQS PI = 30
2466 14:44:40.052360 [0] AVG Duty = 5000%(X100)
2467 14:44:40.052413
2468 14:44:40.052466 ==DQ 1 ==
2469 14:44:40.052519 Final DQ duty delay cell = 0
2470 14:44:40.052612 [0] MAX Duty = 5031%(X100), DQS PI = 2
2471 14:44:40.052665 [0] MIN Duty = 4813%(X100), DQS PI = 34
2472 14:44:40.052718 [0] AVG Duty = 4922%(X100)
2473 14:44:40.052785
2474 14:44:40.052884 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2475 14:44:40.052965
2476 14:44:40.053017 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2477 14:44:40.053069 [DutyScan_Calibration_Flow] ====Done====
2478 14:44:40.053122 nWR fixed to 30
2479 14:44:40.053175 [ModeRegInit_LP4] CH0 RK0
2480 14:44:40.053227 [ModeRegInit_LP4] CH0 RK1
2481 14:44:40.053280 [ModeRegInit_LP4] CH1 RK0
2482 14:44:40.053332 [ModeRegInit_LP4] CH1 RK1
2483 14:44:40.053399 match AC timing 7
2484 14:44:40.053467 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2485 14:44:40.053520 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2486 14:44:40.053573 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2487 14:44:40.053641 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2488 14:44:40.053709 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2489 14:44:40.053762 ==
2490 14:44:40.053830 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 14:44:40.053897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 14:44:40.053950 ==
2493 14:44:40.054002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 14:44:40.054070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2495 14:44:40.054124 [CA 0] Center 38 (8~69) winsize 62
2496 14:44:40.054178 [CA 1] Center 38 (8~69) winsize 62
2497 14:44:40.054231 [CA 2] Center 35 (5~66) winsize 62
2498 14:44:40.054284 [CA 3] Center 35 (4~66) winsize 63
2499 14:44:40.054339 [CA 4] Center 34 (4~65) winsize 62
2500 14:44:40.054393 [CA 5] Center 33 (3~64) winsize 62
2501 14:44:40.054447
2502 14:44:40.054500 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 14:44:40.054553
2504 14:44:40.054607 [CATrainingPosCal] consider 1 rank data
2505 14:44:40.054675 u2DelayCellTimex100 = 270/100 ps
2506 14:44:40.054744 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2507 14:44:40.054797 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2508 14:44:40.054851 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 14:44:40.054904 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2510 14:44:40.054958 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 14:44:40.055011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2512 14:44:40.055065
2513 14:44:40.055118 CA PerBit enable=1, Macro0, CA PI delay=33
2514 14:44:40.055171
2515 14:44:40.055225 [CBTSetCACLKResult] CA Dly = 33
2516 14:44:40.055278 CS Dly: 6 (0~37)
2517 14:44:40.055332 ==
2518 14:44:40.055416 Dram Type= 6, Freq= 0, CH_0, rank 1
2519 14:44:40.055470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 14:44:40.055538 ==
2521 14:44:40.055590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 14:44:40.055644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 14:44:40.055696 [CA 0] Center 39 (8~70) winsize 63
2524 14:44:40.055748 [CA 1] Center 38 (8~69) winsize 62
2525 14:44:40.055801 [CA 2] Center 35 (5~66) winsize 62
2526 14:44:40.056061 [CA 3] Center 35 (5~66) winsize 62
2527 14:44:40.056123 [CA 4] Center 34 (4~65) winsize 62
2528 14:44:40.056179 [CA 5] Center 34 (4~64) winsize 61
2529 14:44:40.056247
2530 14:44:40.056300 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2531 14:44:40.056353
2532 14:44:40.056421 [CATrainingPosCal] consider 2 rank data
2533 14:44:40.056475 u2DelayCellTimex100 = 270/100 ps
2534 14:44:40.056529 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2535 14:44:40.056607 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2536 14:44:40.056660 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2537 14:44:40.056713 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2538 14:44:40.056767 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2539 14:44:40.056820 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2540 14:44:40.056873
2541 14:44:40.056925 CA PerBit enable=1, Macro0, CA PI delay=34
2542 14:44:40.056978
2543 14:44:40.057030 [CBTSetCACLKResult] CA Dly = 34
2544 14:44:40.057082 CS Dly: 7 (0~39)
2545 14:44:40.057134
2546 14:44:40.057186 ----->DramcWriteLeveling(PI) begin...
2547 14:44:40.057240 ==
2548 14:44:40.057293 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 14:44:40.057345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 14:44:40.057398 ==
2551 14:44:40.057450 Write leveling (Byte 0): 34 => 34
2552 14:44:40.057503 Write leveling (Byte 1): 32 => 32
2553 14:44:40.057555 DramcWriteLeveling(PI) end<-----
2554 14:44:40.057607
2555 14:44:40.057659 ==
2556 14:44:40.057711 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 14:44:40.057763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 14:44:40.057816 ==
2559 14:44:40.057868 [Gating] SW mode calibration
2560 14:44:40.057920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2561 14:44:40.057973 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2562 14:44:40.058025 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2563 14:44:40.058078 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2564 14:44:40.058131 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 14:44:40.058183 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 14:44:40.058236 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 14:44:40.058288 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 14:44:40.058340 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2569 14:44:40.058393 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2570 14:44:40.058445 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2571 14:44:40.058497 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 14:44:40.058550 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 14:44:40.058617 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 14:44:40.058671 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 14:44:40.058723 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 14:44:40.058777 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2577 14:44:40.058830 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2578 14:44:40.058882 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2579 14:44:40.058934 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 14:44:40.058987 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 14:44:40.059040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 14:44:40.059093 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 14:44:40.059145 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 14:44:40.059197 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2585 14:44:40.059249 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 14:44:40.059301 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 14:44:40.059354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 14:44:40.059406 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 14:44:40.059459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 14:44:40.059511 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 14:44:40.059564 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 14:44:40.059616 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 14:44:40.059669 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 14:44:40.059721 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 14:44:40.059774 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 14:44:40.059827 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 14:44:40.059879 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 14:44:40.059932 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 14:44:40.060002 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 14:44:40.060070 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2601 14:44:40.060123 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2602 14:44:40.060175 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 14:44:40.060228 Total UI for P1: 0, mck2ui 16
2604 14:44:40.060281 best dqsien dly found for B0: ( 1, 3, 26)
2605 14:44:40.060333 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 14:44:40.060386 Total UI for P1: 0, mck2ui 16
2607 14:44:40.060438 best dqsien dly found for B1: ( 1, 4, 0)
2608 14:44:40.060491 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2609 14:44:40.060543 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2610 14:44:40.060634
2611 14:44:40.060686 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2612 14:44:40.060738 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2613 14:44:40.060790 [Gating] SW calibration Done
2614 14:44:40.060842 ==
2615 14:44:40.060895 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 14:44:40.060947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 14:44:40.061000 ==
2618 14:44:40.061052 RX Vref Scan: 0
2619 14:44:40.061104
2620 14:44:40.061156 RX Vref 0 -> 0, step: 1
2621 14:44:40.061208
2622 14:44:40.061260 RX Delay -40 -> 252, step: 8
2623 14:44:40.061312 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2624 14:44:40.061364 iDelay=208, Bit 1, Center 123 (48 ~ 199) 152
2625 14:44:40.061416 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2626 14:44:40.061469 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2627 14:44:40.061521 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2628 14:44:40.061574 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2629 14:44:40.061625 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2630 14:44:40.061678 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2631 14:44:40.061931 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2632 14:44:40.061991 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2633 14:44:40.062046 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2634 14:44:40.062100 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2635 14:44:40.062185 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2636 14:44:40.062237 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2637 14:44:40.062290 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2638 14:44:40.062342 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2639 14:44:40.062395 ==
2640 14:44:40.062447 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 14:44:40.062500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 14:44:40.062553 ==
2643 14:44:40.062605 DQS Delay:
2644 14:44:40.062658 DQS0 = 0, DQS1 = 0
2645 14:44:40.062710 DQM Delay:
2646 14:44:40.062762 DQM0 = 123, DQM1 = 110
2647 14:44:40.062814 DQ Delay:
2648 14:44:40.062866 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2649 14:44:40.062919 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2650 14:44:40.062972 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2651 14:44:40.063024 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2652 14:44:40.063077
2653 14:44:40.063129
2654 14:44:40.063180 ==
2655 14:44:40.063251 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 14:44:40.063316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 14:44:40.063370 ==
2658 14:44:40.063423
2659 14:44:40.063497
2660 14:44:40.063564 TX Vref Scan disable
2661 14:44:40.063616 == TX Byte 0 ==
2662 14:44:40.063668 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2663 14:44:40.063722 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2664 14:44:40.063774 == TX Byte 1 ==
2665 14:44:40.063827 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2666 14:44:40.063879 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2667 14:44:40.063931 ==
2668 14:44:40.063984 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 14:44:40.064036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 14:44:40.064088 ==
2671 14:44:40.064141 TX Vref=22, minBit 0, minWin=24, winSum=400
2672 14:44:40.064193 TX Vref=24, minBit 7, minWin=24, winSum=410
2673 14:44:40.064246 TX Vref=26, minBit 0, minWin=25, winSum=415
2674 14:44:40.064298 TX Vref=28, minBit 4, minWin=25, winSum=418
2675 14:44:40.064351 TX Vref=30, minBit 3, minWin=25, winSum=419
2676 14:44:40.064404 TX Vref=32, minBit 1, minWin=25, winSum=416
2677 14:44:40.064457 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 30
2678 14:44:40.064509
2679 14:44:40.064587 Final TX Range 1 Vref 30
2680 14:44:40.064655
2681 14:44:40.064707 ==
2682 14:44:40.064759 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 14:44:40.064812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 14:44:40.064864 ==
2685 14:44:40.064916
2686 14:44:40.064968
2687 14:44:40.065020 TX Vref Scan disable
2688 14:44:40.065072 == TX Byte 0 ==
2689 14:44:40.065124 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2690 14:44:40.065176 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2691 14:44:40.065229 == TX Byte 1 ==
2692 14:44:40.065281 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2693 14:44:40.065334 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2694 14:44:40.065387
2695 14:44:40.065438 [DATLAT]
2696 14:44:40.065490 Freq=1200, CH0 RK0
2697 14:44:40.065559
2698 14:44:40.065625 DATLAT Default: 0xd
2699 14:44:40.065677 0, 0xFFFF, sum = 0
2700 14:44:40.065731 1, 0xFFFF, sum = 0
2701 14:44:40.065784 2, 0xFFFF, sum = 0
2702 14:44:40.065837 3, 0xFFFF, sum = 0
2703 14:44:40.065890 4, 0xFFFF, sum = 0
2704 14:44:40.065942 5, 0xFFFF, sum = 0
2705 14:44:40.065995 6, 0xFFFF, sum = 0
2706 14:44:40.066048 7, 0xFFFF, sum = 0
2707 14:44:40.066101 8, 0xFFFF, sum = 0
2708 14:44:40.066154 9, 0xFFFF, sum = 0
2709 14:44:40.066207 10, 0xFFFF, sum = 0
2710 14:44:40.066259 11, 0xFFFF, sum = 0
2711 14:44:40.066313 12, 0x0, sum = 1
2712 14:44:40.066366 13, 0x0, sum = 2
2713 14:44:40.066418 14, 0x0, sum = 3
2714 14:44:40.066471 15, 0x0, sum = 4
2715 14:44:40.066524 best_step = 13
2716 14:44:40.066576
2717 14:44:40.066628 ==
2718 14:44:40.066680 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 14:44:40.066732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 14:44:40.066785 ==
2721 14:44:40.066837 RX Vref Scan: 1
2722 14:44:40.066889
2723 14:44:40.066941 Set Vref Range= 32 -> 127
2724 14:44:40.066993
2725 14:44:40.067044 RX Vref 32 -> 127, step: 1
2726 14:44:40.067096
2727 14:44:40.067148 RX Delay -13 -> 252, step: 4
2728 14:44:40.067199
2729 14:44:40.067250 Set Vref, RX VrefLevel [Byte0]: 32
2730 14:44:40.067303 [Byte1]: 32
2731 14:44:40.067355
2732 14:44:40.067406 Set Vref, RX VrefLevel [Byte0]: 33
2733 14:44:40.067458 [Byte1]: 33
2734 14:44:40.067510
2735 14:44:40.067562 Set Vref, RX VrefLevel [Byte0]: 34
2736 14:44:40.067615 [Byte1]: 34
2737 14:44:40.067667
2738 14:44:40.067719 Set Vref, RX VrefLevel [Byte0]: 35
2739 14:44:40.067771 [Byte1]: 35
2740 14:44:40.067823
2741 14:44:40.067875 Set Vref, RX VrefLevel [Byte0]: 36
2742 14:44:40.067927 [Byte1]: 36
2743 14:44:40.067979
2744 14:44:40.068031 Set Vref, RX VrefLevel [Byte0]: 37
2745 14:44:40.068083 [Byte1]: 37
2746 14:44:40.068135
2747 14:44:40.068187 Set Vref, RX VrefLevel [Byte0]: 38
2748 14:44:40.068239 [Byte1]: 38
2749 14:44:40.068291
2750 14:44:40.068342 Set Vref, RX VrefLevel [Byte0]: 39
2751 14:44:40.068394 [Byte1]: 39
2752 14:44:40.068446
2753 14:44:40.068498 Set Vref, RX VrefLevel [Byte0]: 40
2754 14:44:40.068553 [Byte1]: 40
2755 14:44:40.068669
2756 14:44:40.068722 Set Vref, RX VrefLevel [Byte0]: 41
2757 14:44:40.068773 [Byte1]: 41
2758 14:44:40.068825
2759 14:44:40.068877 Set Vref, RX VrefLevel [Byte0]: 42
2760 14:44:40.068929 [Byte1]: 42
2761 14:44:40.068981
2762 14:44:40.069034 Set Vref, RX VrefLevel [Byte0]: 43
2763 14:44:40.069085 [Byte1]: 43
2764 14:44:40.069137
2765 14:44:40.069189 Set Vref, RX VrefLevel [Byte0]: 44
2766 14:44:40.069241 [Byte1]: 44
2767 14:44:40.069292
2768 14:44:40.069344 Set Vref, RX VrefLevel [Byte0]: 45
2769 14:44:40.069396 [Byte1]: 45
2770 14:44:40.069448
2771 14:44:40.069500 Set Vref, RX VrefLevel [Byte0]: 46
2772 14:44:40.069552 [Byte1]: 46
2773 14:44:40.069604
2774 14:44:40.069656 Set Vref, RX VrefLevel [Byte0]: 47
2775 14:44:40.069708 [Byte1]: 47
2776 14:44:40.069760
2777 14:44:40.069811 Set Vref, RX VrefLevel [Byte0]: 48
2778 14:44:40.069864 [Byte1]: 48
2779 14:44:40.069916
2780 14:44:40.069968 Set Vref, RX VrefLevel [Byte0]: 49
2781 14:44:40.070020 [Byte1]: 49
2782 14:44:40.070073
2783 14:44:40.070124 Set Vref, RX VrefLevel [Byte0]: 50
2784 14:44:40.070176 [Byte1]: 50
2785 14:44:40.070228
2786 14:44:40.070279 Set Vref, RX VrefLevel [Byte0]: 51
2787 14:44:40.070331 [Byte1]: 51
2788 14:44:40.070383
2789 14:44:40.070435 Set Vref, RX VrefLevel [Byte0]: 52
2790 14:44:40.070486 [Byte1]: 52
2791 14:44:40.070538
2792 14:44:40.070789 Set Vref, RX VrefLevel [Byte0]: 53
2793 14:44:40.070849 [Byte1]: 53
2794 14:44:40.070903
2795 14:44:40.070956 Set Vref, RX VrefLevel [Byte0]: 54
2796 14:44:40.071010 [Byte1]: 54
2797 14:44:40.071063
2798 14:44:40.071115 Set Vref, RX VrefLevel [Byte0]: 55
2799 14:44:40.071168 [Byte1]: 55
2800 14:44:40.071220
2801 14:44:40.071272 Set Vref, RX VrefLevel [Byte0]: 56
2802 14:44:40.071325 [Byte1]: 56
2803 14:44:40.071377
2804 14:44:40.071430 Set Vref, RX VrefLevel [Byte0]: 57
2805 14:44:40.071482 [Byte1]: 57
2806 14:44:40.071534
2807 14:44:40.071585 Set Vref, RX VrefLevel [Byte0]: 58
2808 14:44:40.071638 [Byte1]: 58
2809 14:44:40.071690
2810 14:44:40.071742 Set Vref, RX VrefLevel [Byte0]: 59
2811 14:44:40.071794 [Byte1]: 59
2812 14:44:40.071845
2813 14:44:40.071897 Set Vref, RX VrefLevel [Byte0]: 60
2814 14:44:40.071949 [Byte1]: 60
2815 14:44:40.072001
2816 14:44:40.072053 Set Vref, RX VrefLevel [Byte0]: 61
2817 14:44:40.072105 [Byte1]: 61
2818 14:44:40.072156
2819 14:44:40.072208 Set Vref, RX VrefLevel [Byte0]: 62
2820 14:44:40.072261 [Byte1]: 62
2821 14:44:40.072313
2822 14:44:40.072365 Set Vref, RX VrefLevel [Byte0]: 63
2823 14:44:40.072417 [Byte1]: 63
2824 14:44:40.072469
2825 14:44:40.072521 Set Vref, RX VrefLevel [Byte0]: 64
2826 14:44:40.072658 [Byte1]: 64
2827 14:44:40.072735
2828 14:44:40.072803 Set Vref, RX VrefLevel [Byte0]: 65
2829 14:44:40.072862 [Byte1]: 65
2830 14:44:40.072919
2831 14:44:40.072974 Set Vref, RX VrefLevel [Byte0]: 66
2832 14:44:40.073028 [Byte1]: 66
2833 14:44:40.073082
2834 14:44:40.073135 Set Vref, RX VrefLevel [Byte0]: 67
2835 14:44:40.073187 [Byte1]: 67
2836 14:44:40.073240
2837 14:44:40.073292 Set Vref, RX VrefLevel [Byte0]: 68
2838 14:44:40.073348 [Byte1]: 68
2839 14:44:40.073408
2840 14:44:40.073462 Set Vref, RX VrefLevel [Byte0]: 69
2841 14:44:40.073513 [Byte1]: 69
2842 14:44:40.073566
2843 14:44:40.073617 Final RX Vref Byte 0 = 57 to rank0
2844 14:44:40.073669 Final RX Vref Byte 1 = 49 to rank0
2845 14:44:40.073721 Final RX Vref Byte 0 = 57 to rank1
2846 14:44:40.073772 Final RX Vref Byte 1 = 49 to rank1==
2847 14:44:40.073824 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 14:44:40.073875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 14:44:40.073928 ==
2850 14:44:40.073980 DQS Delay:
2851 14:44:40.074031 DQS0 = 0, DQS1 = 0
2852 14:44:40.074083 DQM Delay:
2853 14:44:40.074144 DQM0 = 122, DQM1 = 109
2854 14:44:40.074200 DQ Delay:
2855 14:44:40.074252 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2856 14:44:40.074304 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2857 14:44:40.074356 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2858 14:44:40.074408 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2859 14:44:40.074459
2860 14:44:40.074510
2861 14:44:40.074562 [DQSOSCAuto] RK0, (LSB)MR18= 0xc08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2862 14:44:40.074617 CH0 RK0: MR19=404, MR18=C08
2863 14:44:40.074669 CH0_RK0: MR19=0x404, MR18=0xC08, DQSOSC=405, MR23=63, INC=39, DEC=26
2864 14:44:40.074720
2865 14:44:40.074771 ----->DramcWriteLeveling(PI) begin...
2866 14:44:40.074824 ==
2867 14:44:40.074886 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 14:44:40.074942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 14:44:40.074994 ==
2870 14:44:40.075046 Write leveling (Byte 0): 33 => 33
2871 14:44:40.075098 Write leveling (Byte 1): 29 => 29
2872 14:44:40.075149 DramcWriteLeveling(PI) end<-----
2873 14:44:40.075200
2874 14:44:40.075252 ==
2875 14:44:40.075303 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 14:44:40.075355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 14:44:40.075406 ==
2878 14:44:40.075457 [Gating] SW mode calibration
2879 14:44:40.075509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 14:44:40.075561 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 14:44:40.075612 0 15 0 | B1->B0 | 302f 3434 | 1 1 | (1 1) (1 1)
2882 14:44:40.075664 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 14:44:40.075716 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 14:44:40.075778 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 14:44:40.075831 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 14:44:40.075884 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 14:44:40.075936 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2888 14:44:40.075987 0 15 28 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 0)
2889 14:44:40.076039 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 14:44:40.076090 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 14:44:40.076142 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 14:44:40.076193 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 14:44:40.076245 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 14:44:40.076296 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 14:44:40.076347 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 14:44:40.076399 1 0 28 | B1->B0 | 3838 4040 | 0 1 | (0 0) (0 0)
2897 14:44:40.076450 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 14:44:40.076528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 14:44:40.076626 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 14:44:40.076680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 14:44:40.076731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 14:44:40.076783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 14:44:40.076835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 14:44:40.076887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2905 14:44:40.076938 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 14:44:40.076990 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 14:44:40.077042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 14:44:40.077093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 14:44:40.077144 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 14:44:40.077196 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 14:44:40.077247 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 14:44:40.077299 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 14:44:40.077554 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 14:44:40.077614 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 14:44:40.077667 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 14:44:40.077720 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 14:44:40.077772 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 14:44:40.077823 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 14:44:40.077876 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 14:44:40.077927 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2921 14:44:40.077985 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2922 14:44:40.078044 Total UI for P1: 0, mck2ui 16
2923 14:44:40.078097 best dqsien dly found for B1: ( 1, 3, 28)
2924 14:44:40.078149 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 14:44:40.078201 Total UI for P1: 0, mck2ui 16
2926 14:44:40.078253 best dqsien dly found for B0: ( 1, 3, 30)
2927 14:44:40.078305 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2928 14:44:40.078358 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2929 14:44:40.078409
2930 14:44:40.078460 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2931 14:44:40.078512 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2932 14:44:40.078565 [Gating] SW calibration Done
2933 14:44:40.078617 ==
2934 14:44:40.078668 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 14:44:40.078722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 14:44:40.078783 ==
2937 14:44:40.078836 RX Vref Scan: 0
2938 14:44:40.078887
2939 14:44:40.078938 RX Vref 0 -> 0, step: 1
2940 14:44:40.078990
2941 14:44:40.079042 RX Delay -40 -> 252, step: 8
2942 14:44:40.079093 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2943 14:44:40.079144 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2944 14:44:40.079196 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2945 14:44:40.079248 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2946 14:44:40.079299 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2947 14:44:40.079350 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2948 14:44:40.079402 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2949 14:44:40.079453 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2950 14:44:40.079516 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2951 14:44:40.079570 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2952 14:44:40.079622 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2953 14:44:40.079673 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2954 14:44:40.079725 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2955 14:44:40.079777 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2956 14:44:40.079829 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2957 14:44:40.079880 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2958 14:44:40.079932 ==
2959 14:44:40.079983 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 14:44:40.080035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 14:44:40.080086 ==
2962 14:44:40.080138 DQS Delay:
2963 14:44:40.080189 DQS0 = 0, DQS1 = 0
2964 14:44:40.080241 DQM Delay:
2965 14:44:40.080292 DQM0 = 120, DQM1 = 108
2966 14:44:40.080344 DQ Delay:
2967 14:44:40.080395 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2968 14:44:40.080447 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2969 14:44:40.080498 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2970 14:44:40.080558 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2971 14:44:40.291037
2972 14:44:40.291215
2973 14:44:40.291324 ==
2974 14:44:40.291424 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 14:44:40.291521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 14:44:40.291618 ==
2977 14:44:40.291713
2978 14:44:40.291808
2979 14:44:40.291877 TX Vref Scan disable
2980 14:44:40.291935 == TX Byte 0 ==
2981 14:44:40.292018 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2982 14:44:40.292108 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2983 14:44:40.292212 == TX Byte 1 ==
2984 14:44:40.292297 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2985 14:44:40.292393 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2986 14:44:40.292481 ==
2987 14:44:40.292583 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 14:44:40.292654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 14:44:40.292709 ==
2990 14:44:40.292798 TX Vref=22, minBit 0, minWin=25, winSum=415
2991 14:44:40.292857 TX Vref=24, minBit 0, minWin=25, winSum=418
2992 14:44:40.292910 TX Vref=26, minBit 1, minWin=25, winSum=421
2993 14:44:40.293010 TX Vref=28, minBit 3, minWin=25, winSum=426
2994 14:44:40.293094 TX Vref=30, minBit 1, minWin=25, winSum=426
2995 14:44:40.293198 TX Vref=32, minBit 1, minWin=25, winSum=422
2996 14:44:40.293282 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 28
2997 14:44:40.293385
2998 14:44:40.293467 Final TX Range 1 Vref 28
2999 14:44:40.293568
3000 14:44:40.293650 ==
3001 14:44:40.293748 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 14:44:40.293836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 14:44:40.293937 ==
3004 14:44:40.294019
3005 14:44:40.294109
3006 14:44:40.294201 TX Vref Scan disable
3007 14:44:40.294292 == TX Byte 0 ==
3008 14:44:40.294385 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3009 14:44:40.294472 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3010 14:44:40.294568 == TX Byte 1 ==
3011 14:44:40.294650 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3012 14:44:40.294754 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3013 14:44:40.294836
3014 14:44:40.294937 [DATLAT]
3015 14:44:40.295018 Freq=1200, CH0 RK1
3016 14:44:40.295121
3017 14:44:40.295203 DATLAT Default: 0xd
3018 14:44:40.295304 0, 0xFFFF, sum = 0
3019 14:44:40.295388 1, 0xFFFF, sum = 0
3020 14:44:40.295492 2, 0xFFFF, sum = 0
3021 14:44:40.295576 3, 0xFFFF, sum = 0
3022 14:44:40.295681 4, 0xFFFF, sum = 0
3023 14:44:40.295765 5, 0xFFFF, sum = 0
3024 14:44:40.295866 6, 0xFFFF, sum = 0
3025 14:44:40.295952 7, 0xFFFF, sum = 0
3026 14:44:40.296054 8, 0xFFFF, sum = 0
3027 14:44:40.296143 9, 0xFFFF, sum = 0
3028 14:44:40.296244 10, 0xFFFF, sum = 0
3029 14:44:40.296335 11, 0xFFFF, sum = 0
3030 14:44:40.296437 12, 0x0, sum = 1
3031 14:44:40.296525 13, 0x0, sum = 2
3032 14:44:40.296634 14, 0x0, sum = 3
3033 14:44:40.296723 15, 0x0, sum = 4
3034 14:44:40.296825 best_step = 13
3035 14:44:40.296913
3036 14:44:40.297012 ==
3037 14:44:40.297099 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 14:44:40.297196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 14:44:40.297287 ==
3040 14:44:40.297387 RX Vref Scan: 0
3041 14:44:40.297473
3042 14:44:40.297565 RX Vref 0 -> 0, step: 1
3043 14:44:40.297698
3044 14:44:40.297825 RX Delay -21 -> 252, step: 4
3045 14:44:40.297960 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3046 14:44:40.298081 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3047 14:44:40.298201 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3048 14:44:40.298320 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3049 14:44:40.298437 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3050 14:44:40.298553 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3051 14:44:40.298871 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3052 14:44:40.299018 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3053 14:44:40.299117 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3054 14:44:40.299210 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3055 14:44:40.299304 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3056 14:44:40.299405 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3057 14:44:40.299499 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3058 14:44:40.299601 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3059 14:44:40.299685 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3060 14:44:40.299757 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3061 14:44:40.299811 ==
3062 14:44:40.299881 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 14:44:40.299937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 14:44:40.299992 ==
3065 14:44:40.300058 DQS Delay:
3066 14:44:40.300142 DQS0 = 0, DQS1 = 0
3067 14:44:40.300227 DQM Delay:
3068 14:44:40.300315 DQM0 = 119, DQM1 = 107
3069 14:44:40.300398 DQ Delay:
3070 14:44:40.300487 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3071 14:44:40.300591 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3072 14:44:40.300675 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3073 14:44:40.300730 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3074 14:44:40.300787
3075 14:44:40.300847
3076 14:44:40.300901 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3077 14:44:40.300957 CH0 RK1: MR19=403, MR18=10F7
3078 14:44:40.301028 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3079 14:44:40.301113 [RxdqsGatingPostProcess] freq 1200
3080 14:44:40.301203 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3081 14:44:40.301319 best DQS0 dly(2T, 0.5T) = (0, 11)
3082 14:44:40.301437 best DQS1 dly(2T, 0.5T) = (0, 12)
3083 14:44:40.301521 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3084 14:44:40.301613 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3085 14:44:40.301697 best DQS0 dly(2T, 0.5T) = (0, 11)
3086 14:44:40.301786 best DQS1 dly(2T, 0.5T) = (0, 11)
3087 14:44:40.301870 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3088 14:44:40.301954 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3089 14:44:40.302047 Pre-setting of DQS Precalculation
3090 14:44:40.302132 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3091 14:44:40.302215 ==
3092 14:44:40.302306 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 14:44:40.302390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 14:44:40.302481 ==
3095 14:44:40.302565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 14:44:40.302656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3097 14:44:40.302740 [CA 0] Center 37 (7~68) winsize 62
3098 14:44:40.302829 [CA 1] Center 37 (7~68) winsize 62
3099 14:44:40.302913 [CA 2] Center 35 (5~65) winsize 61
3100 14:44:40.302997 [CA 3] Center 34 (4~65) winsize 62
3101 14:44:40.303084 [CA 4] Center 34 (4~65) winsize 62
3102 14:44:40.303167 [CA 5] Center 33 (3~64) winsize 62
3103 14:44:40.303257
3104 14:44:40.303340 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3105 14:44:40.303430
3106 14:44:40.303513 [CATrainingPosCal] consider 1 rank data
3107 14:44:40.303602 u2DelayCellTimex100 = 270/100 ps
3108 14:44:40.303686 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 14:44:40.303774 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 14:44:40.303833 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3111 14:44:40.303887 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3112 14:44:40.303940 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3113 14:44:40.304044 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3114 14:44:40.304151
3115 14:44:40.304237 CA PerBit enable=1, Macro0, CA PI delay=33
3116 14:44:40.304320
3117 14:44:40.304460 [CBTSetCACLKResult] CA Dly = 33
3118 14:44:40.304555 CS Dly: 5 (0~36)
3119 14:44:40.304628 ==
3120 14:44:40.304682 Dram Type= 6, Freq= 0, CH_1, rank 1
3121 14:44:40.304746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 14:44:40.304803 ==
3123 14:44:40.304857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3124 14:44:40.304917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3125 14:44:40.304979 [CA 0] Center 38 (8~68) winsize 61
3126 14:44:40.305034 [CA 1] Center 38 (8~69) winsize 62
3127 14:44:40.305088 [CA 2] Center 35 (5~66) winsize 62
3128 14:44:40.305168 [CA 3] Center 35 (5~65) winsize 61
3129 14:44:40.305252 [CA 4] Center 34 (4~65) winsize 62
3130 14:44:40.305342 [CA 5] Center 34 (4~64) winsize 61
3131 14:44:40.305425
3132 14:44:40.305514 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3133 14:44:40.305597
3134 14:44:40.305680 [CATrainingPosCal] consider 2 rank data
3135 14:44:40.305770 u2DelayCellTimex100 = 270/100 ps
3136 14:44:40.305854 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3137 14:44:40.305946 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3138 14:44:40.306029 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3139 14:44:40.306119 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3140 14:44:40.306203 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3141 14:44:40.306294 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3142 14:44:40.306377
3143 14:44:40.306463 CA PerBit enable=1, Macro0, CA PI delay=34
3144 14:44:40.306548
3145 14:44:40.306630 [CBTSetCACLKResult] CA Dly = 34
3146 14:44:40.306720 CS Dly: 6 (0~39)
3147 14:44:40.306802
3148 14:44:40.306892 ----->DramcWriteLeveling(PI) begin...
3149 14:44:40.306977 ==
3150 14:44:40.307068 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 14:44:40.307152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 14:44:40.307240 ==
3153 14:44:40.307297 Write leveling (Byte 0): 25 => 25
3154 14:44:40.307351 Write leveling (Byte 1): 27 => 27
3155 14:44:40.307405 DramcWriteLeveling(PI) end<-----
3156 14:44:40.307475
3157 14:44:40.307529 ==
3158 14:44:40.307583 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 14:44:40.307672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 14:44:40.307755 ==
3161 14:44:40.307847 [Gating] SW mode calibration
3162 14:44:40.307932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3163 14:44:40.308025 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3164 14:44:40.308142 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 14:44:40.308267 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 14:44:40.308352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 14:44:40.308445 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 14:44:40.308529 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 14:44:40.308842 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 14:44:40.308907 0 15 24 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 1)
3171 14:44:40.308974 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 14:44:40.309032 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 14:44:40.309087 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 14:44:40.309145 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 14:44:40.309210 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 14:44:40.309265 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 14:44:40.309322 1 0 20 | B1->B0 | 2424 2626 | 0 1 | (0 0) (0 0)
3178 14:44:40.309414 1 0 24 | B1->B0 | 3f3f 4242 | 0 0 | (0 0) (0 0)
3179 14:44:40.309498 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 14:44:40.309589 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 14:44:40.309673 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 14:44:40.309766 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 14:44:40.309850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 14:44:40.309939 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 14:44:40.310023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3186 14:44:40.310109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3187 14:44:40.310198 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 14:44:40.310281 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 14:44:40.310373 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 14:44:40.310457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 14:44:40.310549 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 14:44:40.310633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 14:44:40.310724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 14:44:40.310807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 14:44:40.310898 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 14:44:40.310983 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 14:44:40.311072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 14:44:40.311157 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 14:44:40.311240 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 14:44:40.311363 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 14:44:40.311487 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 14:44:40.311571 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3203 14:44:40.311658 Total UI for P1: 0, mck2ui 16
3204 14:44:40.311716 best dqsien dly found for B0: ( 1, 3, 22)
3205 14:44:40.311770 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3206 14:44:40.311825 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 14:44:40.311895 Total UI for P1: 0, mck2ui 16
3208 14:44:40.311950 best dqsien dly found for B1: ( 1, 3, 26)
3209 14:44:40.312004 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3210 14:44:40.312091 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3211 14:44:40.312174
3212 14:44:40.312267 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3213 14:44:40.312351 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3214 14:44:40.312442 [Gating] SW calibration Done
3215 14:44:40.312525 ==
3216 14:44:40.312651 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 14:44:40.312708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 14:44:40.312762 ==
3219 14:44:40.312837 RX Vref Scan: 0
3220 14:44:40.312892
3221 14:44:40.312945 RX Vref 0 -> 0, step: 1
3222 14:44:40.313010
3223 14:44:40.313066 RX Delay -40 -> 252, step: 8
3224 14:44:40.313120 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3225 14:44:40.313188 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3226 14:44:40.313279 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3227 14:44:40.313365 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3228 14:44:40.313456 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3229 14:44:40.313540 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3230 14:44:40.313632 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3231 14:44:40.313715 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3232 14:44:40.313809 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3233 14:44:40.313893 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3234 14:44:40.313986 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3235 14:44:40.314070 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3236 14:44:40.314160 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3237 14:44:40.314244 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3238 14:44:40.314329 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3239 14:44:40.314420 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3240 14:44:40.314502 ==
3241 14:44:40.314624 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 14:44:40.314747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 14:44:40.314831 ==
3244 14:44:40.314922 DQS Delay:
3245 14:44:40.315005 DQS0 = 0, DQS1 = 0
3246 14:44:40.315088 DQM Delay:
3247 14:44:40.315178 DQM0 = 120, DQM1 = 112
3248 14:44:40.315261 DQ Delay:
3249 14:44:40.315353 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3250 14:44:40.315437 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3251 14:44:40.315528 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3252 14:44:40.315611 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3253 14:44:40.315702
3254 14:44:40.315785
3255 14:44:40.315869 ==
3256 14:44:40.315957 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 14:44:40.316040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 14:44:40.316133 ==
3259 14:44:40.316215
3260 14:44:40.316308
3261 14:44:40.316390 TX Vref Scan disable
3262 14:44:40.316482 == TX Byte 0 ==
3263 14:44:40.316588 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3264 14:44:40.316690 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3265 14:44:40.316774 == TX Byte 1 ==
3266 14:44:40.316866 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3267 14:44:40.316950 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3268 14:44:40.317042 ==
3269 14:44:40.317126 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 14:44:40.317212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 14:44:40.317302 ==
3272 14:44:40.317386 TX Vref=22, minBit 1, minWin=24, winSum=403
3273 14:44:40.317479 TX Vref=24, minBit 11, minWin=24, winSum=412
3274 14:44:40.317584 TX Vref=26, minBit 1, minWin=25, winSum=412
3275 14:44:40.317691 TX Vref=28, minBit 9, minWin=25, winSum=419
3276 14:44:40.317774 TX Vref=30, minBit 11, minWin=25, winSum=423
3277 14:44:40.318069 TX Vref=32, minBit 10, minWin=25, winSum=421
3278 14:44:40.318162 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 30
3279 14:44:40.318256
3280 14:44:40.318341 Final TX Range 1 Vref 30
3281 14:44:40.318433
3282 14:44:40.318516 ==
3283 14:44:40.318608 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 14:44:40.318693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 14:44:40.318806 ==
3286 14:44:40.318909
3287 14:44:40.319002
3288 14:44:40.319086 TX Vref Scan disable
3289 14:44:40.319179 == TX Byte 0 ==
3290 14:44:40.319263 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3291 14:44:40.319355 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3292 14:44:40.319439 == TX Byte 1 ==
3293 14:44:40.319530 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3294 14:44:40.319615 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3295 14:44:40.319769
3296 14:44:40.319885 [DATLAT]
3297 14:44:40.319978 Freq=1200, CH1 RK0
3298 14:44:40.320061
3299 14:44:40.320152 DATLAT Default: 0xd
3300 14:44:40.320235 0, 0xFFFF, sum = 0
3301 14:44:40.320331 1, 0xFFFF, sum = 0
3302 14:44:40.320416 2, 0xFFFF, sum = 0
3303 14:44:40.320510 3, 0xFFFF, sum = 0
3304 14:44:40.320622 4, 0xFFFF, sum = 0
3305 14:44:40.320693 5, 0xFFFF, sum = 0
3306 14:44:40.320752 6, 0xFFFF, sum = 0
3307 14:44:40.320806 7, 0xFFFF, sum = 0
3308 14:44:40.320874 8, 0xFFFF, sum = 0
3309 14:44:40.320932 9, 0xFFFF, sum = 0
3310 14:44:40.320986 10, 0xFFFF, sum = 0
3311 14:44:40.321041 11, 0xFFFF, sum = 0
3312 14:44:40.321113 12, 0x0, sum = 1
3313 14:44:40.321169 13, 0x0, sum = 2
3314 14:44:40.321223 14, 0x0, sum = 3
3315 14:44:40.321300 15, 0x0, sum = 4
3316 14:44:40.321387 best_step = 13
3317 14:44:40.321468
3318 14:44:40.321539 ==
3319 14:44:40.321592 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 14:44:40.321671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 14:44:40.321755 ==
3322 14:44:40.321845 RX Vref Scan: 1
3323 14:44:40.321928
3324 14:44:40.322014 Set Vref Range= 32 -> 127
3325 14:44:40.322103
3326 14:44:40.322187 RX Vref 32 -> 127, step: 1
3327 14:44:40.322257
3328 14:44:40.322311 RX Delay -13 -> 252, step: 4
3329 14:44:40.322364
3330 14:44:40.322438 Set Vref, RX VrefLevel [Byte0]: 32
3331 14:44:40.322493 [Byte1]: 32
3332 14:44:40.322545
3333 14:44:40.322617 Set Vref, RX VrefLevel [Byte0]: 33
3334 14:44:40.322672 [Byte1]: 33
3335 14:44:40.322724
3336 14:44:40.322781 Set Vref, RX VrefLevel [Byte0]: 34
3337 14:44:40.322843 [Byte1]: 34
3338 14:44:40.322895
3339 14:44:40.322946 Set Vref, RX VrefLevel [Byte0]: 35
3340 14:44:40.323021 [Byte1]: 35
3341 14:44:40.323074
3342 14:44:40.323125 Set Vref, RX VrefLevel [Byte0]: 36
3343 14:44:40.323195 [Byte1]: 36
3344 14:44:40.323250
3345 14:44:40.323301 Set Vref, RX VrefLevel [Byte0]: 37
3346 14:44:40.323360 [Byte1]: 37
3347 14:44:40.323448
3348 14:44:40.323529 Set Vref, RX VrefLevel [Byte0]: 38
3349 14:44:40.323620 [Byte1]: 38
3350 14:44:40.323701
3351 14:44:40.323793 Set Vref, RX VrefLevel [Byte0]: 39
3352 14:44:40.323875 [Byte1]: 39
3353 14:44:40.323960
3354 14:44:40.324013 Set Vref, RX VrefLevel [Byte0]: 40
3355 14:44:40.324065 [Byte1]: 40
3356 14:44:40.324120
3357 14:44:40.324190 Set Vref, RX VrefLevel [Byte0]: 41
3358 14:44:40.324243 [Byte1]: 41
3359 14:44:40.324294
3360 14:44:40.324370 Set Vref, RX VrefLevel [Byte0]: 42
3361 14:44:40.324423 [Byte1]: 42
3362 14:44:40.324492
3363 14:44:40.324601 Set Vref, RX VrefLevel [Byte0]: 43
3364 14:44:40.324656 [Byte1]: 43
3365 14:44:40.324728
3366 14:44:40.324783 Set Vref, RX VrefLevel [Byte0]: 44
3367 14:44:40.324834 [Byte1]: 44
3368 14:44:40.324890
3369 14:44:40.324955 Set Vref, RX VrefLevel [Byte0]: 45
3370 14:44:40.325007 [Byte1]: 45
3371 14:44:40.325058
3372 14:44:40.325145 Set Vref, RX VrefLevel [Byte0]: 46
3373 14:44:40.325228 [Byte1]: 46
3374 14:44:40.325318
3375 14:44:40.325400 Set Vref, RX VrefLevel [Byte0]: 47
3376 14:44:40.325493 [Byte1]: 47
3377 14:44:40.325550
3378 14:44:40.325601 Set Vref, RX VrefLevel [Byte0]: 48
3379 14:44:40.325668 [Byte1]: 48
3380 14:44:40.325726
3381 14:44:40.325778 Set Vref, RX VrefLevel [Byte0]: 49
3382 14:44:40.325829 [Byte1]: 49
3383 14:44:40.325904
3384 14:44:40.325956 Set Vref, RX VrefLevel [Byte0]: 50
3385 14:44:40.326007 [Byte1]: 50
3386 14:44:40.326089
3387 14:44:40.326171 Set Vref, RX VrefLevel [Byte0]: 51
3388 14:44:40.326260 [Byte1]: 51
3389 14:44:40.326316
3390 14:44:40.326367 Set Vref, RX VrefLevel [Byte0]: 52
3391 14:44:40.326427 [Byte1]: 52
3392 14:44:40.326490
3393 14:44:40.326542 Set Vref, RX VrefLevel [Byte0]: 53
3394 14:44:40.326593 [Byte1]: 53
3395 14:44:40.326671
3396 14:44:40.326725 Set Vref, RX VrefLevel [Byte0]: 54
3397 14:44:40.326777 [Byte1]: 54
3398 14:44:40.326869
3399 14:44:40.326950 Set Vref, RX VrefLevel [Byte0]: 55
3400 14:44:40.327033 [Byte1]: 55
3401 14:44:40.327113
3402 14:44:40.327203 Set Vref, RX VrefLevel [Byte0]: 56
3403 14:44:40.327265 [Byte1]: 56
3404 14:44:40.327317
3405 14:44:40.327374 Set Vref, RX VrefLevel [Byte0]: 57
3406 14:44:40.327438 [Byte1]: 57
3407 14:44:40.327490
3408 14:44:40.327542 Set Vref, RX VrefLevel [Byte0]: 58
3409 14:44:40.327657 [Byte1]: 58
3410 14:44:40.327728
3411 14:44:40.327835 Set Vref, RX VrefLevel [Byte0]: 59
3412 14:44:40.327917 [Byte1]: 59
3413 14:44:40.327998
3414 14:44:40.328051 Set Vref, RX VrefLevel [Byte0]: 60
3415 14:44:40.328104 [Byte1]: 60
3416 14:44:40.328171
3417 14:44:40.328229 Set Vref, RX VrefLevel [Byte0]: 61
3418 14:44:40.328281 [Byte1]: 61
3419 14:44:40.328333
3420 14:44:40.328424 Set Vref, RX VrefLevel [Byte0]: 62
3421 14:44:40.328505 [Byte1]: 62
3422 14:44:40.328637
3423 14:44:40.328719 Set Vref, RX VrefLevel [Byte0]: 63
3424 14:44:40.328811 [Byte1]: 63
3425 14:44:40.328892
3426 14:44:40.328985 Set Vref, RX VrefLevel [Byte0]: 64
3427 14:44:40.329066 [Byte1]: 64
3428 14:44:40.329152
3429 14:44:40.329206 Set Vref, RX VrefLevel [Byte0]: 65
3430 14:44:40.329258 [Byte1]: 65
3431 14:44:40.329320
3432 14:44:40.329379 Set Vref, RX VrefLevel [Byte0]: 66
3433 14:44:40.329431 [Byte1]: 66
3434 14:44:40.329485
3435 14:44:40.329578 Set Vref, RX VrefLevel [Byte0]: 67
3436 14:44:40.329659 [Byte1]: 67
3437 14:44:40.329741
3438 14:44:40.329794 Set Vref, RX VrefLevel [Byte0]: 68
3439 14:44:40.329846 [Byte1]: 68
3440 14:44:40.329922
3441 14:44:40.329976 Final RX Vref Byte 0 = 52 to rank0
3442 14:44:40.330029 Final RX Vref Byte 1 = 52 to rank0
3443 14:44:40.330093 Final RX Vref Byte 0 = 52 to rank1
3444 14:44:40.330153 Final RX Vref Byte 1 = 52 to rank1==
3445 14:44:40.330206 Dram Type= 6, Freq= 0, CH_1, rank 0
3446 14:44:40.330461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 14:44:40.330554 ==
3448 14:44:40.330637 DQS Delay:
3449 14:44:40.330732 DQS0 = 0, DQS1 = 0
3450 14:44:40.330847 DQM Delay:
3451 14:44:40.330964 DQM0 = 119, DQM1 = 111
3452 14:44:40.331053 DQ Delay:
3453 14:44:40.331114 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3454 14:44:40.331166 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3455 14:44:40.331226 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =106
3456 14:44:40.331316 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =118
3457 14:44:40.331398
3458 14:44:40.331474
3459 14:44:40.331527 [DQSOSCAuto] RK0, (LSB)MR18= 0x519, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3460 14:44:40.331580 CH1 RK0: MR19=404, MR18=519
3461 14:44:40.331672 CH1_RK0: MR19=0x404, MR18=0x519, DQSOSC=400, MR23=63, INC=40, DEC=27
3462 14:44:40.331754
3463 14:44:40.331846 ----->DramcWriteLeveling(PI) begin...
3464 14:44:40.331929 ==
3465 14:44:40.332019 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 14:44:40.332104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 14:44:40.332190 ==
3468 14:44:40.332278 Write leveling (Byte 0): 25 => 25
3469 14:44:40.332359 Write leveling (Byte 1): 28 => 28
3470 14:44:40.332453 DramcWriteLeveling(PI) end<-----
3471 14:44:40.332534
3472 14:44:40.332658 ==
3473 14:44:40.332712 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 14:44:40.332774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 14:44:40.332837 ==
3476 14:44:40.332889 [Gating] SW mode calibration
3477 14:44:40.332946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3478 14:44:40.333039 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3479 14:44:40.333121 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 14:44:40.333202 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 14:44:40.333256 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 14:44:40.333308 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 14:44:40.333386 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 14:44:40.333440 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 14:44:40.333492 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
3486 14:44:40.333564 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3487 14:44:40.333619 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 14:44:40.333671 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 14:44:40.333732 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 14:44:40.333798 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 14:44:40.333851 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 14:44:40.333907 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 14:44:40.333998 1 0 24 | B1->B0 | 3c3c 2c2c | 0 0 | (0 0) (1 1)
3494 14:44:40.334081 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3495 14:44:40.334176 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 14:44:40.334259 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 14:44:40.334352 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 14:44:40.334465 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 14:44:40.334579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 14:44:40.334633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 14:44:40.334701 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3502 14:44:40.334759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3503 14:44:40.334811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 14:44:40.334862 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 14:44:40.334955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 14:44:40.335037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 14:44:40.335132 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 14:44:40.335214 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 14:44:40.335307 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 14:44:40.335390 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 14:44:40.335482 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 14:44:40.335566 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 14:44:40.335654 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 14:44:40.335740 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 14:44:40.335822 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 14:44:40.335917 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 14:44:40.335999 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3518 14:44:40.336094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3519 14:44:40.336176 Total UI for P1: 0, mck2ui 16
3520 14:44:40.336269 best dqsien dly found for B1: ( 1, 3, 24)
3521 14:44:40.336352 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 14:44:40.336446 Total UI for P1: 0, mck2ui 16
3523 14:44:40.336530 best dqsien dly found for B0: ( 1, 3, 26)
3524 14:44:40.336661 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3525 14:44:40.336743 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3526 14:44:40.336837
3527 14:44:40.336919 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3528 14:44:40.337010 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3529 14:44:40.337095 [Gating] SW calibration Done
3530 14:44:40.337182 ==
3531 14:44:40.337270 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 14:44:40.337352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 14:44:40.337446 ==
3534 14:44:40.337527 RX Vref Scan: 0
3535 14:44:40.337621
3536 14:44:40.337702 RX Vref 0 -> 0, step: 1
3537 14:44:40.337794
3538 14:44:40.337876 RX Delay -40 -> 252, step: 8
3539 14:44:40.337970 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3540 14:44:40.338053 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3541 14:44:40.338142 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3542 14:44:40.338229 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3543 14:44:40.338310 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3544 14:44:40.338404 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3545 14:44:40.338485 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3546 14:44:40.338582 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3547 14:44:40.338664 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3548 14:44:40.338758 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3549 14:44:40.339042 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3550 14:44:40.339130 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3551 14:44:40.339187 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3552 14:44:40.339241 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3553 14:44:40.339317 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3554 14:44:40.339372 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3555 14:44:40.339424 ==
3556 14:44:40.339489 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 14:44:40.339578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 14:44:40.339663 ==
3559 14:44:40.339752 DQS Delay:
3560 14:44:40.339833 DQS0 = 0, DQS1 = 0
3561 14:44:40.339918 DQM Delay:
3562 14:44:40.339972 DQM0 = 119, DQM1 = 112
3563 14:44:40.340025 DQ Delay:
3564 14:44:40.340102 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3565 14:44:40.340156 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3566 14:44:40.340208 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3567 14:44:40.340295 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3568 14:44:40.340377
3569 14:44:40.340470
3570 14:44:40.340558 ==
3571 14:44:40.340613 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 14:44:40.340698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 14:44:40.340753 ==
3574 14:44:40.340807
3575 14:44:40.340886
3576 14:44:40.340938 TX Vref Scan disable
3577 14:44:40.340990 == TX Byte 0 ==
3578 14:44:40.341068 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 14:44:40.341123 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 14:44:40.341175 == TX Byte 1 ==
3581 14:44:40.341266 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 14:44:40.341349 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 14:44:40.341445 ==
3584 14:44:40.341500 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 14:44:40.341563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 14:44:40.341650 ==
3587 14:44:40.341705 TX Vref=22, minBit 0, minWin=25, winSum=414
3588 14:44:40.341757 TX Vref=24, minBit 1, minWin=25, winSum=419
3589 14:44:40.341836 TX Vref=26, minBit 10, minWin=25, winSum=426
3590 14:44:40.341892 TX Vref=28, minBit 10, minWin=25, winSum=426
3591 14:44:40.341944 TX Vref=30, minBit 8, minWin=26, winSum=430
3592 14:44:40.342024 TX Vref=32, minBit 1, minWin=26, winSum=427
3593 14:44:40.342079 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3594 14:44:40.342132
3595 14:44:40.342201 Final TX Range 1 Vref 30
3596 14:44:40.342259
3597 14:44:40.342310 ==
3598 14:44:40.342369 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 14:44:40.342429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 14:44:40.342482 ==
3601 14:44:40.342579
3602 14:44:40.342725
3603 14:44:40.342828 TX Vref Scan disable
3604 14:44:40.342913 == TX Byte 0 ==
3605 14:44:40.343000 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3606 14:44:40.343083 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3607 14:44:40.343167 == TX Byte 1 ==
3608 14:44:40.343251 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3609 14:44:40.343337 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3610 14:44:40.343419
3611 14:44:40.343499 [DATLAT]
3612 14:44:40.343583 Freq=1200, CH1 RK1
3613 14:44:40.343664
3614 14:44:40.343737 DATLAT Default: 0xd
3615 14:44:40.343790 0, 0xFFFF, sum = 0
3616 14:44:40.343844 1, 0xFFFF, sum = 0
3617 14:44:40.343903 2, 0xFFFF, sum = 0
3618 14:44:40.343987 3, 0xFFFF, sum = 0
3619 14:44:40.344069 4, 0xFFFF, sum = 0
3620 14:44:40.344155 5, 0xFFFF, sum = 0
3621 14:44:40.344238 6, 0xFFFF, sum = 0
3622 14:44:40.344324 7, 0xFFFF, sum = 0
3623 14:44:40.344407 8, 0xFFFF, sum = 0
3624 14:44:40.344492 9, 0xFFFF, sum = 0
3625 14:44:40.344605 10, 0xFFFF, sum = 0
3626 14:44:40.344665 11, 0xFFFF, sum = 0
3627 14:44:40.344719 12, 0x0, sum = 1
3628 14:44:40.344771 13, 0x0, sum = 2
3629 14:44:40.344824 14, 0x0, sum = 3
3630 14:44:40.344884 15, 0x0, sum = 4
3631 14:44:40.344937 best_step = 13
3632 14:44:40.344989
3633 14:44:40.345044 ==
3634 14:44:40.345098 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 14:44:40.345150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 14:44:40.345202 ==
3637 14:44:40.345262 RX Vref Scan: 0
3638 14:44:40.345343
3639 14:44:40.345424 RX Vref 0 -> 0, step: 1
3640 14:44:40.345508
3641 14:44:40.345588 RX Delay -13 -> 252, step: 4
3642 14:44:40.345673 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3643 14:44:40.345755 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3644 14:44:40.345839 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3645 14:44:40.345921 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3646 14:44:40.346005 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3647 14:44:40.346087 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3648 14:44:40.346168 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3649 14:44:40.346254 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3650 14:44:40.346336 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3651 14:44:40.346422 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3652 14:44:40.346504 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3653 14:44:40.346587 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3654 14:44:40.346670 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3655 14:44:40.346751 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3656 14:44:40.346836 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3657 14:44:40.346917 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3658 14:44:40.347001 ==
3659 14:44:40.347082 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 14:44:40.347167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 14:44:40.347249 ==
3662 14:44:40.347330 DQS Delay:
3663 14:44:40.347414 DQS0 = 0, DQS1 = 0
3664 14:44:40.347495 DQM Delay:
3665 14:44:40.347579 DQM0 = 119, DQM1 = 113
3666 14:44:40.347660 DQ Delay:
3667 14:44:40.347740 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3668 14:44:40.347802 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3669 14:44:40.347855 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3670 14:44:40.347907 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3671 14:44:40.347989
3672 14:44:40.348069
3673 14:44:40.348156 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3674 14:44:40.348238 CH1 RK1: MR19=403, MR18=7EC
3675 14:44:40.348323 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3676 14:44:40.348406 [RxdqsGatingPostProcess] freq 1200
3677 14:44:40.348488 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3678 14:44:40.348594 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 14:44:40.348662 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 14:44:40.348722 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 14:44:40.348775 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 14:44:40.348827 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 14:44:40.348883 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 14:44:40.348936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 14:44:40.348988 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 14:44:40.349049 Pre-setting of DQS Precalculation
3687 14:44:40.349110 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3688 14:44:40.349365 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3689 14:44:40.349463 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3690 14:44:40.349597
3691 14:44:40.349739
3692 14:44:40.349837 [Calibration Summary] 2400 Mbps
3693 14:44:40.349933 CH 0, Rank 0
3694 14:44:40.350017 SW Impedance : PASS
3695 14:44:40.350173 DUTY Scan : NO K
3696 14:44:40.350294 ZQ Calibration : PASS
3697 14:44:40.350388 Jitter Meter : NO K
3698 14:44:40.350478 CBT Training : PASS
3699 14:44:40.350560 Write leveling : PASS
3700 14:44:40.350642 RX DQS gating : PASS
3701 14:44:40.350730 RX DQ/DQS(RDDQC) : PASS
3702 14:44:40.350811 TX DQ/DQS : PASS
3703 14:44:40.350896 RX DATLAT : PASS
3704 14:44:40.350979 RX DQ/DQS(Engine): PASS
3705 14:44:40.351063 TX OE : NO K
3706 14:44:40.351144 All Pass.
3707 14:44:40.351228
3708 14:44:40.351308 CH 0, Rank 1
3709 14:44:40.351392 SW Impedance : PASS
3710 14:44:40.351473 DUTY Scan : NO K
3711 14:44:40.351561 ZQ Calibration : PASS
3712 14:44:40.351618 Jitter Meter : NO K
3713 14:44:40.351670 CBT Training : PASS
3714 14:44:40.351797 Write leveling : PASS
3715 14:44:40.351905 RX DQS gating : PASS
3716 14:44:40.352015 RX DQ/DQS(RDDQC) : PASS
3717 14:44:40.352107 TX DQ/DQS : PASS
3718 14:44:40.352198 RX DATLAT : PASS
3719 14:44:40.352281 RX DQ/DQS(Engine): PASS
3720 14:44:40.352366 TX OE : NO K
3721 14:44:40.352448 All Pass.
3722 14:44:40.352531
3723 14:44:40.352628 CH 1, Rank 0
3724 14:44:40.352681 SW Impedance : PASS
3725 14:44:40.352738 DUTY Scan : NO K
3726 14:44:40.352792 ZQ Calibration : PASS
3727 14:44:40.352860 Jitter Meter : NO K
3728 14:44:40.352932 CBT Training : PASS
3729 14:44:40.353014 Write leveling : PASS
3730 14:44:40.353095 RX DQS gating : PASS
3731 14:44:40.353228 RX DQ/DQS(RDDQC) : PASS
3732 14:44:40.353383 TX DQ/DQS : PASS
3733 14:44:40.353501 RX DATLAT : PASS
3734 14:44:40.353593 RX DQ/DQS(Engine): PASS
3735 14:44:40.353680 TX OE : NO K
3736 14:44:40.353767 All Pass.
3737 14:44:40.353848
3738 14:44:40.353981 CH 1, Rank 1
3739 14:44:40.354066 SW Impedance : PASS
3740 14:44:40.354245 DUTY Scan : NO K
3741 14:44:40.354354 ZQ Calibration : PASS
3742 14:44:40.354441 Jitter Meter : NO K
3743 14:44:40.354558 CBT Training : PASS
3744 14:44:40.354677 Write leveling : PASS
3745 14:44:40.354760 RX DQS gating : PASS
3746 14:44:40.354887 RX DQ/DQS(RDDQC) : PASS
3747 14:44:40.355047 TX DQ/DQS : PASS
3748 14:44:40.355163 RX DATLAT : PASS
3749 14:44:40.355252 RX DQ/DQS(Engine): PASS
3750 14:44:40.355345 TX OE : NO K
3751 14:44:40.355467 All Pass.
3752 14:44:40.355553
3753 14:44:40.355775 DramC Write-DBI off
3754 14:44:40.355918 PER_BANK_REFRESH: Hybrid Mode
3755 14:44:40.356053 TX_TRACKING: ON
3756 14:44:40.356187 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3757 14:44:40.356296 [FAST_K] Save calibration result to emmc
3758 14:44:40.356449 dramc_set_vcore_voltage set vcore to 650000
3759 14:44:40.356573 Read voltage for 600, 5
3760 14:44:40.356647 Vio18 = 0
3761 14:44:40.356701 Vcore = 650000
3762 14:44:40.356846 Vdram = 0
3763 14:44:40.357051 Vddq = 0
3764 14:44:40.357149 Vmddr = 0
3765 14:44:40.357273 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3766 14:44:40.357436 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3767 14:44:40.357583 MEM_TYPE=3, freq_sel=19
3768 14:44:40.357686 sv_algorithm_assistance_LP4_1600
3769 14:44:40.357772 ============ PULL DRAM RESETB DOWN ============
3770 14:44:40.357857 ========== PULL DRAM RESETB DOWN end =========
3771 14:44:40.357979 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3772 14:44:40.358063 ===================================
3773 14:44:40.358148 LPDDR4 DRAM CONFIGURATION
3774 14:44:40.358229 ===================================
3775 14:44:40.358320 EX_ROW_EN[0] = 0x0
3776 14:44:40.358402 EX_ROW_EN[1] = 0x0
3777 14:44:40.358487 LP4Y_EN = 0x0
3778 14:44:40.358611 WORK_FSP = 0x0
3779 14:44:40.358748 WL = 0x2
3780 14:44:40.358880 RL = 0x2
3781 14:44:40.359054 BL = 0x2
3782 14:44:40.359261 RPST = 0x0
3783 14:44:40.359360 RD_PRE = 0x0
3784 14:44:40.359473 WR_PRE = 0x1
3785 14:44:40.359572 WR_PST = 0x0
3786 14:44:40.359649 DBI_WR = 0x0
3787 14:44:40.359706 DBI_RD = 0x0
3788 14:44:40.359828 OTF = 0x1
3789 14:44:40.359910 ===================================
3790 14:44:40.360086 ===================================
3791 14:44:40.360225 ANA top config
3792 14:44:40.360325 ===================================
3793 14:44:40.360415 DLL_ASYNC_EN = 0
3794 14:44:40.360501 ALL_SLAVE_EN = 1
3795 14:44:40.360628 NEW_RANK_MODE = 1
3796 14:44:40.360736 DLL_IDLE_MODE = 1
3797 14:44:40.360823 LP45_APHY_COMB_EN = 1
3798 14:44:40.361060 TX_ODT_DIS = 1
3799 14:44:40.361237 NEW_8X_MODE = 1
3800 14:44:40.361343 ===================================
3801 14:44:40.361502 ===================================
3802 14:44:40.361665 data_rate = 1200
3803 14:44:40.361830 CKR = 1
3804 14:44:40.361978 DQ_P2S_RATIO = 8
3805 14:44:40.362079 ===================================
3806 14:44:40.362162 CA_P2S_RATIO = 8
3807 14:44:40.362248 DQ_CA_OPEN = 0
3808 14:44:40.362330 DQ_SEMI_OPEN = 0
3809 14:44:40.362414 CA_SEMI_OPEN = 0
3810 14:44:40.362495 CA_FULL_RATE = 0
3811 14:44:40.362655 DQ_CKDIV4_EN = 1
3812 14:44:40.362813 CA_CKDIV4_EN = 1
3813 14:44:40.362922 CA_PREDIV_EN = 0
3814 14:44:40.363011 PH8_DLY = 0
3815 14:44:40.363093 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3816 14:44:40.363179 DQ_AAMCK_DIV = 4
3817 14:44:40.363261 CA_AAMCK_DIV = 4
3818 14:44:40.363345 CA_ADMCK_DIV = 4
3819 14:44:40.363427 DQ_TRACK_CA_EN = 0
3820 14:44:40.363507 CA_PICK = 600
3821 14:44:40.363592 CA_MCKIO = 600
3822 14:44:40.363674 MCKIO_SEMI = 0
3823 14:44:40.363849 PLL_FREQ = 2288
3824 14:44:40.363936 DQ_UI_PI_RATIO = 32
3825 14:44:40.364018 CA_UI_PI_RATIO = 0
3826 14:44:40.364099 ===================================
3827 14:44:40.364186 ===================================
3828 14:44:40.364267 memory_type:LPDDR4
3829 14:44:40.364351 GP_NUM : 10
3830 14:44:40.364447 SRAM_EN : 1
3831 14:44:40.364534 MD32_EN : 0
3832 14:44:40.364613 ===================================
3833 14:44:40.364666 [ANA_INIT] >>>>>>>>>>>>>>
3834 14:44:40.364755 <<<<<< [CONFIGURE PHASE]: ANA_TX
3835 14:44:40.364959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3836 14:44:40.365311 ===================================
3837 14:44:40.365406 data_rate = 1200,PCW = 0X5800
3838 14:44:40.365502 ===================================
3839 14:44:40.365588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3840 14:44:40.365676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 14:44:40.365788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 14:44:40.365897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3843 14:44:40.366017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3844 14:44:40.366101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3845 14:44:40.366204 [ANA_INIT] flow start
3846 14:44:40.366287 [ANA_INIT] PLL >>>>>>>>
3847 14:44:40.366369 [ANA_INIT] PLL <<<<<<<<
3848 14:44:40.366472 [ANA_INIT] MIDPI >>>>>>>>
3849 14:44:40.366554 [ANA_INIT] MIDPI <<<<<<<<
3850 14:44:40.366665 [ANA_INIT] DLL >>>>>>>>
3851 14:44:40.366751 [ANA_INIT] flow end
3852 14:44:40.368072 ============ LP4 DIFF to SE enter ============
3853 14:44:40.370981 ============ LP4 DIFF to SE exit ============
3854 14:44:40.374671 [ANA_INIT] <<<<<<<<<<<<<
3855 14:44:40.377704 [Flow] Enable top DCM control >>>>>
3856 14:44:40.381205 [Flow] Enable top DCM control <<<<<
3857 14:44:40.381355 Enable DLL master slave shuffle
3858 14:44:40.387737 ==============================================================
3859 14:44:40.391215 Gating Mode config
3860 14:44:40.394533 ==============================================================
3861 14:44:40.398069 Config description:
3862 14:44:40.407838 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3863 14:44:40.414162 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3864 14:44:40.417647 SELPH_MODE 0: By rank 1: By Phase
3865 14:44:40.424350 ==============================================================
3866 14:44:40.427598 GAT_TRACK_EN = 1
3867 14:44:40.431031 RX_GATING_MODE = 2
3868 14:44:40.434266 RX_GATING_TRACK_MODE = 2
3869 14:44:40.437552 SELPH_MODE = 1
3870 14:44:40.437664 PICG_EARLY_EN = 1
3871 14:44:40.440702 VALID_LAT_VALUE = 1
3872 14:44:40.447592 ==============================================================
3873 14:44:40.450820 Enter into Gating configuration >>>>
3874 14:44:40.454294 Exit from Gating configuration <<<<
3875 14:44:40.457966 Enter into DVFS_PRE_config >>>>>
3876 14:44:40.467585 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3877 14:44:40.470639 Exit from DVFS_PRE_config <<<<<
3878 14:44:40.474486 Enter into PICG configuration >>>>
3879 14:44:40.477589 Exit from PICG configuration <<<<
3880 14:44:40.480727 [RX_INPUT] configuration >>>>>
3881 14:44:40.484043 [RX_INPUT] configuration <<<<<
3882 14:44:40.487440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3883 14:44:40.494170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3884 14:44:40.500836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 14:44:40.507278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 14:44:40.513993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 14:44:40.517257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 14:44:40.523712 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3889 14:44:40.527242 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3890 14:44:40.530333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3891 14:44:40.533970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3892 14:44:40.540626 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3893 14:44:40.543741 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 14:44:40.546951 ===================================
3895 14:44:40.550235 LPDDR4 DRAM CONFIGURATION
3896 14:44:40.553846 ===================================
3897 14:44:40.553917 EX_ROW_EN[0] = 0x0
3898 14:44:40.557313 EX_ROW_EN[1] = 0x0
3899 14:44:40.557410 LP4Y_EN = 0x0
3900 14:44:40.560390 WORK_FSP = 0x0
3901 14:44:40.560485 WL = 0x2
3902 14:44:40.563704 RL = 0x2
3903 14:44:40.563772 BL = 0x2
3904 14:44:40.566962 RPST = 0x0
3905 14:44:40.567030 RD_PRE = 0x0
3906 14:44:40.570659 WR_PRE = 0x1
3907 14:44:40.570753 WR_PST = 0x0
3908 14:44:40.573861 DBI_WR = 0x0
3909 14:44:40.577430 DBI_RD = 0x0
3910 14:44:40.577503 OTF = 0x1
3911 14:44:40.580367 ===================================
3912 14:44:40.583969 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3913 14:44:40.587017 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3914 14:44:40.593553 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 14:44:40.596933 ===================================
3916 14:44:40.600182 LPDDR4 DRAM CONFIGURATION
3917 14:44:40.603545 ===================================
3918 14:44:40.603650 EX_ROW_EN[0] = 0x10
3919 14:44:40.607126 EX_ROW_EN[1] = 0x0
3920 14:44:40.607224 LP4Y_EN = 0x0
3921 14:44:40.610796 WORK_FSP = 0x0
3922 14:44:40.610970 WL = 0x2
3923 14:44:40.613739 RL = 0x2
3924 14:44:40.613914 BL = 0x2
3925 14:44:40.617277 RPST = 0x0
3926 14:44:40.617410 RD_PRE = 0x0
3927 14:44:40.620625 WR_PRE = 0x1
3928 14:44:40.620721 WR_PST = 0x0
3929 14:44:40.623560 DBI_WR = 0x0
3930 14:44:40.623648 DBI_RD = 0x0
3931 14:44:40.626775 OTF = 0x1
3932 14:44:40.630332 ===================================
3933 14:44:40.636770 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3934 14:44:40.639991 nWR fixed to 30
3935 14:44:40.643683 [ModeRegInit_LP4] CH0 RK0
3936 14:44:40.643790 [ModeRegInit_LP4] CH0 RK1
3937 14:44:40.646898 [ModeRegInit_LP4] CH1 RK0
3938 14:44:40.650017 [ModeRegInit_LP4] CH1 RK1
3939 14:44:40.650122 match AC timing 17
3940 14:44:40.656744 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3941 14:44:40.660165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3942 14:44:40.663404 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3943 14:44:40.670072 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3944 14:44:40.673183 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3945 14:44:40.673262 ==
3946 14:44:40.676469 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 14:44:40.679862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 14:44:40.679962 ==
3949 14:44:40.686742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 14:44:40.693178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 14:44:40.696501 [CA 0] Center 36 (6~67) winsize 62
3952 14:44:40.700070 [CA 1] Center 36 (6~67) winsize 62
3953 14:44:40.703123 [CA 2] Center 34 (4~65) winsize 62
3954 14:44:40.706564 [CA 3] Center 34 (3~65) winsize 63
3955 14:44:40.709896 [CA 4] Center 34 (3~65) winsize 63
3956 14:44:40.713282 [CA 5] Center 33 (2~64) winsize 63
3957 14:44:40.713370
3958 14:44:40.716749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 14:44:40.716837
3960 14:44:40.719836 [CATrainingPosCal] consider 1 rank data
3961 14:44:40.723042 u2DelayCellTimex100 = 270/100 ps
3962 14:44:40.726505 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 14:44:40.730199 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 14:44:40.733229 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 14:44:40.736962 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3966 14:44:40.740034 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3967 14:44:40.743122 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3968 14:44:40.743219
3969 14:44:40.749859 CA PerBit enable=1, Macro0, CA PI delay=33
3970 14:44:40.749972
3971 14:44:40.753144 [CBTSetCACLKResult] CA Dly = 33
3972 14:44:40.753249 CS Dly: 5 (0~36)
3973 14:44:40.753340 ==
3974 14:44:40.756646 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 14:44:40.760157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 14:44:40.760258 ==
3977 14:44:40.766526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 14:44:40.772888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3979 14:44:40.776253 [CA 0] Center 36 (6~67) winsize 62
3980 14:44:40.779769 [CA 1] Center 37 (7~67) winsize 61
3981 14:44:40.782943 [CA 2] Center 35 (5~66) winsize 62
3982 14:44:40.786351 [CA 3] Center 35 (4~66) winsize 63
3983 14:44:40.789731 [CA 4] Center 34 (3~65) winsize 63
3984 14:44:40.792979 [CA 5] Center 34 (3~65) winsize 63
3985 14:44:40.793052
3986 14:44:40.796468 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3987 14:44:40.796596
3988 14:44:40.799503 [CATrainingPosCal] consider 2 rank data
3989 14:44:40.802902 u2DelayCellTimex100 = 270/100 ps
3990 14:44:40.806568 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3991 14:44:40.809685 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3992 14:44:40.812953 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3993 14:44:40.816226 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 14:44:40.819733 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3995 14:44:40.826556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 14:44:40.826659
3997 14:44:40.829536 CA PerBit enable=1, Macro0, CA PI delay=33
3998 14:44:40.829641
3999 14:44:40.832977 [CBTSetCACLKResult] CA Dly = 33
4000 14:44:40.833063 CS Dly: 5 (0~37)
4001 14:44:40.833140
4002 14:44:40.836684 ----->DramcWriteLeveling(PI) begin...
4003 14:44:40.836789 ==
4004 14:44:40.839579 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 14:44:40.846429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 14:44:40.846537 ==
4007 14:44:40.849471 Write leveling (Byte 0): 31 => 31
4008 14:44:40.849576 Write leveling (Byte 1): 30 => 30
4009 14:44:40.852778 DramcWriteLeveling(PI) end<-----
4010 14:44:40.852863
4011 14:44:40.852925 ==
4012 14:44:40.856432 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 14:44:40.863233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 14:44:40.863310 ==
4015 14:44:40.866399 [Gating] SW mode calibration
4016 14:44:40.872883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4017 14:44:40.876138 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4018 14:44:40.883119 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 14:44:40.886337 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 14:44:40.889538 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 14:44:40.892682 0 9 12 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (0 0)
4022 14:44:40.899595 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4023 14:44:40.902742 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 14:44:40.906285 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 14:44:40.912684 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 14:44:40.916267 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 14:44:40.919286 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 14:44:40.926175 0 10 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4029 14:44:40.929444 0 10 12 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
4030 14:44:40.932661 0 10 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
4031 14:44:40.939479 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 14:44:40.942842 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 14:44:40.945913 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 14:44:40.953106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 14:44:40.956023 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 14:44:40.959162 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4037 14:44:40.966358 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4038 14:44:40.969511 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 14:44:40.972690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 14:44:40.979282 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 14:44:40.982653 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 14:44:40.985921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 14:44:40.992359 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 14:44:40.996104 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 14:44:40.999124 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 14:44:41.005902 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 14:44:41.008938 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 14:44:41.012515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 14:44:41.018952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 14:44:41.022198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 14:44:41.025679 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 14:44:41.032274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 14:44:41.035747 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 14:44:41.038852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 14:44:41.042248 Total UI for P1: 0, mck2ui 16
4056 14:44:41.045704 best dqsien dly found for B0: ( 0, 13, 14)
4057 14:44:41.048831 Total UI for P1: 0, mck2ui 16
4058 14:44:41.052041 best dqsien dly found for B1: ( 0, 13, 14)
4059 14:44:41.055353 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4060 14:44:41.059155 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4061 14:44:41.059281
4062 14:44:41.062486 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4063 14:44:41.068727 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4064 14:44:41.068821 [Gating] SW calibration Done
4065 14:44:41.068886 ==
4066 14:44:41.072379 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 14:44:41.078694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 14:44:41.078811 ==
4069 14:44:41.078875 RX Vref Scan: 0
4070 14:44:41.078972
4071 14:44:41.081990 RX Vref 0 -> 0, step: 1
4072 14:44:41.082091
4073 14:44:41.085675 RX Delay -230 -> 252, step: 16
4074 14:44:41.089070 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4075 14:44:41.092332 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4076 14:44:41.095715 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4077 14:44:41.102328 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4078 14:44:41.105625 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4079 14:44:41.108929 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4080 14:44:41.112140 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4081 14:44:41.118825 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4082 14:44:41.122244 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4083 14:44:41.125478 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4084 14:44:41.129054 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4085 14:44:41.132482 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4086 14:44:41.139139 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4087 14:44:41.142446 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4088 14:44:41.145838 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4089 14:44:41.148984 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4090 14:44:41.149061 ==
4091 14:44:41.152269 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 14:44:41.158997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 14:44:41.159112 ==
4094 14:44:41.159220 DQS Delay:
4095 14:44:41.162083 DQS0 = 0, DQS1 = 0
4096 14:44:41.162207 DQM Delay:
4097 14:44:41.165614 DQM0 = 50, DQM1 = 41
4098 14:44:41.165730 DQ Delay:
4099 14:44:41.169113 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4100 14:44:41.172078 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4101 14:44:41.175447 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4102 14:44:41.178727 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4103 14:44:41.178845
4104 14:44:41.178948
4105 14:44:41.179041 ==
4106 14:44:41.181903 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 14:44:41.185534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 14:44:41.185659 ==
4109 14:44:41.185786
4110 14:44:41.185918
4111 14:44:41.188982 TX Vref Scan disable
4112 14:44:41.192178 == TX Byte 0 ==
4113 14:44:41.195259 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4114 14:44:41.198622 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4115 14:44:41.201952 == TX Byte 1 ==
4116 14:44:41.205563 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4117 14:44:41.208785 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4118 14:44:41.208908 ==
4119 14:44:41.212167 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 14:44:41.215363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 14:44:41.218668 ==
4122 14:44:41.218774
4123 14:44:41.218866
4124 14:44:41.219010 TX Vref Scan disable
4125 14:44:41.222408 == TX Byte 0 ==
4126 14:44:41.225812 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4127 14:44:41.232229 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4128 14:44:41.232346 == TX Byte 1 ==
4129 14:44:41.235935 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4130 14:44:41.242370 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4131 14:44:41.242482
4132 14:44:41.242582 [DATLAT]
4133 14:44:41.242677 Freq=600, CH0 RK0
4134 14:44:41.242768
4135 14:44:41.245508 DATLAT Default: 0x9
4136 14:44:41.245608 0, 0xFFFF, sum = 0
4137 14:44:41.249052 1, 0xFFFF, sum = 0
4138 14:44:41.249168 2, 0xFFFF, sum = 0
4139 14:44:41.252788 3, 0xFFFF, sum = 0
4140 14:44:41.252943 4, 0xFFFF, sum = 0
4141 14:44:41.255825 5, 0xFFFF, sum = 0
4142 14:44:41.259105 6, 0xFFFF, sum = 0
4143 14:44:41.259270 7, 0xFFFF, sum = 0
4144 14:44:41.259373 8, 0x0, sum = 1
4145 14:44:41.262564 9, 0x0, sum = 2
4146 14:44:41.262729 10, 0x0, sum = 3
4147 14:44:41.265888 11, 0x0, sum = 4
4148 14:44:41.266051 best_step = 9
4149 14:44:41.266151
4150 14:44:41.266242 ==
4151 14:44:41.268769 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 14:44:41.275991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 14:44:41.276145 ==
4154 14:44:41.276221 RX Vref Scan: 1
4155 14:44:41.276284
4156 14:44:41.279165 RX Vref 0 -> 0, step: 1
4157 14:44:41.279259
4158 14:44:41.282455 RX Delay -163 -> 252, step: 8
4159 14:44:41.282630
4160 14:44:41.285658 Set Vref, RX VrefLevel [Byte0]: 57
4161 14:44:41.289058 [Byte1]: 49
4162 14:44:41.289200
4163 14:44:41.292390 Final RX Vref Byte 0 = 57 to rank0
4164 14:44:41.295570 Final RX Vref Byte 1 = 49 to rank0
4165 14:44:41.298976 Final RX Vref Byte 0 = 57 to rank1
4166 14:44:41.302182 Final RX Vref Byte 1 = 49 to rank1==
4167 14:44:41.305457 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 14:44:41.309017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 14:44:41.309131 ==
4170 14:44:41.312225 DQS Delay:
4171 14:44:41.312304 DQS0 = 0, DQS1 = 0
4172 14:44:41.312369 DQM Delay:
4173 14:44:41.315731 DQM0 = 49, DQM1 = 39
4174 14:44:41.315824 DQ Delay:
4175 14:44:41.319037 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =48
4176 14:44:41.322470 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4177 14:44:41.325739 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4178 14:44:41.329050 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4179 14:44:41.329143
4180 14:44:41.329213
4181 14:44:41.338903 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e58, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4182 14:44:41.339103 CH0 RK0: MR19=808, MR18=5E58
4183 14:44:41.345753 CH0_RK0: MR19=0x808, MR18=0x5E58, DQSOSC=392, MR23=63, INC=170, DEC=113
4184 14:44:41.345961
4185 14:44:41.348917 ----->DramcWriteLeveling(PI) begin...
4186 14:44:41.352046 ==
4187 14:44:41.352182 Dram Type= 6, Freq= 0, CH_0, rank 1
4188 14:44:41.358924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 14:44:41.359084 ==
4190 14:44:41.362469 Write leveling (Byte 0): 36 => 36
4191 14:44:41.365514 Write leveling (Byte 1): 31 => 31
4192 14:44:41.365643 DramcWriteLeveling(PI) end<-----
4193 14:44:41.368855
4194 14:44:41.368938 ==
4195 14:44:41.372316 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 14:44:41.375639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 14:44:41.375724 ==
4198 14:44:41.378882 [Gating] SW mode calibration
4199 14:44:41.385740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4200 14:44:41.388959 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4201 14:44:41.395770 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 14:44:41.399071 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 14:44:41.402299 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 14:44:41.408529 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4205 14:44:41.411851 0 9 16 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
4206 14:44:41.415679 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 14:44:41.422011 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 14:44:41.425298 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 14:44:41.428880 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 14:44:41.435541 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 14:44:41.438933 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 14:44:41.442061 0 10 12 | B1->B0 | 2d2d 3737 | 0 0 | (0 0) (0 0)
4213 14:44:41.448885 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4214 14:44:41.452034 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 14:44:41.455504 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 14:44:41.462178 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 14:44:41.465402 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 14:44:41.468465 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 14:44:41.475430 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 14:44:41.478606 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4221 14:44:41.481795 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4222 14:44:41.488460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 14:44:41.491843 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 14:44:41.495418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 14:44:41.498566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 14:44:41.505181 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 14:44:41.508352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 14:44:41.511765 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 14:44:41.518374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 14:44:41.522112 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 14:44:41.525188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 14:44:41.531882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 14:44:41.535270 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 14:44:41.538529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 14:44:41.545152 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 14:44:41.548567 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4237 14:44:41.551962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 14:44:41.555078 Total UI for P1: 0, mck2ui 16
4239 14:44:41.558436 best dqsien dly found for B0: ( 0, 13, 14)
4240 14:44:41.561790 Total UI for P1: 0, mck2ui 16
4241 14:44:41.564853 best dqsien dly found for B1: ( 0, 13, 12)
4242 14:44:41.568507 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4243 14:44:41.571629 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4244 14:44:41.571715
4245 14:44:41.578263 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4246 14:44:41.581739 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4247 14:44:41.581825 [Gating] SW calibration Done
4248 14:44:41.584944 ==
4249 14:44:41.588175 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 14:44:41.591722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 14:44:41.591839 ==
4252 14:44:41.591939 RX Vref Scan: 0
4253 14:44:41.592041
4254 14:44:41.594981 RX Vref 0 -> 0, step: 1
4255 14:44:41.595084
4256 14:44:41.598161 RX Delay -230 -> 252, step: 16
4257 14:44:41.601630 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4258 14:44:41.604981 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4259 14:44:41.611405 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4260 14:44:41.615190 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4261 14:44:41.618226 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4262 14:44:41.621332 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4263 14:44:41.628064 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4264 14:44:41.631568 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4265 14:44:41.634713 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4266 14:44:41.638056 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4267 14:44:41.641274 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4268 14:44:41.648145 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4269 14:44:41.651514 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4270 14:44:41.654705 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4271 14:44:41.658183 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4272 14:44:41.664780 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4273 14:44:41.664897 ==
4274 14:44:41.668006 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 14:44:41.671461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 14:44:41.671587 ==
4277 14:44:41.671687 DQS Delay:
4278 14:44:41.674650 DQS0 = 0, DQS1 = 0
4279 14:44:41.674789 DQM Delay:
4280 14:44:41.677680 DQM0 = 48, DQM1 = 42
4281 14:44:41.677819 DQ Delay:
4282 14:44:41.681578 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =41
4283 14:44:41.684735 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4284 14:44:41.688231 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4285 14:44:41.691399 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4286 14:44:41.691617
4287 14:44:41.691783
4288 14:44:41.691934 ==
4289 14:44:41.694824 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 14:44:41.698320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 14:44:41.698735 ==
4292 14:44:41.701872
4293 14:44:41.702286
4294 14:44:41.702659 TX Vref Scan disable
4295 14:44:41.704822 == TX Byte 0 ==
4296 14:44:41.708419 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4297 14:44:41.711419 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4298 14:44:41.714651 == TX Byte 1 ==
4299 14:44:41.718147 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4300 14:44:41.721594 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4301 14:44:41.724740 ==
4302 14:44:41.725232 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 14:44:41.731600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 14:44:41.732055 ==
4305 14:44:41.732712
4306 14:44:41.733154
4307 14:44:41.734457 TX Vref Scan disable
4308 14:44:41.734873 == TX Byte 0 ==
4309 14:44:41.741249 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4310 14:44:41.744637 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4311 14:44:41.745124 == TX Byte 1 ==
4312 14:44:41.751409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4313 14:44:41.754519 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4314 14:44:41.754966
4315 14:44:41.755444 [DATLAT]
4316 14:44:41.757817 Freq=600, CH0 RK1
4317 14:44:41.758291
4318 14:44:41.758636 DATLAT Default: 0x9
4319 14:44:41.761250 0, 0xFFFF, sum = 0
4320 14:44:41.761686 1, 0xFFFF, sum = 0
4321 14:44:41.764606 2, 0xFFFF, sum = 0
4322 14:44:41.765042 3, 0xFFFF, sum = 0
4323 14:44:41.767736 4, 0xFFFF, sum = 0
4324 14:44:41.771050 5, 0xFFFF, sum = 0
4325 14:44:41.771483 6, 0xFFFF, sum = 0
4326 14:44:41.774285 7, 0xFFFF, sum = 0
4327 14:44:41.774722 8, 0x0, sum = 1
4328 14:44:41.775069 9, 0x0, sum = 2
4329 14:44:41.777891 10, 0x0, sum = 3
4330 14:44:41.778375 11, 0x0, sum = 4
4331 14:44:41.781357 best_step = 9
4332 14:44:41.781772
4333 14:44:41.782098 ==
4334 14:44:41.784389 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 14:44:41.787751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 14:44:41.788171 ==
4337 14:44:41.790911 RX Vref Scan: 0
4338 14:44:41.791325
4339 14:44:41.791657 RX Vref 0 -> 0, step: 1
4340 14:44:41.791962
4341 14:44:41.794374 RX Delay -163 -> 252, step: 8
4342 14:44:41.801641 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4343 14:44:41.804760 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4344 14:44:41.807916 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4345 14:44:41.811172 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4346 14:44:41.814623 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4347 14:44:41.821590 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4348 14:44:41.824407 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4349 14:44:41.827866 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4350 14:44:41.831093 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4351 14:44:41.837774 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4352 14:44:41.841098 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4353 14:44:41.844380 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4354 14:44:41.847702 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4355 14:44:41.851004 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4356 14:44:41.858162 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4357 14:44:41.861571 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4358 14:44:41.861867 ==
4359 14:44:41.865146 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 14:44:41.868117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 14:44:41.868592 ==
4362 14:44:41.871283 DQS Delay:
4363 14:44:41.871697 DQS0 = 0, DQS1 = 0
4364 14:44:41.872200 DQM Delay:
4365 14:44:41.874827 DQM0 = 47, DQM1 = 39
4366 14:44:41.875241 DQ Delay:
4367 14:44:41.878110 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4368 14:44:41.881304 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4369 14:44:41.884966 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4370 14:44:41.888011 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4371 14:44:41.888432
4372 14:44:41.888829
4373 14:44:41.897910 [DQSOSCAuto] RK1, (LSB)MR18= 0x6531, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4374 14:44:41.898327 CH0 RK1: MR19=808, MR18=6531
4375 14:44:41.904695 CH0_RK1: MR19=0x808, MR18=0x6531, DQSOSC=390, MR23=63, INC=172, DEC=114
4376 14:44:41.907846 [RxdqsGatingPostProcess] freq 600
4377 14:44:41.914602 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4378 14:44:41.918041 Pre-setting of DQS Precalculation
4379 14:44:41.921477 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4380 14:44:41.921890 ==
4381 14:44:41.924365 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 14:44:41.931018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 14:44:41.931431 ==
4384 14:44:41.934377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 14:44:41.940923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4386 14:44:41.944337 [CA 0] Center 35 (5~66) winsize 62
4387 14:44:41.947617 [CA 1] Center 35 (5~66) winsize 62
4388 14:44:41.951050 [CA 2] Center 34 (3~65) winsize 63
4389 14:44:41.954212 [CA 3] Center 33 (3~64) winsize 62
4390 14:44:41.957600 [CA 4] Center 34 (3~65) winsize 63
4391 14:44:41.961047 [CA 5] Center 33 (3~64) winsize 62
4392 14:44:41.961563
4393 14:44:41.964168 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4394 14:44:41.964649
4395 14:44:41.967790 [CATrainingPosCal] consider 1 rank data
4396 14:44:41.971234 u2DelayCellTimex100 = 270/100 ps
4397 14:44:41.974509 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 14:44:41.978064 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 14:44:41.984153 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4400 14:44:41.987642 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 14:44:41.991309 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4402 14:44:41.994120 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 14:44:41.994604
4404 14:44:41.997834 CA PerBit enable=1, Macro0, CA PI delay=33
4405 14:44:41.998310
4406 14:44:42.001266 [CBTSetCACLKResult] CA Dly = 33
4407 14:44:42.001700 CS Dly: 5 (0~36)
4408 14:44:42.002069 ==
4409 14:44:42.004306 Dram Type= 6, Freq= 0, CH_1, rank 1
4410 14:44:42.011039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 14:44:42.011623 ==
4412 14:44:42.014498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 14:44:42.020949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4414 14:44:42.024269 [CA 0] Center 35 (5~66) winsize 62
4415 14:44:42.027601 [CA 1] Center 35 (5~66) winsize 62
4416 14:44:42.030701 [CA 2] Center 34 (4~65) winsize 62
4417 14:44:42.034190 [CA 3] Center 34 (4~64) winsize 61
4418 14:44:42.037724 [CA 4] Center 34 (4~65) winsize 62
4419 14:44:42.040746 [CA 5] Center 33 (3~64) winsize 62
4420 14:44:42.041156
4421 14:44:42.044436 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4422 14:44:42.044938
4423 14:44:42.047504 [CATrainingPosCal] consider 2 rank data
4424 14:44:42.051032 u2DelayCellTimex100 = 270/100 ps
4425 14:44:42.054239 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 14:44:42.057378 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 14:44:42.064448 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 14:44:42.067724 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4429 14:44:42.070869 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 14:44:42.074124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 14:44:42.074536
4432 14:44:42.077543 CA PerBit enable=1, Macro0, CA PI delay=33
4433 14:44:42.077983
4434 14:44:42.080672 [CBTSetCACLKResult] CA Dly = 33
4435 14:44:42.081145 CS Dly: 5 (0~36)
4436 14:44:42.084001
4437 14:44:42.087243 ----->DramcWriteLeveling(PI) begin...
4438 14:44:42.087736 ==
4439 14:44:42.090789 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 14:44:42.093989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 14:44:42.094506 ==
4442 14:44:42.097250 Write leveling (Byte 0): 32 => 32
4443 14:44:42.100584 Write leveling (Byte 1): 30 => 30
4444 14:44:42.103942 DramcWriteLeveling(PI) end<-----
4445 14:44:42.104363
4446 14:44:42.104738 ==
4447 14:44:42.107087 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 14:44:42.110509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 14:44:42.111016 ==
4450 14:44:42.113808 [Gating] SW mode calibration
4451 14:44:42.120133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4452 14:44:42.127280 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4453 14:44:42.130540 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 14:44:42.133405 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 14:44:42.140363 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4456 14:44:42.143643 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 1) (0 0)
4457 14:44:42.147199 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 14:44:42.153662 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 14:44:42.157221 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 14:44:42.160666 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 14:44:42.163406 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 14:44:42.170734 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 14:44:42.173678 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 14:44:42.176961 0 10 12 | B1->B0 | 3939 3939 | 0 0 | (0 0) (0 0)
4465 14:44:42.183751 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 14:44:42.187048 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 14:44:42.190408 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 14:44:42.196706 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 14:44:42.200537 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 14:44:42.203542 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 14:44:42.210392 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4472 14:44:42.213300 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4473 14:44:42.216961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 14:44:42.223258 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 14:44:42.226938 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 14:44:42.230216 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 14:44:42.236922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 14:44:42.240152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 14:44:42.243352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 14:44:42.250066 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 14:44:42.253648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 14:44:42.256834 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 14:44:42.263382 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 14:44:42.266746 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 14:44:42.270006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 14:44:42.276845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 14:44:42.280253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4488 14:44:42.283472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 14:44:42.286770 Total UI for P1: 0, mck2ui 16
4490 14:44:42.290008 best dqsien dly found for B0: ( 0, 13, 8)
4491 14:44:42.293304 Total UI for P1: 0, mck2ui 16
4492 14:44:42.296628 best dqsien dly found for B1: ( 0, 13, 10)
4493 14:44:42.299916 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4494 14:44:42.303296 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4495 14:44:42.303728
4496 14:44:42.306525 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4497 14:44:42.313280 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4498 14:44:42.313710 [Gating] SW calibration Done
4499 14:44:42.314055 ==
4500 14:44:42.316327 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 14:44:42.323166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 14:44:42.323601 ==
4503 14:44:42.323941 RX Vref Scan: 0
4504 14:44:42.324336
4505 14:44:42.326609 RX Vref 0 -> 0, step: 1
4506 14:44:42.327037
4507 14:44:42.329766 RX Delay -230 -> 252, step: 16
4508 14:44:42.333162 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4509 14:44:42.336394 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4510 14:44:42.339791 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4511 14:44:42.346516 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4512 14:44:42.349643 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4513 14:44:42.353192 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4514 14:44:42.356251 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4515 14:44:42.359762 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4516 14:44:42.366512 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4517 14:44:42.369779 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4518 14:44:42.372844 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4519 14:44:42.376310 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4520 14:44:42.382860 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4521 14:44:42.386491 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4522 14:44:42.389753 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4523 14:44:42.392836 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4524 14:44:42.393304 ==
4525 14:44:42.396638 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 14:44:42.403053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 14:44:42.403635 ==
4528 14:44:42.403990 DQS Delay:
4529 14:44:42.406268 DQS0 = 0, DQS1 = 0
4530 14:44:42.406783 DQM Delay:
4531 14:44:42.407264 DQM0 = 52, DQM1 = 40
4532 14:44:42.409914 DQ Delay:
4533 14:44:42.413071 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4534 14:44:42.416137 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4535 14:44:42.419750 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4536 14:44:42.422974 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4537 14:44:42.423546
4538 14:44:42.423908
4539 14:44:42.424229 ==
4540 14:44:42.426260 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 14:44:42.429706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 14:44:42.430141 ==
4543 14:44:42.430484
4544 14:44:42.430798
4545 14:44:42.433013 TX Vref Scan disable
4546 14:44:42.436135 == TX Byte 0 ==
4547 14:44:42.439458 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4548 14:44:42.442954 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4549 14:44:42.446579 == TX Byte 1 ==
4550 14:44:42.449437 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4551 14:44:42.453232 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4552 14:44:42.453885 ==
4553 14:44:42.456635 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 14:44:42.459579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 14:44:42.460148 ==
4556 14:44:42.462876
4557 14:44:42.463376
4558 14:44:42.463725 TX Vref Scan disable
4559 14:44:42.466296 == TX Byte 0 ==
4560 14:44:42.469701 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4561 14:44:42.476411 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4562 14:44:42.476873 == TX Byte 1 ==
4563 14:44:42.479685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4564 14:44:42.486317 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4565 14:44:42.486921
4566 14:44:42.487287 [DATLAT]
4567 14:44:42.487603 Freq=600, CH1 RK0
4568 14:44:42.488001
4569 14:44:42.489752 DATLAT Default: 0x9
4570 14:44:42.490174 0, 0xFFFF, sum = 0
4571 14:44:42.493025 1, 0xFFFF, sum = 0
4572 14:44:42.496215 2, 0xFFFF, sum = 0
4573 14:44:42.496675 3, 0xFFFF, sum = 0
4574 14:44:42.499387 4, 0xFFFF, sum = 0
4575 14:44:42.499815 5, 0xFFFF, sum = 0
4576 14:44:42.502985 6, 0xFFFF, sum = 0
4577 14:44:42.503414 7, 0xFFFF, sum = 0
4578 14:44:42.506399 8, 0x0, sum = 1
4579 14:44:42.506827 9, 0x0, sum = 2
4580 14:44:42.507173 10, 0x0, sum = 3
4581 14:44:42.509490 11, 0x0, sum = 4
4582 14:44:42.510044 best_step = 9
4583 14:44:42.510394
4584 14:44:42.510709 ==
4585 14:44:42.512662 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 14:44:42.519936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 14:44:42.520708 ==
4588 14:44:42.521418 RX Vref Scan: 1
4589 14:44:42.522059
4590 14:44:42.523024 RX Vref 0 -> 0, step: 1
4591 14:44:42.523651
4592 14:44:42.526322 RX Delay -179 -> 252, step: 8
4593 14:44:42.526856
4594 14:44:42.529472 Set Vref, RX VrefLevel [Byte0]: 52
4595 14:44:42.532729 [Byte1]: 52
4596 14:44:42.533151
4597 14:44:42.536153 Final RX Vref Byte 0 = 52 to rank0
4598 14:44:42.539647 Final RX Vref Byte 1 = 52 to rank0
4599 14:44:42.542903 Final RX Vref Byte 0 = 52 to rank1
4600 14:44:42.546123 Final RX Vref Byte 1 = 52 to rank1==
4601 14:44:42.549656 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 14:44:42.552774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 14:44:42.553198 ==
4604 14:44:42.556125 DQS Delay:
4605 14:44:42.556545 DQS0 = 0, DQS1 = 0
4606 14:44:42.559535 DQM Delay:
4607 14:44:42.560049 DQM0 = 49, DQM1 = 41
4608 14:44:42.560408 DQ Delay:
4609 14:44:42.562834 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4610 14:44:42.565905 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4611 14:44:42.569520 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4612 14:44:42.572922 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4613 14:44:42.573348
4614 14:44:42.573783
4615 14:44:42.582515 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4616 14:44:42.586277 CH1 RK0: MR19=808, MR18=4C73
4617 14:44:42.589133 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4618 14:44:42.592910
4619 14:44:42.596303 ----->DramcWriteLeveling(PI) begin...
4620 14:44:42.596834 ==
4621 14:44:42.599687 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 14:44:42.602820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 14:44:42.603269 ==
4624 14:44:42.606029 Write leveling (Byte 0): 27 => 27
4625 14:44:42.609468 Write leveling (Byte 1): 27 => 27
4626 14:44:42.612622 DramcWriteLeveling(PI) end<-----
4627 14:44:42.613042
4628 14:44:42.613374 ==
4629 14:44:42.615817 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 14:44:42.619834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 14:44:42.620362 ==
4632 14:44:42.622590 [Gating] SW mode calibration
4633 14:44:42.629394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4634 14:44:42.635883 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4635 14:44:42.639370 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 14:44:42.642580 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 14:44:42.649115 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4638 14:44:42.652645 0 9 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 1)
4639 14:44:42.656101 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 14:44:42.659407 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 14:44:42.665990 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 14:44:42.669060 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 14:44:42.672712 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 14:44:42.679910 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 14:44:42.682934 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4646 14:44:42.686047 0 10 12 | B1->B0 | 3c3c 3131 | 0 0 | (0 0) (0 0)
4647 14:44:42.692516 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 14:44:42.695812 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 14:44:42.699057 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 14:44:42.706117 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 14:44:42.709245 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 14:44:42.712471 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 14:44:42.719352 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 14:44:42.722456 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4655 14:44:42.725813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 14:44:42.732485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 14:44:42.735756 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 14:44:42.738994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 14:44:42.745833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 14:44:42.749290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 14:44:42.752401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 14:44:42.758709 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 14:44:42.762397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 14:44:42.765906 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 14:44:42.772400 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 14:44:42.775594 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 14:44:42.778885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 14:44:42.782149 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 14:44:42.788734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4670 14:44:42.792269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4671 14:44:42.795628 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 14:44:42.798665 Total UI for P1: 0, mck2ui 16
4673 14:44:42.802150 best dqsien dly found for B0: ( 0, 13, 10)
4674 14:44:42.805041 Total UI for P1: 0, mck2ui 16
4675 14:44:42.808696 best dqsien dly found for B1: ( 0, 13, 10)
4676 14:44:42.812228 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4677 14:44:42.815483 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4678 14:44:42.818515
4679 14:44:42.821911 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4680 14:44:42.825093 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4681 14:44:42.828533 [Gating] SW calibration Done
4682 14:44:42.828655 ==
4683 14:44:42.831790 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 14:44:42.834994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 14:44:42.835067 ==
4686 14:44:42.835129 RX Vref Scan: 0
4687 14:44:42.838294
4688 14:44:42.838394 RX Vref 0 -> 0, step: 1
4689 14:44:42.838466
4690 14:44:42.841781 RX Delay -230 -> 252, step: 16
4691 14:44:42.844932 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4692 14:44:42.851552 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4693 14:44:42.855101 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4694 14:44:42.858492 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4695 14:44:42.861462 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4696 14:44:42.864959 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4697 14:44:42.871342 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4698 14:44:42.874691 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4699 14:44:42.878121 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4700 14:44:42.881421 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4701 14:44:42.888491 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4702 14:44:42.891582 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4703 14:44:42.894908 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4704 14:44:42.898423 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4705 14:44:42.901676 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4706 14:44:42.908310 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4707 14:44:42.908778 ==
4708 14:44:42.911751 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 14:44:42.914976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 14:44:42.915408 ==
4711 14:44:42.915753 DQS Delay:
4712 14:44:42.918324 DQS0 = 0, DQS1 = 0
4713 14:44:42.918750 DQM Delay:
4714 14:44:42.921520 DQM0 = 50, DQM1 = 47
4715 14:44:42.921948 DQ Delay:
4716 14:44:42.924860 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4717 14:44:42.928418 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4718 14:44:42.931384 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4719 14:44:42.935004 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4720 14:44:42.935434
4721 14:44:42.935773
4722 14:44:42.936087 ==
4723 14:44:42.938213 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 14:44:42.941431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 14:44:42.944638 ==
4726 14:44:42.945065
4727 14:44:42.945406
4728 14:44:42.945723 TX Vref Scan disable
4729 14:44:42.948460 == TX Byte 0 ==
4730 14:44:42.951551 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4731 14:44:42.954800 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4732 14:44:42.958148 == TX Byte 1 ==
4733 14:44:42.961236 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4734 14:44:42.965833 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4735 14:44:42.968251 ==
4736 14:44:42.971387 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 14:44:42.974812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 14:44:42.975248 ==
4739 14:44:42.975589
4740 14:44:42.975905
4741 14:44:42.977837 TX Vref Scan disable
4742 14:44:42.978262 == TX Byte 0 ==
4743 14:44:42.984462 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4744 14:44:42.988234 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4745 14:44:42.988707 == TX Byte 1 ==
4746 14:44:42.994720 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4747 14:44:42.997792 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4748 14:44:42.998222
4749 14:44:42.998565 [DATLAT]
4750 14:44:43.001112 Freq=600, CH1 RK1
4751 14:44:43.001540
4752 14:44:43.001879 DATLAT Default: 0x9
4753 14:44:43.004919 0, 0xFFFF, sum = 0
4754 14:44:43.005353 1, 0xFFFF, sum = 0
4755 14:44:43.008256 2, 0xFFFF, sum = 0
4756 14:44:43.008726 3, 0xFFFF, sum = 0
4757 14:44:43.011427 4, 0xFFFF, sum = 0
4758 14:44:43.011859 5, 0xFFFF, sum = 0
4759 14:44:43.014875 6, 0xFFFF, sum = 0
4760 14:44:43.018191 7, 0xFFFF, sum = 0
4761 14:44:43.018625 8, 0x0, sum = 1
4762 14:44:43.018969 9, 0x0, sum = 2
4763 14:44:43.021247 10, 0x0, sum = 3
4764 14:44:43.021679 11, 0x0, sum = 4
4765 14:44:43.024494 best_step = 9
4766 14:44:43.024957
4767 14:44:43.025298 ==
4768 14:44:43.027903 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 14:44:43.031509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 14:44:43.031947 ==
4771 14:44:43.034644 RX Vref Scan: 0
4772 14:44:43.035070
4773 14:44:43.035411 RX Vref 0 -> 0, step: 1
4774 14:44:43.035729
4775 14:44:43.037929 RX Delay -163 -> 252, step: 8
4776 14:44:43.044642 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4777 14:44:43.048075 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4778 14:44:43.051316 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4779 14:44:43.055107 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4780 14:44:43.058153 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4781 14:44:43.065142 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4782 14:44:43.068389 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4783 14:44:43.071304 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4784 14:44:43.074476 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4785 14:44:43.081477 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4786 14:44:43.084785 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4787 14:44:43.088213 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4788 14:44:43.091575 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4789 14:44:43.094382 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4790 14:44:43.101175 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4791 14:44:43.104377 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4792 14:44:43.104621 ==
4793 14:44:43.107677 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 14:44:43.111054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 14:44:43.111283 ==
4796 14:44:43.114207 DQS Delay:
4797 14:44:43.114434 DQS0 = 0, DQS1 = 0
4798 14:44:43.114616 DQM Delay:
4799 14:44:43.117540 DQM0 = 47, DQM1 = 45
4800 14:44:43.117766 DQ Delay:
4801 14:44:43.120946 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4802 14:44:43.124351 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =48
4803 14:44:43.127651 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4804 14:44:43.130946 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4805 14:44:43.131028
4806 14:44:43.131093
4807 14:44:43.140914 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4808 14:44:43.143884 CH1 RK1: MR19=808, MR18=5D23
4809 14:44:43.147697 CH1_RK1: MR19=0x808, MR18=0x5D23, DQSOSC=392, MR23=63, INC=170, DEC=113
4810 14:44:43.150906 [RxdqsGatingPostProcess] freq 600
4811 14:44:43.157482 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4812 14:44:43.160755 Pre-setting of DQS Precalculation
4813 14:44:43.163907 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4814 14:44:43.173910 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4815 14:44:43.180360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4816 14:44:43.180470
4817 14:44:43.180568
4818 14:44:43.183562 [Calibration Summary] 1200 Mbps
4819 14:44:43.183633 CH 0, Rank 0
4820 14:44:43.187241 SW Impedance : PASS
4821 14:44:43.187312 DUTY Scan : NO K
4822 14:44:43.190340 ZQ Calibration : PASS
4823 14:44:43.193704 Jitter Meter : NO K
4824 14:44:43.193776 CBT Training : PASS
4825 14:44:43.197304 Write leveling : PASS
4826 14:44:43.200460 RX DQS gating : PASS
4827 14:44:43.200567 RX DQ/DQS(RDDQC) : PASS
4828 14:44:43.203573 TX DQ/DQS : PASS
4829 14:44:43.206953 RX DATLAT : PASS
4830 14:44:43.207028 RX DQ/DQS(Engine): PASS
4831 14:44:43.210547 TX OE : NO K
4832 14:44:43.210619 All Pass.
4833 14:44:43.210681
4834 14:44:43.213440 CH 0, Rank 1
4835 14:44:43.213513 SW Impedance : PASS
4836 14:44:43.216792 DUTY Scan : NO K
4837 14:44:43.216862 ZQ Calibration : PASS
4838 14:44:43.220336 Jitter Meter : NO K
4839 14:44:43.223522 CBT Training : PASS
4840 14:44:43.223593 Write leveling : PASS
4841 14:44:43.226869 RX DQS gating : PASS
4842 14:44:43.230079 RX DQ/DQS(RDDQC) : PASS
4843 14:44:43.230151 TX DQ/DQS : PASS
4844 14:44:43.233477 RX DATLAT : PASS
4845 14:44:43.236970 RX DQ/DQS(Engine): PASS
4846 14:44:43.237040 TX OE : NO K
4847 14:44:43.240018 All Pass.
4848 14:44:43.240087
4849 14:44:43.240146 CH 1, Rank 0
4850 14:44:43.243296 SW Impedance : PASS
4851 14:44:43.243364 DUTY Scan : NO K
4852 14:44:43.246912 ZQ Calibration : PASS
4853 14:44:43.250270 Jitter Meter : NO K
4854 14:44:43.250340 CBT Training : PASS
4855 14:44:43.253479 Write leveling : PASS
4856 14:44:43.256754 RX DQS gating : PASS
4857 14:44:43.256827 RX DQ/DQS(RDDQC) : PASS
4858 14:44:43.260015 TX DQ/DQS : PASS
4859 14:44:43.260086 RX DATLAT : PASS
4860 14:44:43.263270 RX DQ/DQS(Engine): PASS
4861 14:44:43.266638 TX OE : NO K
4862 14:44:43.266725 All Pass.
4863 14:44:43.266791
4864 14:44:43.269991 CH 1, Rank 1
4865 14:44:43.270062 SW Impedance : PASS
4866 14:44:43.273197 DUTY Scan : NO K
4867 14:44:43.273275 ZQ Calibration : PASS
4868 14:44:43.276599 Jitter Meter : NO K
4869 14:44:43.279828 CBT Training : PASS
4870 14:44:43.279898 Write leveling : PASS
4871 14:44:43.283214 RX DQS gating : PASS
4872 14:44:43.286710 RX DQ/DQS(RDDQC) : PASS
4873 14:44:43.286781 TX DQ/DQS : PASS
4874 14:44:43.289877 RX DATLAT : PASS
4875 14:44:43.293318 RX DQ/DQS(Engine): PASS
4876 14:44:43.293395 TX OE : NO K
4877 14:44:43.296467 All Pass.
4878 14:44:43.296583
4879 14:44:43.296668 DramC Write-DBI off
4880 14:44:43.299523 PER_BANK_REFRESH: Hybrid Mode
4881 14:44:43.299592 TX_TRACKING: ON
4882 14:44:43.309920 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4883 14:44:43.312901 [FAST_K] Save calibration result to emmc
4884 14:44:43.316326 dramc_set_vcore_voltage set vcore to 662500
4885 14:44:43.319612 Read voltage for 933, 3
4886 14:44:43.319691 Vio18 = 0
4887 14:44:43.322786 Vcore = 662500
4888 14:44:43.322857 Vdram = 0
4889 14:44:43.322918 Vddq = 0
4890 14:44:43.326459 Vmddr = 0
4891 14:44:43.329903 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4892 14:44:43.336367 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4893 14:44:43.336473 MEM_TYPE=3, freq_sel=17
4894 14:44:43.339729 sv_algorithm_assistance_LP4_1600
4895 14:44:43.342932 ============ PULL DRAM RESETB DOWN ============
4896 14:44:43.349659 ========== PULL DRAM RESETB DOWN end =========
4897 14:44:43.352867 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4898 14:44:43.356075 ===================================
4899 14:44:43.359357 LPDDR4 DRAM CONFIGURATION
4900 14:44:43.362727 ===================================
4901 14:44:43.362797 EX_ROW_EN[0] = 0x0
4902 14:44:43.365986 EX_ROW_EN[1] = 0x0
4903 14:44:43.369642 LP4Y_EN = 0x0
4904 14:44:43.369719 WORK_FSP = 0x0
4905 14:44:43.372883 WL = 0x3
4906 14:44:43.372958 RL = 0x3
4907 14:44:43.376151 BL = 0x2
4908 14:44:43.376221 RPST = 0x0
4909 14:44:43.379476 RD_PRE = 0x0
4910 14:44:43.379546 WR_PRE = 0x1
4911 14:44:43.382750 WR_PST = 0x0
4912 14:44:43.382821 DBI_WR = 0x0
4913 14:44:43.386047 DBI_RD = 0x0
4914 14:44:43.386124 OTF = 0x1
4915 14:44:43.389378 ===================================
4916 14:44:43.392719 ===================================
4917 14:44:43.396098 ANA top config
4918 14:44:43.399413 ===================================
4919 14:44:43.399491 DLL_ASYNC_EN = 0
4920 14:44:43.402479 ALL_SLAVE_EN = 1
4921 14:44:43.405847 NEW_RANK_MODE = 1
4922 14:44:43.409370 DLL_IDLE_MODE = 1
4923 14:44:43.409448 LP45_APHY_COMB_EN = 1
4924 14:44:43.412914 TX_ODT_DIS = 1
4925 14:44:43.415808 NEW_8X_MODE = 1
4926 14:44:43.419431 ===================================
4927 14:44:43.422393 ===================================
4928 14:44:43.425686 data_rate = 1866
4929 14:44:43.429016 CKR = 1
4930 14:44:43.432424 DQ_P2S_RATIO = 8
4931 14:44:43.435934 ===================================
4932 14:44:43.436005 CA_P2S_RATIO = 8
4933 14:44:43.439186 DQ_CA_OPEN = 0
4934 14:44:43.442560 DQ_SEMI_OPEN = 0
4935 14:44:43.445868 CA_SEMI_OPEN = 0
4936 14:44:43.449026 CA_FULL_RATE = 0
4937 14:44:43.452218 DQ_CKDIV4_EN = 1
4938 14:44:43.452294 CA_CKDIV4_EN = 1
4939 14:44:43.455623 CA_PREDIV_EN = 0
4940 14:44:43.458845 PH8_DLY = 0
4941 14:44:43.462586 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4942 14:44:43.465436 DQ_AAMCK_DIV = 4
4943 14:44:43.469277 CA_AAMCK_DIV = 4
4944 14:44:43.469361 CA_ADMCK_DIV = 4
4945 14:44:43.472175 DQ_TRACK_CA_EN = 0
4946 14:44:43.475751 CA_PICK = 933
4947 14:44:43.479100 CA_MCKIO = 933
4948 14:44:43.482351 MCKIO_SEMI = 0
4949 14:44:43.485651 PLL_FREQ = 3732
4950 14:44:43.488970 DQ_UI_PI_RATIO = 32
4951 14:44:43.489048 CA_UI_PI_RATIO = 0
4952 14:44:43.492221 ===================================
4953 14:44:43.495458 ===================================
4954 14:44:43.498788 memory_type:LPDDR4
4955 14:44:43.501928 GP_NUM : 10
4956 14:44:43.502013 SRAM_EN : 1
4957 14:44:43.505581 MD32_EN : 0
4958 14:44:43.508778 ===================================
4959 14:44:43.511960 [ANA_INIT] >>>>>>>>>>>>>>
4960 14:44:43.515325 <<<<<< [CONFIGURE PHASE]: ANA_TX
4961 14:44:43.519104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4962 14:44:43.522301 ===================================
4963 14:44:43.522377 data_rate = 1866,PCW = 0X8f00
4964 14:44:43.525580 ===================================
4965 14:44:43.528583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4966 14:44:43.535582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 14:44:43.542396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 14:44:43.545567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4969 14:44:43.548961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4970 14:44:43.552094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4971 14:44:43.555379 [ANA_INIT] flow start
4972 14:44:43.555490 [ANA_INIT] PLL >>>>>>>>
4973 14:44:43.558568 [ANA_INIT] PLL <<<<<<<<
4974 14:44:43.561989 [ANA_INIT] MIDPI >>>>>>>>
4975 14:44:43.565156 [ANA_INIT] MIDPI <<<<<<<<
4976 14:44:43.565231 [ANA_INIT] DLL >>>>>>>>
4977 14:44:43.568993 [ANA_INIT] flow end
4978 14:44:43.571793 ============ LP4 DIFF to SE enter ============
4979 14:44:43.575679 ============ LP4 DIFF to SE exit ============
4980 14:44:43.578735 [ANA_INIT] <<<<<<<<<<<<<
4981 14:44:43.582009 [Flow] Enable top DCM control >>>>>
4982 14:44:43.585295 [Flow] Enable top DCM control <<<<<
4983 14:44:43.588480 Enable DLL master slave shuffle
4984 14:44:43.595216 ==============================================================
4985 14:44:43.595321 Gating Mode config
4986 14:44:43.602042 ==============================================================
4987 14:44:43.602154 Config description:
4988 14:44:43.611802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4989 14:44:43.618476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4990 14:44:43.625057 SELPH_MODE 0: By rank 1: By Phase
4991 14:44:43.628568 ==============================================================
4992 14:44:43.631946 GAT_TRACK_EN = 1
4993 14:44:43.635004 RX_GATING_MODE = 2
4994 14:44:43.638633 RX_GATING_TRACK_MODE = 2
4995 14:44:43.641738 SELPH_MODE = 1
4996 14:44:43.645225 PICG_EARLY_EN = 1
4997 14:44:43.648577 VALID_LAT_VALUE = 1
4998 14:44:43.651898 ==============================================================
4999 14:44:43.655141 Enter into Gating configuration >>>>
5000 14:44:43.658696 Exit from Gating configuration <<<<
5001 14:44:43.662086 Enter into DVFS_PRE_config >>>>>
5002 14:44:43.675159 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5003 14:44:43.678360 Exit from DVFS_PRE_config <<<<<
5004 14:44:43.682104 Enter into PICG configuration >>>>
5005 14:44:43.682209 Exit from PICG configuration <<<<
5006 14:44:43.685267 [RX_INPUT] configuration >>>>>
5007 14:44:43.688557 [RX_INPUT] configuration <<<<<
5008 14:44:43.695227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5009 14:44:43.698545 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5010 14:44:43.705020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 14:44:43.711561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 14:44:43.718373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 14:44:43.724946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 14:44:43.728252 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5015 14:44:43.731898 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5016 14:44:43.734627 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5017 14:44:43.741496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5018 14:44:43.745282 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5019 14:44:43.747973 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 14:44:43.751270 ===================================
5021 14:44:43.754656 LPDDR4 DRAM CONFIGURATION
5022 14:44:43.758004 ===================================
5023 14:44:43.761383 EX_ROW_EN[0] = 0x0
5024 14:44:43.761460 EX_ROW_EN[1] = 0x0
5025 14:44:43.764683 LP4Y_EN = 0x0
5026 14:44:43.764755 WORK_FSP = 0x0
5027 14:44:43.768045 WL = 0x3
5028 14:44:43.768123 RL = 0x3
5029 14:44:43.771404 BL = 0x2
5030 14:44:43.771481 RPST = 0x0
5031 14:44:43.774565 RD_PRE = 0x0
5032 14:44:43.774633 WR_PRE = 0x1
5033 14:44:43.777860 WR_PST = 0x0
5034 14:44:43.777938 DBI_WR = 0x0
5035 14:44:43.781183 DBI_RD = 0x0
5036 14:44:43.781255 OTF = 0x1
5037 14:44:43.784402 ===================================
5038 14:44:43.791275 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5039 14:44:43.794605 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5040 14:44:43.797572 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 14:44:43.800867 ===================================
5042 14:44:43.804213 LPDDR4 DRAM CONFIGURATION
5043 14:44:43.807654 ===================================
5044 14:44:43.810850 EX_ROW_EN[0] = 0x10
5045 14:44:43.810927 EX_ROW_EN[1] = 0x0
5046 14:44:43.814098 LP4Y_EN = 0x0
5047 14:44:43.814167 WORK_FSP = 0x0
5048 14:44:43.817813 WL = 0x3
5049 14:44:43.817882 RL = 0x3
5050 14:44:43.820985 BL = 0x2
5051 14:44:43.821052 RPST = 0x0
5052 14:44:43.824205 RD_PRE = 0x0
5053 14:44:43.824272 WR_PRE = 0x1
5054 14:44:43.827578 WR_PST = 0x0
5055 14:44:43.827648 DBI_WR = 0x0
5056 14:44:43.831285 DBI_RD = 0x0
5057 14:44:43.831353 OTF = 0x1
5058 14:44:43.834149 ===================================
5059 14:44:43.841022 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5060 14:44:43.845776 nWR fixed to 30
5061 14:44:43.848853 [ModeRegInit_LP4] CH0 RK0
5062 14:44:43.848926 [ModeRegInit_LP4] CH0 RK1
5063 14:44:43.852017 [ModeRegInit_LP4] CH1 RK0
5064 14:44:43.855438 [ModeRegInit_LP4] CH1 RK1
5065 14:44:43.855515 match AC timing 9
5066 14:44:43.862209 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5067 14:44:43.865493 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5068 14:44:43.868613 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5069 14:44:43.875207 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5070 14:44:43.878397 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5071 14:44:43.878473 ==
5072 14:44:43.881642 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 14:44:43.885496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 14:44:43.885566 ==
5075 14:44:43.892203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 14:44:43.898188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5077 14:44:43.902090 [CA 0] Center 38 (7~69) winsize 63
5078 14:44:43.905275 [CA 1] Center 38 (8~69) winsize 62
5079 14:44:43.908475 [CA 2] Center 35 (5~66) winsize 62
5080 14:44:43.911935 [CA 3] Center 34 (4~65) winsize 62
5081 14:44:43.914863 [CA 4] Center 34 (4~65) winsize 62
5082 14:44:43.918505 [CA 5] Center 33 (3~64) winsize 62
5083 14:44:43.918576
5084 14:44:43.921696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5085 14:44:43.921765
5086 14:44:43.925347 [CATrainingPosCal] consider 1 rank data
5087 14:44:43.928619 u2DelayCellTimex100 = 270/100 ps
5088 14:44:43.931466 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5089 14:44:43.934808 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5090 14:44:43.938257 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5091 14:44:43.942012 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5092 14:44:43.944963 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5093 14:44:43.948260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 14:44:43.951659
5095 14:44:43.955033 CA PerBit enable=1, Macro0, CA PI delay=33
5096 14:44:43.955102
5097 14:44:43.958326 [CBTSetCACLKResult] CA Dly = 33
5098 14:44:43.958393 CS Dly: 7 (0~38)
5099 14:44:43.958454 ==
5100 14:44:43.962009 Dram Type= 6, Freq= 0, CH_0, rank 1
5101 14:44:43.965266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 14:44:43.965336 ==
5103 14:44:43.971819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 14:44:43.978514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5105 14:44:43.982043 [CA 0] Center 38 (8~69) winsize 62
5106 14:44:43.985069 [CA 1] Center 38 (8~69) winsize 62
5107 14:44:43.988261 [CA 2] Center 36 (6~66) winsize 61
5108 14:44:43.991611 [CA 3] Center 35 (5~66) winsize 62
5109 14:44:43.994937 [CA 4] Center 34 (4~65) winsize 62
5110 14:44:43.998427 [CA 5] Center 34 (4~65) winsize 62
5111 14:44:43.998502
5112 14:44:44.001902 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5113 14:44:44.001973
5114 14:44:44.004800 [CATrainingPosCal] consider 2 rank data
5115 14:44:44.008150 u2DelayCellTimex100 = 270/100 ps
5116 14:44:44.011706 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5117 14:44:44.014969 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5118 14:44:44.018101 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5119 14:44:44.021385 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5120 14:44:44.024841 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5121 14:44:44.031608 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5122 14:44:44.031687
5123 14:44:44.034705 CA PerBit enable=1, Macro0, CA PI delay=34
5124 14:44:44.034776
5125 14:44:44.038231 [CBTSetCACLKResult] CA Dly = 34
5126 14:44:44.038298 CS Dly: 7 (0~39)
5127 14:44:44.038361
5128 14:44:44.041627 ----->DramcWriteLeveling(PI) begin...
5129 14:44:44.041697 ==
5130 14:44:44.044766 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 14:44:44.051316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 14:44:44.051393 ==
5133 14:44:44.054567 Write leveling (Byte 0): 33 => 33
5134 14:44:44.054637 Write leveling (Byte 1): 33 => 33
5135 14:44:44.058239 DramcWriteLeveling(PI) end<-----
5136 14:44:44.058305
5137 14:44:44.058369 ==
5138 14:44:44.061417 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 14:44:44.067993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 14:44:44.068069 ==
5141 14:44:44.071090 [Gating] SW mode calibration
5142 14:44:44.078211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5143 14:44:44.081257 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5144 14:44:44.088048 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5145 14:44:44.091175 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 14:44:44.094363 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 14:44:44.101070 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 14:44:44.104398 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 14:44:44.107697 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 14:44:44.114265 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5151 14:44:44.117631 0 14 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
5152 14:44:44.121228 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5153 14:44:44.127773 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 14:44:44.130941 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 14:44:44.134664 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 14:44:44.137607 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 14:44:44.144351 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5158 14:44:44.147637 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5159 14:44:44.151144 0 15 28 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
5160 14:44:44.157703 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 14:44:44.160982 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 14:44:44.164409 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 14:44:44.170771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 14:44:44.174247 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 14:44:44.177805 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 14:44:44.184266 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5167 14:44:44.187681 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5168 14:44:44.190820 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5169 14:44:44.197705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5170 14:44:44.200750 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 14:44:44.204491 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 14:44:44.210815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 14:44:44.214069 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 14:44:44.217486 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 14:44:44.224037 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 14:44:44.227259 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 14:44:44.230870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 14:44:44.237198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 14:44:44.240879 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 14:44:44.244117 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 14:44:44.250815 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 14:44:44.254017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5183 14:44:44.257726 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 14:44:44.260941 Total UI for P1: 0, mck2ui 16
5185 14:44:44.264010 best dqsien dly found for B0: ( 1, 2, 24)
5186 14:44:44.267359 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 14:44:44.270642 Total UI for P1: 0, mck2ui 16
5188 14:44:44.274634 best dqsien dly found for B1: ( 1, 2, 28)
5189 14:44:44.277579 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5190 14:44:44.283915 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5191 14:44:44.283989
5192 14:44:44.287311 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5193 14:44:44.290547 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5194 14:44:44.293904 [Gating] SW calibration Done
5195 14:44:44.293973 ==
5196 14:44:44.297206 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 14:44:44.300586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 14:44:44.300671 ==
5199 14:44:44.300739 RX Vref Scan: 0
5200 14:44:44.304104
5201 14:44:44.304188 RX Vref 0 -> 0, step: 1
5202 14:44:44.304255
5203 14:44:44.307037 RX Delay -80 -> 252, step: 8
5204 14:44:44.310430 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5205 14:44:44.316993 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5206 14:44:44.320714 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5207 14:44:44.323985 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5208 14:44:44.327155 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5209 14:44:44.330319 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5210 14:44:44.333574 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5211 14:44:44.340571 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5212 14:44:44.343821 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5213 14:44:44.347126 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5214 14:44:44.350570 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5215 14:44:44.353707 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5216 14:44:44.356970 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5217 14:44:44.363827 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5218 14:44:44.366900 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5219 14:44:44.370065 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5220 14:44:44.370149 ==
5221 14:44:44.373477 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 14:44:44.376726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 14:44:44.376810 ==
5224 14:44:44.380204 DQS Delay:
5225 14:44:44.380277 DQS0 = 0, DQS1 = 0
5226 14:44:44.380341 DQM Delay:
5227 14:44:44.383575 DQM0 = 106, DQM1 = 90
5228 14:44:44.383659 DQ Delay:
5229 14:44:44.386996 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5230 14:44:44.390205 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5231 14:44:44.393735 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5232 14:44:44.397077 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5233 14:44:44.397161
5234 14:44:44.397227
5235 14:44:44.400049 ==
5236 14:44:44.400152 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 14:44:44.406686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 14:44:44.406770 ==
5239 14:44:44.406835
5240 14:44:44.406894
5241 14:44:44.409897 TX Vref Scan disable
5242 14:44:44.409980 == TX Byte 0 ==
5243 14:44:44.413421 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5244 14:44:44.420161 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5245 14:44:44.420243 == TX Byte 1 ==
5246 14:44:44.423299 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5247 14:44:44.429928 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5248 14:44:44.430011 ==
5249 14:44:44.433511 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 14:44:44.436731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 14:44:44.436814 ==
5252 14:44:44.436880
5253 14:44:44.436939
5254 14:44:44.440090 TX Vref Scan disable
5255 14:44:44.443225 == TX Byte 0 ==
5256 14:44:44.446503 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5257 14:44:44.449897 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5258 14:44:44.453297 == TX Byte 1 ==
5259 14:44:44.456674 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5260 14:44:44.459869 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5261 14:44:44.459952
5262 14:44:44.460017 [DATLAT]
5263 14:44:44.463455 Freq=933, CH0 RK0
5264 14:44:44.463537
5265 14:44:44.463602 DATLAT Default: 0xd
5266 14:44:44.466697 0, 0xFFFF, sum = 0
5267 14:44:44.469956 1, 0xFFFF, sum = 0
5268 14:44:44.470040 2, 0xFFFF, sum = 0
5269 14:44:44.473394 3, 0xFFFF, sum = 0
5270 14:44:44.473478 4, 0xFFFF, sum = 0
5271 14:44:44.476610 5, 0xFFFF, sum = 0
5272 14:44:44.476693 6, 0xFFFF, sum = 0
5273 14:44:44.479988 7, 0xFFFF, sum = 0
5274 14:44:44.480071 8, 0xFFFF, sum = 0
5275 14:44:44.483206 9, 0xFFFF, sum = 0
5276 14:44:44.483290 10, 0x0, sum = 1
5277 14:44:44.486401 11, 0x0, sum = 2
5278 14:44:44.486484 12, 0x0, sum = 3
5279 14:44:44.489686 13, 0x0, sum = 4
5280 14:44:44.489770 best_step = 11
5281 14:44:44.489835
5282 14:44:44.489894 ==
5283 14:44:44.493635 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 14:44:44.496524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 14:44:44.496643 ==
5286 14:44:44.499921 RX Vref Scan: 1
5287 14:44:44.500003
5288 14:44:44.503057 RX Vref 0 -> 0, step: 1
5289 14:44:44.503139
5290 14:44:44.503204 RX Delay -53 -> 252, step: 4
5291 14:44:44.503264
5292 14:44:44.506645 Set Vref, RX VrefLevel [Byte0]: 57
5293 14:44:44.509658 [Byte1]: 49
5294 14:44:44.514421
5295 14:44:44.514503 Final RX Vref Byte 0 = 57 to rank0
5296 14:44:44.517797 Final RX Vref Byte 1 = 49 to rank0
5297 14:44:44.521238 Final RX Vref Byte 0 = 57 to rank1
5298 14:44:44.524581 Final RX Vref Byte 1 = 49 to rank1==
5299 14:44:44.527843 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 14:44:44.534434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 14:44:44.534517 ==
5302 14:44:44.534583 DQS Delay:
5303 14:44:44.534685 DQS0 = 0, DQS1 = 0
5304 14:44:44.537576 DQM Delay:
5305 14:44:44.537658 DQM0 = 107, DQM1 = 91
5306 14:44:44.540775 DQ Delay:
5307 14:44:44.544150 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5308 14:44:44.547460 DQ4 =106, DQ5 =98, DQ6 =120, DQ7 =114
5309 14:44:44.550726 DQ8 =84, DQ9 =76, DQ10 =92, DQ11 =90
5310 14:44:44.554432 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =100
5311 14:44:44.554515
5312 14:44:44.554581
5313 14:44:44.561032 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5314 14:44:44.564350 CH0 RK0: MR19=505, MR18=231F
5315 14:44:44.570753 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5316 14:44:44.570839
5317 14:44:44.574458 ----->DramcWriteLeveling(PI) begin...
5318 14:44:44.574547 ==
5319 14:44:44.577612 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 14:44:44.580889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 14:44:44.580973 ==
5322 14:44:44.584185 Write leveling (Byte 0): 34 => 34
5323 14:44:44.587533 Write leveling (Byte 1): 31 => 31
5324 14:44:44.591197 DramcWriteLeveling(PI) end<-----
5325 14:44:44.591279
5326 14:44:44.591344 ==
5327 14:44:44.594455 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 14:44:44.597820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 14:44:44.600950 ==
5330 14:44:44.601033 [Gating] SW mode calibration
5331 14:44:44.611179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5332 14:44:44.614402 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5333 14:44:44.617554 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 14:44:44.624483 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 14:44:44.627633 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 14:44:44.630794 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 14:44:44.637660 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 14:44:44.641043 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 14:44:44.644215 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (0 0) (1 1)
5340 14:44:44.650663 0 14 28 | B1->B0 | 2e2e 2727 | 1 0 | (1 0) (0 0)
5341 14:44:44.654255 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 14:44:44.657686 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 14:44:44.664326 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 14:44:44.667671 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 14:44:44.670783 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 14:44:44.677353 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 14:44:44.680978 0 15 24 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (0 0)
5348 14:44:44.684139 0 15 28 | B1->B0 | 3b3a 4141 | 1 0 | (0 0) (0 0)
5349 14:44:44.687563 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 14:44:44.694137 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 14:44:44.697501 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 14:44:44.700894 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 14:44:44.707447 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 14:44:44.710929 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 14:44:44.714236 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 14:44:44.720767 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5357 14:44:44.724148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5358 14:44:44.727244 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 14:44:44.734169 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 14:44:44.737565 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 14:44:44.740583 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 14:44:44.747507 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 14:44:44.750746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 14:44:44.753908 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 14:44:44.760555 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 14:44:44.763714 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 14:44:44.767021 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 14:44:44.773643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 14:44:44.777254 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 14:44:44.780641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 14:44:44.787064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 14:44:44.790363 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5373 14:44:44.793987 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 14:44:44.797137 Total UI for P1: 0, mck2ui 16
5375 14:44:44.800429 best dqsien dly found for B0: ( 1, 2, 28)
5376 14:44:44.803943 Total UI for P1: 0, mck2ui 16
5377 14:44:44.807178 best dqsien dly found for B1: ( 1, 2, 28)
5378 14:44:44.810502 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5379 14:44:44.813906 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5380 14:44:44.813975
5381 14:44:44.817316 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5382 14:44:44.823950 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5383 14:44:44.824052 [Gating] SW calibration Done
5384 14:44:44.824129 ==
5385 14:44:44.827097 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 14:44:44.834145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 14:44:44.834246 ==
5388 14:44:44.834331 RX Vref Scan: 0
5389 14:44:44.834420
5390 14:44:44.837404 RX Vref 0 -> 0, step: 1
5391 14:44:44.837498
5392 14:44:44.840439 RX Delay -80 -> 252, step: 8
5393 14:44:44.843802 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5394 14:44:44.847098 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5395 14:44:44.850427 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5396 14:44:44.853778 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5397 14:44:44.860166 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5398 14:44:44.863749 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5399 14:44:44.867135 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5400 14:44:44.870598 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5401 14:44:44.874051 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5402 14:44:44.880065 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5403 14:44:44.883551 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5404 14:44:44.886735 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5405 14:44:44.890006 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5406 14:44:44.893541 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5407 14:44:44.896635 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5408 14:44:44.903390 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5409 14:44:44.903823 ==
5410 14:44:44.906853 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 14:44:44.910433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 14:44:44.910876 ==
5413 14:44:44.911197 DQS Delay:
5414 14:44:44.913943 DQS0 = 0, DQS1 = 0
5415 14:44:44.914353 DQM Delay:
5416 14:44:44.916660 DQM0 = 104, DQM1 = 91
5417 14:44:44.917055 DQ Delay:
5418 14:44:44.919899 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5419 14:44:44.923293 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =111
5420 14:44:44.926576 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5421 14:44:44.930258 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5422 14:44:44.930667
5423 14:44:44.931015
5424 14:44:44.931430 ==
5425 14:44:44.933317 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 14:44:44.936625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 14:44:44.940164 ==
5428 14:44:44.940684
5429 14:44:44.941080
5430 14:44:44.941452 TX Vref Scan disable
5431 14:44:44.943388 == TX Byte 0 ==
5432 14:44:44.946785 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5433 14:44:44.950166 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5434 14:44:44.953642 == TX Byte 1 ==
5435 14:44:44.956450 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5436 14:44:44.959429 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5437 14:44:44.963082 ==
5438 14:44:44.963166 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 14:44:44.969693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 14:44:44.969776 ==
5441 14:44:44.969843
5442 14:44:44.969903
5443 14:44:44.972837 TX Vref Scan disable
5444 14:44:44.972921 == TX Byte 0 ==
5445 14:44:44.979497 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5446 14:44:44.982690 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5447 14:44:44.982787 == TX Byte 1 ==
5448 14:44:44.989528 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5449 14:44:44.992639 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5450 14:44:44.992783
5451 14:44:44.992917 [DATLAT]
5452 14:44:44.995899 Freq=933, CH0 RK1
5453 14:44:44.996024
5454 14:44:44.996121 DATLAT Default: 0xb
5455 14:44:44.999283 0, 0xFFFF, sum = 0
5456 14:44:44.999426 1, 0xFFFF, sum = 0
5457 14:44:45.002829 2, 0xFFFF, sum = 0
5458 14:44:45.002970 3, 0xFFFF, sum = 0
5459 14:44:45.006305 4, 0xFFFF, sum = 0
5460 14:44:45.006462 5, 0xFFFF, sum = 0
5461 14:44:45.009587 6, 0xFFFF, sum = 0
5462 14:44:45.009766 7, 0xFFFF, sum = 0
5463 14:44:45.012570 8, 0xFFFF, sum = 0
5464 14:44:45.016043 9, 0xFFFF, sum = 0
5465 14:44:45.016251 10, 0x0, sum = 1
5466 14:44:45.016417 11, 0x0, sum = 2
5467 14:44:45.019489 12, 0x0, sum = 3
5468 14:44:45.019737 13, 0x0, sum = 4
5469 14:44:45.022910 best_step = 11
5470 14:44:45.023153
5471 14:44:45.023366 ==
5472 14:44:45.025978 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 14:44:45.029652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 14:44:45.030050 ==
5475 14:44:45.032984 RX Vref Scan: 0
5476 14:44:45.033431
5477 14:44:45.033883 RX Vref 0 -> 0, step: 1
5478 14:44:45.034209
5479 14:44:45.036492 RX Delay -53 -> 252, step: 4
5480 14:44:45.043277 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5481 14:44:45.046969 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5482 14:44:45.049966 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5483 14:44:45.053301 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5484 14:44:45.056648 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5485 14:44:45.063399 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5486 14:44:45.066709 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5487 14:44:45.070246 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5488 14:44:45.073468 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5489 14:44:45.076957 iDelay=199, Bit 9, Center 82 (3 ~ 162) 160
5490 14:44:45.079826 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5491 14:44:45.087060 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5492 14:44:45.089974 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5493 14:44:45.093227 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5494 14:44:45.096483 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5495 14:44:45.099805 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5496 14:44:45.103284 ==
5497 14:44:45.106839 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 14:44:45.109880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 14:44:45.110312 ==
5500 14:44:45.110653 DQS Delay:
5501 14:44:45.113752 DQS0 = 0, DQS1 = 0
5502 14:44:45.114178 DQM Delay:
5503 14:44:45.116952 DQM0 = 104, DQM1 = 93
5504 14:44:45.117381 DQ Delay:
5505 14:44:45.120257 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5506 14:44:45.123536 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5507 14:44:45.126866 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =92
5508 14:44:45.130146 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =100
5509 14:44:45.130575
5510 14:44:45.130914
5511 14:44:45.140063 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5512 14:44:45.140526 CH0 RK1: MR19=505, MR18=2C0D
5513 14:44:45.146403 CH0_RK1: MR19=0x505, MR18=0x2C0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5514 14:44:45.150184 [RxdqsGatingPostProcess] freq 933
5515 14:44:45.156494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 14:44:45.159828 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 14:44:45.163118 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 14:44:45.166846 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 14:44:45.170028 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 14:44:45.170454 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 14:44:45.173012 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 14:44:45.176395 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 14:44:45.179745 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 14:44:45.183473 Pre-setting of DQS Precalculation
5525 14:44:45.189991 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 14:44:45.190420 ==
5527 14:44:45.193353 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 14:44:45.196391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 14:44:45.196859 ==
5530 14:44:45.203171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 14:44:45.210085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5532 14:44:45.213107 [CA 0] Center 37 (7~68) winsize 62
5533 14:44:45.216385 [CA 1] Center 37 (7~68) winsize 62
5534 14:44:45.219650 [CA 2] Center 35 (5~65) winsize 61
5535 14:44:45.222906 [CA 3] Center 35 (5~65) winsize 61
5536 14:44:45.226731 [CA 4] Center 35 (5~65) winsize 61
5537 14:44:45.227158 [CA 5] Center 34 (4~64) winsize 61
5538 14:44:45.229498
5539 14:44:45.232696 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5540 14:44:45.232780
5541 14:44:45.236133 [CATrainingPosCal] consider 1 rank data
5542 14:44:45.239513 u2DelayCellTimex100 = 270/100 ps
5543 14:44:45.242854 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5544 14:44:45.246089 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5545 14:44:45.249425 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5546 14:44:45.252432 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5547 14:44:45.256145 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5548 14:44:45.259653 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5549 14:44:45.259848
5550 14:44:45.262904 CA PerBit enable=1, Macro0, CA PI delay=34
5551 14:44:45.263096
5552 14:44:45.266245 [CBTSetCACLKResult] CA Dly = 34
5553 14:44:45.269551 CS Dly: 6 (0~37)
5554 14:44:45.269794 ==
5555 14:44:45.272684 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 14:44:45.275708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 14:44:45.275863 ==
5558 14:44:45.282854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 14:44:45.289175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 14:44:45.292761 [CA 0] Center 37 (7~68) winsize 62
5561 14:44:45.296016 [CA 1] Center 38 (8~68) winsize 61
5562 14:44:45.299577 [CA 2] Center 36 (6~66) winsize 61
5563 14:44:45.302816 [CA 3] Center 35 (5~65) winsize 61
5564 14:44:45.306328 [CA 4] Center 35 (6~65) winsize 60
5565 14:44:45.309384 [CA 5] Center 34 (5~64) winsize 60
5566 14:44:45.309857
5567 14:44:45.312639 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 14:44:45.313110
5569 14:44:45.315946 [CATrainingPosCal] consider 2 rank data
5570 14:44:45.319747 u2DelayCellTimex100 = 270/100 ps
5571 14:44:45.322993 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5572 14:44:45.326174 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5573 14:44:45.329337 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5574 14:44:45.333058 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5575 14:44:45.335947 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5576 14:44:45.339338 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5577 14:44:45.339803
5578 14:44:45.342683 CA PerBit enable=1, Macro0, CA PI delay=34
5579 14:44:45.343150
5580 14:44:45.345892 [CBTSetCACLKResult] CA Dly = 34
5581 14:44:45.349136 CS Dly: 7 (0~39)
5582 14:44:45.349598
5583 14:44:45.352879 ----->DramcWriteLeveling(PI) begin...
5584 14:44:45.353351 ==
5585 14:44:45.355932 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 14:44:45.359355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 14:44:45.359924 ==
5588 14:44:45.363089 Write leveling (Byte 0): 26 => 26
5589 14:44:45.365855 Write leveling (Byte 1): 27 => 27
5590 14:44:45.369350 DramcWriteLeveling(PI) end<-----
5591 14:44:45.369951
5592 14:44:45.370330 ==
5593 14:44:45.372764 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 14:44:45.375790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 14:44:45.379321 ==
5596 14:44:45.379886 [Gating] SW mode calibration
5597 14:44:45.385588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 14:44:45.392570 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 14:44:45.395789 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 14:44:45.402223 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 14:44:45.405735 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 14:44:45.408973 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 14:44:45.415722 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 14:44:45.418960 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 14:44:45.422357 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 0)
5606 14:44:45.429020 0 14 28 | B1->B0 | 2424 2424 | 0 0 | (1 0) (0 0)
5607 14:44:45.432122 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 14:44:45.435636 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 14:44:45.442436 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 14:44:45.445213 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 14:44:45.448589 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 14:44:45.455789 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 14:44:45.458555 0 15 24 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
5614 14:44:45.462058 0 15 28 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
5615 14:44:45.465250 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 14:44:45.472309 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 14:44:45.475493 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 14:44:45.478732 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 14:44:45.485301 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 14:44:45.488910 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5621 14:44:45.491838 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5622 14:44:45.498832 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 14:44:45.502122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 14:44:45.505333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 14:44:45.512035 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 14:44:45.515542 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 14:44:45.518799 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 14:44:45.525440 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 14:44:45.528709 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 14:44:45.531989 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 14:44:45.538667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 14:44:45.542293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 14:44:45.545561 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 14:44:45.552141 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 14:44:45.555439 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 14:44:45.558649 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5637 14:44:45.565385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5638 14:44:45.569002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5639 14:44:45.571955 Total UI for P1: 0, mck2ui 16
5640 14:44:45.575239 best dqsien dly found for B0: ( 1, 2, 22)
5641 14:44:45.578587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 14:44:45.581880 Total UI for P1: 0, mck2ui 16
5643 14:44:45.585068 best dqsien dly found for B1: ( 1, 2, 28)
5644 14:44:45.588754 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5645 14:44:45.592312 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5646 14:44:45.592832
5647 14:44:45.595502 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5648 14:44:45.598352 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5649 14:44:45.601867 [Gating] SW calibration Done
5650 14:44:45.602289 ==
5651 14:44:45.605074 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 14:44:45.612093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 14:44:45.612838 ==
5654 14:44:45.613359 RX Vref Scan: 0
5655 14:44:45.613738
5656 14:44:45.615249 RX Vref 0 -> 0, step: 1
5657 14:44:45.615671
5658 14:44:45.618608 RX Delay -80 -> 252, step: 8
5659 14:44:45.621740 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5660 14:44:45.624899 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5661 14:44:45.628648 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5662 14:44:45.631926 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5663 14:44:45.635322 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5664 14:44:45.641652 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5665 14:44:45.645415 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5666 14:44:45.648415 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5667 14:44:45.651811 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5668 14:44:45.655113 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5669 14:44:45.661914 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5670 14:44:45.665198 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5671 14:44:45.668408 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5672 14:44:45.671824 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5673 14:44:45.674989 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5674 14:44:45.678113 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5675 14:44:45.681610 ==
5676 14:44:45.684826 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 14:44:45.688652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 14:44:45.689076 ==
5679 14:44:45.689409 DQS Delay:
5680 14:44:45.691650 DQS0 = 0, DQS1 = 0
5681 14:44:45.692071 DQM Delay:
5682 14:44:45.695113 DQM0 = 102, DQM1 = 95
5683 14:44:45.695533 DQ Delay:
5684 14:44:45.698320 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5685 14:44:45.701603 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5686 14:44:45.705196 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5687 14:44:45.708149 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5688 14:44:45.708591
5689 14:44:45.708933
5690 14:44:45.709244 ==
5691 14:44:45.711383 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 14:44:45.715166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 14:44:45.715588 ==
5694 14:44:45.718416
5695 14:44:45.718836
5696 14:44:45.719170 TX Vref Scan disable
5697 14:44:45.721478 == TX Byte 0 ==
5698 14:44:45.724867 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5699 14:44:45.728188 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5700 14:44:45.731327 == TX Byte 1 ==
5701 14:44:45.734871 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 14:44:45.738159 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 14:44:45.738642 ==
5704 14:44:45.741318 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 14:44:45.747868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 14:44:45.748337 ==
5707 14:44:45.748722
5708 14:44:45.749046
5709 14:44:45.749347 TX Vref Scan disable
5710 14:44:45.752449 == TX Byte 0 ==
5711 14:44:45.755824 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5712 14:44:45.759378 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5713 14:44:45.762583 == TX Byte 1 ==
5714 14:44:45.765662 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5715 14:44:45.772280 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5716 14:44:45.772746
5717 14:44:45.773094 [DATLAT]
5718 14:44:45.773412 Freq=933, CH1 RK0
5719 14:44:45.773717
5720 14:44:45.775613 DATLAT Default: 0xd
5721 14:44:45.776041 0, 0xFFFF, sum = 0
5722 14:44:45.778836 1, 0xFFFF, sum = 0
5723 14:44:45.779290 2, 0xFFFF, sum = 0
5724 14:44:45.782009 3, 0xFFFF, sum = 0
5725 14:44:45.785489 4, 0xFFFF, sum = 0
5726 14:44:45.785916 5, 0xFFFF, sum = 0
5727 14:44:45.788798 6, 0xFFFF, sum = 0
5728 14:44:45.789226 7, 0xFFFF, sum = 0
5729 14:44:45.792156 8, 0xFFFF, sum = 0
5730 14:44:45.792688 9, 0xFFFF, sum = 0
5731 14:44:45.795437 10, 0x0, sum = 1
5732 14:44:45.795865 11, 0x0, sum = 2
5733 14:44:45.798663 12, 0x0, sum = 3
5734 14:44:45.799088 13, 0x0, sum = 4
5735 14:44:45.799458 best_step = 11
5736 14:44:45.799775
5737 14:44:45.802361 ==
5738 14:44:45.805789 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 14:44:45.808667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 14:44:45.809098 ==
5741 14:44:45.809438 RX Vref Scan: 1
5742 14:44:45.809754
5743 14:44:45.812037 RX Vref 0 -> 0, step: 1
5744 14:44:45.812460
5745 14:44:45.815464 RX Delay -53 -> 252, step: 4
5746 14:44:45.815888
5747 14:44:45.818701 Set Vref, RX VrefLevel [Byte0]: 52
5748 14:44:45.822070 [Byte1]: 52
5749 14:44:45.822497
5750 14:44:45.825399 Final RX Vref Byte 0 = 52 to rank0
5751 14:44:45.828585 Final RX Vref Byte 1 = 52 to rank0
5752 14:44:45.832035 Final RX Vref Byte 0 = 52 to rank1
5753 14:44:45.835173 Final RX Vref Byte 1 = 52 to rank1==
5754 14:44:45.838660 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 14:44:45.841908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 14:44:45.842336 ==
5757 14:44:45.845166 DQS Delay:
5758 14:44:45.845637 DQS0 = 0, DQS1 = 0
5759 14:44:45.848535 DQM Delay:
5760 14:44:45.848984 DQM0 = 103, DQM1 = 96
5761 14:44:45.851693 DQ Delay:
5762 14:44:45.855340 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5763 14:44:45.858450 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5764 14:44:45.861696 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5765 14:44:45.865017 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =104
5766 14:44:45.865442
5767 14:44:45.865822
5768 14:44:45.871740 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5769 14:44:45.875334 CH1 RK0: MR19=505, MR18=1D35
5770 14:44:45.882085 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5771 14:44:45.882532
5772 14:44:45.884956 ----->DramcWriteLeveling(PI) begin...
5773 14:44:45.885394 ==
5774 14:44:45.888997 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 14:44:45.892473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 14:44:45.893084 ==
5777 14:44:45.895581 Write leveling (Byte 0): 28 => 28
5778 14:44:45.899023 Write leveling (Byte 1): 28 => 28
5779 14:44:45.902090 DramcWriteLeveling(PI) end<-----
5780 14:44:45.902567
5781 14:44:45.902943 ==
5782 14:44:45.905390 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 14:44:45.908789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 14:44:45.909355 ==
5785 14:44:45.912153 [Gating] SW mode calibration
5786 14:44:45.918522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 14:44:45.925497 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 14:44:45.928768 0 14 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5789 14:44:45.935089 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 14:44:45.938720 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 14:44:45.942127 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 14:44:45.948453 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 14:44:45.951838 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 14:44:45.955361 0 14 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
5795 14:44:45.961757 0 14 28 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 1)
5796 14:44:45.964826 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 14:44:45.969059 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 14:44:45.971721 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 14:44:45.978253 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 14:44:45.981555 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 14:44:45.984921 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 14:44:45.991641 0 15 24 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
5803 14:44:45.995274 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
5804 14:44:45.998389 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5805 14:44:46.004811 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 14:44:46.008842 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 14:44:46.012100 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 14:44:46.018239 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 14:44:46.021591 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 14:44:46.025101 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5811 14:44:46.031796 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5812 14:44:46.035143 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5813 14:44:46.038036 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 14:44:46.045003 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 14:44:46.048385 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 14:44:46.051626 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 14:44:46.058220 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 14:44:46.061755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 14:44:46.065250 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 14:44:46.068421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 14:44:46.075424 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 14:44:46.078214 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 14:44:46.081352 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 14:44:46.088587 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 14:44:46.091879 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 14:44:46.094721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5827 14:44:46.101936 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5828 14:44:46.104993 Total UI for P1: 0, mck2ui 16
5829 14:44:46.108163 best dqsien dly found for B1: ( 1, 2, 24)
5830 14:44:46.111696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 14:44:46.114917 Total UI for P1: 0, mck2ui 16
5832 14:44:46.118135 best dqsien dly found for B0: ( 1, 2, 26)
5833 14:44:46.121809 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5834 14:44:46.125233 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5835 14:44:46.125797
5836 14:44:46.128494 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5837 14:44:46.131761 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5838 14:44:46.134655 [Gating] SW calibration Done
5839 14:44:46.135121 ==
5840 14:44:46.138198 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 14:44:46.141788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 14:44:46.145082 ==
5843 14:44:46.145648 RX Vref Scan: 0
5844 14:44:46.146022
5845 14:44:46.148782 RX Vref 0 -> 0, step: 1
5846 14:44:46.149399
5847 14:44:46.151406 RX Delay -80 -> 252, step: 8
5848 14:44:46.155085 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5849 14:44:46.157983 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5850 14:44:46.161498 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5851 14:44:46.164741 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5852 14:44:46.171315 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5853 14:44:46.174588 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5854 14:44:46.178027 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5855 14:44:46.181755 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5856 14:44:46.184896 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5857 14:44:46.188340 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5858 14:44:46.194692 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5859 14:44:46.198567 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5860 14:44:46.201379 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5861 14:44:46.205043 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5862 14:44:46.208020 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5863 14:44:46.214910 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5864 14:44:46.215483 ==
5865 14:44:46.217734 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 14:44:46.221267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 14:44:46.221836 ==
5868 14:44:46.222214 DQS Delay:
5869 14:44:46.224536 DQS0 = 0, DQS1 = 0
5870 14:44:46.225138 DQM Delay:
5871 14:44:46.227680 DQM0 = 103, DQM1 = 94
5872 14:44:46.228251 DQ Delay:
5873 14:44:46.231086 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5874 14:44:46.234747 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5875 14:44:46.237523 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =91
5876 14:44:46.241089 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5877 14:44:46.241656
5878 14:44:46.242033
5879 14:44:46.242378 ==
5880 14:44:46.244099 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 14:44:46.251049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 14:44:46.251676 ==
5883 14:44:46.252056
5884 14:44:46.252404
5885 14:44:46.252801 TX Vref Scan disable
5886 14:44:46.254155 == TX Byte 0 ==
5887 14:44:46.257307 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5888 14:44:46.260428 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5889 14:44:46.263709 == TX Byte 1 ==
5890 14:44:46.266855 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 14:44:46.270538 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 14:44:46.273924 ==
5893 14:44:46.277306 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 14:44:46.280369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 14:44:46.280477 ==
5896 14:44:46.280559
5897 14:44:46.280631
5898 14:44:46.283795 TX Vref Scan disable
5899 14:44:46.283889 == TX Byte 0 ==
5900 14:44:46.290409 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5901 14:44:46.293672 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5902 14:44:46.293835 == TX Byte 1 ==
5903 14:44:46.300651 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5904 14:44:46.303850 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5905 14:44:46.304067
5906 14:44:46.304186 [DATLAT]
5907 14:44:46.307256 Freq=933, CH1 RK1
5908 14:44:46.307493
5909 14:44:46.307626 DATLAT Default: 0xb
5910 14:44:46.310413 0, 0xFFFF, sum = 0
5911 14:44:46.310679 1, 0xFFFF, sum = 0
5912 14:44:46.313567 2, 0xFFFF, sum = 0
5913 14:44:46.313750 3, 0xFFFF, sum = 0
5914 14:44:46.316977 4, 0xFFFF, sum = 0
5915 14:44:46.317272 5, 0xFFFF, sum = 0
5916 14:44:46.320511 6, 0xFFFF, sum = 0
5917 14:44:46.323926 7, 0xFFFF, sum = 0
5918 14:44:46.324257 8, 0xFFFF, sum = 0
5919 14:44:46.327314 9, 0xFFFF, sum = 0
5920 14:44:46.327719 10, 0x0, sum = 1
5921 14:44:46.327978 11, 0x0, sum = 2
5922 14:44:46.330488 12, 0x0, sum = 3
5923 14:44:46.331000 13, 0x0, sum = 4
5924 14:44:46.333701 best_step = 11
5925 14:44:46.334193
5926 14:44:46.334512 ==
5927 14:44:46.337107 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 14:44:46.340339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 14:44:46.340930 ==
5930 14:44:46.343750 RX Vref Scan: 0
5931 14:44:46.344317
5932 14:44:46.347405 RX Vref 0 -> 0, step: 1
5933 14:44:46.347968
5934 14:44:46.348338 RX Delay -61 -> 252, step: 4
5935 14:44:46.354715 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5936 14:44:46.358116 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5937 14:44:46.361097 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5938 14:44:46.364751 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5939 14:44:46.368173 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5940 14:44:46.374321 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5941 14:44:46.377878 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5942 14:44:46.381123 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5943 14:44:46.384435 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5944 14:44:46.387846 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5945 14:44:46.390906 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5946 14:44:46.397660 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5947 14:44:46.400882 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5948 14:44:46.404725 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5949 14:44:46.408071 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5950 14:44:46.414742 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5951 14:44:46.415308 ==
5952 14:44:46.417753 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 14:44:46.421493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 14:44:46.422058 ==
5955 14:44:46.422434 DQS Delay:
5956 14:44:46.424193 DQS0 = 0, DQS1 = 0
5957 14:44:46.424695 DQM Delay:
5958 14:44:46.427840 DQM0 = 105, DQM1 = 97
5959 14:44:46.428310 DQ Delay:
5960 14:44:46.431167 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104
5961 14:44:46.434214 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5962 14:44:46.437846 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5963 14:44:46.441194 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5964 14:44:46.441618
5965 14:44:46.441954
5966 14:44:46.451179 [DQSOSCAuto] RK1, (LSB)MR18= 0x2703, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5967 14:44:46.451774 CH1 RK1: MR19=505, MR18=2703
5968 14:44:46.457840 CH1_RK1: MR19=0x505, MR18=0x2703, DQSOSC=409, MR23=63, INC=64, DEC=43
5969 14:44:46.460981 [RxdqsGatingPostProcess] freq 933
5970 14:44:46.467930 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 14:44:46.471113 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 14:44:46.474179 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 14:44:46.477462 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 14:44:46.480930 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 14:44:46.484161 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 14:44:46.484728 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 14:44:46.487729 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 14:44:46.490741 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 14:44:46.493991 Pre-setting of DQS Precalculation
5980 14:44:46.500740 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 14:44:46.507904 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 14:44:46.514409 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 14:44:46.514998
5984 14:44:46.515374
5985 14:44:46.517397 [Calibration Summary] 1866 Mbps
5986 14:44:46.517864 CH 0, Rank 0
5987 14:44:46.520744 SW Impedance : PASS
5988 14:44:46.524360 DUTY Scan : NO K
5989 14:44:46.524930 ZQ Calibration : PASS
5990 14:44:46.527560 Jitter Meter : NO K
5991 14:44:46.530861 CBT Training : PASS
5992 14:44:46.531428 Write leveling : PASS
5993 14:44:46.534002 RX DQS gating : PASS
5994 14:44:46.537290 RX DQ/DQS(RDDQC) : PASS
5995 14:44:46.537759 TX DQ/DQS : PASS
5996 14:44:46.540398 RX DATLAT : PASS
5997 14:44:46.544193 RX DQ/DQS(Engine): PASS
5998 14:44:46.544641 TX OE : NO K
5999 14:44:46.547651 All Pass.
6000 14:44:46.548173
6001 14:44:46.548512 CH 0, Rank 1
6002 14:44:46.550298 SW Impedance : PASS
6003 14:44:46.550721 DUTY Scan : NO K
6004 14:44:46.553593 ZQ Calibration : PASS
6005 14:44:46.557075 Jitter Meter : NO K
6006 14:44:46.557604 CBT Training : PASS
6007 14:44:46.560974 Write leveling : PASS
6008 14:44:46.563950 RX DQS gating : PASS
6009 14:44:46.564422 RX DQ/DQS(RDDQC) : PASS
6010 14:44:46.567443 TX DQ/DQS : PASS
6011 14:44:46.568017 RX DATLAT : PASS
6012 14:44:46.570531 RX DQ/DQS(Engine): PASS
6013 14:44:46.573887 TX OE : NO K
6014 14:44:46.574474 All Pass.
6015 14:44:46.574855
6016 14:44:46.575200 CH 1, Rank 0
6017 14:44:46.577001 SW Impedance : PASS
6018 14:44:46.580604 DUTY Scan : NO K
6019 14:44:46.581093 ZQ Calibration : PASS
6020 14:44:46.584012 Jitter Meter : NO K
6021 14:44:46.587793 CBT Training : PASS
6022 14:44:46.588368 Write leveling : PASS
6023 14:44:46.590216 RX DQS gating : PASS
6024 14:44:46.594061 RX DQ/DQS(RDDQC) : PASS
6025 14:44:46.594563 TX DQ/DQS : PASS
6026 14:44:46.597026 RX DATLAT : PASS
6027 14:44:46.600524 RX DQ/DQS(Engine): PASS
6028 14:44:46.601049 TX OE : NO K
6029 14:44:46.603732 All Pass.
6030 14:44:46.604248
6031 14:44:46.604797 CH 1, Rank 1
6032 14:44:46.607083 SW Impedance : PASS
6033 14:44:46.607511 DUTY Scan : NO K
6034 14:44:46.610433 ZQ Calibration : PASS
6035 14:44:46.611038 Jitter Meter : NO K
6036 14:44:46.613738 CBT Training : PASS
6037 14:44:46.617036 Write leveling : PASS
6038 14:44:46.617487 RX DQS gating : PASS
6039 14:44:46.620538 RX DQ/DQS(RDDQC) : PASS
6040 14:44:46.623899 TX DQ/DQS : PASS
6041 14:44:46.624328 RX DATLAT : PASS
6042 14:44:46.627242 RX DQ/DQS(Engine): PASS
6043 14:44:46.630390 TX OE : NO K
6044 14:44:46.630822 All Pass.
6045 14:44:46.631160
6046 14:44:46.633934 DramC Write-DBI off
6047 14:44:46.634359 PER_BANK_REFRESH: Hybrid Mode
6048 14:44:46.637001 TX_TRACKING: ON
6049 14:44:46.643688 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 14:44:46.650088 [FAST_K] Save calibration result to emmc
6051 14:44:46.654173 dramc_set_vcore_voltage set vcore to 650000
6052 14:44:46.654596 Read voltage for 400, 6
6053 14:44:46.657116 Vio18 = 0
6054 14:44:46.657539 Vcore = 650000
6055 14:44:46.657877 Vdram = 0
6056 14:44:46.660439 Vddq = 0
6057 14:44:46.660904 Vmddr = 0
6058 14:44:46.663403 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 14:44:46.670324 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 14:44:46.673612 MEM_TYPE=3, freq_sel=20
6061 14:44:46.676393 sv_algorithm_assistance_LP4_800
6062 14:44:46.680408 ============ PULL DRAM RESETB DOWN ============
6063 14:44:46.683291 ========== PULL DRAM RESETB DOWN end =========
6064 14:44:46.689909 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 14:44:46.693209 ===================================
6066 14:44:46.693630 LPDDR4 DRAM CONFIGURATION
6067 14:44:46.696503 ===================================
6068 14:44:46.700019 EX_ROW_EN[0] = 0x0
6069 14:44:46.700592 EX_ROW_EN[1] = 0x0
6070 14:44:46.702981 LP4Y_EN = 0x0
6071 14:44:46.703661 WORK_FSP = 0x0
6072 14:44:46.706288 WL = 0x2
6073 14:44:46.709501 RL = 0x2
6074 14:44:46.709955 BL = 0x2
6075 14:44:46.713079 RPST = 0x0
6076 14:44:46.713668 RD_PRE = 0x0
6077 14:44:46.716752 WR_PRE = 0x1
6078 14:44:46.717173 WR_PST = 0x0
6079 14:44:46.719639 DBI_WR = 0x0
6080 14:44:46.720060 DBI_RD = 0x0
6081 14:44:46.723197 OTF = 0x1
6082 14:44:46.726365 ===================================
6083 14:44:46.729773 ===================================
6084 14:44:46.730208 ANA top config
6085 14:44:46.732879 ===================================
6086 14:44:46.736408 DLL_ASYNC_EN = 0
6087 14:44:46.739894 ALL_SLAVE_EN = 1
6088 14:44:46.740317 NEW_RANK_MODE = 1
6089 14:44:46.743143 DLL_IDLE_MODE = 1
6090 14:44:46.746332 LP45_APHY_COMB_EN = 1
6091 14:44:46.749709 TX_ODT_DIS = 1
6092 14:44:46.750134 NEW_8X_MODE = 1
6093 14:44:46.752777 ===================================
6094 14:44:46.755941 ===================================
6095 14:44:46.759367 data_rate = 800
6096 14:44:46.762465 CKR = 1
6097 14:44:46.765902 DQ_P2S_RATIO = 4
6098 14:44:46.769404 ===================================
6099 14:44:46.772952 CA_P2S_RATIO = 4
6100 14:44:46.775599 DQ_CA_OPEN = 0
6101 14:44:46.778971 DQ_SEMI_OPEN = 1
6102 14:44:46.779091 CA_SEMI_OPEN = 1
6103 14:44:46.782452 CA_FULL_RATE = 0
6104 14:44:46.785638 DQ_CKDIV4_EN = 0
6105 14:44:46.788937 CA_CKDIV4_EN = 1
6106 14:44:46.792275 CA_PREDIV_EN = 0
6107 14:44:46.792376 PH8_DLY = 0
6108 14:44:46.796030 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 14:44:46.799183 DQ_AAMCK_DIV = 0
6110 14:44:46.802405 CA_AAMCK_DIV = 0
6111 14:44:46.805589 CA_ADMCK_DIV = 4
6112 14:44:46.809630 DQ_TRACK_CA_EN = 0
6113 14:44:46.809726 CA_PICK = 800
6114 14:44:46.812702 CA_MCKIO = 400
6115 14:44:46.815714 MCKIO_SEMI = 400
6116 14:44:46.819098 PLL_FREQ = 3016
6117 14:44:46.822873 DQ_UI_PI_RATIO = 32
6118 14:44:46.826029 CA_UI_PI_RATIO = 32
6119 14:44:46.829418 ===================================
6120 14:44:46.832612 ===================================
6121 14:44:46.835707 memory_type:LPDDR4
6122 14:44:46.836407 GP_NUM : 10
6123 14:44:46.839105 SRAM_EN : 1
6124 14:44:46.839798 MD32_EN : 0
6125 14:44:46.842390 ===================================
6126 14:44:46.846116 [ANA_INIT] >>>>>>>>>>>>>>
6127 14:44:46.849404 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 14:44:46.852650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 14:44:46.855704 ===================================
6130 14:44:46.858995 data_rate = 800,PCW = 0X7400
6131 14:44:46.862263 ===================================
6132 14:44:46.865873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 14:44:46.868796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 14:44:46.882267 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 14:44:46.885470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 14:44:46.889154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 14:44:46.892426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 14:44:46.895984 [ANA_INIT] flow start
6139 14:44:46.899121 [ANA_INIT] PLL >>>>>>>>
6140 14:44:46.899257 [ANA_INIT] PLL <<<<<<<<
6141 14:44:46.902351 [ANA_INIT] MIDPI >>>>>>>>
6142 14:44:46.905442 [ANA_INIT] MIDPI <<<<<<<<
6143 14:44:46.905551 [ANA_INIT] DLL >>>>>>>>
6144 14:44:46.908998 [ANA_INIT] flow end
6145 14:44:46.912090 ============ LP4 DIFF to SE enter ============
6146 14:44:46.915848 ============ LP4 DIFF to SE exit ============
6147 14:44:46.919073 [ANA_INIT] <<<<<<<<<<<<<
6148 14:44:46.922286 [Flow] Enable top DCM control >>>>>
6149 14:44:46.925470 [Flow] Enable top DCM control <<<<<
6150 14:44:46.928899 Enable DLL master slave shuffle
6151 14:44:46.935509 ==============================================================
6152 14:44:46.935617 Gating Mode config
6153 14:44:46.942292 ==============================================================
6154 14:44:46.945662 Config description:
6155 14:44:46.952162 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 14:44:46.958802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 14:44:46.965390 SELPH_MODE 0: By rank 1: By Phase
6158 14:44:46.971955 ==============================================================
6159 14:44:46.972045 GAT_TRACK_EN = 0
6160 14:44:46.975318 RX_GATING_MODE = 2
6161 14:44:46.978439 RX_GATING_TRACK_MODE = 2
6162 14:44:46.982187 SELPH_MODE = 1
6163 14:44:46.985293 PICG_EARLY_EN = 1
6164 14:44:46.988538 VALID_LAT_VALUE = 1
6165 14:44:46.995488 ==============================================================
6166 14:44:46.998903 Enter into Gating configuration >>>>
6167 14:44:47.002027 Exit from Gating configuration <<<<
6168 14:44:47.005106 Enter into DVFS_PRE_config >>>>>
6169 14:44:47.015116 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 14:44:47.018609 Exit from DVFS_PRE_config <<<<<
6171 14:44:47.021758 Enter into PICG configuration >>>>
6172 14:44:47.025333 Exit from PICG configuration <<<<
6173 14:44:47.028658 [RX_INPUT] configuration >>>>>
6174 14:44:47.028754 [RX_INPUT] configuration <<<<<
6175 14:44:47.035256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 14:44:47.041790 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 14:44:47.045480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 14:44:47.051857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 14:44:47.058297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 14:44:47.065227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 14:44:47.068510 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 14:44:47.071831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 14:44:47.078313 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 14:44:47.082087 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 14:44:47.085155 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 14:44:47.091807 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 14:44:47.094929 ===================================
6188 14:44:47.095234 LPDDR4 DRAM CONFIGURATION
6189 14:44:47.098164 ===================================
6190 14:44:47.101899 EX_ROW_EN[0] = 0x0
6191 14:44:47.102200 EX_ROW_EN[1] = 0x0
6192 14:44:47.105260 LP4Y_EN = 0x0
6193 14:44:47.105562 WORK_FSP = 0x0
6194 14:44:47.108625 WL = 0x2
6195 14:44:47.108926 RL = 0x2
6196 14:44:47.112107 BL = 0x2
6197 14:44:47.115244 RPST = 0x0
6198 14:44:47.115544 RD_PRE = 0x0
6199 14:44:47.118571 WR_PRE = 0x1
6200 14:44:47.118871 WR_PST = 0x0
6201 14:44:47.121654 DBI_WR = 0x0
6202 14:44:47.121954 DBI_RD = 0x0
6203 14:44:47.125201 OTF = 0x1
6204 14:44:47.128273 ===================================
6205 14:44:47.131492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 14:44:47.134979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 14:44:47.138131 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 14:44:47.141978 ===================================
6209 14:44:47.144854 LPDDR4 DRAM CONFIGURATION
6210 14:44:47.148402 ===================================
6211 14:44:47.151613 EX_ROW_EN[0] = 0x10
6212 14:44:47.151912 EX_ROW_EN[1] = 0x0
6213 14:44:47.154624 LP4Y_EN = 0x0
6214 14:44:47.154924 WORK_FSP = 0x0
6215 14:44:47.158031 WL = 0x2
6216 14:44:47.158330 RL = 0x2
6217 14:44:47.161387 BL = 0x2
6218 14:44:47.161692 RPST = 0x0
6219 14:44:47.164485 RD_PRE = 0x0
6220 14:44:47.164868 WR_PRE = 0x1
6221 14:44:47.167920 WR_PST = 0x0
6222 14:44:47.171459 DBI_WR = 0x0
6223 14:44:47.171643 DBI_RD = 0x0
6224 14:44:47.174763 OTF = 0x1
6225 14:44:47.177939 ===================================
6226 14:44:47.181416 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 14:44:47.186437 nWR fixed to 30
6228 14:44:47.190041 [ModeRegInit_LP4] CH0 RK0
6229 14:44:47.190169 [ModeRegInit_LP4] CH0 RK1
6230 14:44:47.193060 [ModeRegInit_LP4] CH1 RK0
6231 14:44:47.196353 [ModeRegInit_LP4] CH1 RK1
6232 14:44:47.196446 match AC timing 19
6233 14:44:47.203348 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 14:44:47.206517 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 14:44:47.209977 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 14:44:47.217122 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 14:44:47.220136 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 14:44:47.220672 ==
6239 14:44:47.223505 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 14:44:47.226645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 14:44:47.227077 ==
6242 14:44:47.233711 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 14:44:47.239947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 14:44:47.243310 [CA 0] Center 36 (8~64) winsize 57
6245 14:44:47.246666 [CA 1] Center 36 (8~64) winsize 57
6246 14:44:47.247095 [CA 2] Center 36 (8~64) winsize 57
6247 14:44:47.250316 [CA 3] Center 36 (8~64) winsize 57
6248 14:44:47.253638 [CA 4] Center 36 (8~64) winsize 57
6249 14:44:47.256686 [CA 5] Center 36 (8~64) winsize 57
6250 14:44:47.257118
6251 14:44:47.260157 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 14:44:47.263353
6253 14:44:47.266470 [CATrainingPosCal] consider 1 rank data
6254 14:44:47.266778 u2DelayCellTimex100 = 270/100 ps
6255 14:44:47.273392 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 14:44:47.276441 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 14:44:47.279905 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 14:44:47.283288 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 14:44:47.286448 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 14:44:47.289932 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 14:44:47.290067
6262 14:44:47.293000 CA PerBit enable=1, Macro0, CA PI delay=36
6263 14:44:47.293119
6264 14:44:47.296482 [CBTSetCACLKResult] CA Dly = 36
6265 14:44:47.299761 CS Dly: 1 (0~32)
6266 14:44:47.299878 ==
6267 14:44:47.302909 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 14:44:47.306344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 14:44:47.306463 ==
6270 14:44:47.309928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 14:44:47.316791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6272 14:44:47.319991 [CA 0] Center 36 (8~64) winsize 57
6273 14:44:47.323562 [CA 1] Center 36 (8~64) winsize 57
6274 14:44:47.326405 [CA 2] Center 36 (8~64) winsize 57
6275 14:44:47.329715 [CA 3] Center 36 (8~64) winsize 57
6276 14:44:47.332917 [CA 4] Center 36 (8~64) winsize 57
6277 14:44:47.336594 [CA 5] Center 36 (8~64) winsize 57
6278 14:44:47.336787
6279 14:44:47.339846 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6280 14:44:47.340028
6281 14:44:47.343093 [CATrainingPosCal] consider 2 rank data
6282 14:44:47.346722 u2DelayCellTimex100 = 270/100 ps
6283 14:44:47.350134 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 14:44:47.353285 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 14:44:47.356817 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 14:44:47.360106 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 14:44:47.363427 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 14:44:47.370150 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 14:44:47.370710
6290 14:44:47.373537 CA PerBit enable=1, Macro0, CA PI delay=36
6291 14:44:47.374012
6292 14:44:47.376929 [CBTSetCACLKResult] CA Dly = 36
6293 14:44:47.377414 CS Dly: 1 (0~32)
6294 14:44:47.378019
6295 14:44:47.380309 ----->DramcWriteLeveling(PI) begin...
6296 14:44:47.380832 ==
6297 14:44:47.383499 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 14:44:47.387381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 14:44:47.390327 ==
6300 14:44:47.390853 Write leveling (Byte 0): 40 => 8
6301 14:44:47.393662 Write leveling (Byte 1): 32 => 0
6302 14:44:47.396658 DramcWriteLeveling(PI) end<-----
6303 14:44:47.397147
6304 14:44:47.397519 ==
6305 14:44:47.399908 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 14:44:47.406620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 14:44:47.407176 ==
6308 14:44:47.410124 [Gating] SW mode calibration
6309 14:44:47.416701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 14:44:47.420141 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 14:44:47.426941 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 14:44:47.430039 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 14:44:47.433412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 14:44:47.439973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 14:44:47.443383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 14:44:47.446770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 14:44:47.450019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 14:44:47.456908 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 14:44:47.460324 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 14:44:47.463752 Total UI for P1: 0, mck2ui 16
6321 14:44:47.466801 best dqsien dly found for B0: ( 0, 14, 24)
6322 14:44:47.470286 Total UI for P1: 0, mck2ui 16
6323 14:44:47.473513 best dqsien dly found for B1: ( 0, 14, 24)
6324 14:44:47.477075 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 14:44:47.479788 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 14:44:47.480256
6327 14:44:47.483449 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 14:44:47.487026 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 14:44:47.489696 [Gating] SW calibration Done
6330 14:44:47.490163 ==
6331 14:44:47.493622 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 14:44:47.499601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 14:44:47.500060 ==
6334 14:44:47.500415 RX Vref Scan: 0
6335 14:44:47.500795
6336 14:44:47.503240 RX Vref 0 -> 0, step: 1
6337 14:44:47.503694
6338 14:44:47.506609 RX Delay -410 -> 252, step: 16
6339 14:44:47.509762 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6340 14:44:47.512998 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6341 14:44:47.519365 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6342 14:44:47.522835 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6343 14:44:47.526577 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6344 14:44:47.529466 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6345 14:44:47.536266 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6346 14:44:47.539406 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6347 14:44:47.543057 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6348 14:44:47.546132 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6349 14:44:47.549822 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6350 14:44:47.555950 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6351 14:44:47.559676 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6352 14:44:47.562766 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6353 14:44:47.569689 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6354 14:44:47.573226 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6355 14:44:47.573777 ==
6356 14:44:47.576442 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 14:44:47.579718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 14:44:47.580200 ==
6359 14:44:47.583196 DQS Delay:
6360 14:44:47.583668 DQS0 = 27, DQS1 = 43
6361 14:44:47.584060 DQM Delay:
6362 14:44:47.586214 DQM0 = 12, DQM1 = 12
6363 14:44:47.586669 DQ Delay:
6364 14:44:47.589354 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6365 14:44:47.592914 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6366 14:44:47.595925 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6367 14:44:47.599261 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6368 14:44:47.599715
6369 14:44:47.600068
6370 14:44:47.600406 ==
6371 14:44:47.602596 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 14:44:47.606220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 14:44:47.609688 ==
6374 14:44:47.610248
6375 14:44:47.610610
6376 14:44:47.610942 TX Vref Scan disable
6377 14:44:47.612786 == TX Byte 0 ==
6378 14:44:47.616098 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 14:44:47.619684 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 14:44:47.622924 == TX Byte 1 ==
6381 14:44:47.626310 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 14:44:47.629510 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 14:44:47.630062 ==
6384 14:44:47.632619 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 14:44:47.639651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 14:44:47.640205 ==
6387 14:44:47.640590
6388 14:44:47.640928
6389 14:44:47.641245 TX Vref Scan disable
6390 14:44:47.642635 == TX Byte 0 ==
6391 14:44:47.646145 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 14:44:47.649481 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 14:44:47.652384 == TX Byte 1 ==
6394 14:44:47.656332 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 14:44:47.659432 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 14:44:47.659913
6397 14:44:47.662355 [DATLAT]
6398 14:44:47.662830 Freq=400, CH0 RK0
6399 14:44:47.663190
6400 14:44:47.665695 DATLAT Default: 0xf
6401 14:44:47.666204 0, 0xFFFF, sum = 0
6402 14:44:47.669114 1, 0xFFFF, sum = 0
6403 14:44:47.669574 2, 0xFFFF, sum = 0
6404 14:44:47.672430 3, 0xFFFF, sum = 0
6405 14:44:47.672924 4, 0xFFFF, sum = 0
6406 14:44:47.676154 5, 0xFFFF, sum = 0
6407 14:44:47.676758 6, 0xFFFF, sum = 0
6408 14:44:47.679114 7, 0xFFFF, sum = 0
6409 14:44:47.679667 8, 0xFFFF, sum = 0
6410 14:44:47.682238 9, 0xFFFF, sum = 0
6411 14:44:47.682721 10, 0xFFFF, sum = 0
6412 14:44:47.685860 11, 0xFFFF, sum = 0
6413 14:44:47.689056 12, 0xFFFF, sum = 0
6414 14:44:47.689526 13, 0x0, sum = 1
6415 14:44:47.689898 14, 0x0, sum = 2
6416 14:44:47.692390 15, 0x0, sum = 3
6417 14:44:47.692967 16, 0x0, sum = 4
6418 14:44:47.695686 best_step = 14
6419 14:44:47.696236
6420 14:44:47.696661 ==
6421 14:44:47.698901 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 14:44:47.702444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 14:44:47.702905 ==
6424 14:44:47.705833 RX Vref Scan: 1
6425 14:44:47.706284
6426 14:44:47.706643 RX Vref 0 -> 0, step: 1
6427 14:44:47.706978
6428 14:44:47.709383 RX Delay -327 -> 252, step: 8
6429 14:44:47.709933
6430 14:44:47.712428 Set Vref, RX VrefLevel [Byte0]: 57
6431 14:44:47.715727 [Byte1]: 49
6432 14:44:47.720498
6433 14:44:47.720998 Final RX Vref Byte 0 = 57 to rank0
6434 14:44:47.723662 Final RX Vref Byte 1 = 49 to rank0
6435 14:44:47.727194 Final RX Vref Byte 0 = 57 to rank1
6436 14:44:47.730844 Final RX Vref Byte 1 = 49 to rank1==
6437 14:44:47.733828 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 14:44:47.740367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 14:44:47.740981 ==
6440 14:44:47.741428 DQS Delay:
6441 14:44:47.743774 DQS0 = 28, DQS1 = 48
6442 14:44:47.744320 DQM Delay:
6443 14:44:47.744959 DQM0 = 12, DQM1 = 15
6444 14:44:47.747038 DQ Delay:
6445 14:44:47.750337 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6446 14:44:47.750962 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6447 14:44:47.753543 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6448 14:44:47.757308 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6449 14:44:47.758107
6450 14:44:47.760173
6451 14:44:47.767031 [DQSOSCAuto] RK0, (LSB)MR18= 0xb4ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6452 14:44:47.770252 CH0 RK0: MR19=C0C, MR18=B4AC
6453 14:44:47.776846 CH0_RK0: MR19=0xC0C, MR18=0xB4AC, DQSOSC=387, MR23=63, INC=394, DEC=262
6454 14:44:47.777266 ==
6455 14:44:47.780147 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 14:44:47.783359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 14:44:47.783797 ==
6458 14:44:47.786704 [Gating] SW mode calibration
6459 14:44:47.793348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 14:44:47.799771 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 14:44:47.803449 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 14:44:47.806640 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 14:44:47.813525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 14:44:47.816657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 14:44:47.820216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 14:44:47.826731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 14:44:47.830123 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 14:44:47.833374 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 14:44:47.839663 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 14:44:47.840128 Total UI for P1: 0, mck2ui 16
6471 14:44:47.843502 best dqsien dly found for B0: ( 0, 14, 24)
6472 14:44:47.846245 Total UI for P1: 0, mck2ui 16
6473 14:44:47.849922 best dqsien dly found for B1: ( 0, 14, 24)
6474 14:44:47.856517 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 14:44:47.859605 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 14:44:47.860085
6477 14:44:47.863166 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 14:44:47.866354 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 14:44:47.869617 [Gating] SW calibration Done
6480 14:44:47.870061 ==
6481 14:44:47.873006 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 14:44:47.876432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 14:44:47.876937 ==
6484 14:44:47.879739 RX Vref Scan: 0
6485 14:44:47.880258
6486 14:44:47.880885 RX Vref 0 -> 0, step: 1
6487 14:44:47.881280
6488 14:44:47.882964 RX Delay -410 -> 252, step: 16
6489 14:44:47.886399 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6490 14:44:47.892864 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6491 14:44:47.896398 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6492 14:44:47.899545 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6493 14:44:47.902665 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6494 14:44:47.909850 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6495 14:44:47.912912 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6496 14:44:47.915990 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6497 14:44:47.919342 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6498 14:44:47.926068 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6499 14:44:47.929567 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6500 14:44:47.932647 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6501 14:44:47.936232 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6502 14:44:47.942992 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6503 14:44:47.946144 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6504 14:44:47.949413 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6505 14:44:47.949840 ==
6506 14:44:47.952922 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 14:44:47.959595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 14:44:47.960115 ==
6509 14:44:47.960650 DQS Delay:
6510 14:44:47.962898 DQS0 = 19, DQS1 = 43
6511 14:44:47.963343 DQM Delay:
6512 14:44:47.963689 DQM0 = 2, DQM1 = 17
6513 14:44:47.965969 DQ Delay:
6514 14:44:47.969599 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6515 14:44:47.970059 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6516 14:44:47.972818 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6517 14:44:47.976086 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6518 14:44:47.976673
6519 14:44:47.977074
6520 14:44:47.979450 ==
6521 14:44:47.979955 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 14:44:47.986084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 14:44:47.986659 ==
6524 14:44:47.987160
6525 14:44:47.987619
6526 14:44:47.989723 TX Vref Scan disable
6527 14:44:47.990155 == TX Byte 0 ==
6528 14:44:47.992636 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6529 14:44:47.999153 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6530 14:44:47.999722 == TX Byte 1 ==
6531 14:44:48.002737 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6532 14:44:48.005739 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6533 14:44:48.009541 ==
6534 14:44:48.012342 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 14:44:48.016453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 14:44:48.016960 ==
6537 14:44:48.017531
6538 14:44:48.018098
6539 14:44:48.019210 TX Vref Scan disable
6540 14:44:48.019855 == TX Byte 0 ==
6541 14:44:48.022591 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6542 14:44:48.029000 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6543 14:44:48.029429 == TX Byte 1 ==
6544 14:44:48.032260 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6545 14:44:48.035615 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6546 14:44:48.039116
6547 14:44:48.039674 [DATLAT]
6548 14:44:48.040156 Freq=400, CH0 RK1
6549 14:44:48.040642
6550 14:44:48.042343 DATLAT Default: 0xe
6551 14:44:48.042808 0, 0xFFFF, sum = 0
6552 14:44:48.046303 1, 0xFFFF, sum = 0
6553 14:44:48.046748 2, 0xFFFF, sum = 0
6554 14:44:48.049281 3, 0xFFFF, sum = 0
6555 14:44:48.049735 4, 0xFFFF, sum = 0
6556 14:44:48.052606 5, 0xFFFF, sum = 0
6557 14:44:48.055660 6, 0xFFFF, sum = 0
6558 14:44:48.056268 7, 0xFFFF, sum = 0
6559 14:44:48.058884 8, 0xFFFF, sum = 0
6560 14:44:48.059394 9, 0xFFFF, sum = 0
6561 14:44:48.062316 10, 0xFFFF, sum = 0
6562 14:44:48.062751 11, 0xFFFF, sum = 0
6563 14:44:48.065654 12, 0xFFFF, sum = 0
6564 14:44:48.066089 13, 0x0, sum = 1
6565 14:44:48.069424 14, 0x0, sum = 2
6566 14:44:48.069861 15, 0x0, sum = 3
6567 14:44:48.072451 16, 0x0, sum = 4
6568 14:44:48.072931 best_step = 14
6569 14:44:48.073304
6570 14:44:48.073628 ==
6571 14:44:48.075807 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 14:44:48.079079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 14:44:48.079626 ==
6574 14:44:48.082339 RX Vref Scan: 0
6575 14:44:48.082896
6576 14:44:48.085951 RX Vref 0 -> 0, step: 1
6577 14:44:48.086393
6578 14:44:48.086816 RX Delay -327 -> 252, step: 8
6579 14:44:48.094222 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6580 14:44:48.097696 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6581 14:44:48.101216 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6582 14:44:48.104461 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6583 14:44:48.111014 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6584 14:44:48.114396 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6585 14:44:48.117473 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6586 14:44:48.121030 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6587 14:44:48.127453 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6588 14:44:48.130919 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6589 14:44:48.134474 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6590 14:44:48.137645 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6591 14:44:48.144318 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6592 14:44:48.147498 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6593 14:44:48.150713 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6594 14:44:48.157590 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6595 14:44:48.158021 ==
6596 14:44:48.160833 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 14:44:48.163843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 14:44:48.164367 ==
6599 14:44:48.164817 DQS Delay:
6600 14:44:48.167676 DQS0 = 24, DQS1 = 44
6601 14:44:48.168105 DQM Delay:
6602 14:44:48.170948 DQM0 = 6, DQM1 = 14
6603 14:44:48.171447 DQ Delay:
6604 14:44:48.174071 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =4
6605 14:44:48.177378 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =12
6606 14:44:48.180704 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6607 14:44:48.183964 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6608 14:44:48.184394
6609 14:44:48.184795
6610 14:44:48.190754 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6611 14:44:48.193967 CH0 RK1: MR19=C0C, MR18=B86A
6612 14:44:48.200692 CH0_RK1: MR19=0xC0C, MR18=0xB86A, DQSOSC=386, MR23=63, INC=396, DEC=264
6613 14:44:48.203752 [RxdqsGatingPostProcess] freq 400
6614 14:44:48.207524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 14:44:48.210814 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 14:44:48.213920 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 14:44:48.217501 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 14:44:48.220472 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 14:44:48.223740 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 14:44:48.227122 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 14:44:48.230628 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 14:44:48.233713 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 14:44:48.237118 Pre-setting of DQS Precalculation
6624 14:44:48.240290 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 14:44:48.243974 ==
6626 14:44:48.247038 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 14:44:48.250600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 14:44:48.251033 ==
6629 14:44:48.253650 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 14:44:48.260217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6631 14:44:48.263832 [CA 0] Center 36 (8~64) winsize 57
6632 14:44:48.267087 [CA 1] Center 36 (8~64) winsize 57
6633 14:44:48.270472 [CA 2] Center 36 (8~64) winsize 57
6634 14:44:48.273905 [CA 3] Center 36 (8~64) winsize 57
6635 14:44:48.277107 [CA 4] Center 36 (8~64) winsize 57
6636 14:44:48.280365 [CA 5] Center 36 (8~64) winsize 57
6637 14:44:48.280870
6638 14:44:48.283517 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6639 14:44:48.284014
6640 14:44:48.286842 [CATrainingPosCal] consider 1 rank data
6641 14:44:48.290234 u2DelayCellTimex100 = 270/100 ps
6642 14:44:48.293590 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 14:44:48.296916 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 14:44:48.300298 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 14:44:48.303623 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 14:44:48.310445 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 14:44:48.313782 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 14:44:48.314214
6649 14:44:48.316867 CA PerBit enable=1, Macro0, CA PI delay=36
6650 14:44:48.317300
6651 14:44:48.320254 [CBTSetCACLKResult] CA Dly = 36
6652 14:44:48.320828 CS Dly: 1 (0~32)
6653 14:44:48.321186 ==
6654 14:44:48.323366 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 14:44:48.326677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 14:44:48.330321 ==
6657 14:44:48.333293 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 14:44:48.340218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6659 14:44:48.343355 [CA 0] Center 36 (8~64) winsize 57
6660 14:44:48.346640 [CA 1] Center 36 (8~64) winsize 57
6661 14:44:48.350026 [CA 2] Center 36 (8~64) winsize 57
6662 14:44:48.353531 [CA 3] Center 36 (8~64) winsize 57
6663 14:44:48.356726 [CA 4] Center 36 (8~64) winsize 57
6664 14:44:48.360206 [CA 5] Center 36 (8~64) winsize 57
6665 14:44:48.360806
6666 14:44:48.363626 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6667 14:44:48.364193
6668 14:44:48.366498 [CATrainingPosCal] consider 2 rank data
6669 14:44:48.370142 u2DelayCellTimex100 = 270/100 ps
6670 14:44:48.373394 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 14:44:48.376891 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 14:44:48.380050 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 14:44:48.383124 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 14:44:48.386404 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 14:44:48.389895 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 14:44:48.390465
6677 14:44:48.396699 CA PerBit enable=1, Macro0, CA PI delay=36
6678 14:44:48.397261
6679 14:44:48.397637 [CBTSetCACLKResult] CA Dly = 36
6680 14:44:48.399603 CS Dly: 1 (0~32)
6681 14:44:48.400071
6682 14:44:48.403599 ----->DramcWriteLeveling(PI) begin...
6683 14:44:48.404169 ==
6684 14:44:48.406747 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 14:44:48.409638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 14:44:48.410114 ==
6687 14:44:48.412937 Write leveling (Byte 0): 40 => 8
6688 14:44:48.416656 Write leveling (Byte 1): 32 => 0
6689 14:44:48.419839 DramcWriteLeveling(PI) end<-----
6690 14:44:48.420315
6691 14:44:48.420737 ==
6692 14:44:48.423067 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 14:44:48.426770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 14:44:48.430046 ==
6695 14:44:48.430611 [Gating] SW mode calibration
6696 14:44:48.439694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 14:44:48.442855 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 14:44:48.446309 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 14:44:48.452994 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 14:44:48.455976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 14:44:48.459475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 14:44:48.465786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 14:44:48.469217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 14:44:48.472508 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 14:44:48.479220 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 14:44:48.482582 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 14:44:48.485827 Total UI for P1: 0, mck2ui 16
6708 14:44:48.489379 best dqsien dly found for B0: ( 0, 14, 24)
6709 14:44:48.492791 Total UI for P1: 0, mck2ui 16
6710 14:44:48.496244 best dqsien dly found for B1: ( 0, 14, 24)
6711 14:44:48.499144 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 14:44:48.502971 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 14:44:48.503540
6714 14:44:48.506356 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 14:44:48.509533 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 14:44:48.512696 [Gating] SW calibration Done
6717 14:44:48.513258 ==
6718 14:44:48.516062 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 14:44:48.519398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 14:44:48.522570 ==
6721 14:44:48.523044 RX Vref Scan: 0
6722 14:44:48.523421
6723 14:44:48.526173 RX Vref 0 -> 0, step: 1
6724 14:44:48.526737
6725 14:44:48.529573 RX Delay -410 -> 252, step: 16
6726 14:44:48.533134 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6727 14:44:48.536477 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6728 14:44:48.539111 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6729 14:44:48.546166 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6730 14:44:48.549477 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6731 14:44:48.552826 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6732 14:44:48.555763 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6733 14:44:48.562397 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6734 14:44:48.565984 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6735 14:44:48.569183 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6736 14:44:48.572830 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6737 14:44:48.579255 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6738 14:44:48.582424 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6739 14:44:48.585299 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6740 14:44:48.588752 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6741 14:44:48.595521 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6742 14:44:48.596094 ==
6743 14:44:48.598918 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 14:44:48.602446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 14:44:48.602922 ==
6746 14:44:48.603304 DQS Delay:
6747 14:44:48.606036 DQS0 = 27, DQS1 = 43
6748 14:44:48.606603 DQM Delay:
6749 14:44:48.608661 DQM0 = 8, DQM1 = 16
6750 14:44:48.609134 DQ Delay:
6751 14:44:48.611874 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6752 14:44:48.616126 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6753 14:44:48.618896 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6754 14:44:48.622448 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6755 14:44:48.623009
6756 14:44:48.623429
6757 14:44:48.623953 ==
6758 14:44:48.625426 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 14:44:48.628683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 14:44:48.629114 ==
6761 14:44:48.629479
6762 14:44:48.629859
6763 14:44:48.631942 TX Vref Scan disable
6764 14:44:48.635974 == TX Byte 0 ==
6765 14:44:48.639126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 14:44:48.642354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 14:44:48.645307 == TX Byte 1 ==
6768 14:44:48.649299 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6769 14:44:48.652180 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6770 14:44:48.652782 ==
6771 14:44:48.655397 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 14:44:48.658553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 14:44:48.659029 ==
6774 14:44:48.662118
6775 14:44:48.662678
6776 14:44:48.663059 TX Vref Scan disable
6777 14:44:48.665444 == TX Byte 0 ==
6778 14:44:48.668833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 14:44:48.671655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 14:44:48.675697 == TX Byte 1 ==
6781 14:44:48.678686 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6782 14:44:48.682023 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6783 14:44:48.682607
6784 14:44:48.682987 [DATLAT]
6785 14:44:48.685446 Freq=400, CH1 RK0
6786 14:44:48.685924
6787 14:44:48.689074 DATLAT Default: 0xf
6788 14:44:48.689651 0, 0xFFFF, sum = 0
6789 14:44:48.692256 1, 0xFFFF, sum = 0
6790 14:44:48.692875 2, 0xFFFF, sum = 0
6791 14:44:48.695637 3, 0xFFFF, sum = 0
6792 14:44:48.696222 4, 0xFFFF, sum = 0
6793 14:44:48.698731 5, 0xFFFF, sum = 0
6794 14:44:48.699545 6, 0xFFFF, sum = 0
6795 14:44:48.702068 7, 0xFFFF, sum = 0
6796 14:44:48.702630 8, 0xFFFF, sum = 0
6797 14:44:48.705459 9, 0xFFFF, sum = 0
6798 14:44:48.705943 10, 0xFFFF, sum = 0
6799 14:44:48.708719 11, 0xFFFF, sum = 0
6800 14:44:48.709198 12, 0xFFFF, sum = 0
6801 14:44:48.712098 13, 0x0, sum = 1
6802 14:44:48.712731 14, 0x0, sum = 2
6803 14:44:48.715787 15, 0x0, sum = 3
6804 14:44:48.716369 16, 0x0, sum = 4
6805 14:44:48.718645 best_step = 14
6806 14:44:48.719256
6807 14:44:48.719645 ==
6808 14:44:48.722123 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 14:44:48.725358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 14:44:48.725836 ==
6811 14:44:48.729004 RX Vref Scan: 1
6812 14:44:48.729579
6813 14:44:48.729960 RX Vref 0 -> 0, step: 1
6814 14:44:48.730311
6815 14:44:48.732351 RX Delay -327 -> 252, step: 8
6816 14:44:48.732984
6817 14:44:48.735701 Set Vref, RX VrefLevel [Byte0]: 52
6818 14:44:48.738571 [Byte1]: 52
6819 14:44:48.743057
6820 14:44:48.743720 Final RX Vref Byte 0 = 52 to rank0
6821 14:44:48.746698 Final RX Vref Byte 1 = 52 to rank0
6822 14:44:48.749393 Final RX Vref Byte 0 = 52 to rank1
6823 14:44:48.753017 Final RX Vref Byte 1 = 52 to rank1==
6824 14:44:48.756068 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 14:44:48.763118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 14:44:48.763707 ==
6827 14:44:48.764088 DQS Delay:
6828 14:44:48.764442 DQS0 = 32, DQS1 = 40
6829 14:44:48.766085 DQM Delay:
6830 14:44:48.766559 DQM0 = 11, DQM1 = 12
6831 14:44:48.769508 DQ Delay:
6832 14:44:48.772691 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6833 14:44:48.773167 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6834 14:44:48.776054 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6835 14:44:48.779528 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6836 14:44:48.780007
6837 14:44:48.780481
6838 14:44:48.789593 [DQSOSCAuto] RK0, (LSB)MR18= 0x9dd7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6839 14:44:48.792661 CH1 RK0: MR19=C0C, MR18=9DD7
6840 14:44:48.799072 CH1_RK0: MR19=0xC0C, MR18=0x9DD7, DQSOSC=383, MR23=63, INC=402, DEC=268
6841 14:44:48.799657 ==
6842 14:44:48.802575 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 14:44:48.805697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 14:44:48.806139 ==
6845 14:44:48.809068 [Gating] SW mode calibration
6846 14:44:48.815804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 14:44:48.819489 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 14:44:48.826041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 14:44:48.829277 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 14:44:48.832515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 14:44:48.839507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 14:44:48.842707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 14:44:48.846230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 14:44:48.852971 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 14:44:48.855820 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 14:44:48.859471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 14:44:48.862903 Total UI for P1: 0, mck2ui 16
6858 14:44:48.866386 best dqsien dly found for B0: ( 0, 14, 24)
6859 14:44:48.869359 Total UI for P1: 0, mck2ui 16
6860 14:44:48.872596 best dqsien dly found for B1: ( 0, 14, 24)
6861 14:44:48.876301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 14:44:48.879237 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 14:44:48.879818
6864 14:44:48.886041 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 14:44:48.889389 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 14:44:48.889825 [Gating] SW calibration Done
6867 14:44:48.892509 ==
6868 14:44:48.895760 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 14:44:48.899405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 14:44:48.899844 ==
6871 14:44:48.900273 RX Vref Scan: 0
6872 14:44:48.900777
6873 14:44:48.902599 RX Vref 0 -> 0, step: 1
6874 14:44:48.903135
6875 14:44:48.906274 RX Delay -410 -> 252, step: 16
6876 14:44:48.909033 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6877 14:44:48.912986 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6878 14:44:48.919618 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6879 14:44:48.923001 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6880 14:44:48.926219 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6881 14:44:48.929410 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6882 14:44:48.935955 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6883 14:44:48.939267 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6884 14:44:48.942480 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6885 14:44:48.945866 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6886 14:44:48.952598 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6887 14:44:48.956155 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6888 14:44:48.959252 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6889 14:44:48.962330 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6890 14:44:48.969142 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6891 14:44:48.972538 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6892 14:44:48.973012 ==
6893 14:44:48.975894 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 14:44:48.979475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 14:44:48.980012 ==
6896 14:44:48.982281 DQS Delay:
6897 14:44:48.982711 DQS0 = 35, DQS1 = 43
6898 14:44:48.985743 DQM Delay:
6899 14:44:48.986177 DQM0 = 18, DQM1 = 18
6900 14:44:48.986611 DQ Delay:
6901 14:44:48.989084 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6902 14:44:48.992660 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6903 14:44:48.995911 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6904 14:44:48.998861 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6905 14:44:48.999303
6906 14:44:48.999828
6907 14:44:49.000235 ==
6908 14:44:49.002214 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 14:44:49.009156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 14:44:49.009699 ==
6911 14:44:49.010135
6912 14:44:49.010538
6913 14:44:49.010934 TX Vref Scan disable
6914 14:44:49.012274 == TX Byte 0 ==
6915 14:44:49.015910 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 14:44:49.019216 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 14:44:49.022401 == TX Byte 1 ==
6918 14:44:49.025596 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6919 14:44:49.029276 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6920 14:44:49.032450 ==
6921 14:44:49.033160 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 14:44:49.038796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 14:44:49.039245 ==
6924 14:44:49.039642
6925 14:44:49.039958
6926 14:44:49.042217 TX Vref Scan disable
6927 14:44:49.042641 == TX Byte 0 ==
6928 14:44:49.045451 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6929 14:44:49.048916 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6930 14:44:49.052239 == TX Byte 1 ==
6931 14:44:49.055588 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6932 14:44:49.058672 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6933 14:44:49.062070
6934 14:44:49.062494 [DATLAT]
6935 14:44:49.062833 Freq=400, CH1 RK1
6936 14:44:49.063152
6937 14:44:49.065386 DATLAT Default: 0xe
6938 14:44:49.065858 0, 0xFFFF, sum = 0
6939 14:44:49.068821 1, 0xFFFF, sum = 0
6940 14:44:49.069250 2, 0xFFFF, sum = 0
6941 14:44:49.071902 3, 0xFFFF, sum = 0
6942 14:44:49.072379 4, 0xFFFF, sum = 0
6943 14:44:49.075523 5, 0xFFFF, sum = 0
6944 14:44:49.075955 6, 0xFFFF, sum = 0
6945 14:44:49.078617 7, 0xFFFF, sum = 0
6946 14:44:49.079115 8, 0xFFFF, sum = 0
6947 14:44:49.082176 9, 0xFFFF, sum = 0
6948 14:44:49.085185 10, 0xFFFF, sum = 0
6949 14:44:49.085692 11, 0xFFFF, sum = 0
6950 14:44:49.088776 12, 0xFFFF, sum = 0
6951 14:44:49.089256 13, 0x0, sum = 1
6952 14:44:49.092033 14, 0x0, sum = 2
6953 14:44:49.092464 15, 0x0, sum = 3
6954 14:44:49.095441 16, 0x0, sum = 4
6955 14:44:49.095963 best_step = 14
6956 14:44:49.096421
6957 14:44:49.096824 ==
6958 14:44:49.098797 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 14:44:49.102061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 14:44:49.102495 ==
6961 14:44:49.105398 RX Vref Scan: 0
6962 14:44:49.105825
6963 14:44:49.108654 RX Vref 0 -> 0, step: 1
6964 14:44:49.109080
6965 14:44:49.109422 RX Delay -327 -> 252, step: 8
6966 14:44:49.117085 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6967 14:44:49.120339 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6968 14:44:49.123673 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6969 14:44:49.126857 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6970 14:44:49.133623 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6971 14:44:49.136897 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6972 14:44:49.140113 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6973 14:44:49.143683 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6974 14:44:49.150393 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6975 14:44:49.153436 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6976 14:44:49.156636 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6977 14:44:49.160091 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6978 14:44:49.166974 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6979 14:44:49.170387 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6980 14:44:49.173392 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6981 14:44:49.179784 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6982 14:44:49.180044 ==
6983 14:44:49.183532 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 14:44:49.186479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 14:44:49.186844 ==
6986 14:44:49.187194 DQS Delay:
6987 14:44:49.189735 DQS0 = 32, DQS1 = 36
6988 14:44:49.189983 DQM Delay:
6989 14:44:49.193035 DQM0 = 11, DQM1 = 12
6990 14:44:49.193119 DQ Delay:
6991 14:44:49.196541 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6992 14:44:49.199889 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6993 14:44:49.202842 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6994 14:44:49.206136 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
6995 14:44:49.206220
6996 14:44:49.206287
6997 14:44:49.213059 [DQSOSCAuto] RK1, (LSB)MR18= 0xac55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6998 14:44:49.216336 CH1 RK1: MR19=C0C, MR18=AC55
6999 14:44:49.223220 CH1_RK1: MR19=0xC0C, MR18=0xAC55, DQSOSC=388, MR23=63, INC=392, DEC=261
7000 14:44:49.226063 [RxdqsGatingPostProcess] freq 400
7001 14:44:49.232787 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 14:44:49.232870 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 14:44:49.236489 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 14:44:49.240165 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 14:44:49.243601 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 14:44:49.246933 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 14:44:49.250182 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 14:44:49.253241 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 14:44:49.256580 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 14:44:49.259900 Pre-setting of DQS Precalculation
7011 14:44:49.266949 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 14:44:49.273045 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 14:44:49.279879 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 14:44:49.280357
7015 14:44:49.280781
7016 14:44:49.283084 [Calibration Summary] 800 Mbps
7017 14:44:49.283560 CH 0, Rank 0
7018 14:44:49.286726 SW Impedance : PASS
7019 14:44:49.287366 DUTY Scan : NO K
7020 14:44:49.289876 ZQ Calibration : PASS
7021 14:44:49.293102 Jitter Meter : NO K
7022 14:44:49.293577 CBT Training : PASS
7023 14:44:49.296396 Write leveling : PASS
7024 14:44:49.300044 RX DQS gating : PASS
7025 14:44:49.300538 RX DQ/DQS(RDDQC) : PASS
7026 14:44:49.303331 TX DQ/DQS : PASS
7027 14:44:49.306820 RX DATLAT : PASS
7028 14:44:49.307391 RX DQ/DQS(Engine): PASS
7029 14:44:49.310001 TX OE : NO K
7030 14:44:49.310478 All Pass.
7031 14:44:49.310876
7032 14:44:49.313261 CH 0, Rank 1
7033 14:44:49.313733 SW Impedance : PASS
7034 14:44:49.316837 DUTY Scan : NO K
7035 14:44:49.320104 ZQ Calibration : PASS
7036 14:44:49.320718 Jitter Meter : NO K
7037 14:44:49.323081 CBT Training : PASS
7038 14:44:49.326737 Write leveling : NO K
7039 14:44:49.327298 RX DQS gating : PASS
7040 14:44:49.330124 RX DQ/DQS(RDDQC) : PASS
7041 14:44:49.330691 TX DQ/DQS : PASS
7042 14:44:49.333119 RX DATLAT : PASS
7043 14:44:49.336749 RX DQ/DQS(Engine): PASS
7044 14:44:49.337311 TX OE : NO K
7045 14:44:49.340043 All Pass.
7046 14:44:49.340656
7047 14:44:49.341043 CH 1, Rank 0
7048 14:44:49.343198 SW Impedance : PASS
7049 14:44:49.343672 DUTY Scan : NO K
7050 14:44:49.346419 ZQ Calibration : PASS
7051 14:44:49.349571 Jitter Meter : NO K
7052 14:44:49.350047 CBT Training : PASS
7053 14:44:49.353286 Write leveling : PASS
7054 14:44:49.356422 RX DQS gating : PASS
7055 14:44:49.357005 RX DQ/DQS(RDDQC) : PASS
7056 14:44:49.359585 TX DQ/DQS : PASS
7057 14:44:49.362892 RX DATLAT : PASS
7058 14:44:49.363369 RX DQ/DQS(Engine): PASS
7059 14:44:49.366340 TX OE : NO K
7060 14:44:49.366815 All Pass.
7061 14:44:49.367198
7062 14:44:49.369905 CH 1, Rank 1
7063 14:44:49.370379 SW Impedance : PASS
7064 14:44:49.373291 DUTY Scan : NO K
7065 14:44:49.376608 ZQ Calibration : PASS
7066 14:44:49.377053 Jitter Meter : NO K
7067 14:44:49.379965 CBT Training : PASS
7068 14:44:49.380393 Write leveling : NO K
7069 14:44:49.383095 RX DQS gating : PASS
7070 14:44:49.386513 RX DQ/DQS(RDDQC) : PASS
7071 14:44:49.386946 TX DQ/DQS : PASS
7072 14:44:49.389864 RX DATLAT : PASS
7073 14:44:49.392846 RX DQ/DQS(Engine): PASS
7074 14:44:49.393276 TX OE : NO K
7075 14:44:49.396450 All Pass.
7076 14:44:49.396906
7077 14:44:49.397252 DramC Write-DBI off
7078 14:44:49.399664 PER_BANK_REFRESH: Hybrid Mode
7079 14:44:49.400091 TX_TRACKING: ON
7080 14:44:49.409950 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 14:44:49.413355 [FAST_K] Save calibration result to emmc
7082 14:44:49.416120 dramc_set_vcore_voltage set vcore to 725000
7083 14:44:49.419438 Read voltage for 1600, 0
7084 14:44:49.419910 Vio18 = 0
7085 14:44:49.422708 Vcore = 725000
7086 14:44:49.423132 Vdram = 0
7087 14:44:49.423471 Vddq = 0
7088 14:44:49.426060 Vmddr = 0
7089 14:44:49.429330 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 14:44:49.436036 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 14:44:49.436570 MEM_TYPE=3, freq_sel=13
7092 14:44:49.439585 sv_algorithm_assistance_LP4_3733
7093 14:44:49.446291 ============ PULL DRAM RESETB DOWN ============
7094 14:44:49.449325 ========== PULL DRAM RESETB DOWN end =========
7095 14:44:49.452643 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 14:44:49.456443 ===================================
7097 14:44:49.459805 LPDDR4 DRAM CONFIGURATION
7098 14:44:49.462994 ===================================
7099 14:44:49.463559 EX_ROW_EN[0] = 0x0
7100 14:44:49.466413 EX_ROW_EN[1] = 0x0
7101 14:44:49.469611 LP4Y_EN = 0x0
7102 14:44:49.470082 WORK_FSP = 0x1
7103 14:44:49.472918 WL = 0x5
7104 14:44:49.473407 RL = 0x5
7105 14:44:49.476426 BL = 0x2
7106 14:44:49.477048 RPST = 0x0
7107 14:44:49.479697 RD_PRE = 0x0
7108 14:44:49.480279 WR_PRE = 0x1
7109 14:44:49.482933 WR_PST = 0x1
7110 14:44:49.483498 DBI_WR = 0x0
7111 14:44:49.486229 DBI_RD = 0x0
7112 14:44:49.486701 OTF = 0x1
7113 14:44:49.489113 ===================================
7114 14:44:49.492628 ===================================
7115 14:44:49.496167 ANA top config
7116 14:44:49.499298 ===================================
7117 14:44:49.499815 DLL_ASYNC_EN = 0
7118 14:44:49.502525 ALL_SLAVE_EN = 0
7119 14:44:49.505685 NEW_RANK_MODE = 1
7120 14:44:49.509257 DLL_IDLE_MODE = 1
7121 14:44:49.512536 LP45_APHY_COMB_EN = 1
7122 14:44:49.513049 TX_ODT_DIS = 0
7123 14:44:49.515660 NEW_8X_MODE = 1
7124 14:44:49.519437 ===================================
7125 14:44:49.522737 ===================================
7126 14:44:49.525803 data_rate = 3200
7127 14:44:49.529243 CKR = 1
7128 14:44:49.532579 DQ_P2S_RATIO = 8
7129 14:44:49.535831 ===================================
7130 14:44:49.536366 CA_P2S_RATIO = 8
7131 14:44:49.539399 DQ_CA_OPEN = 0
7132 14:44:49.542575 DQ_SEMI_OPEN = 0
7133 14:44:49.546246 CA_SEMI_OPEN = 0
7134 14:44:49.549278 CA_FULL_RATE = 0
7135 14:44:49.552448 DQ_CKDIV4_EN = 0
7136 14:44:49.552905 CA_CKDIV4_EN = 0
7137 14:44:49.555668 CA_PREDIV_EN = 0
7138 14:44:49.558991 PH8_DLY = 12
7139 14:44:49.562638 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 14:44:49.566232 DQ_AAMCK_DIV = 4
7141 14:44:49.569472 CA_AAMCK_DIV = 4
7142 14:44:49.570003 CA_ADMCK_DIV = 4
7143 14:44:49.572461 DQ_TRACK_CA_EN = 0
7144 14:44:49.575448 CA_PICK = 1600
7145 14:44:49.579048 CA_MCKIO = 1600
7146 14:44:49.582754 MCKIO_SEMI = 0
7147 14:44:49.585804 PLL_FREQ = 3068
7148 14:44:49.588637 DQ_UI_PI_RATIO = 32
7149 14:44:49.592197 CA_UI_PI_RATIO = 0
7150 14:44:49.595309 ===================================
7151 14:44:49.598512 ===================================
7152 14:44:49.598935 memory_type:LPDDR4
7153 14:44:49.601997 GP_NUM : 10
7154 14:44:49.605238 SRAM_EN : 1
7155 14:44:49.605661 MD32_EN : 0
7156 14:44:49.608492 ===================================
7157 14:44:49.611740 [ANA_INIT] >>>>>>>>>>>>>>
7158 14:44:49.615118 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 14:44:49.618458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 14:44:49.621789 ===================================
7161 14:44:49.625085 data_rate = 3200,PCW = 0X7600
7162 14:44:49.628291 ===================================
7163 14:44:49.631960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 14:44:49.635237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 14:44:49.641675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 14:44:49.644876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 14:44:49.648218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 14:44:49.651451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 14:44:49.654771 [ANA_INIT] flow start
7170 14:44:49.658126 [ANA_INIT] PLL >>>>>>>>
7171 14:44:49.658549 [ANA_INIT] PLL <<<<<<<<
7172 14:44:49.661431 [ANA_INIT] MIDPI >>>>>>>>
7173 14:44:49.664648 [ANA_INIT] MIDPI <<<<<<<<
7174 14:44:49.668259 [ANA_INIT] DLL >>>>>>>>
7175 14:44:49.668705 [ANA_INIT] DLL <<<<<<<<
7176 14:44:49.671346 [ANA_INIT] flow end
7177 14:44:49.674630 ============ LP4 DIFF to SE enter ============
7178 14:44:49.678012 ============ LP4 DIFF to SE exit ============
7179 14:44:49.681095 [ANA_INIT] <<<<<<<<<<<<<
7180 14:44:49.684311 [Flow] Enable top DCM control >>>>>
7181 14:44:49.688093 [Flow] Enable top DCM control <<<<<
7182 14:44:49.691394 Enable DLL master slave shuffle
7183 14:44:49.697877 ==============================================================
7184 14:44:49.698181 Gating Mode config
7185 14:44:49.704621 ==============================================================
7186 14:44:49.704962 Config description:
7187 14:44:49.714732 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 14:44:49.720526 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 14:44:49.727344 SELPH_MODE 0: By rank 1: By Phase
7190 14:44:49.730972 ==============================================================
7191 14:44:49.734357 GAT_TRACK_EN = 1
7192 14:44:49.737635 RX_GATING_MODE = 2
7193 14:44:49.740483 RX_GATING_TRACK_MODE = 2
7194 14:44:49.744050 SELPH_MODE = 1
7195 14:44:49.746999 PICG_EARLY_EN = 1
7196 14:44:49.750684 VALID_LAT_VALUE = 1
7197 14:44:49.753921 ==============================================================
7198 14:44:49.757259 Enter into Gating configuration >>>>
7199 14:44:49.760568 Exit from Gating configuration <<<<
7200 14:44:49.763869 Enter into DVFS_PRE_config >>>>>
7201 14:44:49.777193 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 14:44:49.780458 Exit from DVFS_PRE_config <<<<<
7203 14:44:49.783687 Enter into PICG configuration >>>>
7204 14:44:49.787185 Exit from PICG configuration <<<<
7205 14:44:49.787268 [RX_INPUT] configuration >>>>>
7206 14:44:49.790546 [RX_INPUT] configuration <<<<<
7207 14:44:49.797301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 14:44:49.800298 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 14:44:49.807295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 14:44:49.813510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 14:44:49.820286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 14:44:49.827169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 14:44:49.830488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 14:44:49.833718 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 14:44:49.836986 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 14:44:49.843566 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 14:44:49.847221 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 14:44:49.850452 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 14:44:49.853770 ===================================
7220 14:44:49.856980 LPDDR4 DRAM CONFIGURATION
7221 14:44:49.860428 ===================================
7222 14:44:49.863628 EX_ROW_EN[0] = 0x0
7223 14:44:49.863738 EX_ROW_EN[1] = 0x0
7224 14:44:49.867056 LP4Y_EN = 0x0
7225 14:44:49.867158 WORK_FSP = 0x1
7226 14:44:49.870345 WL = 0x5
7227 14:44:49.870425 RL = 0x5
7228 14:44:49.873495 BL = 0x2
7229 14:44:49.873596 RPST = 0x0
7230 14:44:49.877157 RD_PRE = 0x0
7231 14:44:49.877235 WR_PRE = 0x1
7232 14:44:49.880302 WR_PST = 0x1
7233 14:44:49.880398 DBI_WR = 0x0
7234 14:44:49.883549 DBI_RD = 0x0
7235 14:44:49.883624 OTF = 0x1
7236 14:44:49.886826 ===================================
7237 14:44:49.893617 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 14:44:49.897178 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 14:44:49.900222 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 14:44:49.903776 ===================================
7241 14:44:49.907018 LPDDR4 DRAM CONFIGURATION
7242 14:44:49.910127 ===================================
7243 14:44:49.910242 EX_ROW_EN[0] = 0x10
7244 14:44:49.913656 EX_ROW_EN[1] = 0x0
7245 14:44:49.916909 LP4Y_EN = 0x0
7246 14:44:49.917057 WORK_FSP = 0x1
7247 14:44:49.920588 WL = 0x5
7248 14:44:49.920712 RL = 0x5
7249 14:44:49.923549 BL = 0x2
7250 14:44:49.923697 RPST = 0x0
7251 14:44:49.927171 RD_PRE = 0x0
7252 14:44:49.927310 WR_PRE = 0x1
7253 14:44:49.930549 WR_PST = 0x1
7254 14:44:49.930704 DBI_WR = 0x0
7255 14:44:49.933908 DBI_RD = 0x0
7256 14:44:49.934089 OTF = 0x1
7257 14:44:49.937040 ===================================
7258 14:44:49.943607 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 14:44:49.943861 ==
7260 14:44:49.947006 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 14:44:49.950368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 14:44:49.954062 ==
7263 14:44:49.954463 [Duty_Offset_Calibration]
7264 14:44:49.957202 B0:2 B1:0 CA:1
7265 14:44:49.957622
7266 14:44:49.960274 [DutyScan_Calibration_Flow] k_type=0
7267 14:44:49.968705
7268 14:44:49.969224 ==CLK 0==
7269 14:44:49.971763 Final CLK duty delay cell = -4
7270 14:44:49.975082 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7271 14:44:49.978330 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7272 14:44:49.981737 [-4] AVG Duty = 4906%(X100)
7273 14:44:49.982335
7274 14:44:49.985067 CH0 CLK Duty spec in!! Max-Min= 187%
7275 14:44:49.988665 [DutyScan_Calibration_Flow] ====Done====
7276 14:44:49.989213
7277 14:44:49.991662 [DutyScan_Calibration_Flow] k_type=1
7278 14:44:50.008008
7279 14:44:50.008604 ==DQS 0 ==
7280 14:44:50.011267 Final DQS duty delay cell = 0
7281 14:44:50.014773 [0] MAX Duty = 5218%(X100), DQS PI = 30
7282 14:44:50.018131 [0] MIN Duty = 4969%(X100), DQS PI = 0
7283 14:44:50.020921 [0] AVG Duty = 5093%(X100)
7284 14:44:50.021395
7285 14:44:50.021775 ==DQS 1 ==
7286 14:44:50.024511 Final DQS duty delay cell = -4
7287 14:44:50.027636 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7288 14:44:50.031029 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7289 14:44:50.034436 [-4] AVG Duty = 4969%(X100)
7290 14:44:50.034911
7291 14:44:50.037803 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7292 14:44:50.038280
7293 14:44:50.041423 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7294 14:44:50.044277 [DutyScan_Calibration_Flow] ====Done====
7295 14:44:50.044881
7296 14:44:50.047752 [DutyScan_Calibration_Flow] k_type=3
7297 14:44:50.065906
7298 14:44:50.066470 ==DQM 0 ==
7299 14:44:50.069055 Final DQM duty delay cell = 0
7300 14:44:50.072270 [0] MAX Duty = 5062%(X100), DQS PI = 26
7301 14:44:50.075291 [0] MIN Duty = 4813%(X100), DQS PI = 50
7302 14:44:50.075768 [0] AVG Duty = 4937%(X100)
7303 14:44:50.078604
7304 14:44:50.079168 ==DQM 1 ==
7305 14:44:50.081857 Final DQM duty delay cell = 0
7306 14:44:50.085296 [0] MAX Duty = 5249%(X100), DQS PI = 28
7307 14:44:50.088518 [0] MIN Duty = 5000%(X100), DQS PI = 20
7308 14:44:50.091800 [0] AVG Duty = 5124%(X100)
7309 14:44:50.092271
7310 14:44:50.095241 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7311 14:44:50.095712
7312 14:44:50.098489 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7313 14:44:50.101706 [DutyScan_Calibration_Flow] ====Done====
7314 14:44:50.102221
7315 14:44:50.105260 [DutyScan_Calibration_Flow] k_type=2
7316 14:44:50.122255
7317 14:44:50.122722 ==DQ 0 ==
7318 14:44:50.125808 Final DQ duty delay cell = 0
7319 14:44:50.128998 [0] MAX Duty = 5124%(X100), DQS PI = 34
7320 14:44:50.132538 [0] MIN Duty = 5000%(X100), DQS PI = 0
7321 14:44:50.132996 [0] AVG Duty = 5062%(X100)
7322 14:44:50.133339
7323 14:44:50.135687 ==DQ 1 ==
7324 14:44:50.139278 Final DQ duty delay cell = 0
7325 14:44:50.142142 [0] MAX Duty = 4969%(X100), DQS PI = 52
7326 14:44:50.145792 [0] MIN Duty = 4875%(X100), DQS PI = 0
7327 14:44:50.146218 [0] AVG Duty = 4922%(X100)
7328 14:44:50.146557
7329 14:44:50.148977 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7330 14:44:50.149403
7331 14:44:50.152365 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7332 14:44:50.159164 [DutyScan_Calibration_Flow] ====Done====
7333 14:44:50.159580 ==
7334 14:44:50.162275 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 14:44:50.165670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 14:44:50.166088 ==
7337 14:44:50.168902 [Duty_Offset_Calibration]
7338 14:44:50.169315 B0:0 B1:-1 CA:2
7339 14:44:50.169644
7340 14:44:50.172360 [DutyScan_Calibration_Flow] k_type=0
7341 14:44:50.182786
7342 14:44:50.183306 ==CLK 0==
7343 14:44:50.185880 Final CLK duty delay cell = 0
7344 14:44:50.189347 [0] MAX Duty = 5156%(X100), DQS PI = 10
7345 14:44:50.192229 [0] MIN Duty = 4906%(X100), DQS PI = 46
7346 14:44:50.192688 [0] AVG Duty = 5031%(X100)
7347 14:44:50.195941
7348 14:44:50.199397 CH1 CLK Duty spec in!! Max-Min= 250%
7349 14:44:50.202447 [DutyScan_Calibration_Flow] ====Done====
7350 14:44:50.202907
7351 14:44:50.205589 [DutyScan_Calibration_Flow] k_type=1
7352 14:44:50.222540
7353 14:44:50.223103 ==DQS 0 ==
7354 14:44:50.225350 Final DQS duty delay cell = 0
7355 14:44:50.229015 [0] MAX Duty = 5093%(X100), DQS PI = 24
7356 14:44:50.232688 [0] MIN Duty = 4969%(X100), DQS PI = 16
7357 14:44:50.235918 [0] AVG Duty = 5031%(X100)
7358 14:44:50.236466
7359 14:44:50.236867 ==DQS 1 ==
7360 14:44:50.239386 Final DQS duty delay cell = 0
7361 14:44:50.242337 [0] MAX Duty = 5187%(X100), DQS PI = 0
7362 14:44:50.245755 [0] MIN Duty = 4844%(X100), DQS PI = 32
7363 14:44:50.248989 [0] AVG Duty = 5015%(X100)
7364 14:44:50.249539
7365 14:44:50.252271 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7366 14:44:50.252887
7367 14:44:50.255655 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7368 14:44:50.258602 [DutyScan_Calibration_Flow] ====Done====
7369 14:44:50.259064
7370 14:44:50.262526 [DutyScan_Calibration_Flow] k_type=3
7371 14:44:50.280284
7372 14:44:50.280878 ==DQM 0 ==
7373 14:44:50.283728 Final DQM duty delay cell = 4
7374 14:44:50.286381 [4] MAX Duty = 5125%(X100), DQS PI = 8
7375 14:44:50.290304 [4] MIN Duty = 4969%(X100), DQS PI = 46
7376 14:44:50.293145 [4] AVG Duty = 5047%(X100)
7377 14:44:50.293607
7378 14:44:50.293970 ==DQM 1 ==
7379 14:44:50.296599 Final DQM duty delay cell = 0
7380 14:44:50.300518 [0] MAX Duty = 5281%(X100), DQS PI = 58
7381 14:44:50.303659 [0] MIN Duty = 4876%(X100), DQS PI = 34
7382 14:44:50.306939 [0] AVG Duty = 5078%(X100)
7383 14:44:50.307493
7384 14:44:50.309652 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7385 14:44:50.310111
7386 14:44:50.313501 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7387 14:44:50.316850 [DutyScan_Calibration_Flow] ====Done====
7388 14:44:50.317402
7389 14:44:50.320048 [DutyScan_Calibration_Flow] k_type=2
7390 14:44:50.336945
7391 14:44:50.337512 ==DQ 0 ==
7392 14:44:50.340096 Final DQ duty delay cell = 0
7393 14:44:50.343623 [0] MAX Duty = 5062%(X100), DQS PI = 18
7394 14:44:50.346647 [0] MIN Duty = 4969%(X100), DQS PI = 0
7395 14:44:50.347113 [0] AVG Duty = 5015%(X100)
7396 14:44:50.347483
7397 14:44:50.350191 ==DQ 1 ==
7398 14:44:50.353452 Final DQ duty delay cell = 0
7399 14:44:50.356703 [0] MAX Duty = 5062%(X100), DQS PI = 2
7400 14:44:50.360344 [0] MIN Duty = 4813%(X100), DQS PI = 34
7401 14:44:50.360966 [0] AVG Duty = 4937%(X100)
7402 14:44:50.361426
7403 14:44:50.363447 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7404 14:44:50.363911
7405 14:44:50.366846 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7406 14:44:50.373481 [DutyScan_Calibration_Flow] ====Done====
7407 14:44:50.376789 nWR fixed to 30
7408 14:44:50.377370 [ModeRegInit_LP4] CH0 RK0
7409 14:44:50.380078 [ModeRegInit_LP4] CH0 RK1
7410 14:44:50.383585 [ModeRegInit_LP4] CH1 RK0
7411 14:44:50.384149 [ModeRegInit_LP4] CH1 RK1
7412 14:44:50.386825 match AC timing 5
7413 14:44:50.389857 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 14:44:50.393075 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 14:44:50.399506 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 14:44:50.402917 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 14:44:50.409734 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 14:44:50.410201 [MiockJmeterHQA]
7419 14:44:50.410573
7420 14:44:50.413272 [DramcMiockJmeter] u1RxGatingPI = 0
7421 14:44:50.416773 0 : 4253, 4026
7422 14:44:50.417340 4 : 4252, 4027
7423 14:44:50.417721 8 : 4252, 4026
7424 14:44:50.420016 12 : 4252, 4026
7425 14:44:50.420488 16 : 4252, 4027
7426 14:44:50.423201 20 : 4252, 4027
7427 14:44:50.423775 24 : 4252, 4027
7428 14:44:50.426703 28 : 4363, 4138
7429 14:44:50.427176 32 : 4252, 4027
7430 14:44:50.427553 36 : 4363, 4138
7431 14:44:50.429882 40 : 4253, 4027
7432 14:44:50.430455 44 : 4253, 4026
7433 14:44:50.433002 48 : 4253, 4027
7434 14:44:50.433475 52 : 4250, 4026
7435 14:44:50.436743 56 : 4365, 4140
7436 14:44:50.437320 60 : 4363, 4140
7437 14:44:50.439768 64 : 4250, 4027
7438 14:44:50.440339 68 : 4252, 4030
7439 14:44:50.440759 72 : 4361, 4137
7440 14:44:50.443073 76 : 4250, 4026
7441 14:44:50.443661 80 : 4363, 4140
7442 14:44:50.446127 84 : 4250, 4027
7443 14:44:50.446602 88 : 4250, 3511
7444 14:44:50.449851 92 : 4250, 0
7445 14:44:50.450424 96 : 4250, 0
7446 14:44:50.450804 100 : 4250, 0
7447 14:44:50.452759 104 : 4253, 0
7448 14:44:50.453231 108 : 4250, 0
7449 14:44:50.456316 112 : 4250, 0
7450 14:44:50.456821 116 : 4252, 0
7451 14:44:50.457203 120 : 4361, 0
7452 14:44:50.459726 124 : 4361, 0
7453 14:44:50.460200 128 : 4366, 0
7454 14:44:50.460611 132 : 4249, 0
7455 14:44:50.462717 136 : 4361, 0
7456 14:44:50.463191 140 : 4250, 0
7457 14:44:50.466068 144 : 4250, 0
7458 14:44:50.466542 148 : 4250, 0
7459 14:44:50.466921 152 : 4250, 0
7460 14:44:50.469457 156 : 4253, 0
7461 14:44:50.469933 160 : 4250, 0
7462 14:44:50.472730 164 : 4250, 0
7463 14:44:50.473205 168 : 4253, 0
7464 14:44:50.473587 172 : 4361, 0
7465 14:44:50.475946 176 : 4360, 0
7466 14:44:50.476423 180 : 4250, 0
7467 14:44:50.479655 184 : 4249, 0
7468 14:44:50.480124 188 : 4361, 0
7469 14:44:50.480497 192 : 4249, 0
7470 14:44:50.482901 196 : 4250, 0
7471 14:44:50.483394 200 : 4361, 12
7472 14:44:50.486389 204 : 4363, 2611
7473 14:44:50.486956 208 : 4250, 4027
7474 14:44:50.489677 212 : 4250, 4027
7475 14:44:50.490147 216 : 4252, 4030
7476 14:44:50.490524 220 : 4253, 4029
7477 14:44:50.492836 224 : 4252, 4029
7478 14:44:50.493431 228 : 4363, 4140
7479 14:44:50.495933 232 : 4255, 4029
7480 14:44:50.496481 236 : 4250, 4027
7481 14:44:50.499310 240 : 4250, 4027
7482 14:44:50.499811 244 : 4363, 4140
7483 14:44:50.502819 248 : 4362, 4137
7484 14:44:50.503373 252 : 4247, 4024
7485 14:44:50.506053 256 : 4365, 4140
7486 14:44:50.506562 260 : 4250, 4027
7487 14:44:50.509162 264 : 4249, 4027
7488 14:44:50.509636 268 : 4252, 4030
7489 14:44:50.512473 272 : 4250, 4026
7490 14:44:50.512977 276 : 4252, 4029
7491 14:44:50.513427 280 : 4363, 4140
7492 14:44:50.515789 284 : 4255, 4029
7493 14:44:50.516215 288 : 4250, 4027
7494 14:44:50.519307 292 : 4250, 4027
7495 14:44:50.519894 296 : 4363, 4140
7496 14:44:50.522853 300 : 4362, 4137
7497 14:44:50.523425 304 : 4250, 4026
7498 14:44:50.526114 308 : 4365, 4140
7499 14:44:50.526587 312 : 4252, 3916
7500 14:44:50.529678 316 : 4250, 1783
7501 14:44:50.530256
7502 14:44:50.530631 MIOCK jitter meter ch=0
7503 14:44:50.530974
7504 14:44:50.532489 1T = (316-92) = 224 dly cells
7505 14:44:50.539515 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7506 14:44:50.540225 ==
7507 14:44:50.542541 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 14:44:50.546336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 14:44:50.546913 ==
7510 14:44:50.552626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 14:44:50.556059 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 14:44:50.559180 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 14:44:50.565882 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 14:44:50.575693 [CA 0] Center 43 (13~73) winsize 61
7515 14:44:50.578886 [CA 1] Center 43 (13~73) winsize 61
7516 14:44:50.582722 [CA 2] Center 38 (8~68) winsize 61
7517 14:44:50.585719 [CA 3] Center 37 (8~67) winsize 60
7518 14:44:50.589249 [CA 4] Center 36 (6~66) winsize 61
7519 14:44:50.592409 [CA 5] Center 35 (5~66) winsize 62
7520 14:44:50.593042
7521 14:44:50.595424 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 14:44:50.595893
7523 14:44:50.599063 [CATrainingPosCal] consider 1 rank data
7524 14:44:50.602290 u2DelayCellTimex100 = 290/100 ps
7525 14:44:50.605439 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7526 14:44:50.612085 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7527 14:44:50.615446 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7528 14:44:50.618837 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7529 14:44:50.621965 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7530 14:44:50.625213 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7531 14:44:50.625718
7532 14:44:50.628407 CA PerBit enable=1, Macro0, CA PI delay=35
7533 14:44:50.628959
7534 14:44:50.632002 [CBTSetCACLKResult] CA Dly = 35
7535 14:44:50.635153 CS Dly: 10 (0~41)
7536 14:44:50.638506 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 14:44:50.641871 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 14:44:50.642387 ==
7539 14:44:50.644963 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 14:44:50.648519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 14:44:50.652061 ==
7542 14:44:50.655273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 14:44:50.658276 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 14:44:50.665030 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 14:44:50.668315 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 14:44:50.678876 [CA 0] Center 43 (13~74) winsize 62
7547 14:44:50.682290 [CA 1] Center 43 (13~73) winsize 61
7548 14:44:50.685398 [CA 2] Center 38 (9~68) winsize 60
7549 14:44:50.688882 [CA 3] Center 38 (9~68) winsize 60
7550 14:44:50.692225 [CA 4] Center 37 (7~67) winsize 61
7551 14:44:50.695430 [CA 5] Center 36 (7~66) winsize 60
7552 14:44:50.695622
7553 14:44:50.698669 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 14:44:50.698828
7555 14:44:50.702027 [CATrainingPosCal] consider 2 rank data
7556 14:44:50.705292 u2DelayCellTimex100 = 290/100 ps
7557 14:44:50.708498 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7558 14:44:50.715237 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7559 14:44:50.718603 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7560 14:44:50.721849 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7561 14:44:50.724852 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 14:44:50.728220 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7563 14:44:50.728304
7564 14:44:50.731555 CA PerBit enable=1, Macro0, CA PI delay=36
7565 14:44:50.731639
7566 14:44:50.734874 [CBTSetCACLKResult] CA Dly = 36
7567 14:44:50.738208 CS Dly: 11 (0~43)
7568 14:44:50.741746 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 14:44:50.745025 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 14:44:50.745111
7571 14:44:50.748244 ----->DramcWriteLeveling(PI) begin...
7572 14:44:50.748332 ==
7573 14:44:50.751417 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 14:44:50.754966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 14:44:50.758056 ==
7576 14:44:50.761645 Write leveling (Byte 0): 38 => 38
7577 14:44:50.761730 Write leveling (Byte 1): 29 => 29
7578 14:44:50.764939 DramcWriteLeveling(PI) end<-----
7579 14:44:50.765023
7580 14:44:50.765090 ==
7581 14:44:50.767985 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 14:44:50.774718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 14:44:50.774804 ==
7584 14:44:50.777884 [Gating] SW mode calibration
7585 14:44:50.784702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 14:44:50.788245 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 14:44:50.794610 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 14:44:50.797925 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 14:44:50.801544 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7590 14:44:50.808165 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7591 14:44:50.811123 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7592 14:44:50.814396 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7593 14:44:50.821289 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 14:44:50.824746 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 14:44:50.828274 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 14:44:50.831473 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 14:44:50.838049 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7598 14:44:50.841312 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7599 14:44:50.844672 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7600 14:44:50.851167 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7601 14:44:50.854325 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 14:44:50.857781 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 14:44:50.864617 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 14:44:50.867740 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7605 14:44:50.871117 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7606 14:44:50.877452 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7607 14:44:50.881086 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7608 14:44:50.884151 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7609 14:44:50.891150 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 14:44:50.894407 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 14:44:50.897744 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 14:44:50.904438 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 14:44:50.907973 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 14:44:50.911277 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 14:44:50.917711 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7616 14:44:50.920923 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7617 14:44:50.924445 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 14:44:50.931319 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 14:44:50.934145 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 14:44:50.937443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 14:44:50.944036 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 14:44:50.947526 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 14:44:50.950821 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 14:44:50.957797 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 14:44:50.960810 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 14:44:50.964398 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 14:44:50.967581 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 14:44:50.974246 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 14:44:50.977747 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 14:44:50.980738 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7631 14:44:50.984185 Total UI for P1: 0, mck2ui 16
7632 14:44:50.987434 best dqsien dly found for B0: ( 1, 9, 8)
7633 14:44:50.994418 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7634 14:44:50.997667 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 14:44:51.000915 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 14:44:51.004254 Total UI for P1: 0, mck2ui 16
7637 14:44:51.007464 best dqsien dly found for B1: ( 1, 9, 20)
7638 14:44:51.011063 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7639 14:44:51.014281 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7640 14:44:51.014364
7641 14:44:51.020987 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7642 14:44:51.024350 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7643 14:44:51.027330 [Gating] SW calibration Done
7644 14:44:51.027417 ==
7645 14:44:51.030672 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 14:44:51.033848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 14:44:51.033934 ==
7648 14:44:51.034001 RX Vref Scan: 0
7649 14:44:51.034063
7650 14:44:51.037608 RX Vref 0 -> 0, step: 1
7651 14:44:51.037693
7652 14:44:51.040896 RX Delay 0 -> 252, step: 8
7653 14:44:51.044216 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7654 14:44:51.047544 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7655 14:44:51.050826 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7656 14:44:51.057406 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7657 14:44:51.061267 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7658 14:44:51.064528 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7659 14:44:51.067433 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7660 14:44:51.071167 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7661 14:44:51.074094 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7662 14:44:51.080694 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7663 14:44:51.084391 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7664 14:44:51.087418 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7665 14:44:51.090987 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7666 14:44:51.097421 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7667 14:44:51.100663 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7668 14:44:51.103791 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7669 14:44:51.103877 ==
7670 14:44:51.107166 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 14:44:51.110931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 14:44:51.111017 ==
7673 14:44:51.114236 DQS Delay:
7674 14:44:51.114322 DQS0 = 0, DQS1 = 0
7675 14:44:51.114389 DQM Delay:
7676 14:44:51.117581 DQM0 = 138, DQM1 = 126
7677 14:44:51.117666 DQ Delay:
7678 14:44:51.120841 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7679 14:44:51.123935 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7680 14:44:51.130767 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7681 14:44:51.133684 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7682 14:44:51.133769
7683 14:44:51.133834
7684 14:44:51.133896 ==
7685 14:44:51.137127 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 14:44:51.140577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 14:44:51.140691 ==
7688 14:44:51.140758
7689 14:44:51.140821
7690 14:44:51.143955 TX Vref Scan disable
7691 14:44:51.147146 == TX Byte 0 ==
7692 14:44:51.150823 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7693 14:44:51.153730 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7694 14:44:51.157036 == TX Byte 1 ==
7695 14:44:51.160383 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7696 14:44:51.163740 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7697 14:44:51.163826 ==
7698 14:44:51.167159 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 14:44:51.170496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 14:44:51.170584 ==
7701 14:44:51.185462
7702 14:44:51.189033 TX Vref early break, caculate TX vref
7703 14:44:51.192217 TX Vref=16, minBit 12, minWin=22, winSum=376
7704 14:44:51.195572 TX Vref=18, minBit 12, minWin=23, winSum=392
7705 14:44:51.198983 TX Vref=20, minBit 2, minWin=24, winSum=400
7706 14:44:51.202295 TX Vref=22, minBit 2, minWin=24, winSum=408
7707 14:44:51.205894 TX Vref=24, minBit 0, minWin=25, winSum=418
7708 14:44:51.212329 TX Vref=26, minBit 12, minWin=25, winSum=429
7709 14:44:51.215596 TX Vref=28, minBit 0, minWin=26, winSum=433
7710 14:44:51.219001 TX Vref=30, minBit 0, minWin=26, winSum=427
7711 14:44:51.221988 TX Vref=32, minBit 1, minWin=25, winSum=415
7712 14:44:51.225544 TX Vref=34, minBit 7, minWin=24, winSum=405
7713 14:44:51.232077 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
7714 14:44:51.232164
7715 14:44:51.235650 Final TX Range 0 Vref 28
7716 14:44:51.235758
7717 14:44:51.235843 ==
7718 14:44:51.238851 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 14:44:51.242132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 14:44:51.242215 ==
7721 14:44:51.242280
7722 14:44:51.242338
7723 14:44:51.245256 TX Vref Scan disable
7724 14:44:51.252252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7725 14:44:51.252367 == TX Byte 0 ==
7726 14:44:51.255626 u2DelayCellOfst[0]=13 cells (4 PI)
7727 14:44:51.258994 u2DelayCellOfst[1]=20 cells (6 PI)
7728 14:44:51.261926 u2DelayCellOfst[2]=13 cells (4 PI)
7729 14:44:51.265320 u2DelayCellOfst[3]=13 cells (4 PI)
7730 14:44:51.268706 u2DelayCellOfst[4]=10 cells (3 PI)
7731 14:44:51.271967 u2DelayCellOfst[5]=0 cells (0 PI)
7732 14:44:51.275720 u2DelayCellOfst[6]=20 cells (6 PI)
7733 14:44:51.278607 u2DelayCellOfst[7]=16 cells (5 PI)
7734 14:44:51.282074 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7735 14:44:51.285425 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7736 14:44:51.288730 == TX Byte 1 ==
7737 14:44:51.288814 u2DelayCellOfst[8]=0 cells (0 PI)
7738 14:44:51.292224 u2DelayCellOfst[9]=0 cells (0 PI)
7739 14:44:51.295344 u2DelayCellOfst[10]=6 cells (2 PI)
7740 14:44:51.298675 u2DelayCellOfst[11]=3 cells (1 PI)
7741 14:44:51.302255 u2DelayCellOfst[12]=13 cells (4 PI)
7742 14:44:51.305306 u2DelayCellOfst[13]=10 cells (3 PI)
7743 14:44:51.308660 u2DelayCellOfst[14]=13 cells (4 PI)
7744 14:44:51.312110 u2DelayCellOfst[15]=10 cells (3 PI)
7745 14:44:51.315452 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7746 14:44:51.322136 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7747 14:44:51.322232 DramC Write-DBI on
7748 14:44:51.322301 ==
7749 14:44:51.325454 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 14:44:51.328691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 14:44:51.332048 ==
7752 14:44:51.332133
7753 14:44:51.332199
7754 14:44:51.332262 TX Vref Scan disable
7755 14:44:51.335519 == TX Byte 0 ==
7756 14:44:51.339045 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7757 14:44:51.341934 == TX Byte 1 ==
7758 14:44:51.345218 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7759 14:44:51.345303 DramC Write-DBI off
7760 14:44:51.348922
7761 14:44:51.349006 [DATLAT]
7762 14:44:51.349072 Freq=1600, CH0 RK0
7763 14:44:51.349134
7764 14:44:51.352042 DATLAT Default: 0xf
7765 14:44:51.352125 0, 0xFFFF, sum = 0
7766 14:44:51.355396 1, 0xFFFF, sum = 0
7767 14:44:51.355482 2, 0xFFFF, sum = 0
7768 14:44:51.358798 3, 0xFFFF, sum = 0
7769 14:44:51.362028 4, 0xFFFF, sum = 0
7770 14:44:51.362113 5, 0xFFFF, sum = 0
7771 14:44:51.365721 6, 0xFFFF, sum = 0
7772 14:44:51.365807 7, 0xFFFF, sum = 0
7773 14:44:51.368734 8, 0xFFFF, sum = 0
7774 14:44:51.368818 9, 0xFFFF, sum = 0
7775 14:44:51.372061 10, 0xFFFF, sum = 0
7776 14:44:51.372146 11, 0xFFFF, sum = 0
7777 14:44:51.375300 12, 0xFFFF, sum = 0
7778 14:44:51.375385 13, 0xFFFF, sum = 0
7779 14:44:51.378640 14, 0x0, sum = 1
7780 14:44:51.378726 15, 0x0, sum = 2
7781 14:44:51.381847 16, 0x0, sum = 3
7782 14:44:51.381932 17, 0x0, sum = 4
7783 14:44:51.385550 best_step = 15
7784 14:44:51.385635
7785 14:44:51.385701 ==
7786 14:44:51.388531 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 14:44:51.392066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 14:44:51.392150 ==
7789 14:44:51.395068 RX Vref Scan: 1
7790 14:44:51.395152
7791 14:44:51.395218 Set Vref Range= 24 -> 127
7792 14:44:51.395279
7793 14:44:51.398362 RX Vref 24 -> 127, step: 1
7794 14:44:51.398446
7795 14:44:51.402047 RX Delay 19 -> 252, step: 4
7796 14:44:51.402132
7797 14:44:51.405209 Set Vref, RX VrefLevel [Byte0]: 24
7798 14:44:51.408362 [Byte1]: 24
7799 14:44:51.408447
7800 14:44:51.411787 Set Vref, RX VrefLevel [Byte0]: 25
7801 14:44:51.415213 [Byte1]: 25
7802 14:44:51.415299
7803 14:44:51.418864 Set Vref, RX VrefLevel [Byte0]: 26
7804 14:44:51.421722 [Byte1]: 26
7805 14:44:51.425522
7806 14:44:51.425605 Set Vref, RX VrefLevel [Byte0]: 27
7807 14:44:51.428858 [Byte1]: 27
7808 14:44:51.433257
7809 14:44:51.433341 Set Vref, RX VrefLevel [Byte0]: 28
7810 14:44:51.436453 [Byte1]: 28
7811 14:44:51.440684
7812 14:44:51.440766 Set Vref, RX VrefLevel [Byte0]: 29
7813 14:44:51.444138 [Byte1]: 29
7814 14:44:51.448476
7815 14:44:51.448568 Set Vref, RX VrefLevel [Byte0]: 30
7816 14:44:51.451734 [Byte1]: 30
7817 14:44:51.455941
7818 14:44:51.456026 Set Vref, RX VrefLevel [Byte0]: 31
7819 14:44:51.459302 [Byte1]: 31
7820 14:44:51.463467
7821 14:44:51.463552 Set Vref, RX VrefLevel [Byte0]: 32
7822 14:44:51.466929 [Byte1]: 32
7823 14:44:51.471077
7824 14:44:51.471161 Set Vref, RX VrefLevel [Byte0]: 33
7825 14:44:51.474475 [Byte1]: 33
7826 14:44:51.479101
7827 14:44:51.479188 Set Vref, RX VrefLevel [Byte0]: 34
7828 14:44:51.482131 [Byte1]: 34
7829 14:44:51.486413
7830 14:44:51.486511 Set Vref, RX VrefLevel [Byte0]: 35
7831 14:44:51.489666 [Byte1]: 35
7832 14:44:51.494058
7833 14:44:51.494150 Set Vref, RX VrefLevel [Byte0]: 36
7834 14:44:51.497249 [Byte1]: 36
7835 14:44:51.501405
7836 14:44:51.501497 Set Vref, RX VrefLevel [Byte0]: 37
7837 14:44:51.504511 [Byte1]: 37
7838 14:44:51.509026
7839 14:44:51.509116 Set Vref, RX VrefLevel [Byte0]: 38
7840 14:44:51.512076 [Byte1]: 38
7841 14:44:51.516370
7842 14:44:51.516459 Set Vref, RX VrefLevel [Byte0]: 39
7843 14:44:51.520002 [Byte1]: 39
7844 14:44:51.524161
7845 14:44:51.524250 Set Vref, RX VrefLevel [Byte0]: 40
7846 14:44:51.527254 [Byte1]: 40
7847 14:44:51.531424
7848 14:44:51.531513 Set Vref, RX VrefLevel [Byte0]: 41
7849 14:44:51.535163 [Byte1]: 41
7850 14:44:51.539006
7851 14:44:51.539093 Set Vref, RX VrefLevel [Byte0]: 42
7852 14:44:51.542305 [Byte1]: 42
7853 14:44:51.547014
7854 14:44:51.547103 Set Vref, RX VrefLevel [Byte0]: 43
7855 14:44:51.550028 [Byte1]: 43
7856 14:44:51.554333
7857 14:44:51.554422 Set Vref, RX VrefLevel [Byte0]: 44
7858 14:44:51.557546 [Byte1]: 44
7859 14:44:51.562170
7860 14:44:51.562267 Set Vref, RX VrefLevel [Byte0]: 45
7861 14:44:51.565485 [Byte1]: 45
7862 14:44:51.569724
7863 14:44:51.569815 Set Vref, RX VrefLevel [Byte0]: 46
7864 14:44:51.572957 [Byte1]: 46
7865 14:44:51.577287
7866 14:44:51.577375 Set Vref, RX VrefLevel [Byte0]: 47
7867 14:44:51.580682 [Byte1]: 47
7868 14:44:51.584515
7869 14:44:51.584620 Set Vref, RX VrefLevel [Byte0]: 48
7870 14:44:51.587764 [Byte1]: 48
7871 14:44:51.592056
7872 14:44:51.592144 Set Vref, RX VrefLevel [Byte0]: 49
7873 14:44:51.595539 [Byte1]: 49
7874 14:44:51.599710
7875 14:44:51.599820 Set Vref, RX VrefLevel [Byte0]: 50
7876 14:44:51.602956 [Byte1]: 50
7877 14:44:51.607588
7878 14:44:51.607678 Set Vref, RX VrefLevel [Byte0]: 51
7879 14:44:51.610919 [Byte1]: 51
7880 14:44:51.614823
7881 14:44:51.614911 Set Vref, RX VrefLevel [Byte0]: 52
7882 14:44:51.618277 [Byte1]: 52
7883 14:44:51.622595
7884 14:44:51.622685 Set Vref, RX VrefLevel [Byte0]: 53
7885 14:44:51.626041 [Byte1]: 53
7886 14:44:51.630060
7887 14:44:51.630148 Set Vref, RX VrefLevel [Byte0]: 54
7888 14:44:51.633275 [Byte1]: 54
7889 14:44:51.637878
7890 14:44:51.637970 Set Vref, RX VrefLevel [Byte0]: 55
7891 14:44:51.641256 [Byte1]: 55
7892 14:44:51.645517
7893 14:44:51.645618 Set Vref, RX VrefLevel [Byte0]: 56
7894 14:44:51.648711 [Byte1]: 56
7895 14:44:51.652857
7896 14:44:51.652947 Set Vref, RX VrefLevel [Byte0]: 57
7897 14:44:51.659489 [Byte1]: 57
7898 14:44:51.659582
7899 14:44:51.662782 Set Vref, RX VrefLevel [Byte0]: 58
7900 14:44:51.666124 [Byte1]: 58
7901 14:44:51.666210
7902 14:44:51.669504 Set Vref, RX VrefLevel [Byte0]: 59
7903 14:44:51.672774 [Byte1]: 59
7904 14:44:51.672861
7905 14:44:51.675951 Set Vref, RX VrefLevel [Byte0]: 60
7906 14:44:51.679358 [Byte1]: 60
7907 14:44:51.683246
7908 14:44:51.683331 Set Vref, RX VrefLevel [Byte0]: 61
7909 14:44:51.686515 [Byte1]: 61
7910 14:44:51.690714
7911 14:44:51.690800 Set Vref, RX VrefLevel [Byte0]: 62
7912 14:44:51.693832 [Byte1]: 62
7913 14:44:51.698147
7914 14:44:51.698239 Set Vref, RX VrefLevel [Byte0]: 63
7915 14:44:51.701570 [Byte1]: 63
7916 14:44:51.705966
7917 14:44:51.706071 Set Vref, RX VrefLevel [Byte0]: 64
7918 14:44:51.709041 [Byte1]: 64
7919 14:44:51.713271
7920 14:44:51.713361 Set Vref, RX VrefLevel [Byte0]: 65
7921 14:44:51.716974 [Byte1]: 65
7922 14:44:51.721039
7923 14:44:51.721128 Set Vref, RX VrefLevel [Byte0]: 66
7924 14:44:51.724299 [Byte1]: 66
7925 14:44:51.728450
7926 14:44:51.728559 Set Vref, RX VrefLevel [Byte0]: 67
7927 14:44:51.731907 [Byte1]: 67
7928 14:44:51.735927
7929 14:44:51.736014 Set Vref, RX VrefLevel [Byte0]: 68
7930 14:44:51.739528 [Byte1]: 68
7931 14:44:51.743683
7932 14:44:51.743770 Set Vref, RX VrefLevel [Byte0]: 69
7933 14:44:51.746979 [Byte1]: 69
7934 14:44:51.751563
7935 14:44:51.751649 Set Vref, RX VrefLevel [Byte0]: 70
7936 14:44:51.754774 [Byte1]: 70
7937 14:44:51.758660
7938 14:44:51.758745 Set Vref, RX VrefLevel [Byte0]: 71
7939 14:44:51.762017 [Byte1]: 71
7940 14:44:51.766647
7941 14:44:51.766736 Set Vref, RX VrefLevel [Byte0]: 72
7942 14:44:51.769657 [Byte1]: 72
7943 14:44:51.774197
7944 14:44:51.774282 Set Vref, RX VrefLevel [Byte0]: 73
7945 14:44:51.777182 [Byte1]: 73
7946 14:44:51.781446
7947 14:44:51.781531 Set Vref, RX VrefLevel [Byte0]: 74
7948 14:44:51.785123 [Byte1]: 74
7949 14:44:51.789250
7950 14:44:51.789335 Set Vref, RX VrefLevel [Byte0]: 75
7951 14:44:51.792515 [Byte1]: 75
7952 14:44:51.796880
7953 14:44:51.796987 Set Vref, RX VrefLevel [Byte0]: 76
7954 14:44:51.799927 [Byte1]: 76
7955 14:44:51.804328
7956 14:44:51.804413 Set Vref, RX VrefLevel [Byte0]: 77
7957 14:44:51.807511 [Byte1]: 77
7958 14:44:51.811842
7959 14:44:51.811940 Set Vref, RX VrefLevel [Byte0]: 78
7960 14:44:51.814971 [Byte1]: 78
7961 14:44:51.819363
7962 14:44:51.819454 Set Vref, RX VrefLevel [Byte0]: 79
7963 14:44:51.822937 [Byte1]: 79
7964 14:44:51.826802
7965 14:44:51.826892 Final RX Vref Byte 0 = 59 to rank0
7966 14:44:51.830429 Final RX Vref Byte 1 = 62 to rank0
7967 14:44:51.833715 Final RX Vref Byte 0 = 59 to rank1
7968 14:44:51.836857 Final RX Vref Byte 1 = 62 to rank1==
7969 14:44:51.840415 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 14:44:51.846928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 14:44:51.847032 ==
7972 14:44:51.847101 DQS Delay:
7973 14:44:51.847161 DQS0 = 0, DQS1 = 0
7974 14:44:51.850146 DQM Delay:
7975 14:44:51.850229 DQM0 = 135, DQM1 = 123
7976 14:44:51.853476 DQ Delay:
7977 14:44:51.856814 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7978 14:44:51.860516 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =142
7979 14:44:51.863614 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7980 14:44:51.866902 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
7981 14:44:51.866991
7982 14:44:51.867056
7983 14:44:51.867115
7984 14:44:51.870098 [DramC_TX_OE_Calibration] TA2
7985 14:44:51.873403 Original DQ_B0 (3 6) =30, OEN = 27
7986 14:44:51.876814 Original DQ_B1 (3 6) =30, OEN = 27
7987 14:44:51.880038 24, 0x0, End_B0=24 End_B1=24
7988 14:44:51.880128 25, 0x0, End_B0=25 End_B1=25
7989 14:44:51.883342 26, 0x0, End_B0=26 End_B1=26
7990 14:44:51.886704 27, 0x0, End_B0=27 End_B1=27
7991 14:44:51.890228 28, 0x0, End_B0=28 End_B1=28
7992 14:44:51.893443 29, 0x0, End_B0=29 End_B1=29
7993 14:44:51.893533 30, 0x0, End_B0=30 End_B1=30
7994 14:44:51.896734 31, 0x4141, End_B0=30 End_B1=30
7995 14:44:51.900033 Byte0 end_step=30 best_step=27
7996 14:44:51.903352 Byte1 end_step=30 best_step=27
7997 14:44:51.906660 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 14:44:51.910004 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 14:44:51.910090
8000 14:44:51.910156
8001 14:44:51.916357 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8002 14:44:51.919821 CH0 RK0: MR19=303, MR18=201E
8003 14:44:51.926292 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8004 14:44:51.926395
8005 14:44:51.929751 ----->DramcWriteLeveling(PI) begin...
8006 14:44:51.929839 ==
8007 14:44:51.933351 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 14:44:51.936484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 14:44:51.936597 ==
8010 14:44:51.939731 Write leveling (Byte 0): 38 => 38
8011 14:44:51.943312 Write leveling (Byte 1): 30 => 30
8012 14:44:51.946296 DramcWriteLeveling(PI) end<-----
8013 14:44:51.946384
8014 14:44:51.946450 ==
8015 14:44:51.949612 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 14:44:51.952990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 14:44:51.953080 ==
8018 14:44:51.956238 [Gating] SW mode calibration
8019 14:44:51.963083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 14:44:51.969593 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 14:44:51.972702 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 14:44:51.976144 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 14:44:51.982923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 14:44:51.986193 1 4 12 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
8025 14:44:51.989420 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 14:44:51.996482 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 14:44:51.999461 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 14:44:52.002872 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 14:44:52.009605 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 14:44:52.012494 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 14:44:52.016313 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 14:44:52.023285 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8033 14:44:52.026053 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8034 14:44:52.029246 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 14:44:52.036158 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 14:44:52.039106 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 14:44:52.042803 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 14:44:52.049127 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 14:44:52.052853 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8040 14:44:52.055904 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8041 14:44:52.062648 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 14:44:52.065826 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 14:44:52.069267 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 14:44:52.075805 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 14:44:52.079443 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 14:44:52.082414 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 14:44:52.089036 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 14:44:52.092356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8049 14:44:52.095644 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 14:44:52.102288 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 14:44:52.105594 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 14:44:52.109321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 14:44:52.115825 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 14:44:52.118985 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 14:44:52.122359 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 14:44:52.128810 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 14:44:52.132379 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 14:44:52.135854 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 14:44:52.138895 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 14:44:52.145674 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 14:44:52.149063 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 14:44:52.152055 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 14:44:52.158706 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 14:44:52.162138 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8065 14:44:52.165524 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8066 14:44:52.171885 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 14:44:52.175536 Total UI for P1: 0, mck2ui 16
8068 14:44:52.178934 best dqsien dly found for B0: ( 1, 9, 14)
8069 14:44:52.179024 Total UI for P1: 0, mck2ui 16
8070 14:44:52.185216 best dqsien dly found for B1: ( 1, 9, 16)
8071 14:44:52.188489 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8072 14:44:52.191853 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8073 14:44:52.191940
8074 14:44:52.195165 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8075 14:44:52.198640 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8076 14:44:52.202230 [Gating] SW calibration Done
8077 14:44:52.202322 ==
8078 14:44:52.205547 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 14:44:52.208863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 14:44:52.208953 ==
8081 14:44:52.211929 RX Vref Scan: 0
8082 14:44:52.212014
8083 14:44:52.212080 RX Vref 0 -> 0, step: 1
8084 14:44:52.215312
8085 14:44:52.215397 RX Delay 0 -> 252, step: 8
8086 14:44:52.218722 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8087 14:44:52.225309 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8088 14:44:52.228995 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8089 14:44:52.232318 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8090 14:44:52.235636 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8091 14:44:52.238722 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8092 14:44:52.245280 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8093 14:44:52.248752 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8094 14:44:52.252087 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8095 14:44:52.255161 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8096 14:44:52.258704 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8097 14:44:52.265298 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8098 14:44:52.268581 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8099 14:44:52.272086 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8100 14:44:52.275136 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8101 14:44:52.278496 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8102 14:44:52.281695 ==
8103 14:44:52.285058 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 14:44:52.288840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 14:44:52.288933 ==
8106 14:44:52.289001 DQS Delay:
8107 14:44:52.291866 DQS0 = 0, DQS1 = 0
8108 14:44:52.291950 DQM Delay:
8109 14:44:52.295256 DQM0 = 136, DQM1 = 124
8110 14:44:52.295342 DQ Delay:
8111 14:44:52.298632 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8112 14:44:52.301996 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8113 14:44:52.305193 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8114 14:44:52.308393 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8115 14:44:52.308479
8116 14:44:52.308553
8117 14:44:52.308660 ==
8118 14:44:52.311772 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 14:44:52.318392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 14:44:52.318488 ==
8121 14:44:52.318555
8122 14:44:52.318615
8123 14:44:52.318673 TX Vref Scan disable
8124 14:44:52.322293 == TX Byte 0 ==
8125 14:44:52.325643 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8126 14:44:52.329166 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8127 14:44:52.332032 == TX Byte 1 ==
8128 14:44:52.335452 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8129 14:44:52.338929 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8130 14:44:52.341913 ==
8131 14:44:52.345776 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 14:44:52.348699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 14:44:52.348790 ==
8134 14:44:52.362024
8135 14:44:52.365457 TX Vref early break, caculate TX vref
8136 14:44:52.368370 TX Vref=16, minBit 8, minWin=23, winSum=391
8137 14:44:52.371848 TX Vref=18, minBit 8, minWin=23, winSum=396
8138 14:44:52.375474 TX Vref=20, minBit 8, minWin=24, winSum=406
8139 14:44:52.378362 TX Vref=22, minBit 1, minWin=25, winSum=411
8140 14:44:52.382147 TX Vref=24, minBit 0, minWin=25, winSum=423
8141 14:44:52.388454 TX Vref=26, minBit 0, minWin=26, winSum=428
8142 14:44:52.391960 TX Vref=28, minBit 0, minWin=26, winSum=431
8143 14:44:52.395209 TX Vref=30, minBit 0, minWin=26, winSum=429
8144 14:44:52.398563 TX Vref=32, minBit 8, minWin=25, winSum=419
8145 14:44:52.401804 TX Vref=34, minBit 2, minWin=24, winSum=406
8146 14:44:52.408484 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8147 14:44:52.408635
8148 14:44:52.411629 Final TX Range 0 Vref 28
8149 14:44:52.411716
8150 14:44:52.411781 ==
8151 14:44:52.415231 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 14:44:52.418315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 14:44:52.418401 ==
8154 14:44:52.418469
8155 14:44:52.418530
8156 14:44:52.421645 TX Vref Scan disable
8157 14:44:52.428067 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8158 14:44:52.428174 == TX Byte 0 ==
8159 14:44:52.431895 u2DelayCellOfst[0]=16 cells (5 PI)
8160 14:44:52.435008 u2DelayCellOfst[1]=20 cells (6 PI)
8161 14:44:52.438605 u2DelayCellOfst[2]=13 cells (4 PI)
8162 14:44:52.441740 u2DelayCellOfst[3]=13 cells (4 PI)
8163 14:44:52.445047 u2DelayCellOfst[4]=10 cells (3 PI)
8164 14:44:52.448306 u2DelayCellOfst[5]=0 cells (0 PI)
8165 14:44:52.451635 u2DelayCellOfst[6]=20 cells (6 PI)
8166 14:44:52.454665 u2DelayCellOfst[7]=16 cells (5 PI)
8167 14:44:52.458064 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8168 14:44:52.461448 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8169 14:44:52.464751 == TX Byte 1 ==
8170 14:44:52.464843 u2DelayCellOfst[8]=3 cells (1 PI)
8171 14:44:52.468277 u2DelayCellOfst[9]=0 cells (0 PI)
8172 14:44:52.471590 u2DelayCellOfst[10]=6 cells (2 PI)
8173 14:44:52.474743 u2DelayCellOfst[11]=3 cells (1 PI)
8174 14:44:52.478245 u2DelayCellOfst[12]=13 cells (4 PI)
8175 14:44:52.481279 u2DelayCellOfst[13]=13 cells (4 PI)
8176 14:44:52.484686 u2DelayCellOfst[14]=13 cells (4 PI)
8177 14:44:52.488172 u2DelayCellOfst[15]=10 cells (3 PI)
8178 14:44:52.491410 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8179 14:44:52.497929 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8180 14:44:52.498042 DramC Write-DBI on
8181 14:44:52.498113 ==
8182 14:44:52.501233 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 14:44:52.504525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 14:44:52.507988 ==
8185 14:44:52.508076
8186 14:44:52.508144
8187 14:44:52.508207 TX Vref Scan disable
8188 14:44:52.511674 == TX Byte 0 ==
8189 14:44:52.515092 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8190 14:44:52.518325 == TX Byte 1 ==
8191 14:44:52.521671 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8192 14:44:52.525034 DramC Write-DBI off
8193 14:44:52.525125
8194 14:44:52.525192 [DATLAT]
8195 14:44:52.525254 Freq=1600, CH0 RK1
8196 14:44:52.525314
8197 14:44:52.528141 DATLAT Default: 0xf
8198 14:44:52.528226 0, 0xFFFF, sum = 0
8199 14:44:52.531613 1, 0xFFFF, sum = 0
8200 14:44:52.534927 2, 0xFFFF, sum = 0
8201 14:44:52.535015 3, 0xFFFF, sum = 0
8202 14:44:52.537806 4, 0xFFFF, sum = 0
8203 14:44:52.537892 5, 0xFFFF, sum = 0
8204 14:44:52.541221 6, 0xFFFF, sum = 0
8205 14:44:52.541308 7, 0xFFFF, sum = 0
8206 14:44:52.544467 8, 0xFFFF, sum = 0
8207 14:44:52.544600 9, 0xFFFF, sum = 0
8208 14:44:52.548231 10, 0xFFFF, sum = 0
8209 14:44:52.548318 11, 0xFFFF, sum = 0
8210 14:44:52.551344 12, 0xFFFF, sum = 0
8211 14:44:52.551430 13, 0xFFFF, sum = 0
8212 14:44:52.554511 14, 0x0, sum = 1
8213 14:44:52.554598 15, 0x0, sum = 2
8214 14:44:52.557900 16, 0x0, sum = 3
8215 14:44:52.557987 17, 0x0, sum = 4
8216 14:44:52.561599 best_step = 15
8217 14:44:52.561686
8218 14:44:52.561754 ==
8219 14:44:52.564617 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 14:44:52.567913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 14:44:52.568002 ==
8222 14:44:52.571392 RX Vref Scan: 0
8223 14:44:52.571478
8224 14:44:52.571544 RX Vref 0 -> 0, step: 1
8225 14:44:52.571606
8226 14:44:52.574506 RX Delay 11 -> 252, step: 4
8227 14:44:52.577950 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8228 14:44:52.584449 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8229 14:44:52.587735 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8230 14:44:52.591182 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8231 14:44:52.594563 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8232 14:44:52.597754 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8233 14:44:52.604753 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8234 14:44:52.608035 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8235 14:44:52.611311 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8236 14:44:52.614621 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8237 14:44:52.617542 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8238 14:44:52.624390 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8239 14:44:52.627862 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8240 14:44:52.631214 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8241 14:44:52.634770 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8242 14:44:52.637583 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8243 14:44:52.640942 ==
8244 14:44:52.641029 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 14:44:52.647547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 14:44:52.647640 ==
8247 14:44:52.647709 DQS Delay:
8248 14:44:52.650891 DQS0 = 0, DQS1 = 0
8249 14:44:52.650976 DQM Delay:
8250 14:44:52.654496 DQM0 = 133, DQM1 = 123
8251 14:44:52.654581 DQ Delay:
8252 14:44:52.657473 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8253 14:44:52.660829 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8254 14:44:52.664193 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8255 14:44:52.667557 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8256 14:44:52.667646
8257 14:44:52.667713
8258 14:44:52.667774
8259 14:44:52.670899 [DramC_TX_OE_Calibration] TA2
8260 14:44:52.674088 Original DQ_B0 (3 6) =30, OEN = 27
8261 14:44:52.677401 Original DQ_B1 (3 6) =30, OEN = 27
8262 14:44:52.681020 24, 0x0, End_B0=24 End_B1=24
8263 14:44:52.684319 25, 0x0, End_B0=25 End_B1=25
8264 14:44:52.684408 26, 0x0, End_B0=26 End_B1=26
8265 14:44:52.687810 27, 0x0, End_B0=27 End_B1=27
8266 14:44:52.690954 28, 0x0, End_B0=28 End_B1=28
8267 14:44:52.693934 29, 0x0, End_B0=29 End_B1=29
8268 14:44:52.694023 30, 0x0, End_B0=30 End_B1=30
8269 14:44:52.697435 31, 0x4545, End_B0=30 End_B1=30
8270 14:44:52.700900 Byte0 end_step=30 best_step=27
8271 14:44:52.704012 Byte1 end_step=30 best_step=27
8272 14:44:52.707722 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 14:44:52.710817 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 14:44:52.710908
8275 14:44:52.710974
8276 14:44:52.717408 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8277 14:44:52.720700 CH0 RK1: MR19=303, MR18=2310
8278 14:44:52.727477 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8279 14:44:52.730862 [RxdqsGatingPostProcess] freq 1600
8280 14:44:52.737498 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 14:44:52.737600 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 14:44:52.740558 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 14:44:52.743903 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 14:44:52.747198 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 14:44:52.750504 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 14:44:52.753907 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 14:44:52.757136 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 14:44:52.760806 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 14:44:52.764011 Pre-setting of DQS Precalculation
8290 14:44:52.767108 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 14:44:52.767194 ==
8292 14:44:52.770500 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 14:44:52.777039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 14:44:52.777139 ==
8295 14:44:52.780124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 14:44:52.786938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 14:44:52.790288 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 14:44:52.796579 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 14:44:52.804250 [CA 0] Center 40 (11~70) winsize 60
8300 14:44:52.807856 [CA 1] Center 41 (11~71) winsize 61
8301 14:44:52.811250 [CA 2] Center 37 (8~67) winsize 60
8302 14:44:52.814351 [CA 3] Center 36 (7~66) winsize 60
8303 14:44:52.817898 [CA 4] Center 37 (7~67) winsize 61
8304 14:44:52.821293 [CA 5] Center 36 (6~66) winsize 61
8305 14:44:52.821385
8306 14:44:52.824447 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 14:44:52.824582
8308 14:44:52.827975 [CATrainingPosCal] consider 1 rank data
8309 14:44:52.831156 u2DelayCellTimex100 = 290/100 ps
8310 14:44:52.834446 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8311 14:44:52.840935 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8312 14:44:52.844308 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 14:44:52.847546 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 14:44:52.851051 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8315 14:44:52.854497 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8316 14:44:52.854650
8317 14:44:52.857937 CA PerBit enable=1, Macro0, CA PI delay=36
8318 14:44:52.858026
8319 14:44:52.860827 [CBTSetCACLKResult] CA Dly = 36
8320 14:44:52.860919 CS Dly: 8 (0~39)
8321 14:44:52.867677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 14:44:52.870993 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 14:44:52.871187 ==
8324 14:44:52.873949 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 14:44:52.877487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 14:44:52.880734 ==
8327 14:44:52.884034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 14:44:52.887363 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 14:44:52.894100 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 14:44:52.897107 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 14:44:52.907511 [CA 0] Center 42 (12~72) winsize 61
8332 14:44:52.910555 [CA 1] Center 41 (11~71) winsize 61
8333 14:44:52.913881 [CA 2] Center 37 (8~67) winsize 60
8334 14:44:52.917691 [CA 3] Center 37 (8~66) winsize 59
8335 14:44:52.920440 [CA 4] Center 37 (8~67) winsize 60
8336 14:44:52.924242 [CA 5] Center 36 (7~66) winsize 60
8337 14:44:52.924365
8338 14:44:52.927334 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 14:44:52.927439
8340 14:44:52.930634 [CATrainingPosCal] consider 2 rank data
8341 14:44:52.933743 u2DelayCellTimex100 = 290/100 ps
8342 14:44:52.937679 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8343 14:44:52.943972 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8344 14:44:52.947212 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8345 14:44:52.950512 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 14:44:52.953855 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8347 14:44:52.957379 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8348 14:44:52.957473
8349 14:44:52.960489 CA PerBit enable=1, Macro0, CA PI delay=36
8350 14:44:52.960599
8351 14:44:52.964297 [CBTSetCACLKResult] CA Dly = 36
8352 14:44:52.964385 CS Dly: 9 (0~42)
8353 14:44:52.970889 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 14:44:52.974238 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 14:44:52.974331
8356 14:44:52.977564 ----->DramcWriteLeveling(PI) begin...
8357 14:44:52.977649 ==
8358 14:44:52.980761 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 14:44:52.984163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 14:44:52.984251 ==
8361 14:44:52.987364 Write leveling (Byte 0): 24 => 24
8362 14:44:52.990665 Write leveling (Byte 1): 28 => 28
8363 14:44:52.993895 DramcWriteLeveling(PI) end<-----
8364 14:44:52.993981
8365 14:44:52.994047 ==
8366 14:44:52.997616 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 14:44:53.003794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 14:44:53.003903 ==
8369 14:44:53.003972 [Gating] SW mode calibration
8370 14:44:53.013691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 14:44:53.017182 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 14:44:53.020377 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 14:44:53.027125 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 14:44:53.030468 1 4 8 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (0 0)
8375 14:44:53.033709 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 14:44:53.040260 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 14:44:53.043833 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 14:44:53.046973 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 14:44:53.053693 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 14:44:53.057017 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 14:44:53.060419 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8382 14:44:53.067105 1 5 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
8383 14:44:53.070308 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8384 14:44:53.073887 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 14:44:53.080085 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 14:44:53.083392 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 14:44:53.086720 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 14:44:53.093426 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 14:44:53.096794 1 6 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8390 14:44:53.100287 1 6 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8391 14:44:53.107083 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 14:44:53.110088 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 14:44:53.113780 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 14:44:53.120076 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 14:44:53.123549 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 14:44:53.126898 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 14:44:53.133590 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8398 14:44:53.136781 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 14:44:53.139983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8400 14:44:53.146636 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8401 14:44:53.149852 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 14:44:53.153265 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 14:44:53.159918 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 14:44:53.163212 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 14:44:53.166493 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 14:44:53.173153 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 14:44:53.176530 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 14:44:53.179979 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 14:44:53.183347 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 14:44:53.189809 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 14:44:53.192975 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 14:44:53.196629 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 14:44:53.203485 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8414 14:44:53.206548 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 14:44:53.209543 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8416 14:44:53.213357 Total UI for P1: 0, mck2ui 16
8417 14:44:53.216499 best dqsien dly found for B0: ( 1, 9, 6)
8418 14:44:53.223135 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 14:44:53.223242 Total UI for P1: 0, mck2ui 16
8420 14:44:53.229674 best dqsien dly found for B1: ( 1, 9, 10)
8421 14:44:53.232898 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8422 14:44:53.236215 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8423 14:44:53.236303
8424 14:44:53.239679 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8425 14:44:53.243099 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 14:44:53.246163 [Gating] SW calibration Done
8427 14:44:53.246251 ==
8428 14:44:53.249829 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 14:44:53.252763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 14:44:53.252849 ==
8431 14:44:53.255987 RX Vref Scan: 0
8432 14:44:53.256072
8433 14:44:53.256138 RX Vref 0 -> 0, step: 1
8434 14:44:53.259325
8435 14:44:53.259409 RX Delay 0 -> 252, step: 8
8436 14:44:53.262606 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8437 14:44:53.269251 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8438 14:44:53.272470 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8439 14:44:53.275944 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8440 14:44:53.279315 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8441 14:44:53.282997 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 14:44:53.289136 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 14:44:53.292382 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8444 14:44:53.295858 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8445 14:44:53.299551 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8446 14:44:53.302400 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 14:44:53.309179 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8448 14:44:53.312833 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8449 14:44:53.316031 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8450 14:44:53.319233 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8451 14:44:53.322951 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8452 14:44:53.323044 ==
8453 14:44:53.325869 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 14:44:53.332572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 14:44:53.332675 ==
8456 14:44:53.332744 DQS Delay:
8457 14:44:53.336087 DQS0 = 0, DQS1 = 0
8458 14:44:53.336173 DQM Delay:
8459 14:44:53.339318 DQM0 = 138, DQM1 = 130
8460 14:44:53.339404 DQ Delay:
8461 14:44:53.342720 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8462 14:44:53.345886 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8463 14:44:53.349297 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8464 14:44:53.352765 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8465 14:44:53.352856
8466 14:44:53.352924
8467 14:44:53.352985 ==
8468 14:44:53.355876 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 14:44:53.362564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 14:44:53.362661 ==
8471 14:44:53.362731
8472 14:44:53.362791
8473 14:44:53.362850 TX Vref Scan disable
8474 14:44:53.365758 == TX Byte 0 ==
8475 14:44:53.369044 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8476 14:44:53.372335 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 14:44:53.375746 == TX Byte 1 ==
8478 14:44:53.379515 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8479 14:44:53.385721 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 14:44:53.385822 ==
8481 14:44:53.389045 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 14:44:53.392258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 14:44:53.392348 ==
8484 14:44:53.404891
8485 14:44:53.408048 TX Vref early break, caculate TX vref
8486 14:44:53.411443 TX Vref=16, minBit 10, minWin=21, winSum=364
8487 14:44:53.414956 TX Vref=18, minBit 10, minWin=21, winSum=376
8488 14:44:53.418020 TX Vref=20, minBit 9, minWin=23, winSum=389
8489 14:44:53.421199 TX Vref=22, minBit 10, minWin=22, winSum=394
8490 14:44:53.424739 TX Vref=24, minBit 10, minWin=24, winSum=412
8491 14:44:53.431433 TX Vref=26, minBit 10, minWin=24, winSum=415
8492 14:44:53.434789 TX Vref=28, minBit 9, minWin=25, winSum=416
8493 14:44:53.438017 TX Vref=30, minBit 10, minWin=24, winSum=417
8494 14:44:53.441441 TX Vref=32, minBit 10, minWin=23, winSum=404
8495 14:44:53.444388 TX Vref=34, minBit 9, minWin=23, winSum=395
8496 14:44:53.451412 [TxChooseVref] Worse bit 9, Min win 25, Win sum 416, Final Vref 28
8497 14:44:53.451523
8498 14:44:53.454827 Final TX Range 0 Vref 28
8499 14:44:53.454915
8500 14:44:53.454981 ==
8501 14:44:53.458108 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 14:44:53.461211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 14:44:53.461298 ==
8504 14:44:53.461365
8505 14:44:53.461425
8506 14:44:53.464595 TX Vref Scan disable
8507 14:44:53.471400 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8508 14:44:53.471495 == TX Byte 0 ==
8509 14:44:53.474911 u2DelayCellOfst[0]=16 cells (5 PI)
8510 14:44:53.477933 u2DelayCellOfst[1]=10 cells (3 PI)
8511 14:44:53.481009 u2DelayCellOfst[2]=0 cells (0 PI)
8512 14:44:53.484441 u2DelayCellOfst[3]=6 cells (2 PI)
8513 14:44:53.487629 u2DelayCellOfst[4]=6 cells (2 PI)
8514 14:44:53.490989 u2DelayCellOfst[5]=16 cells (5 PI)
8515 14:44:53.494192 u2DelayCellOfst[6]=16 cells (5 PI)
8516 14:44:53.497684 u2DelayCellOfst[7]=6 cells (2 PI)
8517 14:44:53.500944 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8518 14:44:53.504235 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8519 14:44:53.507401 == TX Byte 1 ==
8520 14:44:53.510667 u2DelayCellOfst[8]=0 cells (0 PI)
8521 14:44:53.510760 u2DelayCellOfst[9]=3 cells (1 PI)
8522 14:44:53.514088 u2DelayCellOfst[10]=10 cells (3 PI)
8523 14:44:53.517499 u2DelayCellOfst[11]=3 cells (1 PI)
8524 14:44:53.520832 u2DelayCellOfst[12]=16 cells (5 PI)
8525 14:44:53.524212 u2DelayCellOfst[13]=20 cells (6 PI)
8526 14:44:53.527558 u2DelayCellOfst[14]=20 cells (6 PI)
8527 14:44:53.530547 u2DelayCellOfst[15]=16 cells (5 PI)
8528 14:44:53.534009 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8529 14:44:53.540852 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8530 14:44:53.540953 DramC Write-DBI on
8531 14:44:53.541023 ==
8532 14:44:53.544059 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 14:44:53.550610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 14:44:53.550708 ==
8535 14:44:53.550776
8536 14:44:53.550838
8537 14:44:53.550912 TX Vref Scan disable
8538 14:44:53.554476 == TX Byte 0 ==
8539 14:44:53.557741 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8540 14:44:53.560991 == TX Byte 1 ==
8541 14:44:53.564499 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 14:44:53.567731 DramC Write-DBI off
8543 14:44:53.567819
8544 14:44:53.567887 [DATLAT]
8545 14:44:53.567947 Freq=1600, CH1 RK0
8546 14:44:53.568007
8547 14:44:53.571177 DATLAT Default: 0xf
8548 14:44:53.571262 0, 0xFFFF, sum = 0
8549 14:44:53.574455 1, 0xFFFF, sum = 0
8550 14:44:53.577541 2, 0xFFFF, sum = 0
8551 14:44:53.577628 3, 0xFFFF, sum = 0
8552 14:44:53.580764 4, 0xFFFF, sum = 0
8553 14:44:53.580850 5, 0xFFFF, sum = 0
8554 14:44:53.584081 6, 0xFFFF, sum = 0
8555 14:44:53.584167 7, 0xFFFF, sum = 0
8556 14:44:53.587643 8, 0xFFFF, sum = 0
8557 14:44:53.587729 9, 0xFFFF, sum = 0
8558 14:44:53.590789 10, 0xFFFF, sum = 0
8559 14:44:53.590895 11, 0xFFFF, sum = 0
8560 14:44:53.594418 12, 0xFFFF, sum = 0
8561 14:44:53.594504 13, 0xFFFF, sum = 0
8562 14:44:53.597558 14, 0x0, sum = 1
8563 14:44:53.597669 15, 0x0, sum = 2
8564 14:44:53.600968 16, 0x0, sum = 3
8565 14:44:53.601057 17, 0x0, sum = 4
8566 14:44:53.604374 best_step = 15
8567 14:44:53.604483
8568 14:44:53.604618 ==
8569 14:44:53.607521 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 14:44:53.610786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 14:44:53.610871 ==
8572 14:44:53.613983 RX Vref Scan: 1
8573 14:44:53.614067
8574 14:44:53.614133 Set Vref Range= 24 -> 127
8575 14:44:53.614194
8576 14:44:53.617819 RX Vref 24 -> 127, step: 1
8577 14:44:53.617903
8578 14:44:53.620634 RX Delay 19 -> 252, step: 4
8579 14:44:53.620717
8580 14:44:53.624313 Set Vref, RX VrefLevel [Byte0]: 24
8581 14:44:53.627289 [Byte1]: 24
8582 14:44:53.627373
8583 14:44:53.630895 Set Vref, RX VrefLevel [Byte0]: 25
8584 14:44:53.634034 [Byte1]: 25
8585 14:44:53.634120
8586 14:44:53.637556 Set Vref, RX VrefLevel [Byte0]: 26
8587 14:44:53.640759 [Byte1]: 26
8588 14:44:53.645030
8589 14:44:53.645120 Set Vref, RX VrefLevel [Byte0]: 27
8590 14:44:53.647962 [Byte1]: 27
8591 14:44:53.652258
8592 14:44:53.652344 Set Vref, RX VrefLevel [Byte0]: 28
8593 14:44:53.655594 [Byte1]: 28
8594 14:44:53.659540
8595 14:44:53.659662 Set Vref, RX VrefLevel [Byte0]: 29
8596 14:44:53.663236 [Byte1]: 29
8597 14:44:53.667240
8598 14:44:53.667360 Set Vref, RX VrefLevel [Byte0]: 30
8599 14:44:53.670460 [Byte1]: 30
8600 14:44:53.675133
8601 14:44:53.675222 Set Vref, RX VrefLevel [Byte0]: 31
8602 14:44:53.678469 [Byte1]: 31
8603 14:44:53.682657
8604 14:44:53.682747 Set Vref, RX VrefLevel [Byte0]: 32
8605 14:44:53.685983 [Byte1]: 32
8606 14:44:53.690303
8607 14:44:53.690394 Set Vref, RX VrefLevel [Byte0]: 33
8608 14:44:53.693527 [Byte1]: 33
8609 14:44:53.697693
8610 14:44:53.697794 Set Vref, RX VrefLevel [Byte0]: 34
8611 14:44:53.701033 [Byte1]: 34
8612 14:44:53.705246
8613 14:44:53.705335 Set Vref, RX VrefLevel [Byte0]: 35
8614 14:44:53.708485 [Byte1]: 35
8615 14:44:53.712856
8616 14:44:53.712945 Set Vref, RX VrefLevel [Byte0]: 36
8617 14:44:53.716073 [Byte1]: 36
8618 14:44:53.720230
8619 14:44:53.720319 Set Vref, RX VrefLevel [Byte0]: 37
8620 14:44:53.724026 [Byte1]: 37
8621 14:44:53.728171
8622 14:44:53.728258 Set Vref, RX VrefLevel [Byte0]: 38
8623 14:44:53.731263 [Byte1]: 38
8624 14:44:53.735468
8625 14:44:53.735557 Set Vref, RX VrefLevel [Byte0]: 39
8626 14:44:53.738708 [Byte1]: 39
8627 14:44:53.742964
8628 14:44:53.743053 Set Vref, RX VrefLevel [Byte0]: 40
8629 14:44:53.746157 [Byte1]: 40
8630 14:44:53.750483
8631 14:44:53.750572 Set Vref, RX VrefLevel [Byte0]: 41
8632 14:44:53.753962 [Byte1]: 41
8633 14:44:53.758284
8634 14:44:53.758373 Set Vref, RX VrefLevel [Byte0]: 42
8635 14:44:53.761648 [Byte1]: 42
8636 14:44:53.766059
8637 14:44:53.766148 Set Vref, RX VrefLevel [Byte0]: 43
8638 14:44:53.772380 [Byte1]: 43
8639 14:44:53.772507
8640 14:44:53.775879 Set Vref, RX VrefLevel [Byte0]: 44
8641 14:44:53.778941 [Byte1]: 44
8642 14:44:53.779050
8643 14:44:53.782151 Set Vref, RX VrefLevel [Byte0]: 45
8644 14:44:53.785677 [Byte1]: 45
8645 14:44:53.785765
8646 14:44:53.788983 Set Vref, RX VrefLevel [Byte0]: 46
8647 14:44:53.792228 [Byte1]: 46
8648 14:44:53.796062
8649 14:44:53.796148 Set Vref, RX VrefLevel [Byte0]: 47
8650 14:44:53.799419 [Byte1]: 47
8651 14:44:53.803478
8652 14:44:53.803581 Set Vref, RX VrefLevel [Byte0]: 48
8653 14:44:53.807230 [Byte1]: 48
8654 14:44:53.811461
8655 14:44:53.811548 Set Vref, RX VrefLevel [Byte0]: 49
8656 14:44:53.814391 [Byte1]: 49
8657 14:44:53.818987
8658 14:44:53.819074 Set Vref, RX VrefLevel [Byte0]: 50
8659 14:44:53.822278 [Byte1]: 50
8660 14:44:53.826432
8661 14:44:53.826519 Set Vref, RX VrefLevel [Byte0]: 51
8662 14:44:53.829863 [Byte1]: 51
8663 14:44:53.833910
8664 14:44:53.833997 Set Vref, RX VrefLevel [Byte0]: 52
8665 14:44:53.837356 [Byte1]: 52
8666 14:44:53.841818
8667 14:44:53.841910 Set Vref, RX VrefLevel [Byte0]: 53
8668 14:44:53.844825 [Byte1]: 53
8669 14:44:53.849308
8670 14:44:53.849399 Set Vref, RX VrefLevel [Byte0]: 54
8671 14:44:53.852309 [Byte1]: 54
8672 14:44:53.856727
8673 14:44:53.856821 Set Vref, RX VrefLevel [Byte0]: 55
8674 14:44:53.860203 [Byte1]: 55
8675 14:44:53.864101
8676 14:44:53.864213 Set Vref, RX VrefLevel [Byte0]: 56
8677 14:44:53.867885 [Byte1]: 56
8678 14:44:53.871710
8679 14:44:53.871797 Set Vref, RX VrefLevel [Byte0]: 57
8680 14:44:53.875089 [Byte1]: 57
8681 14:44:53.879411
8682 14:44:53.879526 Set Vref, RX VrefLevel [Byte0]: 58
8683 14:44:53.882627 [Byte1]: 58
8684 14:44:53.887124
8685 14:44:53.887216 Set Vref, RX VrefLevel [Byte0]: 59
8686 14:44:53.890312 [Byte1]: 59
8687 14:44:53.894734
8688 14:44:53.894821 Set Vref, RX VrefLevel [Byte0]: 60
8689 14:44:53.898179 [Byte1]: 60
8690 14:44:53.902012
8691 14:44:53.902102 Set Vref, RX VrefLevel [Byte0]: 61
8692 14:44:53.905348 [Byte1]: 61
8693 14:44:53.910012
8694 14:44:53.910103 Set Vref, RX VrefLevel [Byte0]: 62
8695 14:44:53.912931 [Byte1]: 62
8696 14:44:53.917169
8697 14:44:53.917257 Set Vref, RX VrefLevel [Byte0]: 63
8698 14:44:53.920502 [Byte1]: 63
8699 14:44:53.925067
8700 14:44:53.925164 Set Vref, RX VrefLevel [Byte0]: 64
8701 14:44:53.928362 [Byte1]: 64
8702 14:44:53.932218
8703 14:44:53.932305 Set Vref, RX VrefLevel [Byte0]: 65
8704 14:44:53.935558 [Byte1]: 65
8705 14:44:53.940045
8706 14:44:53.940131 Set Vref, RX VrefLevel [Byte0]: 66
8707 14:44:53.943301 [Byte1]: 66
8708 14:44:53.947773
8709 14:44:53.947862 Set Vref, RX VrefLevel [Byte0]: 67
8710 14:44:53.950954 [Byte1]: 67
8711 14:44:53.955092
8712 14:44:53.955195 Set Vref, RX VrefLevel [Byte0]: 68
8713 14:44:53.958467 [Byte1]: 68
8714 14:44:53.962776
8715 14:44:53.962862 Set Vref, RX VrefLevel [Byte0]: 69
8716 14:44:53.966038 [Byte1]: 69
8717 14:44:53.970113
8718 14:44:53.970201 Set Vref, RX VrefLevel [Byte0]: 70
8719 14:44:53.973592 [Byte1]: 70
8720 14:44:53.978117
8721 14:44:53.978208 Set Vref, RX VrefLevel [Byte0]: 71
8722 14:44:53.981261 [Byte1]: 71
8723 14:44:53.985716
8724 14:44:53.985818 Set Vref, RX VrefLevel [Byte0]: 72
8725 14:44:53.988525 [Byte1]: 72
8726 14:44:53.993060
8727 14:44:53.993150 Set Vref, RX VrefLevel [Byte0]: 73
8728 14:44:53.996315 [Byte1]: 73
8729 14:44:54.000481
8730 14:44:54.000627 Final RX Vref Byte 0 = 59 to rank0
8731 14:44:54.003739 Final RX Vref Byte 1 = 63 to rank0
8732 14:44:54.007388 Final RX Vref Byte 0 = 59 to rank1
8733 14:44:54.010652 Final RX Vref Byte 1 = 63 to rank1==
8734 14:44:54.013906 Dram Type= 6, Freq= 0, CH_1, rank 0
8735 14:44:54.020417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 14:44:54.020520 ==
8737 14:44:54.020646 DQS Delay:
8738 14:44:54.020707 DQS0 = 0, DQS1 = 0
8739 14:44:54.023689 DQM Delay:
8740 14:44:54.023771 DQM0 = 134, DQM1 = 129
8741 14:44:54.027007 DQ Delay:
8742 14:44:54.030607 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8743 14:44:54.033919 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8744 14:44:54.037383 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8745 14:44:54.040765 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8746 14:44:54.040852
8747 14:44:54.040917
8748 14:44:54.040976
8749 14:44:54.043764 [DramC_TX_OE_Calibration] TA2
8750 14:44:54.047690 Original DQ_B0 (3 6) =30, OEN = 27
8751 14:44:54.050553 Original DQ_B1 (3 6) =30, OEN = 27
8752 14:44:54.053703 24, 0x0, End_B0=24 End_B1=24
8753 14:44:54.053794 25, 0x0, End_B0=25 End_B1=25
8754 14:44:54.057215 26, 0x0, End_B0=26 End_B1=26
8755 14:44:54.060651 27, 0x0, End_B0=27 End_B1=27
8756 14:44:54.063990 28, 0x0, End_B0=28 End_B1=28
8757 14:44:54.064077 29, 0x0, End_B0=29 End_B1=29
8758 14:44:54.067256 30, 0x0, End_B0=30 End_B1=30
8759 14:44:54.070386 31, 0x4141, End_B0=30 End_B1=30
8760 14:44:54.073926 Byte0 end_step=30 best_step=27
8761 14:44:54.077049 Byte1 end_step=30 best_step=27
8762 14:44:54.080383 Byte0 TX OE(2T, 0.5T) = (3, 3)
8763 14:44:54.080506 Byte1 TX OE(2T, 0.5T) = (3, 3)
8764 14:44:54.083911
8765 14:44:54.084021
8766 14:44:54.090349 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8767 14:44:54.093784 CH1 RK0: MR19=303, MR18=1927
8768 14:44:54.100254 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8769 14:44:54.100428
8770 14:44:54.103457 ----->DramcWriteLeveling(PI) begin...
8771 14:44:54.103572 ==
8772 14:44:54.106816 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 14:44:54.110288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 14:44:54.110374 ==
8775 14:44:54.113940 Write leveling (Byte 0): 23 => 23
8776 14:44:54.117133 Write leveling (Byte 1): 28 => 28
8777 14:44:54.120250 DramcWriteLeveling(PI) end<-----
8778 14:44:54.120334
8779 14:44:54.120399 ==
8780 14:44:54.123680 Dram Type= 6, Freq= 0, CH_1, rank 1
8781 14:44:54.126992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 14:44:54.127079 ==
8783 14:44:54.130733 [Gating] SW mode calibration
8784 14:44:54.137271 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8785 14:44:54.143510 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8786 14:44:54.147102 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 14:44:54.150439 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 14:44:54.156979 1 4 8 | B1->B0 | 3333 2322 | 0 1 | (0 0) (0 0)
8789 14:44:54.160397 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8790 14:44:54.163615 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 14:44:54.170056 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 14:44:54.173551 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 14:44:54.176999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 14:44:54.183603 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 14:44:54.186978 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 14:44:54.190371 1 5 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 0)
8797 14:44:54.197035 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 0)
8798 14:44:54.200058 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8799 14:44:54.203609 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 14:44:54.209798 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 14:44:54.213551 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 14:44:54.216904 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 14:44:54.223286 1 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8804 14:44:54.226623 1 6 8 | B1->B0 | 4444 2424 | 0 0 | (0 0) (0 0)
8805 14:44:54.229794 1 6 12 | B1->B0 | 4646 3939 | 0 1 | (0 0) (1 1)
8806 14:44:54.233398 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 14:44:54.239783 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 14:44:54.243024 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 14:44:54.246327 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 14:44:54.253208 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 14:44:54.256782 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 14:44:54.259778 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8813 14:44:54.266369 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8814 14:44:54.269745 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 14:44:54.273396 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 14:44:54.279985 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 14:44:54.282938 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 14:44:54.286390 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 14:44:54.293041 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 14:44:54.296530 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 14:44:54.299915 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 14:44:54.306540 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 14:44:54.310027 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 14:44:54.313123 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 14:44:54.319994 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 14:44:54.323267 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 14:44:54.326323 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 14:44:54.333063 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8829 14:44:54.336483 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8830 14:44:54.339675 Total UI for P1: 0, mck2ui 16
8831 14:44:54.343063 best dqsien dly found for B1: ( 1, 9, 8)
8832 14:44:54.346089 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 14:44:54.349401 Total UI for P1: 0, mck2ui 16
8834 14:44:54.352757 best dqsien dly found for B0: ( 1, 9, 10)
8835 14:44:54.356181 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8836 14:44:54.359396 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8837 14:44:54.359486
8838 14:44:54.362650 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8839 14:44:54.369147 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8840 14:44:54.369249 [Gating] SW calibration Done
8841 14:44:54.372776 ==
8842 14:44:54.372864 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 14:44:54.379414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 14:44:54.379507 ==
8845 14:44:54.379574 RX Vref Scan: 0
8846 14:44:54.379637
8847 14:44:54.382492 RX Vref 0 -> 0, step: 1
8848 14:44:54.382579
8849 14:44:54.385685 RX Delay 0 -> 252, step: 8
8850 14:44:54.389235 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8851 14:44:54.392375 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8852 14:44:54.396100 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8853 14:44:54.402370 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8854 14:44:54.406046 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8855 14:44:54.409175 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8856 14:44:54.412341 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8857 14:44:54.415657 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8858 14:44:54.422244 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8859 14:44:54.425489 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8860 14:44:54.429044 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8861 14:44:54.432347 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8862 14:44:54.435796 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8863 14:44:54.442263 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8864 14:44:54.445278 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8865 14:44:54.448811 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8866 14:44:54.448903 ==
8867 14:44:54.452036 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 14:44:54.455281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 14:44:54.458626 ==
8870 14:44:54.458713 DQS Delay:
8871 14:44:54.458781 DQS0 = 0, DQS1 = 0
8872 14:44:54.462058 DQM Delay:
8873 14:44:54.462142 DQM0 = 136, DQM1 = 132
8874 14:44:54.465153 DQ Delay:
8875 14:44:54.468789 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8876 14:44:54.471916 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8877 14:44:54.475432 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8878 14:44:54.478485 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8879 14:44:54.478585
8880 14:44:54.478650
8881 14:44:54.478711 ==
8882 14:44:54.482269 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 14:44:54.485147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 14:44:54.485232 ==
8885 14:44:54.488456
8886 14:44:54.488563
8887 14:44:54.488654 TX Vref Scan disable
8888 14:44:54.492037 == TX Byte 0 ==
8889 14:44:54.495010 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8890 14:44:54.498171 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8891 14:44:54.501382 == TX Byte 1 ==
8892 14:44:54.505028 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8893 14:44:54.508258 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8894 14:44:54.508348 ==
8895 14:44:54.511639 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 14:44:54.518069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 14:44:54.518170 ==
8898 14:44:54.529986
8899 14:44:54.533596 TX Vref early break, caculate TX vref
8900 14:44:54.536872 TX Vref=16, minBit 11, minWin=22, winSum=384
8901 14:44:54.540107 TX Vref=18, minBit 12, minWin=22, winSum=386
8902 14:44:54.543390 TX Vref=20, minBit 11, minWin=23, winSum=394
8903 14:44:54.546663 TX Vref=22, minBit 9, minWin=24, winSum=406
8904 14:44:54.550486 TX Vref=24, minBit 12, minWin=24, winSum=416
8905 14:44:54.557003 TX Vref=26, minBit 11, minWin=25, winSum=422
8906 14:44:54.560255 TX Vref=28, minBit 9, minWin=25, winSum=418
8907 14:44:54.563407 TX Vref=30, minBit 10, minWin=25, winSum=418
8908 14:44:54.566487 TX Vref=32, minBit 9, minWin=24, winSum=408
8909 14:44:54.570123 TX Vref=34, minBit 15, minWin=23, winSum=397
8910 14:44:54.576755 [TxChooseVref] Worse bit 11, Min win 25, Win sum 422, Final Vref 26
8911 14:44:54.576861
8912 14:44:54.579918 Final TX Range 0 Vref 26
8913 14:44:54.580005
8914 14:44:54.580072 ==
8915 14:44:54.583386 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 14:44:54.586709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 14:44:54.586833 ==
8918 14:44:54.586929
8919 14:44:54.590074
8920 14:44:54.590159 TX Vref Scan disable
8921 14:44:54.596347 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8922 14:44:54.596441 == TX Byte 0 ==
8923 14:44:54.599749 u2DelayCellOfst[0]=13 cells (4 PI)
8924 14:44:54.602920 u2DelayCellOfst[1]=10 cells (3 PI)
8925 14:44:54.606275 u2DelayCellOfst[2]=0 cells (0 PI)
8926 14:44:54.609786 u2DelayCellOfst[3]=3 cells (1 PI)
8927 14:44:54.613198 u2DelayCellOfst[4]=6 cells (2 PI)
8928 14:44:54.616238 u2DelayCellOfst[5]=16 cells (5 PI)
8929 14:44:54.619811 u2DelayCellOfst[6]=16 cells (5 PI)
8930 14:44:54.623104 u2DelayCellOfst[7]=3 cells (1 PI)
8931 14:44:54.626491 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8932 14:44:54.629956 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8933 14:44:54.633190 == TX Byte 1 ==
8934 14:44:54.636363 u2DelayCellOfst[8]=0 cells (0 PI)
8935 14:44:54.636449 u2DelayCellOfst[9]=6 cells (2 PI)
8936 14:44:54.639713 u2DelayCellOfst[10]=10 cells (3 PI)
8937 14:44:54.643065 u2DelayCellOfst[11]=6 cells (2 PI)
8938 14:44:54.646398 u2DelayCellOfst[12]=13 cells (4 PI)
8939 14:44:54.649768 u2DelayCellOfst[13]=16 cells (5 PI)
8940 14:44:54.653035 u2DelayCellOfst[14]=20 cells (6 PI)
8941 14:44:54.656340 u2DelayCellOfst[15]=20 cells (6 PI)
8942 14:44:54.660034 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8943 14:44:54.666554 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8944 14:44:54.666656 DramC Write-DBI on
8945 14:44:54.666727 ==
8946 14:44:54.670138 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 14:44:54.673363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 14:44:54.676527 ==
8949 14:44:54.676637
8950 14:44:54.676703
8951 14:44:54.676764 TX Vref Scan disable
8952 14:44:54.680127 == TX Byte 0 ==
8953 14:44:54.683544 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8954 14:44:54.686943 == TX Byte 1 ==
8955 14:44:54.690254 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8956 14:44:54.693563 DramC Write-DBI off
8957 14:44:54.693651
8958 14:44:54.693717 [DATLAT]
8959 14:44:54.693778 Freq=1600, CH1 RK1
8960 14:44:54.693838
8961 14:44:54.696913 DATLAT Default: 0xf
8962 14:44:54.696996 0, 0xFFFF, sum = 0
8963 14:44:54.700039 1, 0xFFFF, sum = 0
8964 14:44:54.700126 2, 0xFFFF, sum = 0
8965 14:44:54.703233 3, 0xFFFF, sum = 0
8966 14:44:54.706667 4, 0xFFFF, sum = 0
8967 14:44:54.706756 5, 0xFFFF, sum = 0
8968 14:44:54.709972 6, 0xFFFF, sum = 0
8969 14:44:54.710059 7, 0xFFFF, sum = 0
8970 14:44:54.713347 8, 0xFFFF, sum = 0
8971 14:44:54.713434 9, 0xFFFF, sum = 0
8972 14:44:54.716899 10, 0xFFFF, sum = 0
8973 14:44:54.716987 11, 0xFFFF, sum = 0
8974 14:44:54.720206 12, 0xFFFF, sum = 0
8975 14:44:54.720292 13, 0xFFFF, sum = 0
8976 14:44:54.723181 14, 0x0, sum = 1
8977 14:44:54.723267 15, 0x0, sum = 2
8978 14:44:54.726891 16, 0x0, sum = 3
8979 14:44:54.726977 17, 0x0, sum = 4
8980 14:44:54.730062 best_step = 15
8981 14:44:54.730148
8982 14:44:54.730215 ==
8983 14:44:54.733506 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 14:44:54.736829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 14:44:54.736917 ==
8986 14:44:54.736986 RX Vref Scan: 0
8987 14:44:54.739936
8988 14:44:54.740021 RX Vref 0 -> 0, step: 1
8989 14:44:54.740088
8990 14:44:54.743116 RX Delay 19 -> 252, step: 4
8991 14:44:54.746383 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8992 14:44:54.753179 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8993 14:44:54.756818 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8994 14:44:54.760133 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8995 14:44:54.763515 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8996 14:44:54.766592 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8997 14:44:54.770197 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8998 14:44:54.776511 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8999 14:44:54.780251 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9000 14:44:54.783332 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9001 14:44:54.786533 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9002 14:44:54.790062 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9003 14:44:54.796884 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9004 14:44:54.799912 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9005 14:44:54.802992 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9006 14:44:54.806455 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9007 14:44:54.806547 ==
9008 14:44:54.809802 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 14:44:54.816531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 14:44:54.816646 ==
9011 14:44:54.816720 DQS Delay:
9012 14:44:54.816783 DQS0 = 0, DQS1 = 0
9013 14:44:54.819947 DQM Delay:
9014 14:44:54.820048 DQM0 = 133, DQM1 = 130
9015 14:44:54.823053 DQ Delay:
9016 14:44:54.826485 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9017 14:44:54.829669 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9018 14:44:54.833109 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9019 14:44:54.836366 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =142
9020 14:44:54.836457
9021 14:44:54.836523
9022 14:44:54.836624
9023 14:44:54.839763 [DramC_TX_OE_Calibration] TA2
9024 14:44:54.842948 Original DQ_B0 (3 6) =30, OEN = 27
9025 14:44:54.846576 Original DQ_B1 (3 6) =30, OEN = 27
9026 14:44:54.849763 24, 0x0, End_B0=24 End_B1=24
9027 14:44:54.849852 25, 0x0, End_B0=25 End_B1=25
9028 14:44:54.853037 26, 0x0, End_B0=26 End_B1=26
9029 14:44:54.856446 27, 0x0, End_B0=27 End_B1=27
9030 14:44:54.859551 28, 0x0, End_B0=28 End_B1=28
9031 14:44:54.859646 29, 0x0, End_B0=29 End_B1=29
9032 14:44:54.862899 30, 0x0, End_B0=30 End_B1=30
9033 14:44:54.866239 31, 0x4545, End_B0=30 End_B1=30
9034 14:44:54.869530 Byte0 end_step=30 best_step=27
9035 14:44:54.872916 Byte1 end_step=30 best_step=27
9036 14:44:54.876254 Byte0 TX OE(2T, 0.5T) = (3, 3)
9037 14:44:54.879479 Byte1 TX OE(2T, 0.5T) = (3, 3)
9038 14:44:54.879569
9039 14:44:54.879636
9040 14:44:54.886195 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9041 14:44:54.889555 CH1 RK1: MR19=303, MR18=1D08
9042 14:44:54.896440 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9043 14:44:54.899307 [RxdqsGatingPostProcess] freq 1600
9044 14:44:54.902594 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9045 14:44:54.905910 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 14:44:54.909387 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 14:44:54.912504 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 14:44:54.916104 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 14:44:54.919220 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 14:44:54.922954 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 14:44:54.926031 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 14:44:54.929437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 14:44:54.932528 Pre-setting of DQS Precalculation
9054 14:44:54.935894 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9055 14:44:54.942535 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9056 14:44:54.949392 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9057 14:44:54.952528
9058 14:44:54.952645
9059 14:44:54.952712 [Calibration Summary] 3200 Mbps
9060 14:44:54.955771 CH 0, Rank 0
9061 14:44:54.955855 SW Impedance : PASS
9062 14:44:54.959006 DUTY Scan : NO K
9063 14:44:54.962370 ZQ Calibration : PASS
9064 14:44:54.962458 Jitter Meter : NO K
9065 14:44:54.965911 CBT Training : PASS
9066 14:44:54.969244 Write leveling : PASS
9067 14:44:54.969333 RX DQS gating : PASS
9068 14:44:54.972576 RX DQ/DQS(RDDQC) : PASS
9069 14:44:54.975811 TX DQ/DQS : PASS
9070 14:44:54.975897 RX DATLAT : PASS
9071 14:44:54.979110 RX DQ/DQS(Engine): PASS
9072 14:44:54.982513 TX OE : PASS
9073 14:44:54.982603 All Pass.
9074 14:44:54.982669
9075 14:44:54.982729 CH 0, Rank 1
9076 14:44:54.985885 SW Impedance : PASS
9077 14:44:54.989068 DUTY Scan : NO K
9078 14:44:54.989199 ZQ Calibration : PASS
9079 14:44:54.992558 Jitter Meter : NO K
9080 14:44:54.992657 CBT Training : PASS
9081 14:44:54.995778 Write leveling : PASS
9082 14:44:54.999486 RX DQS gating : PASS
9083 14:44:54.999574 RX DQ/DQS(RDDQC) : PASS
9084 14:44:55.002270 TX DQ/DQS : PASS
9085 14:44:55.005599 RX DATLAT : PASS
9086 14:44:55.005688 RX DQ/DQS(Engine): PASS
9087 14:44:55.009361 TX OE : PASS
9088 14:44:55.009448 All Pass.
9089 14:44:55.009514
9090 14:44:55.012414 CH 1, Rank 0
9091 14:44:55.012512 SW Impedance : PASS
9092 14:44:55.015589 DUTY Scan : NO K
9093 14:44:55.019031 ZQ Calibration : PASS
9094 14:44:55.019118 Jitter Meter : NO K
9095 14:44:55.022254 CBT Training : PASS
9096 14:44:55.025800 Write leveling : PASS
9097 14:44:55.025889 RX DQS gating : PASS
9098 14:44:55.029069 RX DQ/DQS(RDDQC) : PASS
9099 14:44:55.032246 TX DQ/DQS : PASS
9100 14:44:55.032337 RX DATLAT : PASS
9101 14:44:55.035684 RX DQ/DQS(Engine): PASS
9102 14:44:55.038956 TX OE : PASS
9103 14:44:55.039045 All Pass.
9104 14:44:55.039113
9105 14:44:55.039174 CH 1, Rank 1
9106 14:44:55.042329 SW Impedance : PASS
9107 14:44:55.045726 DUTY Scan : NO K
9108 14:44:55.045813 ZQ Calibration : PASS
9109 14:44:55.048964 Jitter Meter : NO K
9110 14:44:55.049050 CBT Training : PASS
9111 14:44:55.052249 Write leveling : PASS
9112 14:44:55.055742 RX DQS gating : PASS
9113 14:44:55.055833 RX DQ/DQS(RDDQC) : PASS
9114 14:44:55.058908 TX DQ/DQS : PASS
9115 14:44:55.062572 RX DATLAT : PASS
9116 14:44:55.062661 RX DQ/DQS(Engine): PASS
9117 14:44:55.065467 TX OE : PASS
9118 14:44:55.065553 All Pass.
9119 14:44:55.065621
9120 14:44:55.069106 DramC Write-DBI on
9121 14:44:55.072348 PER_BANK_REFRESH: Hybrid Mode
9122 14:44:55.072437 TX_TRACKING: ON
9123 14:44:55.082309 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9124 14:44:55.088756 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9125 14:44:55.095651 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9126 14:44:55.098864 [FAST_K] Save calibration result to emmc
9127 14:44:55.102080 sync common calibartion params.
9128 14:44:55.105481 sync cbt_mode0:1, 1:1
9129 14:44:55.108671 dram_init: ddr_geometry: 2
9130 14:44:55.108784 dram_init: ddr_geometry: 2
9131 14:44:55.111987 dram_init: ddr_geometry: 2
9132 14:44:55.115515 0:dram_rank_size:100000000
9133 14:44:55.118638 1:dram_rank_size:100000000
9134 14:44:55.121896 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9135 14:44:55.125107 DFS_SHUFFLE_HW_MODE: ON
9136 14:44:55.128586 dramc_set_vcore_voltage set vcore to 725000
9137 14:44:55.131623 Read voltage for 1600, 0
9138 14:44:55.131715 Vio18 = 0
9139 14:44:55.131783 Vcore = 725000
9140 14:44:55.135127 Vdram = 0
9141 14:44:55.135218 Vddq = 0
9142 14:44:55.135287 Vmddr = 0
9143 14:44:55.138574 switch to 3200 Mbps bootup
9144 14:44:55.141865 [DramcRunTimeConfig]
9145 14:44:55.141957 PHYPLL
9146 14:44:55.142025 DPM_CONTROL_AFTERK: ON
9147 14:44:55.145303 PER_BANK_REFRESH: ON
9148 14:44:55.148537 REFRESH_OVERHEAD_REDUCTION: ON
9149 14:44:55.148663 CMD_PICG_NEW_MODE: OFF
9150 14:44:55.151862 XRTWTW_NEW_MODE: ON
9151 14:44:55.154915 XRTRTR_NEW_MODE: ON
9152 14:44:55.155003 TX_TRACKING: ON
9153 14:44:55.158557 RDSEL_TRACKING: OFF
9154 14:44:55.158646 DQS Precalculation for DVFS: ON
9155 14:44:55.161695 RX_TRACKING: OFF
9156 14:44:55.161782 HW_GATING DBG: ON
9157 14:44:55.164996 ZQCS_ENABLE_LP4: ON
9158 14:44:55.165083 RX_PICG_NEW_MODE: ON
9159 14:44:55.168350 TX_PICG_NEW_MODE: ON
9160 14:44:55.171655 ENABLE_RX_DCM_DPHY: ON
9161 14:44:55.174853 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9162 14:44:55.174948 DUMMY_READ_FOR_TRACKING: OFF
9163 14:44:55.178583 !!! SPM_CONTROL_AFTERK: OFF
9164 14:44:55.181987 !!! SPM could not control APHY
9165 14:44:55.184859 IMPEDANCE_TRACKING: ON
9166 14:44:55.184948 TEMP_SENSOR: ON
9167 14:44:55.188179 HW_SAVE_FOR_SR: OFF
9168 14:44:55.188265 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9169 14:44:55.195138 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9170 14:44:55.195238 Read ODT Tracking: ON
9171 14:44:55.198260 Refresh Rate DeBounce: ON
9172 14:44:55.198349 DFS_NO_QUEUE_FLUSH: ON
9173 14:44:55.201808 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9174 14:44:55.204894 ENABLE_DFS_RUNTIME_MRW: OFF
9175 14:44:55.208111 DDR_RESERVE_NEW_MODE: ON
9176 14:44:55.208205 MR_CBT_SWITCH_FREQ: ON
9177 14:44:55.211293 =========================
9178 14:44:55.230782 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9179 14:44:55.234318 dram_init: ddr_geometry: 2
9180 14:44:55.252451 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9181 14:44:55.255933 dram_init: dram init end (result: 0)
9182 14:44:55.262630 DRAM-K: Full calibration passed in 24488 msecs
9183 14:44:55.265731 MRC: failed to locate region type 0.
9184 14:44:55.265825 DRAM rank0 size:0x100000000,
9185 14:44:55.269072 DRAM rank1 size=0x100000000
9186 14:44:55.278868 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9187 14:44:55.285606 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9188 14:44:55.292348 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9189 14:44:55.298991 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9190 14:44:55.302034 DRAM rank0 size:0x100000000,
9191 14:44:55.305586 DRAM rank1 size=0x100000000
9192 14:44:55.305686 CBMEM:
9193 14:44:55.308850 IMD: root @ 0xfffff000 254 entries.
9194 14:44:55.312025 IMD: root @ 0xffffec00 62 entries.
9195 14:44:55.315413 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9196 14:44:55.318731 WARNING: RO_VPD is uninitialized or empty.
9197 14:44:55.325325 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9198 14:44:55.332512 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9199 14:44:55.345536 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9200 14:44:55.356851 BS: romstage times (exec / console): total (unknown) / 23987 ms
9201 14:44:55.356991
9202 14:44:55.357065
9203 14:44:55.366746 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9204 14:44:55.369847 ARM64: Exception handlers installed.
9205 14:44:55.373291 ARM64: Testing exception
9206 14:44:55.376953 ARM64: Done test exception
9207 14:44:55.377044 Enumerating buses...
9208 14:44:55.380193 Show all devs... Before device enumeration.
9209 14:44:55.383399 Root Device: enabled 1
9210 14:44:55.386807 CPU_CLUSTER: 0: enabled 1
9211 14:44:55.386899 CPU: 00: enabled 1
9212 14:44:55.389740 Compare with tree...
9213 14:44:55.389826 Root Device: enabled 1
9214 14:44:55.393707 CPU_CLUSTER: 0: enabled 1
9215 14:44:55.396619 CPU: 00: enabled 1
9216 14:44:55.396707 Root Device scanning...
9217 14:44:55.400066 scan_static_bus for Root Device
9218 14:44:55.403091 CPU_CLUSTER: 0 enabled
9219 14:44:55.406601 scan_static_bus for Root Device done
9220 14:44:55.409858 scan_bus: bus Root Device finished in 8 msecs
9221 14:44:55.409997 done
9222 14:44:55.416705 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9223 14:44:55.419745 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9224 14:44:55.426405 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9225 14:44:55.430252 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9226 14:44:55.433072 Allocating resources...
9227 14:44:55.436319 Reading resources...
9228 14:44:55.439866 Root Device read_resources bus 0 link: 0
9229 14:44:55.439958 DRAM rank0 size:0x100000000,
9230 14:44:55.442835 DRAM rank1 size=0x100000000
9231 14:44:55.446170 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9232 14:44:55.449657 CPU: 00 missing read_resources
9233 14:44:55.453236 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9234 14:44:55.459444 Root Device read_resources bus 0 link: 0 done
9235 14:44:55.459527 Done reading resources.
9236 14:44:55.466296 Show resources in subtree (Root Device)...After reading.
9237 14:44:55.469443 Root Device child on link 0 CPU_CLUSTER: 0
9238 14:44:55.473189 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 14:44:55.482882 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 14:44:55.482971 CPU: 00
9241 14:44:55.486125 Root Device assign_resources, bus 0 link: 0
9242 14:44:55.489872 CPU_CLUSTER: 0 missing set_resources
9243 14:44:55.493401 Root Device assign_resources, bus 0 link: 0 done
9244 14:44:55.496399 Done setting resources.
9245 14:44:55.503230 Show resources in subtree (Root Device)...After assigning values.
9246 14:44:55.506259 Root Device child on link 0 CPU_CLUSTER: 0
9247 14:44:55.509511 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 14:44:55.519623 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 14:44:55.519718 CPU: 00
9250 14:44:55.522987 Done allocating resources.
9251 14:44:55.526413 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9252 14:44:55.529844 Enabling resources...
9253 14:44:55.529928 done.
9254 14:44:55.536170 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9255 14:44:55.536312 Initializing devices...
9256 14:44:55.539395 Root Device init
9257 14:44:55.539478 init hardware done!
9258 14:44:55.542743 0x00000018: ctrlr->caps
9259 14:44:55.545859 52.000 MHz: ctrlr->f_max
9260 14:44:55.545944 0.400 MHz: ctrlr->f_min
9261 14:44:55.549823 0x40ff8080: ctrlr->voltages
9262 14:44:55.549908 sclk: 390625
9263 14:44:55.552617 Bus Width = 1
9264 14:44:55.552700 sclk: 390625
9265 14:44:55.555813 Bus Width = 1
9266 14:44:55.555901 Early init status = 3
9267 14:44:55.562446 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9268 14:44:55.565700 in-header: 03 fc 00 00 01 00 00 00
9269 14:44:55.569251 in-data: 00
9270 14:44:55.572390 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9271 14:44:55.577544 in-header: 03 fd 00 00 00 00 00 00
9272 14:44:55.580948 in-data:
9273 14:44:55.584273 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9274 14:44:55.588935 in-header: 03 fc 00 00 01 00 00 00
9275 14:44:55.592146 in-data: 00
9276 14:44:55.595463 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9277 14:44:55.601269 in-header: 03 fd 00 00 00 00 00 00
9278 14:44:55.604483 in-data:
9279 14:44:55.607957 [SSUSB] Setting up USB HOST controller...
9280 14:44:55.611154 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9281 14:44:55.614267 [SSUSB] phy power-on done.
9282 14:44:55.617457 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9283 14:44:55.624335 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9284 14:44:55.627865 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9285 14:44:55.634333 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9286 14:44:55.641081 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9287 14:44:55.647576 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9288 14:44:55.654357 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9289 14:44:55.660986 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9290 14:44:55.664368 SPM: binary array size = 0x9dc
9291 14:44:55.667499 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9292 14:44:55.674190 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9293 14:44:55.680423 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9294 14:44:55.687063 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9295 14:44:55.690255 configure_display: Starting display init
9296 14:44:55.724848 anx7625_power_on_init: Init interface.
9297 14:44:55.727744 anx7625_disable_pd_protocol: Disabled PD feature.
9298 14:44:55.731074 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9299 14:44:55.758830 anx7625_start_dp_work: Secure OCM version=00
9300 14:44:55.762092 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9301 14:44:55.777106 sp_tx_get_edid_block: EDID Block = 1
9302 14:44:55.879655 Extracted contents:
9303 14:44:55.882932 header: 00 ff ff ff ff ff ff 00
9304 14:44:55.886026 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9305 14:44:55.889363 version: 01 04
9306 14:44:55.892602 basic params: 95 1f 11 78 0a
9307 14:44:55.895936 chroma info: 76 90 94 55 54 90 27 21 50 54
9308 14:44:55.899119 established: 00 00 00
9309 14:44:55.906031 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9310 14:44:55.909349 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9311 14:44:55.915979 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9312 14:44:55.922544 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9313 14:44:55.929226 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9314 14:44:55.932464 extensions: 00
9315 14:44:55.932601 checksum: fb
9316 14:44:55.932699
9317 14:44:55.935491 Manufacturer: IVO Model 57d Serial Number 0
9318 14:44:55.939070 Made week 0 of 2020
9319 14:44:55.939163 EDID version: 1.4
9320 14:44:55.942200 Digital display
9321 14:44:55.945505 6 bits per primary color channel
9322 14:44:55.945598 DisplayPort interface
9323 14:44:55.948905 Maximum image size: 31 cm x 17 cm
9324 14:44:55.952127 Gamma: 220%
9325 14:44:55.952221 Check DPMS levels
9326 14:44:55.955682 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9327 14:44:55.962789 First detailed timing is preferred timing
9328 14:44:55.962911 Established timings supported:
9329 14:44:55.965726 Standard timings supported:
9330 14:44:55.968683 Detailed timings
9331 14:44:55.972154 Hex of detail: 383680a07038204018303c0035ae10000019
9332 14:44:55.975470 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9333 14:44:55.982179 0780 0798 07c8 0820 hborder 0
9334 14:44:55.985554 0438 043b 0447 0458 vborder 0
9335 14:44:55.988655 -hsync -vsync
9336 14:44:55.988737 Did detailed timing
9337 14:44:55.995297 Hex of detail: 000000000000000000000000000000000000
9338 14:44:55.995381 Manufacturer-specified data, tag 0
9339 14:44:56.001895 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9340 14:44:56.005585 ASCII string: InfoVision
9341 14:44:56.008759 Hex of detail: 000000fe00523134304e574635205248200a
9342 14:44:56.012106 ASCII string: R140NWF5 RH
9343 14:44:56.012213 Checksum
9344 14:44:56.015328 Checksum: 0xfb (valid)
9345 14:44:56.018666 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9346 14:44:56.021918 DSI data_rate: 832800000 bps
9347 14:44:56.028885 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9348 14:44:56.031934 anx7625_parse_edid: pixelclock(138800).
9349 14:44:56.035327 hactive(1920), hsync(48), hfp(24), hbp(88)
9350 14:44:56.038610 vactive(1080), vsync(12), vfp(3), vbp(17)
9351 14:44:56.041830 anx7625_dsi_config: config dsi.
9352 14:44:56.048560 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9353 14:44:56.061180 anx7625_dsi_config: success to config DSI
9354 14:44:56.064682 anx7625_dp_start: MIPI phy setup OK.
9355 14:44:56.067887 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9356 14:44:56.071252 mtk_ddp_mode_set invalid vrefresh 60
9357 14:44:56.074547 main_disp_path_setup
9358 14:44:56.074632 ovl_layer_smi_id_en
9359 14:44:56.078137 ovl_layer_smi_id_en
9360 14:44:56.078220 ccorr_config
9361 14:44:56.078286 aal_config
9362 14:44:56.081597 gamma_config
9363 14:44:56.081680 postmask_config
9364 14:44:56.084748 dither_config
9365 14:44:56.088138 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9366 14:44:56.094933 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9367 14:44:56.098099 Root Device init finished in 555 msecs
9368 14:44:56.101426 CPU_CLUSTER: 0 init
9369 14:44:56.107973 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9370 14:44:56.111181 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9371 14:44:56.114811 APU_MBOX 0x190000b0 = 0x10001
9372 14:44:56.118054 APU_MBOX 0x190001b0 = 0x10001
9373 14:44:56.121429 APU_MBOX 0x190005b0 = 0x10001
9374 14:44:56.124936 APU_MBOX 0x190006b0 = 0x10001
9375 14:44:56.128519 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9376 14:44:56.140444 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9377 14:44:56.153173 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9378 14:44:56.159367 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9379 14:44:56.170975 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9380 14:44:56.180205 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9381 14:44:56.183655 CPU_CLUSTER: 0 init finished in 81 msecs
9382 14:44:56.186996 Devices initialized
9383 14:44:56.190391 Show all devs... After init.
9384 14:44:56.190475 Root Device: enabled 1
9385 14:44:56.193726 CPU_CLUSTER: 0: enabled 1
9386 14:44:56.196980 CPU: 00: enabled 1
9387 14:44:56.200145 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9388 14:44:56.203377 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9389 14:44:56.206788 ELOG: NV offset 0x57f000 size 0x1000
9390 14:44:56.213364 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9391 14:44:56.219860 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9392 14:44:56.223492 ELOG: Event(17) added with size 13 at 2024-06-04 14:43:29 UTC
9393 14:44:56.226746 out: cmd=0x121: 03 db 21 01 00 00 00 00
9394 14:44:56.230567 in-header: 03 59 00 00 2c 00 00 00
9395 14:44:56.243668 in-data: e6 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9396 14:44:56.250472 ELOG: Event(A1) added with size 10 at 2024-06-04 14:43:29 UTC
9397 14:44:56.257222 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9398 14:44:56.263575 ELOG: Event(A0) added with size 9 at 2024-06-04 14:43:29 UTC
9399 14:44:56.267244 elog_add_boot_reason: Logged dev mode boot
9400 14:44:56.270510 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9401 14:44:56.273838 Finalize devices...
9402 14:44:56.273924 Devices finalized
9403 14:44:56.280496 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9404 14:44:56.283490 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9405 14:44:56.286849 in-header: 03 07 00 00 08 00 00 00
9406 14:44:56.290135 in-data: aa e4 47 04 13 02 00 00
9407 14:44:56.293501 Chrome EC: UHEPI supported
9408 14:44:56.300113 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9409 14:44:56.303575 in-header: 03 a9 00 00 08 00 00 00
9410 14:44:56.306698 in-data: 84 60 60 08 00 00 00 00
9411 14:44:56.309997 ELOG: Event(91) added with size 10 at 2024-06-04 14:43:30 UTC
9412 14:44:56.316806 Chrome EC: clear events_b mask to 0x0000000020004000
9413 14:44:56.323503 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9414 14:44:56.327203 in-header: 03 fd 00 00 00 00 00 00
9415 14:44:56.327291 in-data:
9416 14:44:56.333917 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9417 14:44:56.337062 Writing coreboot table at 0xffe64000
9418 14:44:56.340211 0. 000000000010a000-0000000000113fff: RAMSTAGE
9419 14:44:56.344038 1. 0000000040000000-00000000400fffff: RAM
9420 14:44:56.346940 2. 0000000040100000-000000004032afff: RAMSTAGE
9421 14:44:56.353826 3. 000000004032b000-00000000545fffff: RAM
9422 14:44:56.357076 4. 0000000054600000-000000005465ffff: BL31
9423 14:44:56.360403 5. 0000000054660000-00000000ffe63fff: RAM
9424 14:44:56.363543 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9425 14:44:56.370306 7. 0000000100000000-000000023fffffff: RAM
9426 14:44:56.370394 Passing 5 GPIOs to payload:
9427 14:44:56.377151 NAME | PORT | POLARITY | VALUE
9428 14:44:56.380479 EC in RW | 0x000000aa | low | undefined
9429 14:44:56.383654 EC interrupt | 0x00000005 | low | undefined
9430 14:44:56.390540 TPM interrupt | 0x000000ab | high | undefined
9431 14:44:56.393868 SD card detect | 0x00000011 | high | undefined
9432 14:44:56.400359 speaker enable | 0x00000093 | high | undefined
9433 14:44:56.403584 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9434 14:44:56.407180 in-header: 03 f9 00 00 02 00 00 00
9435 14:44:56.407269 in-data: 02 00
9436 14:44:56.409939 ADC[4]: Raw value=901401 ID=7
9437 14:44:56.413612 ADC[3]: Raw value=213179 ID=1
9438 14:44:56.413698 RAM Code: 0x71
9439 14:44:56.417011 ADC[6]: Raw value=74502 ID=0
9440 14:44:56.419892 ADC[5]: Raw value=212072 ID=1
9441 14:44:56.419976 SKU Code: 0x1
9442 14:44:56.426950 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bb90
9443 14:44:56.429952 coreboot table: 964 bytes.
9444 14:44:56.433258 IMD ROOT 0. 0xfffff000 0x00001000
9445 14:44:56.436672 IMD SMALL 1. 0xffffe000 0x00001000
9446 14:44:56.439935 RO MCACHE 2. 0xffffc000 0x00001104
9447 14:44:56.443021 CONSOLE 3. 0xfff7c000 0x00080000
9448 14:44:56.446386 FMAP 4. 0xfff7b000 0x00000452
9449 14:44:56.449661 TIME STAMP 5. 0xfff7a000 0x00000910
9450 14:44:56.453330 VBOOT WORK 6. 0xfff66000 0x00014000
9451 14:44:56.456446 RAMOOPS 7. 0xffe66000 0x00100000
9452 14:44:56.459898 COREBOOT 8. 0xffe64000 0x00002000
9453 14:44:56.459984 IMD small region:
9454 14:44:56.463205 IMD ROOT 0. 0xffffec00 0x00000400
9455 14:44:56.466406 VPD 1. 0xffffeb80 0x0000006c
9456 14:44:56.470166 MMC STATUS 2. 0xffffeb60 0x00000004
9457 14:44:56.476328 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9458 14:44:56.483150 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9459 14:44:56.522088 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9460 14:44:56.525324 Checking segment from ROM address 0x40100000
9461 14:44:56.529025 Checking segment from ROM address 0x4010001c
9462 14:44:56.535436 Loading segment from ROM address 0x40100000
9463 14:44:56.535530 code (compression=0)
9464 14:44:56.545409 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9465 14:44:56.552198 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9466 14:44:56.552352 it's not compressed!
9467 14:44:56.558738 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9468 14:44:56.564955 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9469 14:44:56.582835 Loading segment from ROM address 0x4010001c
9470 14:44:56.582965 Entry Point 0x80000000
9471 14:44:56.585915 Loaded segments
9472 14:44:56.589307 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9473 14:44:56.596076 Jumping to boot code at 0x80000000(0xffe64000)
9474 14:44:56.602687 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9475 14:44:56.608867 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9476 14:44:56.617109 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9477 14:44:56.620223 Checking segment from ROM address 0x40100000
9478 14:44:56.623510 Checking segment from ROM address 0x4010001c
9479 14:44:56.630143 Loading segment from ROM address 0x40100000
9480 14:44:56.630236 code (compression=1)
9481 14:44:56.637204 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9482 14:44:56.646787 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9483 14:44:56.646891 using LZMA
9484 14:44:56.655445 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9485 14:44:56.662135 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9486 14:44:56.665384 Loading segment from ROM address 0x4010001c
9487 14:44:56.665474 Entry Point 0x54601000
9488 14:44:56.668746 Loaded segments
9489 14:44:56.671973 NOTICE: MT8192 bl31_setup
9490 14:44:56.678838 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9491 14:44:56.682281 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9492 14:44:56.685626 WARNING: region 0:
9493 14:44:56.689490 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 14:44:56.689577 WARNING: region 1:
9495 14:44:56.696082 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9496 14:44:56.698970 WARNING: region 2:
9497 14:44:56.702515 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9498 14:44:56.705476 WARNING: region 3:
9499 14:44:56.708767 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 14:44:56.712492 WARNING: region 4:
9501 14:44:56.718970 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 14:44:56.719058 WARNING: region 5:
9503 14:44:56.722276 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 14:44:56.725626 WARNING: region 6:
9505 14:44:56.728921 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 14:44:56.732252 WARNING: region 7:
9507 14:44:56.735413 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 14:44:56.742170 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9509 14:44:56.745599 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9510 14:44:56.748901 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9511 14:44:56.755392 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9512 14:44:56.758921 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9513 14:44:56.762083 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9514 14:44:56.768709 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9515 14:44:56.771997 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9516 14:44:56.778957 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9517 14:44:56.782316 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9518 14:44:56.785433 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9519 14:44:56.792067 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9520 14:44:56.795292 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9521 14:44:56.798914 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9522 14:44:56.805344 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9523 14:44:56.808550 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9524 14:44:56.815179 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9525 14:44:56.818519 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9526 14:44:56.822260 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9527 14:44:56.828726 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9528 14:44:56.832139 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9529 14:44:56.835265 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9530 14:44:56.841928 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9531 14:44:56.845273 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9532 14:44:56.851784 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9533 14:44:56.855134 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9534 14:44:56.861634 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9535 14:44:56.865325 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9536 14:44:56.868450 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9537 14:44:56.875189 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9538 14:44:56.878645 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9539 14:44:56.881899 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9540 14:44:56.888222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9541 14:44:56.891782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9542 14:44:56.894845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9543 14:44:56.898222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9544 14:44:56.905053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9545 14:44:56.908273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9546 14:44:56.911746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9547 14:44:56.915293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9548 14:44:56.921848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9549 14:44:56.925210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9550 14:44:56.928337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9551 14:44:56.931618 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9552 14:44:56.938385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9553 14:44:56.941458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9554 14:44:56.944970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9555 14:44:56.951704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9556 14:44:56.954923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9557 14:44:56.958274 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9558 14:44:56.965051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9559 14:44:56.968283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9560 14:44:56.974621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9561 14:44:56.978238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9562 14:44:56.984921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9563 14:44:56.988142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9564 14:44:56.991310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9565 14:44:56.997877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9566 14:44:57.001250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9567 14:44:57.008014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9568 14:44:57.011444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9569 14:44:57.018092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9570 14:44:57.021419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9571 14:44:57.028076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9572 14:44:57.031352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9573 14:44:57.034620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9574 14:44:57.041350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9575 14:44:57.044511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9576 14:44:57.051180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9577 14:44:57.054343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9578 14:44:57.061050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9579 14:44:57.064354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9580 14:44:57.067690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9581 14:44:57.074392 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9582 14:44:57.078000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9583 14:44:57.084312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9584 14:44:57.087728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9585 14:44:57.094427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9586 14:44:57.097565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9587 14:44:57.104351 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9588 14:44:57.107705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9589 14:44:57.111185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9590 14:44:57.118043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9591 14:44:57.121385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9592 14:44:57.128000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9593 14:44:57.131269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9594 14:44:57.134069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9595 14:44:57.141443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9596 14:44:57.144502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9597 14:44:57.150941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9598 14:44:57.154208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9599 14:44:57.160800 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9600 14:44:57.164299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9601 14:44:57.170748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9602 14:44:57.173907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9603 14:44:57.177543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9604 14:44:57.184318 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9605 14:44:57.187466 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9606 14:44:57.190809 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9607 14:44:57.193968 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9608 14:44:57.200876 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9609 14:44:57.203992 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9610 14:44:57.210946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9611 14:44:57.214198 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9612 14:44:57.217178 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9613 14:44:57.223928 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9614 14:44:57.227170 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9615 14:44:57.234063 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9616 14:44:57.237446 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9617 14:44:57.240496 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9618 14:44:57.247125 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9619 14:44:57.250342 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9620 14:44:57.257007 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9621 14:44:57.260577 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9622 14:44:57.263903 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9623 14:44:57.270612 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9624 14:44:57.273930 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9625 14:44:57.277020 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9626 14:44:57.283695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9627 14:44:57.286899 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9628 14:44:57.290661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9629 14:44:57.293516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9630 14:44:57.300213 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9631 14:44:57.303844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9632 14:44:57.306957 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9633 14:44:57.313757 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9634 14:44:57.317016 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9635 14:44:57.320161 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9636 14:44:57.327188 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9637 14:44:57.330065 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9638 14:44:57.337203 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9639 14:44:57.340458 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9640 14:44:57.343709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9641 14:44:57.350194 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9642 14:44:57.353636 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9643 14:44:57.360060 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9644 14:44:57.363678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9645 14:44:57.366950 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9646 14:44:57.373501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9647 14:44:57.376724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9648 14:44:57.383704 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9649 14:44:57.386956 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9650 14:44:57.390062 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9651 14:44:57.397025 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9652 14:44:57.400525 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9653 14:44:57.403634 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9654 14:44:57.410402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9655 14:44:57.413454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9656 14:44:57.420383 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9657 14:44:57.423676 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9658 14:44:57.427307 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9659 14:44:57.433581 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9660 14:44:57.436923 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9661 14:44:57.443952 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9662 14:44:57.446921 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9663 14:44:57.450013 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9664 14:44:57.456780 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9665 14:44:57.460029 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9666 14:44:57.463740 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9667 14:44:57.470374 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9668 14:44:57.473570 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9669 14:44:57.480116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9670 14:44:57.483406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9671 14:44:57.486780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9672 14:44:57.493613 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9673 14:44:57.496408 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9674 14:44:57.503354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9675 14:44:57.506583 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9676 14:44:57.509708 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9677 14:44:57.516440 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9678 14:44:57.525683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9679 14:44:57.526719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9680 14:44:57.530087 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9681 14:44:57.533532 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9682 14:44:57.539752 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9683 14:44:57.543469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9684 14:44:57.546346 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9685 14:44:57.553087 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9686 14:44:57.556479 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9687 14:44:57.563092 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9688 14:44:57.566495 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9689 14:44:57.569856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9690 14:44:57.576318 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9691 14:44:57.579743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9692 14:44:57.586807 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9693 14:44:57.589691 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9694 14:44:57.592972 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9695 14:44:57.599856 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9696 14:44:57.603438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9697 14:44:57.609636 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9698 14:44:57.613446 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9699 14:44:57.616366 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9700 14:44:57.623286 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9701 14:44:57.626463 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9702 14:44:57.633333 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9703 14:44:57.636348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9704 14:44:57.639790 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9705 14:44:57.646620 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9706 14:44:57.649889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9707 14:44:57.656499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9708 14:44:57.659612 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9709 14:44:57.663134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9710 14:44:57.669733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9711 14:44:57.673129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9712 14:44:57.679962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9713 14:44:57.684050 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9714 14:44:57.689872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9715 14:44:57.692976 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9716 14:44:57.696482 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9717 14:44:57.703084 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9718 14:44:57.706145 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9719 14:44:57.712932 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9720 14:44:57.716391 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9721 14:44:57.719727 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9722 14:44:57.726582 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9723 14:44:57.729723 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9724 14:44:57.736510 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9725 14:44:57.739747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9726 14:44:57.746348 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9727 14:44:57.749534 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9728 14:44:57.752802 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9729 14:44:57.759544 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9730 14:44:57.762955 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9731 14:44:57.769652 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9732 14:44:57.772891 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9733 14:44:57.776305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9734 14:44:57.782769 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9735 14:44:57.786245 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9736 14:44:57.792821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9737 14:44:57.796232 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9738 14:44:57.799582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9739 14:44:57.802941 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9740 14:44:57.806407 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9741 14:44:57.812885 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9742 14:44:57.816199 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9743 14:44:57.822698 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9744 14:44:57.826202 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9745 14:44:57.829517 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9746 14:44:57.836271 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9747 14:44:57.839251 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9748 14:44:57.842861 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9749 14:44:57.849346 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9750 14:44:57.852505 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9751 14:44:57.855870 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9752 14:44:57.862470 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9753 14:44:57.866216 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9754 14:44:57.872690 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9755 14:44:57.875970 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9756 14:44:57.879360 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9757 14:44:57.885968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9758 14:44:57.889078 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9759 14:44:57.892356 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9760 14:44:57.899115 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9761 14:44:57.902508 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9762 14:44:57.905697 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9763 14:44:57.912693 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9764 14:44:57.915460 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9765 14:44:57.922257 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9766 14:44:57.925920 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9767 14:44:57.929040 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9768 14:44:57.935395 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9769 14:44:57.938977 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9770 14:44:57.942187 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9771 14:44:57.948836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9772 14:44:57.952165 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9773 14:44:57.955493 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9774 14:44:57.962042 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9775 14:44:57.965427 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9776 14:44:57.972333 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9777 14:44:57.975330 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9778 14:44:57.978712 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9779 14:44:57.982159 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9780 14:44:57.985693 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9781 14:44:57.991980 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9782 14:44:57.995298 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9783 14:44:57.998655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9784 14:44:58.002172 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9785 14:44:58.008896 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9786 14:44:58.011995 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9787 14:44:58.015525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9788 14:44:58.018654 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9789 14:44:58.025234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9790 14:44:58.028487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9791 14:44:58.035329 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9792 14:44:58.038456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9793 14:44:58.042015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9794 14:44:58.048860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9795 14:44:58.052162 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9796 14:44:58.058267 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9797 14:44:58.061623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9798 14:44:58.065043 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9799 14:44:58.071646 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9800 14:44:58.075221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9801 14:44:58.081681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9802 14:44:58.085003 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9803 14:44:58.088386 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9804 14:44:58.094933 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9805 14:44:58.098282 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9806 14:44:58.104938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9807 14:44:58.108159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9808 14:44:58.114841 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9809 14:44:58.118026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9810 14:44:58.121509 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9811 14:44:58.128060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9812 14:44:58.131437 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9813 14:44:58.137761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9814 14:44:58.141369 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9815 14:44:58.144680 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9816 14:44:58.151341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9817 14:44:58.154609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9818 14:44:58.160949 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9819 14:44:58.164499 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9820 14:44:58.170861 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9821 14:44:58.174321 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9822 14:44:58.177916 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9823 14:44:58.184485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9824 14:44:58.187815 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9825 14:44:58.194087 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9826 14:44:58.197661 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9827 14:44:58.200876 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9828 14:44:58.207765 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9829 14:44:58.210978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9830 14:44:58.217564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9831 14:44:58.220651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9832 14:44:58.224304 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9833 14:44:58.230771 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9834 14:44:58.234004 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9835 14:44:58.240948 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9836 14:44:58.244150 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9837 14:44:58.247361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9838 14:44:58.253908 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9839 14:44:58.257081 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9840 14:44:58.263869 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9841 14:44:58.267418 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9842 14:44:58.273767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9843 14:44:58.277089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9844 14:44:58.280725 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9845 14:44:58.287300 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9846 14:44:58.290494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9847 14:44:58.297186 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9848 14:44:58.300412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9849 14:44:58.303642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9850 14:44:58.310338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9851 14:44:58.314112 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9852 14:44:58.320305 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9853 14:44:58.323882 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9854 14:44:58.327047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9855 14:44:58.333869 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9856 14:44:58.336986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9857 14:44:58.343866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9858 14:44:58.346948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9859 14:44:58.350064 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9860 14:44:58.357186 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9861 14:44:58.360502 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9862 14:44:58.366993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9863 14:44:58.370399 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9864 14:44:58.376930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9865 14:44:58.380266 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9866 14:44:58.383585 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9867 14:44:58.390337 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9868 14:44:58.393554 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9869 14:44:58.400390 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9870 14:44:58.403643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9871 14:44:58.410118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9872 14:44:58.413429 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9873 14:44:58.416999 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9874 14:44:58.423434 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9875 14:44:58.427032 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9876 14:44:58.433745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9877 14:44:58.436831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9878 14:44:58.440090 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9879 14:44:58.446799 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9880 14:44:58.450390 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9881 14:44:58.456711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9882 14:44:58.460198 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9883 14:44:58.466638 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9884 14:44:58.470068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9885 14:44:58.476810 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9886 14:44:58.480081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9887 14:44:58.483404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9888 14:44:58.490339 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9889 14:44:58.493451 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9890 14:44:58.500273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9891 14:44:58.503182 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9892 14:44:58.510172 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9893 14:44:58.513467 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9894 14:44:58.516505 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9895 14:44:58.523419 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9896 14:44:58.526543 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9897 14:44:58.533387 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9898 14:44:58.536600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9899 14:44:58.543338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9900 14:44:58.546932 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9901 14:44:58.550085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9902 14:44:58.556596 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9903 14:44:58.559714 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9904 14:44:58.566657 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9905 14:44:58.569805 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9906 14:44:58.576513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9907 14:44:58.579724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9908 14:44:58.586579 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9909 14:44:58.590007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9910 14:44:58.593177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9911 14:44:58.599882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9912 14:44:58.603177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9913 14:44:58.610005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9914 14:44:58.613018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9915 14:44:58.619892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9916 14:44:58.623118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9917 14:44:58.626406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9918 14:44:58.633171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9919 14:44:58.636321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9920 14:44:58.643096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9921 14:44:58.646334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9922 14:44:58.652923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9923 14:44:58.656472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9924 14:44:58.662846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9925 14:44:58.666409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9926 14:44:58.673045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9927 14:44:58.676328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9928 14:44:58.683152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9929 14:44:58.686512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9930 14:44:58.693148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9931 14:44:58.696445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9932 14:44:58.702854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9933 14:44:58.706478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9934 14:44:58.712953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9935 14:44:58.716230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9936 14:44:58.723027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9937 14:44:58.725873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9938 14:44:58.732462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9939 14:44:58.736165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9940 14:44:58.742700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9941 14:44:58.746270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9942 14:44:58.749278 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9943 14:44:58.752529 INFO: [APUAPC] vio 0
9944 14:44:58.759133 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9945 14:44:58.762660 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9946 14:44:58.765861 INFO: [APUAPC] D0_APC_0: 0x400510
9947 14:44:58.769571 INFO: [APUAPC] D0_APC_1: 0x0
9948 14:44:58.772513 INFO: [APUAPC] D0_APC_2: 0x1540
9949 14:44:58.775753 INFO: [APUAPC] D0_APC_3: 0x0
9950 14:44:58.779006 INFO: [APUAPC] D1_APC_0: 0xffffffff
9951 14:44:58.782544 INFO: [APUAPC] D1_APC_1: 0xffffffff
9952 14:44:58.785884 INFO: [APUAPC] D1_APC_2: 0x3fffff
9953 14:44:58.789104 INFO: [APUAPC] D1_APC_3: 0x0
9954 14:44:58.792317 INFO: [APUAPC] D2_APC_0: 0xffffffff
9955 14:44:58.795604 INFO: [APUAPC] D2_APC_1: 0xffffffff
9956 14:44:58.799060 INFO: [APUAPC] D2_APC_2: 0x3fffff
9957 14:44:58.802629 INFO: [APUAPC] D2_APC_3: 0x0
9958 14:44:58.805415 INFO: [APUAPC] D3_APC_0: 0xffffffff
9959 14:44:58.809024 INFO: [APUAPC] D3_APC_1: 0xffffffff
9960 14:44:58.812233 INFO: [APUAPC] D3_APC_2: 0x3fffff
9961 14:44:58.815410 INFO: [APUAPC] D3_APC_3: 0x0
9962 14:44:58.818875 INFO: [APUAPC] D4_APC_0: 0xffffffff
9963 14:44:58.822121 INFO: [APUAPC] D4_APC_1: 0xffffffff
9964 14:44:58.825768 INFO: [APUAPC] D4_APC_2: 0x3fffff
9965 14:44:58.825855 INFO: [APUAPC] D4_APC_3: 0x0
9966 14:44:58.829123 INFO: [APUAPC] D5_APC_0: 0xffffffff
9967 14:44:58.832260 INFO: [APUAPC] D5_APC_1: 0xffffffff
9968 14:44:58.835899 INFO: [APUAPC] D5_APC_2: 0x3fffff
9969 14:44:58.838706 INFO: [APUAPC] D5_APC_3: 0x0
9970 14:44:58.842137 INFO: [APUAPC] D6_APC_0: 0xffffffff
9971 14:44:58.845481 INFO: [APUAPC] D6_APC_1: 0xffffffff
9972 14:44:58.848978 INFO: [APUAPC] D6_APC_2: 0x3fffff
9973 14:44:58.852206 INFO: [APUAPC] D6_APC_3: 0x0
9974 14:44:58.855413 INFO: [APUAPC] D7_APC_0: 0xffffffff
9975 14:44:58.858550 INFO: [APUAPC] D7_APC_1: 0xffffffff
9976 14:44:58.861939 INFO: [APUAPC] D7_APC_2: 0x3fffff
9977 14:44:58.865139 INFO: [APUAPC] D7_APC_3: 0x0
9978 14:44:58.868888 INFO: [APUAPC] D8_APC_0: 0xffffffff
9979 14:44:58.871809 INFO: [APUAPC] D8_APC_1: 0xffffffff
9980 14:44:58.875503 INFO: [APUAPC] D8_APC_2: 0x3fffff
9981 14:44:58.878654 INFO: [APUAPC] D8_APC_3: 0x0
9982 14:44:58.881973 INFO: [APUAPC] D9_APC_0: 0xffffffff
9983 14:44:58.885464 INFO: [APUAPC] D9_APC_1: 0xffffffff
9984 14:44:58.888704 INFO: [APUAPC] D9_APC_2: 0x3fffff
9985 14:44:58.892177 INFO: [APUAPC] D9_APC_3: 0x0
9986 14:44:58.895285 INFO: [APUAPC] D10_APC_0: 0xffffffff
9987 14:44:58.898637 INFO: [APUAPC] D10_APC_1: 0xffffffff
9988 14:44:58.901925 INFO: [APUAPC] D10_APC_2: 0x3fffff
9989 14:44:58.905201 INFO: [APUAPC] D10_APC_3: 0x0
9990 14:44:58.908659 INFO: [APUAPC] D11_APC_0: 0xffffffff
9991 14:44:58.911775 INFO: [APUAPC] D11_APC_1: 0xffffffff
9992 14:44:58.915122 INFO: [APUAPC] D11_APC_2: 0x3fffff
9993 14:44:58.918569 INFO: [APUAPC] D11_APC_3: 0x0
9994 14:44:58.921688 INFO: [APUAPC] D12_APC_0: 0xffffffff
9995 14:44:58.925295 INFO: [APUAPC] D12_APC_1: 0xffffffff
9996 14:44:58.928134 INFO: [APUAPC] D12_APC_2: 0x3fffff
9997 14:44:58.931612 INFO: [APUAPC] D12_APC_3: 0x0
9998 14:44:58.934978 INFO: [APUAPC] D13_APC_0: 0xffffffff
9999 14:44:58.938503 INFO: [APUAPC] D13_APC_1: 0xffffffff
10000 14:44:58.941825 INFO: [APUAPC] D13_APC_2: 0x3fffff
10001 14:44:58.944948 INFO: [APUAPC] D13_APC_3: 0x0
10002 14:44:58.948056 INFO: [APUAPC] D14_APC_0: 0xffffffff
10003 14:44:58.951783 INFO: [APUAPC] D14_APC_1: 0xffffffff
10004 14:44:58.954894 INFO: [APUAPC] D14_APC_2: 0x3fffff
10005 14:44:58.958042 INFO: [APUAPC] D14_APC_3: 0x0
10006 14:44:58.961380 INFO: [APUAPC] D15_APC_0: 0xffffffff
10007 14:44:58.964646 INFO: [APUAPC] D15_APC_1: 0xffffffff
10008 14:44:58.968203 INFO: [APUAPC] D15_APC_2: 0x3fffff
10009 14:44:58.971514 INFO: [APUAPC] D15_APC_3: 0x0
10010 14:44:58.974771 INFO: [APUAPC] APC_CON: 0x4
10011 14:44:58.978224 INFO: [NOCDAPC] D0_APC_0: 0x0
10012 14:44:58.981391 INFO: [NOCDAPC] D0_APC_1: 0x0
10013 14:44:58.984333 INFO: [NOCDAPC] D1_APC_0: 0x0
10014 14:44:58.987774 INFO: [NOCDAPC] D1_APC_1: 0xfff
10015 14:44:58.987892 INFO: [NOCDAPC] D2_APC_0: 0x0
10016 14:44:58.991096 INFO: [NOCDAPC] D2_APC_1: 0xfff
10017 14:44:58.994725 INFO: [NOCDAPC] D3_APC_0: 0x0
10018 14:44:58.997970 INFO: [NOCDAPC] D3_APC_1: 0xfff
10019 14:44:59.001282 INFO: [NOCDAPC] D4_APC_0: 0x0
10020 14:44:59.004540 INFO: [NOCDAPC] D4_APC_1: 0xfff
10021 14:44:59.007865 INFO: [NOCDAPC] D5_APC_0: 0x0
10022 14:44:59.011121 INFO: [NOCDAPC] D5_APC_1: 0xfff
10023 14:44:59.014773 INFO: [NOCDAPC] D6_APC_0: 0x0
10024 14:44:59.017610 INFO: [NOCDAPC] D6_APC_1: 0xfff
10025 14:44:59.021318 INFO: [NOCDAPC] D7_APC_0: 0x0
10026 14:44:59.024324 INFO: [NOCDAPC] D7_APC_1: 0xfff
10027 14:44:59.024408 INFO: [NOCDAPC] D8_APC_0: 0x0
10028 14:44:59.027637 INFO: [NOCDAPC] D8_APC_1: 0xfff
10029 14:44:59.031240 INFO: [NOCDAPC] D9_APC_0: 0x0
10030 14:44:59.034439 INFO: [NOCDAPC] D9_APC_1: 0xfff
10031 14:44:59.037747 INFO: [NOCDAPC] D10_APC_0: 0x0
10032 14:44:59.041003 INFO: [NOCDAPC] D10_APC_1: 0xfff
10033 14:44:59.044302 INFO: [NOCDAPC] D11_APC_0: 0x0
10034 14:44:59.047617 INFO: [NOCDAPC] D11_APC_1: 0xfff
10035 14:44:59.050947 INFO: [NOCDAPC] D12_APC_0: 0x0
10036 14:44:59.054520 INFO: [NOCDAPC] D12_APC_1: 0xfff
10037 14:44:59.057673 INFO: [NOCDAPC] D13_APC_0: 0x0
10038 14:44:59.060810 INFO: [NOCDAPC] D13_APC_1: 0xfff
10039 14:44:59.064446 INFO: [NOCDAPC] D14_APC_0: 0x0
10040 14:44:59.067621 INFO: [NOCDAPC] D14_APC_1: 0xfff
10041 14:44:59.067709 INFO: [NOCDAPC] D15_APC_0: 0x0
10042 14:44:59.070855 INFO: [NOCDAPC] D15_APC_1: 0xfff
10043 14:44:59.074180 INFO: [NOCDAPC] APC_CON: 0x4
10044 14:44:59.077376 INFO: [APUAPC] set_apusys_apc done
10045 14:44:59.081104 INFO: [DEVAPC] devapc_init done
10046 14:44:59.084257 INFO: GICv3 without legacy support detected.
10047 14:44:59.090792 INFO: ARM GICv3 driver initialized in EL3
10048 14:44:59.094504 INFO: Maximum SPI INTID supported: 639
10049 14:44:59.097438 INFO: BL31: Initializing runtime services
10050 14:44:59.103880 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10051 14:44:59.107232 INFO: SPM: enable CPC mode
10052 14:44:59.110977 INFO: mcdi ready for mcusys-off-idle and system suspend
10053 14:44:59.117291 INFO: BL31: Preparing for EL3 exit to normal world
10054 14:44:59.120624 INFO: Entry point address = 0x80000000
10055 14:44:59.120710 INFO: SPSR = 0x8
10056 14:44:59.127072
10057 14:44:59.127157
10058 14:44:59.127225
10059 14:44:59.130415 Starting depthcharge on Spherion...
10060 14:44:59.130500
10061 14:44:59.130568 Wipe memory regions:
10062 14:44:59.130629
10063 14:44:59.131230 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10064 14:44:59.131330 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10065 14:44:59.131419 Setting prompt string to ['asurada:']
10066 14:44:59.131504 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10067 14:44:59.133647 [0x00000040000000, 0x00000054600000)
10068 14:44:59.256510
10069 14:44:59.256866 [0x00000054660000, 0x00000080000000)
10070 14:44:59.516450
10071 14:44:59.516647 [0x000000821a7280, 0x000000ffe64000)
10072 14:45:00.262159
10073 14:45:00.262725 [0x00000100000000, 0x00000240000000)
10074 14:45:02.152212
10075 14:45:02.155268 Initializing XHCI USB controller at 0x11200000.
10076 14:45:03.193499
10077 14:45:03.196576 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10078 14:45:03.197006
10079 14:45:03.197342
10080 14:45:03.198309 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 14:45:03.299437 asurada: tftpboot 192.168.201.1 14166994/tftp-deploy-rqbtyl8_/kernel/image.itb 14166994/tftp-deploy-rqbtyl8_/kernel/cmdline
10083 14:45:03.299961 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 14:45:03.300338 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10085 14:45:03.305007 tftpboot 192.168.201.1 14166994/tftp-deploy-rqbtyl8_/kernel/image.itp-deploy-rqbtyl8_/kernel/cmdline
10086 14:45:03.305342
10087 14:45:03.305603 Waiting for link
10088 14:45:03.462821
10089 14:45:03.463072 R8152: Initializing
10090 14:45:03.463224
10091 14:45:03.466039 Version 9 (ocp_data = 6010)
10092 14:45:03.466198
10093 14:45:03.469137 R8152: Done initializing
10094 14:45:03.469272
10095 14:45:03.469379 Adding net device
10096 14:45:05.340968
10097 14:45:05.341122 done.
10098 14:45:05.341195
10099 14:45:05.341263 MAC: 00:e0:4c:72:2d:d6
10100 14:45:05.341353
10101 14:45:05.344335 Sending DHCP discover... done.
10102 14:45:05.344447
10103 14:45:05.347362 Waiting for reply... done.
10104 14:45:05.347447
10105 14:45:05.350424 Sending DHCP request... done.
10106 14:45:05.350513
10107 14:45:05.358644 Waiting for reply... done.
10108 14:45:05.358752
10109 14:45:05.358822 My ip is 192.168.201.21
10110 14:45:05.358884
10111 14:45:05.361868 The DHCP server ip is 192.168.201.1
10112 14:45:05.361956
10113 14:45:05.368715 TFTP server IP predefined by user: 192.168.201.1
10114 14:45:05.368811
10115 14:45:05.375281 Bootfile predefined by user: 14166994/tftp-deploy-rqbtyl8_/kernel/image.itb
10116 14:45:05.375378
10117 14:45:05.375448 Sending tftp read request... done.
10118 14:45:05.378817
10119 14:45:05.378904 Waiting for the transfer...
10120 14:45:05.378972
10121 14:45:05.676133 00000000 ################################################################
10122 14:45:05.676286
10123 14:45:05.946144 00080000 ################################################################
10124 14:45:05.946283
10125 14:45:06.207755 00100000 ################################################################
10126 14:45:06.207908
10127 14:45:06.456472 00180000 ################################################################
10128 14:45:06.456629
10129 14:45:06.706903 00200000 ################################################################
10130 14:45:06.707041
10131 14:45:06.969497 00280000 ################################################################
10132 14:45:06.969636
10133 14:45:07.227121 00300000 ################################################################
10134 14:45:07.227254
10135 14:45:07.492348 00380000 ################################################################
10136 14:45:07.492499
10137 14:45:07.755759 00400000 ################################################################
10138 14:45:07.755908
10139 14:45:08.014225 00480000 ################################################################
10140 14:45:08.014361
10141 14:45:08.272468 00500000 ################################################################
10142 14:45:08.272662
10143 14:45:08.550471 00580000 ################################################################
10144 14:45:08.550612
10145 14:45:08.824885 00600000 ################################################################
10146 14:45:08.825023
10147 14:45:09.099730 00680000 ################################################################
10148 14:45:09.099871
10149 14:45:09.367108 00700000 ################################################################
10150 14:45:09.367243
10151 14:45:09.634951 00780000 ################################################################
10152 14:45:09.635085
10153 14:45:09.886645 00800000 ################################################################
10154 14:45:09.886784
10155 14:45:10.147774 00880000 ################################################################
10156 14:45:10.147913
10157 14:45:10.396838 00900000 ################################################################
10158 14:45:10.396971
10159 14:45:10.648154 00980000 ################################################################
10160 14:45:10.648301
10161 14:45:10.902050 00a00000 ################################################################
10162 14:45:10.902181
10163 14:45:11.165758 00a80000 ################################################################
10164 14:45:11.165919
10165 14:45:11.428100 00b00000 ################################################################
10166 14:45:11.428225
10167 14:45:11.682618 00b80000 ################################################################
10168 14:45:11.682741
10169 14:45:11.946567 00c00000 ################################################################
10170 14:45:11.946726
10171 14:45:12.196945 00c80000 ################################################################
10172 14:45:12.197071
10173 14:45:12.446989 00d00000 ################################################################
10174 14:45:12.447144
10175 14:45:12.698120 00d80000 ################################################################
10176 14:45:12.698258
10177 14:45:12.951066 00e00000 ################################################################
10178 14:45:12.951238
10179 14:45:13.211424 00e80000 ################################################################
10180 14:45:13.211588
10181 14:45:13.489107 00f00000 ################################################################
10182 14:45:13.489261
10183 14:45:13.759951 00f80000 ################################################################
10184 14:45:13.760108
10185 14:45:14.015990 01000000 ################################################################
10186 14:45:14.016149
10187 14:45:14.270168 01080000 ################################################################
10188 14:45:14.270329
10189 14:45:14.527285 01100000 ################################################################
10190 14:45:14.527417
10191 14:45:14.813444 01180000 ################################################################
10192 14:45:14.813569
10193 14:45:15.064904 01200000 ################################################################
10194 14:45:15.065041
10195 14:45:15.305953 01280000 ################################################################
10196 14:45:15.306086
10197 14:45:15.547308 01300000 ################################################################
10198 14:45:15.547465
10199 14:45:15.788849 01380000 ################################################################
10200 14:45:15.789007
10201 14:45:16.030782 01400000 ################################################################
10202 14:45:16.030914
10203 14:45:16.272609 01480000 ################################################################
10204 14:45:16.272774
10205 14:45:16.514878 01500000 ################################################################
10206 14:45:16.515053
10207 14:45:16.756925 01580000 ################################################################
10208 14:45:16.757069
10209 14:45:16.998661 01600000 ################################################################
10210 14:45:16.998816
10211 14:45:17.239666 01680000 ################################################################
10212 14:45:17.239803
10213 14:45:17.483354 01700000 ################################################################
10214 14:45:17.483490
10215 14:45:17.725964 01780000 ################################################################
10216 14:45:17.726095
10217 14:45:17.965853 01800000 ################################################################
10218 14:45:17.966016
10219 14:45:18.205626 01880000 ################################################################
10220 14:45:18.205762
10221 14:45:18.448397 01900000 ################################################################
10222 14:45:18.448535
10223 14:45:18.692219 01980000 ################################################################
10224 14:45:18.692355
10225 14:45:18.934533 01a00000 ################################################################
10226 14:45:18.934667
10227 14:45:19.181056 01a80000 ################################################################
10228 14:45:19.181222
10229 14:45:19.440939 01b00000 ################################################################
10230 14:45:19.441078
10231 14:45:19.710272 01b80000 ################################################################
10232 14:45:19.710406
10233 14:45:19.972559 01c00000 ################################################################
10234 14:45:19.972732
10235 14:45:20.233060 01c80000 ################################################################
10236 14:45:20.233225
10237 14:45:20.489425 01d00000 ################################################################
10238 14:45:20.489559
10239 14:45:20.741744 01d80000 ################################################################
10240 14:45:20.741898
10241 14:45:20.932542 01e00000 ################################################ done.
10242 14:45:20.932688
10243 14:45:20.935970 The bootfile was 31845806 bytes long.
10244 14:45:20.936071
10245 14:45:20.939056 Sending tftp read request... done.
10246 14:45:20.939157
10247 14:45:20.942501 Waiting for the transfer...
10248 14:45:20.942602
10249 14:45:20.942696 00000000 # done.
10250 14:45:20.942787
10251 14:45:20.952491 Command line loaded dynamically from TFTP file: 14166994/tftp-deploy-rqbtyl8_/kernel/cmdline
10252 14:45:20.952618
10253 14:45:20.975362 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10254 14:45:20.975484
10255 14:45:20.975581 Loading FIT.
10256 14:45:20.975673
10257 14:45:20.978730 Image ramdisk-1 has 18735895 bytes.
10258 14:45:20.978829
10259 14:45:20.981928 Image fdt-1 has 47258 bytes.
10260 14:45:20.982031
10261 14:45:20.985477 Image kernel-1 has 13060619 bytes.
10262 14:45:20.985550
10263 14:45:20.992026 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10264 14:45:20.992127
10265 14:45:21.011758 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10266 14:45:21.011846
10267 14:45:21.015269 Choosing best match conf-1 for compat google,spherion-rev2.
10268 14:45:21.020293
10269 14:45:21.024673 Connected to device vid:did:rid of 1ae0:0028:00
10270 14:45:21.032997
10271 14:45:21.036447 tpm_get_response: command 0x17b, return code 0x0
10272 14:45:21.036555
10273 14:45:21.039548 ec_init: CrosEC protocol v3 supported (256, 248)
10274 14:45:21.043278
10275 14:45:21.046722 tpm_cleanup: add release locality here.
10276 14:45:21.046797
10277 14:45:21.046860 Shutting down all USB controllers.
10278 14:45:21.046920
10279 14:45:21.050191 Removing current net device
10280 14:45:21.050261
10281 14:45:21.057005 Exiting depthcharge with code 4 at timestamp: 51243984
10282 14:45:21.057117
10283 14:45:21.060159 LZMA decompressing kernel-1 to 0x821a6718
10284 14:45:21.060258
10285 14:45:21.063277 LZMA decompressing kernel-1 to 0x40000000
10286 14:45:22.676365
10287 14:45:22.676932 jumping to kernel
10288 14:45:22.678715 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10289 14:45:22.679393 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10290 14:45:22.679872 Setting prompt string to ['Linux version [0-9]']
10291 14:45:22.680269 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10292 14:45:22.680689 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10293 14:45:22.758291
10294 14:45:22.761691 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10295 14:45:22.765539 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10296 14:45:22.766157 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10297 14:45:22.766574 Setting prompt string to []
10298 14:45:22.767049 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10299 14:45:22.767735 Using line separator: #'\n'#
10300 14:45:22.768117 No login prompt set.
10301 14:45:22.768474 Parsing kernel messages
10302 14:45:22.768852 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10303 14:45:22.769449 [login-action] Waiting for messages, (timeout 00:04:03)
10304 14:45:22.769836 Waiting using forced prompt support (timeout 00:02:02)
10305 14:45:22.784703 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10306 14:45:22.787995 [ 0.000000] random: crng init done
10307 14:45:22.794680 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10308 14:45:22.798173 [ 0.000000] efi: UEFI not found.
10309 14:45:22.805152 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10310 14:45:22.811529 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10311 14:45:22.821393 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 14:45:22.831387 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 14:45:22.837850 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10314 14:45:22.841398 [ 0.000000] printk: bootconsole [mtk8250] enabled
10315 14:45:22.850484 [ 0.000000] NUMA: No NUMA configuration found
10316 14:45:22.857247 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10317 14:45:22.863627 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10318 14:45:22.864185 [ 0.000000] Zone ranges:
10319 14:45:22.870212 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10320 14:45:22.873957 [ 0.000000] DMA32 empty
10321 14:45:22.880269 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10322 14:45:22.883754 [ 0.000000] Movable zone start for each node
10323 14:45:22.887239 [ 0.000000] Early memory node ranges
10324 14:45:22.893786 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10325 14:45:22.900484 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10326 14:45:22.906956 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10327 14:45:22.913733 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10328 14:45:22.920526 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10329 14:45:22.926731 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10330 14:45:22.982888 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10331 14:45:22.989684 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10332 14:45:22.996298 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10333 14:45:22.999586 [ 0.000000] psci: probing for conduit method from DT.
10334 14:45:23.005981 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10335 14:45:23.009384 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10336 14:45:23.016185 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10337 14:45:23.019602 [ 0.000000] psci: SMC Calling Convention v1.2
10338 14:45:23.026356 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10339 14:45:23.029151 [ 0.000000] Detected VIPT I-cache on CPU0
10340 14:45:23.036153 [ 0.000000] CPU features: detected: GIC system register CPU interface
10341 14:45:23.042579 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10342 14:45:23.049461 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10343 14:45:23.056337 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10344 14:45:23.062652 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10345 14:45:23.072518 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10346 14:45:23.075615 [ 0.000000] alternatives: applying boot alternatives
10347 14:45:23.082701 [ 0.000000] Fallback order for Node 0: 0
10348 14:45:23.089231 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10349 14:45:23.092810 [ 0.000000] Policy zone: Normal
10350 14:45:23.115538 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10351 14:45:23.125313 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10352 14:45:23.136099 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10353 14:45:23.145766 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10354 14:45:23.152688 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10355 14:45:23.155785 <6>[ 0.000000] software IO TLB: area num 8.
10356 14:45:23.212698 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10357 14:45:23.362063 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10358 14:45:23.368508 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10359 14:45:23.375603 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10360 14:45:23.378846 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10361 14:45:23.385594 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10362 14:45:23.391765 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10363 14:45:23.395388 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10364 14:45:23.405155 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10365 14:45:23.411573 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10366 14:45:23.414898 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10367 14:45:23.422671 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10368 14:45:23.426163 <6>[ 0.000000] GICv3: 608 SPIs implemented
10369 14:45:23.432932 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10370 14:45:23.436107 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10371 14:45:23.439367 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10372 14:45:23.449376 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10373 14:45:23.459611 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10374 14:45:23.472666 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10375 14:45:23.479340 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10376 14:45:23.488725 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10377 14:45:23.501813 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10378 14:45:23.508195 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10379 14:45:23.514903 <6>[ 0.009180] Console: colour dummy device 80x25
10380 14:45:23.524996 <6>[ 0.013939] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10381 14:45:23.531305 <6>[ 0.024381] pid_max: default: 32768 minimum: 301
10382 14:45:23.534572 <6>[ 0.029254] LSM: Security Framework initializing
10383 14:45:23.541495 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 14:45:23.551740 <6>[ 0.042051] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 14:45:23.558261 <6>[ 0.051496] cblist_init_generic: Setting adjustable number of callback queues.
10386 14:45:23.564797 <6>[ 0.058985] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 14:45:23.574427 <6>[ 0.065364] cblist_init_generic: Setting adjustable number of callback queues.
10388 14:45:23.580856 <6>[ 0.072836] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 14:45:23.584477 <6>[ 0.079273] rcu: Hierarchical SRCU implementation.
10390 14:45:23.591046 <6>[ 0.084289] rcu: Max phase no-delay instances is 1000.
10391 14:45:23.597319 <6>[ 0.091325] EFI services will not be available.
10392 14:45:23.600664 <6>[ 0.096283] smp: Bringing up secondary CPUs ...
10393 14:45:23.608970 <6>[ 0.101332] Detected VIPT I-cache on CPU1
10394 14:45:23.615525 <6>[ 0.101404] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 14:45:23.622142 <6>[ 0.101436] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 14:45:23.625776 <6>[ 0.101767] Detected VIPT I-cache on CPU2
10397 14:45:23.632285 <6>[ 0.101816] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 14:45:23.642152 <6>[ 0.101832] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 14:45:23.645437 <6>[ 0.102091] Detected VIPT I-cache on CPU3
10400 14:45:23.652063 <6>[ 0.102138] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 14:45:23.658720 <6>[ 0.102152] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 14:45:23.662539 <6>[ 0.102458] CPU features: detected: Spectre-v4
10403 14:45:23.668513 <6>[ 0.102464] CPU features: detected: Spectre-BHB
10404 14:45:23.671829 <6>[ 0.102469] Detected PIPT I-cache on CPU4
10405 14:45:23.678575 <6>[ 0.102526] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 14:45:23.685079 <6>[ 0.102542] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 14:45:23.691648 <6>[ 0.102836] Detected PIPT I-cache on CPU5
10408 14:45:23.698339 <6>[ 0.102896] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 14:45:23.705110 <6>[ 0.102912] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 14:45:23.708173 <6>[ 0.103192] Detected PIPT I-cache on CPU6
10411 14:45:23.714679 <6>[ 0.103257] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 14:45:23.721378 <6>[ 0.103273] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 14:45:23.728274 <6>[ 0.103553] Detected PIPT I-cache on CPU7
10414 14:45:23.734909 <6>[ 0.103610] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 14:45:23.741868 <6>[ 0.103626] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 14:45:23.744886 <6>[ 0.103672] smp: Brought up 1 node, 8 CPUs
10417 14:45:23.751463 <6>[ 0.245173] SMP: Total of 8 processors activated.
10418 14:45:23.754672 <6>[ 0.250094] CPU features: detected: 32-bit EL0 Support
10419 14:45:23.765255 <6>[ 0.255457] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 14:45:23.771339 <6>[ 0.264257] CPU features: detected: Common not Private translations
10421 14:45:23.777997 <6>[ 0.270733] CPU features: detected: CRC32 instructions
10422 14:45:23.781679 <6>[ 0.276118] CPU features: detected: RCpc load-acquire (LDAPR)
10423 14:45:23.787954 <6>[ 0.282078] CPU features: detected: LSE atomic instructions
10424 14:45:23.794554 <6>[ 0.287859] CPU features: detected: Privileged Access Never
10425 14:45:23.797826 <6>[ 0.293639] CPU features: detected: RAS Extension Support
10426 14:45:23.807743 <6>[ 0.299248] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 14:45:23.811101 <6>[ 0.306470] CPU: All CPU(s) started at EL2
10428 14:45:23.817816 <6>[ 0.310787] alternatives: applying system-wide alternatives
10429 14:45:23.827093 <6>[ 0.321595] devtmpfs: initialized
10430 14:45:23.839245 <6>[ 0.330527] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10431 14:45:23.849696 <6>[ 0.340486] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10432 14:45:23.855951 <6>[ 0.348505] pinctrl core: initialized pinctrl subsystem
10433 14:45:23.859343 <6>[ 0.355119] DMI not present or invalid.
10434 14:45:23.866113 <6>[ 0.359528] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10435 14:45:23.873124 <6>[ 0.366391] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10436 14:45:23.883071 <6>[ 0.373978] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10437 14:45:23.889335 <6>[ 0.382200] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10438 14:45:23.896100 <6>[ 0.390442] audit: initializing netlink subsys (disabled)
10439 14:45:23.906135 <5>[ 0.396133] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10440 14:45:23.909458 <6>[ 0.396836] thermal_sys: Registered thermal governor 'step_wise'
10441 14:45:23.919122 <6>[ 0.404098] thermal_sys: Registered thermal governor 'power_allocator'
10442 14:45:23.922605 <6>[ 0.410351] cpuidle: using governor menu
10443 14:45:23.925881 <6>[ 0.421313] NET: Registered PF_QIPCRTR protocol family
10444 14:45:23.935970 <6>[ 0.426804] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10445 14:45:23.938774 <6>[ 0.433905] ASID allocator initialised with 32768 entries
10446 14:45:23.945942 <6>[ 0.440476] Serial: AMBA PL011 UART driver
10447 14:45:23.954704 <4>[ 0.449226] Trying to register duplicate clock ID: 134
10448 14:45:24.013175 <6>[ 0.510804] KASLR enabled
10449 14:45:24.027096 <6>[ 0.518532] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10450 14:45:24.033475 <6>[ 0.525548] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10451 14:45:24.040410 <6>[ 0.532039] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10452 14:45:24.047109 <6>[ 0.539042] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10453 14:45:24.053501 <6>[ 0.545529] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10454 14:45:24.060449 <6>[ 0.552533] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10455 14:45:24.066943 <6>[ 0.559021] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10456 14:45:24.073437 <6>[ 0.566025] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10457 14:45:24.076806 <6>[ 0.573468] ACPI: Interpreter disabled.
10458 14:45:24.085075 <6>[ 0.579899] iommu: Default domain type: Translated
10459 14:45:24.091538 <6>[ 0.585011] iommu: DMA domain TLB invalidation policy: strict mode
10460 14:45:24.095105 <5>[ 0.591671] SCSI subsystem initialized
10461 14:45:24.101879 <6>[ 0.595839] usbcore: registered new interface driver usbfs
10462 14:45:24.108372 <6>[ 0.601571] usbcore: registered new interface driver hub
10463 14:45:24.111972 <6>[ 0.607121] usbcore: registered new device driver usb
10464 14:45:24.118408 <6>[ 0.613221] pps_core: LinuxPPS API ver. 1 registered
10465 14:45:24.128234 <6>[ 0.618414] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10466 14:45:24.131583 <6>[ 0.627756] PTP clock support registered
10467 14:45:24.134846 <6>[ 0.631998] EDAC MC: Ver: 3.0.0
10468 14:45:24.142425 <6>[ 0.637151] FPGA manager framework
10469 14:45:24.149049 <6>[ 0.640837] Advanced Linux Sound Architecture Driver Initialized.
10470 14:45:24.152185 <6>[ 0.647614] vgaarb: loaded
10471 14:45:24.159100 <6>[ 0.650782] clocksource: Switched to clocksource arch_sys_counter
10472 14:45:24.162118 <5>[ 0.657232] VFS: Disk quotas dquot_6.6.0
10473 14:45:24.168669 <6>[ 0.661416] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10474 14:45:24.172174 <6>[ 0.668610] pnp: PnP ACPI: disabled
10475 14:45:24.180453 <6>[ 0.675292] NET: Registered PF_INET protocol family
10476 14:45:24.190592 <6>[ 0.680897] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10477 14:45:24.201554 <6>[ 0.693243] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10478 14:45:24.211733 <6>[ 0.702052] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10479 14:45:24.218241 <6>[ 0.710023] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10480 14:45:24.227873 <6>[ 0.718717] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10481 14:45:24.234588 <6>[ 0.728470] TCP: Hash tables configured (established 65536 bind 65536)
10482 14:45:24.241482 <6>[ 0.735338] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 14:45:24.251485 <6>[ 0.742535] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 14:45:24.258268 <6>[ 0.750239] NET: Registered PF_UNIX/PF_LOCAL protocol family
10485 14:45:24.261224 <6>[ 0.756313] RPC: Registered named UNIX socket transport module.
10486 14:45:24.267718 <6>[ 0.762462] RPC: Registered udp transport module.
10487 14:45:24.271161 <6>[ 0.767392] RPC: Registered tcp transport module.
10488 14:45:24.277617 <6>[ 0.772322] RPC: Registered tcp NFSv4.1 backchannel transport module.
10489 14:45:24.284564 <6>[ 0.778987] PCI: CLS 0 bytes, default 64
10490 14:45:24.287635 <6>[ 0.783317] Unpacking initramfs...
10491 14:45:24.303929 <6>[ 0.795344] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10492 14:45:24.313735 <6>[ 0.803976] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10493 14:45:24.317014 <6>[ 0.812801] kvm [1]: IPA Size Limit: 40 bits
10494 14:45:24.323713 <6>[ 0.817324] kvm [1]: GICv3: no GICV resource entry
10495 14:45:24.327184 <6>[ 0.822346] kvm [1]: disabling GICv2 emulation
10496 14:45:24.333590 <6>[ 0.827033] kvm [1]: GIC system register CPU interface enabled
10497 14:45:24.336695 <6>[ 0.833190] kvm [1]: vgic interrupt IRQ18
10498 14:45:24.343335 <6>[ 0.837542] kvm [1]: VHE mode initialized successfully
10499 14:45:24.350424 <5>[ 0.843896] Initialise system trusted keyrings
10500 14:45:24.356541 <6>[ 0.848699] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10501 14:45:24.364006 <6>[ 0.858618] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10502 14:45:24.370438 <5>[ 0.865008] NFS: Registering the id_resolver key type
10503 14:45:24.374333 <5>[ 0.870311] Key type id_resolver registered
10504 14:45:24.380203 <5>[ 0.874729] Key type id_legacy registered
10505 14:45:24.387196 <6>[ 0.879023] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10506 14:45:24.393784 <6>[ 0.885949] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10507 14:45:24.400194 <6>[ 0.893676] 9p: Installing v9fs 9p2000 file system support
10508 14:45:24.436461 <5>[ 0.931476] Key type asymmetric registered
10509 14:45:24.439980 <5>[ 0.935802] Asymmetric key parser 'x509' registered
10510 14:45:24.450038 <6>[ 0.940939] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10511 14:45:24.453476 <6>[ 0.948554] io scheduler mq-deadline registered
10512 14:45:24.456480 <6>[ 0.953316] io scheduler kyber registered
10513 14:45:24.475202 <6>[ 0.970210] EINJ: ACPI disabled.
10514 14:45:24.508357 <4>[ 0.996108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 14:45:24.518033 <4>[ 1.006722] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 14:45:24.532765 <6>[ 1.027635] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10517 14:45:24.541540 <6>[ 1.035720] printk: console [ttyS0] disabled
10518 14:45:24.568902 <6>[ 1.060347] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10519 14:45:24.575848 <6>[ 1.069818] printk: console [ttyS0] enabled
10520 14:45:24.579082 <6>[ 1.069818] printk: console [ttyS0] enabled
10521 14:45:24.585506 <6>[ 1.078713] printk: bootconsole [mtk8250] disabled
10522 14:45:24.589153 <6>[ 1.078713] printk: bootconsole [mtk8250] disabled
10523 14:45:24.595846 <6>[ 1.089736] SuperH (H)SCI(F) driver initialized
10524 14:45:24.599152 <6>[ 1.095006] msm_serial: driver initialized
10525 14:45:24.612722 <6>[ 1.103902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10526 14:45:24.622422 <6>[ 1.112448] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10527 14:45:24.629258 <6>[ 1.120990] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10528 14:45:24.639056 <6>[ 1.129616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10529 14:45:24.645412 <6>[ 1.138323] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10530 14:45:24.655503 <6>[ 1.147043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10531 14:45:24.665774 <6>[ 1.155583] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10532 14:45:24.671993 <6>[ 1.164398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10533 14:45:24.681875 <6>[ 1.172939] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10534 14:45:24.693724 <6>[ 1.188473] loop: module loaded
10535 14:45:24.700229 <6>[ 1.194221] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10536 14:45:24.722577 <4>[ 1.217500] mtk-pmic-keys: Failed to locate of_node [id: -1]
10537 14:45:24.729530 <6>[ 1.224321] megasas: 07.719.03.00-rc1
10538 14:45:24.739324 <6>[ 1.234019] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10539 14:45:24.747462 <6>[ 1.242174] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10540 14:45:24.763821 <6>[ 1.258639] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10541 14:45:24.819178 <6>[ 1.307575] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10542 14:45:25.072900 <6>[ 1.567679] Freeing initrd memory: 18292K
10543 14:45:25.084215 <6>[ 1.579118] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10544 14:45:25.095365 <6>[ 1.590229] tun: Universal TUN/TAP device driver, 1.6
10545 14:45:25.098742 <6>[ 1.596304] thunder_xcv, ver 1.0
10546 14:45:25.102203 <6>[ 1.599815] thunder_bgx, ver 1.0
10547 14:45:25.105443 <6>[ 1.603309] nicpf, ver 1.0
10548 14:45:25.116119 <6>[ 1.607355] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10549 14:45:25.119541 <6>[ 1.614831] hns3: Copyright (c) 2017 Huawei Corporation.
10550 14:45:25.122593 <6>[ 1.620422] hclge is initializing
10551 14:45:25.129281 <6>[ 1.624004] e1000: Intel(R) PRO/1000 Network Driver
10552 14:45:25.135807 <6>[ 1.629133] e1000: Copyright (c) 1999-2006 Intel Corporation.
10553 14:45:25.139160 <6>[ 1.635145] e1000e: Intel(R) PRO/1000 Network Driver
10554 14:45:25.146511 <6>[ 1.640361] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10555 14:45:25.153092 <6>[ 1.646547] igb: Intel(R) Gigabit Ethernet Network Driver
10556 14:45:25.159782 <6>[ 1.652196] igb: Copyright (c) 2007-2014 Intel Corporation.
10557 14:45:25.166444 <6>[ 1.658033] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10558 14:45:25.172682 <6>[ 1.664551] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10559 14:45:25.176110 <6>[ 1.671018] sky2: driver version 1.30
10560 14:45:25.182897 <6>[ 1.675948] usbcore: registered new device driver r8152-cfgselector
10561 14:45:25.189237 <6>[ 1.682483] usbcore: registered new interface driver r8152
10562 14:45:25.192928 <6>[ 1.688299] VFIO - User Level meta-driver version: 0.3
10563 14:45:25.202232 <6>[ 1.696530] usbcore: registered new interface driver usb-storage
10564 14:45:25.208741 <6>[ 1.702977] usbcore: registered new device driver onboard-usb-hub
10565 14:45:25.218209 <6>[ 1.712134] mt6397-rtc mt6359-rtc: registered as rtc0
10566 14:45:25.227843 <6>[ 1.717594] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:43:58 UTC (1717512238)
10567 14:45:25.231195 <6>[ 1.727169] i2c_dev: i2c /dev entries driver
10568 14:45:25.247793 <6>[ 1.738941] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10569 14:45:25.254841 <4>[ 1.747664] cpu cpu0: supply cpu not found, using dummy regulator
10570 14:45:25.261169 <4>[ 1.754086] cpu cpu1: supply cpu not found, using dummy regulator
10571 14:45:25.268409 <4>[ 1.760506] cpu cpu2: supply cpu not found, using dummy regulator
10572 14:45:25.274421 <4>[ 1.766908] cpu cpu3: supply cpu not found, using dummy regulator
10573 14:45:25.281096 <4>[ 1.773306] cpu cpu4: supply cpu not found, using dummy regulator
10574 14:45:25.288012 <4>[ 1.779717] cpu cpu5: supply cpu not found, using dummy regulator
10575 14:45:25.294822 <4>[ 1.786119] cpu cpu6: supply cpu not found, using dummy regulator
10576 14:45:25.297925 <4>[ 1.792516] cpu cpu7: supply cpu not found, using dummy regulator
10577 14:45:25.318514 <6>[ 1.813095] cpu cpu0: EM: created perf domain
10578 14:45:25.321692 <6>[ 1.818056] cpu cpu4: EM: created perf domain
10579 14:45:25.329221 <6>[ 1.823714] sdhci: Secure Digital Host Controller Interface driver
10580 14:45:25.335935 <6>[ 1.830145] sdhci: Copyright(c) Pierre Ossman
10581 14:45:25.342521 <6>[ 1.835105] Synopsys Designware Multimedia Card Interface Driver
10582 14:45:25.349093 <6>[ 1.841753] sdhci-pltfm: SDHCI platform and OF driver helper
10583 14:45:25.352490 <6>[ 1.841809] mmc0: CQHCI version 5.10
10584 14:45:25.358787 <6>[ 1.851731] ledtrig-cpu: registered to indicate activity on CPUs
10585 14:45:25.365904 <6>[ 1.858854] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10586 14:45:25.372281 <6>[ 1.865901] usbcore: registered new interface driver usbhid
10587 14:45:25.375652 <6>[ 1.871723] usbhid: USB HID core driver
10588 14:45:25.382500 <6>[ 1.875922] spi_master spi0: will run message pump with realtime priority
10589 14:45:25.428095 <6>[ 1.916291] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10590 14:45:25.446767 <6>[ 1.931522] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10591 14:45:25.450607 <6>[ 1.945080] mmc0: Command Queue Engine enabled
10592 14:45:25.456895 <6>[ 1.949842] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10593 14:45:25.463689 <6>[ 1.956751] cros-ec-spi spi0.0: Chrome EC device registered
10594 14:45:25.467096 <6>[ 1.957042] mmcblk0: mmc0:0001 DA4128 116 GiB
10595 14:45:25.477991 <6>[ 1.972902] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10596 14:45:25.485634 <6>[ 1.980215] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10597 14:45:25.492031 <6>[ 1.986076] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10598 14:45:25.498580 <6>[ 1.991968] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10599 14:45:25.512666 <6>[ 2.004220] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10600 14:45:25.520074 <6>[ 2.014761] NET: Registered PF_PACKET protocol family
10601 14:45:25.523309 <6>[ 2.020159] 9pnet: Installing 9P2000 support
10602 14:45:25.530150 <5>[ 2.024725] Key type dns_resolver registered
10603 14:45:25.533278 <6>[ 2.029705] registered taskstats version 1
10604 14:45:25.539993 <5>[ 2.034096] Loading compiled-in X.509 certificates
10605 14:45:25.569825 <4>[ 2.057750] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 14:45:25.579751 <4>[ 2.068496] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10607 14:45:25.594451 <6>[ 2.089001] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10608 14:45:25.601048 <6>[ 2.095788] xhci-mtk 11200000.usb: xHCI Host Controller
10609 14:45:25.608003 <6>[ 2.101298] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10610 14:45:25.618019 <6>[ 2.109163] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10611 14:45:25.624737 <6>[ 2.118599] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10612 14:45:25.631951 <6>[ 2.124788] xhci-mtk 11200000.usb: xHCI Host Controller
10613 14:45:25.638219 <6>[ 2.130291] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10614 14:45:25.644909 <6>[ 2.137960] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10615 14:45:25.651414 <6>[ 2.145849] hub 1-0:1.0: USB hub found
10616 14:45:25.654964 <6>[ 2.149877] hub 1-0:1.0: 1 port detected
10617 14:45:25.661709 <6>[ 2.154173] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10618 14:45:25.668039 <6>[ 2.162799] hub 2-0:1.0: USB hub found
10619 14:45:25.671772 <6>[ 2.166807] hub 2-0:1.0: 1 port detected
10620 14:45:25.679313 <6>[ 2.173853] mtk-msdc 11f70000.mmc: Got CD GPIO
10621 14:45:25.692827 <6>[ 2.184166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10622 14:45:25.699527 <6>[ 2.192198] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10623 14:45:25.709606 <4>[ 2.200112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10624 14:45:25.719685 <6>[ 2.209681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10625 14:45:25.726563 <6>[ 2.217761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10626 14:45:25.732677 <6>[ 2.225784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10627 14:45:25.743239 <6>[ 2.233697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10628 14:45:25.749651 <6>[ 2.241514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10629 14:45:25.759441 <6>[ 2.249334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10630 14:45:25.769370 <6>[ 2.259810] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10631 14:45:25.776002 <6>[ 2.268174] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10632 14:45:25.785830 <6>[ 2.276522] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10633 14:45:25.792568 <6>[ 2.284860] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10634 14:45:25.802795 <6>[ 2.293199] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10635 14:45:25.809361 <6>[ 2.301538] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10636 14:45:25.819448 <6>[ 2.309876] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10637 14:45:25.825920 <6>[ 2.318213] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10638 14:45:25.836013 <6>[ 2.326551] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10639 14:45:25.842688 <6>[ 2.334889] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10640 14:45:25.852697 <6>[ 2.343228] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10641 14:45:25.859373 <6>[ 2.351565] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10642 14:45:25.869323 <6>[ 2.359903] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10643 14:45:25.875975 <6>[ 2.368243] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10644 14:45:25.886115 <6>[ 2.376582] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10645 14:45:25.892933 <6>[ 2.385316] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10646 14:45:25.899859 <6>[ 2.392493] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10647 14:45:25.906455 <6>[ 2.399264] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10648 14:45:25.913102 <6>[ 2.406034] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10649 14:45:25.919642 <6>[ 2.412963] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10650 14:45:25.929658 <6>[ 2.419813] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10651 14:45:25.939724 <6>[ 2.428951] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10652 14:45:25.949415 <6>[ 2.438072] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10653 14:45:25.955975 <6>[ 2.447366] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10654 14:45:25.966094 <6>[ 2.456833] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10655 14:45:25.976258 <6>[ 2.466300] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10656 14:45:25.985496 <6>[ 2.475419] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10657 14:45:25.996156 <6>[ 2.484885] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10658 14:45:26.002597 <6>[ 2.494004] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10659 14:45:26.015709 <6>[ 2.503300] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10660 14:45:26.025472 <6>[ 2.513461] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10661 14:45:26.035576 <6>[ 2.525037] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10662 14:45:26.041966 <6>[ 2.534459] Trying to probe devices needed for running init ...
10663 14:45:26.084102 <6>[ 2.575073] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10664 14:45:26.238703 <6>[ 2.733209] hub 1-1:1.0: USB hub found
10665 14:45:26.242132 <6>[ 2.737707] hub 1-1:1.0: 4 ports detected
10666 14:45:26.251845 <6>[ 2.746299] hub 1-1:1.0: USB hub found
10667 14:45:26.255345 <6>[ 2.750630] hub 1-1:1.0: 4 ports detected
10668 14:45:26.364056 <6>[ 2.855410] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10669 14:45:26.389856 <6>[ 2.884761] hub 2-1:1.0: USB hub found
10670 14:45:26.393754 <6>[ 2.889259] hub 2-1:1.0: 3 ports detected
10671 14:45:26.402704 <6>[ 2.897360] hub 2-1:1.0: USB hub found
10672 14:45:26.406011 <6>[ 2.901806] hub 2-1:1.0: 3 ports detected
10673 14:45:26.579382 <6>[ 3.071098] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10674 14:45:26.712429 <6>[ 3.206858] hub 1-1.4:1.0: USB hub found
10675 14:45:26.715350 <6>[ 3.211519] hub 1-1.4:1.0: 2 ports detected
10676 14:45:26.724970 <6>[ 3.219838] hub 1-1.4:1.0: USB hub found
10677 14:45:26.728668 <6>[ 3.224444] hub 1-1.4:1.0: 2 ports detected
10678 14:45:26.791326 <6>[ 3.283301] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10679 14:45:26.900124 <6>[ 3.391736] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10680 14:45:26.936077 <4>[ 3.427053] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10681 14:45:26.945305 <4>[ 3.436150] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10682 14:45:26.990137 <6>[ 3.484590] r8152 2-1.3:1.0 eth0: v1.12.13
10683 14:45:27.035619 <6>[ 3.527098] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10684 14:45:27.227910 <6>[ 3.718939] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10685 14:45:28.583519 <6>[ 5.078147] r8152 2-1.3:1.0 eth0: carrier on
10686 14:45:30.743156 <5>[ 5.102893] Sending DHCP requests .., OK
10687 14:45:30.749826 <6>[ 7.243228] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10688 14:45:30.753195 <6>[ 7.251510] IP-Config: Complete:
10689 14:45:30.766431 <6>[ 7.254994] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10690 14:45:30.772948 <6>[ 7.265691] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10691 14:45:30.779985 <6>[ 7.274305] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10692 14:45:30.786209 <6>[ 7.274312] nameserver0=192.168.201.1
10693 14:45:30.789729 <6>[ 7.286386] clk: Disabling unused clocks
10694 14:45:30.792926 <6>[ 7.291535] ALSA device list:
10695 14:45:30.796263 <6>[ 7.294837] No soundcards found.
10696 14:45:30.806902 <6>[ 7.302151] Freeing unused kernel memory: 8512K
10697 14:45:30.809754 <6>[ 7.307118] Run /init as init process
10698 14:45:30.820794 Loading, please wait...
10699 14:45:30.846650 Starting systemd-udevd version 252.22-1~deb12u1
10700 14:45:31.131787 <6>[ 7.624025] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10701 14:45:31.145273 <6>[ 7.637582] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10702 14:45:31.152027 <6>[ 7.645302] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10703 14:45:31.158674 <6>[ 7.650438] remoteproc remoteproc0: scp is available
10704 14:45:31.168502 <6>[ 7.654275] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10705 14:45:31.171862 <6>[ 7.659719] remoteproc remoteproc0: powering up scp
10706 14:45:31.181753 <3>[ 7.669180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 14:45:31.188237 <4>[ 7.670497] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10708 14:45:31.194925 <4>[ 7.670615] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10709 14:45:31.204835 <6>[ 7.673178] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10710 14:45:31.208410 <6>[ 7.673197] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10711 14:45:31.218135 <3>[ 7.681426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 14:45:31.224939 <3>[ 7.718453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 14:45:31.239062 <3>[ 7.731275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 14:45:31.242528 <6>[ 7.734088] mc: Linux media interface: v0.10
10715 14:45:31.252541 <3>[ 7.739437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 14:45:31.259020 <3>[ 7.752037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 14:45:31.269000 <3>[ 7.760123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 14:45:31.275992 <3>[ 7.768228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 14:45:31.282463 <6>[ 7.771396] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10720 14:45:31.292376 <3>[ 7.783293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 14:45:31.302319 <6>[ 7.789357] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10722 14:45:31.308845 <3>[ 7.793615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 14:45:31.318862 <4>[ 7.796907] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10724 14:45:31.321976 <4>[ 7.796907] Fallback method does not support PEC.
10725 14:45:31.328944 <6>[ 7.802701] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10726 14:45:31.338647 <3>[ 7.809509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 14:45:31.345413 <3>[ 7.809516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 14:45:31.355344 <3>[ 7.810083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 14:45:31.358630 <6>[ 7.810334] videodev: Linux video capture interface: v2.00
10730 14:45:31.364957 <6>[ 7.814451] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10731 14:45:31.372267 <6>[ 7.823394] pci_bus 0000:00: root bus resource [bus 00-ff]
10732 14:45:31.382290 <6>[ 7.830098] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10733 14:45:31.388845 <3>[ 7.830802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 14:45:31.398817 <3>[ 7.830813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 14:45:31.405087 <3>[ 7.830818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 14:45:31.415747 <3>[ 7.830821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 14:45:31.421915 <3>[ 7.830885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 14:45:31.428594 <6>[ 7.838168] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10739 14:45:31.438502 <6>[ 7.843197] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10740 14:45:31.448648 <6>[ 7.843674] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10741 14:45:31.455142 <6>[ 7.846650] remoteproc remoteproc0: remote processor scp is now up
10742 14:45:31.464902 <6>[ 7.854356] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10743 14:45:31.471380 <6>[ 7.864778] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10744 14:45:31.478122 <6>[ 7.867658] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10745 14:45:31.487879 <6>[ 7.867715] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 14:45:31.491387 <6>[ 7.867953] pci 0000:00:00.0: supports D1 D2
10747 14:45:31.494551 <6>[ 7.883160] Bluetooth: Core ver 2.22
10748 14:45:31.501304 <6>[ 7.890210] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 14:45:31.507755 <6>[ 7.890845] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10750 14:45:31.520964 <6>[ 7.892105] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10751 14:45:31.527591 <6>[ 7.892244] usbcore: registered new interface driver uvcvideo
10752 14:45:31.534377 <6>[ 7.898382] NET: Registered PF_BLUETOOTH protocol family
10753 14:45:31.540895 <6>[ 7.906445] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10754 14:45:31.551004 <6>[ 7.907477] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10755 14:45:31.554216 <6>[ 7.907567] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10756 14:45:31.564029 <6>[ 7.907594] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10757 14:45:31.570939 <6>[ 7.907611] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10758 14:45:31.577180 <6>[ 7.907626] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10759 14:45:31.584020 <6>[ 7.907740] pci 0000:01:00.0: supports D1 D2
10760 14:45:31.590521 <6>[ 7.907743] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10761 14:45:31.597127 <6>[ 7.914456] Bluetooth: HCI device and connection manager initialized
10762 14:45:31.603906 <6>[ 7.922878] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10763 14:45:31.607598 <6>[ 7.929787] Bluetooth: HCI socket layer initialized
10764 14:45:31.617081 <6>[ 7.939779] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10765 14:45:31.620453 <6>[ 7.948816] Bluetooth: L2CAP socket layer initialized
10766 14:45:31.626949 <6>[ 7.949379] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10767 14:45:31.637207 <6>[ 7.955240] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10768 14:45:31.640278 <6>[ 7.965151] Bluetooth: SCO socket layer initialized
10769 14:45:31.650386 <6>[ 7.973396] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10770 14:45:31.653850 <6>[ 8.033795] usbcore: registered new interface driver btusb
10771 14:45:31.663647 <4>[ 8.034445] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10772 14:45:31.670929 <3>[ 8.034460] Bluetooth: hci0: Failed to load firmware file (-2)
10773 14:45:31.676999 <3>[ 8.034466] Bluetooth: hci0: Failed to set up firmware (-2)
10774 14:45:31.686841 <4>[ 8.034472] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10775 14:45:31.696727 <6>[ 8.041586] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10776 14:45:31.703391 <6>[ 8.195995] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10777 14:45:31.710097 <6>[ 8.203997] pci 0000:00:00.0: PCI bridge to [bus 01]
10778 14:45:31.716531 <6>[ 8.209214] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10779 14:45:31.723312 <6>[ 8.217351] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10780 14:45:31.729841 <6>[ 8.224183] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10781 14:45:31.736456 <6>[ 8.230606] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10782 14:45:31.757050 <5>[ 8.249535] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 14:45:31.781778 <5>[ 8.274218] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10784 14:45:31.788492 <5>[ 8.282251] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10785 14:45:31.798851 <4>[ 8.290843] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10786 14:45:31.805392 <6>[ 8.299753] cfg80211: failed to load regulatory.db
10787 14:45:31.859187 <6>[ 8.351714] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10788 14:45:31.865881 <6>[ 8.359268] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10789 14:45:31.891268 <6>[ 8.386287] mt7921e 0000:01:00.0: ASIC revision: 79610010
10790 14:45:31.995137 <6>[ 8.487554] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10791 14:45:31.998512 <6>[ 8.487554]
10792 14:45:32.008350 Begin: Loading essential drivers ... done.
10793 14:45:32.011763 Begin: Running /scripts/init-premount ... done.
10794 14:45:32.018426 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10795 14:45:32.028050 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10796 14:45:32.031501 Device /sys/class/net/eth0 found
10797 14:45:32.031598 done.
10798 14:45:32.055212 Begin: Waiting up to 180 secs for any network device to become available ... done.
10799 14:45:32.123580 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10800 14:45:32.130064 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10801 14:45:32.136558 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10802 14:45:32.143601 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10803 14:45:32.150422 host : mt8192-asurada-spherion-r0-cbg-1
10804 14:45:32.156740 domain : lava-rack
10805 14:45:32.159899 rootserver: 192.168.201.1 rootpath:
10806 14:45:32.159985 filename :
10807 14:45:32.263242 <6>[ 8.755758] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10808 14:45:32.273855 done.
10809 14:45:32.280701 Begin: Running /scripts/nfs-bottom ... done.
10810 14:45:32.293424 Begin: Running /scripts/init-bottom ... done.
10811 14:45:33.599545 <6>[ 10.095290] NET: Registered PF_INET6 protocol family
10812 14:45:33.606830 <6>[ 10.102650] Segment Routing with IPv6
10813 14:45:33.610021 <6>[ 10.106641] In-situ OAM (IOAM) with IPv6
10814 14:45:33.774884 <30>[ 10.244199] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10815 14:45:33.781492 <30>[ 10.277317] systemd[1]: Detected architecture arm64.
10816 14:45:33.788715
10817 14:45:33.792225 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10818 14:45:33.792311
10819 14:45:33.816382 <30>[ 10.312000] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10820 14:45:34.765917 <30>[ 11.258681] systemd[1]: Queued start job for default target graphical.target.
10821 14:45:34.803739 <30>[ 11.296113] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10822 14:45:34.810444 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10823 14:45:34.831992 <30>[ 11.324862] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10824 14:45:34.842210 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10825 14:45:34.860524 <30>[ 11.352858] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10826 14:45:34.869964 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10827 14:45:34.887710 <30>[ 11.380402] systemd[1]: Created slice user.slice - User and Session Slice.
10828 14:45:34.894595 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10829 14:45:34.918915 <30>[ 11.407955] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10830 14:45:34.928498 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10831 14:45:34.945652 <30>[ 11.435317] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10832 14:45:34.952118 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10833 14:45:34.980767 <30>[ 11.463701] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10834 14:45:34.990792 <30>[ 11.483597] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10835 14:45:34.997672 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10836 14:45:35.014392 <30>[ 11.507102] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10837 14:45:35.021211 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10838 14:45:35.038480 <30>[ 11.531115] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10839 14:45:35.048167 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10840 14:45:35.063489 <30>[ 11.559196] systemd[1]: Reached target paths.target - Path Units.
10841 14:45:35.073636 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10842 14:45:35.090810 <30>[ 11.583521] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10843 14:45:35.097510 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10844 14:45:35.111161 <30>[ 11.606998] systemd[1]: Reached target slices.target - Slice Units.
10845 14:45:35.120899 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10846 14:45:35.134812 <30>[ 11.630972] systemd[1]: Reached target swap.target - Swaps.
10847 14:45:35.141558 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10848 14:45:35.158258 <30>[ 11.651146] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10849 14:45:35.168471 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10850 14:45:35.187358 <30>[ 11.680070] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10851 14:45:35.197134 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10852 14:45:35.216595 <30>[ 11.709372] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10853 14:45:35.226629 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10854 14:45:35.243651 <30>[ 11.736466] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10855 14:45:35.253732 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10856 14:45:35.271164 <30>[ 11.763706] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10857 14:45:35.277425 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10858 14:45:35.295747 <30>[ 11.788521] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10859 14:45:35.305571 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10860 14:45:35.325597 <30>[ 11.818203] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10861 14:45:35.335385 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10862 14:45:35.350766 <30>[ 11.843561] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10863 14:45:35.360488 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10864 14:45:35.402419 <30>[ 11.895153] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10865 14:45:35.409248 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10866 14:45:35.430737 <30>[ 11.923282] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10867 14:45:35.437648 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10868 14:45:35.482693 <30>[ 11.975435] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10869 14:45:35.489446 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10870 14:45:35.517410 <30>[ 12.003758] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10871 14:45:35.532467 <30>[ 12.025086] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10872 14:45:35.542413 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10873 14:45:35.563280 <30>[ 12.056080] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10874 14:45:35.569825 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10875 14:45:35.622806 <30>[ 12.115495] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10876 14:45:35.629374 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10877 14:45:35.656764 <30>[ 12.149326] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10878 14:45:35.666407 Startin<6>[ 12.158869] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10879 14:45:35.673035 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10880 14:45:35.695864 <30>[ 12.188823] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10881 14:45:35.702637 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10882 14:45:35.728165 <30>[ 12.221162] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10883 14:45:35.735023 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10884 14:45:35.759757 <30>[ 12.252639] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10885 14:45:35.766527 Startin<6>[ 12.261496] fuse: init (API version 7.37)
10886 14:45:35.773226 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10887 14:45:35.826823 <30>[ 12.319648] systemd[1]: Starting systemd-journald.service - Journal Service...
10888 14:45:35.833361 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10889 14:45:35.856541 <30>[ 12.349630] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10890 14:45:35.863067 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10891 14:45:35.890881 <30>[ 12.380264] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10892 14:45:35.897131 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10893 14:45:35.919796 <30>[ 12.412456] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10894 14:45:35.929324 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10895 14:45:35.983173 <30>[ 12.475840] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10896 14:45:35.989673 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10897 14:45:36.014250 <30>[ 12.507123] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10898 14:45:36.021025 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10899 14:45:36.038686 <30>[ 12.531484] systemd[1]: Started systemd-journald.service - Journal Service.
10900 14:45:36.045300 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10901 14:45:36.066204 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10902 14:45:36.082877 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10903 14:45:36.103443 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10904 14:45:36.125203 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10905 14:45:36.144955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10906 14:45:36.165437 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10907 14:45:36.183797 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10908 14:45:36.204377 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10909 14:45:36.224819 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10910 14:45:36.243992 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10911 14:45:36.264254 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10912 14:45:36.284064 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10913 14:45:36.304980 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10914 14:45:36.355275 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10915 14:45:36.379703 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10916 14:45:36.406711 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10917 14:45:36.428580 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10918 14:45:36.454295 <46>[ 12.947224] systemd-journald[300]: Received client request to flush runtime journal.
10919 14:45:36.461075 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10920 14:45:36.492762 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10921 14:45:36.783680 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10922 14:45:36.803083 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10923 14:45:36.822918 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10924 14:45:36.839304 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10925 14:45:37.232189 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10926 14:45:37.583418 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10927 14:45:37.631422 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10928 14:45:37.882543 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10929 14:45:37.959385 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10930 14:45:37.978684 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10931 14:45:37.998325 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10932 14:45:38.051460 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10933 14:45:38.077739 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10934 14:45:38.266977 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10935 14:45:38.337742 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10936 14:45:38.386458 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10937 14:45:38.426056 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10938 14:45:38.607131 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10939 14:45:38.640001 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10940 14:45:38.718982 <6>[ 15.215335] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10941 14:45:38.787767 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10942 14:45:38.806816 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10943 14:45:38.873237 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10944 14:45:38.918501 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10945 14:45:38.943959 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10946 14:45:38.966272 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10947 14:45:38.986983 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10948 14:45:39.006832 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10949 14:45:39.037594 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10950 14:45:39.062425 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10951 14:45:39.078148 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10952 14:45:39.094200 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10953 14:45:39.117593 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10954 14:45:39.140509 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10955 14:45:39.162214 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10956 14:45:39.181094 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10957 14:45:39.201330 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10958 14:45:39.218171 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10959 14:45:39.235862 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10960 14:45:39.253782 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10961 14:45:39.270718 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10962 14:45:39.323976 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10963 14:45:39.354430 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10964 14:45:39.463866 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10965 14:45:39.490266 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10966 14:45:39.511718 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10967 14:45:39.572194 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10968 14:45:39.593455 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10969 14:45:39.615942 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10970 14:45:39.683265 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10971 14:45:39.702584 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10972 14:45:39.722317 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10973 14:45:39.739986 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10974 14:45:39.905731 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10975 14:45:39.928196 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10976 14:45:39.948988 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10977 14:45:40.015967 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10978 14:45:40.080036 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10979 14:45:40.147857
10980 14:45:40.151050 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10981 14:45:40.151143
10982 14:45:40.154194 debian-bookworm-arm64 login: root (automatic login)
10983 14:45:40.154278
10984 14:45:40.396058 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
10985 14:45:40.396213
10986 14:45:40.402539 The programs included with the Debian GNU/Linux system are free software;
10987 14:45:40.409158 the exact distribution terms for each program are described in the
10988 14:45:40.412310 individual files in /usr/share/doc/*/copyright.
10989 14:45:40.412400
10990 14:45:40.419104 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10991 14:45:40.422078 permitted by applicable law.
10992 14:45:40.499421 Matched prompt #10: / #
10994 14:45:40.499879 Setting prompt string to ['/ #']
10995 14:45:40.500048 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10997 14:45:40.500380 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10998 14:45:40.500514 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
10999 14:45:40.500673 Setting prompt string to ['/ #']
11000 14:45:40.500764 Forcing a shell prompt, looking for ['/ #']
11002 14:45:40.551054 / #
11003 14:45:40.551224 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11004 14:45:40.551313 Waiting using forced prompt support (timeout 00:02:30)
11005 14:45:40.556286
11006 14:45:40.556617 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11007 14:45:40.556732 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
11009 14:45:40.657169 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih'
11010 14:45:40.662406 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166994/extract-nfsrootfs-lsvjnvih'
11012 14:45:40.763008 / # export NFS_SERVER_IP='192.168.201.1'
11013 14:45:40.767924 export NFS_SERVER_IP='192.168.201.1'
11014 14:45:40.768230 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11015 14:45:40.768329 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
11016 14:45:40.768417 end: 2 depthcharge-action (duration 00:01:15) [common]
11017 14:45:40.768509 start: 3 lava-test-retry (timeout 00:30:00) [common]
11018 14:45:40.768633 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11019 14:45:40.768711 Using namespace: common
11021 14:45:40.869011 / # #
11022 14:45:40.869182 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11023 14:45:40.874758 #
11024 14:45:40.875029 Using /lava-14166994
11026 14:45:40.975334 / # export SHELL=/bin/sh
11027 14:45:40.980501 export SHELL=/bin/sh
11029 14:45:41.081033 / # . /lava-14166994/environment
11030 14:45:41.086292 . /lava-14166994/environment
11032 14:45:41.191902 / # /lava-14166994/bin/lava-test-runner /lava-14166994/0
11033 14:45:41.192107 Test shell timeout: 10s (minimum of the action and connection timeout)
11034 14:45:41.197321 /lava-14166994/bin/lava-test-runner /lava-14166994/0
11035 14:45:41.384135 + export TESTRUN_ID=0_lc-compliance
11036 14:45:41.390428 + cd /lava-14166994/0/tests/0_lc-compliance
11037 14:45:41.390559 + cat uuid
11038 14:45:41.394473 + UUID=14166994_1.6.2.3.1
11039 14:45:41.394598 + set +x
11040 14:45:41.400710 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14166994_1.6.2.3.1>
11041 14:45:41.401012 Received signal: <STARTRUN> 0_lc-compliance 14166994_1.6.2.3.1
11042 14:45:41.401132 Starting test lava.0_lc-compliance (14166994_1.6.2.3.1)
11043 14:45:41.401266 Skipping test definition patterns.
11044 14:45:41.403993 + /usr/bin/lc-compliance-parser.sh
11045 14:45:43.008202 [0:00:19.383668462] [407] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11046 14:45:43.011575 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11047 14:45:43.025527 [0:00:19.401009231] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11048 14:45:43.069690 [==========] Running 120 tests from 1 test suite.
11049 14:45:43.087932 [0:00:19.463551847] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11050 14:45:43.118449 [----------] Global test environment set-up.
11051 14:45:43.140436 [0:00:19.515858000] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11052 14:45:43.172416 [----------] 120 tests from CaptureTests/SingleStream
11053 14:45:43.192896 [0:00:19.568479462] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11054 14:45:43.224482 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11055 14:45:43.269213 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11056 14:45:43.269499 Received signal: <TESTSET> START CaptureTests/SingleStream
11057 14:45:43.269581 Starting test_set CaptureTests/SingleStream
11058 14:45:43.272411 Camera needs 4 requests, can't test only 1
11059 14:45:43.316463 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11060 14:45:43.365373
11061 14:45:43.427992 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (62 ms)
11062 14:45:43.500463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11063 14:45:43.500802 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11065 14:45:43.512658 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11066 14:45:43.558780 Camera needs 4 requests, can't test only 2
11067 14:45:43.619270 [0:00:19.995035616] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11068 14:45:43.622820 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11069 14:45:43.679679
11070 14:45:43.744370 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
11071 14:45:43.817411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11072 14:45:43.817701 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11074 14:45:43.828933 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11075 14:45:43.870966 Camera needs 4 requests, can't test only 3
11076 14:45:43.944743 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11077 14:45:44.015050
11078 14:45:44.088501 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (51 ms)
11079 14:45:44.155696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11080 14:45:44.156014 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11082 14:45:44.167460 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11083 14:45:44.209818 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (427 ms)
11084 14:45:44.280907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11085 14:45:44.281246 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11087 14:45:44.295369 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11088 14:45:44.310113 [0:00:20.685413693] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11089 14:45:44.345926 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (690 ms)
11090 14:45:44.414672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11091 14:45:44.415021 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11093 14:45:44.424191 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11094 14:45:45.556128 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1253 ms)
11095 14:45:45.565862 [0:00:21.940602462] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11096 14:45:45.652247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11097 14:45:45.652606 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11099 14:45:45.666743 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11100 14:45:47.373738 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1817 ms)
11101 14:45:47.383963 [0:00:23.758734770] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11102 14:45:47.449993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11103 14:45:47.450348 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11105 14:45:47.460977 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11106 14:45:50.103107 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2728 ms)
11107 14:45:50.112273 [0:00:26.487847385] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11108 14:45:50.182757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11109 14:45:50.183476 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11111 14:45:50.195881 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11112 14:45:54.300922 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
11113 14:45:54.310437 [0:00:30.686428078] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11114 14:45:54.380907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11115 14:45:54.381661 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11117 14:45:54.394240 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11118 14:46:00.878514 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6578 ms)
11119 14:46:00.888301 [0:00:37.264813463] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11120 14:46:00.942910 [0:00:37.319955540] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 14:46:00.980735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11122 14:46:00.980995 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11124 14:46:00.999108 [0:00:37.376697848] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11125 14:46:01.002337 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11126 14:46:01.040905 Camera needs 4 requests, can't test only 1
11127 14:46:01.055470 [0:00:37.433029078] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11128 14:46:01.105341 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11129 14:46:01.164264
11130 14:46:01.235274 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11131 14:46:01.318671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11132 14:46:01.319429 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11134 14:46:01.334624 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11135 14:46:01.389773 Camera needs 4 requests, can't test only 2
11136 14:46:01.466934 ../src/apps/lc-compliance/simple<6>[ 37.967065] vpu: disabling
11137 14:46:01.473431 _capture.cpp:91:<6>[ 37.971575] vproc2: disabling
11138 14:46:01.474021 Skipped
11139 14:46:01.476745 <6>[ 37.976328] vproc1: disabling
11140 14:46:01.480322 <6>[ 37.980300] vaud18: disabling
11141 14:46:01.483726 <6>[ 37.983857] vsram_others: disabling
11142 14:46:01.486638 <6>[ 37.987859] va09: disabling
11143 14:46:01.490233 <6>[ 37.991176] vsram_md: disabling
11144 14:46:01.493147 <6>[ 37.994752] Vgpu: disabling
11145 14:46:01.552026
11146 14:46:01.609397 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11147 14:46:01.671193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11148 14:46:01.671472 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11150 14:46:01.681699 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11151 14:46:01.722961 Camera needs 4 requests, can't test only 3
11152 14:46:01.752820 [0:00:38.130420155] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 14:46:01.783790 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11154 14:46:01.841630
11155 14:46:01.905270 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11156 14:46:01.975997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11157 14:46:01.976304 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11159 14:46:01.989331 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11160 14:46:02.034630 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (697 ms)
11161 14:46:02.107152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11162 14:46:02.107976 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11164 14:46:02.124317 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11165 14:46:02.656797 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (911 ms)
11166 14:46:02.670264 [0:00:39.043256155] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11167 14:46:02.746400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11168 14:46:02.746732 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11170 14:46:02.761724 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11171 14:46:03.913778 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1257 ms)
11172 14:46:03.927176 [0:00:40.300538155] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11173 14:46:04.007469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11174 14:46:04.007797 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11176 14:46:04.021972 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11177 14:46:05.732377 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1818 ms)
11178 14:46:05.745489 [0:00:42.118574694] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 14:46:05.816388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11180 14:46:05.816682 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11182 14:46:05.829917 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11183 14:46:08.459487 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2727 ms)
11184 14:46:08.472902 [0:00:44.846815694] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11185 14:46:08.554090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11186 14:46:08.554820 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11188 14:46:08.569158 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11189 14:46:12.657763 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4198 ms)
11190 14:46:12.670863 [0:00:49.045238541] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11191 14:46:12.750092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11192 14:46:12.750377 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11194 14:46:12.763293 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11195 14:46:19.235857 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6578 ms)
11196 14:46:19.248262 [0:00:55.624039003] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11197 14:46:19.300290 [0:00:55.680171772] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 14:46:19.324713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11199 14:46:19.324978 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11201 14:46:19.339066 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11202 14:46:19.355070 [0:00:55.734840079] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11203 14:46:19.383332 Camera needs 4 requests, can't test only 1
11204 14:46:19.409095 [0:00:55.788812233] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11205 14:46:19.443342 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11206 14:46:19.489575
11207 14:46:19.544919 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11208 14:46:19.619472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11209 14:46:19.619777 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11211 14:46:19.633336 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11212 14:46:19.679009 Camera needs 4 requests, can't test only 2
11213 14:46:19.744308 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11214 14:46:19.805301
11215 14:46:19.873894 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11216 14:46:19.953279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11217 14:46:19.953568 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11219 14:46:19.967084 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11220 14:46:20.010338 Camera needs 4 requests, can't test only 3
11221 14:46:20.067922 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11222 14:46:20.104287 [0:00:56.484060772] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 14:46:20.129371
11224 14:46:20.195139 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11225 14:46:20.259767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11226 14:46:20.260044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11228 14:46:20.273078 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11229 14:46:20.313829 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11230 14:46:20.385012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11231 14:46:20.385286 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11233 14:46:20.397976 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11234 14:46:21.002518 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (907 ms)
11235 14:46:21.016078 [0:00:57.391603541] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11236 14:46:21.076711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11237 14:46:21.076974 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11239 14:46:21.090339 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11240 14:46:22.263909 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11241 14:46:22.273779 [0:00:58.649293003] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11242 14:46:22.355535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11243 14:46:22.356734 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11245 14:46:22.369767 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11246 14:46:24.078816 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1818 ms)
11247 14:46:24.092222 [0:01:00.467935157] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11248 14:46:24.163289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11249 14:46:24.163571 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11251 14:46:24.177790 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11252 14:46:26.809974 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2730 ms)
11253 14:46:26.822896 [0:01:03.198222003] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11254 14:46:26.904102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11255 14:46:26.904828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11257 14:46:26.920458 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11258 14:46:31.004525 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4195 ms)
11259 14:46:31.017879 [0:01:07.394670080] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 14:46:31.082355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11261 14:46:31.082680 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11263 14:46:31.094817 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11264 14:46:37.582486 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6578 ms)
11265 14:46:37.595768 [0:01:13.973365234] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 14:46:37.648888 [0:01:14.030465234] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 14:46:37.658557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11268 14:46:37.658827 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11270 14:46:37.671502 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11271 14:46:37.702705 [0:01:14.084521234] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11272 14:46:37.718198 Camera needs 4 requests, can't test only 1
11273 14:46:37.758700 [0:01:14.140667850] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 14:46:37.787050 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11275 14:46:37.846927
11276 14:46:37.913433 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11277 14:46:37.984900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11278 14:46:37.985191 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11280 14:46:37.997737 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11281 14:46:38.040197 Camera needs 4 requests, can't test only 2
11282 14:46:38.103868 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11283 14:46:38.162064
11284 14:46:38.223020 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11285 14:46:38.291594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11286 14:46:38.291900 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11288 14:46:38.304782 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11289 14:46:38.346636 Camera needs 4 requests, can't test only 3
11290 14:46:38.409933 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11291 14:46:38.453408 [0:01:14.835284465] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 14:46:38.464821
11293 14:46:38.526651 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11294 14:46:38.584321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11295 14:46:38.584631 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11297 14:46:38.595200 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11298 14:46:38.638483 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (695 ms)
11299 14:46:38.708321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11300 14:46:38.708632 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11302 14:46:38.720486 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11303 14:46:39.350138 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (904 ms)
11304 14:46:39.363222 [0:01:15.741279696] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11305 14:46:39.427867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11306 14:46:39.428184 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11308 14:46:39.441953 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11309 14:46:40.607992 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1257 ms)
11310 14:46:40.620979 [0:01:16.999251158] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11311 14:46:40.694472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11312 14:46:40.694858 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11314 14:46:40.708596 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11315 14:46:42.426154 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1818 ms)
11316 14:46:42.439452 [0:01:18.817722312] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11317 14:46:42.501524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11318 14:46:42.501834 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11320 14:46:42.511521 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11321 14:46:45.154929 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11322 14:46:45.167636 [0:01:21.546586850] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11323 14:46:45.228205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11324 14:46:45.228516 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11326 14:46:45.241672 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11327 14:46:49.352237 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11328 14:46:49.365320 [0:01:25.744639851] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11329 14:46:49.432421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11330 14:46:49.432776 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11332 14:46:49.445447 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11333 14:46:55.930700 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6579 ms)
11334 14:46:55.943839 [0:01:32.323920236] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11335 14:46:55.996962 [0:01:32.380594543] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 14:46:56.010633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11337 14:46:56.010957 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11339 14:46:56.021355 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11340 14:46:56.050278 [0:01:32.434424697] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11341 14:46:56.059111 Camera needs 4 requests, can't test only 1
11342 14:46:56.105828 [0:01:32.489873159] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 14:46:56.118043 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11344 14:46:56.167128
11345 14:46:56.231898 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11346 14:46:56.298812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11347 14:46:56.299139 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11349 14:46:56.309717 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11350 14:46:56.344026 Camera needs 4 requests, can't test only 2
11351 14:46:56.398775 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11352 14:46:56.446950
11353 14:46:56.505550 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11354 14:46:56.572446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11355 14:46:56.572812 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11357 14:46:56.583800 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11358 14:46:56.618321 Camera needs 4 requests, can't test only 3
11359 14:46:56.667465 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11360 14:46:56.712469
11361 14:46:56.760883 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11362 14:46:56.825009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11363 14:46:56.825381 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11365 14:46:56.836184 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11366 14:46:58.178674 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2081 ms)
11367 14:46:58.191880 [0:01:34.572223543] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11368 14:46:58.242808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11369 14:46:58.243154 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11371 14:46:58.252710 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11372 14:47:00.896402 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11373 14:47:00.909660 [0:01:37.292515390] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11374 14:47:00.964703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11375 14:47:00.965031 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11377 14:47:00.975384 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11378 14:47:04.660363 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3764 ms)
11379 14:47:04.673340 [0:01:41.056969082] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11380 14:47:04.735518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11381 14:47:04.735846 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11383 14:47:04.746979 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11384 14:47:10.105244 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5444 ms)
11385 14:47:10.118195 [0:01:46.501713544] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11386 14:47:10.203187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11387 14:47:10.203949 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11389 14:47:10.219639 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11390 14:47:18.281372 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8177 ms)
11391 14:47:18.294751 [0:01:54.679123314] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11392 14:47:18.385647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11393 14:47:18.386413 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11395 14:47:18.402214 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11396 14:47:30.865102 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12585 ms)
11397 14:47:30.878218 [0:02:07.264787315] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11398 14:47:30.941244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11399 14:47:30.941516 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11401 14:47:30.951991 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11402 14:47:50.589627 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19724 ms)
11403 14:47:50.603129 [0:02:26.992546854] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11404 14:47:50.658918 [0:02:27.049048777] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 14:47:50.665393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11406 14:47:50.665752 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11408 14:47:50.674344 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11409 14:47:50.713597 [0:02:27.104124085] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11410 14:47:50.716854 Camera needs 4 requests, can't test only 1
11411 14:47:50.768821 [0:02:27.159245162] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 14:47:50.771798 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11413 14:47:50.817181
11414 14:47:50.882113 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11415 14:47:50.949081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11416 14:47:50.949513 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11418 14:47:50.958173 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11419 14:47:50.995298 Camera needs 4 requests, can't test only 2
11420 14:47:51.046235 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11421 14:47:51.105799
11422 14:47:51.174520 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11423 14:47:51.242719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11424 14:47:51.243064 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11426 14:47:51.251376 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11427 14:47:51.292830 Camera needs 4 requests, can't test only 3
11428 14:47:51.346570 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11429 14:47:51.410113
11430 14:47:51.481265 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (55 ms)
11431 14:47:51.558718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11432 14:47:51.559052 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11434 14:47:51.567517 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11435 14:47:52.844014 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2079 ms)
11436 14:47:52.853832 [0:02:29.240095008] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11437 14:47:52.939594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11438 14:47:52.939903 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11440 14:47:52.948340 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11441 14:47:55.557129 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2713 ms)
11442 14:47:55.567038 [0:02:31.955592239] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11443 14:47:55.644194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11444 14:47:55.644478 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11446 14:47:55.656208 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11447 14:47:59.319857 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3763 ms)
11448 14:47:59.329816 [0:02:35.718945239] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 14:47:59.406992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11450 14:47:59.407743 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11452 14:47:59.420685 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11453 14:48:04.763308 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5443 ms)
11454 14:48:04.773144 [0:02:41.162708855] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11455 14:48:04.855347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11456 14:48:04.856087 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11458 14:48:04.866148 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11459 14:48:12.938780 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8176 ms)
11460 14:48:12.948335 [0:02:49.339901471] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11461 14:48:13.026266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11462 14:48:13.027092 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11464 14:48:13.037995 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11465 14:48:25.521986 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12585 ms)
11466 14:48:25.531539 [0:03:01.925409318] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11467 14:48:25.597368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11468 14:48:25.597664 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11470 14:48:25.604937 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11471 14:48:45.248321 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19725 ms)
11472 14:48:45.258190 [0:03:21.653199934] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11473 14:48:45.312641 [0:03:21.709321088] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 14:48:45.341817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11475 14:48:45.342651 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11477 14:48:45.353914 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11478 14:48:45.368569 [0:03:21.765073934] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11479 14:48:45.403421 Camera needs 4 requests, can't test only 1
11480 14:48:45.424660 [0:03:21.821085242] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 14:48:45.472975 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11482 14:48:45.536444
11483 14:48:45.610359 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11484 14:48:45.685811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11485 14:48:45.686091 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11487 14:48:45.696542 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11488 14:48:45.744824 Camera needs 4 requests, can't test only 2
11489 14:48:45.811366 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11490 14:48:45.872415
11491 14:48:45.948728 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)
11492 14:48:46.038921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11493 14:48:46.039723 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11495 14:48:46.050293 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11496 14:48:46.104795 Camera needs 4 requests, can't test only 3
11497 14:48:46.178632 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11498 14:48:46.250616
11499 14:48:46.336428 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11500 14:48:46.420056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11501 14:48:46.420782 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11503 14:48:46.432965 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11504 14:48:47.499191 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2081 ms)
11505 14:48:47.509595 [0:03:23.902158858] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11506 14:48:47.575832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11507 14:48:47.576114 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11509 14:48:47.583747 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11510 14:48:50.212809 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11511 14:48:50.222244 [0:03:26.617503088] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11512 14:48:50.297565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11513 14:48:50.297889 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11515 14:48:50.306997 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11516 14:48:53.975960 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3763 ms)
11517 14:48:53.985654 [0:03:30.381995396] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11518 14:48:54.060332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11519 14:48:54.060608 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11521 14:48:54.071572 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11522 14:48:59.419841 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5444 ms)
11523 14:48:59.430268 [0:03:35.826140243] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 14:48:59.517387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11525 14:48:59.518160 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11527 14:48:59.528660 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11528 14:49:07.596679 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8177 ms)
11529 14:49:07.606537 [0:03:44.003691474] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11530 14:49:07.688350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11531 14:49:07.689114 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11533 14:49:07.701083 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11534 14:49:20.179566 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12585 ms)
11535 14:49:20.189463 [0:03:56.589843552] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11536 14:49:20.261595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11537 14:49:20.261923 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11539 14:49:20.271574 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11540 14:49:39.904085 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19723 ms)
11541 14:49:39.913570 [0:04:16.315292399] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11542 14:49:39.968387 [0:04:16.371486553] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 14:49:40.005588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11544 14:49:40.006347 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11546 14:49:40.024211 [0:04:16.426959630] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 14:49:40.030382 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11548 14:49:40.075932 Camera needs 4 requests, can't test only 1
11549 14:49:40.085853 [0:04:16.487568784] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 14:49:40.152626 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11551 14:49:40.224326
11552 14:49:40.294623 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11553 14:49:40.378888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11554 14:49:40.379726 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11556 14:49:40.393162 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11557 14:49:40.447861 Camera needs 4 requests, can't test only 2
11558 14:49:40.527240 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11559 14:49:40.602900
11560 14:49:40.680841 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (55 ms)
11561 14:49:40.771978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11562 14:49:40.772901 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11564 14:49:40.790996 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11565 14:49:40.844079 Camera needs 4 requests, can't test only 3
11566 14:49:40.918098 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11567 14:49:40.993972
11568 14:49:41.078080 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11569 14:49:41.167510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11570 14:49:41.168298 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11572 14:49:41.179605 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11573 14:49:42.161108 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2083 ms)
11574 14:49:42.170422 [0:04:18.569600938] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 14:49:42.249578 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11577 14:49:42.252586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11578 14:49:42.261732 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11579 14:49:44.873174 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11580 14:49:44.883279 [0:04:21.284697938] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 14:49:44.950169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11582 14:49:44.950457 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11584 14:49:44.958648 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11585 14:49:48.637560 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3764 ms)
11586 14:49:48.647153 [0:04:25.049670554] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11587 14:49:48.730334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11588 14:49:48.731191 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11590 14:49:48.741718 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11591 14:49:54.081527 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5444 ms)
11592 14:49:54.091558 [0:04:30.494298400] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 14:49:54.172505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11594 14:49:54.173347 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11596 14:49:54.186586 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11597 14:50:02.257703 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8177 ms)
11598 14:50:02.267598 [0:04:38.671762400] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 14:50:02.332946 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11601 14:50:02.335425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11602 14:50:02.345718 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11603 14:50:14.841310 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12585 ms)
11604 14:50:14.851499 [0:04:51.257497940] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 14:50:14.914890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11606 14:50:14.915200 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11608 14:50:14.923855 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11609 14:50:34.566256 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19724 ms)
11610 14:50:34.576017 [0:05:10.983635249] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 14:50:34.650032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11612 14:50:34.650963 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11614 14:50:34.659855 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11615 14:50:34.981209 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11616 14:50:34.994246 [0:05:11.401308018] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 14:50:35.050630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11618 14:50:35.050957 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11620 14:50:35.062413 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11621 14:50:35.470822 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11622 14:50:35.480793 [0:05:11.889582864] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 14:50:35.538966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11624 14:50:35.539266 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11626 14:50:35.549997 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11627 14:50:36.028355 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11628 14:50:36.041479 [0:05:12.447236095] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 14:50:36.093983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11630 14:50:36.094302 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11632 14:50:36.104658 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11633 14:50:36.726450 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (698 ms)
11634 14:50:36.739544 [0:05:13.145506172] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 14:50:36.793536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11636 14:50:36.793801 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11638 14:50:36.804181 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11639 14:50:37.635894 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (908 ms)
11640 14:50:37.648827 [0:05:14.054216633] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 14:50:37.725945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11642 14:50:37.726529 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11644 14:50:37.738672 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11645 14:50:38.893200 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1257 ms)
11646 14:50:38.906046 [0:05:15.312392787] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 14:50:38.967692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11648 14:50:38.967988 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11650 14:50:38.979731 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11651 14:50:40.711361 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1818 ms)
11652 14:50:40.724431 [0:05:17.130883634] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 14:50:40.778781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11654 14:50:40.779071 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11656 14:50:40.787462 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11657 14:50:43.440190 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2728 ms)
11658 14:50:43.453223 [0:05:19.859327711] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 14:50:43.528260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11660 14:50:43.528910 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11662 14:50:43.541757 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11663 14:50:47.637733 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4198 ms)
11664 14:50:47.650936 [0:05:24.057729865] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11665 14:50:47.728478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11666 14:50:47.728814 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11668 14:50:47.739088 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11669 14:50:54.216304 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6579 ms)
11670 14:50:54.229465 [0:05:30.636984634] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11671 14:50:54.307939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11672 14:50:54.308729 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11674 14:50:54.322372 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11675 14:50:54.636863 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11676 14:50:54.647066 [0:05:31.054487096] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11677 14:50:54.731975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11678 14:50:54.732720 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11680 14:50:54.742944 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11681 14:50:55.125014 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (487 ms)
11682 14:50:55.134967 [0:05:31.542424634] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11683 14:50:55.212819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11684 14:50:55.213539 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11686 14:50:55.224437 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11687 14:50:55.683061 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (557 ms)
11688 14:50:55.692946 [0:05:32.100223788] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11689 14:50:55.779654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11690 14:50:55.780474 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11692 14:50:55.789457 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11693 14:50:56.380813 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (698 ms)
11694 14:50:56.390815 [0:05:32.798198019] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11695 14:50:56.474915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11696 14:50:56.475662 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11698 14:50:56.485632 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11699 14:50:57.290256 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (909 ms)
11700 14:50:57.300070 [0:05:33.707865635] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11701 14:50:57.372586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11702 14:50:57.372949 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11704 14:50:57.382413 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11705 14:50:58.548426 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1258 ms)
11706 14:50:58.558338 [0:05:34.966169712] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 14:50:58.634184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11708 14:50:58.634507 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11710 14:50:58.642345 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11711 14:51:00.366889 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1818 ms)
11712 14:51:00.376377 [0:05:36.784758250] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11713 14:51:00.463057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11714 14:51:00.463792 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11716 14:51:00.477051 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11717 14:51:03.096838 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2729 ms)
11718 14:51:03.106471 [0:05:39.514782481] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11719 14:51:03.200539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11720 14:51:03.201422 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11722 14:51:03.211691 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11723 14:51:07.294611 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4198 ms)
11724 14:51:07.304315 [0:05:43.713518404] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11725 14:51:07.391102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11726 14:51:07.391992 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11728 14:51:07.404591 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11729 14:51:13.873474 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6578 ms)
11730 14:51:13.883035 [0:05:50.292660405] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11731 14:51:13.970669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11732 14:51:13.971497 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11734 14:51:13.983877 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11735 14:51:14.291201 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (417 ms)
11736 14:51:14.300596 [0:05:50.710526405] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11737 14:51:14.381298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11738 14:51:14.381707 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11740 14:51:14.390786 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11741 14:51:14.779061 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (488 ms)
11742 14:51:14.788820 [0:05:51.198733251] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11743 14:51:14.871486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11744 14:51:14.871754 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11746 14:51:14.882913 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11747 14:51:15.337781 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (558 ms)
11748 14:51:15.347224 [0:05:51.757341020] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11749 14:51:15.423131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11750 14:51:15.423410 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11752 14:51:15.436447 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11753 14:51:16.033181 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (695 ms)
11754 14:51:16.043001 [0:05:52.452920251] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 14:51:16.128231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11756 14:51:16.128583 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11758 14:51:16.137993 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11759 14:51:16.941221 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (908 ms)
11760 14:51:16.951170 [0:05:53.361146866] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11761 14:51:17.027075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11762 14:51:17.027360 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11764 14:51:17.038706 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11765 14:51:18.199223 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1257 ms)
11766 14:51:18.208977 [0:05:54.619401636] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11767 14:51:18.292996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11768 14:51:18.293783 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11770 14:51:18.305767 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11771 14:51:20.017477 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1818 ms)
11772 14:51:20.026864 [0:05:56.437428251] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11773 14:51:20.107205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11774 14:51:20.107590 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11776 14:51:20.117860 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11777 14:51:22.745694 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2728 ms)
11778 14:51:22.755729 [0:05:59.166463175] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11779 14:51:22.842354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11780 14:51:22.843043 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11782 14:51:22.856184 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11783 14:51:26.944040 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4198 ms)
11784 14:51:26.954137 [0:06:03.365107867] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 14:51:27.039385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11786 14:51:27.040162 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11788 14:51:27.050615 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11789 14:51:33.522147 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6578 ms)
11790 14:51:33.531886 [0:06:09.943845329] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11791 14:51:33.623815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11792 14:51:33.624743 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11794 14:51:33.636112 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11795 14:51:33.939951 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (417 ms)
11796 14:51:33.950146 [0:06:10.361526483] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11797 14:51:34.034970 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11799 14:51:34.038010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11800 14:51:34.051532 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11801 14:51:34.426416 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (486 ms)
11802 14:51:34.436219 [0:06:10.848646868] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11803 14:51:34.520179 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11805 14:51:34.523103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11806 14:51:34.533249 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11807 14:51:34.982651 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (556 ms)
11808 14:51:34.992317 [0:06:11.404579714] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11809 14:51:35.065327 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11811 14:51:35.068324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11812 14:51:35.075938 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11813 14:51:35.678590 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (696 ms)
11814 14:51:35.688720 [0:06:12.100946637] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11815 14:51:35.768116 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11817 14:51:35.771081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11818 14:51:35.780508 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11819 14:51:36.585456 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (906 ms)
11820 14:51:36.595308 [0:06:13.007708329] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11821 14:51:36.671116 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11823 14:51:36.674195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11824 14:51:36.686447 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11825 14:51:37.843105 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1257 ms)
11826 14:51:37.852976 [0:06:14.265679175] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11827 14:51:37.936788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11828 14:51:37.937517 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11830 14:51:37.949424 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11831 14:51:39.661418 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1818 ms)
11832 14:51:39.671216 [0:06:16.084084945] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11833 14:51:39.747177 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11835 14:51:39.750431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11836 14:51:39.761841 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11837 14:51:42.390022 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11838 14:51:42.400009 [0:06:18.812855791] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11839 14:51:42.479652 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11841 14:51:42.482724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11842 14:51:42.491165 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11843 14:51:46.586919 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4197 ms)
11844 14:51:46.596525 [0:06:23.010555945] [407] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11845 14:51:46.666407 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11847 14:51:46.669369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11848 14:51:46.677467 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11849 14:51:53.165605 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6579 ms)
11850 14:51:53.247815 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11852 14:51:53.250861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11853 14:51:53.261557 [----------] 120 tests from CaptureTests/SingleStream (370187 ms total)
11854 14:51:53.329391
11855 14:51:53.408691 [----------] Global test environment tear-down
11856 14:51:53.481607 [==========] 120 tests from 1 test suite ran. (370188 ms total)
11857 14:51:53.560048 <LAVA_SIGNAL_TESTSET STOP>
11858 14:51:53.560353 Received signal: <TESTSET> STOP
11859 14:51:53.560457 Closing test_set CaptureTests/SingleStream
11860 14:51:53.563295 + set +x
11861 14:51:53.566574 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14166994_1.6.2.3.1>
11862 14:51:53.566829 Received signal: <ENDRUN> 0_lc-compliance 14166994_1.6.2.3.1
11863 14:51:53.566920 Ending use of test pattern.
11864 14:51:53.566984 Ending test lava.0_lc-compliance (14166994_1.6.2.3.1), duration 372.17
11866 14:51:53.569533 <LAVA_TEST_RUNNER EXIT>
11867 14:51:53.569786 ok: lava_test_shell seems to have completed
11868 14:51:53.571664 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11869 14:51:53.571854 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11870 14:51:53.571950 end: 3 lava-test-retry (duration 00:06:13) [common]
11871 14:51:53.572045 start: 4 finalize (timeout 00:10:00) [common]
11872 14:51:53.572137 start: 4.1 power-off (timeout 00:00:30) [common]
11873 14:51:53.572296 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11874 14:51:53.794344 >> Command sent successfully.
11875 14:51:53.805089 Returned 0 in 0 seconds
11876 14:51:53.906426 end: 4.1 power-off (duration 00:00:00) [common]
11878 14:51:53.907999 start: 4.2 read-feedback (timeout 00:10:00) [common]
11879 14:51:53.909314 Listened to connection for namespace 'common' for up to 1s
11880 14:51:54.909986 Finalising connection for namespace 'common'
11881 14:51:54.910707 Disconnecting from shell: Finalise
11882 14:51:54.911177 / #
11883 14:51:55.012180 end: 4.2 read-feedback (duration 00:00:01) [common]
11884 14:51:55.012954 end: 4 finalize (duration 00:00:01) [common]
11885 14:51:55.013566 Cleaning after the job
11886 14:51:55.014090 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/ramdisk
11887 14:51:55.018598 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/kernel
11888 14:51:55.029323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/dtb
11889 14:51:55.029496 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/nfsrootfs
11890 14:51:55.068691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166994/tftp-deploy-rqbtyl8_/modules
11891 14:51:55.074248 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14166994
11892 14:51:55.313246 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14166994
11893 14:51:55.313428 Job finished correctly