Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 14:42:18.353968 lava-dispatcher, installed at version: 2024.03
2 14:42:18.354182 start: 0 validate
3 14:42:18.354321 Start time: 2024-06-04 14:42:18.354314+00:00 (UTC)
4 14:42:18.354451 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:42:18.354585 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:42:18.637602 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:42:18.637792 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:42:18.898506 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:42:18.899269 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:43:19.224477 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:19.225226 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:43:19.745128 validate duration: 61.39
14 14:43:19.746469 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:43:19.747062 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:43:19.747613 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:43:19.748268 Not decompressing ramdisk as can be used compressed.
18 14:43:19.748748 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 14:43:19.749144 saving as /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/ramdisk/rootfs.cpio.gz
20 14:43:19.749514 total size: 28105535 (26 MB)
21 14:43:37.180445 progress 0 % (0 MB)
22 14:43:37.191274 progress 5 % (1 MB)
23 14:43:37.198450 progress 10 % (2 MB)
24 14:43:37.205797 progress 15 % (4 MB)
25 14:43:37.212863 progress 20 % (5 MB)
26 14:43:37.219960 progress 25 % (6 MB)
27 14:43:37.227037 progress 30 % (8 MB)
28 14:43:37.234108 progress 35 % (9 MB)
29 14:43:37.241304 progress 40 % (10 MB)
30 14:43:37.248256 progress 45 % (12 MB)
31 14:43:37.255590 progress 50 % (13 MB)
32 14:43:37.262808 progress 55 % (14 MB)
33 14:43:37.269939 progress 60 % (16 MB)
34 14:43:37.277180 progress 65 % (17 MB)
35 14:43:37.284323 progress 70 % (18 MB)
36 14:43:37.291558 progress 75 % (20 MB)
37 14:43:37.298805 progress 80 % (21 MB)
38 14:43:37.306015 progress 85 % (22 MB)
39 14:43:37.312939 progress 90 % (24 MB)
40 14:43:37.319987 progress 95 % (25 MB)
41 14:43:37.327197 progress 100 % (26 MB)
42 14:43:37.327411 26 MB downloaded in 17.58 s (1.52 MB/s)
43 14:43:37.327567 end: 1.1.1 http-download (duration 00:00:18) [common]
45 14:43:37.327808 end: 1.1 download-retry (duration 00:00:18) [common]
46 14:43:37.327899 start: 1.2 download-retry (timeout 00:09:42) [common]
47 14:43:37.327984 start: 1.2.1 http-download (timeout 00:09:42) [common]
48 14:43:37.328123 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:43:37.328195 saving as /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/kernel/Image
50 14:43:37.328257 total size: 54682112 (52 MB)
51 14:43:37.328320 No compression specified
52 14:43:37.585675 progress 0 % (0 MB)
53 14:43:37.599616 progress 5 % (2 MB)
54 14:43:37.613460 progress 10 % (5 MB)
55 14:43:37.627406 progress 15 % (7 MB)
56 14:43:37.641290 progress 20 % (10 MB)
57 14:43:37.655375 progress 25 % (13 MB)
58 14:43:37.669362 progress 30 % (15 MB)
59 14:43:37.683512 progress 35 % (18 MB)
60 14:43:37.697566 progress 40 % (20 MB)
61 14:43:37.711521 progress 45 % (23 MB)
62 14:43:37.725591 progress 50 % (26 MB)
63 14:43:37.739481 progress 55 % (28 MB)
64 14:43:37.753493 progress 60 % (31 MB)
65 14:43:37.767294 progress 65 % (33 MB)
66 14:43:37.781147 progress 70 % (36 MB)
67 14:43:37.794914 progress 75 % (39 MB)
68 14:43:37.808985 progress 80 % (41 MB)
69 14:43:37.822998 progress 85 % (44 MB)
70 14:43:37.836701 progress 90 % (46 MB)
71 14:43:37.850622 progress 95 % (49 MB)
72 14:43:37.864199 progress 100 % (52 MB)
73 14:43:37.864451 52 MB downloaded in 0.54 s (97.26 MB/s)
74 14:43:37.864606 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:43:37.864839 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:43:37.864928 start: 1.3 download-retry (timeout 00:09:42) [common]
78 14:43:37.865086 start: 1.3.1 http-download (timeout 00:09:42) [common]
79 14:43:37.865224 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 14:43:37.865299 saving as /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/dtb/mt8192-asurada-spherion-r0.dtb
81 14:43:37.865362 total size: 47258 (0 MB)
82 14:43:37.865424 No compression specified
83 14:43:38.125279 progress 69 % (0 MB)
84 14:43:38.126902 progress 100 % (0 MB)
85 14:43:38.127792 0 MB downloaded in 0.26 s (0.17 MB/s)
86 14:43:38.128511 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:43:38.129807 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:43:38.130294 start: 1.4 download-retry (timeout 00:09:42) [common]
90 14:43:38.130823 start: 1.4.1 http-download (timeout 00:09:42) [common]
91 14:43:38.131490 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:43:38.131880 saving as /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/modules/modules.tar
93 14:43:38.132232 total size: 8608920 (8 MB)
94 14:43:38.132584 Using unxz to decompress xz
95 14:43:38.144118 progress 0 % (0 MB)
96 14:43:38.162929 progress 5 % (0 MB)
97 14:43:38.189504 progress 10 % (0 MB)
98 14:43:38.218974 progress 15 % (1 MB)
99 14:43:38.242623 progress 20 % (1 MB)
100 14:43:38.266069 progress 25 % (2 MB)
101 14:43:38.290262 progress 30 % (2 MB)
102 14:43:38.314704 progress 35 % (2 MB)
103 14:43:38.341612 progress 40 % (3 MB)
104 14:43:38.364545 progress 45 % (3 MB)
105 14:43:38.388493 progress 50 % (4 MB)
106 14:43:38.413791 progress 55 % (4 MB)
107 14:43:38.438049 progress 60 % (4 MB)
108 14:43:38.462376 progress 65 % (5 MB)
109 14:43:38.487428 progress 70 % (5 MB)
110 14:43:38.513274 progress 75 % (6 MB)
111 14:43:38.539771 progress 80 % (6 MB)
112 14:43:38.564217 progress 85 % (7 MB)
113 14:43:38.589547 progress 90 % (7 MB)
114 14:43:38.614912 progress 95 % (7 MB)
115 14:43:38.640229 progress 100 % (8 MB)
116 14:43:38.645874 8 MB downloaded in 0.51 s (15.98 MB/s)
117 14:43:38.646126 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:43:38.646397 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:43:38.646491 start: 1.5 prepare-tftp-overlay (timeout 00:09:41) [common]
121 14:43:38.646583 start: 1.5.1 extract-nfsrootfs (timeout 00:09:41) [common]
122 14:43:38.646665 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:43:38.646759 start: 1.5.2 lava-overlay (timeout 00:09:41) [common]
124 14:43:38.646996 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel
125 14:43:38.647129 makedir: /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin
126 14:43:38.647234 makedir: /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/tests
127 14:43:38.647332 makedir: /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/results
128 14:43:38.647451 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-add-keys
129 14:43:38.647601 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-add-sources
130 14:43:38.647732 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-background-process-start
131 14:43:38.647863 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-background-process-stop
132 14:43:38.647988 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-common-functions
133 14:43:38.648113 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-echo-ipv4
134 14:43:38.648239 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-install-packages
135 14:43:38.648365 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-installed-packages
136 14:43:38.648488 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-os-build
137 14:43:38.648613 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-probe-channel
138 14:43:38.648736 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-probe-ip
139 14:43:38.648860 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-target-ip
140 14:43:38.649039 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-target-mac
141 14:43:38.649166 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-target-storage
142 14:43:38.649295 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-case
143 14:43:38.649423 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-event
144 14:43:38.649571 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-feedback
145 14:43:38.649730 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-raise
146 14:43:38.649866 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-reference
147 14:43:38.649993 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-runner
148 14:43:38.650118 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-set
149 14:43:38.650246 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-test-shell
150 14:43:38.650375 Updating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-install-packages (oe)
151 14:43:38.650527 Updating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/bin/lava-installed-packages (oe)
152 14:43:38.650649 Creating /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/environment
153 14:43:38.650753 LAVA metadata
154 14:43:38.650828 - LAVA_JOB_ID=14167004
155 14:43:38.650893 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:43:38.650994 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:41) [common]
157 14:43:38.651064 skipped lava-vland-overlay
158 14:43:38.651139 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:43:38.651220 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:41) [common]
160 14:43:38.651282 skipped lava-multinode-overlay
161 14:43:38.651358 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:43:38.651447 start: 1.5.2.3 test-definition (timeout 00:09:41) [common]
163 14:43:38.651521 Loading test definitions
164 14:43:38.651616 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:41) [common]
165 14:43:38.651689 Using /lava-14167004 at stage 0
166 14:43:38.651996 uuid=14167004_1.5.2.3.1 testdef=None
167 14:43:38.652086 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:43:38.652174 start: 1.5.2.3.2 test-overlay (timeout 00:09:41) [common]
169 14:43:38.653346 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:43:38.653611 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:41) [common]
172 14:43:38.654223 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:43:38.654457 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:41) [common]
175 14:43:38.655051 runner path: /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/0/tests/0_v4l2-compliance-uvc test_uuid 14167004_1.5.2.3.1
176 14:43:38.655209 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:43:38.655421 Creating lava-test-runner.conf files
179 14:43:38.655486 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167004/lava-overlay-qbkykjel/lava-14167004/0 for stage 0
180 14:43:38.655577 - 0_v4l2-compliance-uvc
181 14:43:38.655675 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:43:38.655761 start: 1.5.2.4 compress-overlay (timeout 00:09:41) [common]
183 14:43:38.662497 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:43:38.662607 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:41) [common]
185 14:43:38.662696 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:43:38.662787 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:43:38.662874 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:41) [common]
188 14:43:39.548018 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 14:43:39.548408 start: 1.5.4 extract-modules (timeout 00:09:40) [common]
190 14:43:39.548520 extracting modules file /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167004/extract-overlay-ramdisk-w_3yl_0n/ramdisk
191 14:43:39.767551 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:43:39.767729 start: 1.5.5 apply-overlay-tftp (timeout 00:09:40) [common]
193 14:43:39.767827 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167004/compress-overlay-4j4vry8o/overlay-1.5.2.4.tar.gz to ramdisk
194 14:43:39.767898 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167004/compress-overlay-4j4vry8o/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167004/extract-overlay-ramdisk-w_3yl_0n/ramdisk
195 14:43:39.774674 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:43:39.774790 start: 1.5.6 configure-preseed-file (timeout 00:09:40) [common]
197 14:43:39.774883 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:43:39.774976 start: 1.5.7 compress-ramdisk (timeout 00:09:40) [common]
199 14:43:39.775055 Building ramdisk /var/lib/lava/dispatcher/tmp/14167004/extract-overlay-ramdisk-w_3yl_0n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167004/extract-overlay-ramdisk-w_3yl_0n/ramdisk
200 14:43:40.502178 >> 275882 blocks
201 14:43:44.547801 rename /var/lib/lava/dispatcher/tmp/14167004/extract-overlay-ramdisk-w_3yl_0n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/ramdisk/ramdisk.cpio.gz
202 14:43:44.548248 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 14:43:44.548373 start: 1.5.8 prepare-kernel (timeout 00:09:35) [common]
204 14:43:44.548477 start: 1.5.8.1 prepare-fit (timeout 00:09:35) [common]
205 14:43:44.548584 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/kernel/Image']
206 14:43:58.141633 Returned 0 in 13 seconds
207 14:43:58.242275 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/kernel/image.itb
208 14:43:58.890575 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:43:58.890949 output: Created: Tue Jun 4 15:43:58 2024
210 14:43:58.891024 output: Image 0 (kernel-1)
211 14:43:58.891088 output: Description:
212 14:43:58.891151 output: Created: Tue Jun 4 15:43:58 2024
213 14:43:58.891211 output: Type: Kernel Image
214 14:43:58.891275 output: Compression: lzma compressed
215 14:43:58.891337 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:43:58.891400 output: Architecture: AArch64
217 14:43:58.891462 output: OS: Linux
218 14:43:58.891523 output: Load Address: 0x00000000
219 14:43:58.891585 output: Entry Point: 0x00000000
220 14:43:58.891643 output: Hash algo: crc32
221 14:43:58.891700 output: Hash value: 88dcd836
222 14:43:58.891758 output: Image 1 (fdt-1)
223 14:43:58.891814 output: Description: mt8192-asurada-spherion-r0
224 14:43:58.891871 output: Created: Tue Jun 4 15:43:58 2024
225 14:43:58.891925 output: Type: Flat Device Tree
226 14:43:58.891979 output: Compression: uncompressed
227 14:43:58.892033 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 14:43:58.892087 output: Architecture: AArch64
229 14:43:58.892140 output: Hash algo: crc32
230 14:43:58.892194 output: Hash value: 0f8e4d2e
231 14:43:58.892248 output: Image 2 (ramdisk-1)
232 14:43:58.892302 output: Description: unavailable
233 14:43:58.892356 output: Created: Tue Jun 4 15:43:58 2024
234 14:43:58.892410 output: Type: RAMDisk Image
235 14:43:58.892464 output: Compression: Unknown Compression
236 14:43:58.892518 output: Data Size: 41209071 Bytes = 40243.23 KiB = 39.30 MiB
237 14:43:58.892572 output: Architecture: AArch64
238 14:43:58.892625 output: OS: Linux
239 14:43:58.892679 output: Load Address: unavailable
240 14:43:58.892733 output: Entry Point: unavailable
241 14:43:58.892786 output: Hash algo: crc32
242 14:43:58.892839 output: Hash value: 342c44e2
243 14:43:58.892893 output: Default Configuration: 'conf-1'
244 14:43:58.892946 output: Configuration 0 (conf-1)
245 14:43:58.893032 output: Description: mt8192-asurada-spherion-r0
246 14:43:58.893101 output: Kernel: kernel-1
247 14:43:58.893156 output: Init Ramdisk: ramdisk-1
248 14:43:58.893210 output: FDT: fdt-1
249 14:43:58.893263 output: Loadables: kernel-1
250 14:43:58.893316 output:
251 14:43:58.893518 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 14:43:58.893612 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 14:43:58.893720 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 14:43:58.893813 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:21) [common]
255 14:43:58.893891 No LXC device requested
256 14:43:58.893971 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:43:58.894055 start: 1.7 deploy-device-env (timeout 00:09:21) [common]
258 14:43:58.894135 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:43:58.894207 Checking files for TFTP limit of 4294967296 bytes.
260 14:43:58.894710 end: 1 tftp-deploy (duration 00:00:39) [common]
261 14:43:58.894819 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:43:58.894910 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:43:58.895036 substitutions:
264 14:43:58.895105 - {DTB}: 14167004/tftp-deploy-z24ttcqp/dtb/mt8192-asurada-spherion-r0.dtb
265 14:43:58.895169 - {INITRD}: 14167004/tftp-deploy-z24ttcqp/ramdisk/ramdisk.cpio.gz
266 14:43:58.895229 - {KERNEL}: 14167004/tftp-deploy-z24ttcqp/kernel/Image
267 14:43:58.895290 - {LAVA_MAC}: None
268 14:43:58.895347 - {PRESEED_CONFIG}: None
269 14:43:58.895404 - {PRESEED_LOCAL}: None
270 14:43:58.895459 - {RAMDISK}: 14167004/tftp-deploy-z24ttcqp/ramdisk/ramdisk.cpio.gz
271 14:43:58.895516 - {ROOT_PART}: None
272 14:43:58.895571 - {ROOT}: None
273 14:43:58.895626 - {SERVER_IP}: 192.168.201.1
274 14:43:58.895681 - {TEE}: None
275 14:43:58.895737 Parsed boot commands:
276 14:43:58.895791 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:43:58.895968 Parsed boot commands: tftpboot 192.168.201.1 14167004/tftp-deploy-z24ttcqp/kernel/image.itb 14167004/tftp-deploy-z24ttcqp/kernel/cmdline
278 14:43:58.896061 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:43:58.896148 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:43:58.896238 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:43:58.896321 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:43:58.896390 Not connected, no need to disconnect.
283 14:43:58.896466 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:43:58.896545 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:43:58.896617 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 14:43:58.900356 Setting prompt string to ['lava-test: # ']
287 14:43:58.900711 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:43:58.900819 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:43:58.900920 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:43:58.901052 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:43:58.901288 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 14:44:04.048464 >> Command sent successfully.
293 14:44:04.058564 Returned 0 in 5 seconds
294 14:44:04.159834 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 14:44:04.161676 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 14:44:04.162201 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 14:44:04.162819 Setting prompt string to 'Starting depthcharge on Spherion...'
299 14:44:04.163304 Changing prompt to 'Starting depthcharge on Spherion...'
300 14:44:04.163723 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 14:44:04.165588 [Enter `^Ec?' for help]
302 14:44:04.326287
303 14:44:04.326825
304 14:44:04.327170 F0: 102B 0000
305 14:44:04.327659
306 14:44:04.328016 F3: 1001 0000 [0200]
307 14:44:04.328345
308 14:44:04.330538 F3: 1001 0000
309 14:44:04.331108
310 14:44:04.331459 F7: 102D 0000
311 14:44:04.331786
312 14:44:04.332672 F1: 0000 0000
313 14:44:04.333159
314 14:44:04.333514 V0: 0000 0000 [0001]
315 14:44:04.333842
316 14:44:04.336772 00: 0007 8000
317 14:44:04.337277
318 14:44:04.337626 01: 0000 0000
319 14:44:04.337962
320 14:44:04.338272 BP: 0C00 0209 [0000]
321 14:44:04.339699
322 14:44:04.340263 G0: 1182 0000
323 14:44:04.340625
324 14:44:04.340950 EC: 0000 0021 [4000]
325 14:44:04.342620
326 14:44:04.343072 S7: 0000 0000 [0000]
327 14:44:04.343418
328 14:44:04.343743 CC: 0000 0000 [0001]
329 14:44:04.346370
330 14:44:04.346801 T0: 0000 0040 [010F]
331 14:44:04.347151
332 14:44:04.347473 Jump to BL
333 14:44:04.347910
334 14:44:04.372878
335 14:44:04.373440
336 14:44:04.380009 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 14:44:04.383955 ARM64: Exception handlers installed.
338 14:44:04.388768 ARM64: Testing exception
339 14:44:04.389348 ARM64: Done test exception
340 14:44:04.397954 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 14:44:04.408251 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 14:44:04.414701 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 14:44:04.424799 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 14:44:04.431627 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 14:44:04.438345 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 14:44:04.449027 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 14:44:04.455524 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 14:44:04.475027 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 14:44:04.478548 WDT: Last reset was cold boot
350 14:44:04.482661 SPI1(PAD0) initialized at 2873684 Hz
351 14:44:04.485308 SPI5(PAD0) initialized at 992727 Hz
352 14:44:04.489702 VBOOT: Loading verstage.
353 14:44:04.495650 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 14:44:04.498367 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 14:44:04.502163 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 14:44:04.505032 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 14:44:04.512401 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 14:44:04.519332 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 14:44:04.530434 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
360 14:44:04.530864
361 14:44:04.531237
362 14:44:04.540429 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 14:44:04.543430 ARM64: Exception handlers installed.
364 14:44:04.547476 ARM64: Testing exception
365 14:44:04.548042 ARM64: Done test exception
366 14:44:04.553211 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 14:44:04.558539 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 14:44:04.572199 Probing TPM: . done!
369 14:44:04.572628 TPM ready after 0 ms
370 14:44:04.579415 Connected to device vid:did:rid of 1ae0:0028:00
371 14:44:04.585803 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 14:44:04.643200 Initialized TPM device CR50 revision 0
373 14:44:04.653911 tlcl_send_startup: Startup return code is 0
374 14:44:04.654357 TPM: setup succeeded
375 14:44:04.666090 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 14:44:04.674210 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 14:44:04.686473 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 14:44:04.696540 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 14:44:04.699038 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 14:44:04.707293 in-header: 03 07 00 00 08 00 00 00
381 14:44:04.710563 in-data: aa e4 47 04 13 02 00 00
382 14:44:04.714522 Chrome EC: UHEPI supported
383 14:44:04.721506 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 14:44:04.725086 in-header: 03 ad 00 00 08 00 00 00
385 14:44:04.728355 in-data: 00 20 20 08 00 00 00 00
386 14:44:04.729085 Phase 1
387 14:44:04.732060 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 14:44:04.740201 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 14:44:04.743173 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 14:44:04.747340 Recovery requested (1009000e)
391 14:44:04.755820 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 14:44:04.761520 tlcl_extend: response is 0
393 14:44:04.770349 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 14:44:04.776100 tlcl_extend: response is 0
395 14:44:04.783093 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 14:44:04.803379 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
397 14:44:04.809852 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 14:44:04.810385
399 14:44:04.810734
400 14:44:04.820940 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 14:44:04.823908 ARM64: Exception handlers installed.
402 14:44:04.824379 ARM64: Testing exception
403 14:44:04.827894 ARM64: Done test exception
404 14:44:04.849502 pmic_efuse_setting: Set efuses in 11 msecs
405 14:44:04.852879 pmwrap_interface_init: Select PMIF_VLD_RDY
406 14:44:04.859005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 14:44:04.862075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 14:44:04.865950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 14:44:04.873120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 14:44:04.877082 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 14:44:04.884252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 14:44:04.887330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 14:44:04.891420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 14:44:04.894659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 14:44:04.902825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 14:44:04.906662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 14:44:04.909974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 14:44:04.913148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 14:44:04.920912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 14:44:04.928476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 14:44:04.932280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 14:44:04.939088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 14:44:04.943742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 14:44:04.950112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 14:44:04.954245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 14:44:04.961383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 14:44:04.965433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 14:44:04.972713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 14:44:04.976418 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 14:44:04.983636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 14:44:04.987397 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 14:44:04.994933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 14:44:04.998187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 14:44:05.001834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 14:44:05.006111 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 14:44:05.013044 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 14:44:05.017405 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 14:44:05.024250 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 14:44:05.028577 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 14:44:05.032325 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 14:44:05.039306 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 14:44:05.042568 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 14:44:05.045845 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 14:44:05.054201 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 14:44:05.057079 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 14:44:05.061393 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 14:44:05.064781 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 14:44:05.068269 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 14:44:05.075855 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 14:44:05.079815 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 14:44:05.083603 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 14:44:05.087886 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 14:44:05.091391 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 14:44:05.095115 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 14:44:05.098485 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 14:44:05.102299 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 14:44:05.113317 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 14:44:05.121125 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 14:44:05.124329 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 14:44:05.132054 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 14:44:05.142099 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 14:44:05.146236 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 14:44:05.150037 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 14:44:05.153319 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 14:44:05.162381 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 14:44:05.168595 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 14:44:05.172461 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 14:44:05.176697 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 14:44:05.186196 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 14:44:05.195235 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 14:44:05.205035 [RTC]rtc_get_frequency_meter,154: input=19, output=883
472 14:44:05.214259 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 14:44:05.224121 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 14:44:05.233575 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 14:44:05.243665 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 14:44:05.247116 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 14:44:05.251133 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 14:44:05.255112 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 14:44:05.262452 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 14:44:05.266997 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 14:44:05.269564 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 14:44:05.274280 ADC[4]: Raw value=901328 ID=7
483 14:44:05.274814 ADC[3]: Raw value=213336 ID=1
484 14:44:05.277459 RAM Code: 0x71
485 14:44:05.280442 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 14:44:05.284307 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 14:44:05.295995 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 14:44:05.299412 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 14:44:05.303558 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 14:44:05.306770 in-header: 03 07 00 00 08 00 00 00
491 14:44:05.310595 in-data: aa e4 47 04 13 02 00 00
492 14:44:05.314765 Chrome EC: UHEPI supported
493 14:44:05.318408 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 14:44:05.322257 in-header: 03 ed 00 00 08 00 00 00
495 14:44:05.325800 in-data: 80 20 60 08 00 00 00 00
496 14:44:05.330212 MRC: failed to locate region type 0.
497 14:44:05.337208 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 14:44:05.340939 DRAM-K: Running full calibration
499 14:44:05.344859 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 14:44:05.348337 header.status = 0x0
501 14:44:05.352239 header.version = 0x6 (expected: 0x6)
502 14:44:05.355731 header.size = 0xd00 (expected: 0xd00)
503 14:44:05.356165 header.flags = 0x0
504 14:44:05.362932 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 14:44:05.380305 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
506 14:44:05.388693 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 14:44:05.389266 dram_init: ddr_geometry: 2
508 14:44:05.391437 [EMI] MDL number = 2
509 14:44:05.396529 [EMI] Get MDL freq = 0
510 14:44:05.397097 dram_init: ddr_type: 0
511 14:44:05.398884 is_discrete_lpddr4: 1
512 14:44:05.402484 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 14:44:05.402925
514 14:44:05.403274
515 14:44:05.403598 [Bian_co] ETT version 0.0.0.1
516 14:44:05.409860 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 14:44:05.410300
518 14:44:05.413465 dramc_set_vcore_voltage set vcore to 650000
519 14:44:05.413905 Read voltage for 800, 4
520 14:44:05.417236 Vio18 = 0
521 14:44:05.417671 Vcore = 650000
522 14:44:05.418021 Vdram = 0
523 14:44:05.418346 Vddq = 0
524 14:44:05.420498 Vmddr = 0
525 14:44:05.421081 dram_init: config_dvfs: 1
526 14:44:05.427558 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 14:44:05.430924 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 14:44:05.437104 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 14:44:05.441375 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 14:44:05.444099 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 14:44:05.447280 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 14:44:05.450960 MEM_TYPE=3, freq_sel=18
533 14:44:05.454539 sv_algorithm_assistance_LP4_1600
534 14:44:05.457644 ============ PULL DRAM RESETB DOWN ============
535 14:44:05.461059 ========== PULL DRAM RESETB DOWN end =========
536 14:44:05.464677 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 14:44:05.467763 ===================================
538 14:44:05.471548 LPDDR4 DRAM CONFIGURATION
539 14:44:05.474746 ===================================
540 14:44:05.478081 EX_ROW_EN[0] = 0x0
541 14:44:05.478648 EX_ROW_EN[1] = 0x0
542 14:44:05.481279 LP4Y_EN = 0x0
543 14:44:05.481885 WORK_FSP = 0x0
544 14:44:05.484745 WL = 0x2
545 14:44:05.485252 RL = 0x2
546 14:44:05.488180 BL = 0x2
547 14:44:05.488747 RPST = 0x0
548 14:44:05.491513 RD_PRE = 0x0
549 14:44:05.492002 WR_PRE = 0x1
550 14:44:05.494619 WR_PST = 0x0
551 14:44:05.495196 DBI_WR = 0x0
552 14:44:05.498375 DBI_RD = 0x0
553 14:44:05.498856 OTF = 0x1
554 14:44:05.501051 ===================================
555 14:44:05.504677 ===================================
556 14:44:05.508072 ANA top config
557 14:44:05.511410 ===================================
558 14:44:05.515205 DLL_ASYNC_EN = 0
559 14:44:05.515757 ALL_SLAVE_EN = 1
560 14:44:05.518180 NEW_RANK_MODE = 1
561 14:44:05.521254 DLL_IDLE_MODE = 1
562 14:44:05.524664 LP45_APHY_COMB_EN = 1
563 14:44:05.525180 TX_ODT_DIS = 1
564 14:44:05.529928 NEW_8X_MODE = 1
565 14:44:05.531030 ===================================
566 14:44:05.534531 ===================================
567 14:44:05.538510 data_rate = 1600
568 14:44:05.541598 CKR = 1
569 14:44:05.545067 DQ_P2S_RATIO = 8
570 14:44:05.547954 ===================================
571 14:44:05.548384 CA_P2S_RATIO = 8
572 14:44:05.552276 DQ_CA_OPEN = 0
573 14:44:05.554993 DQ_SEMI_OPEN = 0
574 14:44:05.558473 CA_SEMI_OPEN = 0
575 14:44:05.561386 CA_FULL_RATE = 0
576 14:44:05.564640 DQ_CKDIV4_EN = 1
577 14:44:05.565107 CA_CKDIV4_EN = 1
578 14:44:05.568513 CA_PREDIV_EN = 0
579 14:44:05.572149 PH8_DLY = 0
580 14:44:05.575809 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 14:44:05.578401 DQ_AAMCK_DIV = 4
582 14:44:05.578945 CA_AAMCK_DIV = 4
583 14:44:05.581731 CA_ADMCK_DIV = 4
584 14:44:05.584831 DQ_TRACK_CA_EN = 0
585 14:44:05.588391 CA_PICK = 800
586 14:44:05.591550 CA_MCKIO = 800
587 14:44:05.595925 MCKIO_SEMI = 0
588 14:44:05.598625 PLL_FREQ = 3068
589 14:44:05.599168 DQ_UI_PI_RATIO = 32
590 14:44:05.602914 CA_UI_PI_RATIO = 0
591 14:44:05.605897 ===================================
592 14:44:05.610055 ===================================
593 14:44:05.610507 memory_type:LPDDR4
594 14:44:05.613791 GP_NUM : 10
595 14:44:05.617608 SRAM_EN : 1
596 14:44:05.618047 MD32_EN : 0
597 14:44:05.621589 ===================================
598 14:44:05.624961 [ANA_INIT] >>>>>>>>>>>>>>
599 14:44:05.625549 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 14:44:05.628930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 14:44:05.632370 ===================================
602 14:44:05.635808 data_rate = 1600,PCW = 0X7600
603 14:44:05.639126 ===================================
604 14:44:05.643644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 14:44:05.649571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 14:44:05.652522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 14:44:05.659491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 14:44:05.662782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 14:44:05.666442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 14:44:05.666889 [ANA_INIT] flow start
611 14:44:05.669315 [ANA_INIT] PLL >>>>>>>>
612 14:44:05.673305 [ANA_INIT] PLL <<<<<<<<
613 14:44:05.673735 [ANA_INIT] MIDPI >>>>>>>>
614 14:44:05.676138 [ANA_INIT] MIDPI <<<<<<<<
615 14:44:05.679302 [ANA_INIT] DLL >>>>>>>>
616 14:44:05.679730 [ANA_INIT] flow end
617 14:44:05.683878 ============ LP4 DIFF to SE enter ============
618 14:44:05.689753 ============ LP4 DIFF to SE exit ============
619 14:44:05.690185 [ANA_INIT] <<<<<<<<<<<<<
620 14:44:05.693175 [Flow] Enable top DCM control >>>>>
621 14:44:05.696516 [Flow] Enable top DCM control <<<<<
622 14:44:05.699557 Enable DLL master slave shuffle
623 14:44:05.706571 ==============================================================
624 14:44:05.707004 Gating Mode config
625 14:44:05.713397 ==============================================================
626 14:44:05.716485 Config description:
627 14:44:05.723626 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 14:44:05.730901 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 14:44:05.736940 SELPH_MODE 0: By rank 1: By Phase
630 14:44:05.743923 ==============================================================
631 14:44:05.744354 GAT_TRACK_EN = 1
632 14:44:05.746520 RX_GATING_MODE = 2
633 14:44:05.749966 RX_GATING_TRACK_MODE = 2
634 14:44:05.753185 SELPH_MODE = 1
635 14:44:05.756887 PICG_EARLY_EN = 1
636 14:44:05.760285 VALID_LAT_VALUE = 1
637 14:44:05.766466 ==============================================================
638 14:44:05.771052 Enter into Gating configuration >>>>
639 14:44:05.773836 Exit from Gating configuration <<<<
640 14:44:05.777494 Enter into DVFS_PRE_config >>>>>
641 14:44:05.787432 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 14:44:05.790205 Exit from DVFS_PRE_config <<<<<
643 14:44:05.794070 Enter into PICG configuration >>>>
644 14:44:05.797046 Exit from PICG configuration <<<<
645 14:44:05.797526 [RX_INPUT] configuration >>>>>
646 14:44:05.800764 [RX_INPUT] configuration <<<<<
647 14:44:05.807183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 14:44:05.810436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 14:44:05.817848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 14:44:05.824781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 14:44:05.831333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 14:44:05.837818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 14:44:05.842382 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 14:44:05.844694 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 14:44:05.847916 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 14:44:05.854906 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 14:44:05.858226 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 14:44:05.861575 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 14:44:05.865429 ===================================
660 14:44:05.868127 LPDDR4 DRAM CONFIGURATION
661 14:44:05.871452 ===================================
662 14:44:05.872032 EX_ROW_EN[0] = 0x0
663 14:44:05.874659 EX_ROW_EN[1] = 0x0
664 14:44:05.875196 LP4Y_EN = 0x0
665 14:44:05.878190 WORK_FSP = 0x0
666 14:44:05.878877 WL = 0x2
667 14:44:05.881992 RL = 0x2
668 14:44:05.882480 BL = 0x2
669 14:44:05.885522 RPST = 0x0
670 14:44:05.886041 RD_PRE = 0x0
671 14:44:05.888332 WR_PRE = 0x1
672 14:44:05.888799 WR_PST = 0x0
673 14:44:05.891707 DBI_WR = 0x0
674 14:44:05.895060 DBI_RD = 0x0
675 14:44:05.895678 OTF = 0x1
676 14:44:05.898293 ===================================
677 14:44:05.902447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 14:44:05.905233 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 14:44:05.911543 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 14:44:05.915105 ===================================
681 14:44:05.915583 LPDDR4 DRAM CONFIGURATION
682 14:44:05.918791 ===================================
683 14:44:05.921616 EX_ROW_EN[0] = 0x10
684 14:44:05.925151 EX_ROW_EN[1] = 0x0
685 14:44:05.925624 LP4Y_EN = 0x0
686 14:44:05.928300 WORK_FSP = 0x0
687 14:44:05.928875 WL = 0x2
688 14:44:05.931933 RL = 0x2
689 14:44:05.932407 BL = 0x2
690 14:44:05.935835 RPST = 0x0
691 14:44:05.936312 RD_PRE = 0x0
692 14:44:05.938597 WR_PRE = 0x1
693 14:44:05.939028 WR_PST = 0x0
694 14:44:05.941670 DBI_WR = 0x0
695 14:44:05.942100 DBI_RD = 0x0
696 14:44:05.945998 OTF = 0x1
697 14:44:05.948351 ===================================
698 14:44:05.955271 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 14:44:05.959078 nWR fixed to 40
700 14:44:05.959662 [ModeRegInit_LP4] CH0 RK0
701 14:44:05.961965 [ModeRegInit_LP4] CH0 RK1
702 14:44:05.965341 [ModeRegInit_LP4] CH1 RK0
703 14:44:05.968902 [ModeRegInit_LP4] CH1 RK1
704 14:44:05.969420 match AC timing 13
705 14:44:05.972829 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 14:44:05.979946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 14:44:05.982365 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 14:44:05.986231 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 14:44:05.991997 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 14:44:05.992446 [EMI DOE] emi_dcm 0
711 14:44:06.000085 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 14:44:06.000630 ==
713 14:44:06.001947 Dram Type= 6, Freq= 0, CH_0, rank 0
714 14:44:06.006250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 14:44:06.006709 ==
716 14:44:06.008828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 14:44:06.015808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 14:44:06.025316 [CA 0] Center 37 (6~68) winsize 63
719 14:44:06.029456 [CA 1] Center 37 (6~68) winsize 63
720 14:44:06.032522 [CA 2] Center 35 (5~66) winsize 62
721 14:44:06.035603 [CA 3] Center 34 (4~65) winsize 62
722 14:44:06.039398 [CA 4] Center 34 (4~65) winsize 62
723 14:44:06.042299 [CA 5] Center 33 (3~64) winsize 62
724 14:44:06.042729
725 14:44:06.045728 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 14:44:06.046160
727 14:44:06.049340 [CATrainingPosCal] consider 1 rank data
728 14:44:06.053099 u2DelayCellTimex100 = 270/100 ps
729 14:44:06.055913 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
730 14:44:06.058934 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 14:44:06.062507 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 14:44:06.068910 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 14:44:06.072485 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 14:44:06.075830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 14:44:06.076263
736 14:44:06.078937 CA PerBit enable=1, Macro0, CA PI delay=33
737 14:44:06.079481
738 14:44:06.082581 [CBTSetCACLKResult] CA Dly = 33
739 14:44:06.083012 CS Dly: 5 (0~36)
740 14:44:06.083356 ==
741 14:44:06.085735 Dram Type= 6, Freq= 0, CH_0, rank 1
742 14:44:06.092650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 14:44:06.093177 ==
744 14:44:06.096394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 14:44:06.102857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 14:44:06.111778 [CA 0] Center 37 (7~68) winsize 62
747 14:44:06.114986 [CA 1] Center 37 (7~68) winsize 62
748 14:44:06.118236 [CA 2] Center 35 (4~66) winsize 63
749 14:44:06.122084 [CA 3] Center 35 (4~66) winsize 63
750 14:44:06.125150 [CA 4] Center 34 (3~65) winsize 63
751 14:44:06.128512 [CA 5] Center 33 (3~64) winsize 62
752 14:44:06.128945
753 14:44:06.132038 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 14:44:06.132470
755 14:44:06.135175 [CATrainingPosCal] consider 2 rank data
756 14:44:06.138305 u2DelayCellTimex100 = 270/100 ps
757 14:44:06.142230 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 14:44:06.145124 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 14:44:06.149222 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 14:44:06.155648 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 14:44:06.159119 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 14:44:06.162062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 14:44:06.162496
764 14:44:06.165207 CA PerBit enable=1, Macro0, CA PI delay=33
765 14:44:06.165641
766 14:44:06.168918 [CBTSetCACLKResult] CA Dly = 33
767 14:44:06.169408 CS Dly: 6 (0~38)
768 14:44:06.169757
769 14:44:06.172461 ----->DramcWriteLeveling(PI) begin...
770 14:44:06.172912 ==
771 14:44:06.175247 Dram Type= 6, Freq= 0, CH_0, rank 0
772 14:44:06.182675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 14:44:06.183111 ==
774 14:44:06.183462 Write leveling (Byte 0): 30 => 30
775 14:44:06.186818 Write leveling (Byte 1): 26 => 26
776 14:44:06.190271 DramcWriteLeveling(PI) end<-----
777 14:44:06.190708
778 14:44:06.191055 ==
779 14:44:06.194082 Dram Type= 6, Freq= 0, CH_0, rank 0
780 14:44:06.197649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 14:44:06.198181 ==
782 14:44:06.200554 [Gating] SW mode calibration
783 14:44:06.207498 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 14:44:06.214582 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 14:44:06.217947 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 14:44:06.221419 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 14:44:06.224689 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 14:44:06.231710 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 14:44:06.234837 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:44:06.238591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:44:06.245035 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:44:06.248672 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:44:06.252615 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:44:06.258479 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:44:06.261643 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 14:44:06.265240 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 14:44:06.268797 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 14:44:06.275317 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 14:44:06.278913 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:44:06.281930 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:44:06.288654 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:44:06.292614 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 14:44:06.295494 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 14:44:06.302201 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 14:44:06.305737 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 14:44:06.308698 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 14:44:06.316001 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 14:44:06.320006 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 14:44:06.323726 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 14:44:06.329133 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 14:44:06.332478 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 14:44:06.336380 0 9 12 | B1->B0 | 2828 3333 | 0 1 | (0 0) (1 1)
813 14:44:06.339535 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 14:44:06.345923 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 14:44:06.349320 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 14:44:06.352757 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 14:44:06.359288 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 14:44:06.362741 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 14:44:06.366249 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
820 14:44:06.372589 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
821 14:44:06.376202 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 14:44:06.380075 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:44:06.386898 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:44:06.389700 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:44:06.392640 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:44:06.396189 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 14:44:06.403071 0 11 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
828 14:44:06.406688 0 11 12 | B1->B0 | 3838 4343 | 1 0 | (0 0) (0 0)
829 14:44:06.409592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 14:44:06.416516 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 14:44:06.419812 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 14:44:06.422837 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 14:44:06.429646 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 14:44:06.432927 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 14:44:06.437540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
836 14:44:06.443023 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 14:44:06.446534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:44:06.450381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:44:06.454062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:44:06.459787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:44:06.463157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:44:06.466492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:44:06.473631 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:44:06.476994 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 14:44:06.479890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 14:44:06.486423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 14:44:06.490158 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 14:44:06.493381 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 14:44:06.500399 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 14:44:06.503607 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 14:44:06.507201 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 14:44:06.513467 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 14:44:06.513902 Total UI for P1: 0, mck2ui 16
854 14:44:06.517090 best dqsien dly found for B0: ( 0, 14, 8)
855 14:44:06.520162 Total UI for P1: 0, mck2ui 16
856 14:44:06.523517 best dqsien dly found for B1: ( 0, 14, 8)
857 14:44:06.527772 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 14:44:06.533597 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 14:44:06.534065
860 14:44:06.537295 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 14:44:06.540935 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 14:44:06.544914 [Gating] SW calibration Done
863 14:44:06.545389 ==
864 14:44:06.547356 Dram Type= 6, Freq= 0, CH_0, rank 0
865 14:44:06.551417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 14:44:06.551863 ==
867 14:44:06.552259 RX Vref Scan: 0
868 14:44:06.552638
869 14:44:06.553474 RX Vref 0 -> 0, step: 1
870 14:44:06.553907
871 14:44:06.557092 RX Delay -130 -> 252, step: 16
872 14:44:06.560626 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 14:44:06.563946 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 14:44:06.567531 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 14:44:06.573500 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 14:44:06.577362 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 14:44:06.580634 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 14:44:06.583947 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
879 14:44:06.587354 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
880 14:44:06.593955 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 14:44:06.597299 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 14:44:06.600652 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 14:44:06.604335 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 14:44:06.607263 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 14:44:06.613893 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
886 14:44:06.617670 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 14:44:06.621152 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 14:44:06.621582 ==
889 14:44:06.623815 Dram Type= 6, Freq= 0, CH_0, rank 0
890 14:44:06.627526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 14:44:06.628067 ==
892 14:44:06.631192 DQS Delay:
893 14:44:06.631729 DQS0 = 0, DQS1 = 0
894 14:44:06.634578 DQM Delay:
895 14:44:06.635113 DQM0 = 84, DQM1 = 78
896 14:44:06.635462 DQ Delay:
897 14:44:06.637635 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 14:44:06.640868 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
899 14:44:06.644639 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
900 14:44:06.647796 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
901 14:44:06.648370
902 14:44:06.648752
903 14:44:06.649153 ==
904 14:44:06.650828 Dram Type= 6, Freq= 0, CH_0, rank 0
905 14:44:06.658616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 14:44:06.659093 ==
907 14:44:06.659537
908 14:44:06.659895
909 14:44:06.660233 TX Vref Scan disable
910 14:44:06.661369 == TX Byte 0 ==
911 14:44:06.664561 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
912 14:44:06.667852 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
913 14:44:06.671328 == TX Byte 1 ==
914 14:44:06.675277 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
915 14:44:06.678056 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
916 14:44:06.681828 ==
917 14:44:06.685359 Dram Type= 6, Freq= 0, CH_0, rank 0
918 14:44:06.688474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 14:44:06.689104 ==
920 14:44:06.700863 TX Vref=22, minBit 8, minWin=26, winSum=433
921 14:44:06.704501 TX Vref=24, minBit 12, minWin=26, winSum=435
922 14:44:06.707783 TX Vref=26, minBit 12, minWin=26, winSum=441
923 14:44:06.711211 TX Vref=28, minBit 3, minWin=27, winSum=444
924 14:44:06.714291 TX Vref=30, minBit 10, minWin=27, winSum=449
925 14:44:06.721667 TX Vref=32, minBit 8, minWin=27, winSum=446
926 14:44:06.724840 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 30
927 14:44:06.725312
928 14:44:06.727828 Final TX Range 1 Vref 30
929 14:44:06.728368
930 14:44:06.728750 ==
931 14:44:06.731549 Dram Type= 6, Freq= 0, CH_0, rank 0
932 14:44:06.734311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 14:44:06.734765 ==
934 14:44:06.737867
935 14:44:06.738297
936 14:44:06.738642 TX Vref Scan disable
937 14:44:06.741249 == TX Byte 0 ==
938 14:44:06.744885 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
939 14:44:06.747811 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
940 14:44:06.751206 == TX Byte 1 ==
941 14:44:06.755652 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
942 14:44:06.759356 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
943 14:44:06.761445
944 14:44:06.761877 [DATLAT]
945 14:44:06.762223 Freq=800, CH0 RK0
946 14:44:06.762553
947 14:44:06.764650 DATLAT Default: 0xa
948 14:44:06.765116 0, 0xFFFF, sum = 0
949 14:44:06.768163 1, 0xFFFF, sum = 0
950 14:44:06.768597 2, 0xFFFF, sum = 0
951 14:44:06.772172 3, 0xFFFF, sum = 0
952 14:44:06.772705 4, 0xFFFF, sum = 0
953 14:44:06.775392 5, 0xFFFF, sum = 0
954 14:44:06.775833 6, 0xFFFF, sum = 0
955 14:44:06.777886 7, 0xFFFF, sum = 0
956 14:44:06.778324 8, 0xFFFF, sum = 0
957 14:44:06.781647 9, 0x0, sum = 1
958 14:44:06.782087 10, 0x0, sum = 2
959 14:44:06.784709 11, 0x0, sum = 3
960 14:44:06.785180 12, 0x0, sum = 4
961 14:44:06.788916 best_step = 10
962 14:44:06.789388
963 14:44:06.789738 ==
964 14:44:06.792118 Dram Type= 6, Freq= 0, CH_0, rank 0
965 14:44:06.795109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 14:44:06.795546 ==
967 14:44:06.798576 RX Vref Scan: 1
968 14:44:06.799110
969 14:44:06.799463 Set Vref Range= 32 -> 127
970 14:44:06.799788
971 14:44:06.802249 RX Vref 32 -> 127, step: 1
972 14:44:06.802682
973 14:44:06.805424 RX Delay -95 -> 252, step: 8
974 14:44:06.805907
975 14:44:06.808815 Set Vref, RX VrefLevel [Byte0]: 32
976 14:44:06.811469 [Byte1]: 32
977 14:44:06.811902
978 14:44:06.814899 Set Vref, RX VrefLevel [Byte0]: 33
979 14:44:06.818488 [Byte1]: 33
980 14:44:06.819021
981 14:44:06.822688 Set Vref, RX VrefLevel [Byte0]: 34
982 14:44:06.826149 [Byte1]: 34
983 14:44:06.829566
984 14:44:06.830006 Set Vref, RX VrefLevel [Byte0]: 35
985 14:44:06.832729 [Byte1]: 35
986 14:44:06.837306
987 14:44:06.837825 Set Vref, RX VrefLevel [Byte0]: 36
988 14:44:06.840797 [Byte1]: 36
989 14:44:06.844870
990 14:44:06.845496 Set Vref, RX VrefLevel [Byte0]: 37
991 14:44:06.848104 [Byte1]: 37
992 14:44:06.852172
993 14:44:06.852614 Set Vref, RX VrefLevel [Byte0]: 38
994 14:44:06.855658 [Byte1]: 38
995 14:44:06.860269
996 14:44:06.860709 Set Vref, RX VrefLevel [Byte0]: 39
997 14:44:06.863507 [Byte1]: 39
998 14:44:06.868173
999 14:44:06.868617 Set Vref, RX VrefLevel [Byte0]: 40
1000 14:44:06.871230 [Byte1]: 40
1001 14:44:06.875133
1002 14:44:06.875586 Set Vref, RX VrefLevel [Byte0]: 41
1003 14:44:06.878262 [Byte1]: 41
1004 14:44:06.882742
1005 14:44:06.883306 Set Vref, RX VrefLevel [Byte0]: 42
1006 14:44:06.886309 [Byte1]: 42
1007 14:44:06.890410
1008 14:44:06.890956 Set Vref, RX VrefLevel [Byte0]: 43
1009 14:44:06.893134 [Byte1]: 43
1010 14:44:06.897561
1011 14:44:06.898025 Set Vref, RX VrefLevel [Byte0]: 44
1012 14:44:06.901189 [Byte1]: 44
1013 14:44:06.906165
1014 14:44:06.906706 Set Vref, RX VrefLevel [Byte0]: 45
1015 14:44:06.908656 [Byte1]: 45
1016 14:44:06.913082
1017 14:44:06.913530 Set Vref, RX VrefLevel [Byte0]: 46
1018 14:44:06.916297 [Byte1]: 46
1019 14:44:06.920204
1020 14:44:06.920646 Set Vref, RX VrefLevel [Byte0]: 47
1021 14:44:06.923757 [Byte1]: 47
1022 14:44:06.928046
1023 14:44:06.928486 Set Vref, RX VrefLevel [Byte0]: 48
1024 14:44:06.931550 [Byte1]: 48
1025 14:44:06.935926
1026 14:44:06.936427 Set Vref, RX VrefLevel [Byte0]: 49
1027 14:44:06.938689 [Byte1]: 49
1028 14:44:06.943380
1029 14:44:06.943929 Set Vref, RX VrefLevel [Byte0]: 50
1030 14:44:06.946370 [Byte1]: 50
1031 14:44:06.951011
1032 14:44:06.951455 Set Vref, RX VrefLevel [Byte0]: 51
1033 14:44:06.954454 [Byte1]: 51
1034 14:44:06.958191
1035 14:44:06.958627 Set Vref, RX VrefLevel [Byte0]: 52
1036 14:44:06.961494 [Byte1]: 52
1037 14:44:06.966136
1038 14:44:06.966634 Set Vref, RX VrefLevel [Byte0]: 53
1039 14:44:06.969253 [Byte1]: 53
1040 14:44:06.973418
1041 14:44:06.973851 Set Vref, RX VrefLevel [Byte0]: 54
1042 14:44:06.976791 [Byte1]: 54
1043 14:44:06.981082
1044 14:44:06.981525 Set Vref, RX VrefLevel [Byte0]: 55
1045 14:44:06.984736 [Byte1]: 55
1046 14:44:06.988941
1047 14:44:06.989513 Set Vref, RX VrefLevel [Byte0]: 56
1048 14:44:06.992149 [Byte1]: 56
1049 14:44:06.996272
1050 14:44:06.996706 Set Vref, RX VrefLevel [Byte0]: 57
1051 14:44:06.999561 [Byte1]: 57
1052 14:44:07.003882
1053 14:44:07.004441 Set Vref, RX VrefLevel [Byte0]: 58
1054 14:44:07.007945 [Byte1]: 58
1055 14:44:07.011719
1056 14:44:07.012155 Set Vref, RX VrefLevel [Byte0]: 59
1057 14:44:07.015025 [Byte1]: 59
1058 14:44:07.019425
1059 14:44:07.019946 Set Vref, RX VrefLevel [Byte0]: 60
1060 14:44:07.022537 [Byte1]: 60
1061 14:44:07.026590
1062 14:44:07.027056 Set Vref, RX VrefLevel [Byte0]: 61
1063 14:44:07.029880 [Byte1]: 61
1064 14:44:07.034191
1065 14:44:07.034670 Set Vref, RX VrefLevel [Byte0]: 62
1066 14:44:07.037657 [Byte1]: 62
1067 14:44:07.041979
1068 14:44:07.042456 Set Vref, RX VrefLevel [Byte0]: 63
1069 14:44:07.046006 [Byte1]: 63
1070 14:44:07.050367
1071 14:44:07.050790 Set Vref, RX VrefLevel [Byte0]: 64
1072 14:44:07.052851 [Byte1]: 64
1073 14:44:07.056816
1074 14:44:07.057311 Set Vref, RX VrefLevel [Byte0]: 65
1075 14:44:07.060862 [Byte1]: 65
1076 14:44:07.064535
1077 14:44:07.064961 Set Vref, RX VrefLevel [Byte0]: 66
1078 14:44:07.068287 [Byte1]: 66
1079 14:44:07.072199
1080 14:44:07.072624 Set Vref, RX VrefLevel [Byte0]: 67
1081 14:44:07.075686 [Byte1]: 67
1082 14:44:07.079790
1083 14:44:07.080215 Set Vref, RX VrefLevel [Byte0]: 68
1084 14:44:07.084069 [Byte1]: 68
1085 14:44:07.087456
1086 14:44:07.087880 Set Vref, RX VrefLevel [Byte0]: 69
1087 14:44:07.090923 [Byte1]: 69
1088 14:44:07.095004
1089 14:44:07.095566 Set Vref, RX VrefLevel [Byte0]: 70
1090 14:44:07.099049 [Byte1]: 70
1091 14:44:07.102569
1092 14:44:07.103011 Set Vref, RX VrefLevel [Byte0]: 71
1093 14:44:07.106211 [Byte1]: 71
1094 14:44:07.109963
1095 14:44:07.110388 Set Vref, RX VrefLevel [Byte0]: 72
1096 14:44:07.113431 [Byte1]: 72
1097 14:44:07.117743
1098 14:44:07.118167 Set Vref, RX VrefLevel [Byte0]: 73
1099 14:44:07.120869 [Byte1]: 73
1100 14:44:07.126250
1101 14:44:07.126786 Set Vref, RX VrefLevel [Byte0]: 74
1102 14:44:07.129271 [Byte1]: 74
1103 14:44:07.133540
1104 14:44:07.134059 Set Vref, RX VrefLevel [Byte0]: 75
1105 14:44:07.136295 [Byte1]: 75
1106 14:44:07.140270
1107 14:44:07.140795 Set Vref, RX VrefLevel [Byte0]: 76
1108 14:44:07.143945 [Byte1]: 76
1109 14:44:07.149154
1110 14:44:07.149582 Final RX Vref Byte 0 = 63 to rank0
1111 14:44:07.151498 Final RX Vref Byte 1 = 58 to rank0
1112 14:44:07.154991 Final RX Vref Byte 0 = 63 to rank1
1113 14:44:07.158498 Final RX Vref Byte 1 = 58 to rank1==
1114 14:44:07.161534 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 14:44:07.165199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 14:44:07.168222 ==
1117 14:44:07.168657 DQS Delay:
1118 14:44:07.169084 DQS0 = 0, DQS1 = 0
1119 14:44:07.171703 DQM Delay:
1120 14:44:07.172212 DQM0 = 87, DQM1 = 79
1121 14:44:07.175225 DQ Delay:
1122 14:44:07.175744 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1123 14:44:07.179653 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1124 14:44:07.182433 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1125 14:44:07.185039 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1126 14:44:07.185469
1127 14:44:07.188224
1128 14:44:07.194982 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1129 14:44:07.198357 CH0 RK0: MR19=606, MR18=2B13
1130 14:44:07.205705 CH0_RK0: MR19=0x606, MR18=0x2B13, DQSOSC=398, MR23=63, INC=93, DEC=62
1131 14:44:07.206360
1132 14:44:07.208917 ----->DramcWriteLeveling(PI) begin...
1133 14:44:07.209438 ==
1134 14:44:07.212217 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 14:44:07.215171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 14:44:07.215664 ==
1137 14:44:07.219424 Write leveling (Byte 0): 29 => 29
1138 14:44:07.222744 Write leveling (Byte 1): 28 => 28
1139 14:44:07.225760 DramcWriteLeveling(PI) end<-----
1140 14:44:07.226227
1141 14:44:07.226598 ==
1142 14:44:07.228742 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 14:44:07.232346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 14:44:07.232911 ==
1145 14:44:07.235850 [Gating] SW mode calibration
1146 14:44:07.241949 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 14:44:07.249087 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 14:44:07.252351 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 14:44:07.255518 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 14:44:07.259113 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1151 14:44:07.303015 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 14:44:07.303945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 14:44:07.304353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 14:44:07.304709 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 14:44:07.305108 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 14:44:07.305526 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 14:44:07.305873 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 14:44:07.306196 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 14:44:07.306514 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 14:44:07.306829 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 14:44:07.323817 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 14:44:07.324878 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 14:44:07.325380 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 14:44:07.327397 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 14:44:07.327867 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1166 14:44:07.330648 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1167 14:44:07.334212 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 14:44:07.340907 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 14:44:07.343966 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 14:44:07.347831 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 14:44:07.354202 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 14:44:07.358765 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 14:44:07.362126 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1174 14:44:07.364024 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1175 14:44:07.371142 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1176 14:44:07.374874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 14:44:07.377407 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 14:44:07.384291 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 14:44:07.387645 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 14:44:07.391420 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 14:44:07.398037 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1182 14:44:07.401376 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
1183 14:44:07.404558 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1184 14:44:07.411359 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 14:44:07.414754 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 14:44:07.418484 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 14:44:07.421363 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 14:44:07.427843 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 14:44:07.432229 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1190 14:44:07.435572 0 11 8 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
1191 14:44:07.439666 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1192 14:44:07.443137 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 14:44:07.450297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 14:44:07.453512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 14:44:07.457141 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 14:44:07.461416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 14:44:07.468089 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1198 14:44:07.471390 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 14:44:07.474932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 14:44:07.481703 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 14:44:07.484783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 14:44:07.488287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:44:07.495483 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:44:07.497782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:44:07.501857 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:44:07.504718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:44:07.511298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:44:07.514913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:44:07.517980 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 14:44:07.525504 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 14:44:07.527992 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 14:44:07.531858 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 14:44:07.539080 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 14:44:07.541429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1215 14:44:07.545204 Total UI for P1: 0, mck2ui 16
1216 14:44:07.548950 best dqsien dly found for B0: ( 0, 14, 6)
1217 14:44:07.552048 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 14:44:07.555211 Total UI for P1: 0, mck2ui 16
1219 14:44:07.559030 best dqsien dly found for B1: ( 0, 14, 10)
1220 14:44:07.561572 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1221 14:44:07.565084 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1222 14:44:07.565557
1223 14:44:07.568564 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 14:44:07.575395 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1225 14:44:07.575962 [Gating] SW calibration Done
1226 14:44:07.576339 ==
1227 14:44:07.578362 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 14:44:07.585419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 14:44:07.585995 ==
1230 14:44:07.586374 RX Vref Scan: 0
1231 14:44:07.586725
1232 14:44:07.589106 RX Vref 0 -> 0, step: 1
1233 14:44:07.589577
1234 14:44:07.592357 RX Delay -130 -> 252, step: 16
1235 14:44:07.595330 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 14:44:07.599495 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1237 14:44:07.602096 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 14:44:07.605540 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1239 14:44:07.612498 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1240 14:44:07.615773 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1241 14:44:07.619326 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1242 14:44:07.622704 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1243 14:44:07.625918 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1244 14:44:07.632669 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1245 14:44:07.636093 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1246 14:44:07.639217 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1247 14:44:07.642502 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1248 14:44:07.645593 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 14:44:07.653338 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1250 14:44:07.656639 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1251 14:44:07.657354 ==
1252 14:44:07.659595 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 14:44:07.663058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 14:44:07.663633 ==
1255 14:44:07.664008 DQS Delay:
1256 14:44:07.666986 DQS0 = 0, DQS1 = 0
1257 14:44:07.667553 DQM Delay:
1258 14:44:07.669670 DQM0 = 83, DQM1 = 75
1259 14:44:07.670137 DQ Delay:
1260 14:44:07.673021 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1261 14:44:07.675996 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1262 14:44:07.679780 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1263 14:44:07.682397 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1264 14:44:07.682860
1265 14:44:07.683229
1266 14:44:07.683572 ==
1267 14:44:07.685730 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 14:44:07.689026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 14:44:07.692684 ==
1270 14:44:07.693257
1271 14:44:07.693763
1272 14:44:07.694124 TX Vref Scan disable
1273 14:44:07.696099 == TX Byte 0 ==
1274 14:44:07.699654 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1275 14:44:07.702825 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1276 14:44:07.705901 == TX Byte 1 ==
1277 14:44:07.709489 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1278 14:44:07.713467 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1279 14:44:07.714017 ==
1280 14:44:07.716160 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 14:44:07.722991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 14:44:07.723473 ==
1283 14:44:07.736091 TX Vref=22, minBit 2, minWin=27, winSum=441
1284 14:44:07.738129 TX Vref=24, minBit 3, minWin=27, winSum=446
1285 14:44:07.741525 TX Vref=26, minBit 3, minWin=27, winSum=449
1286 14:44:07.744850 TX Vref=28, minBit 9, minWin=27, winSum=453
1287 14:44:07.748154 TX Vref=30, minBit 0, minWin=28, winSum=450
1288 14:44:07.751855 TX Vref=32, minBit 0, minWin=28, winSum=453
1289 14:44:07.758400 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1290 14:44:07.758832
1291 14:44:07.761628 Final TX Range 1 Vref 32
1292 14:44:07.762058
1293 14:44:07.762422 ==
1294 14:44:07.765202 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 14:44:07.768472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 14:44:07.769036 ==
1297 14:44:07.769398
1298 14:44:07.769715
1299 14:44:07.772095 TX Vref Scan disable
1300 14:44:07.775026 == TX Byte 0 ==
1301 14:44:07.778170 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1302 14:44:07.781380 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1303 14:44:07.784839 == TX Byte 1 ==
1304 14:44:07.788297 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1305 14:44:07.791985 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1306 14:44:07.792412
1307 14:44:07.795190 [DATLAT]
1308 14:44:07.795629 Freq=800, CH0 RK1
1309 14:44:07.795968
1310 14:44:07.799582 DATLAT Default: 0xa
1311 14:44:07.800153 0, 0xFFFF, sum = 0
1312 14:44:07.802566 1, 0xFFFF, sum = 0
1313 14:44:07.802999 2, 0xFFFF, sum = 0
1314 14:44:07.805086 3, 0xFFFF, sum = 0
1315 14:44:07.805520 4, 0xFFFF, sum = 0
1316 14:44:07.808922 5, 0xFFFF, sum = 0
1317 14:44:07.809507 6, 0xFFFF, sum = 0
1318 14:44:07.812379 7, 0xFFFF, sum = 0
1319 14:44:07.812931 8, 0xFFFF, sum = 0
1320 14:44:07.815248 9, 0x0, sum = 1
1321 14:44:07.815683 10, 0x0, sum = 2
1322 14:44:07.818355 11, 0x0, sum = 3
1323 14:44:07.818787 12, 0x0, sum = 4
1324 14:44:07.821970 best_step = 10
1325 14:44:07.822397
1326 14:44:07.822735 ==
1327 14:44:07.824912 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 14:44:07.828336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 14:44:07.828768 ==
1330 14:44:07.829152 RX Vref Scan: 0
1331 14:44:07.832200
1332 14:44:07.832624 RX Vref 0 -> 0, step: 1
1333 14:44:07.832963
1334 14:44:07.835544 RX Delay -95 -> 252, step: 8
1335 14:44:07.838784 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 14:44:07.845461 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1337 14:44:07.849302 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1338 14:44:07.852263 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1339 14:44:07.855833 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1340 14:44:07.858732 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1341 14:44:07.862581 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1342 14:44:07.869291 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1343 14:44:07.872388 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1344 14:44:07.875320 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 14:44:07.878814 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1346 14:44:07.882930 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1347 14:44:07.889061 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1348 14:44:07.892789 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1349 14:44:07.895994 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1350 14:44:07.899212 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 14:44:07.899635 ==
1352 14:44:07.902783 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 14:44:07.909151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 14:44:07.909576 ==
1355 14:44:07.909910 DQS Delay:
1356 14:44:07.910223 DQS0 = 0, DQS1 = 0
1357 14:44:07.912522 DQM Delay:
1358 14:44:07.912940 DQM0 = 87, DQM1 = 77
1359 14:44:07.916417 DQ Delay:
1360 14:44:07.919474 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1361 14:44:07.919896 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1362 14:44:07.922870 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1363 14:44:07.926149 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1364 14:44:07.929812
1365 14:44:07.930231
1366 14:44:07.936257 [DQSOSCAuto] RK1, (LSB)MR18= 0x331d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1367 14:44:07.939620 CH0 RK1: MR19=606, MR18=331D
1368 14:44:07.946084 CH0_RK1: MR19=0x606, MR18=0x331D, DQSOSC=396, MR23=63, INC=94, DEC=62
1369 14:44:07.946508 [RxdqsGatingPostProcess] freq 800
1370 14:44:07.953147 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 14:44:07.956153 Pre-setting of DQS Precalculation
1372 14:44:07.962699 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 14:44:07.963219 ==
1374 14:44:07.966823 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 14:44:07.969768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 14:44:07.970192 ==
1377 14:44:07.973081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 14:44:07.979866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 14:44:07.989619 [CA 0] Center 36 (6~67) winsize 62
1380 14:44:07.993345 [CA 1] Center 36 (6~67) winsize 62
1381 14:44:07.996521 [CA 2] Center 34 (5~64) winsize 60
1382 14:44:07.999820 [CA 3] Center 33 (3~64) winsize 62
1383 14:44:08.003514 [CA 4] Center 34 (3~65) winsize 63
1384 14:44:08.006266 [CA 5] Center 33 (3~64) winsize 62
1385 14:44:08.006801
1386 14:44:08.009541 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1387 14:44:08.010013
1388 14:44:08.013344 [CATrainingPosCal] consider 1 rank data
1389 14:44:08.016131 u2DelayCellTimex100 = 270/100 ps
1390 14:44:08.019758 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 14:44:08.023044 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 14:44:08.026463 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1393 14:44:08.033193 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 14:44:08.036783 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1395 14:44:08.040525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 14:44:08.041151
1397 14:44:08.043463 CA PerBit enable=1, Macro0, CA PI delay=33
1398 14:44:08.043988
1399 14:44:08.046957 [CBTSetCACLKResult] CA Dly = 33
1400 14:44:08.047459 CS Dly: 4 (0~35)
1401 14:44:08.047842 ==
1402 14:44:08.050013 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 14:44:08.056660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 14:44:08.057296 ==
1405 14:44:08.060137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 14:44:08.066676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 14:44:08.075905 [CA 0] Center 36 (6~66) winsize 61
1408 14:44:08.078646 [CA 1] Center 36 (6~66) winsize 61
1409 14:44:08.083345 [CA 2] Center 34 (4~64) winsize 61
1410 14:44:08.085649 [CA 3] Center 33 (3~64) winsize 62
1411 14:44:08.089289 [CA 4] Center 34 (4~65) winsize 62
1412 14:44:08.093198 [CA 5] Center 33 (3~64) winsize 62
1413 14:44:08.093757
1414 14:44:08.095561 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1415 14:44:08.096036
1416 14:44:08.099164 [CATrainingPosCal] consider 2 rank data
1417 14:44:08.103151 u2DelayCellTimex100 = 270/100 ps
1418 14:44:08.106626 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1419 14:44:08.111044 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 14:44:08.114627 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1421 14:44:08.118012 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 14:44:08.121387 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 14:44:08.125586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 14:44:08.126152
1425 14:44:08.129768 CA PerBit enable=1, Macro0, CA PI delay=33
1426 14:44:08.130338
1427 14:44:08.133816 [CBTSetCACLKResult] CA Dly = 33
1428 14:44:08.134291 CS Dly: 5 (0~38)
1429 14:44:08.134670
1430 14:44:08.137170 ----->DramcWriteLeveling(PI) begin...
1431 14:44:08.137734 ==
1432 14:44:08.140313 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 14:44:08.144261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 14:44:08.144737 ==
1435 14:44:08.147350 Write leveling (Byte 0): 28 => 28
1436 14:44:08.150513 Write leveling (Byte 1): 30 => 30
1437 14:44:08.154248 DramcWriteLeveling(PI) end<-----
1438 14:44:08.154871
1439 14:44:08.155266 ==
1440 14:44:08.157322 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 14:44:08.160849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 14:44:08.161363 ==
1443 14:44:08.163776 [Gating] SW mode calibration
1444 14:44:08.170790 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 14:44:08.177605 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 14:44:08.181395 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 14:44:08.187047 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1448 14:44:08.190703 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 14:44:08.194375 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 14:44:08.197477 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 14:44:08.204099 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 14:44:08.207335 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 14:44:08.211095 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1454 14:44:08.217735 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 14:44:08.221019 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 14:44:08.224283 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 14:44:08.231379 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 14:44:08.233717 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 14:44:08.237544 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 14:44:08.245529 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 14:44:08.248968 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 14:44:08.250865 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 14:44:08.254274 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1464 14:44:08.261581 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 14:44:08.264633 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 14:44:08.267796 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 14:44:08.274567 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1468 14:44:08.277855 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 14:44:08.280949 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 14:44:08.287257 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 14:44:08.290628 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 14:44:08.294751 0 9 8 | B1->B0 | 2525 2424 | 1 1 | (1 1) (0 0)
1473 14:44:08.301723 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1474 14:44:08.304561 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 14:44:08.307828 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1476 14:44:08.314616 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 14:44:08.318677 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 14:44:08.321912 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 14:44:08.327611 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1480 14:44:08.331583 0 10 8 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (1 1)
1481 14:44:08.334805 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 14:44:08.338561 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 14:44:08.345108 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 14:44:08.347815 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 14:44:08.351917 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 14:44:08.358225 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 14:44:08.361150 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1488 14:44:08.365541 0 11 8 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
1489 14:44:08.371630 0 11 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1490 14:44:08.375068 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 14:44:08.378425 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 14:44:08.384824 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 14:44:08.387911 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 14:44:08.392255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 14:44:08.398475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 14:44:08.401421 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 14:44:08.404807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 14:44:08.407989 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 14:44:08.415039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 14:44:08.418157 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 14:44:08.421604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 14:44:08.428846 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 14:44:08.432450 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 14:44:08.434882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 14:44:08.442002 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 14:44:08.445166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 14:44:08.448730 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 14:44:08.455228 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 14:44:08.458930 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 14:44:08.461668 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 14:44:08.468841 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 14:44:08.471657 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 14:44:08.474888 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 14:44:08.478682 Total UI for P1: 0, mck2ui 16
1515 14:44:08.481733 best dqsien dly found for B0: ( 0, 14, 6)
1516 14:44:08.485209 Total UI for P1: 0, mck2ui 16
1517 14:44:08.489376 best dqsien dly found for B1: ( 0, 14, 6)
1518 14:44:08.492484 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 14:44:08.495570 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1520 14:44:08.496141
1521 14:44:08.498548 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 14:44:08.502174 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 14:44:08.505329 [Gating] SW calibration Done
1524 14:44:08.505900 ==
1525 14:44:08.509083 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 14:44:08.512658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 14:44:08.515863 ==
1528 14:44:08.516434 RX Vref Scan: 0
1529 14:44:08.516809
1530 14:44:08.518798 RX Vref 0 -> 0, step: 1
1531 14:44:08.519396
1532 14:44:08.522585 RX Delay -130 -> 252, step: 16
1533 14:44:08.525320 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1534 14:44:08.528573 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1535 14:44:08.532608 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1536 14:44:08.535609 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1537 14:44:08.539473 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1538 14:44:08.545763 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1539 14:44:08.550010 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1540 14:44:08.552959 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1541 14:44:08.556410 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1542 14:44:08.558927 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1543 14:44:08.565850 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1544 14:44:08.569314 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1545 14:44:08.572675 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1546 14:44:08.575676 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1547 14:44:08.579516 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1548 14:44:08.585645 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1549 14:44:08.586181 ==
1550 14:44:08.589216 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 14:44:08.592832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 14:44:08.593468 ==
1553 14:44:08.593852 DQS Delay:
1554 14:44:08.596529 DQS0 = 0, DQS1 = 0
1555 14:44:08.597055 DQM Delay:
1556 14:44:08.599139 DQM0 = 82, DQM1 = 74
1557 14:44:08.599626 DQ Delay:
1558 14:44:08.603083 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1559 14:44:08.605746 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1560 14:44:08.609351 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1561 14:44:08.612782 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1562 14:44:08.613544
1563 14:44:08.614042
1564 14:44:08.614401 ==
1565 14:44:08.615976 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 14:44:08.619112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 14:44:08.619591 ==
1568 14:44:08.619966
1569 14:44:08.620315
1570 14:44:08.623278 TX Vref Scan disable
1571 14:44:08.625561 == TX Byte 0 ==
1572 14:44:08.629280 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1573 14:44:08.632530 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1574 14:44:08.636250 == TX Byte 1 ==
1575 14:44:08.639345 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1576 14:44:08.643517 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1577 14:44:08.644145 ==
1578 14:44:08.645613 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 14:44:08.652619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 14:44:08.653150 ==
1581 14:44:08.664305 TX Vref=22, minBit 11, minWin=26, winSum=439
1582 14:44:08.668037 TX Vref=24, minBit 0, minWin=27, winSum=440
1583 14:44:08.671351 TX Vref=26, minBit 5, minWin=27, winSum=446
1584 14:44:08.675130 TX Vref=28, minBit 0, minWin=27, winSum=449
1585 14:44:08.677859 TX Vref=30, minBit 0, minWin=27, winSum=452
1586 14:44:08.681977 TX Vref=32, minBit 0, minWin=27, winSum=451
1587 14:44:08.688524 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30
1588 14:44:08.689040
1589 14:44:08.691421 Final TX Range 1 Vref 30
1590 14:44:08.691903
1591 14:44:08.692395 ==
1592 14:44:08.694893 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 14:44:08.698118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 14:44:08.698561 ==
1595 14:44:08.699000
1596 14:44:08.699410
1597 14:44:08.702431 TX Vref Scan disable
1598 14:44:08.705459 == TX Byte 0 ==
1599 14:44:08.708559 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1600 14:44:08.711757 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1601 14:44:08.715241 == TX Byte 1 ==
1602 14:44:08.718326 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 14:44:08.721894 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 14:44:08.722479
1605 14:44:08.722935 [DATLAT]
1606 14:44:08.725286 Freq=800, CH1 RK0
1607 14:44:08.725727
1608 14:44:08.728777 DATLAT Default: 0xa
1609 14:44:08.729257 0, 0xFFFF, sum = 0
1610 14:44:08.732575 1, 0xFFFF, sum = 0
1611 14:44:08.733181 2, 0xFFFF, sum = 0
1612 14:44:08.735908 3, 0xFFFF, sum = 0
1613 14:44:08.736464 4, 0xFFFF, sum = 0
1614 14:44:08.739014 5, 0xFFFF, sum = 0
1615 14:44:08.739562 6, 0xFFFF, sum = 0
1616 14:44:08.742027 7, 0xFFFF, sum = 0
1617 14:44:08.742470 8, 0xFFFF, sum = 0
1618 14:44:08.745316 9, 0x0, sum = 1
1619 14:44:08.745762 10, 0x0, sum = 2
1620 14:44:08.748566 11, 0x0, sum = 3
1621 14:44:08.749082 12, 0x0, sum = 4
1622 14:44:08.749656 best_step = 10
1623 14:44:08.750147
1624 14:44:08.751828 ==
1625 14:44:08.756456 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 14:44:08.758906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 14:44:08.759336 ==
1628 14:44:08.759745 RX Vref Scan: 1
1629 14:44:08.760116
1630 14:44:08.762442 Set Vref Range= 32 -> 127
1631 14:44:08.763074
1632 14:44:08.765640 RX Vref 32 -> 127, step: 1
1633 14:44:08.766065
1634 14:44:08.768942 RX Delay -111 -> 252, step: 8
1635 14:44:08.769403
1636 14:44:08.772381 Set Vref, RX VrefLevel [Byte0]: 32
1637 14:44:08.775646 [Byte1]: 32
1638 14:44:08.776185
1639 14:44:08.780254 Set Vref, RX VrefLevel [Byte0]: 33
1640 14:44:08.781992 [Byte1]: 33
1641 14:44:08.782422
1642 14:44:08.785074 Set Vref, RX VrefLevel [Byte0]: 34
1643 14:44:08.788412 [Byte1]: 34
1644 14:44:08.792440
1645 14:44:08.792966 Set Vref, RX VrefLevel [Byte0]: 35
1646 14:44:08.795592 [Byte1]: 35
1647 14:44:08.799692
1648 14:44:08.800121 Set Vref, RX VrefLevel [Byte0]: 36
1649 14:44:08.803372 [Byte1]: 36
1650 14:44:08.807863
1651 14:44:08.808415 Set Vref, RX VrefLevel [Byte0]: 37
1652 14:44:08.810541 [Byte1]: 37
1653 14:44:08.815349
1654 14:44:08.815903 Set Vref, RX VrefLevel [Byte0]: 38
1655 14:44:08.818253 [Byte1]: 38
1656 14:44:08.822785
1657 14:44:08.823225 Set Vref, RX VrefLevel [Byte0]: 39
1658 14:44:08.826145 [Byte1]: 39
1659 14:44:08.830837
1660 14:44:08.831366 Set Vref, RX VrefLevel [Byte0]: 40
1661 14:44:08.835102 [Byte1]: 40
1662 14:44:08.838817
1663 14:44:08.839386 Set Vref, RX VrefLevel [Byte0]: 41
1664 14:44:08.842948 [Byte1]: 41
1665 14:44:08.846353
1666 14:44:08.846890 Set Vref, RX VrefLevel [Byte0]: 42
1667 14:44:08.848954 [Byte1]: 42
1668 14:44:08.853610
1669 14:44:08.854035 Set Vref, RX VrefLevel [Byte0]: 43
1670 14:44:08.856901 [Byte1]: 43
1671 14:44:08.861442
1672 14:44:08.861866 Set Vref, RX VrefLevel [Byte0]: 44
1673 14:44:08.864299 [Byte1]: 44
1674 14:44:08.868658
1675 14:44:08.869221 Set Vref, RX VrefLevel [Byte0]: 45
1676 14:44:08.871936 [Byte1]: 45
1677 14:44:08.876696
1678 14:44:08.877265 Set Vref, RX VrefLevel [Byte0]: 46
1679 14:44:08.879738 [Byte1]: 46
1680 14:44:08.884458
1681 14:44:08.885025 Set Vref, RX VrefLevel [Byte0]: 47
1682 14:44:08.887026 [Byte1]: 47
1683 14:44:08.892079
1684 14:44:08.892501 Set Vref, RX VrefLevel [Byte0]: 48
1685 14:44:08.895409 [Byte1]: 48
1686 14:44:08.898982
1687 14:44:08.899407 Set Vref, RX VrefLevel [Byte0]: 49
1688 14:44:08.903128 [Byte1]: 49
1689 14:44:08.907620
1690 14:44:08.908147 Set Vref, RX VrefLevel [Byte0]: 50
1691 14:44:08.910497 [Byte1]: 50
1692 14:44:08.914964
1693 14:44:08.915390 Set Vref, RX VrefLevel [Byte0]: 51
1694 14:44:08.917608 [Byte1]: 51
1695 14:44:08.922439
1696 14:44:08.922861 Set Vref, RX VrefLevel [Byte0]: 52
1697 14:44:08.926115 [Byte1]: 52
1698 14:44:08.929928
1699 14:44:08.930370 Set Vref, RX VrefLevel [Byte0]: 53
1700 14:44:08.935904 [Byte1]: 53
1701 14:44:08.936339
1702 14:44:08.939579 Set Vref, RX VrefLevel [Byte0]: 54
1703 14:44:08.943241 [Byte1]: 54
1704 14:44:08.943675
1705 14:44:08.946128 Set Vref, RX VrefLevel [Byte0]: 55
1706 14:44:08.949461 [Byte1]: 55
1707 14:44:08.949890
1708 14:44:08.953237 Set Vref, RX VrefLevel [Byte0]: 56
1709 14:44:08.956436 [Byte1]: 56
1710 14:44:08.960363
1711 14:44:08.961006 Set Vref, RX VrefLevel [Byte0]: 57
1712 14:44:08.963505 [Byte1]: 57
1713 14:44:08.967753
1714 14:44:08.968186 Set Vref, RX VrefLevel [Byte0]: 58
1715 14:44:08.972423 [Byte1]: 58
1716 14:44:08.975585
1717 14:44:08.976014 Set Vref, RX VrefLevel [Byte0]: 59
1718 14:44:08.978998 [Byte1]: 59
1719 14:44:08.983942
1720 14:44:08.984373 Set Vref, RX VrefLevel [Byte0]: 60
1721 14:44:08.986755 [Byte1]: 60
1722 14:44:08.991451
1723 14:44:08.991862 Set Vref, RX VrefLevel [Byte0]: 61
1724 14:44:08.994299 [Byte1]: 61
1725 14:44:08.998843
1726 14:44:08.999300 Set Vref, RX VrefLevel [Byte0]: 62
1727 14:44:09.001869 [Byte1]: 62
1728 14:44:09.006530
1729 14:44:09.006955 Set Vref, RX VrefLevel [Byte0]: 63
1730 14:44:09.009693 [Byte1]: 63
1731 14:44:09.013966
1732 14:44:09.014396 Set Vref, RX VrefLevel [Byte0]: 64
1733 14:44:09.017531 [Byte1]: 64
1734 14:44:09.021772
1735 14:44:09.022195 Set Vref, RX VrefLevel [Byte0]: 65
1736 14:44:09.024922 [Byte1]: 65
1737 14:44:09.029145
1738 14:44:09.029730 Set Vref, RX VrefLevel [Byte0]: 66
1739 14:44:09.033236 [Byte1]: 66
1740 14:44:09.037220
1741 14:44:09.037766 Set Vref, RX VrefLevel [Byte0]: 67
1742 14:44:09.040003 [Byte1]: 67
1743 14:44:09.044325
1744 14:44:09.044754 Set Vref, RX VrefLevel [Byte0]: 68
1745 14:44:09.047853 [Byte1]: 68
1746 14:44:09.051996
1747 14:44:09.052424 Set Vref, RX VrefLevel [Byte0]: 69
1748 14:44:09.055509 [Byte1]: 69
1749 14:44:09.060595
1750 14:44:09.061042 Set Vref, RX VrefLevel [Byte0]: 70
1751 14:44:09.062957 [Byte1]: 70
1752 14:44:09.067458
1753 14:44:09.067931 Set Vref, RX VrefLevel [Byte0]: 71
1754 14:44:09.071130 [Byte1]: 71
1755 14:44:09.075079
1756 14:44:09.075501 Set Vref, RX VrefLevel [Byte0]: 72
1757 14:44:09.078408 [Byte1]: 72
1758 14:44:09.082653
1759 14:44:09.083080 Set Vref, RX VrefLevel [Byte0]: 73
1760 14:44:09.085923 [Byte1]: 73
1761 14:44:09.090167
1762 14:44:09.090606 Set Vref, RX VrefLevel [Byte0]: 74
1763 14:44:09.094241 [Byte1]: 74
1764 14:44:09.097880
1765 14:44:09.098344 Set Vref, RX VrefLevel [Byte0]: 75
1766 14:44:09.102013 [Byte1]: 75
1767 14:44:09.105570
1768 14:44:09.105997 Set Vref, RX VrefLevel [Byte0]: 76
1769 14:44:09.108892 [Byte1]: 76
1770 14:44:09.113126
1771 14:44:09.113555 Set Vref, RX VrefLevel [Byte0]: 77
1772 14:44:09.116647 [Byte1]: 77
1773 14:44:09.121472
1774 14:44:09.121900 Set Vref, RX VrefLevel [Byte0]: 78
1775 14:44:09.124640 [Byte1]: 78
1776 14:44:09.128707
1777 14:44:09.129178 Final RX Vref Byte 0 = 62 to rank0
1778 14:44:09.132372 Final RX Vref Byte 1 = 60 to rank0
1779 14:44:09.134796 Final RX Vref Byte 0 = 62 to rank1
1780 14:44:09.138283 Final RX Vref Byte 1 = 60 to rank1==
1781 14:44:09.142143 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 14:44:09.148301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 14:44:09.148384 ==
1784 14:44:09.148452 DQS Delay:
1785 14:44:09.148513 DQS0 = 0, DQS1 = 0
1786 14:44:09.152137 DQM Delay:
1787 14:44:09.152220 DQM0 = 82, DQM1 = 73
1788 14:44:09.155399 DQ Delay:
1789 14:44:09.158548 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =84
1790 14:44:09.158631 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1791 14:44:09.162285 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1792 14:44:09.164875 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1793 14:44:09.168236
1794 14:44:09.168347
1795 14:44:09.175071 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1796 14:44:09.178229 CH1 RK0: MR19=606, MR18=2B00
1797 14:44:09.184741 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1798 14:44:09.184825
1799 14:44:09.188157 ----->DramcWriteLeveling(PI) begin...
1800 14:44:09.188242 ==
1801 14:44:09.192185 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 14:44:09.195382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 14:44:09.195465 ==
1804 14:44:09.198582 Write leveling (Byte 0): 26 => 26
1805 14:44:09.201869 Write leveling (Byte 1): 27 => 27
1806 14:44:09.205093 DramcWriteLeveling(PI) end<-----
1807 14:44:09.205177
1808 14:44:09.205243 ==
1809 14:44:09.208346 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 14:44:09.211612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 14:44:09.211711 ==
1812 14:44:09.215303 [Gating] SW mode calibration
1813 14:44:09.221363 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 14:44:09.228720 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 14:44:09.231492 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 14:44:09.234671 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1817 14:44:09.242130 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 14:44:09.244732 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 14:44:09.248371 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 14:44:09.255341 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 14:44:09.258330 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 14:44:09.261660 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1823 14:44:09.268265 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1824 14:44:09.272499 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 14:44:09.274989 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 14:44:09.278732 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 14:44:09.285410 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1828 14:44:09.288577 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1829 14:44:09.291994 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 14:44:09.298796 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 14:44:09.302467 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1832 14:44:09.305236 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 14:44:09.312005 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 14:44:09.315641 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 14:44:09.319099 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 14:44:09.325088 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 14:44:09.328901 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 14:44:09.332237 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 14:44:09.335447 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 14:44:09.343194 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1841 14:44:09.345914 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1842 14:44:09.349092 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 14:44:09.355331 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 14:44:09.359346 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 14:44:09.361988 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 14:44:09.369096 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 14:44:09.372304 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1848 14:44:09.375908 0 10 4 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (0 0)
1849 14:44:09.382484 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1850 14:44:09.385553 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 14:44:09.388963 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 14:44:09.392379 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1853 14:44:09.399163 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 14:44:09.402554 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 14:44:09.406368 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 14:44:09.412556 0 11 4 | B1->B0 | 2b2b 3939 | 0 0 | (0 0) (0 0)
1857 14:44:09.415959 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1858 14:44:09.419621 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 14:44:09.426606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 14:44:09.429772 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 14:44:09.433149 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 14:44:09.439589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 14:44:09.442519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1864 14:44:09.446484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1865 14:44:09.452911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 14:44:09.456229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 14:44:09.460344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 14:44:09.463137 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 14:44:09.469747 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 14:44:09.473174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 14:44:09.476484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 14:44:09.482958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 14:44:09.486211 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 14:44:09.490038 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 14:44:09.496047 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 14:44:09.499551 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 14:44:09.502788 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 14:44:09.509852 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 14:44:09.512889 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 14:44:09.517078 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1881 14:44:09.523498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1882 14:44:09.523602 Total UI for P1: 0, mck2ui 16
1883 14:44:09.526702 best dqsien dly found for B0: ( 0, 14, 4)
1884 14:44:09.533115 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 14:44:09.536948 Total UI for P1: 0, mck2ui 16
1886 14:44:09.540086 best dqsien dly found for B1: ( 0, 14, 6)
1887 14:44:09.543548 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1888 14:44:09.546649 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1889 14:44:09.546751
1890 14:44:09.549744 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 14:44:09.553710 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 14:44:09.556613 [Gating] SW calibration Done
1893 14:44:09.556725 ==
1894 14:44:09.559818 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 14:44:09.563385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 14:44:09.563489 ==
1897 14:44:09.566525 RX Vref Scan: 0
1898 14:44:09.566624
1899 14:44:09.566725 RX Vref 0 -> 0, step: 1
1900 14:44:09.566816
1901 14:44:09.569806 RX Delay -130 -> 252, step: 16
1902 14:44:09.573763 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1903 14:44:09.580084 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1904 14:44:09.584161 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1905 14:44:09.587258 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1906 14:44:09.590513 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1907 14:44:09.593654 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1908 14:44:09.600166 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1909 14:44:09.603709 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1910 14:44:09.606956 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1911 14:44:09.610435 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1912 14:44:09.613580 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1913 14:44:09.617345 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1914 14:44:09.624312 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1915 14:44:09.627090 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1916 14:44:09.630623 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1917 14:44:09.634233 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1918 14:44:09.634332 ==
1919 14:44:09.637200 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 14:44:09.644255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 14:44:09.644336 ==
1922 14:44:09.644402 DQS Delay:
1923 14:44:09.644463 DQS0 = 0, DQS1 = 0
1924 14:44:09.647174 DQM Delay:
1925 14:44:09.647276 DQM0 = 82, DQM1 = 77
1926 14:44:09.651687 DQ Delay:
1927 14:44:09.654221 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1928 14:44:09.654321 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1929 14:44:09.657961 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1930 14:44:09.660612 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1931 14:44:09.664711
1932 14:44:09.664810
1933 14:44:09.664911 ==
1934 14:44:09.667606 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 14:44:09.671299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 14:44:09.671407 ==
1937 14:44:09.671499
1938 14:44:09.671597
1939 14:44:09.675105 TX Vref Scan disable
1940 14:44:09.675204 == TX Byte 0 ==
1941 14:44:09.680939 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1942 14:44:09.684497 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1943 14:44:09.684601 == TX Byte 1 ==
1944 14:44:09.687544 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1945 14:44:09.694716 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1946 14:44:09.694817 ==
1947 14:44:09.698514 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 14:44:09.701177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 14:44:09.701289 ==
1950 14:44:09.714528 TX Vref=22, minBit 0, minWin=27, winSum=438
1951 14:44:09.717846 TX Vref=24, minBit 0, minWin=27, winSum=443
1952 14:44:09.720712 TX Vref=26, minBit 1, minWin=27, winSum=443
1953 14:44:09.724175 TX Vref=28, minBit 11, minWin=27, winSum=448
1954 14:44:09.727546 TX Vref=30, minBit 0, minWin=28, winSum=450
1955 14:44:09.731119 TX Vref=32, minBit 0, minWin=28, winSum=453
1956 14:44:09.737810 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1957 14:44:09.737900
1958 14:44:09.740992 Final TX Range 1 Vref 32
1959 14:44:09.741074
1960 14:44:09.741139 ==
1961 14:44:09.744413 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 14:44:09.747801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 14:44:09.747883 ==
1964 14:44:09.747952
1965 14:44:09.751031
1966 14:44:09.751139 TX Vref Scan disable
1967 14:44:09.754570 == TX Byte 0 ==
1968 14:44:09.757473 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1969 14:44:09.761223 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1970 14:44:09.764690 == TX Byte 1 ==
1971 14:44:09.767533 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1972 14:44:09.771021 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1973 14:44:09.775106
1974 14:44:09.775205 [DATLAT]
1975 14:44:09.775297 Freq=800, CH1 RK1
1976 14:44:09.775386
1977 14:44:09.777735 DATLAT Default: 0xa
1978 14:44:09.777832 0, 0xFFFF, sum = 0
1979 14:44:09.781364 1, 0xFFFF, sum = 0
1980 14:44:09.781470 2, 0xFFFF, sum = 0
1981 14:44:09.784542 3, 0xFFFF, sum = 0
1982 14:44:09.784643 4, 0xFFFF, sum = 0
1983 14:44:09.787581 5, 0xFFFF, sum = 0
1984 14:44:09.787682 6, 0xFFFF, sum = 0
1985 14:44:09.791312 7, 0xFFFF, sum = 0
1986 14:44:09.791414 8, 0xFFFF, sum = 0
1987 14:44:09.795014 9, 0x0, sum = 1
1988 14:44:09.795118 10, 0x0, sum = 2
1989 14:44:09.797757 11, 0x0, sum = 3
1990 14:44:09.797860 12, 0x0, sum = 4
1991 14:44:09.801427 best_step = 10
1992 14:44:09.801521
1993 14:44:09.801589 ==
1994 14:44:09.804930 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 14:44:09.808333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 14:44:09.808436 ==
1997 14:44:09.811292 RX Vref Scan: 0
1998 14:44:09.811390
1999 14:44:09.811485 RX Vref 0 -> 0, step: 1
2000 14:44:09.811572
2001 14:44:09.814709 RX Delay -95 -> 252, step: 8
2002 14:44:09.821311 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2003 14:44:09.824813 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2004 14:44:09.828090 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2005 14:44:09.831599 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2006 14:44:09.834858 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2007 14:44:09.837889 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2008 14:44:09.844783 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2009 14:44:09.847990 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2010 14:44:09.851863 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2011 14:44:09.854645 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2012 14:44:09.858067 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2013 14:44:09.864705 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2014 14:44:09.868881 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2015 14:44:09.873070 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2016 14:44:09.874878 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2017 14:44:09.878452 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2018 14:44:09.878561 ==
2019 14:44:09.882484 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 14:44:09.888635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 14:44:09.888740 ==
2022 14:44:09.888834 DQS Delay:
2023 14:44:09.891800 DQS0 = 0, DQS1 = 0
2024 14:44:09.891904 DQM Delay:
2025 14:44:09.891997 DQM0 = 81, DQM1 = 75
2026 14:44:09.895373 DQ Delay:
2027 14:44:09.898872 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2028 14:44:09.901750 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2029 14:44:09.905050 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2030 14:44:09.908462 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2031 14:44:09.908561
2032 14:44:09.908651
2033 14:44:09.915144 [DQSOSCAuto] RK1, (LSB)MR18= 0x242f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2034 14:44:09.918636 CH1 RK1: MR19=606, MR18=242F
2035 14:44:09.925585 CH1_RK1: MR19=0x606, MR18=0x242F, DQSOSC=397, MR23=63, INC=93, DEC=62
2036 14:44:09.928828 [RxdqsGatingPostProcess] freq 800
2037 14:44:09.932086 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 14:44:09.935599 Pre-setting of DQS Precalculation
2039 14:44:09.942240 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 14:44:09.949376 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 14:44:09.955658 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 14:44:09.955775
2043 14:44:09.955877
2044 14:44:09.959027 [Calibration Summary] 1600 Mbps
2045 14:44:09.959136 CH 0, Rank 0
2046 14:44:09.962404 SW Impedance : PASS
2047 14:44:09.965438 DUTY Scan : NO K
2048 14:44:09.965514 ZQ Calibration : PASS
2049 14:44:09.968819 Jitter Meter : NO K
2050 14:44:09.972406 CBT Training : PASS
2051 14:44:09.972488 Write leveling : PASS
2052 14:44:09.975601 RX DQS gating : PASS
2053 14:44:09.975740 RX DQ/DQS(RDDQC) : PASS
2054 14:44:09.979354 TX DQ/DQS : PASS
2055 14:44:09.982481 RX DATLAT : PASS
2056 14:44:09.982572 RX DQ/DQS(Engine): PASS
2057 14:44:09.987072 TX OE : NO K
2058 14:44:09.987154 All Pass.
2059 14:44:09.987219
2060 14:44:09.989504 CH 0, Rank 1
2061 14:44:09.989603 SW Impedance : PASS
2062 14:44:09.992446 DUTY Scan : NO K
2063 14:44:09.995772 ZQ Calibration : PASS
2064 14:44:09.995880 Jitter Meter : NO K
2065 14:44:09.999679 CBT Training : PASS
2066 14:44:10.002757 Write leveling : PASS
2067 14:44:10.002840 RX DQS gating : PASS
2068 14:44:10.006245 RX DQ/DQS(RDDQC) : PASS
2069 14:44:10.006329 TX DQ/DQS : PASS
2070 14:44:10.009301 RX DATLAT : PASS
2071 14:44:10.012582 RX DQ/DQS(Engine): PASS
2072 14:44:10.012662 TX OE : NO K
2073 14:44:10.016052 All Pass.
2074 14:44:10.016126
2075 14:44:10.016188 CH 1, Rank 0
2076 14:44:10.019481 SW Impedance : PASS
2077 14:44:10.019555 DUTY Scan : NO K
2078 14:44:10.022671 ZQ Calibration : PASS
2079 14:44:10.026216 Jitter Meter : NO K
2080 14:44:10.026288 CBT Training : PASS
2081 14:44:10.029578 Write leveling : PASS
2082 14:44:10.032580 RX DQS gating : PASS
2083 14:44:10.032663 RX DQ/DQS(RDDQC) : PASS
2084 14:44:10.036291 TX DQ/DQS : PASS
2085 14:44:10.036373 RX DATLAT : PASS
2086 14:44:10.039520 RX DQ/DQS(Engine): PASS
2087 14:44:10.043512 TX OE : NO K
2088 14:44:10.043606 All Pass.
2089 14:44:10.043670
2090 14:44:10.043730 CH 1, Rank 1
2091 14:44:10.046645 SW Impedance : PASS
2092 14:44:10.049472 DUTY Scan : NO K
2093 14:44:10.049553 ZQ Calibration : PASS
2094 14:44:10.052898 Jitter Meter : NO K
2095 14:44:10.056074 CBT Training : PASS
2096 14:44:10.056157 Write leveling : PASS
2097 14:44:10.059849 RX DQS gating : PASS
2098 14:44:10.063544 RX DQ/DQS(RDDQC) : PASS
2099 14:44:10.063626 TX DQ/DQS : PASS
2100 14:44:10.066269 RX DATLAT : PASS
2101 14:44:10.066351 RX DQ/DQS(Engine): PASS
2102 14:44:10.070403 TX OE : NO K
2103 14:44:10.070485 All Pass.
2104 14:44:10.070550
2105 14:44:10.073312 DramC Write-DBI off
2106 14:44:10.076364 PER_BANK_REFRESH: Hybrid Mode
2107 14:44:10.076446 TX_TRACKING: ON
2108 14:44:10.079773 [GetDramInforAfterCalByMRR] Vendor 6.
2109 14:44:10.083104 [GetDramInforAfterCalByMRR] Revision 606.
2110 14:44:10.087642 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 14:44:10.089477 MR0 0x3b3b
2112 14:44:10.089559 MR8 0x5151
2113 14:44:10.093755 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 14:44:10.093838
2115 14:44:10.096627 MR0 0x3b3b
2116 14:44:10.096709 MR8 0x5151
2117 14:44:10.100671 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 14:44:10.100753
2119 14:44:10.109759 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 14:44:10.113829 [FAST_K] Save calibration result to emmc
2121 14:44:10.116906 [FAST_K] Save calibration result to emmc
2122 14:44:10.120256 dram_init: config_dvfs: 1
2123 14:44:10.123443 dramc_set_vcore_voltage set vcore to 662500
2124 14:44:10.123526 Read voltage for 1200, 2
2125 14:44:10.126645 Vio18 = 0
2126 14:44:10.126727 Vcore = 662500
2127 14:44:10.126793 Vdram = 0
2128 14:44:10.130883 Vddq = 0
2129 14:44:10.130965 Vmddr = 0
2130 14:44:10.133379 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 14:44:10.140302 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 14:44:10.143811 MEM_TYPE=3, freq_sel=15
2133 14:44:10.147751 sv_algorithm_assistance_LP4_1600
2134 14:44:10.150211 ============ PULL DRAM RESETB DOWN ============
2135 14:44:10.153794 ========== PULL DRAM RESETB DOWN end =========
2136 14:44:10.157095 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 14:44:10.160208 ===================================
2138 14:44:10.163816 LPDDR4 DRAM CONFIGURATION
2139 14:44:10.167514 ===================================
2140 14:44:10.170507 EX_ROW_EN[0] = 0x0
2141 14:44:10.170590 EX_ROW_EN[1] = 0x0
2142 14:44:10.173700 LP4Y_EN = 0x0
2143 14:44:10.173782 WORK_FSP = 0x0
2144 14:44:10.177186 WL = 0x4
2145 14:44:10.177269 RL = 0x4
2146 14:44:10.180652 BL = 0x2
2147 14:44:10.180792 RPST = 0x0
2148 14:44:10.184222 RD_PRE = 0x0
2149 14:44:10.184337 WR_PRE = 0x1
2150 14:44:10.187148 WR_PST = 0x0
2151 14:44:10.187256 DBI_WR = 0x0
2152 14:44:10.190901 DBI_RD = 0x0
2153 14:44:10.191001 OTF = 0x1
2154 14:44:10.194215 ===================================
2155 14:44:10.197060 ===================================
2156 14:44:10.200452 ANA top config
2157 14:44:10.204322 ===================================
2158 14:44:10.204422 DLL_ASYNC_EN = 0
2159 14:44:10.207397 ALL_SLAVE_EN = 0
2160 14:44:10.210735 NEW_RANK_MODE = 1
2161 14:44:10.213701 DLL_IDLE_MODE = 1
2162 14:44:10.218043 LP45_APHY_COMB_EN = 1
2163 14:44:10.218115 TX_ODT_DIS = 1
2164 14:44:10.221309 NEW_8X_MODE = 1
2165 14:44:10.223943 ===================================
2166 14:44:10.227547 ===================================
2167 14:44:10.231867 data_rate = 2400
2168 14:44:10.234324 CKR = 1
2169 14:44:10.237309 DQ_P2S_RATIO = 8
2170 14:44:10.240568 ===================================
2171 14:44:10.240650 CA_P2S_RATIO = 8
2172 14:44:10.244451 DQ_CA_OPEN = 0
2173 14:44:10.247227 DQ_SEMI_OPEN = 0
2174 14:44:10.250765 CA_SEMI_OPEN = 0
2175 14:44:10.253794 CA_FULL_RATE = 0
2176 14:44:10.257271 DQ_CKDIV4_EN = 0
2177 14:44:10.257349 CA_CKDIV4_EN = 0
2178 14:44:10.260970 CA_PREDIV_EN = 0
2179 14:44:10.264431 PH8_DLY = 17
2180 14:44:10.267284 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 14:44:10.270556 DQ_AAMCK_DIV = 4
2182 14:44:10.270631 CA_AAMCK_DIV = 4
2183 14:44:10.274202 CA_ADMCK_DIV = 4
2184 14:44:10.277822 DQ_TRACK_CA_EN = 0
2185 14:44:10.280950 CA_PICK = 1200
2186 14:44:10.284297 CA_MCKIO = 1200
2187 14:44:10.287598 MCKIO_SEMI = 0
2188 14:44:10.291078 PLL_FREQ = 2366
2189 14:44:10.291177 DQ_UI_PI_RATIO = 32
2190 14:44:10.294581 CA_UI_PI_RATIO = 0
2191 14:44:10.297547 ===================================
2192 14:44:10.301127 ===================================
2193 14:44:10.304363 memory_type:LPDDR4
2194 14:44:10.307661 GP_NUM : 10
2195 14:44:10.307734 SRAM_EN : 1
2196 14:44:10.312356 MD32_EN : 0
2197 14:44:10.315416 ===================================
2198 14:44:10.318794 [ANA_INIT] >>>>>>>>>>>>>>
2199 14:44:10.318870 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 14:44:10.320967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 14:44:10.325444 ===================================
2202 14:44:10.327587 data_rate = 2400,PCW = 0X5b00
2203 14:44:10.331757 ===================================
2204 14:44:10.334322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 14:44:10.341157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 14:44:10.348093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 14:44:10.351079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 14:44:10.354580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 14:44:10.358275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 14:44:10.361772 [ANA_INIT] flow start
2211 14:44:10.361855 [ANA_INIT] PLL >>>>>>>>
2212 14:44:10.364773 [ANA_INIT] PLL <<<<<<<<
2213 14:44:10.368196 [ANA_INIT] MIDPI >>>>>>>>
2214 14:44:10.368279 [ANA_INIT] MIDPI <<<<<<<<
2215 14:44:10.371771 [ANA_INIT] DLL >>>>>>>>
2216 14:44:10.374973 [ANA_INIT] DLL <<<<<<<<
2217 14:44:10.375057 [ANA_INIT] flow end
2218 14:44:10.378777 ============ LP4 DIFF to SE enter ============
2219 14:44:10.384903 ============ LP4 DIFF to SE exit ============
2220 14:44:10.385042 [ANA_INIT] <<<<<<<<<<<<<
2221 14:44:10.389157 [Flow] Enable top DCM control >>>>>
2222 14:44:10.391444 [Flow] Enable top DCM control <<<<<
2223 14:44:10.395548 Enable DLL master slave shuffle
2224 14:44:10.401488 ==============================================================
2225 14:44:10.401566 Gating Mode config
2226 14:44:10.408290 ==============================================================
2227 14:44:10.412438 Config description:
2228 14:44:10.418541 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 14:44:10.425354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 14:44:10.431724 SELPH_MODE 0: By rank 1: By Phase
2231 14:44:10.438229 ==============================================================
2232 14:44:10.438312 GAT_TRACK_EN = 1
2233 14:44:10.441816 RX_GATING_MODE = 2
2234 14:44:10.445681 RX_GATING_TRACK_MODE = 2
2235 14:44:10.448788 SELPH_MODE = 1
2236 14:44:10.451873 PICG_EARLY_EN = 1
2237 14:44:10.455547 VALID_LAT_VALUE = 1
2238 14:44:10.461926 ==============================================================
2239 14:44:10.465120 Enter into Gating configuration >>>>
2240 14:44:10.469359 Exit from Gating configuration <<<<
2241 14:44:10.469442 Enter into DVFS_PRE_config >>>>>
2242 14:44:10.482342 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 14:44:10.485825 Exit from DVFS_PRE_config <<<<<
2244 14:44:10.489391 Enter into PICG configuration >>>>
2245 14:44:10.489474 Exit from PICG configuration <<<<
2246 14:44:10.492157 [RX_INPUT] configuration >>>>>
2247 14:44:10.496018 [RX_INPUT] configuration <<<<<
2248 14:44:10.502318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 14:44:10.505823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 14:44:10.512216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 14:44:10.519277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 14:44:10.525864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 14:44:10.533556 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 14:44:10.535820 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 14:44:10.539438 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 14:44:10.542833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 14:44:10.549162 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 14:44:10.552457 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 14:44:10.555684 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 14:44:10.559480 ===================================
2261 14:44:10.562886 LPDDR4 DRAM CONFIGURATION
2262 14:44:10.566072 ===================================
2263 14:44:10.566155 EX_ROW_EN[0] = 0x0
2264 14:44:10.569862 EX_ROW_EN[1] = 0x0
2265 14:44:10.572928 LP4Y_EN = 0x0
2266 14:44:10.573044 WORK_FSP = 0x0
2267 14:44:10.576425 WL = 0x4
2268 14:44:10.576508 RL = 0x4
2269 14:44:10.579610 BL = 0x2
2270 14:44:10.579692 RPST = 0x0
2271 14:44:10.583011 RD_PRE = 0x0
2272 14:44:10.583127 WR_PRE = 0x1
2273 14:44:10.586453 WR_PST = 0x0
2274 14:44:10.586547 DBI_WR = 0x0
2275 14:44:10.589641 DBI_RD = 0x0
2276 14:44:10.589740 OTF = 0x1
2277 14:44:10.592800 ===================================
2278 14:44:10.596068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 14:44:10.602704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 14:44:10.606600 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 14:44:10.610076 ===================================
2282 14:44:10.612876 LPDDR4 DRAM CONFIGURATION
2283 14:44:10.616200 ===================================
2284 14:44:10.616274 EX_ROW_EN[0] = 0x10
2285 14:44:10.619939 EX_ROW_EN[1] = 0x0
2286 14:44:10.620045 LP4Y_EN = 0x0
2287 14:44:10.623321 WORK_FSP = 0x0
2288 14:44:10.623418 WL = 0x4
2289 14:44:10.626355 RL = 0x4
2290 14:44:10.626426 BL = 0x2
2291 14:44:10.629532 RPST = 0x0
2292 14:44:10.629603 RD_PRE = 0x0
2293 14:44:10.634068 WR_PRE = 0x1
2294 14:44:10.634144 WR_PST = 0x0
2295 14:44:10.636666 DBI_WR = 0x0
2296 14:44:10.636753 DBI_RD = 0x0
2297 14:44:10.640439 OTF = 0x1
2298 14:44:10.643435 ===================================
2299 14:44:10.650292 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 14:44:10.650414 ==
2301 14:44:10.653246 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 14:44:10.656430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 14:44:10.656614 ==
2304 14:44:10.659868 [Duty_Offset_Calibration]
2305 14:44:10.659976 B0:2 B1:-1 CA:1
2306 14:44:10.660068
2307 14:44:10.663073 [DutyScan_Calibration_Flow] k_type=0
2308 14:44:10.672850
2309 14:44:10.672957 ==CLK 0==
2310 14:44:10.676124 Final CLK duty delay cell = -4
2311 14:44:10.679777 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2312 14:44:10.682851 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2313 14:44:10.686852 [-4] AVG Duty = 4953%(X100)
2314 14:44:10.686926
2315 14:44:10.690392 CH0 CLK Duty spec in!! Max-Min= 156%
2316 14:44:10.692859 [DutyScan_Calibration_Flow] ====Done====
2317 14:44:10.692964
2318 14:44:10.696926 [DutyScan_Calibration_Flow] k_type=1
2319 14:44:10.710689
2320 14:44:10.710777 ==DQS 0 ==
2321 14:44:10.714060 Final DQS duty delay cell = -4
2322 14:44:10.717448 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2323 14:44:10.720970 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2324 14:44:10.724509 [-4] AVG Duty = 4938%(X100)
2325 14:44:10.724590
2326 14:44:10.724654 ==DQS 1 ==
2327 14:44:10.728024 Final DQS duty delay cell = -4
2328 14:44:10.730938 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2329 14:44:10.734431 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2330 14:44:10.737747 [-4] AVG Duty = 5062%(X100)
2331 14:44:10.737830
2332 14:44:10.741095 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2333 14:44:10.741176
2334 14:44:10.744564 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2335 14:44:10.748358 [DutyScan_Calibration_Flow] ====Done====
2336 14:44:10.748439
2337 14:44:10.751314 [DutyScan_Calibration_Flow] k_type=3
2338 14:44:10.768117
2339 14:44:10.768199 ==DQM 0 ==
2340 14:44:10.771677 Final DQM duty delay cell = 0
2341 14:44:10.774830 [0] MAX Duty = 5000%(X100), DQS PI = 54
2342 14:44:10.779139 [0] MIN Duty = 4907%(X100), DQS PI = 2
2343 14:44:10.779221 [0] AVG Duty = 4953%(X100)
2344 14:44:10.781424
2345 14:44:10.781505 ==DQM 1 ==
2346 14:44:10.784985 Final DQM duty delay cell = 0
2347 14:44:10.788425 [0] MAX Duty = 5156%(X100), DQS PI = 62
2348 14:44:10.792240 [0] MIN Duty = 4969%(X100), DQS PI = 10
2349 14:44:10.792321 [0] AVG Duty = 5062%(X100)
2350 14:44:10.792386
2351 14:44:10.798284 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2352 14:44:10.798365
2353 14:44:10.801939 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2354 14:44:10.804993 [DutyScan_Calibration_Flow] ====Done====
2355 14:44:10.805088
2356 14:44:10.808717 [DutyScan_Calibration_Flow] k_type=2
2357 14:44:10.824497
2358 14:44:10.824581 ==DQ 0 ==
2359 14:44:10.827060 Final DQ duty delay cell = -4
2360 14:44:10.830362 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2361 14:44:10.833943 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2362 14:44:10.837255 [-4] AVG Duty = 4953%(X100)
2363 14:44:10.837338
2364 14:44:10.837403 ==DQ 1 ==
2365 14:44:10.840546 Final DQ duty delay cell = 0
2366 14:44:10.843822 [0] MAX Duty = 5031%(X100), DQS PI = 18
2367 14:44:10.847261 [0] MIN Duty = 4907%(X100), DQS PI = 46
2368 14:44:10.847343 [0] AVG Duty = 4969%(X100)
2369 14:44:10.850536
2370 14:44:10.854230 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2371 14:44:10.854313
2372 14:44:10.857793 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2373 14:44:10.860846 [DutyScan_Calibration_Flow] ====Done====
2374 14:44:10.860930 ==
2375 14:44:10.864084 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 14:44:10.867327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 14:44:10.867410 ==
2378 14:44:10.870705 [Duty_Offset_Calibration]
2379 14:44:10.870788 B0:1 B1:1 CA:2
2380 14:44:10.870878
2381 14:44:10.874089 [DutyScan_Calibration_Flow] k_type=0
2382 14:44:10.884042
2383 14:44:10.884125 ==CLK 0==
2384 14:44:10.887628 Final CLK duty delay cell = 0
2385 14:44:10.890818 [0] MAX Duty = 5125%(X100), DQS PI = 24
2386 14:44:10.894134 [0] MIN Duty = 4938%(X100), DQS PI = 40
2387 14:44:10.894217 [0] AVG Duty = 5031%(X100)
2388 14:44:10.894283
2389 14:44:10.897676 CH1 CLK Duty spec in!! Max-Min= 187%
2390 14:44:10.904107 [DutyScan_Calibration_Flow] ====Done====
2391 14:44:10.904190
2392 14:44:10.907350 [DutyScan_Calibration_Flow] k_type=1
2393 14:44:10.923435
2394 14:44:10.923518 ==DQS 0 ==
2395 14:44:10.927366 Final DQS duty delay cell = 0
2396 14:44:10.930178 [0] MAX Duty = 5031%(X100), DQS PI = 18
2397 14:44:10.933344 [0] MIN Duty = 4813%(X100), DQS PI = 50
2398 14:44:10.933428 [0] AVG Duty = 4922%(X100)
2399 14:44:10.936811
2400 14:44:10.936893 ==DQS 1 ==
2401 14:44:10.940075 Final DQS duty delay cell = 0
2402 14:44:10.943742 [0] MAX Duty = 5062%(X100), DQS PI = 36
2403 14:44:10.947139 [0] MIN Duty = 4875%(X100), DQS PI = 16
2404 14:44:10.947223 [0] AVG Duty = 4968%(X100)
2405 14:44:10.950511
2406 14:44:10.954025 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2407 14:44:10.954108
2408 14:44:10.956937 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2409 14:44:10.960609 [DutyScan_Calibration_Flow] ====Done====
2410 14:44:10.960691
2411 14:44:10.963675 [DutyScan_Calibration_Flow] k_type=3
2412 14:44:10.980283
2413 14:44:10.980366 ==DQM 0 ==
2414 14:44:10.983542 Final DQM duty delay cell = 0
2415 14:44:10.986920 [0] MAX Duty = 5093%(X100), DQS PI = 18
2416 14:44:10.989834 [0] MIN Duty = 4875%(X100), DQS PI = 50
2417 14:44:10.989916 [0] AVG Duty = 4984%(X100)
2418 14:44:10.993527
2419 14:44:10.993609 ==DQM 1 ==
2420 14:44:10.996555 Final DQM duty delay cell = 0
2421 14:44:11.000565 [0] MAX Duty = 5156%(X100), DQS PI = 62
2422 14:44:11.003752 [0] MIN Duty = 4938%(X100), DQS PI = 22
2423 14:44:11.003835 [0] AVG Duty = 5047%(X100)
2424 14:44:11.006679
2425 14:44:11.010014 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2426 14:44:11.010096
2427 14:44:11.013487 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2428 14:44:11.017342 [DutyScan_Calibration_Flow] ====Done====
2429 14:44:11.017424
2430 14:44:11.020101 [DutyScan_Calibration_Flow] k_type=2
2431 14:44:11.036473
2432 14:44:11.036555 ==DQ 0 ==
2433 14:44:11.040196 Final DQ duty delay cell = 0
2434 14:44:11.043399 [0] MAX Duty = 5156%(X100), DQS PI = 18
2435 14:44:11.046272 [0] MIN Duty = 4907%(X100), DQS PI = 50
2436 14:44:11.046355 [0] AVG Duty = 5031%(X100)
2437 14:44:11.046421
2438 14:44:11.049930 ==DQ 1 ==
2439 14:44:11.053423 Final DQ duty delay cell = 0
2440 14:44:11.056646 [0] MAX Duty = 5093%(X100), DQS PI = 10
2441 14:44:11.059855 [0] MIN Duty = 5000%(X100), DQS PI = 2
2442 14:44:11.059938 [0] AVG Duty = 5046%(X100)
2443 14:44:11.060003
2444 14:44:11.064014 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2445 14:44:11.064097
2446 14:44:11.066947 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2447 14:44:11.070162 [DutyScan_Calibration_Flow] ====Done====
2448 14:44:11.075486 nWR fixed to 30
2449 14:44:11.078691 [ModeRegInit_LP4] CH0 RK0
2450 14:44:11.078773 [ModeRegInit_LP4] CH0 RK1
2451 14:44:11.082215 [ModeRegInit_LP4] CH1 RK0
2452 14:44:11.085473 [ModeRegInit_LP4] CH1 RK1
2453 14:44:11.085556 match AC timing 7
2454 14:44:11.092376 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 14:44:11.095365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 14:44:11.099045 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 14:44:11.105518 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 14:44:11.110412 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 14:44:11.110494 ==
2460 14:44:11.112061 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 14:44:11.115556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 14:44:11.115640 ==
2463 14:44:11.122212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 14:44:11.128859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 14:44:11.136555 [CA 0] Center 40 (10~71) winsize 62
2466 14:44:11.140233 [CA 1] Center 39 (9~70) winsize 62
2467 14:44:11.143065 [CA 2] Center 36 (6~67) winsize 62
2468 14:44:11.146231 [CA 3] Center 35 (5~66) winsize 62
2469 14:44:11.149930 [CA 4] Center 34 (4~65) winsize 62
2470 14:44:11.153390 [CA 5] Center 34 (4~64) winsize 61
2471 14:44:11.153473
2472 14:44:11.156931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2473 14:44:11.157053
2474 14:44:11.159700 [CATrainingPosCal] consider 1 rank data
2475 14:44:11.163475 u2DelayCellTimex100 = 270/100 ps
2476 14:44:11.166529 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2477 14:44:11.170949 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2478 14:44:11.176514 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2479 14:44:11.179826 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2480 14:44:11.183468 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2481 14:44:11.186885 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2482 14:44:11.186968
2483 14:44:11.190293 CA PerBit enable=1, Macro0, CA PI delay=34
2484 14:44:11.190375
2485 14:44:11.193684 [CBTSetCACLKResult] CA Dly = 34
2486 14:44:11.193766 CS Dly: 7 (0~38)
2487 14:44:11.193831 ==
2488 14:44:11.197018 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 14:44:11.203907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 14:44:11.203990 ==
2491 14:44:11.207135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 14:44:11.213494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 14:44:11.222548 [CA 0] Center 39 (9~70) winsize 62
2494 14:44:11.225725 [CA 1] Center 40 (10~70) winsize 61
2495 14:44:11.228942 [CA 2] Center 36 (6~67) winsize 62
2496 14:44:11.232932 [CA 3] Center 36 (5~67) winsize 63
2497 14:44:11.235998 [CA 4] Center 34 (4~65) winsize 62
2498 14:44:11.239049 [CA 5] Center 34 (4~64) winsize 61
2499 14:44:11.239131
2500 14:44:11.242860 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 14:44:11.242942
2502 14:44:11.245842 [CATrainingPosCal] consider 2 rank data
2503 14:44:11.249589 u2DelayCellTimex100 = 270/100 ps
2504 14:44:11.253007 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2505 14:44:11.256213 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 14:44:11.262648 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2507 14:44:11.266015 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2508 14:44:11.269457 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2509 14:44:11.273214 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2510 14:44:11.273297
2511 14:44:11.276399 CA PerBit enable=1, Macro0, CA PI delay=34
2512 14:44:11.276482
2513 14:44:11.280334 [CBTSetCACLKResult] CA Dly = 34
2514 14:44:11.280416 CS Dly: 8 (0~41)
2515 14:44:11.280482
2516 14:44:11.283100 ----->DramcWriteLeveling(PI) begin...
2517 14:44:11.283184 ==
2518 14:44:11.287602 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 14:44:11.292538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 14:44:11.292621 ==
2521 14:44:11.296686 Write leveling (Byte 0): 31 => 31
2522 14:44:11.299664 Write leveling (Byte 1): 29 => 29
2523 14:44:11.299746 DramcWriteLeveling(PI) end<-----
2524 14:44:11.303234
2525 14:44:11.303316 ==
2526 14:44:11.306386 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 14:44:11.309546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 14:44:11.309629 ==
2529 14:44:11.313327 [Gating] SW mode calibration
2530 14:44:11.319547 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 14:44:11.322851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 14:44:11.329692 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 14:44:11.332823 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2534 14:44:11.336046 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2535 14:44:11.342876 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 14:44:11.346584 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 14:44:11.350073 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 14:44:11.356399 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 14:44:11.359810 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 14:44:11.362920 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2541 14:44:11.366515 1 0 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2542 14:44:11.373198 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 14:44:11.376732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 14:44:11.379929 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 14:44:11.386827 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 14:44:11.390532 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 14:44:11.393311 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 14:44:11.399992 1 1 0 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
2549 14:44:11.403443 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2550 14:44:11.406936 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 14:44:11.413630 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 14:44:11.417190 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 14:44:11.420391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 14:44:11.426814 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 14:44:11.430426 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 14:44:11.433640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2557 14:44:11.437187 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2558 14:44:11.443180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 14:44:11.447327 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 14:44:11.450257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 14:44:11.456906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 14:44:11.460404 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 14:44:11.463731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 14:44:11.470136 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 14:44:11.473495 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 14:44:11.476833 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 14:44:11.484261 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 14:44:11.487536 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 14:44:11.490561 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 14:44:11.497677 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 14:44:11.500788 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 14:44:11.504234 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2573 14:44:11.507283 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 14:44:11.511150 Total UI for P1: 0, mck2ui 16
2575 14:44:11.513966 best dqsien dly found for B0: ( 1, 4, 0)
2576 14:44:11.520704 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 14:44:11.520792 Total UI for P1: 0, mck2ui 16
2578 14:44:11.527540 best dqsien dly found for B1: ( 1, 4, 2)
2579 14:44:11.530582 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2580 14:44:11.534307 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2581 14:44:11.534399
2582 14:44:11.537626 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 14:44:11.540849 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2584 14:44:11.543927 [Gating] SW calibration Done
2585 14:44:11.544011 ==
2586 14:44:11.547706 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 14:44:11.550883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 14:44:11.550967 ==
2589 14:44:11.551033 RX Vref Scan: 0
2590 14:44:11.554612
2591 14:44:11.554695 RX Vref 0 -> 0, step: 1
2592 14:44:11.554760
2593 14:44:11.557252 RX Delay -40 -> 252, step: 8
2594 14:44:11.560762 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2595 14:44:11.563861 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2596 14:44:11.570751 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2597 14:44:11.574266 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2598 14:44:11.578106 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2599 14:44:11.582378 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2600 14:44:11.584328 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2601 14:44:11.591010 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2602 14:44:11.594463 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2603 14:44:11.598224 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2604 14:44:11.600716 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2605 14:44:11.604186 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2606 14:44:11.611105 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2607 14:44:11.614124 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2608 14:44:11.617856 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2609 14:44:11.620787 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2610 14:44:11.620870 ==
2611 14:44:11.624948 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 14:44:11.631610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 14:44:11.631711 ==
2614 14:44:11.631812 DQS Delay:
2615 14:44:11.631901 DQS0 = 0, DQS1 = 0
2616 14:44:11.635137 DQM Delay:
2617 14:44:11.635209 DQM0 = 115, DQM1 = 107
2618 14:44:11.637678 DQ Delay:
2619 14:44:11.640807 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2620 14:44:11.644624 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2621 14:44:11.648213 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2622 14:44:11.650655 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2623 14:44:11.650737
2624 14:44:11.650803
2625 14:44:11.650864 ==
2626 14:44:11.654161 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 14:44:11.657982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 14:44:11.658091 ==
2629 14:44:11.658193
2630 14:44:11.658283
2631 14:44:11.661162 TX Vref Scan disable
2632 14:44:11.664023 == TX Byte 0 ==
2633 14:44:11.667990 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2634 14:44:11.671626 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2635 14:44:11.674165 == TX Byte 1 ==
2636 14:44:11.677807 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2637 14:44:11.681338 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2638 14:44:11.681414 ==
2639 14:44:11.684517 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 14:44:11.688126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 14:44:11.690982 ==
2642 14:44:11.701195 TX Vref=22, minBit 1, minWin=24, winSum=413
2643 14:44:11.704891 TX Vref=24, minBit 7, minWin=24, winSum=419
2644 14:44:11.708388 TX Vref=26, minBit 0, minWin=26, winSum=426
2645 14:44:11.711093 TX Vref=28, minBit 0, minWin=26, winSum=431
2646 14:44:11.714557 TX Vref=30, minBit 0, minWin=26, winSum=433
2647 14:44:11.717944 TX Vref=32, minBit 0, minWin=26, winSum=431
2648 14:44:11.725269 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
2649 14:44:11.725348
2650 14:44:11.728332 Final TX Range 1 Vref 30
2651 14:44:11.728413
2652 14:44:11.728480 ==
2653 14:44:11.731403 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 14:44:11.735611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 14:44:11.735694 ==
2656 14:44:11.735762
2657 14:44:11.735834
2658 14:44:11.738265 TX Vref Scan disable
2659 14:44:11.741496 == TX Byte 0 ==
2660 14:44:11.744728 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2661 14:44:11.748182 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2662 14:44:11.751398 == TX Byte 1 ==
2663 14:44:11.755087 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2664 14:44:11.758412 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2665 14:44:11.758491
2666 14:44:11.761528 [DATLAT]
2667 14:44:11.761636 Freq=1200, CH0 RK0
2668 14:44:11.761715
2669 14:44:11.765067 DATLAT Default: 0xd
2670 14:44:11.765147 0, 0xFFFF, sum = 0
2671 14:44:11.768327 1, 0xFFFF, sum = 0
2672 14:44:11.768412 2, 0xFFFF, sum = 0
2673 14:44:11.771850 3, 0xFFFF, sum = 0
2674 14:44:11.771926 4, 0xFFFF, sum = 0
2675 14:44:11.775157 5, 0xFFFF, sum = 0
2676 14:44:11.775240 6, 0xFFFF, sum = 0
2677 14:44:11.779010 7, 0xFFFF, sum = 0
2678 14:44:11.779091 8, 0xFFFF, sum = 0
2679 14:44:11.781725 9, 0xFFFF, sum = 0
2680 14:44:11.781804 10, 0xFFFF, sum = 0
2681 14:44:11.785193 11, 0xFFFF, sum = 0
2682 14:44:11.785276 12, 0x0, sum = 1
2683 14:44:11.789394 13, 0x0, sum = 2
2684 14:44:11.789477 14, 0x0, sum = 3
2685 14:44:11.791917 15, 0x0, sum = 4
2686 14:44:11.791998 best_step = 13
2687 14:44:11.792064
2688 14:44:11.792126 ==
2689 14:44:11.795718 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 14:44:11.798638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 14:44:11.801780 ==
2692 14:44:11.801857 RX Vref Scan: 1
2693 14:44:11.801920
2694 14:44:11.805242 Set Vref Range= 32 -> 127
2695 14:44:11.805318
2696 14:44:11.808859 RX Vref 32 -> 127, step: 1
2697 14:44:11.808931
2698 14:44:11.809028 RX Delay -21 -> 252, step: 4
2699 14:44:11.809097
2700 14:44:11.812201 Set Vref, RX VrefLevel [Byte0]: 32
2701 14:44:11.815601 [Byte1]: 32
2702 14:44:11.820045
2703 14:44:11.820119 Set Vref, RX VrefLevel [Byte0]: 33
2704 14:44:11.822961 [Byte1]: 33
2705 14:44:11.827578
2706 14:44:11.827653 Set Vref, RX VrefLevel [Byte0]: 34
2707 14:44:11.830702 [Byte1]: 34
2708 14:44:11.836058
2709 14:44:11.836137 Set Vref, RX VrefLevel [Byte0]: 35
2710 14:44:11.838812 [Byte1]: 35
2711 14:44:11.843532
2712 14:44:11.843613 Set Vref, RX VrefLevel [Byte0]: 36
2713 14:44:11.846628 [Byte1]: 36
2714 14:44:11.851544
2715 14:44:11.851624 Set Vref, RX VrefLevel [Byte0]: 37
2716 14:44:11.854760 [Byte1]: 37
2717 14:44:11.859827
2718 14:44:11.859908 Set Vref, RX VrefLevel [Byte0]: 38
2719 14:44:11.862522 [Byte1]: 38
2720 14:44:11.867118
2721 14:44:11.867195 Set Vref, RX VrefLevel [Byte0]: 39
2722 14:44:11.870189 [Byte1]: 39
2723 14:44:11.874967
2724 14:44:11.875044 Set Vref, RX VrefLevel [Byte0]: 40
2725 14:44:11.878788 [Byte1]: 40
2726 14:44:11.883169
2727 14:44:11.883255 Set Vref, RX VrefLevel [Byte0]: 41
2728 14:44:11.886735 [Byte1]: 41
2729 14:44:11.890667
2730 14:44:11.890752 Set Vref, RX VrefLevel [Byte0]: 42
2731 14:44:11.894501 [Byte1]: 42
2732 14:44:11.898990
2733 14:44:11.899064 Set Vref, RX VrefLevel [Byte0]: 43
2734 14:44:11.901759 [Byte1]: 43
2735 14:44:11.906695
2736 14:44:11.906773 Set Vref, RX VrefLevel [Byte0]: 44
2737 14:44:11.910147 [Byte1]: 44
2738 14:44:11.914777
2739 14:44:11.914856 Set Vref, RX VrefLevel [Byte0]: 45
2740 14:44:11.917955 [Byte1]: 45
2741 14:44:11.922306
2742 14:44:11.922378 Set Vref, RX VrefLevel [Byte0]: 46
2743 14:44:11.926175 [Byte1]: 46
2744 14:44:11.930938
2745 14:44:11.931029 Set Vref, RX VrefLevel [Byte0]: 47
2746 14:44:11.934843 [Byte1]: 47
2747 14:44:11.938461
2748 14:44:11.938543 Set Vref, RX VrefLevel [Byte0]: 48
2749 14:44:11.941577 [Byte1]: 48
2750 14:44:11.946006
2751 14:44:11.946082 Set Vref, RX VrefLevel [Byte0]: 49
2752 14:44:11.949401 [Byte1]: 49
2753 14:44:11.954233
2754 14:44:11.954309 Set Vref, RX VrefLevel [Byte0]: 50
2755 14:44:11.958074 [Byte1]: 50
2756 14:44:11.962154
2757 14:44:11.962227 Set Vref, RX VrefLevel [Byte0]: 51
2758 14:44:11.965395 [Byte1]: 51
2759 14:44:11.970143
2760 14:44:11.970224 Set Vref, RX VrefLevel [Byte0]: 52
2761 14:44:11.973440 [Byte1]: 52
2762 14:44:11.978298
2763 14:44:11.978377 Set Vref, RX VrefLevel [Byte0]: 53
2764 14:44:11.981177 [Byte1]: 53
2765 14:44:11.986004
2766 14:44:11.986089 Set Vref, RX VrefLevel [Byte0]: 54
2767 14:44:11.989290 [Byte1]: 54
2768 14:44:11.993861
2769 14:44:11.993951 Set Vref, RX VrefLevel [Byte0]: 55
2770 14:44:11.997342 [Byte1]: 55
2771 14:44:12.001580
2772 14:44:12.001653 Set Vref, RX VrefLevel [Byte0]: 56
2773 14:44:12.005097 [Byte1]: 56
2774 14:44:12.009703
2775 14:44:12.009808 Set Vref, RX VrefLevel [Byte0]: 57
2776 14:44:12.013198 [Byte1]: 57
2777 14:44:12.018042
2778 14:44:12.018118 Set Vref, RX VrefLevel [Byte0]: 58
2779 14:44:12.020945 [Byte1]: 58
2780 14:44:12.025579
2781 14:44:12.025655 Set Vref, RX VrefLevel [Byte0]: 59
2782 14:44:12.028640 [Byte1]: 59
2783 14:44:12.033382
2784 14:44:12.033458 Set Vref, RX VrefLevel [Byte0]: 60
2785 14:44:12.036875 [Byte1]: 60
2786 14:44:12.041506
2787 14:44:12.041581 Set Vref, RX VrefLevel [Byte0]: 61
2788 14:44:12.045163 [Byte1]: 61
2789 14:44:12.049594
2790 14:44:12.049677 Set Vref, RX VrefLevel [Byte0]: 62
2791 14:44:12.053075 [Byte1]: 62
2792 14:44:12.057274
2793 14:44:12.057351 Set Vref, RX VrefLevel [Byte0]: 63
2794 14:44:12.060622 [Byte1]: 63
2795 14:44:12.065109
2796 14:44:12.065186 Set Vref, RX VrefLevel [Byte0]: 64
2797 14:44:12.068750 [Byte1]: 64
2798 14:44:12.072852
2799 14:44:12.072930 Set Vref, RX VrefLevel [Byte0]: 65
2800 14:44:12.076656 [Byte1]: 65
2801 14:44:12.081463
2802 14:44:12.081566 Set Vref, RX VrefLevel [Byte0]: 66
2803 14:44:12.084743 [Byte1]: 66
2804 14:44:12.088783
2805 14:44:12.088888 Set Vref, RX VrefLevel [Byte0]: 67
2806 14:44:12.092486 [Byte1]: 67
2807 14:44:12.097426
2808 14:44:12.097503 Set Vref, RX VrefLevel [Byte0]: 68
2809 14:44:12.100438 [Byte1]: 68
2810 14:44:12.104668
2811 14:44:12.104750 Final RX Vref Byte 0 = 53 to rank0
2812 14:44:12.108622 Final RX Vref Byte 1 = 51 to rank0
2813 14:44:12.111591 Final RX Vref Byte 0 = 53 to rank1
2814 14:44:12.114933 Final RX Vref Byte 1 = 51 to rank1==
2815 14:44:12.118134 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 14:44:12.122000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 14:44:12.124902 ==
2818 14:44:12.125041 DQS Delay:
2819 14:44:12.125113 DQS0 = 0, DQS1 = 0
2820 14:44:12.128010 DQM Delay:
2821 14:44:12.128106 DQM0 = 115, DQM1 = 106
2822 14:44:12.131855 DQ Delay:
2823 14:44:12.135388 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2824 14:44:12.138200 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2825 14:44:12.142147 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2826 14:44:12.145427 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =114
2827 14:44:12.145499
2828 14:44:12.145567
2829 14:44:12.151508 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2830 14:44:12.155170 CH0 RK0: MR19=303, MR18=FBEA
2831 14:44:12.161773 CH0_RK0: MR19=0x303, MR18=0xFBEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2832 14:44:12.161850
2833 14:44:12.165441 ----->DramcWriteLeveling(PI) begin...
2834 14:44:12.165520 ==
2835 14:44:12.169196 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 14:44:12.171657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 14:44:12.171763 ==
2838 14:44:12.175247 Write leveling (Byte 0): 33 => 33
2839 14:44:12.178837 Write leveling (Byte 1): 30 => 30
2840 14:44:12.182279 DramcWriteLeveling(PI) end<-----
2841 14:44:12.182360
2842 14:44:12.182429 ==
2843 14:44:12.185104 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 14:44:12.188616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 14:44:12.188693 ==
2846 14:44:12.191806 [Gating] SW mode calibration
2847 14:44:12.198707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 14:44:12.205251 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 14:44:12.208576 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2850 14:44:12.215747 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2851 14:44:12.219057 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 14:44:12.222191 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 14:44:12.225655 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 14:44:12.232139 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 14:44:12.235707 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 14:44:12.239010 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2857 14:44:12.245822 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2858 14:44:12.248887 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2859 14:44:12.252257 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 14:44:12.259374 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 14:44:12.262160 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 14:44:12.265636 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 14:44:12.272362 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2864 14:44:12.276018 1 0 28 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
2865 14:44:12.279217 1 1 0 | B1->B0 | 3636 4040 | 1 0 | (0 0) (0 0)
2866 14:44:12.285985 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 14:44:12.290397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 14:44:12.292595 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 14:44:12.296365 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 14:44:12.302664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 14:44:12.306273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2872 14:44:12.309305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2873 14:44:12.316483 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2874 14:44:12.319817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 14:44:12.323186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 14:44:12.329815 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 14:44:12.333404 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 14:44:12.336295 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 14:44:12.339863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 14:44:12.346256 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 14:44:12.349739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 14:44:12.353084 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 14:44:12.359871 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 14:44:12.363707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 14:44:12.366783 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 14:44:12.373846 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 14:44:12.376734 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 14:44:12.379971 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 14:44:12.387046 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2890 14:44:12.387136 Total UI for P1: 0, mck2ui 16
2891 14:44:12.393829 best dqsien dly found for B0: ( 1, 3, 26)
2892 14:44:12.396661 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 14:44:12.400433 Total UI for P1: 0, mck2ui 16
2894 14:44:12.403587 best dqsien dly found for B1: ( 1, 4, 0)
2895 14:44:12.407215 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2896 14:44:12.410270 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2897 14:44:12.410355
2898 14:44:12.413814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2899 14:44:12.416720 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2900 14:44:12.420526 [Gating] SW calibration Done
2901 14:44:12.420601 ==
2902 14:44:12.423555 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 14:44:12.427390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 14:44:12.427476 ==
2905 14:44:12.430446 RX Vref Scan: 0
2906 14:44:12.430518
2907 14:44:12.430591 RX Vref 0 -> 0, step: 1
2908 14:44:12.430652
2909 14:44:12.433478 RX Delay -40 -> 252, step: 8
2910 14:44:12.437339 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2911 14:44:12.443403 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2912 14:44:12.447464 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2913 14:44:12.450767 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2914 14:44:12.453634 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2915 14:44:12.457572 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2916 14:44:12.464584 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2917 14:44:12.467366 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2918 14:44:12.471206 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2919 14:44:12.474294 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 14:44:12.477433 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2921 14:44:12.480898 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2922 14:44:12.487325 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 14:44:12.490515 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2924 14:44:12.494717 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 14:44:12.497288 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2926 14:44:12.497375 ==
2927 14:44:12.500650 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 14:44:12.507826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 14:44:12.507909 ==
2930 14:44:12.507990 DQS Delay:
2931 14:44:12.508054 DQS0 = 0, DQS1 = 0
2932 14:44:12.510987 DQM Delay:
2933 14:44:12.511059 DQM0 = 115, DQM1 = 106
2934 14:44:12.514446 DQ Delay:
2935 14:44:12.517169 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2936 14:44:12.520850 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2937 14:44:12.523842 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2938 14:44:12.527372 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2939 14:44:12.527456
2940 14:44:12.527521
2941 14:44:12.527630 ==
2942 14:44:12.530814 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 14:44:12.534451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 14:44:12.534538 ==
2945 14:44:12.534605
2946 14:44:12.534673
2947 14:44:12.537955 TX Vref Scan disable
2948 14:44:12.540749 == TX Byte 0 ==
2949 14:44:12.544150 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2950 14:44:12.548513 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2951 14:44:12.550768 == TX Byte 1 ==
2952 14:44:12.555165 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2953 14:44:12.557555 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2954 14:44:12.557641 ==
2955 14:44:12.561301 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 14:44:12.564113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 14:44:12.567690 ==
2958 14:44:12.577762 TX Vref=22, minBit 1, minWin=25, winSum=420
2959 14:44:12.581428 TX Vref=24, minBit 1, minWin=26, winSum=429
2960 14:44:12.584374 TX Vref=26, minBit 0, minWin=26, winSum=431
2961 14:44:12.588291 TX Vref=28, minBit 2, minWin=26, winSum=434
2962 14:44:12.591561 TX Vref=30, minBit 12, minWin=26, winSum=435
2963 14:44:12.597935 TX Vref=32, minBit 12, minWin=26, winSum=434
2964 14:44:12.600937 [TxChooseVref] Worse bit 12, Min win 26, Win sum 435, Final Vref 30
2965 14:44:12.601089
2966 14:44:12.604501 Final TX Range 1 Vref 30
2967 14:44:12.604586
2968 14:44:12.604652 ==
2969 14:44:12.607611 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 14:44:12.611350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 14:44:12.614532 ==
2972 14:44:12.614618
2973 14:44:12.614683
2974 14:44:12.614745 TX Vref Scan disable
2975 14:44:12.618493 == TX Byte 0 ==
2976 14:44:12.621805 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2977 14:44:12.625343 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2978 14:44:12.627904 == TX Byte 1 ==
2979 14:44:12.631259 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2980 14:44:12.634562 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2981 14:44:12.637874
2982 14:44:12.637954 [DATLAT]
2983 14:44:12.638030 Freq=1200, CH0 RK1
2984 14:44:12.638094
2985 14:44:12.641831 DATLAT Default: 0xd
2986 14:44:12.641907 0, 0xFFFF, sum = 0
2987 14:44:12.644943 1, 0xFFFF, sum = 0
2988 14:44:12.645074 2, 0xFFFF, sum = 0
2989 14:44:12.648042 3, 0xFFFF, sum = 0
2990 14:44:12.648119 4, 0xFFFF, sum = 0
2991 14:44:12.651502 5, 0xFFFF, sum = 0
2992 14:44:12.651582 6, 0xFFFF, sum = 0
2993 14:44:12.654494 7, 0xFFFF, sum = 0
2994 14:44:12.658542 8, 0xFFFF, sum = 0
2995 14:44:12.658627 9, 0xFFFF, sum = 0
2996 14:44:12.661523 10, 0xFFFF, sum = 0
2997 14:44:12.661608 11, 0xFFFF, sum = 0
2998 14:44:12.665190 12, 0x0, sum = 1
2999 14:44:12.665273 13, 0x0, sum = 2
3000 14:44:12.668581 14, 0x0, sum = 3
3001 14:44:12.668665 15, 0x0, sum = 4
3002 14:44:12.668733 best_step = 13
3003 14:44:12.668793
3004 14:44:12.671806 ==
3005 14:44:12.671889 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 14:44:12.678383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 14:44:12.678465 ==
3008 14:44:12.678531 RX Vref Scan: 0
3009 14:44:12.678602
3010 14:44:12.681782 RX Vref 0 -> 0, step: 1
3011 14:44:12.681862
3012 14:44:12.684752 RX Delay -21 -> 252, step: 4
3013 14:44:12.688239 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3014 14:44:12.691426 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3015 14:44:12.698441 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3016 14:44:12.701758 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3017 14:44:12.705046 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3018 14:44:12.708386 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3019 14:44:12.711924 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3020 14:44:12.718404 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3021 14:44:12.722435 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3022 14:44:12.725464 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3023 14:44:12.729107 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3024 14:44:12.731904 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3025 14:44:12.735262 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3026 14:44:12.742100 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3027 14:44:12.745146 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3028 14:44:12.749211 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3029 14:44:12.749294 ==
3030 14:44:12.751996 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 14:44:12.755190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 14:44:12.755279 ==
3033 14:44:12.759345 DQS Delay:
3034 14:44:12.759425 DQS0 = 0, DQS1 = 0
3035 14:44:12.761889 DQM Delay:
3036 14:44:12.761968 DQM0 = 114, DQM1 = 104
3037 14:44:12.765356 DQ Delay:
3038 14:44:12.768577 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3039 14:44:12.772066 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3040 14:44:12.775769 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3041 14:44:12.779118 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3042 14:44:12.779201
3043 14:44:12.779266
3044 14:44:12.785537 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3045 14:44:12.788821 CH0 RK1: MR19=403, MR18=2F3
3046 14:44:12.795295 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3047 14:44:12.799274 [RxdqsGatingPostProcess] freq 1200
3048 14:44:12.802611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 14:44:12.805686 best DQS0 dly(2T, 0.5T) = (0, 12)
3050 14:44:12.809149 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 14:44:12.812429 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3052 14:44:12.815949 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 14:44:12.819022 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 14:44:12.825498 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 14:44:12.825941 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 14:44:12.828979 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 14:44:12.832439 Pre-setting of DQS Precalculation
3058 14:44:12.835719 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 14:44:12.835801 ==
3060 14:44:12.838928 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 14:44:12.842716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 14:44:12.845626 ==
3063 14:44:12.849240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 14:44:12.856086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3065 14:44:12.864221 [CA 0] Center 38 (8~68) winsize 61
3066 14:44:12.867147 [CA 1] Center 38 (9~68) winsize 60
3067 14:44:12.870788 [CA 2] Center 35 (5~65) winsize 61
3068 14:44:12.874386 [CA 3] Center 34 (4~65) winsize 62
3069 14:44:12.877843 [CA 4] Center 34 (4~65) winsize 62
3070 14:44:12.880920 [CA 5] Center 33 (3~64) winsize 62
3071 14:44:12.881041
3072 14:44:12.884644 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3073 14:44:12.884729
3074 14:44:12.887209 [CATrainingPosCal] consider 1 rank data
3075 14:44:12.890727 u2DelayCellTimex100 = 270/100 ps
3076 14:44:12.894464 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3077 14:44:12.897546 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3078 14:44:12.900759 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3079 14:44:12.907872 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3080 14:44:12.910921 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3081 14:44:12.914792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3082 14:44:12.914879
3083 14:44:12.917291 CA PerBit enable=1, Macro0, CA PI delay=33
3084 14:44:12.917372
3085 14:44:12.920929 [CBTSetCACLKResult] CA Dly = 33
3086 14:44:12.921083 CS Dly: 6 (0~37)
3087 14:44:12.921179 ==
3088 14:44:12.924714 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 14:44:12.931168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 14:44:12.931251 ==
3091 14:44:12.934330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 14:44:12.940917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3093 14:44:12.949804 [CA 0] Center 38 (8~68) winsize 61
3094 14:44:12.952795 [CA 1] Center 38 (8~68) winsize 61
3095 14:44:12.956319 [CA 2] Center 34 (4~65) winsize 62
3096 14:44:12.959603 [CA 3] Center 34 (4~65) winsize 62
3097 14:44:12.962994 [CA 4] Center 34 (4~65) winsize 62
3098 14:44:12.966584 [CA 5] Center 33 (3~63) winsize 61
3099 14:44:12.966667
3100 14:44:12.969429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 14:44:12.969511
3102 14:44:12.973303 [CATrainingPosCal] consider 2 rank data
3103 14:44:12.976470 u2DelayCellTimex100 = 270/100 ps
3104 14:44:12.979783 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3105 14:44:12.982809 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3106 14:44:12.986589 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 14:44:12.992892 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3108 14:44:12.996148 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3109 14:44:13.000655 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3110 14:44:13.000737
3111 14:44:13.003426 CA PerBit enable=1, Macro0, CA PI delay=33
3112 14:44:13.003508
3113 14:44:13.006726 [CBTSetCACLKResult] CA Dly = 33
3114 14:44:13.006809 CS Dly: 7 (0~40)
3115 14:44:13.006875
3116 14:44:13.010551 ----->DramcWriteLeveling(PI) begin...
3117 14:44:13.010634 ==
3118 14:44:13.013721 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 14:44:13.020378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 14:44:13.020461 ==
3121 14:44:13.023383 Write leveling (Byte 0): 26 => 26
3122 14:44:13.023466 Write leveling (Byte 1): 28 => 28
3123 14:44:13.026791 DramcWriteLeveling(PI) end<-----
3124 14:44:13.026873
3125 14:44:13.026950 ==
3126 14:44:13.030460 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 14:44:13.036824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 14:44:13.036907 ==
3129 14:44:13.040324 [Gating] SW mode calibration
3130 14:44:13.046748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 14:44:13.050497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 14:44:13.056744 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3133 14:44:13.060164 0 15 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
3134 14:44:13.063604 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 14:44:13.067030 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 14:44:13.074112 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3137 14:44:13.076770 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 14:44:13.080140 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 14:44:13.087142 0 15 28 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 1)
3140 14:44:13.090138 1 0 0 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (1 1)
3141 14:44:13.093758 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 14:44:13.100813 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 14:44:13.103727 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 14:44:13.107470 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 14:44:13.114365 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 14:44:13.117561 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3147 14:44:13.120674 1 0 28 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3148 14:44:13.124086 1 1 0 | B1->B0 | 4343 3737 | 0 0 | (0 0) (0 0)
3149 14:44:13.130921 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 14:44:13.134248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 14:44:13.137163 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 14:44:13.144115 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 14:44:13.147444 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 14:44:13.150877 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 14:44:13.157073 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 14:44:13.160697 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 14:44:13.164737 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 14:44:13.171194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 14:44:13.174231 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 14:44:13.177447 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 14:44:13.184462 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 14:44:13.187598 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 14:44:13.190618 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 14:44:13.194532 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 14:44:13.201192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 14:44:13.204072 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 14:44:13.207744 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 14:44:13.214747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 14:44:13.217770 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 14:44:13.221475 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 14:44:13.227591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3172 14:44:13.231634 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 14:44:13.234921 Total UI for P1: 0, mck2ui 16
3174 14:44:13.237883 best dqsien dly found for B0: ( 1, 3, 28)
3175 14:44:13.241085 Total UI for P1: 0, mck2ui 16
3176 14:44:13.244458 best dqsien dly found for B1: ( 1, 3, 28)
3177 14:44:13.247962 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3178 14:44:13.251760 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3179 14:44:13.251836
3180 14:44:13.255234 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3181 14:44:13.258447 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 14:44:13.261342 [Gating] SW calibration Done
3183 14:44:13.261423 ==
3184 14:44:13.264898 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 14:44:13.268598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 14:44:13.268679 ==
3187 14:44:13.271228 RX Vref Scan: 0
3188 14:44:13.271306
3189 14:44:13.274482 RX Vref 0 -> 0, step: 1
3190 14:44:13.274554
3191 14:44:13.274616 RX Delay -40 -> 252, step: 8
3192 14:44:13.281781 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3193 14:44:13.285046 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3194 14:44:13.288334 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3195 14:44:13.291551 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3196 14:44:13.294860 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3197 14:44:13.301353 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3198 14:44:13.305208 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3199 14:44:13.308212 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3200 14:44:13.311436 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3201 14:44:13.314745 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3202 14:44:13.318782 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3203 14:44:13.325309 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3204 14:44:13.328761 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3205 14:44:13.331863 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3206 14:44:13.335231 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3207 14:44:13.339669 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3208 14:44:13.341633 ==
3209 14:44:13.344933 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 14:44:13.348017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 14:44:13.348095 ==
3212 14:44:13.348168 DQS Delay:
3213 14:44:13.351868 DQS0 = 0, DQS1 = 0
3214 14:44:13.351948 DQM Delay:
3215 14:44:13.355394 DQM0 = 116, DQM1 = 108
3216 14:44:13.355477 DQ Delay:
3217 14:44:13.358258 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3218 14:44:13.361710 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3219 14:44:13.365174 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3220 14:44:13.368888 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3221 14:44:13.368966
3222 14:44:13.369074
3223 14:44:13.369142 ==
3224 14:44:13.371656 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 14:44:13.374838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 14:44:13.378395 ==
3227 14:44:13.378477
3228 14:44:13.378541
3229 14:44:13.378602 TX Vref Scan disable
3230 14:44:13.381616 == TX Byte 0 ==
3231 14:44:13.386127 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3232 14:44:13.388313 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3233 14:44:13.392035 == TX Byte 1 ==
3234 14:44:13.396177 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3235 14:44:13.398453 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3236 14:44:13.398536 ==
3237 14:44:13.402109 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 14:44:13.408545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 14:44:13.408655 ==
3240 14:44:13.419233 TX Vref=22, minBit 0, minWin=25, winSum=415
3241 14:44:13.422813 TX Vref=24, minBit 1, minWin=25, winSum=417
3242 14:44:13.426091 TX Vref=26, minBit 0, minWin=26, winSum=425
3243 14:44:13.429859 TX Vref=28, minBit 1, minWin=26, winSum=427
3244 14:44:13.433436 TX Vref=30, minBit 0, minWin=26, winSum=427
3245 14:44:13.436401 TX Vref=32, minBit 3, minWin=25, winSum=428
3246 14:44:13.443561 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3247 14:44:13.443642
3248 14:44:13.446701 Final TX Range 1 Vref 28
3249 14:44:13.446783
3250 14:44:13.446851 ==
3251 14:44:13.449671 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 14:44:13.452835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 14:44:13.452913 ==
3254 14:44:13.452984
3255 14:44:13.453090
3256 14:44:13.456383 TX Vref Scan disable
3257 14:44:13.460327 == TX Byte 0 ==
3258 14:44:13.462984 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 14:44:13.466870 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 14:44:13.469720 == TX Byte 1 ==
3261 14:44:13.473367 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 14:44:13.476329 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 14:44:13.476405
3264 14:44:13.480127 [DATLAT]
3265 14:44:13.480202 Freq=1200, CH1 RK0
3266 14:44:13.480272
3267 14:44:13.483115 DATLAT Default: 0xd
3268 14:44:13.483187 0, 0xFFFF, sum = 0
3269 14:44:13.487026 1, 0xFFFF, sum = 0
3270 14:44:13.487110 2, 0xFFFF, sum = 0
3271 14:44:13.490293 3, 0xFFFF, sum = 0
3272 14:44:13.490373 4, 0xFFFF, sum = 0
3273 14:44:13.492970 5, 0xFFFF, sum = 0
3274 14:44:13.493087 6, 0xFFFF, sum = 0
3275 14:44:13.496476 7, 0xFFFF, sum = 0
3276 14:44:13.496551 8, 0xFFFF, sum = 0
3277 14:44:13.499863 9, 0xFFFF, sum = 0
3278 14:44:13.499948 10, 0xFFFF, sum = 0
3279 14:44:13.503212 11, 0xFFFF, sum = 0
3280 14:44:13.503305 12, 0x0, sum = 1
3281 14:44:13.506322 13, 0x0, sum = 2
3282 14:44:13.506404 14, 0x0, sum = 3
3283 14:44:13.510260 15, 0x0, sum = 4
3284 14:44:13.510340 best_step = 13
3285 14:44:13.510405
3286 14:44:13.510465 ==
3287 14:44:13.513139 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 14:44:13.520044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 14:44:13.520129 ==
3290 14:44:13.520198 RX Vref Scan: 1
3291 14:44:13.520261
3292 14:44:13.523090 Set Vref Range= 32 -> 127
3293 14:44:13.523172
3294 14:44:13.526283 RX Vref 32 -> 127, step: 1
3295 14:44:13.526361
3296 14:44:13.526424 RX Delay -21 -> 252, step: 4
3297 14:44:13.526484
3298 14:44:13.529760 Set Vref, RX VrefLevel [Byte0]: 32
3299 14:44:13.533270 [Byte1]: 32
3300 14:44:13.537835
3301 14:44:13.537917 Set Vref, RX VrefLevel [Byte0]: 33
3302 14:44:13.540615 [Byte1]: 33
3303 14:44:13.545564
3304 14:44:13.545640 Set Vref, RX VrefLevel [Byte0]: 34
3305 14:44:13.549188 [Byte1]: 34
3306 14:44:13.553720
3307 14:44:13.553799 Set Vref, RX VrefLevel [Byte0]: 35
3308 14:44:13.557237 [Byte1]: 35
3309 14:44:13.561404
3310 14:44:13.561484 Set Vref, RX VrefLevel [Byte0]: 36
3311 14:44:13.564571 [Byte1]: 36
3312 14:44:13.569360
3313 14:44:13.569437 Set Vref, RX VrefLevel [Byte0]: 37
3314 14:44:13.572862 [Byte1]: 37
3315 14:44:13.577121
3316 14:44:13.577207 Set Vref, RX VrefLevel [Byte0]: 38
3317 14:44:13.580653 [Byte1]: 38
3318 14:44:13.585007
3319 14:44:13.585109 Set Vref, RX VrefLevel [Byte0]: 39
3320 14:44:13.588170 [Byte1]: 39
3321 14:44:13.593578
3322 14:44:13.593659 Set Vref, RX VrefLevel [Byte0]: 40
3323 14:44:13.596616 [Byte1]: 40
3324 14:44:13.600809
3325 14:44:13.600893 Set Vref, RX VrefLevel [Byte0]: 41
3326 14:44:13.604139 [Byte1]: 41
3327 14:44:13.608730
3328 14:44:13.608812 Set Vref, RX VrefLevel [Byte0]: 42
3329 14:44:13.612107 [Byte1]: 42
3330 14:44:13.617968
3331 14:44:13.618050 Set Vref, RX VrefLevel [Byte0]: 43
3332 14:44:13.619885 [Byte1]: 43
3333 14:44:13.624497
3334 14:44:13.624578 Set Vref, RX VrefLevel [Byte0]: 44
3335 14:44:13.627929 [Byte1]: 44
3336 14:44:13.632467
3337 14:44:13.632549 Set Vref, RX VrefLevel [Byte0]: 45
3338 14:44:13.636549 [Byte1]: 45
3339 14:44:13.640945
3340 14:44:13.641080 Set Vref, RX VrefLevel [Byte0]: 46
3341 14:44:13.644218 [Byte1]: 46
3342 14:44:13.648400
3343 14:44:13.648481 Set Vref, RX VrefLevel [Byte0]: 47
3344 14:44:13.651632 [Byte1]: 47
3345 14:44:13.656234
3346 14:44:13.656315 Set Vref, RX VrefLevel [Byte0]: 48
3347 14:44:13.659782 [Byte1]: 48
3348 14:44:13.664431
3349 14:44:13.664512 Set Vref, RX VrefLevel [Byte0]: 49
3350 14:44:13.667604 [Byte1]: 49
3351 14:44:13.672186
3352 14:44:13.672273 Set Vref, RX VrefLevel [Byte0]: 50
3353 14:44:13.675619 [Byte1]: 50
3354 14:44:13.680694
3355 14:44:13.680776 Set Vref, RX VrefLevel [Byte0]: 51
3356 14:44:13.683250 [Byte1]: 51
3357 14:44:13.688284
3358 14:44:13.688470 Set Vref, RX VrefLevel [Byte0]: 52
3359 14:44:13.691532 [Byte1]: 52
3360 14:44:13.696308
3361 14:44:13.696415 Set Vref, RX VrefLevel [Byte0]: 53
3362 14:44:13.699124 [Byte1]: 53
3363 14:44:13.704741
3364 14:44:13.704854 Set Vref, RX VrefLevel [Byte0]: 54
3365 14:44:13.707665 [Byte1]: 54
3366 14:44:13.711839
3367 14:44:13.711951 Set Vref, RX VrefLevel [Byte0]: 55
3368 14:44:13.715294 [Byte1]: 55
3369 14:44:13.719899
3370 14:44:13.720006 Set Vref, RX VrefLevel [Byte0]: 56
3371 14:44:13.723392 [Byte1]: 56
3372 14:44:13.727478
3373 14:44:13.727581 Set Vref, RX VrefLevel [Byte0]: 57
3374 14:44:13.731804 [Byte1]: 57
3375 14:44:13.735540
3376 14:44:13.735642 Set Vref, RX VrefLevel [Byte0]: 58
3377 14:44:13.738748 [Byte1]: 58
3378 14:44:13.743515
3379 14:44:13.743620 Set Vref, RX VrefLevel [Byte0]: 59
3380 14:44:13.747073 [Byte1]: 59
3381 14:44:13.751317
3382 14:44:13.751432 Set Vref, RX VrefLevel [Byte0]: 60
3383 14:44:13.754533 [Byte1]: 60
3384 14:44:13.759369
3385 14:44:13.759483 Set Vref, RX VrefLevel [Byte0]: 61
3386 14:44:13.763035 [Byte1]: 61
3387 14:44:13.767279
3388 14:44:13.767364 Set Vref, RX VrefLevel [Byte0]: 62
3389 14:44:13.770548 [Byte1]: 62
3390 14:44:13.775397
3391 14:44:13.775479 Set Vref, RX VrefLevel [Byte0]: 63
3392 14:44:13.778571 [Byte1]: 63
3393 14:44:13.783443
3394 14:44:13.783555 Set Vref, RX VrefLevel [Byte0]: 64
3395 14:44:13.786457 [Byte1]: 64
3396 14:44:13.792043
3397 14:44:13.792125 Set Vref, RX VrefLevel [Byte0]: 65
3398 14:44:13.794446 [Byte1]: 65
3399 14:44:13.799092
3400 14:44:13.799174 Set Vref, RX VrefLevel [Byte0]: 66
3401 14:44:13.802471 [Byte1]: 66
3402 14:44:13.807602
3403 14:44:13.807684 Set Vref, RX VrefLevel [Byte0]: 67
3404 14:44:13.810425 [Byte1]: 67
3405 14:44:13.815995
3406 14:44:13.816077 Set Vref, RX VrefLevel [Byte0]: 68
3407 14:44:13.818518 [Byte1]: 68
3408 14:44:13.822625
3409 14:44:13.822707 Set Vref, RX VrefLevel [Byte0]: 69
3410 14:44:13.825785 [Byte1]: 69
3411 14:44:13.831391
3412 14:44:13.831473 Set Vref, RX VrefLevel [Byte0]: 70
3413 14:44:13.834021 [Byte1]: 70
3414 14:44:13.838852
3415 14:44:13.838934 Set Vref, RX VrefLevel [Byte0]: 71
3416 14:44:13.841975 [Byte1]: 71
3417 14:44:13.846617
3418 14:44:13.846699 Set Vref, RX VrefLevel [Byte0]: 72
3419 14:44:13.850432 [Byte1]: 72
3420 14:44:13.854249
3421 14:44:13.854331 Final RX Vref Byte 0 = 57 to rank0
3422 14:44:13.857829 Final RX Vref Byte 1 = 53 to rank0
3423 14:44:13.861012 Final RX Vref Byte 0 = 57 to rank1
3424 14:44:13.864851 Final RX Vref Byte 1 = 53 to rank1==
3425 14:44:13.867678 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 14:44:13.871351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 14:44:13.874740 ==
3428 14:44:13.874858 DQS Delay:
3429 14:44:13.874953 DQS0 = 0, DQS1 = 0
3430 14:44:13.878086 DQM Delay:
3431 14:44:13.878192 DQM0 = 116, DQM1 = 109
3432 14:44:13.881388 DQ Delay:
3433 14:44:13.884693 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3434 14:44:13.887659 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3435 14:44:13.891791 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3436 14:44:13.894539 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3437 14:44:13.894640
3438 14:44:13.894732
3439 14:44:13.902552 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3440 14:44:13.905406 CH1 RK0: MR19=303, MR18=FCE0
3441 14:44:13.911325 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3442 14:44:13.911430
3443 14:44:13.915006 ----->DramcWriteLeveling(PI) begin...
3444 14:44:13.915082 ==
3445 14:44:13.918364 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 14:44:13.921447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 14:44:13.921532 ==
3448 14:44:13.925207 Write leveling (Byte 0): 25 => 25
3449 14:44:13.928114 Write leveling (Byte 1): 28 => 28
3450 14:44:13.931448 DramcWriteLeveling(PI) end<-----
3451 14:44:13.931519
3452 14:44:13.931588 ==
3453 14:44:13.934572 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 14:44:13.938364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 14:44:13.941477 ==
3456 14:44:13.941549 [Gating] SW mode calibration
3457 14:44:13.948292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 14:44:13.955296 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 14:44:13.959021 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3460 14:44:13.965476 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3461 14:44:13.968260 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 14:44:13.971668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 14:44:13.975482 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 14:44:13.982206 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3465 14:44:13.984962 0 15 24 | B1->B0 | 3434 2929 | 0 0 | (0 0) (0 0)
3466 14:44:13.988407 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3467 14:44:13.995062 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 14:44:13.999030 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 14:44:14.002168 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 14:44:14.008409 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3471 14:44:14.011884 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 14:44:14.017045 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 14:44:14.022118 1 0 24 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3474 14:44:14.025004 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3475 14:44:14.028840 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 14:44:14.034964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 14:44:14.038377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 14:44:14.041726 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 14:44:14.048865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 14:44:14.051664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 14:44:14.055799 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 14:44:14.062500 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3483 14:44:14.065237 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 14:44:14.068858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 14:44:14.071801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 14:44:14.078413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 14:44:14.081953 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 14:44:14.084983 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 14:44:14.091921 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 14:44:14.095782 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 14:44:14.098868 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 14:44:14.105612 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 14:44:14.109163 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 14:44:14.112020 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 14:44:14.118346 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 14:44:14.121749 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3497 14:44:14.125803 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 14:44:14.133333 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3499 14:44:14.133438 Total UI for P1: 0, mck2ui 16
3500 14:44:14.138622 best dqsien dly found for B0: ( 1, 3, 22)
3501 14:44:14.142139 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 14:44:14.146174 Total UI for P1: 0, mck2ui 16
3503 14:44:14.148771 best dqsien dly found for B1: ( 1, 3, 28)
3504 14:44:14.151858 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3505 14:44:14.155191 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3506 14:44:14.155266
3507 14:44:14.159085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 14:44:14.162057 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3509 14:44:14.165138 [Gating] SW calibration Done
3510 14:44:14.165219 ==
3511 14:44:14.168888 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 14:44:14.172319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 14:44:14.172422 ==
3514 14:44:14.175137 RX Vref Scan: 0
3515 14:44:14.175233
3516 14:44:14.179045 RX Vref 0 -> 0, step: 1
3517 14:44:14.179143
3518 14:44:14.179234 RX Delay -40 -> 252, step: 8
3519 14:44:14.185287 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3520 14:44:14.188776 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3521 14:44:14.191795 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3522 14:44:14.195103 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3523 14:44:14.198783 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3524 14:44:14.202275 iDelay=200, Bit 5, Center 123 (56 ~ 191) 136
3525 14:44:14.208955 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3526 14:44:14.212742 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3527 14:44:14.215815 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3528 14:44:14.219080 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3529 14:44:14.222560 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3530 14:44:14.229648 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3531 14:44:14.232563 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3532 14:44:14.235426 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3533 14:44:14.238676 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3534 14:44:14.242229 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3535 14:44:14.245524 ==
3536 14:44:14.249068 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 14:44:14.252326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 14:44:14.252430 ==
3539 14:44:14.252552 DQS Delay:
3540 14:44:14.255784 DQS0 = 0, DQS1 = 0
3541 14:44:14.255880 DQM Delay:
3542 14:44:14.258821 DQM0 = 113, DQM1 = 110
3543 14:44:14.258920 DQ Delay:
3544 14:44:14.262148 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3545 14:44:14.266375 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =107
3546 14:44:14.268777 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3547 14:44:14.272163 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3548 14:44:14.272236
3549 14:44:14.272298
3550 14:44:14.272391 ==
3551 14:44:14.276061 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 14:44:14.282729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 14:44:14.282833 ==
3554 14:44:14.282928
3555 14:44:14.283019
3556 14:44:14.283107 TX Vref Scan disable
3557 14:44:14.285725 == TX Byte 0 ==
3558 14:44:14.289214 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3559 14:44:14.292614 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3560 14:44:14.295632 == TX Byte 1 ==
3561 14:44:14.298938 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3562 14:44:14.302939 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3563 14:44:14.305605 ==
3564 14:44:14.309282 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 14:44:14.312292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 14:44:14.312392 ==
3567 14:44:14.323649 TX Vref=22, minBit 0, minWin=25, winSum=417
3568 14:44:14.326817 TX Vref=24, minBit 0, minWin=26, winSum=424
3569 14:44:14.330200 TX Vref=26, minBit 3, minWin=25, winSum=430
3570 14:44:14.334040 TX Vref=28, minBit 9, minWin=26, winSum=433
3571 14:44:14.337079 TX Vref=30, minBit 1, minWin=26, winSum=433
3572 14:44:14.340410 TX Vref=32, minBit 0, minWin=26, winSum=432
3573 14:44:14.347260 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3574 14:44:14.347338
3575 14:44:14.351215 Final TX Range 1 Vref 28
3576 14:44:14.351295
3577 14:44:14.351361 ==
3578 14:44:14.353531 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 14:44:14.357119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 14:44:14.357221 ==
3581 14:44:14.357313
3582 14:44:14.357405
3583 14:44:14.360147 TX Vref Scan disable
3584 14:44:14.363666 == TX Byte 0 ==
3585 14:44:14.367670 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3586 14:44:14.370451 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3587 14:44:14.373762 == TX Byte 1 ==
3588 14:44:14.376903 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3589 14:44:14.380635 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3590 14:44:14.380736
3591 14:44:14.383759 [DATLAT]
3592 14:44:14.383861 Freq=1200, CH1 RK1
3593 14:44:14.383952
3594 14:44:14.387075 DATLAT Default: 0xd
3595 14:44:14.387181 0, 0xFFFF, sum = 0
3596 14:44:14.390635 1, 0xFFFF, sum = 0
3597 14:44:14.390740 2, 0xFFFF, sum = 0
3598 14:44:14.393760 3, 0xFFFF, sum = 0
3599 14:44:14.393866 4, 0xFFFF, sum = 0
3600 14:44:14.397378 5, 0xFFFF, sum = 0
3601 14:44:14.397483 6, 0xFFFF, sum = 0
3602 14:44:14.400516 7, 0xFFFF, sum = 0
3603 14:44:14.400617 8, 0xFFFF, sum = 0
3604 14:44:14.404052 9, 0xFFFF, sum = 0
3605 14:44:14.404151 10, 0xFFFF, sum = 0
3606 14:44:14.407126 11, 0xFFFF, sum = 0
3607 14:44:14.407230 12, 0x0, sum = 1
3608 14:44:14.410240 13, 0x0, sum = 2
3609 14:44:14.410341 14, 0x0, sum = 3
3610 14:44:14.414046 15, 0x0, sum = 4
3611 14:44:14.414148 best_step = 13
3612 14:44:14.414238
3613 14:44:14.414330 ==
3614 14:44:14.417494 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 14:44:14.423772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 14:44:14.423880 ==
3617 14:44:14.423977 RX Vref Scan: 0
3618 14:44:14.424065
3619 14:44:14.426962 RX Vref 0 -> 0, step: 1
3620 14:44:14.427065
3621 14:44:14.430978 RX Delay -21 -> 252, step: 4
3622 14:44:14.433963 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3623 14:44:14.437544 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3624 14:44:14.445420 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3625 14:44:14.447179 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3626 14:44:14.450366 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3627 14:44:14.453962 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3628 14:44:14.457232 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3629 14:44:14.460417 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3630 14:44:14.467088 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3631 14:44:14.470417 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3632 14:44:14.474239 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3633 14:44:14.477246 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3634 14:44:14.481545 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3635 14:44:14.487209 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3636 14:44:14.491001 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3637 14:44:14.494050 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3638 14:44:14.494157 ==
3639 14:44:14.497512 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 14:44:14.500753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 14:44:14.500857 ==
3642 14:44:14.504062 DQS Delay:
3643 14:44:14.504146 DQS0 = 0, DQS1 = 0
3644 14:44:14.507758 DQM Delay:
3645 14:44:14.507862 DQM0 = 113, DQM1 = 109
3646 14:44:14.510397 DQ Delay:
3647 14:44:14.514082 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3648 14:44:14.517493 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3649 14:44:14.520819 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3650 14:44:14.523846 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =116
3651 14:44:14.523947
3652 14:44:14.524039
3653 14:44:14.530518 [DQSOSCAuto] RK1, (LSB)MR18= 0xf800, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3654 14:44:14.533591 CH1 RK1: MR19=304, MR18=F800
3655 14:44:14.540884 CH1_RK1: MR19=0x304, MR18=0xF800, DQSOSC=410, MR23=63, INC=39, DEC=26
3656 14:44:14.543863 [RxdqsGatingPostProcess] freq 1200
3657 14:44:14.550432 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 14:44:14.550541 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 14:44:14.553690 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 14:44:14.557388 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 14:44:14.560632 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 14:44:14.563829 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 14:44:14.566998 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 14:44:14.570127 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 14:44:14.573521 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 14:44:14.577197 Pre-setting of DQS Precalculation
3667 14:44:14.584071 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 14:44:14.590723 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 14:44:14.597328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 14:44:14.597434
3671 14:44:14.597531
3672 14:44:14.600902 [Calibration Summary] 2400 Mbps
3673 14:44:14.601038 CH 0, Rank 0
3674 14:44:14.603373 SW Impedance : PASS
3675 14:44:14.606814 DUTY Scan : NO K
3676 14:44:14.606920 ZQ Calibration : PASS
3677 14:44:14.610110 Jitter Meter : NO K
3678 14:44:14.610201 CBT Training : PASS
3679 14:44:14.613627 Write leveling : PASS
3680 14:44:14.616923 RX DQS gating : PASS
3681 14:44:14.617039 RX DQ/DQS(RDDQC) : PASS
3682 14:44:14.620332 TX DQ/DQS : PASS
3683 14:44:14.624106 RX DATLAT : PASS
3684 14:44:14.624189 RX DQ/DQS(Engine): PASS
3685 14:44:14.627092 TX OE : NO K
3686 14:44:14.627175 All Pass.
3687 14:44:14.627241
3688 14:44:14.630073 CH 0, Rank 1
3689 14:44:14.630155 SW Impedance : PASS
3690 14:44:14.633385 DUTY Scan : NO K
3691 14:44:14.637120 ZQ Calibration : PASS
3692 14:44:14.637203 Jitter Meter : NO K
3693 14:44:14.640090 CBT Training : PASS
3694 14:44:14.643627 Write leveling : PASS
3695 14:44:14.643709 RX DQS gating : PASS
3696 14:44:14.646715 RX DQ/DQS(RDDQC) : PASS
3697 14:44:14.650149 TX DQ/DQS : PASS
3698 14:44:14.650232 RX DATLAT : PASS
3699 14:44:14.653658 RX DQ/DQS(Engine): PASS
3700 14:44:14.653741 TX OE : NO K
3701 14:44:14.656620 All Pass.
3702 14:44:14.656733
3703 14:44:14.656830 CH 1, Rank 0
3704 14:44:14.659948 SW Impedance : PASS
3705 14:44:14.660051 DUTY Scan : NO K
3706 14:44:14.664413 ZQ Calibration : PASS
3707 14:44:14.666700 Jitter Meter : NO K
3708 14:44:14.666804 CBT Training : PASS
3709 14:44:14.669980 Write leveling : PASS
3710 14:44:14.673203 RX DQS gating : PASS
3711 14:44:14.673304 RX DQ/DQS(RDDQC) : PASS
3712 14:44:14.676766 TX DQ/DQS : PASS
3713 14:44:14.680168 RX DATLAT : PASS
3714 14:44:14.680271 RX DQ/DQS(Engine): PASS
3715 14:44:14.683874 TX OE : NO K
3716 14:44:14.683975 All Pass.
3717 14:44:14.684066
3718 14:44:14.686563 CH 1, Rank 1
3719 14:44:14.686668 SW Impedance : PASS
3720 14:44:14.690400 DUTY Scan : NO K
3721 14:44:14.694383 ZQ Calibration : PASS
3722 14:44:14.694485 Jitter Meter : NO K
3723 14:44:14.696972 CBT Training : PASS
3724 14:44:14.700162 Write leveling : PASS
3725 14:44:14.700276 RX DQS gating : PASS
3726 14:44:14.703327 RX DQ/DQS(RDDQC) : PASS
3727 14:44:14.703426 TX DQ/DQS : PASS
3728 14:44:14.706628 RX DATLAT : PASS
3729 14:44:14.710482 RX DQ/DQS(Engine): PASS
3730 14:44:14.710585 TX OE : NO K
3731 14:44:14.713900 All Pass.
3732 14:44:14.714001
3733 14:44:14.714093 DramC Write-DBI off
3734 14:44:14.716626 PER_BANK_REFRESH: Hybrid Mode
3735 14:44:14.719884 TX_TRACKING: ON
3736 14:44:14.727093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 14:44:14.730255 [FAST_K] Save calibration result to emmc
3738 14:44:14.733740 dramc_set_vcore_voltage set vcore to 650000
3739 14:44:14.736654 Read voltage for 600, 5
3740 14:44:14.736755 Vio18 = 0
3741 14:44:14.739795 Vcore = 650000
3742 14:44:14.739894 Vdram = 0
3743 14:44:14.739988 Vddq = 0
3744 14:44:14.744133 Vmddr = 0
3745 14:44:14.746705 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 14:44:14.753076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 14:44:14.753153 MEM_TYPE=3, freq_sel=19
3748 14:44:14.756522 sv_algorithm_assistance_LP4_1600
3749 14:44:14.763852 ============ PULL DRAM RESETB DOWN ============
3750 14:44:14.766690 ========== PULL DRAM RESETB DOWN end =========
3751 14:44:14.770153 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 14:44:14.773859 ===================================
3753 14:44:14.777628 LPDDR4 DRAM CONFIGURATION
3754 14:44:14.780185 ===================================
3755 14:44:14.780291 EX_ROW_EN[0] = 0x0
3756 14:44:14.783868 EX_ROW_EN[1] = 0x0
3757 14:44:14.787290 LP4Y_EN = 0x0
3758 14:44:14.787412 WORK_FSP = 0x0
3759 14:44:14.790223 WL = 0x2
3760 14:44:14.790325 RL = 0x2
3761 14:44:14.793325 BL = 0x2
3762 14:44:14.793424 RPST = 0x0
3763 14:44:14.797097 RD_PRE = 0x0
3764 14:44:14.797170 WR_PRE = 0x1
3765 14:44:14.800818 WR_PST = 0x0
3766 14:44:14.800916 DBI_WR = 0x0
3767 14:44:14.803914 DBI_RD = 0x0
3768 14:44:14.804002 OTF = 0x1
3769 14:44:14.807008 ===================================
3770 14:44:14.810580 ===================================
3771 14:44:14.813598 ANA top config
3772 14:44:14.817238 ===================================
3773 14:44:14.817343 DLL_ASYNC_EN = 0
3774 14:44:14.821064 ALL_SLAVE_EN = 1
3775 14:44:14.823518 NEW_RANK_MODE = 1
3776 14:44:14.827157 DLL_IDLE_MODE = 1
3777 14:44:14.827254 LP45_APHY_COMB_EN = 1
3778 14:44:14.830188 TX_ODT_DIS = 1
3779 14:44:14.833953 NEW_8X_MODE = 1
3780 14:44:14.836853 ===================================
3781 14:44:14.840152 ===================================
3782 14:44:14.843446 data_rate = 1200
3783 14:44:14.847395 CKR = 1
3784 14:44:14.847502 DQ_P2S_RATIO = 8
3785 14:44:14.850899 ===================================
3786 14:44:14.853592 CA_P2S_RATIO = 8
3787 14:44:14.857281 DQ_CA_OPEN = 0
3788 14:44:14.860478 DQ_SEMI_OPEN = 0
3789 14:44:14.863715 CA_SEMI_OPEN = 0
3790 14:44:14.867122 CA_FULL_RATE = 0
3791 14:44:14.867226 DQ_CKDIV4_EN = 1
3792 14:44:14.871070 CA_CKDIV4_EN = 1
3793 14:44:14.873426 CA_PREDIV_EN = 0
3794 14:44:14.877154 PH8_DLY = 0
3795 14:44:14.880295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 14:44:14.883841 DQ_AAMCK_DIV = 4
3797 14:44:14.883945 CA_AAMCK_DIV = 4
3798 14:44:14.887346 CA_ADMCK_DIV = 4
3799 14:44:14.890318 DQ_TRACK_CA_EN = 0
3800 14:44:14.893907 CA_PICK = 600
3801 14:44:14.896806 CA_MCKIO = 600
3802 14:44:14.900502 MCKIO_SEMI = 0
3803 14:44:14.904096 PLL_FREQ = 2288
3804 14:44:14.904201 DQ_UI_PI_RATIO = 32
3805 14:44:14.907221 CA_UI_PI_RATIO = 0
3806 14:44:14.910270 ===================================
3807 14:44:14.913782 ===================================
3808 14:44:14.917494 memory_type:LPDDR4
3809 14:44:14.920836 GP_NUM : 10
3810 14:44:14.920942 SRAM_EN : 1
3811 14:44:14.924487 MD32_EN : 0
3812 14:44:14.926952 ===================================
3813 14:44:14.927053 [ANA_INIT] >>>>>>>>>>>>>>
3814 14:44:14.930488 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 14:44:14.933814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 14:44:14.937111 ===================================
3817 14:44:14.940849 data_rate = 1200,PCW = 0X5800
3818 14:44:14.943662 ===================================
3819 14:44:14.947214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 14:44:14.954215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 14:44:14.956980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 14:44:14.963723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 14:44:14.967417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 14:44:14.970746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 14:44:14.970850 [ANA_INIT] flow start
3826 14:44:14.973822 [ANA_INIT] PLL >>>>>>>>
3827 14:44:14.977188 [ANA_INIT] PLL <<<<<<<<
3828 14:44:14.977296 [ANA_INIT] MIDPI >>>>>>>>
3829 14:44:14.980559 [ANA_INIT] MIDPI <<<<<<<<
3830 14:44:14.983737 [ANA_INIT] DLL >>>>>>>>
3831 14:44:14.983840 [ANA_INIT] flow end
3832 14:44:14.990755 ============ LP4 DIFF to SE enter ============
3833 14:44:14.993901 ============ LP4 DIFF to SE exit ============
3834 14:44:14.997324 [ANA_INIT] <<<<<<<<<<<<<
3835 14:44:15.000864 [Flow] Enable top DCM control >>>>>
3836 14:44:15.004420 [Flow] Enable top DCM control <<<<<
3837 14:44:15.004518 Enable DLL master slave shuffle
3838 14:44:15.011226 ==============================================================
3839 14:44:15.013916 Gating Mode config
3840 14:44:15.017129 ==============================================================
3841 14:44:15.020679 Config description:
3842 14:44:15.031174 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 14:44:15.037528 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 14:44:15.040392 SELPH_MODE 0: By rank 1: By Phase
3845 14:44:15.048140 ==============================================================
3846 14:44:15.050623 GAT_TRACK_EN = 1
3847 14:44:15.054442 RX_GATING_MODE = 2
3848 14:44:15.057409 RX_GATING_TRACK_MODE = 2
3849 14:44:15.057482 SELPH_MODE = 1
3850 14:44:15.060859 PICG_EARLY_EN = 1
3851 14:44:15.063954 VALID_LAT_VALUE = 1
3852 14:44:15.070789 ==============================================================
3853 14:44:15.074037 Enter into Gating configuration >>>>
3854 14:44:15.077544 Exit from Gating configuration <<<<
3855 14:44:15.081104 Enter into DVFS_PRE_config >>>>>
3856 14:44:15.090947 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 14:44:15.094161 Exit from DVFS_PRE_config <<<<<
3858 14:44:15.097375 Enter into PICG configuration >>>>
3859 14:44:15.100766 Exit from PICG configuration <<<<
3860 14:44:15.104114 [RX_INPUT] configuration >>>>>
3861 14:44:15.107449 [RX_INPUT] configuration <<<<<
3862 14:44:15.111714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 14:44:15.117992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 14:44:15.124335 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 14:44:15.127774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 14:44:15.134317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 14:44:15.141173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 14:44:15.144351 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 14:44:15.150828 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 14:44:15.154269 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 14:44:15.158214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 14:44:15.160821 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 14:44:15.167577 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 14:44:15.171206 ===================================
3875 14:44:15.171313 LPDDR4 DRAM CONFIGURATION
3876 14:44:15.174643 ===================================
3877 14:44:15.177863 EX_ROW_EN[0] = 0x0
3878 14:44:15.180816 EX_ROW_EN[1] = 0x0
3879 14:44:15.180919 LP4Y_EN = 0x0
3880 14:44:15.184497 WORK_FSP = 0x0
3881 14:44:15.184597 WL = 0x2
3882 14:44:15.187881 RL = 0x2
3883 14:44:15.187996 BL = 0x2
3884 14:44:15.190940 RPST = 0x0
3885 14:44:15.191041 RD_PRE = 0x0
3886 14:44:15.195043 WR_PRE = 0x1
3887 14:44:15.195149 WR_PST = 0x0
3888 14:44:15.197863 DBI_WR = 0x0
3889 14:44:15.197964 DBI_RD = 0x0
3890 14:44:15.200961 OTF = 0x1
3891 14:44:15.204513 ===================================
3892 14:44:15.208076 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 14:44:15.210746 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 14:44:15.217537 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 14:44:15.217639 ===================================
3896 14:44:15.221456 LPDDR4 DRAM CONFIGURATION
3897 14:44:15.224242 ===================================
3898 14:44:15.227731 EX_ROW_EN[0] = 0x10
3899 14:44:15.227834 EX_ROW_EN[1] = 0x0
3900 14:44:15.231096 LP4Y_EN = 0x0
3901 14:44:15.231194 WORK_FSP = 0x0
3902 14:44:15.234101 WL = 0x2
3903 14:44:15.234179 RL = 0x2
3904 14:44:15.237834 BL = 0x2
3905 14:44:15.241413 RPST = 0x0
3906 14:44:15.241513 RD_PRE = 0x0
3907 14:44:15.244348 WR_PRE = 0x1
3908 14:44:15.244447 WR_PST = 0x0
3909 14:44:15.247422 DBI_WR = 0x0
3910 14:44:15.247522 DBI_RD = 0x0
3911 14:44:15.251350 OTF = 0x1
3912 14:44:15.254885 ===================================
3913 14:44:15.257992 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 14:44:15.262903 nWR fixed to 30
3915 14:44:15.266605 [ModeRegInit_LP4] CH0 RK0
3916 14:44:15.266706 [ModeRegInit_LP4] CH0 RK1
3917 14:44:15.269385 [ModeRegInit_LP4] CH1 RK0
3918 14:44:15.272852 [ModeRegInit_LP4] CH1 RK1
3919 14:44:15.272951 match AC timing 17
3920 14:44:15.279932 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 14:44:15.282796 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 14:44:15.287272 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 14:44:15.292865 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 14:44:15.296391 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 14:44:15.296499 ==
3926 14:44:15.299574 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 14:44:15.303115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 14:44:15.303217 ==
3929 14:44:15.309696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 14:44:15.316691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 14:44:15.319659 [CA 0] Center 36 (6~66) winsize 61
3932 14:44:15.323195 [CA 1] Center 36 (6~66) winsize 61
3933 14:44:15.326402 [CA 2] Center 34 (4~65) winsize 62
3934 14:44:15.329580 [CA 3] Center 34 (4~65) winsize 62
3935 14:44:15.333753 [CA 4] Center 34 (4~64) winsize 61
3936 14:44:15.336535 [CA 5] Center 33 (3~64) winsize 62
3937 14:44:15.336636
3938 14:44:15.339460 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 14:44:15.339557
3940 14:44:15.343052 [CATrainingPosCal] consider 1 rank data
3941 14:44:15.346381 u2DelayCellTimex100 = 270/100 ps
3942 14:44:15.350083 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3943 14:44:15.353160 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3944 14:44:15.356513 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 14:44:15.360036 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 14:44:15.363062 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3947 14:44:15.366287 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 14:44:15.366361
3949 14:44:15.369753 CA PerBit enable=1, Macro0, CA PI delay=33
3950 14:44:15.373002
3951 14:44:15.373099 [CBTSetCACLKResult] CA Dly = 33
3952 14:44:15.376904 CS Dly: 4 (0~35)
3953 14:44:15.377026 ==
3954 14:44:15.379849 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 14:44:15.383449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 14:44:15.383535 ==
3957 14:44:15.389831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 14:44:15.396054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3959 14:44:15.399499 [CA 0] Center 36 (6~66) winsize 61
3960 14:44:15.403018 [CA 1] Center 36 (6~66) winsize 61
3961 14:44:15.407307 [CA 2] Center 34 (4~65) winsize 62
3962 14:44:15.409601 [CA 3] Center 34 (4~65) winsize 62
3963 14:44:15.413602 [CA 4] Center 33 (3~64) winsize 62
3964 14:44:15.416602 [CA 5] Center 33 (3~64) winsize 62
3965 14:44:15.416685
3966 14:44:15.420024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3967 14:44:15.420107
3968 14:44:15.423036 [CATrainingPosCal] consider 2 rank data
3969 14:44:15.426088 u2DelayCellTimex100 = 270/100 ps
3970 14:44:15.430149 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3971 14:44:15.433339 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3972 14:44:15.436656 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3973 14:44:15.440299 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3974 14:44:15.443203 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3975 14:44:15.446830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 14:44:15.446912
3977 14:44:15.453213 CA PerBit enable=1, Macro0, CA PI delay=33
3978 14:44:15.453295
3979 14:44:15.453360 [CBTSetCACLKResult] CA Dly = 33
3980 14:44:15.456691 CS Dly: 4 (0~36)
3981 14:44:15.456774
3982 14:44:15.459962 ----->DramcWriteLeveling(PI) begin...
3983 14:44:15.460045 ==
3984 14:44:15.462926 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 14:44:15.466318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 14:44:15.466400 ==
3987 14:44:15.469595 Write leveling (Byte 0): 31 => 31
3988 14:44:15.473198 Write leveling (Byte 1): 29 => 29
3989 14:44:15.476842 DramcWriteLeveling(PI) end<-----
3990 14:44:15.476924
3991 14:44:15.477013 ==
3992 14:44:15.481037 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 14:44:15.483064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 14:44:15.486709 ==
3995 14:44:15.486791 [Gating] SW mode calibration
3996 14:44:15.492876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 14:44:15.500184 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 14:44:15.503430 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 14:44:15.510004 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 14:44:15.512963 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 14:44:15.516653 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 14:44:15.523360 0 9 16 | B1->B0 | 3131 2a2a | 0 1 | (0 1) (1 0)
4003 14:44:15.526487 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 14:44:15.529716 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 14:44:15.533702 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 14:44:15.539991 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 14:44:15.543147 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 14:44:15.546692 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 14:44:15.553532 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4010 14:44:15.556514 0 10 16 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4011 14:44:15.560187 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 14:44:15.566570 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 14:44:15.570115 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 14:44:15.574288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 14:44:15.579921 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 14:44:15.583376 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 14:44:15.587074 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 14:44:15.593259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4019 14:44:15.596418 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 14:44:15.599757 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 14:44:15.607090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 14:44:15.611189 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 14:44:15.612968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 14:44:15.620637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 14:44:15.623050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 14:44:15.626381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 14:44:15.629946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 14:44:15.636735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 14:44:15.639369 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 14:44:15.642885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 14:44:15.650099 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 14:44:15.653395 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 14:44:15.656363 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4034 14:44:15.662972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4035 14:44:15.666270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 14:44:15.669396 Total UI for P1: 0, mck2ui 16
4037 14:44:15.672936 best dqsien dly found for B0: ( 0, 13, 14)
4038 14:44:15.676206 Total UI for P1: 0, mck2ui 16
4039 14:44:15.679965 best dqsien dly found for B1: ( 0, 13, 16)
4040 14:44:15.683222 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4041 14:44:15.686353 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4042 14:44:15.686435
4043 14:44:15.690152 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4044 14:44:15.693831 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 14:44:15.696390 [Gating] SW calibration Done
4046 14:44:15.696476 ==
4047 14:44:15.699572 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 14:44:15.706346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 14:44:15.706429 ==
4050 14:44:15.706493 RX Vref Scan: 0
4051 14:44:15.706555
4052 14:44:15.709460 RX Vref 0 -> 0, step: 1
4053 14:44:15.709541
4054 14:44:15.713410 RX Delay -230 -> 252, step: 16
4055 14:44:15.716302 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4056 14:44:15.719492 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 14:44:15.722944 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 14:44:15.729480 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4059 14:44:15.733337 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 14:44:15.736436 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4061 14:44:15.740787 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 14:44:15.743357 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 14:44:15.750034 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4064 14:44:15.752801 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 14:44:15.756195 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4066 14:44:15.759560 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4067 14:44:15.766974 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4068 14:44:15.769706 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4069 14:44:15.772782 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4070 14:44:15.776424 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4071 14:44:15.776506 ==
4072 14:44:15.779767 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 14:44:15.786055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 14:44:15.786138 ==
4075 14:44:15.786202 DQS Delay:
4076 14:44:15.790051 DQS0 = 0, DQS1 = 0
4077 14:44:15.790133 DQM Delay:
4078 14:44:15.790198 DQM0 = 41, DQM1 = 32
4079 14:44:15.792858 DQ Delay:
4080 14:44:15.796859 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4081 14:44:15.801440 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4082 14:44:15.803216 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4083 14:44:15.806520 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4084 14:44:15.806608
4085 14:44:15.806676
4086 14:44:15.806736 ==
4087 14:44:15.809621 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 14:44:15.812811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 14:44:15.812919 ==
4090 14:44:15.813049
4091 14:44:15.813113
4092 14:44:15.816990 TX Vref Scan disable
4093 14:44:15.817072 == TX Byte 0 ==
4094 14:44:15.822821 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4095 14:44:15.826387 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4096 14:44:15.826469 == TX Byte 1 ==
4097 14:44:15.832927 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4098 14:44:15.836250 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4099 14:44:15.836335 ==
4100 14:44:15.839740 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 14:44:15.843338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 14:44:15.843420 ==
4103 14:44:15.843485
4104 14:44:15.843545
4105 14:44:15.846345 TX Vref Scan disable
4106 14:44:15.849321 == TX Byte 0 ==
4107 14:44:15.853838 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4108 14:44:15.859532 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4109 14:44:15.859613 == TX Byte 1 ==
4110 14:44:15.862827 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4111 14:44:15.869494 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4112 14:44:15.869576
4113 14:44:15.869641 [DATLAT]
4114 14:44:15.869702 Freq=600, CH0 RK0
4115 14:44:15.869761
4116 14:44:15.874280 DATLAT Default: 0x9
4117 14:44:15.874362 0, 0xFFFF, sum = 0
4118 14:44:15.876013 1, 0xFFFF, sum = 0
4119 14:44:15.876097 2, 0xFFFF, sum = 0
4120 14:44:15.879334 3, 0xFFFF, sum = 0
4121 14:44:15.882576 4, 0xFFFF, sum = 0
4122 14:44:15.882660 5, 0xFFFF, sum = 0
4123 14:44:15.886145 6, 0xFFFF, sum = 0
4124 14:44:15.886229 7, 0xFFFF, sum = 0
4125 14:44:15.886296 8, 0x0, sum = 1
4126 14:44:15.889296 9, 0x0, sum = 2
4127 14:44:15.889381 10, 0x0, sum = 3
4128 14:44:15.892776 11, 0x0, sum = 4
4129 14:44:15.892885 best_step = 9
4130 14:44:15.892983
4131 14:44:15.893080 ==
4132 14:44:15.895910 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 14:44:15.902750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 14:44:15.902832 ==
4135 14:44:15.902897 RX Vref Scan: 1
4136 14:44:15.902958
4137 14:44:15.905980 RX Vref 0 -> 0, step: 1
4138 14:44:15.906062
4139 14:44:15.909359 RX Delay -195 -> 252, step: 8
4140 14:44:15.909440
4141 14:44:15.913544 Set Vref, RX VrefLevel [Byte0]: 53
4142 14:44:15.916030 [Byte1]: 51
4143 14:44:15.916111
4144 14:44:15.919577 Final RX Vref Byte 0 = 53 to rank0
4145 14:44:15.922940 Final RX Vref Byte 1 = 51 to rank0
4146 14:44:15.926713 Final RX Vref Byte 0 = 53 to rank1
4147 14:44:15.929604 Final RX Vref Byte 1 = 51 to rank1==
4148 14:44:15.932761 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 14:44:15.935931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 14:44:15.936014 ==
4151 14:44:15.940064 DQS Delay:
4152 14:44:15.940145 DQS0 = 0, DQS1 = 0
4153 14:44:15.940210 DQM Delay:
4154 14:44:15.943049 DQM0 = 42, DQM1 = 33
4155 14:44:15.943130 DQ Delay:
4156 14:44:15.946835 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4157 14:44:15.949676 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4158 14:44:15.952829 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4159 14:44:15.956202 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4160 14:44:15.956283
4161 14:44:15.956347
4162 14:44:15.966827 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d1c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4163 14:44:15.966910 CH0 RK0: MR19=808, MR18=3D1C
4164 14:44:15.972938 CH0_RK0: MR19=0x808, MR18=0x3D1C, DQSOSC=398, MR23=63, INC=165, DEC=110
4165 14:44:15.973069
4166 14:44:15.976553 ----->DramcWriteLeveling(PI) begin...
4167 14:44:15.976640 ==
4168 14:44:15.980081 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 14:44:15.986752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 14:44:15.986834 ==
4171 14:44:15.989727 Write leveling (Byte 0): 31 => 31
4172 14:44:15.993715 Write leveling (Byte 1): 30 => 30
4173 14:44:15.993796 DramcWriteLeveling(PI) end<-----
4174 14:44:15.993861
4175 14:44:15.996712 ==
4176 14:44:15.999915 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 14:44:16.003349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 14:44:16.003444 ==
4179 14:44:16.006277 [Gating] SW mode calibration
4180 14:44:16.012913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 14:44:16.016727 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 14:44:16.022885 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 14:44:16.026633 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 14:44:16.030624 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 14:44:16.036842 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
4186 14:44:16.040658 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4187 14:44:16.043215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 14:44:16.050448 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 14:44:16.053009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 14:44:16.056760 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 14:44:16.060005 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 14:44:16.066943 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 14:44:16.069968 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
4194 14:44:16.073210 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4195 14:44:16.081713 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 14:44:16.082856 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 14:44:16.086353 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 14:44:16.092880 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 14:44:16.096485 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 14:44:16.100249 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 14:44:16.106204 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4202 14:44:16.109789 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4203 14:44:16.112916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4204 14:44:16.119541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 14:44:16.122882 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 14:44:16.126324 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 14:44:16.133343 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 14:44:16.136143 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 14:44:16.139385 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 14:44:16.146321 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 14:44:16.149474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 14:44:16.152630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 14:44:16.160200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 14:44:16.163430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 14:44:16.166352 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 14:44:16.173140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 14:44:16.176291 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4218 14:44:16.179817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4219 14:44:16.183229 Total UI for P1: 0, mck2ui 16
4220 14:44:16.186061 best dqsien dly found for B0: ( 0, 13, 12)
4221 14:44:16.189843 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 14:44:16.192768 Total UI for P1: 0, mck2ui 16
4223 14:44:16.196452 best dqsien dly found for B1: ( 0, 13, 14)
4224 14:44:16.200381 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4225 14:44:16.206545 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4226 14:44:16.206627
4227 14:44:16.209671 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4228 14:44:16.213103 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4229 14:44:16.216386 [Gating] SW calibration Done
4230 14:44:16.216468 ==
4231 14:44:16.219503 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 14:44:16.223146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 14:44:16.223228 ==
4234 14:44:16.223294 RX Vref Scan: 0
4235 14:44:16.226172
4236 14:44:16.226254 RX Vref 0 -> 0, step: 1
4237 14:44:16.226319
4238 14:44:16.229432 RX Delay -230 -> 252, step: 16
4239 14:44:16.233078 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4240 14:44:16.239332 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4241 14:44:16.242825 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4242 14:44:16.246075 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4243 14:44:16.249495 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4244 14:44:16.252892 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4245 14:44:16.259482 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4246 14:44:16.263124 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4247 14:44:16.266169 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4248 14:44:16.270213 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4249 14:44:16.273428 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4250 14:44:16.280291 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4251 14:44:16.282936 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4252 14:44:16.286626 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4253 14:44:16.289714 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4254 14:44:16.296192 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4255 14:44:16.296274 ==
4256 14:44:16.299792 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 14:44:16.303410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 14:44:16.303518 ==
4259 14:44:16.303612 DQS Delay:
4260 14:44:16.306372 DQS0 = 0, DQS1 = 0
4261 14:44:16.306480 DQM Delay:
4262 14:44:16.309868 DQM0 = 42, DQM1 = 35
4263 14:44:16.309949 DQ Delay:
4264 14:44:16.313285 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4265 14:44:16.316624 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4266 14:44:16.319844 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4267 14:44:16.323578 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4268 14:44:16.323659
4269 14:44:16.323724
4270 14:44:16.323784 ==
4271 14:44:16.326815 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 14:44:16.329591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 14:44:16.329673 ==
4274 14:44:16.329738
4275 14:44:16.333243
4276 14:44:16.333324 TX Vref Scan disable
4277 14:44:16.336906 == TX Byte 0 ==
4278 14:44:16.339799 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4279 14:44:16.343345 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4280 14:44:16.346823 == TX Byte 1 ==
4281 14:44:16.350156 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 14:44:16.353193 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 14:44:16.353275 ==
4284 14:44:16.356591 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 14:44:16.363171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 14:44:16.363279 ==
4287 14:44:16.363372
4288 14:44:16.363463
4289 14:44:16.363550 TX Vref Scan disable
4290 14:44:16.367862 == TX Byte 0 ==
4291 14:44:16.370887 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4292 14:44:16.374381 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4293 14:44:16.377374 == TX Byte 1 ==
4294 14:44:16.381321 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4295 14:44:16.384393 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4296 14:44:16.388061
4297 14:44:16.388142 [DATLAT]
4298 14:44:16.388207 Freq=600, CH0 RK1
4299 14:44:16.388268
4300 14:44:16.391141 DATLAT Default: 0x9
4301 14:44:16.391222 0, 0xFFFF, sum = 0
4302 14:44:16.394511 1, 0xFFFF, sum = 0
4303 14:44:16.394594 2, 0xFFFF, sum = 0
4304 14:44:16.397408 3, 0xFFFF, sum = 0
4305 14:44:16.397491 4, 0xFFFF, sum = 0
4306 14:44:16.401613 5, 0xFFFF, sum = 0
4307 14:44:16.401696 6, 0xFFFF, sum = 0
4308 14:44:16.404462 7, 0xFFFF, sum = 0
4309 14:44:16.404544 8, 0x0, sum = 1
4310 14:44:16.407974 9, 0x0, sum = 2
4311 14:44:16.408057 10, 0x0, sum = 3
4312 14:44:16.411294 11, 0x0, sum = 4
4313 14:44:16.411386 best_step = 9
4314 14:44:16.411451
4315 14:44:16.411512 ==
4316 14:44:16.414988 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 14:44:16.421149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 14:44:16.421239 ==
4319 14:44:16.421304 RX Vref Scan: 0
4320 14:44:16.421365
4321 14:44:16.424213 RX Vref 0 -> 0, step: 1
4322 14:44:16.424294
4323 14:44:16.428118 RX Delay -195 -> 252, step: 8
4324 14:44:16.430735 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4325 14:44:16.437925 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4326 14:44:16.440671 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4327 14:44:16.444492 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4328 14:44:16.447717 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4329 14:44:16.450947 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4330 14:44:16.457343 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4331 14:44:16.460598 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4332 14:44:16.464363 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4333 14:44:16.467408 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4334 14:44:16.474443 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4335 14:44:16.477874 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4336 14:44:16.480918 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4337 14:44:16.484161 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4338 14:44:16.490923 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4339 14:44:16.494342 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4340 14:44:16.494423 ==
4341 14:44:16.497288 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 14:44:16.500932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 14:44:16.501062 ==
4344 14:44:16.501130 DQS Delay:
4345 14:44:16.505726 DQS0 = 0, DQS1 = 0
4346 14:44:16.505808 DQM Delay:
4347 14:44:16.508116 DQM0 = 40, DQM1 = 33
4348 14:44:16.508197 DQ Delay:
4349 14:44:16.511312 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4350 14:44:16.514115 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4351 14:44:16.517889 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4352 14:44:16.520596 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4353 14:44:16.520679
4354 14:44:16.520755
4355 14:44:16.530686 [DQSOSCAuto] RK1, (LSB)MR18= 0x482a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4356 14:44:16.530768 CH0 RK1: MR19=808, MR18=482A
4357 14:44:16.537933 CH0_RK1: MR19=0x808, MR18=0x482A, DQSOSC=396, MR23=63, INC=167, DEC=111
4358 14:44:16.541096 [RxdqsGatingPostProcess] freq 600
4359 14:44:16.547913 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4360 14:44:16.551350 Pre-setting of DQS Precalculation
4361 14:44:16.554038 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4362 14:44:16.554120 ==
4363 14:44:16.557788 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 14:44:16.561182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 14:44:16.561265 ==
4366 14:44:16.567391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 14:44:16.574351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4368 14:44:16.578208 [CA 0] Center 35 (5~66) winsize 62
4369 14:44:16.580770 [CA 1] Center 35 (5~66) winsize 62
4370 14:44:16.584754 [CA 2] Center 34 (4~65) winsize 62
4371 14:44:16.588904 [CA 3] Center 33 (3~64) winsize 62
4372 14:44:16.590945 [CA 4] Center 34 (3~65) winsize 63
4373 14:44:16.595190 [CA 5] Center 33 (3~64) winsize 62
4374 14:44:16.595274
4375 14:44:16.597801 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4376 14:44:16.597883
4377 14:44:16.601623 [CATrainingPosCal] consider 1 rank data
4378 14:44:16.604285 u2DelayCellTimex100 = 270/100 ps
4379 14:44:16.608213 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 14:44:16.612145 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 14:44:16.616384 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 14:44:16.617817 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 14:44:16.621240 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4384 14:44:16.624433 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 14:44:16.624535
4386 14:44:16.631396 CA PerBit enable=1, Macro0, CA PI delay=33
4387 14:44:16.631477
4388 14:44:16.634351 [CBTSetCACLKResult] CA Dly = 33
4389 14:44:16.634433 CS Dly: 4 (0~35)
4390 14:44:16.634498 ==
4391 14:44:16.637724 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 14:44:16.641335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 14:44:16.641417 ==
4394 14:44:16.647612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4395 14:44:16.654193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4396 14:44:16.657661 [CA 0] Center 35 (5~66) winsize 62
4397 14:44:16.661508 [CA 1] Center 35 (5~66) winsize 62
4398 14:44:16.664494 [CA 2] Center 34 (3~65) winsize 63
4399 14:44:16.667968 [CA 3] Center 33 (3~64) winsize 62
4400 14:44:16.671161 [CA 4] Center 34 (4~65) winsize 62
4401 14:44:16.674578 [CA 5] Center 33 (3~64) winsize 62
4402 14:44:16.674660
4403 14:44:16.678088 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4404 14:44:16.678170
4405 14:44:16.681178 [CATrainingPosCal] consider 2 rank data
4406 14:44:16.684860 u2DelayCellTimex100 = 270/100 ps
4407 14:44:16.688513 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4408 14:44:16.692236 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 14:44:16.694611 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 14:44:16.697887 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 14:44:16.701751 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4412 14:44:16.704808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 14:44:16.704916
4414 14:44:16.711110 CA PerBit enable=1, Macro0, CA PI delay=33
4415 14:44:16.711193
4416 14:44:16.714299 [CBTSetCACLKResult] CA Dly = 33
4417 14:44:16.714382 CS Dly: 5 (0~37)
4418 14:44:16.714447
4419 14:44:16.717668 ----->DramcWriteLeveling(PI) begin...
4420 14:44:16.717758 ==
4421 14:44:16.721416 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 14:44:16.725288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 14:44:16.725372 ==
4424 14:44:16.727859 Write leveling (Byte 0): 28 => 28
4425 14:44:16.731419 Write leveling (Byte 1): 29 => 29
4426 14:44:16.734446 DramcWriteLeveling(PI) end<-----
4427 14:44:16.734528
4428 14:44:16.734592 ==
4429 14:44:16.737582 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 14:44:16.744747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 14:44:16.744855 ==
4432 14:44:16.744949 [Gating] SW mode calibration
4433 14:44:16.754785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 14:44:16.758339 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4435 14:44:16.761195 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 14:44:16.767723 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 14:44:16.770965 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4438 14:44:16.774238 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4439 14:44:16.780839 0 9 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
4440 14:44:16.784348 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 14:44:16.788248 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4442 14:44:16.795188 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 14:44:16.798268 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 14:44:16.801285 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 14:44:16.807649 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 14:44:16.811422 0 10 12 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
4447 14:44:16.814555 0 10 16 | B1->B0 | 3e3e 4343 | 1 0 | (0 0) (0 0)
4448 14:44:16.818107 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 14:44:16.824660 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 14:44:16.828618 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 14:44:16.830875 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 14:44:16.837915 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 14:44:16.840980 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 14:44:16.844271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 14:44:16.851151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 14:44:16.854859 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 14:44:16.857653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 14:44:16.864253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 14:44:16.867494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 14:44:16.871245 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 14:44:16.878126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 14:44:16.881302 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 14:44:16.885217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 14:44:16.890878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 14:44:16.894280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 14:44:16.897777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 14:44:16.904246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 14:44:16.907836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 14:44:16.911197 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 14:44:16.917667 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4471 14:44:16.921253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 14:44:16.924350 Total UI for P1: 0, mck2ui 16
4473 14:44:16.928026 best dqsien dly found for B0: ( 0, 13, 12)
4474 14:44:16.930873 Total UI for P1: 0, mck2ui 16
4475 14:44:16.935181 best dqsien dly found for B1: ( 0, 13, 14)
4476 14:44:16.937836 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4477 14:44:16.941159 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4478 14:44:16.941242
4479 14:44:16.943968 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 14:44:16.948078 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4481 14:44:16.951031 [Gating] SW calibration Done
4482 14:44:16.951114 ==
4483 14:44:16.954826 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 14:44:16.957432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 14:44:16.957516 ==
4486 14:44:16.960917 RX Vref Scan: 0
4487 14:44:16.961039
4488 14:44:16.964225 RX Vref 0 -> 0, step: 1
4489 14:44:16.964307
4490 14:44:16.964373 RX Delay -230 -> 252, step: 16
4491 14:44:16.970991 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4492 14:44:16.975110 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4493 14:44:16.978263 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4494 14:44:16.980834 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4495 14:44:16.987504 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4496 14:44:16.991234 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4497 14:44:16.994441 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4498 14:44:16.997903 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4499 14:44:17.001483 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 14:44:17.007876 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4501 14:44:17.011165 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4502 14:44:17.014369 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4503 14:44:17.017516 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4504 14:44:17.024965 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4505 14:44:17.027928 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4506 14:44:17.031264 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4507 14:44:17.031347 ==
4508 14:44:17.034892 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 14:44:17.037398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 14:44:17.037481 ==
4511 14:44:17.041444 DQS Delay:
4512 14:44:17.041527 DQS0 = 0, DQS1 = 0
4513 14:44:17.044417 DQM Delay:
4514 14:44:17.044500 DQM0 = 43, DQM1 = 37
4515 14:44:17.044565 DQ Delay:
4516 14:44:17.048149 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4517 14:44:17.051952 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4518 14:44:17.054479 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =41
4519 14:44:17.058019 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4520 14:44:17.058102
4521 14:44:17.058166
4522 14:44:17.060754 ==
4523 14:44:17.064577 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 14:44:17.067481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 14:44:17.067564 ==
4526 14:44:17.067630
4527 14:44:17.067691
4528 14:44:17.070980 TX Vref Scan disable
4529 14:44:17.071066 == TX Byte 0 ==
4530 14:44:17.077517 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 14:44:17.081718 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 14:44:17.081808 == TX Byte 1 ==
4533 14:44:17.087590 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 14:44:17.091598 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 14:44:17.091681 ==
4536 14:44:17.094441 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 14:44:17.097278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 14:44:17.097362 ==
4539 14:44:17.097428
4540 14:44:17.097505
4541 14:44:17.100809 TX Vref Scan disable
4542 14:44:17.104352 == TX Byte 0 ==
4543 14:44:17.107624 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4544 14:44:17.110640 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4545 14:44:17.113988 == TX Byte 1 ==
4546 14:44:17.117357 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 14:44:17.120720 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 14:44:17.120803
4549 14:44:17.124624 [DATLAT]
4550 14:44:17.124707 Freq=600, CH1 RK0
4551 14:44:17.124773
4552 14:44:17.127491 DATLAT Default: 0x9
4553 14:44:17.127574 0, 0xFFFF, sum = 0
4554 14:44:17.131562 1, 0xFFFF, sum = 0
4555 14:44:17.131647 2, 0xFFFF, sum = 0
4556 14:44:17.134474 3, 0xFFFF, sum = 0
4557 14:44:17.134561 4, 0xFFFF, sum = 0
4558 14:44:17.137893 5, 0xFFFF, sum = 0
4559 14:44:17.137976 6, 0xFFFF, sum = 0
4560 14:44:17.141215 7, 0xFFFF, sum = 0
4561 14:44:17.141299 8, 0x0, sum = 1
4562 14:44:17.144188 9, 0x0, sum = 2
4563 14:44:17.144272 10, 0x0, sum = 3
4564 14:44:17.147764 11, 0x0, sum = 4
4565 14:44:17.147848 best_step = 9
4566 14:44:17.147926
4567 14:44:17.147989 ==
4568 14:44:17.151103 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 14:44:17.154626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 14:44:17.154709 ==
4571 14:44:17.157745 RX Vref Scan: 1
4572 14:44:17.157827
4573 14:44:17.161295 RX Vref 0 -> 0, step: 1
4574 14:44:17.161378
4575 14:44:17.161444 RX Delay -195 -> 252, step: 8
4576 14:44:17.161505
4577 14:44:17.164510 Set Vref, RX VrefLevel [Byte0]: 57
4578 14:44:17.168713 [Byte1]: 53
4579 14:44:17.172465
4580 14:44:17.172547 Final RX Vref Byte 0 = 57 to rank0
4581 14:44:17.175824 Final RX Vref Byte 1 = 53 to rank0
4582 14:44:17.179011 Final RX Vref Byte 0 = 57 to rank1
4583 14:44:17.182202 Final RX Vref Byte 1 = 53 to rank1==
4584 14:44:17.185822 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 14:44:17.191958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 14:44:17.192041 ==
4587 14:44:17.192108 DQS Delay:
4588 14:44:17.192170 DQS0 = 0, DQS1 = 0
4589 14:44:17.195535 DQM Delay:
4590 14:44:17.195619 DQM0 = 40, DQM1 = 33
4591 14:44:17.199218 DQ Delay:
4592 14:44:17.202578 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4593 14:44:17.202661 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4594 14:44:17.205428 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4595 14:44:17.208959 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4596 14:44:17.212992
4597 14:44:17.213076
4598 14:44:17.219101 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
4599 14:44:17.222325 CH1 RK0: MR19=808, MR18=3F04
4600 14:44:17.230235 CH1_RK0: MR19=0x808, MR18=0x3F04, DQSOSC=397, MR23=63, INC=166, DEC=110
4601 14:44:17.230318
4602 14:44:17.232278 ----->DramcWriteLeveling(PI) begin...
4603 14:44:17.232363 ==
4604 14:44:17.235400 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 14:44:17.238751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 14:44:17.238835 ==
4607 14:44:17.242233 Write leveling (Byte 0): 30 => 30
4608 14:44:17.245742 Write leveling (Byte 1): 30 => 30
4609 14:44:17.249275 DramcWriteLeveling(PI) end<-----
4610 14:44:17.249359
4611 14:44:17.249425 ==
4612 14:44:17.252487 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 14:44:17.255775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 14:44:17.255858 ==
4615 14:44:17.259789 [Gating] SW mode calibration
4616 14:44:17.265457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 14:44:17.272297 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 14:44:17.275630 0 9 0 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4619 14:44:17.279449 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4620 14:44:17.286028 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4621 14:44:17.289008 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4622 14:44:17.292291 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 14:44:17.299683 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 14:44:17.302180 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 14:44:17.305883 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 14:44:17.312121 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4627 14:44:17.315452 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 14:44:17.318985 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4629 14:44:17.325651 0 10 12 | B1->B0 | 2f2f 3b3b | 1 0 | (0 0) (0 0)
4630 14:44:17.329248 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 14:44:17.332421 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 14:44:17.335676 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 14:44:17.342336 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 14:44:17.345727 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 14:44:17.348898 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 14:44:17.355815 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 14:44:17.359153 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4638 14:44:17.362490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 14:44:17.370583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 14:44:17.372729 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 14:44:17.375709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 14:44:17.382559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 14:44:17.386465 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 14:44:17.389680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 14:44:17.395797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 14:44:17.399968 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 14:44:17.402446 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 14:44:17.409206 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 14:44:17.412536 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 14:44:17.416666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 14:44:17.419282 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 14:44:17.425890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4653 14:44:17.429147 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 14:44:17.433176 Total UI for P1: 0, mck2ui 16
4655 14:44:17.435755 best dqsien dly found for B0: ( 0, 13, 8)
4656 14:44:17.440494 Total UI for P1: 0, mck2ui 16
4657 14:44:17.442881 best dqsien dly found for B1: ( 0, 13, 10)
4658 14:44:17.445909 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4659 14:44:17.449242 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4660 14:44:17.449317
4661 14:44:17.453327 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4662 14:44:17.456266 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4663 14:44:17.458973 [Gating] SW calibration Done
4664 14:44:17.459076 ==
4665 14:44:17.462276 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 14:44:17.469177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 14:44:17.469263 ==
4668 14:44:17.469333 RX Vref Scan: 0
4669 14:44:17.469396
4670 14:44:17.472797 RX Vref 0 -> 0, step: 1
4671 14:44:17.472897
4672 14:44:17.476656 RX Delay -230 -> 252, step: 16
4673 14:44:17.480320 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4674 14:44:17.483387 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4675 14:44:17.485818 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4676 14:44:17.492779 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4677 14:44:17.495834 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4678 14:44:17.500076 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4679 14:44:17.502719 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4680 14:44:17.505862 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4681 14:44:17.512443 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4682 14:44:17.515716 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4683 14:44:17.519404 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4684 14:44:17.522496 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4685 14:44:17.529197 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4686 14:44:17.532697 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4687 14:44:17.536024 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4688 14:44:17.539469 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4689 14:44:17.539575 ==
4690 14:44:17.542978 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 14:44:17.549687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 14:44:17.549792 ==
4693 14:44:17.549890 DQS Delay:
4694 14:44:17.549982 DQS0 = 0, DQS1 = 0
4695 14:44:17.552970 DQM Delay:
4696 14:44:17.553082 DQM0 = 39, DQM1 = 36
4697 14:44:17.557267 DQ Delay:
4698 14:44:17.559376 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4699 14:44:17.559483 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4700 14:44:17.562610 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4701 14:44:17.569305 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4702 14:44:17.569408
4703 14:44:17.569501
4704 14:44:17.569595 ==
4705 14:44:17.572488 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 14:44:17.576094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 14:44:17.576196 ==
4708 14:44:17.576292
4709 14:44:17.576418
4710 14:44:17.579109 TX Vref Scan disable
4711 14:44:17.579187 == TX Byte 0 ==
4712 14:44:17.586513 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 14:44:17.590309 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 14:44:17.590413 == TX Byte 1 ==
4715 14:44:17.596120 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4716 14:44:17.599219 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4717 14:44:17.599322 ==
4718 14:44:17.603267 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 14:44:17.606255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 14:44:17.606357 ==
4721 14:44:17.606449
4722 14:44:17.606537
4723 14:44:17.609838 TX Vref Scan disable
4724 14:44:17.612588 == TX Byte 0 ==
4725 14:44:17.616608 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 14:44:17.619492 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 14:44:17.622412 == TX Byte 1 ==
4728 14:44:17.626682 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4729 14:44:17.629370 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4730 14:44:17.629469
4731 14:44:17.632605 [DATLAT]
4732 14:44:17.632695 Freq=600, CH1 RK1
4733 14:44:17.632761
4734 14:44:17.635914 DATLAT Default: 0x9
4735 14:44:17.635997 0, 0xFFFF, sum = 0
4736 14:44:17.639481 1, 0xFFFF, sum = 0
4737 14:44:17.639566 2, 0xFFFF, sum = 0
4738 14:44:17.642969 3, 0xFFFF, sum = 0
4739 14:44:17.643053 4, 0xFFFF, sum = 0
4740 14:44:17.646164 5, 0xFFFF, sum = 0
4741 14:44:17.646249 6, 0xFFFF, sum = 0
4742 14:44:17.650113 7, 0xFFFF, sum = 0
4743 14:44:17.650197 8, 0x0, sum = 1
4744 14:44:17.652637 9, 0x0, sum = 2
4745 14:44:17.652721 10, 0x0, sum = 3
4746 14:44:17.656716 11, 0x0, sum = 4
4747 14:44:17.656801 best_step = 9
4748 14:44:17.656867
4749 14:44:17.656929 ==
4750 14:44:17.659553 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 14:44:17.663139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 14:44:17.666241 ==
4753 14:44:17.666324 RX Vref Scan: 0
4754 14:44:17.666390
4755 14:44:17.669403 RX Vref 0 -> 0, step: 1
4756 14:44:17.669486
4757 14:44:17.672648 RX Delay -195 -> 252, step: 8
4758 14:44:17.676152 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4759 14:44:17.679640 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 14:44:17.685748 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4761 14:44:17.689454 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4762 14:44:17.692620 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4763 14:44:17.697376 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4764 14:44:17.703045 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 14:44:17.705974 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4766 14:44:17.709331 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4767 14:44:17.712907 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4768 14:44:17.716065 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4769 14:44:17.722598 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4770 14:44:17.725866 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4771 14:44:17.729413 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4772 14:44:17.733082 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4773 14:44:17.739476 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4774 14:44:17.739559 ==
4775 14:44:17.742887 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 14:44:17.746058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 14:44:17.746142 ==
4778 14:44:17.746208 DQS Delay:
4779 14:44:17.749968 DQS0 = 0, DQS1 = 0
4780 14:44:17.750051 DQM Delay:
4781 14:44:17.753219 DQM0 = 38, DQM1 = 33
4782 14:44:17.753302 DQ Delay:
4783 14:44:17.755831 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4784 14:44:17.759097 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4785 14:44:17.763079 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4786 14:44:17.766054 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4787 14:44:17.766138
4788 14:44:17.766203
4789 14:44:17.772545 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4790 14:44:17.775992 CH1 RK1: MR19=808, MR18=3B4A
4791 14:44:17.782649 CH1_RK1: MR19=0x808, MR18=0x3B4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4792 14:44:17.786055 [RxdqsGatingPostProcess] freq 600
4793 14:44:17.793217 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 14:44:17.795766 Pre-setting of DQS Precalculation
4795 14:44:17.799422 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 14:44:17.805855 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 14:44:17.812408 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 14:44:17.812521
4799 14:44:17.812618
4800 14:44:17.815745 [Calibration Summary] 1200 Mbps
4801 14:44:17.819597 CH 0, Rank 0
4802 14:44:17.819709 SW Impedance : PASS
4803 14:44:17.822639 DUTY Scan : NO K
4804 14:44:17.826144 ZQ Calibration : PASS
4805 14:44:17.826252 Jitter Meter : NO K
4806 14:44:17.829528 CBT Training : PASS
4807 14:44:17.829605 Write leveling : PASS
4808 14:44:17.832665 RX DQS gating : PASS
4809 14:44:17.836266 RX DQ/DQS(RDDQC) : PASS
4810 14:44:17.836377 TX DQ/DQS : PASS
4811 14:44:17.839540 RX DATLAT : PASS
4812 14:44:17.842390 RX DQ/DQS(Engine): PASS
4813 14:44:17.842514 TX OE : NO K
4814 14:44:17.846363 All Pass.
4815 14:44:17.846468
4816 14:44:17.846561 CH 0, Rank 1
4817 14:44:17.849401 SW Impedance : PASS
4818 14:44:17.849501 DUTY Scan : NO K
4819 14:44:17.852378 ZQ Calibration : PASS
4820 14:44:17.855922 Jitter Meter : NO K
4821 14:44:17.856023 CBT Training : PASS
4822 14:44:17.859241 Write leveling : PASS
4823 14:44:17.862704 RX DQS gating : PASS
4824 14:44:17.862803 RX DQ/DQS(RDDQC) : PASS
4825 14:44:17.866126 TX DQ/DQS : PASS
4826 14:44:17.869600 RX DATLAT : PASS
4827 14:44:17.869700 RX DQ/DQS(Engine): PASS
4828 14:44:17.872507 TX OE : NO K
4829 14:44:17.872607 All Pass.
4830 14:44:17.872700
4831 14:44:17.872797 CH 1, Rank 0
4832 14:44:17.876254 SW Impedance : PASS
4833 14:44:17.879522 DUTY Scan : NO K
4834 14:44:17.879626 ZQ Calibration : PASS
4835 14:44:17.882605 Jitter Meter : NO K
4836 14:44:17.885956 CBT Training : PASS
4837 14:44:17.886057 Write leveling : PASS
4838 14:44:17.890096 RX DQS gating : PASS
4839 14:44:17.892819 RX DQ/DQS(RDDQC) : PASS
4840 14:44:17.892923 TX DQ/DQS : PASS
4841 14:44:17.896213 RX DATLAT : PASS
4842 14:44:17.899532 RX DQ/DQS(Engine): PASS
4843 14:44:17.899635 TX OE : NO K
4844 14:44:17.902867 All Pass.
4845 14:44:17.902966
4846 14:44:17.903062 CH 1, Rank 1
4847 14:44:17.906178 SW Impedance : PASS
4848 14:44:17.906277 DUTY Scan : NO K
4849 14:44:17.909459 ZQ Calibration : PASS
4850 14:44:17.912858 Jitter Meter : NO K
4851 14:44:17.912961 CBT Training : PASS
4852 14:44:17.916455 Write leveling : PASS
4853 14:44:17.916559 RX DQS gating : PASS
4854 14:44:17.919800 RX DQ/DQS(RDDQC) : PASS
4855 14:44:17.922533 TX DQ/DQS : PASS
4856 14:44:17.922636 RX DATLAT : PASS
4857 14:44:17.926247 RX DQ/DQS(Engine): PASS
4858 14:44:17.929188 TX OE : NO K
4859 14:44:17.929292 All Pass.
4860 14:44:17.929384
4861 14:44:17.933560 DramC Write-DBI off
4862 14:44:17.933636 PER_BANK_REFRESH: Hybrid Mode
4863 14:44:17.937399 TX_TRACKING: ON
4864 14:44:17.942902 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 14:44:17.949737 [FAST_K] Save calibration result to emmc
4866 14:44:17.952718 dramc_set_vcore_voltage set vcore to 662500
4867 14:44:17.952822 Read voltage for 933, 3
4868 14:44:17.955952 Vio18 = 0
4869 14:44:17.956053 Vcore = 662500
4870 14:44:17.956147 Vdram = 0
4871 14:44:17.959475 Vddq = 0
4872 14:44:17.959576 Vmddr = 0
4873 14:44:17.962634 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 14:44:17.969435 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 14:44:17.973482 MEM_TYPE=3, freq_sel=17
4876 14:44:17.973584 sv_algorithm_assistance_LP4_1600
4877 14:44:17.979915 ============ PULL DRAM RESETB DOWN ============
4878 14:44:17.983226 ========== PULL DRAM RESETB DOWN end =========
4879 14:44:17.986657 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 14:44:17.989779 ===================================
4881 14:44:17.993211 LPDDR4 DRAM CONFIGURATION
4882 14:44:17.996367 ===================================
4883 14:44:17.999587 EX_ROW_EN[0] = 0x0
4884 14:44:17.999693 EX_ROW_EN[1] = 0x0
4885 14:44:18.003347 LP4Y_EN = 0x0
4886 14:44:18.003449 WORK_FSP = 0x0
4887 14:44:18.006743 WL = 0x3
4888 14:44:18.006847 RL = 0x3
4889 14:44:18.010077 BL = 0x2
4890 14:44:18.010178 RPST = 0x0
4891 14:44:18.013131 RD_PRE = 0x0
4892 14:44:18.013243 WR_PRE = 0x1
4893 14:44:18.016253 WR_PST = 0x0
4894 14:44:18.016353 DBI_WR = 0x0
4895 14:44:18.019915 DBI_RD = 0x0
4896 14:44:18.019998 OTF = 0x1
4897 14:44:18.023184 ===================================
4898 14:44:18.026559 ===================================
4899 14:44:18.029880 ANA top config
4900 14:44:18.033052 ===================================
4901 14:44:18.036877 DLL_ASYNC_EN = 0
4902 14:44:18.036984 ALL_SLAVE_EN = 1
4903 14:44:18.039620 NEW_RANK_MODE = 1
4904 14:44:18.043878 DLL_IDLE_MODE = 1
4905 14:44:18.046400 LP45_APHY_COMB_EN = 1
4906 14:44:18.046508 TX_ODT_DIS = 1
4907 14:44:18.049731 NEW_8X_MODE = 1
4908 14:44:18.053241 ===================================
4909 14:44:18.056568 ===================================
4910 14:44:18.059792 data_rate = 1866
4911 14:44:18.063508 CKR = 1
4912 14:44:18.066308 DQ_P2S_RATIO = 8
4913 14:44:18.069742 ===================================
4914 14:44:18.069852 CA_P2S_RATIO = 8
4915 14:44:18.073258 DQ_CA_OPEN = 0
4916 14:44:18.076378 DQ_SEMI_OPEN = 0
4917 14:44:18.079740 CA_SEMI_OPEN = 0
4918 14:44:18.083360 CA_FULL_RATE = 0
4919 14:44:18.086657 DQ_CKDIV4_EN = 1
4920 14:44:18.086759 CA_CKDIV4_EN = 1
4921 14:44:18.089852 CA_PREDIV_EN = 0
4922 14:44:18.093265 PH8_DLY = 0
4923 14:44:18.096931 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 14:44:18.099610 DQ_AAMCK_DIV = 4
4925 14:44:18.103397 CA_AAMCK_DIV = 4
4926 14:44:18.103500 CA_ADMCK_DIV = 4
4927 14:44:18.106233 DQ_TRACK_CA_EN = 0
4928 14:44:18.109683 CA_PICK = 933
4929 14:44:18.113151 CA_MCKIO = 933
4930 14:44:18.116542 MCKIO_SEMI = 0
4931 14:44:18.119801 PLL_FREQ = 3732
4932 14:44:18.123215 DQ_UI_PI_RATIO = 32
4933 14:44:18.123318 CA_UI_PI_RATIO = 0
4934 14:44:18.126556 ===================================
4935 14:44:18.130415 ===================================
4936 14:44:18.133365 memory_type:LPDDR4
4937 14:44:18.136805 GP_NUM : 10
4938 14:44:18.136906 SRAM_EN : 1
4939 14:44:18.139925 MD32_EN : 0
4940 14:44:18.143128 ===================================
4941 14:44:18.146605 [ANA_INIT] >>>>>>>>>>>>>>
4942 14:44:18.146708 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 14:44:18.149811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 14:44:18.153760 ===================================
4945 14:44:18.156894 data_rate = 1866,PCW = 0X8f00
4946 14:44:18.160004 ===================================
4947 14:44:18.163193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 14:44:18.170018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 14:44:18.176788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 14:44:18.180317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 14:44:18.183214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 14:44:18.186853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 14:44:18.189758 [ANA_INIT] flow start
4954 14:44:18.189833 [ANA_INIT] PLL >>>>>>>>
4955 14:44:18.193343 [ANA_INIT] PLL <<<<<<<<
4956 14:44:18.196677 [ANA_INIT] MIDPI >>>>>>>>
4957 14:44:18.196782 [ANA_INIT] MIDPI <<<<<<<<
4958 14:44:18.200013 [ANA_INIT] DLL >>>>>>>>
4959 14:44:18.203450 [ANA_INIT] flow end
4960 14:44:18.206833 ============ LP4 DIFF to SE enter ============
4961 14:44:18.209699 ============ LP4 DIFF to SE exit ============
4962 14:44:18.214375 [ANA_INIT] <<<<<<<<<<<<<
4963 14:44:18.216714 [Flow] Enable top DCM control >>>>>
4964 14:44:18.219873 [Flow] Enable top DCM control <<<<<
4965 14:44:18.223591 Enable DLL master slave shuffle
4966 14:44:18.226949 ==============================================================
4967 14:44:18.229847 Gating Mode config
4968 14:44:18.236534 ==============================================================
4969 14:44:18.236641 Config description:
4970 14:44:18.246758 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 14:44:18.253168 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 14:44:18.257212 SELPH_MODE 0: By rank 1: By Phase
4973 14:44:18.263269 ==============================================================
4974 14:44:18.267154 GAT_TRACK_EN = 1
4975 14:44:18.270342 RX_GATING_MODE = 2
4976 14:44:18.273509 RX_GATING_TRACK_MODE = 2
4977 14:44:18.276643 SELPH_MODE = 1
4978 14:44:18.280254 PICG_EARLY_EN = 1
4979 14:44:18.283607 VALID_LAT_VALUE = 1
4980 14:44:18.286680 ==============================================================
4981 14:44:18.290295 Enter into Gating configuration >>>>
4982 14:44:18.293283 Exit from Gating configuration <<<<
4983 14:44:18.297210 Enter into DVFS_PRE_config >>>>>
4984 14:44:18.306857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 14:44:18.310237 Exit from DVFS_PRE_config <<<<<
4986 14:44:18.313494 Enter into PICG configuration >>>>
4987 14:44:18.317617 Exit from PICG configuration <<<<
4988 14:44:18.320207 [RX_INPUT] configuration >>>>>
4989 14:44:18.323522 [RX_INPUT] configuration <<<<<
4990 14:44:18.330595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 14:44:18.333374 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 14:44:18.340412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 14:44:18.346766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 14:44:18.353360 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 14:44:18.360327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 14:44:18.363554 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 14:44:18.366716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 14:44:18.369988 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 14:44:18.373912 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 14:44:18.380219 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 14:44:18.383476 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 14:44:18.386653 ===================================
5003 14:44:18.390130 LPDDR4 DRAM CONFIGURATION
5004 14:44:18.393052 ===================================
5005 14:44:18.393149 EX_ROW_EN[0] = 0x0
5006 14:44:18.396631 EX_ROW_EN[1] = 0x0
5007 14:44:18.396731 LP4Y_EN = 0x0
5008 14:44:18.399705 WORK_FSP = 0x0
5009 14:44:18.399808 WL = 0x3
5010 14:44:18.403563 RL = 0x3
5011 14:44:18.403665 BL = 0x2
5012 14:44:18.406910 RPST = 0x0
5013 14:44:18.407013 RD_PRE = 0x0
5014 14:44:18.409976 WR_PRE = 0x1
5015 14:44:18.413299 WR_PST = 0x0
5016 14:44:18.413405 DBI_WR = 0x0
5017 14:44:18.416905 DBI_RD = 0x0
5018 14:44:18.417009 OTF = 0x1
5019 14:44:18.420592 ===================================
5020 14:44:18.423442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 14:44:18.427143 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 14:44:18.433826 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 14:44:18.437649 ===================================
5024 14:44:18.437741 LPDDR4 DRAM CONFIGURATION
5025 14:44:18.440464 ===================================
5026 14:44:18.443651 EX_ROW_EN[0] = 0x10
5027 14:44:18.448204 EX_ROW_EN[1] = 0x0
5028 14:44:18.448288 LP4Y_EN = 0x0
5029 14:44:18.450177 WORK_FSP = 0x0
5030 14:44:18.450260 WL = 0x3
5031 14:44:18.453557 RL = 0x3
5032 14:44:18.453639 BL = 0x2
5033 14:44:18.456928 RPST = 0x0
5034 14:44:18.457055 RD_PRE = 0x0
5035 14:44:18.460545 WR_PRE = 0x1
5036 14:44:18.460652 WR_PST = 0x0
5037 14:44:18.463590 DBI_WR = 0x0
5038 14:44:18.463704 DBI_RD = 0x0
5039 14:44:18.466819 OTF = 0x1
5040 14:44:18.470765 ===================================
5041 14:44:18.476890 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 14:44:18.480360 nWR fixed to 30
5043 14:44:18.480469 [ModeRegInit_LP4] CH0 RK0
5044 14:44:18.483680 [ModeRegInit_LP4] CH0 RK1
5045 14:44:18.487044 [ModeRegInit_LP4] CH1 RK0
5046 14:44:18.489992 [ModeRegInit_LP4] CH1 RK1
5047 14:44:18.490105 match AC timing 9
5048 14:44:18.496700 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 14:44:18.499923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 14:44:18.503718 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 14:44:18.511273 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 14:44:18.513614 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 14:44:18.513721 ==
5054 14:44:18.516802 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 14:44:18.520226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 14:44:18.520333 ==
5057 14:44:18.526958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 14:44:18.533682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5059 14:44:18.537138 [CA 0] Center 38 (7~69) winsize 63
5060 14:44:18.540331 [CA 1] Center 38 (7~69) winsize 63
5061 14:44:18.544020 [CA 2] Center 35 (5~65) winsize 61
5062 14:44:18.547258 [CA 3] Center 35 (5~65) winsize 61
5063 14:44:18.550261 [CA 4] Center 34 (4~64) winsize 61
5064 14:44:18.554017 [CA 5] Center 34 (4~64) winsize 61
5065 14:44:18.554119
5066 14:44:18.557420 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5067 14:44:18.557519
5068 14:44:18.560833 [CATrainingPosCal] consider 1 rank data
5069 14:44:18.563958 u2DelayCellTimex100 = 270/100 ps
5070 14:44:18.566955 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5071 14:44:18.569980 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5072 14:44:18.573278 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5073 14:44:18.576825 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5074 14:44:18.580042 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5075 14:44:18.583935 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5076 14:44:18.584035
5077 14:44:18.587352 CA PerBit enable=1, Macro0, CA PI delay=34
5078 14:44:18.587450
5079 14:44:18.590009 [CBTSetCACLKResult] CA Dly = 34
5080 14:44:18.594393 CS Dly: 6 (0~37)
5081 14:44:18.594499 ==
5082 14:44:18.596901 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 14:44:18.600547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 14:44:18.600654 ==
5085 14:44:18.606487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 14:44:18.613676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5087 14:44:18.617614 [CA 0] Center 38 (7~69) winsize 63
5088 14:44:18.620312 [CA 1] Center 38 (7~69) winsize 63
5089 14:44:18.624097 [CA 2] Center 35 (5~66) winsize 62
5090 14:44:18.626995 [CA 3] Center 35 (4~66) winsize 63
5091 14:44:18.630233 [CA 4] Center 34 (3~65) winsize 63
5092 14:44:18.633383 [CA 5] Center 33 (3~64) winsize 62
5093 14:44:18.633486
5094 14:44:18.637210 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5095 14:44:18.637314
5096 14:44:18.639814 [CATrainingPosCal] consider 2 rank data
5097 14:44:18.643692 u2DelayCellTimex100 = 270/100 ps
5098 14:44:18.646816 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5099 14:44:18.650609 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5100 14:44:18.653276 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5101 14:44:18.657029 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5102 14:44:18.659863 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5103 14:44:18.663711 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5104 14:44:18.663813
5105 14:44:18.666951 CA PerBit enable=1, Macro0, CA PI delay=34
5106 14:44:18.667054
5107 14:44:18.670182 [CBTSetCACLKResult] CA Dly = 34
5108 14:44:18.673639 CS Dly: 7 (0~39)
5109 14:44:18.673715
5110 14:44:18.677129 ----->DramcWriteLeveling(PI) begin...
5111 14:44:18.677229 ==
5112 14:44:18.679877 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 14:44:18.683683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 14:44:18.683786 ==
5115 14:44:18.686836 Write leveling (Byte 0): 31 => 31
5116 14:44:18.689997 Write leveling (Byte 1): 26 => 26
5117 14:44:18.693556 DramcWriteLeveling(PI) end<-----
5118 14:44:18.693660
5119 14:44:18.693752 ==
5120 14:44:18.696700 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 14:44:18.700392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 14:44:18.700498 ==
5123 14:44:18.704386 [Gating] SW mode calibration
5124 14:44:18.710075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 14:44:18.716831 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 14:44:18.720460 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5127 14:44:18.723519 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5128 14:44:18.730208 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 14:44:18.733905 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 14:44:18.736888 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 14:44:18.744082 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 14:44:18.746707 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 14:44:18.750338 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 14:44:18.756936 0 15 0 | B1->B0 | 3333 2a2a | 0 0 | (1 0) (1 1)
5135 14:44:18.760038 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5136 14:44:18.763951 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 14:44:18.770434 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 14:44:18.773441 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 14:44:18.776636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 14:44:18.784415 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 14:44:18.787218 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5142 14:44:18.790395 1 0 0 | B1->B0 | 2f2f 3f3f | 0 0 | (1 1) (0 0)
5143 14:44:18.797639 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5144 14:44:18.800022 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 14:44:18.803953 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 14:44:18.811585 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 14:44:18.813489 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 14:44:18.817272 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 14:44:18.820058 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5150 14:44:18.826996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5151 14:44:18.830433 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5152 14:44:18.833351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 14:44:18.840052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 14:44:18.843724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 14:44:18.847322 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 14:44:18.853398 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 14:44:18.856885 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 14:44:18.860657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 14:44:18.867142 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 14:44:18.870626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 14:44:18.873889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 14:44:18.880408 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 14:44:18.883898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 14:44:18.887261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 14:44:18.890304 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5166 14:44:18.897361 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5167 14:44:18.900520 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 14:44:18.903521 Total UI for P1: 0, mck2ui 16
5169 14:44:18.906843 best dqsien dly found for B0: ( 1, 2, 30)
5170 14:44:18.910848 Total UI for P1: 0, mck2ui 16
5171 14:44:18.913669 best dqsien dly found for B1: ( 1, 3, 0)
5172 14:44:18.917080 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5173 14:44:18.920568 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5174 14:44:18.920669
5175 14:44:18.924368 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5176 14:44:18.926719 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5177 14:44:18.931207 [Gating] SW calibration Done
5178 14:44:18.931310 ==
5179 14:44:18.933841 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 14:44:18.937252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 14:44:18.940908 ==
5182 14:44:18.941018 RX Vref Scan: 0
5183 14:44:18.941092
5184 14:44:18.943473 RX Vref 0 -> 0, step: 1
5185 14:44:18.943569
5186 14:44:18.946978 RX Delay -80 -> 252, step: 8
5187 14:44:18.950469 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5188 14:44:18.953976 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5189 14:44:18.957115 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5190 14:44:18.960636 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5191 14:44:18.964151 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5192 14:44:18.970718 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5193 14:44:18.973896 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5194 14:44:18.976788 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5195 14:44:18.980246 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5196 14:44:18.983965 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5197 14:44:18.990403 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5198 14:44:18.993514 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5199 14:44:18.997214 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5200 14:44:19.000625 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5201 14:44:19.003461 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5202 14:44:19.006942 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5203 14:44:19.010401 ==
5204 14:44:19.010508 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 14:44:19.017010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 14:44:19.017116 ==
5207 14:44:19.017211 DQS Delay:
5208 14:44:19.020874 DQS0 = 0, DQS1 = 0
5209 14:44:19.020970 DQM Delay:
5210 14:44:19.023520 DQM0 = 99, DQM1 = 86
5211 14:44:19.023617 DQ Delay:
5212 14:44:19.028869 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5213 14:44:19.030378 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5214 14:44:19.034592 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5215 14:44:19.037472 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5216 14:44:19.037548
5217 14:44:19.037614
5218 14:44:19.037692 ==
5219 14:44:19.040391 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 14:44:19.043969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 14:44:19.044090 ==
5222 14:44:19.044183
5223 14:44:19.044272
5224 14:44:19.047192 TX Vref Scan disable
5225 14:44:19.050345 == TX Byte 0 ==
5226 14:44:19.053821 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5227 14:44:19.057423 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5228 14:44:19.060641 == TX Byte 1 ==
5229 14:44:19.064277 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5230 14:44:19.066959 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5231 14:44:19.067069 ==
5232 14:44:19.070258 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 14:44:19.074110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 14:44:19.074209 ==
5235 14:44:19.077403
5236 14:44:19.077476
5237 14:44:19.077541 TX Vref Scan disable
5238 14:44:19.080463 == TX Byte 0 ==
5239 14:44:19.083958 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5240 14:44:19.090606 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5241 14:44:19.090710 == TX Byte 1 ==
5242 14:44:19.094173 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5243 14:44:19.100620 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5244 14:44:19.100733
5245 14:44:19.100827 [DATLAT]
5246 14:44:19.100929 Freq=933, CH0 RK0
5247 14:44:19.101058
5248 14:44:19.103727 DATLAT Default: 0xd
5249 14:44:19.103824 0, 0xFFFF, sum = 0
5250 14:44:19.107789 1, 0xFFFF, sum = 0
5251 14:44:19.107892 2, 0xFFFF, sum = 0
5252 14:44:19.110990 3, 0xFFFF, sum = 0
5253 14:44:19.114032 4, 0xFFFF, sum = 0
5254 14:44:19.114137 5, 0xFFFF, sum = 0
5255 14:44:19.117190 6, 0xFFFF, sum = 0
5256 14:44:19.117267 7, 0xFFFF, sum = 0
5257 14:44:19.120359 8, 0xFFFF, sum = 0
5258 14:44:19.120464 9, 0xFFFF, sum = 0
5259 14:44:19.124086 10, 0x0, sum = 1
5260 14:44:19.124194 11, 0x0, sum = 2
5261 14:44:19.124292 12, 0x0, sum = 3
5262 14:44:19.128008 13, 0x0, sum = 4
5263 14:44:19.128114 best_step = 11
5264 14:44:19.128206
5265 14:44:19.130828 ==
5266 14:44:19.130929 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 14:44:19.136917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 14:44:19.137062 ==
5269 14:44:19.137165 RX Vref Scan: 1
5270 14:44:19.137258
5271 14:44:19.140691 RX Vref 0 -> 0, step: 1
5272 14:44:19.140789
5273 14:44:19.144307 RX Delay -61 -> 252, step: 4
5274 14:44:19.144406
5275 14:44:19.147467 Set Vref, RX VrefLevel [Byte0]: 53
5276 14:44:19.150772 [Byte1]: 51
5277 14:44:19.150873
5278 14:44:19.154054 Final RX Vref Byte 0 = 53 to rank0
5279 14:44:19.156959 Final RX Vref Byte 1 = 51 to rank0
5280 14:44:19.160511 Final RX Vref Byte 0 = 53 to rank1
5281 14:44:19.163599 Final RX Vref Byte 1 = 51 to rank1==
5282 14:44:19.167351 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 14:44:19.170463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 14:44:19.170566 ==
5285 14:44:19.174222 DQS Delay:
5286 14:44:19.174322 DQS0 = 0, DQS1 = 0
5287 14:44:19.177082 DQM Delay:
5288 14:44:19.177183 DQM0 = 97, DQM1 = 87
5289 14:44:19.177286 DQ Delay:
5290 14:44:19.180302 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5291 14:44:19.184258 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5292 14:44:19.187417 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5293 14:44:19.190778 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5294 14:44:19.190880
5295 14:44:19.190971
5296 14:44:19.200650 [DQSOSCAuto] RK0, (LSB)MR18= 0x1602, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5297 14:44:19.204276 CH0 RK0: MR19=505, MR18=1602
5298 14:44:19.207603 CH0_RK0: MR19=0x505, MR18=0x1602, DQSOSC=414, MR23=63, INC=63, DEC=42
5299 14:44:19.207712
5300 14:44:19.211096 ----->DramcWriteLeveling(PI) begin...
5301 14:44:19.214356 ==
5302 14:44:19.217609 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 14:44:19.220695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 14:44:19.220794 ==
5305 14:44:19.224179 Write leveling (Byte 0): 28 => 28
5306 14:44:19.227296 Write leveling (Byte 1): 27 => 27
5307 14:44:19.230778 DramcWriteLeveling(PI) end<-----
5308 14:44:19.230877
5309 14:44:19.230979 ==
5310 14:44:19.234109 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 14:44:19.237105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 14:44:19.237210 ==
5313 14:44:19.241144 [Gating] SW mode calibration
5314 14:44:19.247714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5315 14:44:19.253785 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5316 14:44:19.257181 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5317 14:44:19.260901 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5318 14:44:19.263894 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 14:44:19.271104 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 14:44:19.273537 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 14:44:19.277136 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 14:44:19.284310 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5323 14:44:19.287046 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5324 14:44:19.291135 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
5325 14:44:19.297698 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5326 14:44:19.300626 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 14:44:19.304006 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 14:44:19.310705 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 14:44:19.314195 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 14:44:19.317256 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 14:44:19.323888 0 15 28 | B1->B0 | 2929 3a3a | 1 0 | (0 0) (0 0)
5332 14:44:19.327922 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5333 14:44:19.330548 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 14:44:19.337472 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 14:44:19.341284 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 14:44:19.344521 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 14:44:19.350713 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 14:44:19.354105 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 14:44:19.357531 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 14:44:19.360689 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 14:44:19.367212 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5342 14:44:19.370979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 14:44:19.373933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 14:44:19.381125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 14:44:19.383923 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 14:44:19.387156 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 14:44:19.395259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 14:44:19.397352 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 14:44:19.401428 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 14:44:19.407198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 14:44:19.410892 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 14:44:19.414403 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 14:44:19.420895 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 14:44:19.424343 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5355 14:44:19.427605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 14:44:19.433906 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 14:44:19.434010 Total UI for P1: 0, mck2ui 16
5358 14:44:19.441963 best dqsien dly found for B0: ( 1, 2, 26)
5359 14:44:19.444519 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 14:44:19.447307 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 14:44:19.450484 Total UI for P1: 0, mck2ui 16
5362 14:44:19.454234 best dqsien dly found for B1: ( 1, 3, 2)
5363 14:44:19.457580 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5364 14:44:19.461060 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5365 14:44:19.461144
5366 14:44:19.463888 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5367 14:44:19.467624 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5368 14:44:19.470370 [Gating] SW calibration Done
5369 14:44:19.470453 ==
5370 14:44:19.473800 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 14:44:19.480924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 14:44:19.481046 ==
5373 14:44:19.481112 RX Vref Scan: 0
5374 14:44:19.481175
5375 14:44:19.484087 RX Vref 0 -> 0, step: 1
5376 14:44:19.484170
5377 14:44:19.487726 RX Delay -80 -> 252, step: 8
5378 14:44:19.490915 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5379 14:44:19.494012 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5380 14:44:19.497161 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5381 14:44:19.501146 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5382 14:44:19.504458 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5383 14:44:19.510530 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5384 14:44:19.513679 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5385 14:44:19.517121 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5386 14:44:19.520920 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5387 14:44:19.524613 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5388 14:44:19.527271 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5389 14:44:19.533800 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5390 14:44:19.537195 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5391 14:44:19.540799 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5392 14:44:19.543696 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5393 14:44:19.546962 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5394 14:44:19.547065 ==
5395 14:44:19.550800 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 14:44:19.557367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 14:44:19.557475 ==
5398 14:44:19.557569 DQS Delay:
5399 14:44:19.560253 DQS0 = 0, DQS1 = 0
5400 14:44:19.560352 DQM Delay:
5401 14:44:19.560444 DQM0 = 97, DQM1 = 87
5402 14:44:19.563521 DQ Delay:
5403 14:44:19.567030 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5404 14:44:19.570241 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5405 14:44:19.573893 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5406 14:44:19.576855 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5407 14:44:19.576956
5408 14:44:19.577091
5409 14:44:19.577180 ==
5410 14:44:19.580656 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 14:44:19.583813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 14:44:19.583912 ==
5413 14:44:19.584004
5414 14:44:19.584088
5415 14:44:19.587288 TX Vref Scan disable
5416 14:44:19.587388 == TX Byte 0 ==
5417 14:44:19.593672 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5418 14:44:19.597143 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5419 14:44:19.597235 == TX Byte 1 ==
5420 14:44:19.603744 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5421 14:44:19.607234 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5422 14:44:19.607341 ==
5423 14:44:19.610288 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 14:44:19.613886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 14:44:19.613990 ==
5426 14:44:19.614091
5427 14:44:19.614187
5428 14:44:19.617407 TX Vref Scan disable
5429 14:44:19.620283 == TX Byte 0 ==
5430 14:44:19.624345 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5431 14:44:19.627861 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5432 14:44:19.630902 == TX Byte 1 ==
5433 14:44:19.634330 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5434 14:44:19.637541 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5435 14:44:19.637642
5436 14:44:19.640747 [DATLAT]
5437 14:44:19.640855 Freq=933, CH0 RK1
5438 14:44:19.640953
5439 14:44:19.644147 DATLAT Default: 0xb
5440 14:44:19.644221 0, 0xFFFF, sum = 0
5441 14:44:19.647573 1, 0xFFFF, sum = 0
5442 14:44:19.647678 2, 0xFFFF, sum = 0
5443 14:44:19.651862 3, 0xFFFF, sum = 0
5444 14:44:19.651968 4, 0xFFFF, sum = 0
5445 14:44:19.654716 5, 0xFFFF, sum = 0
5446 14:44:19.654808 6, 0xFFFF, sum = 0
5447 14:44:19.657618 7, 0xFFFF, sum = 0
5448 14:44:19.657703 8, 0xFFFF, sum = 0
5449 14:44:19.660709 9, 0xFFFF, sum = 0
5450 14:44:19.660794 10, 0x0, sum = 1
5451 14:44:19.664298 11, 0x0, sum = 2
5452 14:44:19.664383 12, 0x0, sum = 3
5453 14:44:19.667432 13, 0x0, sum = 4
5454 14:44:19.667518 best_step = 11
5455 14:44:19.667584
5456 14:44:19.667646 ==
5457 14:44:19.671113 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 14:44:19.674362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 14:44:19.677530 ==
5460 14:44:19.677614 RX Vref Scan: 0
5461 14:44:19.677680
5462 14:44:19.681395 RX Vref 0 -> 0, step: 1
5463 14:44:19.681478
5464 14:44:19.684495 RX Delay -61 -> 252, step: 4
5465 14:44:19.687505 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5466 14:44:19.690996 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 14:44:19.694543 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 14:44:19.701241 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 14:44:19.704549 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5470 14:44:19.707722 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5471 14:44:19.711053 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 14:44:19.713953 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5473 14:44:19.718450 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5474 14:44:19.723918 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5475 14:44:19.727180 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 14:44:19.731219 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5477 14:44:19.734298 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5478 14:44:19.737841 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5479 14:44:19.744621 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5480 14:44:19.747122 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5481 14:44:19.747232 ==
5482 14:44:19.752075 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 14:44:19.754290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 14:44:19.754396 ==
5485 14:44:19.754492 DQS Delay:
5486 14:44:19.758035 DQS0 = 0, DQS1 = 0
5487 14:44:19.758125 DQM Delay:
5488 14:44:19.760876 DQM0 = 95, DQM1 = 88
5489 14:44:19.760959 DQ Delay:
5490 14:44:19.763892 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5491 14:44:19.767481 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5492 14:44:19.771120 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5493 14:44:19.774099 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5494 14:44:19.774182
5495 14:44:19.774248
5496 14:44:19.784656 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5497 14:44:19.784740 CH0 RK1: MR19=505, MR18=1B08
5498 14:44:19.790733 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5499 14:44:19.794377 [RxdqsGatingPostProcess] freq 933
5500 14:44:19.800370 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 14:44:19.804171 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 14:44:19.807745 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 14:44:19.810931 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 14:44:19.814944 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 14:44:19.815049 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 14:44:19.817378 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 14:44:19.820314 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 14:44:19.823919 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 14:44:19.827541 Pre-setting of DQS Precalculation
5510 14:44:19.834282 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 14:44:19.834363 ==
5512 14:44:19.837497 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 14:44:19.840921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 14:44:19.841064 ==
5515 14:44:19.847283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 14:44:19.854103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5517 14:44:19.857612 [CA 0] Center 36 (6~67) winsize 62
5518 14:44:19.860823 [CA 1] Center 36 (6~67) winsize 62
5519 14:44:19.864537 [CA 2] Center 33 (3~64) winsize 62
5520 14:44:19.867138 [CA 3] Center 33 (3~64) winsize 62
5521 14:44:19.867221 [CA 4] Center 33 (3~64) winsize 62
5522 14:44:19.871237 [CA 5] Center 32 (2~63) winsize 62
5523 14:44:19.871320
5524 14:44:19.877280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5525 14:44:19.877363
5526 14:44:19.881374 [CATrainingPosCal] consider 1 rank data
5527 14:44:19.884053 u2DelayCellTimex100 = 270/100 ps
5528 14:44:19.887101 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5529 14:44:19.891205 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5530 14:44:19.894147 CA2 delay=33 (3~64),Diff = 1 PI (6 cell)
5531 14:44:19.897196 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5532 14:44:19.900555 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5533 14:44:19.903807 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5534 14:44:19.903891
5535 14:44:19.907988 CA PerBit enable=1, Macro0, CA PI delay=32
5536 14:44:19.908072
5537 14:44:19.910640 [CBTSetCACLKResult] CA Dly = 32
5538 14:44:19.914071 CS Dly: 4 (0~35)
5539 14:44:19.914153 ==
5540 14:44:19.917168 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 14:44:19.920609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 14:44:19.920719 ==
5543 14:44:19.927481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 14:44:19.933674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 14:44:19.936943 [CA 0] Center 36 (6~67) winsize 62
5546 14:44:19.941797 [CA 1] Center 36 (6~67) winsize 62
5547 14:44:19.943807 [CA 2] Center 33 (3~64) winsize 62
5548 14:44:19.947070 [CA 3] Center 33 (3~64) winsize 62
5549 14:44:19.950995 [CA 4] Center 33 (3~64) winsize 62
5550 14:44:19.951079 [CA 5] Center 32 (2~63) winsize 62
5551 14:44:19.953834
5552 14:44:19.957120 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 14:44:19.957204
5554 14:44:19.960463 [CATrainingPosCal] consider 2 rank data
5555 14:44:19.964267 u2DelayCellTimex100 = 270/100 ps
5556 14:44:19.967432 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5557 14:44:19.970229 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5558 14:44:19.974301 CA2 delay=33 (3~64),Diff = 1 PI (6 cell)
5559 14:44:19.976968 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5560 14:44:19.980641 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5561 14:44:19.984191 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5562 14:44:19.984274
5563 14:44:19.987193 CA PerBit enable=1, Macro0, CA PI delay=32
5564 14:44:19.987277
5565 14:44:19.990645 [CBTSetCACLKResult] CA Dly = 32
5566 14:44:19.993584 CS Dly: 5 (0~37)
5567 14:44:19.993667
5568 14:44:19.996936 ----->DramcWriteLeveling(PI) begin...
5569 14:44:19.997057 ==
5570 14:44:20.000415 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 14:44:20.003698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 14:44:20.003782 ==
5573 14:44:20.007380 Write leveling (Byte 0): 28 => 28
5574 14:44:20.010641 Write leveling (Byte 1): 29 => 29
5575 14:44:20.014978 DramcWriteLeveling(PI) end<-----
5576 14:44:20.015061
5577 14:44:20.015127 ==
5578 14:44:20.017383 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 14:44:20.020422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 14:44:20.020506 ==
5581 14:44:20.024677 [Gating] SW mode calibration
5582 14:44:20.030816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 14:44:20.037237 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 14:44:20.041007 0 14 0 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
5585 14:44:20.043784 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 14:44:20.051281 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 14:44:20.054404 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 14:44:20.057354 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 14:44:20.063887 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 14:44:20.067296 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 14:44:20.070755 0 14 28 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
5592 14:44:20.077690 0 15 0 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
5593 14:44:20.080535 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 14:44:20.083561 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 14:44:20.090814 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 14:44:20.094280 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 14:44:20.097182 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 14:44:20.104280 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 14:44:20.107141 0 15 28 | B1->B0 | 2424 2828 | 1 0 | (0 0) (0 0)
5600 14:44:20.110326 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5601 14:44:20.117341 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 14:44:20.120545 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 14:44:20.123854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 14:44:20.127294 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 14:44:20.134045 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 14:44:20.136980 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5607 14:44:20.140334 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 14:44:20.147416 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 14:44:20.150540 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 14:44:20.153810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 14:44:20.160843 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 14:44:20.164129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 14:44:20.167296 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 14:44:20.173723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 14:44:20.176905 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 14:44:20.180300 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 14:44:20.187216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 14:44:20.190482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 14:44:20.193996 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 14:44:20.200542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 14:44:20.204485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 14:44:20.207959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 14:44:20.210770 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 14:44:20.217911 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 14:44:20.220335 Total UI for P1: 0, mck2ui 16
5626 14:44:20.224294 best dqsien dly found for B0: ( 1, 2, 30)
5627 14:44:20.228134 Total UI for P1: 0, mck2ui 16
5628 14:44:20.230955 best dqsien dly found for B1: ( 1, 2, 30)
5629 14:44:20.233972 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5630 14:44:20.237447 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5631 14:44:20.237544
5632 14:44:20.240988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5633 14:44:20.243860 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5634 14:44:20.247273 [Gating] SW calibration Done
5635 14:44:20.247356 ==
5636 14:44:20.251098 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 14:44:20.254016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 14:44:20.254100 ==
5639 14:44:20.257378 RX Vref Scan: 0
5640 14:44:20.257461
5641 14:44:20.257528 RX Vref 0 -> 0, step: 1
5642 14:44:20.257621
5643 14:44:20.260672 RX Delay -80 -> 252, step: 8
5644 14:44:20.264259 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5645 14:44:20.270260 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5646 14:44:20.274079 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5647 14:44:20.276900 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5648 14:44:20.280181 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5649 14:44:20.284122 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5650 14:44:20.287180 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5651 14:44:20.293917 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5652 14:44:20.297433 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5653 14:44:20.300652 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5654 14:44:20.304337 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5655 14:44:20.307383 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5656 14:44:20.314044 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5657 14:44:20.317151 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5658 14:44:20.320872 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5659 14:44:20.324008 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5660 14:44:20.324092 ==
5661 14:44:20.327509 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 14:44:20.330662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 14:44:20.330746 ==
5664 14:44:20.334311 DQS Delay:
5665 14:44:20.334395 DQS0 = 0, DQS1 = 0
5666 14:44:20.337616 DQM Delay:
5667 14:44:20.337699 DQM0 = 96, DQM1 = 89
5668 14:44:20.337765 DQ Delay:
5669 14:44:20.340571 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5670 14:44:20.343894 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5671 14:44:20.347480 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5672 14:44:20.350573 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5673 14:44:20.350656
5674 14:44:20.350723
5675 14:44:20.353905 ==
5676 14:44:20.353988 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 14:44:20.360525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 14:44:20.360608 ==
5679 14:44:20.360675
5680 14:44:20.360736
5681 14:44:20.363982 TX Vref Scan disable
5682 14:44:20.364066 == TX Byte 0 ==
5683 14:44:20.367119 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5684 14:44:20.373926 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5685 14:44:20.374009 == TX Byte 1 ==
5686 14:44:20.377664 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5687 14:44:20.384233 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5688 14:44:20.384317 ==
5689 14:44:20.387066 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 14:44:20.390487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 14:44:20.390571 ==
5692 14:44:20.390638
5693 14:44:20.390700
5694 14:44:20.393995 TX Vref Scan disable
5695 14:44:20.396936 == TX Byte 0 ==
5696 14:44:20.400791 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5697 14:44:20.403778 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5698 14:44:20.406943 == TX Byte 1 ==
5699 14:44:20.410333 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5700 14:44:20.413927 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5701 14:44:20.414011
5702 14:44:20.414078 [DATLAT]
5703 14:44:20.417209 Freq=933, CH1 RK0
5704 14:44:20.417293
5705 14:44:20.417358 DATLAT Default: 0xd
5706 14:44:20.420899 0, 0xFFFF, sum = 0
5707 14:44:20.423772 1, 0xFFFF, sum = 0
5708 14:44:20.423856 2, 0xFFFF, sum = 0
5709 14:44:20.427773 3, 0xFFFF, sum = 0
5710 14:44:20.427857 4, 0xFFFF, sum = 0
5711 14:44:20.430765 5, 0xFFFF, sum = 0
5712 14:44:20.430850 6, 0xFFFF, sum = 0
5713 14:44:20.433913 7, 0xFFFF, sum = 0
5714 14:44:20.433998 8, 0xFFFF, sum = 0
5715 14:44:20.437250 9, 0xFFFF, sum = 0
5716 14:44:20.437335 10, 0x0, sum = 1
5717 14:44:20.440775 11, 0x0, sum = 2
5718 14:44:20.440860 12, 0x0, sum = 3
5719 14:44:20.444497 13, 0x0, sum = 4
5720 14:44:20.444582 best_step = 11
5721 14:44:20.444648
5722 14:44:20.444710 ==
5723 14:44:20.447577 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 14:44:20.450429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 14:44:20.450512 ==
5726 14:44:20.454291 RX Vref Scan: 1
5727 14:44:20.454374
5728 14:44:20.454440 RX Vref 0 -> 0, step: 1
5729 14:44:20.457444
5730 14:44:20.457526 RX Delay -61 -> 252, step: 4
5731 14:44:20.457593
5732 14:44:20.460805 Set Vref, RX VrefLevel [Byte0]: 57
5733 14:44:20.464298 [Byte1]: 53
5734 14:44:20.468993
5735 14:44:20.469090 Final RX Vref Byte 0 = 57 to rank0
5736 14:44:20.471618 Final RX Vref Byte 1 = 53 to rank0
5737 14:44:20.475178 Final RX Vref Byte 0 = 57 to rank1
5738 14:44:20.478600 Final RX Vref Byte 1 = 53 to rank1==
5739 14:44:20.481659 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 14:44:20.484935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 14:44:20.488334 ==
5742 14:44:20.488418 DQS Delay:
5743 14:44:20.488483 DQS0 = 0, DQS1 = 0
5744 14:44:20.491782 DQM Delay:
5745 14:44:20.491896 DQM0 = 97, DQM1 = 91
5746 14:44:20.495263 DQ Delay:
5747 14:44:20.498856 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5748 14:44:20.502228 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5749 14:44:20.502311 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5750 14:44:20.509248 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =94
5751 14:44:20.509331
5752 14:44:20.509396
5753 14:44:20.515439 [DQSOSCAuto] RK0, (LSB)MR18= 0x16f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5754 14:44:20.518403 CH1 RK0: MR19=504, MR18=16F3
5755 14:44:20.525088 CH1_RK0: MR19=0x504, MR18=0x16F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5756 14:44:20.525175
5757 14:44:20.528897 ----->DramcWriteLeveling(PI) begin...
5758 14:44:20.528988 ==
5759 14:44:20.531985 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 14:44:20.534965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 14:44:20.535048 ==
5762 14:44:20.538688 Write leveling (Byte 0): 28 => 28
5763 14:44:20.541996 Write leveling (Byte 1): 28 => 28
5764 14:44:20.545674 DramcWriteLeveling(PI) end<-----
5765 14:44:20.545757
5766 14:44:20.545823 ==
5767 14:44:20.548481 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 14:44:20.552739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 14:44:20.552824 ==
5770 14:44:20.555171 [Gating] SW mode calibration
5771 14:44:20.561862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 14:44:20.568252 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 14:44:20.571423 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 14:44:20.575031 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 14:44:20.582348 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 14:44:20.585068 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 14:44:20.588624 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 14:44:20.595228 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5779 14:44:20.598102 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (0 0)
5780 14:44:20.601520 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5781 14:44:20.608136 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 14:44:20.611669 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 14:44:20.615356 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 14:44:20.622243 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 14:44:20.624666 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 14:44:20.628556 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 14:44:20.634698 0 15 24 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (0 0)
5788 14:44:20.637923 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5789 14:44:20.641451 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 14:44:20.648055 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 14:44:20.651597 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 14:44:20.654655 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 14:44:20.661645 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 14:44:20.664754 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 14:44:20.667854 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5796 14:44:20.674813 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 14:44:20.678040 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 14:44:20.681343 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 14:44:20.685245 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 14:44:20.691505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 14:44:20.694670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 14:44:20.698279 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 14:44:20.704951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 14:44:20.708213 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 14:44:20.711342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 14:44:20.718479 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 14:44:20.721694 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 14:44:20.726473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 14:44:20.731556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 14:44:20.734737 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5811 14:44:20.738201 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5812 14:44:20.741871 Total UI for P1: 0, mck2ui 16
5813 14:44:20.744871 best dqsien dly found for B0: ( 1, 2, 20)
5814 14:44:20.751398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 14:44:20.751483 Total UI for P1: 0, mck2ui 16
5816 14:44:20.754775 best dqsien dly found for B1: ( 1, 2, 24)
5817 14:44:20.761297 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5818 14:44:20.764869 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5819 14:44:20.764969
5820 14:44:20.767869 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5821 14:44:20.771707 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 14:44:20.774649 [Gating] SW calibration Done
5823 14:44:20.774732 ==
5824 14:44:20.778912 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 14:44:20.781673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 14:44:20.781757 ==
5827 14:44:20.785260 RX Vref Scan: 0
5828 14:44:20.785343
5829 14:44:20.785409 RX Vref 0 -> 0, step: 1
5830 14:44:20.785470
5831 14:44:20.788254 RX Delay -80 -> 252, step: 8
5832 14:44:20.791750 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5833 14:44:20.794555 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5834 14:44:20.801586 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5835 14:44:20.804736 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5836 14:44:20.807825 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5837 14:44:20.811825 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5838 14:44:20.814764 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5839 14:44:20.818448 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5840 14:44:20.825321 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5841 14:44:20.828381 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5842 14:44:20.831814 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5843 14:44:20.835340 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5844 14:44:20.838254 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5845 14:44:20.841511 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5846 14:44:20.848018 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5847 14:44:20.851318 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5848 14:44:20.851402 ==
5849 14:44:20.855513 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 14:44:20.858565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 14:44:20.858649 ==
5852 14:44:20.858716 DQS Delay:
5853 14:44:20.861807 DQS0 = 0, DQS1 = 0
5854 14:44:20.861891 DQM Delay:
5855 14:44:20.865035 DQM0 = 95, DQM1 = 88
5856 14:44:20.865125 DQ Delay:
5857 14:44:20.868102 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5858 14:44:20.872135 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5859 14:44:20.874981 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5860 14:44:20.878790 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5861 14:44:20.878874
5862 14:44:20.878940
5863 14:44:20.879001 ==
5864 14:44:20.882282 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 14:44:20.885334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 14:44:20.888579 ==
5867 14:44:20.888663
5868 14:44:20.888729
5869 14:44:20.888790 TX Vref Scan disable
5870 14:44:20.892294 == TX Byte 0 ==
5871 14:44:20.895169 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 14:44:20.898023 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 14:44:20.901673 == TX Byte 1 ==
5874 14:44:20.905253 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5875 14:44:20.908721 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5876 14:44:20.911596 ==
5877 14:44:20.911679 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 14:44:20.918818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 14:44:20.918902 ==
5880 14:44:20.918969
5881 14:44:20.919030
5882 14:44:20.919090 TX Vref Scan disable
5883 14:44:20.922602 == TX Byte 0 ==
5884 14:44:20.925860 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 14:44:20.932544 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 14:44:20.932664 == TX Byte 1 ==
5887 14:44:20.936578 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5888 14:44:20.942880 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5889 14:44:20.942963
5890 14:44:20.943029 [DATLAT]
5891 14:44:20.943091 Freq=933, CH1 RK1
5892 14:44:20.943152
5893 14:44:20.945769 DATLAT Default: 0xb
5894 14:44:20.945852 0, 0xFFFF, sum = 0
5895 14:44:20.949242 1, 0xFFFF, sum = 0
5896 14:44:20.949327 2, 0xFFFF, sum = 0
5897 14:44:20.952419 3, 0xFFFF, sum = 0
5898 14:44:20.952504 4, 0xFFFF, sum = 0
5899 14:44:20.955662 5, 0xFFFF, sum = 0
5900 14:44:20.958993 6, 0xFFFF, sum = 0
5901 14:44:20.959078 7, 0xFFFF, sum = 0
5902 14:44:20.962452 8, 0xFFFF, sum = 0
5903 14:44:20.962537 9, 0xFFFF, sum = 0
5904 14:44:20.966315 10, 0x0, sum = 1
5905 14:44:20.966399 11, 0x0, sum = 2
5906 14:44:20.966466 12, 0x0, sum = 3
5907 14:44:20.969561 13, 0x0, sum = 4
5908 14:44:20.969646 best_step = 11
5909 14:44:20.969712
5910 14:44:20.973239 ==
5911 14:44:20.973323 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 14:44:20.979118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 14:44:20.979202 ==
5914 14:44:20.979269 RX Vref Scan: 0
5915 14:44:20.979331
5916 14:44:20.982461 RX Vref 0 -> 0, step: 1
5917 14:44:20.982544
5918 14:44:20.985642 RX Delay -61 -> 252, step: 4
5919 14:44:20.989166 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5920 14:44:20.995748 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5921 14:44:20.999138 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5922 14:44:21.002242 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5923 14:44:21.005724 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5924 14:44:21.009743 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5925 14:44:21.012961 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5926 14:44:21.019018 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5927 14:44:21.022395 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5928 14:44:21.026455 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5929 14:44:21.028929 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5930 14:44:21.032472 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5931 14:44:21.038687 iDelay=199, Bit 12, Center 100 (15 ~ 186) 172
5932 14:44:21.041989 iDelay=199, Bit 13, Center 96 (3 ~ 190) 188
5933 14:44:21.046012 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5934 14:44:21.048958 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5935 14:44:21.049050 ==
5936 14:44:21.053210 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 14:44:21.055698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 14:44:21.055775 ==
5939 14:44:21.059061 DQS Delay:
5940 14:44:21.059133 DQS0 = 0, DQS1 = 0
5941 14:44:21.062265 DQM Delay:
5942 14:44:21.062337 DQM0 = 95, DQM1 = 90
5943 14:44:21.062399 DQ Delay:
5944 14:44:21.066025 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5945 14:44:21.068753 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5946 14:44:21.072200 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =82
5947 14:44:21.075285 DQ12 =100, DQ13 =96, DQ14 =98, DQ15 =98
5948 14:44:21.075357
5949 14:44:21.078759
5950 14:44:21.085315 [DQSOSCAuto] RK1, (LSB)MR18= 0xe18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5951 14:44:21.088730 CH1 RK1: MR19=505, MR18=E18
5952 14:44:21.092624 CH1_RK1: MR19=0x505, MR18=0xE18, DQSOSC=414, MR23=63, INC=63, DEC=42
5953 14:44:21.095393 [RxdqsGatingPostProcess] freq 933
5954 14:44:21.102477 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 14:44:21.105686 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 14:44:21.108634 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 14:44:21.112177 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 14:44:21.115538 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 14:44:21.119049 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 14:44:21.122676 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 14:44:21.125578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 14:44:21.129319 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 14:44:21.129403 Pre-setting of DQS Precalculation
5964 14:44:21.135987 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 14:44:21.142356 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 14:44:21.148875 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 14:44:21.148959
5968 14:44:21.149073
5969 14:44:21.152030 [Calibration Summary] 1866 Mbps
5970 14:44:21.155511 CH 0, Rank 0
5971 14:44:21.155594 SW Impedance : PASS
5972 14:44:21.159015 DUTY Scan : NO K
5973 14:44:21.162507 ZQ Calibration : PASS
5974 14:44:21.162627 Jitter Meter : NO K
5975 14:44:21.166426 CBT Training : PASS
5976 14:44:21.166509 Write leveling : PASS
5977 14:44:21.168655 RX DQS gating : PASS
5978 14:44:21.172735 RX DQ/DQS(RDDQC) : PASS
5979 14:44:21.172818 TX DQ/DQS : PASS
5980 14:44:21.175377 RX DATLAT : PASS
5981 14:44:21.179819 RX DQ/DQS(Engine): PASS
5982 14:44:21.179902 TX OE : NO K
5983 14:44:21.182321 All Pass.
5984 14:44:21.182404
5985 14:44:21.182471 CH 0, Rank 1
5986 14:44:21.185841 SW Impedance : PASS
5987 14:44:21.185924 DUTY Scan : NO K
5988 14:44:21.188607 ZQ Calibration : PASS
5989 14:44:21.192067 Jitter Meter : NO K
5990 14:44:21.192150 CBT Training : PASS
5991 14:44:21.196095 Write leveling : PASS
5992 14:44:21.199297 RX DQS gating : PASS
5993 14:44:21.199381 RX DQ/DQS(RDDQC) : PASS
5994 14:44:21.201978 TX DQ/DQS : PASS
5995 14:44:21.205802 RX DATLAT : PASS
5996 14:44:21.205885 RX DQ/DQS(Engine): PASS
5997 14:44:21.208933 TX OE : NO K
5998 14:44:21.209067 All Pass.
5999 14:44:21.209134
6000 14:44:21.212399 CH 1, Rank 0
6001 14:44:21.212481 SW Impedance : PASS
6002 14:44:21.215680 DUTY Scan : NO K
6003 14:44:21.215764 ZQ Calibration : PASS
6004 14:44:21.219329 Jitter Meter : NO K
6005 14:44:21.222043 CBT Training : PASS
6006 14:44:21.222126 Write leveling : PASS
6007 14:44:21.225474 RX DQS gating : PASS
6008 14:44:21.228775 RX DQ/DQS(RDDQC) : PASS
6009 14:44:21.228858 TX DQ/DQS : PASS
6010 14:44:21.232658 RX DATLAT : PASS
6011 14:44:21.235388 RX DQ/DQS(Engine): PASS
6012 14:44:21.235471 TX OE : NO K
6013 14:44:21.239369 All Pass.
6014 14:44:21.239452
6015 14:44:21.239518 CH 1, Rank 1
6016 14:44:21.242041 SW Impedance : PASS
6017 14:44:21.242124 DUTY Scan : NO K
6018 14:44:21.245696 ZQ Calibration : PASS
6019 14:44:21.249813 Jitter Meter : NO K
6020 14:44:21.249896 CBT Training : PASS
6021 14:44:21.252131 Write leveling : PASS
6022 14:44:21.255668 RX DQS gating : PASS
6023 14:44:21.255750 RX DQ/DQS(RDDQC) : PASS
6024 14:44:21.258743 TX DQ/DQS : PASS
6025 14:44:21.258827 RX DATLAT : PASS
6026 14:44:21.262220 RX DQ/DQS(Engine): PASS
6027 14:44:21.265850 TX OE : NO K
6028 14:44:21.265934 All Pass.
6029 14:44:21.266000
6030 14:44:21.269342 DramC Write-DBI off
6031 14:44:21.269425 PER_BANK_REFRESH: Hybrid Mode
6032 14:44:21.272682 TX_TRACKING: ON
6033 14:44:21.278913 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 14:44:21.286246 [FAST_K] Save calibration result to emmc
6035 14:44:21.289277 dramc_set_vcore_voltage set vcore to 650000
6036 14:44:21.289360 Read voltage for 400, 6
6037 14:44:21.292504 Vio18 = 0
6038 14:44:21.292588 Vcore = 650000
6039 14:44:21.292654 Vdram = 0
6040 14:44:21.295960 Vddq = 0
6041 14:44:21.296043 Vmddr = 0
6042 14:44:21.299226 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 14:44:21.306025 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 14:44:21.309104 MEM_TYPE=3, freq_sel=20
6045 14:44:21.312346 sv_algorithm_assistance_LP4_800
6046 14:44:21.316153 ============ PULL DRAM RESETB DOWN ============
6047 14:44:21.319038 ========== PULL DRAM RESETB DOWN end =========
6048 14:44:21.322180 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 14:44:21.325864 ===================================
6050 14:44:21.329221 LPDDR4 DRAM CONFIGURATION
6051 14:44:21.332795 ===================================
6052 14:44:21.335940 EX_ROW_EN[0] = 0x0
6053 14:44:21.336023 EX_ROW_EN[1] = 0x0
6054 14:44:21.339313 LP4Y_EN = 0x0
6055 14:44:21.339396 WORK_FSP = 0x0
6056 14:44:21.342522 WL = 0x2
6057 14:44:21.342605 RL = 0x2
6058 14:44:21.345707 BL = 0x2
6059 14:44:21.345791 RPST = 0x0
6060 14:44:21.349714 RD_PRE = 0x0
6061 14:44:21.349797 WR_PRE = 0x1
6062 14:44:21.353028 WR_PST = 0x0
6063 14:44:21.353112 DBI_WR = 0x0
6064 14:44:21.356350 DBI_RD = 0x0
6065 14:44:21.356433 OTF = 0x1
6066 14:44:21.359301 ===================================
6067 14:44:21.362763 ===================================
6068 14:44:21.366004 ANA top config
6069 14:44:21.369367 ===================================
6070 14:44:21.372555 DLL_ASYNC_EN = 0
6071 14:44:21.372641 ALL_SLAVE_EN = 1
6072 14:44:21.375654 NEW_RANK_MODE = 1
6073 14:44:21.379194 DLL_IDLE_MODE = 1
6074 14:44:21.382449 LP45_APHY_COMB_EN = 1
6075 14:44:21.382532 TX_ODT_DIS = 1
6076 14:44:21.386415 NEW_8X_MODE = 1
6077 14:44:21.389284 ===================================
6078 14:44:21.392404 ===================================
6079 14:44:21.395600 data_rate = 800
6080 14:44:21.399833 CKR = 1
6081 14:44:21.402772 DQ_P2S_RATIO = 4
6082 14:44:21.406277 ===================================
6083 14:44:21.409400 CA_P2S_RATIO = 4
6084 14:44:21.409484 DQ_CA_OPEN = 0
6085 14:44:21.412302 DQ_SEMI_OPEN = 1
6086 14:44:21.415603 CA_SEMI_OPEN = 1
6087 14:44:21.419265 CA_FULL_RATE = 0
6088 14:44:21.422147 DQ_CKDIV4_EN = 0
6089 14:44:21.425700 CA_CKDIV4_EN = 1
6090 14:44:21.425783 CA_PREDIV_EN = 0
6091 14:44:21.429576 PH8_DLY = 0
6092 14:44:21.432068 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 14:44:21.435588 DQ_AAMCK_DIV = 0
6094 14:44:21.438649 CA_AAMCK_DIV = 0
6095 14:44:21.442145 CA_ADMCK_DIV = 4
6096 14:44:21.442228 DQ_TRACK_CA_EN = 0
6097 14:44:21.445470 CA_PICK = 800
6098 14:44:21.448916 CA_MCKIO = 400
6099 14:44:21.452409 MCKIO_SEMI = 400
6100 14:44:21.455517 PLL_FREQ = 3016
6101 14:44:21.459016 DQ_UI_PI_RATIO = 32
6102 14:44:21.461990 CA_UI_PI_RATIO = 32
6103 14:44:21.465339 ===================================
6104 14:44:21.468787 ===================================
6105 14:44:21.468870 memory_type:LPDDR4
6106 14:44:21.472094 GP_NUM : 10
6107 14:44:21.475720 SRAM_EN : 1
6108 14:44:21.475803 MD32_EN : 0
6109 14:44:21.478993 ===================================
6110 14:44:21.482462 [ANA_INIT] >>>>>>>>>>>>>>
6111 14:44:21.485996 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 14:44:21.488824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 14:44:21.492145 ===================================
6114 14:44:21.495986 data_rate = 800,PCW = 0X7400
6115 14:44:21.499123 ===================================
6116 14:44:21.501897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 14:44:21.505513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 14:44:21.519662 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 14:44:21.521891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 14:44:21.525328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 14:44:21.529085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 14:44:21.532165 [ANA_INIT] flow start
6123 14:44:21.532251 [ANA_INIT] PLL >>>>>>>>
6124 14:44:21.535835 [ANA_INIT] PLL <<<<<<<<
6125 14:44:21.539000 [ANA_INIT] MIDPI >>>>>>>>
6126 14:44:21.542555 [ANA_INIT] MIDPI <<<<<<<<
6127 14:44:21.542665 [ANA_INIT] DLL >>>>>>>>
6128 14:44:21.545444 [ANA_INIT] flow end
6129 14:44:21.549224 ============ LP4 DIFF to SE enter ============
6130 14:44:21.551998 ============ LP4 DIFF to SE exit ============
6131 14:44:21.555455 [ANA_INIT] <<<<<<<<<<<<<
6132 14:44:21.559292 [Flow] Enable top DCM control >>>>>
6133 14:44:21.562578 [Flow] Enable top DCM control <<<<<
6134 14:44:21.566161 Enable DLL master slave shuffle
6135 14:44:21.569074 ==============================================================
6136 14:44:21.573243 Gating Mode config
6137 14:44:21.579459 ==============================================================
6138 14:44:21.579543 Config description:
6139 14:44:21.589364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 14:44:21.595727 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 14:44:21.599028 SELPH_MODE 0: By rank 1: By Phase
6142 14:44:21.605923 ==============================================================
6143 14:44:21.609151 GAT_TRACK_EN = 0
6144 14:44:21.613191 RX_GATING_MODE = 2
6145 14:44:21.616047 RX_GATING_TRACK_MODE = 2
6146 14:44:21.619339 SELPH_MODE = 1
6147 14:44:21.622283 PICG_EARLY_EN = 1
6148 14:44:21.625637 VALID_LAT_VALUE = 1
6149 14:44:21.629390 ==============================================================
6150 14:44:21.632114 Enter into Gating configuration >>>>
6151 14:44:21.635815 Exit from Gating configuration <<<<
6152 14:44:21.638823 Enter into DVFS_PRE_config >>>>>
6153 14:44:21.648985 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 14:44:21.652208 Exit from DVFS_PRE_config <<<<<
6155 14:44:21.656198 Enter into PICG configuration >>>>
6156 14:44:21.659197 Exit from PICG configuration <<<<
6157 14:44:21.662628 [RX_INPUT] configuration >>>>>
6158 14:44:21.666329 [RX_INPUT] configuration <<<<<
6159 14:44:21.672271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 14:44:21.675848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 14:44:21.682557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 14:44:21.689214 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 14:44:21.695694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 14:44:21.702247 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 14:44:21.705821 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 14:44:21.708798 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 14:44:21.712212 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 14:44:21.718944 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 14:44:21.722589 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 14:44:21.725574 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 14:44:21.729346 ===================================
6172 14:44:21.732660 LPDDR4 DRAM CONFIGURATION
6173 14:44:21.735845 ===================================
6174 14:44:21.735946 EX_ROW_EN[0] = 0x0
6175 14:44:21.738798 EX_ROW_EN[1] = 0x0
6176 14:44:21.738915 LP4Y_EN = 0x0
6177 14:44:21.742442 WORK_FSP = 0x0
6178 14:44:21.742546 WL = 0x2
6179 14:44:21.745566 RL = 0x2
6180 14:44:21.748900 BL = 0x2
6181 14:44:21.749003 RPST = 0x0
6182 14:44:21.752111 RD_PRE = 0x0
6183 14:44:21.752184 WR_PRE = 0x1
6184 14:44:21.755620 WR_PST = 0x0
6185 14:44:21.755720 DBI_WR = 0x0
6186 14:44:21.759389 DBI_RD = 0x0
6187 14:44:21.759493 OTF = 0x1
6188 14:44:21.762968 ===================================
6189 14:44:21.766058 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 14:44:21.769222 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 14:44:21.776306 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 14:44:21.778841 ===================================
6193 14:44:21.782491 LPDDR4 DRAM CONFIGURATION
6194 14:44:21.786040 ===================================
6195 14:44:21.786141 EX_ROW_EN[0] = 0x10
6196 14:44:21.788817 EX_ROW_EN[1] = 0x0
6197 14:44:21.788916 LP4Y_EN = 0x0
6198 14:44:21.792681 WORK_FSP = 0x0
6199 14:44:21.792782 WL = 0x2
6200 14:44:21.795804 RL = 0x2
6201 14:44:21.795907 BL = 0x2
6202 14:44:21.799094 RPST = 0x0
6203 14:44:21.799199 RD_PRE = 0x0
6204 14:44:21.802244 WR_PRE = 0x1
6205 14:44:21.802316 WR_PST = 0x0
6206 14:44:21.805750 DBI_WR = 0x0
6207 14:44:21.805851 DBI_RD = 0x0
6208 14:44:21.808845 OTF = 0x1
6209 14:44:21.812073 ===================================
6210 14:44:21.818663 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 14:44:21.822703 nWR fixed to 30
6212 14:44:21.825379 [ModeRegInit_LP4] CH0 RK0
6213 14:44:21.825481 [ModeRegInit_LP4] CH0 RK1
6214 14:44:21.829271 [ModeRegInit_LP4] CH1 RK0
6215 14:44:21.832586 [ModeRegInit_LP4] CH1 RK1
6216 14:44:21.832674 match AC timing 19
6217 14:44:21.839286 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 14:44:21.842182 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 14:44:21.845382 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 14:44:21.852639 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 14:44:21.856003 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 14:44:21.856105 ==
6223 14:44:21.859119 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 14:44:21.862020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 14:44:21.862120 ==
6226 14:44:21.869129 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 14:44:21.876238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 14:44:21.878924 [CA 0] Center 36 (8~64) winsize 57
6229 14:44:21.882506 [CA 1] Center 36 (8~64) winsize 57
6230 14:44:21.882609 [CA 2] Center 36 (8~64) winsize 57
6231 14:44:21.886195 [CA 3] Center 36 (8~64) winsize 57
6232 14:44:21.889238 [CA 4] Center 36 (8~64) winsize 57
6233 14:44:21.892338 [CA 5] Center 36 (8~64) winsize 57
6234 14:44:21.892436
6235 14:44:21.895889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 14:44:21.895990
6237 14:44:21.899930 [CATrainingPosCal] consider 1 rank data
6238 14:44:21.903392 u2DelayCellTimex100 = 270/100 ps
6239 14:44:21.906257 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 14:44:21.912951 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 14:44:21.915639 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 14:44:21.918808 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 14:44:21.922544 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 14:44:21.925705 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 14:44:21.925810
6246 14:44:21.929542 CA PerBit enable=1, Macro0, CA PI delay=36
6247 14:44:21.929645
6248 14:44:21.932152 [CBTSetCACLKResult] CA Dly = 36
6249 14:44:21.932252 CS Dly: 1 (0~32)
6250 14:44:21.935583 ==
6251 14:44:21.939572 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 14:44:21.942007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 14:44:21.942112 ==
6254 14:44:21.945474 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 14:44:21.952300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6256 14:44:21.955159 [CA 0] Center 36 (8~64) winsize 57
6257 14:44:21.958893 [CA 1] Center 36 (8~64) winsize 57
6258 14:44:21.962152 [CA 2] Center 36 (8~64) winsize 57
6259 14:44:21.965298 [CA 3] Center 36 (8~64) winsize 57
6260 14:44:21.969193 [CA 4] Center 36 (8~64) winsize 57
6261 14:44:21.972621 [CA 5] Center 36 (8~64) winsize 57
6262 14:44:21.972726
6263 14:44:21.975522 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6264 14:44:21.975623
6265 14:44:21.978475 [CATrainingPosCal] consider 2 rank data
6266 14:44:21.982105 u2DelayCellTimex100 = 270/100 ps
6267 14:44:21.985437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 14:44:21.988274 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 14:44:21.991792 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 14:44:21.998318 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 14:44:22.001722 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 14:44:22.005152 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 14:44:22.005254
6274 14:44:22.008534 CA PerBit enable=1, Macro0, CA PI delay=36
6275 14:44:22.008638
6276 14:44:22.013075 [CBTSetCACLKResult] CA Dly = 36
6277 14:44:22.013155 CS Dly: 1 (0~32)
6278 14:44:22.013231
6279 14:44:22.015293 ----->DramcWriteLeveling(PI) begin...
6280 14:44:22.015399 ==
6281 14:44:22.018472 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 14:44:22.025476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 14:44:22.025583 ==
6284 14:44:22.028967 Write leveling (Byte 0): 40 => 8
6285 14:44:22.029106 Write leveling (Byte 1): 32 => 0
6286 14:44:22.032130 DramcWriteLeveling(PI) end<-----
6287 14:44:22.032231
6288 14:44:22.032323 ==
6289 14:44:22.035164 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 14:44:22.042122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 14:44:22.042230 ==
6292 14:44:22.045264 [Gating] SW mode calibration
6293 14:44:22.052173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 14:44:22.055105 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 14:44:22.061873 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 14:44:22.065627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 14:44:22.068704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 14:44:22.074977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 14:44:22.078417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 14:44:22.081878 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 14:44:22.085082 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 14:44:22.091898 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 14:44:22.095202 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 14:44:22.098307 Total UI for P1: 0, mck2ui 16
6305 14:44:22.101613 best dqsien dly found for B0: ( 0, 14, 24)
6306 14:44:22.105442 Total UI for P1: 0, mck2ui 16
6307 14:44:22.108785 best dqsien dly found for B1: ( 0, 14, 24)
6308 14:44:22.111959 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 14:44:22.115009 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 14:44:22.115112
6311 14:44:22.119128 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 14:44:22.121891 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 14:44:22.125177 [Gating] SW calibration Done
6314 14:44:22.125253 ==
6315 14:44:22.129099 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 14:44:22.135630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 14:44:22.135720 ==
6318 14:44:22.135787 RX Vref Scan: 0
6319 14:44:22.135848
6320 14:44:22.138877 RX Vref 0 -> 0, step: 1
6321 14:44:22.138974
6322 14:44:22.142389 RX Delay -410 -> 252, step: 16
6323 14:44:22.146180 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6324 14:44:22.149129 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6325 14:44:22.152955 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6326 14:44:22.158699 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6327 14:44:22.162689 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6328 14:44:22.165523 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6329 14:44:22.168648 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6330 14:44:22.175796 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6331 14:44:22.179010 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6332 14:44:22.182593 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6333 14:44:22.185582 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6334 14:44:22.192154 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6335 14:44:22.195572 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6336 14:44:22.198757 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6337 14:44:22.202191 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6338 14:44:22.208676 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6339 14:44:22.208774 ==
6340 14:44:22.212182 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 14:44:22.215354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 14:44:22.215438 ==
6343 14:44:22.215504 DQS Delay:
6344 14:44:22.218887 DQS0 = 35, DQS1 = 51
6345 14:44:22.218970 DQM Delay:
6346 14:44:22.222184 DQM0 = 8, DQM1 = 10
6347 14:44:22.222268 DQ Delay:
6348 14:44:22.225831 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6349 14:44:22.229025 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6350 14:44:22.232550 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6351 14:44:22.235865 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6352 14:44:22.235949
6353 14:44:22.236015
6354 14:44:22.236137 ==
6355 14:44:22.238921 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 14:44:22.242735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 14:44:22.242818 ==
6358 14:44:22.242885
6359 14:44:22.242946
6360 14:44:22.245680 TX Vref Scan disable
6361 14:44:22.249963 == TX Byte 0 ==
6362 14:44:22.251885 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 14:44:22.255905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 14:44:22.255984 == TX Byte 1 ==
6365 14:44:22.262687 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 14:44:22.265327 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 14:44:22.265411 ==
6368 14:44:22.269430 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 14:44:22.272134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 14:44:22.272243 ==
6371 14:44:22.272343
6372 14:44:22.272409
6373 14:44:22.276206 TX Vref Scan disable
6374 14:44:22.279359 == TX Byte 0 ==
6375 14:44:22.282609 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 14:44:22.285623 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 14:44:22.285707 == TX Byte 1 ==
6378 14:44:22.291996 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 14:44:22.295849 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 14:44:22.295936
6381 14:44:22.296003 [DATLAT]
6382 14:44:22.298852 Freq=400, CH0 RK0
6383 14:44:22.298935
6384 14:44:22.299002 DATLAT Default: 0xf
6385 14:44:22.302234 0, 0xFFFF, sum = 0
6386 14:44:22.302318 1, 0xFFFF, sum = 0
6387 14:44:22.306022 2, 0xFFFF, sum = 0
6388 14:44:22.306106 3, 0xFFFF, sum = 0
6389 14:44:22.309329 4, 0xFFFF, sum = 0
6390 14:44:22.312508 5, 0xFFFF, sum = 0
6391 14:44:22.312592 6, 0xFFFF, sum = 0
6392 14:44:22.315809 7, 0xFFFF, sum = 0
6393 14:44:22.315894 8, 0xFFFF, sum = 0
6394 14:44:22.318814 9, 0xFFFF, sum = 0
6395 14:44:22.318899 10, 0xFFFF, sum = 0
6396 14:44:22.322159 11, 0xFFFF, sum = 0
6397 14:44:22.322244 12, 0xFFFF, sum = 0
6398 14:44:22.325929 13, 0x0, sum = 1
6399 14:44:22.326014 14, 0x0, sum = 2
6400 14:44:22.328788 15, 0x0, sum = 3
6401 14:44:22.328887 16, 0x0, sum = 4
6402 14:44:22.328993 best_step = 14
6403 14:44:22.329085
6404 14:44:22.332139 ==
6405 14:44:22.335626 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 14:44:22.339466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 14:44:22.339550 ==
6408 14:44:22.339617 RX Vref Scan: 1
6409 14:44:22.339680
6410 14:44:22.342497 RX Vref 0 -> 0, step: 1
6411 14:44:22.342581
6412 14:44:22.345517 RX Delay -343 -> 252, step: 8
6413 14:44:22.345601
6414 14:44:22.350042 Set Vref, RX VrefLevel [Byte0]: 53
6415 14:44:22.352393 [Byte1]: 51
6416 14:44:22.355753
6417 14:44:22.355837 Final RX Vref Byte 0 = 53 to rank0
6418 14:44:22.359379 Final RX Vref Byte 1 = 51 to rank0
6419 14:44:22.362958 Final RX Vref Byte 0 = 53 to rank1
6420 14:44:22.365847 Final RX Vref Byte 1 = 51 to rank1==
6421 14:44:22.369201 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 14:44:22.372677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 14:44:22.376128 ==
6424 14:44:22.376212 DQS Delay:
6425 14:44:22.376278 DQS0 = 40, DQS1 = 60
6426 14:44:22.379114 DQM Delay:
6427 14:44:22.379197 DQM0 = 8, DQM1 = 14
6428 14:44:22.382630 DQ Delay:
6429 14:44:22.382712 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6430 14:44:22.385880 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6431 14:44:22.389326 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6432 14:44:22.392869 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6433 14:44:22.392951
6434 14:44:22.393054
6435 14:44:22.402992 [DQSOSCAuto] RK0, (LSB)MR18= 0x8453, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6436 14:44:22.406002 CH0 RK0: MR19=C0C, MR18=8453
6437 14:44:22.410236 CH0_RK0: MR19=0xC0C, MR18=0x8453, DQSOSC=393, MR23=63, INC=382, DEC=254
6438 14:44:22.412678 ==
6439 14:44:22.412761 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 14:44:22.419402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 14:44:22.419486 ==
6442 14:44:22.423155 [Gating] SW mode calibration
6443 14:44:22.430051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 14:44:22.432870 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 14:44:22.440069 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 14:44:22.443676 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 14:44:22.446500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 14:44:22.453196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 14:44:22.456119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 14:44:22.459488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 14:44:22.466295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 14:44:22.469281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 14:44:22.472720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 14:44:22.476254 Total UI for P1: 0, mck2ui 16
6455 14:44:22.479504 best dqsien dly found for B0: ( 0, 14, 24)
6456 14:44:22.482719 Total UI for P1: 0, mck2ui 16
6457 14:44:22.486037 best dqsien dly found for B1: ( 0, 14, 24)
6458 14:44:22.489167 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 14:44:22.492922 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 14:44:22.493040
6461 14:44:22.496377 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 14:44:22.502788 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 14:44:22.502871 [Gating] SW calibration Done
6464 14:44:22.502938 ==
6465 14:44:22.506575 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 14:44:22.513024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 14:44:22.513108 ==
6468 14:44:22.513174 RX Vref Scan: 0
6469 14:44:22.513237
6470 14:44:22.516926 RX Vref 0 -> 0, step: 1
6471 14:44:22.517019
6472 14:44:22.519406 RX Delay -410 -> 252, step: 16
6473 14:44:22.522545 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6474 14:44:22.525790 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6475 14:44:22.532377 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6476 14:44:22.535800 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6477 14:44:22.539338 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6478 14:44:22.542964 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6479 14:44:22.549590 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6480 14:44:22.552386 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6481 14:44:22.556223 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6482 14:44:22.559063 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6483 14:44:22.566612 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6484 14:44:22.569220 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6485 14:44:22.572744 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6486 14:44:22.576142 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6487 14:44:22.582652 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6488 14:44:22.585789 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6489 14:44:22.585893 ==
6490 14:44:22.589226 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 14:44:22.592963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 14:44:22.593087 ==
6493 14:44:22.596331 DQS Delay:
6494 14:44:22.596429 DQS0 = 43, DQS1 = 51
6495 14:44:22.596524 DQM Delay:
6496 14:44:22.599063 DQM0 = 11, DQM1 = 10
6497 14:44:22.599167 DQ Delay:
6498 14:44:22.602830 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6499 14:44:22.606804 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6500 14:44:22.610079 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6501 14:44:22.612347 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6502 14:44:22.612449
6503 14:44:22.612543
6504 14:44:22.612632 ==
6505 14:44:22.615839 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 14:44:22.619268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 14:44:22.619369 ==
6508 14:44:22.622869
6509 14:44:22.622974
6510 14:44:22.623067 TX Vref Scan disable
6511 14:44:22.626160 == TX Byte 0 ==
6512 14:44:22.629181 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6513 14:44:22.632979 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6514 14:44:22.636125 == TX Byte 1 ==
6515 14:44:22.639257 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6516 14:44:22.643023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6517 14:44:22.643124 ==
6518 14:44:22.646004 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 14:44:22.649929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 14:44:22.650003 ==
6521 14:44:22.652613
6522 14:44:22.652718
6523 14:44:22.652813 TX Vref Scan disable
6524 14:44:22.656115 == TX Byte 0 ==
6525 14:44:22.659568 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6526 14:44:22.662578 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6527 14:44:22.666199 == TX Byte 1 ==
6528 14:44:22.669330 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6529 14:44:22.673383 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6530 14:44:22.673486
6531 14:44:22.673574 [DATLAT]
6532 14:44:22.676339 Freq=400, CH0 RK1
6533 14:44:22.676439
6534 14:44:22.676533 DATLAT Default: 0xe
6535 14:44:22.679276 0, 0xFFFF, sum = 0
6536 14:44:22.679382 1, 0xFFFF, sum = 0
6537 14:44:22.683247 2, 0xFFFF, sum = 0
6538 14:44:22.683346 3, 0xFFFF, sum = 0
6539 14:44:22.685934 4, 0xFFFF, sum = 0
6540 14:44:22.686035 5, 0xFFFF, sum = 0
6541 14:44:22.689392 6, 0xFFFF, sum = 0
6542 14:44:22.692961 7, 0xFFFF, sum = 0
6543 14:44:22.693077 8, 0xFFFF, sum = 0
6544 14:44:22.696269 9, 0xFFFF, sum = 0
6545 14:44:22.696371 10, 0xFFFF, sum = 0
6546 14:44:22.699709 11, 0xFFFF, sum = 0
6547 14:44:22.699817 12, 0xFFFF, sum = 0
6548 14:44:22.702884 13, 0x0, sum = 1
6549 14:44:22.702990 14, 0x0, sum = 2
6550 14:44:22.706415 15, 0x0, sum = 3
6551 14:44:22.706516 16, 0x0, sum = 4
6552 14:44:22.706612 best_step = 14
6553 14:44:22.706702
6554 14:44:22.709773 ==
6555 14:44:22.712771 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 14:44:22.716512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 14:44:22.716616 ==
6558 14:44:22.716712 RX Vref Scan: 0
6559 14:44:22.716803
6560 14:44:22.719420 RX Vref 0 -> 0, step: 1
6561 14:44:22.719522
6562 14:44:22.722639 RX Delay -343 -> 252, step: 8
6563 14:44:22.729814 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6564 14:44:22.733518 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6565 14:44:22.736760 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6566 14:44:22.740060 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6567 14:44:22.746600 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6568 14:44:22.750132 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6569 14:44:22.753473 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6570 14:44:22.757069 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6571 14:44:22.763168 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6572 14:44:22.766765 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6573 14:44:22.769813 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6574 14:44:22.773760 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6575 14:44:22.779956 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6576 14:44:22.783060 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6577 14:44:22.787280 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6578 14:44:22.793068 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6579 14:44:22.793147 ==
6580 14:44:22.796252 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 14:44:22.799526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 14:44:22.799635 ==
6583 14:44:22.799730 DQS Delay:
6584 14:44:22.803349 DQS0 = 48, DQS1 = 60
6585 14:44:22.803452 DQM Delay:
6586 14:44:22.806508 DQM0 = 13, DQM1 = 13
6587 14:44:22.806608 DQ Delay:
6588 14:44:22.809804 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6589 14:44:22.813098 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6590 14:44:22.816501 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6591 14:44:22.820068 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6592 14:44:22.820143
6593 14:44:22.820227
6594 14:44:22.826719 [DQSOSCAuto] RK1, (LSB)MR18= 0x9467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6595 14:44:22.829813 CH0 RK1: MR19=C0C, MR18=9467
6596 14:44:22.836472 CH0_RK1: MR19=0xC0C, MR18=0x9467, DQSOSC=391, MR23=63, INC=386, DEC=257
6597 14:44:22.839845 [RxdqsGatingPostProcess] freq 400
6598 14:44:22.846320 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 14:44:22.846426 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 14:44:22.849720 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 14:44:22.853457 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 14:44:22.856254 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 14:44:22.859966 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 14:44:22.862954 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 14:44:22.866323 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 14:44:22.869859 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 14:44:22.872893 Pre-setting of DQS Precalculation
6608 14:44:22.876369 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 14:44:22.881144 ==
6610 14:44:22.881227 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 14:44:22.886329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 14:44:22.886413 ==
6613 14:44:22.890129 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 14:44:22.896736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6615 14:44:22.899901 [CA 0] Center 36 (8~64) winsize 57
6616 14:44:22.903458 [CA 1] Center 36 (8~64) winsize 57
6617 14:44:22.906534 [CA 2] Center 36 (8~64) winsize 57
6618 14:44:22.909797 [CA 3] Center 36 (8~64) winsize 57
6619 14:44:22.913616 [CA 4] Center 36 (8~64) winsize 57
6620 14:44:22.916796 [CA 5] Center 36 (8~64) winsize 57
6621 14:44:22.916906
6622 14:44:22.920017 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6623 14:44:22.920100
6624 14:44:22.923467 [CATrainingPosCal] consider 1 rank data
6625 14:44:22.926595 u2DelayCellTimex100 = 270/100 ps
6626 14:44:22.930060 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 14:44:22.933427 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 14:44:22.936744 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 14:44:22.940021 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 14:44:22.943171 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 14:44:22.946573 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 14:44:22.949940
6633 14:44:22.953196 CA PerBit enable=1, Macro0, CA PI delay=36
6634 14:44:22.953279
6635 14:44:22.956605 [CBTSetCACLKResult] CA Dly = 36
6636 14:44:22.956688 CS Dly: 1 (0~32)
6637 14:44:22.956755 ==
6638 14:44:22.960138 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 14:44:22.963720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 14:44:22.963804 ==
6641 14:44:22.969714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 14:44:22.976927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 14:44:22.979952 [CA 0] Center 36 (8~64) winsize 57
6644 14:44:22.983693 [CA 1] Center 36 (8~64) winsize 57
6645 14:44:22.986748 [CA 2] Center 36 (8~64) winsize 57
6646 14:44:22.990253 [CA 3] Center 36 (8~64) winsize 57
6647 14:44:22.990337 [CA 4] Center 36 (8~64) winsize 57
6648 14:44:22.994196 [CA 5] Center 36 (8~64) winsize 57
6649 14:44:22.994279
6650 14:44:23.001331 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 14:44:23.001439
6652 14:44:23.004191 [CATrainingPosCal] consider 2 rank data
6653 14:44:23.007161 u2DelayCellTimex100 = 270/100 ps
6654 14:44:23.010273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 14:44:23.013352 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 14:44:23.016314 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 14:44:23.020058 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 14:44:23.023531 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 14:44:23.026512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 14:44:23.026622
6661 14:44:23.029793 CA PerBit enable=1, Macro0, CA PI delay=36
6662 14:44:23.029868
6663 14:44:23.033128 [CBTSetCACLKResult] CA Dly = 36
6664 14:44:23.036164 CS Dly: 1 (0~32)
6665 14:44:23.036266
6666 14:44:23.040107 ----->DramcWriteLeveling(PI) begin...
6667 14:44:23.040185 ==
6668 14:44:23.043166 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 14:44:23.046236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 14:44:23.046312 ==
6671 14:44:23.049711 Write leveling (Byte 0): 40 => 8
6672 14:44:23.053001 Write leveling (Byte 1): 40 => 8
6673 14:44:23.056606 DramcWriteLeveling(PI) end<-----
6674 14:44:23.056682
6675 14:44:23.056786 ==
6676 14:44:23.059789 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 14:44:23.063336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 14:44:23.063449 ==
6679 14:44:23.066553 [Gating] SW mode calibration
6680 14:44:23.072870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 14:44:23.080160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 14:44:23.083405 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 14:44:23.086778 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 14:44:23.093338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 14:44:23.097355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 14:44:23.099860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 14:44:23.107148 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 14:44:23.110394 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 14:44:23.113599 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 14:44:23.119739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 14:44:23.119845 Total UI for P1: 0, mck2ui 16
6692 14:44:23.123248 best dqsien dly found for B0: ( 0, 14, 24)
6693 14:44:23.126223 Total UI for P1: 0, mck2ui 16
6694 14:44:23.129787 best dqsien dly found for B1: ( 0, 14, 24)
6695 14:44:23.136329 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 14:44:23.139944 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 14:44:23.140046
6698 14:44:23.143187 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 14:44:23.146122 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 14:44:23.149687 [Gating] SW calibration Done
6701 14:44:23.149778 ==
6702 14:44:23.152767 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 14:44:23.156803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 14:44:23.156888 ==
6705 14:44:23.159445 RX Vref Scan: 0
6706 14:44:23.159528
6707 14:44:23.159594 RX Vref 0 -> 0, step: 1
6708 14:44:23.159656
6709 14:44:23.163265 RX Delay -410 -> 252, step: 16
6710 14:44:23.169675 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6711 14:44:23.173573 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6712 14:44:23.176669 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6713 14:44:23.179475 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6714 14:44:23.186353 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6715 14:44:23.189485 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6716 14:44:23.192897 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6717 14:44:23.196325 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6718 14:44:23.199987 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6719 14:44:23.206315 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6720 14:44:23.209242 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6721 14:44:23.212710 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6722 14:44:23.219377 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6723 14:44:23.222978 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6724 14:44:23.226134 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6725 14:44:23.230058 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6726 14:44:23.230163 ==
6727 14:44:23.232696 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 14:44:23.239351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 14:44:23.239457 ==
6730 14:44:23.239555 DQS Delay:
6731 14:44:23.243045 DQS0 = 51, DQS1 = 59
6732 14:44:23.243122 DQM Delay:
6733 14:44:23.243194 DQM0 = 19, DQM1 = 17
6734 14:44:23.246051 DQ Delay:
6735 14:44:23.249631 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6736 14:44:23.252632 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6737 14:44:23.256756 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6738 14:44:23.259739 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6739 14:44:23.259842
6740 14:44:23.259938
6741 14:44:23.260028 ==
6742 14:44:23.262992 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 14:44:23.266875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 14:44:23.266982 ==
6745 14:44:23.267081
6746 14:44:23.267173
6747 14:44:23.269372 TX Vref Scan disable
6748 14:44:23.269477 == TX Byte 0 ==
6749 14:44:23.272765 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 14:44:23.279387 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 14:44:23.279483 == TX Byte 1 ==
6752 14:44:23.282789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 14:44:23.289648 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 14:44:23.289732 ==
6755 14:44:23.292762 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 14:44:23.296247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 14:44:23.296330 ==
6758 14:44:23.296397
6759 14:44:23.296465
6760 14:44:23.299320 TX Vref Scan disable
6761 14:44:23.299403 == TX Byte 0 ==
6762 14:44:23.303083 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 14:44:23.309659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 14:44:23.309744 == TX Byte 1 ==
6765 14:44:23.312808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 14:44:23.319326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 14:44:23.319410
6768 14:44:23.319476 [DATLAT]
6769 14:44:23.319538 Freq=400, CH1 RK0
6770 14:44:23.322764
6771 14:44:23.322847 DATLAT Default: 0xf
6772 14:44:23.326344 0, 0xFFFF, sum = 0
6773 14:44:23.326461 1, 0xFFFF, sum = 0
6774 14:44:23.329865 2, 0xFFFF, sum = 0
6775 14:44:23.329966 3, 0xFFFF, sum = 0
6776 14:44:23.333358 4, 0xFFFF, sum = 0
6777 14:44:23.333443 5, 0xFFFF, sum = 0
6778 14:44:23.336438 6, 0xFFFF, sum = 0
6779 14:44:23.336521 7, 0xFFFF, sum = 0
6780 14:44:23.339307 8, 0xFFFF, sum = 0
6781 14:44:23.339392 9, 0xFFFF, sum = 0
6782 14:44:23.343143 10, 0xFFFF, sum = 0
6783 14:44:23.343227 11, 0xFFFF, sum = 0
6784 14:44:23.346341 12, 0xFFFF, sum = 0
6785 14:44:23.346426 13, 0x0, sum = 1
6786 14:44:23.349364 14, 0x0, sum = 2
6787 14:44:23.349448 15, 0x0, sum = 3
6788 14:44:23.352844 16, 0x0, sum = 4
6789 14:44:23.352955 best_step = 14
6790 14:44:23.353074
6791 14:44:23.353137 ==
6792 14:44:23.355805 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 14:44:23.362655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 14:44:23.362740 ==
6795 14:44:23.362807 RX Vref Scan: 1
6796 14:44:23.362869
6797 14:44:23.365822 RX Vref 0 -> 0, step: 1
6798 14:44:23.365906
6799 14:44:23.369460 RX Delay -359 -> 252, step: 8
6800 14:44:23.369543
6801 14:44:23.373117 Set Vref, RX VrefLevel [Byte0]: 57
6802 14:44:23.376329 [Byte1]: 53
6803 14:44:23.376412
6804 14:44:23.379574 Final RX Vref Byte 0 = 57 to rank0
6805 14:44:23.382638 Final RX Vref Byte 1 = 53 to rank0
6806 14:44:23.385985 Final RX Vref Byte 0 = 57 to rank1
6807 14:44:23.389205 Final RX Vref Byte 1 = 53 to rank1==
6808 14:44:23.393436 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 14:44:23.395915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 14:44:23.399365 ==
6811 14:44:23.399449 DQS Delay:
6812 14:44:23.399515 DQS0 = 48, DQS1 = 60
6813 14:44:23.402740 DQM Delay:
6814 14:44:23.402823 DQM0 = 12, DQM1 = 13
6815 14:44:23.406107 DQ Delay:
6816 14:44:23.406191 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6817 14:44:23.409272 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6818 14:44:23.412506 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6819 14:44:23.415798 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6820 14:44:23.415882
6821 14:44:23.415947
6822 14:44:23.426055 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f37, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6823 14:44:23.429204 CH1 RK0: MR19=C0C, MR18=8F37
6824 14:44:23.432598 CH1_RK0: MR19=0xC0C, MR18=0x8F37, DQSOSC=391, MR23=63, INC=386, DEC=257
6825 14:44:23.436054 ==
6826 14:44:23.439097 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 14:44:23.442736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 14:44:23.442845 ==
6829 14:44:23.445639 [Gating] SW mode calibration
6830 14:44:23.452589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 14:44:23.456677 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 14:44:23.463211 0 11 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
6833 14:44:23.466411 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6834 14:44:23.469440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 14:44:23.475907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 14:44:23.479004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 14:44:23.482698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 14:44:23.489899 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 14:44:23.492437 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 14:44:23.496387 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 14:44:23.499036 Total UI for P1: 0, mck2ui 16
6842 14:44:23.502702 best dqsien dly found for B0: ( 0, 14, 24)
6843 14:44:23.505702 Total UI for P1: 0, mck2ui 16
6844 14:44:23.509508 best dqsien dly found for B1: ( 0, 14, 24)
6845 14:44:23.512594 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 14:44:23.516512 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 14:44:23.516617
6848 14:44:23.519287 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 14:44:23.526025 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 14:44:23.526130 [Gating] SW calibration Done
6851 14:44:23.526206 ==
6852 14:44:23.529246 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 14:44:23.536321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 14:44:23.536428 ==
6855 14:44:23.536520 RX Vref Scan: 0
6856 14:44:23.536612
6857 14:44:23.539982 RX Vref 0 -> 0, step: 1
6858 14:44:23.540083
6859 14:44:23.543150 RX Delay -410 -> 252, step: 16
6860 14:44:23.545975 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6861 14:44:23.550518 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6862 14:44:23.556159 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6863 14:44:23.559642 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6864 14:44:23.563030 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6865 14:44:23.566006 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6866 14:44:23.572471 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6867 14:44:23.576181 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6868 14:44:23.579137 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6869 14:44:23.583007 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6870 14:44:23.589351 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6871 14:44:23.593064 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6872 14:44:23.596529 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6873 14:44:23.599374 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6874 14:44:23.606186 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6875 14:44:23.609578 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6876 14:44:23.609683 ==
6877 14:44:23.613188 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 14:44:23.615899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 14:44:23.616004 ==
6880 14:44:23.619665 DQS Delay:
6881 14:44:23.619769 DQS0 = 43, DQS1 = 59
6882 14:44:23.619862 DQM Delay:
6883 14:44:23.622705 DQM0 = 9, DQM1 = 20
6884 14:44:23.622806 DQ Delay:
6885 14:44:23.625904 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6886 14:44:23.629175 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6887 14:44:23.632654 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6888 14:44:23.635967 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6889 14:44:23.636070
6890 14:44:23.636167
6891 14:44:23.636256 ==
6892 14:44:23.639299 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 14:44:23.642728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 14:44:23.642832 ==
6895 14:44:23.642931
6896 14:44:23.643020
6897 14:44:23.646711 TX Vref Scan disable
6898 14:44:23.649354 == TX Byte 0 ==
6899 14:44:23.653177 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6900 14:44:23.656377 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6901 14:44:23.656478 == TX Byte 1 ==
6902 14:44:23.662935 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 14:44:23.666500 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 14:44:23.666582 ==
6905 14:44:23.669523 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 14:44:23.673271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 14:44:23.673354 ==
6908 14:44:23.673420
6909 14:44:23.675831
6910 14:44:23.675912 TX Vref Scan disable
6911 14:44:23.679690 == TX Byte 0 ==
6912 14:44:23.682707 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6913 14:44:23.686187 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6914 14:44:23.689454 == TX Byte 1 ==
6915 14:44:23.692902 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 14:44:23.696395 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 14:44:23.696501
6918 14:44:23.696595 [DATLAT]
6919 14:44:23.699181 Freq=400, CH1 RK1
6920 14:44:23.699289
6921 14:44:23.699385 DATLAT Default: 0xe
6922 14:44:23.702413 0, 0xFFFF, sum = 0
6923 14:44:23.702520 1, 0xFFFF, sum = 0
6924 14:44:23.706043 2, 0xFFFF, sum = 0
6925 14:44:23.708925 3, 0xFFFF, sum = 0
6926 14:44:23.709069 4, 0xFFFF, sum = 0
6927 14:44:23.712433 5, 0xFFFF, sum = 0
6928 14:44:23.712533 6, 0xFFFF, sum = 0
6929 14:44:23.715682 7, 0xFFFF, sum = 0
6930 14:44:23.715788 8, 0xFFFF, sum = 0
6931 14:44:23.719271 9, 0xFFFF, sum = 0
6932 14:44:23.719375 10, 0xFFFF, sum = 0
6933 14:44:23.722709 11, 0xFFFF, sum = 0
6934 14:44:23.722814 12, 0xFFFF, sum = 0
6935 14:44:23.726448 13, 0x0, sum = 1
6936 14:44:23.726550 14, 0x0, sum = 2
6937 14:44:23.729347 15, 0x0, sum = 3
6938 14:44:23.729447 16, 0x0, sum = 4
6939 14:44:23.732568 best_step = 14
6940 14:44:23.732669
6941 14:44:23.732762 ==
6942 14:44:23.735780 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 14:44:23.739447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 14:44:23.739553 ==
6945 14:44:23.739647 RX Vref Scan: 0
6946 14:44:23.739737
6947 14:44:23.742693 RX Vref 0 -> 0, step: 1
6948 14:44:23.742795
6949 14:44:23.745994 RX Delay -359 -> 252, step: 8
6950 14:44:23.753105 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6951 14:44:23.756907 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6952 14:44:23.761780 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6953 14:44:23.763519 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6954 14:44:23.770352 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6955 14:44:23.773474 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6956 14:44:23.776790 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6957 14:44:23.780268 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6958 14:44:23.787452 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6959 14:44:23.790280 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6960 14:44:23.793471 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6961 14:44:23.797059 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6962 14:44:23.803790 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6963 14:44:23.807323 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6964 14:44:23.810183 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6965 14:44:23.813798 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6966 14:44:23.813884 ==
6967 14:44:23.816811 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 14:44:23.823836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 14:44:23.823941 ==
6970 14:44:23.824034 DQS Delay:
6971 14:44:23.826967 DQS0 = 52, DQS1 = 56
6972 14:44:23.827070 DQM Delay:
6973 14:44:23.830579 DQM0 = 13, DQM1 = 8
6974 14:44:23.830680 DQ Delay:
6975 14:44:23.833587 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6976 14:44:23.837078 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6977 14:44:23.837155 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6978 14:44:23.843413 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6979 14:44:23.843518
6980 14:44:23.843610
6981 14:44:23.850946 [DQSOSCAuto] RK1, (LSB)MR18= 0x738a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6982 14:44:23.853913 CH1 RK1: MR19=C0C, MR18=738A
6983 14:44:23.860026 CH1_RK1: MR19=0xC0C, MR18=0x738A, DQSOSC=392, MR23=63, INC=384, DEC=256
6984 14:44:23.863602 [RxdqsGatingPostProcess] freq 400
6985 14:44:23.866891 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 14:44:23.869909 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 14:44:23.873693 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 14:44:23.877216 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 14:44:23.880088 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 14:44:23.883203 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 14:44:23.886838 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 14:44:23.890227 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 14:44:23.893640 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 14:44:23.897286 Pre-setting of DQS Precalculation
6995 14:44:23.900070 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 14:44:23.906546 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 14:44:23.916854 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 14:44:23.916958
6999 14:44:23.917062
7000 14:44:23.917155 [Calibration Summary] 800 Mbps
7001 14:44:23.920049 CH 0, Rank 0
7002 14:44:23.923583 SW Impedance : PASS
7003 14:44:23.923684 DUTY Scan : NO K
7004 14:44:23.926939 ZQ Calibration : PASS
7005 14:44:23.927014 Jitter Meter : NO K
7006 14:44:23.929969 CBT Training : PASS
7007 14:44:23.933273 Write leveling : PASS
7008 14:44:23.933372 RX DQS gating : PASS
7009 14:44:23.936749 RX DQ/DQS(RDDQC) : PASS
7010 14:44:23.939925 TX DQ/DQS : PASS
7011 14:44:23.940030 RX DATLAT : PASS
7012 14:44:23.943842 RX DQ/DQS(Engine): PASS
7013 14:44:23.947140 TX OE : NO K
7014 14:44:23.947242 All Pass.
7015 14:44:23.947333
7016 14:44:23.947428 CH 0, Rank 1
7017 14:44:23.950303 SW Impedance : PASS
7018 14:44:23.953552 DUTY Scan : NO K
7019 14:44:23.953657 ZQ Calibration : PASS
7020 14:44:23.956948 Jitter Meter : NO K
7021 14:44:23.957060 CBT Training : PASS
7022 14:44:23.960196 Write leveling : NO K
7023 14:44:23.964756 RX DQS gating : PASS
7024 14:44:23.964861 RX DQ/DQS(RDDQC) : PASS
7025 14:44:23.966802 TX DQ/DQS : PASS
7026 14:44:23.970599 RX DATLAT : PASS
7027 14:44:23.970698 RX DQ/DQS(Engine): PASS
7028 14:44:23.973569 TX OE : NO K
7029 14:44:23.973669 All Pass.
7030 14:44:23.973761
7031 14:44:23.976743 CH 1, Rank 0
7032 14:44:23.976842 SW Impedance : PASS
7033 14:44:23.980601 DUTY Scan : NO K
7034 14:44:23.984039 ZQ Calibration : PASS
7035 14:44:23.984116 Jitter Meter : NO K
7036 14:44:23.986718 CBT Training : PASS
7037 14:44:23.992235 Write leveling : PASS
7038 14:44:23.992338 RX DQS gating : PASS
7039 14:44:23.993497 RX DQ/DQS(RDDQC) : PASS
7040 14:44:23.996871 TX DQ/DQS : PASS
7041 14:44:23.996971 RX DATLAT : PASS
7042 14:44:24.000033 RX DQ/DQS(Engine): PASS
7043 14:44:24.003588 TX OE : NO K
7044 14:44:24.003697 All Pass.
7045 14:44:24.003789
7046 14:44:24.003891 CH 1, Rank 1
7047 14:44:24.006910 SW Impedance : PASS
7048 14:44:24.007010 DUTY Scan : NO K
7049 14:44:24.010339 ZQ Calibration : PASS
7050 14:44:24.013773 Jitter Meter : NO K
7051 14:44:24.013875 CBT Training : PASS
7052 14:44:24.016952 Write leveling : NO K
7053 14:44:24.020330 RX DQS gating : PASS
7054 14:44:24.020429 RX DQ/DQS(RDDQC) : PASS
7055 14:44:24.023772 TX DQ/DQS : PASS
7056 14:44:24.026818 RX DATLAT : PASS
7057 14:44:24.026918 RX DQ/DQS(Engine): PASS
7058 14:44:24.030777 TX OE : NO K
7059 14:44:24.030877 All Pass.
7060 14:44:24.030970
7061 14:44:24.033360 DramC Write-DBI off
7062 14:44:24.036983 PER_BANK_REFRESH: Hybrid Mode
7063 14:44:24.037056 TX_TRACKING: ON
7064 14:44:24.047385 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 14:44:24.050324 [FAST_K] Save calibration result to emmc
7066 14:44:24.053517 dramc_set_vcore_voltage set vcore to 725000
7067 14:44:24.057203 Read voltage for 1600, 0
7068 14:44:24.057309 Vio18 = 0
7069 14:44:24.057402 Vcore = 725000
7070 14:44:24.060428 Vdram = 0
7071 14:44:24.060527 Vddq = 0
7072 14:44:24.060619 Vmddr = 0
7073 14:44:24.067370 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 14:44:24.070309 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 14:44:24.073514 MEM_TYPE=3, freq_sel=13
7076 14:44:24.076784 sv_algorithm_assistance_LP4_3733
7077 14:44:24.080903 ============ PULL DRAM RESETB DOWN ============
7078 14:44:24.083952 ========== PULL DRAM RESETB DOWN end =========
7079 14:44:24.090062 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 14:44:24.094832 ===================================
7081 14:44:24.094938 LPDDR4 DRAM CONFIGURATION
7082 14:44:24.096784 ===================================
7083 14:44:24.100167 EX_ROW_EN[0] = 0x0
7084 14:44:24.103911 EX_ROW_EN[1] = 0x0
7085 14:44:24.104013 LP4Y_EN = 0x0
7086 14:44:24.106846 WORK_FSP = 0x1
7087 14:44:24.106943 WL = 0x5
7088 14:44:24.110512 RL = 0x5
7089 14:44:24.110611 BL = 0x2
7090 14:44:24.113634 RPST = 0x0
7091 14:44:24.113737 RD_PRE = 0x0
7092 14:44:24.117066 WR_PRE = 0x1
7093 14:44:24.117167 WR_PST = 0x1
7094 14:44:24.120715 DBI_WR = 0x0
7095 14:44:24.120817 DBI_RD = 0x0
7096 14:44:24.123742 OTF = 0x1
7097 14:44:24.127058 ===================================
7098 14:44:24.130196 ===================================
7099 14:44:24.130300 ANA top config
7100 14:44:24.133873 ===================================
7101 14:44:24.136833 DLL_ASYNC_EN = 0
7102 14:44:24.140172 ALL_SLAVE_EN = 0
7103 14:44:24.140273 NEW_RANK_MODE = 1
7104 14:44:24.143794 DLL_IDLE_MODE = 1
7105 14:44:24.147286 LP45_APHY_COMB_EN = 1
7106 14:44:24.150390 TX_ODT_DIS = 0
7107 14:44:24.153851 NEW_8X_MODE = 1
7108 14:44:24.156835 ===================================
7109 14:44:24.160284 ===================================
7110 14:44:24.160388 data_rate = 3200
7111 14:44:24.164047 CKR = 1
7112 14:44:24.166798 DQ_P2S_RATIO = 8
7113 14:44:24.170478 ===================================
7114 14:44:24.173607 CA_P2S_RATIO = 8
7115 14:44:24.177184 DQ_CA_OPEN = 0
7116 14:44:24.180689 DQ_SEMI_OPEN = 0
7117 14:44:24.180791 CA_SEMI_OPEN = 0
7118 14:44:24.183770 CA_FULL_RATE = 0
7119 14:44:24.187141 DQ_CKDIV4_EN = 0
7120 14:44:24.190747 CA_CKDIV4_EN = 0
7121 14:44:24.193927 CA_PREDIV_EN = 0
7122 14:44:24.197335 PH8_DLY = 12
7123 14:44:24.197437 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 14:44:24.201358 DQ_AAMCK_DIV = 4
7125 14:44:24.203927 CA_AAMCK_DIV = 4
7126 14:44:24.208384 CA_ADMCK_DIV = 4
7127 14:44:24.211230 DQ_TRACK_CA_EN = 0
7128 14:44:24.213918 CA_PICK = 1600
7129 14:44:24.214031 CA_MCKIO = 1600
7130 14:44:24.217384 MCKIO_SEMI = 0
7131 14:44:24.220693 PLL_FREQ = 3068
7132 14:44:24.224270 DQ_UI_PI_RATIO = 32
7133 14:44:24.227507 CA_UI_PI_RATIO = 0
7134 14:44:24.230574 ===================================
7135 14:44:24.234316 ===================================
7136 14:44:24.237510 memory_type:LPDDR4
7137 14:44:24.237601 GP_NUM : 10
7138 14:44:24.240606 SRAM_EN : 1
7139 14:44:24.240704 MD32_EN : 0
7140 14:44:24.243932 ===================================
7141 14:44:24.247353 [ANA_INIT] >>>>>>>>>>>>>>
7142 14:44:24.251420 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 14:44:24.254111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 14:44:24.257733 ===================================
7145 14:44:24.260911 data_rate = 3200,PCW = 0X7600
7146 14:44:24.263929 ===================================
7147 14:44:24.267231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 14:44:24.271641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 14:44:24.277434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 14:44:24.280803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 14:44:24.284586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 14:44:24.287310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 14:44:24.290532 [ANA_INIT] flow start
7154 14:44:24.294439 [ANA_INIT] PLL >>>>>>>>
7155 14:44:24.294544 [ANA_INIT] PLL <<<<<<<<
7156 14:44:24.297782 [ANA_INIT] MIDPI >>>>>>>>
7157 14:44:24.301231 [ANA_INIT] MIDPI <<<<<<<<
7158 14:44:24.304900 [ANA_INIT] DLL >>>>>>>>
7159 14:44:24.305040 [ANA_INIT] DLL <<<<<<<<
7160 14:44:24.307411 [ANA_INIT] flow end
7161 14:44:24.311005 ============ LP4 DIFF to SE enter ============
7162 14:44:24.314733 ============ LP4 DIFF to SE exit ============
7163 14:44:24.317714 [ANA_INIT] <<<<<<<<<<<<<
7164 14:44:24.320611 [Flow] Enable top DCM control >>>>>
7165 14:44:24.324503 [Flow] Enable top DCM control <<<<<
7166 14:44:24.327700 Enable DLL master slave shuffle
7167 14:44:24.333892 ==============================================================
7168 14:44:24.334001 Gating Mode config
7169 14:44:24.340642 ==============================================================
7170 14:44:24.340747 Config description:
7171 14:44:24.350748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 14:44:24.357340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 14:44:24.364167 SELPH_MODE 0: By rank 1: By Phase
7174 14:44:24.367430 ==============================================================
7175 14:44:24.370532 GAT_TRACK_EN = 1
7176 14:44:24.374026 RX_GATING_MODE = 2
7177 14:44:24.377236 RX_GATING_TRACK_MODE = 2
7178 14:44:24.380599 SELPH_MODE = 1
7179 14:44:24.384111 PICG_EARLY_EN = 1
7180 14:44:24.387411 VALID_LAT_VALUE = 1
7181 14:44:24.391006 ==============================================================
7182 14:44:24.394319 Enter into Gating configuration >>>>
7183 14:44:24.397521 Exit from Gating configuration <<<<
7184 14:44:24.400939 Enter into DVFS_PRE_config >>>>>
7185 14:44:24.414010 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 14:44:24.414130 Exit from DVFS_PRE_config <<<<<
7187 14:44:24.417836 Enter into PICG configuration >>>>
7188 14:44:24.420856 Exit from PICG configuration <<<<
7189 14:44:24.424215 [RX_INPUT] configuration >>>>>
7190 14:44:24.427702 [RX_INPUT] configuration <<<<<
7191 14:44:24.434042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 14:44:24.437449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 14:44:24.444136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 14:44:24.450740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 14:44:24.457514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 14:44:24.464489 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 14:44:24.467979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 14:44:24.470917 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 14:44:24.474516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 14:44:24.480685 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 14:44:24.484101 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 14:44:24.487442 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 14:44:24.490844 ===================================
7204 14:44:24.495047 LPDDR4 DRAM CONFIGURATION
7205 14:44:24.497832 ===================================
7206 14:44:24.497933 EX_ROW_EN[0] = 0x0
7207 14:44:24.500928 EX_ROW_EN[1] = 0x0
7208 14:44:24.501074 LP4Y_EN = 0x0
7209 14:44:24.504400 WORK_FSP = 0x1
7210 14:44:24.504506 WL = 0x5
7211 14:44:24.507378 RL = 0x5
7212 14:44:24.511152 BL = 0x2
7213 14:44:24.511256 RPST = 0x0
7214 14:44:24.514169 RD_PRE = 0x0
7215 14:44:24.514272 WR_PRE = 0x1
7216 14:44:24.517611 WR_PST = 0x1
7217 14:44:24.517715 DBI_WR = 0x0
7218 14:44:24.520919 DBI_RD = 0x0
7219 14:44:24.521063 OTF = 0x1
7220 14:44:24.524303 ===================================
7221 14:44:24.528410 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 14:44:24.534091 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 14:44:24.537676 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 14:44:24.541235 ===================================
7225 14:44:24.544138 LPDDR4 DRAM CONFIGURATION
7226 14:44:24.547763 ===================================
7227 14:44:24.547846 EX_ROW_EN[0] = 0x10
7228 14:44:24.551384 EX_ROW_EN[1] = 0x0
7229 14:44:24.551466 LP4Y_EN = 0x0
7230 14:44:24.554066 WORK_FSP = 0x1
7231 14:44:24.554149 WL = 0x5
7232 14:44:24.557867 RL = 0x5
7233 14:44:24.557949 BL = 0x2
7234 14:44:24.560945 RPST = 0x0
7235 14:44:24.561080 RD_PRE = 0x0
7236 14:44:24.564042 WR_PRE = 0x1
7237 14:44:24.564125 WR_PST = 0x1
7238 14:44:24.567451 DBI_WR = 0x0
7239 14:44:24.567533 DBI_RD = 0x0
7240 14:44:24.571122 OTF = 0x1
7241 14:44:24.574266 ===================================
7242 14:44:24.581120 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 14:44:24.581203 ==
7244 14:44:24.584473 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 14:44:24.587457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 14:44:24.587540 ==
7247 14:44:24.590668 [Duty_Offset_Calibration]
7248 14:44:24.590750 B0:2 B1:-1 CA:1
7249 14:44:24.590815
7250 14:44:24.594334 [DutyScan_Calibration_Flow] k_type=0
7251 14:44:24.604785
7252 14:44:24.604868 ==CLK 0==
7253 14:44:24.607944 Final CLK duty delay cell = -4
7254 14:44:24.611346 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7255 14:44:24.615035 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7256 14:44:24.617927 [-4] AVG Duty = 4937%(X100)
7257 14:44:24.618009
7258 14:44:24.621564 CH0 CLK Duty spec in!! Max-Min= 187%
7259 14:44:24.624446 [DutyScan_Calibration_Flow] ====Done====
7260 14:44:24.624527
7261 14:44:24.627907 [DutyScan_Calibration_Flow] k_type=1
7262 14:44:24.644107
7263 14:44:24.644189 ==DQS 0 ==
7264 14:44:24.647419 Final DQS duty delay cell = 0
7265 14:44:24.651137 [0] MAX Duty = 5125%(X100), DQS PI = 54
7266 14:44:24.654017 [0] MIN Duty = 5000%(X100), DQS PI = 14
7267 14:44:24.654100 [0] AVG Duty = 5062%(X100)
7268 14:44:24.657679
7269 14:44:24.657762 ==DQS 1 ==
7270 14:44:24.660874 Final DQS duty delay cell = -4
7271 14:44:24.664094 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7272 14:44:24.667494 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7273 14:44:24.670697 [-4] AVG Duty = 5046%(X100)
7274 14:44:24.670779
7275 14:44:24.674270 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7276 14:44:24.674352
7277 14:44:24.677644 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7278 14:44:24.680483 [DutyScan_Calibration_Flow] ====Done====
7279 14:44:24.680565
7280 14:44:24.684108 [DutyScan_Calibration_Flow] k_type=3
7281 14:44:24.701698
7282 14:44:24.701809 ==DQM 0 ==
7283 14:44:24.704756 Final DQM duty delay cell = 0
7284 14:44:24.708404 [0] MAX Duty = 5000%(X100), DQS PI = 20
7285 14:44:24.711644 [0] MIN Duty = 4875%(X100), DQS PI = 4
7286 14:44:24.711746 [0] AVG Duty = 4937%(X100)
7287 14:44:24.714820
7288 14:44:24.714924 ==DQM 1 ==
7289 14:44:24.718308 Final DQM duty delay cell = 0
7290 14:44:24.721273 [0] MAX Duty = 5187%(X100), DQS PI = 58
7291 14:44:24.724828 [0] MIN Duty = 4969%(X100), DQS PI = 18
7292 14:44:24.724932 [0] AVG Duty = 5078%(X100)
7293 14:44:24.728504
7294 14:44:24.731647 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7295 14:44:24.731748
7296 14:44:24.734779 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7297 14:44:24.738404 [DutyScan_Calibration_Flow] ====Done====
7298 14:44:24.738503
7299 14:44:24.741162 [DutyScan_Calibration_Flow] k_type=2
7300 14:44:24.757550
7301 14:44:24.757665 ==DQ 0 ==
7302 14:44:24.760937 Final DQ duty delay cell = -4
7303 14:44:24.764325 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7304 14:44:24.767941 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7305 14:44:24.771360 [-4] AVG Duty = 4922%(X100)
7306 14:44:24.771469
7307 14:44:24.771564 ==DQ 1 ==
7308 14:44:24.774612 Final DQ duty delay cell = 0
7309 14:44:24.777512 [0] MAX Duty = 5031%(X100), DQS PI = 30
7310 14:44:24.780537 [0] MIN Duty = 4938%(X100), DQS PI = 4
7311 14:44:24.780640 [0] AVG Duty = 4984%(X100)
7312 14:44:24.784604
7313 14:44:24.787575 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7314 14:44:24.787677
7315 14:44:24.790666 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7316 14:44:24.794185 [DutyScan_Calibration_Flow] ====Done====
7317 14:44:24.794262 ==
7318 14:44:24.797381 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 14:44:24.801369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 14:44:24.801473 ==
7321 14:44:24.804741 [Duty_Offset_Calibration]
7322 14:44:24.804844 B0:1 B1:1 CA:2
7323 14:44:24.804934
7324 14:44:24.808469 [DutyScan_Calibration_Flow] k_type=0
7325 14:44:24.818079
7326 14:44:24.818181 ==CLK 0==
7327 14:44:24.821242 Final CLK duty delay cell = 0
7328 14:44:24.825008 [0] MAX Duty = 5187%(X100), DQS PI = 24
7329 14:44:24.828168 [0] MIN Duty = 4938%(X100), DQS PI = 50
7330 14:44:24.828269 [0] AVG Duty = 5062%(X100)
7331 14:44:24.831389
7332 14:44:24.834246 CH1 CLK Duty spec in!! Max-Min= 249%
7333 14:44:24.837484 [DutyScan_Calibration_Flow] ====Done====
7334 14:44:24.837584
7335 14:44:24.841717 [DutyScan_Calibration_Flow] k_type=1
7336 14:44:24.857283
7337 14:44:24.857360 ==DQS 0 ==
7338 14:44:24.861160 Final DQS duty delay cell = 0
7339 14:44:24.864148 [0] MAX Duty = 5062%(X100), DQS PI = 20
7340 14:44:24.867483 [0] MIN Duty = 4813%(X100), DQS PI = 50
7341 14:44:24.867583 [0] AVG Duty = 4937%(X100)
7342 14:44:24.871109
7343 14:44:24.871216 ==DQS 1 ==
7344 14:44:24.874427 Final DQS duty delay cell = 0
7345 14:44:24.877227 [0] MAX Duty = 5031%(X100), DQS PI = 34
7346 14:44:24.880980 [0] MIN Duty = 4938%(X100), DQS PI = 14
7347 14:44:24.881115 [0] AVG Duty = 4984%(X100)
7348 14:44:24.884244
7349 14:44:24.887617 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7350 14:44:24.887716
7351 14:44:24.891313 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7352 14:44:24.894618 [DutyScan_Calibration_Flow] ====Done====
7353 14:44:24.894725
7354 14:44:24.897669 [DutyScan_Calibration_Flow] k_type=3
7355 14:44:24.914520
7356 14:44:24.914611 ==DQM 0 ==
7357 14:44:24.918006 Final DQM duty delay cell = 0
7358 14:44:24.921050 [0] MAX Duty = 5156%(X100), DQS PI = 20
7359 14:44:24.924269 [0] MIN Duty = 4844%(X100), DQS PI = 50
7360 14:44:24.927590 [0] AVG Duty = 5000%(X100)
7361 14:44:24.927676
7362 14:44:24.927742 ==DQM 1 ==
7363 14:44:24.931059 Final DQM duty delay cell = 0
7364 14:44:24.934306 [0] MAX Duty = 5125%(X100), DQS PI = 8
7365 14:44:24.937575 [0] MIN Duty = 4875%(X100), DQS PI = 20
7366 14:44:24.937659 [0] AVG Duty = 5000%(X100)
7367 14:44:24.940720
7368 14:44:24.944449 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7369 14:44:24.944532
7370 14:44:24.947686 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7371 14:44:24.951055 [DutyScan_Calibration_Flow] ====Done====
7372 14:44:24.951139
7373 14:44:24.954683 [DutyScan_Calibration_Flow] k_type=2
7374 14:44:24.971071
7375 14:44:24.971154 ==DQ 0 ==
7376 14:44:24.974628 Final DQ duty delay cell = 0
7377 14:44:24.977737 [0] MAX Duty = 5125%(X100), DQS PI = 20
7378 14:44:24.980863 [0] MIN Duty = 4907%(X100), DQS PI = 52
7379 14:44:24.980946 [0] AVG Duty = 5016%(X100)
7380 14:44:24.984775
7381 14:44:24.984858 ==DQ 1 ==
7382 14:44:24.987638 Final DQ duty delay cell = 0
7383 14:44:24.990993 [0] MAX Duty = 5093%(X100), DQS PI = 6
7384 14:44:24.994692 [0] MIN Duty = 5031%(X100), DQS PI = 0
7385 14:44:24.994775 [0] AVG Duty = 5062%(X100)
7386 14:44:24.994855
7387 14:44:24.998057 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7388 14:44:24.998140
7389 14:44:25.002001 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7390 14:44:25.007685 [DutyScan_Calibration_Flow] ====Done====
7391 14:44:25.011249 nWR fixed to 30
7392 14:44:25.011333 [ModeRegInit_LP4] CH0 RK0
7393 14:44:25.014823 [ModeRegInit_LP4] CH0 RK1
7394 14:44:25.017568 [ModeRegInit_LP4] CH1 RK0
7395 14:44:25.017651 [ModeRegInit_LP4] CH1 RK1
7396 14:44:25.021583 match AC timing 5
7397 14:44:25.024709 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 14:44:25.027673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 14:44:25.035808 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 14:44:25.037659 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 14:44:25.044251 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 14:44:25.044335 [MiockJmeterHQA]
7403 14:44:25.044401
7404 14:44:25.048025 [DramcMiockJmeter] u1RxGatingPI = 0
7405 14:44:25.048110 0 : 4368, 4140
7406 14:44:25.051114 4 : 4252, 4027
7407 14:44:25.051198 8 : 4252, 4027
7408 14:44:25.054149 12 : 4255, 4029
7409 14:44:25.054236 16 : 4252, 4027
7410 14:44:25.058235 20 : 4363, 4137
7411 14:44:25.058318 24 : 4368, 4140
7412 14:44:25.061706 28 : 4255, 4026
7413 14:44:25.061785 32 : 4257, 4029
7414 14:44:25.061851 36 : 4252, 4027
7415 14:44:25.065042 40 : 4252, 4027
7416 14:44:25.065119 44 : 4254, 4029
7417 14:44:25.068427 48 : 4258, 4029
7418 14:44:25.068503 52 : 4252, 4027
7419 14:44:25.071054 56 : 4257, 4030
7420 14:44:25.071131 60 : 4252, 4027
7421 14:44:25.071195 64 : 4252, 4027
7422 14:44:25.074133 68 : 4252, 4027
7423 14:44:25.074209 72 : 4253, 4027
7424 14:44:25.077960 76 : 4366, 4140
7425 14:44:25.078040 80 : 4363, 4137
7426 14:44:25.080743 84 : 4365, 4140
7427 14:44:25.080817 88 : 4255, 4029
7428 14:44:25.084754 92 : 4360, 4138
7429 14:44:25.084826 96 : 4250, 3314
7430 14:44:25.084918 100 : 4253, 0
7431 14:44:25.087703 104 : 4250, 0
7432 14:44:25.087780 108 : 4250, 0
7433 14:44:25.091637 112 : 4250, 0
7434 14:44:25.091710 116 : 4252, 0
7435 14:44:25.091778 120 : 4360, 0
7436 14:44:25.094166 124 : 4250, 0
7437 14:44:25.094238 128 : 4250, 0
7438 14:44:25.094302 132 : 4363, 0
7439 14:44:25.098115 136 : 4250, 0
7440 14:44:25.098187 140 : 4255, 0
7441 14:44:25.101180 144 : 4252, 0
7442 14:44:25.101261 148 : 4250, 0
7443 14:44:25.101335 152 : 4257, 0
7444 14:44:25.104451 156 : 4253, 0
7445 14:44:25.104534 160 : 4365, 0
7446 14:44:25.108121 164 : 4250, 0
7447 14:44:25.108196 168 : 4363, 0
7448 14:44:25.108267 172 : 4252, 0
7449 14:44:25.111587 176 : 4250, 0
7450 14:44:25.111659 180 : 4255, 0
7451 14:44:25.114526 184 : 4250, 0
7452 14:44:25.114610 188 : 4250, 0
7453 14:44:25.114674 192 : 4250, 0
7454 14:44:25.117580 196 : 4249, 0
7455 14:44:25.117655 200 : 4252, 0
7456 14:44:25.117718 204 : 4258, 0
7457 14:44:25.121064 208 : 4252, 0
7458 14:44:25.121136 212 : 4250, 46
7459 14:44:25.124146 216 : 4255, 3064
7460 14:44:25.124220 220 : 4361, 4137
7461 14:44:25.127568 224 : 4250, 4026
7462 14:44:25.127646 228 : 4252, 4029
7463 14:44:25.131123 232 : 4252, 4030
7464 14:44:25.131199 236 : 4250, 4027
7465 14:44:25.134332 240 : 4361, 4137
7466 14:44:25.134410 244 : 4250, 4027
7467 14:44:25.134474 248 : 4249, 4027
7468 14:44:25.137905 252 : 4257, 4034
7469 14:44:25.137982 256 : 4253, 4029
7470 14:44:25.140894 260 : 4361, 4137
7471 14:44:25.140968 264 : 4361, 4138
7472 14:44:25.144563 268 : 4250, 4027
7473 14:44:25.144636 272 : 4250, 4027
7474 14:44:25.147563 276 : 4250, 4027
7475 14:44:25.147640 280 : 4249, 4027
7476 14:44:25.150945 284 : 4250, 4026
7477 14:44:25.151017 288 : 4247, 4025
7478 14:44:25.154221 292 : 4252, 4030
7479 14:44:25.154302 296 : 4250, 4027
7480 14:44:25.154369 300 : 4255, 4030
7481 14:44:25.157936 304 : 4365, 4140
7482 14:44:25.158013 308 : 4255, 4029
7483 14:44:25.161381 312 : 4250, 4027
7484 14:44:25.161459 316 : 4366, 4140
7485 14:44:25.164426 320 : 4250, 4027
7486 14:44:25.164509 324 : 4250, 4027
7487 14:44:25.167785 328 : 4363, 4137
7488 14:44:25.167859 332 : 4361, 3590
7489 14:44:25.170976 336 : 4249, 334
7490 14:44:25.171053
7491 14:44:25.171117 MIOCK jitter meter ch=0
7492 14:44:25.171187
7493 14:44:25.174117 1T = (336-100) = 236 dly cells
7494 14:44:25.181497 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7495 14:44:25.181585 ==
7496 14:44:25.184369 Dram Type= 6, Freq= 0, CH_0, rank 0
7497 14:44:25.187742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 14:44:25.187824 ==
7499 14:44:25.194666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 14:44:25.197637 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 14:44:25.200818 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 14:44:25.207958 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 14:44:25.217506 [CA 0] Center 44 (14~75) winsize 62
7504 14:44:25.221542 [CA 1] Center 44 (13~75) winsize 63
7505 14:44:25.224312 [CA 2] Center 40 (11~69) winsize 59
7506 14:44:25.228378 [CA 3] Center 39 (10~69) winsize 60
7507 14:44:25.230981 [CA 4] Center 38 (8~68) winsize 61
7508 14:44:25.234208 [CA 5] Center 37 (7~67) winsize 61
7509 14:44:25.234289
7510 14:44:25.237966 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 14:44:25.238045
7512 14:44:25.241379 [CATrainingPosCal] consider 1 rank data
7513 14:44:25.244689 u2DelayCellTimex100 = 275/100 ps
7514 14:44:25.248132 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7515 14:44:25.254373 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7516 14:44:25.258031 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7517 14:44:25.261379 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7518 14:44:25.264595 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7519 14:44:25.267690 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7520 14:44:25.267776
7521 14:44:25.271012 CA PerBit enable=1, Macro0, CA PI delay=37
7522 14:44:25.271099
7523 14:44:25.274552 [CBTSetCACLKResult] CA Dly = 37
7524 14:44:25.274661 CS Dly: 11 (0~42)
7525 14:44:25.281937 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 14:44:25.285253 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 14:44:25.285332 ==
7528 14:44:25.288060 Dram Type= 6, Freq= 0, CH_0, rank 1
7529 14:44:25.291129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 14:44:25.291205 ==
7531 14:44:25.297960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 14:44:25.301379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 14:44:25.305046 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 14:44:25.311446 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 14:44:25.321444 [CA 0] Center 43 (13~74) winsize 62
7536 14:44:25.324917 [CA 1] Center 43 (13~74) winsize 62
7537 14:44:25.327901 [CA 2] Center 39 (10~69) winsize 60
7538 14:44:25.331234 [CA 3] Center 38 (9~68) winsize 60
7539 14:44:25.334718 [CA 4] Center 37 (7~67) winsize 61
7540 14:44:25.338018 [CA 5] Center 36 (6~67) winsize 62
7541 14:44:25.338094
7542 14:44:25.341478 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 14:44:25.341554
7544 14:44:25.344997 [CATrainingPosCal] consider 2 rank data
7545 14:44:25.347981 u2DelayCellTimex100 = 275/100 ps
7546 14:44:25.351739 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7547 14:44:25.359105 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7548 14:44:25.361317 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7549 14:44:25.364849 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7550 14:44:25.368009 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7551 14:44:25.371622 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7552 14:44:25.371696
7553 14:44:25.375133 CA PerBit enable=1, Macro0, CA PI delay=37
7554 14:44:25.375225
7555 14:44:25.378399 [CBTSetCACLKResult] CA Dly = 37
7556 14:44:25.381454 CS Dly: 12 (0~44)
7557 14:44:25.384883 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 14:44:25.388821 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 14:44:25.388906
7560 14:44:25.391319 ----->DramcWriteLeveling(PI) begin...
7561 14:44:25.391434 ==
7562 14:44:25.395206 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 14:44:25.398732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 14:44:25.402591 ==
7565 14:44:25.402730 Write leveling (Byte 0): 31 => 31
7566 14:44:25.405105 Write leveling (Byte 1): 28 => 28
7567 14:44:25.408395 DramcWriteLeveling(PI) end<-----
7568 14:44:25.408498
7569 14:44:25.408580 ==
7570 14:44:25.411553 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 14:44:25.418624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 14:44:25.418711 ==
7573 14:44:25.418796 [Gating] SW mode calibration
7574 14:44:25.428135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7575 14:44:25.432013 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7576 14:44:25.435630 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 14:44:25.442015 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 14:44:25.445536 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 14:44:25.448439 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 14:44:25.455243 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7581 14:44:25.458314 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7582 14:44:25.461459 1 4 24 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
7583 14:44:25.468558 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 14:44:25.471514 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 14:44:25.475315 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 14:44:25.481731 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 14:44:25.485021 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 14:44:25.488327 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7589 14:44:25.495042 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
7590 14:44:25.498359 1 5 24 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
7591 14:44:25.502551 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 14:44:25.508699 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 14:44:25.511775 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 14:44:25.515027 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 14:44:25.521697 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 14:44:25.525516 1 6 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7597 14:44:25.528325 1 6 20 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
7598 14:44:25.532001 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7599 14:44:25.538193 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 14:44:25.542005 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 14:44:25.544766 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 14:44:25.551471 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 14:44:25.555048 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 14:44:25.558322 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7605 14:44:25.566153 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7606 14:44:25.568798 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7607 14:44:25.571849 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 14:44:25.578584 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 14:44:25.581899 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 14:44:25.585491 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 14:44:25.592352 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 14:44:25.594967 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 14:44:25.598790 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 14:44:25.601711 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 14:44:25.608758 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 14:44:25.612094 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 14:44:25.615426 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 14:44:25.622258 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 14:44:25.625629 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 14:44:25.628870 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7621 14:44:25.635809 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 14:44:25.636380 Total UI for P1: 0, mck2ui 16
7623 14:44:25.642284 best dqsien dly found for B0: ( 1, 9, 14)
7624 14:44:25.645596 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 14:44:25.649126 Total UI for P1: 0, mck2ui 16
7626 14:44:25.652702 best dqsien dly found for B1: ( 1, 9, 20)
7627 14:44:25.656227 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7628 14:44:25.659214 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7629 14:44:25.659810
7630 14:44:25.662124 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7631 14:44:25.665960 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7632 14:44:25.668790 [Gating] SW calibration Done
7633 14:44:25.669260 ==
7634 14:44:25.672316 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 14:44:25.675722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 14:44:25.679482 ==
7637 14:44:25.680075 RX Vref Scan: 0
7638 14:44:25.680514
7639 14:44:25.682021 RX Vref 0 -> 0, step: 1
7640 14:44:25.682532
7641 14:44:25.683004 RX Delay 0 -> 252, step: 8
7642 14:44:25.688742 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7643 14:44:25.692683 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7644 14:44:25.695912 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7645 14:44:25.699137 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7646 14:44:25.702789 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7647 14:44:25.709504 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7648 14:44:25.712554 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7649 14:44:25.715702 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7650 14:44:25.719002 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7651 14:44:25.722106 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7652 14:44:25.729283 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7653 14:44:25.732506 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7654 14:44:25.735706 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7655 14:44:25.738525 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7656 14:44:25.741998 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7657 14:44:25.749262 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7658 14:44:25.749345 ==
7659 14:44:25.751998 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 14:44:25.755301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 14:44:25.755384 ==
7662 14:44:25.755450 DQS Delay:
7663 14:44:25.758474 DQS0 = 0, DQS1 = 0
7664 14:44:25.758557 DQM Delay:
7665 14:44:25.761840 DQM0 = 132, DQM1 = 125
7666 14:44:25.761923 DQ Delay:
7667 14:44:25.765317 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7668 14:44:25.768505 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7669 14:44:25.771960 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7670 14:44:25.775761 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7671 14:44:25.775844
7672 14:44:25.775909
7673 14:44:25.778724 ==
7674 14:44:25.781747 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 14:44:25.785446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 14:44:25.785529 ==
7677 14:44:25.785594
7678 14:44:25.785656
7679 14:44:25.788358 TX Vref Scan disable
7680 14:44:25.788440 == TX Byte 0 ==
7681 14:44:25.792282 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7682 14:44:25.798568 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7683 14:44:25.798651 == TX Byte 1 ==
7684 14:44:25.801668 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7685 14:44:25.808583 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7686 14:44:25.808669 ==
7687 14:44:25.811765 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 14:44:25.815365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 14:44:25.815448 ==
7690 14:44:25.829787
7691 14:44:25.832883 TX Vref early break, caculate TX vref
7692 14:44:25.836359 TX Vref=16, minBit 0, minWin=21, winSum=359
7693 14:44:25.840094 TX Vref=18, minBit 4, minWin=21, winSum=369
7694 14:44:25.842984 TX Vref=20, minBit 1, minWin=22, winSum=379
7695 14:44:25.846758 TX Vref=22, minBit 0, minWin=23, winSum=388
7696 14:44:25.849669 TX Vref=24, minBit 1, minWin=22, winSum=402
7697 14:44:25.853467 TX Vref=26, minBit 1, minWin=24, winSum=412
7698 14:44:25.860233 TX Vref=28, minBit 1, minWin=24, winSum=419
7699 14:44:25.863741 TX Vref=30, minBit 4, minWin=24, winSum=417
7700 14:44:25.866762 TX Vref=32, minBit 4, minWin=23, winSum=412
7701 14:44:25.870201 TX Vref=34, minBit 0, minWin=23, winSum=399
7702 14:44:25.873173 TX Vref=36, minBit 4, minWin=22, winSum=389
7703 14:44:25.879774 [TxChooseVref] Worse bit 1, Min win 24, Win sum 419, Final Vref 28
7704 14:44:25.879857
7705 14:44:25.883700 Final TX Range 0 Vref 28
7706 14:44:25.883783
7707 14:44:25.883848 ==
7708 14:44:25.886658 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 14:44:25.890108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 14:44:25.890191 ==
7711 14:44:25.890256
7712 14:44:25.890317
7713 14:44:25.893262 TX Vref Scan disable
7714 14:44:25.899819 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7715 14:44:25.899901 == TX Byte 0 ==
7716 14:44:25.903063 u2DelayCellOfst[0]=17 cells (5 PI)
7717 14:44:25.906803 u2DelayCellOfst[1]=24 cells (7 PI)
7718 14:44:25.910086 u2DelayCellOfst[2]=14 cells (4 PI)
7719 14:44:25.913009 u2DelayCellOfst[3]=17 cells (5 PI)
7720 14:44:25.916671 u2DelayCellOfst[4]=14 cells (4 PI)
7721 14:44:25.920008 u2DelayCellOfst[5]=0 cells (0 PI)
7722 14:44:25.923056 u2DelayCellOfst[6]=24 cells (7 PI)
7723 14:44:25.926293 u2DelayCellOfst[7]=24 cells (7 PI)
7724 14:44:25.929906 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7725 14:44:25.933347 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7726 14:44:25.936811 == TX Byte 1 ==
7727 14:44:25.936893 u2DelayCellOfst[8]=3 cells (1 PI)
7728 14:44:25.940501 u2DelayCellOfst[9]=0 cells (0 PI)
7729 14:44:25.943405 u2DelayCellOfst[10]=7 cells (2 PI)
7730 14:44:25.946328 u2DelayCellOfst[11]=3 cells (1 PI)
7731 14:44:25.949660 u2DelayCellOfst[12]=14 cells (4 PI)
7732 14:44:25.952933 u2DelayCellOfst[13]=14 cells (4 PI)
7733 14:44:25.956262 u2DelayCellOfst[14]=17 cells (5 PI)
7734 14:44:25.959977 u2DelayCellOfst[15]=10 cells (3 PI)
7735 14:44:25.962962 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7736 14:44:25.969815 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7737 14:44:25.969897 DramC Write-DBI on
7738 14:44:25.969963 ==
7739 14:44:25.973286 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 14:44:25.976663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 14:44:25.979696 ==
7742 14:44:25.979779
7743 14:44:25.979843
7744 14:44:25.979904 TX Vref Scan disable
7745 14:44:25.983323 == TX Byte 0 ==
7746 14:44:25.986862 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7747 14:44:25.989839 == TX Byte 1 ==
7748 14:44:25.993980 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7749 14:44:25.996207 DramC Write-DBI off
7750 14:44:25.996288
7751 14:44:25.996354 [DATLAT]
7752 14:44:25.996415 Freq=1600, CH0 RK0
7753 14:44:25.996475
7754 14:44:25.999827 DATLAT Default: 0xf
7755 14:44:25.999909 0, 0xFFFF, sum = 0
7756 14:44:26.003368 1, 0xFFFF, sum = 0
7757 14:44:26.003458 2, 0xFFFF, sum = 0
7758 14:44:26.006242 3, 0xFFFF, sum = 0
7759 14:44:26.009546 4, 0xFFFF, sum = 0
7760 14:44:26.009630 5, 0xFFFF, sum = 0
7761 14:44:26.013491 6, 0xFFFF, sum = 0
7762 14:44:26.013575 7, 0xFFFF, sum = 0
7763 14:44:26.016500 8, 0xFFFF, sum = 0
7764 14:44:26.016583 9, 0xFFFF, sum = 0
7765 14:44:26.020229 10, 0xFFFF, sum = 0
7766 14:44:26.020312 11, 0xFFFF, sum = 0
7767 14:44:26.023561 12, 0xFFFF, sum = 0
7768 14:44:26.023644 13, 0xFFFF, sum = 0
7769 14:44:26.026621 14, 0x0, sum = 1
7770 14:44:26.026705 15, 0x0, sum = 2
7771 14:44:26.030212 16, 0x0, sum = 3
7772 14:44:26.030296 17, 0x0, sum = 4
7773 14:44:26.033365 best_step = 15
7774 14:44:26.033448
7775 14:44:26.033514 ==
7776 14:44:26.037341 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 14:44:26.039679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 14:44:26.039762 ==
7779 14:44:26.039828 RX Vref Scan: 1
7780 14:44:26.039889
7781 14:44:26.043430 Set Vref Range= 24 -> 127
7782 14:44:26.043512
7783 14:44:26.046242 RX Vref 24 -> 127, step: 1
7784 14:44:26.046325
7785 14:44:26.050346 RX Delay 11 -> 252, step: 4
7786 14:44:26.050428
7787 14:44:26.053375 Set Vref, RX VrefLevel [Byte0]: 24
7788 14:44:26.056496 [Byte1]: 24
7789 14:44:26.056578
7790 14:44:26.060094 Set Vref, RX VrefLevel [Byte0]: 25
7791 14:44:26.062971 [Byte1]: 25
7792 14:44:26.063065
7793 14:44:26.066609 Set Vref, RX VrefLevel [Byte0]: 26
7794 14:44:26.070069 [Byte1]: 26
7795 14:44:26.073252
7796 14:44:26.073333 Set Vref, RX VrefLevel [Byte0]: 27
7797 14:44:26.076753 [Byte1]: 27
7798 14:44:26.081606
7799 14:44:26.081688 Set Vref, RX VrefLevel [Byte0]: 28
7800 14:44:26.084596 [Byte1]: 28
7801 14:44:26.088942
7802 14:44:26.089064 Set Vref, RX VrefLevel [Byte0]: 29
7803 14:44:26.092312 [Byte1]: 29
7804 14:44:26.097507
7805 14:44:26.097589 Set Vref, RX VrefLevel [Byte0]: 30
7806 14:44:26.100866 [Byte1]: 30
7807 14:44:26.104117
7808 14:44:26.104200 Set Vref, RX VrefLevel [Byte0]: 31
7809 14:44:26.107338 [Byte1]: 31
7810 14:44:26.111385
7811 14:44:26.111467 Set Vref, RX VrefLevel [Byte0]: 32
7812 14:44:26.114961 [Byte1]: 32
7813 14:44:26.119269
7814 14:44:26.119351 Set Vref, RX VrefLevel [Byte0]: 33
7815 14:44:26.122663 [Byte1]: 33
7816 14:44:26.126862
7817 14:44:26.126943 Set Vref, RX VrefLevel [Byte0]: 34
7818 14:44:26.130231 [Byte1]: 34
7819 14:44:26.134201
7820 14:44:26.134283 Set Vref, RX VrefLevel [Byte0]: 35
7821 14:44:26.138076 [Byte1]: 35
7822 14:44:26.141824
7823 14:44:26.141906 Set Vref, RX VrefLevel [Byte0]: 36
7824 14:44:26.145286 [Byte1]: 36
7825 14:44:26.149916
7826 14:44:26.150003 Set Vref, RX VrefLevel [Byte0]: 37
7827 14:44:26.152966 [Byte1]: 37
7828 14:44:26.157020
7829 14:44:26.157104 Set Vref, RX VrefLevel [Byte0]: 38
7830 14:44:26.160759 [Byte1]: 38
7831 14:44:26.164832
7832 14:44:26.164914 Set Vref, RX VrefLevel [Byte0]: 39
7833 14:44:26.168677 [Byte1]: 39
7834 14:44:26.172270
7835 14:44:26.172353 Set Vref, RX VrefLevel [Byte0]: 40
7836 14:44:26.176093 [Byte1]: 40
7837 14:44:26.180517
7838 14:44:26.180600 Set Vref, RX VrefLevel [Byte0]: 41
7839 14:44:26.183579 [Byte1]: 41
7840 14:44:26.187882
7841 14:44:26.187964 Set Vref, RX VrefLevel [Byte0]: 42
7842 14:44:26.191001 [Byte1]: 42
7843 14:44:26.195780
7844 14:44:26.195861 Set Vref, RX VrefLevel [Byte0]: 43
7845 14:44:26.198663 [Byte1]: 43
7846 14:44:26.202930
7847 14:44:26.203012 Set Vref, RX VrefLevel [Byte0]: 44
7848 14:44:26.206569 [Byte1]: 44
7849 14:44:26.210679
7850 14:44:26.210762 Set Vref, RX VrefLevel [Byte0]: 45
7851 14:44:26.213888 [Byte1]: 45
7852 14:44:26.218232
7853 14:44:26.218314 Set Vref, RX VrefLevel [Byte0]: 46
7854 14:44:26.221594 [Byte1]: 46
7855 14:44:26.226306
7856 14:44:26.226388 Set Vref, RX VrefLevel [Byte0]: 47
7857 14:44:26.229243 [Byte1]: 47
7858 14:44:26.233021
7859 14:44:26.233104 Set Vref, RX VrefLevel [Byte0]: 48
7860 14:44:26.237005 [Byte1]: 48
7861 14:44:26.240950
7862 14:44:26.241037 Set Vref, RX VrefLevel [Byte0]: 49
7863 14:44:26.244747 [Byte1]: 49
7864 14:44:26.249305
7865 14:44:26.249387 Set Vref, RX VrefLevel [Byte0]: 50
7866 14:44:26.251954 [Byte1]: 50
7867 14:44:26.256137
7868 14:44:26.256219 Set Vref, RX VrefLevel [Byte0]: 51
7869 14:44:26.260082 [Byte1]: 51
7870 14:44:26.263567
7871 14:44:26.263649 Set Vref, RX VrefLevel [Byte0]: 52
7872 14:44:26.267505 [Byte1]: 52
7873 14:44:26.271221
7874 14:44:26.271315 Set Vref, RX VrefLevel [Byte0]: 53
7875 14:44:26.275114 [Byte1]: 53
7876 14:44:26.279438
7877 14:44:26.279520 Set Vref, RX VrefLevel [Byte0]: 54
7878 14:44:26.282443 [Byte1]: 54
7879 14:44:26.286734
7880 14:44:26.286815 Set Vref, RX VrefLevel [Byte0]: 55
7881 14:44:26.289952 [Byte1]: 55
7882 14:44:26.294284
7883 14:44:26.294366 Set Vref, RX VrefLevel [Byte0]: 56
7884 14:44:26.297530 [Byte1]: 56
7885 14:44:26.301871
7886 14:44:26.301952 Set Vref, RX VrefLevel [Byte0]: 57
7887 14:44:26.305113 [Byte1]: 57
7888 14:44:26.309357
7889 14:44:26.309439 Set Vref, RX VrefLevel [Byte0]: 58
7890 14:44:26.312852 [Byte1]: 58
7891 14:44:26.317009
7892 14:44:26.317091 Set Vref, RX VrefLevel [Byte0]: 59
7893 14:44:26.320310 [Byte1]: 59
7894 14:44:26.324859
7895 14:44:26.324941 Set Vref, RX VrefLevel [Byte0]: 60
7896 14:44:26.327831 [Byte1]: 60
7897 14:44:26.332809
7898 14:44:26.332891 Set Vref, RX VrefLevel [Byte0]: 61
7899 14:44:26.335574 [Byte1]: 61
7900 14:44:26.339793
7901 14:44:26.339875 Set Vref, RX VrefLevel [Byte0]: 62
7902 14:44:26.343440 [Byte1]: 62
7903 14:44:26.347993
7904 14:44:26.348076 Set Vref, RX VrefLevel [Byte0]: 63
7905 14:44:26.351873 [Byte1]: 63
7906 14:44:26.355922
7907 14:44:26.356004 Set Vref, RX VrefLevel [Byte0]: 64
7908 14:44:26.358285 [Byte1]: 64
7909 14:44:26.363767
7910 14:44:26.363850 Set Vref, RX VrefLevel [Byte0]: 65
7911 14:44:26.366235 [Byte1]: 65
7912 14:44:26.370914
7913 14:44:26.370996 Set Vref, RX VrefLevel [Byte0]: 66
7914 14:44:26.373739 [Byte1]: 66
7915 14:44:26.377950
7916 14:44:26.378031 Set Vref, RX VrefLevel [Byte0]: 67
7917 14:44:26.381205 [Byte1]: 67
7918 14:44:26.385908
7919 14:44:26.385990 Set Vref, RX VrefLevel [Byte0]: 68
7920 14:44:26.388670 [Byte1]: 68
7921 14:44:26.393574
7922 14:44:26.393656 Set Vref, RX VrefLevel [Byte0]: 69
7923 14:44:26.396326 [Byte1]: 69
7924 14:44:26.401098
7925 14:44:26.401180 Set Vref, RX VrefLevel [Byte0]: 70
7926 14:44:26.403889 [Byte1]: 70
7927 14:44:26.408765
7928 14:44:26.408847 Set Vref, RX VrefLevel [Byte0]: 71
7929 14:44:26.412902 [Byte1]: 71
7930 14:44:26.415866
7931 14:44:26.415948 Set Vref, RX VrefLevel [Byte0]: 72
7932 14:44:26.419401 [Byte1]: 72
7933 14:44:26.424463
7934 14:44:26.424545 Set Vref, RX VrefLevel [Byte0]: 73
7935 14:44:26.426888 [Byte1]: 73
7936 14:44:26.431660
7937 14:44:26.431741 Set Vref, RX VrefLevel [Byte0]: 74
7938 14:44:26.434595 [Byte1]: 74
7939 14:44:26.439234
7940 14:44:26.439316 Set Vref, RX VrefLevel [Byte0]: 75
7941 14:44:26.442110 [Byte1]: 75
7942 14:44:26.446753
7943 14:44:26.446834 Final RX Vref Byte 0 = 62 to rank0
7944 14:44:26.449991 Final RX Vref Byte 1 = 63 to rank0
7945 14:44:26.453009 Final RX Vref Byte 0 = 62 to rank1
7946 14:44:26.456614 Final RX Vref Byte 1 = 63 to rank1==
7947 14:44:26.459784 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 14:44:26.466547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 14:44:26.466630 ==
7950 14:44:26.466696 DQS Delay:
7951 14:44:26.466758 DQS0 = 0, DQS1 = 0
7952 14:44:26.470337 DQM Delay:
7953 14:44:26.470419 DQM0 = 129, DQM1 = 122
7954 14:44:26.473928 DQ Delay:
7955 14:44:26.477181 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7956 14:44:26.480606 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7957 14:44:26.483259 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7958 14:44:26.486628 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7959 14:44:26.486711
7960 14:44:26.486776
7961 14:44:26.486835
7962 14:44:26.489721 [DramC_TX_OE_Calibration] TA2
7963 14:44:26.493583 Original DQ_B0 (3 6) =30, OEN = 27
7964 14:44:26.496745 Original DQ_B1 (3 6) =30, OEN = 27
7965 14:44:26.500232 24, 0x0, End_B0=24 End_B1=24
7966 14:44:26.500316 25, 0x0, End_B0=25 End_B1=25
7967 14:44:26.503171 26, 0x0, End_B0=26 End_B1=26
7968 14:44:26.507374 27, 0x0, End_B0=27 End_B1=27
7969 14:44:26.509521 28, 0x0, End_B0=28 End_B1=28
7970 14:44:26.509605 29, 0x0, End_B0=29 End_B1=29
7971 14:44:26.513475 30, 0x0, End_B0=30 End_B1=30
7972 14:44:26.516372 31, 0x4141, End_B0=30 End_B1=30
7973 14:44:26.520083 Byte0 end_step=30 best_step=27
7974 14:44:26.522972 Byte1 end_step=30 best_step=27
7975 14:44:26.526535 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 14:44:26.526617 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 14:44:26.526682
7978 14:44:26.530268
7979 14:44:26.536520 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7980 14:44:26.540250 CH0 RK0: MR19=303, MR18=1408
7981 14:44:26.546815 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
7982 14:44:26.546898
7983 14:44:26.549824 ----->DramcWriteLeveling(PI) begin...
7984 14:44:26.549908 ==
7985 14:44:26.553220 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 14:44:26.556430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 14:44:26.556512 ==
7988 14:44:26.559899 Write leveling (Byte 0): 33 => 33
7989 14:44:26.563481 Write leveling (Byte 1): 25 => 25
7990 14:44:26.566354 DramcWriteLeveling(PI) end<-----
7991 14:44:26.566436
7992 14:44:26.566501 ==
7993 14:44:26.569573 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 14:44:26.573137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 14:44:26.573220 ==
7996 14:44:26.576573 [Gating] SW mode calibration
7997 14:44:26.584324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 14:44:26.589959 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 14:44:26.593896 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 14:44:26.596391 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 14:44:26.603026 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 14:44:26.606561 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8003 14:44:26.610281 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8004 14:44:26.616694 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
8005 14:44:26.619879 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 14:44:26.623226 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 14:44:26.626572 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 14:44:26.633523 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 14:44:26.636531 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
8010 14:44:26.640194 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
8011 14:44:26.646671 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8012 14:44:26.650171 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8013 14:44:26.653767 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8014 14:44:26.659880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 14:44:26.664078 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 14:44:26.667186 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 14:44:26.673167 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8018 14:44:26.676620 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8019 14:44:26.679651 1 6 16 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
8020 14:44:26.686382 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8021 14:44:26.690100 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 14:44:26.693373 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 14:44:26.700159 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 14:44:26.703320 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 14:44:26.706548 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 14:44:26.710033 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 14:44:26.716671 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 14:44:26.719922 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 14:44:26.723503 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8030 14:44:26.730450 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 14:44:26.733651 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 14:44:26.736626 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 14:44:26.743259 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 14:44:26.746665 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 14:44:26.751008 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 14:44:26.757103 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 14:44:26.760347 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 14:44:26.763508 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 14:44:26.770222 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 14:44:26.773310 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 14:44:26.777185 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 14:44:26.783642 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 14:44:26.786808 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8044 14:44:26.790190 Total UI for P1: 0, mck2ui 16
8045 14:44:26.793487 best dqsien dly found for B0: ( 1, 9, 10)
8046 14:44:26.796815 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 14:44:26.800379 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 14:44:26.803321 Total UI for P1: 0, mck2ui 16
8049 14:44:26.806667 best dqsien dly found for B1: ( 1, 9, 18)
8050 14:44:26.810533 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8051 14:44:26.813555 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8052 14:44:26.816807
8053 14:44:26.820441 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8054 14:44:26.823708 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8055 14:44:26.826881 [Gating] SW calibration Done
8056 14:44:26.826964 ==
8057 14:44:26.830184 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 14:44:26.833209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 14:44:26.833293 ==
8060 14:44:26.833357 RX Vref Scan: 0
8061 14:44:26.836967
8062 14:44:26.837084 RX Vref 0 -> 0, step: 1
8063 14:44:26.837150
8064 14:44:26.840084 RX Delay 0 -> 252, step: 8
8065 14:44:26.843422 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8066 14:44:26.847143 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8067 14:44:26.854207 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8068 14:44:26.856918 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8069 14:44:26.860482 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8070 14:44:26.863767 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8071 14:44:26.867208 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8072 14:44:26.870180 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8073 14:44:26.876993 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8074 14:44:26.880238 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8075 14:44:26.883582 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8076 14:44:26.887256 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8077 14:44:26.893579 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8078 14:44:26.897468 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8079 14:44:26.900703 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8080 14:44:26.903856 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8081 14:44:26.903983 ==
8082 14:44:26.906921 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 14:44:26.910107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 14:44:26.913715 ==
8085 14:44:26.913798 DQS Delay:
8086 14:44:26.913862 DQS0 = 0, DQS1 = 0
8087 14:44:26.916805 DQM Delay:
8088 14:44:26.916888 DQM0 = 130, DQM1 = 125
8089 14:44:26.919952 DQ Delay:
8090 14:44:26.923476 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8091 14:44:26.926668 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8092 14:44:26.930496 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
8093 14:44:26.933681 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8094 14:44:26.933763
8095 14:44:26.933828
8096 14:44:26.933889 ==
8097 14:44:26.936628 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 14:44:26.940563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 14:44:26.940645 ==
8100 14:44:26.940711
8101 14:44:26.943655
8102 14:44:26.943737 TX Vref Scan disable
8103 14:44:26.946887 == TX Byte 0 ==
8104 14:44:26.950290 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8105 14:44:26.953584 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8106 14:44:26.956957 == TX Byte 1 ==
8107 14:44:26.960284 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8108 14:44:26.963521 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8109 14:44:26.963603 ==
8110 14:44:26.966846 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 14:44:26.973658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 14:44:26.973754 ==
8113 14:44:26.987404
8114 14:44:26.990585 TX Vref early break, caculate TX vref
8115 14:44:26.993573 TX Vref=16, minBit 0, minWin=22, winSum=366
8116 14:44:26.996794 TX Vref=18, minBit 9, minWin=22, winSum=376
8117 14:44:27.000452 TX Vref=20, minBit 5, minWin=23, winSum=388
8118 14:44:27.003481 TX Vref=22, minBit 0, minWin=24, winSum=393
8119 14:44:27.007134 TX Vref=24, minBit 1, minWin=24, winSum=399
8120 14:44:27.014127 TX Vref=26, minBit 1, minWin=24, winSum=407
8121 14:44:27.016934 TX Vref=28, minBit 4, minWin=25, winSum=416
8122 14:44:27.021519 TX Vref=30, minBit 0, minWin=24, winSum=413
8123 14:44:27.023410 TX Vref=32, minBit 0, minWin=24, winSum=407
8124 14:44:27.027410 TX Vref=34, minBit 0, minWin=24, winSum=397
8125 14:44:27.030432 TX Vref=36, minBit 0, minWin=24, winSum=391
8126 14:44:27.036867 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
8127 14:44:27.036951
8128 14:44:27.040702 Final TX Range 0 Vref 28
8129 14:44:27.040785
8130 14:44:27.040850 ==
8131 14:44:27.043534 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 14:44:27.047000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 14:44:27.047083 ==
8134 14:44:27.047148
8135 14:44:27.047208
8136 14:44:27.050538 TX Vref Scan disable
8137 14:44:27.057319 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8138 14:44:27.057402 == TX Byte 0 ==
8139 14:44:27.060076 u2DelayCellOfst[0]=14 cells (4 PI)
8140 14:44:27.063644 u2DelayCellOfst[1]=21 cells (6 PI)
8141 14:44:27.066722 u2DelayCellOfst[2]=10 cells (3 PI)
8142 14:44:27.070707 u2DelayCellOfst[3]=10 cells (3 PI)
8143 14:44:27.073589 u2DelayCellOfst[4]=7 cells (2 PI)
8144 14:44:27.076854 u2DelayCellOfst[5]=0 cells (0 PI)
8145 14:44:27.080790 u2DelayCellOfst[6]=17 cells (5 PI)
8146 14:44:27.083588 u2DelayCellOfst[7]=17 cells (5 PI)
8147 14:44:27.087843 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8148 14:44:27.090211 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8149 14:44:27.093564 == TX Byte 1 ==
8150 14:44:27.096920 u2DelayCellOfst[8]=0 cells (0 PI)
8151 14:44:27.097010 u2DelayCellOfst[9]=0 cells (0 PI)
8152 14:44:27.100236 u2DelayCellOfst[10]=3 cells (1 PI)
8153 14:44:27.104544 u2DelayCellOfst[11]=0 cells (0 PI)
8154 14:44:27.107458 u2DelayCellOfst[12]=10 cells (3 PI)
8155 14:44:27.110075 u2DelayCellOfst[13]=10 cells (3 PI)
8156 14:44:27.113745 u2DelayCellOfst[14]=14 cells (4 PI)
8157 14:44:27.117023 u2DelayCellOfst[15]=10 cells (3 PI)
8158 14:44:27.120701 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8159 14:44:27.126842 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8160 14:44:27.126925 DramC Write-DBI on
8161 14:44:27.126990 ==
8162 14:44:27.130754 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 14:44:27.134008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 14:44:27.137223 ==
8165 14:44:27.137305
8166 14:44:27.137370
8167 14:44:27.137430 TX Vref Scan disable
8168 14:44:27.140764 == TX Byte 0 ==
8169 14:44:27.143810 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8170 14:44:27.147517 == TX Byte 1 ==
8171 14:44:27.151114 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8172 14:44:27.151197 DramC Write-DBI off
8173 14:44:27.153789
8174 14:44:27.153871 [DATLAT]
8175 14:44:27.153937 Freq=1600, CH0 RK1
8176 14:44:27.153998
8177 14:44:27.157345 DATLAT Default: 0xf
8178 14:44:27.157427 0, 0xFFFF, sum = 0
8179 14:44:27.160538 1, 0xFFFF, sum = 0
8180 14:44:27.160622 2, 0xFFFF, sum = 0
8181 14:44:27.163925 3, 0xFFFF, sum = 0
8182 14:44:27.164009 4, 0xFFFF, sum = 0
8183 14:44:27.167542 5, 0xFFFF, sum = 0
8184 14:44:27.170961 6, 0xFFFF, sum = 0
8185 14:44:27.171045 7, 0xFFFF, sum = 0
8186 14:44:27.174538 8, 0xFFFF, sum = 0
8187 14:44:27.174622 9, 0xFFFF, sum = 0
8188 14:44:27.177644 10, 0xFFFF, sum = 0
8189 14:44:27.177727 11, 0xFFFF, sum = 0
8190 14:44:27.180817 12, 0xFFFF, sum = 0
8191 14:44:27.180901 13, 0xFFFF, sum = 0
8192 14:44:27.184107 14, 0x0, sum = 1
8193 14:44:27.184190 15, 0x0, sum = 2
8194 14:44:27.187039 16, 0x0, sum = 3
8195 14:44:27.187123 17, 0x0, sum = 4
8196 14:44:27.190746 best_step = 15
8197 14:44:27.190828
8198 14:44:27.190893 ==
8199 14:44:27.194387 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 14:44:27.196933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 14:44:27.197052 ==
8202 14:44:27.197118 RX Vref Scan: 0
8203 14:44:27.197180
8204 14:44:27.201465 RX Vref 0 -> 0, step: 1
8205 14:44:27.201547
8206 14:44:27.204058 RX Delay 11 -> 252, step: 4
8207 14:44:27.208160 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8208 14:44:27.214411 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8209 14:44:27.217533 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8210 14:44:27.221567 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8211 14:44:27.224337 iDelay=191, Bit 4, Center 126 (71 ~ 182) 112
8212 14:44:27.227215 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8213 14:44:27.230689 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8214 14:44:27.237025 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8215 14:44:27.240800 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8216 14:44:27.244316 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8217 14:44:27.247229 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8218 14:44:27.251193 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8219 14:44:27.257530 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8220 14:44:27.260735 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8221 14:44:27.264406 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8222 14:44:27.267090 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8223 14:44:27.267172 ==
8224 14:44:27.270433 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 14:44:27.276970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 14:44:27.277088 ==
8227 14:44:27.277154 DQS Delay:
8228 14:44:27.281246 DQS0 = 0, DQS1 = 0
8229 14:44:27.281328 DQM Delay:
8230 14:44:27.281394 DQM0 = 127, DQM1 = 122
8231 14:44:27.284180 DQ Delay:
8232 14:44:27.287551 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8233 14:44:27.290727 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =136
8234 14:44:27.293961 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8235 14:44:27.297589 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8236 14:44:27.297671
8237 14:44:27.297736
8238 14:44:27.297797
8239 14:44:27.300806 [DramC_TX_OE_Calibration] TA2
8240 14:44:27.303655 Original DQ_B0 (3 6) =30, OEN = 27
8241 14:44:27.307737 Original DQ_B1 (3 6) =30, OEN = 27
8242 14:44:27.311293 24, 0x0, End_B0=24 End_B1=24
8243 14:44:27.311377 25, 0x0, End_B0=25 End_B1=25
8244 14:44:27.314242 26, 0x0, End_B0=26 End_B1=26
8245 14:44:27.317420 27, 0x0, End_B0=27 End_B1=27
8246 14:44:27.321244 28, 0x0, End_B0=28 End_B1=28
8247 14:44:27.324192 29, 0x0, End_B0=29 End_B1=29
8248 14:44:27.324277 30, 0x0, End_B0=30 End_B1=30
8249 14:44:27.327207 31, 0x4141, End_B0=30 End_B1=30
8250 14:44:27.330325 Byte0 end_step=30 best_step=27
8251 14:44:27.334132 Byte1 end_step=30 best_step=27
8252 14:44:27.337241 Byte0 TX OE(2T, 0.5T) = (3, 3)
8253 14:44:27.340604 Byte1 TX OE(2T, 0.5T) = (3, 3)
8254 14:44:27.340686
8255 14:44:27.340751
8256 14:44:27.347200 [DQSOSCAuto] RK1, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8257 14:44:27.350751 CH0 RK1: MR19=303, MR18=170C
8258 14:44:27.357302 CH0_RK1: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8259 14:44:27.360607 [RxdqsGatingPostProcess] freq 1600
8260 14:44:27.364052 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8261 14:44:27.367502 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 14:44:27.370520 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 14:44:27.374039 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 14:44:27.377447 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 14:44:27.380792 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 14:44:27.383767 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 14:44:27.388164 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 14:44:27.390593 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 14:44:27.394701 Pre-setting of DQS Precalculation
8270 14:44:27.397224 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8271 14:44:27.397307 ==
8272 14:44:27.401120 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 14:44:27.404080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 14:44:27.404163 ==
8275 14:44:27.410681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 14:44:27.414070 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 14:44:27.417509 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 14:44:27.425057 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 14:44:27.433429 [CA 0] Center 43 (14~72) winsize 59
8280 14:44:27.437645 [CA 1] Center 43 (14~72) winsize 59
8281 14:44:27.440289 [CA 2] Center 38 (9~67) winsize 59
8282 14:44:27.443795 [CA 3] Center 37 (8~66) winsize 59
8283 14:44:27.447223 [CA 4] Center 38 (9~68) winsize 60
8284 14:44:27.450460 [CA 5] Center 37 (8~66) winsize 59
8285 14:44:27.450542
8286 14:44:27.454072 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 14:44:27.454154
8288 14:44:27.457844 [CATrainingPosCal] consider 1 rank data
8289 14:44:27.460697 u2DelayCellTimex100 = 275/100 ps
8290 14:44:27.463775 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8291 14:44:27.466945 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8292 14:44:27.473985 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8293 14:44:27.477952 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8294 14:44:27.480990 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 14:44:27.484508 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 14:44:27.484608
8297 14:44:27.487125 CA PerBit enable=1, Macro0, CA PI delay=37
8298 14:44:27.487209
8299 14:44:27.490421 [CBTSetCACLKResult] CA Dly = 37
8300 14:44:27.490504 CS Dly: 8 (0~39)
8301 14:44:27.497955 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 14:44:27.500748 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 14:44:27.500831 ==
8304 14:44:27.503788 Dram Type= 6, Freq= 0, CH_1, rank 1
8305 14:44:27.507157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 14:44:27.507239 ==
8307 14:44:27.513631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 14:44:27.517145 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 14:44:27.520631 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 14:44:27.527642 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 14:44:27.536968 [CA 0] Center 43 (14~73) winsize 60
8312 14:44:27.540066 [CA 1] Center 43 (15~72) winsize 58
8313 14:44:27.543308 [CA 2] Center 38 (9~67) winsize 59
8314 14:44:27.547105 [CA 3] Center 37 (9~66) winsize 58
8315 14:44:27.550116 [CA 4] Center 38 (9~68) winsize 60
8316 14:44:27.553463 [CA 5] Center 37 (8~66) winsize 59
8317 14:44:27.553545
8318 14:44:27.556848 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 14:44:27.556929
8320 14:44:27.560158 [CATrainingPosCal] consider 2 rank data
8321 14:44:27.563719 u2DelayCellTimex100 = 275/100 ps
8322 14:44:27.567173 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8323 14:44:27.574267 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8324 14:44:27.577021 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8325 14:44:27.580073 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8326 14:44:27.583681 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8327 14:44:27.587255 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8328 14:44:27.587336
8329 14:44:27.590286 CA PerBit enable=1, Macro0, CA PI delay=37
8330 14:44:27.590368
8331 14:44:27.593710 [CBTSetCACLKResult] CA Dly = 37
8332 14:44:27.593794 CS Dly: 11 (0~45)
8333 14:44:27.600285 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 14:44:27.604048 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 14:44:27.604131
8336 14:44:27.607138 ----->DramcWriteLeveling(PI) begin...
8337 14:44:27.607221 ==
8338 14:44:27.610316 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 14:44:27.613456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 14:44:27.613541 ==
8341 14:44:27.617779 Write leveling (Byte 0): 24 => 24
8342 14:44:27.620248 Write leveling (Byte 1): 28 => 28
8343 14:44:27.624033 DramcWriteLeveling(PI) end<-----
8344 14:44:27.624114
8345 14:44:27.624178 ==
8346 14:44:27.626570 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 14:44:27.630376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 14:44:27.633648 ==
8349 14:44:27.633730 [Gating] SW mode calibration
8350 14:44:27.640345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8351 14:44:27.647055 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8352 14:44:27.650373 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 14:44:27.657154 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 14:44:27.660482 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 14:44:27.663823 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 14:44:27.670534 1 4 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
8357 14:44:27.673870 1 4 20 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
8358 14:44:27.676931 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 14:44:27.683650 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 14:44:27.686995 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 14:44:27.691026 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 14:44:27.697157 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 14:44:27.700687 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 14:44:27.703799 1 5 16 | B1->B0 | 2e2e 3232 | 0 0 | (1 0) (0 1)
8365 14:44:27.707991 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 14:44:27.714436 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 14:44:27.716900 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 14:44:27.720615 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 14:44:27.727510 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 14:44:27.730912 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 14:44:27.733941 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8372 14:44:27.740837 1 6 16 | B1->B0 | 3c3c 2f2f | 0 0 | (0 0) (0 0)
8373 14:44:27.743874 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 14:44:27.747524 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 14:44:27.754333 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 14:44:27.757431 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 14:44:27.760362 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 14:44:27.767251 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 14:44:27.770504 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8380 14:44:27.774091 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8381 14:44:27.780283 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8382 14:44:27.783962 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 14:44:27.787009 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 14:44:27.793876 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 14:44:27.797025 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 14:44:27.800215 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 14:44:27.803737 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 14:44:27.811025 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 14:44:27.813888 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 14:44:27.817865 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 14:44:27.823697 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 14:44:27.827587 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 14:44:27.830737 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 14:44:27.836884 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 14:44:27.840699 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 14:44:27.843558 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 14:44:27.850505 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8398 14:44:27.850589 Total UI for P1: 0, mck2ui 16
8399 14:44:27.857011 best dqsien dly found for B1: ( 1, 9, 16)
8400 14:44:27.860684 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 14:44:27.863506 Total UI for P1: 0, mck2ui 16
8402 14:44:27.866963 best dqsien dly found for B0: ( 1, 9, 18)
8403 14:44:27.870868 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
8404 14:44:27.874165 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8405 14:44:27.874248
8406 14:44:27.877114 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
8407 14:44:27.880949 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8408 14:44:27.883871 [Gating] SW calibration Done
8409 14:44:27.883953 ==
8410 14:44:27.887139 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 14:44:27.890323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 14:44:27.893882 ==
8413 14:44:27.893965 RX Vref Scan: 0
8414 14:44:27.894031
8415 14:44:27.896936 RX Vref 0 -> 0, step: 1
8416 14:44:27.897075
8417 14:44:27.897142 RX Delay 0 -> 252, step: 8
8418 14:44:27.903670 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8419 14:44:27.906973 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8420 14:44:27.910164 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8421 14:44:27.914171 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8422 14:44:27.917590 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8423 14:44:27.923521 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8424 14:44:27.927269 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8425 14:44:27.931040 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8426 14:44:27.933727 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8427 14:44:27.936870 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8428 14:44:27.943842 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8429 14:44:27.947008 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8430 14:44:27.950843 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8431 14:44:27.954186 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8432 14:44:27.957030 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8433 14:44:27.963699 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8434 14:44:27.963781 ==
8435 14:44:27.967171 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 14:44:27.971366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 14:44:27.971449 ==
8438 14:44:27.971514 DQS Delay:
8439 14:44:27.973816 DQS0 = 0, DQS1 = 0
8440 14:44:27.973898 DQM Delay:
8441 14:44:27.977512 DQM0 = 135, DQM1 = 126
8442 14:44:27.977616 DQ Delay:
8443 14:44:27.981807 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8444 14:44:27.983675 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8445 14:44:27.987037 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8446 14:44:27.990354 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8447 14:44:27.990436
8448 14:44:27.990499
8449 14:44:27.994189 ==
8450 14:44:27.994271 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 14:44:28.000859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 14:44:28.000947 ==
8453 14:44:28.001053
8454 14:44:28.001115
8455 14:44:28.004268 TX Vref Scan disable
8456 14:44:28.004349 == TX Byte 0 ==
8457 14:44:28.007747 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8458 14:44:28.013664 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8459 14:44:28.013746 == TX Byte 1 ==
8460 14:44:28.017135 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8461 14:44:28.023660 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8462 14:44:28.023744 ==
8463 14:44:28.027432 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 14:44:28.031085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 14:44:28.031168 ==
8466 14:44:28.044665
8467 14:44:28.047797 TX Vref early break, caculate TX vref
8468 14:44:28.051265 TX Vref=16, minBit 8, minWin=21, winSum=367
8469 14:44:28.055110 TX Vref=18, minBit 8, minWin=21, winSum=372
8470 14:44:28.058034 TX Vref=20, minBit 5, minWin=23, winSum=385
8471 14:44:28.061605 TX Vref=22, minBit 8, minWin=22, winSum=394
8472 14:44:28.064729 TX Vref=24, minBit 8, minWin=23, winSum=404
8473 14:44:28.071879 TX Vref=26, minBit 5, minWin=24, winSum=412
8474 14:44:28.074237 TX Vref=28, minBit 5, minWin=25, winSum=416
8475 14:44:28.078339 TX Vref=30, minBit 8, minWin=25, winSum=417
8476 14:44:28.080927 TX Vref=32, minBit 1, minWin=25, winSum=413
8477 14:44:28.084371 TX Vref=34, minBit 11, minWin=23, winSum=397
8478 14:44:28.088097 TX Vref=36, minBit 8, minWin=23, winSum=388
8479 14:44:28.094541 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 30
8480 14:44:28.094624
8481 14:44:28.098008 Final TX Range 0 Vref 30
8482 14:44:28.098091
8483 14:44:28.098156 ==
8484 14:44:28.101146 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 14:44:28.104429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 14:44:28.104511 ==
8487 14:44:28.104577
8488 14:44:28.104637
8489 14:44:28.107977 TX Vref Scan disable
8490 14:44:28.114429 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8491 14:44:28.114512 == TX Byte 0 ==
8492 14:44:28.118010 u2DelayCellOfst[0]=17 cells (5 PI)
8493 14:44:28.120945 u2DelayCellOfst[1]=14 cells (4 PI)
8494 14:44:28.124513 u2DelayCellOfst[2]=0 cells (0 PI)
8495 14:44:28.128169 u2DelayCellOfst[3]=7 cells (2 PI)
8496 14:44:28.131137 u2DelayCellOfst[4]=7 cells (2 PI)
8497 14:44:28.134847 u2DelayCellOfst[5]=17 cells (5 PI)
8498 14:44:28.138241 u2DelayCellOfst[6]=17 cells (5 PI)
8499 14:44:28.141902 u2DelayCellOfst[7]=7 cells (2 PI)
8500 14:44:28.144409 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8501 14:44:28.147686 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8502 14:44:28.151054 == TX Byte 1 ==
8503 14:44:28.151136 u2DelayCellOfst[8]=0 cells (0 PI)
8504 14:44:28.155293 u2DelayCellOfst[9]=7 cells (2 PI)
8505 14:44:28.158111 u2DelayCellOfst[10]=10 cells (3 PI)
8506 14:44:28.161525 u2DelayCellOfst[11]=7 cells (2 PI)
8507 14:44:28.164366 u2DelayCellOfst[12]=14 cells (4 PI)
8508 14:44:28.168436 u2DelayCellOfst[13]=17 cells (5 PI)
8509 14:44:28.171529 u2DelayCellOfst[14]=17 cells (5 PI)
8510 14:44:28.175318 u2DelayCellOfst[15]=17 cells (5 PI)
8511 14:44:28.178240 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8512 14:44:28.185211 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8513 14:44:28.185291 DramC Write-DBI on
8514 14:44:28.185357 ==
8515 14:44:28.188041 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 14:44:28.191357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 14:44:28.191439 ==
8518 14:44:28.195145
8519 14:44:28.195220
8520 14:44:28.195282 TX Vref Scan disable
8521 14:44:28.197754 == TX Byte 0 ==
8522 14:44:28.201699 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8523 14:44:28.204699 == TX Byte 1 ==
8524 14:44:28.207777 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8525 14:44:28.207851 DramC Write-DBI off
8526 14:44:28.211296
8527 14:44:28.211378 [DATLAT]
8528 14:44:28.211442 Freq=1600, CH1 RK0
8529 14:44:28.211502
8530 14:44:28.214565 DATLAT Default: 0xf
8531 14:44:28.214647 0, 0xFFFF, sum = 0
8532 14:44:28.217934 1, 0xFFFF, sum = 0
8533 14:44:28.218016 2, 0xFFFF, sum = 0
8534 14:44:28.221274 3, 0xFFFF, sum = 0
8535 14:44:28.221357 4, 0xFFFF, sum = 0
8536 14:44:28.224873 5, 0xFFFF, sum = 0
8537 14:44:28.227581 6, 0xFFFF, sum = 0
8538 14:44:28.227664 7, 0xFFFF, sum = 0
8539 14:44:28.231145 8, 0xFFFF, sum = 0
8540 14:44:28.231229 9, 0xFFFF, sum = 0
8541 14:44:28.235467 10, 0xFFFF, sum = 0
8542 14:44:28.235551 11, 0xFFFF, sum = 0
8543 14:44:28.237906 12, 0xFFFF, sum = 0
8544 14:44:28.237989 13, 0xFFFF, sum = 0
8545 14:44:28.240921 14, 0x0, sum = 1
8546 14:44:28.241042 15, 0x0, sum = 2
8547 14:44:28.244650 16, 0x0, sum = 3
8548 14:44:28.244734 17, 0x0, sum = 4
8549 14:44:28.247772 best_step = 15
8550 14:44:28.247854
8551 14:44:28.247920 ==
8552 14:44:28.251300 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 14:44:28.254627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 14:44:28.254710 ==
8555 14:44:28.254775 RX Vref Scan: 1
8556 14:44:28.254835
8557 14:44:28.257745 Set Vref Range= 24 -> 127
8558 14:44:28.257828
8559 14:44:28.260965 RX Vref 24 -> 127, step: 1
8560 14:44:28.261082
8561 14:44:28.264939 RX Delay 11 -> 252, step: 4
8562 14:44:28.265057
8563 14:44:28.268044 Set Vref, RX VrefLevel [Byte0]: 24
8564 14:44:28.271097 [Byte1]: 24
8565 14:44:28.271180
8566 14:44:28.274776 Set Vref, RX VrefLevel [Byte0]: 25
8567 14:44:28.277853 [Byte1]: 25
8568 14:44:28.277936
8569 14:44:28.281808 Set Vref, RX VrefLevel [Byte0]: 26
8570 14:44:28.284536 [Byte1]: 26
8571 14:44:28.288382
8572 14:44:28.288464 Set Vref, RX VrefLevel [Byte0]: 27
8573 14:44:28.291283 [Byte1]: 27
8574 14:44:28.296197
8575 14:44:28.296279 Set Vref, RX VrefLevel [Byte0]: 28
8576 14:44:28.298866 [Byte1]: 28
8577 14:44:28.303800
8578 14:44:28.303882 Set Vref, RX VrefLevel [Byte0]: 29
8579 14:44:28.306527 [Byte1]: 29
8580 14:44:28.311003
8581 14:44:28.311084 Set Vref, RX VrefLevel [Byte0]: 30
8582 14:44:28.313994 [Byte1]: 30
8583 14:44:28.318741
8584 14:44:28.318823 Set Vref, RX VrefLevel [Byte0]: 31
8585 14:44:28.321988 [Byte1]: 31
8586 14:44:28.326014
8587 14:44:28.326098 Set Vref, RX VrefLevel [Byte0]: 32
8588 14:44:28.329335 [Byte1]: 32
8589 14:44:28.333973
8590 14:44:28.334054 Set Vref, RX VrefLevel [Byte0]: 33
8591 14:44:28.337158 [Byte1]: 33
8592 14:44:28.341162
8593 14:44:28.341242 Set Vref, RX VrefLevel [Byte0]: 34
8594 14:44:28.344552 [Byte1]: 34
8595 14:44:28.349223
8596 14:44:28.349305 Set Vref, RX VrefLevel [Byte0]: 35
8597 14:44:28.352833 [Byte1]: 35
8598 14:44:28.356522
8599 14:44:28.356603 Set Vref, RX VrefLevel [Byte0]: 36
8600 14:44:28.360648 [Byte1]: 36
8601 14:44:28.364067
8602 14:44:28.364148 Set Vref, RX VrefLevel [Byte0]: 37
8603 14:44:28.367717 [Byte1]: 37
8604 14:44:28.372107
8605 14:44:28.372189 Set Vref, RX VrefLevel [Byte0]: 38
8606 14:44:28.375157 [Byte1]: 38
8607 14:44:28.379196
8608 14:44:28.379278 Set Vref, RX VrefLevel [Byte0]: 39
8609 14:44:28.382759 [Byte1]: 39
8610 14:44:28.387694
8611 14:44:28.387775 Set Vref, RX VrefLevel [Byte0]: 40
8612 14:44:28.390655 [Byte1]: 40
8613 14:44:28.394667
8614 14:44:28.394749 Set Vref, RX VrefLevel [Byte0]: 41
8615 14:44:28.397975 [Byte1]: 41
8616 14:44:28.402460
8617 14:44:28.402536 Set Vref, RX VrefLevel [Byte0]: 42
8618 14:44:28.405605 [Byte1]: 42
8619 14:44:28.409961
8620 14:44:28.410043 Set Vref, RX VrefLevel [Byte0]: 43
8621 14:44:28.413517 [Byte1]: 43
8622 14:44:28.417821
8623 14:44:28.417903 Set Vref, RX VrefLevel [Byte0]: 44
8624 14:44:28.420691 [Byte1]: 44
8625 14:44:28.425386
8626 14:44:28.425468 Set Vref, RX VrefLevel [Byte0]: 45
8627 14:44:28.429633 [Byte1]: 45
8628 14:44:28.433135
8629 14:44:28.433217 Set Vref, RX VrefLevel [Byte0]: 46
8630 14:44:28.436458 [Byte1]: 46
8631 14:44:28.440275
8632 14:44:28.440357 Set Vref, RX VrefLevel [Byte0]: 47
8633 14:44:28.444106 [Byte1]: 47
8634 14:44:28.447864
8635 14:44:28.447945 Set Vref, RX VrefLevel [Byte0]: 48
8636 14:44:28.451485 [Byte1]: 48
8637 14:44:28.455543
8638 14:44:28.455624 Set Vref, RX VrefLevel [Byte0]: 49
8639 14:44:28.459460 [Byte1]: 49
8640 14:44:28.463220
8641 14:44:28.463301 Set Vref, RX VrefLevel [Byte0]: 50
8642 14:44:28.466479 [Byte1]: 50
8643 14:44:28.471617
8644 14:44:28.471698 Set Vref, RX VrefLevel [Byte0]: 51
8645 14:44:28.474292 [Byte1]: 51
8646 14:44:28.478345
8647 14:44:28.478426 Set Vref, RX VrefLevel [Byte0]: 52
8648 14:44:28.481849 [Byte1]: 52
8649 14:44:28.485960
8650 14:44:28.486041 Set Vref, RX VrefLevel [Byte0]: 53
8651 14:44:28.489989 [Byte1]: 53
8652 14:44:28.493787
8653 14:44:28.493869 Set Vref, RX VrefLevel [Byte0]: 54
8654 14:44:28.496978 [Byte1]: 54
8655 14:44:28.501219
8656 14:44:28.501294 Set Vref, RX VrefLevel [Byte0]: 55
8657 14:44:28.505248 [Byte1]: 55
8658 14:44:28.509354
8659 14:44:28.509436 Set Vref, RX VrefLevel [Byte0]: 56
8660 14:44:28.512113 [Byte1]: 56
8661 14:44:28.517540
8662 14:44:28.517622 Set Vref, RX VrefLevel [Byte0]: 57
8663 14:44:28.519868 [Byte1]: 57
8664 14:44:28.524251
8665 14:44:28.524335 Set Vref, RX VrefLevel [Byte0]: 58
8666 14:44:28.527731 [Byte1]: 58
8667 14:44:28.532149
8668 14:44:28.532232 Set Vref, RX VrefLevel [Byte0]: 59
8669 14:44:28.535187 [Byte1]: 59
8670 14:44:28.540238
8671 14:44:28.540318 Set Vref, RX VrefLevel [Byte0]: 60
8672 14:44:28.542933 [Byte1]: 60
8673 14:44:28.546999
8674 14:44:28.547081 Set Vref, RX VrefLevel [Byte0]: 61
8675 14:44:28.550369 [Byte1]: 61
8676 14:44:28.554618
8677 14:44:28.554699 Set Vref, RX VrefLevel [Byte0]: 62
8678 14:44:28.558188 [Byte1]: 62
8679 14:44:28.561991
8680 14:44:28.562072 Set Vref, RX VrefLevel [Byte0]: 63
8681 14:44:28.565518 [Byte1]: 63
8682 14:44:28.570105
8683 14:44:28.570187 Set Vref, RX VrefLevel [Byte0]: 64
8684 14:44:28.573084 [Byte1]: 64
8685 14:44:28.577989
8686 14:44:28.578070 Set Vref, RX VrefLevel [Byte0]: 65
8687 14:44:28.580809 [Byte1]: 65
8688 14:44:28.584885
8689 14:44:28.584967 Set Vref, RX VrefLevel [Byte0]: 66
8690 14:44:28.588477 [Byte1]: 66
8691 14:44:28.592635
8692 14:44:28.592716 Set Vref, RX VrefLevel [Byte0]: 67
8693 14:44:28.596120 [Byte1]: 67
8694 14:44:28.600098
8695 14:44:28.600179 Set Vref, RX VrefLevel [Byte0]: 68
8696 14:44:28.603753 [Byte1]: 68
8697 14:44:28.608891
8698 14:44:28.608981 Set Vref, RX VrefLevel [Byte0]: 69
8699 14:44:28.611400 [Byte1]: 69
8700 14:44:28.615230
8701 14:44:28.615301 Set Vref, RX VrefLevel [Byte0]: 70
8702 14:44:28.618780 [Byte1]: 70
8703 14:44:28.623015
8704 14:44:28.623098 Set Vref, RX VrefLevel [Byte0]: 71
8705 14:44:28.626568 [Byte1]: 71
8706 14:44:28.630617
8707 14:44:28.630699 Set Vref, RX VrefLevel [Byte0]: 72
8708 14:44:28.634153 [Byte1]: 72
8709 14:44:28.638238
8710 14:44:28.638320 Set Vref, RX VrefLevel [Byte0]: 73
8711 14:44:28.641611 [Byte1]: 73
8712 14:44:28.646022
8713 14:44:28.646103 Set Vref, RX VrefLevel [Byte0]: 74
8714 14:44:28.649358 [Byte1]: 74
8715 14:44:28.653520
8716 14:44:28.653601 Set Vref, RX VrefLevel [Byte0]: 75
8717 14:44:28.656739 [Byte1]: 75
8718 14:44:28.661161
8719 14:44:28.661243 Final RX Vref Byte 0 = 54 to rank0
8720 14:44:28.664564 Final RX Vref Byte 1 = 58 to rank0
8721 14:44:28.668033 Final RX Vref Byte 0 = 54 to rank1
8722 14:44:28.671435 Final RX Vref Byte 1 = 58 to rank1==
8723 14:44:28.674754 Dram Type= 6, Freq= 0, CH_1, rank 0
8724 14:44:28.677980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 14:44:28.681469 ==
8726 14:44:28.681552 DQS Delay:
8727 14:44:28.681617 DQS0 = 0, DQS1 = 0
8728 14:44:28.684314 DQM Delay:
8729 14:44:28.684396 DQM0 = 130, DQM1 = 124
8730 14:44:28.688445 DQ Delay:
8731 14:44:28.691463 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8732 14:44:28.694779 DQ4 =128, DQ5 =142, DQ6 =140, DQ7 =128
8733 14:44:28.697836 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8734 14:44:28.701797 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8735 14:44:28.701880
8736 14:44:28.701945
8737 14:44:28.702004
8738 14:44:28.705035 [DramC_TX_OE_Calibration] TA2
8739 14:44:28.708010 Original DQ_B0 (3 6) =30, OEN = 27
8740 14:44:28.711089 Original DQ_B1 (3 6) =30, OEN = 27
8741 14:44:28.711172 24, 0x0, End_B0=24 End_B1=24
8742 14:44:28.714637 25, 0x0, End_B0=25 End_B1=25
8743 14:44:28.718040 26, 0x0, End_B0=26 End_B1=26
8744 14:44:28.721444 27, 0x0, End_B0=27 End_B1=27
8745 14:44:28.724621 28, 0x0, End_B0=28 End_B1=28
8746 14:44:28.724705 29, 0x0, End_B0=29 End_B1=29
8747 14:44:28.727941 30, 0x0, End_B0=30 End_B1=30
8748 14:44:28.731334 31, 0x4545, End_B0=30 End_B1=30
8749 14:44:28.734743 Byte0 end_step=30 best_step=27
8750 14:44:28.738178 Byte1 end_step=30 best_step=27
8751 14:44:28.741017 Byte0 TX OE(2T, 0.5T) = (3, 3)
8752 14:44:28.741100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8753 14:44:28.741164
8754 14:44:28.741225
8755 14:44:28.751284 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8756 14:44:28.754404 CH1 RK0: MR19=302, MR18=13FD
8757 14:44:28.760916 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8758 14:44:28.761037
8759 14:44:28.764861 ----->DramcWriteLeveling(PI) begin...
8760 14:44:28.764944 ==
8761 14:44:28.767868 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 14:44:28.771628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 14:44:28.771710 ==
8764 14:44:28.774793 Write leveling (Byte 0): 28 => 28
8765 14:44:28.778338 Write leveling (Byte 1): 28 => 28
8766 14:44:28.781506 DramcWriteLeveling(PI) end<-----
8767 14:44:28.781589
8768 14:44:28.781655 ==
8769 14:44:28.784902 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 14:44:28.787872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 14:44:28.787955 ==
8772 14:44:28.791470 [Gating] SW mode calibration
8773 14:44:28.798386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8774 14:44:28.804927 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8775 14:44:28.807840 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 14:44:28.811545 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 14:44:28.818253 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8778 14:44:28.821150 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
8779 14:44:28.825394 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 14:44:28.828555 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 14:44:28.835131 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 14:44:28.838704 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 14:44:28.841702 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 14:44:28.848339 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8785 14:44:28.851514 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8786 14:44:28.855157 1 5 12 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
8787 14:44:28.862086 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 14:44:28.865517 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 14:44:28.868007 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 14:44:28.875040 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 14:44:28.879046 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 14:44:28.882292 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 14:44:28.888409 1 6 8 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
8794 14:44:28.891545 1 6 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8795 14:44:28.895343 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 14:44:28.901375 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 14:44:28.905149 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 14:44:28.908390 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 14:44:28.911601 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 14:44:28.918128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8801 14:44:28.921869 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8802 14:44:28.925231 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8803 14:44:28.931849 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 14:44:28.934773 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 14:44:28.938262 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 14:44:28.944888 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 14:44:28.948086 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 14:44:28.951670 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 14:44:28.958383 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 14:44:28.961632 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 14:44:28.964762 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 14:44:28.971557 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 14:44:28.974875 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 14:44:28.978956 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 14:44:28.985418 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 14:44:28.987955 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 14:44:28.991618 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 14:44:28.995137 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8819 14:44:28.998082 Total UI for P1: 0, mck2ui 16
8820 14:44:29.001608 best dqsien dly found for B0: ( 1, 9, 6)
8821 14:44:29.008064 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 14:44:29.012113 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 14:44:29.014690 Total UI for P1: 0, mck2ui 16
8824 14:44:29.018868 best dqsien dly found for B1: ( 1, 9, 14)
8825 14:44:29.021418 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8826 14:44:29.024919 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8827 14:44:29.025036
8828 14:44:29.028308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8829 14:44:29.031905 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8830 14:44:29.034985 [Gating] SW calibration Done
8831 14:44:29.035068 ==
8832 14:44:29.038170 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 14:44:29.044964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 14:44:29.045086 ==
8835 14:44:29.045152 RX Vref Scan: 0
8836 14:44:29.045213
8837 14:44:29.048324 RX Vref 0 -> 0, step: 1
8838 14:44:29.048407
8839 14:44:29.051410 RX Delay 0 -> 252, step: 8
8840 14:44:29.055167 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8841 14:44:29.058276 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 14:44:29.061767 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8843 14:44:29.064683 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8844 14:44:29.071654 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8845 14:44:29.074686 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8846 14:44:29.078159 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8847 14:44:29.081567 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8848 14:44:29.084614 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8849 14:44:29.088118 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 14:44:29.095511 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 14:44:29.098103 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8852 14:44:29.101988 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8853 14:44:29.105265 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8854 14:44:29.112274 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8855 14:44:29.115346 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8856 14:44:29.115429 ==
8857 14:44:29.118424 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 14:44:29.121449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 14:44:29.121533 ==
8860 14:44:29.121599 DQS Delay:
8861 14:44:29.125143 DQS0 = 0, DQS1 = 0
8862 14:44:29.125225 DQM Delay:
8863 14:44:29.128467 DQM0 = 132, DQM1 = 129
8864 14:44:29.128549 DQ Delay:
8865 14:44:29.131682 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8866 14:44:29.134932 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8867 14:44:29.138988 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8868 14:44:29.141590 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8869 14:44:29.141672
8870 14:44:29.144753
8871 14:44:29.144862 ==
8872 14:44:29.149467 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 14:44:29.152222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 14:44:29.152331 ==
8875 14:44:29.152424
8876 14:44:29.152513
8877 14:44:29.154961 TX Vref Scan disable
8878 14:44:29.155044 == TX Byte 0 ==
8879 14:44:29.161863 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8880 14:44:29.165438 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8881 14:44:29.165527 == TX Byte 1 ==
8882 14:44:29.172642 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8883 14:44:29.174948 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8884 14:44:29.175031 ==
8885 14:44:29.178804 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 14:44:29.182208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 14:44:29.182291 ==
8888 14:44:29.194825
8889 14:44:29.198150 TX Vref early break, caculate TX vref
8890 14:44:29.201625 TX Vref=16, minBit 8, minWin=21, winSum=370
8891 14:44:29.204826 TX Vref=18, minBit 0, minWin=23, winSum=384
8892 14:44:29.208291 TX Vref=20, minBit 8, minWin=23, winSum=387
8893 14:44:29.211403 TX Vref=22, minBit 0, minWin=24, winSum=399
8894 14:44:29.214567 TX Vref=24, minBit 1, minWin=25, winSum=407
8895 14:44:29.221555 TX Vref=26, minBit 8, minWin=25, winSum=411
8896 14:44:29.224523 TX Vref=28, minBit 0, minWin=25, winSum=419
8897 14:44:29.227965 TX Vref=30, minBit 5, minWin=24, winSum=414
8898 14:44:29.231512 TX Vref=32, minBit 0, minWin=25, winSum=412
8899 14:44:29.234541 TX Vref=34, minBit 9, minWin=23, winSum=396
8900 14:44:29.241410 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8901 14:44:29.241494
8902 14:44:29.244562 Final TX Range 0 Vref 28
8903 14:44:29.244644
8904 14:44:29.244710 ==
8905 14:44:29.248070 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 14:44:29.251134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 14:44:29.251217 ==
8908 14:44:29.251283
8909 14:44:29.251344
8910 14:44:29.254839 TX Vref Scan disable
8911 14:44:29.261446 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8912 14:44:29.261528 == TX Byte 0 ==
8913 14:44:29.264962 u2DelayCellOfst[0]=17 cells (5 PI)
8914 14:44:29.267767 u2DelayCellOfst[1]=14 cells (4 PI)
8915 14:44:29.271424 u2DelayCellOfst[2]=0 cells (0 PI)
8916 14:44:29.274679 u2DelayCellOfst[3]=7 cells (2 PI)
8917 14:44:29.277866 u2DelayCellOfst[4]=10 cells (3 PI)
8918 14:44:29.281533 u2DelayCellOfst[5]=21 cells (6 PI)
8919 14:44:29.281615 u2DelayCellOfst[6]=17 cells (5 PI)
8920 14:44:29.284617 u2DelayCellOfst[7]=7 cells (2 PI)
8921 14:44:29.291516 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8922 14:44:29.295076 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8923 14:44:29.295155 == TX Byte 1 ==
8924 14:44:29.298334 u2DelayCellOfst[8]=0 cells (0 PI)
8925 14:44:29.301865 u2DelayCellOfst[9]=7 cells (2 PI)
8926 14:44:29.305166 u2DelayCellOfst[10]=10 cells (3 PI)
8927 14:44:29.308623 u2DelayCellOfst[11]=7 cells (2 PI)
8928 14:44:29.311496 u2DelayCellOfst[12]=14 cells (4 PI)
8929 14:44:29.315133 u2DelayCellOfst[13]=14 cells (4 PI)
8930 14:44:29.318296 u2DelayCellOfst[14]=17 cells (5 PI)
8931 14:44:29.321439 u2DelayCellOfst[15]=17 cells (5 PI)
8932 14:44:29.325197 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 14:44:29.328615 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8934 14:44:29.331988 DramC Write-DBI on
8935 14:44:29.332099 ==
8936 14:44:29.335064 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 14:44:29.338440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 14:44:29.338524 ==
8939 14:44:29.338589
8940 14:44:29.338650
8941 14:44:29.341187 TX Vref Scan disable
8942 14:44:29.345771 == TX Byte 0 ==
8943 14:44:29.348046 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8944 14:44:29.348129 == TX Byte 1 ==
8945 14:44:29.355496 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8946 14:44:29.355583 DramC Write-DBI off
8947 14:44:29.355661
8948 14:44:29.357965 [DATLAT]
8949 14:44:29.358048 Freq=1600, CH1 RK1
8950 14:44:29.358114
8951 14:44:29.361423 DATLAT Default: 0xf
8952 14:44:29.361506 0, 0xFFFF, sum = 0
8953 14:44:29.364852 1, 0xFFFF, sum = 0
8954 14:44:29.364940 2, 0xFFFF, sum = 0
8955 14:44:29.368152 3, 0xFFFF, sum = 0
8956 14:44:29.368234 4, 0xFFFF, sum = 0
8957 14:44:29.371024 5, 0xFFFF, sum = 0
8958 14:44:29.371110 6, 0xFFFF, sum = 0
8959 14:44:29.376023 7, 0xFFFF, sum = 0
8960 14:44:29.376107 8, 0xFFFF, sum = 0
8961 14:44:29.378018 9, 0xFFFF, sum = 0
8962 14:44:29.378102 10, 0xFFFF, sum = 0
8963 14:44:29.381732 11, 0xFFFF, sum = 0
8964 14:44:29.384570 12, 0xFFFF, sum = 0
8965 14:44:29.384654 13, 0xFFFF, sum = 0
8966 14:44:29.388080 14, 0x0, sum = 1
8967 14:44:29.388165 15, 0x0, sum = 2
8968 14:44:29.388232 16, 0x0, sum = 3
8969 14:44:29.391278 17, 0x0, sum = 4
8970 14:44:29.391402 best_step = 15
8971 14:44:29.391468
8972 14:44:29.394976 ==
8973 14:44:29.395059 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 14:44:29.401818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 14:44:29.401903 ==
8976 14:44:29.401968 RX Vref Scan: 0
8977 14:44:29.402030
8978 14:44:29.404817 RX Vref 0 -> 0, step: 1
8979 14:44:29.404900
8980 14:44:29.408533 RX Delay 11 -> 252, step: 4
8981 14:44:29.411617 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8982 14:44:29.414481 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8983 14:44:29.421771 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8984 14:44:29.425130 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8985 14:44:29.427932 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8986 14:44:29.431252 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8987 14:44:29.434648 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8988 14:44:29.441712 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8989 14:44:29.444805 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8990 14:44:29.448748 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8991 14:44:29.451293 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8992 14:44:29.455040 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8993 14:44:29.461193 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8994 14:44:29.465252 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8995 14:44:29.468633 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8996 14:44:29.471292 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8997 14:44:29.471376 ==
8998 14:44:29.474627 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 14:44:29.478424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 14:44:29.481560 ==
9001 14:44:29.481643 DQS Delay:
9002 14:44:29.481709 DQS0 = 0, DQS1 = 0
9003 14:44:29.485464 DQM Delay:
9004 14:44:29.485548 DQM0 = 129, DQM1 = 126
9005 14:44:29.487863 DQ Delay:
9006 14:44:29.491785 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =128
9007 14:44:29.494486 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9008 14:44:29.498261 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
9009 14:44:29.501382 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9010 14:44:29.501465
9011 14:44:29.501531
9012 14:44:29.501592
9013 14:44:29.504565 [DramC_TX_OE_Calibration] TA2
9014 14:44:29.508078 Original DQ_B0 (3 6) =30, OEN = 27
9015 14:44:29.511693 Original DQ_B1 (3 6) =30, OEN = 27
9016 14:44:29.511777 24, 0x0, End_B0=24 End_B1=24
9017 14:44:29.514455 25, 0x0, End_B0=25 End_B1=25
9018 14:44:29.518203 26, 0x0, End_B0=26 End_B1=26
9019 14:44:29.521141 27, 0x0, End_B0=27 End_B1=27
9020 14:44:29.525078 28, 0x0, End_B0=28 End_B1=28
9021 14:44:29.525164 29, 0x0, End_B0=29 End_B1=29
9022 14:44:29.528703 30, 0x0, End_B0=30 End_B1=30
9023 14:44:29.531125 31, 0x4141, End_B0=30 End_B1=30
9024 14:44:29.534420 Byte0 end_step=30 best_step=27
9025 14:44:29.538547 Byte1 end_step=30 best_step=27
9026 14:44:29.541010 Byte0 TX OE(2T, 0.5T) = (3, 3)
9027 14:44:29.541110 Byte1 TX OE(2T, 0.5T) = (3, 3)
9028 14:44:29.541176
9029 14:44:29.541285
9030 14:44:29.551340 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9031 14:44:29.554950 CH1 RK1: MR19=303, MR18=1016
9032 14:44:29.562598 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9033 14:44:29.562683 [RxdqsGatingPostProcess] freq 1600
9034 14:44:29.568393 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9035 14:44:29.570996 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 14:44:29.575247 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 14:44:29.577974 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 14:44:29.581119 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 14:44:29.584510 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 14:44:29.588150 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 14:44:29.591574 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 14:44:29.591657 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 14:44:29.594854 Pre-setting of DQS Precalculation
9044 14:44:29.601544 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9045 14:44:29.608010 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9046 14:44:29.615581 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9047 14:44:29.615666
9048 14:44:29.615731
9049 14:44:29.617939 [Calibration Summary] 3200 Mbps
9050 14:44:29.618021 CH 0, Rank 0
9051 14:44:29.621682 SW Impedance : PASS
9052 14:44:29.625350 DUTY Scan : NO K
9053 14:44:29.625432 ZQ Calibration : PASS
9054 14:44:29.627924 Jitter Meter : NO K
9055 14:44:29.631398 CBT Training : PASS
9056 14:44:29.631493 Write leveling : PASS
9057 14:44:29.634777 RX DQS gating : PASS
9058 14:44:29.638442 RX DQ/DQS(RDDQC) : PASS
9059 14:44:29.638524 TX DQ/DQS : PASS
9060 14:44:29.641287 RX DATLAT : PASS
9061 14:44:29.644957 RX DQ/DQS(Engine): PASS
9062 14:44:29.645065 TX OE : PASS
9063 14:44:29.647949 All Pass.
9064 14:44:29.648032
9065 14:44:29.648109 CH 0, Rank 1
9066 14:44:29.651489 SW Impedance : PASS
9067 14:44:29.651615 DUTY Scan : NO K
9068 14:44:29.654652 ZQ Calibration : PASS
9069 14:44:29.658064 Jitter Meter : NO K
9070 14:44:29.658146 CBT Training : PASS
9071 14:44:29.661366 Write leveling : PASS
9072 14:44:29.661449 RX DQS gating : PASS
9073 14:44:29.664672 RX DQ/DQS(RDDQC) : PASS
9074 14:44:29.668267 TX DQ/DQS : PASS
9075 14:44:29.668352 RX DATLAT : PASS
9076 14:44:29.671175 RX DQ/DQS(Engine): PASS
9077 14:44:29.675198 TX OE : PASS
9078 14:44:29.675287 All Pass.
9079 14:44:29.675354
9080 14:44:29.675415 CH 1, Rank 0
9081 14:44:29.678852 SW Impedance : PASS
9082 14:44:29.682028 DUTY Scan : NO K
9083 14:44:29.682111 ZQ Calibration : PASS
9084 14:44:29.685097 Jitter Meter : NO K
9085 14:44:29.688402 CBT Training : PASS
9086 14:44:29.688485 Write leveling : PASS
9087 14:44:29.691174 RX DQS gating : PASS
9088 14:44:29.694722 RX DQ/DQS(RDDQC) : PASS
9089 14:44:29.694805 TX DQ/DQS : PASS
9090 14:44:29.697861 RX DATLAT : PASS
9091 14:44:29.697944 RX DQ/DQS(Engine): PASS
9092 14:44:29.701443 TX OE : PASS
9093 14:44:29.701526 All Pass.
9094 14:44:29.701592
9095 14:44:29.704806 CH 1, Rank 1
9096 14:44:29.704888 SW Impedance : PASS
9097 14:44:29.709016 DUTY Scan : NO K
9098 14:44:29.712002 ZQ Calibration : PASS
9099 14:44:29.712085 Jitter Meter : NO K
9100 14:44:29.715021 CBT Training : PASS
9101 14:44:29.718051 Write leveling : PASS
9102 14:44:29.718134 RX DQS gating : PASS
9103 14:44:29.721793 RX DQ/DQS(RDDQC) : PASS
9104 14:44:29.725373 TX DQ/DQS : PASS
9105 14:44:29.725457 RX DATLAT : PASS
9106 14:44:29.728556 RX DQ/DQS(Engine): PASS
9107 14:44:29.731871 TX OE : PASS
9108 14:44:29.731954 All Pass.
9109 14:44:29.732036
9110 14:44:29.732126 DramC Write-DBI on
9111 14:44:29.735325 PER_BANK_REFRESH: Hybrid Mode
9112 14:44:29.738093 TX_TRACKING: ON
9113 14:44:29.745209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9114 14:44:29.755400 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9115 14:44:29.762233 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9116 14:44:29.764925 [FAST_K] Save calibration result to emmc
9117 14:44:29.769274 sync common calibartion params.
9118 14:44:29.769358 sync cbt_mode0:1, 1:1
9119 14:44:29.772274 dram_init: ddr_geometry: 2
9120 14:44:29.775127 dram_init: ddr_geometry: 2
9121 14:44:29.778688 dram_init: ddr_geometry: 2
9122 14:44:29.778779 0:dram_rank_size:100000000
9123 14:44:29.781947 1:dram_rank_size:100000000
9124 14:44:29.788981 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9125 14:44:29.789095 DFS_SHUFFLE_HW_MODE: ON
9126 14:44:29.794950 dramc_set_vcore_voltage set vcore to 725000
9127 14:44:29.795033 Read voltage for 1600, 0
9128 14:44:29.795099 Vio18 = 0
9129 14:44:29.798199 Vcore = 725000
9130 14:44:29.798288 Vdram = 0
9131 14:44:29.798355 Vddq = 0
9132 14:44:29.801726 Vmddr = 0
9133 14:44:29.801817 switch to 3200 Mbps bootup
9134 14:44:29.804858 [DramcRunTimeConfig]
9135 14:44:29.804940 PHYPLL
9136 14:44:29.808382 DPM_CONTROL_AFTERK: ON
9137 14:44:29.808465 PER_BANK_REFRESH: ON
9138 14:44:29.811613 REFRESH_OVERHEAD_REDUCTION: ON
9139 14:44:29.815108 CMD_PICG_NEW_MODE: OFF
9140 14:44:29.815190 XRTWTW_NEW_MODE: ON
9141 14:44:29.819013 XRTRTR_NEW_MODE: ON
9142 14:44:29.819096 TX_TRACKING: ON
9143 14:44:29.821622 RDSEL_TRACKING: OFF
9144 14:44:29.825178 DQS Precalculation for DVFS: ON
9145 14:44:29.825261 RX_TRACKING: OFF
9146 14:44:29.828381 HW_GATING DBG: ON
9147 14:44:29.828466 ZQCS_ENABLE_LP4: ON
9148 14:44:29.831789 RX_PICG_NEW_MODE: ON
9149 14:44:29.831871 TX_PICG_NEW_MODE: ON
9150 14:44:29.834880 ENABLE_RX_DCM_DPHY: ON
9151 14:44:29.838212 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9152 14:44:29.841858 DUMMY_READ_FOR_TRACKING: OFF
9153 14:44:29.841940 !!! SPM_CONTROL_AFTERK: OFF
9154 14:44:29.844767 !!! SPM could not control APHY
9155 14:44:29.848204 IMPEDANCE_TRACKING: ON
9156 14:44:29.848287 TEMP_SENSOR: ON
9157 14:44:29.851461 HW_SAVE_FOR_SR: OFF
9158 14:44:29.855105 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9159 14:44:29.858253 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9160 14:44:29.861578 Read ODT Tracking: ON
9161 14:44:29.861661 Refresh Rate DeBounce: ON
9162 14:44:29.864515 DFS_NO_QUEUE_FLUSH: ON
9163 14:44:29.868481 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9164 14:44:29.871684 ENABLE_DFS_RUNTIME_MRW: OFF
9165 14:44:29.871767 DDR_RESERVE_NEW_MODE: ON
9166 14:44:29.874743 MR_CBT_SWITCH_FREQ: ON
9167 14:44:29.877926 =========================
9168 14:44:29.896277 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9169 14:44:29.898698 dram_init: ddr_geometry: 2
9170 14:44:29.917399 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9171 14:44:29.920300 dram_init: dram init end (result: 0)
9172 14:44:29.926938 DRAM-K: Full calibration passed in 24576 msecs
9173 14:44:29.930478 MRC: failed to locate region type 0.
9174 14:44:29.930562 DRAM rank0 size:0x100000000,
9175 14:44:29.934035 DRAM rank1 size=0x100000000
9176 14:44:29.944123 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9177 14:44:29.951331 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9178 14:44:29.957157 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9179 14:44:29.963816 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9180 14:44:29.967314 DRAM rank0 size:0x100000000,
9181 14:44:29.970782 DRAM rank1 size=0x100000000
9182 14:44:29.970866 CBMEM:
9183 14:44:29.974277 IMD: root @ 0xfffff000 254 entries.
9184 14:44:29.977211 IMD: root @ 0xffffec00 62 entries.
9185 14:44:29.980256 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9186 14:44:29.983801 WARNING: RO_VPD is uninitialized or empty.
9187 14:44:29.991087 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9188 14:44:29.997625 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9189 14:44:30.009848 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9190 14:44:30.021497 BS: romstage times (exec / console): total (unknown) / 24079 ms
9191 14:44:30.021582
9192 14:44:30.021648
9193 14:44:30.031196 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9194 14:44:30.034997 ARM64: Exception handlers installed.
9195 14:44:30.038305 ARM64: Testing exception
9196 14:44:30.041376 ARM64: Done test exception
9197 14:44:30.041459 Enumerating buses...
9198 14:44:30.044516 Show all devs... Before device enumeration.
9199 14:44:30.048492 Root Device: enabled 1
9200 14:44:30.051308 CPU_CLUSTER: 0: enabled 1
9201 14:44:30.051391 CPU: 00: enabled 1
9202 14:44:30.054709 Compare with tree...
9203 14:44:30.054809 Root Device: enabled 1
9204 14:44:30.057839 CPU_CLUSTER: 0: enabled 1
9205 14:44:30.061385 CPU: 00: enabled 1
9206 14:44:30.061468 Root Device scanning...
9207 14:44:30.065006 scan_static_bus for Root Device
9208 14:44:30.067739 CPU_CLUSTER: 0 enabled
9209 14:44:30.071432 scan_static_bus for Root Device done
9210 14:44:30.074628 scan_bus: bus Root Device finished in 8 msecs
9211 14:44:30.074711 done
9212 14:44:30.081408 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9213 14:44:30.084923 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9214 14:44:30.091220 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9215 14:44:30.094559 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9216 14:44:30.097839 Allocating resources...
9217 14:44:30.097922 Reading resources...
9218 14:44:30.104860 Root Device read_resources bus 0 link: 0
9219 14:44:30.104944 DRAM rank0 size:0x100000000,
9220 14:44:30.108247 DRAM rank1 size=0x100000000
9221 14:44:30.112795 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9222 14:44:30.114532 CPU: 00 missing read_resources
9223 14:44:30.118389 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9224 14:44:30.124730 Root Device read_resources bus 0 link: 0 done
9225 14:44:30.124813 Done reading resources.
9226 14:44:30.131445 Show resources in subtree (Root Device)...After reading.
9227 14:44:30.134842 Root Device child on link 0 CPU_CLUSTER: 0
9228 14:44:30.137987 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 14:44:30.148049 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 14:44:30.148133 CPU: 00
9231 14:44:30.151224 Root Device assign_resources, bus 0 link: 0
9232 14:44:30.155524 CPU_CLUSTER: 0 missing set_resources
9233 14:44:30.158295 Root Device assign_resources, bus 0 link: 0 done
9234 14:44:30.161127 Done setting resources.
9235 14:44:30.168568 Show resources in subtree (Root Device)...After assigning values.
9236 14:44:30.171300 Root Device child on link 0 CPU_CLUSTER: 0
9237 14:44:30.174765 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 14:44:30.184955 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 14:44:30.185082 CPU: 00
9240 14:44:30.188803 Done allocating resources.
9241 14:44:30.191747 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9242 14:44:30.194397 Enabling resources...
9243 14:44:30.194481 done.
9244 14:44:30.198051 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9245 14:44:30.201946 Initializing devices...
9246 14:44:30.204782 Root Device init
9247 14:44:30.204868 init hardware done!
9248 14:44:30.208103 0x00000018: ctrlr->caps
9249 14:44:30.208231 52.000 MHz: ctrlr->f_max
9250 14:44:30.211334 0.400 MHz: ctrlr->f_min
9251 14:44:30.214340 0x40ff8080: ctrlr->voltages
9252 14:44:30.214425 sclk: 390625
9253 14:44:30.218086 Bus Width = 1
9254 14:44:30.218187 sclk: 390625
9255 14:44:30.218283 Bus Width = 1
9256 14:44:30.221052 Early init status = 3
9257 14:44:30.224351 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9258 14:44:30.232393 in-header: 03 fc 00 00 01 00 00 00
9259 14:44:30.232475 in-data: 00
9260 14:44:30.235234 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9261 14:44:30.240475 in-header: 03 fd 00 00 00 00 00 00
9262 14:44:30.244402 in-data:
9263 14:44:30.247337 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9264 14:44:30.251474 in-header: 03 fc 00 00 01 00 00 00
9265 14:44:30.254783 in-data: 00
9266 14:44:30.258493 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9267 14:44:30.263840 in-header: 03 fd 00 00 00 00 00 00
9268 14:44:30.267350 in-data:
9269 14:44:30.270515 [SSUSB] Setting up USB HOST controller...
9270 14:44:30.273867 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9271 14:44:30.277051 [SSUSB] phy power-on done.
9272 14:44:30.280539 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9273 14:44:30.287194 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9274 14:44:30.290682 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9275 14:44:30.296958 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9276 14:44:30.304110 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9277 14:44:30.310554 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9278 14:44:30.317583 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9279 14:44:30.324694 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9280 14:44:30.327128 SPM: binary array size = 0x9dc
9281 14:44:30.330687 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9282 14:44:30.336905 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9283 14:44:30.344660 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9284 14:44:30.347283 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9285 14:44:30.350376 configure_display: Starting display init
9286 14:44:30.387580 anx7625_power_on_init: Init interface.
9287 14:44:30.390432 anx7625_disable_pd_protocol: Disabled PD feature.
9288 14:44:30.394115 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9289 14:44:30.421806 anx7625_start_dp_work: Secure OCM version=00
9290 14:44:30.425299 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9291 14:44:30.440278 sp_tx_get_edid_block: EDID Block = 1
9292 14:44:30.542357 Extracted contents:
9293 14:44:30.545760 header: 00 ff ff ff ff ff ff 00
9294 14:44:30.548651 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9295 14:44:30.551891 version: 01 04
9296 14:44:30.555321 basic params: 95 1f 11 78 0a
9297 14:44:30.559213 chroma info: 76 90 94 55 54 90 27 21 50 54
9298 14:44:30.562699 established: 00 00 00
9299 14:44:30.565445 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9300 14:44:30.572358 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9301 14:44:30.579568 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9302 14:44:30.586197 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9303 14:44:30.591977 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9304 14:44:30.595274 extensions: 00
9305 14:44:30.595375 checksum: fb
9306 14:44:30.595475
9307 14:44:30.598600 Manufacturer: IVO Model 57d Serial Number 0
9308 14:44:30.602056 Made week 0 of 2020
9309 14:44:30.602157 EDID version: 1.4
9310 14:44:30.605528 Digital display
9311 14:44:30.608778 6 bits per primary color channel
9312 14:44:30.608879 DisplayPort interface
9313 14:44:30.613680 Maximum image size: 31 cm x 17 cm
9314 14:44:30.613754 Gamma: 220%
9315 14:44:30.615278 Check DPMS levels
9316 14:44:30.619327 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9317 14:44:30.622806 First detailed timing is preferred timing
9318 14:44:30.625874 Established timings supported:
9319 14:44:30.628878 Standard timings supported:
9320 14:44:30.628981 Detailed timings
9321 14:44:30.635176 Hex of detail: 383680a07038204018303c0035ae10000019
9322 14:44:30.639045 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9323 14:44:30.642009 0780 0798 07c8 0820 hborder 0
9324 14:44:30.648744 0438 043b 0447 0458 vborder 0
9325 14:44:30.648846 -hsync -vsync
9326 14:44:30.652592 Did detailed timing
9327 14:44:30.655459 Hex of detail: 000000000000000000000000000000000000
9328 14:44:30.658928 Manufacturer-specified data, tag 0
9329 14:44:30.665337 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9330 14:44:30.665427 ASCII string: InfoVision
9331 14:44:30.672513 Hex of detail: 000000fe00523134304e574635205248200a
9332 14:44:30.672621 ASCII string: R140NWF5 RH
9333 14:44:30.675684 Checksum
9334 14:44:30.675783 Checksum: 0xfb (valid)
9335 14:44:30.682313 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9336 14:44:30.682389 DSI data_rate: 832800000 bps
9337 14:44:30.689614 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9338 14:44:30.693209 anx7625_parse_edid: pixelclock(138800).
9339 14:44:30.696285 hactive(1920), hsync(48), hfp(24), hbp(88)
9340 14:44:30.699531 vactive(1080), vsync(12), vfp(3), vbp(17)
9341 14:44:30.703480 anx7625_dsi_config: config dsi.
9342 14:44:30.710105 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9343 14:44:30.723978 anx7625_dsi_config: success to config DSI
9344 14:44:30.727948 anx7625_dp_start: MIPI phy setup OK.
9345 14:44:30.730974 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9346 14:44:30.734238 mtk_ddp_mode_set invalid vrefresh 60
9347 14:44:30.737768 main_disp_path_setup
9348 14:44:30.737876 ovl_layer_smi_id_en
9349 14:44:30.741209 ovl_layer_smi_id_en
9350 14:44:30.741291 ccorr_config
9351 14:44:30.741357 aal_config
9352 14:44:30.744222 gamma_config
9353 14:44:30.744304 postmask_config
9354 14:44:30.747667 dither_config
9355 14:44:30.750883 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9356 14:44:30.757882 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9357 14:44:30.760854 Root Device init finished in 553 msecs
9358 14:44:30.760940 CPU_CLUSTER: 0 init
9359 14:44:30.770793 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9360 14:44:30.773890 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9361 14:44:30.777996 APU_MBOX 0x190000b0 = 0x10001
9362 14:44:30.781350 APU_MBOX 0x190001b0 = 0x10001
9363 14:44:30.784066 APU_MBOX 0x190005b0 = 0x10001
9364 14:44:30.787543 APU_MBOX 0x190006b0 = 0x10001
9365 14:44:30.790703 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9366 14:44:30.802885 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9367 14:44:30.815563 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9368 14:44:30.822653 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9369 14:44:30.833954 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9370 14:44:30.843218 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9371 14:44:30.846561 CPU_CLUSTER: 0 init finished in 81 msecs
9372 14:44:30.849384 Devices initialized
9373 14:44:30.853091 Show all devs... After init.
9374 14:44:30.853166 Root Device: enabled 1
9375 14:44:30.856534 CPU_CLUSTER: 0: enabled 1
9376 14:44:30.859308 CPU: 00: enabled 1
9377 14:44:30.863508 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9378 14:44:30.866245 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9379 14:44:30.870562 ELOG: NV offset 0x57f000 size 0x1000
9380 14:44:30.876093 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9381 14:44:30.882802 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9382 14:44:30.886436 ELOG: Event(17) added with size 13 at 2024-06-04 14:44:31 UTC
9383 14:44:30.889924 out: cmd=0x121: 03 db 21 01 00 00 00 00
9384 14:44:30.894290 in-header: 03 d6 00 00 2c 00 00 00
9385 14:44:30.907563 in-data: 89 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9386 14:44:30.914274 ELOG: Event(A1) added with size 10 at 2024-06-04 14:44:31 UTC
9387 14:44:30.921653 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9388 14:44:30.927588 ELOG: Event(A0) added with size 9 at 2024-06-04 14:44:31 UTC
9389 14:44:30.931392 elog_add_boot_reason: Logged dev mode boot
9390 14:44:30.934350 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9391 14:44:30.937409 Finalize devices...
9392 14:44:30.937493 Devices finalized
9393 14:44:30.944578 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9394 14:44:30.947180 Writing coreboot table at 0xffe64000
9395 14:44:30.950688 0. 000000000010a000-0000000000113fff: RAMSTAGE
9396 14:44:30.954075 1. 0000000040000000-00000000400fffff: RAM
9397 14:44:30.957349 2. 0000000040100000-000000004032afff: RAMSTAGE
9398 14:44:30.963934 3. 000000004032b000-00000000545fffff: RAM
9399 14:44:30.967468 4. 0000000054600000-000000005465ffff: BL31
9400 14:44:30.971651 5. 0000000054660000-00000000ffe63fff: RAM
9401 14:44:30.974157 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9402 14:44:30.980754 7. 0000000100000000-000000023fffffff: RAM
9403 14:44:30.980838 Passing 5 GPIOs to payload:
9404 14:44:30.987128 NAME | PORT | POLARITY | VALUE
9405 14:44:30.990760 EC in RW | 0x000000aa | low | undefined
9406 14:44:30.997817 EC interrupt | 0x00000005 | low | undefined
9407 14:44:31.000772 TPM interrupt | 0x000000ab | high | undefined
9408 14:44:31.004337 SD card detect | 0x00000011 | high | undefined
9409 14:44:31.010603 speaker enable | 0x00000093 | high | undefined
9410 14:44:31.014485 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9411 14:44:31.018081 in-header: 03 f9 00 00 02 00 00 00
9412 14:44:31.018164 in-data: 02 00
9413 14:44:31.020896 ADC[4]: Raw value=900221 ID=7
9414 14:44:31.024280 ADC[3]: Raw value=213336 ID=1
9415 14:44:31.024363 RAM Code: 0x71
9416 14:44:31.027416 ADC[6]: Raw value=74557 ID=0
9417 14:44:31.030564 ADC[5]: Raw value=212229 ID=1
9418 14:44:31.030648 SKU Code: 0x1
9419 14:44:31.038206 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cb8c
9420 14:44:31.040685 coreboot table: 964 bytes.
9421 14:44:31.044518 IMD ROOT 0. 0xfffff000 0x00001000
9422 14:44:31.048165 IMD SMALL 1. 0xffffe000 0x00001000
9423 14:44:31.051202 RO MCACHE 2. 0xffffc000 0x00001104
9424 14:44:31.054421 CONSOLE 3. 0xfff7c000 0x00080000
9425 14:44:31.057855 FMAP 4. 0xfff7b000 0x00000452
9426 14:44:31.060956 TIME STAMP 5. 0xfff7a000 0x00000910
9427 14:44:31.064240 VBOOT WORK 6. 0xfff66000 0x00014000
9428 14:44:31.067627 RAMOOPS 7. 0xffe66000 0x00100000
9429 14:44:31.070608 COREBOOT 8. 0xffe64000 0x00002000
9430 14:44:31.070692 IMD small region:
9431 14:44:31.074806 IMD ROOT 0. 0xffffec00 0x00000400
9432 14:44:31.077602 VPD 1. 0xffffeb80 0x0000006c
9433 14:44:31.081028 MMC STATUS 2. 0xffffeb60 0x00000004
9434 14:44:31.087547 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9435 14:44:31.087631 Probing TPM: done!
9436 14:44:31.094623 Connected to device vid:did:rid of 1ae0:0028:00
9437 14:44:31.101973 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9438 14:44:31.104379 Initialized TPM device CR50 revision 0
9439 14:44:31.108428 Checking cr50 for pending updates
9440 14:44:31.113423 Reading cr50 TPM mode
9441 14:44:31.122082 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9442 14:44:31.129111 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9443 14:44:31.168820 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9444 14:44:31.172229 Checking segment from ROM address 0x40100000
9445 14:44:31.175408 Checking segment from ROM address 0x4010001c
9446 14:44:31.183200 Loading segment from ROM address 0x40100000
9447 14:44:31.183277 code (compression=0)
9448 14:44:31.189280 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9449 14:44:31.199386 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9450 14:44:31.199465 it's not compressed!
9451 14:44:31.205976 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9452 14:44:31.209208 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9453 14:44:31.229576 Loading segment from ROM address 0x4010001c
9454 14:44:31.229661 Entry Point 0x80000000
9455 14:44:31.232797 Loaded segments
9456 14:44:31.236424 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9457 14:44:31.242818 Jumping to boot code at 0x80000000(0xffe64000)
9458 14:44:31.249753 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9459 14:44:31.256321 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9460 14:44:31.264213 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9461 14:44:31.267219 Checking segment from ROM address 0x40100000
9462 14:44:31.270711 Checking segment from ROM address 0x4010001c
9463 14:44:31.274098 Loading segment from ROM address 0x40100000
9464 14:44:31.277518 code (compression=1)
9465 14:44:31.283894 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9466 14:44:31.294152 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9467 14:44:31.294258 using LZMA
9468 14:44:31.302242 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9469 14:44:31.309233 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9470 14:44:31.312187 Loading segment from ROM address 0x4010001c
9471 14:44:31.312269 Entry Point 0x54601000
9472 14:44:31.315343 Loaded segments
9473 14:44:31.319151 NOTICE: MT8192 bl31_setup
9474 14:44:31.325989 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9475 14:44:31.329268 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9476 14:44:31.332362 WARNING: region 0:
9477 14:44:31.335839 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 14:44:31.335921 WARNING: region 1:
9479 14:44:31.342902 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9480 14:44:31.345858 WARNING: region 2:
9481 14:44:31.349822 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9482 14:44:31.352558 WARNING: region 3:
9483 14:44:31.356215 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9484 14:44:31.359321 WARNING: region 4:
9485 14:44:31.362789 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9486 14:44:31.366145 WARNING: region 5:
9487 14:44:31.369116 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 14:44:31.372617 WARNING: region 6:
9489 14:44:31.376049 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 14:44:31.376132 WARNING: region 7:
9491 14:44:31.383464 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 14:44:31.389496 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9493 14:44:31.393441 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9494 14:44:31.396235 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9495 14:44:31.399659 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9496 14:44:31.406064 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9497 14:44:31.409715 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9498 14:44:31.416198 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9499 14:44:31.420174 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9500 14:44:31.423083 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9501 14:44:31.430016 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9502 14:44:31.433236 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9503 14:44:31.436436 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9504 14:44:31.443421 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9505 14:44:31.446706 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9506 14:44:31.453846 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9507 14:44:31.456845 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9508 14:44:31.459739 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9509 14:44:31.466631 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9510 14:44:31.470121 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9511 14:44:31.473363 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9512 14:44:31.480057 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9513 14:44:31.483963 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9514 14:44:31.486540 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9515 14:44:31.493612 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9516 14:44:31.496867 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9517 14:44:31.503498 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9518 14:44:31.506863 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9519 14:44:31.510174 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9520 14:44:31.517970 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9521 14:44:31.521849 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9522 14:44:31.526962 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9523 14:44:31.530600 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9524 14:44:31.534158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9525 14:44:31.536880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9526 14:44:31.544087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9527 14:44:31.546954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9528 14:44:31.550834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9529 14:44:31.554409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9530 14:44:31.560311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9531 14:44:31.564272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9532 14:44:31.567643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9533 14:44:31.571074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9534 14:44:31.574014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9535 14:44:31.580873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9536 14:44:31.584364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9537 14:44:31.587515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9538 14:44:31.594334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9539 14:44:31.598261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9540 14:44:31.601140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9541 14:44:31.607684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9542 14:44:31.611223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9543 14:44:31.614321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9544 14:44:31.621228 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9545 14:44:31.624742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9546 14:44:31.632226 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9547 14:44:31.634667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9548 14:44:31.637833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9549 14:44:31.644474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9550 14:44:31.647850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9551 14:44:31.654593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9552 14:44:31.657771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9553 14:44:31.664736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9554 14:44:31.668644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9555 14:44:31.674573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9556 14:44:31.677813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9557 14:44:31.681777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9558 14:44:31.688240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9559 14:44:31.691162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9560 14:44:31.698214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9561 14:44:31.701671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9562 14:44:31.704961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9563 14:44:31.711365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9564 14:44:31.714859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9565 14:44:31.721596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9566 14:44:31.725286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9567 14:44:31.732490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9568 14:44:31.735426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9569 14:44:31.739435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9570 14:44:31.745048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9571 14:44:31.749129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9572 14:44:31.755202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9573 14:44:31.758602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9574 14:44:31.765397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9575 14:44:31.768320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9576 14:44:31.771793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9577 14:44:31.778929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9578 14:44:31.782509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9579 14:44:31.788553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9580 14:44:31.791777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9581 14:44:31.795759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9582 14:44:31.802063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9583 14:44:31.805570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9584 14:44:31.812405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9585 14:44:31.816164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9586 14:44:31.822087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9587 14:44:31.825482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9588 14:44:31.828934 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9589 14:44:31.836047 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9590 14:44:31.838829 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9591 14:44:31.842127 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9592 14:44:31.845678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9593 14:44:31.852832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9594 14:44:31.855614 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9595 14:44:31.859391 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9596 14:44:31.865711 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9597 14:44:31.869445 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9598 14:44:31.876006 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9599 14:44:31.879297 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9600 14:44:31.882558 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9601 14:44:31.889511 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9602 14:44:31.892602 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9603 14:44:31.896280 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9604 14:44:31.902874 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9605 14:44:31.906179 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9606 14:44:31.913616 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9607 14:44:31.916660 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9608 14:44:31.920469 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9609 14:44:31.926916 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9610 14:44:31.930072 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9611 14:44:31.932967 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9612 14:44:31.936361 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9613 14:44:31.943319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9614 14:44:31.946472 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9615 14:44:31.950201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9616 14:44:31.953416 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9617 14:44:31.960071 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9618 14:44:31.963053 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9619 14:44:31.971187 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9620 14:44:31.973643 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9621 14:44:31.976456 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9622 14:44:31.983120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9623 14:44:31.986559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9624 14:44:31.990615 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9625 14:44:31.997172 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9626 14:44:32.000020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9627 14:44:32.006893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9628 14:44:32.009823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9629 14:44:32.013952 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9630 14:44:32.019864 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9631 14:44:32.023279 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9632 14:44:32.030376 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9633 14:44:32.033480 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9634 14:44:32.036766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9635 14:44:32.044072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9636 14:44:32.046974 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9637 14:44:32.050355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9638 14:44:32.057241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9639 14:44:32.060490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9640 14:44:32.067383 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9641 14:44:32.070433 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9642 14:44:32.073835 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9643 14:44:32.080925 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9644 14:44:32.084516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9645 14:44:32.087104 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9646 14:44:32.093934 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9647 14:44:32.097679 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9648 14:44:32.104060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9649 14:44:32.107461 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9650 14:44:32.110834 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9651 14:44:32.117421 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9652 14:44:32.120739 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9653 14:44:32.124181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9654 14:44:32.130848 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9655 14:44:32.134016 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9656 14:44:32.140648 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9657 14:44:32.144252 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9658 14:44:32.147499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9659 14:44:32.153976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9660 14:44:32.157699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9661 14:44:32.164528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9662 14:44:32.167120 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9663 14:44:32.170885 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9664 14:44:32.177275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9665 14:44:32.180644 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9666 14:44:32.184304 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9667 14:44:32.191781 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9668 14:44:32.195266 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9669 14:44:32.201020 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9670 14:44:32.204319 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9671 14:44:32.207800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9672 14:44:32.214038 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9673 14:44:32.217740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9674 14:44:32.224115 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9675 14:44:32.227784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9676 14:44:32.230805 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9677 14:44:32.237507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9678 14:44:32.240954 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9679 14:44:32.244217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9680 14:44:32.250954 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9681 14:44:32.254403 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9682 14:44:32.260921 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9683 14:44:32.264050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9684 14:44:32.268267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9685 14:44:32.274507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9686 14:44:32.277539 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9687 14:44:32.284766 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9688 14:44:32.287331 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9689 14:44:32.294505 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9690 14:44:32.297542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9691 14:44:32.301010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9692 14:44:32.307468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9693 14:44:32.311280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9694 14:44:32.317846 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9695 14:44:32.321506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9696 14:44:32.324142 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9697 14:44:32.330701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9698 14:44:32.334286 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9699 14:44:32.341677 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9700 14:44:32.344375 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9701 14:44:32.347619 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9702 14:44:32.354532 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9703 14:44:32.357601 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9704 14:44:32.364362 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9705 14:44:32.367735 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9706 14:44:32.370892 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9707 14:44:32.377645 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9708 14:44:32.380918 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9709 14:44:32.387551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9710 14:44:32.390889 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9711 14:44:32.397487 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9712 14:44:32.400933 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9713 14:44:32.404881 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9714 14:44:32.411007 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9715 14:44:32.414420 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9716 14:44:32.420814 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9717 14:44:32.424327 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9718 14:44:32.428255 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9719 14:44:32.434885 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9720 14:44:32.438419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9721 14:44:32.440818 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9722 14:44:32.447739 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9723 14:44:32.451304 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9724 14:44:32.454974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9725 14:44:32.457663 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9726 14:44:32.464490 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9727 14:44:32.467910 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9728 14:44:32.471364 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9729 14:44:32.478117 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9730 14:44:32.481150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9731 14:44:32.484558 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9732 14:44:32.491370 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9733 14:44:32.495042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9734 14:44:32.500954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9735 14:44:32.505126 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9736 14:44:32.508176 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9737 14:44:32.516129 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9738 14:44:32.518713 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9739 14:44:32.521337 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9740 14:44:32.528178 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9741 14:44:32.531392 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9742 14:44:32.534480 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9743 14:44:32.541107 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9744 14:44:32.544561 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9745 14:44:32.547945 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9746 14:44:32.555477 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9747 14:44:32.557838 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9748 14:44:32.564771 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9749 14:44:32.568193 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9750 14:44:32.571449 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9751 14:44:32.577911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9752 14:44:32.581788 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9753 14:44:32.585001 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9754 14:44:32.591281 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9755 14:44:32.594996 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9756 14:44:32.598220 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9757 14:44:32.604549 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9758 14:44:32.607911 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9759 14:44:32.614870 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9760 14:44:32.619486 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9761 14:44:32.621389 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9762 14:44:32.624756 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9763 14:44:32.628230 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9764 14:44:32.634804 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9765 14:44:32.638316 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9766 14:44:32.641581 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9767 14:44:32.644951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9768 14:44:32.651226 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9769 14:44:32.655184 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9770 14:44:32.658243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9771 14:44:32.662213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9772 14:44:32.668338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9773 14:44:32.671337 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9774 14:44:32.675021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9775 14:44:32.681595 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9776 14:44:32.685117 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9777 14:44:32.691427 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9778 14:44:32.694826 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9779 14:44:32.698246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9780 14:44:32.705206 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9781 14:44:32.708179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9782 14:44:32.711888 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9783 14:44:32.718495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9784 14:44:32.721801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9785 14:44:32.729386 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9786 14:44:32.732618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9787 14:44:32.735552 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9788 14:44:32.741778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9789 14:44:32.745130 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9790 14:44:32.751722 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9791 14:44:32.755085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9792 14:44:32.758982 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9793 14:44:32.765808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9794 14:44:32.768479 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9795 14:44:32.775401 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9796 14:44:32.778896 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9797 14:44:32.781949 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9798 14:44:32.789076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9799 14:44:32.792043 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9800 14:44:32.798918 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9801 14:44:32.801853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9802 14:44:32.805762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9803 14:44:32.812187 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9804 14:44:32.815681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9805 14:44:32.822438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9806 14:44:32.825240 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9807 14:44:32.828856 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9808 14:44:32.835556 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9809 14:44:32.838751 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9810 14:44:32.845969 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9811 14:44:32.849325 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9812 14:44:32.852328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9813 14:44:32.858776 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9814 14:44:32.862001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9815 14:44:32.868840 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9816 14:44:32.871975 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9817 14:44:32.875794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9818 14:44:32.882416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9819 14:44:32.886377 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9820 14:44:32.892312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9821 14:44:32.895896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9822 14:44:32.899152 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9823 14:44:32.905690 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9824 14:44:32.908986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9825 14:44:32.915592 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9826 14:44:32.919406 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9827 14:44:32.922298 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9828 14:44:32.928936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9829 14:44:32.932536 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9830 14:44:32.939069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9831 14:44:32.942266 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9832 14:44:32.945734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9833 14:44:32.952387 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9834 14:44:32.955921 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9835 14:44:32.962165 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9836 14:44:32.965530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9837 14:44:32.968862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9838 14:44:32.975341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9839 14:44:32.978939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9840 14:44:32.985674 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9841 14:44:32.988935 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9842 14:44:32.992255 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9843 14:44:32.998852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9844 14:44:33.002802 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9845 14:44:33.009168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9846 14:44:33.012744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9847 14:44:33.016052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9848 14:44:33.022683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9849 14:44:33.025648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9850 14:44:33.032132 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9851 14:44:33.035610 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9852 14:44:33.043638 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9853 14:44:33.045568 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9854 14:44:33.048860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9855 14:44:33.055878 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9856 14:44:33.059252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9857 14:44:33.066307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9858 14:44:33.068829 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9859 14:44:33.076329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9860 14:44:33.078802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9861 14:44:33.082298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9862 14:44:33.089012 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9863 14:44:33.092346 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9864 14:44:33.098788 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9865 14:44:33.102265 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9866 14:44:33.108959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9867 14:44:33.112066 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9868 14:44:33.119330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9869 14:44:33.122035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9870 14:44:33.125440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9871 14:44:33.132144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9872 14:44:33.135513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9873 14:44:33.142492 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9874 14:44:33.145355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9875 14:44:33.152970 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9876 14:44:33.155115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9877 14:44:33.158890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9878 14:44:33.165815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9879 14:44:33.168622 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9880 14:44:33.175596 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9881 14:44:33.178531 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9882 14:44:33.185587 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9883 14:44:33.189086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9884 14:44:33.192807 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9885 14:44:33.198742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9886 14:44:33.202592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9887 14:44:33.208820 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9888 14:44:33.212746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9889 14:44:33.219154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9890 14:44:33.222298 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9891 14:44:33.225510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9892 14:44:33.232531 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9893 14:44:33.235614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9894 14:44:33.239156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9895 14:44:33.246040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9896 14:44:33.248874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9897 14:44:33.255489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9898 14:44:33.258937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9899 14:44:33.265916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9900 14:44:33.269139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9901 14:44:33.275864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9902 14:44:33.278935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9903 14:44:33.285932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9904 14:44:33.289898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9905 14:44:33.296388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9906 14:44:33.299460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9907 14:44:33.306091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9908 14:44:33.309764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9909 14:44:33.312483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9910 14:44:33.319474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9911 14:44:33.322774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9912 14:44:33.329549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9913 14:44:33.332555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9914 14:44:33.339403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9915 14:44:33.342262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9916 14:44:33.349573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9917 14:44:33.352314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9918 14:44:33.358938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9919 14:44:33.362679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9920 14:44:33.368897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9921 14:44:33.372824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9922 14:44:33.379661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9923 14:44:33.382424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9924 14:44:33.389123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9925 14:44:33.392951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9926 14:44:33.399037 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9927 14:44:33.399146 INFO: [APUAPC] vio 0
9928 14:44:33.405589 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9929 14:44:33.409429 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9930 14:44:33.412744 INFO: [APUAPC] D0_APC_0: 0x400510
9931 14:44:33.415490 INFO: [APUAPC] D0_APC_1: 0x0
9932 14:44:33.418939 INFO: [APUAPC] D0_APC_2: 0x1540
9933 14:44:33.422817 INFO: [APUAPC] D0_APC_3: 0x0
9934 14:44:33.425896 INFO: [APUAPC] D1_APC_0: 0xffffffff
9935 14:44:33.429007 INFO: [APUAPC] D1_APC_1: 0xffffffff
9936 14:44:33.432672 INFO: [APUAPC] D1_APC_2: 0x3fffff
9937 14:44:33.435544 INFO: [APUAPC] D1_APC_3: 0x0
9938 14:44:33.439033 INFO: [APUAPC] D2_APC_0: 0xffffffff
9939 14:44:33.443213 INFO: [APUAPC] D2_APC_1: 0xffffffff
9940 14:44:33.445532 INFO: [APUAPC] D2_APC_2: 0x3fffff
9941 14:44:33.448948 INFO: [APUAPC] D2_APC_3: 0x0
9942 14:44:33.452025 INFO: [APUAPC] D3_APC_0: 0xffffffff
9943 14:44:33.455986 INFO: [APUAPC] D3_APC_1: 0xffffffff
9944 14:44:33.459154 INFO: [APUAPC] D3_APC_2: 0x3fffff
9945 14:44:33.459237 INFO: [APUAPC] D3_APC_3: 0x0
9946 14:44:33.466107 INFO: [APUAPC] D4_APC_0: 0xffffffff
9947 14:44:33.469207 INFO: [APUAPC] D4_APC_1: 0xffffffff
9948 14:44:33.472407 INFO: [APUAPC] D4_APC_2: 0x3fffff
9949 14:44:33.472514 INFO: [APUAPC] D4_APC_3: 0x0
9950 14:44:33.475451 INFO: [APUAPC] D5_APC_0: 0xffffffff
9951 14:44:33.478763 INFO: [APUAPC] D5_APC_1: 0xffffffff
9952 14:44:33.482395 INFO: [APUAPC] D5_APC_2: 0x3fffff
9953 14:44:33.485390 INFO: [APUAPC] D5_APC_3: 0x0
9954 14:44:33.488892 INFO: [APUAPC] D6_APC_0: 0xffffffff
9955 14:44:33.492758 INFO: [APUAPC] D6_APC_1: 0xffffffff
9956 14:44:33.496118 INFO: [APUAPC] D6_APC_2: 0x3fffff
9957 14:44:33.498775 INFO: [APUAPC] D6_APC_3: 0x0
9958 14:44:33.502360 INFO: [APUAPC] D7_APC_0: 0xffffffff
9959 14:44:33.505649 INFO: [APUAPC] D7_APC_1: 0xffffffff
9960 14:44:33.508882 INFO: [APUAPC] D7_APC_2: 0x3fffff
9961 14:44:33.512965 INFO: [APUAPC] D7_APC_3: 0x0
9962 14:44:33.515321 INFO: [APUAPC] D8_APC_0: 0xffffffff
9963 14:44:33.518705 INFO: [APUAPC] D8_APC_1: 0xffffffff
9964 14:44:33.522164 INFO: [APUAPC] D8_APC_2: 0x3fffff
9965 14:44:33.525337 INFO: [APUAPC] D8_APC_3: 0x0
9966 14:44:33.528733 INFO: [APUAPC] D9_APC_0: 0xffffffff
9967 14:44:33.532604 INFO: [APUAPC] D9_APC_1: 0xffffffff
9968 14:44:33.535805 INFO: [APUAPC] D9_APC_2: 0x3fffff
9969 14:44:33.539243 INFO: [APUAPC] D9_APC_3: 0x0
9970 14:44:33.542842 INFO: [APUAPC] D10_APC_0: 0xffffffff
9971 14:44:33.545856 INFO: [APUAPC] D10_APC_1: 0xffffffff
9972 14:44:33.548905 INFO: [APUAPC] D10_APC_2: 0x3fffff
9973 14:44:33.552607 INFO: [APUAPC] D10_APC_3: 0x0
9974 14:44:33.556008 INFO: [APUAPC] D11_APC_0: 0xffffffff
9975 14:44:33.559103 INFO: [APUAPC] D11_APC_1: 0xffffffff
9976 14:44:33.562002 INFO: [APUAPC] D11_APC_2: 0x3fffff
9977 14:44:33.566035 INFO: [APUAPC] D11_APC_3: 0x0
9978 14:44:33.569331 INFO: [APUAPC] D12_APC_0: 0xffffffff
9979 14:44:33.572090 INFO: [APUAPC] D12_APC_1: 0xffffffff
9980 14:44:33.575618 INFO: [APUAPC] D12_APC_2: 0x3fffff
9981 14:44:33.578979 INFO: [APUAPC] D12_APC_3: 0x0
9982 14:44:33.582366 INFO: [APUAPC] D13_APC_0: 0xffffffff
9983 14:44:33.585796 INFO: [APUAPC] D13_APC_1: 0xffffffff
9984 14:44:33.588863 INFO: [APUAPC] D13_APC_2: 0x3fffff
9985 14:44:33.592387 INFO: [APUAPC] D13_APC_3: 0x0
9986 14:44:33.595922 INFO: [APUAPC] D14_APC_0: 0xffffffff
9987 14:44:33.599470 INFO: [APUAPC] D14_APC_1: 0xffffffff
9988 14:44:33.602957 INFO: [APUAPC] D14_APC_2: 0x3fffff
9989 14:44:33.605708 INFO: [APUAPC] D14_APC_3: 0x0
9990 14:44:33.609768 INFO: [APUAPC] D15_APC_0: 0xffffffff
9991 14:44:33.612229 INFO: [APUAPC] D15_APC_1: 0xffffffff
9992 14:44:33.615931 INFO: [APUAPC] D15_APC_2: 0x3fffff
9993 14:44:33.619266 INFO: [APUAPC] D15_APC_3: 0x0
9994 14:44:33.622268 INFO: [APUAPC] APC_CON: 0x4
9995 14:44:33.625721 INFO: [NOCDAPC] D0_APC_0: 0x0
9996 14:44:33.629669 INFO: [NOCDAPC] D0_APC_1: 0x0
9997 14:44:33.629750 INFO: [NOCDAPC] D1_APC_0: 0x0
9998 14:44:33.632515 INFO: [NOCDAPC] D1_APC_1: 0xfff
9999 14:44:33.636251 INFO: [NOCDAPC] D2_APC_0: 0x0
10000 14:44:33.639724 INFO: [NOCDAPC] D2_APC_1: 0xfff
10001 14:44:33.642398 INFO: [NOCDAPC] D3_APC_0: 0x0
10002 14:44:33.645874 INFO: [NOCDAPC] D3_APC_1: 0xfff
10003 14:44:33.649168 INFO: [NOCDAPC] D4_APC_0: 0x0
10004 14:44:33.652896 INFO: [NOCDAPC] D4_APC_1: 0xfff
10005 14:44:33.655904 INFO: [NOCDAPC] D5_APC_0: 0x0
10006 14:44:33.659275 INFO: [NOCDAPC] D5_APC_1: 0xfff
10007 14:44:33.659358 INFO: [NOCDAPC] D6_APC_0: 0x0
10008 14:44:33.662210 INFO: [NOCDAPC] D6_APC_1: 0xfff
10009 14:44:33.665589 INFO: [NOCDAPC] D7_APC_0: 0x0
10010 14:44:33.670080 INFO: [NOCDAPC] D7_APC_1: 0xfff
10011 14:44:33.672281 INFO: [NOCDAPC] D8_APC_0: 0x0
10012 14:44:33.675876 INFO: [NOCDAPC] D8_APC_1: 0xfff
10013 14:44:33.679062 INFO: [NOCDAPC] D9_APC_0: 0x0
10014 14:44:33.682251 INFO: [NOCDAPC] D9_APC_1: 0xfff
10015 14:44:33.686050 INFO: [NOCDAPC] D10_APC_0: 0x0
10016 14:44:33.689135 INFO: [NOCDAPC] D10_APC_1: 0xfff
10017 14:44:33.692251 INFO: [NOCDAPC] D11_APC_0: 0x0
10018 14:44:33.695599 INFO: [NOCDAPC] D11_APC_1: 0xfff
10019 14:44:33.695681 INFO: [NOCDAPC] D12_APC_0: 0x0
10020 14:44:33.698963 INFO: [NOCDAPC] D12_APC_1: 0xfff
10021 14:44:33.702028 INFO: [NOCDAPC] D13_APC_0: 0x0
10022 14:44:33.706090 INFO: [NOCDAPC] D13_APC_1: 0xfff
10023 14:44:33.709046 INFO: [NOCDAPC] D14_APC_0: 0x0
10024 14:44:33.712219 INFO: [NOCDAPC] D14_APC_1: 0xfff
10025 14:44:33.715687 INFO: [NOCDAPC] D15_APC_0: 0x0
10026 14:44:33.719022 INFO: [NOCDAPC] D15_APC_1: 0xfff
10027 14:44:33.722108 INFO: [NOCDAPC] APC_CON: 0x4
10028 14:44:33.725338 INFO: [APUAPC] set_apusys_apc done
10029 14:44:33.729066 INFO: [DEVAPC] devapc_init done
10030 14:44:33.732238 INFO: GICv3 without legacy support detected.
10031 14:44:33.735992 INFO: ARM GICv3 driver initialized in EL3
10032 14:44:33.738959 INFO: Maximum SPI INTID supported: 639
10033 14:44:33.746131 INFO: BL31: Initializing runtime services
10034 14:44:33.749023 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10035 14:44:33.752350 INFO: SPM: enable CPC mode
10036 14:44:33.758922 INFO: mcdi ready for mcusys-off-idle and system suspend
10037 14:44:33.762592 INFO: BL31: Preparing for EL3 exit to normal world
10038 14:44:33.765705 INFO: Entry point address = 0x80000000
10039 14:44:33.768846 INFO: SPSR = 0x8
10040 14:44:33.773861
10041 14:44:33.773943
10042 14:44:33.774008
10043 14:44:33.777181 Starting depthcharge on Spherion...
10044 14:44:33.777263
10045 14:44:33.777327 Wipe memory regions:
10046 14:44:33.777388
10047 14:44:33.778040 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10048 14:44:33.778140 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10049 14:44:33.778226 Setting prompt string to ['asurada:']
10050 14:44:33.778303 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10051 14:44:33.781057 [0x00000040000000, 0x00000054600000)
10052 14:44:33.902495
10053 14:44:33.902614 [0x00000054660000, 0x00000080000000)
10054 14:44:34.163124
10055 14:44:34.163305 [0x000000821a7280, 0x000000ffe64000)
10056 14:44:34.908047
10057 14:44:34.908189 [0x00000100000000, 0x00000240000000)
10058 14:44:36.798168
10059 14:44:36.801534 Initializing XHCI USB controller at 0x11200000.
10060 14:44:37.839446
10061 14:44:37.842495 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10062 14:44:37.842605
10063 14:44:37.842703
10064 14:44:37.843019 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 14:44:37.943384 asurada: tftpboot 192.168.201.1 14167004/tftp-deploy-z24ttcqp/kernel/image.itb 14167004/tftp-deploy-z24ttcqp/kernel/cmdline
10067 14:44:37.943536 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 14:44:37.943689 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 14:44:37.948244 tftpboot 192.168.201.1 14167004/tftp-deploy-z24ttcqp/kernel/image.itp-deploy-z24ttcqp/kernel/cmdline
10070 14:44:37.948351
10071 14:44:37.948451 Waiting for link
10072 14:44:38.109270
10073 14:44:38.109411 R8152: Initializing
10074 14:44:38.109481
10075 14:44:38.112044 Version 6 (ocp_data = 5c30)
10076 14:44:38.112143
10077 14:44:38.115017 R8152: Done initializing
10078 14:44:38.115099
10079 14:44:38.115163 Adding net device
10080 14:44:40.018599
10081 14:44:40.019201 done.
10082 14:44:40.019665
10083 14:44:40.020023 MAC: 00:24:32:30:78:52
10084 14:44:40.020363
10085 14:44:40.021523 Sending DHCP discover... done.
10086 14:44:40.021995
10087 14:44:40.025453 Waiting for reply... done.
10088 14:44:40.025923
10089 14:44:40.028026 Sending DHCP request... done.
10090 14:44:40.028495
10091 14:44:40.033354 Waiting for reply... done.
10092 14:44:40.033825
10093 14:44:40.034213 My ip is 192.168.201.14
10094 14:44:40.034595
10095 14:44:40.036906 The DHCP server ip is 192.168.201.1
10096 14:44:40.037513
10097 14:44:40.043549 TFTP server IP predefined by user: 192.168.201.1
10098 14:44:40.044114
10099 14:44:40.049936 Bootfile predefined by user: 14167004/tftp-deploy-z24ttcqp/kernel/image.itb
10100 14:44:40.050409
10101 14:44:40.050782 Sending tftp read request... done.
10102 14:44:40.053090
10103 14:44:40.057147 Waiting for the transfer...
10104 14:44:40.057722
10105 14:44:40.760705 00000000 ################################################################
10106 14:44:40.761323
10107 14:44:41.469257 00080000 ################################################################
10108 14:44:41.469770
10109 14:44:42.173603 00100000 ################################################################
10110 14:44:42.174267
10111 14:44:42.894093 00180000 ################################################################
10112 14:44:42.894640
10113 14:44:43.594266 00200000 ################################################################
10114 14:44:43.594784
10115 14:44:44.284776 00280000 ################################################################
10116 14:44:44.285316
10117 14:44:44.997842 00300000 ################################################################
10118 14:44:44.998392
10119 14:44:45.696630 00380000 ################################################################
10120 14:44:45.697168
10121 14:44:46.407980 00400000 ################################################################
10122 14:44:46.408543
10123 14:44:47.130844 00480000 ################################################################
10124 14:44:47.131375
10125 14:44:47.829209 00500000 ################################################################
10126 14:44:47.829746
10127 14:44:48.543319 00580000 ################################################################
10128 14:44:48.543984
10129 14:44:49.252247 00600000 ################################################################
10130 14:44:49.252788
10131 14:44:49.960935 00680000 ################################################################
10132 14:44:49.961487
10133 14:44:50.667062 00700000 ################################################################
10134 14:44:50.667202
10135 14:44:51.228228 00780000 ################################################################
10136 14:44:51.228365
10137 14:44:51.795482 00800000 ################################################################
10138 14:44:51.795624
10139 14:44:52.368148 00880000 ################################################################
10140 14:44:52.368286
10141 14:44:52.936894 00900000 ################################################################
10142 14:44:52.937084
10143 14:44:53.537242 00980000 ################################################################
10144 14:44:53.537454
10145 14:44:54.106413 00a00000 ################################################################
10146 14:44:54.106554
10147 14:44:54.675781 00a80000 ################################################################
10148 14:44:54.675921
10149 14:44:55.258744 00b00000 ################################################################
10150 14:44:55.258922
10151 14:44:55.833688 00b80000 ################################################################
10152 14:44:55.833828
10153 14:44:56.423942 00c00000 ################################################################
10154 14:44:56.424098
10155 14:44:57.022965 00c80000 ################################################################
10156 14:44:57.023118
10157 14:44:57.603169 00d00000 ################################################################
10158 14:44:57.603328
10159 14:44:58.203252 00d80000 ################################################################
10160 14:44:58.203425
10161 14:44:58.794865 00e00000 ################################################################
10162 14:44:58.795016
10163 14:44:59.398706 00e80000 ################################################################
10164 14:44:59.398868
10165 14:44:59.991907 00f00000 ################################################################
10166 14:44:59.992072
10167 14:45:00.589545 00f80000 ################################################################
10168 14:45:00.589716
10169 14:45:01.182037 01000000 ################################################################
10170 14:45:01.182211
10171 14:45:01.758423 01080000 ################################################################
10172 14:45:01.758588
10173 14:45:02.338288 01100000 ################################################################
10174 14:45:02.338442
10175 14:45:02.926541 01180000 ################################################################
10176 14:45:02.926704
10177 14:45:03.512090 01200000 ################################################################
10178 14:45:03.512251
10179 14:45:04.112543 01280000 ################################################################
10180 14:45:04.112706
10181 14:45:04.706497 01300000 ################################################################
10182 14:45:04.706662
10183 14:45:05.301662 01380000 ################################################################
10184 14:45:05.301829
10185 14:45:05.891748 01400000 ################################################################
10186 14:45:05.891904
10187 14:45:06.492072 01480000 ################################################################
10188 14:45:06.492237
10189 14:45:07.071817 01500000 ################################################################
10190 14:45:07.071983
10191 14:45:07.672128 01580000 ################################################################
10192 14:45:07.672280
10193 14:45:08.267013 01600000 ################################################################
10194 14:45:08.267173
10195 14:45:08.860204 01680000 ################################################################
10196 14:45:08.860366
10197 14:45:09.460477 01700000 ################################################################
10198 14:45:09.460643
10199 14:45:10.063850 01780000 ################################################################
10200 14:45:10.064014
10201 14:45:10.660957 01800000 ################################################################
10202 14:45:10.661118
10203 14:45:11.263759 01880000 ################################################################
10204 14:45:11.263915
10205 14:45:11.872020 01900000 ################################################################
10206 14:45:11.872544
10207 14:45:12.505472 01980000 ################################################################
10208 14:45:12.505972
10209 14:45:13.210592 01a00000 ################################################################
10210 14:45:13.211117
10211 14:45:13.923118 01a80000 ################################################################
10212 14:45:13.923651
10213 14:45:14.613851 01b00000 ################################################################
10214 14:45:14.614375
10215 14:45:15.289136 01b80000 ################################################################
10216 14:45:15.289687
10217 14:45:15.996009 01c00000 ################################################################
10218 14:45:15.996541
10219 14:45:16.693252 01c80000 ################################################################
10220 14:45:16.693819
10221 14:45:17.410830 01d00000 ################################################################
10222 14:45:17.411467
10223 14:45:18.124539 01d80000 ################################################################
10224 14:45:18.125184
10225 14:45:18.820323 01e00000 ################################################################
10226 14:45:18.820845
10227 14:45:19.501766 01e80000 ################################################################
10228 14:45:19.502278
10229 14:45:20.150584 01f00000 ################################################################
10230 14:45:20.151089
10231 14:45:20.793833 01f80000 ################################################################
10232 14:45:20.794029
10233 14:45:21.483189 02000000 ################################################################
10234 14:45:21.483784
10235 14:45:22.183773 02080000 ################################################################
10236 14:45:22.184304
10237 14:45:22.845735 02100000 ################################################################
10238 14:45:22.845884
10239 14:45:23.373956 02180000 ################################################################
10240 14:45:23.374104
10241 14:45:23.912784 02200000 ################################################################
10242 14:45:23.912934
10243 14:45:24.429375 02280000 ################################################################
10244 14:45:24.429531
10245 14:45:24.946261 02300000 ################################################################
10246 14:45:24.946412
10247 14:45:25.474435 02380000 ################################################################
10248 14:45:25.474580
10249 14:45:25.996093 02400000 ################################################################
10250 14:45:25.996231
10251 14:45:26.521350 02480000 ################################################################
10252 14:45:26.521502
10253 14:45:27.041791 02500000 ################################################################
10254 14:45:27.041929
10255 14:45:27.578265 02580000 ################################################################
10256 14:45:27.578409
10257 14:45:28.098392 02600000 ################################################################
10258 14:45:28.098528
10259 14:45:28.626085 02680000 ################################################################
10260 14:45:28.626220
10261 14:45:29.143955 02700000 ################################################################
10262 14:45:29.144100
10263 14:45:29.683413 02780000 ################################################################
10264 14:45:29.683549
10265 14:45:30.209894 02800000 ################################################################
10266 14:45:30.210031
10267 14:45:30.738166 02880000 ################################################################
10268 14:45:30.738300
10269 14:45:31.271230 02900000 ################################################################
10270 14:45:31.271418
10271 14:45:31.804706 02980000 ################################################################
10272 14:45:31.804852
10273 14:45:32.360206 02a00000 ################################################################
10274 14:45:32.360339
10275 14:45:32.888313 02a80000 ################################################################
10276 14:45:32.888445
10277 14:45:33.406284 02b00000 ################################################################
10278 14:45:33.406429
10279 14:45:33.927169 02b80000 ################################################################
10280 14:45:33.927322
10281 14:45:34.446722 02c00000 ################################################################
10282 14:45:34.446867
10283 14:45:34.973606 02c80000 ################################################################
10284 14:45:34.973753
10285 14:45:35.499158 02d00000 ################################################################
10286 14:45:35.499301
10287 14:45:36.016619 02d80000 ################################################################
10288 14:45:36.016792
10289 14:45:36.546733 02e00000 ################################################################
10290 14:45:36.546875
10291 14:45:37.063359 02e80000 ################################################################
10292 14:45:37.063529
10293 14:45:37.584920 02f00000 ################################################################
10294 14:45:37.585074
10295 14:45:38.106126 02f80000 ################################################################
10296 14:45:38.106268
10297 14:45:38.632385 03000000 ################################################################
10298 14:45:38.632559
10299 14:45:39.173931 03080000 ################################################################
10300 14:45:39.174100
10301 14:45:39.703451 03100000 ################################################################
10302 14:45:39.703591
10303 14:45:40.291314 03180000 ################################################################
10304 14:45:40.291452
10305 14:45:40.894060 03200000 ################################################################
10306 14:45:40.894561
10307 14:45:41.553873 03280000 ################################################################
10308 14:45:41.554026
10309 14:45:42.140229 03300000 ################################################################
10310 14:45:42.140416
10311 14:45:42.482601 03380000 ####################################### done.
10312 14:45:42.482733
10313 14:45:42.485985 The bootfile was 54318982 bytes long.
10314 14:45:42.486069
10315 14:45:42.488823 Sending tftp read request... done.
10316 14:45:42.488954
10317 14:45:42.489051 Waiting for the transfer...
10318 14:45:42.489128
10319 14:45:42.492290 00000000 # done.
10320 14:45:42.492366
10321 14:45:42.498912 Command line loaded dynamically from TFTP file: 14167004/tftp-deploy-z24ttcqp/kernel/cmdline
10322 14:45:42.498999
10323 14:45:42.512351 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10324 14:45:42.512440
10325 14:45:42.515663 Loading FIT.
10326 14:45:42.515746
10327 14:45:42.519113 Image ramdisk-1 has 41209071 bytes.
10328 14:45:42.519198
10329 14:45:42.519263 Image fdt-1 has 47258 bytes.
10330 14:45:42.519325
10331 14:45:42.522398 Image kernel-1 has 13060619 bytes.
10332 14:45:42.522482
10333 14:45:42.532161 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 14:45:42.532289
10335 14:45:42.549256 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 14:45:42.549358
10337 14:45:42.555904 Choosing best match conf-1 for compat google,spherion-rev2.
10338 14:45:42.559670
10339 14:45:42.564222 Connected to device vid:did:rid of 1ae0:0028:00
10340 14:45:42.570811
10341 14:45:42.574026 tpm_get_response: command 0x17b, return code 0x0
10342 14:45:42.574111
10343 14:45:42.577240 ec_init: CrosEC protocol v3 supported (256, 248)
10344 14:45:42.583116
10345 14:45:42.585746 tpm_cleanup: add release locality here.
10346 14:45:42.585830
10347 14:45:42.585900 Shutting down all USB controllers.
10348 14:45:42.585968
10349 14:45:42.589455 Removing current net device
10350 14:45:42.589539
10351 14:45:42.596013 Exiting depthcharge with code 4 at timestamp: 98220480
10352 14:45:42.596099
10353 14:45:42.600290 LZMA decompressing kernel-1 to 0x821a6718
10354 14:45:42.600374
10355 14:45:42.602564 LZMA decompressing kernel-1 to 0x40000000
10356 14:45:44.214062
10357 14:45:44.214215 jumping to kernel
10358 14:45:44.214731 end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10359 14:45:44.214835 start: 2.2.5 auto-login-action (timeout 00:03:15) [common]
10360 14:45:44.214920 Setting prompt string to ['Linux version [0-9]']
10361 14:45:44.214994 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 14:45:44.215064 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 14:45:44.297906
10364 14:45:44.302182 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 14:45:44.304523 start: 2.2.5.1 login-action (timeout 00:03:15) [common]
10366 14:45:44.304648 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 14:45:44.304749 Setting prompt string to []
10368 14:45:44.304856 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 14:45:44.304959 Using line separator: #'\n'#
10370 14:45:44.305062 No login prompt set.
10371 14:45:44.305151 Parsing kernel messages
10372 14:45:44.305284 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 14:45:44.305471 [login-action] Waiting for messages, (timeout 00:03:15)
10374 14:45:44.305567 Waiting using forced prompt support (timeout 00:01:37)
10375 14:45:44.323705 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10376 14:45:44.326958 [ 0.000000] random: crng init done
10377 14:45:44.333819 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10378 14:45:44.333900 [ 0.000000] efi: UEFI not found.
10379 14:45:44.343860 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10380 14:45:44.350888 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10381 14:45:44.360711 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10382 14:45:44.371334 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10383 14:45:44.377102 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10384 14:45:44.380756 [ 0.000000] printk: bootconsole [mtk8250] enabled
10385 14:45:44.389058 [ 0.000000] NUMA: No NUMA configuration found
10386 14:45:44.396010 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10387 14:45:44.402087 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10388 14:45:44.402206 [ 0.000000] Zone ranges:
10389 14:45:44.409233 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10390 14:45:44.412915 [ 0.000000] DMA32 empty
10391 14:45:44.418840 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10392 14:45:44.422575 [ 0.000000] Movable zone start for each node
10393 14:45:44.425463 [ 0.000000] Early memory node ranges
10394 14:45:44.432861 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10395 14:45:44.439117 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10396 14:45:44.446048 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10397 14:45:44.452726 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10398 14:45:44.459658 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10399 14:45:44.465814 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10400 14:45:44.521258 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10401 14:45:44.527881 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10402 14:45:44.534492 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10403 14:45:44.537662 [ 0.000000] psci: probing for conduit method from DT.
10404 14:45:44.544254 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10405 14:45:44.547729 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10406 14:45:44.554456 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10407 14:45:44.557501 [ 0.000000] psci: SMC Calling Convention v1.2
10408 14:45:44.564069 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10409 14:45:44.568125 [ 0.000000] Detected VIPT I-cache on CPU0
10410 14:45:44.574358 [ 0.000000] CPU features: detected: GIC system register CPU interface
10411 14:45:44.581651 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10412 14:45:44.588066 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10413 14:45:44.594744 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10414 14:45:44.601497 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10415 14:45:44.607868 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10416 14:45:44.614324 [ 0.000000] alternatives: applying boot alternatives
10417 14:45:44.617357 [ 0.000000] Fallback order for Node 0: 0
10418 14:45:44.624585 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10419 14:45:44.628114 [ 0.000000] Policy zone: Normal
10420 14:45:44.644840 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10421 14:45:44.654108 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10422 14:45:44.665593 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10423 14:45:44.675487 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10424 14:45:44.682330 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10425 14:45:44.685251 <6>[ 0.000000] software IO TLB: area num 8.
10426 14:45:44.742794 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10427 14:45:44.890847 <6>[ 0.000000] Memory: 7923944K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428824K reserved, 32768K cma-reserved)
10428 14:45:44.897396 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10429 14:45:44.904271 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10430 14:45:44.907159 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10431 14:45:44.914375 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10432 14:45:44.921472 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10433 14:45:44.923913 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10434 14:45:44.933860 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10435 14:45:44.940864 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10436 14:45:44.943781 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10437 14:45:44.953439 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10438 14:45:44.955000 <6>[ 0.000000] GICv3: 608 SPIs implemented
10439 14:45:44.961287 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10440 14:45:44.965426 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10441 14:45:44.968439 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10442 14:45:44.977999 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10443 14:45:44.988025 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10444 14:45:45.001637 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10445 14:45:45.007841 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10446 14:45:45.016940 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10447 14:45:45.030889 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10448 14:45:45.038060 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10449 14:45:45.044157 <6>[ 0.009184] Console: colour dummy device 80x25
10450 14:45:45.053842 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10451 14:45:45.057472 <6>[ 0.024418] pid_max: default: 32768 minimum: 301
10452 14:45:45.064248 <6>[ 0.029319] LSM: Security Framework initializing
10453 14:45:45.071077 <6>[ 0.034258] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 14:45:45.080571 <6>[ 0.042078] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 14:45:45.086961 <6>[ 0.051503] cblist_init_generic: Setting adjustable number of callback queues.
10456 14:45:45.093451 <6>[ 0.058994] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 14:45:45.103504 <6>[ 0.065333] cblist_init_generic: Setting adjustable number of callback queues.
10458 14:45:45.107311 <6>[ 0.072759] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 14:45:45.113694 <6>[ 0.079161] rcu: Hierarchical SRCU implementation.
10460 14:45:45.120393 <6>[ 0.084208] rcu: Max phase no-delay instances is 1000.
10461 14:45:45.126645 <6>[ 0.091232] EFI services will not be available.
10462 14:45:45.130316 <6>[ 0.096189] smp: Bringing up secondary CPUs ...
10463 14:45:45.137761 <6>[ 0.101237] Detected VIPT I-cache on CPU1
10464 14:45:45.145102 <6>[ 0.101308] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10465 14:45:45.151532 <6>[ 0.101339] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10466 14:45:45.154836 <6>[ 0.101679] Detected VIPT I-cache on CPU2
10467 14:45:45.161748 <6>[ 0.101730] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10468 14:45:45.168156 <6>[ 0.101748] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10469 14:45:45.175541 <6>[ 0.102011] Detected VIPT I-cache on CPU3
10470 14:45:45.182065 <6>[ 0.102059] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10471 14:45:45.187912 <6>[ 0.102073] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10472 14:45:45.191375 <6>[ 0.102378] CPU features: detected: Spectre-v4
10473 14:45:45.198695 <6>[ 0.102384] CPU features: detected: Spectre-BHB
10474 14:45:45.201447 <6>[ 0.102389] Detected PIPT I-cache on CPU4
10475 14:45:45.208231 <6>[ 0.102446] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10476 14:45:45.214535 <6>[ 0.102462] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10477 14:45:45.218113 <6>[ 0.102757] Detected PIPT I-cache on CPU5
10478 14:45:45.228064 <6>[ 0.102818] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10479 14:45:45.234910 <6>[ 0.102834] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10480 14:45:45.239175 <6>[ 0.103116] Detected PIPT I-cache on CPU6
10481 14:45:45.245223 <6>[ 0.103181] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10482 14:45:45.251286 <6>[ 0.103196] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10483 14:45:45.254881 <6>[ 0.103493] Detected PIPT I-cache on CPU7
10484 14:45:45.265332 <6>[ 0.103558] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10485 14:45:45.271021 <6>[ 0.103574] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10486 14:45:45.274101 <6>[ 0.103621] smp: Brought up 1 node, 8 CPUs
10487 14:45:45.277753 <6>[ 0.245027] SMP: Total of 8 processors activated.
10488 14:45:45.284349 <6>[ 0.249948] CPU features: detected: 32-bit EL0 Support
10489 14:45:45.294244 <6>[ 0.255311] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10490 14:45:45.301330 <6>[ 0.264112] CPU features: detected: Common not Private translations
10491 14:45:45.303989 <6>[ 0.270588] CPU features: detected: CRC32 instructions
10492 14:45:45.310822 <6>[ 0.275939] CPU features: detected: RCpc load-acquire (LDAPR)
10493 14:45:45.317246 <6>[ 0.281899] CPU features: detected: LSE atomic instructions
10494 14:45:45.324150 <6>[ 0.287681] CPU features: detected: Privileged Access Never
10495 14:45:45.327344 <6>[ 0.293460] CPU features: detected: RAS Extension Support
10496 14:45:45.334308 <6>[ 0.299069] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10497 14:45:45.340805 <6>[ 0.306292] CPU: All CPU(s) started at EL2
10498 14:45:45.343986 <6>[ 0.310609] alternatives: applying system-wide alternatives
10499 14:45:45.355797 <6>[ 0.321462] devtmpfs: initialized
10500 14:45:45.368596 <6>[ 0.330430] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10501 14:45:45.377855 <6>[ 0.340384] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10502 14:45:45.384794 <6>[ 0.348404] pinctrl core: initialized pinctrl subsystem
10503 14:45:45.388112 <6>[ 0.355051] DMI not present or invalid.
10504 14:45:45.394251 <6>[ 0.359459] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10505 14:45:45.404237 <6>[ 0.366317] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10506 14:45:45.410759 <6>[ 0.373890] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10507 14:45:45.420989 <6>[ 0.382109] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10508 14:45:45.424044 <6>[ 0.390351] audit: initializing netlink subsys (disabled)
10509 14:45:45.434272 <5>[ 0.396041] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10510 14:45:45.440862 <6>[ 0.396739] thermal_sys: Registered thermal governor 'step_wise'
10511 14:45:45.447275 <6>[ 0.404008] thermal_sys: Registered thermal governor 'power_allocator'
10512 14:45:45.451273 <6>[ 0.410266] cpuidle: using governor menu
10513 14:45:45.457909 <6>[ 0.421226] NET: Registered PF_QIPCRTR protocol family
10514 14:45:45.463914 <6>[ 0.426709] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10515 14:45:45.467437 <6>[ 0.433813] ASID allocator initialised with 32768 entries
10516 14:45:45.475746 <6>[ 0.440393] Serial: AMBA PL011 UART driver
10517 14:45:45.483406 <4>[ 0.449118] Trying to register duplicate clock ID: 134
10518 14:45:45.542839 <6>[ 0.511933] KASLR enabled
10519 14:45:45.558077 <6>[ 0.519818] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10520 14:45:45.564101 <6>[ 0.526830] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10521 14:45:45.571470 <6>[ 0.533319] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10522 14:45:45.577768 <6>[ 0.540325] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10523 14:45:45.584725 <6>[ 0.546815] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10524 14:45:45.590661 <6>[ 0.553816] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10525 14:45:45.597512 <6>[ 0.560305] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10526 14:45:45.604442 <6>[ 0.567308] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10527 14:45:45.607195 <6>[ 0.574832] ACPI: Interpreter disabled.
10528 14:45:45.616564 <6>[ 0.581271] iommu: Default domain type: Translated
10529 14:45:45.622419 <6>[ 0.586382] iommu: DMA domain TLB invalidation policy: strict mode
10530 14:45:45.625895 <5>[ 0.593041] SCSI subsystem initialized
10531 14:45:45.632772 <6>[ 0.597210] usbcore: registered new interface driver usbfs
10532 14:45:45.638919 <6>[ 0.602944] usbcore: registered new interface driver hub
10533 14:45:45.642436 <6>[ 0.608496] usbcore: registered new device driver usb
10534 14:45:45.648912 <6>[ 0.614593] pps_core: LinuxPPS API ver. 1 registered
10535 14:45:45.658579 <6>[ 0.619782] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10536 14:45:45.662093 <6>[ 0.629128] PTP clock support registered
10537 14:45:45.665763 <6>[ 0.633371] EDAC MC: Ver: 3.0.0
10538 14:45:45.673259 <6>[ 0.638527] FPGA manager framework
10539 14:45:45.676153 <6>[ 0.642205] Advanced Linux Sound Architecture Driver Initialized.
10540 14:45:45.680157 <6>[ 0.648987] vgaarb: loaded
10541 14:45:45.687133 <6>[ 0.652145] clocksource: Switched to clocksource arch_sys_counter
10542 14:45:45.693184 <5>[ 0.658586] VFS: Disk quotas dquot_6.6.0
10543 14:45:45.700430 <6>[ 0.662768] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10544 14:45:45.703279 <6>[ 0.669958] pnp: PnP ACPI: disabled
10545 14:45:45.711099 <6>[ 0.676660] NET: Registered PF_INET protocol family
10546 14:45:45.722349 <6>[ 0.682262] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10547 14:45:45.732751 <6>[ 0.694599] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10548 14:45:45.742634 <6>[ 0.703414] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10549 14:45:45.748699 <6>[ 0.711386] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10550 14:45:45.755330 <6>[ 0.720088] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10551 14:45:45.767270 <6>[ 0.729837] TCP: Hash tables configured (established 65536 bind 65536)
10552 14:45:45.773795 <6>[ 0.736704] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 14:45:45.780641 <6>[ 0.743904] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 14:45:45.787855 <6>[ 0.751612] NET: Registered PF_UNIX/PF_LOCAL protocol family
10555 14:45:45.794677 <6>[ 0.757765] RPC: Registered named UNIX socket transport module.
10556 14:45:45.797522 <6>[ 0.763921] RPC: Registered udp transport module.
10557 14:45:45.804697 <6>[ 0.768855] RPC: Registered tcp transport module.
10558 14:45:45.810707 <6>[ 0.773789] RPC: Registered tcp NFSv4.1 backchannel transport module.
10559 14:45:45.814684 <6>[ 0.780454] PCI: CLS 0 bytes, default 64
10560 14:45:45.817520 <6>[ 0.784765] Unpacking initramfs...
10561 14:45:45.839905 <6>[ 0.800716] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10562 14:45:45.848633 <6>[ 0.809348] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10563 14:45:45.852641 <6>[ 0.818173] kvm [1]: IPA Size Limit: 40 bits
10564 14:45:45.858282 <6>[ 0.822700] kvm [1]: GICv3: no GICV resource entry
10565 14:45:45.861724 <6>[ 0.827723] kvm [1]: disabling GICv2 emulation
10566 14:45:45.868908 <6>[ 0.832408] kvm [1]: GIC system register CPU interface enabled
10567 14:45:45.872275 <6>[ 0.838563] kvm [1]: vgic interrupt IRQ18
10568 14:45:45.878540 <6>[ 0.842909] kvm [1]: VHE mode initialized successfully
10569 14:45:45.881881 <5>[ 0.849301] Initialise system trusted keyrings
10570 14:45:45.888272 <6>[ 0.854099] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10571 14:45:45.898169 <6>[ 0.864164] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10572 14:45:45.905283 <5>[ 0.870569] NFS: Registering the id_resolver key type
10573 14:45:45.908128 <5>[ 0.875874] Key type id_resolver registered
10574 14:45:45.915171 <5>[ 0.880290] Key type id_legacy registered
10575 14:45:45.921434 <6>[ 0.884573] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10576 14:45:45.928271 <6>[ 0.891490] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10577 14:45:45.935821 <6>[ 0.899208] 9p: Installing v9fs 9p2000 file system support
10578 14:45:45.971962 <5>[ 0.937675] Key type asymmetric registered
10579 14:45:45.975544 <5>[ 0.942008] Asymmetric key parser 'x509' registered
10580 14:45:45.985769 <6>[ 0.947151] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10581 14:45:45.988370 <6>[ 0.954783] io scheduler mq-deadline registered
10582 14:45:45.991892 <6>[ 0.959553] io scheduler kyber registered
10583 14:45:46.010945 <6>[ 0.976594] EINJ: ACPI disabled.
10584 14:45:46.045085 <4>[ 1.003194] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 14:45:46.055285 <4>[ 1.013816] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 14:45:46.069598 <6>[ 1.035076] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10587 14:45:46.078048 <6>[ 1.043163] printk: console [ttyS0] disabled
10588 14:45:46.105672 <6>[ 1.067797] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10589 14:45:46.112000 <6>[ 1.077291] printk: console [ttyS0] enabled
10590 14:45:46.116322 <6>[ 1.077291] printk: console [ttyS0] enabled
10591 14:45:46.119305 <6>[ 1.086186] printk: bootconsole [mtk8250] disabled
10592 14:45:46.125609 <6>[ 1.086186] printk: bootconsole [mtk8250] disabled
10593 14:45:46.132164 <6>[ 1.097437] SuperH (H)SCI(F) driver initialized
10594 14:45:46.135437 <6>[ 1.102711] msm_serial: driver initialized
10595 14:45:46.149564 <6>[ 1.111661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10596 14:45:46.159307 <6>[ 1.120208] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10597 14:45:46.166102 <6>[ 1.128750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10598 14:45:46.175999 <6>[ 1.137378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10599 14:45:46.182724 <6>[ 1.146085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10600 14:45:46.192409 <6>[ 1.154808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10601 14:45:46.202579 <6>[ 1.163349] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10602 14:45:46.209251 <6>[ 1.172172] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10603 14:45:46.219162 <6>[ 1.180718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10604 14:45:46.230492 <6>[ 1.196374] loop: module loaded
10605 14:45:46.237720 <6>[ 1.202459] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10606 14:45:46.260214 <4>[ 1.225813] mtk-pmic-keys: Failed to locate of_node [id: -1]
10607 14:45:46.268246 <6>[ 1.232609] megasas: 07.719.03.00-rc1
10608 14:45:46.276937 <6>[ 1.242344] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10609 14:45:46.285916 <6>[ 1.251517] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10610 14:45:46.303231 <6>[ 1.268006] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10611 14:45:46.357995 <6>[ 1.317165] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10612 14:45:47.533083 <6>[ 2.499092] Freeing initrd memory: 40240K
10613 14:45:47.546530 <6>[ 2.510651] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10614 14:45:47.556206 <6>[ 2.521784] tun: Universal TUN/TAP device driver, 1.6
10615 14:45:47.559321 <6>[ 2.527853] thunder_xcv, ver 1.0
10616 14:45:47.562713 <6>[ 2.531363] thunder_bgx, ver 1.0
10617 14:45:47.565998 <6>[ 2.534860] nicpf, ver 1.0
10618 14:45:47.576180 <6>[ 2.538891] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10619 14:45:47.579378 <6>[ 2.546367] hns3: Copyright (c) 2017 Huawei Corporation.
10620 14:45:47.584352 <6>[ 2.551958] hclge is initializing
10621 14:45:47.589513 <6>[ 2.555540] e1000: Intel(R) PRO/1000 Network Driver
10622 14:45:47.596133 <6>[ 2.560670] e1000: Copyright (c) 1999-2006 Intel Corporation.
10623 14:45:47.599575 <6>[ 2.566683] e1000e: Intel(R) PRO/1000 Network Driver
10624 14:45:47.606827 <6>[ 2.571899] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10625 14:45:47.613294 <6>[ 2.578083] igb: Intel(R) Gigabit Ethernet Network Driver
10626 14:45:47.619495 <6>[ 2.583732] igb: Copyright (c) 2007-2014 Intel Corporation.
10627 14:45:47.626563 <6>[ 2.589572] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10628 14:45:47.633341 <6>[ 2.596090] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 14:45:47.636122 <6>[ 2.602551] sky2: driver version 1.30
10630 14:45:47.642785 <6>[ 2.607475] usbcore: registered new device driver r8152-cfgselector
10631 14:45:47.649291 <6>[ 2.614009] usbcore: registered new interface driver r8152
10632 14:45:47.653550 <6>[ 2.619828] VFIO - User Level meta-driver version: 0.3
10633 14:45:47.662043 <6>[ 2.628082] usbcore: registered new interface driver usb-storage
10634 14:45:47.668695 <6>[ 2.634529] usbcore: registered new device driver onboard-usb-hub
10635 14:45:47.678756 <6>[ 2.643678] mt6397-rtc mt6359-rtc: registered as rtc0
10636 14:45:47.687791 <6>[ 2.649140] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:45:47 UTC (1717512347)
10637 14:45:47.691507 <6>[ 2.658704] i2c_dev: i2c /dev entries driver
10638 14:45:47.708630 <6>[ 2.670658] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10639 14:45:47.714573 <4>[ 2.679426] cpu cpu0: supply cpu not found, using dummy regulator
10640 14:45:47.721733 <4>[ 2.685856] cpu cpu1: supply cpu not found, using dummy regulator
10641 14:45:47.729022 <4>[ 2.692257] cpu cpu2: supply cpu not found, using dummy regulator
10642 14:45:47.734532 <4>[ 2.698659] cpu cpu3: supply cpu not found, using dummy regulator
10643 14:45:47.741521 <4>[ 2.705077] cpu cpu4: supply cpu not found, using dummy regulator
10644 14:45:47.747852 <4>[ 2.711472] cpu cpu5: supply cpu not found, using dummy regulator
10645 14:45:47.754779 <4>[ 2.717873] cpu cpu6: supply cpu not found, using dummy regulator
10646 14:45:47.762899 <4>[ 2.724267] cpu cpu7: supply cpu not found, using dummy regulator
10647 14:45:47.779585 <6>[ 2.744903] cpu cpu0: EM: created perf domain
10648 14:45:47.782400 <6>[ 2.749876] cpu cpu4: EM: created perf domain
10649 14:45:47.790038 <6>[ 2.755506] sdhci: Secure Digital Host Controller Interface driver
10650 14:45:47.796887 <6>[ 2.761941] sdhci: Copyright(c) Pierre Ossman
10651 14:45:47.803431 <6>[ 2.766902] Synopsys Designware Multimedia Card Interface Driver
10652 14:45:47.809694 <6>[ 2.773541] sdhci-pltfm: SDHCI platform and OF driver helper
10653 14:45:47.813269 <6>[ 2.773646] mmc0: CQHCI version 5.10
10654 14:45:47.819519 <6>[ 2.783673] ledtrig-cpu: registered to indicate activity on CPUs
10655 14:45:47.826343 <6>[ 2.790793] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10656 14:45:47.833265 <6>[ 2.797845] usbcore: registered new interface driver usbhid
10657 14:45:47.837011 <6>[ 2.803667] usbhid: USB HID core driver
10658 14:45:47.843245 <6>[ 2.807880] spi_master spi0: will run message pump with realtime priority
10659 14:45:47.888993 <6>[ 2.848331] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10660 14:45:47.908106 <6>[ 2.863948] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10661 14:45:47.915385 <6>[ 2.878867] cros-ec-spi spi0.0: Chrome EC device registered
10662 14:45:47.918302 <6>[ 2.884958] mmc0: Command Queue Engine enabled
10663 14:45:47.926070 <6>[ 2.889755] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10664 14:45:47.932362 <6>[ 2.897119] mmcblk0: mmc0:0001 DA4128 116 GiB
10665 14:45:47.938427 <6>[ 2.898328] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10666 14:45:47.945331 <6>[ 2.907524] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10667 14:45:47.952058 <6>[ 2.912173] NET: Registered PF_PACKET protocol family
10668 14:45:47.954869 <6>[ 2.918503] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10669 14:45:47.961891 <6>[ 2.922456] 9pnet: Installing 9P2000 support
10670 14:45:47.965586 <6>[ 2.928195] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10671 14:45:47.972374 <5>[ 2.932145] Key type dns_resolver registered
10672 14:45:47.978282 <6>[ 2.937958] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10673 14:45:47.981942 <6>[ 2.942395] registered taskstats version 1
10674 14:45:47.987944 <5>[ 2.952775] Loading compiled-in X.509 certificates
10675 14:45:48.020509 <4>[ 2.979373] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10676 14:45:48.030207 <4>[ 2.990076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 14:45:48.045088 <6>[ 3.010488] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10678 14:45:48.051319 <6>[ 3.017426] xhci-mtk 11200000.usb: xHCI Host Controller
10679 14:45:48.058323 <6>[ 3.022926] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10680 14:45:48.068278 <6>[ 3.030786] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10681 14:45:48.075075 <6>[ 3.040247] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10682 14:45:48.081629 <6>[ 3.046348] xhci-mtk 11200000.usb: xHCI Host Controller
10683 14:45:48.088656 <6>[ 3.051833] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10684 14:45:48.094752 <6>[ 3.059580] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10685 14:45:48.101474 <6>[ 3.067396] hub 1-0:1.0: USB hub found
10686 14:45:48.104767 <6>[ 3.071423] hub 1-0:1.0: 1 port detected
10687 14:45:48.115011 <6>[ 3.075722] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10688 14:45:48.117936 <6>[ 3.084289] hub 2-0:1.0: USB hub found
10689 14:45:48.121318 <6>[ 3.088297] hub 2-0:1.0: 1 port detected
10690 14:45:48.128937 <6>[ 3.095014] mtk-msdc 11f70000.mmc: Got CD GPIO
10691 14:45:48.147421 <6>[ 3.109640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10692 14:45:48.153689 <6>[ 3.117758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10693 14:45:48.164181 <4>[ 3.125674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10694 14:45:48.174073 <6>[ 3.135230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10695 14:45:48.180937 <6>[ 3.143311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10696 14:45:48.190343 <6>[ 3.151428] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10697 14:45:48.196968 <6>[ 3.159356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10698 14:45:48.203606 <6>[ 3.167173] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10699 14:45:48.213110 <6>[ 3.174991] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10700 14:45:48.223798 <6>[ 3.185464] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10701 14:45:48.229665 <6>[ 3.193824] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10702 14:45:48.239723 <6>[ 3.202164] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10703 14:45:48.246581 <6>[ 3.210502] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10704 14:45:48.256232 <6>[ 3.218840] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10705 14:45:48.266210 <6>[ 3.227178] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10706 14:45:48.272641 <6>[ 3.235518] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10707 14:45:48.280072 <6>[ 3.243856] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10708 14:45:48.290399 <6>[ 3.252201] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10709 14:45:48.299612 <6>[ 3.260539] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10710 14:45:48.306847 <6>[ 3.268877] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10711 14:45:48.316300 <6>[ 3.277215] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10712 14:45:48.322944 <6>[ 3.285552] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10713 14:45:48.332807 <6>[ 3.293890] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10714 14:45:48.339342 <6>[ 3.302228] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10715 14:45:48.345775 <6>[ 3.310954] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10716 14:45:48.352455 <6>[ 3.318117] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10717 14:45:48.359066 <6>[ 3.324885] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10718 14:45:48.366246 <6>[ 3.331662] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10719 14:45:48.376275 <6>[ 3.338604] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10720 14:45:48.382808 <6>[ 3.345454] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10721 14:45:48.392726 <6>[ 3.354592] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10722 14:45:48.402692 <6>[ 3.363713] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10723 14:45:48.412401 <6>[ 3.373007] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10724 14:45:48.422704 <6>[ 3.382475] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10725 14:45:48.429829 <6>[ 3.391941] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10726 14:45:48.438895 <6>[ 3.401061] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10727 14:45:48.449006 <6>[ 3.410529] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10728 14:45:48.458948 <6>[ 3.419648] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10729 14:45:48.469156 <6>[ 3.428942] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10730 14:45:48.478886 <6>[ 3.439103] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10731 14:45:48.488506 <6>[ 3.450614] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10732 14:45:48.534216 <6>[ 3.496501] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10733 14:45:48.689702 <6>[ 3.654583] hub 1-1:1.0: USB hub found
10734 14:45:48.691861 <6>[ 3.659075] hub 1-1:1.0: 4 ports detected
10735 14:45:48.701836 <6>[ 3.667817] hub 1-1:1.0: USB hub found
10736 14:45:48.705010 <6>[ 3.672293] hub 1-1:1.0: 4 ports detected
10737 14:45:48.814104 <6>[ 3.776774] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10738 14:45:48.840416 <6>[ 3.806023] hub 2-1:1.0: USB hub found
10739 14:45:48.843466 <6>[ 3.810520] hub 2-1:1.0: 3 ports detected
10740 14:45:48.852502 <6>[ 3.818543] hub 2-1:1.0: USB hub found
10741 14:45:48.856886 <6>[ 3.822990] hub 2-1:1.0: 3 ports detected
10742 14:45:49.029675 <6>[ 3.992447] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10743 14:45:49.162108 <6>[ 4.127700] hub 1-1.4:1.0: USB hub found
10744 14:45:49.164923 <6>[ 4.132341] hub 1-1.4:1.0: 2 ports detected
10745 14:45:49.174306 <6>[ 4.140240] hub 1-1.4:1.0: USB hub found
10746 14:45:49.177299 <6>[ 4.144826] hub 1-1.4:1.0: 2 ports detected
10747 14:45:49.242013 <6>[ 4.204593] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10748 14:45:49.350696 <6>[ 4.313067] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10749 14:45:49.387239 <4>[ 4.349693] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10750 14:45:49.396831 <4>[ 4.358855] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10751 14:45:49.432219 <6>[ 4.398015] r8152 2-1.3:1.0 eth0: v1.12.13
10752 14:45:49.477435 <6>[ 4.440466] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10753 14:45:49.669442 <6>[ 4.632305] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10754 14:45:51.095412 <6>[ 6.061648] r8152 2-1.3:1.0 eth0: carrier on
10755 14:45:51.891766 <5>[ 6.092232] Sending DHCP requests .
10756 14:45:51.897928 <3>[ 6.857582] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[707ce831]
10757 14:45:51.904250 <3>[ 6.868227] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[707ce831]
10758 14:45:53.362739 <4>[ 8.316461] ., OK
10759 14:45:53.372197 <6>[ 8.334511] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10760 14:45:53.376036 <6>[ 8.342810] IP-Config: Complete:
10761 14:45:53.386202 <6>[ 8.346305] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10762 14:45:53.396843 <6>[ 8.357032] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10763 14:45:53.402505 <6>[ 8.365653] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10764 14:45:53.405531 <6>[ 8.365663] nameserver0=192.168.201.1
10765 14:45:53.409866 <6>[ 8.377859] clk: Disabling unused clocks
10766 14:45:53.413308 <6>[ 8.383322] ALSA device list:
10767 14:45:53.419869 <6>[ 8.386616] No soundcards found.
10768 14:45:53.428732 <6>[ 8.394328] Freeing unused kernel memory: 8512K
10769 14:45:53.431176 <6>[ 8.399301] Run /init as init process
10770 14:45:53.465539 <6>[ 8.431054] NET: Registered PF_INET6 protocol family
10771 14:45:53.471904 <6>[ 8.438014] Segment Routing with IPv6
10772 14:45:53.474461 <6>[ 8.441996] In-situ OAM (IOAM) with IPv6
10773 14:45:53.516006 <30>[ 8.455452] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10774 14:45:53.522444 <30>[ 8.488666] systemd[1]: Detected architecture arm64.
10775 14:45:53.522543
10776 14:45:53.528994 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10777 14:45:53.529103
10778 14:45:53.541638 <30>[ 8.508459] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10779 14:45:53.664415 <30>[ 8.627773] systemd[1]: Queued start job for default target graphical.target.
10780 14:45:53.711476 <30>[ 8.674394] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10781 14:45:53.717757 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10782 14:45:53.737871 <30>[ 8.700764] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10783 14:45:53.747175 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10784 14:45:53.761986 <30>[ 8.725421] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10785 14:45:53.772264 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10786 14:45:53.790767 <30>[ 8.752892] systemd[1]: Created slice user.slice - User and Session Slice.
10787 14:45:53.796058 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10788 14:45:53.817328 <30>[ 8.777148] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10789 14:45:53.823644 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10790 14:45:53.844744 <30>[ 8.804568] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10791 14:45:53.851512 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10792 14:45:53.880102 <30>[ 8.833015] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10793 14:45:53.889746 <30>[ 8.852937] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10794 14:45:53.896919 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10795 14:45:53.913294 <30>[ 8.876745] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10796 14:45:53.920100 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10797 14:45:53.941886 <30>[ 8.904919] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10798 14:45:53.952213 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10799 14:45:53.966252 <30>[ 8.932958] systemd[1]: Reached target paths.target - Path Units.
10800 14:45:53.976399 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10801 14:45:53.994116 <30>[ 8.956925] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10802 14:45:54.000209 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10803 14:45:54.014328 <30>[ 8.980429] systemd[1]: Reached target slices.target - Slice Units.
10804 14:45:54.024052 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10805 14:45:54.038371 <30>[ 9.004851] systemd[1]: Reached target swap.target - Swaps.
10806 14:45:54.044957 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10807 14:45:54.065468 <30>[ 9.028954] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10808 14:45:54.075190 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10809 14:45:54.093703 <30>[ 9.056908] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10810 14:45:54.103102 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10811 14:45:54.123402 <30>[ 9.086424] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10812 14:45:54.132842 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10813 14:45:54.149643 <30>[ 9.113058] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10814 14:45:54.160035 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10815 14:45:54.177881 <30>[ 9.141031] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10816 14:45:54.184225 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10817 14:45:54.202076 <30>[ 9.165113] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10818 14:45:54.211837 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10819 14:45:54.229853 <30>[ 9.193141] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10820 14:45:54.240184 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10821 14:45:54.258556 <30>[ 9.221042] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10822 14:45:54.267505 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10823 14:45:54.317178 <30>[ 9.280600] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10824 14:45:54.323680 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10825 14:45:54.345591 <30>[ 9.308831] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10826 14:45:54.352213 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10827 14:45:54.393305 <30>[ 9.356517] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10828 14:45:54.399625 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10829 14:45:54.424162 <30>[ 9.380859] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10830 14:45:54.437619 <30>[ 9.401205] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10831 14:45:54.448216 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10832 14:45:54.489737 <30>[ 9.452688] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10833 14:45:54.495631 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10834 14:45:54.522980 <30>[ 9.485733] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10835 14:45:54.535200 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 9.499250] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10836 14:45:54.538527 Module dm_mod...
10837 14:45:54.577806 <30>[ 9.540776] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10838 14:45:54.584093 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10839 14:45:54.605954 <30>[ 9.569360] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10840 14:45:54.615952 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10841 14:45:54.653100 <30>[ 9.616685] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10842 14:45:54.659816 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10843 14:45:54.686216 <30>[ 9.649302] systemd[1]: Starting systemd-journald.service - Journal Service...
10844 14:45:54.692213 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10845 14:45:54.734133 <30>[ 9.697382] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10846 14:45:54.740659 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10847 14:45:54.767017 <30>[ 9.727182] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10848 14:45:54.773665 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10849 14:45:54.796650 <30>[ 9.760086] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10850 14:45:54.808081 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10851 14:45:54.830698 <30>[ 9.794185] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10852 14:45:54.837451 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10853 14:45:54.864845 <30>[ 9.828099] systemd[1]: Started systemd-journald.service - Journal Service.
10854 14:45:54.871717 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10855 14:45:54.893797 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10856 14:45:54.913990 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10857 14:45:54.934017 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10858 14:45:54.955333 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10859 14:45:54.975843 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10860 14:45:54.995765 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10861 14:45:55.016016 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10862 14:45:55.035986 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10863 14:45:55.057732 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10864 14:45:55.079724 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10865 14:45:55.102491 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10866 14:45:55.127752 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10867 14:45:55.133843 See 'systemctl status systemd-remount-fs.service' for details.
10868 14:45:55.144015 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10869 14:45:55.163736 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10870 14:45:55.206407 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10871 14:45:55.225793 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10872 14:45:55.247832 <46>[ 10.210720] systemd-journald[190]: Received client request to flush runtime journal.
10873 14:45:55.254575 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10874 14:45:55.277295 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10875 14:45:55.297933 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10876 14:45:55.322858 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10877 14:45:55.342849 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10878 14:45:55.362402 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10879 14:45:55.382531 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10880 14:45:55.402748 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10881 14:45:55.449914 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10882 14:45:55.483898 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10883 14:45:55.506385 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10884 14:45:55.529436 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10885 14:45:55.573957 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10886 14:45:55.594766 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10887 14:45:55.620608 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10888 14:45:55.666189 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10889 14:45:55.697583 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10890 14:45:55.709353 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10891 14:45:55.764402 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10892 14:45:55.785892 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10893 14:45:55.811934 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10894 14:45:55.915441 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10895 14:45:55.934424 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10896 14:45:55.954427 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10897 14:45:55.974699 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10898 14:45:55.993180 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10899 14:45:56.015236 [[0;32m OK [<6>[ 10.979123] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10900 14:45:56.027972 0m] Listening on [0;1;39mdbus.socket[…- D-Bu<6>[ 10.989835] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10901 14:45:56.034647 s System Message<6>[ 10.990972] remoteproc remoteproc0: scp is available
10902 14:45:56.034732 Bus Socket.
10903 14:45:56.045228 <6>[ 10.999596] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10904 14:45:56.047908 <6>[ 11.008031] remoteproc remoteproc0: powering up scp
10905 14:45:56.058236 <6>[ 11.018709] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10906 14:45:56.065264 <6>[ 11.020640] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10907 14:45:56.071128 <6>[ 11.020708] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10908 14:45:56.074710 <6>[ 11.023182] mc: Linux media interface: v0.10
10909 14:45:56.084619 <4>[ 11.025774] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10910 14:45:56.091199 <4>[ 11.025889] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10911 14:45:56.097910 <6>[ 11.039617] videodev: Linux video capture interface: v2.00
10912 14:45:56.104818 <3>[ 11.063860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 14:45:56.114607 [[0;32m OK [<3>[ 11.077977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 14:45:56.124656 0m] Reached targ<3>[ 11.087202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 14:45:56.134900 et [0;1;39msockets.target[0m -<6>[ 11.098314] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10916 14:45:56.137752 Socket Units.
10917 14:45:56.144323 <3>[ 11.103271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10918 14:45:56.144407
10919 14:45:56.154077 <3>[ 11.116668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 14:45:56.160963 <3>[ 11.125138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 14:45:56.171523 <3>[ 11.133378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 14:45:56.180971 <6>[ 11.135547] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10923 14:45:56.188407 <3>[ 11.141465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 14:45:56.194216 <3>[ 11.141551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 14:45:56.203833 <3>[ 11.141643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 14:45:56.210932 <3>[ 11.141649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 14:45:56.220596 <3>[ 11.141652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 14:45:56.227499 <3>[ 11.141723] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 14:45:56.237248 <3>[ 11.141729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 14:45:56.244022 <3>[ 11.141734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 14:45:56.250750 <3>[ 11.141737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 14:45:56.260580 <3>[ 11.141740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 14:45:56.267871 <3>[ 11.141755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 14:45:56.273640 <6>[ 11.149415] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10935 14:45:56.283524 <6>[ 11.159235] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10936 14:45:56.293791 <6>[ 11.164877] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10937 14:45:56.300060 <6>[ 11.164938] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10938 14:45:56.306659 <6>[ 11.164945] remoteproc remoteproc0: remote processor scp is now up
10939 14:45:56.313631 <6>[ 11.167435] pci_bus 0000:00: root bus resource [bus 00-ff]
10940 14:45:56.323721 <6>[ 11.176588] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10941 14:45:56.330824 <6>[ 11.183452] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10942 14:45:56.341249 <6>[ 11.183456] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10943 14:45:56.344562 <6>[ 11.183516] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10944 14:45:56.348246 <6>[ 11.232616] Bluetooth: Core ver 2.22
10945 14:45:56.358562 <6>[ 11.240074] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10946 14:45:56.365458 <6>[ 11.240082] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10947 14:45:56.368697 <6>[ 11.240162] pci 0000:00:00.0: supports D1 D2
10948 14:45:56.375417 <6>[ 11.240165] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10949 14:45:56.385104 <4>[ 11.241273] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10950 14:45:56.388506 <4>[ 11.241273] Fallback method does not support PEC.
10951 14:45:56.398903 <6>[ 11.242272] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10952 14:45:56.405559 <6>[ 11.242396] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10953 14:45:56.411696 <6>[ 11.242422] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10954 14:45:56.419465 <6>[ 11.242440] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10955 14:45:56.428898 <6>[ 11.242455] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10956 14:45:56.432035 <6>[ 11.242565] pci 0000:01:00.0: supports D1 D2
10957 14:45:56.438295 <6>[ 11.242567] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10958 14:45:56.445539 <6>[ 11.247093] NET: Registered PF_BLUETOOTH protocol family
10959 14:45:56.451632 <6>[ 11.248616] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10960 14:45:56.465826 <6>[ 11.257241] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10961 14:45:56.471661 <6>[ 11.258566] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10962 14:45:56.478149 <6>[ 11.258612] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10963 14:45:56.488228 <6>[ 11.258617] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10964 14:45:56.494971 <6>[ 11.258625] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10965 14:45:56.502133 <6>[ 11.258640] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10966 14:45:56.511507 <6>[ 11.258665] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10967 14:45:56.515280 <6>[ 11.258678] pci 0000:00:00.0: PCI bridge to [bus 01]
10968 14:45:56.525578 <6>[ 11.258684] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10969 14:45:56.531236 <6>[ 11.258956] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10970 14:45:56.538069 <6>[ 11.259672] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10971 14:45:56.541112 <6>[ 11.259893] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10972 14:45:56.547702 <6>[ 11.264082] Bluetooth: HCI device and connection manager initialized
10973 14:45:56.554321 <6>[ 11.264106] Bluetooth: HCI socket layer initialized
10974 14:45:56.561326 <6>[ 11.273079] usbcore: registered new interface driver uvcvideo
10975 14:45:56.567405 <6>[ 11.275343] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10976 14:45:56.574383 <6>[ 11.279147] Bluetooth: L2CAP socket layer initialized
10977 14:45:56.581148 <5>[ 11.281811] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10978 14:45:56.587489 <5>[ 11.300533] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10979 14:45:56.594982 <6>[ 11.301082] Bluetooth: SCO socket layer initialized
10980 14:45:56.601634 <6>[ 11.301823] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10981 14:45:56.607819 <5>[ 11.311470] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10982 14:45:56.617735 <3>[ 11.322755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 14:45:56.623913 <3>[ 11.323535] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10984 14:45:56.634985 <4>[ 11.329465] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10985 14:45:56.644021 <3>[ 11.348510] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 14:45:56.647948 <6>[ 11.361914] cfg80211: failed to load regulatory.db
10987 14:45:56.654269 <6>[ 11.363323] usbcore: registered new interface driver btusb
10988 14:45:56.663822 <4>[ 11.370988] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10989 14:45:56.670441 <6>[ 11.418669] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10990 14:45:56.677295 <3>[ 11.423374] Bluetooth: hci0: Failed to load firmware file (-2)
10991 14:45:56.684184 <6>[ 11.435852] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10992 14:45:56.689800 <3>[ 11.442571] Bluetooth: hci0: Failed to set up firmware (-2)
10993 14:45:56.693124 <6>[ 11.469271] mt7921e 0000:01:00.0: ASIC revision: 79610010
10994 14:45:56.706653 <4>[ 11.474619] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10995 14:45:56.713693 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10996 14:45:56.725034 <3>[ 11.688574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 14:45:56.735320 <3>[ 11.698083] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10998 14:45:56.741499 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10999 14:45:56.755102 <3>[ 11.718452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 14:45:56.787036 <3>[ 11.750749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 14:45:56.807112 <6>[ 11.770542] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11002 14:45:56.811382 <6>[ 11.770542]
11003 14:45:56.817329 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11004 14:45:56.824411 <3>[ 11.788176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 14:45:56.844567 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11006 14:45:56.854967 <3>[ 11.818652] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 14:45:56.868758 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11008 14:45:56.891275 [[0;32m OK [0m] Started [0;1;39mdbus.servic<3>[ 11.852044] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 14:45:56.894600 e[0m - D-Bus System Message Bus.
11010 14:45:56.943661 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11011 14:45:56.968466 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11012 14:45:56.988944 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11013 14:45:57.004918 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11014 14:45:57.023532 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11015 14:45:57.058407 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11016 14:45:57.075723 <6>[ 12.039563] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11017 14:45:57.091126 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11018 14:45:57.114154 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11019 14:45:57.134998 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11020 14:45:57.181497 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11021 14:45:57.227666 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11022 14:45:57.247455 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11023 14:45:57.262215 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11024 14:45:57.281561 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11025 14:45:57.333894 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11026 14:45:57.358766 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11027 14:45:57.380277 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11028 14:45:57.420562 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11029 14:45:57.450922
11030 14:45:57.454556 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11031 14:45:57.454642
11032 14:45:57.457949 debian-bookworm-arm64 login: root (automatic login)
11033 14:45:57.458033
11034 14:45:57.469502 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11035 14:45:57.469598
11036 14:45:57.476555 The programs included with the Debian GNU/Linux system are free software;
11037 14:45:57.483093 the exact distribution terms for each program are described in the
11038 14:45:57.486445 individual files in /usr/share/doc/*/copyright.
11039 14:45:57.486530
11040 14:45:57.493343 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11041 14:45:57.496322 permitted by applicable law.
11042 14:45:57.496781 Matched prompt #10: / #
11044 14:45:57.497075 Setting prompt string to ['/ #']
11045 14:45:57.497169 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11047 14:45:57.497364 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11048 14:45:57.497451 start: 2.2.6 expect-shell-connection (timeout 00:03:01) [common]
11049 14:45:57.497523 Setting prompt string to ['/ #']
11050 14:45:57.497609 Forcing a shell prompt, looking for ['/ #']
11052 14:45:57.547845 / #
11053 14:45:57.548022 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11054 14:45:57.548155 Waiting using forced prompt support (timeout 00:02:30)
11055 14:45:57.553574
11056 14:45:57.553879 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11057 14:45:57.553986 start: 2.2.7 export-device-env (timeout 00:03:01) [common]
11058 14:45:57.554081 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11059 14:45:57.554168 end: 2.2 depthcharge-retry (duration 00:01:59) [common]
11060 14:45:57.554253 end: 2 depthcharge-action (duration 00:01:59) [common]
11061 14:45:57.554336 start: 3 lava-test-retry (timeout 00:07:22) [common]
11062 14:45:57.554418 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11063 14:45:57.554492 Using namespace: common
11065 14:45:57.654878 / # #
11066 14:45:57.655066 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11067 14:45:57.660264 #
11068 14:45:57.660541 Using /lava-14167004
11070 14:45:57.760929 / # export SHELL=/bin/sh
11071 14:45:57.766660 export SHELL=/bin/sh
11073 14:45:57.867243 / # . /lava-14167004/environment
11074 14:45:57.874103 . /lava-14167004/environment
11076 14:45:57.974723 / # /lava-14167004/bin/lava-test-runner /lava-14167004/0
11077 14:45:57.974907 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 14:45:57.975264 /lava-14167004/bin/lava-test-runner /lava-14167004/0<6>[ 12.915718] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11079 14:45:57.980139
11080 14:45:58.021236 + export TESTRUN_ID=0_v4l2-compliance-uvc
11081 14:45:58.021399 + cd /lava-14167004/0/tests/0_v4l2-compliance-uvc
11082 14:45:58.021471 + cat uuid
11083 14:45:58.021534 + UUID=14167004_1.5.2.3.1
11084 14:45:58.021594 + set +x
11085 14:45:58.023547 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14167004_1.5.2.3.1>
11086 14:45:58.023811 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14167004_1.5.2.3.1
11087 14:45:58.023887 Starting test lava.0_v4l2-compliance-uvc (14167004_1.5.2.3.1)
11088 14:45:58.023974 Skipping test definition patterns.
11089 14:45:58.027508 + /usr/bin/v4l2-parser.sh -d uvcvideo
11090 14:45:58.033883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11091 14:45:58.033982 device: /dev/video0
11092 14:45:58.034229 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11094 14:46:04.485019 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11095 14:46:04.493861 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11096 14:46:04.501754
11097 14:46:04.521076 Compliance test for uvcvideo device /dev/video0:
11098 14:46:04.528251
11099 14:46:04.539036 Driver Info:
11100 14:46:04.552822 Driver name : uvcvideo
11101 14:46:04.569394 Card type : HD User Facing: HD User Facing
11102 14:46:04.579663 Bus info : usb-11200000.usb-1.4.1
11103 14:46:04.591451 Driver version : 6.1.91
11104 14:46:04.602247 Capabilities : 0x84a00001
11105 14:46:04.614512 Metadata Capture
11106 14:46:04.625173 Streaming
11107 14:46:04.636961 Extended Pix Format
11108 14:46:04.647129 Device Capabilities
11109 14:46:04.659182 Device Caps : 0x04200001
11110 14:46:04.675130 Streaming
11111 14:46:04.685649 Extended Pix Format
11112 14:46:04.697037 Media Driver Info:
11113 14:46:04.707128 Driver name : uvcvideo
11114 14:46:04.722605 Model : HD User Facing: HD User Facing
11115 14:46:04.730688 Serial : 200901010001
11116 14:46:04.745349 Bus info : usb-11200000.usb-1.4.1
11117 14:46:04.750719 Media version : 6.1.91
11118 14:46:04.765564 Hardware revision: 0x00009758 (38744)
11119 14:46:04.772162 Driver version : 6.1.91
11120 14:46:04.782943 Interface Info:
11121 14:46:04.797465 <LAVA_SIGNAL_TESTSET START Interface-Info>
11122 14:46:04.797576 ID : 0x03000002
11123 14:46:04.797822 Received signal: <TESTSET> START Interface-Info
11124 14:46:04.797899 Starting test_set Interface-Info
11125 14:46:04.808855 Type : V4L Video
11126 14:46:04.824471 Entity Info:
11127 14:46:04.831314 <LAVA_SIGNAL_TESTSET STOP>
11128 14:46:04.831650 Received signal: <TESTSET> STOP
11129 14:46:04.831737 Closing test_set Interface-Info
11130 14:46:04.840993 <LAVA_SIGNAL_TESTSET START Entity-Info>
11131 14:46:04.841280 Received signal: <TESTSET> START Entity-Info
11132 14:46:04.841353 Starting test_set Entity-Info
11133 14:46:04.844116 ID : 0x00000001 (1)
11134 14:46:04.853268 Name : HD User Facing: HD User Facing
11135 14:46:04.861259 Function : V4L2 I/O
11136 14:46:04.872740 Flags : default
11137 14:46:04.882050 Pad 0x01000007 : 0: Sink
11138 14:46:04.908366 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11139 14:46:04.908508
11140 14:46:04.921677 Required ioctls:
11141 14:46:04.929310 <LAVA_SIGNAL_TESTSET STOP>
11142 14:46:04.929601 Received signal: <TESTSET> STOP
11143 14:46:04.929679 Closing test_set Entity-Info
11144 14:46:04.939288 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11145 14:46:04.939583 Received signal: <TESTSET> START Required-ioctls
11146 14:46:04.939660 Starting test_set Required-ioctls
11147 14:46:04.942196 test MC information (see 'Media Driver Info' above): OK
11148 14:46:04.967035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11149 14:46:04.967449 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11151 14:46:04.969957 test VIDIOC_QUERYCAP: OK
11152 14:46:04.987851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11153 14:46:04.988172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11155 14:46:04.991010 test invalid ioctls: OK
11156 14:46:05.012630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11157 14:46:05.012774
11158 14:46:05.013038 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11160 14:46:05.023636 Allow for multiple opens:
11161 14:46:05.030942 <LAVA_SIGNAL_TESTSET STOP>
11162 14:46:05.031266 Received signal: <TESTSET> STOP
11163 14:46:05.031342 Closing test_set Required-ioctls
11164 14:46:05.041614 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11165 14:46:05.041931 Received signal: <TESTSET> START Allow-for-multiple-opens
11166 14:46:05.042006 Starting test_set Allow-for-multiple-opens
11167 14:46:05.044103 test second /dev/video0 open: OK
11168 14:46:05.066855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11169 14:46:05.067175 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11171 14:46:05.069670 test VIDIOC_QUERYCAP: OK
11172 14:46:05.093089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11173 14:46:05.093400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11175 14:46:05.095653 test VIDIOC_G/S_PRIORITY: OK
11176 14:46:05.119956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11177 14:46:05.120270 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11179 14:46:05.123160 test for unlimited opens: OK
11180 14:46:05.148173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11181 14:46:05.148323
11182 14:46:05.148573 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11184 14:46:05.159395 Debug ioctls:
11185 14:46:05.167099 <LAVA_SIGNAL_TESTSET STOP>
11186 14:46:05.167374 Received signal: <TESTSET> STOP
11187 14:46:05.167451 Closing test_set Allow-for-multiple-opens
11188 14:46:05.176336 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11189 14:46:05.176635 Received signal: <TESTSET> START Debug-ioctls
11190 14:46:05.176707 Starting test_set Debug-ioctls
11191 14:46:05.179615 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11192 14:46:05.204453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11193 14:46:05.204778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11195 14:46:05.210513 test VIDIOC_LOG_STATUS: OK (Not Supported)
11196 14:46:05.229281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11197 14:46:05.229397
11198 14:46:05.229640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11200 14:46:05.240089 Input ioctls:
11201 14:46:05.247873 <LAVA_SIGNAL_TESTSET STOP>
11202 14:46:05.248135 Received signal: <TESTSET> STOP
11203 14:46:05.248205 Closing test_set Debug-ioctls
11204 14:46:05.257718 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11205 14:46:05.257983 Received signal: <TESTSET> START Input-ioctls
11206 14:46:05.258057 Starting test_set Input-ioctls
11207 14:46:05.260608 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11208 14:46:05.284560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11209 14:46:05.284871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11211 14:46:05.287670 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11212 14:46:05.310767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11213 14:46:05.311064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11215 14:46:05.318324 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11216 14:46:05.336189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11217 14:46:05.336488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11219 14:46:05.342934 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11220 14:46:05.361483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11221 14:46:05.361794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11223 14:46:05.364887 test VIDIOC_G/S/ENUMINPUT: OK
11224 14:46:05.386215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11225 14:46:05.386518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11227 14:46:05.389404 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11228 14:46:05.410087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11229 14:46:05.410416 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11231 14:46:05.413972 Inputs: 1 Audio Inputs: 0 Tuners: 0
11232 14:46:05.421007
11233 14:46:05.440551 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11234 14:46:05.462529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11235 14:46:05.462848 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11237 14:46:05.469522 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11238 14:46:05.485585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11239 14:46:05.485901 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11241 14:46:05.491775 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11242 14:46:05.511382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11243 14:46:05.511691 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11245 14:46:05.517994 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11246 14:46:05.538585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11247 14:46:05.538884 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11249 14:46:05.545033 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11250 14:46:05.564196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11251 14:46:05.564326
11252 14:46:05.564570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11254 14:46:05.584403 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11255 14:46:05.605580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11256 14:46:05.605911 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11258 14:46:05.611539 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11259 14:46:05.635593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11260 14:46:05.635983 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11262 14:46:05.638800 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11263 14:46:05.656947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11264 14:46:05.657306 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11266 14:46:05.659875 test VIDIOC_G/S_EDID: OK (Not Supported)
11267 14:46:05.679405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11268 14:46:05.679534
11269 14:46:05.679792 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11271 14:46:05.691840 Control ioctls (Input 0):
11272 14:46:05.699439 <LAVA_SIGNAL_TESTSET STOP>
11273 14:46:05.699716 Received signal: <TESTSET> STOP
11274 14:46:05.699789 Closing test_set Input-ioctls
11275 14:46:05.708908 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11276 14:46:05.709210 Received signal: <TESTSET> START Control-ioctls-Input-0
11277 14:46:05.709283 Starting test_set Control-ioctls-Input-0
11278 14:46:05.712011 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11279 14:46:05.738510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11280 14:46:05.738673 test VIDIOC_QUERYCTRL: OK
11281 14:46:05.738921 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11283 14:46:05.763654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11284 14:46:05.763970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11286 14:46:05.767052 test VIDIOC_G/S_CTRL: OK
11287 14:46:05.787612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11288 14:46:05.787920 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11290 14:46:05.790736 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11291 14:46:05.812002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11292 14:46:05.812342 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11294 14:46:05.819194 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11295 14:46:05.839458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11296 14:46:05.839773 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11298 14:46:05.843074 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11299 14:46:05.860594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11300 14:46:05.860898 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11302 14:46:05.864191 Standard Controls: 16 Private Controls: 0
11303 14:46:05.870471
11304 14:46:05.881846 Format ioctls (Input 0):
11305 14:46:05.887830 <LAVA_SIGNAL_TESTSET STOP>
11306 14:46:05.888090 Received signal: <TESTSET> STOP
11307 14:46:05.888163 Closing test_set Control-ioctls-Input-0
11308 14:46:05.898025 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11309 14:46:05.898281 Received signal: <TESTSET> START Format-ioctls-Input-0
11310 14:46:05.898352 Starting test_set Format-ioctls-Input-0
11311 14:46:05.901271 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11312 14:46:05.928918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11313 14:46:05.929268 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11315 14:46:05.933262 test VIDIOC_G/S_PARM: OK
11316 14:46:05.950183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11317 14:46:05.950480 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11319 14:46:05.953405 test VIDIOC_G_FBUF: OK (Not Supported)
11320 14:46:05.974716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11321 14:46:05.974984 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11323 14:46:05.978036 test VIDIOC_G_FMT: OK
11324 14:46:05.998958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11325 14:46:05.999230 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11327 14:46:06.002189 test VIDIOC_TRY_FMT: OK
11328 14:46:06.027956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11329 14:46:06.028244 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11331 14:46:06.035362 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11332 14:46:06.038022 test VIDIOC_S_FMT: OK
11333 14:46:06.065891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11334 14:46:06.066183 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11336 14:46:06.069413 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11337 14:46:06.092765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11338 14:46:06.093057 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11340 14:46:06.096091 test Cropping: OK (Not Supported)
11341 14:46:06.118095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11342 14:46:06.118363 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11344 14:46:06.120961 test Composing: OK (Not Supported)
11345 14:46:06.143456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11346 14:46:06.143729 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11348 14:46:06.146436 test Scaling: OK (Not Supported)
11349 14:46:06.167622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11350 14:46:06.167715
11351 14:46:06.167996 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11353 14:46:06.181468 Codec ioctls (Input 0):
11354 14:46:06.188621 <LAVA_SIGNAL_TESTSET STOP>
11355 14:46:06.188890 Received signal: <TESTSET> STOP
11356 14:46:06.188963 Closing test_set Format-ioctls-Input-0
11357 14:46:06.198408 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11358 14:46:06.198684 Received signal: <TESTSET> START Codec-ioctls-Input-0
11359 14:46:06.198762 Starting test_set Codec-ioctls-Input-0
11360 14:46:06.202398 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11361 14:46:06.224526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11362 14:46:06.224845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11364 14:46:06.230970 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11365 14:46:06.254474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11366 14:46:06.254801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11368 14:46:06.260637 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11369 14:46:06.277338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11370 14:46:06.277469
11371 14:46:06.277713 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11373 14:46:06.287076 Buffer ioctls (Input 0):
11374 14:46:06.292914 <LAVA_SIGNAL_TESTSET STOP>
11375 14:46:06.293218 Received signal: <TESTSET> STOP
11376 14:46:06.293297 Closing test_set Codec-ioctls-Input-0
11377 14:46:06.302671 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11378 14:46:06.302945 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11379 14:46:06.303019 Starting test_set Buffer-ioctls-Input-0
11380 14:46:06.305794 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11381 14:46:06.327835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11382 14:46:06.328165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11384 14:46:06.330485 test CREATE_BUFS maximum buffers: OK
11385 14:46:06.346826 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11387 14:46:06.349824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11388 14:46:06.349910 test VIDIOC_EXPBUF: OK
11389 14:46:06.373638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11390 14:46:06.373964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11392 14:46:06.377456 test Requests: OK (Not Supported)
11393 14:46:06.398313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11394 14:46:06.398445
11395 14:46:06.398691 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11397 14:46:06.406796 Test input 0:
11398 14:46:06.416217
11399 14:46:06.429169 Streaming ioctls:
11400 14:46:06.436210 <LAVA_SIGNAL_TESTSET STOP>
11401 14:46:06.436485 Received signal: <TESTSET> STOP
11402 14:46:06.436556 Closing test_set Buffer-ioctls-Input-0
11403 14:46:06.446250 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11404 14:46:06.446518 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11405 14:46:06.446593 Starting test_set Streaming-ioctls_Test-input-0
11406 14:46:06.449505 test read/write: OK (Not Supported)
11407 14:46:06.476428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11408 14:46:06.476742 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11410 14:46:06.479704 test blocking wait: OK
11411 14:46:06.502207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11412 14:46:06.502526 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11414 14:46:06.508216 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11415 14:46:06.510952 test MMAP (no poll): FAIL
11416 14:46:06.540047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11417 14:46:06.540371 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11419 14:46:06.546412 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11420 14:46:06.551705 test MMAP (select): FAIL
11421 14:46:06.576524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11422 14:46:06.576831 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11424 14:46:06.582726 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11425 14:46:06.589595 test MMAP (epoll): FAIL
11426 14:46:06.615858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11427 14:46:06.616008
11428 14:46:06.616253 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11430 14:46:06.629744
11431 14:46:06.811884
11432 14:46:06.823410 test USERPTR (no poll): OK
11433 14:46:06.848220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11434 14:46:06.848369
11435 14:46:06.848613 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11437 14:46:06.865035
11438 14:46:07.043345
11439 14:46:07.052121 test USERPTR (select): OK
11440 14:46:07.077360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11441 14:46:07.077684 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11443 14:46:07.083345 test DMABUF: Cannot test, specify --expbuf-device
11444 14:46:07.087440
11445 14:46:07.108853 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11446 14:46:07.113667 <LAVA_TEST_RUNNER EXIT>
11447 14:46:07.113994 ok: lava_test_shell seems to have completed
11448 14:46:07.114072 Marking unfinished test run as failed
11450 14:46:07.115012 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11451 14:46:07.115137 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11452 14:46:07.115225 end: 3 lava-test-retry (duration 00:00:10) [common]
11453 14:46:07.115314 start: 4 finalize (timeout 00:07:13) [common]
11454 14:46:07.115403 start: 4.1 power-off (timeout 00:00:30) [common]
11455 14:46:07.115553 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11456 14:46:07.191531 >> Command sent successfully.
11457 14:46:07.193976 Returned 0 in 0 seconds
11458 14:46:07.294395 end: 4.1 power-off (duration 00:00:00) [common]
11460 14:46:07.294741 start: 4.2 read-feedback (timeout 00:07:12) [common]
11461 14:46:07.295003 Listened to connection for namespace 'common' for up to 1s
11462 14:46:08.295980 Finalising connection for namespace 'common'
11463 14:46:08.296163 Disconnecting from shell: Finalise
11464 14:46:08.296243 / #
11465 14:46:08.396610 end: 4.2 read-feedback (duration 00:00:01) [common]
11466 14:46:08.396796 end: 4 finalize (duration 00:00:01) [common]
11467 14:46:08.396913 Cleaning after the job
11468 14:46:08.397059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/ramdisk
11469 14:46:08.401504 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/kernel
11470 14:46:08.414398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/dtb
11471 14:46:08.414611 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167004/tftp-deploy-z24ttcqp/modules
11472 14:46:08.420098 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167004
11473 14:46:08.481426 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167004
11474 14:46:08.481610 Job finished correctly