Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 14:47:49.889868 lava-dispatcher, installed at version: 2024.03
2 14:47:49.890140 start: 0 validate
3 14:47:49.890352 Start time: 2024-06-04 14:47:49.890341+00:00 (UTC)
4 14:47:49.890538 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:47:49.890712 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:47:50.151884 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:47:50.152146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:47:50.410649 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:47:50.410882 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:47:50.668917 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:47:50.669099 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:47:50.929047 validate duration: 1.04
14 14:47:50.929495 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:47:50.929689 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:47:50.929866 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:47:50.930071 Not decompressing ramdisk as can be used compressed.
18 14:47:50.930217 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 14:47:50.930337 saving as /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/ramdisk/rootfs.cpio.gz
20 14:47:50.930457 total size: 47897469 (45 MB)
21 14:47:50.932128 progress 0 % (0 MB)
22 14:47:50.951259 progress 5 % (2 MB)
23 14:47:50.968352 progress 10 % (4 MB)
24 14:47:50.981238 progress 15 % (6 MB)
25 14:47:50.993953 progress 20 % (9 MB)
26 14:47:51.006407 progress 25 % (11 MB)
27 14:47:51.018717 progress 30 % (13 MB)
28 14:47:51.031249 progress 35 % (16 MB)
29 14:47:51.043800 progress 40 % (18 MB)
30 14:47:51.056221 progress 45 % (20 MB)
31 14:47:51.068769 progress 50 % (22 MB)
32 14:47:51.082229 progress 55 % (25 MB)
33 14:47:51.095876 progress 60 % (27 MB)
34 14:47:51.108929 progress 65 % (29 MB)
35 14:47:51.121480 progress 70 % (32 MB)
36 14:47:51.133905 progress 75 % (34 MB)
37 14:47:51.146922 progress 80 % (36 MB)
38 14:47:51.159719 progress 85 % (38 MB)
39 14:47:51.172259 progress 90 % (41 MB)
40 14:47:51.185047 progress 95 % (43 MB)
41 14:47:51.197614 progress 100 % (45 MB)
42 14:47:51.197887 45 MB downloaded in 0.27 s (170.80 MB/s)
43 14:47:51.198055 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:47:51.198295 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:47:51.198382 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:47:51.198467 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:47:51.198607 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:47:51.198680 saving as /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/kernel/Image
50 14:47:51.198741 total size: 54682112 (52 MB)
51 14:47:51.198823 No compression specified
52 14:47:51.200071 progress 0 % (0 MB)
53 14:47:51.214685 progress 5 % (2 MB)
54 14:47:51.229116 progress 10 % (5 MB)
55 14:47:51.243648 progress 15 % (7 MB)
56 14:47:51.258099 progress 20 % (10 MB)
57 14:47:51.272689 progress 25 % (13 MB)
58 14:47:51.287089 progress 30 % (15 MB)
59 14:47:51.301836 progress 35 % (18 MB)
60 14:47:51.316497 progress 40 % (20 MB)
61 14:47:51.330554 progress 45 % (23 MB)
62 14:47:51.344799 progress 50 % (26 MB)
63 14:47:51.359048 progress 55 % (28 MB)
64 14:47:51.373813 progress 60 % (31 MB)
65 14:47:51.387950 progress 65 % (33 MB)
66 14:47:51.402513 progress 70 % (36 MB)
67 14:47:51.417078 progress 75 % (39 MB)
68 14:47:51.432069 progress 80 % (41 MB)
69 14:47:51.446392 progress 85 % (44 MB)
70 14:47:51.460672 progress 90 % (46 MB)
71 14:47:51.474762 progress 95 % (49 MB)
72 14:47:51.489239 progress 100 % (52 MB)
73 14:47:51.489509 52 MB downloaded in 0.29 s (179.35 MB/s)
74 14:47:51.489671 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:47:51.489912 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:47:51.490000 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:47:51.490085 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:47:51.490224 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 14:47:51.490302 saving as /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/dtb/mt8192-asurada-spherion-r0.dtb
81 14:47:51.490365 total size: 47258 (0 MB)
82 14:47:51.490500 No compression specified
83 14:47:51.492023 progress 69 % (0 MB)
84 14:47:51.492343 progress 100 % (0 MB)
85 14:47:51.492507 0 MB downloaded in 0.00 s (21.06 MB/s)
86 14:47:51.492657 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:47:51.492887 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:47:51.492973 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:47:51.493056 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:47:51.493177 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:47:51.493246 saving as /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/modules/modules.tar
93 14:47:51.493306 total size: 8608920 (8 MB)
94 14:47:51.493368 Using unxz to decompress xz
95 14:47:51.497709 progress 0 % (0 MB)
96 14:47:51.517433 progress 5 % (0 MB)
97 14:47:51.549253 progress 10 % (0 MB)
98 14:47:51.580500 progress 15 % (1 MB)
99 14:47:51.606556 progress 20 % (1 MB)
100 14:47:51.631396 progress 25 % (2 MB)
101 14:47:51.656426 progress 30 % (2 MB)
102 14:47:51.682318 progress 35 % (2 MB)
103 14:47:51.714168 progress 40 % (3 MB)
104 14:47:51.742621 progress 45 % (3 MB)
105 14:47:51.769102 progress 50 % (4 MB)
106 14:47:51.795037 progress 55 % (4 MB)
107 14:47:51.820201 progress 60 % (4 MB)
108 14:47:51.845108 progress 65 % (5 MB)
109 14:47:51.870958 progress 70 % (5 MB)
110 14:47:51.897717 progress 75 % (6 MB)
111 14:47:51.925177 progress 80 % (6 MB)
112 14:47:51.950410 progress 85 % (7 MB)
113 14:47:51.976990 progress 90 % (7 MB)
114 14:47:52.003428 progress 95 % (7 MB)
115 14:47:52.029845 progress 100 % (8 MB)
116 14:47:52.035523 8 MB downloaded in 0.54 s (15.14 MB/s)
117 14:47:52.035913 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:47:52.036397 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:47:52.036551 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 14:47:52.036715 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 14:47:52.036858 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:47:52.037009 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 14:47:52.037348 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo
125 14:47:52.037562 makedir: /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin
126 14:47:52.037730 makedir: /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/tests
127 14:47:52.037888 makedir: /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/results
128 14:47:52.038068 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-add-keys
129 14:47:52.038297 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-add-sources
130 14:47:52.038509 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-background-process-start
131 14:47:52.038714 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-background-process-stop
132 14:47:52.038922 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-common-functions
133 14:47:52.039123 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-echo-ipv4
134 14:47:52.039321 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-install-packages
135 14:47:52.039524 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-installed-packages
136 14:47:52.039720 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-os-build
137 14:47:52.039922 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-probe-channel
138 14:47:52.040125 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-probe-ip
139 14:47:52.040329 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-target-ip
140 14:47:52.040531 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-target-mac
141 14:47:52.040742 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-target-storage
142 14:47:52.040947 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-case
143 14:47:52.041155 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-event
144 14:47:52.041360 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-feedback
145 14:47:52.041573 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-raise
146 14:47:52.041772 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-reference
147 14:47:52.041975 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-runner
148 14:47:52.042179 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-set
149 14:47:52.042387 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-test-shell
150 14:47:52.042599 Updating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-install-packages (oe)
151 14:47:52.042838 Updating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/bin/lava-installed-packages (oe)
152 14:47:52.043034 Creating /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/environment
153 14:47:52.043197 LAVA metadata
154 14:47:52.043325 - LAVA_JOB_ID=14167057
155 14:47:52.043444 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:47:52.043628 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 14:47:52.043749 skipped lava-vland-overlay
158 14:47:52.043880 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:47:52.044029 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 14:47:52.044172 skipped lava-multinode-overlay
161 14:47:52.044307 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:47:52.044455 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 14:47:52.044597 Loading test definitions
164 14:47:52.044762 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 14:47:52.044889 Using /lava-14167057 at stage 0
166 14:47:52.045405 uuid=14167057_1.5.2.3.1 testdef=None
167 14:47:52.045553 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:47:52.045695 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 14:47:52.046557 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:47:52.046957 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 14:47:52.048005 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:47:52.048427 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 14:47:52.049462 runner path: /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/0/tests/0_igt-kms-mediatek test_uuid 14167057_1.5.2.3.1
176 14:47:52.049702 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:47:52.050087 Creating lava-test-runner.conf files
179 14:47:52.050202 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167057/lava-overlay-urvklsjo/lava-14167057/0 for stage 0
180 14:47:52.050355 - 0_igt-kms-mediatek
181 14:47:52.050511 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:47:52.050655 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 14:47:52.061921 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:47:52.062137 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 14:47:52.062290 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:47:52.062436 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:47:52.062579 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 14:47:53.938409 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 14:47:53.938801 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 14:47:53.938967 extracting modules file /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167057/extract-overlay-ramdisk-iq5eycdr/ramdisk
191 14:47:54.219180 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:47:54.219440 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 14:47:54.219593 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167057/compress-overlay-zzsa_oe8/overlay-1.5.2.4.tar.gz to ramdisk
194 14:47:54.219718 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167057/compress-overlay-zzsa_oe8/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167057/extract-overlay-ramdisk-iq5eycdr/ramdisk
195 14:47:54.231987 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:47:54.232213 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 14:47:54.232364 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:47:54.232519 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 14:47:54.232670 Building ramdisk /var/lib/lava/dispatcher/tmp/14167057/extract-overlay-ramdisk-iq5eycdr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167057/extract-overlay-ramdisk-iq5eycdr/ramdisk
200 14:47:55.471667 >> 465919 blocks
201 14:48:02.046214 rename /var/lib/lava/dispatcher/tmp/14167057/extract-overlay-ramdisk-iq5eycdr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/ramdisk/ramdisk.cpio.gz
202 14:48:02.046784 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 14:48:02.046972 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 14:48:02.047140 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 14:48:02.047295 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/kernel/Image']
206 14:48:16.924399 Returned 0 in 14 seconds
207 14:48:17.025161 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/kernel/image.itb
208 14:48:17.893710 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:48:17.894098 output: Created: Tue Jun 4 15:48:17 2024
210 14:48:17.894177 output: Image 0 (kernel-1)
211 14:48:17.894242 output: Description:
212 14:48:17.894301 output: Created: Tue Jun 4 15:48:17 2024
213 14:48:17.894373 output: Type: Kernel Image
214 14:48:17.894440 output: Compression: lzma compressed
215 14:48:17.894501 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:48:17.894562 output: Architecture: AArch64
217 14:48:17.894633 output: OS: Linux
218 14:48:17.894726 output: Load Address: 0x00000000
219 14:48:17.894817 output: Entry Point: 0x00000000
220 14:48:17.894905 output: Hash algo: crc32
221 14:48:17.895002 output: Hash value: 88dcd836
222 14:48:17.895089 output: Image 1 (fdt-1)
223 14:48:17.895173 output: Description: mt8192-asurada-spherion-r0
224 14:48:17.895263 output: Created: Tue Jun 4 15:48:17 2024
225 14:48:17.895324 output: Type: Flat Device Tree
226 14:48:17.895379 output: Compression: uncompressed
227 14:48:17.895433 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 14:48:17.895497 output: Architecture: AArch64
229 14:48:17.895582 output: Hash algo: crc32
230 14:48:17.895665 output: Hash value: 0f8e4d2e
231 14:48:17.895755 output: Image 2 (ramdisk-1)
232 14:48:17.895840 output: Description: unavailable
233 14:48:17.895927 output: Created: Tue Jun 4 15:48:17 2024
234 14:48:17.896030 output: Type: RAMDisk Image
235 14:48:17.896128 output: Compression: Unknown Compression
236 14:48:17.896209 output: Data Size: 60983930 Bytes = 59554.62 KiB = 58.16 MiB
237 14:48:17.896286 output: Architecture: AArch64
238 14:48:17.896367 output: OS: Linux
239 14:48:17.896456 output: Load Address: unavailable
240 14:48:17.896540 output: Entry Point: unavailable
241 14:48:17.896614 output: Hash algo: crc32
242 14:48:17.896705 output: Hash value: cabb09f3
243 14:48:17.896789 output: Default Configuration: 'conf-1'
244 14:48:17.896871 output: Configuration 0 (conf-1)
245 14:48:17.896953 output: Description: mt8192-asurada-spherion-r0
246 14:48:17.897045 output: Kernel: kernel-1
247 14:48:17.897128 output: Init Ramdisk: ramdisk-1
248 14:48:17.897211 output: FDT: fdt-1
249 14:48:17.897285 output: Loadables: kernel-1
250 14:48:17.897339 output:
251 14:48:17.897552 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 14:48:17.897649 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 14:48:17.897770 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 14:48:17.897870 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 14:48:17.897960 No LXC device requested
256 14:48:17.898066 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:48:17.898151 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 14:48:17.898227 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:48:17.898296 Checking files for TFTP limit of 4294967296 bytes.
260 14:48:17.898827 end: 1 tftp-deploy (duration 00:00:27) [common]
261 14:48:17.898961 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:48:17.899084 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:48:17.899256 substitutions:
264 14:48:17.899352 - {DTB}: 14167057/tftp-deploy-88w71y31/dtb/mt8192-asurada-spherion-r0.dtb
265 14:48:17.899446 - {INITRD}: 14167057/tftp-deploy-88w71y31/ramdisk/ramdisk.cpio.gz
266 14:48:17.899546 - {KERNEL}: 14167057/tftp-deploy-88w71y31/kernel/Image
267 14:48:17.899636 - {LAVA_MAC}: None
268 14:48:17.899722 - {PRESEED_CONFIG}: None
269 14:48:17.899807 - {PRESEED_LOCAL}: None
270 14:48:17.899887 - {RAMDISK}: 14167057/tftp-deploy-88w71y31/ramdisk/ramdisk.cpio.gz
271 14:48:17.899944 - {ROOT_PART}: None
272 14:48:17.900000 - {ROOT}: None
273 14:48:17.900059 - {SERVER_IP}: 192.168.201.1
274 14:48:17.900138 - {TEE}: None
275 14:48:17.900195 Parsed boot commands:
276 14:48:17.900250 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:48:17.900445 Parsed boot commands: tftpboot 192.168.201.1 14167057/tftp-deploy-88w71y31/kernel/image.itb 14167057/tftp-deploy-88w71y31/kernel/cmdline
278 14:48:17.900569 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:48:17.900697 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:48:17.900812 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:48:17.900933 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:48:17.901017 Not connected, no need to disconnect.
283 14:48:17.901144 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:48:17.901268 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:48:17.901382 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 14:48:17.905200 Setting prompt string to ['lava-test: # ']
287 14:48:17.905589 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:48:17.905696 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:48:17.905810 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:48:17.905898 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:48:17.906112 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
292 14:48:23.043205 >> Command sent successfully.
293 14:48:23.045791 Returned 0 in 5 seconds
294 14:48:23.146221 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 14:48:23.146610 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 14:48:23.146725 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 14:48:23.146816 Setting prompt string to 'Starting depthcharge on Spherion...'
299 14:48:23.146884 Changing prompt to 'Starting depthcharge on Spherion...'
300 14:48:23.146969 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 14:48:23.147400 [Enter `^Ec?' for help]
302 14:48:23.317579
303 14:48:23.317735
304 14:48:23.317804 F0: 102B 0000
305 14:48:23.317866
306 14:48:23.317946 F3: 1001 0000 [0200]
307 14:48:23.320775
308 14:48:23.320852 F3: 1001 0000
309 14:48:23.320916
310 14:48:23.320975 F7: 102D 0000
311 14:48:23.321034
312 14:48:23.323998 F1: 0000 0000
313 14:48:23.324102
314 14:48:23.324193 V0: 0000 0000 [0001]
315 14:48:23.324295
316 14:48:23.327674 00: 0007 8000
317 14:48:23.327754
318 14:48:23.327816 01: 0000 0000
319 14:48:23.327889
320 14:48:23.331259 BP: 0C00 0209 [0000]
321 14:48:23.331358
322 14:48:23.331448 G0: 1182 0000
323 14:48:23.331538
324 14:48:23.334547 EC: 0000 0021 [4000]
325 14:48:23.334687
326 14:48:23.334775 S7: 0000 0000 [0000]
327 14:48:23.334861
328 14:48:23.337947 CC: 0000 0000 [0001]
329 14:48:23.338031
330 14:48:23.338090 T0: 0000 0040 [010F]
331 14:48:23.338147
332 14:48:23.338201 Jump to BL
333 14:48:23.338256
334 14:48:23.364742
335 14:48:23.364886
336 14:48:23.372040 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 14:48:23.376120 ARM64: Exception handlers installed.
338 14:48:23.379456 ARM64: Testing exception
339 14:48:23.382619 ARM64: Done test exception
340 14:48:23.389177 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 14:48:23.399430 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 14:48:23.406445 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 14:48:23.416696 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 14:48:23.422905 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 14:48:23.429682 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 14:48:23.441774 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 14:48:23.448001 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 14:48:23.467458 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 14:48:23.470829 WDT: Last reset was cold boot
350 14:48:23.474010 SPI1(PAD0) initialized at 2873684 Hz
351 14:48:23.477609 SPI5(PAD0) initialized at 992727 Hz
352 14:48:23.480776 VBOOT: Loading verstage.
353 14:48:23.487517 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 14:48:23.490580 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 14:48:23.493940 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 14:48:23.497414 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 14:48:23.504714 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 14:48:23.511374 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 14:48:23.522677 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
360 14:48:23.522777
361 14:48:23.522852
362 14:48:23.532346 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 14:48:23.535825 ARM64: Exception handlers installed.
364 14:48:23.539287 ARM64: Testing exception
365 14:48:23.539376 ARM64: Done test exception
366 14:48:23.545817 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 14:48:23.549195 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 14:48:23.563185 Probing TPM: . done!
369 14:48:23.563283 TPM ready after 0 ms
370 14:48:23.570243 Connected to device vid:did:rid of 1ae0:0028:00
371 14:48:23.577574 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 14:48:23.618244 Initialized TPM device CR50 revision 0
373 14:48:23.630279 tlcl_send_startup: Startup return code is 0
374 14:48:23.630371 TPM: setup succeeded
375 14:48:23.641676 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 14:48:23.650448 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 14:48:23.662878 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 14:48:23.671124 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 14:48:23.674508 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 14:48:23.677759 in-header: 03 07 00 00 08 00 00 00
381 14:48:23.681394 in-data: aa e4 47 04 13 02 00 00
382 14:48:23.685341 Chrome EC: UHEPI supported
383 14:48:23.692276 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 14:48:23.696002 in-header: 03 9d 00 00 08 00 00 00
385 14:48:23.700424 in-data: 10 20 20 08 00 00 00 00
386 14:48:23.700536 Phase 1
387 14:48:23.703503 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 14:48:23.710396 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 14:48:23.714186 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 14:48:23.718318 Recovery requested (1009000e)
391 14:48:23.722564 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 14:48:23.730867 tlcl_extend: response is 0
393 14:48:23.739037 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 14:48:23.744672 tlcl_extend: response is 0
395 14:48:23.751224 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 14:48:23.772591 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 14:48:23.779402 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 14:48:23.779496
399 14:48:23.779562
400 14:48:23.790216 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 14:48:23.790317 ARM64: Exception handlers installed.
402 14:48:23.793995 ARM64: Testing exception
403 14:48:23.797224 ARM64: Done test exception
404 14:48:23.814421 pmic_efuse_setting: Set efuses in 11 msecs
405 14:48:23.823406 pmwrap_interface_init: Select PMIF_VLD_RDY
406 14:48:23.826948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 14:48:23.830697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 14:48:23.837803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 14:48:23.841278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 14:48:23.845085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 14:48:23.852291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 14:48:23.855743 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 14:48:23.859608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 14:48:23.866590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 14:48:23.869561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 14:48:23.872733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 14:48:23.879355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 14:48:23.883142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 14:48:23.889406 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 14:48:23.896440 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 14:48:23.899740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 14:48:23.905914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 14:48:23.912687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 14:48:23.920093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 14:48:23.923818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 14:48:23.927499 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 14:48:23.935092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 14:48:23.941475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 14:48:23.944930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 14:48:23.949303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 14:48:23.955893 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 14:48:23.963001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 14:48:23.966882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 14:48:23.970164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 14:48:23.977026 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 14:48:23.980016 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 14:48:23.987041 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 14:48:23.990744 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 14:48:23.998157 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 14:48:24.002054 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 14:48:24.005518 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 14:48:24.012760 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 14:48:24.016122 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 14:48:24.019524 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 14:48:24.025682 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 14:48:24.029128 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 14:48:24.032484 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 14:48:24.039193 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 14:48:24.042494 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 14:48:24.046012 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 14:48:24.052802 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 14:48:24.056031 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 14:48:24.059374 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 14:48:24.062843 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 14:48:24.069638 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 14:48:24.072920 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 14:48:24.079006 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 14:48:24.089037 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 14:48:24.092222 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 14:48:24.102281 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 14:48:24.108811 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 14:48:24.115548 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 14:48:24.119169 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 14:48:24.122353 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 14:48:24.130157 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 14:48:24.136472 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 14:48:24.139848 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 14:48:24.143066 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 14:48:24.154492 [RTC]rtc_get_frequency_meter,154: input=15, output=793
470 14:48:24.158191 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 14:48:24.164842 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 14:48:24.167947 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
473 14:48:24.171210 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 14:48:24.174496 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
475 14:48:24.177892 ADC[4]: Raw value=897780 ID=7
476 14:48:24.181258 ADC[3]: Raw value=212700 ID=1
477 14:48:24.185053 RAM Code: 0x71
478 14:48:24.188327 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 14:48:24.192101 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 14:48:24.199797 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 14:48:24.207100 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 14:48:24.210720 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 14:48:24.214297 in-header: 03 07 00 00 08 00 00 00
484 14:48:24.218140 in-data: aa e4 47 04 13 02 00 00
485 14:48:24.221963 Chrome EC: UHEPI supported
486 14:48:24.225313 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 14:48:24.230292 in-header: 03 95 00 00 08 00 00 00
488 14:48:24.233588 in-data: 18 20 20 08 00 00 00 00
489 14:48:24.236987 MRC: failed to locate region type 0.
490 14:48:24.244572 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 14:48:24.248333 DRAM-K: Running full calibration
492 14:48:24.255756 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 14:48:24.255884 header.status = 0x0
494 14:48:24.259699 header.version = 0x6 (expected: 0x6)
495 14:48:24.263014 header.size = 0xd00 (expected: 0xd00)
496 14:48:24.263137 header.flags = 0x0
497 14:48:24.269734 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 14:48:24.288103 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
499 14:48:24.294681 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 14:48:24.298487 dram_init: ddr_geometry: 2
501 14:48:24.298608 [EMI] MDL number = 2
502 14:48:24.301344 [EMI] Get MDL freq = 0
503 14:48:24.305066 dram_init: ddr_type: 0
504 14:48:24.305191 is_discrete_lpddr4: 1
505 14:48:24.308876 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 14:48:24.309013
507 14:48:24.309127
508 14:48:24.312590 [Bian_co] ETT version 0.0.0.1
509 14:48:24.316401 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 14:48:24.316525
511 14:48:24.319836 dramc_set_vcore_voltage set vcore to 650000
512 14:48:24.323171 Read voltage for 800, 4
513 14:48:24.323292 Vio18 = 0
514 14:48:24.323404 Vcore = 650000
515 14:48:24.326971 Vdram = 0
516 14:48:24.327097 Vddq = 0
517 14:48:24.327212 Vmddr = 0
518 14:48:24.330465 dram_init: config_dvfs: 1
519 14:48:24.333682 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 14:48:24.340332 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 14:48:24.343582 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 14:48:24.347061 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 14:48:24.350173 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 14:48:24.356533 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 14:48:24.356668 MEM_TYPE=3, freq_sel=18
526 14:48:24.359804 sv_algorithm_assistance_LP4_1600
527 14:48:24.366716 ============ PULL DRAM RESETB DOWN ============
528 14:48:24.370028 ========== PULL DRAM RESETB DOWN end =========
529 14:48:24.373337 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 14:48:24.376507 ===================================
531 14:48:24.380271 LPDDR4 DRAM CONFIGURATION
532 14:48:24.383593 ===================================
533 14:48:24.383717 EX_ROW_EN[0] = 0x0
534 14:48:24.386963 EX_ROW_EN[1] = 0x0
535 14:48:24.390210 LP4Y_EN = 0x0
536 14:48:24.390333 WORK_FSP = 0x0
537 14:48:24.393001 WL = 0x2
538 14:48:24.393123 RL = 0x2
539 14:48:24.396804 BL = 0x2
540 14:48:24.396925 RPST = 0x0
541 14:48:24.399977 RD_PRE = 0x0
542 14:48:24.400099 WR_PRE = 0x1
543 14:48:24.403215 WR_PST = 0x0
544 14:48:24.403336 DBI_WR = 0x0
545 14:48:24.406564 DBI_RD = 0x0
546 14:48:24.406684 OTF = 0x1
547 14:48:24.409965 ===================================
548 14:48:24.413182 ===================================
549 14:48:24.416155 ANA top config
550 14:48:24.420152 ===================================
551 14:48:24.420270 DLL_ASYNC_EN = 0
552 14:48:24.422962 ALL_SLAVE_EN = 1
553 14:48:24.426795 NEW_RANK_MODE = 1
554 14:48:24.430045 DLL_IDLE_MODE = 1
555 14:48:24.433038 LP45_APHY_COMB_EN = 1
556 14:48:24.433158 TX_ODT_DIS = 1
557 14:48:24.436404 NEW_8X_MODE = 1
558 14:48:24.439714 ===================================
559 14:48:24.443387 ===================================
560 14:48:24.446589 data_rate = 1600
561 14:48:24.449777 CKR = 1
562 14:48:24.453066 DQ_P2S_RATIO = 8
563 14:48:24.456189 ===================================
564 14:48:24.456313 CA_P2S_RATIO = 8
565 14:48:24.459572 DQ_CA_OPEN = 0
566 14:48:24.463117 DQ_SEMI_OPEN = 0
567 14:48:24.466382 CA_SEMI_OPEN = 0
568 14:48:24.469854 CA_FULL_RATE = 0
569 14:48:24.473272 DQ_CKDIV4_EN = 1
570 14:48:24.473397 CA_CKDIV4_EN = 1
571 14:48:24.476609 CA_PREDIV_EN = 0
572 14:48:24.479808 PH8_DLY = 0
573 14:48:24.482786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 14:48:24.486621 DQ_AAMCK_DIV = 4
575 14:48:24.489765 CA_AAMCK_DIV = 4
576 14:48:24.489901 CA_ADMCK_DIV = 4
577 14:48:24.493561 DQ_TRACK_CA_EN = 0
578 14:48:24.496449 CA_PICK = 800
579 14:48:24.499521 CA_MCKIO = 800
580 14:48:24.502902 MCKIO_SEMI = 0
581 14:48:24.506367 PLL_FREQ = 3068
582 14:48:24.509492 DQ_UI_PI_RATIO = 32
583 14:48:24.509613 CA_UI_PI_RATIO = 0
584 14:48:24.512761 ===================================
585 14:48:24.516283 ===================================
586 14:48:24.519482 memory_type:LPDDR4
587 14:48:24.522706 GP_NUM : 10
588 14:48:24.522825 SRAM_EN : 1
589 14:48:24.526732 MD32_EN : 0
590 14:48:24.529413 ===================================
591 14:48:24.532767 [ANA_INIT] >>>>>>>>>>>>>>
592 14:48:24.532889 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 14:48:24.539366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 14:48:24.543018 ===================================
595 14:48:24.543141 data_rate = 1600,PCW = 0X7600
596 14:48:24.546513 ===================================
597 14:48:24.549837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 14:48:24.556074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 14:48:24.562684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 14:48:24.566337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 14:48:24.569940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 14:48:24.573393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 14:48:24.576457 [ANA_INIT] flow start
604 14:48:24.576599 [ANA_INIT] PLL >>>>>>>>
605 14:48:24.580379 [ANA_INIT] PLL <<<<<<<<
606 14:48:24.580498 [ANA_INIT] MIDPI >>>>>>>>
607 14:48:24.583709 [ANA_INIT] MIDPI <<<<<<<<
608 14:48:24.587666 [ANA_INIT] DLL >>>>>>>>
609 14:48:24.587789 [ANA_INIT] flow end
610 14:48:24.591195 ============ LP4 DIFF to SE enter ============
611 14:48:24.598192 ============ LP4 DIFF to SE exit ============
612 14:48:24.598324 [ANA_INIT] <<<<<<<<<<<<<
613 14:48:24.602052 [Flow] Enable top DCM control >>>>>
614 14:48:24.605672 [Flow] Enable top DCM control <<<<<
615 14:48:24.609941 Enable DLL master slave shuffle
616 14:48:24.613037 ==============================================================
617 14:48:24.616919 Gating Mode config
618 14:48:24.620298 ==============================================================
619 14:48:24.623326 Config description:
620 14:48:24.634346 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 14:48:24.641646 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 14:48:24.645191 SELPH_MODE 0: By rank 1: By Phase
623 14:48:24.648452 ==============================================================
624 14:48:24.652144 GAT_TRACK_EN = 1
625 14:48:24.655651 RX_GATING_MODE = 2
626 14:48:24.659025 RX_GATING_TRACK_MODE = 2
627 14:48:24.662835 SELPH_MODE = 1
628 14:48:24.666191 PICG_EARLY_EN = 1
629 14:48:24.669419 VALID_LAT_VALUE = 1
630 14:48:24.673387 ==============================================================
631 14:48:24.677043 Enter into Gating configuration >>>>
632 14:48:24.680820 Exit from Gating configuration <<<<
633 14:48:24.684222 Enter into DVFS_PRE_config >>>>>
634 14:48:24.694927 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 14:48:24.698443 Exit from DVFS_PRE_config <<<<<
636 14:48:24.702320 Enter into PICG configuration >>>>
637 14:48:24.706167 Exit from PICG configuration <<<<
638 14:48:24.706250 [RX_INPUT] configuration >>>>>
639 14:48:24.709398 [RX_INPUT] configuration <<<<<
640 14:48:24.713303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 14:48:24.720635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 14:48:24.728095 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 14:48:24.731657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 14:48:24.739375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 14:48:24.746933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 14:48:24.750242 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 14:48:24.754115 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 14:48:24.757924 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 14:48:24.761789 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 14:48:24.765363 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 14:48:24.768762 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 14:48:24.772754 ===================================
653 14:48:24.776618 LPDDR4 DRAM CONFIGURATION
654 14:48:24.780390 ===================================
655 14:48:24.780513 EX_ROW_EN[0] = 0x0
656 14:48:24.783828 EX_ROW_EN[1] = 0x0
657 14:48:24.783957 LP4Y_EN = 0x0
658 14:48:24.787198 WORK_FSP = 0x0
659 14:48:24.787322 WL = 0x2
660 14:48:24.791284 RL = 0x2
661 14:48:24.791408 BL = 0x2
662 14:48:24.794951 RPST = 0x0
663 14:48:24.795076 RD_PRE = 0x0
664 14:48:24.795187 WR_PRE = 0x1
665 14:48:24.798920 WR_PST = 0x0
666 14:48:24.799043 DBI_WR = 0x0
667 14:48:24.802361 DBI_RD = 0x0
668 14:48:24.802485 OTF = 0x1
669 14:48:24.806498 ===================================
670 14:48:24.809955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 14:48:24.813357 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 14:48:24.820730 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 14:48:24.820856 ===================================
674 14:48:24.824677 LPDDR4 DRAM CONFIGURATION
675 14:48:24.828434 ===================================
676 14:48:24.831725 EX_ROW_EN[0] = 0x10
677 14:48:24.831809 EX_ROW_EN[1] = 0x0
678 14:48:24.835782 LP4Y_EN = 0x0
679 14:48:24.835866 WORK_FSP = 0x0
680 14:48:24.835932 WL = 0x2
681 14:48:24.839267 RL = 0x2
682 14:48:24.839377 BL = 0x2
683 14:48:24.843137 RPST = 0x0
684 14:48:24.843220 RD_PRE = 0x0
685 14:48:24.846951 WR_PRE = 0x1
686 14:48:24.847034 WR_PST = 0x0
687 14:48:24.850519 DBI_WR = 0x0
688 14:48:24.850602 DBI_RD = 0x0
689 14:48:24.853897 OTF = 0x1
690 14:48:24.857873 ===================================
691 14:48:24.860804 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 14:48:24.866635 nWR fixed to 40
693 14:48:24.869983 [ModeRegInit_LP4] CH0 RK0
694 14:48:24.870104 [ModeRegInit_LP4] CH0 RK1
695 14:48:24.873638 [ModeRegInit_LP4] CH1 RK0
696 14:48:24.873764 [ModeRegInit_LP4] CH1 RK1
697 14:48:24.877540 match AC timing 13
698 14:48:24.881394 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 14:48:24.884740 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 14:48:24.888396 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 14:48:24.895562 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 14:48:24.899320 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 14:48:24.899446 [EMI DOE] emi_dcm 0
704 14:48:24.906406 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 14:48:24.906535 ==
706 14:48:24.910378 Dram Type= 6, Freq= 0, CH_0, rank 0
707 14:48:24.914682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 14:48:24.914810 ==
709 14:48:24.918204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 14:48:24.924919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 14:48:24.933530 [CA 0] Center 38 (7~69) winsize 63
712 14:48:24.936907 [CA 1] Center 37 (7~68) winsize 62
713 14:48:24.940254 [CA 2] Center 35 (5~66) winsize 62
714 14:48:24.943331 [CA 3] Center 35 (5~66) winsize 62
715 14:48:24.947095 [CA 4] Center 34 (4~65) winsize 62
716 14:48:24.949928 [CA 5] Center 34 (3~65) winsize 63
717 14:48:24.950053
718 14:48:24.953404 [CmdBusTrainingLP45] Vref(ca) range 1: 34
719 14:48:24.953530
720 14:48:24.956904 [CATrainingPosCal] consider 1 rank data
721 14:48:24.960295 u2DelayCellTimex100 = 270/100 ps
722 14:48:24.963620 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 14:48:24.966630 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
724 14:48:24.973667 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 14:48:24.977038 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 14:48:24.980261 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 14:48:24.983775 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
728 14:48:24.983898
729 14:48:24.986879 CA PerBit enable=1, Macro0, CA PI delay=34
730 14:48:24.987005
731 14:48:24.990242 [CBTSetCACLKResult] CA Dly = 34
732 14:48:24.990366 CS Dly: 6 (0~37)
733 14:48:24.990479 ==
734 14:48:24.993508 Dram Type= 6, Freq= 0, CH_0, rank 1
735 14:48:25.000101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 14:48:25.000228 ==
737 14:48:25.003765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 14:48:25.010469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 14:48:25.019630 [CA 0] Center 38 (7~69) winsize 63
740 14:48:25.023075 [CA 1] Center 38 (7~69) winsize 63
741 14:48:25.026577 [CA 2] Center 35 (5~66) winsize 62
742 14:48:25.029918 [CA 3] Center 35 (5~66) winsize 62
743 14:48:25.033104 [CA 4] Center 34 (4~65) winsize 62
744 14:48:25.036500 [CA 5] Center 34 (4~65) winsize 62
745 14:48:25.036632
746 14:48:25.039619 [CmdBusTrainingLP45] Vref(ca) range 1: 32
747 14:48:25.039743
748 14:48:25.043168 [CATrainingPosCal] consider 2 rank data
749 14:48:25.046545 u2DelayCellTimex100 = 270/100 ps
750 14:48:25.049696 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 14:48:25.053089 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
752 14:48:25.059964 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 14:48:25.063402 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 14:48:25.066727 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 14:48:25.069613 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 14:48:25.069737
757 14:48:25.073179 CA PerBit enable=1, Macro0, CA PI delay=34
758 14:48:25.073301
759 14:48:25.076425 [CBTSetCACLKResult] CA Dly = 34
760 14:48:25.076549 CS Dly: 6 (0~38)
761 14:48:25.076670
762 14:48:25.079685 ----->DramcWriteLeveling(PI) begin...
763 14:48:25.083250 ==
764 14:48:25.086563 Dram Type= 6, Freq= 0, CH_0, rank 0
765 14:48:25.089588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 14:48:25.089724 ==
767 14:48:25.093088 Write leveling (Byte 0): 31 => 31
768 14:48:25.096485 Write leveling (Byte 1): 31 => 31
769 14:48:25.099827 DramcWriteLeveling(PI) end<-----
770 14:48:25.099950
771 14:48:25.100063 ==
772 14:48:25.103048 Dram Type= 6, Freq= 0, CH_0, rank 0
773 14:48:25.106351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 14:48:25.106474 ==
775 14:48:25.109680 [Gating] SW mode calibration
776 14:48:25.116222 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 14:48:25.119823 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 14:48:25.126383 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 14:48:25.129610 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 14:48:25.132833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
781 14:48:25.139535 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 14:48:25.142796 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 14:48:25.146233 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 14:48:25.153296 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 14:48:25.156587 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 14:48:25.160458 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 14:48:25.163920 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 14:48:25.171760 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 14:48:25.175655 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:48:25.178880 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:48:25.182114 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:48:25.185809 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:48:25.192735 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:48:25.196139 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:48:25.199480 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
796 14:48:25.206294 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 14:48:25.209655 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
798 14:48:25.212902 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 14:48:25.219385 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:48:25.222633 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:48:25.225812 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:48:25.232834 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 14:48:25.236178 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 14:48:25.239549 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 14:48:25.242968 0 9 12 | B1->B0 | 2524 3333 | 1 1 | (0 0) (1 1)
806 14:48:25.249315 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 14:48:25.253030 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 14:48:25.256078 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 14:48:25.262736 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 14:48:25.266116 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 14:48:25.269374 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 14:48:25.276254 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
813 14:48:25.279422 0 10 12 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
814 14:48:25.282832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 14:48:25.289524 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 14:48:25.293197 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 14:48:25.295947 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 14:48:25.302561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 14:48:25.305698 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 14:48:25.309214 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
821 14:48:25.315949 0 11 12 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
822 14:48:25.319218 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 14:48:25.322330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 14:48:25.329426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 14:48:25.332350 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 14:48:25.336059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 14:48:25.342584 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 14:48:25.345927 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
829 14:48:25.349394 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 14:48:25.355909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 14:48:25.359303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 14:48:25.362488 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 14:48:25.365666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 14:48:25.372487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 14:48:25.375886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 14:48:25.379292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 14:48:25.385949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:48:25.389321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:48:25.392438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:48:25.399506 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:48:25.402714 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:48:25.406088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:48:25.412545 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:48:25.415774 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 14:48:25.419270 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 14:48:25.422452 Total UI for P1: 0, mck2ui 16
847 14:48:25.425624 best dqsien dly found for B0: ( 0, 14, 8)
848 14:48:25.432335 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 14:48:25.432457 Total UI for P1: 0, mck2ui 16
850 14:48:25.436086 best dqsien dly found for B1: ( 0, 14, 12)
851 14:48:25.442297 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 14:48:25.445732 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
853 14:48:25.445815
854 14:48:25.449293 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 14:48:25.452354 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
856 14:48:25.455705 [Gating] SW calibration Done
857 14:48:25.455830 ==
858 14:48:25.458945 Dram Type= 6, Freq= 0, CH_0, rank 0
859 14:48:25.462511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 14:48:25.462631 ==
861 14:48:25.465732 RX Vref Scan: 0
862 14:48:25.465853
863 14:48:25.465965 RX Vref 0 -> 0, step: 1
864 14:48:25.466073
865 14:48:25.469041 RX Delay -130 -> 252, step: 16
866 14:48:25.472394 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 14:48:25.478722 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 14:48:25.482236 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 14:48:25.485527 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 14:48:25.488821 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 14:48:25.492234 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 14:48:25.498782 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 14:48:25.502039 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 14:48:25.505151 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 14:48:25.508963 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 14:48:25.511862 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 14:48:25.519033 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 14:48:25.521843 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 14:48:25.525307 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 14:48:25.528544 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
881 14:48:25.531972 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 14:48:25.535659 ==
883 14:48:25.535743 Dram Type= 6, Freq= 0, CH_0, rank 0
884 14:48:25.542341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 14:48:25.542424 ==
886 14:48:25.542490 DQS Delay:
887 14:48:25.545532 DQS0 = 0, DQS1 = 0
888 14:48:25.545614 DQM Delay:
889 14:48:25.549060 DQM0 = 81, DQM1 = 70
890 14:48:25.549143 DQ Delay:
891 14:48:25.552021 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 14:48:25.555531 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 14:48:25.558729 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 14:48:25.562061 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
895 14:48:25.562144
896 14:48:25.562208
897 14:48:25.562269 ==
898 14:48:25.566295 Dram Type= 6, Freq= 0, CH_0, rank 0
899 14:48:25.569596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 14:48:25.569705 ==
901 14:48:25.569773
902 14:48:25.569834
903 14:48:25.572983 TX Vref Scan disable
904 14:48:25.573066 == TX Byte 0 ==
905 14:48:25.579684 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 14:48:25.582658 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 14:48:25.582733 == TX Byte 1 ==
908 14:48:25.589401 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 14:48:25.592918 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 14:48:25.593019 ==
911 14:48:25.596137 Dram Type= 6, Freq= 0, CH_0, rank 0
912 14:48:25.599469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 14:48:25.599552 ==
914 14:48:25.613181 TX Vref=22, minBit 1, minWin=26, winSum=435
915 14:48:25.616445 TX Vref=24, minBit 7, minWin=26, winSum=437
916 14:48:25.619809 TX Vref=26, minBit 14, minWin=26, winSum=440
917 14:48:25.623168 TX Vref=28, minBit 2, minWin=27, winSum=440
918 14:48:25.626129 TX Vref=30, minBit 9, minWin=27, winSum=441
919 14:48:25.629555 TX Vref=32, minBit 9, minWin=27, winSum=443
920 14:48:25.636361 [TxChooseVref] Worse bit 9, Min win 27, Win sum 443, Final Vref 32
921 14:48:25.636481
922 14:48:25.639790 Final TX Range 1 Vref 32
923 14:48:25.639909
924 14:48:25.640020 ==
925 14:48:25.642771 Dram Type= 6, Freq= 0, CH_0, rank 0
926 14:48:25.646412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 14:48:25.646535 ==
928 14:48:25.646648
929 14:48:25.649513
930 14:48:25.649635 TX Vref Scan disable
931 14:48:25.653361 == TX Byte 0 ==
932 14:48:25.656227 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 14:48:25.659779 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 14:48:25.663531 == TX Byte 1 ==
935 14:48:25.666628 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 14:48:25.670289 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 14:48:25.670370
938 14:48:25.673210 [DATLAT]
939 14:48:25.673291 Freq=800, CH0 RK0
940 14:48:25.673355
941 14:48:25.676473 DATLAT Default: 0xa
942 14:48:25.676610 0, 0xFFFF, sum = 0
943 14:48:25.679724 1, 0xFFFF, sum = 0
944 14:48:25.679861 2, 0xFFFF, sum = 0
945 14:48:25.683083 3, 0xFFFF, sum = 0
946 14:48:25.683166 4, 0xFFFF, sum = 0
947 14:48:25.686390 5, 0xFFFF, sum = 0
948 14:48:25.686473 6, 0xFFFF, sum = 0
949 14:48:25.689988 7, 0xFFFF, sum = 0
950 14:48:25.690070 8, 0xFFFF, sum = 0
951 14:48:25.692938 9, 0x0, sum = 1
952 14:48:25.693020 10, 0x0, sum = 2
953 14:48:25.696160 11, 0x0, sum = 3
954 14:48:25.696243 12, 0x0, sum = 4
955 14:48:25.699444 best_step = 10
956 14:48:25.699537
957 14:48:25.699601 ==
958 14:48:25.703143 Dram Type= 6, Freq= 0, CH_0, rank 0
959 14:48:25.706709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 14:48:25.706791 ==
961 14:48:25.709616 RX Vref Scan: 1
962 14:48:25.709696
963 14:48:25.709760 Set Vref Range= 32 -> 127
964 14:48:25.709819
965 14:48:25.712975 RX Vref 32 -> 127, step: 1
966 14:48:25.713056
967 14:48:25.716350 RX Delay -111 -> 252, step: 8
968 14:48:25.716431
969 14:48:25.719416 Set Vref, RX VrefLevel [Byte0]: 32
970 14:48:25.722710 [Byte1]: 32
971 14:48:25.722832
972 14:48:25.726648 Set Vref, RX VrefLevel [Byte0]: 33
973 14:48:25.729341 [Byte1]: 33
974 14:48:25.733636
975 14:48:25.733754 Set Vref, RX VrefLevel [Byte0]: 34
976 14:48:25.737036 [Byte1]: 34
977 14:48:25.740897
978 14:48:25.741014 Set Vref, RX VrefLevel [Byte0]: 35
979 14:48:25.744269 [Byte1]: 35
980 14:48:25.748631
981 14:48:25.748751 Set Vref, RX VrefLevel [Byte0]: 36
982 14:48:25.752125 [Byte1]: 36
983 14:48:25.756128
984 14:48:25.756232 Set Vref, RX VrefLevel [Byte0]: 37
985 14:48:25.759565 [Byte1]: 37
986 14:48:25.764086
987 14:48:25.764167 Set Vref, RX VrefLevel [Byte0]: 38
988 14:48:25.767569 [Byte1]: 38
989 14:48:25.771847
990 14:48:25.771928 Set Vref, RX VrefLevel [Byte0]: 39
991 14:48:25.774631 [Byte1]: 39
992 14:48:25.779107
993 14:48:25.779187 Set Vref, RX VrefLevel [Byte0]: 40
994 14:48:25.782446 [Byte1]: 40
995 14:48:25.786875
996 14:48:25.786955 Set Vref, RX VrefLevel [Byte0]: 41
997 14:48:25.790089 [Byte1]: 41
998 14:48:25.794407
999 14:48:25.794488 Set Vref, RX VrefLevel [Byte0]: 42
1000 14:48:25.797769 [Byte1]: 42
1001 14:48:25.802023
1002 14:48:25.802104 Set Vref, RX VrefLevel [Byte0]: 43
1003 14:48:25.805383 [Byte1]: 43
1004 14:48:25.810001
1005 14:48:25.810082 Set Vref, RX VrefLevel [Byte0]: 44
1006 14:48:25.813029 [Byte1]: 44
1007 14:48:25.817702
1008 14:48:25.817783 Set Vref, RX VrefLevel [Byte0]: 45
1009 14:48:25.820783 [Byte1]: 45
1010 14:48:25.825341
1011 14:48:25.825423 Set Vref, RX VrefLevel [Byte0]: 46
1012 14:48:25.828946 [Byte1]: 46
1013 14:48:25.833408
1014 14:48:25.833488 Set Vref, RX VrefLevel [Byte0]: 47
1015 14:48:25.836296 [Byte1]: 47
1016 14:48:25.841213
1017 14:48:25.841295 Set Vref, RX VrefLevel [Byte0]: 48
1018 14:48:25.844407 [Byte1]: 48
1019 14:48:25.848782
1020 14:48:25.848862 Set Vref, RX VrefLevel [Byte0]: 49
1021 14:48:25.852076 [Byte1]: 49
1022 14:48:25.855829
1023 14:48:25.855911 Set Vref, RX VrefLevel [Byte0]: 50
1024 14:48:25.859041 [Byte1]: 50
1025 14:48:25.863576
1026 14:48:25.863658 Set Vref, RX VrefLevel [Byte0]: 51
1027 14:48:25.867029 [Byte1]: 51
1028 14:48:25.870747
1029 14:48:25.870825 Set Vref, RX VrefLevel [Byte0]: 52
1030 14:48:25.874131 [Byte1]: 52
1031 14:48:25.878752
1032 14:48:25.878830 Set Vref, RX VrefLevel [Byte0]: 53
1033 14:48:25.882121 [Byte1]: 53
1034 14:48:25.886019
1035 14:48:25.886103 Set Vref, RX VrefLevel [Byte0]: 54
1036 14:48:25.889318 [Byte1]: 54
1037 14:48:25.894144
1038 14:48:25.894261 Set Vref, RX VrefLevel [Byte0]: 55
1039 14:48:25.897264 [Byte1]: 55
1040 14:48:25.901244
1041 14:48:25.901312 Set Vref, RX VrefLevel [Byte0]: 56
1042 14:48:25.904807 [Byte1]: 56
1043 14:48:25.908997
1044 14:48:25.909075 Set Vref, RX VrefLevel [Byte0]: 57
1045 14:48:25.912674 [Byte1]: 57
1046 14:48:25.916503
1047 14:48:25.916635 Set Vref, RX VrefLevel [Byte0]: 58
1048 14:48:25.920174 [Byte1]: 58
1049 14:48:25.924267
1050 14:48:25.924345 Set Vref, RX VrefLevel [Byte0]: 59
1051 14:48:25.927707 [Byte1]: 59
1052 14:48:25.932434
1053 14:48:25.932512 Set Vref, RX VrefLevel [Byte0]: 60
1054 14:48:25.935478 [Byte1]: 60
1055 14:48:25.939661
1056 14:48:25.939740 Set Vref, RX VrefLevel [Byte0]: 61
1057 14:48:25.943347 [Byte1]: 61
1058 14:48:25.947362
1059 14:48:25.947447 Set Vref, RX VrefLevel [Byte0]: 62
1060 14:48:25.950539 [Byte1]: 62
1061 14:48:25.955161
1062 14:48:25.955232 Set Vref, RX VrefLevel [Byte0]: 63
1063 14:48:25.958446 [Byte1]: 63
1064 14:48:25.962746
1065 14:48:25.962826 Set Vref, RX VrefLevel [Byte0]: 64
1066 14:48:25.966043 [Byte1]: 64
1067 14:48:25.970694
1068 14:48:25.970772 Set Vref, RX VrefLevel [Byte0]: 65
1069 14:48:25.973784 [Byte1]: 65
1070 14:48:25.977767
1071 14:48:25.977838 Set Vref, RX VrefLevel [Byte0]: 66
1072 14:48:25.981214 [Byte1]: 66
1073 14:48:25.985612
1074 14:48:25.985690 Set Vref, RX VrefLevel [Byte0]: 67
1075 14:48:25.988885 [Byte1]: 67
1076 14:48:25.993520
1077 14:48:25.993637 Set Vref, RX VrefLevel [Byte0]: 68
1078 14:48:25.996499 [Byte1]: 68
1079 14:48:26.000811
1080 14:48:26.000891 Set Vref, RX VrefLevel [Byte0]: 69
1081 14:48:26.004120 [Byte1]: 69
1082 14:48:26.008709
1083 14:48:26.008822 Set Vref, RX VrefLevel [Byte0]: 70
1084 14:48:26.011818 [Byte1]: 70
1085 14:48:26.016019
1086 14:48:26.016106 Set Vref, RX VrefLevel [Byte0]: 71
1087 14:48:26.019495 [Byte1]: 71
1088 14:48:26.023915
1089 14:48:26.023998 Set Vref, RX VrefLevel [Byte0]: 72
1090 14:48:26.026860 [Byte1]: 72
1091 14:48:26.031385
1092 14:48:26.031475 Set Vref, RX VrefLevel [Byte0]: 73
1093 14:48:26.034584 [Byte1]: 73
1094 14:48:26.039148
1095 14:48:26.039242 Set Vref, RX VrefLevel [Byte0]: 74
1096 14:48:26.042183 [Byte1]: 74
1097 14:48:26.047069
1098 14:48:26.047165 Set Vref, RX VrefLevel [Byte0]: 75
1099 14:48:26.050261 [Byte1]: 75
1100 14:48:26.054501
1101 14:48:26.054588 Set Vref, RX VrefLevel [Byte0]: 76
1102 14:48:26.057739 [Byte1]: 76
1103 14:48:26.062275
1104 14:48:26.062352 Set Vref, RX VrefLevel [Byte0]: 77
1105 14:48:26.065370 [Byte1]: 77
1106 14:48:26.069477
1107 14:48:26.069557 Set Vref, RX VrefLevel [Byte0]: 78
1108 14:48:26.072733 [Byte1]: 78
1109 14:48:26.077373
1110 14:48:26.077450 Set Vref, RX VrefLevel [Byte0]: 79
1111 14:48:26.081037 [Byte1]: 79
1112 14:48:26.084740
1113 14:48:26.084839 Final RX Vref Byte 0 = 61 to rank0
1114 14:48:26.088214 Final RX Vref Byte 1 = 61 to rank0
1115 14:48:26.091502 Final RX Vref Byte 0 = 61 to rank1
1116 14:48:26.094936 Final RX Vref Byte 1 = 61 to rank1==
1117 14:48:26.098154 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 14:48:26.104969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 14:48:26.105063 ==
1120 14:48:26.105147 DQS Delay:
1121 14:48:26.105239 DQS0 = 0, DQS1 = 0
1122 14:48:26.108202 DQM Delay:
1123 14:48:26.108315 DQM0 = 81, DQM1 = 67
1124 14:48:26.111485 DQ Delay:
1125 14:48:26.114813 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 14:48:26.114911 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1127 14:48:26.118551 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 14:48:26.121659 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1129 14:48:26.125301
1130 14:48:26.125401
1131 14:48:26.131844 [DQSOSCAuto] RK0, (LSB)MR18= 0x2625, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1132 14:48:26.135270 CH0 RK0: MR19=606, MR18=2625
1133 14:48:26.141878 CH0_RK0: MR19=0x606, MR18=0x2625, DQSOSC=400, MR23=63, INC=92, DEC=61
1134 14:48:26.141958
1135 14:48:26.145071 ----->DramcWriteLeveling(PI) begin...
1136 14:48:26.145171 ==
1137 14:48:26.148362 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 14:48:26.151617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 14:48:26.151715 ==
1140 14:48:26.155009 Write leveling (Byte 0): 31 => 31
1141 14:48:26.158251 Write leveling (Byte 1): 29 => 29
1142 14:48:26.161844 DramcWriteLeveling(PI) end<-----
1143 14:48:26.161939
1144 14:48:26.162025 ==
1145 14:48:26.165254 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 14:48:26.168776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 14:48:26.168852 ==
1148 14:48:26.171927 [Gating] SW mode calibration
1149 14:48:26.178481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 14:48:26.185375 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 14:48:26.188261 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 14:48:26.191617 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 14:48:26.198419 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 14:48:26.202215 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 14:48:26.204992 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 14:48:26.211953 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 14:48:26.215347 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 14:48:26.218635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 14:48:26.225491 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 14:48:26.228426 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 14:48:26.231772 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 14:48:26.235284 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 14:48:26.241842 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 14:48:26.285622 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 14:48:26.285945 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 14:48:26.286045 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 14:48:26.286175 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 14:48:26.286539 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 14:48:26.286856 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 14:48:26.287138 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 14:48:26.287237 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 14:48:26.287314 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 14:48:26.287564 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 14:48:26.322251 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 14:48:26.322607 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 14:48:26.322739 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 14:48:26.322883 0 9 8 | B1->B0 | 2424 2c2c | 0 0 | (1 1) (0 0)
1178 14:48:26.323036 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1179 14:48:26.323176 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 14:48:26.323322 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 14:48:26.323414 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 14:48:26.326492 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 14:48:26.329909 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 14:48:26.333319 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1185 14:48:26.336463 0 10 8 | B1->B0 | 3030 2929 | 0 0 | (0 1) (1 1)
1186 14:48:26.343275 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 14:48:26.346386 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 14:48:26.349730 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 14:48:26.356174 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 14:48:26.359738 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 14:48:26.363003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 14:48:26.369759 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1193 14:48:26.373083 0 11 8 | B1->B0 | 2e2e 3b3b | 0 0 | (1 1) (0 0)
1194 14:48:26.376423 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1195 14:48:26.382996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 14:48:26.386454 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 14:48:26.389640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 14:48:26.396480 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 14:48:26.400478 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 14:48:26.403504 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 14:48:26.407210 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 14:48:26.411187 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 14:48:26.417955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 14:48:26.421198 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 14:48:26.425167 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 14:48:26.432337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 14:48:26.435236 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 14:48:26.438681 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 14:48:26.442095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 14:48:26.448611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 14:48:26.451972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 14:48:26.455231 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 14:48:26.461628 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 14:48:26.465258 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 14:48:26.468633 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 14:48:26.474749 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 14:48:26.478077 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 14:48:26.481512 Total UI for P1: 0, mck2ui 16
1219 14:48:26.485256 best dqsien dly found for B0: ( 0, 14, 4)
1220 14:48:26.488434 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 14:48:26.491388 Total UI for P1: 0, mck2ui 16
1222 14:48:26.494719 best dqsien dly found for B1: ( 0, 14, 8)
1223 14:48:26.498332 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1224 14:48:26.501740 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 14:48:26.501821
1226 14:48:26.505040 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 14:48:26.511510 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 14:48:26.511632 [Gating] SW calibration Done
1229 14:48:26.511738 ==
1230 14:48:26.514872 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 14:48:26.521590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 14:48:26.521680 ==
1233 14:48:26.521779 RX Vref Scan: 0
1234 14:48:26.521869
1235 14:48:26.525165 RX Vref 0 -> 0, step: 1
1236 14:48:26.525280
1237 14:48:26.528535 RX Delay -130 -> 252, step: 16
1238 14:48:26.531439 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1239 14:48:26.535121 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 14:48:26.538684 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1241 14:48:26.544754 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1242 14:48:26.548276 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1243 14:48:26.551710 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1244 14:48:26.555077 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1245 14:48:26.558040 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 14:48:26.564805 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1247 14:48:26.568174 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 14:48:26.571734 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 14:48:26.574825 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1250 14:48:26.578488 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1251 14:48:26.584861 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1252 14:48:26.588228 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1253 14:48:26.591499 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1254 14:48:26.591625 ==
1255 14:48:26.594977 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 14:48:26.598355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 14:48:26.598478 ==
1258 14:48:26.601678 DQS Delay:
1259 14:48:26.601804 DQS0 = 0, DQS1 = 0
1260 14:48:26.604891 DQM Delay:
1261 14:48:26.605017 DQM0 = 78, DQM1 = 69
1262 14:48:26.605132 DQ Delay:
1263 14:48:26.608530 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1264 14:48:26.611569 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1265 14:48:26.614801 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1266 14:48:26.618144 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1267 14:48:26.618270
1268 14:48:26.618382
1269 14:48:26.618491 ==
1270 14:48:26.621491 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 14:48:26.628176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 14:48:26.628301 ==
1273 14:48:26.628422
1274 14:48:26.628532
1275 14:48:26.628648 TX Vref Scan disable
1276 14:48:26.631929 == TX Byte 0 ==
1277 14:48:26.635424 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1278 14:48:26.639155 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1279 14:48:26.642179 == TX Byte 1 ==
1280 14:48:26.645224 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1281 14:48:26.652134 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1282 14:48:26.652230 ==
1283 14:48:26.655243 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 14:48:26.658751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 14:48:26.658851 ==
1286 14:48:26.671320 TX Vref=22, minBit 11, minWin=26, winSum=435
1287 14:48:26.674414 TX Vref=24, minBit 0, minWin=27, winSum=436
1288 14:48:26.677678 TX Vref=26, minBit 7, minWin=27, winSum=442
1289 14:48:26.681185 TX Vref=28, minBit 7, minWin=27, winSum=446
1290 14:48:26.684463 TX Vref=30, minBit 2, minWin=27, winSum=445
1291 14:48:26.687845 TX Vref=32, minBit 2, minWin=27, winSum=443
1292 14:48:26.694656 [TxChooseVref] Worse bit 7, Min win 27, Win sum 446, Final Vref 28
1293 14:48:26.694799
1294 14:48:26.697791 Final TX Range 1 Vref 28
1295 14:48:26.697873
1296 14:48:26.697937 ==
1297 14:48:26.701113 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 14:48:26.704546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 14:48:26.704640 ==
1300 14:48:26.704704
1301 14:48:26.707820
1302 14:48:26.707934 TX Vref Scan disable
1303 14:48:26.711192 == TX Byte 0 ==
1304 14:48:26.714452 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 14:48:26.717798 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 14:48:26.721049 == TX Byte 1 ==
1307 14:48:26.724745 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1308 14:48:26.728229 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1309 14:48:26.731479
1310 14:48:26.731552 [DATLAT]
1311 14:48:26.731617 Freq=800, CH0 RK1
1312 14:48:26.731678
1313 14:48:26.734817 DATLAT Default: 0xa
1314 14:48:26.734887 0, 0xFFFF, sum = 0
1315 14:48:26.738192 1, 0xFFFF, sum = 0
1316 14:48:26.738278 2, 0xFFFF, sum = 0
1317 14:48:26.741548 3, 0xFFFF, sum = 0
1318 14:48:26.741631 4, 0xFFFF, sum = 0
1319 14:48:26.744822 5, 0xFFFF, sum = 0
1320 14:48:26.744904 6, 0xFFFF, sum = 0
1321 14:48:26.747887 7, 0xFFFF, sum = 0
1322 14:48:26.751469 8, 0xFFFF, sum = 0
1323 14:48:26.751583 9, 0x0, sum = 1
1324 14:48:26.751684 10, 0x0, sum = 2
1325 14:48:26.754551 11, 0x0, sum = 3
1326 14:48:26.754633 12, 0x0, sum = 4
1327 14:48:26.757980 best_step = 10
1328 14:48:26.758062
1329 14:48:26.758125 ==
1330 14:48:26.761313 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 14:48:26.764443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 14:48:26.764526 ==
1333 14:48:26.767817 RX Vref Scan: 0
1334 14:48:26.767931
1335 14:48:26.768021 RX Vref 0 -> 0, step: 1
1336 14:48:26.768106
1337 14:48:26.771475 RX Delay -111 -> 252, step: 8
1338 14:48:26.778198 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1339 14:48:26.781511 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1340 14:48:26.784618 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1341 14:48:26.788008 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1342 14:48:26.791490 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1343 14:48:26.797708 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1344 14:48:26.801177 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1345 14:48:26.805327 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1346 14:48:26.807938 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1347 14:48:26.811142 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1348 14:48:26.817844 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1349 14:48:26.821092 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1350 14:48:26.824573 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1351 14:48:26.828186 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1352 14:48:26.831589 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1353 14:48:26.837802 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1354 14:48:26.837876 ==
1355 14:48:26.841250 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 14:48:26.844547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 14:48:26.844631 ==
1358 14:48:26.844692 DQS Delay:
1359 14:48:26.847760 DQS0 = 0, DQS1 = 0
1360 14:48:26.847829 DQM Delay:
1361 14:48:26.851106 DQM0 = 78, DQM1 = 70
1362 14:48:26.851179 DQ Delay:
1363 14:48:26.854372 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1364 14:48:26.857868 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1365 14:48:26.861200 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1366 14:48:26.864321 DQ12 =80, DQ13 =72, DQ14 =80, DQ15 =80
1367 14:48:26.864427
1368 14:48:26.864518
1369 14:48:26.874280 [DQSOSCAuto] RK1, (LSB)MR18= 0x4520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1370 14:48:26.874362 CH0 RK1: MR19=606, MR18=4520
1371 14:48:26.881364 CH0_RK1: MR19=0x606, MR18=0x4520, DQSOSC=392, MR23=63, INC=96, DEC=64
1372 14:48:26.884618 [RxdqsGatingPostProcess] freq 800
1373 14:48:26.891019 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 14:48:26.894525 Pre-setting of DQS Precalculation
1375 14:48:26.898348 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 14:48:26.898465 ==
1377 14:48:26.901545 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 14:48:26.904945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 14:48:26.905027 ==
1380 14:48:26.911343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 14:48:26.918200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 14:48:26.926694 [CA 0] Center 36 (6~66) winsize 61
1383 14:48:26.929867 [CA 1] Center 36 (6~67) winsize 62
1384 14:48:26.932957 [CA 2] Center 34 (5~64) winsize 60
1385 14:48:26.936520 [CA 3] Center 34 (4~64) winsize 61
1386 14:48:26.939872 [CA 4] Center 34 (4~65) winsize 62
1387 14:48:26.943183 [CA 5] Center 34 (4~64) winsize 61
1388 14:48:26.943262
1389 14:48:26.946422 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 14:48:26.946501
1391 14:48:26.949768 [CATrainingPosCal] consider 1 rank data
1392 14:48:26.952863 u2DelayCellTimex100 = 270/100 ps
1393 14:48:26.956768 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1394 14:48:26.960006 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 14:48:26.966429 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1396 14:48:26.969901 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 14:48:26.973202 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 14:48:26.976082 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 14:48:26.976161
1400 14:48:26.979895 CA PerBit enable=1, Macro0, CA PI delay=34
1401 14:48:26.979974
1402 14:48:26.983059 [CBTSetCACLKResult] CA Dly = 34
1403 14:48:26.983138 CS Dly: 5 (0~36)
1404 14:48:26.983201 ==
1405 14:48:26.986361 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 14:48:26.992990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 14:48:26.993070 ==
1408 14:48:26.996444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 14:48:27.003155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 14:48:27.012357 [CA 0] Center 36 (6~67) winsize 62
1411 14:48:27.015629 [CA 1] Center 36 (6~67) winsize 62
1412 14:48:27.018845 [CA 2] Center 34 (4~65) winsize 62
1413 14:48:27.022217 [CA 3] Center 33 (3~64) winsize 62
1414 14:48:27.025818 [CA 4] Center 34 (4~65) winsize 62
1415 14:48:27.028836 [CA 5] Center 33 (3~64) winsize 62
1416 14:48:27.028933
1417 14:48:27.032324 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 14:48:27.032406
1419 14:48:27.036053 [CATrainingPosCal] consider 2 rank data
1420 14:48:27.038969 u2DelayCellTimex100 = 270/100 ps
1421 14:48:27.042150 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1422 14:48:27.049103 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 14:48:27.052388 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1424 14:48:27.055905 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 14:48:27.059757 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 14:48:27.063121 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 14:48:27.063201
1428 14:48:27.066441 CA PerBit enable=1, Macro0, CA PI delay=34
1429 14:48:27.066521
1430 14:48:27.070195 [CBTSetCACLKResult] CA Dly = 34
1431 14:48:27.070275 CS Dly: 6 (0~38)
1432 14:48:27.070338
1433 14:48:27.073896 ----->DramcWriteLeveling(PI) begin...
1434 14:48:27.073995 ==
1435 14:48:27.077292 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 14:48:27.081203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 14:48:27.081283 ==
1438 14:48:27.084523 Write leveling (Byte 0): 27 => 27
1439 14:48:27.088920 Write leveling (Byte 1): 30 => 30
1440 14:48:27.092301 DramcWriteLeveling(PI) end<-----
1441 14:48:27.092391
1442 14:48:27.092452 ==
1443 14:48:27.096144 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 14:48:27.099290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 14:48:27.099387 ==
1446 14:48:27.102503 [Gating] SW mode calibration
1447 14:48:27.108999 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 14:48:27.112648 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 14:48:27.119017 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 14:48:27.122583 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 14:48:27.125937 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1452 14:48:27.132552 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 14:48:27.135595 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 14:48:27.139356 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 14:48:27.145940 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 14:48:27.149218 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 14:48:27.152391 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 14:48:27.159390 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 14:48:27.162403 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 14:48:27.165812 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 14:48:27.172348 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 14:48:27.175640 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 14:48:27.178978 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 14:48:27.185770 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 14:48:27.188978 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 14:48:27.192442 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 14:48:27.195772 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 14:48:27.202363 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 14:48:27.205535 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 14:48:27.209302 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 14:48:27.215797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 14:48:27.218954 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 14:48:27.222263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 14:48:27.228747 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 14:48:27.232389 0 9 8 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
1476 14:48:27.235703 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 14:48:27.242414 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 14:48:27.245593 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 14:48:27.249180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 14:48:27.255797 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 14:48:27.259182 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 14:48:27.262392 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1483 14:48:27.268915 0 10 8 | B1->B0 | 2e2e 2c2c | 1 0 | (1 1) (0 1)
1484 14:48:27.272115 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 14:48:27.275838 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 14:48:27.282422 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 14:48:27.285715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 14:48:27.288903 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 14:48:27.295669 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 14:48:27.299101 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1491 14:48:27.302188 0 11 8 | B1->B0 | 3e3e 3a3a | 0 0 | (0 0) (1 1)
1492 14:48:27.305614 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 14:48:27.312259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 14:48:27.315541 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 14:48:27.319010 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 14:48:27.325586 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 14:48:27.329138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 14:48:27.332292 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 14:48:27.338782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 14:48:27.342329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 14:48:27.345504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 14:48:27.352456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 14:48:27.355485 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 14:48:27.358740 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 14:48:27.365710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 14:48:27.368532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 14:48:27.372220 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 14:48:27.378732 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 14:48:27.382182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 14:48:27.385336 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 14:48:27.391937 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 14:48:27.395503 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 14:48:27.398624 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 14:48:27.402279 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 14:48:27.408717 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 14:48:27.412037 Total UI for P1: 0, mck2ui 16
1517 14:48:27.415687 best dqsien dly found for B0: ( 0, 14, 4)
1518 14:48:27.418760 Total UI for P1: 0, mck2ui 16
1519 14:48:27.422235 best dqsien dly found for B1: ( 0, 14, 4)
1520 14:48:27.425438 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1521 14:48:27.428627 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1522 14:48:27.428701
1523 14:48:27.431949 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 14:48:27.435286 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 14:48:27.438945 [Gating] SW calibration Done
1526 14:48:27.439018 ==
1527 14:48:27.442173 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 14:48:27.445296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 14:48:27.445371 ==
1530 14:48:27.448653 RX Vref Scan: 0
1531 14:48:27.448724
1532 14:48:27.448784 RX Vref 0 -> 0, step: 1
1533 14:48:27.448840
1534 14:48:27.452254 RX Delay -130 -> 252, step: 16
1535 14:48:27.458755 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1536 14:48:27.462266 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1537 14:48:27.465148 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1538 14:48:27.469110 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1539 14:48:27.471853 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1540 14:48:27.478366 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1541 14:48:27.482056 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1542 14:48:27.485146 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1543 14:48:27.488879 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1544 14:48:27.491852 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1545 14:48:27.495070 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1546 14:48:27.502414 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1547 14:48:27.505644 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1548 14:48:27.509066 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1549 14:48:27.512151 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1550 14:48:27.518663 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1551 14:48:27.518743 ==
1552 14:48:27.521886 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 14:48:27.525276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 14:48:27.525364 ==
1555 14:48:27.525443 DQS Delay:
1556 14:48:27.528807 DQS0 = 0, DQS1 = 0
1557 14:48:27.528877 DQM Delay:
1558 14:48:27.532063 DQM0 = 82, DQM1 = 72
1559 14:48:27.532140 DQ Delay:
1560 14:48:27.535351 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1561 14:48:27.538694 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1562 14:48:27.541991 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1563 14:48:27.545627 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1564 14:48:27.545699
1565 14:48:27.545763
1566 14:48:27.545819 ==
1567 14:48:27.548953 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 14:48:27.552249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 14:48:27.552320 ==
1570 14:48:27.552378
1571 14:48:27.552434
1572 14:48:27.555535 TX Vref Scan disable
1573 14:48:27.558937 == TX Byte 0 ==
1574 14:48:27.562363 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 14:48:27.565586 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 14:48:27.568830 == TX Byte 1 ==
1577 14:48:27.572384 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 14:48:27.575696 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 14:48:27.575768 ==
1580 14:48:27.579055 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 14:48:27.582264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 14:48:27.585498 ==
1583 14:48:27.596966 TX Vref=22, minBit 1, minWin=27, winSum=442
1584 14:48:27.600238 TX Vref=24, minBit 1, minWin=27, winSum=442
1585 14:48:27.603548 TX Vref=26, minBit 6, minWin=27, winSum=448
1586 14:48:27.606844 TX Vref=28, minBit 5, minWin=27, winSum=447
1587 14:48:27.609943 TX Vref=30, minBit 5, minWin=27, winSum=449
1588 14:48:27.613302 TX Vref=32, minBit 0, minWin=27, winSum=444
1589 14:48:27.620297 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 30
1590 14:48:27.620379
1591 14:48:27.623476 Final TX Range 1 Vref 30
1592 14:48:27.623557
1593 14:48:27.623619 ==
1594 14:48:27.626474 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 14:48:27.629975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 14:48:27.630056 ==
1597 14:48:27.630118
1598 14:48:27.633289
1599 14:48:27.633368 TX Vref Scan disable
1600 14:48:27.637074 == TX Byte 0 ==
1601 14:48:27.640905 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 14:48:27.644397 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 14:48:27.647423 == TX Byte 1 ==
1604 14:48:27.650741 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 14:48:27.653847 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 14:48:27.653928
1607 14:48:27.657186 [DATLAT]
1608 14:48:27.657265 Freq=800, CH1 RK0
1609 14:48:27.657328
1610 14:48:27.660525 DATLAT Default: 0xa
1611 14:48:27.660671 0, 0xFFFF, sum = 0
1612 14:48:27.664107 1, 0xFFFF, sum = 0
1613 14:48:27.664204 2, 0xFFFF, sum = 0
1614 14:48:27.667485 3, 0xFFFF, sum = 0
1615 14:48:27.667566 4, 0xFFFF, sum = 0
1616 14:48:27.670819 5, 0xFFFF, sum = 0
1617 14:48:27.670900 6, 0xFFFF, sum = 0
1618 14:48:27.673934 7, 0xFFFF, sum = 0
1619 14:48:27.674032 8, 0xFFFF, sum = 0
1620 14:48:27.677625 9, 0x0, sum = 1
1621 14:48:27.677722 10, 0x0, sum = 2
1622 14:48:27.680595 11, 0x0, sum = 3
1623 14:48:27.680691 12, 0x0, sum = 4
1624 14:48:27.684215 best_step = 10
1625 14:48:27.684294
1626 14:48:27.684357 ==
1627 14:48:27.687276 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 14:48:27.690555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 14:48:27.690653 ==
1630 14:48:27.693785 RX Vref Scan: 1
1631 14:48:27.693864
1632 14:48:27.693926 Set Vref Range= 32 -> 127
1633 14:48:27.693985
1634 14:48:27.697591 RX Vref 32 -> 127, step: 1
1635 14:48:27.697671
1636 14:48:27.700842 RX Delay -111 -> 252, step: 8
1637 14:48:27.700937
1638 14:48:27.704206 Set Vref, RX VrefLevel [Byte0]: 32
1639 14:48:27.707453 [Byte1]: 32
1640 14:48:27.707532
1641 14:48:27.710832 Set Vref, RX VrefLevel [Byte0]: 33
1642 14:48:27.714052 [Byte1]: 33
1643 14:48:27.717353
1644 14:48:27.717433 Set Vref, RX VrefLevel [Byte0]: 34
1645 14:48:27.720670 [Byte1]: 34
1646 14:48:27.725381
1647 14:48:27.725460 Set Vref, RX VrefLevel [Byte0]: 35
1648 14:48:27.728077 [Byte1]: 35
1649 14:48:27.732578
1650 14:48:27.732671 Set Vref, RX VrefLevel [Byte0]: 36
1651 14:48:27.736013 [Byte1]: 36
1652 14:48:27.740272
1653 14:48:27.740353 Set Vref, RX VrefLevel [Byte0]: 37
1654 14:48:27.743466 [Byte1]: 37
1655 14:48:27.747887
1656 14:48:27.747993 Set Vref, RX VrefLevel [Byte0]: 38
1657 14:48:27.751112 [Byte1]: 38
1658 14:48:27.755394
1659 14:48:27.755475 Set Vref, RX VrefLevel [Byte0]: 39
1660 14:48:27.758684 [Byte1]: 39
1661 14:48:27.763116
1662 14:48:27.763196 Set Vref, RX VrefLevel [Byte0]: 40
1663 14:48:27.766384 [Byte1]: 40
1664 14:48:27.770497
1665 14:48:27.770574 Set Vref, RX VrefLevel [Byte0]: 41
1666 14:48:27.773779 [Byte1]: 41
1667 14:48:27.778688
1668 14:48:27.778815 Set Vref, RX VrefLevel [Byte0]: 42
1669 14:48:27.781495 [Byte1]: 42
1670 14:48:27.785847
1671 14:48:27.785928 Set Vref, RX VrefLevel [Byte0]: 43
1672 14:48:27.789265 [Byte1]: 43
1673 14:48:27.793882
1674 14:48:27.794005 Set Vref, RX VrefLevel [Byte0]: 44
1675 14:48:27.797348 [Byte1]: 44
1676 14:48:27.801096
1677 14:48:27.801177 Set Vref, RX VrefLevel [Byte0]: 45
1678 14:48:27.804892 [Byte1]: 45
1679 14:48:27.809231
1680 14:48:27.809311 Set Vref, RX VrefLevel [Byte0]: 46
1681 14:48:27.812404 [Byte1]: 46
1682 14:48:27.816734
1683 14:48:27.816814 Set Vref, RX VrefLevel [Byte0]: 47
1684 14:48:27.819968 [Byte1]: 47
1685 14:48:27.824467
1686 14:48:27.824548 Set Vref, RX VrefLevel [Byte0]: 48
1687 14:48:27.827720 [Byte1]: 48
1688 14:48:27.831778
1689 14:48:27.831858 Set Vref, RX VrefLevel [Byte0]: 49
1690 14:48:27.835562 [Byte1]: 49
1691 14:48:27.839702
1692 14:48:27.839782 Set Vref, RX VrefLevel [Byte0]: 50
1693 14:48:27.843054 [Byte1]: 50
1694 14:48:27.847479
1695 14:48:27.847559 Set Vref, RX VrefLevel [Byte0]: 51
1696 14:48:27.850431 [Byte1]: 51
1697 14:48:27.854839
1698 14:48:27.854922 Set Vref, RX VrefLevel [Byte0]: 52
1699 14:48:27.858015 [Byte1]: 52
1700 14:48:27.862421
1701 14:48:27.862502 Set Vref, RX VrefLevel [Byte0]: 53
1702 14:48:27.865920 [Byte1]: 53
1703 14:48:27.870304
1704 14:48:27.870384 Set Vref, RX VrefLevel [Byte0]: 54
1705 14:48:27.873429 [Byte1]: 54
1706 14:48:27.877837
1707 14:48:27.877917 Set Vref, RX VrefLevel [Byte0]: 55
1708 14:48:27.881324 [Byte1]: 55
1709 14:48:27.885814
1710 14:48:27.885893 Set Vref, RX VrefLevel [Byte0]: 56
1711 14:48:27.888522 [Byte1]: 56
1712 14:48:27.892852
1713 14:48:27.892932 Set Vref, RX VrefLevel [Byte0]: 57
1714 14:48:27.896134 [Byte1]: 57
1715 14:48:27.900938
1716 14:48:27.901018 Set Vref, RX VrefLevel [Byte0]: 58
1717 14:48:27.903872 [Byte1]: 58
1718 14:48:27.908325
1719 14:48:27.908405 Set Vref, RX VrefLevel [Byte0]: 59
1720 14:48:27.911968 [Byte1]: 59
1721 14:48:27.916118
1722 14:48:27.916230 Set Vref, RX VrefLevel [Byte0]: 60
1723 14:48:27.919223 [Byte1]: 60
1724 14:48:27.923451
1725 14:48:27.923531 Set Vref, RX VrefLevel [Byte0]: 61
1726 14:48:27.926956 [Byte1]: 61
1727 14:48:27.931466
1728 14:48:27.931546 Set Vref, RX VrefLevel [Byte0]: 62
1729 14:48:27.934658 [Byte1]: 62
1730 14:48:27.939124
1731 14:48:27.939204 Set Vref, RX VrefLevel [Byte0]: 63
1732 14:48:27.942167 [Byte1]: 63
1733 14:48:27.946615
1734 14:48:27.946695 Set Vref, RX VrefLevel [Byte0]: 64
1735 14:48:27.949982 [Byte1]: 64
1736 14:48:27.954481
1737 14:48:27.954561 Set Vref, RX VrefLevel [Byte0]: 65
1738 14:48:27.957740 [Byte1]: 65
1739 14:48:27.961868
1740 14:48:27.961950 Set Vref, RX VrefLevel [Byte0]: 66
1741 14:48:27.965620 [Byte1]: 66
1742 14:48:27.969587
1743 14:48:27.969667 Set Vref, RX VrefLevel [Byte0]: 67
1744 14:48:27.972976 [Byte1]: 67
1745 14:48:27.977140
1746 14:48:27.977266 Set Vref, RX VrefLevel [Byte0]: 68
1747 14:48:27.980414 [Byte1]: 68
1748 14:48:27.984795
1749 14:48:27.984919 Set Vref, RX VrefLevel [Byte0]: 69
1750 14:48:27.988127 [Byte1]: 69
1751 14:48:27.992779
1752 14:48:27.992900 Set Vref, RX VrefLevel [Byte0]: 70
1753 14:48:27.995819 [Byte1]: 70
1754 14:48:28.000069
1755 14:48:28.000187 Set Vref, RX VrefLevel [Byte0]: 71
1756 14:48:28.003586 [Byte1]: 71
1757 14:48:28.008169
1758 14:48:28.008300 Set Vref, RX VrefLevel [Byte0]: 72
1759 14:48:28.010820 [Byte1]: 72
1760 14:48:28.015218
1761 14:48:28.015336 Set Vref, RX VrefLevel [Byte0]: 73
1762 14:48:28.018875 [Byte1]: 73
1763 14:48:28.023202
1764 14:48:28.023323 Set Vref, RX VrefLevel [Byte0]: 74
1765 14:48:28.026104 [Byte1]: 74
1766 14:48:28.030957
1767 14:48:28.031077 Final RX Vref Byte 0 = 59 to rank0
1768 14:48:28.034157 Final RX Vref Byte 1 = 57 to rank0
1769 14:48:28.037546 Final RX Vref Byte 0 = 59 to rank1
1770 14:48:28.040818 Final RX Vref Byte 1 = 57 to rank1==
1771 14:48:28.044481 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 14:48:28.047744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 14:48:28.050649 ==
1774 14:48:28.050730 DQS Delay:
1775 14:48:28.050794 DQS0 = 0, DQS1 = 0
1776 14:48:28.054010 DQM Delay:
1777 14:48:28.054091 DQM0 = 81, DQM1 = 71
1778 14:48:28.057282 DQ Delay:
1779 14:48:28.060709 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1780 14:48:28.060791 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1781 14:48:28.064386 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1782 14:48:28.067419 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1783 14:48:28.070801
1784 14:48:28.070882
1785 14:48:28.077255 [DQSOSCAuto] RK0, (LSB)MR18= 0xe19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1786 14:48:28.080722 CH1 RK0: MR19=606, MR18=E19
1787 14:48:28.087122 CH1_RK0: MR19=0x606, MR18=0xE19, DQSOSC=403, MR23=63, INC=90, DEC=60
1788 14:48:28.087204
1789 14:48:28.090584 ----->DramcWriteLeveling(PI) begin...
1790 14:48:28.090667 ==
1791 14:48:28.093962 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 14:48:28.097317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 14:48:28.097398 ==
1794 14:48:28.100727 Write leveling (Byte 0): 27 => 27
1795 14:48:28.103463 Write leveling (Byte 1): 28 => 28
1796 14:48:28.107037 DramcWriteLeveling(PI) end<-----
1797 14:48:28.107119
1798 14:48:28.107182 ==
1799 14:48:28.110737 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 14:48:28.114185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 14:48:28.114266 ==
1802 14:48:28.117500 [Gating] SW mode calibration
1803 14:48:28.124204 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 14:48:28.130369 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 14:48:28.133870 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 14:48:28.136911 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1807 14:48:28.143438 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1808 14:48:28.147429 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 14:48:28.150422 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 14:48:28.156826 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 14:48:28.160822 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 14:48:28.163535 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 14:48:28.170550 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 14:48:28.173949 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 14:48:28.177010 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 14:48:28.183693 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 14:48:28.186823 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 14:48:28.190382 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 14:48:28.193851 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 14:48:28.200327 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 14:48:28.203631 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 14:48:28.206944 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1823 14:48:28.213903 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 14:48:28.217451 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 14:48:28.220701 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 14:48:28.226846 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 14:48:28.230627 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 14:48:28.233791 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 14:48:28.240692 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 14:48:28.243439 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1831 14:48:28.247008 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1832 14:48:28.253512 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 14:48:28.256925 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 14:48:28.260532 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 14:48:28.267441 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 14:48:28.270577 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 14:48:28.273666 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 14:48:28.280244 0 10 4 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
1839 14:48:28.283488 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
1840 14:48:28.286851 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 14:48:28.293571 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 14:48:28.296942 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 14:48:28.300488 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 14:48:28.303368 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 14:48:28.310356 0 11 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1846 14:48:28.313753 0 11 4 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
1847 14:48:28.317052 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
1848 14:48:28.323391 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 14:48:28.326854 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 14:48:28.330158 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 14:48:28.336744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 14:48:28.339997 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 14:48:28.343933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 14:48:28.350564 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 14:48:28.353385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1856 14:48:28.356711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 14:48:28.363828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 14:48:28.366915 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 14:48:28.370249 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 14:48:28.377018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 14:48:28.380376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 14:48:28.383882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 14:48:28.386964 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 14:48:28.393852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 14:48:28.397229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 14:48:28.400515 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 14:48:28.406929 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 14:48:28.410248 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 14:48:28.413723 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 14:48:28.420121 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1871 14:48:28.423715 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1872 14:48:28.426701 Total UI for P1: 0, mck2ui 16
1873 14:48:28.430218 best dqsien dly found for B0: ( 0, 14, 4)
1874 14:48:28.433919 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 14:48:28.437199 Total UI for P1: 0, mck2ui 16
1876 14:48:28.440453 best dqsien dly found for B1: ( 0, 14, 6)
1877 14:48:28.443837 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1878 14:48:28.446962 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1879 14:48:28.447043
1880 14:48:28.450375 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1881 14:48:28.457084 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1882 14:48:28.457166 [Gating] SW calibration Done
1883 14:48:28.457230 ==
1884 14:48:28.460345 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 14:48:28.467101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 14:48:28.467184 ==
1887 14:48:28.467248 RX Vref Scan: 0
1888 14:48:28.467308
1889 14:48:28.470324 RX Vref 0 -> 0, step: 1
1890 14:48:28.470405
1891 14:48:28.473717 RX Delay -130 -> 252, step: 16
1892 14:48:28.476944 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1893 14:48:28.480200 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1894 14:48:28.483542 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1895 14:48:28.490503 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1896 14:48:28.493861 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1897 14:48:28.497418 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1898 14:48:28.500547 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1899 14:48:28.504488 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1900 14:48:28.510442 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1901 14:48:28.513739 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1902 14:48:28.517195 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1903 14:48:28.520513 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1904 14:48:28.523658 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1905 14:48:28.530336 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1906 14:48:28.533632 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1907 14:48:28.536824 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1908 14:48:28.536906 ==
1909 14:48:28.540519 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 14:48:28.543786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 14:48:28.543869 ==
1912 14:48:28.546818 DQS Delay:
1913 14:48:28.546915 DQS0 = 0, DQS1 = 0
1914 14:48:28.550195 DQM Delay:
1915 14:48:28.550276 DQM0 = 77, DQM1 = 73
1916 14:48:28.550341 DQ Delay:
1917 14:48:28.553644 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1918 14:48:28.556632 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1919 14:48:28.560463 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1920 14:48:28.563422 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1921 14:48:28.563503
1922 14:48:28.563567
1923 14:48:28.566839 ==
1924 14:48:28.570262 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 14:48:28.573392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 14:48:28.573474 ==
1927 14:48:28.573538
1928 14:48:28.573597
1929 14:48:28.577298 TX Vref Scan disable
1930 14:48:28.577379 == TX Byte 0 ==
1931 14:48:28.579981 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1932 14:48:28.586623 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1933 14:48:28.586704 == TX Byte 1 ==
1934 14:48:28.590211 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 14:48:28.596864 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 14:48:28.596946 ==
1937 14:48:28.600294 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 14:48:28.603598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 14:48:28.603679 ==
1940 14:48:28.616972 TX Vref=22, minBit 9, minWin=27, winSum=452
1941 14:48:28.619880 TX Vref=24, minBit 0, minWin=28, winSum=453
1942 14:48:28.623425 TX Vref=26, minBit 0, minWin=28, winSum=456
1943 14:48:28.626939 TX Vref=28, minBit 1, minWin=28, winSum=460
1944 14:48:28.630099 TX Vref=30, minBit 1, minWin=28, winSum=462
1945 14:48:28.633544 TX Vref=32, minBit 0, minWin=28, winSum=457
1946 14:48:28.639786 [TxChooseVref] Worse bit 1, Min win 28, Win sum 462, Final Vref 30
1947 14:48:28.639871
1948 14:48:28.643214 Final TX Range 1 Vref 30
1949 14:48:28.643302
1950 14:48:28.643389 ==
1951 14:48:28.646359 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 14:48:28.649863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 14:48:28.649946 ==
1954 14:48:28.650010
1955 14:48:28.653474
1956 14:48:28.653554 TX Vref Scan disable
1957 14:48:28.656334 == TX Byte 0 ==
1958 14:48:28.659546 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1959 14:48:28.666882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1960 14:48:28.666965 == TX Byte 1 ==
1961 14:48:28.669600 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 14:48:28.676766 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 14:48:28.676848
1964 14:48:28.676910 [DATLAT]
1965 14:48:28.676969 Freq=800, CH1 RK1
1966 14:48:28.677027
1967 14:48:28.679556 DATLAT Default: 0xa
1968 14:48:28.679637 0, 0xFFFF, sum = 0
1969 14:48:28.682980 1, 0xFFFF, sum = 0
1970 14:48:28.683063 2, 0xFFFF, sum = 0
1971 14:48:28.686328 3, 0xFFFF, sum = 0
1972 14:48:28.686411 4, 0xFFFF, sum = 0
1973 14:48:28.689615 5, 0xFFFF, sum = 0
1974 14:48:28.693211 6, 0xFFFF, sum = 0
1975 14:48:28.693310 7, 0xFFFF, sum = 0
1976 14:48:28.696057 8, 0xFFFF, sum = 0
1977 14:48:28.696139 9, 0x0, sum = 1
1978 14:48:28.696204 10, 0x0, sum = 2
1979 14:48:28.699849 11, 0x0, sum = 3
1980 14:48:28.699931 12, 0x0, sum = 4
1981 14:48:28.703151 best_step = 10
1982 14:48:28.703231
1983 14:48:28.703294 ==
1984 14:48:28.706336 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 14:48:28.709716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 14:48:28.709797 ==
1987 14:48:28.713019 RX Vref Scan: 0
1988 14:48:28.713100
1989 14:48:28.713167 RX Vref 0 -> 0, step: 1
1990 14:48:28.713227
1991 14:48:28.716263 RX Delay -111 -> 252, step: 8
1992 14:48:28.723324 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1993 14:48:28.726513 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
1994 14:48:28.730164 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1995 14:48:28.733517 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1996 14:48:28.736681 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1997 14:48:28.743310 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1998 14:48:28.746635 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1999 14:48:28.749764 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2000 14:48:28.753122 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2001 14:48:28.756346 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2002 14:48:28.762963 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2003 14:48:28.766682 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2004 14:48:28.769848 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2005 14:48:28.773016 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2006 14:48:28.776674 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2007 14:48:28.783237 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2008 14:48:28.783319 ==
2009 14:48:28.786569 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 14:48:28.789821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 14:48:28.789903 ==
2012 14:48:28.789971 DQS Delay:
2013 14:48:28.793224 DQS0 = 0, DQS1 = 0
2014 14:48:28.793320 DQM Delay:
2015 14:48:28.796279 DQM0 = 76, DQM1 = 73
2016 14:48:28.796348 DQ Delay:
2017 14:48:28.799990 DQ0 =80, DQ1 =68, DQ2 =64, DQ3 =72
2018 14:48:28.803248 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2019 14:48:28.806661 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2020 14:48:28.809878 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2021 14:48:28.809959
2022 14:48:28.810022
2023 14:48:28.816447 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c34, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2024 14:48:28.819686 CH1 RK1: MR19=606, MR18=1C34
2025 14:48:28.826687 CH1_RK1: MR19=0x606, MR18=0x1C34, DQSOSC=396, MR23=63, INC=94, DEC=62
2026 14:48:28.829858 [RxdqsGatingPostProcess] freq 800
2027 14:48:28.836440 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 14:48:28.839889 Pre-setting of DQS Precalculation
2029 14:48:28.843166 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 14:48:28.849709 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 14:48:28.856309 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 14:48:28.856392
2033 14:48:28.856455
2034 14:48:28.859534 [Calibration Summary] 1600 Mbps
2035 14:48:28.863400 CH 0, Rank 0
2036 14:48:28.863482 SW Impedance : PASS
2037 14:48:28.866144 DUTY Scan : NO K
2038 14:48:28.869382 ZQ Calibration : PASS
2039 14:48:28.869519 Jitter Meter : NO K
2040 14:48:28.872722 CBT Training : PASS
2041 14:48:28.876277 Write leveling : PASS
2042 14:48:28.876416 RX DQS gating : PASS
2043 14:48:28.879531 RX DQ/DQS(RDDQC) : PASS
2044 14:48:28.882878 TX DQ/DQS : PASS
2045 14:48:28.882997 RX DATLAT : PASS
2046 14:48:28.885958 RX DQ/DQS(Engine): PASS
2047 14:48:28.889553 TX OE : NO K
2048 14:48:28.889674 All Pass.
2049 14:48:28.889792
2050 14:48:28.889899 CH 0, Rank 1
2051 14:48:28.893287 SW Impedance : PASS
2052 14:48:28.896381 DUTY Scan : NO K
2053 14:48:28.896505 ZQ Calibration : PASS
2054 14:48:28.899796 Jitter Meter : NO K
2055 14:48:28.899920 CBT Training : PASS
2056 14:48:28.902626 Write leveling : PASS
2057 14:48:28.906184 RX DQS gating : PASS
2058 14:48:28.906290 RX DQ/DQS(RDDQC) : PASS
2059 14:48:28.909362 TX DQ/DQS : PASS
2060 14:48:28.912738 RX DATLAT : PASS
2061 14:48:28.912823 RX DQ/DQS(Engine): PASS
2062 14:48:28.916185 TX OE : NO K
2063 14:48:28.916287 All Pass.
2064 14:48:28.916376
2065 14:48:28.919562 CH 1, Rank 0
2066 14:48:28.919670 SW Impedance : PASS
2067 14:48:28.923236 DUTY Scan : NO K
2068 14:48:28.926639 ZQ Calibration : PASS
2069 14:48:28.926712 Jitter Meter : NO K
2070 14:48:28.929362 CBT Training : PASS
2071 14:48:28.932819 Write leveling : PASS
2072 14:48:28.932898 RX DQS gating : PASS
2073 14:48:28.936252 RX DQ/DQS(RDDQC) : PASS
2074 14:48:28.939398 TX DQ/DQS : PASS
2075 14:48:28.939520 RX DATLAT : PASS
2076 14:48:28.942707 RX DQ/DQS(Engine): PASS
2077 14:48:28.942831 TX OE : NO K
2078 14:48:28.946116 All Pass.
2079 14:48:28.946241
2080 14:48:28.946352 CH 1, Rank 1
2081 14:48:28.949453 SW Impedance : PASS
2082 14:48:28.949581 DUTY Scan : NO K
2083 14:48:28.952541 ZQ Calibration : PASS
2084 14:48:28.956261 Jitter Meter : NO K
2085 14:48:28.956375 CBT Training : PASS
2086 14:48:28.959245 Write leveling : PASS
2087 14:48:28.962668 RX DQS gating : PASS
2088 14:48:28.962788 RX DQ/DQS(RDDQC) : PASS
2089 14:48:28.966216 TX DQ/DQS : PASS
2090 14:48:28.969202 RX DATLAT : PASS
2091 14:48:28.969282 RX DQ/DQS(Engine): PASS
2092 14:48:28.972494 TX OE : NO K
2093 14:48:28.972618 All Pass.
2094 14:48:28.972683
2095 14:48:28.976383 DramC Write-DBI off
2096 14:48:28.979512 PER_BANK_REFRESH: Hybrid Mode
2097 14:48:28.979592 TX_TRACKING: ON
2098 14:48:28.982919 [GetDramInforAfterCalByMRR] Vendor 6.
2099 14:48:28.986038 [GetDramInforAfterCalByMRR] Revision 606.
2100 14:48:28.989314 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 14:48:28.992905 MR0 0x3b3b
2102 14:48:28.993025 MR8 0x5151
2103 14:48:28.995947 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 14:48:28.996077
2105 14:48:28.996184 MR0 0x3b3b
2106 14:48:28.999296 MR8 0x5151
2107 14:48:29.002682 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 14:48:29.002803
2109 14:48:29.013075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 14:48:29.016247 [FAST_K] Save calibration result to emmc
2111 14:48:29.019610 [FAST_K] Save calibration result to emmc
2112 14:48:29.019736 dram_init: config_dvfs: 1
2113 14:48:29.025969 dramc_set_vcore_voltage set vcore to 662500
2114 14:48:29.026101 Read voltage for 1200, 2
2115 14:48:29.029120 Vio18 = 0
2116 14:48:29.029240 Vcore = 662500
2117 14:48:29.029360 Vdram = 0
2118 14:48:29.029470 Vddq = 0
2119 14:48:29.032864 Vmddr = 0
2120 14:48:29.036110 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 14:48:29.042814 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 14:48:29.042938 MEM_TYPE=3, freq_sel=15
2123 14:48:29.046240 sv_algorithm_assistance_LP4_1600
2124 14:48:29.052951 ============ PULL DRAM RESETB DOWN ============
2125 14:48:29.056381 ========== PULL DRAM RESETB DOWN end =========
2126 14:48:29.059717 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 14:48:29.063045 ===================================
2128 14:48:29.066010 LPDDR4 DRAM CONFIGURATION
2129 14:48:29.069613 ===================================
2130 14:48:29.072435 EX_ROW_EN[0] = 0x0
2131 14:48:29.072545 EX_ROW_EN[1] = 0x0
2132 14:48:29.076241 LP4Y_EN = 0x0
2133 14:48:29.076323 WORK_FSP = 0x0
2134 14:48:29.079288 WL = 0x4
2135 14:48:29.079370 RL = 0x4
2136 14:48:29.082626 BL = 0x2
2137 14:48:29.082715 RPST = 0x0
2138 14:48:29.085615 RD_PRE = 0x0
2139 14:48:29.085739 WR_PRE = 0x1
2140 14:48:29.089023 WR_PST = 0x0
2141 14:48:29.089125 DBI_WR = 0x0
2142 14:48:29.092702 DBI_RD = 0x0
2143 14:48:29.092789 OTF = 0x1
2144 14:48:29.095973 ===================================
2145 14:48:29.099256 ===================================
2146 14:48:29.102305 ANA top config
2147 14:48:29.106072 ===================================
2148 14:48:29.108942 DLL_ASYNC_EN = 0
2149 14:48:29.109069 ALL_SLAVE_EN = 0
2150 14:48:29.112474 NEW_RANK_MODE = 1
2151 14:48:29.115865 DLL_IDLE_MODE = 1
2152 14:48:29.118877 LP45_APHY_COMB_EN = 1
2153 14:48:29.122374 TX_ODT_DIS = 1
2154 14:48:29.122498 NEW_8X_MODE = 1
2155 14:48:29.125670 ===================================
2156 14:48:29.128975 ===================================
2157 14:48:29.132126 data_rate = 2400
2158 14:48:29.135384 CKR = 1
2159 14:48:29.138974 DQ_P2S_RATIO = 8
2160 14:48:29.142071 ===================================
2161 14:48:29.145409 CA_P2S_RATIO = 8
2162 14:48:29.145526 DQ_CA_OPEN = 0
2163 14:48:29.148725 DQ_SEMI_OPEN = 0
2164 14:48:29.152220 CA_SEMI_OPEN = 0
2165 14:48:29.155686 CA_FULL_RATE = 0
2166 14:48:29.158871 DQ_CKDIV4_EN = 0
2167 14:48:29.162310 CA_CKDIV4_EN = 0
2168 14:48:29.162436 CA_PREDIV_EN = 0
2169 14:48:29.165483 PH8_DLY = 17
2170 14:48:29.168929 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 14:48:29.172338 DQ_AAMCK_DIV = 4
2172 14:48:29.175509 CA_AAMCK_DIV = 4
2173 14:48:29.178985 CA_ADMCK_DIV = 4
2174 14:48:29.179101 DQ_TRACK_CA_EN = 0
2175 14:48:29.182358 CA_PICK = 1200
2176 14:48:29.185428 CA_MCKIO = 1200
2177 14:48:29.188880 MCKIO_SEMI = 0
2178 14:48:29.192357 PLL_FREQ = 2366
2179 14:48:29.195762 DQ_UI_PI_RATIO = 32
2180 14:48:29.199031 CA_UI_PI_RATIO = 0
2181 14:48:29.202032 ===================================
2182 14:48:29.205274 ===================================
2183 14:48:29.205397 memory_type:LPDDR4
2184 14:48:29.208637 GP_NUM : 10
2185 14:48:29.212125 SRAM_EN : 1
2186 14:48:29.212256 MD32_EN : 0
2187 14:48:29.215556 ===================================
2188 14:48:29.218673 [ANA_INIT] >>>>>>>>>>>>>>
2189 14:48:29.222278 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 14:48:29.225777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 14:48:29.228693 ===================================
2192 14:48:29.232340 data_rate = 2400,PCW = 0X5b00
2193 14:48:29.235687 ===================================
2194 14:48:29.238811 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 14:48:29.242371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 14:48:29.248910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 14:48:29.252345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 14:48:29.255753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 14:48:29.259068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 14:48:29.262573 [ANA_INIT] flow start
2201 14:48:29.265905 [ANA_INIT] PLL >>>>>>>>
2202 14:48:29.265987 [ANA_INIT] PLL <<<<<<<<
2203 14:48:29.269300 [ANA_INIT] MIDPI >>>>>>>>
2204 14:48:29.272070 [ANA_INIT] MIDPI <<<<<<<<
2205 14:48:29.272151 [ANA_INIT] DLL >>>>>>>>
2206 14:48:29.275963 [ANA_INIT] DLL <<<<<<<<
2207 14:48:29.278910 [ANA_INIT] flow end
2208 14:48:29.282359 ============ LP4 DIFF to SE enter ============
2209 14:48:29.285703 ============ LP4 DIFF to SE exit ============
2210 14:48:29.288929 [ANA_INIT] <<<<<<<<<<<<<
2211 14:48:29.292297 [Flow] Enable top DCM control >>>>>
2212 14:48:29.296036 [Flow] Enable top DCM control <<<<<
2213 14:48:29.298951 Enable DLL master slave shuffle
2214 14:48:29.302063 ==============================================================
2215 14:48:29.305850 Gating Mode config
2216 14:48:29.312190 ==============================================================
2217 14:48:29.312323 Config description:
2218 14:48:29.322311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 14:48:29.328899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 14:48:29.332197 SELPH_MODE 0: By rank 1: By Phase
2221 14:48:29.339160 ==============================================================
2222 14:48:29.342027 GAT_TRACK_EN = 1
2223 14:48:29.345590 RX_GATING_MODE = 2
2224 14:48:29.348964 RX_GATING_TRACK_MODE = 2
2225 14:48:29.352072 SELPH_MODE = 1
2226 14:48:29.355557 PICG_EARLY_EN = 1
2227 14:48:29.358969 VALID_LAT_VALUE = 1
2228 14:48:29.362288 ==============================================================
2229 14:48:29.365569 Enter into Gating configuration >>>>
2230 14:48:29.369052 Exit from Gating configuration <<<<
2231 14:48:29.372504 Enter into DVFS_PRE_config >>>>>
2232 14:48:29.382270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 14:48:29.385635 Exit from DVFS_PRE_config <<<<<
2234 14:48:29.388793 Enter into PICG configuration >>>>
2235 14:48:29.392135 Exit from PICG configuration <<<<
2236 14:48:29.395670 [RX_INPUT] configuration >>>>>
2237 14:48:29.398888 [RX_INPUT] configuration <<<<<
2238 14:48:29.402315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 14:48:29.408733 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 14:48:29.415761 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 14:48:29.422194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 14:48:29.428818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 14:48:29.435711 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 14:48:29.438679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 14:48:29.442018 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 14:48:29.445334 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 14:48:29.448671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 14:48:29.455515 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 14:48:29.458685 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 14:48:29.462420 ===================================
2251 14:48:29.465281 LPDDR4 DRAM CONFIGURATION
2252 14:48:29.468692 ===================================
2253 14:48:29.468823 EX_ROW_EN[0] = 0x0
2254 14:48:29.472032 EX_ROW_EN[1] = 0x0
2255 14:48:29.472161 LP4Y_EN = 0x0
2256 14:48:29.475553 WORK_FSP = 0x0
2257 14:48:29.475672 WL = 0x4
2258 14:48:29.479008 RL = 0x4
2259 14:48:29.479132 BL = 0x2
2260 14:48:29.482154 RPST = 0x0
2261 14:48:29.482282 RD_PRE = 0x0
2262 14:48:29.485473 WR_PRE = 0x1
2263 14:48:29.488685 WR_PST = 0x0
2264 14:48:29.488806 DBI_WR = 0x0
2265 14:48:29.492062 DBI_RD = 0x0
2266 14:48:29.492176 OTF = 0x1
2267 14:48:29.495361 ===================================
2268 14:48:29.499480 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 14:48:29.502201 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 14:48:29.508757 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 14:48:29.511973 ===================================
2272 14:48:29.515753 LPDDR4 DRAM CONFIGURATION
2273 14:48:29.518717 ===================================
2274 14:48:29.518846 EX_ROW_EN[0] = 0x10
2275 14:48:29.522287 EX_ROW_EN[1] = 0x0
2276 14:48:29.522407 LP4Y_EN = 0x0
2277 14:48:29.525482 WORK_FSP = 0x0
2278 14:48:29.525608 WL = 0x4
2279 14:48:29.528925 RL = 0x4
2280 14:48:29.529050 BL = 0x2
2281 14:48:29.532051 RPST = 0x0
2282 14:48:29.532168 RD_PRE = 0x0
2283 14:48:29.535488 WR_PRE = 0x1
2284 14:48:29.535617 WR_PST = 0x0
2285 14:48:29.538671 DBI_WR = 0x0
2286 14:48:29.538794 DBI_RD = 0x0
2287 14:48:29.542364 OTF = 0x1
2288 14:48:29.545543 ===================================
2289 14:48:29.551758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 14:48:29.551841 ==
2291 14:48:29.555456 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 14:48:29.558664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 14:48:29.558744 ==
2294 14:48:29.562294 [Duty_Offset_Calibration]
2295 14:48:29.562373 B0:2 B1:0 CA:3
2296 14:48:29.562435
2297 14:48:29.565175 [DutyScan_Calibration_Flow] k_type=0
2298 14:48:29.576189
2299 14:48:29.576348 ==CLK 0==
2300 14:48:29.579032 Final CLK duty delay cell = 0
2301 14:48:29.582309 [0] MAX Duty = 5031%(X100), DQS PI = 12
2302 14:48:29.585741 [0] MIN Duty = 4906%(X100), DQS PI = 54
2303 14:48:29.585835 [0] AVG Duty = 4968%(X100)
2304 14:48:29.589227
2305 14:48:29.592337 CH0 CLK Duty spec in!! Max-Min= 125%
2306 14:48:29.595791 [DutyScan_Calibration_Flow] ====Done====
2307 14:48:29.595922
2308 14:48:29.599165 [DutyScan_Calibration_Flow] k_type=1
2309 14:48:29.614232
2310 14:48:29.614365 ==DQS 0 ==
2311 14:48:29.617923 Final DQS duty delay cell = 0
2312 14:48:29.621113 [0] MAX Duty = 5062%(X100), DQS PI = 12
2313 14:48:29.624531 [0] MIN Duty = 4907%(X100), DQS PI = 2
2314 14:48:29.624675 [0] AVG Duty = 4984%(X100)
2315 14:48:29.627928
2316 14:48:29.628052 ==DQS 1 ==
2317 14:48:29.631144 Final DQS duty delay cell = -4
2318 14:48:29.634539 [-4] MAX Duty = 4969%(X100), DQS PI = 34
2319 14:48:29.637715 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 14:48:29.641036 [-4] AVG Duty = 4922%(X100)
2321 14:48:29.641145
2322 14:48:29.644259 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2323 14:48:29.644362
2324 14:48:29.647776 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2325 14:48:29.650956 [DutyScan_Calibration_Flow] ====Done====
2326 14:48:29.651029
2327 14:48:29.654676 [DutyScan_Calibration_Flow] k_type=3
2328 14:48:29.672005
2329 14:48:29.672087 ==DQM 0 ==
2330 14:48:29.675022 Final DQM duty delay cell = 0
2331 14:48:29.678511 [0] MAX Duty = 5124%(X100), DQS PI = 12
2332 14:48:29.681750 [0] MIN Duty = 4876%(X100), DQS PI = 0
2333 14:48:29.681829 [0] AVG Duty = 5000%(X100)
2334 14:48:29.685171
2335 14:48:29.685291 ==DQM 1 ==
2336 14:48:29.688474 Final DQM duty delay cell = 4
2337 14:48:29.692062 [4] MAX Duty = 5124%(X100), DQS PI = 50
2338 14:48:29.694942 [4] MIN Duty = 5000%(X100), DQS PI = 14
2339 14:48:29.695062 [4] AVG Duty = 5062%(X100)
2340 14:48:29.698751
2341 14:48:29.701766 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2342 14:48:29.701886
2343 14:48:29.705255 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2344 14:48:29.708459 [DutyScan_Calibration_Flow] ====Done====
2345 14:48:29.708615
2346 14:48:29.711663 [DutyScan_Calibration_Flow] k_type=2
2347 14:48:29.726711
2348 14:48:29.726838 ==DQ 0 ==
2349 14:48:29.729929 Final DQ duty delay cell = -4
2350 14:48:29.733233 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2351 14:48:29.736748 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2352 14:48:29.740044 [-4] AVG Duty = 4969%(X100)
2353 14:48:29.740164
2354 14:48:29.740280 ==DQ 1 ==
2355 14:48:29.743405 Final DQ duty delay cell = -4
2356 14:48:29.746431 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2357 14:48:29.749770 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2358 14:48:29.753103 [-4] AVG Duty = 4938%(X100)
2359 14:48:29.753207
2360 14:48:29.756812 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2361 14:48:29.756916
2362 14:48:29.760025 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2363 14:48:29.763507 [DutyScan_Calibration_Flow] ====Done====
2364 14:48:29.763629 ==
2365 14:48:29.766628 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 14:48:29.770178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 14:48:29.770257 ==
2368 14:48:29.773512 [Duty_Offset_Calibration]
2369 14:48:29.773591 B0:1 B1:-2 CA:0
2370 14:48:29.773652
2371 14:48:29.776513 [DutyScan_Calibration_Flow] k_type=0
2372 14:48:29.787292
2373 14:48:29.787410 ==CLK 0==
2374 14:48:29.790637 Final CLK duty delay cell = 0
2375 14:48:29.793913 [0] MAX Duty = 5031%(X100), DQS PI = 16
2376 14:48:29.797402 [0] MIN Duty = 4876%(X100), DQS PI = 58
2377 14:48:29.797521 [0] AVG Duty = 4953%(X100)
2378 14:48:29.800745
2379 14:48:29.800863 CH1 CLK Duty spec in!! Max-Min= 155%
2380 14:48:29.807559 [DutyScan_Calibration_Flow] ====Done====
2381 14:48:29.807740
2382 14:48:29.810456 [DutyScan_Calibration_Flow] k_type=1
2383 14:48:29.825712
2384 14:48:29.825804 ==DQS 0 ==
2385 14:48:29.829186 Final DQS duty delay cell = -4
2386 14:48:29.832831 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2387 14:48:29.835661 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2388 14:48:29.839429 [-4] AVG Duty = 4953%(X100)
2389 14:48:29.839549
2390 14:48:29.839670 ==DQS 1 ==
2391 14:48:29.842715 Final DQS duty delay cell = 0
2392 14:48:29.846150 [0] MAX Duty = 5093%(X100), DQS PI = 0
2393 14:48:29.849210 [0] MIN Duty = 4875%(X100), DQS PI = 26
2394 14:48:29.852329 [0] AVG Duty = 4984%(X100)
2395 14:48:29.852406
2396 14:48:29.855601 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2397 14:48:29.855706
2398 14:48:29.858904 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2399 14:48:29.862271 [DutyScan_Calibration_Flow] ====Done====
2400 14:48:29.862351
2401 14:48:29.865996 [DutyScan_Calibration_Flow] k_type=3
2402 14:48:29.882236
2403 14:48:29.882328 ==DQM 0 ==
2404 14:48:29.885513 Final DQM duty delay cell = 0
2405 14:48:29.888767 [0] MAX Duty = 5000%(X100), DQS PI = 24
2406 14:48:29.892367 [0] MIN Duty = 4876%(X100), DQS PI = 0
2407 14:48:29.892465 [0] AVG Duty = 4938%(X100)
2408 14:48:29.895747
2409 14:48:29.895823 ==DQM 1 ==
2410 14:48:29.898931 Final DQM duty delay cell = 0
2411 14:48:29.902293 [0] MAX Duty = 5031%(X100), DQS PI = 34
2412 14:48:29.905432 [0] MIN Duty = 4907%(X100), DQS PI = 4
2413 14:48:29.905502 [0] AVG Duty = 4969%(X100)
2414 14:48:29.908917
2415 14:48:29.912224 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2416 14:48:29.912329
2417 14:48:29.915571 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2418 14:48:29.919082 [DutyScan_Calibration_Flow] ====Done====
2419 14:48:29.919161
2420 14:48:29.922095 [DutyScan_Calibration_Flow] k_type=2
2421 14:48:29.938704
2422 14:48:29.938865 ==DQ 0 ==
2423 14:48:29.942063 Final DQ duty delay cell = 0
2424 14:48:29.945681 [0] MAX Duty = 5062%(X100), DQS PI = 12
2425 14:48:29.948476 [0] MIN Duty = 4938%(X100), DQS PI = 56
2426 14:48:29.948579 [0] AVG Duty = 5000%(X100)
2427 14:48:29.952366
2428 14:48:29.952445 ==DQ 1 ==
2429 14:48:29.955457 Final DQ duty delay cell = 0
2430 14:48:29.958772 [0] MAX Duty = 5125%(X100), DQS PI = 36
2431 14:48:29.961973 [0] MIN Duty = 4938%(X100), DQS PI = 26
2432 14:48:29.962111 [0] AVG Duty = 5031%(X100)
2433 14:48:29.962263
2434 14:48:29.965494 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2435 14:48:29.968817
2436 14:48:29.972061 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2437 14:48:29.975407 [DutyScan_Calibration_Flow] ====Done====
2438 14:48:29.978892 nWR fixed to 30
2439 14:48:29.979013 [ModeRegInit_LP4] CH0 RK0
2440 14:48:29.982271 [ModeRegInit_LP4] CH0 RK1
2441 14:48:29.985408 [ModeRegInit_LP4] CH1 RK0
2442 14:48:29.985534 [ModeRegInit_LP4] CH1 RK1
2443 14:48:29.988578 match AC timing 7
2444 14:48:29.992109 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 14:48:29.995352 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 14:48:30.002086 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 14:48:30.005272 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 14:48:30.011795 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 14:48:30.011877 ==
2450 14:48:30.015246 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 14:48:30.018677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 14:48:30.018758 ==
2453 14:48:30.025538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 14:48:30.031857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2455 14:48:30.038704 [CA 0] Center 40 (10~71) winsize 62
2456 14:48:30.042268 [CA 1] Center 39 (9~70) winsize 62
2457 14:48:30.045337 [CA 2] Center 36 (6~66) winsize 61
2458 14:48:30.048666 [CA 3] Center 35 (5~66) winsize 62
2459 14:48:30.052499 [CA 4] Center 34 (4~65) winsize 62
2460 14:48:30.055575 [CA 5] Center 33 (3~63) winsize 61
2461 14:48:30.055655
2462 14:48:30.059181 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2463 14:48:30.059261
2464 14:48:30.062038 [CATrainingPosCal] consider 1 rank data
2465 14:48:30.065734 u2DelayCellTimex100 = 270/100 ps
2466 14:48:30.069067 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2467 14:48:30.075766 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2468 14:48:30.079018 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2469 14:48:30.082431 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 14:48:30.085765 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2471 14:48:30.089156 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2472 14:48:30.089282
2473 14:48:30.092443 CA PerBit enable=1, Macro0, CA PI delay=33
2474 14:48:30.092583
2475 14:48:30.095715 [CBTSetCACLKResult] CA Dly = 33
2476 14:48:30.095835 CS Dly: 7 (0~38)
2477 14:48:30.099173 ==
2478 14:48:30.099289 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 14:48:30.105308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 14:48:30.105439 ==
2481 14:48:30.109221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 14:48:30.115344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2483 14:48:30.124754 [CA 0] Center 40 (10~70) winsize 61
2484 14:48:30.128506 [CA 1] Center 39 (9~70) winsize 62
2485 14:48:30.131317 [CA 2] Center 35 (5~66) winsize 62
2486 14:48:30.134805 [CA 3] Center 35 (5~66) winsize 62
2487 14:48:30.138442 [CA 4] Center 34 (4~65) winsize 62
2488 14:48:30.141358 [CA 5] Center 33 (3~63) winsize 61
2489 14:48:30.141460
2490 14:48:30.144735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2491 14:48:30.144815
2492 14:48:30.148173 [CATrainingPosCal] consider 2 rank data
2493 14:48:30.151631 u2DelayCellTimex100 = 270/100 ps
2494 14:48:30.154812 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2495 14:48:30.161596 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 14:48:30.164839 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2497 14:48:30.168332 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 14:48:30.171345 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 14:48:30.174782 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 14:48:30.174862
2501 14:48:30.178022 CA PerBit enable=1, Macro0, CA PI delay=33
2502 14:48:30.178103
2503 14:48:30.181380 [CBTSetCACLKResult] CA Dly = 33
2504 14:48:30.181460 CS Dly: 8 (0~40)
2505 14:48:30.184698
2506 14:48:30.188008 ----->DramcWriteLeveling(PI) begin...
2507 14:48:30.188089 ==
2508 14:48:30.191268 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 14:48:30.194825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 14:48:30.194905 ==
2511 14:48:30.198334 Write leveling (Byte 0): 33 => 33
2512 14:48:30.201420 Write leveling (Byte 1): 29 => 29
2513 14:48:30.204976 DramcWriteLeveling(PI) end<-----
2514 14:48:30.205056
2515 14:48:30.205118 ==
2516 14:48:30.208285 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 14:48:30.211486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 14:48:30.211566 ==
2519 14:48:30.214812 [Gating] SW mode calibration
2520 14:48:30.221316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 14:48:30.227963 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 14:48:30.231794 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2523 14:48:30.234836 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2524 14:48:30.241473 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 14:48:30.244832 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 14:48:30.248344 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 14:48:30.251356 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 14:48:30.258411 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 14:48:30.261280 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2530 14:48:30.265147 1 0 0 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2531 14:48:30.271591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2532 14:48:30.274669 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 14:48:30.278339 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 14:48:30.284663 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 14:48:30.288159 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 14:48:30.291346 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 14:48:30.298137 1 0 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2538 14:48:30.301514 1 1 0 | B1->B0 | 2525 302f | 1 1 | (0 0) (0 0)
2539 14:48:30.304683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 14:48:30.311189 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 14:48:30.314639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 14:48:30.317492 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 14:48:30.324234 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 14:48:30.327718 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 14:48:30.330909 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 14:48:30.337435 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 14:48:30.340786 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 14:48:30.344231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 14:48:30.350730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 14:48:30.353873 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 14:48:30.357520 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 14:48:30.363918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 14:48:30.367358 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 14:48:30.370726 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 14:48:30.377245 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 14:48:30.380410 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 14:48:30.383804 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 14:48:30.390831 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 14:48:30.393731 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 14:48:30.397315 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 14:48:30.403840 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 14:48:30.407004 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 14:48:30.410738 Total UI for P1: 0, mck2ui 16
2564 14:48:30.414063 best dqsien dly found for B0: ( 1, 3, 28)
2565 14:48:30.417377 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 14:48:30.420294 Total UI for P1: 0, mck2ui 16
2567 14:48:30.423891 best dqsien dly found for B1: ( 1, 4, 0)
2568 14:48:30.427049 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2569 14:48:30.430460 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2570 14:48:30.430578
2571 14:48:30.433750 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2572 14:48:30.440215 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 14:48:30.440333 [Gating] SW calibration Done
2574 14:48:30.440425 ==
2575 14:48:30.443418 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 14:48:30.450348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 14:48:30.450467 ==
2578 14:48:30.450579 RX Vref Scan: 0
2579 14:48:30.450686
2580 14:48:30.453583 RX Vref 0 -> 0, step: 1
2581 14:48:30.453699
2582 14:48:30.456867 RX Delay -40 -> 252, step: 8
2583 14:48:30.460266 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2584 14:48:30.463705 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2585 14:48:30.467063 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2586 14:48:30.470151 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2587 14:48:30.477182 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2588 14:48:30.480251 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2589 14:48:30.483632 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2590 14:48:30.486962 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2591 14:48:30.490377 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2592 14:48:30.493901 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2593 14:48:30.500388 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2594 14:48:30.504121 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2595 14:48:30.507215 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2596 14:48:30.510491 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2597 14:48:30.516936 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2598 14:48:30.520185 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2599 14:48:30.520291 ==
2600 14:48:30.523638 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 14:48:30.527088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 14:48:30.527161 ==
2603 14:48:30.527226 DQS Delay:
2604 14:48:30.530263 DQS0 = 0, DQS1 = 0
2605 14:48:30.530348 DQM Delay:
2606 14:48:30.533633 DQM0 = 112, DQM1 = 102
2607 14:48:30.533708 DQ Delay:
2608 14:48:30.536707 DQ0 =115, DQ1 =111, DQ2 =111, DQ3 =107
2609 14:48:30.540186 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2610 14:48:30.543620 DQ8 =95, DQ9 =83, DQ10 =103, DQ11 =95
2611 14:48:30.546732 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2612 14:48:30.546858
2613 14:48:30.550254
2614 14:48:30.550363 ==
2615 14:48:30.553746 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 14:48:30.556945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 14:48:30.557029 ==
2618 14:48:30.557101
2619 14:48:30.557166
2620 14:48:30.560341 TX Vref Scan disable
2621 14:48:30.560447 == TX Byte 0 ==
2622 14:48:30.563431 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2623 14:48:30.570561 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2624 14:48:30.570641 == TX Byte 1 ==
2625 14:48:30.573669 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2626 14:48:30.580272 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2627 14:48:30.580401 ==
2628 14:48:30.583410 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 14:48:30.586785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 14:48:30.586895 ==
2631 14:48:30.599432 TX Vref=22, minBit 7, minWin=25, winSum=414
2632 14:48:30.602393 TX Vref=24, minBit 7, minWin=25, winSum=421
2633 14:48:30.605836 TX Vref=26, minBit 4, minWin=26, winSum=430
2634 14:48:30.609272 TX Vref=28, minBit 10, minWin=26, winSum=433
2635 14:48:30.612442 TX Vref=30, minBit 3, minWin=26, winSum=434
2636 14:48:30.619289 TX Vref=32, minBit 1, minWin=26, winSum=429
2637 14:48:30.622378 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 30
2638 14:48:30.622474
2639 14:48:30.625995 Final TX Range 1 Vref 30
2640 14:48:30.626075
2641 14:48:30.626143 ==
2642 14:48:30.629039 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 14:48:30.632314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 14:48:30.632394 ==
2645 14:48:30.635701
2646 14:48:30.635832
2647 14:48:30.635950 TX Vref Scan disable
2648 14:48:30.639460 == TX Byte 0 ==
2649 14:48:30.642681 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2650 14:48:30.645789 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2651 14:48:30.649080 == TX Byte 1 ==
2652 14:48:30.652321 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2653 14:48:30.655976 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2654 14:48:30.659261
2655 14:48:30.659385 [DATLAT]
2656 14:48:30.659493 Freq=1200, CH0 RK0
2657 14:48:30.659612
2658 14:48:30.662576 DATLAT Default: 0xd
2659 14:48:30.662698 0, 0xFFFF, sum = 0
2660 14:48:30.666009 1, 0xFFFF, sum = 0
2661 14:48:30.666140 2, 0xFFFF, sum = 0
2662 14:48:30.669116 3, 0xFFFF, sum = 0
2663 14:48:30.669242 4, 0xFFFF, sum = 0
2664 14:48:30.672391 5, 0xFFFF, sum = 0
2665 14:48:30.672514 6, 0xFFFF, sum = 0
2666 14:48:30.675746 7, 0xFFFF, sum = 0
2667 14:48:30.679438 8, 0xFFFF, sum = 0
2668 14:48:30.679562 9, 0xFFFF, sum = 0
2669 14:48:30.682570 10, 0xFFFF, sum = 0
2670 14:48:30.682676 11, 0xFFFF, sum = 0
2671 14:48:30.685793 12, 0x0, sum = 1
2672 14:48:30.685916 13, 0x0, sum = 2
2673 14:48:30.689184 14, 0x0, sum = 3
2674 14:48:30.689268 15, 0x0, sum = 4
2675 14:48:30.689333 best_step = 13
2676 14:48:30.689393
2677 14:48:30.692565 ==
2678 14:48:30.695915 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 14:48:30.699313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 14:48:30.699399 ==
2681 14:48:30.699463 RX Vref Scan: 1
2682 14:48:30.699523
2683 14:48:30.702692 Set Vref Range= 32 -> 127
2684 14:48:30.702774
2685 14:48:30.705817 RX Vref 32 -> 127, step: 1
2686 14:48:30.705925
2687 14:48:30.709102 RX Delay -37 -> 252, step: 4
2688 14:48:30.709185
2689 14:48:30.712386 Set Vref, RX VrefLevel [Byte0]: 32
2690 14:48:30.715660 [Byte1]: 32
2691 14:48:30.715742
2692 14:48:30.719004 Set Vref, RX VrefLevel [Byte0]: 33
2693 14:48:30.722183 [Byte1]: 33
2694 14:48:30.726146
2695 14:48:30.726228 Set Vref, RX VrefLevel [Byte0]: 34
2696 14:48:30.729369 [Byte1]: 34
2697 14:48:30.734114
2698 14:48:30.734196 Set Vref, RX VrefLevel [Byte0]: 35
2699 14:48:30.737026 [Byte1]: 35
2700 14:48:30.742198
2701 14:48:30.742283 Set Vref, RX VrefLevel [Byte0]: 36
2702 14:48:30.745351 [Byte1]: 36
2703 14:48:30.749790
2704 14:48:30.749872 Set Vref, RX VrefLevel [Byte0]: 37
2705 14:48:30.752897 [Byte1]: 37
2706 14:48:30.757565
2707 14:48:30.757648 Set Vref, RX VrefLevel [Byte0]: 38
2708 14:48:30.761165 [Byte1]: 38
2709 14:48:30.765912
2710 14:48:30.765997 Set Vref, RX VrefLevel [Byte0]: 39
2711 14:48:30.769145 [Byte1]: 39
2712 14:48:30.773791
2713 14:48:30.773901 Set Vref, RX VrefLevel [Byte0]: 40
2714 14:48:30.780252 [Byte1]: 40
2715 14:48:30.780329
2716 14:48:30.783523 Set Vref, RX VrefLevel [Byte0]: 41
2717 14:48:30.787008 [Byte1]: 41
2718 14:48:30.787080
2719 14:48:30.789862 Set Vref, RX VrefLevel [Byte0]: 42
2720 14:48:30.793578 [Byte1]: 42
2721 14:48:30.797736
2722 14:48:30.797812 Set Vref, RX VrefLevel [Byte0]: 43
2723 14:48:30.801115 [Byte1]: 43
2724 14:48:30.805514
2725 14:48:30.805639 Set Vref, RX VrefLevel [Byte0]: 44
2726 14:48:30.808877 [Byte1]: 44
2727 14:48:30.813716
2728 14:48:30.813842 Set Vref, RX VrefLevel [Byte0]: 45
2729 14:48:30.817141 [Byte1]: 45
2730 14:48:30.821653
2731 14:48:30.821777 Set Vref, RX VrefLevel [Byte0]: 46
2732 14:48:30.825004 [Byte1]: 46
2733 14:48:30.829884
2734 14:48:30.829966 Set Vref, RX VrefLevel [Byte0]: 47
2735 14:48:30.833219 [Byte1]: 47
2736 14:48:30.837612
2737 14:48:30.837693 Set Vref, RX VrefLevel [Byte0]: 48
2738 14:48:30.841514 [Byte1]: 48
2739 14:48:30.846011
2740 14:48:30.846094 Set Vref, RX VrefLevel [Byte0]: 49
2741 14:48:30.849173 [Byte1]: 49
2742 14:48:30.853966
2743 14:48:30.854047 Set Vref, RX VrefLevel [Byte0]: 50
2744 14:48:30.857325 [Byte1]: 50
2745 14:48:30.861784
2746 14:48:30.861865 Set Vref, RX VrefLevel [Byte0]: 51
2747 14:48:30.865151 [Byte1]: 51
2748 14:48:30.869740
2749 14:48:30.869823 Set Vref, RX VrefLevel [Byte0]: 52
2750 14:48:30.872913 [Byte1]: 52
2751 14:48:30.877940
2752 14:48:30.878023 Set Vref, RX VrefLevel [Byte0]: 53
2753 14:48:30.881037 [Byte1]: 53
2754 14:48:30.885745
2755 14:48:30.885828 Set Vref, RX VrefLevel [Byte0]: 54
2756 14:48:30.888912 [Byte1]: 54
2757 14:48:30.893990
2758 14:48:30.894072 Set Vref, RX VrefLevel [Byte0]: 55
2759 14:48:30.896811 [Byte1]: 55
2760 14:48:30.902157
2761 14:48:30.902286 Set Vref, RX VrefLevel [Byte0]: 56
2762 14:48:30.904955 [Byte1]: 56
2763 14:48:30.909590
2764 14:48:30.909677 Set Vref, RX VrefLevel [Byte0]: 57
2765 14:48:30.913189 [Byte1]: 57
2766 14:48:30.917791
2767 14:48:30.917873 Set Vref, RX VrefLevel [Byte0]: 58
2768 14:48:30.921184 [Byte1]: 58
2769 14:48:30.926118
2770 14:48:30.926211 Set Vref, RX VrefLevel [Byte0]: 59
2771 14:48:30.929016 [Byte1]: 59
2772 14:48:30.933483
2773 14:48:30.933565 Set Vref, RX VrefLevel [Byte0]: 60
2774 14:48:30.936957 [Byte1]: 60
2775 14:48:30.941958
2776 14:48:30.942040 Set Vref, RX VrefLevel [Byte0]: 61
2777 14:48:30.945193 [Byte1]: 61
2778 14:48:30.949855
2779 14:48:30.949937 Set Vref, RX VrefLevel [Byte0]: 62
2780 14:48:30.952857 [Byte1]: 62
2781 14:48:30.957957
2782 14:48:30.958039 Set Vref, RX VrefLevel [Byte0]: 63
2783 14:48:30.961185 [Byte1]: 63
2784 14:48:30.965577
2785 14:48:30.965660 Set Vref, RX VrefLevel [Byte0]: 64
2786 14:48:30.969227 [Byte1]: 64
2787 14:48:30.973720
2788 14:48:30.973803 Set Vref, RX VrefLevel [Byte0]: 65
2789 14:48:30.976940 [Byte1]: 65
2790 14:48:30.981914
2791 14:48:30.982023 Set Vref, RX VrefLevel [Byte0]: 66
2792 14:48:30.985173 [Byte1]: 66
2793 14:48:30.989642
2794 14:48:30.989722 Set Vref, RX VrefLevel [Byte0]: 67
2795 14:48:30.993131 [Byte1]: 67
2796 14:48:30.997512
2797 14:48:30.997594 Set Vref, RX VrefLevel [Byte0]: 68
2798 14:48:31.001510 [Byte1]: 68
2799 14:48:31.005773
2800 14:48:31.005856 Set Vref, RX VrefLevel [Byte0]: 69
2801 14:48:31.008971 [Byte1]: 69
2802 14:48:31.013708
2803 14:48:31.013790 Set Vref, RX VrefLevel [Byte0]: 70
2804 14:48:31.017002 [Byte1]: 70
2805 14:48:31.021754
2806 14:48:31.021837 Set Vref, RX VrefLevel [Byte0]: 71
2807 14:48:31.025180 [Byte1]: 71
2808 14:48:31.029638
2809 14:48:31.029720 Set Vref, RX VrefLevel [Byte0]: 72
2810 14:48:31.032870 [Byte1]: 72
2811 14:48:31.037908
2812 14:48:31.037990 Set Vref, RX VrefLevel [Byte0]: 73
2813 14:48:31.041359 [Byte1]: 73
2814 14:48:31.045779
2815 14:48:31.045861 Set Vref, RX VrefLevel [Byte0]: 74
2816 14:48:31.048854 [Byte1]: 74
2817 14:48:31.053961
2818 14:48:31.054045 Final RX Vref Byte 0 = 62 to rank0
2819 14:48:31.057246 Final RX Vref Byte 1 = 58 to rank0
2820 14:48:31.060671 Final RX Vref Byte 0 = 62 to rank1
2821 14:48:31.063938 Final RX Vref Byte 1 = 58 to rank1==
2822 14:48:31.067299 Dram Type= 6, Freq= 0, CH_0, rank 0
2823 14:48:31.070601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 14:48:31.073816 ==
2825 14:48:31.073899 DQS Delay:
2826 14:48:31.073985 DQS0 = 0, DQS1 = 0
2827 14:48:31.076872 DQM Delay:
2828 14:48:31.076954 DQM0 = 112, DQM1 = 102
2829 14:48:31.080357 DQ Delay:
2830 14:48:31.083797 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =108
2831 14:48:31.087108 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2832 14:48:31.090185 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2833 14:48:31.093979 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =108
2834 14:48:31.094060
2835 14:48:31.094123
2836 14:48:31.100374 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2837 14:48:31.103641 CH0 RK0: MR19=303, MR18=FEFD
2838 14:48:31.110299 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2839 14:48:31.110384
2840 14:48:31.113353 ----->DramcWriteLeveling(PI) begin...
2841 14:48:31.113436 ==
2842 14:48:31.117376 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 14:48:31.120066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 14:48:31.123388 ==
2845 14:48:31.123470 Write leveling (Byte 0): 33 => 33
2846 14:48:31.126662 Write leveling (Byte 1): 29 => 29
2847 14:48:31.129907 DramcWriteLeveling(PI) end<-----
2848 14:48:31.129994
2849 14:48:31.130058 ==
2850 14:48:31.133402 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 14:48:31.140428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 14:48:31.140509 ==
2853 14:48:31.140586 [Gating] SW mode calibration
2854 14:48:31.150454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2855 14:48:31.153759 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2856 14:48:31.157149 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2857 14:48:31.163769 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 14:48:31.167339 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 14:48:31.170533 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 14:48:31.176508 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 14:48:31.180234 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 14:48:31.183965 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2863 14:48:31.190386 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2864 14:48:31.193540 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2865 14:48:31.196462 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 14:48:31.203166 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 14:48:31.206958 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 14:48:31.210369 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 14:48:31.216812 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 14:48:31.220224 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2871 14:48:31.223577 1 0 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
2872 14:48:31.229785 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2873 14:48:31.233034 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 14:48:31.236762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 14:48:31.243473 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 14:48:31.246618 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 14:48:31.249734 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 14:48:31.256660 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 14:48:31.260052 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2880 14:48:31.263361 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 14:48:31.266685 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 14:48:31.273405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 14:48:31.276620 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 14:48:31.279912 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 14:48:31.286789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 14:48:31.289770 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 14:48:31.293147 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 14:48:31.300008 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 14:48:31.303192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 14:48:31.306625 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 14:48:31.313450 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 14:48:31.316794 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 14:48:31.319773 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 14:48:31.326443 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 14:48:31.329908 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 14:48:31.333384 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2897 14:48:31.336596 Total UI for P1: 0, mck2ui 16
2898 14:48:31.339909 best dqsien dly found for B0: ( 1, 3, 28)
2899 14:48:31.346658 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 14:48:31.346771 Total UI for P1: 0, mck2ui 16
2901 14:48:31.350296 best dqsien dly found for B1: ( 1, 4, 0)
2902 14:48:31.356831 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2903 14:48:31.359805 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2904 14:48:31.359914
2905 14:48:31.363542 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 14:48:31.367017 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2907 14:48:31.369861 [Gating] SW calibration Done
2908 14:48:31.369968 ==
2909 14:48:31.373555 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 14:48:31.376977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 14:48:31.377086 ==
2912 14:48:31.377180 RX Vref Scan: 0
2913 14:48:31.377280
2914 14:48:31.380477 RX Vref 0 -> 0, step: 1
2915 14:48:31.380590
2916 14:48:31.383249 RX Delay -40 -> 252, step: 8
2917 14:48:31.386977 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2918 14:48:31.389970 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2919 14:48:31.396508 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2920 14:48:31.400131 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2921 14:48:31.403666 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2922 14:48:31.406735 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2923 14:48:31.410009 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2924 14:48:31.416500 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2925 14:48:31.420451 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2926 14:48:31.423214 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2927 14:48:31.426629 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2928 14:48:31.429879 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2929 14:48:31.433524 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2930 14:48:31.439950 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2931 14:48:31.443475 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2932 14:48:31.446795 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2933 14:48:31.446909 ==
2934 14:48:31.450198 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 14:48:31.453143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 14:48:31.456804 ==
2937 14:48:31.456888 DQS Delay:
2938 14:48:31.456980 DQS0 = 0, DQS1 = 0
2939 14:48:31.460006 DQM Delay:
2940 14:48:31.460120 DQM0 = 112, DQM1 = 102
2941 14:48:31.463265 DQ Delay:
2942 14:48:31.467113 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2943 14:48:31.470231 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2944 14:48:31.473453 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2945 14:48:31.476640 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2946 14:48:31.476741
2947 14:48:31.476848
2948 14:48:31.476947 ==
2949 14:48:31.479897 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 14:48:31.483406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 14:48:31.483508 ==
2952 14:48:31.483598
2953 14:48:31.483685
2954 14:48:31.486546 TX Vref Scan disable
2955 14:48:31.489988 == TX Byte 0 ==
2956 14:48:31.493578 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2957 14:48:31.496965 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2958 14:48:31.500137 == TX Byte 1 ==
2959 14:48:31.503554 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2960 14:48:31.506676 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2961 14:48:31.506783 ==
2962 14:48:31.510671 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 14:48:31.513365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 14:48:31.516770 ==
2965 14:48:31.526901 TX Vref=22, minBit 0, minWin=26, winSum=428
2966 14:48:31.530237 TX Vref=24, minBit 2, minWin=26, winSum=429
2967 14:48:31.533437 TX Vref=26, minBit 0, minWin=26, winSum=433
2968 14:48:31.537292 TX Vref=28, minBit 1, minWin=26, winSum=438
2969 14:48:31.540298 TX Vref=30, minBit 1, minWin=27, winSum=443
2970 14:48:31.543422 TX Vref=32, minBit 1, minWin=26, winSum=439
2971 14:48:31.550528 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
2972 14:48:31.550606
2973 14:48:31.553556 Final TX Range 1 Vref 30
2974 14:48:31.553657
2975 14:48:31.553746 ==
2976 14:48:31.557002 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 14:48:31.560256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 14:48:31.560368 ==
2979 14:48:31.560460
2980 14:48:31.563582
2981 14:48:31.563683 TX Vref Scan disable
2982 14:48:31.567261 == TX Byte 0 ==
2983 14:48:31.570546 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2984 14:48:31.573881 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2985 14:48:31.576763 == TX Byte 1 ==
2986 14:48:31.580290 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2987 14:48:31.583389 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2988 14:48:31.583488
2989 14:48:31.586961 [DATLAT]
2990 14:48:31.587059 Freq=1200, CH0 RK1
2991 14:48:31.587148
2992 14:48:31.590335 DATLAT Default: 0xd
2993 14:48:31.590430 0, 0xFFFF, sum = 0
2994 14:48:31.593629 1, 0xFFFF, sum = 0
2995 14:48:31.593705 2, 0xFFFF, sum = 0
2996 14:48:31.596682 3, 0xFFFF, sum = 0
2997 14:48:31.596783 4, 0xFFFF, sum = 0
2998 14:48:31.600466 5, 0xFFFF, sum = 0
2999 14:48:31.603308 6, 0xFFFF, sum = 0
3000 14:48:31.603409 7, 0xFFFF, sum = 0
3001 14:48:31.606962 8, 0xFFFF, sum = 0
3002 14:48:31.607064 9, 0xFFFF, sum = 0
3003 14:48:31.610355 10, 0xFFFF, sum = 0
3004 14:48:31.610455 11, 0xFFFF, sum = 0
3005 14:48:31.613546 12, 0x0, sum = 1
3006 14:48:31.613653 13, 0x0, sum = 2
3007 14:48:31.616530 14, 0x0, sum = 3
3008 14:48:31.616620 15, 0x0, sum = 4
3009 14:48:31.616681 best_step = 13
3010 14:48:31.619862
3011 14:48:31.619957 ==
3012 14:48:31.623372 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 14:48:31.626751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 14:48:31.626823 ==
3015 14:48:31.626918 RX Vref Scan: 0
3016 14:48:31.627004
3017 14:48:31.630007 RX Vref 0 -> 0, step: 1
3018 14:48:31.630109
3019 14:48:31.633510 RX Delay -29 -> 252, step: 4
3020 14:48:31.636530 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3021 14:48:31.643279 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3022 14:48:31.646984 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3023 14:48:31.650046 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3024 14:48:31.653216 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3025 14:48:31.656479 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3026 14:48:31.663183 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3027 14:48:31.666859 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3028 14:48:31.670223 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3029 14:48:31.673459 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3030 14:48:31.677188 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3031 14:48:31.679964 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3032 14:48:31.687108 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3033 14:48:31.690087 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3034 14:48:31.693504 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3035 14:48:31.696492 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3036 14:48:31.696597 ==
3037 14:48:31.699952 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 14:48:31.706792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 14:48:31.706869 ==
3040 14:48:31.706932 DQS Delay:
3041 14:48:31.710114 DQS0 = 0, DQS1 = 0
3042 14:48:31.710189 DQM Delay:
3043 14:48:31.710250 DQM0 = 110, DQM1 = 101
3044 14:48:31.713430 DQ Delay:
3045 14:48:31.716717 DQ0 =108, DQ1 =112, DQ2 =106, DQ3 =108
3046 14:48:31.719888 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3047 14:48:31.723664 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3048 14:48:31.726861 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3049 14:48:31.726942
3050 14:48:31.727037
3051 14:48:31.736239 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3052 14:48:31.736343 CH0 RK1: MR19=403, MR18=14FD
3053 14:48:31.743259 CH0_RK1: MR19=0x403, MR18=0x14FD, DQSOSC=402, MR23=63, INC=40, DEC=27
3054 14:48:31.746320 [RxdqsGatingPostProcess] freq 1200
3055 14:48:31.753238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 14:48:31.756438 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 14:48:31.759682 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 14:48:31.762948 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 14:48:31.766311 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 14:48:31.769689 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 14:48:31.769792 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 14:48:31.773003 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 14:48:31.776178 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 14:48:31.779711 Pre-setting of DQS Precalculation
3065 14:48:31.786274 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 14:48:31.786359 ==
3067 14:48:31.789392 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 14:48:31.793041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 14:48:31.793124 ==
3070 14:48:31.799365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 14:48:31.806264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3072 14:48:31.812948 [CA 0] Center 37 (7~67) winsize 61
3073 14:48:31.816261 [CA 1] Center 37 (7~68) winsize 62
3074 14:48:31.819600 [CA 2] Center 34 (4~64) winsize 61
3075 14:48:31.822977 [CA 3] Center 33 (3~64) winsize 62
3076 14:48:31.826436 [CA 4] Center 34 (4~64) winsize 61
3077 14:48:31.829753 [CA 5] Center 33 (3~63) winsize 61
3078 14:48:31.829840
3079 14:48:31.833082 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3080 14:48:31.833161
3081 14:48:31.836307 [CATrainingPosCal] consider 1 rank data
3082 14:48:31.839613 u2DelayCellTimex100 = 270/100 ps
3083 14:48:31.842960 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3084 14:48:31.846361 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 14:48:31.852773 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 14:48:31.856227 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3087 14:48:31.859523 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 14:48:31.863003 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3089 14:48:31.863103
3090 14:48:31.866273 CA PerBit enable=1, Macro0, CA PI delay=33
3091 14:48:31.866378
3092 14:48:31.869631 [CBTSetCACLKResult] CA Dly = 33
3093 14:48:31.869705 CS Dly: 6 (0~37)
3094 14:48:31.873071 ==
3095 14:48:31.873153 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 14:48:31.879854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 14:48:31.879936 ==
3098 14:48:31.883232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 14:48:31.889683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3100 14:48:31.898635 [CA 0] Center 37 (7~67) winsize 61
3101 14:48:31.902086 [CA 1] Center 37 (7~68) winsize 62
3102 14:48:31.905461 [CA 2] Center 34 (4~65) winsize 62
3103 14:48:31.908716 [CA 3] Center 33 (3~64) winsize 62
3104 14:48:31.911957 [CA 4] Center 34 (4~65) winsize 62
3105 14:48:31.915441 [CA 5] Center 32 (2~63) winsize 62
3106 14:48:31.915553
3107 14:48:31.918679 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3108 14:48:31.918778
3109 14:48:31.922036 [CATrainingPosCal] consider 2 rank data
3110 14:48:31.925504 u2DelayCellTimex100 = 270/100 ps
3111 14:48:31.928571 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3112 14:48:31.932107 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 14:48:31.938947 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 14:48:31.942093 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3115 14:48:31.945710 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 14:48:31.949060 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3117 14:48:31.949142
3118 14:48:31.951873 CA PerBit enable=1, Macro0, CA PI delay=33
3119 14:48:31.951955
3120 14:48:31.955122 [CBTSetCACLKResult] CA Dly = 33
3121 14:48:31.955203 CS Dly: 7 (0~39)
3122 14:48:31.955267
3123 14:48:31.958904 ----->DramcWriteLeveling(PI) begin...
3124 14:48:31.958986 ==
3125 14:48:31.962198 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 14:48:31.968463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 14:48:31.968580 ==
3128 14:48:31.971757 Write leveling (Byte 0): 26 => 26
3129 14:48:31.975157 Write leveling (Byte 1): 27 => 27
3130 14:48:31.978472 DramcWriteLeveling(PI) end<-----
3131 14:48:31.978578
3132 14:48:31.978681 ==
3133 14:48:31.982338 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 14:48:31.985516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 14:48:31.985596 ==
3136 14:48:31.988978 [Gating] SW mode calibration
3137 14:48:31.995385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 14:48:31.998650 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 14:48:32.005553 0 15 0 | B1->B0 | 2d2d 2625 | 1 1 | (0 0) (0 0)
3140 14:48:32.008538 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 14:48:32.011999 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 14:48:32.018568 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 14:48:32.021991 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 14:48:32.024946 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 14:48:32.031839 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 14:48:32.035079 0 15 28 | B1->B0 | 3030 3131 | 0 0 | (0 1) (0 1)
3147 14:48:32.038589 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3148 14:48:32.045051 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 14:48:32.048893 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 14:48:32.051649 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 14:48:32.058590 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 14:48:32.061874 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 14:48:32.065198 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3154 14:48:32.072310 1 0 28 | B1->B0 | 4040 4040 | 0 0 | (0 0) (0 0)
3155 14:48:32.074987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 14:48:32.078339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 14:48:32.081662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 14:48:32.088317 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 14:48:32.091659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 14:48:32.094992 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 14:48:32.101520 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 14:48:32.105316 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 14:48:32.108131 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 14:48:32.115165 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 14:48:32.118233 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 14:48:32.121652 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 14:48:32.128168 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 14:48:32.131568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 14:48:32.134848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 14:48:32.141592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 14:48:32.145088 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 14:48:32.148481 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 14:48:32.155287 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 14:48:32.158279 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 14:48:32.162046 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 14:48:32.168626 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 14:48:32.171888 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 14:48:32.175024 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 14:48:32.179014 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 14:48:32.182337 Total UI for P1: 0, mck2ui 16
3181 14:48:32.185523 best dqsien dly found for B0: ( 1, 3, 28)
3182 14:48:32.188900 Total UI for P1: 0, mck2ui 16
3183 14:48:32.192285 best dqsien dly found for B1: ( 1, 3, 28)
3184 14:48:32.195502 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3185 14:48:32.198879 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3186 14:48:32.202177
3187 14:48:32.205371 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 14:48:32.208488 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3189 14:48:32.211792 [Gating] SW calibration Done
3190 14:48:32.211871 ==
3191 14:48:32.215311 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 14:48:32.218616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 14:48:32.218691 ==
3194 14:48:32.218753 RX Vref Scan: 0
3195 14:48:32.218811
3196 14:48:32.222138 RX Vref 0 -> 0, step: 1
3197 14:48:32.222206
3198 14:48:32.225351 RX Delay -40 -> 252, step: 8
3199 14:48:32.228880 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3200 14:48:32.231852 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3201 14:48:32.238684 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3202 14:48:32.242225 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3203 14:48:32.245232 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3204 14:48:32.248675 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3205 14:48:32.252157 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3206 14:48:32.258654 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3207 14:48:32.261992 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3208 14:48:32.265259 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3209 14:48:32.268847 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3210 14:48:32.271951 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3211 14:48:32.275219 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3212 14:48:32.281748 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3213 14:48:32.285068 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3214 14:48:32.288466 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3215 14:48:32.288571 ==
3216 14:48:32.291893 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 14:48:32.295160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 14:48:32.298517 ==
3219 14:48:32.298602 DQS Delay:
3220 14:48:32.298666 DQS0 = 0, DQS1 = 0
3221 14:48:32.302139 DQM Delay:
3222 14:48:32.302250 DQM0 = 113, DQM1 = 106
3223 14:48:32.305505 DQ Delay:
3224 14:48:32.308779 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =111
3225 14:48:32.311870 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3226 14:48:32.315209 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3227 14:48:32.318709 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3228 14:48:32.318786
3229 14:48:32.318858
3230 14:48:32.318917 ==
3231 14:48:32.321954 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 14:48:32.325310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 14:48:32.325386 ==
3234 14:48:32.325451
3235 14:48:32.325521
3236 14:48:32.328749 TX Vref Scan disable
3237 14:48:32.332244 == TX Byte 0 ==
3238 14:48:32.335346 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3239 14:48:32.338317 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3240 14:48:32.341743 == TX Byte 1 ==
3241 14:48:32.345053 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 14:48:32.348437 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 14:48:32.348519 ==
3244 14:48:32.351794 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 14:48:32.355029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 14:48:32.358419 ==
3247 14:48:32.368750 TX Vref=22, minBit 10, minWin=24, winSum=405
3248 14:48:32.371755 TX Vref=24, minBit 8, minWin=25, winSum=411
3249 14:48:32.375133 TX Vref=26, minBit 8, minWin=25, winSum=413
3250 14:48:32.378465 TX Vref=28, minBit 9, minWin=25, winSum=420
3251 14:48:32.381846 TX Vref=30, minBit 9, minWin=25, winSum=421
3252 14:48:32.388695 TX Vref=32, minBit 9, minWin=24, winSum=419
3253 14:48:32.391907 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 30
3254 14:48:32.392035
3255 14:48:32.395304 Final TX Range 1 Vref 30
3256 14:48:32.395427
3257 14:48:32.395540 ==
3258 14:48:32.398645 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 14:48:32.402107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 14:48:32.402233 ==
3261 14:48:32.405559
3262 14:48:32.405681
3263 14:48:32.405793 TX Vref Scan disable
3264 14:48:32.408495 == TX Byte 0 ==
3265 14:48:32.411850 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3266 14:48:32.415528 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3267 14:48:32.418582 == TX Byte 1 ==
3268 14:48:32.421993 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 14:48:32.425369 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 14:48:32.425445
3271 14:48:32.428711 [DATLAT]
3272 14:48:32.428791 Freq=1200, CH1 RK0
3273 14:48:32.428855
3274 14:48:32.432032 DATLAT Default: 0xd
3275 14:48:32.432107 0, 0xFFFF, sum = 0
3276 14:48:32.435447 1, 0xFFFF, sum = 0
3277 14:48:32.435528 2, 0xFFFF, sum = 0
3278 14:48:32.438644 3, 0xFFFF, sum = 0
3279 14:48:32.438743 4, 0xFFFF, sum = 0
3280 14:48:32.442148 5, 0xFFFF, sum = 0
3281 14:48:32.442258 6, 0xFFFF, sum = 0
3282 14:48:32.445238 7, 0xFFFF, sum = 0
3283 14:48:32.448542 8, 0xFFFF, sum = 0
3284 14:48:32.448673 9, 0xFFFF, sum = 0
3285 14:48:32.451974 10, 0xFFFF, sum = 0
3286 14:48:32.452098 11, 0xFFFF, sum = 0
3287 14:48:32.455405 12, 0x0, sum = 1
3288 14:48:32.455533 13, 0x0, sum = 2
3289 14:48:32.458808 14, 0x0, sum = 3
3290 14:48:32.458935 15, 0x0, sum = 4
3291 14:48:32.459051 best_step = 13
3292 14:48:32.459162
3293 14:48:32.461732 ==
3294 14:48:32.461840 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 14:48:32.468576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 14:48:32.468692 ==
3297 14:48:32.468788 RX Vref Scan: 1
3298 14:48:32.468878
3299 14:48:32.471824 Set Vref Range= 32 -> 127
3300 14:48:32.471951
3301 14:48:32.475417 RX Vref 32 -> 127, step: 1
3302 14:48:32.475499
3303 14:48:32.478594 RX Delay -21 -> 252, step: 4
3304 14:48:32.478678
3305 14:48:32.482009 Set Vref, RX VrefLevel [Byte0]: 32
3306 14:48:32.485430 [Byte1]: 32
3307 14:48:32.485537
3308 14:48:32.488659 Set Vref, RX VrefLevel [Byte0]: 33
3309 14:48:32.491725 [Byte1]: 33
3310 14:48:32.491833
3311 14:48:32.495281 Set Vref, RX VrefLevel [Byte0]: 34
3312 14:48:32.498636 [Byte1]: 34
3313 14:48:32.502813
3314 14:48:32.502921 Set Vref, RX VrefLevel [Byte0]: 35
3315 14:48:32.506186 [Byte1]: 35
3316 14:48:32.510563
3317 14:48:32.510648 Set Vref, RX VrefLevel [Byte0]: 36
3318 14:48:32.513963 [Byte1]: 36
3319 14:48:32.518685
3320 14:48:32.518765 Set Vref, RX VrefLevel [Byte0]: 37
3321 14:48:32.522114 [Byte1]: 37
3322 14:48:32.526457
3323 14:48:32.526540 Set Vref, RX VrefLevel [Byte0]: 38
3324 14:48:32.529887 [Byte1]: 38
3325 14:48:32.534267
3326 14:48:32.534345 Set Vref, RX VrefLevel [Byte0]: 39
3327 14:48:32.537718 [Byte1]: 39
3328 14:48:32.542357
3329 14:48:32.542437 Set Vref, RX VrefLevel [Byte0]: 40
3330 14:48:32.545633 [Byte1]: 40
3331 14:48:32.550176
3332 14:48:32.550259 Set Vref, RX VrefLevel [Byte0]: 41
3333 14:48:32.553470 [Byte1]: 41
3334 14:48:32.558471
3335 14:48:32.558594 Set Vref, RX VrefLevel [Byte0]: 42
3336 14:48:32.561636 [Byte1]: 42
3337 14:48:32.566248
3338 14:48:32.566372 Set Vref, RX VrefLevel [Byte0]: 43
3339 14:48:32.569264 [Byte1]: 43
3340 14:48:32.574077
3341 14:48:32.574158 Set Vref, RX VrefLevel [Byte0]: 44
3342 14:48:32.577433 [Byte1]: 44
3343 14:48:32.581960
3344 14:48:32.582041 Set Vref, RX VrefLevel [Byte0]: 45
3345 14:48:32.585209 [Byte1]: 45
3346 14:48:32.590292
3347 14:48:32.590373 Set Vref, RX VrefLevel [Byte0]: 46
3348 14:48:32.593073 [Byte1]: 46
3349 14:48:32.597727
3350 14:48:32.597808 Set Vref, RX VrefLevel [Byte0]: 47
3351 14:48:32.601383 [Byte1]: 47
3352 14:48:32.605585
3353 14:48:32.605659 Set Vref, RX VrefLevel [Byte0]: 48
3354 14:48:32.608930 [Byte1]: 48
3355 14:48:32.613504
3356 14:48:32.613609 Set Vref, RX VrefLevel [Byte0]: 49
3357 14:48:32.616815 [Byte1]: 49
3358 14:48:32.621507
3359 14:48:32.621593 Set Vref, RX VrefLevel [Byte0]: 50
3360 14:48:32.624787 [Byte1]: 50
3361 14:48:32.629774
3362 14:48:32.629846 Set Vref, RX VrefLevel [Byte0]: 51
3363 14:48:32.633255 [Byte1]: 51
3364 14:48:32.637639
3365 14:48:32.637716 Set Vref, RX VrefLevel [Byte0]: 52
3366 14:48:32.640813 [Byte1]: 52
3367 14:48:32.645198
3368 14:48:32.645277 Set Vref, RX VrefLevel [Byte0]: 53
3369 14:48:32.648715 [Byte1]: 53
3370 14:48:32.653349
3371 14:48:32.653421 Set Vref, RX VrefLevel [Byte0]: 54
3372 14:48:32.656902 [Byte1]: 54
3373 14:48:32.661445
3374 14:48:32.661520 Set Vref, RX VrefLevel [Byte0]: 55
3375 14:48:32.664841 [Byte1]: 55
3376 14:48:32.669114
3377 14:48:32.669198 Set Vref, RX VrefLevel [Byte0]: 56
3378 14:48:32.672355 [Byte1]: 56
3379 14:48:32.677256
3380 14:48:32.677337 Set Vref, RX VrefLevel [Byte0]: 57
3381 14:48:32.680553 [Byte1]: 57
3382 14:48:32.685138
3383 14:48:32.685220 Set Vref, RX VrefLevel [Byte0]: 58
3384 14:48:32.688355 [Byte1]: 58
3385 14:48:32.692672
3386 14:48:32.692782 Set Vref, RX VrefLevel [Byte0]: 59
3387 14:48:32.696457 [Byte1]: 59
3388 14:48:32.700762
3389 14:48:32.700837 Set Vref, RX VrefLevel [Byte0]: 60
3390 14:48:32.704224 [Byte1]: 60
3391 14:48:32.708819
3392 14:48:32.708900 Set Vref, RX VrefLevel [Byte0]: 61
3393 14:48:32.712311 [Byte1]: 61
3394 14:48:32.716685
3395 14:48:32.716767 Set Vref, RX VrefLevel [Byte0]: 62
3396 14:48:32.719748 [Byte1]: 62
3397 14:48:32.724275
3398 14:48:32.724404 Set Vref, RX VrefLevel [Byte0]: 63
3399 14:48:32.727913 [Byte1]: 63
3400 14:48:32.732645
3401 14:48:32.732770 Set Vref, RX VrefLevel [Byte0]: 64
3402 14:48:32.736726 [Byte1]: 64
3403 14:48:32.740471
3404 14:48:32.740596 Final RX Vref Byte 0 = 59 to rank0
3405 14:48:32.743742 Final RX Vref Byte 1 = 54 to rank0
3406 14:48:32.747149 Final RX Vref Byte 0 = 59 to rank1
3407 14:48:32.750625 Final RX Vref Byte 1 = 54 to rank1==
3408 14:48:32.753848 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 14:48:32.760180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 14:48:32.760308 ==
3411 14:48:32.760425 DQS Delay:
3412 14:48:32.760537 DQS0 = 0, DQS1 = 0
3413 14:48:32.763971 DQM Delay:
3414 14:48:32.764092 DQM0 = 113, DQM1 = 107
3415 14:48:32.767315 DQ Delay:
3416 14:48:32.770192 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =110
3417 14:48:32.773439 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3418 14:48:32.776839 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =100
3419 14:48:32.780434 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3420 14:48:32.780554
3421 14:48:32.780678
3422 14:48:32.787152 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3423 14:48:32.790651 CH1 RK0: MR19=303, MR18=EDF4
3424 14:48:32.797034 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3425 14:48:32.797160
3426 14:48:32.800316 ----->DramcWriteLeveling(PI) begin...
3427 14:48:32.800439 ==
3428 14:48:32.803839 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 14:48:32.806860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 14:48:32.810399 ==
3431 14:48:32.810523 Write leveling (Byte 0): 23 => 23
3432 14:48:32.813856 Write leveling (Byte 1): 27 => 27
3433 14:48:32.816932 DramcWriteLeveling(PI) end<-----
3434 14:48:32.817055
3435 14:48:32.817163 ==
3436 14:48:32.820342 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 14:48:32.826999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 14:48:32.827124 ==
3439 14:48:32.827238 [Gating] SW mode calibration
3440 14:48:32.836981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 14:48:32.840602 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 14:48:32.843859 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3443 14:48:32.850571 0 15 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
3444 14:48:32.853444 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 14:48:32.857152 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 14:48:32.863620 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 14:48:32.867252 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3448 14:48:32.870344 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 1)
3449 14:48:32.877007 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3450 14:48:32.880729 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 14:48:32.883768 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 14:48:32.890313 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 14:48:32.893756 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 14:48:32.897036 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 14:48:32.903547 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3456 14:48:32.906771 1 0 24 | B1->B0 | 2e2e 4544 | 0 1 | (0 0) (0 0)
3457 14:48:32.910212 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3458 14:48:32.916949 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 14:48:32.920375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 14:48:32.923448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 14:48:32.930614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 14:48:32.933638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 14:48:32.936789 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 14:48:32.940178 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 14:48:32.946708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3466 14:48:32.950230 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3467 14:48:32.953741 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 14:48:32.960244 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 14:48:32.963568 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 14:48:32.966625 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 14:48:32.973078 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 14:48:32.976506 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 14:48:32.979822 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 14:48:32.986295 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 14:48:32.989638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 14:48:32.993272 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 14:48:32.999590 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 14:48:33.002836 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 14:48:33.006046 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 14:48:33.012808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 14:48:33.016094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3482 14:48:33.019443 Total UI for P1: 0, mck2ui 16
3483 14:48:33.022771 best dqsien dly found for B0: ( 1, 3, 24)
3484 14:48:33.026204 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 14:48:33.029130 Total UI for P1: 0, mck2ui 16
3486 14:48:33.032407 best dqsien dly found for B1: ( 1, 3, 26)
3487 14:48:33.035706 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3488 14:48:33.042487 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3489 14:48:33.042570
3490 14:48:33.046024 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3491 14:48:33.049067 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3492 14:48:33.052704 [Gating] SW calibration Done
3493 14:48:33.052785 ==
3494 14:48:33.055878 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 14:48:33.058926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 14:48:33.059009 ==
3497 14:48:33.062195 RX Vref Scan: 0
3498 14:48:33.062276
3499 14:48:33.062340 RX Vref 0 -> 0, step: 1
3500 14:48:33.062399
3501 14:48:33.065643 RX Delay -40 -> 252, step: 8
3502 14:48:33.068968 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3503 14:48:33.075608 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3504 14:48:33.078802 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3505 14:48:33.082292 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3506 14:48:33.085308 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3507 14:48:33.088465 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3508 14:48:33.095438 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3509 14:48:33.098792 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3510 14:48:33.102189 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3511 14:48:33.105672 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3512 14:48:33.108888 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3513 14:48:33.111752 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3514 14:48:33.118321 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3515 14:48:33.121597 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3516 14:48:33.125391 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3517 14:48:33.128291 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3518 14:48:33.128364 ==
3519 14:48:33.131548 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 14:48:33.138401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 14:48:33.138483 ==
3522 14:48:33.138547 DQS Delay:
3523 14:48:33.141847 DQS0 = 0, DQS1 = 0
3524 14:48:33.141944 DQM Delay:
3525 14:48:33.144921 DQM0 = 109, DQM1 = 108
3526 14:48:33.145028 DQ Delay:
3527 14:48:33.148200 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3528 14:48:33.151350 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3529 14:48:33.154787 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3530 14:48:33.158151 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3531 14:48:33.158228
3532 14:48:33.158313
3533 14:48:33.158381 ==
3534 14:48:33.161249 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 14:48:33.168136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 14:48:33.168220 ==
3537 14:48:33.168285
3538 14:48:33.168344
3539 14:48:33.168402 TX Vref Scan disable
3540 14:48:33.171403 == TX Byte 0 ==
3541 14:48:33.174752 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3542 14:48:33.181309 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3543 14:48:33.181394 == TX Byte 1 ==
3544 14:48:33.184719 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3545 14:48:33.191223 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3546 14:48:33.191307 ==
3547 14:48:33.194366 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 14:48:33.197691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 14:48:33.197775 ==
3550 14:48:33.209478 TX Vref=22, minBit 9, minWin=25, winSum=421
3551 14:48:33.212801 TX Vref=24, minBit 0, minWin=25, winSum=424
3552 14:48:33.216115 TX Vref=26, minBit 8, minWin=26, winSum=431
3553 14:48:33.219457 TX Vref=28, minBit 9, minWin=26, winSum=433
3554 14:48:33.222888 TX Vref=30, minBit 9, minWin=26, winSum=431
3555 14:48:33.229000 TX Vref=32, minBit 4, minWin=26, winSum=430
3556 14:48:33.232960 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3557 14:48:33.233045
3558 14:48:33.235625 Final TX Range 1 Vref 28
3559 14:48:33.235709
3560 14:48:33.235792 ==
3561 14:48:33.239003 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 14:48:33.242154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 14:48:33.245605 ==
3564 14:48:33.245689
3565 14:48:33.245789
3566 14:48:33.245886 TX Vref Scan disable
3567 14:48:33.249280 == TX Byte 0 ==
3568 14:48:33.252767 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3569 14:48:33.259053 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3570 14:48:33.259137 == TX Byte 1 ==
3571 14:48:33.262182 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 14:48:33.269330 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 14:48:33.269421
3574 14:48:33.269506 [DATLAT]
3575 14:48:33.269604 Freq=1200, CH1 RK1
3576 14:48:33.269702
3577 14:48:33.271991 DATLAT Default: 0xd
3578 14:48:33.276050 0, 0xFFFF, sum = 0
3579 14:48:33.276136 1, 0xFFFF, sum = 0
3580 14:48:33.279011 2, 0xFFFF, sum = 0
3581 14:48:33.279122 3, 0xFFFF, sum = 0
3582 14:48:33.282522 4, 0xFFFF, sum = 0
3583 14:48:33.282607 5, 0xFFFF, sum = 0
3584 14:48:33.285650 6, 0xFFFF, sum = 0
3585 14:48:33.285735 7, 0xFFFF, sum = 0
3586 14:48:33.288787 8, 0xFFFF, sum = 0
3587 14:48:33.288874 9, 0xFFFF, sum = 0
3588 14:48:33.292123 10, 0xFFFF, sum = 0
3589 14:48:33.292208 11, 0xFFFF, sum = 0
3590 14:48:33.295347 12, 0x0, sum = 1
3591 14:48:33.295432 13, 0x0, sum = 2
3592 14:48:33.298840 14, 0x0, sum = 3
3593 14:48:33.298935 15, 0x0, sum = 4
3594 14:48:33.302023 best_step = 13
3595 14:48:33.302106
3596 14:48:33.302190 ==
3597 14:48:33.305480 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 14:48:33.308995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 14:48:33.309080 ==
3600 14:48:33.311753 RX Vref Scan: 0
3601 14:48:33.311868
3602 14:48:33.311953 RX Vref 0 -> 0, step: 1
3603 14:48:33.312051
3604 14:48:33.315376 RX Delay -21 -> 252, step: 4
3605 14:48:33.321874 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3606 14:48:33.325245 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3607 14:48:33.328738 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3608 14:48:33.331991 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3609 14:48:33.335089 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3610 14:48:33.341761 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3611 14:48:33.345171 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3612 14:48:33.348432 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3613 14:48:33.351813 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3614 14:48:33.355309 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3615 14:48:33.361464 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3616 14:48:33.364974 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3617 14:48:33.368542 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3618 14:48:33.371603 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3619 14:48:33.375059 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3620 14:48:33.381758 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3621 14:48:33.381848 ==
3622 14:48:33.385309 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 14:48:33.388039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 14:48:33.388123 ==
3625 14:48:33.388208 DQS Delay:
3626 14:48:33.391293 DQS0 = 0, DQS1 = 0
3627 14:48:33.391377 DQM Delay:
3628 14:48:33.394907 DQM0 = 111, DQM1 = 109
3629 14:48:33.394991 DQ Delay:
3630 14:48:33.397984 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3631 14:48:33.401096 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3632 14:48:33.404939 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3633 14:48:33.407880 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3634 14:48:33.407964
3635 14:48:33.411325
3636 14:48:33.417782 [DQSOSCAuto] RK1, (LSB)MR18= 0xf909, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3637 14:48:33.421196 CH1 RK1: MR19=304, MR18=F909
3638 14:48:33.427710 CH1_RK1: MR19=0x304, MR18=0xF909, DQSOSC=406, MR23=63, INC=39, DEC=26
3639 14:48:33.431265 [RxdqsGatingPostProcess] freq 1200
3640 14:48:33.434553 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 14:48:33.437886 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 14:48:33.441094 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 14:48:33.444543 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 14:48:33.447828 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 14:48:33.451203 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 14:48:33.454408 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 14:48:33.457778 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 14:48:33.461002 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 14:48:33.464196 Pre-setting of DQS Precalculation
3650 14:48:33.467633 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 14:48:33.474412 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 14:48:33.484616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 14:48:33.484746
3654 14:48:33.484859
3655 14:48:33.484969 [Calibration Summary] 2400 Mbps
3656 14:48:33.487767 CH 0, Rank 0
3657 14:48:33.490751 SW Impedance : PASS
3658 14:48:33.490873 DUTY Scan : NO K
3659 14:48:33.494374 ZQ Calibration : PASS
3660 14:48:33.494479 Jitter Meter : NO K
3661 14:48:33.497748 CBT Training : PASS
3662 14:48:33.501059 Write leveling : PASS
3663 14:48:33.501142 RX DQS gating : PASS
3664 14:48:33.504699 RX DQ/DQS(RDDQC) : PASS
3665 14:48:33.507489 TX DQ/DQS : PASS
3666 14:48:33.507572 RX DATLAT : PASS
3667 14:48:33.510843 RX DQ/DQS(Engine): PASS
3668 14:48:33.514089 TX OE : NO K
3669 14:48:33.514172 All Pass.
3670 14:48:33.514236
3671 14:48:33.514296 CH 0, Rank 1
3672 14:48:33.517812 SW Impedance : PASS
3673 14:48:33.520709 DUTY Scan : NO K
3674 14:48:33.520790 ZQ Calibration : PASS
3675 14:48:33.524067 Jitter Meter : NO K
3676 14:48:33.527278 CBT Training : PASS
3677 14:48:33.527369 Write leveling : PASS
3678 14:48:33.530764 RX DQS gating : PASS
3679 14:48:33.534206 RX DQ/DQS(RDDQC) : PASS
3680 14:48:33.534288 TX DQ/DQS : PASS
3681 14:48:33.537219 RX DATLAT : PASS
3682 14:48:33.540498 RX DQ/DQS(Engine): PASS
3683 14:48:33.540610 TX OE : NO K
3684 14:48:33.540697 All Pass.
3685 14:48:33.543714
3686 14:48:33.543798 CH 1, Rank 0
3687 14:48:33.547099 SW Impedance : PASS
3688 14:48:33.547184 DUTY Scan : NO K
3689 14:48:33.550474 ZQ Calibration : PASS
3690 14:48:33.553817 Jitter Meter : NO K
3691 14:48:33.553905 CBT Training : PASS
3692 14:48:33.557235 Write leveling : PASS
3693 14:48:33.557321 RX DQS gating : PASS
3694 14:48:33.560489 RX DQ/DQS(RDDQC) : PASS
3695 14:48:33.563797 TX DQ/DQS : PASS
3696 14:48:33.563882 RX DATLAT : PASS
3697 14:48:33.567050 RX DQ/DQS(Engine): PASS
3698 14:48:33.570302 TX OE : NO K
3699 14:48:33.570389 All Pass.
3700 14:48:33.570475
3701 14:48:33.570556 CH 1, Rank 1
3702 14:48:33.573693 SW Impedance : PASS
3703 14:48:33.576988 DUTY Scan : NO K
3704 14:48:33.577075 ZQ Calibration : PASS
3705 14:48:33.580124 Jitter Meter : NO K
3706 14:48:33.583447 CBT Training : PASS
3707 14:48:33.583532 Write leveling : PASS
3708 14:48:33.586632 RX DQS gating : PASS
3709 14:48:33.590038 RX DQ/DQS(RDDQC) : PASS
3710 14:48:33.590123 TX DQ/DQS : PASS
3711 14:48:33.593241 RX DATLAT : PASS
3712 14:48:33.596826 RX DQ/DQS(Engine): PASS
3713 14:48:33.596911 TX OE : NO K
3714 14:48:33.599758 All Pass.
3715 14:48:33.599881
3716 14:48:33.599994 DramC Write-DBI off
3717 14:48:33.603748 PER_BANK_REFRESH: Hybrid Mode
3718 14:48:33.603875 TX_TRACKING: ON
3719 14:48:33.612892 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 14:48:33.617012 [FAST_K] Save calibration result to emmc
3721 14:48:33.619816 dramc_set_vcore_voltage set vcore to 650000
3722 14:48:33.623189 Read voltage for 600, 5
3723 14:48:33.623314 Vio18 = 0
3724 14:48:33.626432 Vcore = 650000
3725 14:48:33.626554 Vdram = 0
3726 14:48:33.626661 Vddq = 0
3727 14:48:33.629817 Vmddr = 0
3728 14:48:33.632776 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 14:48:33.639594 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 14:48:33.639720 MEM_TYPE=3, freq_sel=19
3731 14:48:33.643218 sv_algorithm_assistance_LP4_1600
3732 14:48:33.649564 ============ PULL DRAM RESETB DOWN ============
3733 14:48:33.652807 ========== PULL DRAM RESETB DOWN end =========
3734 14:48:33.656007 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 14:48:33.659296 ===================================
3736 14:48:33.662710 LPDDR4 DRAM CONFIGURATION
3737 14:48:33.666403 ===================================
3738 14:48:33.666487 EX_ROW_EN[0] = 0x0
3739 14:48:33.669304 EX_ROW_EN[1] = 0x0
3740 14:48:33.672460 LP4Y_EN = 0x0
3741 14:48:33.672572 WORK_FSP = 0x0
3742 14:48:33.675752 WL = 0x2
3743 14:48:33.675835 RL = 0x2
3744 14:48:33.679235 BL = 0x2
3745 14:48:33.679318 RPST = 0x0
3746 14:48:33.682665 RD_PRE = 0x0
3747 14:48:33.682748 WR_PRE = 0x1
3748 14:48:33.686020 WR_PST = 0x0
3749 14:48:33.686103 DBI_WR = 0x0
3750 14:48:33.688922 DBI_RD = 0x0
3751 14:48:33.689010 OTF = 0x1
3752 14:48:33.692191 ===================================
3753 14:48:33.695564 ===================================
3754 14:48:33.699163 ANA top config
3755 14:48:33.702562 ===================================
3756 14:48:33.705558 DLL_ASYNC_EN = 0
3757 14:48:33.705642 ALL_SLAVE_EN = 1
3758 14:48:33.708589 NEW_RANK_MODE = 1
3759 14:48:33.712227 DLL_IDLE_MODE = 1
3760 14:48:33.715201 LP45_APHY_COMB_EN = 1
3761 14:48:33.718828 TX_ODT_DIS = 1
3762 14:48:33.718908 NEW_8X_MODE = 1
3763 14:48:33.721808 ===================================
3764 14:48:33.725150 ===================================
3765 14:48:33.728767 data_rate = 1200
3766 14:48:33.731721 CKR = 1
3767 14:48:33.735058 DQ_P2S_RATIO = 8
3768 14:48:33.738297 ===================================
3769 14:48:33.741545 CA_P2S_RATIO = 8
3770 14:48:33.744983 DQ_CA_OPEN = 0
3771 14:48:33.745066 DQ_SEMI_OPEN = 0
3772 14:48:33.748309 CA_SEMI_OPEN = 0
3773 14:48:33.751864 CA_FULL_RATE = 0
3774 14:48:33.755308 DQ_CKDIV4_EN = 1
3775 14:48:33.758574 CA_CKDIV4_EN = 1
3776 14:48:33.762107 CA_PREDIV_EN = 0
3777 14:48:33.762189 PH8_DLY = 0
3778 14:48:33.764943 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 14:48:33.768337 DQ_AAMCK_DIV = 4
3780 14:48:33.771711 CA_AAMCK_DIV = 4
3781 14:48:33.774944 CA_ADMCK_DIV = 4
3782 14:48:33.778159 DQ_TRACK_CA_EN = 0
3783 14:48:33.778245 CA_PICK = 600
3784 14:48:33.781547 CA_MCKIO = 600
3785 14:48:33.784871 MCKIO_SEMI = 0
3786 14:48:33.788175 PLL_FREQ = 2288
3787 14:48:33.791377 DQ_UI_PI_RATIO = 32
3788 14:48:33.794606 CA_UI_PI_RATIO = 0
3789 14:48:33.798331 ===================================
3790 14:48:33.801166 ===================================
3791 14:48:33.801249 memory_type:LPDDR4
3792 14:48:33.804590 GP_NUM : 10
3793 14:48:33.808095 SRAM_EN : 1
3794 14:48:33.808177 MD32_EN : 0
3795 14:48:33.811042 ===================================
3796 14:48:33.814394 [ANA_INIT] >>>>>>>>>>>>>>
3797 14:48:33.817753 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 14:48:33.821260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 14:48:33.824699 ===================================
3800 14:48:33.827645 data_rate = 1200,PCW = 0X5800
3801 14:48:33.830826 ===================================
3802 14:48:33.834325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 14:48:33.837764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 14:48:33.843973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 14:48:33.850654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 14:48:33.854130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 14:48:33.857451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 14:48:33.857538 [ANA_INIT] flow start
3809 14:48:33.860649 [ANA_INIT] PLL >>>>>>>>
3810 14:48:33.863893 [ANA_INIT] PLL <<<<<<<<
3811 14:48:33.863971 [ANA_INIT] MIDPI >>>>>>>>
3812 14:48:33.867446 [ANA_INIT] MIDPI <<<<<<<<
3813 14:48:33.871778 [ANA_INIT] DLL >>>>>>>>
3814 14:48:33.871883 [ANA_INIT] flow end
3815 14:48:33.877547 ============ LP4 DIFF to SE enter ============
3816 14:48:33.880968 ============ LP4 DIFF to SE exit ============
3817 14:48:33.881051 [ANA_INIT] <<<<<<<<<<<<<
3818 14:48:33.884142 [Flow] Enable top DCM control >>>>>
3819 14:48:33.887547 [Flow] Enable top DCM control <<<<<
3820 14:48:33.890935 Enable DLL master slave shuffle
3821 14:48:33.897507 ==============================================================
3822 14:48:33.901018 Gating Mode config
3823 14:48:33.904143 ==============================================================
3824 14:48:33.906915 Config description:
3825 14:48:33.916849 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 14:48:33.923653 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 14:48:33.926971 SELPH_MODE 0: By rank 1: By Phase
3828 14:48:33.933374 ==============================================================
3829 14:48:33.936800 GAT_TRACK_EN = 1
3830 14:48:33.940436 RX_GATING_MODE = 2
3831 14:48:33.943554 RX_GATING_TRACK_MODE = 2
3832 14:48:33.946887 SELPH_MODE = 1
3833 14:48:33.946968 PICG_EARLY_EN = 1
3834 14:48:33.950306 VALID_LAT_VALUE = 1
3835 14:48:33.957035 ==============================================================
3836 14:48:33.959878 Enter into Gating configuration >>>>
3837 14:48:33.963390 Exit from Gating configuration <<<<
3838 14:48:33.966562 Enter into DVFS_PRE_config >>>>>
3839 14:48:33.976626 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 14:48:33.979596 Exit from DVFS_PRE_config <<<<<
3841 14:48:33.983111 Enter into PICG configuration >>>>
3842 14:48:33.986694 Exit from PICG configuration <<<<
3843 14:48:33.989974 [RX_INPUT] configuration >>>>>
3844 14:48:33.992797 [RX_INPUT] configuration <<<<<
3845 14:48:33.996472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 14:48:34.003033 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 14:48:34.009717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 14:48:34.016459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 14:48:34.022754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 14:48:34.029203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 14:48:34.033022 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 14:48:34.036140 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 14:48:34.039646 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 14:48:34.045708 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 14:48:34.049328 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 14:48:34.052209 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 14:48:34.055771 ===================================
3858 14:48:34.059162 LPDDR4 DRAM CONFIGURATION
3859 14:48:34.062458 ===================================
3860 14:48:34.062585 EX_ROW_EN[0] = 0x0
3861 14:48:34.065507 EX_ROW_EN[1] = 0x0
3862 14:48:34.065630 LP4Y_EN = 0x0
3863 14:48:34.068930 WORK_FSP = 0x0
3864 14:48:34.072352 WL = 0x2
3865 14:48:34.072463 RL = 0x2
3866 14:48:34.075831 BL = 0x2
3867 14:48:34.075913 RPST = 0x0
3868 14:48:34.078953 RD_PRE = 0x0
3869 14:48:34.079035 WR_PRE = 0x1
3870 14:48:34.082086 WR_PST = 0x0
3871 14:48:34.082167 DBI_WR = 0x0
3872 14:48:34.085686 DBI_RD = 0x0
3873 14:48:34.085767 OTF = 0x1
3874 14:48:34.088881 ===================================
3875 14:48:34.092141 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 14:48:34.099057 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 14:48:34.101847 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 14:48:34.105269 ===================================
3879 14:48:34.108624 LPDDR4 DRAM CONFIGURATION
3880 14:48:34.111909 ===================================
3881 14:48:34.112008 EX_ROW_EN[0] = 0x10
3882 14:48:34.115205 EX_ROW_EN[1] = 0x0
3883 14:48:34.115315 LP4Y_EN = 0x0
3884 14:48:34.118900 WORK_FSP = 0x0
3885 14:48:34.122217 WL = 0x2
3886 14:48:34.122296 RL = 0x2
3887 14:48:34.125029 BL = 0x2
3888 14:48:34.125109 RPST = 0x0
3889 14:48:34.128457 RD_PRE = 0x0
3890 14:48:34.128539 WR_PRE = 0x1
3891 14:48:34.131467 WR_PST = 0x0
3892 14:48:34.131549 DBI_WR = 0x0
3893 14:48:34.134810 DBI_RD = 0x0
3894 14:48:34.134921 OTF = 0x1
3895 14:48:34.138454 ===================================
3896 14:48:34.144874 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 14:48:34.148966 nWR fixed to 30
3898 14:48:34.152231 [ModeRegInit_LP4] CH0 RK0
3899 14:48:34.152313 [ModeRegInit_LP4] CH0 RK1
3900 14:48:34.155767 [ModeRegInit_LP4] CH1 RK0
3901 14:48:34.159114 [ModeRegInit_LP4] CH1 RK1
3902 14:48:34.159193 match AC timing 17
3903 14:48:34.165980 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 14:48:34.169044 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 14:48:34.172452 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 14:48:34.178996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 14:48:34.182341 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 14:48:34.182448 ==
3909 14:48:34.185720 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 14:48:34.188832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 14:48:34.189014 ==
3912 14:48:34.195672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 14:48:34.202066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3914 14:48:34.205664 [CA 0] Center 37 (7~67) winsize 61
3915 14:48:34.209385 [CA 1] Center 37 (7~67) winsize 61
3916 14:48:34.212003 [CA 2] Center 35 (5~65) winsize 61
3917 14:48:34.215440 [CA 3] Center 35 (5~65) winsize 61
3918 14:48:34.218636 [CA 4] Center 34 (4~65) winsize 62
3919 14:48:34.222235 [CA 5] Center 33 (3~64) winsize 62
3920 14:48:34.222362
3921 14:48:34.225421 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3922 14:48:34.225523
3923 14:48:34.228717 [CATrainingPosCal] consider 1 rank data
3924 14:48:34.232210 u2DelayCellTimex100 = 270/100 ps
3925 14:48:34.235636 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3926 14:48:34.238599 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3927 14:48:34.241824 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3928 14:48:34.245446 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3929 14:48:34.248690 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 14:48:34.255273 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 14:48:34.255348
3932 14:48:34.258676 CA PerBit enable=1, Macro0, CA PI delay=33
3933 14:48:34.258749
3934 14:48:34.262060 [CBTSetCACLKResult] CA Dly = 33
3935 14:48:34.262135 CS Dly: 6 (0~37)
3936 14:48:34.262212 ==
3937 14:48:34.265431 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 14:48:34.268859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 14:48:34.272117 ==
3940 14:48:34.275597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 14:48:34.281904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 14:48:34.285594 [CA 0] Center 37 (7~67) winsize 61
3943 14:48:34.288385 [CA 1] Center 36 (6~67) winsize 62
3944 14:48:34.291899 [CA 2] Center 35 (5~65) winsize 61
3945 14:48:34.295505 [CA 3] Center 35 (5~65) winsize 61
3946 14:48:34.298686 [CA 4] Center 34 (4~65) winsize 62
3947 14:48:34.301744 [CA 5] Center 33 (3~64) winsize 62
3948 14:48:34.301821
3949 14:48:34.305220 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 14:48:34.305295
3951 14:48:34.308445 [CATrainingPosCal] consider 2 rank data
3952 14:48:34.311624 u2DelayCellTimex100 = 270/100 ps
3953 14:48:34.315314 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3954 14:48:34.318542 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3955 14:48:34.321858 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3956 14:48:34.328116 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3957 14:48:34.331429 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 14:48:34.334770 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 14:48:34.334875
3960 14:48:34.338048 CA PerBit enable=1, Macro0, CA PI delay=33
3961 14:48:34.338125
3962 14:48:34.341631 [CBTSetCACLKResult] CA Dly = 33
3963 14:48:34.341709 CS Dly: 6 (0~38)
3964 14:48:34.341784
3965 14:48:34.344794 ----->DramcWriteLeveling(PI) begin...
3966 14:48:34.348088 ==
3967 14:48:34.351417 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 14:48:34.354680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 14:48:34.354782 ==
3970 14:48:34.358089 Write leveling (Byte 0): 32 => 32
3971 14:48:34.361354 Write leveling (Byte 1): 31 => 31
3972 14:48:34.364596 DramcWriteLeveling(PI) end<-----
3973 14:48:34.364677
3974 14:48:34.364746 ==
3975 14:48:34.368084 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 14:48:34.371608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 14:48:34.371711 ==
3978 14:48:34.374710 [Gating] SW mode calibration
3979 14:48:34.381147 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 14:48:34.384508 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 14:48:34.391631 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 14:48:34.394587 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 14:48:34.398105 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 14:48:34.404492 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 14:48:34.407835 0 9 16 | B1->B0 | 3131 2929 | 0 0 | (0 1) (0 0)
3986 14:48:34.411269 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 14:48:34.417638 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 14:48:34.421149 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 14:48:34.424316 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 14:48:34.431176 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 14:48:34.434597 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 14:48:34.437884 0 10 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
3993 14:48:34.443978 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
3994 14:48:34.447357 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 14:48:34.451021 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 14:48:34.457399 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 14:48:34.460684 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 14:48:34.464133 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 14:48:34.470878 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 14:48:34.474167 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 14:48:34.477751 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 14:48:34.484268 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 14:48:34.487639 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 14:48:34.491043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 14:48:34.497292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 14:48:34.501044 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 14:48:34.504403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 14:48:34.510636 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 14:48:34.514229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 14:48:34.517422 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 14:48:34.523870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 14:48:34.527027 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 14:48:34.530545 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 14:48:34.537356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 14:48:34.540490 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 14:48:34.543861 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 14:48:34.550483 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 14:48:34.550559 Total UI for P1: 0, mck2ui 16
4019 14:48:34.553917 best dqsien dly found for B0: ( 0, 13, 12)
4020 14:48:34.557219 Total UI for P1: 0, mck2ui 16
4021 14:48:34.560518 best dqsien dly found for B1: ( 0, 13, 14)
4022 14:48:34.566758 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 14:48:34.570079 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4024 14:48:34.570158
4025 14:48:34.573552 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 14:48:34.576784 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 14:48:34.580070 [Gating] SW calibration Done
4028 14:48:34.580143 ==
4029 14:48:34.583414 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 14:48:34.586488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 14:48:34.586566 ==
4032 14:48:34.589851 RX Vref Scan: 0
4033 14:48:34.589925
4034 14:48:34.589993 RX Vref 0 -> 0, step: 1
4035 14:48:34.590052
4036 14:48:34.593202 RX Delay -230 -> 252, step: 16
4037 14:48:34.596362 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4038 14:48:34.603418 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4039 14:48:34.606924 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4040 14:48:34.610012 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4041 14:48:34.613481 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4042 14:48:34.619781 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4043 14:48:34.623305 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4044 14:48:34.626370 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4045 14:48:34.629894 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4046 14:48:34.632965 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4047 14:48:34.639919 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4048 14:48:34.642893 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4049 14:48:34.646320 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4050 14:48:34.649645 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4051 14:48:34.656355 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4052 14:48:34.659729 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4053 14:48:34.659830 ==
4054 14:48:34.662670 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 14:48:34.666125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 14:48:34.666209 ==
4057 14:48:34.669413 DQS Delay:
4058 14:48:34.669496 DQS0 = 0, DQS1 = 0
4059 14:48:34.672843 DQM Delay:
4060 14:48:34.672925 DQM0 = 38, DQM1 = 30
4061 14:48:34.673008 DQ Delay:
4062 14:48:34.676023 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4063 14:48:34.679541 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4064 14:48:34.682801 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4065 14:48:34.686203 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4066 14:48:34.686282
4067 14:48:34.686363
4068 14:48:34.689358 ==
4069 14:48:34.692832 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 14:48:34.695707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 14:48:34.695791 ==
4072 14:48:34.695891
4073 14:48:34.695989
4074 14:48:34.699278 TX Vref Scan disable
4075 14:48:34.699362 == TX Byte 0 ==
4076 14:48:34.706067 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 14:48:34.708973 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 14:48:34.709052 == TX Byte 1 ==
4079 14:48:34.715667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4080 14:48:34.719060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4081 14:48:34.719142 ==
4082 14:48:34.722327 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 14:48:34.725732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 14:48:34.725836 ==
4085 14:48:34.725928
4086 14:48:34.726015
4087 14:48:34.729249 TX Vref Scan disable
4088 14:48:34.732404 == TX Byte 0 ==
4089 14:48:34.736187 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4090 14:48:34.739228 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4091 14:48:34.742248 == TX Byte 1 ==
4092 14:48:34.745694 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4093 14:48:34.748841 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4094 14:48:34.748925
4095 14:48:34.752424 [DATLAT]
4096 14:48:34.752506 Freq=600, CH0 RK0
4097 14:48:34.752586
4098 14:48:34.755850 DATLAT Default: 0x9
4099 14:48:34.755933 0, 0xFFFF, sum = 0
4100 14:48:34.758926 1, 0xFFFF, sum = 0
4101 14:48:34.759014 2, 0xFFFF, sum = 0
4102 14:48:34.762457 3, 0xFFFF, sum = 0
4103 14:48:34.762541 4, 0xFFFF, sum = 0
4104 14:48:34.765546 5, 0xFFFF, sum = 0
4105 14:48:34.765621 6, 0xFFFF, sum = 0
4106 14:48:34.768675 7, 0xFFFF, sum = 0
4107 14:48:34.768760 8, 0x0, sum = 1
4108 14:48:34.772502 9, 0x0, sum = 2
4109 14:48:34.772612 10, 0x0, sum = 3
4110 14:48:34.775820 11, 0x0, sum = 4
4111 14:48:34.775920 best_step = 9
4112 14:48:34.776019
4113 14:48:34.776106 ==
4114 14:48:34.779249 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 14:48:34.782541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 14:48:34.785850 ==
4117 14:48:34.785935 RX Vref Scan: 1
4118 14:48:34.786000
4119 14:48:34.789134 RX Vref 0 -> 0, step: 1
4120 14:48:34.789231
4121 14:48:34.792388 RX Delay -195 -> 252, step: 8
4122 14:48:34.792505
4123 14:48:34.795694 Set Vref, RX VrefLevel [Byte0]: 62
4124 14:48:34.798940 [Byte1]: 58
4125 14:48:34.799053
4126 14:48:34.802214 Final RX Vref Byte 0 = 62 to rank0
4127 14:48:34.805419 Final RX Vref Byte 1 = 58 to rank0
4128 14:48:34.808946 Final RX Vref Byte 0 = 62 to rank1
4129 14:48:34.812161 Final RX Vref Byte 1 = 58 to rank1==
4130 14:48:34.815394 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 14:48:34.818548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 14:48:34.818677 ==
4133 14:48:34.821859 DQS Delay:
4134 14:48:34.821944 DQS0 = 0, DQS1 = 0
4135 14:48:34.822028 DQM Delay:
4136 14:48:34.825243 DQM0 = 35, DQM1 = 28
4137 14:48:34.825327 DQ Delay:
4138 14:48:34.828476 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4139 14:48:34.832302 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =48
4140 14:48:34.835482 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4141 14:48:34.838429 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4142 14:48:34.838528
4143 14:48:34.838615
4144 14:48:34.848428 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4145 14:48:34.848540 CH0 RK0: MR19=808, MR18=3C3B
4146 14:48:34.854985 CH0_RK0: MR19=0x808, MR18=0x3C3B, DQSOSC=398, MR23=63, INC=165, DEC=110
4147 14:48:34.855071
4148 14:48:34.858678 ----->DramcWriteLeveling(PI) begin...
4149 14:48:34.858758 ==
4150 14:48:34.862248 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 14:48:34.868839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 14:48:34.868923 ==
4153 14:48:34.871484 Write leveling (Byte 0): 31 => 31
4154 14:48:34.875203 Write leveling (Byte 1): 32 => 32
4155 14:48:34.878113 DramcWriteLeveling(PI) end<-----
4156 14:48:34.878195
4157 14:48:34.878260 ==
4158 14:48:34.881556 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 14:48:34.884834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 14:48:34.884918 ==
4161 14:48:34.888209 [Gating] SW mode calibration
4162 14:48:34.894930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 14:48:34.898383 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 14:48:34.904958 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 14:48:34.908211 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 14:48:34.911606 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4167 14:48:34.918287 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
4168 14:48:34.921182 0 9 16 | B1->B0 | 3030 2626 | 1 0 | (1 1) (0 0)
4169 14:48:34.924581 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 14:48:34.931336 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 14:48:34.934846 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 14:48:34.937683 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 14:48:34.944437 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 14:48:34.947814 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 14:48:34.951056 0 10 12 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (0 0)
4176 14:48:34.958053 0 10 16 | B1->B0 | 3636 4444 | 0 0 | (1 1) (0 0)
4177 14:48:34.961179 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 14:48:34.964045 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 14:48:34.970812 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 14:48:34.974391 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 14:48:34.977678 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 14:48:34.984110 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 14:48:34.987600 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4184 14:48:34.991028 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4185 14:48:34.997220 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 14:48:35.001165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 14:48:35.004003 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 14:48:35.010632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 14:48:35.014148 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 14:48:35.017165 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 14:48:35.024250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 14:48:35.027204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 14:48:35.030945 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 14:48:35.037492 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 14:48:35.040663 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 14:48:35.044048 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 14:48:35.050718 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 14:48:35.053624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 14:48:35.056845 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4200 14:48:35.060310 Total UI for P1: 0, mck2ui 16
4201 14:48:35.064033 best dqsien dly found for B0: ( 0, 13, 10)
4202 14:48:35.070257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4203 14:48:35.073921 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 14:48:35.077237 Total UI for P1: 0, mck2ui 16
4205 14:48:35.080810 best dqsien dly found for B1: ( 0, 13, 18)
4206 14:48:35.083486 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4207 14:48:35.087005 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4208 14:48:35.087127
4209 14:48:35.090435 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4210 14:48:35.093523 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4211 14:48:35.096910 [Gating] SW calibration Done
4212 14:48:35.097032 ==
4213 14:48:35.100177 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 14:48:35.103451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 14:48:35.103574 ==
4216 14:48:35.106820 RX Vref Scan: 0
4217 14:48:35.106943
4218 14:48:35.110084 RX Vref 0 -> 0, step: 1
4219 14:48:35.110201
4220 14:48:35.113230 RX Delay -230 -> 252, step: 16
4221 14:48:35.116727 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4222 14:48:35.120135 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4223 14:48:35.123438 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4224 14:48:35.126876 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4225 14:48:35.133419 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4226 14:48:35.136523 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4227 14:48:35.140118 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4228 14:48:35.143443 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4229 14:48:35.149674 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4230 14:48:35.153182 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4231 14:48:35.156457 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4232 14:48:35.159919 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4233 14:48:35.166564 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4234 14:48:35.169692 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4235 14:48:35.172993 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4236 14:48:35.176713 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4237 14:48:35.176797 ==
4238 14:48:35.179942 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 14:48:35.186573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 14:48:35.186657 ==
4241 14:48:35.186723 DQS Delay:
4242 14:48:35.189585 DQS0 = 0, DQS1 = 0
4243 14:48:35.189667 DQM Delay:
4244 14:48:35.189732 DQM0 = 34, DQM1 = 27
4245 14:48:35.192919 DQ Delay:
4246 14:48:35.196255 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4247 14:48:35.199513 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4248 14:48:35.202930 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4249 14:48:35.206415 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4250 14:48:35.206499
4251 14:48:35.206563
4252 14:48:35.206624 ==
4253 14:48:35.209731 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 14:48:35.213104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 14:48:35.213187 ==
4256 14:48:35.213267
4257 14:48:35.213330
4258 14:48:35.216544 TX Vref Scan disable
4259 14:48:35.219369 == TX Byte 0 ==
4260 14:48:35.222887 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4261 14:48:35.225961 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4262 14:48:35.229352 == TX Byte 1 ==
4263 14:48:35.233118 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4264 14:48:35.236327 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4265 14:48:35.236452 ==
4266 14:48:35.239547 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 14:48:35.242896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 14:48:35.243012 ==
4269 14:48:35.245957
4270 14:48:35.246086
4271 14:48:35.246193 TX Vref Scan disable
4272 14:48:35.249671 == TX Byte 0 ==
4273 14:48:35.253005 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 14:48:35.259584 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 14:48:35.259706 == TX Byte 1 ==
4276 14:48:35.262725 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4277 14:48:35.269453 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4278 14:48:35.269577
4279 14:48:35.269690 [DATLAT]
4280 14:48:35.269793 Freq=600, CH0 RK1
4281 14:48:35.269902
4282 14:48:35.272626 DATLAT Default: 0x9
4283 14:48:35.272733 0, 0xFFFF, sum = 0
4284 14:48:35.275793 1, 0xFFFF, sum = 0
4285 14:48:35.279529 2, 0xFFFF, sum = 0
4286 14:48:35.279652 3, 0xFFFF, sum = 0
4287 14:48:35.282723 4, 0xFFFF, sum = 0
4288 14:48:35.282843 5, 0xFFFF, sum = 0
4289 14:48:35.285966 6, 0xFFFF, sum = 0
4290 14:48:35.286089 7, 0xFFFF, sum = 0
4291 14:48:35.289175 8, 0x0, sum = 1
4292 14:48:35.289301 9, 0x0, sum = 2
4293 14:48:35.289416 10, 0x0, sum = 3
4294 14:48:35.292753 11, 0x0, sum = 4
4295 14:48:35.292875 best_step = 9
4296 14:48:35.292987
4297 14:48:35.296406 ==
4298 14:48:35.296516 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 14:48:35.302493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 14:48:35.302575 ==
4301 14:48:35.302640 RX Vref Scan: 0
4302 14:48:35.302710
4303 14:48:35.306067 RX Vref 0 -> 0, step: 1
4304 14:48:35.306145
4305 14:48:35.308982 RX Delay -195 -> 252, step: 8
4306 14:48:35.312446 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4307 14:48:35.319129 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4308 14:48:35.322379 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4309 14:48:35.325822 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4310 14:48:35.328971 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4311 14:48:35.335679 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4312 14:48:35.338789 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4313 14:48:35.342377 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4314 14:48:35.345714 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4315 14:48:35.352033 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4316 14:48:35.355638 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4317 14:48:35.359048 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4318 14:48:35.362417 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4319 14:48:35.368717 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4320 14:48:35.372172 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4321 14:48:35.375197 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4322 14:48:35.375278 ==
4323 14:48:35.378644 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 14:48:35.382009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 14:48:35.382091 ==
4326 14:48:35.385288 DQS Delay:
4327 14:48:35.385411 DQS0 = 0, DQS1 = 0
4328 14:48:35.388325 DQM Delay:
4329 14:48:35.388445 DQM0 = 33, DQM1 = 27
4330 14:48:35.388553 DQ Delay:
4331 14:48:35.392161 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4332 14:48:35.395385 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4333 14:48:35.398381 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4334 14:48:35.401949 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4335 14:48:35.402053
4336 14:48:35.402145
4337 14:48:35.411902 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4338 14:48:35.415182 CH0 RK1: MR19=808, MR18=6D3C
4339 14:48:35.421553 CH0_RK1: MR19=0x808, MR18=0x6D3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4340 14:48:35.421658 [RxdqsGatingPostProcess] freq 600
4341 14:48:35.428604 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4342 14:48:35.431897 Pre-setting of DQS Precalculation
4343 14:48:35.435010 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4344 14:48:35.438303 ==
4345 14:48:35.438402 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 14:48:35.444916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 14:48:35.444990 ==
4348 14:48:35.448580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 14:48:35.455251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4350 14:48:35.458733 [CA 0] Center 35 (5~66) winsize 62
4351 14:48:35.461899 [CA 1] Center 35 (5~66) winsize 62
4352 14:48:35.465293 [CA 2] Center 34 (4~65) winsize 62
4353 14:48:35.468282 [CA 3] Center 34 (4~65) winsize 62
4354 14:48:35.471761 [CA 4] Center 34 (4~65) winsize 62
4355 14:48:35.475007 [CA 5] Center 33 (3~64) winsize 62
4356 14:48:35.475079
4357 14:48:35.478423 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4358 14:48:35.478492
4359 14:48:35.481677 [CATrainingPosCal] consider 1 rank data
4360 14:48:35.484840 u2DelayCellTimex100 = 270/100 ps
4361 14:48:35.488367 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 14:48:35.494715 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 14:48:35.498305 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 14:48:35.501454 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 14:48:35.504898 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4366 14:48:35.508104 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4367 14:48:35.508244
4368 14:48:35.511499 CA PerBit enable=1, Macro0, CA PI delay=33
4369 14:48:35.511613
4370 14:48:35.514876 [CBTSetCACLKResult] CA Dly = 33
4371 14:48:35.518082 CS Dly: 5 (0~36)
4372 14:48:35.518184 ==
4373 14:48:35.521404 Dram Type= 6, Freq= 0, CH_1, rank 1
4374 14:48:35.524499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 14:48:35.524627 ==
4376 14:48:35.531442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 14:48:35.534614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4378 14:48:35.538907 [CA 0] Center 36 (6~66) winsize 61
4379 14:48:35.542379 [CA 1] Center 36 (5~67) winsize 63
4380 14:48:35.545617 [CA 2] Center 34 (4~65) winsize 62
4381 14:48:35.548590 [CA 3] Center 34 (3~65) winsize 63
4382 14:48:35.552057 [CA 4] Center 34 (4~65) winsize 62
4383 14:48:35.555484 [CA 5] Center 33 (3~64) winsize 62
4384 14:48:35.555602
4385 14:48:35.558701 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4386 14:48:35.558836
4387 14:48:35.562312 [CATrainingPosCal] consider 2 rank data
4388 14:48:35.565170 u2DelayCellTimex100 = 270/100 ps
4389 14:48:35.568901 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4390 14:48:35.575342 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4391 14:48:35.578532 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 14:48:35.581862 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 14:48:35.585243 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 14:48:35.588493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 14:48:35.588604
4396 14:48:35.591930 CA PerBit enable=1, Macro0, CA PI delay=33
4397 14:48:35.592038
4398 14:48:35.595227 [CBTSetCACLKResult] CA Dly = 33
4399 14:48:35.595338 CS Dly: 5 (0~36)
4400 14:48:35.598596
4401 14:48:35.601859 ----->DramcWriteLeveling(PI) begin...
4402 14:48:35.601947 ==
4403 14:48:35.605236 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 14:48:35.608452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 14:48:35.608536 ==
4406 14:48:35.611570 Write leveling (Byte 0): 31 => 31
4407 14:48:35.615131 Write leveling (Byte 1): 32 => 32
4408 14:48:35.618198 DramcWriteLeveling(PI) end<-----
4409 14:48:35.618281
4410 14:48:35.618365 ==
4411 14:48:35.621631 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 14:48:35.624866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 14:48:35.624950 ==
4414 14:48:35.628272 [Gating] SW mode calibration
4415 14:48:35.635090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 14:48:35.641538 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4417 14:48:35.645260 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 14:48:35.648673 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 14:48:35.655096 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 14:48:35.658575 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
4421 14:48:35.661785 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
4422 14:48:35.668339 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 14:48:35.671477 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 14:48:35.674647 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 14:48:35.678086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 14:48:35.684810 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 14:48:35.688237 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 14:48:35.691421 0 10 12 | B1->B0 | 2e2e 3131 | 1 0 | (0 0) (0 0)
4429 14:48:35.698093 0 10 16 | B1->B0 | 4343 4040 | 0 0 | (0 0) (1 1)
4430 14:48:35.701287 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 14:48:35.704538 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 14:48:35.711437 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 14:48:35.714670 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 14:48:35.717704 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 14:48:35.724542 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 14:48:35.728233 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4437 14:48:35.731297 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4438 14:48:35.738024 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 14:48:35.740764 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 14:48:35.744203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 14:48:35.751211 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 14:48:35.754165 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 14:48:35.757473 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 14:48:35.763984 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 14:48:35.767250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 14:48:35.770794 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 14:48:35.777416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 14:48:35.780723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 14:48:35.784143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 14:48:35.790599 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 14:48:35.793979 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 14:48:35.797201 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 14:48:35.803959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 14:48:35.804071 Total UI for P1: 0, mck2ui 16
4455 14:48:35.810575 best dqsien dly found for B0: ( 0, 13, 14)
4456 14:48:35.810675 Total UI for P1: 0, mck2ui 16
4457 14:48:35.817445 best dqsien dly found for B1: ( 0, 13, 14)
4458 14:48:35.820430 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4459 14:48:35.823902 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4460 14:48:35.824003
4461 14:48:35.826833 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4462 14:48:35.830294 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4463 14:48:35.833706 [Gating] SW calibration Done
4464 14:48:35.833787 ==
4465 14:48:35.836802 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 14:48:35.840174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 14:48:35.840256 ==
4468 14:48:35.843375 RX Vref Scan: 0
4469 14:48:35.843494
4470 14:48:35.843623 RX Vref 0 -> 0, step: 1
4471 14:48:35.846699
4472 14:48:35.846812 RX Delay -230 -> 252, step: 16
4473 14:48:35.853581 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4474 14:48:35.857117 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4475 14:48:35.860087 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4476 14:48:35.863444 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4477 14:48:35.866673 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4478 14:48:35.873447 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4479 14:48:35.876711 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4480 14:48:35.880216 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4481 14:48:35.883182 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4482 14:48:35.889867 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4483 14:48:35.893263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4484 14:48:35.896506 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4485 14:48:35.899685 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4486 14:48:35.906242 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4487 14:48:35.909624 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4488 14:48:35.913127 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4489 14:48:35.913235 ==
4490 14:48:35.916362 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 14:48:35.919516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 14:48:35.922959 ==
4493 14:48:35.923062 DQS Delay:
4494 14:48:35.923157 DQS0 = 0, DQS1 = 0
4495 14:48:35.926021 DQM Delay:
4496 14:48:35.926129 DQM0 = 36, DQM1 = 29
4497 14:48:35.929655 DQ Delay:
4498 14:48:35.929755 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4499 14:48:35.932695 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4500 14:48:35.936542 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4501 14:48:35.939696 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4502 14:48:35.939796
4503 14:48:35.942754
4504 14:48:35.942852 ==
4505 14:48:35.946085 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 14:48:35.949493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 14:48:35.949596 ==
4508 14:48:35.949693
4509 14:48:35.949794
4510 14:48:35.952795 TX Vref Scan disable
4511 14:48:35.952898 == TX Byte 0 ==
4512 14:48:35.959542 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4513 14:48:35.962747 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4514 14:48:35.962842 == TX Byte 1 ==
4515 14:48:35.969292 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4516 14:48:35.972592 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4517 14:48:35.972682 ==
4518 14:48:35.976001 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 14:48:35.979241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 14:48:35.979325 ==
4521 14:48:35.979409
4522 14:48:35.979488
4523 14:48:35.982610 TX Vref Scan disable
4524 14:48:35.985955 == TX Byte 0 ==
4525 14:48:35.989344 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4526 14:48:35.992408 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4527 14:48:35.996076 == TX Byte 1 ==
4528 14:48:35.998961 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4529 14:48:36.002697 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4530 14:48:36.005984
4531 14:48:36.006072 [DATLAT]
4532 14:48:36.006158 Freq=600, CH1 RK0
4533 14:48:36.006256
4534 14:48:36.008782 DATLAT Default: 0x9
4535 14:48:36.008858 0, 0xFFFF, sum = 0
4536 14:48:36.012202 1, 0xFFFF, sum = 0
4537 14:48:36.012278 2, 0xFFFF, sum = 0
4538 14:48:36.015575 3, 0xFFFF, sum = 0
4539 14:48:36.015651 4, 0xFFFF, sum = 0
4540 14:48:36.018997 5, 0xFFFF, sum = 0
4541 14:48:36.019076 6, 0xFFFF, sum = 0
4542 14:48:36.022288 7, 0xFFFF, sum = 0
4543 14:48:36.022397 8, 0x0, sum = 1
4544 14:48:36.025409 9, 0x0, sum = 2
4545 14:48:36.025515 10, 0x0, sum = 3
4546 14:48:36.029088 11, 0x0, sum = 4
4547 14:48:36.029188 best_step = 9
4548 14:48:36.029295
4549 14:48:36.029387 ==
4550 14:48:36.032300 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 14:48:36.039077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 14:48:36.039163 ==
4553 14:48:36.039247 RX Vref Scan: 1
4554 14:48:36.039352
4555 14:48:36.042264 RX Vref 0 -> 0, step: 1
4556 14:48:36.042365
4557 14:48:36.045644 RX Delay -195 -> 252, step: 8
4558 14:48:36.045746
4559 14:48:36.048830 Set Vref, RX VrefLevel [Byte0]: 59
4560 14:48:36.052284 [Byte1]: 54
4561 14:48:36.052381
4562 14:48:36.055383 Final RX Vref Byte 0 = 59 to rank0
4563 14:48:36.058528 Final RX Vref Byte 1 = 54 to rank0
4564 14:48:36.061923 Final RX Vref Byte 0 = 59 to rank1
4565 14:48:36.065205 Final RX Vref Byte 1 = 54 to rank1==
4566 14:48:36.069171 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 14:48:36.071901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 14:48:36.072013 ==
4569 14:48:36.075560 DQS Delay:
4570 14:48:36.075661 DQS0 = 0, DQS1 = 0
4571 14:48:36.078342 DQM Delay:
4572 14:48:36.078448 DQM0 = 39, DQM1 = 28
4573 14:48:36.078545 DQ Delay:
4574 14:48:36.081895 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4575 14:48:36.085364 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4576 14:48:36.088596 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4577 14:48:36.092034 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4578 14:48:36.092121
4579 14:48:36.092215
4580 14:48:36.102182 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4581 14:48:36.104837 CH1 RK0: MR19=808, MR18=2330
4582 14:48:36.111347 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4583 14:48:36.111488
4584 14:48:36.114785 ----->DramcWriteLeveling(PI) begin...
4585 14:48:36.114939 ==
4586 14:48:36.118197 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 14:48:36.121532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 14:48:36.121652 ==
4589 14:48:36.124788 Write leveling (Byte 0): 28 => 28
4590 14:48:36.128095 Write leveling (Byte 1): 29 => 29
4591 14:48:36.131264 DramcWriteLeveling(PI) end<-----
4592 14:48:36.131399
4593 14:48:36.131514 ==
4594 14:48:36.134912 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 14:48:36.138235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 14:48:36.138321 ==
4597 14:48:36.141237 [Gating] SW mode calibration
4598 14:48:36.147836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 14:48:36.154328 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 14:48:36.157752 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 14:48:36.161391 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 14:48:36.168071 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4603 14:48:36.171307 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4604 14:48:36.174296 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4605 14:48:36.181114 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 14:48:36.184293 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 14:48:36.187322 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 14:48:36.194068 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 14:48:36.197506 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 14:48:36.200416 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4611 14:48:36.207330 0 10 12 | B1->B0 | 3333 4040 | 0 1 | (0 0) (0 0)
4612 14:48:36.211059 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4613 14:48:36.214021 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 14:48:36.220651 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 14:48:36.224026 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 14:48:36.227278 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 14:48:36.233659 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 14:48:36.237495 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 14:48:36.240277 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4620 14:48:36.246951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 14:48:36.250152 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 14:48:36.253572 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 14:48:36.260273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 14:48:36.263528 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 14:48:36.266917 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 14:48:36.273479 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 14:48:36.276793 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 14:48:36.280285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 14:48:36.286488 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 14:48:36.289801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 14:48:36.293041 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 14:48:36.299935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 14:48:36.303177 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 14:48:36.306284 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 14:48:36.312903 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4636 14:48:36.316392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 14:48:36.319473 Total UI for P1: 0, mck2ui 16
4638 14:48:36.323394 best dqsien dly found for B0: ( 0, 13, 12)
4639 14:48:36.326548 Total UI for P1: 0, mck2ui 16
4640 14:48:36.329560 best dqsien dly found for B1: ( 0, 13, 12)
4641 14:48:36.332920 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4642 14:48:36.336246 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4643 14:48:36.336346
4644 14:48:36.339210 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 14:48:36.343022 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4646 14:48:36.346362 [Gating] SW calibration Done
4647 14:48:36.346439 ==
4648 14:48:36.349157 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 14:48:36.352649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 14:48:36.356060 ==
4651 14:48:36.356136 RX Vref Scan: 0
4652 14:48:36.356198
4653 14:48:36.359226 RX Vref 0 -> 0, step: 1
4654 14:48:36.359298
4655 14:48:36.362834 RX Delay -230 -> 252, step: 16
4656 14:48:36.366212 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4657 14:48:36.369566 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4658 14:48:36.372708 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4659 14:48:36.379486 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4660 14:48:36.382865 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4661 14:48:36.386105 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4662 14:48:36.389334 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4663 14:48:36.392450 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4664 14:48:36.398961 iDelay=218, Bit 8, Center 9 (-166 ~ 185) 352
4665 14:48:36.402231 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4666 14:48:36.405811 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4667 14:48:36.408942 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4668 14:48:36.415537 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4669 14:48:36.419011 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4670 14:48:36.422261 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4671 14:48:36.425700 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4672 14:48:36.425779 ==
4673 14:48:36.428511 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 14:48:36.435626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 14:48:36.435733 ==
4676 14:48:36.435801 DQS Delay:
4677 14:48:36.438971 DQS0 = 0, DQS1 = 0
4678 14:48:36.439096 DQM Delay:
4679 14:48:36.442029 DQM0 = 37, DQM1 = 30
4680 14:48:36.442153 DQ Delay:
4681 14:48:36.445508 DQ0 =49, DQ1 =33, DQ2 =17, DQ3 =33
4682 14:48:36.448993 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4683 14:48:36.452113 DQ8 =9, DQ9 =17, DQ10 =33, DQ11 =25
4684 14:48:36.455116 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4685 14:48:36.455237
4686 14:48:36.455351
4687 14:48:36.455454 ==
4688 14:48:36.458685 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 14:48:36.462113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 14:48:36.462241 ==
4691 14:48:36.462351
4692 14:48:36.462455
4693 14:48:36.465076 TX Vref Scan disable
4694 14:48:36.468240 == TX Byte 0 ==
4695 14:48:36.471456 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 14:48:36.474745 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 14:48:36.478043 == TX Byte 1 ==
4698 14:48:36.481418 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 14:48:36.484690 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 14:48:36.484772 ==
4701 14:48:36.487955 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 14:48:36.494958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 14:48:36.495065 ==
4704 14:48:36.495156
4705 14:48:36.495243
4706 14:48:36.495330 TX Vref Scan disable
4707 14:48:36.498918 == TX Byte 0 ==
4708 14:48:36.502173 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4709 14:48:36.509071 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4710 14:48:36.509173 == TX Byte 1 ==
4711 14:48:36.512159 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 14:48:36.518670 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 14:48:36.518773
4714 14:48:36.518862 [DATLAT]
4715 14:48:36.518946 Freq=600, CH1 RK1
4716 14:48:36.519005
4717 14:48:36.521912 DATLAT Default: 0x9
4718 14:48:36.522028 0, 0xFFFF, sum = 0
4719 14:48:36.525292 1, 0xFFFF, sum = 0
4720 14:48:36.525394 2, 0xFFFF, sum = 0
4721 14:48:36.528468 3, 0xFFFF, sum = 0
4722 14:48:36.531821 4, 0xFFFF, sum = 0
4723 14:48:36.531935 5, 0xFFFF, sum = 0
4724 14:48:36.535306 6, 0xFFFF, sum = 0
4725 14:48:36.535412 7, 0xFFFF, sum = 0
4726 14:48:36.538771 8, 0x0, sum = 1
4727 14:48:36.538847 9, 0x0, sum = 2
4728 14:48:36.538913 10, 0x0, sum = 3
4729 14:48:36.541985 11, 0x0, sum = 4
4730 14:48:36.542057 best_step = 9
4731 14:48:36.542116
4732 14:48:36.542180 ==
4733 14:48:36.545615 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 14:48:36.552225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 14:48:36.552335 ==
4736 14:48:36.552461 RX Vref Scan: 0
4737 14:48:36.552550
4738 14:48:36.555213 RX Vref 0 -> 0, step: 1
4739 14:48:36.555315
4740 14:48:36.558352 RX Delay -211 -> 252, step: 8
4741 14:48:36.564979 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4742 14:48:36.568218 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4743 14:48:36.571772 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4744 14:48:36.574851 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4745 14:48:36.578335 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4746 14:48:36.584809 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4747 14:48:36.588122 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4748 14:48:36.592227 iDelay=205, Bit 7, Center 32 (-131 ~ 196) 328
4749 14:48:36.595169 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4750 14:48:36.598541 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4751 14:48:36.605118 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4752 14:48:36.608535 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4753 14:48:36.611409 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4754 14:48:36.614758 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4755 14:48:36.621331 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4756 14:48:36.624898 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4757 14:48:36.624979 ==
4758 14:48:36.628174 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 14:48:36.631354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 14:48:36.631466 ==
4761 14:48:36.634752 DQS Delay:
4762 14:48:36.634853 DQS0 = 0, DQS1 = 0
4763 14:48:36.638007 DQM Delay:
4764 14:48:36.638112 DQM0 = 36, DQM1 = 29
4765 14:48:36.638208 DQ Delay:
4766 14:48:36.641330 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4767 14:48:36.644773 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4768 14:48:36.648172 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4769 14:48:36.651159 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4770 14:48:36.651260
4771 14:48:36.651350
4772 14:48:36.661179 [DQSOSCAuto] RK1, (LSB)MR18= 0x3555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4773 14:48:36.664113 CH1 RK1: MR19=808, MR18=3555
4774 14:48:36.670953 CH1_RK1: MR19=0x808, MR18=0x3555, DQSOSC=393, MR23=63, INC=169, DEC=113
4775 14:48:36.671061 [RxdqsGatingPostProcess] freq 600
4776 14:48:36.677497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 14:48:36.681219 Pre-setting of DQS Precalculation
4778 14:48:36.684453 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 14:48:36.694118 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 14:48:36.701174 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 14:48:36.701262
4782 14:48:36.701327
4783 14:48:36.703911 [Calibration Summary] 1200 Mbps
4784 14:48:36.703987 CH 0, Rank 0
4785 14:48:36.707338 SW Impedance : PASS
4786 14:48:36.707416 DUTY Scan : NO K
4787 14:48:36.710740 ZQ Calibration : PASS
4788 14:48:36.714500 Jitter Meter : NO K
4789 14:48:36.714580 CBT Training : PASS
4790 14:48:36.717387 Write leveling : PASS
4791 14:48:36.720649 RX DQS gating : PASS
4792 14:48:36.720727 RX DQ/DQS(RDDQC) : PASS
4793 14:48:36.724083 TX DQ/DQS : PASS
4794 14:48:36.727428 RX DATLAT : PASS
4795 14:48:36.727503 RX DQ/DQS(Engine): PASS
4796 14:48:36.730928 TX OE : NO K
4797 14:48:36.731030 All Pass.
4798 14:48:36.731120
4799 14:48:36.733955 CH 0, Rank 1
4800 14:48:36.734056 SW Impedance : PASS
4801 14:48:36.737575 DUTY Scan : NO K
4802 14:48:36.740730 ZQ Calibration : PASS
4803 14:48:36.740806 Jitter Meter : NO K
4804 14:48:36.744092 CBT Training : PASS
4805 14:48:36.747249 Write leveling : PASS
4806 14:48:36.747331 RX DQS gating : PASS
4807 14:48:36.750717 RX DQ/DQS(RDDQC) : PASS
4808 14:48:36.750803 TX DQ/DQS : PASS
4809 14:48:36.753961 RX DATLAT : PASS
4810 14:48:36.757168 RX DQ/DQS(Engine): PASS
4811 14:48:36.757243 TX OE : NO K
4812 14:48:36.760585 All Pass.
4813 14:48:36.760687
4814 14:48:36.760789 CH 1, Rank 0
4815 14:48:36.763777 SW Impedance : PASS
4816 14:48:36.763886 DUTY Scan : NO K
4817 14:48:36.767038 ZQ Calibration : PASS
4818 14:48:36.770465 Jitter Meter : NO K
4819 14:48:36.770570 CBT Training : PASS
4820 14:48:36.773656 Write leveling : PASS
4821 14:48:36.777363 RX DQS gating : PASS
4822 14:48:36.777482 RX DQ/DQS(RDDQC) : PASS
4823 14:48:36.780365 TX DQ/DQS : PASS
4824 14:48:36.783555 RX DATLAT : PASS
4825 14:48:36.783662 RX DQ/DQS(Engine): PASS
4826 14:48:36.786853 TX OE : NO K
4827 14:48:36.786963 All Pass.
4828 14:48:36.787054
4829 14:48:36.790168 CH 1, Rank 1
4830 14:48:36.790269 SW Impedance : PASS
4831 14:48:36.793343 DUTY Scan : NO K
4832 14:48:36.796887 ZQ Calibration : PASS
4833 14:48:36.796964 Jitter Meter : NO K
4834 14:48:36.800304 CBT Training : PASS
4835 14:48:36.803637 Write leveling : PASS
4836 14:48:36.803713 RX DQS gating : PASS
4837 14:48:36.807682 RX DQ/DQS(RDDQC) : PASS
4838 14:48:36.807788 TX DQ/DQS : PASS
4839 14:48:36.810400 RX DATLAT : PASS
4840 14:48:36.813290 RX DQ/DQS(Engine): PASS
4841 14:48:36.813395 TX OE : NO K
4842 14:48:36.816599 All Pass.
4843 14:48:36.816679
4844 14:48:36.816742 DramC Write-DBI off
4845 14:48:36.819969 PER_BANK_REFRESH: Hybrid Mode
4846 14:48:36.823414 TX_TRACKING: ON
4847 14:48:36.829876 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 14:48:36.833234 [FAST_K] Save calibration result to emmc
4849 14:48:36.839860 dramc_set_vcore_voltage set vcore to 662500
4850 14:48:36.839942 Read voltage for 933, 3
4851 14:48:36.840006 Vio18 = 0
4852 14:48:36.843281 Vcore = 662500
4853 14:48:36.843379 Vdram = 0
4854 14:48:36.843471 Vddq = 0
4855 14:48:36.846336 Vmddr = 0
4856 14:48:36.849915 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 14:48:36.856087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 14:48:36.859371 MEM_TYPE=3, freq_sel=17
4859 14:48:36.859475 sv_algorithm_assistance_LP4_1600
4860 14:48:36.866387 ============ PULL DRAM RESETB DOWN ============
4861 14:48:36.869713 ========== PULL DRAM RESETB DOWN end =========
4862 14:48:36.872731 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 14:48:36.876483 ===================================
4864 14:48:36.879443 LPDDR4 DRAM CONFIGURATION
4865 14:48:36.882484 ===================================
4866 14:48:36.886045 EX_ROW_EN[0] = 0x0
4867 14:48:36.886148 EX_ROW_EN[1] = 0x0
4868 14:48:36.889359 LP4Y_EN = 0x0
4869 14:48:36.889435 WORK_FSP = 0x0
4870 14:48:36.892682 WL = 0x3
4871 14:48:36.892756 RL = 0x3
4872 14:48:36.895839 BL = 0x2
4873 14:48:36.895937 RPST = 0x0
4874 14:48:36.899154 RD_PRE = 0x0
4875 14:48:36.899229 WR_PRE = 0x1
4876 14:48:36.902432 WR_PST = 0x0
4877 14:48:36.905736 DBI_WR = 0x0
4878 14:48:36.905868 DBI_RD = 0x0
4879 14:48:36.908927 OTF = 0x1
4880 14:48:36.912194 ===================================
4881 14:48:36.915502 ===================================
4882 14:48:36.915604 ANA top config
4883 14:48:36.919039 ===================================
4884 14:48:36.922309 DLL_ASYNC_EN = 0
4885 14:48:36.925722 ALL_SLAVE_EN = 1
4886 14:48:36.925814 NEW_RANK_MODE = 1
4887 14:48:36.929255 DLL_IDLE_MODE = 1
4888 14:48:36.932535 LP45_APHY_COMB_EN = 1
4889 14:48:36.935789 TX_ODT_DIS = 1
4890 14:48:36.935907 NEW_8X_MODE = 1
4891 14:48:36.939206 ===================================
4892 14:48:36.942049 ===================================
4893 14:48:36.945523 data_rate = 1866
4894 14:48:36.948647 CKR = 1
4895 14:48:36.952037 DQ_P2S_RATIO = 8
4896 14:48:36.955129 ===================================
4897 14:48:36.958849 CA_P2S_RATIO = 8
4898 14:48:36.962156 DQ_CA_OPEN = 0
4899 14:48:36.965335 DQ_SEMI_OPEN = 0
4900 14:48:36.965452 CA_SEMI_OPEN = 0
4901 14:48:36.968476 CA_FULL_RATE = 0
4902 14:48:36.971619 DQ_CKDIV4_EN = 1
4903 14:48:36.975447 CA_CKDIV4_EN = 1
4904 14:48:36.978362 CA_PREDIV_EN = 0
4905 14:48:36.981578 PH8_DLY = 0
4906 14:48:36.981694 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 14:48:36.984790 DQ_AAMCK_DIV = 4
4908 14:48:36.988216 CA_AAMCK_DIV = 4
4909 14:48:36.991391 CA_ADMCK_DIV = 4
4910 14:48:36.995082 DQ_TRACK_CA_EN = 0
4911 14:48:36.998107 CA_PICK = 933
4912 14:48:36.998212 CA_MCKIO = 933
4913 14:48:37.001508 MCKIO_SEMI = 0
4914 14:48:37.004790 PLL_FREQ = 3732
4915 14:48:37.008407 DQ_UI_PI_RATIO = 32
4916 14:48:37.011503 CA_UI_PI_RATIO = 0
4917 14:48:37.014332 ===================================
4918 14:48:37.017926 ===================================
4919 14:48:37.021217 memory_type:LPDDR4
4920 14:48:37.021317 GP_NUM : 10
4921 14:48:37.024310 SRAM_EN : 1
4922 14:48:37.027607 MD32_EN : 0
4923 14:48:37.031338 ===================================
4924 14:48:37.031438 [ANA_INIT] >>>>>>>>>>>>>>
4925 14:48:37.035070 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 14:48:37.038003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 14:48:37.040985 ===================================
4928 14:48:37.044172 data_rate = 1866,PCW = 0X8f00
4929 14:48:37.047621 ===================================
4930 14:48:37.050854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 14:48:37.057343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 14:48:37.060834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 14:48:37.067498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 14:48:37.070969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 14:48:37.074088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 14:48:37.074220 [ANA_INIT] flow start
4937 14:48:37.077332 [ANA_INIT] PLL >>>>>>>>
4938 14:48:37.080707 [ANA_INIT] PLL <<<<<<<<
4939 14:48:37.083885 [ANA_INIT] MIDPI >>>>>>>>
4940 14:48:37.084009 [ANA_INIT] MIDPI <<<<<<<<
4941 14:48:37.087136 [ANA_INIT] DLL >>>>>>>>
4942 14:48:37.090325 [ANA_INIT] flow end
4943 14:48:37.094080 ============ LP4 DIFF to SE enter ============
4944 14:48:37.097239 ============ LP4 DIFF to SE exit ============
4945 14:48:37.100324 [ANA_INIT] <<<<<<<<<<<<<
4946 14:48:37.103737 [Flow] Enable top DCM control >>>>>
4947 14:48:37.107029 [Flow] Enable top DCM control <<<<<
4948 14:48:37.110292 Enable DLL master slave shuffle
4949 14:48:37.113597 ==============================================================
4950 14:48:37.116964 Gating Mode config
4951 14:48:37.123673 ==============================================================
4952 14:48:37.123755 Config description:
4953 14:48:37.133606 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 14:48:37.140088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 14:48:37.143947 SELPH_MODE 0: By rank 1: By Phase
4956 14:48:37.150090 ==============================================================
4957 14:48:37.153421 GAT_TRACK_EN = 1
4958 14:48:37.156827 RX_GATING_MODE = 2
4959 14:48:37.160165 RX_GATING_TRACK_MODE = 2
4960 14:48:37.163657 SELPH_MODE = 1
4961 14:48:37.166783 PICG_EARLY_EN = 1
4962 14:48:37.170200 VALID_LAT_VALUE = 1
4963 14:48:37.173542 ==============================================================
4964 14:48:37.176942 Enter into Gating configuration >>>>
4965 14:48:37.179704 Exit from Gating configuration <<<<
4966 14:48:37.182992 Enter into DVFS_PRE_config >>>>>
4967 14:48:37.196332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 14:48:37.196419 Exit from DVFS_PRE_config <<<<<
4969 14:48:37.199923 Enter into PICG configuration >>>>
4970 14:48:37.202822 Exit from PICG configuration <<<<
4971 14:48:37.206578 [RX_INPUT] configuration >>>>>
4972 14:48:37.209391 [RX_INPUT] configuration <<<<<
4973 14:48:37.216159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 14:48:37.219773 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 14:48:37.226107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 14:48:37.232778 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 14:48:37.239185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 14:48:37.245975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 14:48:37.248841 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 14:48:37.252540 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 14:48:37.258913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 14:48:37.262204 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 14:48:37.265573 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 14:48:37.269019 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 14:48:37.272270 ===================================
4986 14:48:37.275484 LPDDR4 DRAM CONFIGURATION
4987 14:48:37.278866 ===================================
4988 14:48:37.282253 EX_ROW_EN[0] = 0x0
4989 14:48:37.282376 EX_ROW_EN[1] = 0x0
4990 14:48:37.285660 LP4Y_EN = 0x0
4991 14:48:37.285763 WORK_FSP = 0x0
4992 14:48:37.288502 WL = 0x3
4993 14:48:37.288603 RL = 0x3
4994 14:48:37.291852 BL = 0x2
4995 14:48:37.291959 RPST = 0x0
4996 14:48:37.295129 RD_PRE = 0x0
4997 14:48:37.295230 WR_PRE = 0x1
4998 14:48:37.298854 WR_PST = 0x0
4999 14:48:37.298935 DBI_WR = 0x0
5000 14:48:37.301816 DBI_RD = 0x0
5001 14:48:37.305253 OTF = 0x1
5002 14:48:37.308192 ===================================
5003 14:48:37.311749 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 14:48:37.314796 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 14:48:37.318605 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 14:48:37.321789 ===================================
5007 14:48:37.325170 LPDDR4 DRAM CONFIGURATION
5008 14:48:37.328018 ===================================
5009 14:48:37.331305 EX_ROW_EN[0] = 0x10
5010 14:48:37.331430 EX_ROW_EN[1] = 0x0
5011 14:48:37.334911 LP4Y_EN = 0x0
5012 14:48:37.335034 WORK_FSP = 0x0
5013 14:48:37.337962 WL = 0x3
5014 14:48:37.338043 RL = 0x3
5015 14:48:37.341470 BL = 0x2
5016 14:48:37.341551 RPST = 0x0
5017 14:48:37.344896 RD_PRE = 0x0
5018 14:48:37.348154 WR_PRE = 0x1
5019 14:48:37.348236 WR_PST = 0x0
5020 14:48:37.351460 DBI_WR = 0x0
5021 14:48:37.351567 DBI_RD = 0x0
5022 14:48:37.354250 OTF = 0x1
5023 14:48:37.357619 ===================================
5024 14:48:37.360854 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 14:48:37.366375 nWR fixed to 30
5026 14:48:37.369966 [ModeRegInit_LP4] CH0 RK0
5027 14:48:37.370056 [ModeRegInit_LP4] CH0 RK1
5028 14:48:37.373109 [ModeRegInit_LP4] CH1 RK0
5029 14:48:37.376422 [ModeRegInit_LP4] CH1 RK1
5030 14:48:37.376529 match AC timing 9
5031 14:48:37.383003 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 14:48:37.386417 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 14:48:37.389644 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 14:48:37.396284 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 14:48:37.399597 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 14:48:37.399721 ==
5037 14:48:37.403012 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 14:48:37.406091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 14:48:37.406213 ==
5040 14:48:37.412808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 14:48:37.419322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5042 14:48:37.422352 [CA 0] Center 38 (8~69) winsize 62
5043 14:48:37.425968 [CA 1] Center 38 (7~69) winsize 63
5044 14:48:37.429417 [CA 2] Center 35 (5~66) winsize 62
5045 14:48:37.432484 [CA 3] Center 35 (4~66) winsize 63
5046 14:48:37.435876 [CA 4] Center 34 (4~65) winsize 62
5047 14:48:37.439073 [CA 5] Center 33 (3~64) winsize 62
5048 14:48:37.439155
5049 14:48:37.442196 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5050 14:48:37.442303
5051 14:48:37.445666 [CATrainingPosCal] consider 1 rank data
5052 14:48:37.449194 u2DelayCellTimex100 = 270/100 ps
5053 14:48:37.452158 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5054 14:48:37.455701 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5055 14:48:37.458756 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5056 14:48:37.465324 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5057 14:48:37.468566 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5058 14:48:37.472452 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5059 14:48:37.472569
5060 14:48:37.475305 CA PerBit enable=1, Macro0, CA PI delay=33
5061 14:48:37.475394
5062 14:48:37.478668 [CBTSetCACLKResult] CA Dly = 33
5063 14:48:37.478755 CS Dly: 7 (0~38)
5064 14:48:37.478827 ==
5065 14:48:37.482161 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 14:48:37.488759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 14:48:37.488866 ==
5068 14:48:37.491941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 14:48:37.498743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5070 14:48:37.502117 [CA 0] Center 38 (8~69) winsize 62
5071 14:48:37.505452 [CA 1] Center 38 (8~69) winsize 62
5072 14:48:37.508729 [CA 2] Center 35 (5~66) winsize 62
5073 14:48:37.511888 [CA 3] Center 35 (5~66) winsize 62
5074 14:48:37.515250 [CA 4] Center 34 (4~65) winsize 62
5075 14:48:37.518400 [CA 5] Center 33 (3~64) winsize 62
5076 14:48:37.518481
5077 14:48:37.521881 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5078 14:48:37.521962
5079 14:48:37.524809 [CATrainingPosCal] consider 2 rank data
5080 14:48:37.528532 u2DelayCellTimex100 = 270/100 ps
5081 14:48:37.531940 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5082 14:48:37.535267 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5083 14:48:37.541382 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5084 14:48:37.545051 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5085 14:48:37.547999 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5086 14:48:37.551488 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5087 14:48:37.551596
5088 14:48:37.554601 CA PerBit enable=1, Macro0, CA PI delay=33
5089 14:48:37.554682
5090 14:48:37.558361 [CBTSetCACLKResult] CA Dly = 33
5091 14:48:37.558447 CS Dly: 7 (0~38)
5092 14:48:37.561394
5093 14:48:37.564714 ----->DramcWriteLeveling(PI) begin...
5094 14:48:37.564797 ==
5095 14:48:37.568641 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 14:48:37.571497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 14:48:37.571579 ==
5098 14:48:37.574505 Write leveling (Byte 0): 34 => 34
5099 14:48:37.577953 Write leveling (Byte 1): 28 => 28
5100 14:48:37.581375 DramcWriteLeveling(PI) end<-----
5101 14:48:37.581478
5102 14:48:37.581574 ==
5103 14:48:37.584877 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 14:48:37.587590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 14:48:37.587678 ==
5106 14:48:37.591466 [Gating] SW mode calibration
5107 14:48:37.597836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 14:48:37.604321 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 14:48:37.608082 0 14 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
5110 14:48:37.611234 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5111 14:48:37.617811 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 14:48:37.620938 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 14:48:37.624329 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 14:48:37.631044 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 14:48:37.633930 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 14:48:37.637851 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5117 14:48:37.643969 0 15 0 | B1->B0 | 3333 2b2b | 1 1 | (1 1) (1 0)
5118 14:48:37.647338 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 14:48:37.650560 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 14:48:37.657357 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 14:48:37.660679 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 14:48:37.664024 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 14:48:37.670405 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 14:48:37.673857 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 14:48:37.677083 1 0 0 | B1->B0 | 2a2a 3d3c | 0 1 | (0 0) (0 0)
5126 14:48:37.683607 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5127 14:48:37.687314 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 14:48:37.690318 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 14:48:37.697081 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 14:48:37.700169 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 14:48:37.703774 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 14:48:37.710745 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 14:48:37.713562 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 14:48:37.716759 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 14:48:37.723406 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 14:48:37.726689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 14:48:37.730462 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 14:48:37.736682 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 14:48:37.740474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 14:48:37.743302 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 14:48:37.746615 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 14:48:37.753419 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 14:48:37.756540 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 14:48:37.759746 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 14:48:37.766557 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 14:48:37.769608 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 14:48:37.773454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 14:48:37.779815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5149 14:48:37.783094 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5150 14:48:37.786330 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 14:48:37.789710 Total UI for P1: 0, mck2ui 16
5152 14:48:37.793119 best dqsien dly found for B0: ( 1, 2, 30)
5153 14:48:37.796427 Total UI for P1: 0, mck2ui 16
5154 14:48:37.799747 best dqsien dly found for B1: ( 1, 3, 2)
5155 14:48:37.802896 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5156 14:48:37.806298 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5157 14:48:37.809476
5158 14:48:37.812607 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5159 14:48:37.816205 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5160 14:48:37.819234 [Gating] SW calibration Done
5161 14:48:37.819335 ==
5162 14:48:37.822860 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 14:48:37.826081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 14:48:37.826157 ==
5165 14:48:37.826224 RX Vref Scan: 0
5166 14:48:37.829283
5167 14:48:37.829355 RX Vref 0 -> 0, step: 1
5168 14:48:37.829416
5169 14:48:37.832381 RX Delay -80 -> 252, step: 8
5170 14:48:37.835885 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5171 14:48:37.839241 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5172 14:48:37.846305 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5173 14:48:37.849392 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5174 14:48:37.852810 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5175 14:48:37.856007 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5176 14:48:37.859519 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5177 14:48:37.862845 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5178 14:48:37.869470 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5179 14:48:37.872524 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5180 14:48:37.875859 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5181 14:48:37.878964 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5182 14:48:37.882336 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5183 14:48:37.888982 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5184 14:48:37.892452 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5185 14:48:37.895772 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5186 14:48:37.895848 ==
5187 14:48:37.899202 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 14:48:37.902428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 14:48:37.905726 ==
5190 14:48:37.905798 DQS Delay:
5191 14:48:37.905858 DQS0 = 0, DQS1 = 0
5192 14:48:37.909112 DQM Delay:
5193 14:48:37.909182 DQM0 = 94, DQM1 = 82
5194 14:48:37.909252 DQ Delay:
5195 14:48:37.912774 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5196 14:48:37.915210 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5197 14:48:37.918752 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5198 14:48:37.921932 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5199 14:48:37.924908
5200 14:48:37.924990
5201 14:48:37.925053 ==
5202 14:48:37.928485 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 14:48:37.931690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 14:48:37.931797 ==
5205 14:48:37.931862
5206 14:48:37.931920
5207 14:48:37.935441 TX Vref Scan disable
5208 14:48:37.935523 == TX Byte 0 ==
5209 14:48:37.941774 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5210 14:48:37.945120 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5211 14:48:37.945202 == TX Byte 1 ==
5212 14:48:37.951710 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5213 14:48:37.954809 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5214 14:48:37.954918 ==
5215 14:48:37.958184 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 14:48:37.962266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 14:48:37.962348 ==
5218 14:48:37.962411
5219 14:48:37.962469
5220 14:48:37.964967 TX Vref Scan disable
5221 14:48:37.968459 == TX Byte 0 ==
5222 14:48:37.971173 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5223 14:48:37.975050 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5224 14:48:37.978117 == TX Byte 1 ==
5225 14:48:37.981165 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5226 14:48:37.984445 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5227 14:48:37.987667
5228 14:48:37.987750 [DATLAT]
5229 14:48:37.987818 Freq=933, CH0 RK0
5230 14:48:37.987877
5231 14:48:37.991491 DATLAT Default: 0xd
5232 14:48:37.991606 0, 0xFFFF, sum = 0
5233 14:48:37.994728 1, 0xFFFF, sum = 0
5234 14:48:37.994802 2, 0xFFFF, sum = 0
5235 14:48:37.998182 3, 0xFFFF, sum = 0
5236 14:48:37.998280 4, 0xFFFF, sum = 0
5237 14:48:38.001529 5, 0xFFFF, sum = 0
5238 14:48:38.004346 6, 0xFFFF, sum = 0
5239 14:48:38.004422 7, 0xFFFF, sum = 0
5240 14:48:38.007755 8, 0xFFFF, sum = 0
5241 14:48:38.007832 9, 0xFFFF, sum = 0
5242 14:48:38.010921 10, 0x0, sum = 1
5243 14:48:38.010995 11, 0x0, sum = 2
5244 14:48:38.011066 12, 0x0, sum = 3
5245 14:48:38.014283 13, 0x0, sum = 4
5246 14:48:38.014356 best_step = 11
5247 14:48:38.014417
5248 14:48:38.018156 ==
5249 14:48:38.018227 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 14:48:38.024291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 14:48:38.024382 ==
5252 14:48:38.024479 RX Vref Scan: 1
5253 14:48:38.024575
5254 14:48:38.027811 RX Vref 0 -> 0, step: 1
5255 14:48:38.027934
5256 14:48:38.031250 RX Delay -77 -> 252, step: 4
5257 14:48:38.031331
5258 14:48:38.034224 Set Vref, RX VrefLevel [Byte0]: 62
5259 14:48:38.037781 [Byte1]: 58
5260 14:48:38.037864
5261 14:48:38.040956 Final RX Vref Byte 0 = 62 to rank0
5262 14:48:38.044176 Final RX Vref Byte 1 = 58 to rank0
5263 14:48:38.047750 Final RX Vref Byte 0 = 62 to rank1
5264 14:48:38.050620 Final RX Vref Byte 1 = 58 to rank1==
5265 14:48:38.054351 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 14:48:38.057877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 14:48:38.060717 ==
5268 14:48:38.060825 DQS Delay:
5269 14:48:38.060916 DQS0 = 0, DQS1 = 0
5270 14:48:38.064054 DQM Delay:
5271 14:48:38.064135 DQM0 = 95, DQM1 = 83
5272 14:48:38.064200 DQ Delay:
5273 14:48:38.067732 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5274 14:48:38.071296 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =108
5275 14:48:38.074126 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5276 14:48:38.077300 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =90
5277 14:48:38.077381
5278 14:48:38.082992
5279 14:48:38.087274 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5280 14:48:38.090689 CH0 RK0: MR19=505, MR18=1514
5281 14:48:38.097841 CH0_RK0: MR19=0x505, MR18=0x1514, DQSOSC=415, MR23=63, INC=62, DEC=41
5282 14:48:38.097922
5283 14:48:38.100438 ----->DramcWriteLeveling(PI) begin...
5284 14:48:38.100546 ==
5285 14:48:38.103933 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 14:48:38.107284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 14:48:38.107388 ==
5288 14:48:38.110619 Write leveling (Byte 0): 31 => 31
5289 14:48:38.113980 Write leveling (Byte 1): 31 => 31
5290 14:48:38.117194 DramcWriteLeveling(PI) end<-----
5291 14:48:38.117270
5292 14:48:38.117332 ==
5293 14:48:38.120778 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 14:48:38.123678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 14:48:38.123759 ==
5296 14:48:38.127051 [Gating] SW mode calibration
5297 14:48:38.133594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 14:48:38.140249 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 14:48:38.143598 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5300 14:48:38.146747 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5301 14:48:38.153319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 14:48:38.157124 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 14:48:38.160171 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 14:48:38.166794 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 14:48:38.170012 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5306 14:48:38.173365 0 14 28 | B1->B0 | 3333 2c2c | 1 1 | (1 1) (1 0)
5307 14:48:38.180052 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5308 14:48:38.183336 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 14:48:38.186827 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 14:48:38.193381 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 14:48:38.196411 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 14:48:38.200144 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 14:48:38.206359 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 14:48:38.209937 0 15 28 | B1->B0 | 2626 3736 | 0 1 | (0 0) (0 0)
5315 14:48:38.212950 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5316 14:48:38.219646 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 14:48:38.223394 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 14:48:38.226408 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 14:48:38.233508 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 14:48:38.236630 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 14:48:38.239962 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 14:48:38.246402 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5323 14:48:38.249445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5324 14:48:38.253224 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5325 14:48:38.259741 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 14:48:38.262625 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 14:48:38.266443 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 14:48:38.272762 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 14:48:38.275928 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 14:48:38.279162 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 14:48:38.286248 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 14:48:38.289600 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 14:48:38.292970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 14:48:38.299156 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 14:48:38.302478 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 14:48:38.305878 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 14:48:38.312327 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5338 14:48:38.315920 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5339 14:48:38.319678 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5340 14:48:38.322177 Total UI for P1: 0, mck2ui 16
5341 14:48:38.325922 best dqsien dly found for B0: ( 1, 2, 26)
5342 14:48:38.332357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 14:48:38.332469 Total UI for P1: 0, mck2ui 16
5344 14:48:38.335479 best dqsien dly found for B1: ( 1, 3, 0)
5345 14:48:38.342162 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5346 14:48:38.345344 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5347 14:48:38.345419
5348 14:48:38.348633 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5349 14:48:38.352582 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5350 14:48:38.355530 [Gating] SW calibration Done
5351 14:48:38.355605 ==
5352 14:48:38.358673 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 14:48:38.362238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 14:48:38.362335 ==
5355 14:48:38.365349 RX Vref Scan: 0
5356 14:48:38.365430
5357 14:48:38.365494 RX Vref 0 -> 0, step: 1
5358 14:48:38.365554
5359 14:48:38.368726 RX Delay -80 -> 252, step: 8
5360 14:48:38.372154 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5361 14:48:38.375368 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5362 14:48:38.382196 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5363 14:48:38.385209 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5364 14:48:38.388466 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5365 14:48:38.392044 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5366 14:48:38.395160 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5367 14:48:38.401912 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5368 14:48:38.405154 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5369 14:48:38.408458 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5370 14:48:38.411782 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5371 14:48:38.415233 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5372 14:48:38.421941 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5373 14:48:38.425174 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5374 14:48:38.428285 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5375 14:48:38.431701 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5376 14:48:38.431783 ==
5377 14:48:38.434739 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 14:48:38.441683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 14:48:38.441767 ==
5380 14:48:38.441832 DQS Delay:
5381 14:48:38.444857 DQS0 = 0, DQS1 = 0
5382 14:48:38.444940 DQM Delay:
5383 14:48:38.445004 DQM0 = 91, DQM1 = 82
5384 14:48:38.448219 DQ Delay:
5385 14:48:38.452755 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5386 14:48:38.454791 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5387 14:48:38.457788 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5388 14:48:38.461378 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5389 14:48:38.461476
5390 14:48:38.461554
5391 14:48:38.461615 ==
5392 14:48:38.464507 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 14:48:38.467739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 14:48:38.467829 ==
5395 14:48:38.467896
5396 14:48:38.467956
5397 14:48:38.471319 TX Vref Scan disable
5398 14:48:38.474174 == TX Byte 0 ==
5399 14:48:38.477627 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5400 14:48:38.480931 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5401 14:48:38.484251 == TX Byte 1 ==
5402 14:48:38.487550 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5403 14:48:38.490806 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5404 14:48:38.490891 ==
5405 14:48:38.494158 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 14:48:38.497349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 14:48:38.500747 ==
5408 14:48:38.500833
5409 14:48:38.500900
5410 14:48:38.500962 TX Vref Scan disable
5411 14:48:38.504310 == TX Byte 0 ==
5412 14:48:38.507551 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5413 14:48:38.514211 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5414 14:48:38.514336 == TX Byte 1 ==
5415 14:48:38.517465 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5416 14:48:38.524475 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5417 14:48:38.524587
5418 14:48:38.524661 [DATLAT]
5419 14:48:38.524742 Freq=933, CH0 RK1
5420 14:48:38.524809
5421 14:48:38.527923 DATLAT Default: 0xb
5422 14:48:38.528051 0, 0xFFFF, sum = 0
5423 14:48:38.530918 1, 0xFFFF, sum = 0
5424 14:48:38.531028 2, 0xFFFF, sum = 0
5425 14:48:38.533929 3, 0xFFFF, sum = 0
5426 14:48:38.537868 4, 0xFFFF, sum = 0
5427 14:48:38.537955 5, 0xFFFF, sum = 0
5428 14:48:38.540612 6, 0xFFFF, sum = 0
5429 14:48:38.540697 7, 0xFFFF, sum = 0
5430 14:48:38.544459 8, 0xFFFF, sum = 0
5431 14:48:38.544544 9, 0xFFFF, sum = 0
5432 14:48:38.547199 10, 0x0, sum = 1
5433 14:48:38.547285 11, 0x0, sum = 2
5434 14:48:38.550594 12, 0x0, sum = 3
5435 14:48:38.550679 13, 0x0, sum = 4
5436 14:48:38.550745 best_step = 11
5437 14:48:38.550805
5438 14:48:38.554370 ==
5439 14:48:38.557119 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 14:48:38.560495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 14:48:38.560618 ==
5442 14:48:38.560726 RX Vref Scan: 0
5443 14:48:38.560817
5444 14:48:38.564052 RX Vref 0 -> 0, step: 1
5445 14:48:38.564137
5446 14:48:38.567768 RX Delay -77 -> 252, step: 4
5447 14:48:38.574801 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5448 14:48:38.577320 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5449 14:48:38.580493 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5450 14:48:38.583998 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5451 14:48:38.587032 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5452 14:48:38.590682 iDelay=199, Bit 5, Center 80 (-9 ~ 170) 180
5453 14:48:38.597445 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5454 14:48:38.600754 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5455 14:48:38.603946 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5456 14:48:38.607233 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5457 14:48:38.610739 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5458 14:48:38.613896 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5459 14:48:38.620320 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5460 14:48:38.623731 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5461 14:48:38.626863 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5462 14:48:38.630277 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5463 14:48:38.630351 ==
5464 14:48:38.633530 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 14:48:38.640500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 14:48:38.640586 ==
5467 14:48:38.640671 DQS Delay:
5468 14:48:38.640757 DQS0 = 0, DQS1 = 0
5469 14:48:38.643781 DQM Delay:
5470 14:48:38.643854 DQM0 = 93, DQM1 = 85
5471 14:48:38.646901 DQ Delay:
5472 14:48:38.650520 DQ0 =90, DQ1 =96, DQ2 =90, DQ3 =88
5473 14:48:38.653822 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5474 14:48:38.656970 DQ8 =80, DQ9 =72, DQ10 =84, DQ11 =80
5475 14:48:38.660240 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5476 14:48:38.660316
5477 14:48:38.660403
5478 14:48:38.666943 [DQSOSCAuto] RK1, (LSB)MR18= 0x3214, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5479 14:48:38.670034 CH0 RK1: MR19=505, MR18=3214
5480 14:48:38.677346 CH0_RK1: MR19=0x505, MR18=0x3214, DQSOSC=406, MR23=63, INC=65, DEC=43
5481 14:48:38.679920 [RxdqsGatingPostProcess] freq 933
5482 14:48:38.683255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 14:48:38.686845 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 14:48:38.689984 best DQS1 dly(2T, 0.5T) = (0, 11)
5485 14:48:38.693324 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 14:48:38.696518 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5487 14:48:38.699726 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 14:48:38.703436 best DQS1 dly(2T, 0.5T) = (0, 11)
5489 14:48:38.706469 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 14:48:38.709972 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5491 14:48:38.712880 Pre-setting of DQS Precalculation
5492 14:48:38.716526 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 14:48:38.716648 ==
5494 14:48:38.719576 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 14:48:38.726365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 14:48:38.726449 ==
5497 14:48:38.729871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 14:48:38.736339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 14:48:38.739442 [CA 0] Center 37 (7~68) winsize 62
5500 14:48:38.743363 [CA 1] Center 37 (7~68) winsize 62
5501 14:48:38.746384 [CA 2] Center 34 (5~64) winsize 60
5502 14:48:38.749761 [CA 3] Center 34 (5~64) winsize 60
5503 14:48:38.752730 [CA 4] Center 34 (5~64) winsize 60
5504 14:48:38.755968 [CA 5] Center 34 (4~64) winsize 61
5505 14:48:38.756050
5506 14:48:38.759979 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 14:48:38.760079
5508 14:48:38.763341 [CATrainingPosCal] consider 1 rank data
5509 14:48:38.766429 u2DelayCellTimex100 = 270/100 ps
5510 14:48:38.769647 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 14:48:38.772666 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 14:48:38.779651 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5513 14:48:38.782888 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5514 14:48:38.786310 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5515 14:48:38.789636 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5516 14:48:38.789721
5517 14:48:38.792904 CA PerBit enable=1, Macro0, CA PI delay=34
5518 14:48:38.792978
5519 14:48:38.796363 [CBTSetCACLKResult] CA Dly = 34
5520 14:48:38.796460 CS Dly: 6 (0~37)
5521 14:48:38.799764 ==
5522 14:48:38.799844 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 14:48:38.806045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 14:48:38.806120 ==
5525 14:48:38.809233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 14:48:38.815921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5527 14:48:38.819514 [CA 0] Center 37 (7~67) winsize 61
5528 14:48:38.822847 [CA 1] Center 37 (7~68) winsize 62
5529 14:48:38.826344 [CA 2] Center 35 (5~65) winsize 61
5530 14:48:38.829406 [CA 3] Center 34 (4~64) winsize 61
5531 14:48:38.832759 [CA 4] Center 34 (4~65) winsize 62
5532 14:48:38.836669 [CA 5] Center 33 (3~64) winsize 62
5533 14:48:38.836778
5534 14:48:38.839666 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5535 14:48:38.839740
5536 14:48:38.843233 [CATrainingPosCal] consider 2 rank data
5537 14:48:38.846228 u2DelayCellTimex100 = 270/100 ps
5538 14:48:38.849442 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5539 14:48:38.856054 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 14:48:38.859287 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5541 14:48:38.862552 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5542 14:48:38.865919 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5543 14:48:38.869221 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 14:48:38.869305
5545 14:48:38.872549 CA PerBit enable=1, Macro0, CA PI delay=34
5546 14:48:38.872630
5547 14:48:38.875977 [CBTSetCACLKResult] CA Dly = 34
5548 14:48:38.876049 CS Dly: 7 (0~39)
5549 14:48:38.879033
5550 14:48:38.882359 ----->DramcWriteLeveling(PI) begin...
5551 14:48:38.882475 ==
5552 14:48:38.885691 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 14:48:38.889021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 14:48:38.889106 ==
5555 14:48:38.892488 Write leveling (Byte 0): 25 => 25
5556 14:48:38.895695 Write leveling (Byte 1): 28 => 28
5557 14:48:38.898983 DramcWriteLeveling(PI) end<-----
5558 14:48:38.899065
5559 14:48:38.899138 ==
5560 14:48:38.902405 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 14:48:38.905586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 14:48:38.905693 ==
5563 14:48:38.908941 [Gating] SW mode calibration
5564 14:48:38.915736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 14:48:38.922316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 14:48:38.925534 0 14 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
5567 14:48:38.928687 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 14:48:38.935577 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 14:48:38.938553 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 14:48:38.942082 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 14:48:38.948355 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 14:48:38.951632 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 14:48:38.955400 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5574 14:48:38.961880 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5575 14:48:38.964952 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 14:48:38.968287 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 14:48:38.975259 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 14:48:38.978651 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 14:48:38.981960 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 14:48:38.988355 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 14:48:38.991685 0 15 28 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (1 1)
5582 14:48:38.995061 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 14:48:39.001786 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 14:48:39.004893 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 14:48:39.008320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 14:48:39.015200 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 14:48:39.018425 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 14:48:39.021623 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 14:48:39.025033 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 14:48:39.031714 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5591 14:48:39.035256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 14:48:39.038052 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 14:48:39.044649 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 14:48:39.048777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 14:48:39.051426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 14:48:39.058081 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 14:48:39.061354 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 14:48:39.064770 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 14:48:39.071554 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 14:48:39.074850 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 14:48:39.078227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 14:48:39.084546 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 14:48:39.087763 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 14:48:39.091043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 14:48:39.097722 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 14:48:39.101188 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5607 14:48:39.104280 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 14:48:39.107644 Total UI for P1: 0, mck2ui 16
5609 14:48:39.110988 best dqsien dly found for B0: ( 1, 2, 30)
5610 14:48:39.114427 Total UI for P1: 0, mck2ui 16
5611 14:48:39.117705 best dqsien dly found for B1: ( 1, 2, 30)
5612 14:48:39.120833 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5613 14:48:39.124666 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5614 14:48:39.124749
5615 14:48:39.130667 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5616 14:48:39.134512 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5617 14:48:39.137596 [Gating] SW calibration Done
5618 14:48:39.137677 ==
5619 14:48:39.140932 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 14:48:39.144167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 14:48:39.144275 ==
5622 14:48:39.144367 RX Vref Scan: 0
5623 14:48:39.144455
5624 14:48:39.147379 RX Vref 0 -> 0, step: 1
5625 14:48:39.147485
5626 14:48:39.150573 RX Delay -80 -> 252, step: 8
5627 14:48:39.153981 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5628 14:48:39.157381 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5629 14:48:39.164328 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5630 14:48:39.167183 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5631 14:48:39.170606 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5632 14:48:39.173849 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5633 14:48:39.177274 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5634 14:48:39.180714 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5635 14:48:39.186963 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5636 14:48:39.190425 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5637 14:48:39.194044 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5638 14:48:39.196851 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5639 14:48:39.200518 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5640 14:48:39.206917 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5641 14:48:39.210532 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5642 14:48:39.213595 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5643 14:48:39.213681 ==
5644 14:48:39.216792 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 14:48:39.220100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 14:48:39.220186 ==
5647 14:48:39.223681 DQS Delay:
5648 14:48:39.223766 DQS0 = 0, DQS1 = 0
5649 14:48:39.226887 DQM Delay:
5650 14:48:39.226973 DQM0 = 93, DQM1 = 86
5651 14:48:39.227059 DQ Delay:
5652 14:48:39.230021 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5653 14:48:39.233665 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5654 14:48:39.236627 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5655 14:48:39.240285 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5656 14:48:39.240370
5657 14:48:39.240472
5658 14:48:39.243333 ==
5659 14:48:39.247162 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 14:48:39.250297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 14:48:39.250383 ==
5662 14:48:39.250469
5663 14:48:39.250549
5664 14:48:39.253572 TX Vref Scan disable
5665 14:48:39.253657 == TX Byte 0 ==
5666 14:48:39.259754 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 14:48:39.263342 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 14:48:39.263428 == TX Byte 1 ==
5669 14:48:39.270077 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5670 14:48:39.273277 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5671 14:48:39.273362 ==
5672 14:48:39.276493 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 14:48:39.279917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 14:48:39.280004 ==
5675 14:48:39.280090
5676 14:48:39.280171
5677 14:48:39.283246 TX Vref Scan disable
5678 14:48:39.286548 == TX Byte 0 ==
5679 14:48:39.289799 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5680 14:48:39.293314 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5681 14:48:39.296419 == TX Byte 1 ==
5682 14:48:39.299835 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5683 14:48:39.303109 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5684 14:48:39.303194
5685 14:48:39.306280 [DATLAT]
5686 14:48:39.306365 Freq=933, CH1 RK0
5687 14:48:39.306452
5688 14:48:39.309727 DATLAT Default: 0xd
5689 14:48:39.309812 0, 0xFFFF, sum = 0
5690 14:48:39.313066 1, 0xFFFF, sum = 0
5691 14:48:39.313153 2, 0xFFFF, sum = 0
5692 14:48:39.316029 3, 0xFFFF, sum = 0
5693 14:48:39.316115 4, 0xFFFF, sum = 0
5694 14:48:39.319319 5, 0xFFFF, sum = 0
5695 14:48:39.319406 6, 0xFFFF, sum = 0
5696 14:48:39.322885 7, 0xFFFF, sum = 0
5697 14:48:39.322971 8, 0xFFFF, sum = 0
5698 14:48:39.326242 9, 0xFFFF, sum = 0
5699 14:48:39.326329 10, 0x0, sum = 1
5700 14:48:39.329334 11, 0x0, sum = 2
5701 14:48:39.329416 12, 0x0, sum = 3
5702 14:48:39.332686 13, 0x0, sum = 4
5703 14:48:39.332774 best_step = 11
5704 14:48:39.332839
5705 14:48:39.332897 ==
5706 14:48:39.335847 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 14:48:39.342603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 14:48:39.342685 ==
5709 14:48:39.342748 RX Vref Scan: 1
5710 14:48:39.342808
5711 14:48:39.345848 RX Vref 0 -> 0, step: 1
5712 14:48:39.345930
5713 14:48:39.349172 RX Delay -69 -> 252, step: 4
5714 14:48:39.349265
5715 14:48:39.352668 Set Vref, RX VrefLevel [Byte0]: 59
5716 14:48:39.356904 [Byte1]: 54
5717 14:48:39.356986
5718 14:48:39.359141 Final RX Vref Byte 0 = 59 to rank0
5719 14:48:39.362547 Final RX Vref Byte 1 = 54 to rank0
5720 14:48:39.366337 Final RX Vref Byte 0 = 59 to rank1
5721 14:48:39.369557 Final RX Vref Byte 1 = 54 to rank1==
5722 14:48:39.372465 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 14:48:39.376023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 14:48:39.376109 ==
5725 14:48:39.378920 DQS Delay:
5726 14:48:39.379006 DQS0 = 0, DQS1 = 0
5727 14:48:39.382314 DQM Delay:
5728 14:48:39.382403 DQM0 = 95, DQM1 = 89
5729 14:48:39.382488 DQ Delay:
5730 14:48:39.385682 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5731 14:48:39.388929 DQ4 =94, DQ5 =104, DQ6 =104, DQ7 =94
5732 14:48:39.392093 DQ8 =78, DQ9 =82, DQ10 =88, DQ11 =84
5733 14:48:39.395486 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5734 14:48:39.395572
5735 14:48:39.398748
5736 14:48:39.405401 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5737 14:48:39.408835 CH1 RK0: MR19=405, MR18=FE07
5738 14:48:39.415153 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5739 14:48:39.415239
5740 14:48:39.418470 ----->DramcWriteLeveling(PI) begin...
5741 14:48:39.418557 ==
5742 14:48:39.421701 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 14:48:39.425141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 14:48:39.425227 ==
5745 14:48:39.428432 Write leveling (Byte 0): 25 => 25
5746 14:48:39.431726 Write leveling (Byte 1): 27 => 27
5747 14:48:39.435152 DramcWriteLeveling(PI) end<-----
5748 14:48:39.435237
5749 14:48:39.435322 ==
5750 14:48:39.438484 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 14:48:39.441385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 14:48:39.441487 ==
5753 14:48:39.444873 [Gating] SW mode calibration
5754 14:48:39.451664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5755 14:48:39.458286 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5756 14:48:39.461522 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5757 14:48:39.465041 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 14:48:39.471417 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 14:48:39.474713 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 14:48:39.477955 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 14:48:39.484599 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5762 14:48:39.487915 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5763 14:48:39.491281 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5764 14:48:39.498201 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 14:48:39.501606 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 14:48:39.504463 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 14:48:39.511222 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 14:48:39.514445 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 14:48:39.517697 0 15 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5770 14:48:39.524398 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5771 14:48:39.527768 0 15 28 | B1->B0 | 3737 4545 | 0 0 | (1 1) (0 0)
5772 14:48:39.531063 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 14:48:39.537856 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 14:48:39.540686 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 14:48:39.543977 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 14:48:39.550878 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 14:48:39.554215 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 14:48:39.557395 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5779 14:48:39.564403 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 14:48:39.567676 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 14:48:39.571220 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 14:48:39.577438 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 14:48:39.580658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 14:48:39.583754 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 14:48:39.590467 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 14:48:39.593795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 14:48:39.597048 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 14:48:39.603607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 14:48:39.607448 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 14:48:39.610472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 14:48:39.617269 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 14:48:39.620373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 14:48:39.623849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 14:48:39.630177 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5795 14:48:39.633482 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5796 14:48:39.636892 Total UI for P1: 0, mck2ui 16
5797 14:48:39.640187 best dqsien dly found for B0: ( 1, 2, 24)
5798 14:48:39.643830 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 14:48:39.647245 Total UI for P1: 0, mck2ui 16
5800 14:48:39.650190 best dqsien dly found for B1: ( 1, 2, 28)
5801 14:48:39.653592 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5802 14:48:39.656913 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5803 14:48:39.656994
5804 14:48:39.660002 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5805 14:48:39.666679 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5806 14:48:39.666761 [Gating] SW calibration Done
5807 14:48:39.666826 ==
5808 14:48:39.670443 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 14:48:39.676690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 14:48:39.676772 ==
5811 14:48:39.676836 RX Vref Scan: 0
5812 14:48:39.676896
5813 14:48:39.679979 RX Vref 0 -> 0, step: 1
5814 14:48:39.680061
5815 14:48:39.683370 RX Delay -80 -> 252, step: 8
5816 14:48:39.686540 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5817 14:48:39.690046 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5818 14:48:39.693122 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5819 14:48:39.699677 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5820 14:48:39.702927 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5821 14:48:39.706242 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5822 14:48:39.709829 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5823 14:48:39.712825 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5824 14:48:39.716195 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5825 14:48:39.722976 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5826 14:48:39.726513 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5827 14:48:39.729899 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5828 14:48:39.733392 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5829 14:48:39.736190 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5830 14:48:39.742896 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5831 14:48:39.746255 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5832 14:48:39.746383 ==
5833 14:48:39.749578 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 14:48:39.752742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 14:48:39.752869 ==
5836 14:48:39.755990 DQS Delay:
5837 14:48:39.756099 DQS0 = 0, DQS1 = 0
5838 14:48:39.756188 DQM Delay:
5839 14:48:39.759203 DQM0 = 93, DQM1 = 89
5840 14:48:39.759290 DQ Delay:
5841 14:48:39.762874 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5842 14:48:39.766332 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5843 14:48:39.769481 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5844 14:48:39.772463 DQ12 =99, DQ13 =95, DQ14 =91, DQ15 =95
5845 14:48:39.772577
5846 14:48:39.772659
5847 14:48:39.772725 ==
5848 14:48:39.776250 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 14:48:39.782320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 14:48:39.782404 ==
5851 14:48:39.782468
5852 14:48:39.782527
5853 14:48:39.785893 TX Vref Scan disable
5854 14:48:39.785974 == TX Byte 0 ==
5855 14:48:39.789211 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5856 14:48:39.795829 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5857 14:48:39.795911 == TX Byte 1 ==
5858 14:48:39.799235 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5859 14:48:39.805769 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5860 14:48:39.805870 ==
5861 14:48:39.808894 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 14:48:39.812472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 14:48:39.812584 ==
5864 14:48:39.812676
5865 14:48:39.812763
5866 14:48:39.815364 TX Vref Scan disable
5867 14:48:39.818461 == TX Byte 0 ==
5868 14:48:39.822159 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5869 14:48:39.825365 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5870 14:48:39.828608 == TX Byte 1 ==
5871 14:48:39.832107 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5872 14:48:39.835385 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5873 14:48:39.835507
5874 14:48:39.838579 [DATLAT]
5875 14:48:39.838702 Freq=933, CH1 RK1
5876 14:48:39.838815
5877 14:48:39.842098 DATLAT Default: 0xb
5878 14:48:39.842215 0, 0xFFFF, sum = 0
5879 14:48:39.844888 1, 0xFFFF, sum = 0
5880 14:48:39.845012 2, 0xFFFF, sum = 0
5881 14:48:39.848444 3, 0xFFFF, sum = 0
5882 14:48:39.848575 4, 0xFFFF, sum = 0
5883 14:48:39.851926 5, 0xFFFF, sum = 0
5884 14:48:39.852047 6, 0xFFFF, sum = 0
5885 14:48:39.855009 7, 0xFFFF, sum = 0
5886 14:48:39.855134 8, 0xFFFF, sum = 0
5887 14:48:39.858202 9, 0xFFFF, sum = 0
5888 14:48:39.858325 10, 0x0, sum = 1
5889 14:48:39.861877 11, 0x0, sum = 2
5890 14:48:39.862000 12, 0x0, sum = 3
5891 14:48:39.865082 13, 0x0, sum = 4
5892 14:48:39.865206 best_step = 11
5893 14:48:39.865314
5894 14:48:39.865421 ==
5895 14:48:39.868452 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 14:48:39.871656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 14:48:39.875074 ==
5898 14:48:39.875197 RX Vref Scan: 0
5899 14:48:39.875310
5900 14:48:39.878329 RX Vref 0 -> 0, step: 1
5901 14:48:39.878435
5902 14:48:39.881630 RX Delay -69 -> 252, step: 4
5903 14:48:39.885078 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5904 14:48:39.888432 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5905 14:48:39.895117 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5906 14:48:39.898183 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5907 14:48:39.901501 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5908 14:48:39.905022 iDelay=203, Bit 5, Center 104 (7 ~ 202) 196
5909 14:48:39.908434 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5910 14:48:39.911757 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5911 14:48:39.918291 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5912 14:48:39.921594 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5913 14:48:39.925668 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5914 14:48:39.928186 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5915 14:48:39.931469 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5916 14:48:39.935288 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5917 14:48:39.941138 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5918 14:48:39.944555 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5919 14:48:39.944694 ==
5920 14:48:39.947753 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 14:48:39.951167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 14:48:39.951277 ==
5923 14:48:39.954718 DQS Delay:
5924 14:48:39.954803 DQS0 = 0, DQS1 = 0
5925 14:48:39.954887 DQM Delay:
5926 14:48:39.958017 DQM0 = 92, DQM1 = 91
5927 14:48:39.958111 DQ Delay:
5928 14:48:39.961182 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =90
5929 14:48:39.965021 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =88
5930 14:48:39.968149 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5931 14:48:39.971450 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5932 14:48:39.971531
5933 14:48:39.971592
5934 14:48:39.981589 [DQSOSCAuto] RK1, (LSB)MR18= 0x1224, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5935 14:48:39.984245 CH1 RK1: MR19=505, MR18=1224
5936 14:48:39.988074 CH1_RK1: MR19=0x505, MR18=0x1224, DQSOSC=410, MR23=63, INC=64, DEC=42
5937 14:48:39.991303 [RxdqsGatingPostProcess] freq 933
5938 14:48:39.997643 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5939 14:48:40.000876 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 14:48:40.004464 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 14:48:40.007593 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 14:48:40.011143 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 14:48:40.014566 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 14:48:40.017699 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 14:48:40.021359 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 14:48:40.024125 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 14:48:40.024203 Pre-setting of DQS Precalculation
5948 14:48:40.031135 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5949 14:48:40.037780 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5950 14:48:40.044016 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5951 14:48:40.044124
5952 14:48:40.044236
5953 14:48:40.047493 [Calibration Summary] 1866 Mbps
5954 14:48:40.050830 CH 0, Rank 0
5955 14:48:40.050923 SW Impedance : PASS
5956 14:48:40.054322 DUTY Scan : NO K
5957 14:48:40.057637 ZQ Calibration : PASS
5958 14:48:40.057724 Jitter Meter : NO K
5959 14:48:40.061090 CBT Training : PASS
5960 14:48:40.064274 Write leveling : PASS
5961 14:48:40.064365 RX DQS gating : PASS
5962 14:48:40.067687 RX DQ/DQS(RDDQC) : PASS
5963 14:48:40.067767 TX DQ/DQS : PASS
5964 14:48:40.070718 RX DATLAT : PASS
5965 14:48:40.073989 RX DQ/DQS(Engine): PASS
5966 14:48:40.074067 TX OE : NO K
5967 14:48:40.077307 All Pass.
5968 14:48:40.077383
5969 14:48:40.077465 CH 0, Rank 1
5970 14:48:40.080652 SW Impedance : PASS
5971 14:48:40.080738 DUTY Scan : NO K
5972 14:48:40.084136 ZQ Calibration : PASS
5973 14:48:40.087405 Jitter Meter : NO K
5974 14:48:40.087487 CBT Training : PASS
5975 14:48:40.090729 Write leveling : PASS
5976 14:48:40.094210 RX DQS gating : PASS
5977 14:48:40.094286 RX DQ/DQS(RDDQC) : PASS
5978 14:48:40.097342 TX DQ/DQS : PASS
5979 14:48:40.100849 RX DATLAT : PASS
5980 14:48:40.100924 RX DQ/DQS(Engine): PASS
5981 14:48:40.104156 TX OE : NO K
5982 14:48:40.104237 All Pass.
5983 14:48:40.104320
5984 14:48:40.107331 CH 1, Rank 0
5985 14:48:40.107415 SW Impedance : PASS
5986 14:48:40.110546 DUTY Scan : NO K
5987 14:48:40.113956 ZQ Calibration : PASS
5988 14:48:40.114033 Jitter Meter : NO K
5989 14:48:40.117649 CBT Training : PASS
5990 14:48:40.117750 Write leveling : PASS
5991 14:48:40.121041 RX DQS gating : PASS
5992 14:48:40.124132 RX DQ/DQS(RDDQC) : PASS
5993 14:48:40.124209 TX DQ/DQS : PASS
5994 14:48:40.127134 RX DATLAT : PASS
5995 14:48:40.130562 RX DQ/DQS(Engine): PASS
5996 14:48:40.130644 TX OE : NO K
5997 14:48:40.133871 All Pass.
5998 14:48:40.133952
5999 14:48:40.134039 CH 1, Rank 1
6000 14:48:40.136983 SW Impedance : PASS
6001 14:48:40.137060 DUTY Scan : NO K
6002 14:48:40.140337 ZQ Calibration : PASS
6003 14:48:40.143684 Jitter Meter : NO K
6004 14:48:40.143789 CBT Training : PASS
6005 14:48:40.146936 Write leveling : PASS
6006 14:48:40.150465 RX DQS gating : PASS
6007 14:48:40.150549 RX DQ/DQS(RDDQC) : PASS
6008 14:48:40.153696 TX DQ/DQS : PASS
6009 14:48:40.156986 RX DATLAT : PASS
6010 14:48:40.157060 RX DQ/DQS(Engine): PASS
6011 14:48:40.160234 TX OE : NO K
6012 14:48:40.160307 All Pass.
6013 14:48:40.160375
6014 14:48:40.163727 DramC Write-DBI off
6015 14:48:40.167193 PER_BANK_REFRESH: Hybrid Mode
6016 14:48:40.167301 TX_TRACKING: ON
6017 14:48:40.177096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6018 14:48:40.180555 [FAST_K] Save calibration result to emmc
6019 14:48:40.183725 dramc_set_vcore_voltage set vcore to 650000
6020 14:48:40.186855 Read voltage for 400, 6
6021 14:48:40.186962 Vio18 = 0
6022 14:48:40.187058 Vcore = 650000
6023 14:48:40.190386 Vdram = 0
6024 14:48:40.190486 Vddq = 0
6025 14:48:40.190576 Vmddr = 0
6026 14:48:40.197169 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6027 14:48:40.200477 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6028 14:48:40.203749 MEM_TYPE=3, freq_sel=20
6029 14:48:40.207030 sv_algorithm_assistance_LP4_800
6030 14:48:40.210448 ============ PULL DRAM RESETB DOWN ============
6031 14:48:40.213742 ========== PULL DRAM RESETB DOWN end =========
6032 14:48:40.220345 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6033 14:48:40.223382 ===================================
6034 14:48:40.223484 LPDDR4 DRAM CONFIGURATION
6035 14:48:40.226949 ===================================
6036 14:48:40.230357 EX_ROW_EN[0] = 0x0
6037 14:48:40.233501 EX_ROW_EN[1] = 0x0
6038 14:48:40.233608 LP4Y_EN = 0x0
6039 14:48:40.236650 WORK_FSP = 0x0
6040 14:48:40.236755 WL = 0x2
6041 14:48:40.240223 RL = 0x2
6042 14:48:40.240332 BL = 0x2
6043 14:48:40.243374 RPST = 0x0
6044 14:48:40.243476 RD_PRE = 0x0
6045 14:48:40.246540 WR_PRE = 0x1
6046 14:48:40.246638 WR_PST = 0x0
6047 14:48:40.249816 DBI_WR = 0x0
6048 14:48:40.249918 DBI_RD = 0x0
6049 14:48:40.253486 OTF = 0x1
6050 14:48:40.256695 ===================================
6051 14:48:40.259578 ===================================
6052 14:48:40.259689 ANA top config
6053 14:48:40.262934 ===================================
6054 14:48:40.266564 DLL_ASYNC_EN = 0
6055 14:48:40.269682 ALL_SLAVE_EN = 1
6056 14:48:40.272918 NEW_RANK_MODE = 1
6057 14:48:40.273029 DLL_IDLE_MODE = 1
6058 14:48:40.276503 LP45_APHY_COMB_EN = 1
6059 14:48:40.279941 TX_ODT_DIS = 1
6060 14:48:40.282949 NEW_8X_MODE = 1
6061 14:48:40.285977 ===================================
6062 14:48:40.289810 ===================================
6063 14:48:40.292545 data_rate = 800
6064 14:48:40.292658 CKR = 1
6065 14:48:40.295894 DQ_P2S_RATIO = 4
6066 14:48:40.299196 ===================================
6067 14:48:40.302613 CA_P2S_RATIO = 4
6068 14:48:40.305953 DQ_CA_OPEN = 0
6069 14:48:40.309301 DQ_SEMI_OPEN = 1
6070 14:48:40.312553 CA_SEMI_OPEN = 1
6071 14:48:40.312692 CA_FULL_RATE = 0
6072 14:48:40.315948 DQ_CKDIV4_EN = 0
6073 14:48:40.319287 CA_CKDIV4_EN = 1
6074 14:48:40.322612 CA_PREDIV_EN = 0
6075 14:48:40.325941 PH8_DLY = 0
6076 14:48:40.329535 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6077 14:48:40.329618 DQ_AAMCK_DIV = 0
6078 14:48:40.332859 CA_AAMCK_DIV = 0
6079 14:48:40.336228 CA_ADMCK_DIV = 4
6080 14:48:40.339053 DQ_TRACK_CA_EN = 0
6081 14:48:40.342817 CA_PICK = 800
6082 14:48:40.345732 CA_MCKIO = 400
6083 14:48:40.349289 MCKIO_SEMI = 400
6084 14:48:40.349370 PLL_FREQ = 3016
6085 14:48:40.352417 DQ_UI_PI_RATIO = 32
6086 14:48:40.355821 CA_UI_PI_RATIO = 32
6087 14:48:40.359088 ===================================
6088 14:48:40.362684 ===================================
6089 14:48:40.365519 memory_type:LPDDR4
6090 14:48:40.368984 GP_NUM : 10
6091 14:48:40.369088 SRAM_EN : 1
6092 14:48:40.372154 MD32_EN : 0
6093 14:48:40.375858 ===================================
6094 14:48:40.375960 [ANA_INIT] >>>>>>>>>>>>>>
6095 14:48:40.379424 <<<<<< [CONFIGURE PHASE]: ANA_TX
6096 14:48:40.382166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6097 14:48:40.385844 ===================================
6098 14:48:40.388894 data_rate = 800,PCW = 0X7400
6099 14:48:40.392382 ===================================
6100 14:48:40.395757 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6101 14:48:40.402393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 14:48:40.412002 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 14:48:40.418838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6104 14:48:40.422155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6105 14:48:40.425660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6106 14:48:40.425732 [ANA_INIT] flow start
6107 14:48:40.428738 [ANA_INIT] PLL >>>>>>>>
6108 14:48:40.432161 [ANA_INIT] PLL <<<<<<<<
6109 14:48:40.432253 [ANA_INIT] MIDPI >>>>>>>>
6110 14:48:40.435374 [ANA_INIT] MIDPI <<<<<<<<
6111 14:48:40.438817 [ANA_INIT] DLL >>>>>>>>
6112 14:48:40.438913 [ANA_INIT] flow end
6113 14:48:40.445089 ============ LP4 DIFF to SE enter ============
6114 14:48:40.448799 ============ LP4 DIFF to SE exit ============
6115 14:48:40.451863 [ANA_INIT] <<<<<<<<<<<<<
6116 14:48:40.455335 [Flow] Enable top DCM control >>>>>
6117 14:48:40.458752 [Flow] Enable top DCM control <<<<<
6118 14:48:40.461995 Enable DLL master slave shuffle
6119 14:48:40.465441 ==============================================================
6120 14:48:40.468585 Gating Mode config
6121 14:48:40.471718 ==============================================================
6122 14:48:40.475109 Config description:
6123 14:48:40.484603 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6124 14:48:40.491633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6125 14:48:40.495029 SELPH_MODE 0: By rank 1: By Phase
6126 14:48:40.501724 ==============================================================
6127 14:48:40.504800 GAT_TRACK_EN = 0
6128 14:48:40.507897 RX_GATING_MODE = 2
6129 14:48:40.511188 RX_GATING_TRACK_MODE = 2
6130 14:48:40.514330 SELPH_MODE = 1
6131 14:48:40.517952 PICG_EARLY_EN = 1
6132 14:48:40.520773 VALID_LAT_VALUE = 1
6133 14:48:40.524285 ==============================================================
6134 14:48:40.527566 Enter into Gating configuration >>>>
6135 14:48:40.530894 Exit from Gating configuration <<<<
6136 14:48:40.534300 Enter into DVFS_PRE_config >>>>>
6137 14:48:40.547239 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6138 14:48:40.547323 Exit from DVFS_PRE_config <<<<<
6139 14:48:40.550633 Enter into PICG configuration >>>>
6140 14:48:40.553932 Exit from PICG configuration <<<<
6141 14:48:40.557236 [RX_INPUT] configuration >>>>>
6142 14:48:40.560813 [RX_INPUT] configuration <<<<<
6143 14:48:40.567268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6144 14:48:40.570605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6145 14:48:40.577458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 14:48:40.583741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 14:48:40.590447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6148 14:48:40.597454 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6149 14:48:40.600293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6150 14:48:40.603508 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6151 14:48:40.607118 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6152 14:48:40.613666 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6153 14:48:40.616958 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6154 14:48:40.620204 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 14:48:40.623744 ===================================
6156 14:48:40.626864 LPDDR4 DRAM CONFIGURATION
6157 14:48:40.630497 ===================================
6158 14:48:40.633447 EX_ROW_EN[0] = 0x0
6159 14:48:40.633565 EX_ROW_EN[1] = 0x0
6160 14:48:40.636948 LP4Y_EN = 0x0
6161 14:48:40.637062 WORK_FSP = 0x0
6162 14:48:40.640169 WL = 0x2
6163 14:48:40.640278 RL = 0x2
6164 14:48:40.642991 BL = 0x2
6165 14:48:40.643097 RPST = 0x0
6166 14:48:40.646694 RD_PRE = 0x0
6167 14:48:40.646794 WR_PRE = 0x1
6168 14:48:40.650115 WR_PST = 0x0
6169 14:48:40.650215 DBI_WR = 0x0
6170 14:48:40.653303 DBI_RD = 0x0
6171 14:48:40.653395 OTF = 0x1
6172 14:48:40.656607 ===================================
6173 14:48:40.663248 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6174 14:48:40.666536 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6175 14:48:40.669792 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 14:48:40.673255 ===================================
6177 14:48:40.676371 LPDDR4 DRAM CONFIGURATION
6178 14:48:40.679607 ===================================
6179 14:48:40.683067 EX_ROW_EN[0] = 0x10
6180 14:48:40.683152 EX_ROW_EN[1] = 0x0
6181 14:48:40.686401 LP4Y_EN = 0x0
6182 14:48:40.686482 WORK_FSP = 0x0
6183 14:48:40.689675 WL = 0x2
6184 14:48:40.689753 RL = 0x2
6185 14:48:40.692780 BL = 0x2
6186 14:48:40.692888 RPST = 0x0
6187 14:48:40.695886 RD_PRE = 0x0
6188 14:48:40.695983 WR_PRE = 0x1
6189 14:48:40.699503 WR_PST = 0x0
6190 14:48:40.699595 DBI_WR = 0x0
6191 14:48:40.702782 DBI_RD = 0x0
6192 14:48:40.702935 OTF = 0x1
6193 14:48:40.705960 ===================================
6194 14:48:40.712246 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6195 14:48:40.717375 nWR fixed to 30
6196 14:48:40.720665 [ModeRegInit_LP4] CH0 RK0
6197 14:48:40.720802 [ModeRegInit_LP4] CH0 RK1
6198 14:48:40.723804 [ModeRegInit_LP4] CH1 RK0
6199 14:48:40.727210 [ModeRegInit_LP4] CH1 RK1
6200 14:48:40.727305 match AC timing 19
6201 14:48:40.734121 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6202 14:48:40.737238 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6203 14:48:40.740688 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6204 14:48:40.747564 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6205 14:48:40.750807 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6206 14:48:40.750948 ==
6207 14:48:40.753711 Dram Type= 6, Freq= 0, CH_0, rank 0
6208 14:48:40.756867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 14:48:40.757023 ==
6210 14:48:40.763544 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 14:48:40.770297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6212 14:48:40.773686 [CA 0] Center 36 (8~64) winsize 57
6213 14:48:40.777007 [CA 1] Center 36 (8~64) winsize 57
6214 14:48:40.780299 [CA 2] Center 36 (8~64) winsize 57
6215 14:48:40.783730 [CA 3] Center 36 (8~64) winsize 57
6216 14:48:40.783828 [CA 4] Center 36 (8~64) winsize 57
6217 14:48:40.787252 [CA 5] Center 36 (8~64) winsize 57
6218 14:48:40.787335
6219 14:48:40.793869 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6220 14:48:40.793951
6221 14:48:40.797083 [CATrainingPosCal] consider 1 rank data
6222 14:48:40.800419 u2DelayCellTimex100 = 270/100 ps
6223 14:48:40.803990 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 14:48:40.806979 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 14:48:40.810532 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 14:48:40.813701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 14:48:40.816675 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 14:48:40.820684 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 14:48:40.820770
6230 14:48:40.823979 CA PerBit enable=1, Macro0, CA PI delay=36
6231 14:48:40.824074
6232 14:48:40.826652 [CBTSetCACLKResult] CA Dly = 36
6233 14:48:40.829891 CS Dly: 1 (0~32)
6234 14:48:40.829962 ==
6235 14:48:40.833191 Dram Type= 6, Freq= 0, CH_0, rank 1
6236 14:48:40.836512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 14:48:40.836591 ==
6238 14:48:40.843219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 14:48:40.850108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6240 14:48:40.853110 [CA 0] Center 36 (8~64) winsize 57
6241 14:48:40.853191 [CA 1] Center 36 (8~64) winsize 57
6242 14:48:40.857089 [CA 2] Center 36 (8~64) winsize 57
6243 14:48:40.859704 [CA 3] Center 36 (8~64) winsize 57
6244 14:48:40.863156 [CA 4] Center 36 (8~64) winsize 57
6245 14:48:40.866822 [CA 5] Center 36 (8~64) winsize 57
6246 14:48:40.866917
6247 14:48:40.869786 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6248 14:48:40.869868
6249 14:48:40.873230 [CATrainingPosCal] consider 2 rank data
6250 14:48:40.876565 u2DelayCellTimex100 = 270/100 ps
6251 14:48:40.879482 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 14:48:40.886112 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 14:48:40.889799 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 14:48:40.892787 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 14:48:40.896173 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 14:48:40.899783 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 14:48:40.899881
6258 14:48:40.902668 CA PerBit enable=1, Macro0, CA PI delay=36
6259 14:48:40.902751
6260 14:48:40.906565 [CBTSetCACLKResult] CA Dly = 36
6261 14:48:40.906648 CS Dly: 1 (0~32)
6262 14:48:40.909678
6263 14:48:40.912799 ----->DramcWriteLeveling(PI) begin...
6264 14:48:40.912883 ==
6265 14:48:40.916434 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 14:48:40.919808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 14:48:40.919890 ==
6268 14:48:40.922913 Write leveling (Byte 0): 40 => 8
6269 14:48:40.926162 Write leveling (Byte 1): 40 => 8
6270 14:48:40.929425 DramcWriteLeveling(PI) end<-----
6271 14:48:40.929507
6272 14:48:40.929572 ==
6273 14:48:40.933211 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 14:48:40.936056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 14:48:40.936171 ==
6276 14:48:40.939902 [Gating] SW mode calibration
6277 14:48:40.946501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6278 14:48:40.952585 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6279 14:48:40.955999 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 14:48:40.959234 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 14:48:40.966149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 14:48:40.969401 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 14:48:40.972931 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 14:48:40.979578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 14:48:40.982651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 14:48:40.985965 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 14:48:40.992680 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 14:48:40.992762 Total UI for P1: 0, mck2ui 16
6289 14:48:40.995894 best dqsien dly found for B0: ( 0, 14, 24)
6290 14:48:40.999316 Total UI for P1: 0, mck2ui 16
6291 14:48:41.002787 best dqsien dly found for B1: ( 0, 14, 24)
6292 14:48:41.005955 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6293 14:48:41.012388 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6294 14:48:41.012469
6295 14:48:41.015607 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 14:48:41.019078 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 14:48:41.022444 [Gating] SW calibration Done
6298 14:48:41.022553 ==
6299 14:48:41.025577 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 14:48:41.028938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 14:48:41.029036 ==
6302 14:48:41.032026 RX Vref Scan: 0
6303 14:48:41.032107
6304 14:48:41.032171 RX Vref 0 -> 0, step: 1
6305 14:48:41.032249
6306 14:48:41.035550 RX Delay -410 -> 252, step: 16
6307 14:48:41.042148 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6308 14:48:41.045577 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6309 14:48:41.048795 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6310 14:48:41.052383 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6311 14:48:41.058645 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6312 14:48:41.061865 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6313 14:48:41.065294 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6314 14:48:41.068541 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6315 14:48:41.075210 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6316 14:48:41.078895 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6317 14:48:41.082108 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6318 14:48:41.085320 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6319 14:48:41.091746 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6320 14:48:41.095220 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6321 14:48:41.098642 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6322 14:48:41.101854 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6323 14:48:41.105197 ==
6324 14:48:41.105270 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 14:48:41.111778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 14:48:41.111860 ==
6327 14:48:41.111923 DQS Delay:
6328 14:48:41.114648 DQS0 = 59, DQS1 = 59
6329 14:48:41.114755 DQM Delay:
6330 14:48:41.118382 DQM0 = 18, DQM1 = 10
6331 14:48:41.118487 DQ Delay:
6332 14:48:41.122002 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6333 14:48:41.124986 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6334 14:48:41.128307 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6335 14:48:41.131670 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6336 14:48:41.131786
6337 14:48:41.131858
6338 14:48:41.131919 ==
6339 14:48:41.134473 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 14:48:41.137839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 14:48:41.137921 ==
6342 14:48:41.138001
6343 14:48:41.138062
6344 14:48:41.141454 TX Vref Scan disable
6345 14:48:41.141536 == TX Byte 0 ==
6346 14:48:41.148175 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 14:48:41.151360 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 14:48:41.151461 == TX Byte 1 ==
6349 14:48:41.157889 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 14:48:41.161085 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 14:48:41.161168 ==
6352 14:48:41.164466 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 14:48:41.167944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 14:48:41.168055 ==
6355 14:48:41.168148
6356 14:48:41.168244
6357 14:48:41.171357 TX Vref Scan disable
6358 14:48:41.174205 == TX Byte 0 ==
6359 14:48:41.177464 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 14:48:41.181146 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 14:48:41.184394 == TX Byte 1 ==
6362 14:48:41.187338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 14:48:41.190649 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 14:48:41.190729
6365 14:48:41.190791 [DATLAT]
6366 14:48:41.194290 Freq=400, CH0 RK0
6367 14:48:41.194432
6368 14:48:41.194505 DATLAT Default: 0xf
6369 14:48:41.197434 0, 0xFFFF, sum = 0
6370 14:48:41.197562 1, 0xFFFF, sum = 0
6371 14:48:41.200575 2, 0xFFFF, sum = 0
6372 14:48:41.204267 3, 0xFFFF, sum = 0
6373 14:48:41.204375 4, 0xFFFF, sum = 0
6374 14:48:41.207725 5, 0xFFFF, sum = 0
6375 14:48:41.207808 6, 0xFFFF, sum = 0
6376 14:48:41.210416 7, 0xFFFF, sum = 0
6377 14:48:41.210497 8, 0xFFFF, sum = 0
6378 14:48:41.213943 9, 0xFFFF, sum = 0
6379 14:48:41.214231 10, 0xFFFF, sum = 0
6380 14:48:41.217313 11, 0xFFFF, sum = 0
6381 14:48:41.217413 12, 0xFFFF, sum = 0
6382 14:48:41.220574 13, 0x0, sum = 1
6383 14:48:41.220670 14, 0x0, sum = 2
6384 14:48:41.223926 15, 0x0, sum = 3
6385 14:48:41.224137 16, 0x0, sum = 4
6386 14:48:41.226950 best_step = 14
6387 14:48:41.227029
6388 14:48:41.227092 ==
6389 14:48:41.230879 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 14:48:41.233635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 14:48:41.233747 ==
6392 14:48:41.233836 RX Vref Scan: 1
6393 14:48:41.236896
6394 14:48:41.236987 RX Vref 0 -> 0, step: 1
6395 14:48:41.237052
6396 14:48:41.240275 RX Delay -359 -> 252, step: 8
6397 14:48:41.240355
6398 14:48:41.243610 Set Vref, RX VrefLevel [Byte0]: 62
6399 14:48:41.246856 [Byte1]: 58
6400 14:48:41.251505
6401 14:48:41.251608 Final RX Vref Byte 0 = 62 to rank0
6402 14:48:41.254729 Final RX Vref Byte 1 = 58 to rank0
6403 14:48:41.258270 Final RX Vref Byte 0 = 62 to rank1
6404 14:48:41.261555 Final RX Vref Byte 1 = 58 to rank1==
6405 14:48:41.264482 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 14:48:41.270956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 14:48:41.271063 ==
6408 14:48:41.271155 DQS Delay:
6409 14:48:41.274328 DQS0 = 60, DQS1 = 68
6410 14:48:41.274408 DQM Delay:
6411 14:48:41.274471 DQM0 = 14, DQM1 = 14
6412 14:48:41.277929 DQ Delay:
6413 14:48:41.281225 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6414 14:48:41.284472 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6415 14:48:41.284616 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6416 14:48:41.291111 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6417 14:48:41.291233
6418 14:48:41.291345
6419 14:48:41.297624 [DQSOSCAuto] RK0, (LSB)MR18= 0x8887, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6420 14:48:41.301093 CH0 RK0: MR19=C0C, MR18=8887
6421 14:48:41.307299 CH0_RK0: MR19=0xC0C, MR18=0x8887, DQSOSC=392, MR23=63, INC=384, DEC=256
6422 14:48:41.307381 ==
6423 14:48:41.310697 Dram Type= 6, Freq= 0, CH_0, rank 1
6424 14:48:41.314421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 14:48:41.314548 ==
6426 14:48:41.317728 [Gating] SW mode calibration
6427 14:48:41.324265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6428 14:48:41.330605 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6429 14:48:41.333850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 14:48:41.337189 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 14:48:41.343973 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 14:48:41.347118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 14:48:41.350441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 14:48:41.357017 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 14:48:41.360442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 14:48:41.363923 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 14:48:41.370466 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 14:48:41.370548 Total UI for P1: 0, mck2ui 16
6439 14:48:41.376932 best dqsien dly found for B0: ( 0, 14, 24)
6440 14:48:41.377013 Total UI for P1: 0, mck2ui 16
6441 14:48:41.383469 best dqsien dly found for B1: ( 0, 14, 24)
6442 14:48:41.386734 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6443 14:48:41.390228 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6444 14:48:41.390310
6445 14:48:41.393653 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 14:48:41.396907 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 14:48:41.400356 [Gating] SW calibration Done
6448 14:48:41.400437 ==
6449 14:48:41.403479 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 14:48:41.406932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 14:48:41.407015 ==
6452 14:48:41.410126 RX Vref Scan: 0
6453 14:48:41.410207
6454 14:48:41.410272 RX Vref 0 -> 0, step: 1
6455 14:48:41.410331
6456 14:48:41.413509 RX Delay -410 -> 252, step: 16
6457 14:48:41.419964 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6458 14:48:41.423047 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6459 14:48:41.426664 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6460 14:48:41.429978 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6461 14:48:41.436660 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6462 14:48:41.440132 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6463 14:48:41.442801 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6464 14:48:41.446144 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6465 14:48:41.452824 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6466 14:48:41.456491 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6467 14:48:41.459494 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6468 14:48:41.462869 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6469 14:48:41.469526 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6470 14:48:41.472657 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6471 14:48:41.475895 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6472 14:48:41.482885 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6473 14:48:41.482971 ==
6474 14:48:41.486651 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 14:48:41.489219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 14:48:41.489301 ==
6477 14:48:41.489365 DQS Delay:
6478 14:48:41.492770 DQS0 = 59, DQS1 = 59
6479 14:48:41.492851 DQM Delay:
6480 14:48:41.496114 DQM0 = 16, DQM1 = 10
6481 14:48:41.496194 DQ Delay:
6482 14:48:41.499418 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6483 14:48:41.502779 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6484 14:48:41.505927 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6485 14:48:41.509262 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6486 14:48:41.509385
6487 14:48:41.509493
6488 14:48:41.509603 ==
6489 14:48:41.512618 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 14:48:41.516210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 14:48:41.516331 ==
6492 14:48:41.516444
6493 14:48:41.516548
6494 14:48:41.518838 TX Vref Scan disable
6495 14:48:41.522199 == TX Byte 0 ==
6496 14:48:41.525397 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 14:48:41.528785 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 14:48:41.532093 == TX Byte 1 ==
6499 14:48:41.535587 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6500 14:48:41.538853 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6501 14:48:41.538976 ==
6502 14:48:41.542249 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 14:48:41.545730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 14:48:41.545850 ==
6505 14:48:41.548758
6506 14:48:41.548879
6507 14:48:41.548992 TX Vref Scan disable
6508 14:48:41.552232 == TX Byte 0 ==
6509 14:48:41.555380 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 14:48:41.558718 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 14:48:41.561849 == TX Byte 1 ==
6512 14:48:41.565138 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6513 14:48:41.569051 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6514 14:48:41.569134
6515 14:48:41.569197 [DATLAT]
6516 14:48:41.572125 Freq=400, CH0 RK1
6517 14:48:41.572232
6518 14:48:41.575527 DATLAT Default: 0xe
6519 14:48:41.575648 0, 0xFFFF, sum = 0
6520 14:48:41.578601 1, 0xFFFF, sum = 0
6521 14:48:41.578705 2, 0xFFFF, sum = 0
6522 14:48:41.581988 3, 0xFFFF, sum = 0
6523 14:48:41.582072 4, 0xFFFF, sum = 0
6524 14:48:41.585202 5, 0xFFFF, sum = 0
6525 14:48:41.585285 6, 0xFFFF, sum = 0
6526 14:48:41.588578 7, 0xFFFF, sum = 0
6527 14:48:41.588661 8, 0xFFFF, sum = 0
6528 14:48:41.592104 9, 0xFFFF, sum = 0
6529 14:48:41.592213 10, 0xFFFF, sum = 0
6530 14:48:41.595150 11, 0xFFFF, sum = 0
6531 14:48:41.595232 12, 0xFFFF, sum = 0
6532 14:48:41.598546 13, 0x0, sum = 1
6533 14:48:41.598630 14, 0x0, sum = 2
6534 14:48:41.601733 15, 0x0, sum = 3
6535 14:48:41.601816 16, 0x0, sum = 4
6536 14:48:41.605248 best_step = 14
6537 14:48:41.605329
6538 14:48:41.605392 ==
6539 14:48:41.608641 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 14:48:41.611772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 14:48:41.611869 ==
6542 14:48:41.614987 RX Vref Scan: 0
6543 14:48:41.615062
6544 14:48:41.615125 RX Vref 0 -> 0, step: 1
6545 14:48:41.615184
6546 14:48:41.618209 RX Delay -359 -> 252, step: 8
6547 14:48:41.626158 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6548 14:48:41.629499 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6549 14:48:41.632890 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6550 14:48:41.636324 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6551 14:48:41.642869 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6552 14:48:41.646178 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6553 14:48:41.649273 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6554 14:48:41.652725 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6555 14:48:41.659107 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6556 14:48:41.662396 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6557 14:48:41.666027 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6558 14:48:41.672790 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6559 14:48:41.675647 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6560 14:48:41.679480 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6561 14:48:41.682390 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6562 14:48:41.688925 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6563 14:48:41.689015 ==
6564 14:48:41.692391 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 14:48:41.695763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 14:48:41.695846 ==
6567 14:48:41.695916 DQS Delay:
6568 14:48:41.699254 DQS0 = 60, DQS1 = 68
6569 14:48:41.699335 DQM Delay:
6570 14:48:41.702179 DQM0 = 11, DQM1 = 14
6571 14:48:41.702261 DQ Delay:
6572 14:48:41.705525 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6573 14:48:41.709101 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6574 14:48:41.712384 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6575 14:48:41.715526 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6576 14:48:41.715608
6577 14:48:41.715672
6578 14:48:41.722285 [DQSOSCAuto] RK1, (LSB)MR18= 0xc980, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6579 14:48:41.725817 CH0 RK1: MR19=C0C, MR18=C980
6580 14:48:41.731964 CH0_RK1: MR19=0xC0C, MR18=0xC980, DQSOSC=384, MR23=63, INC=400, DEC=267
6581 14:48:41.735191 [RxdqsGatingPostProcess] freq 400
6582 14:48:41.741807 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6583 14:48:41.745217 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 14:48:41.745299 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 14:48:41.748506 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 14:48:41.751979 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 14:48:41.755050 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 14:48:41.758543 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 14:48:41.762001 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 14:48:41.765638 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 14:48:41.768271 Pre-setting of DQS Precalculation
6592 14:48:41.774994 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6593 14:48:41.775078 ==
6594 14:48:41.778173 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 14:48:41.781466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 14:48:41.781550 ==
6597 14:48:41.788020 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 14:48:41.794785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6599 14:48:41.798096 [CA 0] Center 36 (8~64) winsize 57
6600 14:48:41.798213 [CA 1] Center 36 (8~64) winsize 57
6601 14:48:41.801209 [CA 2] Center 36 (8~64) winsize 57
6602 14:48:41.804705 [CA 3] Center 36 (8~64) winsize 57
6603 14:48:41.807709 [CA 4] Center 36 (8~64) winsize 57
6604 14:48:41.811195 [CA 5] Center 36 (8~64) winsize 57
6605 14:48:41.811278
6606 14:48:41.814425 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6607 14:48:41.814508
6608 14:48:41.821172 [CATrainingPosCal] consider 1 rank data
6609 14:48:41.821256 u2DelayCellTimex100 = 270/100 ps
6610 14:48:41.824451 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 14:48:41.831070 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 14:48:41.834375 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 14:48:41.837643 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 14:48:41.841029 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 14:48:41.844314 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 14:48:41.844393
6617 14:48:41.847791 CA PerBit enable=1, Macro0, CA PI delay=36
6618 14:48:41.847873
6619 14:48:41.851041 [CBTSetCACLKResult] CA Dly = 36
6620 14:48:41.854489 CS Dly: 1 (0~32)
6621 14:48:41.854565 ==
6622 14:48:41.857460 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 14:48:41.860510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 14:48:41.860613 ==
6625 14:48:41.867340 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 14:48:41.870552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6627 14:48:41.873909 [CA 0] Center 36 (8~64) winsize 57
6628 14:48:41.877230 [CA 1] Center 36 (8~64) winsize 57
6629 14:48:41.880468 [CA 2] Center 36 (8~64) winsize 57
6630 14:48:41.884052 [CA 3] Center 36 (8~64) winsize 57
6631 14:48:41.887394 [CA 4] Center 36 (8~64) winsize 57
6632 14:48:41.890913 [CA 5] Center 36 (8~64) winsize 57
6633 14:48:41.890993
6634 14:48:41.894059 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6635 14:48:41.894150
6636 14:48:41.897009 [CATrainingPosCal] consider 2 rank data
6637 14:48:41.900241 u2DelayCellTimex100 = 270/100 ps
6638 14:48:41.903771 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 14:48:41.907233 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 14:48:41.910412 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 14:48:41.917171 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 14:48:41.920193 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 14:48:41.923555 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 14:48:41.923638
6645 14:48:41.926660 CA PerBit enable=1, Macro0, CA PI delay=36
6646 14:48:41.926768
6647 14:48:41.930286 [CBTSetCACLKResult] CA Dly = 36
6648 14:48:41.930387 CS Dly: 1 (0~32)
6649 14:48:41.930477
6650 14:48:41.933543 ----->DramcWriteLeveling(PI) begin...
6651 14:48:41.936501 ==
6652 14:48:41.940196 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 14:48:41.943185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 14:48:41.943267 ==
6655 14:48:41.946938 Write leveling (Byte 0): 40 => 8
6656 14:48:41.949845 Write leveling (Byte 1): 40 => 8
6657 14:48:41.953265 DramcWriteLeveling(PI) end<-----
6658 14:48:41.953346
6659 14:48:41.953409 ==
6660 14:48:41.956655 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 14:48:41.959948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 14:48:41.960021 ==
6663 14:48:41.963491 [Gating] SW mode calibration
6664 14:48:41.970141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6665 14:48:41.973339 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6666 14:48:41.980233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 14:48:41.983051 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 14:48:41.986782 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 14:48:41.993253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 14:48:41.996845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 14:48:42.000185 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 14:48:42.006777 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 14:48:42.009888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 14:48:42.012971 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 14:48:42.016415 Total UI for P1: 0, mck2ui 16
6676 14:48:42.019565 best dqsien dly found for B0: ( 0, 14, 24)
6677 14:48:42.022934 Total UI for P1: 0, mck2ui 16
6678 14:48:42.026188 best dqsien dly found for B1: ( 0, 14, 24)
6679 14:48:42.029853 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6680 14:48:42.036221 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6681 14:48:42.036303
6682 14:48:42.039841 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 14:48:42.043086 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 14:48:42.045916 [Gating] SW calibration Done
6685 14:48:42.045998 ==
6686 14:48:42.049374 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 14:48:42.052997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 14:48:42.053107 ==
6689 14:48:42.055892 RX Vref Scan: 0
6690 14:48:42.055975
6691 14:48:42.056039 RX Vref 0 -> 0, step: 1
6692 14:48:42.056101
6693 14:48:42.059128 RX Delay -410 -> 252, step: 16
6694 14:48:42.062687 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6695 14:48:42.069132 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6696 14:48:42.072648 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6697 14:48:42.076001 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6698 14:48:42.078863 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6699 14:48:42.085618 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6700 14:48:42.088900 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6701 14:48:42.092125 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6702 14:48:42.095848 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6703 14:48:42.102613 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6704 14:48:42.105314 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6705 14:48:42.108962 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6706 14:48:42.115644 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6707 14:48:42.119025 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6708 14:48:42.122398 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6709 14:48:42.125378 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6710 14:48:42.125458 ==
6711 14:48:42.128709 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 14:48:42.135307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 14:48:42.135420 ==
6714 14:48:42.135484 DQS Delay:
6715 14:48:42.138813 DQS0 = 51, DQS1 = 67
6716 14:48:42.138893 DQM Delay:
6717 14:48:42.142422 DQM0 = 12, DQM1 = 19
6718 14:48:42.142522 DQ Delay:
6719 14:48:42.145589 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6720 14:48:42.148604 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6721 14:48:42.148711 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6722 14:48:42.155217 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6723 14:48:42.155298
6724 14:48:42.155392
6725 14:48:42.155451 ==
6726 14:48:42.158567 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 14:48:42.162217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 14:48:42.162314 ==
6729 14:48:42.162392
6730 14:48:42.162451
6731 14:48:42.165362 TX Vref Scan disable
6732 14:48:42.165457 == TX Byte 0 ==
6733 14:48:42.171638 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 14:48:42.175147 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 14:48:42.175228 == TX Byte 1 ==
6736 14:48:42.178551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 14:48:42.185336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 14:48:42.185419 ==
6739 14:48:42.188814 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 14:48:42.191649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 14:48:42.191729 ==
6742 14:48:42.191792
6743 14:48:42.191850
6744 14:48:42.194997 TX Vref Scan disable
6745 14:48:42.195071 == TX Byte 0 ==
6746 14:48:42.201460 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 14:48:42.204717 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 14:48:42.204794 == TX Byte 1 ==
6749 14:48:42.211474 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 14:48:42.214753 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 14:48:42.214829
6752 14:48:42.214892 [DATLAT]
6753 14:48:42.218308 Freq=400, CH1 RK0
6754 14:48:42.218391
6755 14:48:42.218458 DATLAT Default: 0xf
6756 14:48:42.221395 0, 0xFFFF, sum = 0
6757 14:48:42.221465 1, 0xFFFF, sum = 0
6758 14:48:42.225105 2, 0xFFFF, sum = 0
6759 14:48:42.225178 3, 0xFFFF, sum = 0
6760 14:48:42.228218 4, 0xFFFF, sum = 0
6761 14:48:42.228289 5, 0xFFFF, sum = 0
6762 14:48:42.231395 6, 0xFFFF, sum = 0
6763 14:48:42.231494 7, 0xFFFF, sum = 0
6764 14:48:42.235243 8, 0xFFFF, sum = 0
6765 14:48:42.235317 9, 0xFFFF, sum = 0
6766 14:48:42.238074 10, 0xFFFF, sum = 0
6767 14:48:42.238146 11, 0xFFFF, sum = 0
6768 14:48:42.241506 12, 0xFFFF, sum = 0
6769 14:48:42.241584 13, 0x0, sum = 1
6770 14:48:42.244776 14, 0x0, sum = 2
6771 14:48:42.244850 15, 0x0, sum = 3
6772 14:48:42.247992 16, 0x0, sum = 4
6773 14:48:42.248065 best_step = 14
6774 14:48:42.248127
6775 14:48:42.248191 ==
6776 14:48:42.251611 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 14:48:42.257904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 14:48:42.257987 ==
6779 14:48:42.258051 RX Vref Scan: 1
6780 14:48:42.258111
6781 14:48:42.261247 RX Vref 0 -> 0, step: 1
6782 14:48:42.261329
6783 14:48:42.264546 RX Delay -375 -> 252, step: 8
6784 14:48:42.264626
6785 14:48:42.268067 Set Vref, RX VrefLevel [Byte0]: 59
6786 14:48:42.271478 [Byte1]: 54
6787 14:48:42.274653
6788 14:48:42.274734 Final RX Vref Byte 0 = 59 to rank0
6789 14:48:42.278230 Final RX Vref Byte 1 = 54 to rank0
6790 14:48:42.281199 Final RX Vref Byte 0 = 59 to rank1
6791 14:48:42.284356 Final RX Vref Byte 1 = 54 to rank1==
6792 14:48:42.287749 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 14:48:42.294399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 14:48:42.294483 ==
6795 14:48:42.294553 DQS Delay:
6796 14:48:42.297872 DQS0 = 56, DQS1 = 64
6797 14:48:42.297960 DQM Delay:
6798 14:48:42.298026 DQM0 = 13, DQM1 = 10
6799 14:48:42.300845 DQ Delay:
6800 14:48:42.304321 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6801 14:48:42.307666 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6802 14:48:42.307748 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6803 14:48:42.314028 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6804 14:48:42.314109
6805 14:48:42.314172
6806 14:48:42.320675 [DQSOSCAuto] RK0, (LSB)MR18= 0x596d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6807 14:48:42.323966 CH1 RK0: MR19=C0C, MR18=596D
6808 14:48:42.330564 CH1_RK0: MR19=0xC0C, MR18=0x596D, DQSOSC=396, MR23=63, INC=376, DEC=251
6809 14:48:42.330644 ==
6810 14:48:42.333848 Dram Type= 6, Freq= 0, CH_1, rank 1
6811 14:48:42.337222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 14:48:42.337304 ==
6813 14:48:42.340512 [Gating] SW mode calibration
6814 14:48:42.347489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6815 14:48:42.353669 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6816 14:48:42.357042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 14:48:42.360438 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 14:48:42.366977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 14:48:42.370257 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 14:48:42.373433 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 14:48:42.380282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 14:48:42.383508 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 14:48:42.386797 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 14:48:42.393616 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 14:48:42.393727 Total UI for P1: 0, mck2ui 16
6826 14:48:42.399883 best dqsien dly found for B0: ( 0, 14, 24)
6827 14:48:42.400013 Total UI for P1: 0, mck2ui 16
6828 14:48:42.406921 best dqsien dly found for B1: ( 0, 14, 24)
6829 14:48:42.410194 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6830 14:48:42.413530 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6831 14:48:42.413652
6832 14:48:42.416948 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 14:48:42.420144 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 14:48:42.423462 [Gating] SW calibration Done
6835 14:48:42.423585 ==
6836 14:48:42.426842 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 14:48:42.430200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 14:48:42.430324 ==
6839 14:48:42.433223 RX Vref Scan: 0
6840 14:48:42.433346
6841 14:48:42.433457 RX Vref 0 -> 0, step: 1
6842 14:48:42.433568
6843 14:48:42.436857 RX Delay -410 -> 252, step: 16
6844 14:48:42.443345 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6845 14:48:42.446242 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6846 14:48:42.449896 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6847 14:48:42.453139 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6848 14:48:42.459788 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6849 14:48:42.462941 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6850 14:48:42.466713 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6851 14:48:42.469787 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6852 14:48:42.476232 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6853 14:48:42.479524 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6854 14:48:42.483139 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6855 14:48:42.486658 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6856 14:48:42.493308 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6857 14:48:42.496635 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6858 14:48:42.499711 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6859 14:48:42.502767 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6860 14:48:42.506037 ==
6861 14:48:42.509459 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 14:48:42.512772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 14:48:42.512884 ==
6864 14:48:42.512978 DQS Delay:
6865 14:48:42.516077 DQS0 = 59, DQS1 = 67
6866 14:48:42.516155 DQM Delay:
6867 14:48:42.519294 DQM0 = 19, DQM1 = 21
6868 14:48:42.519377 DQ Delay:
6869 14:48:42.522528 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6870 14:48:42.526014 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6871 14:48:42.529327 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6872 14:48:42.532503 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6873 14:48:42.532593
6874 14:48:42.532658
6875 14:48:42.532719 ==
6876 14:48:42.535890 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 14:48:42.539288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 14:48:42.539396 ==
6879 14:48:42.539492
6880 14:48:42.539582
6881 14:48:42.542712 TX Vref Scan disable
6882 14:48:42.546090 == TX Byte 0 ==
6883 14:48:42.549377 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 14:48:42.552232 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 14:48:42.556040 == TX Byte 1 ==
6886 14:48:42.558828 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6887 14:48:42.562841 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6888 14:48:42.562923 ==
6889 14:48:42.565911 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 14:48:42.568828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 14:48:42.568911 ==
6892 14:48:42.568976
6893 14:48:42.572351
6894 14:48:42.572432 TX Vref Scan disable
6895 14:48:42.575884 == TX Byte 0 ==
6896 14:48:42.579183 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 14:48:42.582350 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 14:48:42.586297 == TX Byte 1 ==
6899 14:48:42.589032 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6900 14:48:42.592287 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6901 14:48:42.592370
6902 14:48:42.592436 [DATLAT]
6903 14:48:42.595704 Freq=400, CH1 RK1
6904 14:48:42.595787
6905 14:48:42.595853 DATLAT Default: 0xe
6906 14:48:42.598992 0, 0xFFFF, sum = 0
6907 14:48:42.599075 1, 0xFFFF, sum = 0
6908 14:48:42.602349 2, 0xFFFF, sum = 0
6909 14:48:42.605781 3, 0xFFFF, sum = 0
6910 14:48:42.605865 4, 0xFFFF, sum = 0
6911 14:48:42.608870 5, 0xFFFF, sum = 0
6912 14:48:42.608956 6, 0xFFFF, sum = 0
6913 14:48:42.612507 7, 0xFFFF, sum = 0
6914 14:48:42.612615 8, 0xFFFF, sum = 0
6915 14:48:42.615437 9, 0xFFFF, sum = 0
6916 14:48:42.615548 10, 0xFFFF, sum = 0
6917 14:48:42.619424 11, 0xFFFF, sum = 0
6918 14:48:42.619537 12, 0xFFFF, sum = 0
6919 14:48:42.622129 13, 0x0, sum = 1
6920 14:48:42.622212 14, 0x0, sum = 2
6921 14:48:42.625584 15, 0x0, sum = 3
6922 14:48:42.625668 16, 0x0, sum = 4
6923 14:48:42.629004 best_step = 14
6924 14:48:42.629086
6925 14:48:42.629151 ==
6926 14:48:42.631856 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 14:48:42.635148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 14:48:42.635261 ==
6929 14:48:42.635353 RX Vref Scan: 0
6930 14:48:42.638608
6931 14:48:42.638690 RX Vref 0 -> 0, step: 1
6932 14:48:42.638755
6933 14:48:42.641927 RX Delay -375 -> 252, step: 8
6934 14:48:42.649624 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6935 14:48:42.652924 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6936 14:48:42.656301 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6937 14:48:42.659528 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6938 14:48:42.666155 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6939 14:48:42.669366 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6940 14:48:42.672528 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6941 14:48:42.676058 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6942 14:48:42.682832 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6943 14:48:42.686185 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6944 14:48:42.689276 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6945 14:48:42.695801 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
6946 14:48:42.699413 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6947 14:48:42.702321 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6948 14:48:42.706014 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6949 14:48:42.713144 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6950 14:48:42.713281 ==
6951 14:48:42.716067 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 14:48:42.719255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 14:48:42.719337 ==
6954 14:48:42.719401 DQS Delay:
6955 14:48:42.722255 DQS0 = 60, DQS1 = 64
6956 14:48:42.722335 DQM Delay:
6957 14:48:42.725522 DQM0 = 13, DQM1 = 11
6958 14:48:42.725604 DQ Delay:
6959 14:48:42.729148 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6960 14:48:42.732372 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6961 14:48:42.735362 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6962 14:48:42.738598 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6963 14:48:42.738720
6964 14:48:42.738824
6965 14:48:42.745265 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aa9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6966 14:48:42.748449 CH1 RK1: MR19=C0C, MR18=7AA9
6967 14:48:42.755179 CH1_RK1: MR19=0xC0C, MR18=0x7AA9, DQSOSC=388, MR23=63, INC=392, DEC=261
6968 14:48:42.758602 [RxdqsGatingPostProcess] freq 400
6969 14:48:42.765196 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6970 14:48:42.768705 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 14:48:42.771958 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 14:48:42.775353 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 14:48:42.778686 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 14:48:42.778767 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 14:48:42.781667 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 14:48:42.785287 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 14:48:42.788217 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 14:48:42.791621 Pre-setting of DQS Precalculation
6979 14:48:42.798676 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6980 14:48:42.805385 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6981 14:48:42.811397 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6982 14:48:42.811522
6983 14:48:42.811635
6984 14:48:42.815315 [Calibration Summary] 800 Mbps
6985 14:48:42.815419 CH 0, Rank 0
6986 14:48:42.818401 SW Impedance : PASS
6987 14:48:42.821511 DUTY Scan : NO K
6988 14:48:42.821621 ZQ Calibration : PASS
6989 14:48:42.824739 Jitter Meter : NO K
6990 14:48:42.828451 CBT Training : PASS
6991 14:48:42.828578 Write leveling : PASS
6992 14:48:42.831233 RX DQS gating : PASS
6993 14:48:42.834515 RX DQ/DQS(RDDQC) : PASS
6994 14:48:42.834643 TX DQ/DQS : PASS
6995 14:48:42.838057 RX DATLAT : PASS
6996 14:48:42.841420 RX DQ/DQS(Engine): PASS
6997 14:48:42.841544 TX OE : NO K
6998 14:48:42.844720 All Pass.
6999 14:48:42.844844
7000 14:48:42.844957 CH 0, Rank 1
7001 14:48:42.847980 SW Impedance : PASS
7002 14:48:42.848103 DUTY Scan : NO K
7003 14:48:42.851053 ZQ Calibration : PASS
7004 14:48:42.854783 Jitter Meter : NO K
7005 14:48:42.854905 CBT Training : PASS
7006 14:48:42.858110 Write leveling : NO K
7007 14:48:42.858236 RX DQS gating : PASS
7008 14:48:42.861449 RX DQ/DQS(RDDQC) : PASS
7009 14:48:42.864953 TX DQ/DQS : PASS
7010 14:48:42.865078 RX DATLAT : PASS
7011 14:48:42.868138 RX DQ/DQS(Engine): PASS
7012 14:48:42.871367 TX OE : NO K
7013 14:48:42.871485 All Pass.
7014 14:48:42.871600
7015 14:48:42.871703 CH 1, Rank 0
7016 14:48:42.874350 SW Impedance : PASS
7017 14:48:42.878054 DUTY Scan : NO K
7018 14:48:42.878175 ZQ Calibration : PASS
7019 14:48:42.880971 Jitter Meter : NO K
7020 14:48:42.884240 CBT Training : PASS
7021 14:48:42.884364 Write leveling : PASS
7022 14:48:42.887674 RX DQS gating : PASS
7023 14:48:42.890912 RX DQ/DQS(RDDQC) : PASS
7024 14:48:42.891031 TX DQ/DQS : PASS
7025 14:48:42.894493 RX DATLAT : PASS
7026 14:48:42.897944 RX DQ/DQS(Engine): PASS
7027 14:48:42.898067 TX OE : NO K
7028 14:48:42.900812 All Pass.
7029 14:48:42.900936
7030 14:48:42.901049 CH 1, Rank 1
7031 14:48:42.904280 SW Impedance : PASS
7032 14:48:42.904403 DUTY Scan : NO K
7033 14:48:42.907635 ZQ Calibration : PASS
7034 14:48:42.910926 Jitter Meter : NO K
7035 14:48:42.911051 CBT Training : PASS
7036 14:48:42.913987 Write leveling : NO K
7037 14:48:42.917279 RX DQS gating : PASS
7038 14:48:42.917357 RX DQ/DQS(RDDQC) : PASS
7039 14:48:42.920554 TX DQ/DQS : PASS
7040 14:48:42.920633 RX DATLAT : PASS
7041 14:48:42.923889 RX DQ/DQS(Engine): PASS
7042 14:48:42.927230 TX OE : NO K
7043 14:48:42.927321 All Pass.
7044 14:48:42.927431
7045 14:48:42.930481 DramC Write-DBI off
7046 14:48:42.933777 PER_BANK_REFRESH: Hybrid Mode
7047 14:48:42.933900 TX_TRACKING: ON
7048 14:48:42.943553 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7049 14:48:42.946971 [FAST_K] Save calibration result to emmc
7050 14:48:42.950665 dramc_set_vcore_voltage set vcore to 725000
7051 14:48:42.953841 Read voltage for 1600, 0
7052 14:48:42.953962 Vio18 = 0
7053 14:48:42.954076 Vcore = 725000
7054 14:48:42.957213 Vdram = 0
7055 14:48:42.957333 Vddq = 0
7056 14:48:42.957447 Vmddr = 0
7057 14:48:42.963586 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7058 14:48:42.967030 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7059 14:48:42.970282 MEM_TYPE=3, freq_sel=13
7060 14:48:42.973690 sv_algorithm_assistance_LP4_3733
7061 14:48:42.977179 ============ PULL DRAM RESETB DOWN ============
7062 14:48:42.979859 ========== PULL DRAM RESETB DOWN end =========
7063 14:48:42.986567 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7064 14:48:42.989919 ===================================
7065 14:48:42.990003 LPDDR4 DRAM CONFIGURATION
7066 14:48:42.993257 ===================================
7067 14:48:42.996506 EX_ROW_EN[0] = 0x0
7068 14:48:42.999612 EX_ROW_EN[1] = 0x0
7069 14:48:42.999694 LP4Y_EN = 0x0
7070 14:48:43.003603 WORK_FSP = 0x1
7071 14:48:43.003711 WL = 0x5
7072 14:48:43.006359 RL = 0x5
7073 14:48:43.006452 BL = 0x2
7074 14:48:43.009944 RPST = 0x0
7075 14:48:43.010053 RD_PRE = 0x0
7076 14:48:43.013650 WR_PRE = 0x1
7077 14:48:43.013748 WR_PST = 0x1
7078 14:48:43.016375 DBI_WR = 0x0
7079 14:48:43.016506 DBI_RD = 0x0
7080 14:48:43.019760 OTF = 0x1
7081 14:48:43.023376 ===================================
7082 14:48:43.026284 ===================================
7083 14:48:43.026408 ANA top config
7084 14:48:43.029716 ===================================
7085 14:48:43.032970 DLL_ASYNC_EN = 0
7086 14:48:43.036473 ALL_SLAVE_EN = 0
7087 14:48:43.039545 NEW_RANK_MODE = 1
7088 14:48:43.039634 DLL_IDLE_MODE = 1
7089 14:48:43.042692 LP45_APHY_COMB_EN = 1
7090 14:48:43.046140 TX_ODT_DIS = 0
7091 14:48:43.049310 NEW_8X_MODE = 1
7092 14:48:43.052790 ===================================
7093 14:48:43.055888 ===================================
7094 14:48:43.059647 data_rate = 3200
7095 14:48:43.059730 CKR = 1
7096 14:48:43.062802 DQ_P2S_RATIO = 8
7097 14:48:43.066201 ===================================
7098 14:48:43.069514 CA_P2S_RATIO = 8
7099 14:48:43.072602 DQ_CA_OPEN = 0
7100 14:48:43.076121 DQ_SEMI_OPEN = 0
7101 14:48:43.079636 CA_SEMI_OPEN = 0
7102 14:48:43.079718 CA_FULL_RATE = 0
7103 14:48:43.082697 DQ_CKDIV4_EN = 0
7104 14:48:43.086167 CA_CKDIV4_EN = 0
7105 14:48:43.089547 CA_PREDIV_EN = 0
7106 14:48:43.092812 PH8_DLY = 12
7107 14:48:43.095643 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7108 14:48:43.095725 DQ_AAMCK_DIV = 4
7109 14:48:43.099426 CA_AAMCK_DIV = 4
7110 14:48:43.102406 CA_ADMCK_DIV = 4
7111 14:48:43.105686 DQ_TRACK_CA_EN = 0
7112 14:48:43.109141 CA_PICK = 1600
7113 14:48:43.112414 CA_MCKIO = 1600
7114 14:48:43.115867 MCKIO_SEMI = 0
7115 14:48:43.118900 PLL_FREQ = 3068
7116 14:48:43.119003 DQ_UI_PI_RATIO = 32
7117 14:48:43.122517 CA_UI_PI_RATIO = 0
7118 14:48:43.125845 ===================================
7119 14:48:43.128990 ===================================
7120 14:48:43.132355 memory_type:LPDDR4
7121 14:48:43.135560 GP_NUM : 10
7122 14:48:43.135677 SRAM_EN : 1
7123 14:48:43.138723 MD32_EN : 0
7124 14:48:43.141948 ===================================
7125 14:48:43.145650 [ANA_INIT] >>>>>>>>>>>>>>
7126 14:48:43.145732 <<<<<< [CONFIGURE PHASE]: ANA_TX
7127 14:48:43.148897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7128 14:48:43.152148 ===================================
7129 14:48:43.155347 data_rate = 3200,PCW = 0X7600
7130 14:48:43.159147 ===================================
7131 14:48:43.161886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7132 14:48:43.168687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 14:48:43.175362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 14:48:43.178494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7135 14:48:43.181821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7136 14:48:43.185639 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7137 14:48:43.188538 [ANA_INIT] flow start
7138 14:48:43.188669 [ANA_INIT] PLL >>>>>>>>
7139 14:48:43.191760 [ANA_INIT] PLL <<<<<<<<
7140 14:48:43.194913 [ANA_INIT] MIDPI >>>>>>>>
7141 14:48:43.195044 [ANA_INIT] MIDPI <<<<<<<<
7142 14:48:43.198267 [ANA_INIT] DLL >>>>>>>>
7143 14:48:43.201553 [ANA_INIT] DLL <<<<<<<<
7144 14:48:43.201676 [ANA_INIT] flow end
7145 14:48:43.208284 ============ LP4 DIFF to SE enter ============
7146 14:48:43.211553 ============ LP4 DIFF to SE exit ============
7147 14:48:43.215100 [ANA_INIT] <<<<<<<<<<<<<
7148 14:48:43.218358 [Flow] Enable top DCM control >>>>>
7149 14:48:43.221662 [Flow] Enable top DCM control <<<<<
7150 14:48:43.221783 Enable DLL master slave shuffle
7151 14:48:43.228114 ==============================================================
7152 14:48:43.231559 Gating Mode config
7153 14:48:43.235282 ==============================================================
7154 14:48:43.237943 Config description:
7155 14:48:43.248227 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7156 14:48:43.255061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7157 14:48:43.258183 SELPH_MODE 0: By rank 1: By Phase
7158 14:48:43.264909 ==============================================================
7159 14:48:43.268222 GAT_TRACK_EN = 1
7160 14:48:43.271644 RX_GATING_MODE = 2
7161 14:48:43.274844 RX_GATING_TRACK_MODE = 2
7162 14:48:43.277880 SELPH_MODE = 1
7163 14:48:43.281373 PICG_EARLY_EN = 1
7164 14:48:43.281482 VALID_LAT_VALUE = 1
7165 14:48:43.288416 ==============================================================
7166 14:48:43.291277 Enter into Gating configuration >>>>
7167 14:48:43.294446 Exit from Gating configuration <<<<
7168 14:48:43.298251 Enter into DVFS_PRE_config >>>>>
7169 14:48:43.308116 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7170 14:48:43.310981 Exit from DVFS_PRE_config <<<<<
7171 14:48:43.314403 Enter into PICG configuration >>>>
7172 14:48:43.318165 Exit from PICG configuration <<<<
7173 14:48:43.320960 [RX_INPUT] configuration >>>>>
7174 14:48:43.324272 [RX_INPUT] configuration <<<<<
7175 14:48:43.327526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7176 14:48:43.334269 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7177 14:48:43.340827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 14:48:43.347442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 14:48:43.354127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7180 14:48:43.360966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7181 14:48:43.364489 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7182 14:48:43.367966 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7183 14:48:43.371050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7184 14:48:43.374112 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7185 14:48:43.380867 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7186 14:48:43.384337 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 14:48:43.387471 ===================================
7188 14:48:43.391148 LPDDR4 DRAM CONFIGURATION
7189 14:48:43.394116 ===================================
7190 14:48:43.394241 EX_ROW_EN[0] = 0x0
7191 14:48:43.397417 EX_ROW_EN[1] = 0x0
7192 14:48:43.397501 LP4Y_EN = 0x0
7193 14:48:43.400855 WORK_FSP = 0x1
7194 14:48:43.400937 WL = 0x5
7195 14:48:43.404229 RL = 0x5
7196 14:48:43.407522 BL = 0x2
7197 14:48:43.407605 RPST = 0x0
7198 14:48:43.410721 RD_PRE = 0x0
7199 14:48:43.410804 WR_PRE = 0x1
7200 14:48:43.413938 WR_PST = 0x1
7201 14:48:43.414021 DBI_WR = 0x0
7202 14:48:43.417228 DBI_RD = 0x0
7203 14:48:43.417311 OTF = 0x1
7204 14:48:43.420844 ===================================
7205 14:48:43.424300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7206 14:48:43.430810 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7207 14:48:43.434184 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 14:48:43.436973 ===================================
7209 14:48:43.440259 LPDDR4 DRAM CONFIGURATION
7210 14:48:43.443669 ===================================
7211 14:48:43.443751 EX_ROW_EN[0] = 0x10
7212 14:48:43.447118 EX_ROW_EN[1] = 0x0
7213 14:48:43.447201 LP4Y_EN = 0x0
7214 14:48:43.450462 WORK_FSP = 0x1
7215 14:48:43.450545 WL = 0x5
7216 14:48:43.453810 RL = 0x5
7217 14:48:43.453893 BL = 0x2
7218 14:48:43.457077 RPST = 0x0
7219 14:48:43.460145 RD_PRE = 0x0
7220 14:48:43.460227 WR_PRE = 0x1
7221 14:48:43.463618 WR_PST = 0x1
7222 14:48:43.463701 DBI_WR = 0x0
7223 14:48:43.466619 DBI_RD = 0x0
7224 14:48:43.466702 OTF = 0x1
7225 14:48:43.470254 ===================================
7226 14:48:43.476671 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7227 14:48:43.476755 ==
7228 14:48:43.479945 Dram Type= 6, Freq= 0, CH_0, rank 0
7229 14:48:43.483347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7230 14:48:43.483430 ==
7231 14:48:43.486536 [Duty_Offset_Calibration]
7232 14:48:43.489931 B0:2 B1:0 CA:3
7233 14:48:43.490015
7234 14:48:43.493116 [DutyScan_Calibration_Flow] k_type=0
7235 14:48:43.501862
7236 14:48:43.501986 ==CLK 0==
7237 14:48:43.505061 Final CLK duty delay cell = 0
7238 14:48:43.508143 [0] MAX Duty = 5031%(X100), DQS PI = 12
7239 14:48:43.511612 [0] MIN Duty = 4907%(X100), DQS PI = 6
7240 14:48:43.511734 [0] AVG Duty = 4969%(X100)
7241 14:48:43.514707
7242 14:48:43.514830 CH0 CLK Duty spec in!! Max-Min= 124%
7243 14:48:43.521710 [DutyScan_Calibration_Flow] ====Done====
7244 14:48:43.521836
7245 14:48:43.524550 [DutyScan_Calibration_Flow] k_type=1
7246 14:48:43.541511
7247 14:48:43.541603 ==DQS 0 ==
7248 14:48:43.544728 Final DQS duty delay cell = 0
7249 14:48:43.548097 [0] MAX Duty = 5094%(X100), DQS PI = 30
7250 14:48:43.551522 [0] MIN Duty = 4875%(X100), DQS PI = 0
7251 14:48:43.551597 [0] AVG Duty = 4984%(X100)
7252 14:48:43.554712
7253 14:48:43.554784 ==DQS 1 ==
7254 14:48:43.558143 Final DQS duty delay cell = 0
7255 14:48:43.561238 [0] MAX Duty = 5156%(X100), DQS PI = 32
7256 14:48:43.564501 [0] MIN Duty = 5031%(X100), DQS PI = 12
7257 14:48:43.567654 [0] AVG Duty = 5093%(X100)
7258 14:48:43.567774
7259 14:48:43.571394 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7260 14:48:43.571523
7261 14:48:43.574285 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7262 14:48:43.577636 [DutyScan_Calibration_Flow] ====Done====
7263 14:48:43.577789
7264 14:48:43.580924 [DutyScan_Calibration_Flow] k_type=3
7265 14:48:43.599401
7266 14:48:43.599562 ==DQM 0 ==
7267 14:48:43.602470 Final DQM duty delay cell = 0
7268 14:48:43.606098 [0] MAX Duty = 5156%(X100), DQS PI = 32
7269 14:48:43.609132 [0] MIN Duty = 4844%(X100), DQS PI = 48
7270 14:48:43.612386 [0] AVG Duty = 5000%(X100)
7271 14:48:43.612518
7272 14:48:43.612638 ==DQM 1 ==
7273 14:48:43.615951 Final DQM duty delay cell = 4
7274 14:48:43.618765 [4] MAX Duty = 5187%(X100), DQS PI = 60
7275 14:48:43.622088 [4] MIN Duty = 5000%(X100), DQS PI = 14
7276 14:48:43.625427 [4] AVG Duty = 5093%(X100)
7277 14:48:43.625561
7278 14:48:43.628712 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7279 14:48:43.628836
7280 14:48:43.631997 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7281 14:48:43.635374 [DutyScan_Calibration_Flow] ====Done====
7282 14:48:43.635498
7283 14:48:43.638748 [DutyScan_Calibration_Flow] k_type=2
7284 14:48:43.655382
7285 14:48:43.655513 ==DQ 0 ==
7286 14:48:43.658758 Final DQ duty delay cell = -4
7287 14:48:43.661797 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7288 14:48:43.665217 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7289 14:48:43.668445 [-4] AVG Duty = 4938%(X100)
7290 14:48:43.668575
7291 14:48:43.668689 ==DQ 1 ==
7292 14:48:43.672031 Final DQ duty delay cell = 0
7293 14:48:43.675272 [0] MAX Duty = 5156%(X100), DQS PI = 58
7294 14:48:43.678470 [0] MIN Duty = 5000%(X100), DQS PI = 18
7295 14:48:43.681868 [0] AVG Duty = 5078%(X100)
7296 14:48:43.681991
7297 14:48:43.685057 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7298 14:48:43.685182
7299 14:48:43.688537 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7300 14:48:43.691643 [DutyScan_Calibration_Flow] ====Done====
7301 14:48:43.691766 ==
7302 14:48:43.695183 Dram Type= 6, Freq= 0, CH_1, rank 0
7303 14:48:43.698497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 14:48:43.698629 ==
7305 14:48:43.701804 [Duty_Offset_Calibration]
7306 14:48:43.701925 B0:1 B1:-2 CA:1
7307 14:48:43.702040
7308 14:48:43.705276 [DutyScan_Calibration_Flow] k_type=0
7309 14:48:43.716176
7310 14:48:43.716303 ==CLK 0==
7311 14:48:43.719206 Final CLK duty delay cell = 0
7312 14:48:43.722369 [0] MAX Duty = 5062%(X100), DQS PI = 20
7313 14:48:43.725633 [0] MIN Duty = 4813%(X100), DQS PI = 62
7314 14:48:43.725742 [0] AVG Duty = 4937%(X100)
7315 14:48:43.729046
7316 14:48:43.732452 CH1 CLK Duty spec in!! Max-Min= 249%
7317 14:48:43.735717 [DutyScan_Calibration_Flow] ====Done====
7318 14:48:43.735799
7319 14:48:43.738960 [DutyScan_Calibration_Flow] k_type=1
7320 14:48:43.755636
7321 14:48:43.755719 ==DQS 0 ==
7322 14:48:43.758626 Final DQS duty delay cell = 0
7323 14:48:43.762287 [0] MAX Duty = 5187%(X100), DQS PI = 24
7324 14:48:43.765146 [0] MIN Duty = 5031%(X100), DQS PI = 52
7325 14:48:43.768942 [0] AVG Duty = 5109%(X100)
7326 14:48:43.769014
7327 14:48:43.769076 ==DQS 1 ==
7328 14:48:43.771871 Final DQS duty delay cell = 0
7329 14:48:43.775283 [0] MAX Duty = 5093%(X100), DQS PI = 60
7330 14:48:43.778642 [0] MIN Duty = 4844%(X100), DQS PI = 24
7331 14:48:43.782223 [0] AVG Duty = 4968%(X100)
7332 14:48:43.782304
7333 14:48:43.785462 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7334 14:48:43.785541
7335 14:48:43.788731 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7336 14:48:43.792012 [DutyScan_Calibration_Flow] ====Done====
7337 14:48:43.792089
7338 14:48:43.794903 [DutyScan_Calibration_Flow] k_type=3
7339 14:48:43.812503
7340 14:48:43.812630 ==DQM 0 ==
7341 14:48:43.815435 Final DQM duty delay cell = 0
7342 14:48:43.819079 [0] MAX Duty = 5031%(X100), DQS PI = 24
7343 14:48:43.822011 [0] MIN Duty = 4813%(X100), DQS PI = 56
7344 14:48:43.825988 [0] AVG Duty = 4922%(X100)
7345 14:48:43.826064
7346 14:48:43.826126 ==DQM 1 ==
7347 14:48:43.829275 Final DQM duty delay cell = 0
7348 14:48:43.832324 [0] MAX Duty = 5062%(X100), DQS PI = 34
7349 14:48:43.835429 [0] MIN Duty = 4875%(X100), DQS PI = 24
7350 14:48:43.838843 [0] AVG Duty = 4968%(X100)
7351 14:48:43.838923
7352 14:48:43.841934 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7353 14:48:43.842047
7354 14:48:43.845387 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7355 14:48:43.848788 [DutyScan_Calibration_Flow] ====Done====
7356 14:48:43.848864
7357 14:48:43.852203 [DutyScan_Calibration_Flow] k_type=2
7358 14:48:43.868977
7359 14:48:43.869089 ==DQ 0 ==
7360 14:48:43.872438 Final DQ duty delay cell = 0
7361 14:48:43.875989 [0] MAX Duty = 5093%(X100), DQS PI = 20
7362 14:48:43.879163 [0] MIN Duty = 4907%(X100), DQS PI = 62
7363 14:48:43.882240 [0] AVG Duty = 5000%(X100)
7364 14:48:43.882323
7365 14:48:43.882394 ==DQ 1 ==
7366 14:48:43.885454 Final DQ duty delay cell = 0
7367 14:48:43.888796 [0] MAX Duty = 5125%(X100), DQS PI = 34
7368 14:48:43.892177 [0] MIN Duty = 4969%(X100), DQS PI = 24
7369 14:48:43.895447 [0] AVG Duty = 5047%(X100)
7370 14:48:43.895528
7371 14:48:43.898726 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7372 14:48:43.898808
7373 14:48:43.902072 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7374 14:48:43.905176 [DutyScan_Calibration_Flow] ====Done====
7375 14:48:43.908445 nWR fixed to 30
7376 14:48:43.911927 [ModeRegInit_LP4] CH0 RK0
7377 14:48:43.912003 [ModeRegInit_LP4] CH0 RK1
7378 14:48:43.915261 [ModeRegInit_LP4] CH1 RK0
7379 14:48:43.918515 [ModeRegInit_LP4] CH1 RK1
7380 14:48:43.918598 match AC timing 5
7381 14:48:43.925262 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7382 14:48:43.928500 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7383 14:48:43.931843 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7384 14:48:43.938446 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7385 14:48:43.942184 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7386 14:48:43.942266 [MiockJmeterHQA]
7387 14:48:43.942333
7388 14:48:43.944940 [DramcMiockJmeter] u1RxGatingPI = 0
7389 14:48:43.948279 0 : 4257, 4030
7390 14:48:43.948362 4 : 4258, 4030
7391 14:48:43.951631 8 : 4259, 4032
7392 14:48:43.951714 12 : 4368, 4139
7393 14:48:43.955039 16 : 4367, 4140
7394 14:48:43.955121 20 : 4255, 4029
7395 14:48:43.955187 24 : 4258, 4029
7396 14:48:43.958233 28 : 4257, 4029
7397 14:48:43.958353 32 : 4255, 4030
7398 14:48:43.962097 36 : 4257, 4032
7399 14:48:43.962180 40 : 4368, 4140
7400 14:48:43.964751 44 : 4365, 4140
7401 14:48:43.964822 48 : 4252, 4027
7402 14:48:43.968226 52 : 4253, 4029
7403 14:48:43.968334 56 : 4254, 4030
7404 14:48:43.968427 60 : 4255, 4029
7405 14:48:43.971241 64 : 4366, 4139
7406 14:48:43.971338 68 : 4365, 4140
7407 14:48:43.974692 72 : 4365, 4139
7408 14:48:43.974793 76 : 4255, 4029
7409 14:48:43.978297 80 : 4255, 4029
7410 14:48:43.978399 84 : 4255, 4029
7411 14:48:43.981388 88 : 4257, 4032
7412 14:48:43.981490 92 : 4253, 4029
7413 14:48:43.981592 96 : 4366, 4140
7414 14:48:43.984518 100 : 4255, 4029
7415 14:48:43.984624 104 : 4255, 3540
7416 14:48:43.987804 108 : 4253, 0
7417 14:48:43.987880 112 : 4255, 0
7418 14:48:43.991466 116 : 4257, 0
7419 14:48:43.991550 120 : 4250, 0
7420 14:48:43.991616 124 : 4253, 0
7421 14:48:43.994488 128 : 4257, 0
7422 14:48:43.994572 132 : 4253, 0
7423 14:48:43.994638 136 : 4363, 0
7424 14:48:43.998023 140 : 4253, 0
7425 14:48:43.998107 144 : 4252, 0
7426 14:48:44.001030 148 : 4363, 0
7427 14:48:44.001114 152 : 4253, 0
7428 14:48:44.001180 156 : 4253, 0
7429 14:48:44.004676 160 : 4252, 0
7430 14:48:44.004760 164 : 4255, 0
7431 14:48:44.007880 168 : 4253, 0
7432 14:48:44.007964 172 : 4363, 0
7433 14:48:44.008030 176 : 4363, 0
7434 14:48:44.011191 180 : 4250, 0
7435 14:48:44.011275 184 : 4253, 0
7436 14:48:44.014638 188 : 4363, 0
7437 14:48:44.014723 192 : 4252, 0
7438 14:48:44.014790 196 : 4257, 0
7439 14:48:44.017374 200 : 4252, 0
7440 14:48:44.017458 204 : 4253, 0
7441 14:48:44.020958 208 : 4252, 0
7442 14:48:44.021043 212 : 4252, 0
7443 14:48:44.021110 216 : 4255, 0
7444 14:48:44.024523 220 : 4257, 0
7445 14:48:44.024626 224 : 4363, 0
7446 14:48:44.024705 228 : 4255, 0
7447 14:48:44.027927 232 : 4363, 0
7448 14:48:44.028027 236 : 4363, 1049
7449 14:48:44.030989 240 : 4252, 4027
7450 14:48:44.031099 244 : 4368, 4143
7451 14:48:44.034249 248 : 4253, 4029
7452 14:48:44.034323 252 : 4366, 4139
7453 14:48:44.037392 256 : 4253, 4029
7454 14:48:44.037476 260 : 4252, 4029
7455 14:48:44.040891 264 : 4255, 4029
7456 14:48:44.040963 268 : 4252, 4030
7457 14:48:44.044457 272 : 4252, 4029
7458 14:48:44.044569 276 : 4367, 4143
7459 14:48:44.047562 280 : 4253, 4029
7460 14:48:44.047669 284 : 4253, 4029
7461 14:48:44.047761 288 : 4252, 4029
7462 14:48:44.050688 292 : 4257, 4032
7463 14:48:44.050790 296 : 4255, 4029
7464 14:48:44.054072 300 : 4255, 4029
7465 14:48:44.054145 304 : 4252, 4029
7466 14:48:44.056953 308 : 4257, 4032
7467 14:48:44.057058 312 : 4255, 4029
7468 14:48:44.060252 316 : 4365, 4140
7469 14:48:44.060352 320 : 4252, 4030
7470 14:48:44.063584 324 : 4252, 4029
7471 14:48:44.063687 328 : 4367, 4143
7472 14:48:44.067252 332 : 4255, 4029
7473 14:48:44.067337 336 : 4362, 4140
7474 14:48:44.070405 340 : 4366, 4139
7475 14:48:44.070482 344 : 4252, 4027
7476 14:48:44.073639 348 : 4253, 4027
7477 14:48:44.073718 352 : 4255, 4012
7478 14:48:44.073782 356 : 4363, 2644
7479 14:48:44.077008 360 : 4252, 0
7480 14:48:44.077113
7481 14:48:44.080426 MIOCK jitter meter ch=0
7482 14:48:44.080501
7483 14:48:44.080573 1T = (360-108) = 252 dly cells
7484 14:48:44.086925 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7485 14:48:44.087005 ==
7486 14:48:44.090154 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 14:48:44.093702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7488 14:48:44.096917 ==
7489 14:48:44.100088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7490 14:48:44.103660 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7491 14:48:44.110131 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7492 14:48:44.116687 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7493 14:48:44.124507 [CA 0] Center 44 (14~75) winsize 62
7494 14:48:44.127468 [CA 1] Center 43 (13~74) winsize 62
7495 14:48:44.130916 [CA 2] Center 40 (11~69) winsize 59
7496 14:48:44.134099 [CA 3] Center 39 (10~69) winsize 60
7497 14:48:44.137323 [CA 4] Center 37 (8~67) winsize 60
7498 14:48:44.140964 [CA 5] Center 37 (8~66) winsize 59
7499 14:48:44.141083
7500 14:48:44.144216 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7501 14:48:44.144318
7502 14:48:44.150976 [CATrainingPosCal] consider 1 rank data
7503 14:48:44.151083 u2DelayCellTimex100 = 258/100 ps
7504 14:48:44.157632 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7505 14:48:44.160965 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7506 14:48:44.164011 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7507 14:48:44.167514 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7508 14:48:44.170881 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7509 14:48:44.174253 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7510 14:48:44.174327
7511 14:48:44.177430 CA PerBit enable=1, Macro0, CA PI delay=37
7512 14:48:44.177514
7513 14:48:44.180877 [CBTSetCACLKResult] CA Dly = 37
7514 14:48:44.184242 CS Dly: 11 (0~42)
7515 14:48:44.187537 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7516 14:48:44.190827 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7517 14:48:44.190926 ==
7518 14:48:44.193607 Dram Type= 6, Freq= 0, CH_0, rank 1
7519 14:48:44.200358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 14:48:44.200466 ==
7521 14:48:44.203590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7522 14:48:44.210405 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7523 14:48:44.213863 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7524 14:48:44.220416 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7525 14:48:44.228285 [CA 0] Center 44 (14~75) winsize 62
7526 14:48:44.231411 [CA 1] Center 43 (13~74) winsize 62
7527 14:48:44.234798 [CA 2] Center 39 (10~69) winsize 60
7528 14:48:44.238081 [CA 3] Center 39 (10~69) winsize 60
7529 14:48:44.241837 [CA 4] Center 37 (8~67) winsize 60
7530 14:48:44.244331 [CA 5] Center 37 (7~67) winsize 61
7531 14:48:44.244433
7532 14:48:44.248130 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7533 14:48:44.248244
7534 14:48:44.251420 [CATrainingPosCal] consider 2 rank data
7535 14:48:44.254757 u2DelayCellTimex100 = 258/100 ps
7536 14:48:44.261358 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7537 14:48:44.264927 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7538 14:48:44.268091 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7539 14:48:44.271118 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7540 14:48:44.274258 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7541 14:48:44.278000 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7542 14:48:44.278082
7543 14:48:44.281274 CA PerBit enable=1, Macro0, CA PI delay=37
7544 14:48:44.281415
7545 14:48:44.284606 [CBTSetCACLKResult] CA Dly = 37
7546 14:48:44.287528 CS Dly: 11 (0~42)
7547 14:48:44.290771 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7548 14:48:44.294058 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7549 14:48:44.294179
7550 14:48:44.297371 ----->DramcWriteLeveling(PI) begin...
7551 14:48:44.297482 ==
7552 14:48:44.300786 Dram Type= 6, Freq= 0, CH_0, rank 0
7553 14:48:44.307661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 14:48:44.307745 ==
7555 14:48:44.310693 Write leveling (Byte 0): 35 => 35
7556 14:48:44.314597 Write leveling (Byte 1): 28 => 28
7557 14:48:44.314698 DramcWriteLeveling(PI) end<-----
7558 14:48:44.317220
7559 14:48:44.317301 ==
7560 14:48:44.320680 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 14:48:44.324197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 14:48:44.324269 ==
7563 14:48:44.327393 [Gating] SW mode calibration
7564 14:48:44.334068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7565 14:48:44.337234 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7566 14:48:44.344175 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 14:48:44.347151 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 14:48:44.350945 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 14:48:44.357371 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 14:48:44.360708 1 4 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7571 14:48:44.364091 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7572 14:48:44.370754 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7573 14:48:44.374068 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 14:48:44.376657 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 14:48:44.383901 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 14:48:44.386650 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 14:48:44.390061 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7578 14:48:44.396608 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7579 14:48:44.399970 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7580 14:48:44.403359 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7581 14:48:44.410084 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 14:48:44.413367 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 14:48:44.416822 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 14:48:44.422910 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 14:48:44.426492 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 14:48:44.429815 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7587 14:48:44.436065 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7588 14:48:44.439493 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7589 14:48:44.443143 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 14:48:44.449702 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 14:48:44.452900 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 14:48:44.455988 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 14:48:44.462651 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7594 14:48:44.466046 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7595 14:48:44.469281 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7596 14:48:44.475871 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7597 14:48:44.479487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 14:48:44.482767 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 14:48:44.489419 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 14:48:44.492580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 14:48:44.495866 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 14:48:44.502175 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 14:48:44.505414 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 14:48:44.508869 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 14:48:44.515697 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 14:48:44.518822 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 14:48:44.522166 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 14:48:44.528895 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 14:48:44.532160 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7610 14:48:44.535330 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7611 14:48:44.541882 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7612 14:48:44.545225 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 14:48:44.548577 Total UI for P1: 0, mck2ui 16
7614 14:48:44.551748 best dqsien dly found for B0: ( 1, 9, 16)
7615 14:48:44.555071 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 14:48:44.558612 Total UI for P1: 0, mck2ui 16
7617 14:48:44.561995 best dqsien dly found for B1: ( 1, 9, 24)
7618 14:48:44.565136 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7619 14:48:44.568447 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7620 14:48:44.568527
7621 14:48:44.575036 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7622 14:48:44.578533 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7623 14:48:44.581751 [Gating] SW calibration Done
7624 14:48:44.581842 ==
7625 14:48:44.585148 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 14:48:44.588334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 14:48:44.588442 ==
7628 14:48:44.588544 RX Vref Scan: 0
7629 14:48:44.588654
7630 14:48:44.591767 RX Vref 0 -> 0, step: 1
7631 14:48:44.591868
7632 14:48:44.595135 RX Delay 0 -> 252, step: 8
7633 14:48:44.598367 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7634 14:48:44.601654 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7635 14:48:44.608154 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7636 14:48:44.611579 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7637 14:48:44.615204 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7638 14:48:44.618205 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7639 14:48:44.621543 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7640 14:48:44.624895 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7641 14:48:44.631283 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7642 14:48:44.634689 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7643 14:48:44.638050 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7644 14:48:44.641379 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7645 14:48:44.648051 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7646 14:48:44.651466 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7647 14:48:44.654587 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7648 14:48:44.657925 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7649 14:48:44.658034 ==
7650 14:48:44.661035 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 14:48:44.667926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 14:48:44.668024 ==
7653 14:48:44.668119 DQS Delay:
7654 14:48:44.668195 DQS0 = 0, DQS1 = 0
7655 14:48:44.671115 DQM Delay:
7656 14:48:44.671199 DQM0 = 127, DQM1 = 124
7657 14:48:44.674795 DQ Delay:
7658 14:48:44.678071 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7659 14:48:44.681183 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7660 14:48:44.684554 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7661 14:48:44.687882 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7662 14:48:44.687964
7663 14:48:44.688027
7664 14:48:44.688086 ==
7665 14:48:44.690862 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 14:48:44.694275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 14:48:44.697692 ==
7668 14:48:44.697827
7669 14:48:44.697919
7670 14:48:44.698008 TX Vref Scan disable
7671 14:48:44.700733 == TX Byte 0 ==
7672 14:48:44.704142 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7673 14:48:44.707580 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7674 14:48:44.710910 == TX Byte 1 ==
7675 14:48:44.714167 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7676 14:48:44.717444 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7677 14:48:44.720706 ==
7678 14:48:44.724173 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 14:48:44.727605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 14:48:44.727698 ==
7681 14:48:44.739088
7682 14:48:44.742342 TX Vref early break, caculate TX vref
7683 14:48:44.745688 TX Vref=16, minBit 8, minWin=21, winSum=363
7684 14:48:44.749148 TX Vref=18, minBit 8, minWin=22, winSum=370
7685 14:48:44.752459 TX Vref=20, minBit 11, minWin=22, winSum=377
7686 14:48:44.755818 TX Vref=22, minBit 8, minWin=23, winSum=389
7687 14:48:44.758931 TX Vref=24, minBit 8, minWin=23, winSum=396
7688 14:48:44.765724 TX Vref=26, minBit 11, minWin=24, winSum=408
7689 14:48:44.768910 TX Vref=28, minBit 8, minWin=24, winSum=409
7690 14:48:44.772256 TX Vref=30, minBit 7, minWin=24, winSum=397
7691 14:48:44.775490 TX Vref=32, minBit 8, minWin=22, winSum=387
7692 14:48:44.782160 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
7693 14:48:44.782239
7694 14:48:44.785549 Final TX Range 0 Vref 28
7695 14:48:44.785655
7696 14:48:44.785750 ==
7697 14:48:44.788653 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 14:48:44.792418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 14:48:44.792521 ==
7700 14:48:44.792629
7701 14:48:44.792719
7702 14:48:44.795143 TX Vref Scan disable
7703 14:48:44.801819 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7704 14:48:44.801929 == TX Byte 0 ==
7705 14:48:44.805221 u2DelayCellOfst[0]=11 cells (3 PI)
7706 14:48:44.808840 u2DelayCellOfst[1]=15 cells (4 PI)
7707 14:48:44.811908 u2DelayCellOfst[2]=7 cells (2 PI)
7708 14:48:44.815239 u2DelayCellOfst[3]=11 cells (3 PI)
7709 14:48:44.818666 u2DelayCellOfst[4]=7 cells (2 PI)
7710 14:48:44.821981 u2DelayCellOfst[5]=0 cells (0 PI)
7711 14:48:44.822065 u2DelayCellOfst[6]=18 cells (5 PI)
7712 14:48:44.825474 u2DelayCellOfst[7]=15 cells (4 PI)
7713 14:48:44.831800 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7714 14:48:44.834957 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7715 14:48:44.835050 == TX Byte 1 ==
7716 14:48:44.839416 u2DelayCellOfst[8]=0 cells (0 PI)
7717 14:48:44.841871 u2DelayCellOfst[9]=0 cells (0 PI)
7718 14:48:44.845176 u2DelayCellOfst[10]=7 cells (2 PI)
7719 14:48:44.848624 u2DelayCellOfst[11]=3 cells (1 PI)
7720 14:48:44.851896 u2DelayCellOfst[12]=11 cells (3 PI)
7721 14:48:44.855146 u2DelayCellOfst[13]=11 cells (3 PI)
7722 14:48:44.858544 u2DelayCellOfst[14]=15 cells (4 PI)
7723 14:48:44.861849 u2DelayCellOfst[15]=11 cells (3 PI)
7724 14:48:44.865103 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7725 14:48:44.868289 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7726 14:48:44.871857 DramC Write-DBI on
7727 14:48:44.871960 ==
7728 14:48:44.875144 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 14:48:44.878468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 14:48:44.878580 ==
7731 14:48:44.878647
7732 14:48:44.881732
7733 14:48:44.881812 TX Vref Scan disable
7734 14:48:44.884984 == TX Byte 0 ==
7735 14:48:44.888411 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7736 14:48:44.891787 == TX Byte 1 ==
7737 14:48:44.894849 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7738 14:48:44.894948 DramC Write-DBI off
7739 14:48:44.898014
7740 14:48:44.898120 [DATLAT]
7741 14:48:44.898211 Freq=1600, CH0 RK0
7742 14:48:44.898308
7743 14:48:44.901446 DATLAT Default: 0xf
7744 14:48:44.901516 0, 0xFFFF, sum = 0
7745 14:48:44.905000 1, 0xFFFF, sum = 0
7746 14:48:44.905092 2, 0xFFFF, sum = 0
7747 14:48:44.908086 3, 0xFFFF, sum = 0
7748 14:48:44.911495 4, 0xFFFF, sum = 0
7749 14:48:44.911589 5, 0xFFFF, sum = 0
7750 14:48:44.914619 6, 0xFFFF, sum = 0
7751 14:48:44.914717 7, 0xFFFF, sum = 0
7752 14:48:44.918191 8, 0xFFFF, sum = 0
7753 14:48:44.918302 9, 0xFFFF, sum = 0
7754 14:48:44.921678 10, 0xFFFF, sum = 0
7755 14:48:44.921778 11, 0xFFFF, sum = 0
7756 14:48:44.924607 12, 0xFFFF, sum = 0
7757 14:48:44.924679 13, 0xEFFF, sum = 0
7758 14:48:44.927834 14, 0x0, sum = 1
7759 14:48:44.927905 15, 0x0, sum = 2
7760 14:48:44.931182 16, 0x0, sum = 3
7761 14:48:44.931281 17, 0x0, sum = 4
7762 14:48:44.934463 best_step = 15
7763 14:48:44.934571
7764 14:48:44.934663 ==
7765 14:48:44.937885 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 14:48:44.941461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 14:48:44.941561 ==
7768 14:48:44.941627 RX Vref Scan: 1
7769 14:48:44.944702
7770 14:48:44.944784 Set Vref Range= 24 -> 127
7771 14:48:44.944849
7772 14:48:44.947930 RX Vref 24 -> 127, step: 1
7773 14:48:44.948012
7774 14:48:44.951348 RX Delay 11 -> 252, step: 4
7775 14:48:44.951430
7776 14:48:44.954446 Set Vref, RX VrefLevel [Byte0]: 24
7777 14:48:44.958244 [Byte1]: 24
7778 14:48:44.958326
7779 14:48:44.960947 Set Vref, RX VrefLevel [Byte0]: 25
7780 14:48:44.964214 [Byte1]: 25
7781 14:48:44.964296
7782 14:48:44.967936 Set Vref, RX VrefLevel [Byte0]: 26
7783 14:48:44.971185 [Byte1]: 26
7784 14:48:44.975029
7785 14:48:44.975111 Set Vref, RX VrefLevel [Byte0]: 27
7786 14:48:44.978454 [Byte1]: 27
7787 14:48:44.982877
7788 14:48:44.982959 Set Vref, RX VrefLevel [Byte0]: 28
7789 14:48:44.986137 [Byte1]: 28
7790 14:48:44.990206
7791 14:48:44.990288 Set Vref, RX VrefLevel [Byte0]: 29
7792 14:48:44.994034 [Byte1]: 29
7793 14:48:44.997854
7794 14:48:44.997935 Set Vref, RX VrefLevel [Byte0]: 30
7795 14:48:45.001224 [Byte1]: 30
7796 14:48:45.005519
7797 14:48:45.005600 Set Vref, RX VrefLevel [Byte0]: 31
7798 14:48:45.009031 [Byte1]: 31
7799 14:48:45.013344
7800 14:48:45.013425 Set Vref, RX VrefLevel [Byte0]: 32
7801 14:48:45.016429 [Byte1]: 32
7802 14:48:45.020782
7803 14:48:45.020863 Set Vref, RX VrefLevel [Byte0]: 33
7804 14:48:45.024119 [Byte1]: 33
7805 14:48:45.028841
7806 14:48:45.028922 Set Vref, RX VrefLevel [Byte0]: 34
7807 14:48:45.031911 [Byte1]: 34
7808 14:48:45.036335
7809 14:48:45.036416 Set Vref, RX VrefLevel [Byte0]: 35
7810 14:48:45.039415 [Byte1]: 35
7811 14:48:45.043710
7812 14:48:45.043817 Set Vref, RX VrefLevel [Byte0]: 36
7813 14:48:45.046832 [Byte1]: 36
7814 14:48:45.051149
7815 14:48:45.051237 Set Vref, RX VrefLevel [Byte0]: 37
7816 14:48:45.054449 [Byte1]: 37
7817 14:48:45.059180
7818 14:48:45.059288 Set Vref, RX VrefLevel [Byte0]: 38
7819 14:48:45.062350 [Byte1]: 38
7820 14:48:45.066792
7821 14:48:45.066866 Set Vref, RX VrefLevel [Byte0]: 39
7822 14:48:45.069642 [Byte1]: 39
7823 14:48:45.074205
7824 14:48:45.074286 Set Vref, RX VrefLevel [Byte0]: 40
7825 14:48:45.077450 [Byte1]: 40
7826 14:48:45.081789
7827 14:48:45.081865 Set Vref, RX VrefLevel [Byte0]: 41
7828 14:48:45.085078 [Byte1]: 41
7829 14:48:45.089128
7830 14:48:45.089221 Set Vref, RX VrefLevel [Byte0]: 42
7831 14:48:45.092864 [Byte1]: 42
7832 14:48:45.097302
7833 14:48:45.097397 Set Vref, RX VrefLevel [Byte0]: 43
7834 14:48:45.100100 [Byte1]: 43
7835 14:48:45.104520
7836 14:48:45.104662 Set Vref, RX VrefLevel [Byte0]: 44
7837 14:48:45.108005 [Byte1]: 44
7838 14:48:45.112359
7839 14:48:45.112453 Set Vref, RX VrefLevel [Byte0]: 45
7840 14:48:45.115685 [Byte1]: 45
7841 14:48:45.119705
7842 14:48:45.119800 Set Vref, RX VrefLevel [Byte0]: 46
7843 14:48:45.123321 [Byte1]: 46
7844 14:48:45.127215
7845 14:48:45.127311 Set Vref, RX VrefLevel [Byte0]: 47
7846 14:48:45.130435 [Byte1]: 47
7847 14:48:45.135182
7848 14:48:45.135277 Set Vref, RX VrefLevel [Byte0]: 48
7849 14:48:45.138141 [Byte1]: 48
7850 14:48:45.142589
7851 14:48:45.142711 Set Vref, RX VrefLevel [Byte0]: 49
7852 14:48:45.146054 [Byte1]: 49
7853 14:48:45.150243
7854 14:48:45.150339 Set Vref, RX VrefLevel [Byte0]: 50
7855 14:48:45.153846 [Byte1]: 50
7856 14:48:45.157680
7857 14:48:45.157846 Set Vref, RX VrefLevel [Byte0]: 51
7858 14:48:45.161056 [Byte1]: 51
7859 14:48:45.165475
7860 14:48:45.165569 Set Vref, RX VrefLevel [Byte0]: 52
7861 14:48:45.168492 [Byte1]: 52
7862 14:48:45.173198
7863 14:48:45.173277 Set Vref, RX VrefLevel [Byte0]: 53
7864 14:48:45.176581 [Byte1]: 53
7865 14:48:45.180491
7866 14:48:45.180629 Set Vref, RX VrefLevel [Byte0]: 54
7867 14:48:45.183799 [Byte1]: 54
7868 14:48:45.188301
7869 14:48:45.188411 Set Vref, RX VrefLevel [Byte0]: 55
7870 14:48:45.191594 [Byte1]: 55
7871 14:48:45.196186
7872 14:48:45.196280 Set Vref, RX VrefLevel [Byte0]: 56
7873 14:48:45.199508 [Byte1]: 56
7874 14:48:45.203405
7875 14:48:45.203508 Set Vref, RX VrefLevel [Byte0]: 57
7876 14:48:45.207467 [Byte1]: 57
7877 14:48:45.211468
7878 14:48:45.211565 Set Vref, RX VrefLevel [Byte0]: 58
7879 14:48:45.214222 [Byte1]: 58
7880 14:48:45.218635
7881 14:48:45.218706 Set Vref, RX VrefLevel [Byte0]: 59
7882 14:48:45.222025 [Byte1]: 59
7883 14:48:45.226584
7884 14:48:45.226655 Set Vref, RX VrefLevel [Byte0]: 60
7885 14:48:45.229872 [Byte1]: 60
7886 14:48:45.233802
7887 14:48:45.233898 Set Vref, RX VrefLevel [Byte0]: 61
7888 14:48:45.237771 [Byte1]: 61
7889 14:48:45.241593
7890 14:48:45.241664 Set Vref, RX VrefLevel [Byte0]: 62
7891 14:48:45.244833 [Byte1]: 62
7892 14:48:45.249099
7893 14:48:45.249184 Set Vref, RX VrefLevel [Byte0]: 63
7894 14:48:45.252321 [Byte1]: 63
7895 14:48:45.256601
7896 14:48:45.256681 Set Vref, RX VrefLevel [Byte0]: 64
7897 14:48:45.260236 [Byte1]: 64
7898 14:48:45.264581
7899 14:48:45.264664 Set Vref, RX VrefLevel [Byte0]: 65
7900 14:48:45.267603 [Byte1]: 65
7901 14:48:45.271768
7902 14:48:45.271850 Set Vref, RX VrefLevel [Byte0]: 66
7903 14:48:45.275176 [Byte1]: 66
7904 14:48:45.279580
7905 14:48:45.279688 Set Vref, RX VrefLevel [Byte0]: 67
7906 14:48:45.283039 [Byte1]: 67
7907 14:48:45.287222
7908 14:48:45.287331 Set Vref, RX VrefLevel [Byte0]: 68
7909 14:48:45.293645 [Byte1]: 68
7910 14:48:45.293733
7911 14:48:45.296850 Set Vref, RX VrefLevel [Byte0]: 69
7912 14:48:45.300456 [Byte1]: 69
7913 14:48:45.300533
7914 14:48:45.303696 Set Vref, RX VrefLevel [Byte0]: 70
7915 14:48:45.306969 [Byte1]: 70
7916 14:48:45.310176
7917 14:48:45.310256 Set Vref, RX VrefLevel [Byte0]: 71
7918 14:48:45.313559 [Byte1]: 71
7919 14:48:45.317999
7920 14:48:45.318078 Set Vref, RX VrefLevel [Byte0]: 72
7921 14:48:45.321255 [Byte1]: 72
7922 14:48:45.325092
7923 14:48:45.325171 Set Vref, RX VrefLevel [Byte0]: 73
7924 14:48:45.328644 [Byte1]: 73
7925 14:48:45.332976
7926 14:48:45.333056 Set Vref, RX VrefLevel [Byte0]: 74
7927 14:48:45.336183 [Byte1]: 74
7928 14:48:45.340705
7929 14:48:45.340785 Set Vref, RX VrefLevel [Byte0]: 75
7930 14:48:45.344062 [Byte1]: 75
7931 14:48:45.348318
7932 14:48:45.348398 Set Vref, RX VrefLevel [Byte0]: 76
7933 14:48:45.351777 [Byte1]: 76
7934 14:48:45.355656
7935 14:48:45.355736 Set Vref, RX VrefLevel [Byte0]: 77
7936 14:48:45.358894 [Byte1]: 77
7937 14:48:45.363234
7938 14:48:45.363330 Final RX Vref Byte 0 = 61 to rank0
7939 14:48:45.366556 Final RX Vref Byte 1 = 62 to rank0
7940 14:48:45.370156 Final RX Vref Byte 0 = 61 to rank1
7941 14:48:45.373375 Final RX Vref Byte 1 = 62 to rank1==
7942 14:48:45.376639 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 14:48:45.383187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 14:48:45.383270 ==
7945 14:48:45.383354 DQS Delay:
7946 14:48:45.383432 DQS0 = 0, DQS1 = 0
7947 14:48:45.387026 DQM Delay:
7948 14:48:45.387169 DQM0 = 126, DQM1 = 119
7949 14:48:45.389497 DQ Delay:
7950 14:48:45.393112 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
7951 14:48:45.396347 DQ4 =128, DQ5 =112, DQ6 =132, DQ7 =138
7952 14:48:45.399609 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7953 14:48:45.403184 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7954 14:48:45.403283
7955 14:48:45.403372
7956 14:48:45.403457
7957 14:48:45.406503 [DramC_TX_OE_Calibration] TA2
7958 14:48:45.409517 Original DQ_B0 (3 6) =30, OEN = 27
7959 14:48:45.413183 Original DQ_B1 (3 6) =30, OEN = 27
7960 14:48:45.416307 24, 0x0, End_B0=24 End_B1=24
7961 14:48:45.416380 25, 0x0, End_B0=25 End_B1=25
7962 14:48:45.419461 26, 0x0, End_B0=26 End_B1=26
7963 14:48:45.422830 27, 0x0, End_B0=27 End_B1=27
7964 14:48:45.426112 28, 0x0, End_B0=28 End_B1=28
7965 14:48:45.429380 29, 0x0, End_B0=29 End_B1=29
7966 14:48:45.429479 30, 0x0, End_B0=30 End_B1=30
7967 14:48:45.432792 31, 0x4141, End_B0=30 End_B1=30
7968 14:48:45.436512 Byte0 end_step=30 best_step=27
7969 14:48:45.439052 Byte1 end_step=30 best_step=27
7970 14:48:45.442317 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 14:48:45.445732 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 14:48:45.445837
7973 14:48:45.445927
7974 14:48:45.452505 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7975 14:48:45.455768 CH0 RK0: MR19=303, MR18=1312
7976 14:48:45.462531 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
7977 14:48:45.462611
7978 14:48:45.465796 ----->DramcWriteLeveling(PI) begin...
7979 14:48:45.465893 ==
7980 14:48:45.469098 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 14:48:45.472321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 14:48:45.472401 ==
7983 14:48:45.475586 Write leveling (Byte 0): 33 => 33
7984 14:48:45.478678 Write leveling (Byte 1): 27 => 27
7985 14:48:45.482541 DramcWriteLeveling(PI) end<-----
7986 14:48:45.482620
7987 14:48:45.482683 ==
7988 14:48:45.485523 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 14:48:45.488776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 14:48:45.492346 ==
7991 14:48:45.492452 [Gating] SW mode calibration
7992 14:48:45.501997 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 14:48:45.505553 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 14:48:45.508761 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 14:48:45.515407 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 14:48:45.518736 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 14:48:45.521805 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7998 14:48:45.528327 1 4 16 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
7999 14:48:45.531644 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 14:48:45.535227 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 14:48:45.541540 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 14:48:45.544710 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 14:48:45.548530 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 14:48:45.554734 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8005 14:48:45.558473 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8006 14:48:45.561958 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8007 14:48:45.568041 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 14:48:45.571788 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 14:48:45.575072 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 14:48:45.581665 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 14:48:45.585056 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 14:48:45.588210 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8013 14:48:45.595135 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8014 14:48:45.598194 1 6 16 | B1->B0 | 302f 4646 | 1 0 | (0 0) (0 0)
8015 14:48:45.601703 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 14:48:45.608441 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 14:48:45.611573 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 14:48:45.614617 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 14:48:45.618481 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 14:48:45.624895 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8021 14:48:45.628260 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 14:48:45.631364 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8023 14:48:45.638290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8024 14:48:45.641339 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 14:48:45.644785 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 14:48:45.651424 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 14:48:45.654588 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 14:48:45.658198 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 14:48:45.664515 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 14:48:45.667889 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 14:48:45.671427 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 14:48:45.677586 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 14:48:45.681133 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 14:48:45.684412 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 14:48:45.691000 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 14:48:45.694347 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8037 14:48:45.697836 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 14:48:45.704166 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 14:48:45.707640 Total UI for P1: 0, mck2ui 16
8040 14:48:45.710776 best dqsien dly found for B0: ( 1, 9, 10)
8041 14:48:45.714180 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8042 14:48:45.717504 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 14:48:45.720817 Total UI for P1: 0, mck2ui 16
8044 14:48:45.724015 best dqsien dly found for B1: ( 1, 9, 18)
8045 14:48:45.727557 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8046 14:48:45.730981 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8047 14:48:45.731077
8048 14:48:45.737163 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8049 14:48:45.740393 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8050 14:48:45.743969 [Gating] SW calibration Done
8051 14:48:45.744073 ==
8052 14:48:45.747169 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 14:48:45.750275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 14:48:45.750396 ==
8055 14:48:45.750500 RX Vref Scan: 0
8056 14:48:45.753684
8057 14:48:45.753752 RX Vref 0 -> 0, step: 1
8058 14:48:45.753809
8059 14:48:45.757404 RX Delay 0 -> 252, step: 8
8060 14:48:45.760356 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8061 14:48:45.763768 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8062 14:48:45.770335 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8063 14:48:45.773645 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8064 14:48:45.776674 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8065 14:48:45.780106 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8066 14:48:45.783562 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8067 14:48:45.790455 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8068 14:48:45.793299 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8069 14:48:45.796915 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8070 14:48:45.799934 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8071 14:48:45.803748 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8072 14:48:45.810239 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8073 14:48:45.813083 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8074 14:48:45.816442 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8075 14:48:45.819718 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8076 14:48:45.819813 ==
8077 14:48:45.823101 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 14:48:45.830027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 14:48:45.830102 ==
8080 14:48:45.830164 DQS Delay:
8081 14:48:45.833356 DQS0 = 0, DQS1 = 0
8082 14:48:45.833437 DQM Delay:
8083 14:48:45.833502 DQM0 = 128, DQM1 = 121
8084 14:48:45.836490 DQ Delay:
8085 14:48:45.840102 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8086 14:48:45.843529 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8087 14:48:45.846667 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8088 14:48:45.849742 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8089 14:48:45.849822
8090 14:48:45.849882
8091 14:48:45.849939 ==
8092 14:48:45.853142 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 14:48:45.856478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 14:48:45.859916 ==
8095 14:48:45.860017
8096 14:48:45.860107
8097 14:48:45.860191 TX Vref Scan disable
8098 14:48:45.863312 == TX Byte 0 ==
8099 14:48:45.866417 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8100 14:48:45.869675 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8101 14:48:45.872900 == TX Byte 1 ==
8102 14:48:45.876361 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8103 14:48:45.879704 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8104 14:48:45.883098 ==
8105 14:48:45.886503 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 14:48:45.889348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 14:48:45.889431 ==
8108 14:48:45.903422
8109 14:48:45.906695 TX Vref early break, caculate TX vref
8110 14:48:45.909980 TX Vref=16, minBit 0, minWin=22, winSum=364
8111 14:48:45.913262 TX Vref=18, minBit 0, minWin=22, winSum=369
8112 14:48:45.916526 TX Vref=20, minBit 8, minWin=22, winSum=376
8113 14:48:45.920271 TX Vref=22, minBit 8, minWin=22, winSum=389
8114 14:48:45.923575 TX Vref=24, minBit 0, minWin=24, winSum=396
8115 14:48:45.929830 TX Vref=26, minBit 8, minWin=24, winSum=403
8116 14:48:45.933546 TX Vref=28, minBit 8, minWin=24, winSum=407
8117 14:48:45.936701 TX Vref=30, minBit 8, minWin=24, winSum=402
8118 14:48:45.940016 TX Vref=32, minBit 3, minWin=23, winSum=395
8119 14:48:45.943105 TX Vref=34, minBit 8, minWin=23, winSum=389
8120 14:48:45.946682 TX Vref=36, minBit 8, minWin=21, winSum=379
8121 14:48:45.953067 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 28
8122 14:48:45.953150
8123 14:48:45.956272 Final TX Range 0 Vref 28
8124 14:48:45.956380
8125 14:48:45.956474 ==
8126 14:48:45.959777 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 14:48:45.962940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 14:48:45.963041 ==
8129 14:48:45.963139
8130 14:48:45.966493
8131 14:48:45.966568 TX Vref Scan disable
8132 14:48:45.973013 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8133 14:48:45.973089 == TX Byte 0 ==
8134 14:48:45.976116 u2DelayCellOfst[0]=15 cells (4 PI)
8135 14:48:45.979884 u2DelayCellOfst[1]=22 cells (6 PI)
8136 14:48:45.983451 u2DelayCellOfst[2]=15 cells (4 PI)
8137 14:48:45.986712 u2DelayCellOfst[3]=15 cells (4 PI)
8138 14:48:45.989631 u2DelayCellOfst[4]=11 cells (3 PI)
8139 14:48:45.992969 u2DelayCellOfst[5]=0 cells (0 PI)
8140 14:48:45.996369 u2DelayCellOfst[6]=22 cells (6 PI)
8141 14:48:45.999850 u2DelayCellOfst[7]=22 cells (6 PI)
8142 14:48:46.002541 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8143 14:48:46.005783 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8144 14:48:46.009769 == TX Byte 1 ==
8145 14:48:46.012498 u2DelayCellOfst[8]=0 cells (0 PI)
8146 14:48:46.015753 u2DelayCellOfst[9]=3 cells (1 PI)
8147 14:48:46.019514 u2DelayCellOfst[10]=7 cells (2 PI)
8148 14:48:46.022835 u2DelayCellOfst[11]=3 cells (1 PI)
8149 14:48:46.022917 u2DelayCellOfst[12]=15 cells (4 PI)
8150 14:48:46.026193 u2DelayCellOfst[13]=15 cells (4 PI)
8151 14:48:46.029290 u2DelayCellOfst[14]=15 cells (4 PI)
8152 14:48:46.032476 u2DelayCellOfst[15]=11 cells (3 PI)
8153 14:48:46.039521 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8154 14:48:46.042899 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8155 14:48:46.042973 DramC Write-DBI on
8156 14:48:46.046125 ==
8157 14:48:46.046197 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 14:48:46.052511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 14:48:46.052619 ==
8160 14:48:46.052716
8161 14:48:46.052803
8162 14:48:46.055581 TX Vref Scan disable
8163 14:48:46.055663 == TX Byte 0 ==
8164 14:48:46.062579 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8165 14:48:46.062694 == TX Byte 1 ==
8166 14:48:46.066031 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8167 14:48:46.069340 DramC Write-DBI off
8168 14:48:46.069415
8169 14:48:46.069478 [DATLAT]
8170 14:48:46.072928 Freq=1600, CH0 RK1
8171 14:48:46.073000
8172 14:48:46.073060 DATLAT Default: 0xf
8173 14:48:46.075805 0, 0xFFFF, sum = 0
8174 14:48:46.075908 1, 0xFFFF, sum = 0
8175 14:48:46.078936 2, 0xFFFF, sum = 0
8176 14:48:46.079021 3, 0xFFFF, sum = 0
8177 14:48:46.082285 4, 0xFFFF, sum = 0
8178 14:48:46.082359 5, 0xFFFF, sum = 0
8179 14:48:46.085369 6, 0xFFFF, sum = 0
8180 14:48:46.085464 7, 0xFFFF, sum = 0
8181 14:48:46.088999 8, 0xFFFF, sum = 0
8182 14:48:46.092124 9, 0xFFFF, sum = 0
8183 14:48:46.092215 10, 0xFFFF, sum = 0
8184 14:48:46.095447 11, 0xFFFF, sum = 0
8185 14:48:46.095543 12, 0xFFFF, sum = 0
8186 14:48:46.098591 13, 0xEFFF, sum = 0
8187 14:48:46.098689 14, 0x0, sum = 1
8188 14:48:46.101963 15, 0x0, sum = 2
8189 14:48:46.102069 16, 0x0, sum = 3
8190 14:48:46.105477 17, 0x0, sum = 4
8191 14:48:46.105585 best_step = 15
8192 14:48:46.105679
8193 14:48:46.105769 ==
8194 14:48:46.108701 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 14:48:46.112242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 14:48:46.112351 ==
8197 14:48:46.115562 RX Vref Scan: 0
8198 14:48:46.115669
8199 14:48:46.118775 RX Vref 0 -> 0, step: 1
8200 14:48:46.118883
8201 14:48:46.118983 RX Delay 3 -> 252, step: 4
8202 14:48:46.125849 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8203 14:48:46.129103 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8204 14:48:46.132423 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8205 14:48:46.135887 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8206 14:48:46.139384 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8207 14:48:46.145687 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8208 14:48:46.149376 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8209 14:48:46.152499 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8210 14:48:46.155871 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8211 14:48:46.159102 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8212 14:48:46.165556 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8213 14:48:46.168818 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8214 14:48:46.172132 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8215 14:48:46.175381 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8216 14:48:46.182120 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8217 14:48:46.185412 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8218 14:48:46.185522 ==
8219 14:48:46.188569 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 14:48:46.192302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 14:48:46.192407 ==
8222 14:48:46.195189 DQS Delay:
8223 14:48:46.195296 DQS0 = 0, DQS1 = 0
8224 14:48:46.195387 DQM Delay:
8225 14:48:46.198559 DQM0 = 124, DQM1 = 117
8226 14:48:46.198657 DQ Delay:
8227 14:48:46.201913 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =120
8228 14:48:46.205132 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8229 14:48:46.208356 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8230 14:48:46.215671 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8231 14:48:46.215779
8232 14:48:46.215846
8233 14:48:46.215907
8234 14:48:46.218598 [DramC_TX_OE_Calibration] TA2
8235 14:48:46.218704 Original DQ_B0 (3 6) =30, OEN = 27
8236 14:48:46.221794 Original DQ_B1 (3 6) =30, OEN = 27
8237 14:48:46.225263 24, 0x0, End_B0=24 End_B1=24
8238 14:48:46.228396 25, 0x0, End_B0=25 End_B1=25
8239 14:48:46.231981 26, 0x0, End_B0=26 End_B1=26
8240 14:48:46.235060 27, 0x0, End_B0=27 End_B1=27
8241 14:48:46.235139 28, 0x0, End_B0=28 End_B1=28
8242 14:48:46.238615 29, 0x0, End_B0=29 End_B1=29
8243 14:48:46.241959 30, 0x0, End_B0=30 End_B1=30
8244 14:48:46.245284 31, 0x4141, End_B0=30 End_B1=30
8245 14:48:46.248482 Byte0 end_step=30 best_step=27
8246 14:48:46.248592 Byte1 end_step=30 best_step=27
8247 14:48:46.251705 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 14:48:46.254739 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 14:48:46.254812
8250 14:48:46.254874
8251 14:48:46.264859 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8252 14:48:46.264972 CH0 RK1: MR19=303, MR18=2512
8253 14:48:46.271667 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8254 14:48:46.274705 [RxdqsGatingPostProcess] freq 1600
8255 14:48:46.281348 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 14:48:46.284463 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 14:48:46.287966 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 14:48:46.291421 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 14:48:46.294663 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 14:48:46.297970 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 14:48:46.298075 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 14:48:46.301234 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 14:48:46.304795 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 14:48:46.307769 Pre-setting of DQS Precalculation
8265 14:48:46.314811 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 14:48:46.314892 ==
8267 14:48:46.317684 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 14:48:46.321420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 14:48:46.321501 ==
8270 14:48:46.327658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 14:48:46.331099 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 14:48:46.334380 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 14:48:46.340791 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 14:48:46.350293 [CA 0] Center 42 (13~71) winsize 59
8275 14:48:46.353220 [CA 1] Center 42 (12~72) winsize 61
8276 14:48:46.356794 [CA 2] Center 37 (9~66) winsize 58
8277 14:48:46.359841 [CA 3] Center 36 (7~66) winsize 60
8278 14:48:46.363314 [CA 4] Center 37 (8~66) winsize 59
8279 14:48:46.366639 [CA 5] Center 36 (7~66) winsize 60
8280 14:48:46.366735
8281 14:48:46.369832 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8282 14:48:46.369913
8283 14:48:46.373180 [CATrainingPosCal] consider 1 rank data
8284 14:48:46.376457 u2DelayCellTimex100 = 258/100 ps
8285 14:48:46.383475 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8286 14:48:46.386822 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8287 14:48:46.390507 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8288 14:48:46.392866 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8289 14:48:46.396222 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8290 14:48:46.399522 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8291 14:48:46.399616
8292 14:48:46.402978 CA PerBit enable=1, Macro0, CA PI delay=36
8293 14:48:46.403059
8294 14:48:46.406444 [CBTSetCACLKResult] CA Dly = 36
8295 14:48:46.409755 CS Dly: 9 (0~40)
8296 14:48:46.413054 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 14:48:46.415937 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 14:48:46.416017 ==
8299 14:48:46.419337 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 14:48:46.422912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 14:48:46.426218 ==
8302 14:48:46.429371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 14:48:46.432770 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 14:48:46.439412 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 14:48:46.446118 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 14:48:46.453441 [CA 0] Center 41 (12~71) winsize 60
8307 14:48:46.456598 [CA 1] Center 42 (12~72) winsize 61
8308 14:48:46.459522 [CA 2] Center 37 (8~66) winsize 59
8309 14:48:46.462969 [CA 3] Center 36 (7~66) winsize 60
8310 14:48:46.466773 [CA 4] Center 37 (7~67) winsize 61
8311 14:48:46.469683 [CA 5] Center 36 (6~66) winsize 61
8312 14:48:46.469764
8313 14:48:46.472810 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 14:48:46.472890
8315 14:48:46.476747 [CATrainingPosCal] consider 2 rank data
8316 14:48:46.479681 u2DelayCellTimex100 = 258/100 ps
8317 14:48:46.486321 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8318 14:48:46.489678 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8319 14:48:46.492964 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8320 14:48:46.496239 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8321 14:48:46.499276 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8322 14:48:46.502549 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 14:48:46.502656
8324 14:48:46.506464 CA PerBit enable=1, Macro0, CA PI delay=36
8325 14:48:46.506546
8326 14:48:46.509624 [CBTSetCACLKResult] CA Dly = 36
8327 14:48:46.512875 CS Dly: 11 (0~44)
8328 14:48:46.516132 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 14:48:46.519532 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 14:48:46.519619
8331 14:48:46.522611 ----->DramcWriteLeveling(PI) begin...
8332 14:48:46.522695 ==
8333 14:48:46.525631 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 14:48:46.532596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 14:48:46.532678 ==
8336 14:48:46.536131 Write leveling (Byte 0): 24 => 24
8337 14:48:46.539165 Write leveling (Byte 1): 27 => 27
8338 14:48:46.539239 DramcWriteLeveling(PI) end<-----
8339 14:48:46.539301
8340 14:48:46.542520 ==
8341 14:48:46.545905 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 14:48:46.549306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 14:48:46.549412 ==
8344 14:48:46.552128 [Gating] SW mode calibration
8345 14:48:46.558958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 14:48:46.561962 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 14:48:46.568671 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 14:48:46.572254 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 14:48:46.575540 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 14:48:46.582227 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8351 14:48:46.585227 1 4 16 | B1->B0 | 3232 3232 | 1 0 | (0 0) (0 0)
8352 14:48:46.588604 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 14:48:46.595075 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 14:48:46.598558 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 14:48:46.601889 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 14:48:46.608539 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 14:48:46.611916 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 14:48:46.615286 1 5 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8359 14:48:46.621761 1 5 16 | B1->B0 | 2626 2929 | 0 0 | (1 0) (1 0)
8360 14:48:46.625172 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 14:48:46.628473 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 14:48:46.634961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 14:48:46.638398 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 14:48:46.641172 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 14:48:46.648176 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 14:48:46.650969 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8367 14:48:46.654339 1 6 16 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
8368 14:48:46.661240 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 14:48:46.664555 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 14:48:46.667650 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 14:48:46.674528 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 14:48:46.677588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 14:48:46.681044 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 14:48:46.687440 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 14:48:46.690691 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8376 14:48:46.694428 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8377 14:48:46.700708 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 14:48:46.704187 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 14:48:46.707210 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 14:48:46.714422 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 14:48:46.717017 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 14:48:46.720619 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 14:48:46.727466 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 14:48:46.730740 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 14:48:46.733993 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 14:48:46.740432 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 14:48:46.743707 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 14:48:46.747165 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 14:48:46.753501 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 14:48:46.756680 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 14:48:46.760032 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8392 14:48:46.766897 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 14:48:46.767007 Total UI for P1: 0, mck2ui 16
8394 14:48:46.773320 best dqsien dly found for B0: ( 1, 9, 14)
8395 14:48:46.773431 Total UI for P1: 0, mck2ui 16
8396 14:48:46.780050 best dqsien dly found for B1: ( 1, 9, 14)
8397 14:48:46.783301 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8398 14:48:46.786595 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8399 14:48:46.786705
8400 14:48:46.789855 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8401 14:48:46.793125 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8402 14:48:46.796523 [Gating] SW calibration Done
8403 14:48:46.796628 ==
8404 14:48:46.799680 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 14:48:46.803113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 14:48:46.803194 ==
8407 14:48:46.806434 RX Vref Scan: 0
8408 14:48:46.806515
8409 14:48:46.806578 RX Vref 0 -> 0, step: 1
8410 14:48:46.809939
8411 14:48:46.810019 RX Delay 0 -> 252, step: 8
8412 14:48:46.816317 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8413 14:48:46.819592 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8414 14:48:46.823025 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8415 14:48:46.826485 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8416 14:48:46.829563 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8417 14:48:46.836194 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8418 14:48:46.839289 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8419 14:48:46.842677 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8420 14:48:46.846301 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8421 14:48:46.849260 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8422 14:48:46.856233 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8423 14:48:46.859169 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8424 14:48:46.862582 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8425 14:48:46.865604 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8426 14:48:46.869234 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8427 14:48:46.875735 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8428 14:48:46.875859 ==
8429 14:48:46.878957 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 14:48:46.882493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 14:48:46.882613 ==
8432 14:48:46.882725 DQS Delay:
8433 14:48:46.885870 DQS0 = 0, DQS1 = 0
8434 14:48:46.885967 DQM Delay:
8435 14:48:46.889459 DQM0 = 133, DQM1 = 126
8436 14:48:46.889543 DQ Delay:
8437 14:48:46.892895 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8438 14:48:46.896103 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8439 14:48:46.899249 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8440 14:48:46.902730 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8441 14:48:46.902812
8442 14:48:46.902877
8443 14:48:46.906003 ==
8444 14:48:46.909314 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 14:48:46.912685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 14:48:46.912768 ==
8447 14:48:46.912861
8448 14:48:46.912925
8449 14:48:46.915988 TX Vref Scan disable
8450 14:48:46.916070 == TX Byte 0 ==
8451 14:48:46.919283 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8452 14:48:46.925736 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8453 14:48:46.925850 == TX Byte 1 ==
8454 14:48:46.928872 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8455 14:48:46.936077 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8456 14:48:46.936183 ==
8457 14:48:46.939064 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 14:48:46.942172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 14:48:46.942255 ==
8460 14:48:46.956414
8461 14:48:46.959783 TX Vref early break, caculate TX vref
8462 14:48:46.963354 TX Vref=16, minBit 1, minWin=22, winSum=363
8463 14:48:46.966238 TX Vref=18, minBit 9, minWin=22, winSum=376
8464 14:48:46.969714 TX Vref=20, minBit 8, minWin=23, winSum=387
8465 14:48:46.973111 TX Vref=22, minBit 6, minWin=24, winSum=397
8466 14:48:46.976307 TX Vref=24, minBit 11, minWin=24, winSum=404
8467 14:48:46.982897 TX Vref=26, minBit 5, minWin=25, winSum=415
8468 14:48:46.986210 TX Vref=28, minBit 1, minWin=25, winSum=422
8469 14:48:46.989255 TX Vref=30, minBit 0, minWin=25, winSum=418
8470 14:48:46.992847 TX Vref=32, minBit 0, minWin=24, winSum=408
8471 14:48:46.996011 TX Vref=34, minBit 0, minWin=24, winSum=400
8472 14:48:46.999327 TX Vref=36, minBit 1, minWin=23, winSum=387
8473 14:48:47.005881 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8474 14:48:47.005974
8475 14:48:47.009368 Final TX Range 0 Vref 28
8476 14:48:47.009442
8477 14:48:47.009518 ==
8478 14:48:47.012784 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 14:48:47.016200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 14:48:47.016315 ==
8481 14:48:47.018992
8482 14:48:47.019087
8483 14:48:47.019173 TX Vref Scan disable
8484 14:48:47.025849 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8485 14:48:47.025926 == TX Byte 0 ==
8486 14:48:47.029494 u2DelayCellOfst[0]=18 cells (5 PI)
8487 14:48:47.032272 u2DelayCellOfst[1]=11 cells (3 PI)
8488 14:48:47.035848 u2DelayCellOfst[2]=0 cells (0 PI)
8489 14:48:47.038991 u2DelayCellOfst[3]=7 cells (2 PI)
8490 14:48:47.042512 u2DelayCellOfst[4]=7 cells (2 PI)
8491 14:48:47.045651 u2DelayCellOfst[5]=22 cells (6 PI)
8492 14:48:47.049219 u2DelayCellOfst[6]=18 cells (5 PI)
8493 14:48:47.052321 u2DelayCellOfst[7]=7 cells (2 PI)
8494 14:48:47.055402 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8495 14:48:47.058963 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8496 14:48:47.062137 == TX Byte 1 ==
8497 14:48:47.065713 u2DelayCellOfst[8]=0 cells (0 PI)
8498 14:48:47.068826 u2DelayCellOfst[9]=11 cells (3 PI)
8499 14:48:47.071952 u2DelayCellOfst[10]=15 cells (4 PI)
8500 14:48:47.075409 u2DelayCellOfst[11]=7 cells (2 PI)
8501 14:48:47.078976 u2DelayCellOfst[12]=18 cells (5 PI)
8502 14:48:47.079056 u2DelayCellOfst[13]=22 cells (6 PI)
8503 14:48:47.082326 u2DelayCellOfst[14]=22 cells (6 PI)
8504 14:48:47.085506 u2DelayCellOfst[15]=22 cells (6 PI)
8505 14:48:47.091785 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8506 14:48:47.095418 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8507 14:48:47.095509 DramC Write-DBI on
8508 14:48:47.098554 ==
8509 14:48:47.101751 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 14:48:47.105243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 14:48:47.105325 ==
8512 14:48:47.105391
8513 14:48:47.105450
8514 14:48:47.108455 TX Vref Scan disable
8515 14:48:47.108537 == TX Byte 0 ==
8516 14:48:47.115222 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8517 14:48:47.115303 == TX Byte 1 ==
8518 14:48:47.118040 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8519 14:48:47.121323 DramC Write-DBI off
8520 14:48:47.121404
8521 14:48:47.121469 [DATLAT]
8522 14:48:47.125194 Freq=1600, CH1 RK0
8523 14:48:47.125275
8524 14:48:47.125339 DATLAT Default: 0xf
8525 14:48:47.128136 0, 0xFFFF, sum = 0
8526 14:48:47.128219 1, 0xFFFF, sum = 0
8527 14:48:47.131388 2, 0xFFFF, sum = 0
8528 14:48:47.134549 3, 0xFFFF, sum = 0
8529 14:48:47.134631 4, 0xFFFF, sum = 0
8530 14:48:47.138198 5, 0xFFFF, sum = 0
8531 14:48:47.138281 6, 0xFFFF, sum = 0
8532 14:48:47.141031 7, 0xFFFF, sum = 0
8533 14:48:47.141113 8, 0xFFFF, sum = 0
8534 14:48:47.144482 9, 0xFFFF, sum = 0
8535 14:48:47.144572 10, 0xFFFF, sum = 0
8536 14:48:47.147785 11, 0xFFFF, sum = 0
8537 14:48:47.147899 12, 0xFFFF, sum = 0
8538 14:48:47.151275 13, 0x8FFF, sum = 0
8539 14:48:47.151358 14, 0x0, sum = 1
8540 14:48:47.154322 15, 0x0, sum = 2
8541 14:48:47.154404 16, 0x0, sum = 3
8542 14:48:47.157884 17, 0x0, sum = 4
8543 14:48:47.157967 best_step = 15
8544 14:48:47.158031
8545 14:48:47.158091 ==
8546 14:48:47.161014 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 14:48:47.164293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 14:48:47.167657 ==
8549 14:48:47.167738 RX Vref Scan: 1
8550 14:48:47.167802
8551 14:48:47.171058 Set Vref Range= 24 -> 127
8552 14:48:47.171138
8553 14:48:47.174246 RX Vref 24 -> 127, step: 1
8554 14:48:47.174327
8555 14:48:47.174392 RX Delay 11 -> 252, step: 4
8556 14:48:47.174452
8557 14:48:47.177295 Set Vref, RX VrefLevel [Byte0]: 24
8558 14:48:47.180657 [Byte1]: 24
8559 14:48:47.185269
8560 14:48:47.185350 Set Vref, RX VrefLevel [Byte0]: 25
8561 14:48:47.188551 [Byte1]: 25
8562 14:48:47.192356
8563 14:48:47.192476 Set Vref, RX VrefLevel [Byte0]: 26
8564 14:48:47.196227 [Byte1]: 26
8565 14:48:47.200055
8566 14:48:47.200134 Set Vref, RX VrefLevel [Byte0]: 27
8567 14:48:47.203647 [Byte1]: 27
8568 14:48:47.207622
8569 14:48:47.207701 Set Vref, RX VrefLevel [Byte0]: 28
8570 14:48:47.211032 [Byte1]: 28
8571 14:48:47.215394
8572 14:48:47.215515 Set Vref, RX VrefLevel [Byte0]: 29
8573 14:48:47.218649 [Byte1]: 29
8574 14:48:47.223165
8575 14:48:47.223284 Set Vref, RX VrefLevel [Byte0]: 30
8576 14:48:47.226427 [Byte1]: 30
8577 14:48:47.230927
8578 14:48:47.231044 Set Vref, RX VrefLevel [Byte0]: 31
8579 14:48:47.234326 [Byte1]: 31
8580 14:48:47.238233
8581 14:48:47.238353 Set Vref, RX VrefLevel [Byte0]: 32
8582 14:48:47.241517 [Byte1]: 32
8583 14:48:47.246227
8584 14:48:47.246345 Set Vref, RX VrefLevel [Byte0]: 33
8585 14:48:47.249173 [Byte1]: 33
8586 14:48:47.253294
8587 14:48:47.253427 Set Vref, RX VrefLevel [Byte0]: 34
8588 14:48:47.256797 [Byte1]: 34
8589 14:48:47.261410
8590 14:48:47.261512 Set Vref, RX VrefLevel [Byte0]: 35
8591 14:48:47.264566 [Byte1]: 35
8592 14:48:47.268451
8593 14:48:47.268532 Set Vref, RX VrefLevel [Byte0]: 36
8594 14:48:47.271972 [Byte1]: 36
8595 14:48:47.276268
8596 14:48:47.276376 Set Vref, RX VrefLevel [Byte0]: 37
8597 14:48:47.279808 [Byte1]: 37
8598 14:48:47.284253
8599 14:48:47.284328 Set Vref, RX VrefLevel [Byte0]: 38
8600 14:48:47.286906 [Byte1]: 38
8601 14:48:47.291269
8602 14:48:47.291370 Set Vref, RX VrefLevel [Byte0]: 39
8603 14:48:47.294841 [Byte1]: 39
8604 14:48:47.299071
8605 14:48:47.299184 Set Vref, RX VrefLevel [Byte0]: 40
8606 14:48:47.302455 [Byte1]: 40
8607 14:48:47.306673
8608 14:48:47.306832 Set Vref, RX VrefLevel [Byte0]: 41
8609 14:48:47.309955 [Byte1]: 41
8610 14:48:47.314229
8611 14:48:47.314335 Set Vref, RX VrefLevel [Byte0]: 42
8612 14:48:47.317921 [Byte1]: 42
8613 14:48:47.321905
8614 14:48:47.322007 Set Vref, RX VrefLevel [Byte0]: 43
8615 14:48:47.325019 [Byte1]: 43
8616 14:48:47.329592
8617 14:48:47.329704 Set Vref, RX VrefLevel [Byte0]: 44
8618 14:48:47.332799 [Byte1]: 44
8619 14:48:47.337284
8620 14:48:47.337391 Set Vref, RX VrefLevel [Byte0]: 45
8621 14:48:47.340554 [Byte1]: 45
8622 14:48:47.344859
8623 14:48:47.344964 Set Vref, RX VrefLevel [Byte0]: 46
8624 14:48:47.347794 [Byte1]: 46
8625 14:48:47.352524
8626 14:48:47.352712 Set Vref, RX VrefLevel [Byte0]: 47
8627 14:48:47.355689 [Byte1]: 47
8628 14:48:47.360256
8629 14:48:47.360392 Set Vref, RX VrefLevel [Byte0]: 48
8630 14:48:47.363398 [Byte1]: 48
8631 14:48:47.367639
8632 14:48:47.367760 Set Vref, RX VrefLevel [Byte0]: 49
8633 14:48:47.370634 [Byte1]: 49
8634 14:48:47.375684
8635 14:48:47.375805 Set Vref, RX VrefLevel [Byte0]: 50
8636 14:48:47.378433 [Byte1]: 50
8637 14:48:47.383282
8638 14:48:47.383402 Set Vref, RX VrefLevel [Byte0]: 51
8639 14:48:47.386290 [Byte1]: 51
8640 14:48:47.390333
8641 14:48:47.390444 Set Vref, RX VrefLevel [Byte0]: 52
8642 14:48:47.394037 [Byte1]: 52
8643 14:48:47.398156
8644 14:48:47.398266 Set Vref, RX VrefLevel [Byte0]: 53
8645 14:48:47.401642 [Byte1]: 53
8646 14:48:47.405579
8647 14:48:47.405660 Set Vref, RX VrefLevel [Byte0]: 54
8648 14:48:47.408980 [Byte1]: 54
8649 14:48:47.413174
8650 14:48:47.413257 Set Vref, RX VrefLevel [Byte0]: 55
8651 14:48:47.416412 [Byte1]: 55
8652 14:48:47.420748
8653 14:48:47.420877 Set Vref, RX VrefLevel [Byte0]: 56
8654 14:48:47.424504 [Byte1]: 56
8655 14:48:47.428478
8656 14:48:47.428577 Set Vref, RX VrefLevel [Byte0]: 57
8657 14:48:47.431784 [Byte1]: 57
8658 14:48:47.436300
8659 14:48:47.436421 Set Vref, RX VrefLevel [Byte0]: 58
8660 14:48:47.439758 [Byte1]: 58
8661 14:48:47.443587
8662 14:48:47.443708 Set Vref, RX VrefLevel [Byte0]: 59
8663 14:48:47.446973 [Byte1]: 59
8664 14:48:47.451447
8665 14:48:47.451576 Set Vref, RX VrefLevel [Byte0]: 60
8666 14:48:47.454760 [Byte1]: 60
8667 14:48:47.458845
8668 14:48:47.458969 Set Vref, RX VrefLevel [Byte0]: 61
8669 14:48:47.462223 [Byte1]: 61
8670 14:48:47.466881
8671 14:48:47.466962 Set Vref, RX VrefLevel [Byte0]: 62
8672 14:48:47.470243 [Byte1]: 62
8673 14:48:47.474050
8674 14:48:47.474131 Set Vref, RX VrefLevel [Byte0]: 63
8675 14:48:47.477816 [Byte1]: 63
8676 14:48:47.482278
8677 14:48:47.482358 Set Vref, RX VrefLevel [Byte0]: 64
8678 14:48:47.484944 [Byte1]: 64
8679 14:48:47.489224
8680 14:48:47.489304 Set Vref, RX VrefLevel [Byte0]: 65
8681 14:48:47.492900 [Byte1]: 65
8682 14:48:47.496956
8683 14:48:47.497035 Set Vref, RX VrefLevel [Byte0]: 66
8684 14:48:47.500397 [Byte1]: 66
8685 14:48:47.504833
8686 14:48:47.504912 Set Vref, RX VrefLevel [Byte0]: 67
8687 14:48:47.508358 [Byte1]: 67
8688 14:48:47.512429
8689 14:48:47.512540 Set Vref, RX VrefLevel [Byte0]: 68
8690 14:48:47.515847 [Byte1]: 68
8691 14:48:47.519886
8692 14:48:47.519965 Set Vref, RX VrefLevel [Byte0]: 69
8693 14:48:47.523120 [Byte1]: 69
8694 14:48:47.527249
8695 14:48:47.527368 Set Vref, RX VrefLevel [Byte0]: 70
8696 14:48:47.530879 [Byte1]: 70
8697 14:48:47.534884
8698 14:48:47.534963 Set Vref, RX VrefLevel [Byte0]: 71
8699 14:48:47.538266 [Byte1]: 71
8700 14:48:47.543142
8701 14:48:47.543221 Final RX Vref Byte 0 = 58 to rank0
8702 14:48:47.545928 Final RX Vref Byte 1 = 52 to rank0
8703 14:48:47.549230 Final RX Vref Byte 0 = 58 to rank1
8704 14:48:47.552537 Final RX Vref Byte 1 = 52 to rank1==
8705 14:48:47.555838 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 14:48:47.562576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 14:48:47.562697 ==
8708 14:48:47.562808 DQS Delay:
8709 14:48:47.562913 DQS0 = 0, DQS1 = 0
8710 14:48:47.565892 DQM Delay:
8711 14:48:47.566011 DQM0 = 130, DQM1 = 123
8712 14:48:47.569182 DQ Delay:
8713 14:48:47.572427 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8714 14:48:47.575839 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =124
8715 14:48:47.579224 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8716 14:48:47.582431 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8717 14:48:47.582550
8718 14:48:47.582662
8719 14:48:47.582767
8720 14:48:47.585655 [DramC_TX_OE_Calibration] TA2
8721 14:48:47.588889 Original DQ_B0 (3 6) =30, OEN = 27
8722 14:48:47.592532 Original DQ_B1 (3 6) =30, OEN = 27
8723 14:48:47.595836 24, 0x0, End_B0=24 End_B1=24
8724 14:48:47.595952 25, 0x0, End_B0=25 End_B1=25
8725 14:48:47.599001 26, 0x0, End_B0=26 End_B1=26
8726 14:48:47.602403 27, 0x0, End_B0=27 End_B1=27
8727 14:48:47.605728 28, 0x0, End_B0=28 End_B1=28
8728 14:48:47.608962 29, 0x0, End_B0=29 End_B1=29
8729 14:48:47.609066 30, 0x0, End_B0=30 End_B1=30
8730 14:48:47.612075 31, 0x4141, End_B0=30 End_B1=30
8731 14:48:47.615405 Byte0 end_step=30 best_step=27
8732 14:48:47.618510 Byte1 end_step=30 best_step=27
8733 14:48:47.621877 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 14:48:47.625705 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 14:48:47.625785
8736 14:48:47.625849
8737 14:48:47.631849 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8738 14:48:47.635587 CH1 RK0: MR19=303, MR18=B0F
8739 14:48:47.641998 CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8740 14:48:47.642073
8741 14:48:47.645439 ----->DramcWriteLeveling(PI) begin...
8742 14:48:47.645520 ==
8743 14:48:47.648843 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 14:48:47.651994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 14:48:47.652075 ==
8746 14:48:47.655198 Write leveling (Byte 0): 23 => 23
8747 14:48:47.658453 Write leveling (Byte 1): 25 => 25
8748 14:48:47.661841 DramcWriteLeveling(PI) end<-----
8749 14:48:47.661921
8750 14:48:47.661984 ==
8751 14:48:47.665216 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 14:48:47.668244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 14:48:47.668362 ==
8754 14:48:47.671428 [Gating] SW mode calibration
8755 14:48:47.678233 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 14:48:47.684785 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 14:48:47.688671 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 14:48:47.694983 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 14:48:47.698279 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8760 14:48:47.701495 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8761 14:48:47.708223 1 4 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8762 14:48:47.711341 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 14:48:47.715171 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 14:48:47.721168 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 14:48:47.724518 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 14:48:47.728322 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8767 14:48:47.734322 1 5 8 | B1->B0 | 3333 2929 | 1 1 | (1 0) (1 0)
8768 14:48:47.737645 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8769 14:48:47.740994 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 14:48:47.747690 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 14:48:47.750803 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 14:48:47.754585 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 14:48:47.760848 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 14:48:47.764171 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 14:48:47.767295 1 6 8 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
8776 14:48:47.774144 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8777 14:48:47.777396 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 14:48:47.780718 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 14:48:47.787523 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 14:48:47.790691 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 14:48:47.793946 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 14:48:47.797243 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 14:48:47.803949 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8784 14:48:47.807114 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8785 14:48:47.813740 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8786 14:48:47.816870 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 14:48:47.820418 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 14:48:47.823961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 14:48:47.829973 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 14:48:47.833633 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 14:48:47.836763 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 14:48:47.843617 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 14:48:47.846754 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 14:48:47.849981 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 14:48:47.856478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 14:48:47.860005 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 14:48:47.863348 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 14:48:47.869819 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 14:48:47.873090 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8800 14:48:47.876749 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8801 14:48:47.880238 Total UI for P1: 0, mck2ui 16
8802 14:48:47.883023 best dqsien dly found for B0: ( 1, 9, 8)
8803 14:48:47.890162 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 14:48:47.890242 Total UI for P1: 0, mck2ui 16
8805 14:48:47.896300 best dqsien dly found for B1: ( 1, 9, 10)
8806 14:48:47.899649 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8807 14:48:47.902794 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8808 14:48:47.902898
8809 14:48:47.906277 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8810 14:48:47.909937 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8811 14:48:47.912662 [Gating] SW calibration Done
8812 14:48:47.912741 ==
8813 14:48:47.916355 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 14:48:47.919628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 14:48:47.919708 ==
8816 14:48:47.922760 RX Vref Scan: 0
8817 14:48:47.922839
8818 14:48:47.922902 RX Vref 0 -> 0, step: 1
8819 14:48:47.926153
8820 14:48:47.926232 RX Delay 0 -> 252, step: 8
8821 14:48:47.932760 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8822 14:48:47.935794 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8823 14:48:47.939745 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8824 14:48:47.942518 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8825 14:48:47.945783 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8826 14:48:47.952596 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8827 14:48:47.955780 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8828 14:48:47.959050 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8829 14:48:47.962838 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8830 14:48:47.965668 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8831 14:48:47.972641 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8832 14:48:47.975835 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8833 14:48:47.979327 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8834 14:48:47.982432 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8835 14:48:47.985702 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8836 14:48:47.992330 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8837 14:48:47.992436 ==
8838 14:48:47.995597 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 14:48:47.999271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 14:48:47.999351 ==
8841 14:48:47.999414 DQS Delay:
8842 14:48:48.002102 DQS0 = 0, DQS1 = 0
8843 14:48:48.002182 DQM Delay:
8844 14:48:48.005681 DQM0 = 129, DQM1 = 127
8845 14:48:48.005760 DQ Delay:
8846 14:48:48.008809 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8847 14:48:48.012323 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8848 14:48:48.015546 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8849 14:48:48.018694 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8850 14:48:48.018773
8851 14:48:48.021997
8852 14:48:48.022076 ==
8853 14:48:48.025243 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 14:48:48.029028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 14:48:48.029108 ==
8856 14:48:48.029171
8857 14:48:48.029229
8858 14:48:48.031723 TX Vref Scan disable
8859 14:48:48.031803 == TX Byte 0 ==
8860 14:48:48.038772 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8861 14:48:48.042146 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8862 14:48:48.042225 == TX Byte 1 ==
8863 14:48:48.048694 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8864 14:48:48.051860 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8865 14:48:48.051939 ==
8866 14:48:48.055169 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 14:48:48.058425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 14:48:48.058505 ==
8869 14:48:48.073789
8870 14:48:48.076357 TX Vref early break, caculate TX vref
8871 14:48:48.079709 TX Vref=16, minBit 6, minWin=22, winSum=383
8872 14:48:48.082997 TX Vref=18, minBit 0, minWin=22, winSum=392
8873 14:48:48.086226 TX Vref=20, minBit 0, minWin=24, winSum=401
8874 14:48:48.089582 TX Vref=22, minBit 0, minWin=23, winSum=404
8875 14:48:48.092709 TX Vref=24, minBit 0, minWin=24, winSum=417
8876 14:48:48.099645 TX Vref=26, minBit 0, minWin=25, winSum=421
8877 14:48:48.102708 TX Vref=28, minBit 5, minWin=24, winSum=419
8878 14:48:48.105851 TX Vref=30, minBit 0, minWin=25, winSum=419
8879 14:48:48.109267 TX Vref=32, minBit 5, minWin=23, winSum=409
8880 14:48:48.112468 TX Vref=34, minBit 5, minWin=22, winSum=399
8881 14:48:48.119366 TX Vref=36, minBit 0, minWin=23, winSum=394
8882 14:48:48.122542 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8883 14:48:48.122622
8884 14:48:48.126144 Final TX Range 0 Vref 26
8885 14:48:48.126224
8886 14:48:48.126286 ==
8887 14:48:48.129289 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 14:48:48.132499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 14:48:48.132621 ==
8890 14:48:48.135595
8891 14:48:48.135674
8892 14:48:48.135737 TX Vref Scan disable
8893 14:48:48.142071 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8894 14:48:48.142150 == TX Byte 0 ==
8895 14:48:48.145477 u2DelayCellOfst[0]=18 cells (5 PI)
8896 14:48:48.148843 u2DelayCellOfst[1]=11 cells (3 PI)
8897 14:48:48.152211 u2DelayCellOfst[2]=0 cells (0 PI)
8898 14:48:48.155421 u2DelayCellOfst[3]=3 cells (1 PI)
8899 14:48:48.158954 u2DelayCellOfst[4]=7 cells (2 PI)
8900 14:48:48.162267 u2DelayCellOfst[5]=22 cells (6 PI)
8901 14:48:48.165398 u2DelayCellOfst[6]=15 cells (4 PI)
8902 14:48:48.168719 u2DelayCellOfst[7]=3 cells (1 PI)
8903 14:48:48.172120 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8904 14:48:48.175211 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8905 14:48:48.178697 == TX Byte 1 ==
8906 14:48:48.181914 u2DelayCellOfst[8]=0 cells (0 PI)
8907 14:48:48.185217 u2DelayCellOfst[9]=7 cells (2 PI)
8908 14:48:48.188710 u2DelayCellOfst[10]=15 cells (4 PI)
8909 14:48:48.191907 u2DelayCellOfst[11]=7 cells (2 PI)
8910 14:48:48.191987 u2DelayCellOfst[12]=18 cells (5 PI)
8911 14:48:48.195244 u2DelayCellOfst[13]=18 cells (5 PI)
8912 14:48:48.198839 u2DelayCellOfst[14]=18 cells (5 PI)
8913 14:48:48.201926 u2DelayCellOfst[15]=18 cells (5 PI)
8914 14:48:48.208777 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8915 14:48:48.211929 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8916 14:48:48.212009 DramC Write-DBI on
8917 14:48:48.215221 ==
8918 14:48:48.215300 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 14:48:48.221877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 14:48:48.221957 ==
8921 14:48:48.222020
8922 14:48:48.222078
8923 14:48:48.225206 TX Vref Scan disable
8924 14:48:48.225290 == TX Byte 0 ==
8925 14:48:48.231778 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8926 14:48:48.231875 == TX Byte 1 ==
8927 14:48:48.235173 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8928 14:48:48.238481 DramC Write-DBI off
8929 14:48:48.238561
8930 14:48:48.238659 [DATLAT]
8931 14:48:48.241502 Freq=1600, CH1 RK1
8932 14:48:48.241581
8933 14:48:48.241644 DATLAT Default: 0xf
8934 14:48:48.245143 0, 0xFFFF, sum = 0
8935 14:48:48.245234 1, 0xFFFF, sum = 0
8936 14:48:48.248339 2, 0xFFFF, sum = 0
8937 14:48:48.248419 3, 0xFFFF, sum = 0
8938 14:48:48.251924 4, 0xFFFF, sum = 0
8939 14:48:48.252005 5, 0xFFFF, sum = 0
8940 14:48:48.254715 6, 0xFFFF, sum = 0
8941 14:48:48.254813 7, 0xFFFF, sum = 0
8942 14:48:48.258442 8, 0xFFFF, sum = 0
8943 14:48:48.258544 9, 0xFFFF, sum = 0
8944 14:48:48.261306 10, 0xFFFF, sum = 0
8945 14:48:48.264759 11, 0xFFFF, sum = 0
8946 14:48:48.264840 12, 0xFFFF, sum = 0
8947 14:48:48.267832 13, 0x8FFF, sum = 0
8948 14:48:48.267913 14, 0x0, sum = 1
8949 14:48:48.271384 15, 0x0, sum = 2
8950 14:48:48.271466 16, 0x0, sum = 3
8951 14:48:48.274569 17, 0x0, sum = 4
8952 14:48:48.274650 best_step = 15
8953 14:48:48.274713
8954 14:48:48.274809 ==
8955 14:48:48.277871 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 14:48:48.281092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 14:48:48.281172 ==
8958 14:48:48.284861 RX Vref Scan: 0
8959 14:48:48.284940
8960 14:48:48.287975 RX Vref 0 -> 0, step: 1
8961 14:48:48.288055
8962 14:48:48.288117 RX Delay 3 -> 252, step: 4
8963 14:48:48.295476 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8964 14:48:48.298179 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8965 14:48:48.301491 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8966 14:48:48.304774 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8967 14:48:48.308397 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8968 14:48:48.314801 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8969 14:48:48.318039 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8970 14:48:48.321386 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8971 14:48:48.324797 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8972 14:48:48.328181 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8973 14:48:48.334564 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8974 14:48:48.337878 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8975 14:48:48.341340 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8976 14:48:48.344681 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8977 14:48:48.351406 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8978 14:48:48.354869 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8979 14:48:48.354948 ==
8980 14:48:48.357685 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 14:48:48.360765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 14:48:48.360861 ==
8983 14:48:48.364219 DQS Delay:
8984 14:48:48.364298 DQS0 = 0, DQS1 = 0
8985 14:48:48.364375 DQM Delay:
8986 14:48:48.367931 DQM0 = 127, DQM1 = 125
8987 14:48:48.368010 DQ Delay:
8988 14:48:48.370969 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
8989 14:48:48.374668 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
8990 14:48:48.377808 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
8991 14:48:48.384263 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =134
8992 14:48:48.384342
8993 14:48:48.384405
8994 14:48:48.384477
8995 14:48:48.387717 [DramC_TX_OE_Calibration] TA2
8996 14:48:48.391028 Original DQ_B0 (3 6) =30, OEN = 27
8997 14:48:48.391108 Original DQ_B1 (3 6) =30, OEN = 27
8998 14:48:48.394047 24, 0x0, End_B0=24 End_B1=24
8999 14:48:48.397514 25, 0x0, End_B0=25 End_B1=25
9000 14:48:48.400695 26, 0x0, End_B0=26 End_B1=26
9001 14:48:48.403862 27, 0x0, End_B0=27 End_B1=27
9002 14:48:48.403943 28, 0x0, End_B0=28 End_B1=28
9003 14:48:48.407246 29, 0x0, End_B0=29 End_B1=29
9004 14:48:48.410364 30, 0x0, End_B0=30 End_B1=30
9005 14:48:48.413896 31, 0x4141, End_B0=30 End_B1=30
9006 14:48:48.417321 Byte0 end_step=30 best_step=27
9007 14:48:48.420265 Byte1 end_step=30 best_step=27
9008 14:48:48.420370 Byte0 TX OE(2T, 0.5T) = (3, 3)
9009 14:48:48.423786 Byte1 TX OE(2T, 0.5T) = (3, 3)
9010 14:48:48.423866
9011 14:48:48.423929
9012 14:48:48.433791 [DQSOSCAuto] RK1, (LSB)MR18= 0xd19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
9013 14:48:48.436920 CH1 RK1: MR19=303, MR18=D19
9014 14:48:48.440263 CH1_RK1: MR19=0x303, MR18=0xD19, DQSOSC=397, MR23=63, INC=23, DEC=15
9015 14:48:48.443534 [RxdqsGatingPostProcess] freq 1600
9016 14:48:48.450400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9017 14:48:48.453718 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 14:48:48.456658 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 14:48:48.460022 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 14:48:48.463419 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 14:48:48.466713 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 14:48:48.466793 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 14:48:48.469928 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 14:48:48.473274 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 14:48:48.476446 Pre-setting of DQS Precalculation
9026 14:48:48.483547 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9027 14:48:48.489491 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9028 14:48:48.496298 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9029 14:48:48.496429
9030 14:48:48.496520
9031 14:48:48.499559 [Calibration Summary] 3200 Mbps
9032 14:48:48.502797 CH 0, Rank 0
9033 14:48:48.502873 SW Impedance : PASS
9034 14:48:48.506156 DUTY Scan : NO K
9035 14:48:48.509606 ZQ Calibration : PASS
9036 14:48:48.509696 Jitter Meter : NO K
9037 14:48:48.512817 CBT Training : PASS
9038 14:48:48.512892 Write leveling : PASS
9039 14:48:48.516445 RX DQS gating : PASS
9040 14:48:48.520004 RX DQ/DQS(RDDQC) : PASS
9041 14:48:48.520104 TX DQ/DQS : PASS
9042 14:48:48.522526 RX DATLAT : PASS
9043 14:48:48.526139 RX DQ/DQS(Engine): PASS
9044 14:48:48.526237 TX OE : PASS
9045 14:48:48.529461 All Pass.
9046 14:48:48.529534
9047 14:48:48.529594 CH 0, Rank 1
9048 14:48:48.532816 SW Impedance : PASS
9049 14:48:48.532894 DUTY Scan : NO K
9050 14:48:48.536308 ZQ Calibration : PASS
9051 14:48:48.539299 Jitter Meter : NO K
9052 14:48:48.539419 CBT Training : PASS
9053 14:48:48.542606 Write leveling : PASS
9054 14:48:48.545904 RX DQS gating : PASS
9055 14:48:48.546023 RX DQ/DQS(RDDQC) : PASS
9056 14:48:48.549390 TX DQ/DQS : PASS
9057 14:48:48.552924 RX DATLAT : PASS
9058 14:48:48.553005 RX DQ/DQS(Engine): PASS
9059 14:48:48.555542 TX OE : PASS
9060 14:48:48.555648 All Pass.
9061 14:48:48.555748
9062 14:48:48.558868 CH 1, Rank 0
9063 14:48:48.558968 SW Impedance : PASS
9064 14:48:48.562317 DUTY Scan : NO K
9065 14:48:48.565665 ZQ Calibration : PASS
9066 14:48:48.565752 Jitter Meter : NO K
9067 14:48:48.568954 CBT Training : PASS
9068 14:48:48.572116 Write leveling : PASS
9069 14:48:48.572188 RX DQS gating : PASS
9070 14:48:48.575467 RX DQ/DQS(RDDQC) : PASS
9071 14:48:48.578642 TX DQ/DQS : PASS
9072 14:48:48.578739 RX DATLAT : PASS
9073 14:48:48.582434 RX DQ/DQS(Engine): PASS
9074 14:48:48.582540 TX OE : PASS
9075 14:48:48.585420 All Pass.
9076 14:48:48.585493
9077 14:48:48.585554 CH 1, Rank 1
9078 14:48:48.588736 SW Impedance : PASS
9079 14:48:48.588846 DUTY Scan : NO K
9080 14:48:48.592233 ZQ Calibration : PASS
9081 14:48:48.595358 Jitter Meter : NO K
9082 14:48:48.595440 CBT Training : PASS
9083 14:48:48.598587 Write leveling : PASS
9084 14:48:48.601802 RX DQS gating : PASS
9085 14:48:48.601883 RX DQ/DQS(RDDQC) : PASS
9086 14:48:48.605446 TX DQ/DQS : PASS
9087 14:48:48.608495 RX DATLAT : PASS
9088 14:48:48.608586 RX DQ/DQS(Engine): PASS
9089 14:48:48.612058 TX OE : PASS
9090 14:48:48.612156 All Pass.
9091 14:48:48.612222
9092 14:48:48.615056 DramC Write-DBI on
9093 14:48:48.618259 PER_BANK_REFRESH: Hybrid Mode
9094 14:48:48.618341 TX_TRACKING: ON
9095 14:48:48.628235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9096 14:48:48.634897 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9097 14:48:48.641514 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 14:48:48.648050 [FAST_K] Save calibration result to emmc
9099 14:48:48.648136 sync common calibartion params.
9100 14:48:48.651363 sync cbt_mode0:1, 1:1
9101 14:48:48.654674 dram_init: ddr_geometry: 2
9102 14:48:48.654752 dram_init: ddr_geometry: 2
9103 14:48:48.657910 dram_init: ddr_geometry: 2
9104 14:48:48.661294 0:dram_rank_size:100000000
9105 14:48:48.664627 1:dram_rank_size:100000000
9106 14:48:48.667963 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9107 14:48:48.671260 DFS_SHUFFLE_HW_MODE: ON
9108 14:48:48.674498 dramc_set_vcore_voltage set vcore to 725000
9109 14:48:48.677744 Read voltage for 1600, 0
9110 14:48:48.677826 Vio18 = 0
9111 14:48:48.681057 Vcore = 725000
9112 14:48:48.681138 Vdram = 0
9113 14:48:48.681203 Vddq = 0
9114 14:48:48.681263 Vmddr = 0
9115 14:48:48.684729 switch to 3200 Mbps bootup
9116 14:48:48.687843 [DramcRunTimeConfig]
9117 14:48:48.687922 PHYPLL
9118 14:48:48.691008 DPM_CONTROL_AFTERK: ON
9119 14:48:48.691087 PER_BANK_REFRESH: ON
9120 14:48:48.694469 REFRESH_OVERHEAD_REDUCTION: ON
9121 14:48:48.697740 CMD_PICG_NEW_MODE: OFF
9122 14:48:48.697825 XRTWTW_NEW_MODE: ON
9123 14:48:48.701079 XRTRTR_NEW_MODE: ON
9124 14:48:48.701158 TX_TRACKING: ON
9125 14:48:48.704227 RDSEL_TRACKING: OFF
9126 14:48:48.704306 DQS Precalculation for DVFS: ON
9127 14:48:48.707702 RX_TRACKING: OFF
9128 14:48:48.707781 HW_GATING DBG: ON
9129 14:48:48.711008 ZQCS_ENABLE_LP4: ON
9130 14:48:48.714230 RX_PICG_NEW_MODE: ON
9131 14:48:48.714314 TX_PICG_NEW_MODE: ON
9132 14:48:48.717937 ENABLE_RX_DCM_DPHY: ON
9133 14:48:48.720831 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9134 14:48:48.720910 DUMMY_READ_FOR_TRACKING: OFF
9135 14:48:48.724679 !!! SPM_CONTROL_AFTERK: OFF
9136 14:48:48.727622 !!! SPM could not control APHY
9137 14:48:48.730894 IMPEDANCE_TRACKING: ON
9138 14:48:48.730974 TEMP_SENSOR: ON
9139 14:48:48.734054 HW_SAVE_FOR_SR: OFF
9140 14:48:48.737734 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9141 14:48:48.741126 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9142 14:48:48.741206 Read ODT Tracking: ON
9143 14:48:48.744153 Refresh Rate DeBounce: ON
9144 14:48:48.747309 DFS_NO_QUEUE_FLUSH: ON
9145 14:48:48.750795 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9146 14:48:48.750874 ENABLE_DFS_RUNTIME_MRW: OFF
9147 14:48:48.753985 DDR_RESERVE_NEW_MODE: ON
9148 14:48:48.757154 MR_CBT_SWITCH_FREQ: ON
9149 14:48:48.757233 =========================
9150 14:48:48.777210 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9151 14:48:48.780896 dram_init: ddr_geometry: 2
9152 14:48:48.798721 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9153 14:48:48.802452 dram_init: dram init end (result: 0)
9154 14:48:48.809144 DRAM-K: Full calibration passed in 24549 msecs
9155 14:48:48.811946 MRC: failed to locate region type 0.
9156 14:48:48.812026 DRAM rank0 size:0x100000000,
9157 14:48:48.815360 DRAM rank1 size=0x100000000
9158 14:48:48.825386 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9159 14:48:48.832210 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9160 14:48:48.838838 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9161 14:48:48.848402 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9162 14:48:48.848483 DRAM rank0 size:0x100000000,
9163 14:48:48.851378 DRAM rank1 size=0x100000000
9164 14:48:48.851457 CBMEM:
9165 14:48:48.854950 IMD: root @ 0xfffff000 254 entries.
9166 14:48:48.858208 IMD: root @ 0xffffec00 62 entries.
9167 14:48:48.861760 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9168 14:48:48.868256 WARNING: RO_VPD is uninitialized or empty.
9169 14:48:48.871435 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9170 14:48:48.879361 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9171 14:48:48.891878 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9172 14:48:48.903155 BS: romstage times (exec / console): total (unknown) / 24017 ms
9173 14:48:48.903253
9174 14:48:48.903330
9175 14:48:48.912977 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9176 14:48:48.916212 ARM64: Exception handlers installed.
9177 14:48:48.919479 ARM64: Testing exception
9178 14:48:48.922830 ARM64: Done test exception
9179 14:48:48.922938 Enumerating buses...
9180 14:48:48.926141 Show all devs... Before device enumeration.
9181 14:48:48.929775 Root Device: enabled 1
9182 14:48:48.933229 CPU_CLUSTER: 0: enabled 1
9183 14:48:48.933308 CPU: 00: enabled 1
9184 14:48:48.936372 Compare with tree...
9185 14:48:48.936481 Root Device: enabled 1
9186 14:48:48.939527 CPU_CLUSTER: 0: enabled 1
9187 14:48:48.943018 CPU: 00: enabled 1
9188 14:48:48.943098 Root Device scanning...
9189 14:48:48.946164 scan_static_bus for Root Device
9190 14:48:48.949262 CPU_CLUSTER: 0 enabled
9191 14:48:48.953106 scan_static_bus for Root Device done
9192 14:48:48.956192 scan_bus: bus Root Device finished in 8 msecs
9193 14:48:48.956288 done
9194 14:48:48.962610 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9195 14:48:48.965979 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9196 14:48:48.972921 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9197 14:48:48.975914 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9198 14:48:48.978964 Allocating resources...
9199 14:48:48.982594 Reading resources...
9200 14:48:48.985673 Root Device read_resources bus 0 link: 0
9201 14:48:48.985753 DRAM rank0 size:0x100000000,
9202 14:48:48.988962 DRAM rank1 size=0x100000000
9203 14:48:48.992906 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9204 14:48:48.995565 CPU: 00 missing read_resources
9205 14:48:49.002041 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9206 14:48:49.005429 Root Device read_resources bus 0 link: 0 done
9207 14:48:49.005516 Done reading resources.
9208 14:48:49.012024 Show resources in subtree (Root Device)...After reading.
9209 14:48:49.015543 Root Device child on link 0 CPU_CLUSTER: 0
9210 14:48:49.018931 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 14:48:49.028757 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 14:48:49.028838 CPU: 00
9213 14:48:49.031889 Root Device assign_resources, bus 0 link: 0
9214 14:48:49.035668 CPU_CLUSTER: 0 missing set_resources
9215 14:48:49.041672 Root Device assign_resources, bus 0 link: 0 done
9216 14:48:49.041752 Done setting resources.
9217 14:48:49.048814 Show resources in subtree (Root Device)...After assigning values.
9218 14:48:49.051887 Root Device child on link 0 CPU_CLUSTER: 0
9219 14:48:49.055370 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 14:48:49.065127 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 14:48:49.065208 CPU: 00
9222 14:48:49.068311 Done allocating resources.
9223 14:48:49.074826 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9224 14:48:49.074906 Enabling resources...
9225 14:48:49.074970 done.
9226 14:48:49.081646 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9227 14:48:49.081726 Initializing devices...
9228 14:48:49.084966 Root Device init
9229 14:48:49.088446 init hardware done!
9230 14:48:49.088547 0x00000018: ctrlr->caps
9231 14:48:49.091426 52.000 MHz: ctrlr->f_max
9232 14:48:49.094654 0.400 MHz: ctrlr->f_min
9233 14:48:49.094737 0x40ff8080: ctrlr->voltages
9234 14:48:49.098319 sclk: 390625
9235 14:48:49.098399 Bus Width = 1
9236 14:48:49.098462 sclk: 390625
9237 14:48:49.101273 Bus Width = 1
9238 14:48:49.101355 Early init status = 3
9239 14:48:49.107924 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9240 14:48:49.111259 in-header: 03 fc 00 00 01 00 00 00
9241 14:48:49.114881 in-data: 00
9242 14:48:49.118189 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9243 14:48:49.122217 in-header: 03 fd 00 00 00 00 00 00
9244 14:48:49.125754 in-data:
9245 14:48:49.129000 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9246 14:48:49.133351 in-header: 03 fc 00 00 01 00 00 00
9247 14:48:49.136688 in-data: 00
9248 14:48:49.139943 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9249 14:48:49.145589 in-header: 03 fd 00 00 00 00 00 00
9250 14:48:49.148685 in-data:
9251 14:48:49.151804 [SSUSB] Setting up USB HOST controller...
9252 14:48:49.155177 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9253 14:48:49.158956 [SSUSB] phy power-on done.
9254 14:48:49.161764 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9255 14:48:49.168914 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9256 14:48:49.171860 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9257 14:48:49.178298 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9258 14:48:49.185244 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9259 14:48:49.191804 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9260 14:48:49.198705 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9261 14:48:49.205194 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9262 14:48:49.208796 SPM: binary array size = 0x9dc
9263 14:48:49.212057 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9264 14:48:49.218468 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9265 14:48:49.225142 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9266 14:48:49.228405 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9267 14:48:49.234966 configure_display: Starting display init
9268 14:48:49.268546 anx7625_power_on_init: Init interface.
9269 14:48:49.271962 anx7625_disable_pd_protocol: Disabled PD feature.
9270 14:48:49.275141 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9271 14:48:49.303048 anx7625_start_dp_work: Secure OCM version=00
9272 14:48:49.306136 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9273 14:48:49.321179 sp_tx_get_edid_block: EDID Block = 1
9274 14:48:49.423492 Extracted contents:
9275 14:48:49.427112 header: 00 ff ff ff ff ff ff 00
9276 14:48:49.430650 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9277 14:48:49.433470 version: 01 04
9278 14:48:49.436623 basic params: 95 1f 11 78 0a
9279 14:48:49.440008 chroma info: 76 90 94 55 54 90 27 21 50 54
9280 14:48:49.443769 established: 00 00 00
9281 14:48:49.450087 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9282 14:48:49.453672 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9283 14:48:49.459724 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9284 14:48:49.466434 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9285 14:48:49.473311 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9286 14:48:49.476538 extensions: 00
9287 14:48:49.476641 checksum: fb
9288 14:48:49.476704
9289 14:48:49.479906 Manufacturer: IVO Model 57d Serial Number 0
9290 14:48:49.483234 Made week 0 of 2020
9291 14:48:49.483314 EDID version: 1.4
9292 14:48:49.486304 Digital display
9293 14:48:49.489641 6 bits per primary color channel
9294 14:48:49.489721 DisplayPort interface
9295 14:48:49.493036 Maximum image size: 31 cm x 17 cm
9296 14:48:49.496383 Gamma: 220%
9297 14:48:49.496466 Check DPMS levels
9298 14:48:49.499589 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9299 14:48:49.506538 First detailed timing is preferred timing
9300 14:48:49.506618 Established timings supported:
9301 14:48:49.509503 Standard timings supported:
9302 14:48:49.513209 Detailed timings
9303 14:48:49.516488 Hex of detail: 383680a07038204018303c0035ae10000019
9304 14:48:49.523032 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9305 14:48:49.526451 0780 0798 07c8 0820 hborder 0
9306 14:48:49.529470 0438 043b 0447 0458 vborder 0
9307 14:48:49.532989 -hsync -vsync
9308 14:48:49.533069 Did detailed timing
9309 14:48:49.539601 Hex of detail: 000000000000000000000000000000000000
9310 14:48:49.543086 Manufacturer-specified data, tag 0
9311 14:48:49.545937 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9312 14:48:49.549262 ASCII string: InfoVision
9313 14:48:49.552956 Hex of detail: 000000fe00523134304e574635205248200a
9314 14:48:49.556113 ASCII string: R140NWF5 RH
9315 14:48:49.556193 Checksum
9316 14:48:49.559398 Checksum: 0xfb (valid)
9317 14:48:49.562575 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9318 14:48:49.565904 DSI data_rate: 832800000 bps
9319 14:48:49.572518 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9320 14:48:49.576068 anx7625_parse_edid: pixelclock(138800).
9321 14:48:49.579111 hactive(1920), hsync(48), hfp(24), hbp(88)
9322 14:48:49.582832 vactive(1080), vsync(12), vfp(3), vbp(17)
9323 14:48:49.585711 anx7625_dsi_config: config dsi.
9324 14:48:49.592524 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9325 14:48:49.605648 anx7625_dsi_config: success to config DSI
9326 14:48:49.608834 anx7625_dp_start: MIPI phy setup OK.
9327 14:48:49.612209 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9328 14:48:49.615711 mtk_ddp_mode_set invalid vrefresh 60
9329 14:48:49.618805 main_disp_path_setup
9330 14:48:49.618884 ovl_layer_smi_id_en
9331 14:48:49.622406 ovl_layer_smi_id_en
9332 14:48:49.622486 ccorr_config
9333 14:48:49.622548 aal_config
9334 14:48:49.625532 gamma_config
9335 14:48:49.625612 postmask_config
9336 14:48:49.629351 dither_config
9337 14:48:49.632539 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9338 14:48:49.639264 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9339 14:48:49.642094 Root Device init finished in 553 msecs
9340 14:48:49.645565 CPU_CLUSTER: 0 init
9341 14:48:49.652191 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9342 14:48:49.655597 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9343 14:48:49.658798 APU_MBOX 0x190000b0 = 0x10001
9344 14:48:49.662073 APU_MBOX 0x190001b0 = 0x10001
9345 14:48:49.665312 APU_MBOX 0x190005b0 = 0x10001
9346 14:48:49.668846 APU_MBOX 0x190006b0 = 0x10001
9347 14:48:49.672137 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9348 14:48:49.684706 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9349 14:48:49.697156 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9350 14:48:49.703647 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9351 14:48:49.715389 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9352 14:48:49.724745 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9353 14:48:49.727816 CPU_CLUSTER: 0 init finished in 81 msecs
9354 14:48:49.730855 Devices initialized
9355 14:48:49.734322 Show all devs... After init.
9356 14:48:49.734399 Root Device: enabled 1
9357 14:48:49.737650 CPU_CLUSTER: 0: enabled 1
9358 14:48:49.741177 CPU: 00: enabled 1
9359 14:48:49.744158 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9360 14:48:49.747718 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9361 14:48:49.750800 ELOG: NV offset 0x57f000 size 0x1000
9362 14:48:49.757720 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9363 14:48:49.764235 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9364 14:48:49.767529 ELOG: Event(17) added with size 13 at 2024-06-04 14:48:49 UTC
9365 14:48:49.774255 out: cmd=0x121: 03 db 21 01 00 00 00 00
9366 14:48:49.777212 in-header: 03 76 00 00 2c 00 00 00
9367 14:48:49.787438 in-data: e9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9368 14:48:49.794028 ELOG: Event(A1) added with size 10 at 2024-06-04 14:48:49 UTC
9369 14:48:49.800553 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9370 14:48:49.807394 ELOG: Event(A0) added with size 9 at 2024-06-04 14:48:49 UTC
9371 14:48:49.810685 elog_add_boot_reason: Logged dev mode boot
9372 14:48:49.817160 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9373 14:48:49.817241 Finalize devices...
9374 14:48:49.820349 Devices finalized
9375 14:48:49.824003 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9376 14:48:49.827285 Writing coreboot table at 0xffe64000
9377 14:48:49.830520 0. 000000000010a000-0000000000113fff: RAMSTAGE
9378 14:48:49.833841 1. 0000000040000000-00000000400fffff: RAM
9379 14:48:49.840241 2. 0000000040100000-000000004032afff: RAMSTAGE
9380 14:48:49.843613 3. 000000004032b000-00000000545fffff: RAM
9381 14:48:49.846651 4. 0000000054600000-000000005465ffff: BL31
9382 14:48:49.850215 5. 0000000054660000-00000000ffe63fff: RAM
9383 14:48:49.857268 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9384 14:48:49.860156 7. 0000000100000000-000000023fffffff: RAM
9385 14:48:49.863580 Passing 5 GPIOs to payload:
9386 14:48:49.867024 NAME | PORT | POLARITY | VALUE
9387 14:48:49.873430 EC in RW | 0x000000aa | low | undefined
9388 14:48:49.876526 EC interrupt | 0x00000005 | low | undefined
9389 14:48:49.879850 TPM interrupt | 0x000000ab | high | undefined
9390 14:48:49.886449 SD card detect | 0x00000011 | high | undefined
9391 14:48:49.889853 speaker enable | 0x00000093 | high | undefined
9392 14:48:49.893084 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9393 14:48:49.896313 in-header: 03 f9 00 00 02 00 00 00
9394 14:48:49.899517 in-data: 02 00
9395 14:48:49.902847 ADC[4]: Raw value=894081 ID=7
9396 14:48:49.902949 ADC[3]: Raw value=213440 ID=1
9397 14:48:49.906465 RAM Code: 0x71
9398 14:48:49.909754 ADC[6]: Raw value=74722 ID=0
9399 14:48:49.909858 ADC[5]: Raw value=212700 ID=1
9400 14:48:49.913053 SKU Code: 0x1
9401 14:48:49.916460 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 236
9402 14:48:49.919569 coreboot table: 964 bytes.
9403 14:48:49.922919 IMD ROOT 0. 0xfffff000 0x00001000
9404 14:48:49.926330 IMD SMALL 1. 0xffffe000 0x00001000
9405 14:48:49.929770 RO MCACHE 2. 0xffffc000 0x00001104
9406 14:48:49.932563 CONSOLE 3. 0xfff7c000 0x00080000
9407 14:48:49.936577 FMAP 4. 0xfff7b000 0x00000452
9408 14:48:49.939616 TIME STAMP 5. 0xfff7a000 0x00000910
9409 14:48:49.943091 VBOOT WORK 6. 0xfff66000 0x00014000
9410 14:48:49.945803 RAMOOPS 7. 0xffe66000 0x00100000
9411 14:48:49.949223 COREBOOT 8. 0xffe64000 0x00002000
9412 14:48:49.952346 IMD small region:
9413 14:48:49.955815 IMD ROOT 0. 0xffffec00 0x00000400
9414 14:48:49.959444 VPD 1. 0xffffeb80 0x0000006c
9415 14:48:49.962470 MMC STATUS 2. 0xffffeb60 0x00000004
9416 14:48:49.965662 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9417 14:48:49.969467 Probing TPM: done!
9418 14:48:49.972505 Connected to device vid:did:rid of 1ae0:0028:00
9419 14:48:49.983430 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9420 14:48:49.986833 Initialized TPM device CR50 revision 0
9421 14:48:49.990201 Checking cr50 for pending updates
9422 14:48:49.994302 Reading cr50 TPM mode
9423 14:48:50.002744 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9424 14:48:50.009397 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9425 14:48:50.049487 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9426 14:48:50.052592 Checking segment from ROM address 0x40100000
9427 14:48:50.056183 Checking segment from ROM address 0x4010001c
9428 14:48:50.062871 Loading segment from ROM address 0x40100000
9429 14:48:50.062980 code (compression=0)
9430 14:48:50.072298 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9431 14:48:50.079198 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9432 14:48:50.079286 it's not compressed!
9433 14:48:50.085898 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9434 14:48:50.092543 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9435 14:48:50.110263 Loading segment from ROM address 0x4010001c
9436 14:48:50.110378 Entry Point 0x80000000
9437 14:48:50.113561 Loaded segments
9438 14:48:50.116102 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9439 14:48:50.123214 Jumping to boot code at 0x80000000(0xffe64000)
9440 14:48:50.129746 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9441 14:48:50.136574 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9442 14:48:50.144325 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9443 14:48:50.147426 Checking segment from ROM address 0x40100000
9444 14:48:50.150912 Checking segment from ROM address 0x4010001c
9445 14:48:50.157337 Loading segment from ROM address 0x40100000
9446 14:48:50.157440 code (compression=1)
9447 14:48:50.164610 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9448 14:48:50.174000 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9449 14:48:50.174127 using LZMA
9450 14:48:50.182643 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9451 14:48:50.189366 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9452 14:48:50.192889 Loading segment from ROM address 0x4010001c
9453 14:48:50.193000 Entry Point 0x54601000
9454 14:48:50.195991 Loaded segments
9455 14:48:50.199190 NOTICE: MT8192 bl31_setup
9456 14:48:50.206039 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9457 14:48:50.209376 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9458 14:48:50.213119 WARNING: region 0:
9459 14:48:50.216142 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 14:48:50.216252 WARNING: region 1:
9461 14:48:50.222646 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9462 14:48:50.226251 WARNING: region 2:
9463 14:48:50.229231 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9464 14:48:50.232745 WARNING: region 3:
9465 14:48:50.236166 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 14:48:50.239520 WARNING: region 4:
9467 14:48:50.246221 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 14:48:50.246308 WARNING: region 5:
9469 14:48:50.249457 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 14:48:50.253060 WARNING: region 6:
9471 14:48:50.256437 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 14:48:50.259705 WARNING: region 7:
9473 14:48:50.262705 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 14:48:50.269250 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9475 14:48:50.272638 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9476 14:48:50.276459 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9477 14:48:50.282891 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9478 14:48:50.286247 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9479 14:48:50.289499 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9480 14:48:50.296142 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9481 14:48:50.299480 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9482 14:48:50.306053 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9483 14:48:50.309503 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9484 14:48:50.312716 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9485 14:48:50.319291 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9486 14:48:50.322998 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9487 14:48:50.326590 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9488 14:48:50.332848 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9489 14:48:50.336177 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9490 14:48:50.342572 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9491 14:48:50.346279 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9492 14:48:50.349175 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9493 14:48:50.355818 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9494 14:48:50.359301 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9495 14:48:50.362649 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9496 14:48:50.369259 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9497 14:48:50.372594 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9498 14:48:50.379427 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9499 14:48:50.382246 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9500 14:48:50.388908 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9501 14:48:50.392271 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9502 14:48:50.395605 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9503 14:48:50.402247 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9504 14:48:50.405874 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9505 14:48:50.408736 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9506 14:48:50.415229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9507 14:48:50.419053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9508 14:48:50.422069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9509 14:48:50.425722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9510 14:48:50.432112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9511 14:48:50.435718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9512 14:48:50.438972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9513 14:48:50.442074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9514 14:48:50.449074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9515 14:48:50.452092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9516 14:48:50.455465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9517 14:48:50.459153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9518 14:48:50.465895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9519 14:48:50.469167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9520 14:48:50.472414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9521 14:48:50.475505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9522 14:48:50.482289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9523 14:48:50.485643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9524 14:48:50.492427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9525 14:48:50.495351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9526 14:48:50.502150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9527 14:48:50.505610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9528 14:48:50.509014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9529 14:48:50.515766 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9530 14:48:50.519081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9531 14:48:50.525313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9532 14:48:50.528681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9533 14:48:50.535823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9534 14:48:50.539035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9535 14:48:50.545515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9536 14:48:50.548865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9537 14:48:50.552288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9538 14:48:50.559196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9539 14:48:50.562574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9540 14:48:50.568924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9541 14:48:50.572294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9542 14:48:50.578939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9543 14:48:50.581956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9544 14:48:50.585288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9545 14:48:50.592093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9546 14:48:50.595490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9547 14:48:50.601797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9548 14:48:50.605732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9549 14:48:50.611994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9550 14:48:50.615434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9551 14:48:50.618669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9552 14:48:50.625409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9553 14:48:50.628692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9554 14:48:50.635838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9555 14:48:50.638569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9556 14:48:50.645364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9557 14:48:50.649030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9558 14:48:50.652349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9559 14:48:50.658911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9560 14:48:50.662151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9561 14:48:50.668641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9562 14:48:50.672047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9563 14:48:50.678632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9564 14:48:50.682245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9565 14:48:50.685563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9566 14:48:50.691889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9567 14:48:50.695545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9568 14:48:50.702180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9569 14:48:50.705386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9570 14:48:50.709146 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9571 14:48:50.715243 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9572 14:48:50.718540 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9573 14:48:50.721862 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9574 14:48:50.725812 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9575 14:48:50.731869 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9576 14:48:50.735162 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9577 14:48:50.742367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9578 14:48:50.745153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9579 14:48:50.748514 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9580 14:48:50.755570 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9581 14:48:50.758989 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9582 14:48:50.765186 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9583 14:48:50.768355 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9584 14:48:50.771687 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9585 14:48:50.778672 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9586 14:48:50.781894 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9587 14:48:50.788339 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9588 14:48:50.791710 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9589 14:48:50.794919 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9590 14:48:50.801587 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9591 14:48:50.805062 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9592 14:48:50.808392 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9593 14:48:50.814997 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9594 14:48:50.818238 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9595 14:48:50.821757 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9596 14:48:50.824857 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9597 14:48:50.831373 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9598 14:48:50.834881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9599 14:48:50.837871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9600 14:48:50.845128 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9601 14:48:50.848189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9602 14:48:50.855139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9603 14:48:50.858034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9604 14:48:50.861338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9605 14:48:50.868135 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9606 14:48:50.871334 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9607 14:48:50.877870 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9608 14:48:50.881175 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9609 14:48:50.884589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9610 14:48:50.891621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9611 14:48:50.894898 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9612 14:48:50.898183 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9613 14:48:50.904881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9614 14:48:50.907907 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9615 14:48:50.914541 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9616 14:48:50.918260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9617 14:48:50.921560 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9618 14:48:50.928177 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9619 14:48:50.931419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9620 14:48:50.937878 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9621 14:48:50.941169 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9622 14:48:50.944989 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9623 14:48:50.951105 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9624 14:48:50.954466 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9625 14:48:50.957942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9626 14:48:50.965045 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9627 14:48:50.967909 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9628 14:48:50.974846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9629 14:48:50.978092 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9630 14:48:50.981576 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9631 14:48:50.988051 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9632 14:48:50.991210 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9633 14:48:50.997842 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9634 14:48:51.001180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9635 14:48:51.004522 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9636 14:48:51.011113 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9637 14:48:51.014642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9638 14:48:51.021108 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9639 14:48:51.024436 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9640 14:48:51.027868 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9641 14:48:51.034119 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9642 14:48:51.037361 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9643 14:48:51.043875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9644 14:48:51.047168 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9645 14:48:51.050957 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9646 14:48:51.057221 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9647 14:48:51.060653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9648 14:48:51.067207 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9649 14:48:51.070515 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9650 14:48:51.073940 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9651 14:48:51.080481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9652 14:48:51.084364 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9653 14:48:51.090584 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9654 14:48:51.093807 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9655 14:48:51.097453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9656 14:48:51.103800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9657 14:48:51.106891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9658 14:48:51.113578 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9659 14:48:51.117024 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9660 14:48:51.120262 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9661 14:48:51.126775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9662 14:48:51.130265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9663 14:48:51.136964 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9664 14:48:51.140440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9665 14:48:51.143786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9666 14:48:51.150278 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9667 14:48:51.153751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9668 14:48:51.159949 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9669 14:48:51.163179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9670 14:48:51.170153 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9671 14:48:51.173378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9672 14:48:51.176405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9673 14:48:51.183022 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9674 14:48:51.186449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9675 14:48:51.193465 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9676 14:48:51.196433 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9677 14:48:51.199900 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9678 14:48:51.206302 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9679 14:48:51.209849 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9680 14:48:51.216850 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9681 14:48:51.219758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9682 14:48:51.223246 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9683 14:48:51.229800 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9684 14:48:51.233114 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9685 14:48:51.239956 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9686 14:48:51.243327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9687 14:48:51.249562 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9688 14:48:51.252809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9689 14:48:51.256356 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9690 14:48:51.262873 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9691 14:48:51.266086 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9692 14:48:51.273394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9693 14:48:51.276583 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9694 14:48:51.279980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9695 14:48:51.286073 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9696 14:48:51.289507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9697 14:48:51.295876 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9698 14:48:51.299072 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9699 14:48:51.306006 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9700 14:48:51.309448 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9701 14:48:51.315820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9702 14:48:51.319150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9703 14:48:51.322455 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9704 14:48:51.325920 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9705 14:48:51.332449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9706 14:48:51.335752 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9707 14:48:51.339112 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9708 14:48:51.342398 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9709 14:48:51.348890 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9710 14:48:51.352143 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9711 14:48:51.358784 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9712 14:48:51.362168 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9713 14:48:51.365561 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9714 14:48:51.372120 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9715 14:48:51.375287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9716 14:48:51.382132 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9717 14:48:51.385588 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9718 14:48:51.388915 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9719 14:48:51.395081 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9720 14:48:51.398486 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9721 14:48:51.401937 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9722 14:48:51.408646 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9723 14:48:51.411452 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9724 14:48:51.415129 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9725 14:48:51.421818 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9726 14:48:51.424803 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9727 14:48:51.427961 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9728 14:48:51.434901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9729 14:48:51.438244 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9730 14:48:51.444421 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9731 14:48:51.448051 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9732 14:48:51.451429 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9733 14:48:51.457707 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9734 14:48:51.460959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9735 14:48:51.467709 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9736 14:48:51.471256 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9737 14:48:51.474150 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9738 14:48:51.481203 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9739 14:48:51.484172 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9740 14:48:51.487372 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9741 14:48:51.494207 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9742 14:48:51.497297 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9743 14:48:51.500810 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9744 14:48:51.504228 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9745 14:48:51.510912 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9746 14:48:51.513927 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9747 14:48:51.517144 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9748 14:48:51.520544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9749 14:48:51.527722 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9750 14:48:51.530900 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9751 14:48:51.533685 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9752 14:48:51.536893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9753 14:48:51.543889 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9754 14:48:51.547065 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9755 14:48:51.550260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9756 14:48:51.556685 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9757 14:48:51.560178 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9758 14:48:51.566864 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9759 14:48:51.570368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9760 14:48:51.573370 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9761 14:48:51.579842 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9762 14:48:51.583372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9763 14:48:51.589937 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9764 14:48:51.593381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9765 14:48:51.599882 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9766 14:48:51.602924 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9767 14:48:51.606311 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9768 14:48:51.613163 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9769 14:48:51.616615 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9770 14:48:51.623158 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9771 14:48:51.626363 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9772 14:48:51.629711 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9773 14:48:51.636271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9774 14:48:51.639565 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9775 14:48:51.646243 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9776 14:48:51.649570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9777 14:48:51.656471 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9778 14:48:51.659296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9779 14:48:51.662754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9780 14:48:51.669301 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9781 14:48:51.672482 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9782 14:48:51.679155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9783 14:48:51.682366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9784 14:48:51.685948 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9785 14:48:51.692299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9786 14:48:51.695919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9787 14:48:51.702823 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9788 14:48:51.705626 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9789 14:48:51.709457 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9790 14:48:51.715656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9791 14:48:51.719076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9792 14:48:51.725604 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9793 14:48:51.728994 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9794 14:48:51.735596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9795 14:48:51.739008 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9796 14:48:51.742897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9797 14:48:51.749105 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9798 14:48:51.752038 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9799 14:48:51.758577 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9800 14:48:51.762369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9801 14:48:51.765673 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9802 14:48:51.771893 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9803 14:48:51.775477 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9804 14:48:51.782282 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9805 14:48:51.785632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9806 14:48:51.788862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9807 14:48:51.795376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9808 14:48:51.798763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9809 14:48:51.805204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9810 14:48:51.808725 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9811 14:48:51.811864 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9812 14:48:51.818845 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9813 14:48:51.821691 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9814 14:48:51.828249 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9815 14:48:51.831642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9816 14:48:51.838205 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9817 14:48:51.841885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9818 14:48:51.844688 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9819 14:48:51.851676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9820 14:48:51.854645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9821 14:48:51.861335 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9822 14:48:51.864575 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9823 14:48:51.871126 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9824 14:48:51.874458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9825 14:48:51.878001 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9826 14:48:51.884257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9827 14:48:51.887596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9828 14:48:51.894244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9829 14:48:51.897545 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9830 14:48:51.900827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9831 14:48:51.907848 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9832 14:48:51.910625 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9833 14:48:51.917392 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9834 14:48:51.920816 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9835 14:48:51.927116 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9836 14:48:51.930658 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9837 14:48:51.937142 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9838 14:48:51.940680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9839 14:48:51.943916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9840 14:48:51.950544 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9841 14:48:51.953653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9842 14:48:51.960402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9843 14:48:51.963703 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9844 14:48:51.970548 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9845 14:48:51.973956 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9846 14:48:51.980149 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9847 14:48:51.983923 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9848 14:48:51.986884 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9849 14:48:51.993804 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9850 14:48:51.996475 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9851 14:48:52.003335 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9852 14:48:52.006711 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9853 14:48:52.013600 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9854 14:48:52.016888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9855 14:48:52.020130 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9856 14:48:52.026382 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9857 14:48:52.029833 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9858 14:48:52.036934 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9859 14:48:52.040213 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9860 14:48:52.046591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9861 14:48:52.049646 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9862 14:48:52.056359 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9863 14:48:52.059978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9864 14:48:52.063372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9865 14:48:52.069808 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9866 14:48:52.073175 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9867 14:48:52.079450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9868 14:48:52.082757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9869 14:48:52.089841 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9870 14:48:52.092566 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9871 14:48:52.096187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9872 14:48:52.102953 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9873 14:48:52.106330 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9874 14:48:52.112764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9875 14:48:52.115852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9876 14:48:52.119763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9877 14:48:52.125814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9878 14:48:52.129231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9879 14:48:52.135573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9880 14:48:52.139324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9881 14:48:52.145967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9882 14:48:52.149177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9883 14:48:52.155981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9884 14:48:52.158938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9885 14:48:52.165656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9886 14:48:52.169309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9887 14:48:52.175887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9888 14:48:52.178910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9889 14:48:52.185437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9890 14:48:52.189071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9891 14:48:52.195224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9892 14:48:52.198798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9893 14:48:52.205499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9894 14:48:52.208933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9895 14:48:52.215407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9896 14:48:52.218800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9897 14:48:52.225478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9898 14:48:52.228705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9899 14:48:52.234858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9900 14:48:52.238285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9901 14:48:52.245279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9902 14:48:52.248234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9903 14:48:52.254889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9904 14:48:52.258463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9905 14:48:52.264834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9906 14:48:52.268177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9907 14:48:52.275182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9908 14:48:52.278047 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9909 14:48:52.281714 INFO: [APUAPC] vio 0
9910 14:48:52.284755 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9911 14:48:52.291237 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9912 14:48:52.294635 INFO: [APUAPC] D0_APC_0: 0x400510
9913 14:48:52.294726 INFO: [APUAPC] D0_APC_1: 0x0
9914 14:48:52.297826 INFO: [APUAPC] D0_APC_2: 0x1540
9915 14:48:52.301493 INFO: [APUAPC] D0_APC_3: 0x0
9916 14:48:52.304357 INFO: [APUAPC] D1_APC_0: 0xffffffff
9917 14:48:52.307741 INFO: [APUAPC] D1_APC_1: 0xffffffff
9918 14:48:52.311239 INFO: [APUAPC] D1_APC_2: 0x3fffff
9919 14:48:52.314622 INFO: [APUAPC] D1_APC_3: 0x0
9920 14:48:52.317974 INFO: [APUAPC] D2_APC_0: 0xffffffff
9921 14:48:52.321161 INFO: [APUAPC] D2_APC_1: 0xffffffff
9922 14:48:52.324463 INFO: [APUAPC] D2_APC_2: 0x3fffff
9923 14:48:52.327705 INFO: [APUAPC] D2_APC_3: 0x0
9924 14:48:52.331328 INFO: [APUAPC] D3_APC_0: 0xffffffff
9925 14:48:52.334177 INFO: [APUAPC] D3_APC_1: 0xffffffff
9926 14:48:52.337802 INFO: [APUAPC] D3_APC_2: 0x3fffff
9927 14:48:52.340756 INFO: [APUAPC] D3_APC_3: 0x0
9928 14:48:52.344015 INFO: [APUAPC] D4_APC_0: 0xffffffff
9929 14:48:52.347414 INFO: [APUAPC] D4_APC_1: 0xffffffff
9930 14:48:52.350872 INFO: [APUAPC] D4_APC_2: 0x3fffff
9931 14:48:52.354068 INFO: [APUAPC] D4_APC_3: 0x0
9932 14:48:52.357397 INFO: [APUAPC] D5_APC_0: 0xffffffff
9933 14:48:52.361039 INFO: [APUAPC] D5_APC_1: 0xffffffff
9934 14:48:52.364424 INFO: [APUAPC] D5_APC_2: 0x3fffff
9935 14:48:52.367623 INFO: [APUAPC] D5_APC_3: 0x0
9936 14:48:52.370994 INFO: [APUAPC] D6_APC_0: 0xffffffff
9937 14:48:52.374172 INFO: [APUAPC] D6_APC_1: 0xffffffff
9938 14:48:52.377301 INFO: [APUAPC] D6_APC_2: 0x3fffff
9939 14:48:52.380961 INFO: [APUAPC] D6_APC_3: 0x0
9940 14:48:52.383891 INFO: [APUAPC] D7_APC_0: 0xffffffff
9941 14:48:52.387248 INFO: [APUAPC] D7_APC_1: 0xffffffff
9942 14:48:52.390665 INFO: [APUAPC] D7_APC_2: 0x3fffff
9943 14:48:52.393903 INFO: [APUAPC] D7_APC_3: 0x0
9944 14:48:52.397429 INFO: [APUAPC] D8_APC_0: 0xffffffff
9945 14:48:52.400438 INFO: [APUAPC] D8_APC_1: 0xffffffff
9946 14:48:52.403954 INFO: [APUAPC] D8_APC_2: 0x3fffff
9947 14:48:52.407260 INFO: [APUAPC] D8_APC_3: 0x0
9948 14:48:52.410313 INFO: [APUAPC] D9_APC_0: 0xffffffff
9949 14:48:52.413522 INFO: [APUAPC] D9_APC_1: 0xffffffff
9950 14:48:52.416752 INFO: [APUAPC] D9_APC_2: 0x3fffff
9951 14:48:52.420162 INFO: [APUAPC] D9_APC_3: 0x0
9952 14:48:52.423650 INFO: [APUAPC] D10_APC_0: 0xffffffff
9953 14:48:52.427338 INFO: [APUAPC] D10_APC_1: 0xffffffff
9954 14:48:52.430191 INFO: [APUAPC] D10_APC_2: 0x3fffff
9955 14:48:52.433593 INFO: [APUAPC] D10_APC_3: 0x0
9956 14:48:52.436850 INFO: [APUAPC] D11_APC_0: 0xffffffff
9957 14:48:52.440514 INFO: [APUAPC] D11_APC_1: 0xffffffff
9958 14:48:52.443332 INFO: [APUAPC] D11_APC_2: 0x3fffff
9959 14:48:52.446668 INFO: [APUAPC] D11_APC_3: 0x0
9960 14:48:52.449894 INFO: [APUAPC] D12_APC_0: 0xffffffff
9961 14:48:52.453448 INFO: [APUAPC] D12_APC_1: 0xffffffff
9962 14:48:52.456740 INFO: [APUAPC] D12_APC_2: 0x3fffff
9963 14:48:52.460044 INFO: [APUAPC] D12_APC_3: 0x0
9964 14:48:52.463183 INFO: [APUAPC] D13_APC_0: 0xffffffff
9965 14:48:52.466900 INFO: [APUAPC] D13_APC_1: 0xffffffff
9966 14:48:52.470249 INFO: [APUAPC] D13_APC_2: 0x3fffff
9967 14:48:52.473584 INFO: [APUAPC] D13_APC_3: 0x0
9968 14:48:52.476909 INFO: [APUAPC] D14_APC_0: 0xffffffff
9969 14:48:52.479629 INFO: [APUAPC] D14_APC_1: 0xffffffff
9970 14:48:52.482950 INFO: [APUAPC] D14_APC_2: 0x3fffff
9971 14:48:52.486219 INFO: [APUAPC] D14_APC_3: 0x0
9972 14:48:52.489699 INFO: [APUAPC] D15_APC_0: 0xffffffff
9973 14:48:52.492836 INFO: [APUAPC] D15_APC_1: 0xffffffff
9974 14:48:52.496246 INFO: [APUAPC] D15_APC_2: 0x3fffff
9975 14:48:52.499808 INFO: [APUAPC] D15_APC_3: 0x0
9976 14:48:52.502838 INFO: [APUAPC] APC_CON: 0x4
9977 14:48:52.506200 INFO: [NOCDAPC] D0_APC_0: 0x0
9978 14:48:52.509571 INFO: [NOCDAPC] D0_APC_1: 0x0
9979 14:48:52.509651 INFO: [NOCDAPC] D1_APC_0: 0x0
9980 14:48:52.512735 INFO: [NOCDAPC] D1_APC_1: 0xfff
9981 14:48:52.516130 INFO: [NOCDAPC] D2_APC_0: 0x0
9982 14:48:52.519393 INFO: [NOCDAPC] D2_APC_1: 0xfff
9983 14:48:52.522743 INFO: [NOCDAPC] D3_APC_0: 0x0
9984 14:48:52.526048 INFO: [NOCDAPC] D3_APC_1: 0xfff
9985 14:48:52.529421 INFO: [NOCDAPC] D4_APC_0: 0x0
9986 14:48:52.532506 INFO: [NOCDAPC] D4_APC_1: 0xfff
9987 14:48:52.535918 INFO: [NOCDAPC] D5_APC_0: 0x0
9988 14:48:52.539304 INFO: [NOCDAPC] D5_APC_1: 0xfff
9989 14:48:52.542750 INFO: [NOCDAPC] D6_APC_0: 0x0
9990 14:48:52.542830 INFO: [NOCDAPC] D6_APC_1: 0xfff
9991 14:48:52.546236 INFO: [NOCDAPC] D7_APC_0: 0x0
9992 14:48:52.549246 INFO: [NOCDAPC] D7_APC_1: 0xfff
9993 14:48:52.552762 INFO: [NOCDAPC] D8_APC_0: 0x0
9994 14:48:52.555901 INFO: [NOCDAPC] D8_APC_1: 0xfff
9995 14:48:52.559370 INFO: [NOCDAPC] D9_APC_0: 0x0
9996 14:48:52.562540 INFO: [NOCDAPC] D9_APC_1: 0xfff
9997 14:48:52.566043 INFO: [NOCDAPC] D10_APC_0: 0x0
9998 14:48:52.569161 INFO: [NOCDAPC] D10_APC_1: 0xfff
9999 14:48:52.572479 INFO: [NOCDAPC] D11_APC_0: 0x0
10000 14:48:52.575920 INFO: [NOCDAPC] D11_APC_1: 0xfff
10001 14:48:52.579417 INFO: [NOCDAPC] D12_APC_0: 0x0
10002 14:48:52.582689 INFO: [NOCDAPC] D12_APC_1: 0xfff
10003 14:48:52.582769 INFO: [NOCDAPC] D13_APC_0: 0x0
10004 14:48:52.585994 INFO: [NOCDAPC] D13_APC_1: 0xfff
10005 14:48:52.589186 INFO: [NOCDAPC] D14_APC_0: 0x0
10006 14:48:52.592482 INFO: [NOCDAPC] D14_APC_1: 0xfff
10007 14:48:52.595783 INFO: [NOCDAPC] D15_APC_0: 0x0
10008 14:48:52.598863 INFO: [NOCDAPC] D15_APC_1: 0xfff
10009 14:48:52.602077 INFO: [NOCDAPC] APC_CON: 0x4
10010 14:48:52.605522 INFO: [APUAPC] set_apusys_apc done
10011 14:48:52.609064 INFO: [DEVAPC] devapc_init done
10012 14:48:52.612388 INFO: GICv3 without legacy support detected.
10013 14:48:52.615648 INFO: ARM GICv3 driver initialized in EL3
10014 14:48:52.621807 INFO: Maximum SPI INTID supported: 639
10015 14:48:52.625152 INFO: BL31: Initializing runtime services
10016 14:48:52.631878 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10017 14:48:52.631958 INFO: SPM: enable CPC mode
10018 14:48:52.638443 INFO: mcdi ready for mcusys-off-idle and system suspend
10019 14:48:52.641840 INFO: BL31: Preparing for EL3 exit to normal world
10020 14:48:52.645335 INFO: Entry point address = 0x80000000
10021 14:48:52.648180 INFO: SPSR = 0x8
10022 14:48:52.654528
10023 14:48:52.654607
10024 14:48:52.654670
10025 14:48:52.657836 Starting depthcharge on Spherion...
10026 14:48:52.657915
10027 14:48:52.657991 Wipe memory regions:
10028 14:48:52.658063
10029 14:48:52.658997 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10030 14:48:52.659122 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10031 14:48:52.659263 Setting prompt string to ['asurada:']
10032 14:48:52.659367 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10033 14:48:52.660819 [0x00000040000000, 0x00000054600000)
10034 14:48:52.783586
10035 14:48:52.783700 [0x00000054660000, 0x00000080000000)
10036 14:48:53.043904
10037 14:48:53.044032 [0x000000821a7280, 0x000000ffe64000)
10038 14:48:53.788319
10039 14:48:53.788462 [0x00000100000000, 0x00000240000000)
10040 14:48:55.678201
10041 14:48:55.681344 Initializing XHCI USB controller at 0x11200000.
10042 14:48:56.719774
10043 14:48:56.722458 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10044 14:48:56.722543
10045 14:48:56.722628
10046 14:48:56.722927 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 14:48:56.823277 asurada: tftpboot 192.168.201.1 14167057/tftp-deploy-88w71y31/kernel/image.itb 14167057/tftp-deploy-88w71y31/kernel/cmdline
10049 14:48:56.823443 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 14:48:56.823578 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10051 14:48:56.827634 tftpboot 192.168.201.1 14167057/tftp-deploy-88w71y31/kernel/image.itp-deploy-88w71y31/kernel/cmdline
10052 14:48:56.827759
10053 14:48:56.827870 Waiting for link
10054 14:48:56.987966
10055 14:48:56.988141 R8152: Initializing
10056 14:48:56.988253
10057 14:48:56.991324 Version 6 (ocp_data = 5c30)
10058 14:48:56.991445
10059 14:48:56.994464 R8152: Done initializing
10060 14:48:56.994584
10061 14:48:56.994691 Adding net device
10062 14:48:58.898797
10063 14:48:58.898935 done.
10064 14:48:58.898999
10065 14:48:58.899058 MAC: 00:24:32:30:78:ff
10066 14:48:58.899113
10067 14:48:58.901897 Sending DHCP discover... done.
10068 14:48:58.901977
10069 14:49:02.001385 Waiting for reply... done.
10070 14:49:02.001528
10071 14:49:02.001597 Sending DHCP request... done.
10072 14:49:02.005171
10073 14:49:02.008493 Waiting for reply... done.
10074 14:49:02.008608
10075 14:49:02.008707 My ip is 192.168.201.21
10076 14:49:02.008804
10077 14:49:02.011841 The DHCP server ip is 192.168.201.1
10078 14:49:02.011955
10079 14:49:02.019058 TFTP server IP predefined by user: 192.168.201.1
10080 14:49:02.019175
10081 14:49:02.025694 Bootfile predefined by user: 14167057/tftp-deploy-88w71y31/kernel/image.itb
10082 14:49:02.025809
10083 14:49:02.028471 Sending tftp read request... done.
10084 14:49:02.028566
10085 14:49:02.032368 Waiting for the transfer...
10086 14:49:02.032452
10087 14:49:02.565959 00000000 ################################################################
10088 14:49:02.566094
10089 14:49:03.113659 00080000 ################################################################
10090 14:49:03.113842
10091 14:49:03.647607 00100000 ################################################################
10092 14:49:03.647745
10093 14:49:04.184087 00180000 ################################################################
10094 14:49:04.184245
10095 14:49:04.710192 00200000 ################################################################
10096 14:49:04.710329
10097 14:49:05.247414 00280000 ################################################################
10098 14:49:05.247574
10099 14:49:05.785942 00300000 ################################################################
10100 14:49:05.786110
10101 14:49:06.330357 00380000 ################################################################
10102 14:49:06.330497
10103 14:49:06.871355 00400000 ################################################################
10104 14:49:06.871494
10105 14:49:07.408478 00480000 ################################################################
10106 14:49:07.408639
10107 14:49:07.951265 00500000 ################################################################
10108 14:49:07.951401
10109 14:49:08.509680 00580000 ################################################################
10110 14:49:08.509822
10111 14:49:09.055923 00600000 ################################################################
10112 14:49:09.056066
10113 14:49:09.603999 00680000 ################################################################
10114 14:49:09.604192
10115 14:49:10.139740 00700000 ################################################################
10116 14:49:10.139871
10117 14:49:10.683314 00780000 ################################################################
10118 14:49:10.683453
10119 14:49:11.234522 00800000 ################################################################
10120 14:49:11.234661
10121 14:49:11.798802 00880000 ################################################################
10122 14:49:11.799003
10123 14:49:12.375002 00900000 ################################################################
10124 14:49:12.375197
10125 14:49:12.954784 00980000 ################################################################
10126 14:49:12.954933
10127 14:49:13.515168 00a00000 ################################################################
10128 14:49:13.515314
10129 14:49:14.073128 00a80000 ################################################################
10130 14:49:14.073274
10131 14:49:14.620902 00b00000 ################################################################
10132 14:49:14.621107
10133 14:49:15.180940 00b80000 ################################################################
10134 14:49:15.181133
10135 14:49:15.729060 00c00000 ################################################################
10136 14:49:15.729199
10137 14:49:16.291735 00c80000 ################################################################
10138 14:49:16.291867
10139 14:49:16.840826 00d00000 ################################################################
10140 14:49:16.840961
10141 14:49:17.387343 00d80000 ################################################################
10142 14:49:17.387473
10143 14:49:17.932277 00e00000 ################################################################
10144 14:49:17.932503
10145 14:49:18.479628 00e80000 ################################################################
10146 14:49:18.479767
10147 14:49:19.032933 00f00000 ################################################################
10148 14:49:19.033072
10149 14:49:19.595124 00f80000 ################################################################
10150 14:49:19.595258
10151 14:49:20.153515 01000000 ################################################################
10152 14:49:20.153654
10153 14:49:20.701430 01080000 ################################################################
10154 14:49:20.701561
10155 14:49:21.272922 01100000 ################################################################
10156 14:49:21.273092
10157 14:49:21.831262 01180000 ################################################################
10158 14:49:21.831405
10159 14:49:22.402023 01200000 ################################################################
10160 14:49:22.402166
10161 14:49:22.952996 01280000 ################################################################
10162 14:49:22.953147
10163 14:49:23.504049 01300000 ################################################################
10164 14:49:23.504194
10165 14:49:24.075713 01380000 ################################################################
10166 14:49:24.075882
10167 14:49:24.630910 01400000 ################################################################
10168 14:49:24.631061
10169 14:49:25.209867 01480000 ################################################################
10170 14:49:25.210017
10171 14:49:25.789743 01500000 ################################################################
10172 14:49:25.789891
10173 14:49:26.349851 01580000 ################################################################
10174 14:49:26.350000
10175 14:49:26.921651 01600000 ################################################################
10176 14:49:26.921801
10177 14:49:27.495753 01680000 ################################################################
10178 14:49:27.495904
10179 14:49:28.070705 01700000 ################################################################
10180 14:49:28.070856
10181 14:49:28.628550 01780000 ################################################################
10182 14:49:28.628699
10183 14:49:29.176356 01800000 ################################################################
10184 14:49:29.176526
10185 14:49:29.717286 01880000 ################################################################
10186 14:49:29.717429
10187 14:49:30.277598 01900000 ################################################################
10188 14:49:30.277744
10189 14:49:30.823800 01980000 ################################################################
10190 14:49:30.823960
10191 14:49:31.363657 01a00000 ################################################################
10192 14:49:31.363802
10193 14:49:31.902076 01a80000 ################################################################
10194 14:49:31.902215
10195 14:49:32.444788 01b00000 ################################################################
10196 14:49:32.444920
10197 14:49:32.984429 01b80000 ################################################################
10198 14:49:32.984575
10199 14:49:33.517463 01c00000 ################################################################
10200 14:49:33.517605
10201 14:49:34.059558 01c80000 ################################################################
10202 14:49:34.059696
10203 14:49:34.633730 01d00000 ################################################################
10204 14:49:34.633876
10205 14:49:35.222819 01d80000 ################################################################
10206 14:49:35.222957
10207 14:49:35.784914 01e00000 ################################################################
10208 14:49:35.785050
10209 14:49:36.353645 01e80000 ################################################################
10210 14:49:36.353776
10211 14:49:36.916150 01f00000 ################################################################
10212 14:49:36.916354
10213 14:49:37.451781 01f80000 ################################################################
10214 14:49:37.451926
10215 14:49:37.995754 02000000 ################################################################
10216 14:49:37.995892
10217 14:49:38.555922 02080000 ################################################################
10218 14:49:38.556061
10219 14:49:39.123073 02100000 ################################################################
10220 14:49:39.123213
10221 14:49:39.681595 02180000 ################################################################
10222 14:49:39.681745
10223 14:49:40.244760 02200000 ################################################################
10224 14:49:40.244913
10225 14:49:40.835996 02280000 ################################################################
10226 14:49:40.836171
10227 14:49:41.395888 02300000 ################################################################
10228 14:49:41.396064
10229 14:49:41.936882 02380000 ################################################################
10230 14:49:41.937030
10231 14:49:42.494581 02400000 ################################################################
10232 14:49:42.494760
10233 14:49:43.044149 02480000 ################################################################
10234 14:49:43.044298
10235 14:49:43.598079 02500000 ################################################################
10236 14:49:43.598293
10237 14:49:44.140414 02580000 ################################################################
10238 14:49:44.140569
10239 14:49:44.694738 02600000 ################################################################
10240 14:49:44.694888
10241 14:49:45.251685 02680000 ################################################################
10242 14:49:45.251852
10243 14:49:45.809418 02700000 ################################################################
10244 14:49:45.809564
10245 14:49:46.376924 02780000 ################################################################
10246 14:49:46.377096
10247 14:49:46.911320 02800000 ################################################################
10248 14:49:46.911472
10249 14:49:47.465097 02880000 ################################################################
10250 14:49:47.465286
10251 14:49:48.033479 02900000 ################################################################
10252 14:49:48.033732
10253 14:49:48.595158 02980000 ################################################################
10254 14:49:48.595308
10255 14:49:49.159560 02a00000 ################################################################
10256 14:49:49.159703
10257 14:49:49.728499 02a80000 ################################################################
10258 14:49:49.728716
10259 14:49:50.283542 02b00000 ################################################################
10260 14:49:50.283683
10261 14:49:50.826587 02b80000 ################################################################
10262 14:49:50.826736
10263 14:49:51.389981 02c00000 ################################################################
10264 14:49:51.390173
10265 14:49:51.939076 02c80000 ################################################################
10266 14:49:51.939286
10267 14:49:52.506063 02d00000 ################################################################
10268 14:49:52.506214
10269 14:49:53.049315 02d80000 ################################################################
10270 14:49:53.049472
10271 14:49:53.579268 02e00000 ################################################################
10272 14:49:53.579475
10273 14:49:54.109526 02e80000 ################################################################
10274 14:49:54.109746
10275 14:49:54.671531 02f00000 ################################################################
10276 14:49:54.671724
10277 14:49:55.235782 02f80000 ################################################################
10278 14:49:55.235931
10279 14:49:55.803424 03000000 ################################################################
10280 14:49:55.803615
10281 14:49:56.361166 03080000 ################################################################
10282 14:49:56.361314
10283 14:49:56.939585 03100000 ################################################################
10284 14:49:56.939791
10285 14:49:57.521623 03180000 ################################################################
10286 14:49:57.521807
10287 14:49:58.094151 03200000 ################################################################
10288 14:49:58.094299
10289 14:49:58.679118 03280000 ################################################################
10290 14:49:58.679273
10291 14:49:59.247259 03300000 ################################################################
10292 14:49:59.247406
10293 14:49:59.833906 03380000 ################################################################
10294 14:49:59.834117
10295 14:50:00.402165 03400000 ################################################################
10296 14:50:00.402313
10297 14:50:00.970686 03480000 ################################################################
10298 14:50:00.970828
10299 14:50:01.540974 03500000 ################################################################
10300 14:50:01.541122
10301 14:50:02.115869 03580000 ################################################################
10302 14:50:02.116018
10303 14:50:02.692858 03600000 ################################################################
10304 14:50:02.693009
10305 14:50:03.257403 03680000 ################################################################
10306 14:50:03.257561
10307 14:50:03.823141 03700000 ################################################################
10308 14:50:03.823302
10309 14:50:04.400418 03780000 ################################################################
10310 14:50:04.400591
10311 14:50:04.953282 03800000 ################################################################
10312 14:50:04.953433
10313 14:50:05.519363 03880000 ################################################################
10314 14:50:05.519512
10315 14:50:06.080226 03900000 ################################################################
10316 14:50:06.080397
10317 14:50:06.641594 03980000 ################################################################
10318 14:50:06.641766
10319 14:50:07.220274 03a00000 ################################################################
10320 14:50:07.220451
10321 14:50:07.794078 03a80000 ################################################################
10322 14:50:07.794288
10323 14:50:08.339732 03b00000 ################################################################
10324 14:50:08.339916
10325 14:50:08.895732 03b80000 ################################################################
10326 14:50:08.895934
10327 14:50:09.457289 03c00000 ################################################################
10328 14:50:09.457506
10329 14:50:10.007070 03c80000 ################################################################
10330 14:50:10.007227
10331 14:50:10.586722 03d00000 ################################################################
10332 14:50:10.586871
10333 14:50:11.158033 03d80000 ################################################################
10334 14:50:11.158224
10335 14:50:11.725334 03e00000 ################################################################
10336 14:50:11.725547
10337 14:50:12.279889 03e80000 ################################################################
10338 14:50:12.280106
10339 14:50:12.844786 03f00000 ################################################################
10340 14:50:12.844942
10341 14:50:13.401204 03f80000 ################################################################
10342 14:50:13.401357
10343 14:50:13.972073 04000000 ################################################################
10344 14:50:13.972285
10345 14:50:14.544381 04080000 ################################################################
10346 14:50:14.544568
10347 14:50:15.093569 04100000 ################################################################
10348 14:50:15.093722
10349 14:50:15.648284 04180000 ################################################################
10350 14:50:15.648461
10351 14:50:16.192138 04200000 ################################################################
10352 14:50:16.192293
10353 14:50:16.738741 04280000 ################################################################
10354 14:50:16.738936
10355 14:50:17.282422 04300000 ################################################################
10356 14:50:17.282589
10357 14:50:17.848541 04380000 ################################################################
10358 14:50:17.848698
10359 14:50:18.406303 04400000 ################################################################
10360 14:50:18.406457
10361 14:50:18.963093 04480000 ################################################################
10362 14:50:18.963240
10363 14:50:19.521156 04500000 ################################################################
10364 14:50:19.521364
10365 14:50:20.068539 04580000 ################################################################
10366 14:50:20.068707
10367 14:50:20.626390 04600000 ################################################################
10368 14:50:20.626549
10369 14:50:20.810809 04680000 ##################### done.
10370 14:50:20.810970
10371 14:50:20.813980 The bootfile was 74093842 bytes long.
10372 14:50:20.814089
10373 14:50:20.818076 Sending tftp read request... done.
10374 14:50:20.818254
10375 14:50:20.818375 Waiting for the transfer...
10376 14:50:20.818441
10377 14:50:20.820578 00000000 # done.
10378 14:50:20.820713
10379 14:50:20.827299 Command line loaded dynamically from TFTP file: 14167057/tftp-deploy-88w71y31/kernel/cmdline
10380 14:50:20.827440
10381 14:50:20.840834 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10382 14:50:20.840988
10383 14:50:20.844081 Loading FIT.
10384 14:50:20.844192
10385 14:50:20.847233 Image ramdisk-1 has 60983930 bytes.
10386 14:50:20.847333
10387 14:50:20.847400 Image fdt-1 has 47258 bytes.
10388 14:50:20.850399
10389 14:50:20.850495 Image kernel-1 has 13060619 bytes.
10390 14:50:20.850561
10391 14:50:20.860944 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10392 14:50:20.861099
10393 14:50:20.877043 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10394 14:50:20.880344
10395 14:50:20.883346 Choosing best match conf-1 for compat google,spherion-rev2.
10396 14:50:20.888199
10397 14:50:20.892433 Connected to device vid:did:rid of 1ae0:0028:00
10398 14:50:20.899674
10399 14:50:20.902484 tpm_get_response: command 0x17b, return code 0x0
10400 14:50:20.902612
10401 14:50:20.905885 ec_init: CrosEC protocol v3 supported (256, 248)
10402 14:50:20.910433
10403 14:50:20.910533 tpm_cleanup: add release locality here.
10404 14:50:20.913299
10405 14:50:20.913383 Shutting down all USB controllers.
10406 14:50:20.913450
10407 14:50:20.916507 Removing current net device
10408 14:50:20.916669
10409 14:50:20.923235 Exiting depthcharge with code 4 at timestamp: 117554764
10410 14:50:20.923364
10411 14:50:20.926916 LZMA decompressing kernel-1 to 0x821a6718
10412 14:50:20.927024
10413 14:50:20.930019 LZMA decompressing kernel-1 to 0x40000000
10414 14:50:22.542317
10415 14:50:22.542468 jumping to kernel
10416 14:50:22.543399 end: 2.2.4 bootloader-commands (duration 00:01:30) [common]
10417 14:50:22.543510 start: 2.2.5 auto-login-action (timeout 00:02:55) [common]
10418 14:50:22.543593 Setting prompt string to ['Linux version [0-9]']
10419 14:50:22.543678 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10420 14:50:22.543783 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10421 14:50:22.624403
10422 14:50:22.627541 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10423 14:50:22.631397 start: 2.2.5.1 login-action (timeout 00:02:55) [common]
10424 14:50:22.631509 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10425 14:50:22.631583 Setting prompt string to []
10426 14:50:22.631661 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10427 14:50:22.631765 Using line separator: #'\n'#
10428 14:50:22.631825 No login prompt set.
10429 14:50:22.631888 Parsing kernel messages
10430 14:50:22.631943 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10431 14:50:22.632048 [login-action] Waiting for messages, (timeout 00:02:55)
10432 14:50:22.632114 Waiting using forced prompt support (timeout 00:01:28)
10433 14:50:22.650692 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10434 14:50:22.654199 [ 0.000000] random: crng init done
10435 14:50:22.660875 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10436 14:50:22.664077 [ 0.000000] efi: UEFI not found.
10437 14:50:22.670336 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10438 14:50:22.680915 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10439 14:50:22.690206 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10440 14:50:22.696942 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10441 14:50:22.703474 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10442 14:50:22.709989 [ 0.000000] printk: bootconsole [mtk8250] enabled
10443 14:50:22.716541 [ 0.000000] NUMA: No NUMA configuration found
10444 14:50:22.723189 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10445 14:50:22.729831 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10446 14:50:22.729928 [ 0.000000] Zone ranges:
10447 14:50:22.736236 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10448 14:50:22.739971 [ 0.000000] DMA32 empty
10449 14:50:22.746294 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10450 14:50:22.749717 [ 0.000000] Movable zone start for each node
10451 14:50:22.753350 [ 0.000000] Early memory node ranges
10452 14:50:22.759429 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10453 14:50:22.765934 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10454 14:50:22.772703 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10455 14:50:22.779342 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10456 14:50:22.785837 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10457 14:50:22.792463 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10458 14:50:22.848807 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10459 14:50:22.855952 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10460 14:50:22.862381 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10461 14:50:22.865874 [ 0.000000] psci: probing for conduit method from DT.
10462 14:50:22.872030 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10463 14:50:22.875630 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10464 14:50:22.882763 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10465 14:50:22.885432 [ 0.000000] psci: SMC Calling Convention v1.2
10466 14:50:22.892409 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10467 14:50:22.895223 [ 0.000000] Detected VIPT I-cache on CPU0
10468 14:50:22.902461 [ 0.000000] CPU features: detected: GIC system register CPU interface
10469 14:50:22.908492 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10470 14:50:22.915432 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10471 14:50:22.921846 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10472 14:50:22.928257 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10473 14:50:22.938404 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10474 14:50:22.941547 [ 0.000000] alternatives: applying boot alternatives
10475 14:50:22.948249 [ 0.000000] Fallback order for Node 0: 0
10476 14:50:22.954658 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10477 14:50:22.957938 [ 0.000000] Policy zone: Normal
10478 14:50:22.971031 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10479 14:50:22.981063 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10480 14:50:22.993623 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10481 14:50:23.003228 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10482 14:50:23.009952 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10483 14:50:23.013278 <6>[ 0.000000] software IO TLB: area num 8.
10484 14:50:23.070032 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10485 14:50:23.219309 <6>[ 0.000000] Memory: 7904636K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448132K reserved, 32768K cma-reserved)
10486 14:50:23.225891 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10487 14:50:23.231999 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10488 14:50:23.235295 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10489 14:50:23.242061 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10490 14:50:23.248388 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10491 14:50:23.251803 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10492 14:50:23.261620 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10493 14:50:23.268416 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10494 14:50:23.275087 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10495 14:50:23.281596 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10496 14:50:23.284760 <6>[ 0.000000] GICv3: 608 SPIs implemented
10497 14:50:23.288373 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10498 14:50:23.294691 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10499 14:50:23.297985 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10500 14:50:23.304699 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10501 14:50:23.318289 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10502 14:50:23.331276 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10503 14:50:23.337662 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10504 14:50:23.345269 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10505 14:50:23.358653 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10506 14:50:23.365139 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10507 14:50:23.372179 <6>[ 0.009225] Console: colour dummy device 80x25
10508 14:50:23.381972 <6>[ 0.013980] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10509 14:50:23.388871 <6>[ 0.024422] pid_max: default: 32768 minimum: 301
10510 14:50:23.391760 <6>[ 0.029293] LSM: Security Framework initializing
10511 14:50:23.398560 <6>[ 0.034229] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10512 14:50:23.408410 <6>[ 0.042041] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10513 14:50:23.415183 <6>[ 0.051461] cblist_init_generic: Setting adjustable number of callback queues.
10514 14:50:23.421539 <6>[ 0.058903] cblist_init_generic: Setting shift to 3 and lim to 1.
10515 14:50:23.431633 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10516 14:50:23.438757 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10517 14:50:23.441724 <6>[ 0.079148] rcu: Hierarchical SRCU implementation.
10518 14:50:23.448481 <6>[ 0.084194] rcu: Max phase no-delay instances is 1000.
10519 14:50:23.454785 <6>[ 0.091253] EFI services will not be available.
10520 14:50:23.458039 <6>[ 0.096207] smp: Bringing up secondary CPUs ...
10521 14:50:23.466624 <6>[ 0.101253] Detected VIPT I-cache on CPU1
10522 14:50:23.473194 <6>[ 0.101326] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10523 14:50:23.479585 <6>[ 0.101357] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10524 14:50:23.483309 <6>[ 0.101691] Detected VIPT I-cache on CPU2
10525 14:50:23.493000 <6>[ 0.101740] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10526 14:50:23.499234 <6>[ 0.101756] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10527 14:50:23.502528 <6>[ 0.102018] Detected VIPT I-cache on CPU3
10528 14:50:23.509126 <6>[ 0.102064] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10529 14:50:23.515880 <6>[ 0.102078] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10530 14:50:23.522091 <6>[ 0.102382] CPU features: detected: Spectre-v4
10531 14:50:23.526166 <6>[ 0.102389] CPU features: detected: Spectre-BHB
10532 14:50:23.528926 <6>[ 0.102394] Detected PIPT I-cache on CPU4
10533 14:50:23.535663 <6>[ 0.102451] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10534 14:50:23.545475 <6>[ 0.102467] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10535 14:50:23.548840 <6>[ 0.102759] Detected PIPT I-cache on CPU5
10536 14:50:23.555294 <6>[ 0.102821] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10537 14:50:23.561887 <6>[ 0.102837] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10538 14:50:23.565292 <6>[ 0.103118] Detected PIPT I-cache on CPU6
10539 14:50:23.575250 <6>[ 0.103183] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10540 14:50:23.581709 <6>[ 0.103199] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10541 14:50:23.584751 <6>[ 0.103496] Detected PIPT I-cache on CPU7
10542 14:50:23.591361 <6>[ 0.103560] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10543 14:50:23.597973 <6>[ 0.103576] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10544 14:50:23.601192 <6>[ 0.103623] smp: Brought up 1 node, 8 CPUs
10545 14:50:23.608010 <6>[ 0.244903] SMP: Total of 8 processors activated.
10546 14:50:23.614928 <6>[ 0.249855] CPU features: detected: 32-bit EL0 Support
10547 14:50:23.621484 <6>[ 0.255218] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10548 14:50:23.627622 <6>[ 0.264073] CPU features: detected: Common not Private translations
10549 14:50:23.634405 <6>[ 0.270589] CPU features: detected: CRC32 instructions
10550 14:50:23.640919 <6>[ 0.275941] CPU features: detected: RCpc load-acquire (LDAPR)
10551 14:50:23.644149 <6>[ 0.281901] CPU features: detected: LSE atomic instructions
10552 14:50:23.650864 <6>[ 0.287683] CPU features: detected: Privileged Access Never
10553 14:50:23.657629 <6>[ 0.293498] CPU features: detected: RAS Extension Support
10554 14:50:23.664080 <6>[ 0.299107] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10555 14:50:23.667458 <6>[ 0.306326] CPU: All CPU(s) started at EL2
10556 14:50:23.673986 <6>[ 0.310642] alternatives: applying system-wide alternatives
10557 14:50:23.684188 <6>[ 0.321530] devtmpfs: initialized
10558 14:50:23.700085 <6>[ 0.330490] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10559 14:50:23.706741 <6>[ 0.340449] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10560 14:50:23.712924 <6>[ 0.348356] pinctrl core: initialized pinctrl subsystem
10561 14:50:23.716355 <6>[ 0.355001] DMI not present or invalid.
10562 14:50:23.723080 <6>[ 0.359411] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10563 14:50:23.732892 <6>[ 0.366272] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10564 14:50:23.739470 <6>[ 0.373858] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10565 14:50:23.749772 <6>[ 0.382074] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10566 14:50:23.753020 <6>[ 0.390315] audit: initializing netlink subsys (disabled)
10567 14:50:23.762748 <5>[ 0.396008] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10568 14:50:23.769250 <6>[ 0.396708] thermal_sys: Registered thermal governor 'step_wise'
10569 14:50:23.775878 <6>[ 0.403971] thermal_sys: Registered thermal governor 'power_allocator'
10570 14:50:23.779680 <6>[ 0.410225] cpuidle: using governor menu
10571 14:50:23.785908 <6>[ 0.421181] NET: Registered PF_QIPCRTR protocol family
10572 14:50:23.792451 <6>[ 0.426657] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10573 14:50:23.795933 <6>[ 0.433761] ASID allocator initialised with 32768 entries
10574 14:50:23.803132 <6>[ 0.440336] Serial: AMBA PL011 UART driver
10575 14:50:23.811891 <4>[ 0.449093] Trying to register duplicate clock ID: 134
10576 14:50:23.871554 <6>[ 0.512204] KASLR enabled
10577 14:50:23.885966 <6>[ 0.519924] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10578 14:50:23.892341 <6>[ 0.526934] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10579 14:50:23.899365 <6>[ 0.533426] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10580 14:50:23.906013 <6>[ 0.540429] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10581 14:50:23.912530 <6>[ 0.546916] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10582 14:50:23.919203 <6>[ 0.553919] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10583 14:50:23.925380 <6>[ 0.560403] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10584 14:50:23.932037 <6>[ 0.567409] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10585 14:50:23.935359 <6>[ 0.574872] ACPI: Interpreter disabled.
10586 14:50:23.944026 <6>[ 0.581301] iommu: Default domain type: Translated
10587 14:50:23.950475 <6>[ 0.586448] iommu: DMA domain TLB invalidation policy: strict mode
10588 14:50:23.953812 <5>[ 0.593110] SCSI subsystem initialized
10589 14:50:23.960761 <6>[ 0.597359] usbcore: registered new interface driver usbfs
10590 14:50:23.967390 <6>[ 0.603091] usbcore: registered new interface driver hub
10591 14:50:23.971144 <6>[ 0.608639] usbcore: registered new device driver usb
10592 14:50:23.977618 <6>[ 0.614760] pps_core: LinuxPPS API ver. 1 registered
10593 14:50:23.987706 <6>[ 0.619951] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10594 14:50:23.990693 <6>[ 0.629294] PTP clock support registered
10595 14:50:23.993777 <6>[ 0.633535] EDAC MC: Ver: 3.0.0
10596 14:50:24.001193 <6>[ 0.638722] FPGA manager framework
10597 14:50:24.007902 <6>[ 0.642399] Advanced Linux Sound Architecture Driver Initialized.
10598 14:50:24.011174 <6>[ 0.649174] vgaarb: loaded
10599 14:50:24.018053 <6>[ 0.652326] clocksource: Switched to clocksource arch_sys_counter
10600 14:50:24.021229 <5>[ 0.658774] VFS: Disk quotas dquot_6.6.0
10601 14:50:24.027859 <6>[ 0.662958] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10602 14:50:24.030822 <6>[ 0.670149] pnp: PnP ACPI: disabled
10603 14:50:24.039705 <6>[ 0.676817] NET: Registered PF_INET protocol family
10604 14:50:24.049171 <6>[ 0.682404] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10605 14:50:24.060772 <6>[ 0.694739] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10606 14:50:24.070615 <6>[ 0.703547] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10607 14:50:24.077828 <6>[ 0.711516] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10608 14:50:24.083925 <6>[ 0.720214] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10609 14:50:24.096282 <6>[ 0.729963] TCP: Hash tables configured (established 65536 bind 65536)
10610 14:50:24.102541 <6>[ 0.736833] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10611 14:50:24.109279 <6>[ 0.744031] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10612 14:50:24.115972 <6>[ 0.751734] NET: Registered PF_UNIX/PF_LOCAL protocol family
10613 14:50:24.122416 <6>[ 0.757885] RPC: Registered named UNIX socket transport module.
10614 14:50:24.126001 <6>[ 0.764040] RPC: Registered udp transport module.
10615 14:50:24.132393 <6>[ 0.768976] RPC: Registered tcp transport module.
10616 14:50:24.139019 <6>[ 0.773907] RPC: Registered tcp NFSv4.1 backchannel transport module.
10617 14:50:24.142299 <6>[ 0.780569] PCI: CLS 0 bytes, default 64
10618 14:50:24.145531 <6>[ 0.784939] Unpacking initramfs...
10619 14:50:24.155462 <6>[ 0.788677] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10620 14:50:24.162169 <6>[ 0.797305] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10621 14:50:24.169085 <6>[ 0.806093] kvm [1]: IPA Size Limit: 40 bits
10622 14:50:24.172296 <6>[ 0.810620] kvm [1]: GICv3: no GICV resource entry
10623 14:50:24.178601 <6>[ 0.815642] kvm [1]: disabling GICv2 emulation
10624 14:50:24.185515 <6>[ 0.820330] kvm [1]: GIC system register CPU interface enabled
10625 14:50:24.188536 <6>[ 0.826484] kvm [1]: vgic interrupt IRQ18
10626 14:50:24.195876 <6>[ 0.832397] kvm [1]: VHE mode initialized successfully
10627 14:50:24.202371 <5>[ 0.838827] Initialise system trusted keyrings
10628 14:50:24.208624 <6>[ 0.843644] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10629 14:50:24.216315 <6>[ 0.853639] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10630 14:50:24.222912 <5>[ 0.860016] NFS: Registering the id_resolver key type
10631 14:50:24.226262 <5>[ 0.865313] Key type id_resolver registered
10632 14:50:24.233150 <5>[ 0.869729] Key type id_legacy registered
10633 14:50:24.239467 <6>[ 0.874008] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10634 14:50:24.246337 <6>[ 0.880928] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10635 14:50:24.252835 <6>[ 0.888640] 9p: Installing v9fs 9p2000 file system support
10636 14:50:24.289180 <5>[ 0.926377] Key type asymmetric registered
10637 14:50:24.292307 <5>[ 0.930708] Asymmetric key parser 'x509' registered
10638 14:50:24.302155 <6>[ 0.935841] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10639 14:50:24.305314 <6>[ 0.943455] io scheduler mq-deadline registered
10640 14:50:24.309186 <6>[ 0.948215] io scheduler kyber registered
10641 14:50:24.328235 <6>[ 0.965397] EINJ: ACPI disabled.
10642 14:50:24.361172 <4>[ 0.991750] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 14:50:24.371128 <4>[ 1.002372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 14:50:24.386261 <6>[ 1.023329] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10645 14:50:24.394551 <6>[ 1.031321] printk: console [ttyS0] disabled
10646 14:50:24.422049 <6>[ 1.055952] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10647 14:50:24.428567 <6>[ 1.065423] printk: console [ttyS0] enabled
10648 14:50:24.431932 <6>[ 1.065423] printk: console [ttyS0] enabled
10649 14:50:24.438661 <6>[ 1.074334] printk: bootconsole [mtk8250] disabled
10650 14:50:24.442031 <6>[ 1.074334] printk: bootconsole [mtk8250] disabled
10651 14:50:24.448520 <6>[ 1.085417] SuperH (H)SCI(F) driver initialized
10652 14:50:24.452001 <6>[ 1.090685] msm_serial: driver initialized
10653 14:50:24.465508 <6>[ 1.099620] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10654 14:50:24.475621 <6>[ 1.108171] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10655 14:50:24.482153 <6>[ 1.116715] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10656 14:50:24.492222 <6>[ 1.125344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10657 14:50:24.502353 <6>[ 1.134052] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10658 14:50:24.509000 <6>[ 1.142768] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10659 14:50:24.518930 <6>[ 1.151309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10660 14:50:24.525021 <6>[ 1.160109] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10661 14:50:24.534988 <6>[ 1.168651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10662 14:50:24.547646 <6>[ 1.184726] loop: module loaded
10663 14:50:24.554193 <6>[ 1.190799] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10664 14:50:24.577139 <4>[ 1.214276] mtk-pmic-keys: Failed to locate of_node [id: -1]
10665 14:50:24.583902 <6>[ 1.221151] megasas: 07.719.03.00-rc1
10666 14:50:24.593359 <6>[ 1.230816] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10667 14:50:24.602578 <6>[ 1.239731] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10668 14:50:24.619181 <6>[ 1.256244] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10669 14:50:24.674550 <6>[ 1.305583] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10670 14:50:26.835669 <6>[ 3.473381] Freeing initrd memory: 59548K
10671 14:50:26.847295 <6>[ 3.484974] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10672 14:50:26.858866 <6>[ 3.496141] tun: Universal TUN/TAP device driver, 1.6
10673 14:50:26.862047 <6>[ 3.502210] thunder_xcv, ver 1.0
10674 14:50:26.865259 <6>[ 3.505721] thunder_bgx, ver 1.0
10675 14:50:26.868485 <6>[ 3.509215] nicpf, ver 1.0
10676 14:50:26.878950 <6>[ 3.513242] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10677 14:50:26.882164 <6>[ 3.520718] hns3: Copyright (c) 2017 Huawei Corporation.
10678 14:50:26.889031 <6>[ 3.526310] hclge is initializing
10679 14:50:26.892493 <6>[ 3.529891] e1000: Intel(R) PRO/1000 Network Driver
10680 14:50:26.898907 <6>[ 3.535020] e1000: Copyright (c) 1999-2006 Intel Corporation.
10681 14:50:26.902110 <6>[ 3.541032] e1000e: Intel(R) PRO/1000 Network Driver
10682 14:50:26.909071 <6>[ 3.546248] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10683 14:50:26.915460 <6>[ 3.552433] igb: Intel(R) Gigabit Ethernet Network Driver
10684 14:50:26.922125 <6>[ 3.558083] igb: Copyright (c) 2007-2014 Intel Corporation.
10685 14:50:26.928853 <6>[ 3.563919] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10686 14:50:26.935341 <6>[ 3.570437] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10687 14:50:26.938440 <6>[ 3.576898] sky2: driver version 1.30
10688 14:50:26.945340 <6>[ 3.581830] usbcore: registered new device driver r8152-cfgselector
10689 14:50:26.951886 <6>[ 3.588365] usbcore: registered new interface driver r8152
10690 14:50:26.958180 <6>[ 3.594183] VFIO - User Level meta-driver version: 0.3
10691 14:50:26.965119 <6>[ 3.602416] usbcore: registered new interface driver usb-storage
10692 14:50:26.971516 <6>[ 3.608858] usbcore: registered new device driver onboard-usb-hub
10693 14:50:26.980829 <6>[ 3.618007] mt6397-rtc mt6359-rtc: registered as rtc0
10694 14:50:26.990337 <6>[ 3.623467] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:50:26 UTC (1717512626)
10695 14:50:26.993418 <6>[ 3.633030] i2c_dev: i2c /dev entries driver
10696 14:50:27.010695 <6>[ 3.644916] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10697 14:50:27.017093 <4>[ 3.653644] cpu cpu0: supply cpu not found, using dummy regulator
10698 14:50:27.023886 <4>[ 3.660086] cpu cpu1: supply cpu not found, using dummy regulator
10699 14:50:27.030584 <4>[ 3.666485] cpu cpu2: supply cpu not found, using dummy regulator
10700 14:50:27.037146 <4>[ 3.672888] cpu cpu3: supply cpu not found, using dummy regulator
10701 14:50:27.044317 <4>[ 3.679290] cpu cpu4: supply cpu not found, using dummy regulator
10702 14:50:27.050761 <4>[ 3.685686] cpu cpu5: supply cpu not found, using dummy regulator
10703 14:50:27.057142 <4>[ 3.692101] cpu cpu6: supply cpu not found, using dummy regulator
10704 14:50:27.063566 <4>[ 3.698497] cpu cpu7: supply cpu not found, using dummy regulator
10705 14:50:27.081567 <6>[ 3.719136] cpu cpu0: EM: created perf domain
10706 14:50:27.084892 <6>[ 3.724074] cpu cpu4: EM: created perf domain
10707 14:50:27.092436 <6>[ 3.729700] sdhci: Secure Digital Host Controller Interface driver
10708 14:50:27.098771 <6>[ 3.736132] sdhci: Copyright(c) Pierre Ossman
10709 14:50:27.105657 <6>[ 3.741086] Synopsys Designware Multimedia Card Interface Driver
10710 14:50:27.112080 <6>[ 3.747711] sdhci-pltfm: SDHCI platform and OF driver helper
10711 14:50:27.115531 <6>[ 3.747722] mmc0: CQHCI version 5.10
10712 14:50:27.122093 <6>[ 3.757929] ledtrig-cpu: registered to indicate activity on CPUs
10713 14:50:27.128319 <6>[ 3.765068] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10714 14:50:27.135366 <6>[ 3.772140] usbcore: registered new interface driver usbhid
10715 14:50:27.138515 <6>[ 3.777962] usbhid: USB HID core driver
10716 14:50:27.145380 <6>[ 3.782158] spi_master spi0: will run message pump with realtime priority
10717 14:50:27.188838 <6>[ 3.819854] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10718 14:50:27.207403 <6>[ 3.835135] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10719 14:50:27.211047 <6>[ 3.848774] mmc0: Command Queue Engine enabled
10720 14:50:27.217714 <6>[ 3.853584] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10721 14:50:27.224732 <6>[ 3.860863] mmcblk0: mmc0:0001 DA4128 116 GiB
10722 14:50:27.227820 <6>[ 3.865811] cros-ec-spi spi0.0: Chrome EC device registered
10723 14:50:27.234209 <6>[ 3.870139] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10724 14:50:27.241944 <6>[ 3.879352] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10725 14:50:27.248346 <6>[ 3.885203] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10726 14:50:27.255175 <6>[ 3.891437] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10727 14:50:27.272912 <6>[ 3.907004] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10728 14:50:27.279973 <6>[ 3.917656] NET: Registered PF_PACKET protocol family
10729 14:50:27.283449 <6>[ 3.923058] 9pnet: Installing 9P2000 support
10730 14:50:27.290136 <5>[ 3.927626] Key type dns_resolver registered
10731 14:50:27.293426 <6>[ 3.932652] registered taskstats version 1
10732 14:50:27.299866 <5>[ 3.937037] Loading compiled-in X.509 certificates
10733 14:50:27.331853 <4>[ 3.962962] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10734 14:50:27.341732 <4>[ 3.973804] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10735 14:50:27.357582 <6>[ 3.994720] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10736 14:50:27.364162 <6>[ 4.001630] xhci-mtk 11200000.usb: xHCI Host Controller
10737 14:50:27.370652 <6>[ 4.007138] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10738 14:50:27.380806 <6>[ 4.015095] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10739 14:50:27.387259 <6>[ 4.024561] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10740 14:50:27.394032 <6>[ 4.030724] xhci-mtk 11200000.usb: xHCI Host Controller
10741 14:50:27.400582 <6>[ 4.036217] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10742 14:50:27.407439 <6>[ 4.043875] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10743 14:50:27.414014 <6>[ 4.051699] hub 1-0:1.0: USB hub found
10744 14:50:27.417778 <6>[ 4.055727] hub 1-0:1.0: 1 port detected
10745 14:50:27.427555 <6>[ 4.060011] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10746 14:50:27.430708 <6>[ 4.068667] hub 2-0:1.0: USB hub found
10747 14:50:27.434231 <6>[ 4.072686] hub 2-0:1.0: 1 port detected
10748 14:50:27.441803 <6>[ 4.079669] mtk-msdc 11f70000.mmc: Got CD GPIO
10749 14:50:27.460520 <6>[ 4.094513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10750 14:50:27.467068 <6>[ 4.102549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10751 14:50:27.476836 <4>[ 4.110475] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10752 14:50:27.487130 <6>[ 4.120003] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10753 14:50:27.493383 <6>[ 4.128079] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10754 14:50:27.500069 <6>[ 4.136068] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10755 14:50:27.509980 <6>[ 4.143989] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10756 14:50:27.516332 <6>[ 4.151806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10757 14:50:27.526235 <6>[ 4.159623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10758 14:50:27.536448 <6>[ 4.169611] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10759 14:50:27.543205 <6>[ 4.177969] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10760 14:50:27.552660 <6>[ 4.186317] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10761 14:50:27.559441 <6>[ 4.194656] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10762 14:50:27.569391 <6>[ 4.202994] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10763 14:50:27.575972 <6>[ 4.211332] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10764 14:50:27.585977 <6>[ 4.219670] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10765 14:50:27.592899 <6>[ 4.228007] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10766 14:50:27.602515 <6>[ 4.236346] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10767 14:50:27.609352 <6>[ 4.244690] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10768 14:50:27.618927 <6>[ 4.253028] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10769 14:50:27.625586 <6>[ 4.261366] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10770 14:50:27.635412 <6>[ 4.269704] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10771 14:50:27.642399 <6>[ 4.278041] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10772 14:50:27.651967 <6>[ 4.286380] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10773 14:50:27.658654 <6>[ 4.295118] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10774 14:50:27.665407 <6>[ 4.302282] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10775 14:50:27.671904 <6>[ 4.309059] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10776 14:50:27.678351 <6>[ 4.315837] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10777 14:50:27.685403 <6>[ 4.322775] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10778 14:50:27.695348 <6>[ 4.329660] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10779 14:50:27.705142 <6>[ 4.338792] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10780 14:50:27.715276 <6>[ 4.347914] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10781 14:50:27.725579 <6>[ 4.357208] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10782 14:50:27.735314 <6>[ 4.366676] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10783 14:50:27.741882 <6>[ 4.376143] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10784 14:50:27.751490 <6>[ 4.385262] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10785 14:50:27.761629 <6>[ 4.394733] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10786 14:50:27.771539 <6>[ 4.403852] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10787 14:50:27.781501 <6>[ 4.413146] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10788 14:50:27.791003 <6>[ 4.423307] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10789 14:50:27.800914 <6>[ 4.434937] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10790 14:50:27.846076 <6>[ 4.480597] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10791 14:50:28.001305 <6>[ 4.638531] hub 1-1:1.0: USB hub found
10792 14:50:28.004499 <6>[ 4.643040] hub 1-1:1.0: 4 ports detected
10793 14:50:28.014205 <6>[ 4.651667] hub 1-1:1.0: USB hub found
10794 14:50:28.017406 <6>[ 4.656047] hub 1-1:1.0: 4 ports detected
10795 14:50:28.126422 <6>[ 4.760881] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10796 14:50:28.151974 <6>[ 4.789595] hub 2-1:1.0: USB hub found
10797 14:50:28.155522 <6>[ 4.794042] hub 2-1:1.0: 3 ports detected
10798 14:50:28.164138 <6>[ 4.801361] hub 2-1:1.0: USB hub found
10799 14:50:28.167172 <6>[ 4.805760] hub 2-1:1.0: 3 ports detected
10800 14:50:28.342243 <6>[ 4.976708] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10801 14:50:28.474107 <6>[ 5.111868] hub 1-1.4:1.0: USB hub found
10802 14:50:28.477317 <6>[ 5.116475] hub 1-1.4:1.0: 2 ports detected
10803 14:50:28.486446 <6>[ 5.123801] hub 1-1.4:1.0: USB hub found
10804 14:50:28.489419 <6>[ 5.128347] hub 1-1.4:1.0: 2 ports detected
10805 14:50:28.554302 <6>[ 5.188666] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10806 14:50:28.662799 <6>[ 5.297058] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10807 14:50:28.695030 <4>[ 5.329498] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10808 14:50:28.704751 <4>[ 5.338605] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10809 14:50:28.739913 <6>[ 5.377587] r8152 2-1.3:1.0 eth0: v1.12.13
10810 14:50:28.790427 <6>[ 5.424656] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10811 14:50:28.982078 <6>[ 5.616634] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10812 14:50:30.328516 <6>[ 6.966125] r8152 2-1.3:1.0 eth0: carrier on
10813 14:50:32.654149 <5>[ 6.996561] Sending DHCP requests .., OK
10814 14:50:32.660703 <6>[ 9.296877] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10815 14:50:32.664223 <6>[ 9.305216] IP-Config: Complete:
10816 14:50:32.677436 <6>[ 9.308725] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10817 14:50:32.684029 <6>[ 9.319450] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10818 14:50:32.694629 <6>[ 9.328073] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10819 14:50:32.697292 <6>[ 9.328084] nameserver0=192.168.201.1
10820 14:50:32.700744 <6>[ 9.340262] clk: Disabling unused clocks
10821 14:50:32.704453 <6>[ 9.345836] ALSA device list:
10822 14:50:32.710792 <6>[ 9.349119] No soundcards found.
10823 14:50:32.719000 <6>[ 9.356962] Freeing unused kernel memory: 8512K
10824 14:50:32.721844 <6>[ 9.361973] Run /init as init process
10825 14:50:32.752292 <6>[ 9.390687] NET: Registered PF_INET6 protocol family
10826 14:50:32.759347 <6>[ 9.397582] Segment Routing with IPv6
10827 14:50:32.762772 <6>[ 9.401570] In-situ OAM (IOAM) with IPv6
10828 14:50:32.803223 <30>[ 9.415200] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10829 14:50:32.810280 <30>[ 9.448508] systemd[1]: Detected architecture arm64.
10830 14:50:32.810362
10831 14:50:32.817113 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10832 14:50:32.817196
10833 14:50:32.830692 <30>[ 9.468697] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10834 14:50:32.955163 <30>[ 9.589946] systemd[1]: Queued start job for default target graphical.target.
10835 14:50:33.003798 <30>[ 9.638528] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10836 14:50:33.010252 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10837 14:50:33.030793 <30>[ 9.665924] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10838 14:50:33.037670 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10839 14:50:33.058345 <30>[ 9.693418] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10840 14:50:33.068449 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10841 14:50:33.087377 <30>[ 9.722322] systemd[1]: Created slice user.slice - User and Session Slice.
10842 14:50:33.094046 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10843 14:50:33.117503 <30>[ 9.749073] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10844 14:50:33.124340 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10845 14:50:33.145225 <30>[ 9.776797] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10846 14:50:33.152047 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10847 14:50:33.180389 <30>[ 9.805217] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10848 14:50:33.190020 <30>[ 9.825129] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10849 14:50:33.196496 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10850 14:50:33.213911 <30>[ 9.848677] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10851 14:50:33.220318 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10852 14:50:33.237893 <30>[ 9.872702] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10853 14:50:33.247516 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10854 14:50:33.262600 <30>[ 9.900744] systemd[1]: Reached target paths.target - Path Units.
10855 14:50:33.272289 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10856 14:50:33.289973 <30>[ 9.925102] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10857 14:50:33.297089 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10858 14:50:33.310714 <30>[ 9.948643] systemd[1]: Reached target slices.target - Slice Units.
10859 14:50:33.320326 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10860 14:50:33.334847 <30>[ 9.973061] systemd[1]: Reached target swap.target - Swaps.
10861 14:50:33.341596 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10862 14:50:33.362524 <30>[ 9.997165] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10863 14:50:33.372162 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10864 14:50:33.390467 <30>[ 10.025667] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10865 14:50:33.400812 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10866 14:50:33.419231 <30>[ 10.054266] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10867 14:50:33.429314 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10868 14:50:33.446373 <30>[ 10.081386] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10869 14:50:33.456287 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10870 14:50:33.474584 <30>[ 10.109462] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10871 14:50:33.481592 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10872 14:50:33.498628 <30>[ 10.133370] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10873 14:50:33.508519 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10874 14:50:33.526968 <30>[ 10.161907] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10875 14:50:33.536750 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10876 14:50:33.590040 <30>[ 10.224897] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10877 14:50:33.596448 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10878 14:50:33.617065 <30>[ 10.251870] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10879 14:50:33.623758 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10880 14:50:33.643889 <30>[ 10.278747] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10881 14:50:33.650426 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10882 14:50:33.676401 <30>[ 10.304833] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10883 14:50:33.722666 <30>[ 10.357528] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10884 14:50:33.732450 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10885 14:50:33.755466 <30>[ 10.390145] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10886 14:50:33.761941 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10887 14:50:33.810440 <30>[ 10.445386] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10888 14:50:33.820224 Startin<6>[ 10.454846] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10889 14:50:33.826934 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10890 14:50:33.851922 <30>[ 10.486937] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10891 14:50:33.858902 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10892 14:50:33.883968 <30>[ 10.518814] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10893 14:50:33.894069 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10894 14:50:33.915735 <30>[ 10.550680] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10895 14:50:33.922112 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10896 14:50:33.951440 <30>[ 10.586601] systemd[1]: Starting systemd-journald.service - Journal Service...
10897 14:50:33.958394 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10898 14:50:33.976505 <30>[ 10.611277] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10899 14:50:33.982921 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10900 14:50:34.008357 <30>[ 10.639706] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10901 14:50:34.014797 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10902 14:50:34.066419 <30>[ 10.701251] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10903 14:50:34.076409 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10904 14:50:34.098776 <30>[ 10.733670] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10905 14:50:34.105405 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10906 14:50:34.138557 <30>[ 10.773457] systemd[1]: Started systemd-journald.service - Journal Service.
10907 14:50:34.145182 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10908 14:50:34.166281 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10909 14:50:34.186270 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10910 14:50:34.202282 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10911 14:50:34.218454 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10912 14:50:34.239434 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10913 14:50:34.260375 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10914 14:50:34.280517 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10915 14:50:34.300687 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10916 14:50:34.321191 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10917 14:50:34.344124 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10918 14:50:34.367819 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10919 14:50:34.392786 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10920 14:50:34.398850 See 'systemctl status systemd-remount-fs.service' for details.
10921 14:50:34.408708 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10922 14:50:34.432872 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10923 14:50:34.469830 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10924 14:50:34.494997 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10925 14:50:34.516031 <46>[ 11.151124] systemd-journald[190]: Received client request to flush runtime journal.
10926 14:50:34.522375 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10927 14:50:34.550181 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10928 14:50:34.579200 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10929 14:50:34.603384 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10930 14:50:34.623035 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10931 14:50:34.647077 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10932 14:50:34.671127 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10933 14:50:34.690905 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10934 14:50:34.742432 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10935 14:50:34.776197 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10936 14:50:34.794255 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10937 14:50:34.813968 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10938 14:50:34.853955 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10939 14:50:34.874707 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10940 14:50:34.898503 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10941 14:50:34.948986 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10942 14:50:34.977880 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10943 14:50:34.996902 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10944 14:50:35.070964 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10945 14:50:35.091357 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10946 14:50:35.122320 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10947 14:50:35.225541 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10948 14:50:35.242164 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10949 14:50:35.257888 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10950 14:50:35.280756 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10951 14:50:35.298423 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10952 14:50:35.318375 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bu<6>[ 11.954377] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10953 14:50:35.321513 s System Message Bus Socket.
10954 14:50:35.334105 <3>[ 11.968982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10955 14:50:35.340287 <6>[ 11.969390] remoteproc remoteproc0: scp is available
10956 14:50:35.347335 <3>[ 11.978053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10957 14:50:35.353801 <6>[ 11.982749] remoteproc remoteproc0: powering up scp
10958 14:50:35.360326 <6>[ 11.983730] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10959 14:50:35.370057 <6>[ 11.983760] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10960 14:50:35.376668 <6>[ 11.983768] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10961 14:50:35.387130 <3>[ 11.992040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 14:50:35.393531 <6>[ 11.996074] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10963 14:50:35.403091 <3>[ 12.006858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 14:50:35.406449 <6>[ 12.012476] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10965 14:50:35.416483 <3>[ 12.021221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 14:50:35.419873 <6>[ 12.041321] mc: Linux media interface: v0.10
10967 14:50:35.429551 <4>[ 12.045294] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10968 14:50:35.436100 <4>[ 12.045394] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10969 14:50:35.442727 <3>[ 12.045484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 14:50:35.452981 <3>[ 12.045495] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10971 14:50:35.459950 <3>[ 12.045500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10972 14:50:35.469378 <3>[ 12.045560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10973 14:50:35.476256 <3>[ 12.045629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 14:50:35.482726 <3>[ 12.045633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 14:50:35.492458 <3>[ 12.045638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 14:50:35.498995 <3>[ 12.045728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10977 14:50:35.509256 <3>[ 12.045733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 14:50:35.515779 <3>[ 12.045737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 14:50:35.526080 <3>[ 12.045741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 14:50:35.532267 <3>[ 12.045745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 14:50:35.539333 <3>[ 12.045853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10982 14:50:35.549549 <6>[ 12.047183] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10983 14:50:35.556054 <4>[ 12.071135] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10984 14:50:35.562792 <4>[ 12.071135] Fallback method does not support PEC.
10985 14:50:35.572409 <6>[ 12.151553] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10986 14:50:35.579172 <6>[ 12.154700] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10987 14:50:35.589427 <6>[ 12.154737] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10988 14:50:35.592520 <6>[ 12.154746] remoteproc remoteproc0: remote processor scp is now up
10989 14:50:35.602613 <6>[ 12.165191] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10990 14:50:35.609162 <3>[ 12.184631] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 14:50:35.618957 <6>[ 12.188976] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10992 14:50:35.628993 <6>[ 12.192199] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10993 14:50:35.635902 <6>[ 12.192422] pci_bus 0000:00: root bus resource [bus 00-ff]
10994 14:50:35.642048 <6>[ 12.192430] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10995 14:50:35.652152 <6>[ 12.192436] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10996 14:50:35.659075 <6>[ 12.192473] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10997 14:50:35.665512 <6>[ 12.192493] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10998 14:50:35.668797 <6>[ 12.192573] pci 0000:00:00.0: supports D1 D2
10999 14:50:35.675264 <6>[ 12.192577] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11000 14:50:35.684959 <6>[ 12.194501] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11001 14:50:35.691846 <6>[ 12.194635] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11002 14:50:35.698566 <6>[ 12.194668] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11003 14:50:35.704811 <6>[ 12.194690] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11004 14:50:35.715050 <6>[ 12.194709] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11005 14:50:35.718206 <6>[ 12.194832] pci 0000:01:00.0: supports D1 D2
11006 14:50:35.724965 <6>[ 12.194836] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11007 14:50:35.731604 <6>[ 12.204436] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11008 14:50:35.741561 <6>[ 12.204490] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11009 14:50:35.747979 <6>[ 12.204498] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11010 14:50:35.754548 <6>[ 12.204511] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11011 14:50:35.764658 <6>[ 12.204528] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11012 14:50:35.771218 <6>[ 12.204545] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11013 14:50:35.777911 <6>[ 12.204562] pci 0000:00:00.0: PCI bridge to [bus 01]
11014 14:50:35.785123 <6>[ 12.204570] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11015 14:50:35.792010 <6>[ 12.204733] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11016 14:50:35.799116 <6>[ 12.206024] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11017 14:50:35.805962 <6>[ 12.218609] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11018 14:50:35.813261 <6>[ 12.223628] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11019 14:50:35.819364 <6>[ 12.232010] videodev: Linux video capture interface: v2.00
11020 14:50:35.826040 <6>[ 12.235870] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11021 14:50:35.829563 <6>[ 12.239029] Bluetooth: Core ver 2.22
11022 14:50:35.836959 <5>[ 12.266069] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11023 14:50:35.843530 <6>[ 12.272622] NET: Registered PF_BLUETOOTH protocol family
11024 14:50:35.850155 <5>[ 12.289783] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11025 14:50:35.856779 <6>[ 12.295320] Bluetooth: HCI device and connection manager initialized
11026 14:50:35.863206 <6>[ 12.295354] Bluetooth: HCI socket layer initialized
11027 14:50:35.870288 <5>[ 12.301871] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11028 14:50:35.876863 <6>[ 12.309070] Bluetooth: L2CAP socket layer initialized
11029 14:50:35.883269 <6>[ 12.309943] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11030 14:50:35.896422 <6>[ 12.311186] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11031 14:50:35.899770 <6>[ 12.311288] usbcore: registered new interface driver uvcvideo
11032 14:50:35.909691 <4>[ 12.315572] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11033 14:50:35.916392 <6>[ 12.320490] Bluetooth: SCO socket layer initialized
11034 14:50:35.919574 <6>[ 12.328734] cfg80211: failed to load regulatory.db
11035 14:50:35.926160 <6>[ 12.343159] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11036 14:50:35.933060 <6>[ 12.400313] usbcore: registered new interface driver btusb
11037 14:50:35.942782 <4>[ 12.401412] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11038 14:50:35.949172 <3>[ 12.401424] Bluetooth: hci0: Failed to load firmware file (-2)
11039 14:50:35.956080 <3>[ 12.401429] Bluetooth: hci0: Failed to set up firmware (-2)
11040 14:50:35.966847 <4>[ 12.401433] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11041 14:50:35.973226 <3>[ 12.431715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11042 14:50:35.983357 <6>[ 12.436562] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11043 14:50:35.989824 <3>[ 12.441651] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11044 14:50:35.996672 <6>[ 12.449782] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11045 14:50:36.006281 <3>[ 12.454507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11046 14:50:36.012849 <3>[ 12.455276] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11047 14:50:36.019494 <6>[ 12.470177] mt7921e 0000:01:00.0: ASIC revision: 79610010
11048 14:50:36.029351 <3>[ 12.479330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 14:50:36.035832 <6>[ 12.577105] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11050 14:50:36.039551 <6>[ 12.577105]
11051 14:50:36.049160 <3>[ 12.608541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11052 14:50:36.055767 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11053 14:50:36.077821 [[0;32m OK [0m] Reached targ<3>[ 12.711508] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11054 14:50:36.080666 et [0;1;39mbasic.target[0m - Basic System.
11055 14:50:36.109419 <3>[ 12.744914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 14:50:36.141901 <3>[ 12.776733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 14:50:36.148981 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11058 14:50:36.185158 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11059 14:50:36.210496 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11060 14:50:36.231117 <6>[ 12.866008] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11061 14:50:36.237692 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11062 14:50:36.266936 <46>[ 12.888722] systemd-journald[190]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11063 14:50:36.279831 <46>[ 12.909955] systemd-journald[190]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11064 14:50:36.289784 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11065 14:50:36.342859 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11066 14:50:36.366157 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11067 14:50:36.386467 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11068 14:50:36.406794 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11069 14:50:36.450583 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11070 14:50:36.471997 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11071 14:50:36.490903 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11072 14:50:36.506280 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11073 14:50:36.526293 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11074 14:50:36.579386 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11075 14:50:36.604711 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11076 14:50:36.629944 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11077 14:50:36.712736 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11078 14:50:36.731930 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11079 14:50:36.761082 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11080 14:50:36.798368
11081 14:50:36.801635 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11082 14:50:36.801717
11083 14:50:36.804947 debian-bookworm-arm64 login: root (automatic login)
11084 14:50:36.805026
11085 14:50:36.820205 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11086 14:50:36.820302
11087 14:50:36.826720 The programs included with the Debian GNU/Linux system are free software;
11088 14:50:36.833630 the exact distribution terms for each program are described in the
11089 14:50:36.836527 individual files in /usr/share/doc/*/copyright.
11090 14:50:36.836630
11091 14:50:36.843455 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11092 14:50:36.846678 permitted by applicable law.
11093 14:50:36.847118 Matched prompt #10: / #
11095 14:50:36.847453 Setting prompt string to ['/ #']
11096 14:50:36.847609 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11098 14:50:36.847861 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11099 14:50:36.847959 start: 2.2.6 expect-shell-connection (timeout 00:02:41) [common]
11100 14:50:36.848039 Setting prompt string to ['/ #']
11101 14:50:36.848149 Forcing a shell prompt, looking for ['/ #']
11103 14:50:36.898427 / #
11104 14:50:36.898568 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11105 14:50:36.898657 Waiting using forced prompt support (timeout 00:02:30)
11106 14:50:36.903679
11107 14:50:36.904013 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11108 14:50:36.904164 start: 2.2.7 export-device-env (timeout 00:02:41) [common]
11109 14:50:36.904319 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11110 14:50:36.904467 end: 2.2 depthcharge-retry (duration 00:02:19) [common]
11111 14:50:36.904616 end: 2 depthcharge-action (duration 00:02:19) [common]
11112 14:50:36.904762 start: 3 lava-test-retry (timeout 00:07:14) [common]
11113 14:50:36.904905 start: 3.1 lava-test-shell (timeout 00:07:14) [common]
11114 14:50:36.905035 Using namespace: common
11116 14:50:37.005446 / # #
11117 14:50:37.005616 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11118 14:50:37.010166 #
11119 14:50:37.010502 Using /lava-14167057
11121 14:50:37.110970 / # export SHELL=/bin/sh
11122 14:50:37.111170 export SHELL=/bin/sh<6>[ 13.732820] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11123 14:50:37.116047
11125 14:50:37.216551 / # . /lava-14167057/environment
11126 14:50:37.222223 . /lava-14167057/environment
11128 14:50:37.322865 / # /lava-14167057/bin/lava-test-runner /lava-14167057/0
11129 14:50:37.323102 Test shell timeout: 10s (minimum of the action and connection timeout)
11130 14:50:37.327744 /lava-14167057/bin/lava-test-runner /lava-14167057/0
11131 14:50:37.353569 + export TESTRUN_ID=0_igt-kms-me<8>[ 13.991136] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14167057_1.5.2.3.1>
11132 14:50:37.353880 Received signal: <STARTRUN> 0_igt-kms-mediatek 14167057_1.5.2.3.1
11133 14:50:37.353959 Starting test lava.0_igt-kms-mediatek (14167057_1.5.2.3.1)
11134 14:50:37.354044 Skipping test definition patterns.
11135 14:50:37.356785 diatek
11136 14:50:37.360139 + cd /lava-14167057/0/tests/0_igt-kms-mediatek
11137 14:50:37.360222 + cat uuid
11138 14:50:37.363332 + UUID=14167057_1.5.2.3.1
11139 14:50:37.363415 + set +x
11140 14:50:37.376432 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 14.016041] <LAVA_SIGNAL_TESTSET START core_auth>
11141 14:50:37.376777 Received signal: <TESTSET> START core_auth
11142 14:50:37.376870 Starting test_set core_auth
11143 14:50:37.389446 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11144 14:50:37.410619 <14>[ 14.049330] [IGT] core_auth: executing
11145 14:50:37.417078 IGT-Version: 1.2<14>[ 14.053778] [IGT] core_auth: starting subtest getclient-simple
11146 14:50:37.427271 8-ga44ebfe (aarc<14>[ 14.061551] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11147 14:50:37.430384 h64) (Linux: 6.1<14>[ 14.069548] [IGT] core_auth: exiting, ret=0
11148 14:50:37.433589 .91-cip21 aarch64)
11149 14:50:37.436965 Using IGT_SRANDOM=1717512637 for randomisation
11150 14:50:37.447261 Starting sub<8>[ 14.082240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11151 14:50:37.447398 test: getclient-simple
11152 14:50:37.447664 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11154 14:50:37.450408 Opened device: /dev/dri/card0
11155 14:50:37.456675 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11156 14:50:37.464932 <14>[ 14.103351] [IGT] core_auth: executing
11157 14:50:37.471221 IGT-Version: 1.2<14>[ 14.107709] [IGT] core_auth: starting subtest getclient-master-drop
11158 14:50:37.481201 8-ga44ebfe (aarc<14>[ 14.115745] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11159 14:50:37.484497 <14>[ 14.124470] [IGT] core_auth: exiting, ret=0
11160 14:50:37.487801 h64) (Linux: 6.1.91-cip21 aarch64)
11161 14:50:37.497495 Using IGT_SRANDOM=1717512637<8>[ 14.134500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11162 14:50:37.497824 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11164 14:50:37.501078 for randomisation
11165 14:50:37.504405 Starting subtest: getclient-master-drop
11166 14:50:37.507427 Opened device: /dev/dri/card0
11167 14:50:37.510749 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11168 14:50:37.517621 <14>[ 14.156155] [IGT] core_auth: executing
11169 14:50:37.524070 IGT-Version: 1.2<14>[ 14.160741] [IGT] core_auth: starting subtest basic-auth
11170 14:50:37.530667 8-ga44ebfe (aarc<14>[ 14.167747] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11171 14:50:37.538133 h64) (Linux: 6.1<14>[ 14.175439] [IGT] core_auth: exiting, ret=0
11172 14:50:37.540860 .91-cip21 aarch64)
11173 14:50:37.544267 Using IGT_SRANDOM=1717512637 for randomisation
11174 14:50:37.550710 Opened devic<8>[ 14.187971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11175 14:50:37.550999 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11177 14:50:37.553828 e: /dev/dri/card0
11178 14:50:37.557497 Starting subtest: basic-auth
11179 14:50:37.560434 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11180 14:50:37.570092 <14>[ 14.208985] [IGT] core_auth: executing
11181 14:50:37.576941 IGT-Version: 1.2<14>[ 14.213395] [IGT] core_auth: starting subtest many-magics
11182 14:50:37.579995 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11183 14:50:37.590265 Using IGT_SRANDOM=1717512637<14>[ 14.227026] [IGT] core_auth: finished subtest many-magics, SUCCESS
11184 14:50:37.596736 for randomisati<14>[ 14.234067] [IGT] core_auth: exiting, ret=0
11185 14:50:37.596896 on
11186 14:50:37.600074 Opened device: /dev/dri/card0
11187 14:50:37.610149 Starting subtest: many-magics<8>[ 14.245404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11188 14:50:37.610326
11189 14:50:37.610639 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11191 14:50:37.616515 Reopening device failed after <8>[ 14.254006] <LAVA_SIGNAL_TESTSET STOP>
11192 14:50:37.616648 1020 opens
11193 14:50:37.616922 Received signal: <TESTSET> STOP
11194 14:50:37.617021 Closing test_set core_auth
11195 14:50:37.619669 [1mSubtest many-magics: SUCCESS (0.006s)[0m
11196 14:50:37.665982 <14>[ 14.304781] [IGT] core_getclient: executing
11197 14:50:37.672534 IGT-Version: 1.2<14>[ 14.309965] [IGT] core_getclient: exiting, ret=0
11198 14:50:37.675966 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11199 14:50:37.689312 Using IGT_SRANDOM=1717512637 for randomisati<8>[ 14.323806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11200 14:50:37.689502 on
11201 14:50:37.689576 Opened device: /dev/dri/card0
11202 14:50:37.689814 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11204 14:50:37.692093 SUCCESS (0.006s)
11205 14:50:37.741420 <14>[ 14.379756] [IGT] core_getstats: executing
11206 14:50:37.748000 IGT-Version: 1.2<14>[ 14.384973] [IGT] core_getstats: exiting, ret=0
11207 14:50:37.751081 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11208 14:50:37.761083 Using IGT_SRANDOM=1717512637 for randomisati<8>[ 14.398980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11209 14:50:37.761411 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11211 14:50:37.764530 on
11212 14:50:37.764673 Opened device: /dev/dri/card0
11213 14:50:37.767722 SUCCESS (0.006s)
11214 14:50:37.807337 <14>[ 14.446227] [IGT] core_getversion: executing
11215 14:50:37.813808 IGT-Version: 1.2<14>[ 14.451501] [IGT] core_getversion: exiting, ret=0
11216 14:50:37.817131 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11217 14:50:37.823862 Using IGT_SRANDOM=1717512637 for randomisation
11218 14:50:37.830370 Opened device: /dev/dri/card<8>[ 14.467769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11219 14:50:37.830663 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11221 14:50:37.833735 0
11222 14:50:37.833816 SUCCESS (0.006s)
11223 14:50:37.885513 <14>[ 14.524190] [IGT] core_setmaster_vs_auth: executing
11224 14:50:37.891884 IGT-Version: 1.2<14>[ 14.530116] [IGT] core_setmaster_vs_auth: exiting, ret=0
11225 14:50:37.898724 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11226 14:50:37.901919 Using IGT_SRANDOM=1717512637 for randomisation
11227 14:50:37.911559 Opened devic<8>[ 14.545178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11228 14:50:37.911705 e: /dev/dri/card0
11229 14:50:37.911977 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11231 14:50:37.914902 SUCCESS (0.007s)
11232 14:50:37.942586 <8>[ 14.581247] <LAVA_SIGNAL_TESTSET START drm_read>
11233 14:50:37.942907 Received signal: <TESTSET> START drm_read
11234 14:50:37.942983 Starting test_set drm_read
11235 14:50:37.969444 <14>[ 14.608286] [IGT] drm_read: executing
11236 14:50:37.976418 IGT-Version: 1.2<14>[ 14.613110] [IGT] drm_read: exiting, ret=77
11237 14:50:37.979694 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11238 14:50:37.986177 Using IGT_SR<8>[ 14.623670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11239 14:50:37.986464 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11241 14:50:37.989517 ANDOM=1717512637 for randomisation
11242 14:50:37.992691 Opened device: /dev/dri/card0
11243 14:50:37.999498 No KMS driver or no outputs, pipes: 16, outputs: 0
11244 14:50:38.002662 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11245 14:50:38.005725 <14>[ 14.645048] [IGT] drm_read: executing
11246 14:50:38.012815 IGT-Version: 1.2<14>[ 14.650025] [IGT] drm_read: exiting, ret=77
11247 14:50:38.015970 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11248 14:50:38.025614 Using IGT_SRANDOM=1717512637<8>[ 14.662046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11249 14:50:38.025910 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11251 14:50:38.029084 for randomisation
11252 14:50:38.029163 Opened device: /dev/dri/card0
11253 14:50:38.035665 No KMS driver or no outputs, pipes: 16, outputs: 0
11254 14:50:38.038688 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11255 14:50:38.047592 <14>[ 14.685773] [IGT] drm_read: executing
11256 14:50:38.053624 IGT-Version: 1.2<14>[ 14.690237] [IGT] drm_read: exiting, ret=77
11257 14:50:38.057434 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11258 14:50:38.066859 Using IGT_SRANDOM=1717512638<8>[ 14.702169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11259 14:50:38.066990 for randomisation
11260 14:50:38.067234 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11262 14:50:38.070241 Opened device: /dev/dri/card0
11263 14:50:38.073447 No KMS driver or no outputs, pipes: 16, outputs: 0
11264 14:50:38.079920 [1mSubtest empty-block: SKIP (0.000s)[0m
11265 14:50:38.093479 <14>[ 14.732381] [IGT] drm_read: executing
11266 14:50:38.100092 IGT-Version: 1.2<14>[ 14.737059] [IGT] drm_read: exiting, ret=77
11267 14:50:38.103757 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11268 14:50:38.106827 Using IGT_SRANDOM=1717512638 for randomisation
11269 14:50:38.116654 Opened devic<8>[ 14.750875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11270 14:50:38.116803 e: /dev/dri/card0
11271 14:50:38.117076 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11273 14:50:38.123310 No KMS driver or no outputs, pipes: 16, outputs: 0
11274 14:50:38.126569 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11275 14:50:38.136003 <14>[ 14.774304] [IGT] drm_read: executing
11276 14:50:38.142038 IGT-Version: 1.2<14>[ 14.778793] [IGT] drm_read: exiting, ret=77
11277 14:50:38.145191 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11278 14:50:38.155415 Using IGT_SRANDOM=1717512638<8>[ 14.791083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11279 14:50:38.155551 for randomisation
11280 14:50:38.155796 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11282 14:50:38.158707 Opened device: /dev/dri/card0
11283 14:50:38.165144 No KMS driver or no outputs, pipes: 16, outputs: 0
11284 14:50:38.168435 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11285 14:50:38.183054 <14>[ 14.821739] [IGT] drm_read: executing
11286 14:50:38.189529 IGT-Version: 1.2<14>[ 14.826581] [IGT] drm_read: exiting, ret=77
11287 14:50:38.192741 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11288 14:50:38.202609 Using IGT_SRANDOM=1717512638<8>[ 14.837696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11289 14:50:38.202912 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11291 14:50:38.206146 for randomisation
11292 14:50:38.206239 Opened device: /dev/dri/card0
11293 14:50:38.212882 No KMS driver or no outputs, pipes: 16, outputs: 0
11294 14:50:38.216031 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11295 14:50:38.230700 <14>[ 14.869688] [IGT] drm_read: executing
11296 14:50:38.237872 IGT-Version: 1.2<14>[ 14.874515] [IGT] drm_read: exiting, ret=77
11297 14:50:38.240997 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11298 14:50:38.250594 Using IGT_SRANDOM=1717512638<8>[ 14.886100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11299 14:50:38.250972 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11301 14:50:38.254184 for randomisation
11302 14:50:38.257418 Opened devic<8>[ 14.895945] <LAVA_SIGNAL_TESTSET STOP>
11303 14:50:38.257731 Received signal: <TESTSET> STOP
11304 14:50:38.257851 Closing test_set drm_read
11305 14:50:38.260579 e: /dev/dri/card0
11306 14:50:38.264247 No KMS driver or no outputs, pipes: 16, outputs: 0
11307 14:50:38.267332 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11308 14:50:38.289759 <8>[ 14.928837] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11309 14:50:38.290082 Received signal: <TESTSET> START kms_addfb_basic
11310 14:50:38.290162 Starting test_set kms_addfb_basic
11311 14:50:38.316709 <14>[ 14.955684] [IGT] kms_addfb_basic: executing
11312 14:50:38.330066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch6<14>[ 14.965457] [IGT] kms_addfb_basic: starting subtest unused-handle
11313 14:50:38.330209 4)
11314 14:50:38.336676 Using IGT_SR<14>[ 14.972850] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11315 14:50:38.339830 ANDOM=1717512638 for randomisation
11316 14:50:38.343560 Opened device: /dev/dri/card0
11317 14:50:38.346734 Starting subtest: unused-handle
11318 14:50:38.353452 [1mSubtest <14>[ 14.990259] [IGT] kms_addfb_basic: exiting, ret=0
11319 14:50:38.356828 unused-handle: SUCCESS (0.000s)[0m
11320 14:50:38.366695 Test requirement not met in function igt_re<8>[ 15.003070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11321 14:50:38.367009 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11323 14:50:38.369925 quire_intel, file ../lib/drmtest.c:880:
11324 14:50:38.373186 Test requirement: is_intel_device(fd)
11325 14:50:38.379859 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11326 14:50:38.383093 Test requirement: is_intel_device(fd)
11327 14:50:38.389892 No KMS driver or no outputs, pipes: 16, outputs: 0
11328 14:50:38.392796 <14>[ 15.032603] [IGT] kms_addfb_basic: executing
11329 14:50:38.406133 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch6<14>[ 15.042257] [IGT] kms_addfb_basic: starting subtest unused-pitches
11330 14:50:38.406308 4)
11331 14:50:38.416247 Using IGT_SR<14>[ 15.049816] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11332 14:50:38.416409 ANDOM=1717512638 for randomisation
11333 14:50:38.419562 Opened device: /dev/dri/card0
11334 14:50:38.422549 Starting subtest: unused-pitches
11335 14:50:38.429382 [1mSubtest<14>[ 15.067308] [IGT] kms_addfb_basic: exiting, ret=0
11336 14:50:38.432834 unused-pitches: SUCCESS (0.000s)[0m
11337 14:50:38.442633 Test requirement not met in function igt_<8>[ 15.080180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11338 14:50:38.442966 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11340 14:50:38.446002 require_intel, file ../lib/drmtest.c:880:
11341 14:50:38.449207 Test requirement: is_intel_device(fd)
11342 14:50:38.462370 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 15.101116] [IGT] kms_addfb_basic: executing
11343 14:50:38.462504 880:
11344 14:50:38.465634 Test requirement: is_intel_device(fd)
11345 14:50:38.475659 No KMS driver or no<14>[ 15.110351] [IGT] kms_addfb_basic: starting subtest unused-offsets
11346 14:50:38.482069 outputs, pipes:<14>[ 15.118349] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11347 14:50:38.485388 16, outputs: 0
11348 14:50:38.492260 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11349 14:50:38.495255 Using IGT_S<14>[ 15.134755] [IGT] kms_addfb_basic: exiting, ret=0
11350 14:50:38.498917 RANDOM=1717512638 for randomisation
11351 14:50:38.502168 Opened device: /dev/dri/card0
11352 14:50:38.512001 Starting sub<8>[ 15.147205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11353 14:50:38.512129 test: unused-offsets
11354 14:50:38.512375 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11356 14:50:38.518264 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11357 14:50:38.524744 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11358 14:50:38.528289 Test requirement: is_intel_device(fd)
11359 14:50:38.538420 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 15.177346] [IGT] kms_addfb_basic: executing
11360 14:50:38.538545 :880:
11361 14:50:38.541362 Test requirement: is_intel_device(fd)
11362 14:50:38.551180 No KMS driver or n<14>[ 15.187750] [IGT] kms_addfb_basic: starting subtest unused-modifier
11363 14:50:38.561368 o outputs, pipes<14>[ 15.195067] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11364 14:50:38.561515 : 16, outputs: 0
11365 14:50:38.567698 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11366 14:50:38.574256 Using IGT_SRANDOM=17175126<14>[ 15.212710] [IGT] kms_addfb_basic: exiting, ret=0
11367 14:50:38.577502 38 for randomisation
11368 14:50:38.580705 Opened device: /dev/dri/card0
11369 14:50:38.580804 Starting subtest: unused-modifier
11370 14:50:38.590774 [1mSubt<8>[ 15.225619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11371 14:50:38.591084 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11373 14:50:38.593959 est unused-modifier: SUCCESS (0.000s)[0m
11374 14:50:38.600945 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11375 14:50:38.603958 Test requirement: is_intel_device(fd)
11376 14:50:38.610603 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11377 14:50:38.617543 Test requirement: is_i<14>[ 15.256636] [IGT] kms_addfb_basic: executing
11378 14:50:38.620706 ntel_device(fd)
11379 14:50:38.630322 No KMS driver or no outputs, pipes: 16, outputs<14>[ 15.267622] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11380 14:50:38.630462 : 0
11381 14:50:38.640038 IGT-Version<14>[ 15.275142] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11382 14:50:38.643592 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11383 14:50:38.650245 Using IGT_SRANDOM=1717512638 for randomisation
11384 14:50:38.653539 Opened <14>[ 15.292793] [IGT] kms_addfb_basic: exiting, ret=77
11385 14:50:38.656708 device: /dev/dri/card0
11386 14:50:38.660009 Starting subtest: clobberred-modifier
11387 14:50:38.670050 Test requirement not met in funct<8>[ 15.305979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11388 14:50:38.670391 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11390 14:50:38.676608 ion igt_require_i915, file ../lib/drmtest.c:885:
11391 14:50:38.680060 Test requirement: is_i915_device(fd)
11392 14:50:38.682942 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11393 14:50:38.689465 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11394 14:50:38.693444 Test requirement: is_intel_device(fd)
11395 14:50:38.699590 Test requ<14>[ 15.337555] [IGT] kms_addfb_basic: executing
11396 14:50:38.712565 irement not met in function igt_require_intel, file ../lib/drmte<14>[ 15.348137] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11397 14:50:38.712730 st.c:880:
11398 14:50:38.722869 Test <14>[ 15.356526] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11399 14:50:38.726178 requirement: is_intel_device(fd)
11400 14:50:38.729153 No KMS driver or no outputs, pipes: 16, outputs: 0
11401 14:50:38.736049 IGT-Version: 1.28-ga44ebfe<14>[ 15.374888] [IGT] kms_addfb_basic: exiting, ret=77
11402 14:50:38.739242 (aarch64) (Linux: 6.1.91-cip21 aarch64)
11403 14:50:38.752540 Using IGT_SRANDOM=1717512638 for rando<8>[ 15.386810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11404 14:50:38.752737 misation
11405 14:50:38.752999 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11407 14:50:38.755696 Opened device: /dev/dri/card0
11408 14:50:38.759164 Starting subtest: invalid-smem-bo-on-discrete
11409 14:50:38.766077 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11410 14:50:38.772244 Test requirement: is_intel_device(fd)
11411 14:50:38.775543 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11412 14:50:38.781812 T<14>[ 15.419061] [IGT] kms_addfb_basic: executing
11413 14:50:38.791991 est requirement not met in function igt_require_intel, file ../l<14>[ 15.429398] [IGT] kms_addfb_basic: starting subtest legacy-format
11414 14:50:38.795461 ib/drmtest.c:880:
11415 14:50:38.798764 Test requirement: is_intel_device(fd)
11416 14:50:38.811814 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 15.446961] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11417 14:50:38.811987 mtest.c:880:
11418 14:50:38.815212 Test requirement: is_intel_device(fd)
11419 14:50:38.818702 No KMS driver or no outputs, pipes: 16, outputs: 0
11420 14:50:38.825257 IGT-Ver<14>[ 15.463326] [IGT] kms_addfb_basic: exiting, ret=0
11421 14:50:38.832010 sion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11422 14:50:38.838502 Using IGT_SRANDOM=1<8>[ 15.476487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11423 14:50:38.838791 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11425 14:50:38.841681 717512638 for randomisation
11426 14:50:38.844863 Opened device: /dev/dri/card0
11427 14:50:38.848031 Starting subtest: legacy-format
11428 14:50:38.851459 Successfully fuzzed 10000 {bpp, depth} variations
11429 14:50:38.858271 [1mSubtest lega<14>[ 15.496789] [IGT] kms_addfb_basic: executing
11430 14:50:38.861677 cy-format: SUCCESS (0.010s)[0m
11431 14:50:38.871406 Test requirement not met in function igt_requir<14>[ 15.508952] [IGT] kms_addfb_basic: starting subtest no-handle
11432 14:50:38.881100 e_intel, file ..<14>[ 15.515424] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11433 14:50:38.881233 /lib/drmtest.c:880:
11434 14:50:38.884376 Test requirement: is_intel_device(fd)
11435 14:50:38.891600 Test requirement not<14>[ 15.529607] [IGT] kms_addfb_basic: exiting, ret=0
11436 14:50:38.897774 met in function igt_require_intel, file ../lib/drmtest.c:880:
11437 14:50:38.904135 Test requirement<8>[ 15.542478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11438 14:50:38.904444 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11440 14:50:38.907409 : is_intel_device(fd)
11441 14:50:38.910811 No KMS driver or no outputs, pipes: 16, outputs: 0
11442 14:50:38.917381 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11443 14:50:38.920773 Using IGT_SRANDOM=1717512638 for randomisation
11444 14:50:38.924451 Opened device: /dev/dri/card0
11445 14:50:38.927378 Starting subtest: no-handle
11446 14:50:38.933705 [1mSubtest no-handle<14>[ 15.571832] [IGT] kms_addfb_basic: executing
11447 14:50:38.937119 : SUCCESS (0.000s)[0m
11448 14:50:38.946937 Test requirement not met in function igt_require_intel, file ../lib/drmt<14>[ 15.585033] [IGT] kms_addfb_basic: starting subtest basic
11449 14:50:38.950693 est.c:880:
11450 14:50:38.957280 Test<14>[ 15.591949] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11451 14:50:38.960285 requirement: is_intel_device(fd)
11452 14:50:38.967251 Test requirement not met in function igt_requ<14>[ 15.606403] [IGT] kms_addfb_basic: exiting, ret=0
11453 14:50:38.970413 ire_intel, file ../lib/drmtest.c:880:
11454 14:50:38.973618 Test requirement: is_intel_device(fd)
11455 14:50:38.980179 No<8>[ 15.618547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11456 14:50:38.980513 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11458 14:50:38.986747 KMS driver or no outputs, pipes: 16, outputs: 0
11459 14:50:38.990851 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11460 14:50:38.996974 Using IGT_SRANDOM=1717512638 for randomisation
11461 14:50:39.000098 Opened dev<14>[ 15.639699] [IGT] kms_addfb_basic: executing
11462 14:50:39.003650 ice: /dev/dri/card0
11463 14:50:39.006804 Starting subtest: basic
11464 14:50:39.013543 [1mSubtest basic: SUCCESS (0.000s<14>[ 15.651645] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11465 14:50:39.016671 )[0m
11466 14:50:39.023022 Test requ<14>[ 15.658523] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11467 14:50:39.029712 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11468 14:50:39.036416 Test <14>[ 15.672817] [IGT] kms_addfb_basic: exiting, ret=0
11469 14:50:39.039482 requirement: is_intel_device(fd)
11470 14:50:39.049648 Test requirement not met in function igt_require_intel, file .<8>[ 15.686131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11471 14:50:39.049965 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11473 14:50:39.053311 ./lib/drmtest.c:880:
11474 14:50:39.056324 Test requirement: is_intel_device(fd)
11475 14:50:39.059516 No KMS driver or no outputs, pipes: 16, outputs: 0
11476 14:50:39.065902 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11477 14:50:39.069152 Using IGT_SRANDOM=1717512638 for randomisation
11478 14:50:39.072939 Opened device: /dev/dri/card0
11479 14:50:39.075761 Starting subtest: bad-pitch-0
11480 14:50:39.082393 [1mSubtest b<14>[ 15.719386] [IGT] kms_addfb_basic: executing
11481 14:50:39.085996 ad-pitch-0: SUCCESS (0.000s)[0m
11482 14:50:39.096291 Test requirement not met in function igt_require_intel, file .<14>[ 15.732705] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11483 14:50:39.105843 ./lib/drmtest.c:<14>[ 15.740158] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11484 14:50:39.105978 880:
11485 14:50:39.109363 Test requirement: is_intel_device(fd)
11486 14:50:39.115753 Test requirement not met in functio<14>[ 15.755070] [IGT] kms_addfb_basic: exiting, ret=0
11487 14:50:39.122093 n igt_require_intel, file ../lib/drmtest.c:880:
11488 14:50:39.128788 Test requiremen<8>[ 15.765680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11489 14:50:39.129114 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11491 14:50:39.132101 t: is_intel_device(fd)
11492 14:50:39.135515 No KMS driver or no outputs, pipes: 16, outputs: 0
11493 14:50:39.142050 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11494 14:50:39.145550 Using IGT_SRANDOM=1717512639 for randomisation
11495 14:50:39.152081 <14>[ 15.789881] [IGT] kms_addfb_basic: executing
11496 14:50:39.152190 Opened device: /dev/dri/card0
11497 14:50:39.155383 Starting subtest: bad-pitch-32
11498 14:50:39.165138 [1mSubtest bad-p<14>[ 15.801273] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11499 14:50:39.172059 itch-32: SUCCESS<14>[ 15.808095] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11500 14:50:39.175267 (0.000s)[0m
11501 14:50:39.185063 Test requirement not met in function igt_require_intel, file ../l<14>[ 15.822544] [IGT] kms_addfb_basic: exiting, ret=0
11502 14:50:39.185206 ib/drmtest.c:880:
11503 14:50:39.188303 Test requirement: is_intel_device(fd)
11504 14:50:39.199018 Test requirement not m<8>[ 15.835351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11505 14:50:39.199325 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11507 14:50:39.205166 et in function igt_require_intel, file ../lib/drmtest.c:880:
11508 14:50:39.208276 Test requirement: is_intel_device(fd)
11509 14:50:39.211951 No KMS driver or no outputs, pipes: 16, outputs: 0
11510 14:50:39.218246 IGT-Version: 1.28-ga44e<14>[ 15.857708] [IGT] kms_addfb_basic: executing
11511 14:50:39.221374 bfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11512 14:50:39.231217 Using IGT_SRANDOM=1717512639 for ra<14>[ 15.869095] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11513 14:50:39.234781 ndomisation
11514 14:50:39.241465 Ope<14>[ 15.876068] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11515 14:50:39.244778 ned device: /dev/dri/card0
11516 14:50:39.244907 Starting subtest: bad-pitch-63
11517 14:50:39.251177 [1mSubtest bad-pitc<14>[ 15.890581] [IGT] kms_addfb_basic: exiting, ret=0
11518 14:50:39.254589 h-63: SUCCESS (0.000s)[0m
11519 14:50:39.267892 Test requirement not met in function igt_require_int<8>[ 15.902869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11520 14:50:39.268248 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11522 14:50:39.271247 el, file ../lib/drmtest.c:880:
11523 14:50:39.274153 Test requirement: is_intel_device(fd)
11524 14:50:39.280870 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11525 14:50:39.288066 Test requirement: is_<14>[ 15.925269] [IGT] kms_addfb_basic: executing
11526 14:50:39.288194 intel_device(fd)
11527 14:50:39.294439 No KMS driver or no outputs, pipes: 16, outputs: 0
11528 14:50:39.300884 IGT-Versio<14>[ 15.937293] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11529 14:50:39.307530 n: 1.28-ga44ebfe<14>[ 15.944250] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11530 14:50:39.313823 (aarch64) (Linux: 6.1.91-cip21 aarch64)
11531 14:50:39.320693 Using IGT_SRANDOM=1717512639 for rando<14>[ 15.958797] [IGT] kms_addfb_basic: exiting, ret=0
11532 14:50:39.320816 misation
11533 14:50:39.323733 Opened device: /dev/dri/card0
11534 14:50:39.327428 Starting subtest: bad-pitch-128
11535 14:50:39.333980 [1mSu<8>[ 15.971522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11536 14:50:39.334275 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11538 14:50:39.337476 btest bad-pitch-128: SUCCESS (0.000s)[0m
11539 14:50:39.347019 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11540 14:50:39.350499 Test requirement: is_intel_device(fd)
11541 14:50:39.356952 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11542 14:50:39.363799 Test requirement: is_i<14>[ 16.001613] [IGT] kms_addfb_basic: executing
11543 14:50:39.363921 ntel_device(fd)
11544 14:50:39.370215 No KMS driver or no outputs, pipes: 16, outputs: 0
11545 14:50:39.376806 IGT-Version: 1.28-ga44ebfe <14>[ 16.014650] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11546 14:50:39.386973 (aarch64) (Linux<14>[ 16.022273] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11547 14:50:39.390479 : 6.1.91-cip21 aarch64)
11548 14:50:39.393525 Using IGT_SRANDOM=1717512639 for randomisation
11549 14:50:39.400023 Opened <14>[ 16.037353] [IGT] kms_addfb_basic: exiting, ret=0
11550 14:50:39.400142 device: /dev/dri/card0
11551 14:50:39.403427 Starting subtest: bad-pitch-256
11552 14:50:39.413654 [1mSubtest bad-pitch-2<8>[ 16.049724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11553 14:50:39.413962 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11555 14:50:39.416934 56: SUCCESS (0.000s)[0m
11556 14:50:39.423139 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11557 14:50:39.426932 Test requirement: is_intel_device(fd)
11558 14:50:39.433183 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11559 14:50:39.436448 Test requirement: is_intel_device(fd)
11560 14:50:39.439711 <14>[ 16.079563] [IGT] kms_addfb_basic: executing
11561 14:50:39.446305 No KMS driver or no outputs, pipes: 16, outputs: 0
11562 14:50:39.456381 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 16.092659] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11563 14:50:39.466498 6.1.91-cip21 aa<14>[ 16.100250] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11564 14:50:39.466698 rch64)
11565 14:50:39.470063 Using IGT_SRANDOM=1717512639 for randomisation
11566 14:50:39.476045 Opened device: /dev/dri/<14>[ 16.115350] [IGT] kms_addfb_basic: exiting, ret=0
11567 14:50:39.476178 card0
11568 14:50:39.479352 Starting subtest: bad-pitch-1024
11569 14:50:39.489763 [1mSubtest bad-pitch-1024: SUCCESS (0.<8>[ 16.127597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11570 14:50:39.490098 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11572 14:50:39.492893 000s)[0m
11573 14:50:39.499409 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11574 14:50:39.502905 Test requirement: is_intel_device(fd)
11575 14:50:39.512771 Test requirement not met in function igt_r<14>[ 16.149434] [IGT] kms_addfb_basic: executing
11576 14:50:39.516002 equire_intel, file ../lib/drmtest.c:880:
11577 14:50:39.519340 Test requirement: is_intel_device(fd)
11578 14:50:39.526047 <14>[ 16.161561] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11579 14:50:39.526172
11580 14:50:39.532413 No KMS driver o<14>[ 16.168843] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11581 14:50:39.535640 r no outputs, pipes: 16, outputs: 0
11582 14:50:39.546361 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 16.183320] [IGT] kms_addfb_basic: exiting, ret=0
11583 14:50:39.548896 : 6.1.91-cip21 aarch64)
11584 14:50:39.552191 Using IGT_SRANDOM=1717512639 for randomisation
11585 14:50:39.558646 Opened <8>[ 16.196379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11586 14:50:39.558972 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11588 14:50:39.562399 device: /dev/dri/card0
11589 14:50:39.565374 Starting subtest: bad-pitch-999
11590 14:50:39.568673 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11591 14:50:39.575111 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11592 14:50:39.578932 Test requirement: is_intel_device(fd)
11593 14:50:39.588455 Test requirement not met in function igt_re<14>[ 16.226585] [IGT] kms_addfb_basic: executing
11594 14:50:39.591542 quire_intel, file ../lib/drmtest.c:880:
11595 14:50:39.594965 Test requirement: is_intel_device(fd)
11596 14:50:39.604985 No KMS driver or no outputs, pip<14>[ 16.241525] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11597 14:50:39.614885 es: 16, outputs:<14>[ 16.248940] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11598 14:50:39.615029 0
11599 14:50:39.624616 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aa<14>[ 16.262534] [IGT] kms_addfb_basic: exiting, ret=0
11600 14:50:39.624746 rch64)
11601 14:50:39.628182 Using IGT_SRANDOM=1717512639 for randomisation
11602 14:50:39.637976 Opened device: /dev/dri/<8>[ 16.275546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11603 14:50:39.638292 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11605 14:50:39.641207 card0
11606 14:50:39.644506 Starting subtest: bad-pitch-65536
11607 14:50:39.647923 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11608 14:50:39.654571 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11609 14:50:39.657684 Test requirement: is_intel_device(fd)
11610 14:50:39.667845 Test requirement not met in function igt_require_intel, <14>[ 16.306021] [IGT] kms_addfb_basic: executing
11611 14:50:39.671494 file ../lib/drmtest.c:880:
11612 14:50:39.674268 Test requirement: is_intel_device(fd)
11613 14:50:39.684502 No KMS driver or no outputs, pipes: 16, outpu<14>[ 16.321162] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11614 14:50:39.684677 ts: 0
11615 14:50:39.694301 IGT-Versi<14>[ 16.328204] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11616 14:50:39.697665 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11617 14:50:39.704355 Using<14>[ 16.341496] [IGT] kms_addfb_basic: exiting, ret=0
11618 14:50:39.707843 IGT_SRANDOM=1717512639 for randomisation
11619 14:50:39.710701 Opened device: /dev/dri/card0
11620 14:50:39.717463 Starti<8>[ 16.354336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11621 14:50:39.717759 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11623 14:50:39.720889 ng subtest: invalid-get-prop-any
11624 14:50:39.724109 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11625 14:50:39.734131 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11626 14:50:39.737427 Te<14>[ 16.377050] [IGT] kms_addfb_basic: executing
11627 14:50:39.740915 st requirement: is_intel_device(fd)
11628 14:50:39.753948 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 16.390238] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11629 14:50:39.754117 .c:880:
11630 14:50:39.763648 Test re<14>[ 16.398823] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11631 14:50:39.767377 quirement: is_intel_device(fd)
11632 14:50:39.773569 No KMS driver or<14>[ 16.412025] [IGT] kms_addfb_basic: exiting, ret=0
11633 14:50:39.776772 no outputs, pipes: 16, outputs: 0
11634 14:50:39.786967 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 16.423693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11635 14:50:39.787286 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11637 14:50:39.790472 6.1.91-cip21 aarch64)
11638 14:50:39.793273 Using IGT_SRANDOM=1717512639 for randomisation
11639 14:50:39.797034 Opened device: /dev/dri/card0
11640 14:50:39.799826 Starting subtest: invalid-get-prop
11641 14:50:39.803628 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11642 14:50:39.816772 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880<14>[ 16.454356] [IGT] kms_addfb_basic: executing
11643 14:50:39.816916 :
11644 14:50:39.820157 Test requirement: is_intel_device(fd)
11645 14:50:39.832958 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 16.469684] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11646 14:50:39.833105 mtest.c:880:
11647 14:50:39.842789 Te<14>[ 16.476761] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11648 14:50:39.846372 st requirement: is_intel_device(fd)
11649 14:50:39.852881 No KMS driver or no outputs<14>[ 16.489995] [IGT] kms_addfb_basic: exiting, ret=0
11650 14:50:39.853030 , pipes: 16, outputs: 0
11651 14:50:39.859426 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11652 14:50:39.866243 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11654 14:50:39.869399 Usi<8>[ 16.503147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11655 14:50:39.872635 ng IGT_SRANDOM=1717512639 for randomisation
11656 14:50:39.876296 Opened device: /dev/dri/card0
11657 14:50:39.879096 Starting subtest: invalid-set-prop-any
11658 14:50:39.882956 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11659 14:50:39.888988 Test<14>[ 16.526800] [IGT] kms_addfb_basic: executing
11660 14:50:39.895702 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11661 14:50:39.899246 Test requirement: is_intel_device(fd)
11662 14:50:39.905903 Test requ<14>[ 16.542372] [IGT] kms_addfb_basic: starting subtest master-rmfb
11663 14:50:39.912292 irement not met <14>[ 16.549527] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11664 14:50:39.922682 in function igt_require_intel, f<14>[ 16.559906] [IGT] kms_addfb_basic: exiting, ret=0
11665 14:50:39.925832 ile ../lib/drmtest.c:880:
11666 14:50:39.928797 Test requirement: is_intel_device(fd)
11667 14:50:39.935267 No KMS driver <8>[ 16.572490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11668 14:50:39.935586 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11670 14:50:39.938729 or no outputs, pipes: 16, outputs: 0
11671 14:50:39.945551 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11672 14:50:39.948993 Using IGT_SRANDOM=1717512639 for randomisation
11673 14:50:39.952177 Opened device: /dev/dri/card0
11674 14:50:39.955279 Starting subtest: invalid-set-prop
11675 14:50:39.958648 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11676 14:50:39.965436 <14>[ 16.602302] [IGT] kms_addfb_basic: executing
11677 14:50:39.965580
11678 14:50:39.972029 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11679 14:50:39.975214 Test requirement: is_intel_device(fd)
11680 14:50:39.985142 Test requirement not met in function<14>[ 16.621459] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11681 14:50:39.994921 igt_require_int<14>[ 16.629187] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11682 14:50:40.001594 el, file ../lib/<14>[ 16.639009] [IGT] kms_addfb_basic: exiting, ret=0
11683 14:50:40.001734 drmtest.c:880:
11684 14:50:40.005168 Test requirement: is_intel_device(fd)
11685 14:50:40.014734 No KMS driver or no outpu<8>[ 16.651815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11686 14:50:40.015109 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11688 14:50:40.018355 ts, pipes: 16, outputs: 0
11689 14:50:40.024567 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11690 14:50:40.028332 Using IGT_SRANDOM=1717512639 for randomisation
11691 14:50:40.031575 Opened device: /dev/dri/card0
11692 14:50:40.034641 Starting subtest: master-rmfb
11693 14:50:40.037965 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11694 14:50:40.044347 Test requirement not<14>[ 16.683200] [IGT] kms_addfb_basic: executing
11695 14:50:40.051284 met in function igt_require_intel, file ../lib/drmtest.c:880:
11696 14:50:40.054747 Test requirement: is_intel_device(fd)
11697 14:50:40.064512 Test requirement not met in function igt_require_intel, f<14>[ 16.702053] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11698 14:50:40.067534 ile ../lib/drmtest.c:880:
11699 14:50:40.071156 Test requirement: is_intel_device(fd)
11700 14:50:40.083970 No KMS driver or no outputs, pipes: 16, output<14>[ 16.717788] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11701 14:50:40.084118 s: 0
11702 14:50:40.090932 IGT-Versio<14>[ 16.727071] [IGT] kms_addfb_basic: exiting, ret=98
11703 14:50:40.094529 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11704 14:50:40.103798 Using IGT_SRANDOM=1717<8>[ 16.740148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11705 14:50:40.104114 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11707 14:50:40.107112 512639 for randomisation
11708 14:50:40.107202 Opened device: /dev/dri/card0
11709 14:50:40.113798 Starting subtest: addfb25-modifier-no-flag
11710 14:50:40.117394 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11711 14:50:40.123533 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11712 14:50:40.133499 Test requirement: is_intel_<14>[ 16.770327] [IGT] kms_addfb_basic: executing
11713 14:50:40.133669 device(fd)
11714 14:50:40.140196 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11715 14:50:40.143857 Test requirement: is_intel_device(fd)
11716 14:50:40.153625 No KMS driver or no outputs, pipes: 16, o<14>[ 16.790443] [IGT] kms_addfb_basic: exiting, ret=77
11717 14:50:40.153764 utputs: 0
11718 14:50:40.160006 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11719 14:50:40.166693 U<8>[ 16.803552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11720 14:50:40.167001 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11722 14:50:40.173173 sing IGT_SRANDOM=1717512640 for randomisation
11723 14:50:40.176394 Opened device: /dev/dri/card0
11724 14:50:40.179795 Starting subtest: addfb25-bad-modifier
11725 14:50:40.189662 (kms_addfb_basic:436) CRITICAL: Test assertion failure fun<14>[ 16.826321] [IGT] kms_addfb_basic: executing
11726 14:50:40.193396 ction addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11727 14:50:40.206342 (kms_addfb_basic:436) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | (((<14>[ 16.844980] [IGT] kms_addfb_basic: exiting, ret=77
11728 14:50:40.222677 'd')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((<8>[ 16.858103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11729 14:50:40.222831 0+8)+8)))), (&f)) == -1
11730 14:50:40.223144 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11732 14:50:40.229192 (kms_addfb_basic:436) CRITICAL: error: 0 != -1
11733 14:50:40.229297 Stack trace:
11734 14:50:40.232681 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11735 14:50:40.236101 #1 [<unknown>+0xd78b4358]
11736 14:50:40.242307 #2 [<unkn<14>[ 16.880750] [IGT] kms_addfb_basic: executing
11737 14:50:40.242425 own>+0xd78b5fbc]
11738 14:50:40.245826 #3 [<unknown>+0xd78b156c]
11739 14:50:40.249484 #4 [__libc_init_first+0x80]
11740 14:50:40.252527 #5 [__libc_start_main+0x98]
11741 14:50:40.255794 #6 [<unknown>+0xd78b15b0]
11742 14:50:40.262486 Subtest addfb25-bad-mo<14>[ 16.898805] [IGT] kms_addfb_basic: exiting, ret=77
11743 14:50:40.262648 difier failed.
11744 14:50:40.265742 **** DEBUG ****
11745 14:50:40.275557 (kms_addfb_basic:436) ioctl_wrappers-DEBUG: Tes<8>[ 16.911637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11746 14:50:40.275930 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11748 14:50:40.281763 t requirement passed: igt_has_fb_modifiers(fd)
11749 14:50:40.292060 (kms_addfb_basic:436) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11750 14:50:40.305021 (kms_addfb_basic:436) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) <14>[ 16.943309] [IGT] kms_addfb_basic: executing
11751 14:50:40.314895 << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11752 14:50:40.318701 (kms_addfb_basic:436) CRITICAL: error: 0 != -1
11753 14:50:40.325131 (kms_addfb_basic:436) igt_cor<14>[ 16.963226] [IGT] kms_addfb_basic: exiting, ret=77
11754 14:50:40.328234 e-INFO: Stack trace:
11755 14:50:40.341558 (kms_addfb_basic:436) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fai<8>[ 16.976715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11756 14:50:40.341697 l_assert()
11757 14:50:40.341974 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11759 14:50:40.348001 (kms_addfb_basic:436) igt_core-INFO: #1 [<unknown>+0xd78b4358]
11760 14:50:40.354775 (kms_addfb_basic:436) igt_core-INFO: #2 [<unknown>+0xd78b5fbc]
11761 14:50:40.361402 (kms_addfb_basic:436) igt_core-INFO: #3 [<unknown>+0xd78b156c]
11762 14:50:40.371372 (kms_addfb_basic:436) igt_core-INFO: #4 [__libc_init_first+0<14>[ 17.008061] [IGT] kms_addfb_basic: executing
11763 14:50:40.371513 x80]
11764 14:50:40.377822 (kms_addfb_basic:436) igt_core-INFO: #5 [__libc_start_main+0x98]
11765 14:50:40.381162 (kms_addfb_basic:436) igt_core-INFO: #6 [<unknown>+0xd78b15b0]
11766 14:50:40.384302 **** END ****
11767 14:50:40.390758 [1mSubtest addfb25<14>[ 17.028155] [IGT] kms_addfb_basic: exiting, ret=77
11768 14:50:40.394007 -bad-modifier: FAIL (0.008s)[0m
11769 14:50:40.403744 Test requirement not met in function igt_requi<8>[ 17.040555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11770 14:50:40.404051 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11772 14:50:40.407095 re_intel, file ../lib/drmtest.c:880:
11773 14:50:40.413793 Test requirement: is_intel_device(fd)
11774 14:50:40.420480 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11775 14:50:40.427136 Test requirement: is_intel_devi<14>[ 17.065733] [IGT] kms_addfb_basic: executing
11776 14:50:40.427253 ce(fd)
11777 14:50:40.433813 No KMS driver or no outputs, pipes: 16, outputs: 0
11778 14:50:40.437231 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11779 14:50:40.443341 Using IGT_SRANDO<14>[ 17.083436] [IGT] kms_addfb_basic: exiting, ret=77
11780 14:50:40.446954 M=1717512640 for randomisation
11781 14:50:40.450225 Opened device: /dev/dri/card0
11782 14:50:40.459990 Test requirement <8>[ 17.095291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11783 14:50:40.460298 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11785 14:50:40.466883 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11786 14:50:40.469652 Test requirement: is_intel_device(fd)
11787 14:50:40.476401 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.0<14>[ 17.116701] [IGT] kms_addfb_basic: executing
11788 14:50:40.479700 00s)[0m
11789 14:50:40.486275 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11790 14:50:40.489432 Test requirement: is_intel_device(fd)
11791 14:50:40.496184 No KMS driv<14>[ 17.134317] [IGT] kms_addfb_basic: exiting, ret=77
11792 14:50:40.499789 er or no outputs, pipes: 16, outputs: 0
11793 14:50:40.509524 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 17.146193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11794 14:50:40.509832 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11796 14:50:40.512581 inux: 6.1.91-cip21 aarch64)
11797 14:50:40.516536 Using IGT_SRANDOM=1717512640 for randomisation
11798 14:50:40.519663 Opened device: /dev/dri/card0
11799 14:50:40.525876 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11800 14:50:40.532468 <14>[ 17.169979] [IGT] kms_addfb_basic: executing
11801 14:50:40.535778 Test requirement: is_intel_device(fd)
11802 14:50:40.539200 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11803 14:50:40.549218 Test requirement not met in function igt_require_intel, file ../li<14>[ 17.188177] [IGT] kms_addfb_basic: exiting, ret=77
11804 14:50:40.552611 b/drmtest.c:880:
11805 14:50:40.555668 Test requirement: is_intel_device(fd)
11806 14:50:40.565766 No KMS driver or no out<8>[ 17.201219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11807 14:50:40.565899 puts, pipes: 16, outputs: 0
11808 14:50:40.566146 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11810 14:50:40.572513 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11811 14:50:40.575649 Using IGT_SRANDOM=1717512640 for randomisation
11812 14:50:40.578682 Opened device: /dev/dri/card0
11813 14:50:40.585401 <14>[ 17.223550] [IGT] kms_addfb_basic: executing
11814 14:50:40.592471 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11815 14:50:40.595804 Test requirement: is_intel_device(fd)
11816 14:50:40.602137 [1mSubtest addfb25-framebuffer-vs-se<14>[ 17.241007] [IGT] kms_addfb_basic: exiting, ret=77
11817 14:50:40.605500 t-tiling: SKIP (0.000s)[0m
11818 14:50:40.615497 Test requirement not met in function igt_require_in<8>[ 17.254075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11819 14:50:40.615804 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11821 14:50:40.618637 tel, file ../lib/drmtest.c:880:
11822 14:50:40.621871 Test requirement: is_intel_device(fd)
11823 14:50:40.628774 No KMS driver or no outputs, pipes: 16, outputs: 0
11824 14:50:40.635270 IGT-Version: 1.28-ga44ebfe (aarch64)<14>[ 17.273828] [IGT] kms_addfb_basic: executing
11825 14:50:40.638446 (Linux: 6.1.91-cip21 aarch64)
11826 14:50:40.641922 Using IGT_SRANDOM=1717512640 for randomisation
11827 14:50:40.644882 Opened device: /dev/dri/card0
11828 14:50:40.654897 Test requirement not met in function igt_require_<14>[ 17.292206] [IGT] kms_addfb_basic: exiting, ret=77
11829 14:50:40.658174 intel, file ../lib/drmtest.c:880:
11830 14:50:40.661661 Test requirement: is_intel_device(fd)
11831 14:50:40.667984 Test r<8>[ 17.305370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11832 14:50:40.668296 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11834 14:50:40.674770 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11835 14:50:40.677706 Test requirement: is_intel_device(fd)
11836 14:50:40.684440 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11837 14:50:40.687908 No KMS driver or no outputs, pipes: 16, outputs: 0
11838 14:50:40.697685 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.9<14>[ 17.334845] [IGT] kms_addfb_basic: executing
11839 14:50:40.697848 1-cip21 aarch64)
11840 14:50:40.701251 Using IGT_SRANDOM=1717512640 for randomisation
11841 14:50:40.704463 Opened device: /dev/dri/card0
11842 14:50:40.717518 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 17.354688] [IGT] kms_addfb_basic: exiting, ret=77
11843 14:50:40.717677 80:
11844 14:50:40.721148 Test requirement: is_intel_device(fd)
11845 14:50:40.730939 Test requirement not met in function igt_require_int<8>[ 17.367881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11846 14:50:40.731263 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11848 14:50:40.734152 el, file ../lib/drmtest.c:880:
11849 14:50:40.737394 Test requirement: is_intel_device(fd)
11850 14:50:40.743981 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11851 14:50:40.747755 No KMS driver or no outputs, pipes: 16, outputs: 0
11852 14:50:40.754260 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11853 14:50:40.761047 Using IGT_SRANDOM=17175<14>[ 17.399031] [IGT] kms_addfb_basic: executing
11854 14:50:40.763912 12640 for randomisation
11855 14:50:40.764028 Opened device: /dev/dri/card0
11856 14:50:40.774108 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11857 14:50:40.780530 Test requirement: is_intel_device(fd<14>[ 17.418740] [IGT] kms_addfb_basic: exiting, ret=77
11858 14:50:40.780760 )
11859 14:50:40.793643 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<8>[ 17.431172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11860 14:50:40.793786 :880:
11861 14:50:40.794043 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11863 14:50:40.796900 Test requirement: is_intel_device(fd)
11864 14:50:40.803867 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11865 14:50:40.807074 No KMS driver or no outputs, pipes: 16, outputs: 0
11866 14:50:40.813488 IGT-Versio<14>[ 17.452523] [IGT] kms_addfb_basic: executing
11867 14:50:40.817225 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11868 14:50:40.823727 Using IGT_SRANDOM=1717512640 for randomisation
11869 14:50:40.823844 Opened device: /dev/dri/card0
11870 14:50:40.833803 Test requirement not me<14>[ 17.469987] [IGT] kms_addfb_basic: exiting, ret=77
11871 14:50:40.836906 t in function igt_require_intel, file ../lib/drmtest.c:880:
11872 14:50:40.846659 Test requirement: i<8>[ 17.482810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11873 14:50:40.846964 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11875 14:50:40.849838 s_intel_device(fd)
11876 14:50:40.856820 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11877 14:50:40.859849 Test requirement: is_intel_device(fd)
11878 14:50:40.863037 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11879 14:50:40.869545 No KMS driver or no outputs, pipes: 16, outputs: 0
11880 14:50:40.876562 IGT-Version: 1.28-ga44eb<14>[ 17.513773] [IGT] kms_addfb_basic: executing
11881 14:50:40.879959 fe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11882 14:50:40.883280 Using IGT_SRANDOM=1717512640 for randomisation
11883 14:50:40.886290 Opened device: /dev/dri/card0
11884 14:50:40.895970 Test requirement not met in function igt_require_inte<14>[ 17.533946] [IGT] kms_addfb_basic: exiting, ret=77
11885 14:50:40.899325 l, file ../lib/drmtest.c:880:
11886 14:50:40.902980 Test requirement: is_intel_device(fd)
11887 14:50:40.912406 Test requirement not met in function igt_r<8>[ 17.549875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11888 14:50:40.912749 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11890 14:50:40.915774 equire_intel, file ../lib/drmtest.c:880:
11891 14:50:40.919151 Test requirement: is_intel_device(fd)
11892 14:50:40.925820 No KMS driver or no outputs, pipes: 16, outputs: 0
11893 14:50:40.932663 [1mSubtest size-max: SKIP <14>[ 17.571564] [IGT] kms_addfb_basic: executing
11894 14:50:40.932786 (0.000s)[0m
11895 14:50:40.939365 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11896 14:50:40.942639 Using IGT_SRANDOM=1717512640 for randomisation
11897 14:50:40.948956 Opened device:<14>[ 17.588879] [IGT] kms_addfb_basic: exiting, ret=77
11898 14:50:40.952234 /dev/dri/card0
11899 14:50:40.965466 Test requirement not met in function igt_require_intel, file ..<8>[ 17.600523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11900 14:50:40.965676 /lib/drmtest.c:880:
11901 14:50:40.965981 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11903 14:50:40.968963 Test requirement: is_intel_device(fd)
11904 14:50:40.978933 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11905 14:50:40.982187 Test requirement: is_intel_device(fd)
11906 14:50:40.985353 No KMS driver or no outputs, pipes: 16, outputs: 0
11907 14:50:40.991925 [1mSubtest too-wide: SKIP (0.000s)[<14>[ 17.631348] [IGT] kms_addfb_basic: executing
11908 14:50:40.992041 0m
11909 14:50:40.998402 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11910 14:50:41.001756 Using IGT_SRANDOM=1717512640 for randomisation
11911 14:50:41.004979 Opened device: /dev/dri/card0
11912 14:50:41.015029 Test requirement not met <14>[ 17.651272] [IGT] kms_addfb_basic: exiting, ret=77
11913 14:50:41.018343 in function igt_require_intel, file ../lib/drmtest.c:880:
11914 14:50:41.031644 Test requirement: is_intel_device(fd)<8>[ 17.664699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11915 14:50:41.031848
11916 14:50:41.032156 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11918 14:50:41.038417 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11919 14:50:41.041765 Test requirement: is_intel_device(fd)
11920 14:50:41.045162 No KMS driver or no outputs, pipes: 16, outputs: 0
11921 14:50:41.048485 [1mSubtest too-high: SKIP (0.000s)[0m
11922 14:50:41.058224 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-ci<14>[ 17.697831] [IGT] kms_addfb_basic: executing
11923 14:50:41.058401 p21 aarch64)
11924 14:50:41.064927 Using IGT_SRANDOM=1717512640 for randomisation
11925 14:50:41.068080 Opened device: /dev/dri/card0
11926 14:50:41.074470 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11927 14:50:41.078462 <14>[ 17.716887] [IGT] kms_addfb_basic: exiting, ret=77
11928 14:50:41.078550
11929 14:50:41.081492 Test requirement: is_intel_device(fd)
11930 14:50:41.094533 Test requirement not met in function igt<8>[ 17.729791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11931 14:50:41.094857 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11933 14:50:41.100929 _require_intel, file ../lib/drmt<8>[ 17.738686] <LAVA_SIGNAL_TESTSET STOP>
11934 14:50:41.101063 est.c:880:
11935 14:50:41.101360 Received signal: <TESTSET> STOP
11936 14:50:41.101451 Closing test_set kms_addfb_basic
11937 14:50:41.104218 Test requirement: is_intel_device(fd)
11938 14:50:41.108023 No KMS driver or no outputs, pipes: 16, outputs: 0
11939 14:50:41.114368 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11940 14:50:41.117771 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11941 14:50:41.124106 Using IGT_SRANDOM=1717512640 for randomisation
11942 14:50:41.124270 Opened device: /dev/dri/card0
11943 14:50:41.130648 Test requ<8>[ 17.770097] <LAVA_SIGNAL_TESTSET START kms_atomic>
11944 14:50:41.131015 Received signal: <TESTSET> START kms_atomic
11945 14:50:41.131109 Starting test_set kms_atomic
11946 14:50:41.137279 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11947 14:50:41.140594 Test requirement: is_intel_device(fd)
11948 14:50:41.147230 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11949 14:50:41.150783 Test requirement: is_intel_device(fd)
11950 14:50:41.160384 No KMS driver or no outputs, pipes:<14>[ 17.798076] [IGT] kms_atomic: executing
11951 14:50:41.160610 16, outputs: 0
11952 14:50:41.164115 <14>[ 17.804173] [IGT] kms_atomic: exiting, ret=77
11953 14:50:41.164231
11954 14:50:41.170693 [1mSubtest small-bo: SKIP (0.000s)[0m
11955 14:50:41.177329 IGT-Version: 1.28-ga44<8>[ 17.814962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11956 14:50:41.177672 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11958 14:50:41.183641 ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11959 14:50:41.187121 Using IGT_SRANDOM=1717512640 for randomisation
11960 14:50:41.190366 Opened device: /dev/dri/card0
11961 14:50:41.196802 Test requirement not met in function igt_require_in<14>[ 17.837320] [IGT] kms_atomic: executing
11962 14:50:41.203721 tel, file ../lib<14>[ 17.842816] [IGT] kms_atomic: exiting, ret=77
11963 14:50:41.206452 /drmtest.c:880:
11964 14:50:41.209753 Test requirement: is_intel_device(fd)
11965 14:50:41.220519 Test requirement not met<8>[ 17.854160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11966 14:50:41.220839 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11968 14:50:41.223503 in function igt_require_intel, file ../lib/drmtest.c:880:
11969 14:50:41.226577 Test requirement: is_intel_device(fd)
11970 14:50:41.233095 No KMS driver or no outputs, pipes: 16, outputs: 0
11971 14:50:41.236299 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11972 14:50:41.245938 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarc<14>[ 17.886035] [IGT] kms_atomic: executing
11973 14:50:41.246103 h64)
11974 14:50:41.252768 Using IGT_<14>[ 17.892033] [IGT] kms_atomic: exiting, ret=77
11975 14:50:41.256078 SRANDOM=1717512640 for randomisation
11976 14:50:41.266034 Opened device: /dev/dri/ca<8>[ 17.902472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11977 14:50:41.266369 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11979 14:50:41.269442 rd0
11980 14:50:41.275859 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11981 14:50:41.279402 Test requirement: is_intel_device(fd)
11982 14:50:41.289248 Test requirement not met in function igt_require_intel, file ../<14>[ 17.927104] [IGT] kms_atomic: executing
11983 14:50:41.295841 lib/drmtest.c:88<14>[ 17.932937] [IGT] kms_atomic: exiting, ret=77
11984 14:50:41.295988 0:
11985 14:50:41.299076 Test requirement: is_intel_device(fd)
11986 14:50:41.309355 No KMS driver or no outputs, pipes: 1<8>[ 17.944943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11987 14:50:41.309506 6, outputs: 0
11988 14:50:41.309760 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11990 14:50:41.315751 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11991 14:50:41.322217 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11992 14:50:41.328795 Using IGT_SRANDOM=1717512640 for rando<14>[ 17.967741] [IGT] kms_atomic: executing
11993 14:50:41.328912 misation
11994 14:50:41.335208 Opened<14>[ 17.973163] [IGT] kms_atomic: exiting, ret=77
11995 14:50:41.335314 device: /dev/dri/card0
11996 14:50:41.348827 Test requirement not met in function igt_require_intel,<8>[ 17.985369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11997 14:50:41.349149 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11999 14:50:41.351704 file ../lib/drmtest.c:880:
12000 14:50:41.355139 Test requirement: is_intel_device(fd)
12001 14:50:41.361965 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12002 14:50:41.364901 Test requirement: is_intel_device(fd)
12003 14:50:41.368253 No KMS driver or no outputs, pipes: 16, outputs: 0
12004 14:50:41.374870 [1mSubtest addfb25-yf-tiled-<14>[ 18.014987] [IGT] kms_atomic: executing
12005 14:50:41.381931 legacy: SKIP (0.<14>[ 18.021166] [IGT] kms_atomic: exiting, ret=77
12006 14:50:41.384876 000s)[0m
12007 14:50:41.388201 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12008 14:50:41.394811 Using IGT_SRANDOM=1717512640 for randomisation
12009 14:50:41.401820 O<8>[ 18.036769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12010 14:50:41.402123 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12012 14:50:41.405364 pened device: /dev/dri/card0
12013 14:50:41.411334 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12014 14:50:41.414581 Test requirement: is_intel_device(fd)
12015 14:50:41.421583 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12016 14:50:41.424743 Test requirement: is_intel_device(fd)
12017 14:50:41.431118 No KMS drive<14>[ 18.069371] [IGT] kms_atomic: executing
12018 14:50:41.437604 r or no outputs,<14>[ 18.075222] [IGT] kms_atomic: exiting, ret=77
12019 14:50:41.437709 pipes: 16, outputs: 0
12020 14:50:41.450856 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)<8>[ 18.086227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12021 14:50:41.450996 [0m
12022 14:50:41.451242 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12024 14:50:41.457795 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12025 14:50:41.460817 Using IGT_SRANDOM=1717512641 for randomisation
12026 14:50:41.463855 Opened device: /dev/dri/card0
12027 14:50:41.470706 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12028 14:50:41.477285 Test requirement: is_intel_device(fd<14>[ 18.118129] [IGT] kms_atomic: executing
12029 14:50:41.480904 )
12030 14:50:41.483586 Test requirem<14>[ 18.123803] [IGT] kms_atomic: exiting, ret=77
12031 14:50:41.496878 ent not met in function igt_require_intel, file ../lib/drmtest.c<8>[ 18.134577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12032 14:50:41.497204 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12034 14:50:41.500221 :880:
12035 14:50:41.503846 Test requirement: is_intel_device(fd)
12036 14:50:41.507034 No KMS driver or no outputs, pipes: 16, outputs: 0
12037 14:50:41.510212 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12038 14:50:41.517145 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12039 14:50:41.520611 Using IGT_SRANDOM=1717512641 for randomisation
12040 14:50:41.527036 Opened device: /dev/dri/ca<14>[ 18.166737] [IGT] kms_atomic: executing
12041 14:50:41.527177 rd0
12042 14:50:41.533853 No KMS driv<14>[ 18.173266] [IGT] kms_atomic: exiting, ret=77
12043 14:50:41.536660 er or no outputs, pipes: 16, outputs: 0
12044 14:50:41.546723 [1mSubtest plane-overl<8>[ 18.183704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12045 14:50:41.547026 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12047 14:50:41.550243 ay-legacy: SKIP (0.000s)[0m
12048 14:50:41.557104 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12049 14:50:41.560027 Using IGT_SRANDOM=1717512641 for randomisation
12050 14:50:41.563308 Opened device: /dev/dri/card0
12051 14:50:41.566826 <14>[ 18.206151] [IGT] kms_atomic: executing
12052 14:50:41.566944
12053 14:50:41.573229 No KMS driver o<14>[ 18.211456] [IGT] kms_atomic: exiting, ret=77
12054 14:50:41.576423 r no outputs, pipes: 16, outputs: 0
12055 14:50:41.586535 [1mSubtest plane-primary-legacy: SKIP (0.0<8>[ 18.223506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12056 14:50:41.586849 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12058 14:50:41.589796 00s)[0m
12059 14:50:41.596663 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12060 14:50:41.599390 Using IGT_SRANDOM=1717512641 for randomisation
12061 14:50:41.602799 Opened device: /dev/dri/card0
12062 14:50:41.606100 No <14>[ 18.245290] [IGT] kms_atomic: executing
12063 14:50:41.612698 KMS driver or no<14>[ 18.250713] [IGT] kms_atomic: exiting, ret=77
12064 14:50:41.616129 outputs, pipes: 16, outputs: 0
12065 14:50:41.625970 [1mSubtest plane-primary-overlay-mutable-zpos:<8>[ 18.262744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12066 14:50:41.626272 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12068 14:50:41.629472 SKIP (0.000s)[0m
12069 14:50:41.636103 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12070 14:50:41.639306 Using IGT_SRANDOM=1717512641 for randomisation
12071 14:50:41.642585 Opened device: /dev/dri/card0
12072 14:50:41.645853 No KMS driver or no outputs, pipes: 16, outputs: 0
12073 14:50:41.649026 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12074 14:50:41.655893 <14>[ 18.293918] [IGT] kms_atomic: executing
12075 14:50:41.662330 IGT-Version: 1.2<14>[ 18.299747] [IGT] kms_atomic: exiting, ret=77
12076 14:50:41.665429 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12077 14:50:41.668665 Using IGT_SRANDOM=1717512641 for randomisation
12078 14:50:41.679116 Opened device: /dev/dri/card<8>[ 18.315104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12079 14:50:41.679253 0
12080 14:50:41.679502 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12082 14:50:41.685344 No KMS driver or no outputs, <8>[ 18.325971] <LAVA_SIGNAL_TESTSET STOP>
12083 14:50:41.685651 Received signal: <TESTSET> STOP
12084 14:50:41.685738 Closing test_set kms_atomic
12085 14:50:41.688838 pipes: 16, outputs: 0
12086 14:50:41.691805 [1mSubtest test-only: SKIP (0.000s)[0m
12087 14:50:41.698521 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12088 14:50:41.701723 Using IGT_SRANDOM=1717512641 for randomisation
12089 14:50:41.705240 Opened device: /dev/dri/card0
12090 14:50:41.708472 No KMS driver or no outputs, pipes: 16, outputs: 0
12091 14:50:41.715000 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12092 14:50:41.718708 IGT-<8>[ 18.357987] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12093 14:50:41.718981 Received signal: <TESTSET> START kms_flip_event_leak
12094 14:50:41.719055 Starting test_set kms_flip_event_leak
12095 14:50:41.725304 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12096 14:50:41.728597 Using IGT_SRANDOM=1717512641 for randomisation
12097 14:50:41.731662 Opened device: /dev/dri/card0
12098 14:50:41.738359 No KMS driver or no outputs, pipes: 16, outputs: 0
12099 14:50:41.741730 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12100 14:50:41.748267 IGT-Version: 1.28-ga44eb<14>[ 18.386719] [IGT] kms_flip_event_leak: executing
12101 14:50:41.754927 fe (aarch64) (Li<14>[ 18.393785] [IGT] kms_flip_event_leak: exiting, ret=77
12102 14:50:41.758412 nux: 6.1.91-cip21 aarch64)
12103 14:50:41.761416 Using IGT_SRANDOM=1717512641 for randomisation
12104 14:50:41.771518 Opened device: /dev/<8>[ 18.407468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12105 14:50:41.771660 dri/card0
12106 14:50:41.771940 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12108 14:50:41.778361 No KMS driver or no o<8>[ 18.415918] <LAVA_SIGNAL_TESTSET STOP>
12109 14:50:41.778472 utputs, pipes: 16, outputs: 0
12110 14:50:41.778714 Received signal: <TESTSET> STOP
12111 14:50:41.778784 Closing test_set kms_flip_event_leak
12112 14:50:41.784625 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12113 14:50:41.791358 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12114 14:50:41.794954 Using IGT_SRANDOM=1717512641 for randomisation
12115 14:50:41.797710 Opened device: /dev/dri/card0
12116 14:50:41.801058 No KMS driver or no outputs, pipes: 16, outputs: 0
12117 14:50:41.811398 [1mSubtest crtc-invalid-params<8>[ 18.448681] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12118 14:50:41.811530 : SKIP (0.000s)[0m
12119 14:50:41.811779 Received signal: <TESTSET> START kms_prop_blob
12120 14:50:41.811880 Starting test_set kms_prop_blob
12121 14:50:41.817813 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12122 14:50:41.820742 Using IGT_SRANDOM=1717512641 for randomisation
12123 14:50:41.824119 Opened device: /dev/dri/card0
12124 14:50:41.827908 No KMS driver or no outputs, pipes: 16, outputs: 0
12125 14:50:41.834195 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12126 14:50:41.841215 IGT-Versio<14>[ 18.478794] [IGT] kms_prop_blob: executing
12127 14:50:41.847190 n: 1.28-ga44ebfe<14>[ 18.484504] [IGT] kms_prop_blob: starting subtest basic
12128 14:50:41.853690 (aarch64) (Linu<14>[ 18.490942] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12129 14:50:41.860453 x: 6.1.91-cip21 <14>[ 18.498760] [IGT] kms_prop_blob: exiting, ret=0
12130 14:50:41.860591 aarch64)
12131 14:50:41.867006 Using IGT_SRANDOM=1717512641 for randomisation
12132 14:50:41.873804 Opened device: /dev/dr<8>[ 18.511582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12133 14:50:41.873931 i/card0
12134 14:50:41.874175 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12136 14:50:41.880254 No KMS driver or no outputs, pipes: 16, outputs: 0
12137 14:50:41.883913 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12138 14:50:41.893769 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aar<14>[ 18.532767] [IGT] kms_prop_blob: executing
12139 14:50:41.893904 ch64)
12140 14:50:41.900290 Using IGT<14>[ 18.538385] [IGT] kms_prop_blob: starting subtest blob-prop-core
12141 14:50:41.910522 _SRANDOM=1717512<14>[ 18.545937] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12142 14:50:41.916821 641 for randomis<14>[ 18.554513] [IGT] kms_prop_blob: exiting, ret=0
12143 14:50:41.916934 ation
12144 14:50:41.919982 Opened device: /dev/dri/card0
12145 14:50:41.930309 No KMS driver or no outputs, pipes: 16, ou<8>[ 18.566758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12146 14:50:41.930450 tputs: 0
12147 14:50:41.930692 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12149 14:50:41.936726 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12150 14:50:41.943006 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12151 14:50:41.946861 Using IGT_SRANDOM=1717512641 for randomisation
12152 14:50:41.949795 Opened device: /dev/dri/card0
12153 14:50:41.952935 No KMS driver or no outputs, pipes: 16, outputs: 0
12154 14:50:41.959920 [1mSubtest<14>[ 18.597436] [IGT] kms_prop_blob: executing
12155 14:50:41.966514 basic: SKIP (0.<14>[ 18.603524] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12156 14:50:41.966675 000s)[0m
12157 14:50:41.976451 IGT-V<14>[ 18.611266] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12158 14:50:41.982770 ersion: 1.28-ga4<14>[ 18.620123] [IGT] kms_prop_blob: exiting, ret=0
12159 14:50:41.986106 4ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12160 14:50:41.996027 Using IGT_SRANDOM=1717512641 for <8>[ 18.632998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12161 14:50:41.996380 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12163 14:50:41.999548 randomisation
12164 14:50:41.999668 Opened device: /dev/dri/card0
12165 14:50:42.002788 Starting subtest: basic
12166 14:50:42.005943 [1mSubtest basic: SUCCESS (0.000s)[0m
12167 14:50:42.012490 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12168 14:50:42.016015 Using IGT_SRANDOM=1717512641 for randomisation
12169 14:50:42.019080 Opened device: /dev/dri/card0
12170 14:50:42.025723 Starting subt<14>[ 18.663329] [IGT] kms_prop_blob: executing
12171 14:50:42.032376 est: blob-prop-c<14>[ 18.669361] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12172 14:50:42.032494 ore
12173 14:50:42.042035 [1mSubtest<14>[ 18.677121] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12174 14:50:42.049176 blob-prop-core:<14>[ 18.685901] [IGT] kms_prop_blob: exiting, ret=0
12175 14:50:42.049315 SUCCESS (0.000s)[0m
12176 14:50:42.062449 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21<8>[ 18.698740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12177 14:50:42.062623 aarch64)
12178 14:50:42.062887 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12180 14:50:42.068771 Using IGT_SRANDOM=1717512641 for randomisation
12181 14:50:42.068880 Opened device: /dev/dri/card0
12182 14:50:42.072200 Starting subtest: blob-prop-validate
12183 14:50:42.078569 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12184 14:50:42.085457 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12185 14:50:42.091589 Using IGT_SRANDOM=1717512642 for rando<14>[ 18.730239] [IGT] kms_prop_blob: executing
12186 14:50:42.091710 misation
12187 14:50:42.098362 Opened<14>[ 18.736825] [IGT] kms_prop_blob: starting subtest blob-multiple
12188 14:50:42.108315 device: /dev/dr<14>[ 18.744048] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12189 14:50:42.108482 i/card0
12190 14:50:42.114827 Startin<14>[ 18.752358] [IGT] kms_prop_blob: exiting, ret=0
12191 14:50:42.118171 g subtest: blob-prop-lifetime
12192 14:50:42.128182 [1mSubtest blob-prop-lifetime: S<8>[ 18.763748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12193 14:50:42.128310 UCCESS (0.000s)[0m
12194 14:50:42.128571 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12196 14:50:42.134459 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12197 14:50:42.138037 Using IGT_SRANDOM=1717512642 for randomisation
12198 14:50:42.144828 Opened device: /dev/dri<14>[ 18.785193] [IGT] kms_prop_blob: executing
12199 14:50:42.144953 /card0
12200 14:50:42.154544 Starting<14>[ 18.789978] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12201 14:50:42.161629 subtest: blob-m<14>[ 18.798045] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12202 14:50:42.164941 ultiple
12203 14:50:42.168122 [1mSub<14>[ 18.807151] [IGT] kms_prop_blob: exiting, ret=0
12204 14:50:42.171051 test blob-multiple: SUCCESS (0.000s)[0m
12205 14:50:42.181187 IGT-Version: 1.28-ga44<8>[ 18.818598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12206 14:50:42.181506 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12208 14:50:42.188007 ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12209 14:50:42.191227 Using IGT_SRANDOM=1717512642 for randomisation
12210 14:50:42.194888 Opened device: /dev/dri/card0
12211 14:50:42.200891 Starting subtest: invalid-get-prop-<14>[ 18.840225] [IGT] kms_prop_blob: executing
12212 14:50:42.201011 any
12213 14:50:42.207624 [1mSubtest<14>[ 18.845478] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12214 14:50:42.217474 invalid-get-pro<14>[ 18.853052] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12215 14:50:42.224213 p-any: SUCCESS (<14>[ 18.861814] [IGT] kms_prop_blob: exiting, ret=0
12216 14:50:42.224334 0.000s)[0m
12217 14:50:42.230679 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12218 14:50:42.237108 <8>[ 18.874430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12219 14:50:42.237225
12220 14:50:42.237473 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12222 14:50:42.243822 Using IGT_SRANDOM=1717512642 for randomisation
12223 14:50:42.243934 Opened device: /dev/dri/card0
12224 14:50:42.247150 Starting subtest: invalid-get-prop
12225 14:50:42.253496 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12226 14:50:42.266099 <14>[ 18.905633] [IGT] kms_prop_blob: executing
12227 14:50:42.276267 IGT-Version: 1.2<14>[ 18.910963] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12228 14:50:42.282868 8-ga44ebfe (aarc<14>[ 18.919077] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12229 14:50:42.289554 h64) (Linux: 6.1<14>[ 18.928133] [IGT] kms_prop_blob: exiting, ret=0
12230 14:50:42.292988 .91-cip21 aarch64)
12231 14:50:42.296295 Using IGT_SRANDOM=1717512642 for randomisation
12232 14:50:42.305891 Opened devic<8>[ 18.940936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12233 14:50:42.306016 e: /dev/dri/card0
12234 14:50:42.306263 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12236 14:50:42.309324 Starting subtest: invalid-set-prop-any
12237 14:50:42.315740 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12238 14:50:42.332040 <14>[ 18.971283] [IGT] kms_prop_blob: executing
12239 14:50:42.338685 IGT-Version: 1.2<14>[ 18.976377] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12240 14:50:42.348728 8-ga44ebfe (aarc<14>[ 18.984015] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12241 14:50:42.355473 h64) (Linux: 6.1<14>[ 18.992779] [IGT] kms_prop_blob: exiting, ret=0
12242 14:50:42.355613 .91-cip21 aarch64)
12243 14:50:42.362106 Using IGT_SRANDOM=1717512642 for randomisation
12244 14:50:42.371815 Opened device: /dev/dri/card<8>[ 19.006038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12245 14:50:42.371998 0
12246 14:50:42.372306 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12248 14:50:42.374810 Starting subt<8>[ 19.016053] <LAVA_SIGNAL_TESTSET STOP>
12249 14:50:42.375128 Received signal: <TESTSET> STOP
12250 14:50:42.375243 Closing test_set kms_prop_blob
12251 14:50:42.378105 est: invalid-set-prop
12252 14:50:42.381402 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12253 14:50:42.426116 <8>[ 19.065713] <LAVA_SIGNAL_TESTSET START kms_setmode>
12254 14:50:42.426455 Received signal: <TESTSET> START kms_setmode
12255 14:50:42.426530 Starting test_set kms_setmode
12256 14:50:42.445046 <14>[ 19.084273] [IGT] kms_setmode: executing
12257 14:50:42.451656 IGT-Version: 1.2<14>[ 19.089078] [IGT] kms_setmode: starting subtest basic
12258 14:50:42.458275 8-ga44ebfe (aarc<14>[ 19.095678] [IGT] kms_setmode: finished subtest basic, SKIP
12259 14:50:42.464825 h64) (Linux: 6.1<14>[ 19.103152] [IGT] kms_setmode: exiting, ret=77
12260 14:50:42.468078 .91-cip21 aarch64)
12261 14:50:42.478353 Using IGT_SRANDOM=1717512642 for randomisati<8>[ 19.114503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12262 14:50:42.478516 on
12263 14:50:42.478800 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12265 14:50:42.481703 Opened device: /dev/dri/card0
12266 14:50:42.481783 Starting subtest: basic
12267 14:50:42.484973 No dynamic tests executed.
12268 14:50:42.488135 [1mSubtest basic: SKIP (0.000s)[0m
12269 14:50:42.495099 <14>[ 19.134429] [IGT] kms_setmode: executing
12270 14:50:42.501955 IGT-Version: 1.2<14>[ 19.139136] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12271 14:50:42.511488 8-ga44ebfe (aarc<14>[ 19.147251] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12272 14:50:42.518592 h64) (Linux: 6.1<14>[ 19.156218] [IGT] kms_setmode: exiting, ret=77
12273 14:50:42.518719 .91-cip21 aarch64)
12274 14:50:42.531293 Using IGT_SRANDOM=1717512642 for randomisati<8>[ 19.167573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12275 14:50:42.531431 on
12276 14:50:42.531675 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12278 14:50:42.534470 Opened device: /dev/dri/card0
12279 14:50:42.538395 Starting subtest: basic-clone-single-crtc
12280 14:50:42.541602 No dynamic tests executed.
12281 14:50:42.551652 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m<14>[ 19.189720] [IGT] kms_setmode: executing
12282 14:50:42.551782
12283 14:50:42.558163 IGT-Version: 1.2<14>[ 19.194483] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12284 14:50:42.567667 8-ga44ebfe (aarc<14>[ 19.202885] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12285 14:50:42.574612 h64) (Linux: 6.1<14>[ 19.211996] [IGT] kms_setmode: exiting, ret=77
12286 14:50:42.574733 .91-cip21 aarch64)
12287 14:50:42.580928 Using IGT_SRANDOM=1717512642 for randomisation
12288 14:50:42.587593 Opened devic<8>[ 19.224397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12289 14:50:42.587895 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12291 14:50:42.590878 e: /dev/dri/card0
12292 14:50:42.594559 Starting subtest: invalid-clone-single-crtc
12293 14:50:42.597565 No dynamic tests executed.
12294 14:50:42.600807 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12295 14:50:42.615996 <14>[ 19.255469] [IGT] kms_setmode: executing
12296 14:50:42.625902 IGT-Version: 1.2<14>[ 19.260606] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12297 14:50:42.632615 8-ga44ebfe (aarc<14>[ 19.269016] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12298 14:50:42.639511 h64) (Linux: 6.1<14>[ 19.278368] [IGT] kms_setmode: exiting, ret=77
12299 14:50:42.642839 .91-cip21 aarch64)
12300 14:50:42.646105 Using IGT_SRANDOM=1717512642 for randomisation
12301 14:50:42.655686 Opened devic<8>[ 19.291366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12302 14:50:42.655853 e: /dev/dri/card0
12303 14:50:42.656126 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12305 14:50:42.662359 Starting subtest: invalid-clone-exclusive-crtc
12306 14:50:42.662451 No dynamic tests executed.
12307 14:50:42.668935 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12308 14:50:42.672385 <14>[ 19.313782] [IGT] kms_setmode: executing
12309 14:50:42.682439 IGT-Version: 1.2<14>[ 19.318518] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12310 14:50:42.692402 8-ga44ebfe (aarc<14>[ 19.326422] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12311 14:50:42.695365 h64) (Linux: 6.1<14>[ 19.335201] [IGT] kms_setmode: exiting, ret=77
12312 14:50:42.698721 .91-cip21 aarch64)
12313 14:50:42.702414 Using IGT_SRANDOM=1717512642 for randomisation
12314 14:50:42.712124 Opened devic<8>[ 19.347498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12315 14:50:42.712281 e: /dev/dri/card0
12316 14:50:42.712571 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12318 14:50:42.715048 Starting subtest: clone-exclusive-crtc
12319 14:50:42.718755 No dynamic tests executed.
12320 14:50:42.725119 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12321 14:50:42.728411 <14>[ 19.368458] [IGT] kms_setmode: executing
12322 14:50:42.738453 IGT-Version: 1.2<14>[ 19.373116] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12323 14:50:42.748306 8-ga44ebfe (aarc<14>[ 19.382407] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12324 14:50:42.754856 h64) (Linux: 6.1<14>[ 19.392079] [IGT] kms_setmode: exiting, ret=77
12325 14:50:42.754990 .91-cip21 aarch64)
12326 14:50:42.761297 Using IGT_SRANDOM=1717512642 for randomisation
12327 14:50:42.768392 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12329 14:50:42.771398 Opened devic<8>[ 19.404506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12330 14:50:42.771478 e: /dev/dri/card0
12331 14:50:42.778013 Starting subt<8>[ 19.415763] <LAVA_SIGNAL_TESTSET STOP>
12332 14:50:42.778319 Received signal: <TESTSET> STOP
12333 14:50:42.778391 Closing test_set kms_setmode
12334 14:50:42.781053 est: invalid-clone-single-crtc-stealing
12335 14:50:42.781137 No dynamic tests executed.
12336 14:50:42.787649 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12337 14:50:42.808816 <8>[ 19.447882] <LAVA_SIGNAL_TESTSET START kms_vblank>
12338 14:50:42.809150 Received signal: <TESTSET> START kms_vblank
12339 14:50:42.809231 Starting test_set kms_vblank
12340 14:50:42.835718 <14>[ 19.475007] [IGT] kms_vblank: executing
12341 14:50:42.842490 IGT-Version: 1.2<14>[ 19.480041] [IGT] kms_vblank: exiting, ret=77
12342 14:50:42.845496 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12343 14:50:42.855428 Using IGT_SRANDOM=1717512642<8>[ 19.491269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12344 14:50:42.855616 for randomisation
12345 14:50:42.855931 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12347 14:50:42.858747 Opened device: /dev/dri/card0
12348 14:50:42.862385 No KMS driver or no outputs, pipes: 16, outputs: 0
12349 14:50:42.868803 [1mSubtest invalid: SKIP (0.000s)[0m
12350 14:50:42.872030 <14>[ 19.513305] [IGT] kms_vblank: executing
12351 14:50:42.878939 IGT-Version: 1.2<14>[ 19.517924] [IGT] kms_vblank: exiting, ret=77
12352 14:50:42.885293 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12353 14:50:42.892064 Using IGT_SRANDOM=1717512642<8>[ 19.529408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12354 14:50:42.892380 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12356 14:50:42.895201 for randomisation
12357 14:50:42.898301 Opened device: /dev/dri/card0
12358 14:50:42.901863 No KMS driver or no outputs, pipes: 16, outputs: 0
12359 14:50:42.904974 [1mSubtest crtc-id: SKIP (0.000s)[0m
12360 14:50:42.913905 <14>[ 19.553373] [IGT] kms_vblank: executing
12361 14:50:42.920944 IGT-Version: 1.2<14>[ 19.558013] [IGT] kms_vblank: exiting, ret=77
12362 14:50:42.923550 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12363 14:50:42.933740 Using IGT_SRANDOM=1717512642<8>[ 19.570527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12364 14:50:42.933943 for randomisation
12365 14:50:42.934249 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12367 14:50:42.937002 Opened device: /dev/dri/card0
12368 14:50:42.943826 No KMS driver or no outputs, pipes: 16, outputs: 0
12369 14:50:42.946633 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12370 14:50:42.960660 <14>[ 19.599996] [IGT] kms_vblank: executing
12371 14:50:42.967147 IGT-Version: 1.2<14>[ 19.605042] [IGT] kms_vblank: exiting, ret=77
12372 14:50:42.970456 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12373 14:50:42.980234 Using IGT_SRANDOM=1717512642 for randomisati<8>[ 19.618114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12374 14:50:42.980409 on
12375 14:50:42.980694 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12377 14:50:42.983673 Opened device: /dev/dri/card0
12378 14:50:42.990111 No KMS driver or no outputs, pipes: 16, outputs: 0
12379 14:50:42.993871 [1mSubtest query-idle: SKIP (0.000s)[0m
12380 14:50:43.010968 <14>[ 19.650308] [IGT] kms_vblank: executing
12381 14:50:43.017318 IGT-Version: 1.2<14>[ 19.655227] [IGT] kms_vblank: exiting, ret=77
12382 14:50:43.020647 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12383 14:50:43.023992 Using IGT_SRANDOM=1717512643 for randomisation
12384 14:50:43.034430 Opened device: /dev/dri/card<8>[ 19.671371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12385 14:50:43.034575 0
12386 14:50:43.034825 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12388 14:50:43.040516 No KMS driver or no outputs, pipes: 16, outputs: 0
12389 14:50:43.043887 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12390 14:50:43.063578 <14>[ 19.702782] [IGT] kms_vblank: executing
12391 14:50:43.069954 IGT-Version: 1.2<14>[ 19.707817] [IGT] kms_vblank: exiting, ret=77
12392 14:50:43.073438 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12393 14:50:43.083093 Using IGT_SRANDOM=1717512643<8>[ 19.719542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12394 14:50:43.083228 for randomisation
12395 14:50:43.083474 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12397 14:50:43.086843 Opened device: /dev/dri/card0
12398 14:50:43.093143 No KMS driver or no outputs, pipes: 16, outputs: 0
12399 14:50:43.096541 [1mSubtest query-forked: SKIP (0.000s)[0m
12400 14:50:43.110347 <14>[ 19.749969] [IGT] kms_vblank: executing
12401 14:50:43.117298 IGT-Version: 1.2<14>[ 19.754977] [IGT] kms_vblank: exiting, ret=77
12402 14:50:43.120711 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12403 14:50:43.130287 Using IGT_SRANDOM=1717512643<8>[ 19.767158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12404 14:50:43.130631 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12406 14:50:43.133695 for randomisation
12407 14:50:43.133787 Opened device: /dev/dri/card0
12408 14:50:43.140430 No KMS driver or no outputs, pipes: 16, outputs: 0
12409 14:50:43.143682 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12410 14:50:43.146791 <14>[ 19.788847] [IGT] kms_vblank: executing
12411 14:50:43.153797 IGT-Version: 1.2<14>[ 19.793468] [IGT] kms_vblank: exiting, ret=77
12412 14:50:43.160144 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12413 14:50:43.163396 Using IGT_SRANDOM=1717512643 for randomisation
12414 14:50:43.170081 Opened devic<8>[ 19.808665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12415 14:50:43.170477 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12417 14:50:43.173801 e: /dev/dri/card0
12418 14:50:43.177126 No KMS driver or no outputs, pipes: 16, outputs: 0
12419 14:50:43.180292 [1mSubtest query-busy: SKIP (0.000s)[0m
12420 14:50:43.190638 <14>[ 19.829818] [IGT] kms_vblank: executing
12421 14:50:43.197218 IGT-Version: 1.2<14>[ 19.834459] [IGT] kms_vblank: exiting, ret=77
12422 14:50:43.200199 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12423 14:50:43.210160 Using IGT_SRANDOM=1717512643<8>[ 19.846687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12424 14:50:43.210327 for randomisation
12425 14:50:43.210609 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12427 14:50:43.213707 Opened device: /dev/dri/card0
12428 14:50:43.219916 No KMS driver or no outputs, pipes: 16, outputs: 0
12429 14:50:43.223352 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12430 14:50:43.238453 <14>[ 19.877884] [IGT] kms_vblank: executing
12431 14:50:43.245135 IGT-Version: 1.2<14>[ 19.882691] [IGT] kms_vblank: exiting, ret=77
12432 14:50:43.248412 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12433 14:50:43.258690 Using IGT_SRANDOM=1717512643 for randomisati<8>[ 19.896581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12434 14:50:43.259046 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12436 14:50:43.261517 on
12437 14:50:43.261602 Opened device: /dev/dri/card0
12438 14:50:43.267974 No KMS driver or no outputs, pipes: 16, outputs: 0
12439 14:50:43.271306 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12440 14:50:43.279145 <14>[ 19.918565] [IGT] kms_vblank: executing
12441 14:50:43.286015 IGT-Version: 1.2<14>[ 19.923308] [IGT] kms_vblank: exiting, ret=77
12442 14:50:43.289242 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12443 14:50:43.298911 Using IGT_SRANDOM=1717512643<8>[ 19.934813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12444 14:50:43.299225 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12446 14:50:43.302080 for randomisation
12447 14:50:43.305737 Opened device: /dev/dri/card0
12448 14:50:43.308786 No KMS driver or no outputs, pipes: 16, outputs: 0
12449 14:50:43.312370 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12450 14:50:43.326976 <14>[ 19.966371] [IGT] kms_vblank: executing
12451 14:50:43.333898 IGT-Version: 1.2<14>[ 19.971370] [IGT] kms_vblank: exiting, ret=77
12452 14:50:43.336862 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12453 14:50:43.340377 Using IGT_SRANDOM=1717512643 for randomisation
12454 14:50:43.350107 Opened devic<8>[ 19.986592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12455 14:50:43.350226 e: /dev/dri/card0
12456 14:50:43.350468 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12458 14:50:43.356532 No KMS driver or no outputs, pipes: 16, outputs: 0
12459 14:50:43.359870 [1mSubtest wait-idle: SKIP (0.000s)[0m
12460 14:50:43.378741 <14>[ 20.018052] [IGT] kms_vblank: executing
12461 14:50:43.385017 IGT-Version: 1.2<14>[ 20.023049] [IGT] kms_vblank: exiting, ret=77
12462 14:50:43.388683 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12463 14:50:43.391878 Using IGT_SRANDOM=1717512643 for randomisation
12464 14:50:43.401896 Opened device: /dev/dri/card<8>[ 20.038959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12465 14:50:43.402029 0
12466 14:50:43.402266 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12468 14:50:43.408372 No KMS driver or no outputs, pipes: 16, outputs: 0
12469 14:50:43.411949 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12470 14:50:43.432070 <14>[ 20.071167] [IGT] kms_vblank: executing
12471 14:50:43.438494 IGT-Version: 1.2<14>[ 20.076211] [IGT] kms_vblank: exiting, ret=77
12472 14:50:43.442056 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12473 14:50:43.452195 Using IGT_SRANDOM=1717512643 for randomisati<8>[ 20.089829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12474 14:50:43.452365 on
12475 14:50:43.452644 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12477 14:50:43.454825 Opened device: /dev/dri/card0
12478 14:50:43.461906 No KMS driver or no outputs, pipes: 16, outputs: 0
12479 14:50:43.464921 [1mSubtest wait-forked: SKIP (0.000s)[0m
12480 14:50:43.472774 <14>[ 20.112207] [IGT] kms_vblank: executing
12481 14:50:43.479747 IGT-Version: 1.2<14>[ 20.117035] [IGT] kms_vblank: exiting, ret=77
12482 14:50:43.482894 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12483 14:50:43.492541 Using IGT_SRANDOM=1717512643<8>[ 20.129467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12484 14:50:43.492869 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12486 14:50:43.495713 for randomisation
12487 14:50:43.495826 Opened device: /dev/dri/card0
12488 14:50:43.502470 No KMS driver or no outputs, pipes: 16, outputs: 0
12489 14:50:43.506047 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12490 14:50:43.513334 <14>[ 20.153057] [IGT] kms_vblank: executing
12491 14:50:43.520415 IGT-Version: 1.2<14>[ 20.157701] [IGT] kms_vblank: exiting, ret=77
12492 14:50:43.523515 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12493 14:50:43.533673 Using IGT_SRANDOM=1717512643 for randomisati<8>[ 20.171084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12494 14:50:43.533812 on
12495 14:50:43.534058 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12497 14:50:43.537042 Opened device: /dev/dri/card0
12498 14:50:43.543453 No KMS driver or no outputs, pipes: 16, outputs: 0
12499 14:50:43.546820 [1mSubtest wait-busy: SKIP (0.000s)[0m
12500 14:50:43.553212 <14>[ 20.191946] [IGT] kms_vblank: executing
12501 14:50:43.556846 IGT-Version: 1.2<14>[ 20.196804] [IGT] kms_vblank: exiting, ret=77
12502 14:50:43.563956 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12503 14:50:43.573261 Using IGT_SRANDOM=1717512643 for randomisati<8>[ 20.210009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12504 14:50:43.573395 on
12505 14:50:43.573646 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12507 14:50:43.576302 Opened device: /dev/dri/card0
12508 14:50:43.579908 No KMS driver or no outputs, pipes: 16, outputs: 0
12509 14:50:43.586407 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12510 14:50:43.600620 <14>[ 20.240040] [IGT] kms_vblank: executing
12511 14:50:43.607408 IGT-Version: 1.2<14>[ 20.245131] [IGT] kms_vblank: exiting, ret=77
12512 14:50:43.610776 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12513 14:50:43.620257 Using IGT_SR<8>[ 20.256222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12514 14:50:43.620604 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12516 14:50:43.623849 ANDOM=1717512643 for randomisation
12517 14:50:43.623938 Opened device: /dev/dri/card0
12518 14:50:43.630247 No KMS driver or no outputs, pipes: 16, outputs: 0
12519 14:50:43.637085 [1mSubtest wait-forked-busy: SKIP (0.000<14>[ 20.277152] [IGT] kms_vblank: executing
12520 14:50:43.637201 s)[0m
12521 14:50:43.643366 <14>[ 20.282272] [IGT] kms_vblank: exiting, ret=77
12522 14:50:43.650054 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12523 14:50:43.659985 Using IGT_SRANDOM=1717512643<8>[ 20.294917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12524 14:50:43.660124 for randomisation
12525 14:50:43.660400 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12527 14:50:43.663333 Opened device: /dev/dri/card0
12528 14:50:43.666554 No KMS driver or no outputs, pipes: 16, outputs: 0
12529 14:50:43.672951 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12530 14:50:43.686973 <14>[ 20.325960] [IGT] kms_vblank: executing
12531 14:50:43.692905 IGT-Version: 1.2<14>[ 20.330951] [IGT] kms_vblank: exiting, ret=77
12532 14:50:43.696166 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12533 14:50:43.706323 Using IGT_SRANDOM=1717512643<8>[ 20.342600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12534 14:50:43.706646 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12536 14:50:43.709472 for randomisation
12537 14:50:43.709565 Opened device: /dev/dri/card0
12538 14:50:43.716489 No KMS driver or no outputs, pipes: 16, outputs: 0
12539 14:50:43.719872 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12540 14:50:43.733939 <14>[ 20.373489] [IGT] kms_vblank: executing
12541 14:50:43.740912 IGT-Version: 1.2<14>[ 20.378462] [IGT] kms_vblank: exiting, ret=77
12542 14:50:43.743838 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12543 14:50:43.753672 Using IGT_SRANDOM=1717512643<8>[ 20.390028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12544 14:50:43.753988 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12546 14:50:43.757511 for randomisation
12547 14:50:43.760677 Opened device: /dev/dri/card0
12548 14:50:43.764060 No KMS driver or no outputs, pipes: 16, outputs: 0
12549 14:50:43.766967 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12550 14:50:43.782505 <14>[ 20.421932] [IGT] kms_vblank: executing
12551 14:50:43.789115 IGT-Version: 1.2<14>[ 20.426848] [IGT] kms_vblank: exiting, ret=77
12552 14:50:43.792187 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12553 14:50:43.802489 Using IGT_SRANDOM=1717512643<8>[ 20.438341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12554 14:50:43.802809 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12556 14:50:43.805552 for randomisation
12557 14:50:43.808830 Opened device: /dev/dri/card0
12558 14:50:43.812207 No KMS driver or no outputs, pipes: 16, outputs: 0
12559 14:50:43.815844 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12560 14:50:43.830663 <14>[ 20.470000] [IGT] kms_vblank: executing
12561 14:50:43.837495 IGT-Version: 1.2<14>[ 20.475045] [IGT] kms_vblank: exiting, ret=77
12562 14:50:43.840773 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12563 14:50:43.850405 Using IGT_SRANDOM=1717512643<8>[ 20.486993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12564 14:50:43.850717 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12566 14:50:43.853988 for randomisation
12567 14:50:43.856772 Opened device: /dev/dri/card0
12568 14:50:43.860015 No KMS driver or no outputs, pipes: 16, outputs: 0
12569 14:50:43.866927 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12570 14:50:43.878809 <14>[ 20.518460] [IGT] kms_vblank: executing
12571 14:50:43.886068 IGT-Version: 1.2<14>[ 20.523410] [IGT] kms_vblank: exiting, ret=77
12572 14:50:43.888833 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12573 14:50:43.892295 Using IGT_SRANDOM=1717512643 for randomisation
12574 14:50:43.902159 Opened devic<8>[ 20.538458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12575 14:50:43.902301 e: /dev/dri/card0
12576 14:50:43.902573 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12578 14:50:43.909118 No KMS driver or no outputs, pipes: 16, outputs: 0
12579 14:50:43.912538 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12580 14:50:43.922073 <14>[ 20.560970] [IGT] kms_vblank: executing
12581 14:50:43.928327 IGT-Version: 1.2<14>[ 20.565609] [IGT] kms_vblank: exiting, ret=77
12582 14:50:43.931359 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12583 14:50:43.941229 Using IGT_SRANDOM=1717512643<8>[ 20.577866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12584 14:50:43.941602 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12586 14:50:43.944620 for randomisation
12587 14:50:43.947882 Opened device: /dev/dri/card0
12588 14:50:43.951117 No KMS driver or no outputs, pipes: 16, outputs: 0
12589 14:50:43.954724 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12590 14:50:43.961069 <14>[ 20.599543] [IGT] kms_vblank: executing
12591 14:50:43.967791 IGT-Version: 1.2<14>[ 20.604874] [IGT] kms_vblank: exiting, ret=77
12592 14:50:43.970878 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12593 14:50:43.981015 Using IGT_SRANDOM=1717512643<8>[ 20.616872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12594 14:50:43.981323 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12596 14:50:43.984224 for randomisation
12597 14:50:43.987467 Opened device: /dev/dri/card0
12598 14:50:43.990669 No KMS driver or no outputs, pipes: 16, outputs: 0
12599 14:50:43.994217 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12600 14:50:44.000917 <14>[ 20.640072] [IGT] kms_vblank: executing
12601 14:50:44.007887 IGT-Version: 1.2<14>[ 20.644913] [IGT] kms_vblank: exiting, ret=77
12602 14:50:44.010948 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12603 14:50:44.020793 Using IGT_SRANDOM=1717512643<8>[ 20.656900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12604 14:50:44.021118 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12606 14:50:44.024275 for randomisation
12607 14:50:44.027056 Opened devic<8>[ 20.667667] <LAVA_SIGNAL_TESTSET STOP>
12608 14:50:44.027341 Received signal: <TESTSET> STOP
12609 14:50:44.027434 Closing test_set kms_vblank
12610 14:50:44.037037 e: /dev/dri/card<8>[ 20.673563] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14167057_1.5.2.3.1>
12611 14:50:44.037172 0
12612 14:50:44.037414 Received signal: <ENDRUN> 0_igt-kms-mediatek 14167057_1.5.2.3.1
12613 14:50:44.037494 Ending use of test pattern.
12614 14:50:44.037554 Ending test lava.0_igt-kms-mediatek (14167057_1.5.2.3.1), duration 6.68
12616 14:50:44.040264 No KMS driver or no outputs, pipes: 16, outputs: 0
12617 14:50:44.047297 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12618 14:50:44.047394 + set +x
12619 14:50:44.050364 <LAVA_TEST_RUNNER EXIT>
12620 14:50:44.050635 ok: lava_test_shell seems to have completed
12621 14:50:44.052206 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12622 14:50:44.052360 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12623 14:50:44.052446 end: 3 lava-test-retry (duration 00:00:07) [common]
12624 14:50:44.052537 start: 4 finalize (timeout 00:07:07) [common]
12625 14:50:44.052683 start: 4.1 power-off (timeout 00:00:30) [common]
12626 14:50:44.052837 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
12627 14:50:44.129532 >> Command sent successfully.
12628 14:50:44.132028 Returned 0 in 0 seconds
12629 14:50:44.232468 end: 4.1 power-off (duration 00:00:00) [common]
12631 14:50:44.232884 start: 4.2 read-feedback (timeout 00:07:07) [common]
12632 14:50:44.233257 Listened to connection for namespace 'common' for up to 1s
12633 14:50:45.234111 Finalising connection for namespace 'common'
12634 14:50:45.234398 Disconnecting from shell: Finalise
12635 14:50:45.234532 / #
12636 14:50:45.334868 end: 4.2 read-feedback (duration 00:00:01) [common]
12637 14:50:45.335049 end: 4 finalize (duration 00:00:01) [common]
12638 14:50:45.335162 Cleaning after the job
12639 14:50:45.335286 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/ramdisk
12640 14:50:45.342806 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/kernel
12641 14:50:45.358800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/dtb
12642 14:50:45.359038 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167057/tftp-deploy-88w71y31/modules
12643 14:50:45.364927 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167057
12644 14:50:45.477831 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167057
12645 14:50:45.478013 Job finished correctly