Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 14:42:24.949715 lava-dispatcher, installed at version: 2024.03
2 14:42:24.949933 start: 0 validate
3 14:42:24.950068 Start time: 2024-06-04 14:42:24.950059+00:00 (UTC)
4 14:42:24.950210 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:42:24.950345 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:42:25.211637 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:42:25.211816 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:42:25.469155 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:42:25.469338 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:43:04.260307 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:04.261188 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:43:04.773856 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:43:04.774560 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:43:05.047496 validate duration: 40.10
16 14:43:05.048678 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:43:05.049199 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:43:05.049630 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:43:05.050218 Not decompressing ramdisk as can be used compressed.
20 14:43:05.050680 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:43:05.051024 saving as /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/ramdisk/initrd.cpio.gz
22 14:43:05.051454 total size: 5628169 (5 MB)
23 14:43:07.719912 progress 0 % (0 MB)
24 14:43:07.724767 progress 5 % (0 MB)
25 14:43:07.726381 progress 10 % (0 MB)
26 14:43:07.727783 progress 15 % (0 MB)
27 14:43:07.729313 progress 20 % (1 MB)
28 14:43:07.730744 progress 25 % (1 MB)
29 14:43:07.732269 progress 30 % (1 MB)
30 14:43:07.733794 progress 35 % (1 MB)
31 14:43:07.735207 progress 40 % (2 MB)
32 14:43:07.736766 progress 45 % (2 MB)
33 14:43:07.738139 progress 50 % (2 MB)
34 14:43:07.739704 progress 55 % (2 MB)
35 14:43:07.741226 progress 60 % (3 MB)
36 14:43:07.742621 progress 65 % (3 MB)
37 14:43:07.744143 progress 70 % (3 MB)
38 14:43:07.745491 progress 75 % (4 MB)
39 14:43:07.747128 progress 80 % (4 MB)
40 14:43:07.748484 progress 85 % (4 MB)
41 14:43:07.750013 progress 90 % (4 MB)
42 14:43:07.751571 progress 95 % (5 MB)
43 14:43:07.752940 progress 100 % (5 MB)
44 14:43:07.753143 5 MB downloaded in 2.70 s (1.99 MB/s)
45 14:43:07.753292 end: 1.1.1 http-download (duration 00:00:03) [common]
47 14:43:07.753533 end: 1.1 download-retry (duration 00:00:03) [common]
48 14:43:07.753619 start: 1.2 download-retry (timeout 00:09:57) [common]
49 14:43:07.753703 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 14:43:07.753839 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:43:07.753910 saving as /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/kernel/Image
52 14:43:07.753971 total size: 54682112 (52 MB)
53 14:43:07.754032 No compression specified
54 14:43:07.755217 progress 0 % (0 MB)
55 14:43:07.768909 progress 5 % (2 MB)
56 14:43:07.782698 progress 10 % (5 MB)
57 14:43:07.796595 progress 15 % (7 MB)
58 14:43:07.810348 progress 20 % (10 MB)
59 14:43:07.824453 progress 25 % (13 MB)
60 14:43:07.838449 progress 30 % (15 MB)
61 14:43:07.852580 progress 35 % (18 MB)
62 14:43:07.866410 progress 40 % (20 MB)
63 14:43:07.880299 progress 45 % (23 MB)
64 14:43:07.894252 progress 50 % (26 MB)
65 14:43:07.908086 progress 55 % (28 MB)
66 14:43:07.922261 progress 60 % (31 MB)
67 14:43:07.936282 progress 65 % (33 MB)
68 14:43:07.950735 progress 70 % (36 MB)
69 14:43:07.964759 progress 75 % (39 MB)
70 14:43:07.978819 progress 80 % (41 MB)
71 14:43:07.992827 progress 85 % (44 MB)
72 14:43:08.006762 progress 90 % (46 MB)
73 14:43:08.020534 progress 95 % (49 MB)
74 14:43:08.034253 progress 100 % (52 MB)
75 14:43:08.034489 52 MB downloaded in 0.28 s (185.90 MB/s)
76 14:43:08.034640 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:43:08.034871 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:43:08.034957 start: 1.3 download-retry (timeout 00:09:57) [common]
80 14:43:08.035040 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 14:43:08.035172 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:43:08.035241 saving as /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/dtb/mt8192-asurada-spherion-r0.dtb
83 14:43:08.035302 total size: 47258 (0 MB)
84 14:43:08.035363 No compression specified
85 14:43:08.036502 progress 69 % (0 MB)
86 14:43:08.036797 progress 100 % (0 MB)
87 14:43:08.036950 0 MB downloaded in 0.00 s (27.38 MB/s)
88 14:43:08.037072 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:43:08.037296 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:43:08.037382 start: 1.4 download-retry (timeout 00:09:57) [common]
92 14:43:08.037465 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 14:43:08.037575 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:43:08.037643 saving as /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/nfsrootfs/full.rootfs.tar
95 14:43:08.037704 total size: 120894716 (115 MB)
96 14:43:08.037765 Using unxz to decompress xz
97 14:43:08.046626 progress 0 % (0 MB)
98 14:43:08.402405 progress 5 % (5 MB)
99 14:43:08.773091 progress 10 % (11 MB)
100 14:43:09.137476 progress 15 % (17 MB)
101 14:43:09.478472 progress 20 % (23 MB)
102 14:43:09.778623 progress 25 % (28 MB)
103 14:43:10.142871 progress 30 % (34 MB)
104 14:43:10.489861 progress 35 % (40 MB)
105 14:43:10.664378 progress 40 % (46 MB)
106 14:43:10.854600 progress 45 % (51 MB)
107 14:43:11.181616 progress 50 % (57 MB)
108 14:43:11.589567 progress 55 % (63 MB)
109 14:43:11.961492 progress 60 % (69 MB)
110 14:43:12.333172 progress 65 % (74 MB)
111 14:43:12.708566 progress 70 % (80 MB)
112 14:43:13.091903 progress 75 % (86 MB)
113 14:43:13.444138 progress 80 % (92 MB)
114 14:43:13.791059 progress 85 % (98 MB)
115 14:43:14.156510 progress 90 % (103 MB)
116 14:43:14.493292 progress 95 % (109 MB)
117 14:43:14.858433 progress 100 % (115 MB)
118 14:43:14.864333 115 MB downloaded in 6.83 s (16.89 MB/s)
119 14:43:14.864701 end: 1.4.1 http-download (duration 00:00:07) [common]
121 14:43:14.864973 end: 1.4 download-retry (duration 00:00:07) [common]
122 14:43:14.865067 start: 1.5 download-retry (timeout 00:09:50) [common]
123 14:43:14.865152 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 14:43:14.865335 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:43:14.865408 saving as /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/modules/modules.tar
126 14:43:14.865469 total size: 8608920 (8 MB)
127 14:43:14.865534 Using unxz to decompress xz
128 14:43:14.869635 progress 0 % (0 MB)
129 14:43:14.888651 progress 5 % (0 MB)
130 14:43:14.916059 progress 10 % (0 MB)
131 14:43:14.946912 progress 15 % (1 MB)
132 14:43:14.970812 progress 20 % (1 MB)
133 14:43:14.995397 progress 25 % (2 MB)
134 14:43:15.019585 progress 30 % (2 MB)
135 14:43:15.044291 progress 35 % (2 MB)
136 14:43:15.071842 progress 40 % (3 MB)
137 14:43:15.095504 progress 45 % (3 MB)
138 14:43:15.121241 progress 50 % (4 MB)
139 14:43:15.148211 progress 55 % (4 MB)
140 14:43:15.174315 progress 60 % (4 MB)
141 14:43:15.198750 progress 65 % (5 MB)
142 14:43:15.224353 progress 70 % (5 MB)
143 14:43:15.250757 progress 75 % (6 MB)
144 14:43:15.277176 progress 80 % (6 MB)
145 14:43:15.301704 progress 85 % (7 MB)
146 14:43:15.328202 progress 90 % (7 MB)
147 14:43:15.355074 progress 95 % (7 MB)
148 14:43:15.382088 progress 100 % (8 MB)
149 14:43:15.387775 8 MB downloaded in 0.52 s (15.72 MB/s)
150 14:43:15.388031 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:43:15.388297 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:43:15.388393 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 14:43:15.388487 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 14:43:18.939850 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b
156 14:43:18.940105 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 14:43:18.940248 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 14:43:18.940508 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c
159 14:43:18.940683 makedir: /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin
160 14:43:18.940817 makedir: /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/tests
161 14:43:18.940949 makedir: /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/results
162 14:43:18.941083 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-add-keys
163 14:43:18.941318 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-add-sources
164 14:43:18.941466 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-background-process-start
165 14:43:18.941683 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-background-process-stop
166 14:43:18.941853 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-common-functions
167 14:43:18.942028 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-echo-ipv4
168 14:43:18.942304 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-install-packages
169 14:43:18.942437 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-installed-packages
170 14:43:18.942561 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-os-build
171 14:43:18.942778 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-probe-channel
172 14:43:18.942912 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-probe-ip
173 14:43:18.943095 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-target-ip
174 14:43:18.943325 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-target-mac
175 14:43:18.943473 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-target-storage
176 14:43:18.943646 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-case
177 14:43:18.943833 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-event
178 14:43:18.943983 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-feedback
179 14:43:18.944125 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-raise
180 14:43:18.944308 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-reference
181 14:43:18.944529 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-runner
182 14:43:18.944662 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-set
183 14:43:18.944872 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-test-shell
184 14:43:18.948460 Updating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-add-keys (debian)
185 14:43:18.948979 Updating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-add-sources (debian)
186 14:43:18.949336 Updating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-install-packages (debian)
187 14:43:18.949649 Updating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-installed-packages (debian)
188 14:43:18.949969 Updating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/bin/lava-os-build (debian)
189 14:43:18.950254 Creating /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/environment
190 14:43:18.950396 LAVA metadata
191 14:43:18.950468 - LAVA_JOB_ID=14166996
192 14:43:18.950535 - LAVA_DISPATCHER_IP=192.168.201.1
193 14:43:18.950729 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 14:43:18.950842 skipped lava-vland-overlay
195 14:43:18.950924 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 14:43:18.951040 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 14:43:18.951106 skipped lava-multinode-overlay
198 14:43:18.951199 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 14:43:18.951285 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 14:43:18.951378 Loading test definitions
201 14:43:18.951507 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 14:43:18.951618 Using /lava-14166996 at stage 0
203 14:43:18.952028 uuid=14166996_1.6.2.3.1 testdef=None
204 14:43:18.952139 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 14:43:18.952224 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 14:43:18.952686 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 14:43:18.953046 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 14:43:18.953743 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 14:43:18.954022 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 14:43:18.954930 runner path: /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/0/tests/0_timesync-off test_uuid 14166996_1.6.2.3.1
213 14:43:18.955129 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 14:43:18.955517 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 14:43:18.955628 Using /lava-14166996 at stage 0
217 14:43:18.955799 Fetching tests from https://github.com/kernelci/test-definitions.git
218 14:43:18.955920 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/0/tests/1_kselftest-alsa'
219 14:43:22.648597 Running '/usr/bin/git checkout kernelci.org
220 14:43:22.798834 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 14:43:22.799674 uuid=14166996_1.6.2.3.5 testdef=None
222 14:43:22.799889 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 14:43:22.800251 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 14:43:22.801008 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 14:43:22.801245 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 14:43:22.802280 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 14:43:22.802519 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 14:43:22.803690 runner path: /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/0/tests/1_kselftest-alsa test_uuid 14166996_1.6.2.3.5
232 14:43:22.803783 BOARD='mt8192-asurada-spherion-r0'
233 14:43:22.803848 BRANCH='cip'
234 14:43:22.803908 SKIPFILE='/dev/null'
235 14:43:22.803967 SKIP_INSTALL='True'
236 14:43:22.804023 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 14:43:22.804080 TST_CASENAME=''
238 14:43:22.804135 TST_CMDFILES='alsa'
239 14:43:22.804281 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 14:43:22.804487 Creating lava-test-runner.conf files
242 14:43:22.804550 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14166996/lava-overlay-0_fdeq2c/lava-14166996/0 for stage 0
243 14:43:22.804644 - 0_timesync-off
244 14:43:22.804716 - 1_kselftest-alsa
245 14:43:22.804809 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 14:43:22.804895 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 14:43:30.351922 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 14:43:30.352076 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 14:43:30.352167 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 14:43:30.352269 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 14:43:30.352356 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 14:43:30.520041 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 14:43:30.520420 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 14:43:30.520527 extracting modules file /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b
255 14:43:30.742276 extracting modules file /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166996/extract-overlay-ramdisk-mm1676f_/ramdisk
256 14:43:30.968798 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 14:43:30.968966 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 14:43:30.969063 [common] Applying overlay to NFS
259 14:43:30.969136 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166996/compress-overlay-hmue7w3k/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b
260 14:43:31.906198 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 14:43:31.906375 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 14:43:31.906469 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 14:43:31.906561 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 14:43:31.906640 Building ramdisk /var/lib/lava/dispatcher/tmp/14166996/extract-overlay-ramdisk-mm1676f_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14166996/extract-overlay-ramdisk-mm1676f_/ramdisk
265 14:43:32.225763 >> 130335 blocks
266 14:43:34.274895 rename /var/lib/lava/dispatcher/tmp/14166996/extract-overlay-ramdisk-mm1676f_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/ramdisk/ramdisk.cpio.gz
267 14:43:34.275370 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 14:43:34.275517 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 14:43:34.275647 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 14:43:34.275785 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/kernel/Image']
271 14:43:48.236621 Returned 0 in 13 seconds
272 14:43:48.337630 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/kernel/image.itb
273 14:43:48.729063 output: FIT description: Kernel Image image with one or more FDT blobs
274 14:43:48.729460 output: Created: Tue Jun 4 15:43:48 2024
275 14:43:48.729557 output: Image 0 (kernel-1)
276 14:43:48.729625 output: Description:
277 14:43:48.729687 output: Created: Tue Jun 4 15:43:48 2024
278 14:43:48.729747 output: Type: Kernel Image
279 14:43:48.729810 output: Compression: lzma compressed
280 14:43:48.729873 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
281 14:43:48.729932 output: Architecture: AArch64
282 14:43:48.729990 output: OS: Linux
283 14:43:48.730050 output: Load Address: 0x00000000
284 14:43:48.730137 output: Entry Point: 0x00000000
285 14:43:48.730267 output: Hash algo: crc32
286 14:43:48.730352 output: Hash value: 88dcd836
287 14:43:48.730437 output: Image 1 (fdt-1)
288 14:43:48.730510 output: Description: mt8192-asurada-spherion-r0
289 14:43:48.730567 output: Created: Tue Jun 4 15:43:48 2024
290 14:43:48.730636 output: Type: Flat Device Tree
291 14:43:48.730719 output: Compression: uncompressed
292 14:43:48.730800 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 14:43:48.730882 output: Architecture: AArch64
294 14:43:48.730963 output: Hash algo: crc32
295 14:43:48.731044 output: Hash value: 0f8e4d2e
296 14:43:48.731124 output: Image 2 (ramdisk-1)
297 14:43:48.731200 output: Description: unavailable
298 14:43:48.731283 output: Created: Tue Jun 4 15:43:48 2024
299 14:43:48.731364 output: Type: RAMDisk Image
300 14:43:48.731445 output: Compression: Unknown Compression
301 14:43:48.731527 output: Data Size: 18733849 Bytes = 18294.77 KiB = 17.87 MiB
302 14:43:48.731608 output: Architecture: AArch64
303 14:43:48.731673 output: OS: Linux
304 14:43:48.731727 output: Load Address: unavailable
305 14:43:48.731780 output: Entry Point: unavailable
306 14:43:48.731832 output: Hash algo: crc32
307 14:43:48.731884 output: Hash value: 842862cb
308 14:43:48.731936 output: Default Configuration: 'conf-1'
309 14:43:48.731988 output: Configuration 0 (conf-1)
310 14:43:48.732040 output: Description: mt8192-asurada-spherion-r0
311 14:43:48.732093 output: Kernel: kernel-1
312 14:43:48.732145 output: Init Ramdisk: ramdisk-1
313 14:43:48.732205 output: FDT: fdt-1
314 14:43:48.732259 output: Loadables: kernel-1
315 14:43:48.732314 output:
316 14:43:48.732513 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 14:43:48.732614 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 14:43:48.732726 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 14:43:48.732822 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 14:43:48.732903 No LXC device requested
321 14:43:48.732981 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 14:43:48.733065 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 14:43:48.733142 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 14:43:48.733207 Checking files for TFTP limit of 4294967296 bytes.
325 14:43:48.733711 end: 1 tftp-deploy (duration 00:00:44) [common]
326 14:43:48.733824 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 14:43:48.733912 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 14:43:48.734036 substitutions:
329 14:43:48.734102 - {DTB}: 14166996/tftp-deploy-z467xwy8/dtb/mt8192-asurada-spherion-r0.dtb
330 14:43:48.734173 - {INITRD}: 14166996/tftp-deploy-z467xwy8/ramdisk/ramdisk.cpio.gz
331 14:43:48.734271 - {KERNEL}: 14166996/tftp-deploy-z467xwy8/kernel/Image
332 14:43:48.734334 - {LAVA_MAC}: None
333 14:43:48.734394 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b
334 14:43:48.734453 - {NFS_SERVER_IP}: 192.168.201.1
335 14:43:48.734508 - {PRESEED_CONFIG}: None
336 14:43:48.734562 - {PRESEED_LOCAL}: None
337 14:43:48.734616 - {RAMDISK}: 14166996/tftp-deploy-z467xwy8/ramdisk/ramdisk.cpio.gz
338 14:43:48.734669 - {ROOT_PART}: None
339 14:43:48.734723 - {ROOT}: None
340 14:43:48.734776 - {SERVER_IP}: 192.168.201.1
341 14:43:48.734833 - {TEE}: None
342 14:43:48.734891 Parsed boot commands:
343 14:43:48.734947 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 14:43:48.735122 Parsed boot commands: tftpboot 192.168.201.1 14166996/tftp-deploy-z467xwy8/kernel/image.itb 14166996/tftp-deploy-z467xwy8/kernel/cmdline
345 14:43:48.735209 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 14:43:48.735292 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 14:43:48.735387 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 14:43:48.735478 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 14:43:48.735550 Not connected, no need to disconnect.
350 14:43:48.735623 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 14:43:48.735709 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 14:43:48.735778 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 14:43:48.739540 Setting prompt string to ['lava-test: # ']
354 14:43:48.739915 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 14:43:48.740022 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 14:43:48.740120 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 14:43:48.740212 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 14:43:48.740396 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 14:44:02.785500 Returned 0 in 14 seconds
360 14:44:02.886596 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 14:44:02.888070 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 14:44:02.888613 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 14:44:02.889215 Setting prompt string to 'Starting depthcharge on Spherion...'
365 14:44:02.889821 Changing prompt to 'Starting depthcharge on Spherion...'
366 14:44:02.890407 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 14:44:02.892790 [Enter `^Ec?' for help]
368 14:44:02.893350
369 14:44:02.893733
370 14:44:02.894199 F0: 102B 0000
371 14:44:02.894592
372 14:44:02.895092 F3: 1001 0000 [0200]
373 14:44:02.895658
374 14:44:02.896018 F3: 1001 0000
375 14:44:02.896375
376 14:44:02.896695 F7: 102D 0000
377 14:44:02.897028
378 14:44:02.897327 F1: 0000 0000
379 14:44:02.897663
380 14:44:02.897957 V0: 0000 0000 [0001]
381 14:44:02.898351
382 14:44:02.898644 00: 0007 8000
383 14:44:02.898994
384 14:44:02.899285 01: 0000 0000
385 14:44:02.899619
386 14:44:02.899904 BP: 0C00 0209 [0000]
387 14:44:02.900233
388 14:44:02.900520 G0: 1182 0000
389 14:44:02.900905
390 14:44:02.901203 EC: 0000 0021 [4000]
391 14:44:02.901601
392 14:44:02.901892 S7: 0000 0000 [0000]
393 14:44:02.902371
394 14:44:02.902772 CC: 0000 0000 [0001]
395 14:44:02.903064
396 14:44:02.903446 T0: 0000 0040 [010F]
397 14:44:02.903780
398 14:44:02.904100 Jump to BL
399 14:44:02.904456
400 14:44:02.904751
401 14:44:02.905136
402 14:44:02.905426 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 14:44:02.905842 ARM64: Exception handlers installed.
404 14:44:02.906193 ARM64: Testing exception
405 14:44:02.906536 ARM64: Done test exception
406 14:44:02.906898 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 14:44:02.907201 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 14:44:02.907489 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 14:44:02.907768 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 14:44:02.908050 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 14:44:02.908328 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 14:44:02.908690 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 14:44:02.908993 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 14:44:02.909377 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 14:44:02.909671 WDT: Last reset was cold boot
416 14:44:02.910059 SPI1(PAD0) initialized at 2873684 Hz
417 14:44:02.910457 SPI5(PAD0) initialized at 992727 Hz
418 14:44:02.910768 VBOOT: Loading verstage.
419 14:44:02.911140 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 14:44:02.911443 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 14:44:02.911840 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 14:44:02.912138 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 14:44:02.912513 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 14:44:02.912858 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 14:44:02.913182 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 14:44:02.913543
427 14:44:02.913841
428 14:44:02.914371 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 14:44:02.914898 ARM64: Exception handlers installed.
430 14:44:02.915220 ARM64: Testing exception
431 14:44:02.915554 ARM64: Done test exception
432 14:44:02.915839 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 14:44:02.916167 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 14:44:02.916451 Probing TPM: . done!
435 14:44:02.916772 TPM ready after 0 ms
436 14:44:02.917056 Connected to device vid:did:rid of 1ae0:0028:00
437 14:44:02.917383 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 14:44:02.917685 Initialized TPM device CR50 revision 0
439 14:44:02.917964 tlcl_send_startup: Startup return code is 0
440 14:44:02.918192 TPM: setup succeeded
441 14:44:02.918474 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 14:44:02.918686 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 14:44:02.918928 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 14:44:02.919157 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 14:44:02.919355 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 14:44:02.919634 in-header: 03 07 00 00 08 00 00 00
447 14:44:02.919841 in-data: aa e4 47 04 13 02 00 00
448 14:44:02.920093 Chrome EC: UHEPI supported
449 14:44:02.920306 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 14:44:02.920510 in-header: 03 a9 00 00 08 00 00 00
451 14:44:02.920786 in-data: 84 60 60 08 00 00 00 00
452 14:44:02.920990 Phase 1
453 14:44:02.921248 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 14:44:02.921465 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 14:44:02.921668 VB2:vb2_check_recovery() Recovery was requested manually
456 14:44:02.921954 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 14:44:02.922193 Recovery requested (1009000e)
458 14:44:02.922447 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 14:44:02.922690 tlcl_extend: response is 0
460 14:44:02.922850 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 14:44:02.923049 tlcl_extend: response is 0
462 14:44:02.923210 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 14:44:02.923363 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 14:44:02.923533 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 14:44:02.923722
466 14:44:02.923884
467 14:44:02.924033 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 14:44:02.924252 ARM64: Exception handlers installed.
469 14:44:02.924407 ARM64: Testing exception
470 14:44:02.924558 ARM64: Done test exception
471 14:44:02.924767 pmic_efuse_setting: Set efuses in 11 msecs
472 14:44:02.924923 pmwrap_interface_init: Select PMIF_VLD_RDY
473 14:44:02.925075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 14:44:02.925244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 14:44:02.925687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 14:44:02.925913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 14:44:02.926074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 14:44:02.926253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 14:44:02.926470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 14:44:02.926664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 14:44:02.926821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 14:44:02.927041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 14:44:02.927196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 14:44:02.927344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 14:44:02.927545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 14:44:02.927709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 14:44:02.927831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 14:44:02.927951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 14:44:02.928121 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 14:44:02.928246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 14:44:02.928368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 14:44:02.928486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 14:44:02.928654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 14:44:02.928781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 14:44:02.928901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 14:44:02.929020 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 14:44:02.929186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 14:44:02.929313 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 14:44:02.929434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 14:44:02.929635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 14:44:02.929851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 14:44:02.929987 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 14:44:02.930110 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 14:44:02.930264 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 14:44:02.930397 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 14:44:02.930519 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 14:44:02.930640 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 14:44:02.930760 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 14:44:02.930899 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 14:44:02.931022 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 14:44:02.931143 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 14:44:02.931262 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 14:44:02.931392 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 14:44:02.931522 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 14:44:02.931642 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 14:44:02.931761 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 14:44:02.931880 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 14:44:02.932012 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 14:44:02.932139 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 14:44:02.932257 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 14:44:02.932375 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 14:44:02.932494 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 14:44:02.932623 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 14:44:02.932752 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 14:44:02.932854 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 14:44:02.932955 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 14:44:02.933054 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 14:44:02.933163 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 14:44:02.933271 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 14:44:02.933417 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 14:44:02.933604 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 14:44:02.933779 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2c
533 14:44:02.933943 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 14:44:02.934100 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 14:44:02.934292 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 14:44:02.934456 [RTC]rtc_get_frequency_meter,154: input=15, output=835
537 14:44:02.934613 [RTC]rtc_get_frequency_meter,154: input=7, output=709
538 14:44:02.934770 [RTC]rtc_get_frequency_meter,154: input=11, output=772
539 14:44:02.934934 [RTC]rtc_get_frequency_meter,154: input=13, output=804
540 14:44:02.935093 [RTC]rtc_get_frequency_meter,154: input=12, output=788
541 14:44:02.935249 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 14:44:02.935408 [RTC]rtc_get_frequency_meter,154: input=13, output=804
543 14:44:02.935568 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 14:44:02.935725 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 14:44:02.936102 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 14:44:02.936219 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 14:44:02.936322 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 14:44:02.936423 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 14:44:02.936527 ADC[4]: Raw value=903031 ID=7
550 14:44:02.936699 ADC[3]: Raw value=212912 ID=1
551 14:44:02.936807 RAM Code: 0x71
552 14:44:02.936907 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 14:44:02.937010 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 14:44:02.937112 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 14:44:02.937228 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 14:44:02.937330 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 14:44:02.937431 in-header: 03 07 00 00 08 00 00 00
558 14:44:02.937530 in-data: aa e4 47 04 13 02 00 00
559 14:44:02.937628 Chrome EC: UHEPI supported
560 14:44:02.937742 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 14:44:02.937835 in-header: 03 a9 00 00 08 00 00 00
562 14:44:02.937921 in-data: 84 60 60 08 00 00 00 00
563 14:44:02.938005 MRC: failed to locate region type 0.
564 14:44:02.938091 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 14:44:02.938190 DRAM-K: Running full calibration
566 14:44:02.938285 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 14:44:02.938376 header.status = 0x0
568 14:44:02.938462 header.version = 0x6 (expected: 0x6)
569 14:44:02.938546 header.size = 0xd00 (expected: 0xd00)
570 14:44:02.938632 header.flags = 0x0
571 14:44:02.938717 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 14:44:02.938803 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 14:44:02.938901 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 14:44:02.938989 dram_init: ddr_geometry: 2
575 14:44:02.939075 [EMI] MDL number = 2
576 14:44:02.939160 [EMI] Get MDL freq = 0
577 14:44:02.939244 dram_init: ddr_type: 0
578 14:44:02.939328 is_discrete_lpddr4: 1
579 14:44:02.939422 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 14:44:02.939544
581 14:44:02.939676
582 14:44:02.939808 [Bian_co] ETT version 0.0.0.1
583 14:44:02.939944 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 14:44:02.940041
585 14:44:02.940175 dramc_set_vcore_voltage set vcore to 650000
586 14:44:02.940308 Read voltage for 800, 4
587 14:44:02.940440 Vio18 = 0
588 14:44:02.940567 Vcore = 650000
589 14:44:02.940661 Vdram = 0
590 14:44:02.940748 Vddq = 0
591 14:44:02.940832 Vmddr = 0
592 14:44:02.940916 dram_init: config_dvfs: 1
593 14:44:02.941001 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 14:44:02.941087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 14:44:02.941185 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 14:44:02.941272 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 14:44:02.941358 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 14:44:02.941444 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 14:44:02.941529 MEM_TYPE=3, freq_sel=18
600 14:44:02.941614 sv_algorithm_assistance_LP4_1600
601 14:44:02.941711 ============ PULL DRAM RESETB DOWN ============
602 14:44:02.941807 ========== PULL DRAM RESETB DOWN end =========
603 14:44:02.941894 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 14:44:02.941979 ===================================
605 14:44:02.942065 LPDDR4 DRAM CONFIGURATION
606 14:44:02.942149 ===================================
607 14:44:02.942263 EX_ROW_EN[0] = 0x0
608 14:44:02.942351 EX_ROW_EN[1] = 0x0
609 14:44:02.942436 LP4Y_EN = 0x0
610 14:44:02.942521 WORK_FSP = 0x0
611 14:44:02.942605 WL = 0x2
612 14:44:02.942698 RL = 0x2
613 14:44:02.942783 BL = 0x2
614 14:44:02.942859 RPST = 0x0
615 14:44:02.942934 RD_PRE = 0x0
616 14:44:02.943009 WR_PRE = 0x1
617 14:44:02.943084 WR_PST = 0x0
618 14:44:02.943159 DBI_WR = 0x0
619 14:44:02.943233 DBI_RD = 0x0
620 14:44:02.943341 OTF = 0x1
621 14:44:02.943421 ===================================
622 14:44:02.943497 ===================================
623 14:44:02.943571 ANA top config
624 14:44:02.943645 ===================================
625 14:44:02.943721 DLL_ASYNC_EN = 0
626 14:44:02.943805 ALL_SLAVE_EN = 1
627 14:44:02.943899 NEW_RANK_MODE = 1
628 14:44:02.943976 DLL_IDLE_MODE = 1
629 14:44:02.944051 LP45_APHY_COMB_EN = 1
630 14:44:02.944125 TX_ODT_DIS = 1
631 14:44:02.944199 NEW_8X_MODE = 1
632 14:44:02.944274 ===================================
633 14:44:02.944379 ===================================
634 14:44:02.944457 data_rate = 1600
635 14:44:02.944533 CKR = 1
636 14:44:02.944608 DQ_P2S_RATIO = 8
637 14:44:02.944682 ===================================
638 14:44:02.944757 CA_P2S_RATIO = 8
639 14:44:02.944830 DQ_CA_OPEN = 0
640 14:44:02.944938 DQ_SEMI_OPEN = 0
641 14:44:02.945016 CA_SEMI_OPEN = 0
642 14:44:02.945090 CA_FULL_RATE = 0
643 14:44:02.945164 DQ_CKDIV4_EN = 1
644 14:44:02.945238 CA_CKDIV4_EN = 1
645 14:44:02.945312 CA_PREDIV_EN = 0
646 14:44:02.945385 PH8_DLY = 0
647 14:44:02.945512 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 14:44:02.945629 DQ_AAMCK_DIV = 4
649 14:44:02.945745 CA_AAMCK_DIV = 4
650 14:44:02.945861 CA_ADMCK_DIV = 4
651 14:44:02.945994 DQ_TRACK_CA_EN = 0
652 14:44:02.946112 CA_PICK = 800
653 14:44:02.946249 CA_MCKIO = 800
654 14:44:02.946366 MCKIO_SEMI = 0
655 14:44:02.946498 PLL_FREQ = 3068
656 14:44:02.946618 DQ_UI_PI_RATIO = 32
657 14:44:02.946734 CA_UI_PI_RATIO = 0
658 14:44:02.946851 ===================================
659 14:44:02.946968 ===================================
660 14:44:02.947114 memory_type:LPDDR4
661 14:44:02.947254 GP_NUM : 10
662 14:44:02.947382 SRAM_EN : 1
663 14:44:02.947504 MD32_EN : 0
664 14:44:02.947838 ===================================
665 14:44:02.947917 [ANA_INIT] >>>>>>>>>>>>>>
666 14:44:02.947988 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 14:44:02.948093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 14:44:02.948202 ===================================
669 14:44:02.948310 data_rate = 1600,PCW = 0X7600
670 14:44:02.948435 ===================================
671 14:44:02.948554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 14:44:02.948673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 14:44:02.948780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 14:44:02.948891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 14:44:02.948996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 14:44:02.949114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 14:44:02.949224 [ANA_INIT] flow start
678 14:44:02.949328 [ANA_INIT] PLL >>>>>>>>
679 14:44:02.949433 [ANA_INIT] PLL <<<<<<<<
680 14:44:02.949537 [ANA_INIT] MIDPI >>>>>>>>
681 14:44:02.949652 [ANA_INIT] MIDPI <<<<<<<<
682 14:44:02.949724 [ANA_INIT] DLL >>>>>>>>
683 14:44:02.949791 [ANA_INIT] flow end
684 14:44:02.949857 ============ LP4 DIFF to SE enter ============
685 14:44:02.949924 ============ LP4 DIFF to SE exit ============
686 14:44:02.949992 [ANA_INIT] <<<<<<<<<<<<<
687 14:44:02.950059 [Flow] Enable top DCM control >>>>>
688 14:44:02.950132 [Flow] Enable top DCM control <<<<<
689 14:44:02.950230 Enable DLL master slave shuffle
690 14:44:02.950300 ==============================================================
691 14:44:02.950366 Gating Mode config
692 14:44:02.950432 ==============================================================
693 14:44:02.950499 Config description:
694 14:44:02.950566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 14:44:02.950634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 14:44:02.950732 SELPH_MODE 0: By rank 1: By Phase
697 14:44:02.950802 ==============================================================
698 14:44:02.950869 GAT_TRACK_EN = 1
699 14:44:02.950936 RX_GATING_MODE = 2
700 14:44:02.951003 RX_GATING_TRACK_MODE = 2
701 14:44:02.951070 SELPH_MODE = 1
702 14:44:02.951135 PICG_EARLY_EN = 1
703 14:44:02.951224 VALID_LAT_VALUE = 1
704 14:44:02.951296 ==============================================================
705 14:44:02.951363 Enter into Gating configuration >>>>
706 14:44:02.951430 Exit from Gating configuration <<<<
707 14:44:02.951496 Enter into DVFS_PRE_config >>>>>
708 14:44:02.951563 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 14:44:02.951636 Exit from DVFS_PRE_config <<<<<
710 14:44:02.951704 Enter into PICG configuration >>>>
711 14:44:02.951815 Exit from PICG configuration <<<<
712 14:44:02.951920 [RX_INPUT] configuration >>>>>
713 14:44:02.952023 [RX_INPUT] configuration <<<<<
714 14:44:02.952130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 14:44:02.952251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 14:44:02.952375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 14:44:02.952485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 14:44:02.952594 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 14:44:02.952717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 14:44:02.952817 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 14:44:02.952915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 14:44:02.953009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 14:44:02.953104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 14:44:02.953198 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 14:44:02.953291 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 14:44:02.953358 ===================================
727 14:44:02.953420 LPDDR4 DRAM CONFIGURATION
728 14:44:02.953481 ===================================
729 14:44:02.953541 EX_ROW_EN[0] = 0x0
730 14:44:02.953601 EX_ROW_EN[1] = 0x0
731 14:44:02.953661 LP4Y_EN = 0x0
732 14:44:02.953720 WORK_FSP = 0x0
733 14:44:02.953779 WL = 0x2
734 14:44:02.953838 RL = 0x2
735 14:44:02.953935 BL = 0x2
736 14:44:02.954028 RPST = 0x0
737 14:44:02.954122 RD_PRE = 0x0
738 14:44:02.954207 WR_PRE = 0x1
739 14:44:02.954269 WR_PST = 0x0
740 14:44:02.954329 DBI_WR = 0x0
741 14:44:02.954394 DBI_RD = 0x0
742 14:44:02.954459 OTF = 0x1
743 14:44:02.954520 ===================================
744 14:44:02.954581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 14:44:02.954641 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 14:44:02.954701 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 14:44:02.954762 ===================================
748 14:44:02.954822 LPDDR4 DRAM CONFIGURATION
749 14:44:02.954886 ===================================
750 14:44:02.954951 EX_ROW_EN[0] = 0x10
751 14:44:02.955012 EX_ROW_EN[1] = 0x0
752 14:44:02.955072 LP4Y_EN = 0x0
753 14:44:02.955131 WORK_FSP = 0x0
754 14:44:02.955191 WL = 0x2
755 14:44:02.955250 RL = 0x2
756 14:44:02.955310 BL = 0x2
757 14:44:02.955369 RPST = 0x0
758 14:44:02.955439 RD_PRE = 0x0
759 14:44:02.955533 WR_PRE = 0x1
760 14:44:02.955625 WR_PST = 0x0
761 14:44:02.955718 DBI_WR = 0x0
762 14:44:02.955810 DBI_RD = 0x0
763 14:44:02.955903 OTF = 0x1
764 14:44:02.956002 ===================================
765 14:44:02.956097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 14:44:02.956190 nWR fixed to 40
767 14:44:02.956284 [ModeRegInit_LP4] CH0 RK0
768 14:44:02.956378 [ModeRegInit_LP4] CH0 RK1
769 14:44:02.956474 [ModeRegInit_LP4] CH1 RK0
770 14:44:02.956569 [ModeRegInit_LP4] CH1 RK1
771 14:44:02.956663 match AC timing 13
772 14:44:02.956756 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 14:44:02.957057 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 14:44:02.957160 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 14:44:02.957257 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 14:44:02.957352 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 14:44:02.957446 [EMI DOE] emi_dcm 0
778 14:44:02.957525 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 14:44:02.957590 ==
780 14:44:02.957651 Dram Type= 6, Freq= 0, CH_0, rank 0
781 14:44:02.957721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 14:44:02.957777 ==
783 14:44:02.957832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 14:44:02.957887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 14:44:02.957943 [CA 0] Center 37 (6~68) winsize 63
786 14:44:02.957998 [CA 1] Center 37 (6~68) winsize 63
787 14:44:02.958088 [CA 2] Center 34 (4~65) winsize 62
788 14:44:02.958182 [CA 3] Center 34 (4~65) winsize 62
789 14:44:02.958240 [CA 4] Center 33 (3~64) winsize 62
790 14:44:02.958295 [CA 5] Center 33 (3~64) winsize 62
791 14:44:02.958350
792 14:44:02.958405 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 14:44:02.958461
794 14:44:02.958520 [CATrainingPosCal] consider 1 rank data
795 14:44:02.958580 u2DelayCellTimex100 = 270/100 ps
796 14:44:02.958636 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
797 14:44:02.958691 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 14:44:02.958746 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 14:44:02.958800 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 14:44:02.958855 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 14:44:02.958909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 14:44:02.958962
803 14:44:02.959020 CA PerBit enable=1, Macro0, CA PI delay=33
804 14:44:02.959080
805 14:44:02.959135 [CBTSetCACLKResult] CA Dly = 33
806 14:44:02.959189 CS Dly: 7 (0~38)
807 14:44:02.959244 ==
808 14:44:02.959299 Dram Type= 6, Freq= 0, CH_0, rank 1
809 14:44:02.959354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 14:44:02.959416 ==
811 14:44:02.959473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 14:44:02.959534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 14:44:02.959595 [CA 0] Center 37 (6~68) winsize 63
814 14:44:02.959651 [CA 1] Center 37 (7~68) winsize 62
815 14:44:02.959705 [CA 2] Center 34 (4~65) winsize 62
816 14:44:02.959759 [CA 3] Center 34 (4~65) winsize 62
817 14:44:02.959814 [CA 4] Center 33 (3~64) winsize 62
818 14:44:02.959869 [CA 5] Center 33 (3~64) winsize 62
819 14:44:02.959923
820 14:44:02.959977 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 14:44:02.960039
822 14:44:02.960127 [CATrainingPosCal] consider 2 rank data
823 14:44:02.960213 u2DelayCellTimex100 = 270/100 ps
824 14:44:02.960298 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
825 14:44:02.960383 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 14:44:02.960468 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 14:44:02.960556 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 14:44:02.960644 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 14:44:02.960729 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 14:44:02.960813
831 14:44:02.960898 CA PerBit enable=1, Macro0, CA PI delay=33
832 14:44:02.960982
833 14:44:02.961068 [CBTSetCACLKResult] CA Dly = 33
834 14:44:02.961158 CS Dly: 7 (0~38)
835 14:44:02.961242
836 14:44:02.961328 ----->DramcWriteLeveling(PI) begin...
837 14:44:02.961416 ==
838 14:44:02.961502 Dram Type= 6, Freq= 0, CH_0, rank 0
839 14:44:02.961589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 14:44:02.961650 ==
841 14:44:02.961706 Write leveling (Byte 0): 32 => 32
842 14:44:02.961761 Write leveling (Byte 1): 29 => 29
843 14:44:02.961816 DramcWriteLeveling(PI) end<-----
844 14:44:02.961870
845 14:44:02.961924 ==
846 14:44:02.961979 Dram Type= 6, Freq= 0, CH_0, rank 0
847 14:44:02.962034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 14:44:02.962088 ==
849 14:44:02.962190 [Gating] SW mode calibration
850 14:44:02.962278 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 14:44:02.962364 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 14:44:02.962450 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 14:44:02.962536 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 14:44:02.962623 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
855 14:44:02.962681 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 14:44:02.962752 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 14:44:02.962807 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:44:02.962860 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:44:02.962913 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:44:02.962967 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 14:44:02.963020 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 14:44:02.963074 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 14:44:02.963128 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 14:44:02.963185 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 14:44:02.963287 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 14:44:02.963373 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 14:44:02.963461 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 14:44:02.963516 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 14:44:02.963569 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 14:44:02.963623 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 14:44:02.963676 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 14:44:02.963729 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 14:44:02.963788 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 14:44:02.963846 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 14:44:02.963899 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 14:44:02.963953 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 14:44:02.964007 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 14:44:02.964060 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
879 14:44:02.964113 0 9 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
880 14:44:02.964167 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 14:44:02.964415 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 14:44:02.964475 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 14:44:02.964566 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 14:44:02.964620 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 14:44:02.964674 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 14:44:02.964727 0 10 8 | B1->B0 | 3131 2a2a | 0 1 | (0 0) (1 0)
887 14:44:02.964781 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
888 14:44:02.964857 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 14:44:02.964964 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 14:44:02.965049 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 14:44:02.965133 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 14:44:02.965217 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 14:44:02.965300 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 14:44:02.965386 0 11 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
895 14:44:02.965459 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
896 14:44:02.965513 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 14:44:02.965568 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 14:44:02.965621 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 14:44:02.965674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 14:44:02.965728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 14:44:02.965782 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 14:44:02.965862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 14:44:02.965927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 14:44:02.966017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 14:44:02.966102 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 14:44:02.966215 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 14:44:02.966272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 14:44:02.966341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 14:44:02.966410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 14:44:02.966516 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 14:44:02.966589 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 14:44:02.966660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 14:44:02.966714 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 14:44:02.966767 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 14:44:02.966821 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 14:44:02.966874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 14:44:02.966927 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 14:44:02.966982 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 14:44:02.967056 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 14:44:02.967111 Total UI for P1: 0, mck2ui 16
921 14:44:02.967166 best dqsien dly found for B0: ( 0, 14, 8)
922 14:44:02.967220 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 14:44:02.967273 Total UI for P1: 0, mck2ui 16
924 14:44:02.967341 best dqsien dly found for B1: ( 0, 14, 12)
925 14:44:02.967408 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 14:44:02.967461 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
927 14:44:02.967523
928 14:44:02.967588 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 14:44:02.967643 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
930 14:44:02.967700 [Gating] SW calibration Done
931 14:44:02.967791 ==
932 14:44:02.967844 Dram Type= 6, Freq= 0, CH_0, rank 0
933 14:44:02.967898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 14:44:02.967951 ==
935 14:44:02.968005 RX Vref Scan: 0
936 14:44:02.968079
937 14:44:02.968192 RX Vref 0 -> 0, step: 1
938 14:44:02.968275
939 14:44:02.968357 RX Delay -130 -> 252, step: 16
940 14:44:02.968441 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 14:44:02.968553 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 14:44:02.968649 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 14:44:02.968733 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 14:44:02.968816 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 14:44:02.968913 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 14:44:02.969010 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 14:44:02.969133 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 14:44:02.969218 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 14:44:02.969301 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 14:44:02.969384 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 14:44:02.969467 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 14:44:02.969550 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 14:44:02.969655 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 14:44:02.969727 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 14:44:02.969780 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 14:44:02.969833 ==
957 14:44:02.969901 Dram Type= 6, Freq= 0, CH_0, rank 0
958 14:44:02.969969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 14:44:02.970022 ==
960 14:44:02.970076 DQS Delay:
961 14:44:02.970130 DQS0 = 0, DQS1 = 0
962 14:44:02.970240 DQM Delay:
963 14:44:02.970295 DQM0 = 86, DQM1 = 72
964 14:44:02.970348 DQ Delay:
965 14:44:02.970402 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 14:44:02.970456 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 14:44:02.970510 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 14:44:02.970563 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
969 14:44:02.970617
970 14:44:02.970679
971 14:44:02.970743 ==
972 14:44:02.970797 Dram Type= 6, Freq= 0, CH_0, rank 0
973 14:44:02.970851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 14:44:02.970905 ==
975 14:44:02.970958
976 14:44:02.971011
977 14:44:02.971064 TX Vref Scan disable
978 14:44:02.971118 == TX Byte 0 ==
979 14:44:02.971171 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 14:44:02.971249 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 14:44:02.971328 == TX Byte 1 ==
982 14:44:02.971423 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 14:44:02.971477 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 14:44:02.971530 ==
985 14:44:02.971583 Dram Type= 6, Freq= 0, CH_0, rank 0
986 14:44:02.971636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 14:44:02.971690 ==
988 14:44:02.971766 TX Vref=22, minBit 4, minWin=27, winSum=439
989 14:44:02.972015 TX Vref=24, minBit 8, minWin=27, winSum=444
990 14:44:02.972077 TX Vref=26, minBit 8, minWin=27, winSum=445
991 14:44:02.972133 TX Vref=28, minBit 8, minWin=27, winSum=448
992 14:44:02.972188 TX Vref=30, minBit 5, minWin=27, winSum=448
993 14:44:02.972250 TX Vref=32, minBit 11, minWin=26, winSum=442
994 14:44:02.972344 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 28
995 14:44:02.972427
996 14:44:02.972511 Final TX Range 1 Vref 28
997 14:44:02.972594
998 14:44:02.972677 ==
999 14:44:02.972768 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 14:44:02.972894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 14:44:02.972978 ==
1002 14:44:02.973060
1003 14:44:02.973142
1004 14:44:02.973225 TX Vref Scan disable
1005 14:44:02.973313 == TX Byte 0 ==
1006 14:44:02.973370 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 14:44:02.973424 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 14:44:02.973478 == TX Byte 1 ==
1009 14:44:02.973532 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 14:44:02.973585 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 14:44:02.973639
1012 14:44:02.973696 [DATLAT]
1013 14:44:02.973749 Freq=800, CH0 RK0
1014 14:44:02.973834
1015 14:44:02.973917 DATLAT Default: 0xa
1016 14:44:02.974000 0, 0xFFFF, sum = 0
1017 14:44:02.974085 1, 0xFFFF, sum = 0
1018 14:44:02.974193 2, 0xFFFF, sum = 0
1019 14:44:02.974264 3, 0xFFFF, sum = 0
1020 14:44:02.974340 4, 0xFFFF, sum = 0
1021 14:44:02.974400 5, 0xFFFF, sum = 0
1022 14:44:02.974454 6, 0xFFFF, sum = 0
1023 14:44:02.974508 7, 0xFFFF, sum = 0
1024 14:44:02.974562 8, 0xFFFF, sum = 0
1025 14:44:02.974623 9, 0x0, sum = 1
1026 14:44:02.974682 10, 0x0, sum = 2
1027 14:44:02.974737 11, 0x0, sum = 3
1028 14:44:02.974791 12, 0x0, sum = 4
1029 14:44:02.974868 best_step = 10
1030 14:44:02.974924
1031 14:44:02.974977 ==
1032 14:44:02.975030 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 14:44:02.975097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 14:44:02.975165 ==
1035 14:44:02.975218 RX Vref Scan: 1
1036 14:44:02.975270
1037 14:44:02.975323 Set Vref Range= 32 -> 127
1038 14:44:02.975399
1039 14:44:02.975453 RX Vref 32 -> 127, step: 1
1040 14:44:02.975506
1041 14:44:02.975558 RX Delay -111 -> 252, step: 8
1042 14:44:02.975611
1043 14:44:02.975663 Set Vref, RX VrefLevel [Byte0]: 32
1044 14:44:02.975716 [Byte1]: 32
1045 14:44:02.975769
1046 14:44:02.975821 Set Vref, RX VrefLevel [Byte0]: 33
1047 14:44:02.975887 [Byte1]: 33
1048 14:44:02.975948
1049 14:44:02.976000 Set Vref, RX VrefLevel [Byte0]: 34
1050 14:44:02.976053 [Byte1]: 34
1051 14:44:02.976106
1052 14:44:02.976158 Set Vref, RX VrefLevel [Byte0]: 35
1053 14:44:02.976210 [Byte1]: 35
1054 14:44:02.976263
1055 14:44:02.976315 Set Vref, RX VrefLevel [Byte0]: 36
1056 14:44:02.976368 [Byte1]: 36
1057 14:44:02.976444
1058 14:44:02.976499 Set Vref, RX VrefLevel [Byte0]: 37
1059 14:44:02.976553 [Byte1]: 37
1060 14:44:02.976605
1061 14:44:02.976657 Set Vref, RX VrefLevel [Byte0]: 38
1062 14:44:02.976709 [Byte1]: 38
1063 14:44:02.976761
1064 14:44:02.976814 Set Vref, RX VrefLevel [Byte0]: 39
1065 14:44:02.976867 [Byte1]: 39
1066 14:44:02.976925
1067 14:44:02.976990 Set Vref, RX VrefLevel [Byte0]: 40
1068 14:44:02.977044 [Byte1]: 40
1069 14:44:02.977098
1070 14:44:02.977150 Set Vref, RX VrefLevel [Byte0]: 41
1071 14:44:02.977202 [Byte1]: 41
1072 14:44:02.977255
1073 14:44:02.977307 Set Vref, RX VrefLevel [Byte0]: 42
1074 14:44:02.977358 [Byte1]: 42
1075 14:44:02.977411
1076 14:44:02.977486 Set Vref, RX VrefLevel [Byte0]: 43
1077 14:44:02.977542 [Byte1]: 43
1078 14:44:02.977594
1079 14:44:02.977647 Set Vref, RX VrefLevel [Byte0]: 44
1080 14:44:02.977700 [Byte1]: 44
1081 14:44:02.977752
1082 14:44:02.977804 Set Vref, RX VrefLevel [Byte0]: 45
1083 14:44:02.977857 [Byte1]: 45
1084 14:44:02.977909
1085 14:44:02.977962 Set Vref, RX VrefLevel [Byte0]: 46
1086 14:44:02.978055 [Byte1]: 46
1087 14:44:02.978137
1088 14:44:02.978242 Set Vref, RX VrefLevel [Byte0]: 47
1089 14:44:02.978297 [Byte1]: 47
1090 14:44:02.978350
1091 14:44:02.978402 Set Vref, RX VrefLevel [Byte0]: 48
1092 14:44:02.978455 [Byte1]: 48
1093 14:44:02.978519
1094 14:44:02.978581 Set Vref, RX VrefLevel [Byte0]: 49
1095 14:44:02.978634 [Byte1]: 49
1096 14:44:02.978686
1097 14:44:02.978739 Set Vref, RX VrefLevel [Byte0]: 50
1098 14:44:02.978791 [Byte1]: 50
1099 14:44:02.978864
1100 14:44:02.978917 Set Vref, RX VrefLevel [Byte0]: 51
1101 14:44:02.978971 [Byte1]: 51
1102 14:44:02.979035
1103 14:44:02.979097 Set Vref, RX VrefLevel [Byte0]: 52
1104 14:44:02.979152 [Byte1]: 52
1105 14:44:02.979205
1106 14:44:02.979259 Set Vref, RX VrefLevel [Byte0]: 53
1107 14:44:02.979313 [Byte1]: 53
1108 14:44:02.979366
1109 14:44:02.979419 Set Vref, RX VrefLevel [Byte0]: 54
1110 14:44:02.979473 [Byte1]: 54
1111 14:44:02.979527
1112 14:44:02.979602 Set Vref, RX VrefLevel [Byte0]: 55
1113 14:44:02.979658 [Byte1]: 55
1114 14:44:02.979712
1115 14:44:02.979765 Set Vref, RX VrefLevel [Byte0]: 56
1116 14:44:02.979818 [Byte1]: 56
1117 14:44:02.979871
1118 14:44:02.979924 Set Vref, RX VrefLevel [Byte0]: 57
1119 14:44:02.979977 [Byte1]: 57
1120 14:44:02.980030
1121 14:44:02.980097 Set Vref, RX VrefLevel [Byte0]: 58
1122 14:44:02.980158 [Byte1]: 58
1123 14:44:02.980212
1124 14:44:02.980265 Set Vref, RX VrefLevel [Byte0]: 59
1125 14:44:02.980319 [Byte1]: 59
1126 14:44:02.980373
1127 14:44:02.980426 Set Vref, RX VrefLevel [Byte0]: 60
1128 14:44:02.980478 [Byte1]: 60
1129 14:44:02.980532
1130 14:44:02.980585 Set Vref, RX VrefLevel [Byte0]: 61
1131 14:44:02.980667 [Byte1]: 61
1132 14:44:02.980751
1133 14:44:02.980835 Set Vref, RX VrefLevel [Byte0]: 62
1134 14:44:02.980918 [Byte1]: 62
1135 14:44:02.981001
1136 14:44:02.981085 Set Vref, RX VrefLevel [Byte0]: 63
1137 14:44:02.981181 [Byte1]: 63
1138 14:44:02.981265
1139 14:44:02.981348 Set Vref, RX VrefLevel [Byte0]: 64
1140 14:44:02.981432 [Byte1]: 64
1141 14:44:02.981515
1142 14:44:02.981598 Set Vref, RX VrefLevel [Byte0]: 65
1143 14:44:02.981693 [Byte1]: 65
1144 14:44:02.981777
1145 14:44:02.981861 Set Vref, RX VrefLevel [Byte0]: 66
1146 14:44:02.981944 [Byte1]: 66
1147 14:44:02.982027
1148 14:44:02.982110 Set Vref, RX VrefLevel [Byte0]: 67
1149 14:44:02.982210 [Byte1]: 67
1150 14:44:02.982269
1151 14:44:02.982323 Set Vref, RX VrefLevel [Byte0]: 68
1152 14:44:02.982377 [Byte1]: 68
1153 14:44:02.982431
1154 14:44:02.982485 Set Vref, RX VrefLevel [Byte0]: 69
1155 14:44:02.982539 [Byte1]: 69
1156 14:44:02.982593
1157 14:44:02.982844 Set Vref, RX VrefLevel [Byte0]: 70
1158 14:44:02.982937 [Byte1]: 70
1159 14:44:02.983022
1160 14:44:02.983114 Set Vref, RX VrefLevel [Byte0]: 71
1161 14:44:02.983203 [Byte1]: 71
1162 14:44:02.983301
1163 14:44:02.983386 Set Vref, RX VrefLevel [Byte0]: 72
1164 14:44:02.983471 [Byte1]: 72
1165 14:44:02.983554
1166 14:44:02.983637 Set Vref, RX VrefLevel [Byte0]: 73
1167 14:44:02.983721 [Byte1]: 73
1168 14:44:02.983818
1169 14:44:02.983902 Set Vref, RX VrefLevel [Byte0]: 74
1170 14:44:02.983986 [Byte1]: 74
1171 14:44:02.984069
1172 14:44:02.984153 Set Vref, RX VrefLevel [Byte0]: 75
1173 14:44:02.984237 [Byte1]: 75
1174 14:44:02.984316
1175 14:44:02.984401 Set Vref, RX VrefLevel [Byte0]: 76
1176 14:44:02.984484 [Byte1]: 76
1177 14:44:02.984567
1178 14:44:02.984650 Set Vref, RX VrefLevel [Byte0]: 77
1179 14:44:02.984734 [Byte1]: 77
1180 14:44:02.984820
1181 14:44:02.984877 Set Vref, RX VrefLevel [Byte0]: 78
1182 14:44:02.984930 [Byte1]: 78
1183 14:44:02.984984
1184 14:44:02.985038 Set Vref, RX VrefLevel [Byte0]: 79
1185 14:44:02.985092 [Byte1]: 79
1186 14:44:02.985145
1187 14:44:02.985198 Set Vref, RX VrefLevel [Byte0]: 80
1188 14:44:02.985252 [Byte1]: 80
1189 14:44:02.985320
1190 14:44:02.985379 Final RX Vref Byte 0 = 64 to rank0
1191 14:44:02.985434 Final RX Vref Byte 1 = 51 to rank0
1192 14:44:02.985488 Final RX Vref Byte 0 = 64 to rank1
1193 14:44:02.985542 Final RX Vref Byte 1 = 51 to rank1==
1194 14:44:02.985596 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 14:44:02.985650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 14:44:02.985704 ==
1197 14:44:02.985758 DQS Delay:
1198 14:44:02.985811 DQS0 = 0, DQS1 = 0
1199 14:44:02.985889 DQM Delay:
1200 14:44:02.985945 DQM0 = 86, DQM1 = 76
1201 14:44:02.985999 DQ Delay:
1202 14:44:02.986053 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1203 14:44:02.986106 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1204 14:44:02.986159 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1205 14:44:02.986224 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1206 14:44:02.986277
1207 14:44:02.986330
1208 14:44:02.986408 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1209 14:44:02.986466 CH0 RK0: MR19=606, MR18=4325
1210 14:44:02.986520 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1211 14:44:02.986575
1212 14:44:02.986628 ----->DramcWriteLeveling(PI) begin...
1213 14:44:02.986683 ==
1214 14:44:02.986737 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 14:44:02.986791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 14:44:02.986845 ==
1217 14:44:02.986923 Write leveling (Byte 0): 34 => 34
1218 14:44:02.986979 Write leveling (Byte 1): 31 => 31
1219 14:44:02.987033 DramcWriteLeveling(PI) end<-----
1220 14:44:02.987104
1221 14:44:02.987193 ==
1222 14:44:02.987257 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 14:44:02.987313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 14:44:02.987367 ==
1225 14:44:02.987444 [Gating] SW mode calibration
1226 14:44:02.987504 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 14:44:02.987562 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 14:44:02.987617 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 14:44:02.987672 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 14:44:02.987726 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 14:44:02.987780 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1232 14:44:02.987833 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 14:44:02.987886 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 14:44:02.987964 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 14:44:02.988021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 14:44:02.988075 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 14:44:02.988129 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 14:44:02.988193 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 14:44:02.988250 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 14:44:02.988303 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 14:44:02.988357 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 14:44:02.988411 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 14:44:02.988486 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 14:44:02.988544 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 14:44:02.988598 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1246 14:44:02.988652 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1247 14:44:02.988706 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 14:44:02.988761 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 14:44:02.988814 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 14:44:02.988868 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 14:44:02.988922 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 14:44:02.988989 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 14:44:02.989051 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 14:44:02.989105 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1255 14:44:02.989159 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1256 14:44:02.989213 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 14:44:02.989266 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 14:44:02.989320 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 14:44:02.989374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 14:44:02.989427 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 14:44:02.989486 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1262 14:44:02.989555 0 10 8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
1263 14:44:02.989611 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 14:44:02.989665 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 14:44:02.989718 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 14:44:02.989772 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 14:44:02.989826 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 14:44:02.989879 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 14:44:02.990132 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1270 14:44:02.990213 0 11 8 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)
1271 14:44:02.990271 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1272 14:44:02.990325 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 14:44:02.990379 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 14:44:02.990433 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 14:44:02.990488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 14:44:02.990567 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 14:44:02.990625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 14:44:02.990679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1279 14:44:02.990733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 14:44:02.990787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 14:44:02.990840 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 14:44:02.990894 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 14:44:02.990948 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 14:44:02.991002 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 14:44:02.991081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 14:44:02.991138 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 14:44:02.991193 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 14:44:02.991247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 14:44:02.991301 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 14:44:02.991355 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 14:44:02.991408 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 14:44:02.991461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 14:44:02.991515 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1294 14:44:02.991591 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1295 14:44:02.991648 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1296 14:44:02.991702 Total UI for P1: 0, mck2ui 16
1297 14:44:02.991757 best dqsien dly found for B0: ( 0, 14, 8)
1298 14:44:02.991811 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1299 14:44:02.991865 Total UI for P1: 0, mck2ui 16
1300 14:44:02.991919 best dqsien dly found for B1: ( 0, 14, 8)
1301 14:44:02.991973 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1302 14:44:02.992027 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1303 14:44:02.992093
1304 14:44:02.992156 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 14:44:02.992211 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1306 14:44:02.992265 [Gating] SW calibration Done
1307 14:44:02.992319 ==
1308 14:44:02.992373 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 14:44:02.992427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 14:44:02.992481 ==
1311 14:44:02.992535 RX Vref Scan: 0
1312 14:44:02.992588
1313 14:44:02.992665 RX Vref 0 -> 0, step: 1
1314 14:44:02.992721
1315 14:44:02.992775 RX Delay -130 -> 252, step: 16
1316 14:44:02.992829 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 14:44:02.992883 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1318 14:44:02.992937 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1319 14:44:02.992991 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 14:44:02.993044 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 14:44:02.993098 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 14:44:02.993171 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1323 14:44:02.993232 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1324 14:44:02.993286 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1325 14:44:02.993340 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1326 14:44:02.993394 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 14:44:02.993447 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 14:44:02.993501 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 14:44:02.993554 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 14:44:02.993608 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 14:44:02.993676 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1332 14:44:02.993736 ==
1333 14:44:02.993791 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 14:44:02.993845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 14:44:02.993900 ==
1336 14:44:02.993954 DQS Delay:
1337 14:44:02.994007 DQS0 = 0, DQS1 = 0
1338 14:44:02.994060 DQM Delay:
1339 14:44:02.994114 DQM0 = 87, DQM1 = 76
1340 14:44:02.994191 DQ Delay:
1341 14:44:02.994255 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1342 14:44:02.994310 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1343 14:44:02.994365 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1344 14:44:02.994418 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1345 14:44:02.994472
1346 14:44:02.994526
1347 14:44:02.994579 ==
1348 14:44:02.994632 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 14:44:02.994694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 14:44:02.994761 ==
1351 14:44:02.994816
1352 14:44:02.994869
1353 14:44:02.994922 TX Vref Scan disable
1354 14:44:02.994976 == TX Byte 0 ==
1355 14:44:02.995030 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1356 14:44:02.995084 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1357 14:44:02.995138 == TX Byte 1 ==
1358 14:44:02.995192 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 14:44:02.995269 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 14:44:02.995326 ==
1361 14:44:02.995380 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 14:44:02.995433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 14:44:02.995488 ==
1364 14:44:02.995541 TX Vref=22, minBit 3, minWin=27, winSum=444
1365 14:44:02.995596 TX Vref=24, minBit 5, minWin=27, winSum=443
1366 14:44:02.995649 TX Vref=26, minBit 3, minWin=27, winSum=448
1367 14:44:02.995703 TX Vref=28, minBit 8, minWin=27, winSum=447
1368 14:44:02.995772 TX Vref=30, minBit 0, minWin=28, winSum=451
1369 14:44:02.995832 TX Vref=32, minBit 5, minWin=27, winSum=447
1370 14:44:02.995886 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1371 14:44:02.995941
1372 14:44:02.995994 Final TX Range 1 Vref 30
1373 14:44:02.996047
1374 14:44:02.996100 ==
1375 14:44:02.996153 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 14:44:02.996207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 14:44:02.996268 ==
1378 14:44:02.996335
1379 14:44:02.996389
1380 14:44:02.996442 TX Vref Scan disable
1381 14:44:02.996495 == TX Byte 0 ==
1382 14:44:02.996548 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1383 14:44:02.996602 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1384 14:44:02.996655 == TX Byte 1 ==
1385 14:44:02.996905 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1386 14:44:02.996967 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1387 14:44:02.997022
1388 14:44:02.997075 [DATLAT]
1389 14:44:02.997129 Freq=800, CH0 RK1
1390 14:44:02.997183
1391 14:44:02.997236 DATLAT Default: 0xa
1392 14:44:02.997289 0, 0xFFFF, sum = 0
1393 14:44:02.997363 1, 0xFFFF, sum = 0
1394 14:44:02.997424 2, 0xFFFF, sum = 0
1395 14:44:02.997479 3, 0xFFFF, sum = 0
1396 14:44:02.997533 4, 0xFFFF, sum = 0
1397 14:44:02.997586 5, 0xFFFF, sum = 0
1398 14:44:02.997640 6, 0xFFFF, sum = 0
1399 14:44:02.997693 7, 0xFFFF, sum = 0
1400 14:44:02.997747 8, 0xFFFF, sum = 0
1401 14:44:02.997800 9, 0x0, sum = 1
1402 14:44:02.997868 10, 0x0, sum = 2
1403 14:44:02.997930 11, 0x0, sum = 3
1404 14:44:02.997985 12, 0x0, sum = 4
1405 14:44:02.998039 best_step = 10
1406 14:44:02.998092
1407 14:44:02.998144 ==
1408 14:44:02.998207 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 14:44:02.998261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 14:44:02.998314 ==
1411 14:44:02.998376 RX Vref Scan: 0
1412 14:44:02.998443
1413 14:44:02.998496 RX Vref 0 -> 0, step: 1
1414 14:44:02.998549
1415 14:44:02.998602 RX Delay -111 -> 252, step: 8
1416 14:44:02.998655 iDelay=217, Bit 0, Center 80 (-31 ~ 192) 224
1417 14:44:02.998708 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1418 14:44:02.998761 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1419 14:44:02.998814 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1420 14:44:02.998867 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1421 14:44:02.998943 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1422 14:44:02.998999 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1423 14:44:02.999052 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1424 14:44:02.999105 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1425 14:44:02.999157 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1426 14:44:02.999210 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1427 14:44:02.999263 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1428 14:44:02.999315 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1429 14:44:02.999368 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1430 14:44:02.999444 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1431 14:44:02.999500 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1432 14:44:02.999554 ==
1433 14:44:02.999607 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 14:44:02.999660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 14:44:02.999714 ==
1436 14:44:02.999767 DQS Delay:
1437 14:44:02.999819 DQS0 = 0, DQS1 = 0
1438 14:44:02.999872 DQM Delay:
1439 14:44:02.999938 DQM0 = 85, DQM1 = 77
1440 14:44:02.999999 DQ Delay:
1441 14:44:03.000053 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =80
1442 14:44:03.000107 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =100
1443 14:44:03.000160 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1444 14:44:03.000215 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 14:44:03.000268
1446 14:44:03.000321
1447 14:44:03.000374 [DQSOSCAuto] RK1, (LSB)MR18= 0x430a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1448 14:44:03.000428 CH0 RK1: MR19=606, MR18=430A
1449 14:44:03.000505 CH0_RK1: MR19=0x606, MR18=0x430A, DQSOSC=393, MR23=63, INC=95, DEC=63
1450 14:44:03.000561 [RxdqsGatingPostProcess] freq 800
1451 14:44:03.000615 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 14:44:03.000668 Pre-setting of DQS Precalculation
1453 14:44:03.000721 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 14:44:03.000774 ==
1455 14:44:03.000827 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 14:44:03.000881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 14:44:03.000935 ==
1458 14:44:03.001008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 14:44:03.001066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 14:44:03.001120 [CA 0] Center 36 (6~67) winsize 62
1461 14:44:03.001173 [CA 1] Center 37 (6~68) winsize 63
1462 14:44:03.001226 [CA 2] Center 34 (4~65) winsize 62
1463 14:44:03.001279 [CA 3] Center 34 (3~65) winsize 63
1464 14:44:03.001332 [CA 4] Center 34 (4~65) winsize 62
1465 14:44:03.001385 [CA 5] Center 34 (4~65) winsize 62
1466 14:44:03.001438
1467 14:44:03.001505 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 14:44:03.001566
1469 14:44:03.001620 [CATrainingPosCal] consider 1 rank data
1470 14:44:03.001673 u2DelayCellTimex100 = 270/100 ps
1471 14:44:03.001727 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 14:44:03.001781 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1473 14:44:03.001833 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 14:44:03.001886 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 14:44:03.001939 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 14:44:03.001992 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 14:44:03.002084
1478 14:44:03.002173 CA PerBit enable=1, Macro0, CA PI delay=34
1479 14:44:03.002231
1480 14:44:03.002284 [CBTSetCACLKResult] CA Dly = 34
1481 14:44:03.002337 CS Dly: 5 (0~36)
1482 14:44:03.002392 ==
1483 14:44:03.002446 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 14:44:03.002499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 14:44:03.002578 ==
1486 14:44:03.002633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 14:44:03.002687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 14:44:03.002741 [CA 0] Center 36 (6~67) winsize 62
1489 14:44:03.002794 [CA 1] Center 37 (6~68) winsize 63
1490 14:44:03.002847 [CA 2] Center 34 (4~65) winsize 62
1491 14:44:03.002900 [CA 3] Center 34 (4~65) winsize 62
1492 14:44:03.002952 [CA 4] Center 34 (4~65) winsize 62
1493 14:44:03.003005 [CA 5] Center 33 (3~64) winsize 62
1494 14:44:03.003079
1495 14:44:03.003137 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1496 14:44:03.003191
1497 14:44:03.003244 [CATrainingPosCal] consider 2 rank data
1498 14:44:03.003297 u2DelayCellTimex100 = 270/100 ps
1499 14:44:03.003350 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 14:44:03.003403 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1501 14:44:03.003456 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 14:44:03.003509 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1503 14:44:03.003575 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 14:44:03.003635 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1505 14:44:03.003689
1506 14:44:03.003742 CA PerBit enable=1, Macro0, CA PI delay=34
1507 14:44:03.003795
1508 14:44:03.003847 [CBTSetCACLKResult] CA Dly = 34
1509 14:44:03.003900 CS Dly: 6 (0~38)
1510 14:44:03.003952
1511 14:44:03.004005 ----->DramcWriteLeveling(PI) begin...
1512 14:44:03.004059 ==
1513 14:44:03.004134 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 14:44:03.004190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 14:44:03.004244 ==
1516 14:44:03.004297 Write leveling (Byte 0): 25 => 25
1517 14:44:03.004350 Write leveling (Byte 1): 29 => 29
1518 14:44:03.004604 DramcWriteLeveling(PI) end<-----
1519 14:44:03.004676
1520 14:44:03.004732 ==
1521 14:44:03.004786 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 14:44:03.004841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 14:44:03.004896 ==
1524 14:44:03.004950 [Gating] SW mode calibration
1525 14:44:03.005005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 14:44:03.005060 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 14:44:03.005127 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1528 14:44:03.005189 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1529 14:44:03.005244 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 14:44:03.005297 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 14:44:03.005351 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 14:44:03.005404 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 14:44:03.005457 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 14:44:03.005511 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 14:44:03.005564 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 14:44:03.005621 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 14:44:03.005691 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 14:44:03.005746 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 14:44:03.005799 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 14:44:03.005852 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 14:44:03.005905 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 14:44:03.005958 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 14:44:03.006012 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1544 14:44:03.006065 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1545 14:44:03.006119 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1546 14:44:03.006207 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 14:44:03.006263 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 14:44:03.006317 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 14:44:03.006371 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 14:44:03.006424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 14:44:03.006478 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 14:44:03.006530 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 14:44:03.006584 0 9 8 | B1->B0 | 2c2b 2e2e | 1 1 | (0 0) (1 1)
1554 14:44:03.006637 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 14:44:03.006715 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 14:44:03.006771 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 14:44:03.006826 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 14:44:03.006880 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 14:44:03.006933 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1560 14:44:03.006986 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1561 14:44:03.007040 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1562 14:44:03.007094 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 14:44:03.007148 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 14:44:03.007224 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 14:44:03.007281 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 14:44:03.007335 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 14:44:03.007388 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 14:44:03.007441 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (1 1)
1569 14:44:03.007495 0 11 8 | B1->B0 | 3939 3b3b | 1 0 | (0 0) (0 0)
1570 14:44:03.007548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 14:44:03.007601 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 14:44:03.007654 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 14:44:03.007722 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 14:44:03.007781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 14:44:03.007835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 14:44:03.007888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 14:44:03.007942 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1578 14:44:03.007994 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 14:44:03.008048 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 14:44:03.008101 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 14:44:03.008153 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 14:44:03.008207 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 14:44:03.008283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 14:44:03.008338 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 14:44:03.008392 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 14:44:03.008446 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 14:44:03.008499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 14:44:03.008552 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 14:44:03.008605 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 14:44:03.008659 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 14:44:03.008713 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 14:44:03.008790 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1593 14:44:03.008845 Total UI for P1: 0, mck2ui 16
1594 14:44:03.008900 best dqsien dly found for B0: ( 0, 14, 2)
1595 14:44:03.008954 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1596 14:44:03.009008 Total UI for P1: 0, mck2ui 16
1597 14:44:03.009062 best dqsien dly found for B1: ( 0, 14, 4)
1598 14:44:03.009116 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1599 14:44:03.009170 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1600 14:44:03.009222
1601 14:44:03.009298 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1602 14:44:03.009354 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1603 14:44:03.009408 [Gating] SW calibration Done
1604 14:44:03.009462 ==
1605 14:44:03.009515 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 14:44:03.009761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 14:44:03.009844 ==
1608 14:44:03.009900 RX Vref Scan: 0
1609 14:44:03.009955
1610 14:44:03.010008 RX Vref 0 -> 0, step: 1
1611 14:44:03.010061
1612 14:44:03.010114 RX Delay -130 -> 252, step: 16
1613 14:44:03.010185 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1614 14:44:03.010241 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1615 14:44:03.010301 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1616 14:44:03.010370 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1617 14:44:03.010425 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1618 14:44:03.010478 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1619 14:44:03.010532 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1620 14:44:03.010585 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1621 14:44:03.010639 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1622 14:44:03.010691 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1623 14:44:03.010744 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1624 14:44:03.010796 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1625 14:44:03.010873 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1626 14:44:03.010928 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1627 14:44:03.010981 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1628 14:44:03.011035 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1629 14:44:03.011087 ==
1630 14:44:03.011140 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 14:44:03.011194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 14:44:03.011248 ==
1633 14:44:03.011301 DQS Delay:
1634 14:44:03.011362 DQS0 = 0, DQS1 = 0
1635 14:44:03.011428 DQM Delay:
1636 14:44:03.011482 DQM0 = 89, DQM1 = 79
1637 14:44:03.011535 DQ Delay:
1638 14:44:03.011589 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1639 14:44:03.011643 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1640 14:44:03.011696 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1641 14:44:03.011749 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1642 14:44:03.011802
1643 14:44:03.011855
1644 14:44:03.011930 ==
1645 14:44:03.011985 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 14:44:03.012038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 14:44:03.012091 ==
1648 14:44:03.012144
1649 14:44:03.012196
1650 14:44:03.012249 TX Vref Scan disable
1651 14:44:03.012302 == TX Byte 0 ==
1652 14:44:03.012355 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1653 14:44:03.012426 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1654 14:44:03.012485 == TX Byte 1 ==
1655 14:44:03.012540 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1656 14:44:03.012593 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1657 14:44:03.012646 ==
1658 14:44:03.012699 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 14:44:03.012752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 14:44:03.012806 ==
1661 14:44:03.012859 TX Vref=22, minBit 10, minWin=26, winSum=442
1662 14:44:03.012926 TX Vref=24, minBit 8, minWin=27, winSum=445
1663 14:44:03.012988 TX Vref=26, minBit 9, minWin=27, winSum=448
1664 14:44:03.013042 TX Vref=28, minBit 9, minWin=27, winSum=446
1665 14:44:03.013095 TX Vref=30, minBit 10, minWin=27, winSum=447
1666 14:44:03.013148 TX Vref=32, minBit 15, minWin=26, winSum=446
1667 14:44:03.013201 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1668 14:44:03.013255
1669 14:44:03.013309 Final TX Range 1 Vref 26
1670 14:44:03.013363
1671 14:44:03.013420 ==
1672 14:44:03.013489 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 14:44:03.013544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 14:44:03.013598 ==
1675 14:44:03.013651
1676 14:44:03.013704
1677 14:44:03.013757 TX Vref Scan disable
1678 14:44:03.013810 == TX Byte 0 ==
1679 14:44:03.013863 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1680 14:44:03.013916 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1681 14:44:03.013996 == TX Byte 1 ==
1682 14:44:03.014081 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1683 14:44:03.014168 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1684 14:44:03.014225
1685 14:44:03.014278 [DATLAT]
1686 14:44:03.014331 Freq=800, CH1 RK0
1687 14:44:03.014385
1688 14:44:03.014438 DATLAT Default: 0xa
1689 14:44:03.014514 0, 0xFFFF, sum = 0
1690 14:44:03.014572 1, 0xFFFF, sum = 0
1691 14:44:03.014628 2, 0xFFFF, sum = 0
1692 14:44:03.014682 3, 0xFFFF, sum = 0
1693 14:44:03.014737 4, 0xFFFF, sum = 0
1694 14:44:03.014791 5, 0xFFFF, sum = 0
1695 14:44:03.014846 6, 0xFFFF, sum = 0
1696 14:44:03.014899 7, 0xFFFF, sum = 0
1697 14:44:03.014953 8, 0xFFFF, sum = 0
1698 14:44:03.015021 9, 0x0, sum = 1
1699 14:44:03.015082 10, 0x0, sum = 2
1700 14:44:03.015136 11, 0x0, sum = 3
1701 14:44:03.015190 12, 0x0, sum = 4
1702 14:44:03.015243 best_step = 10
1703 14:44:03.015295
1704 14:44:03.015348 ==
1705 14:44:03.015401 Dram Type= 6, Freq= 0, CH_1, rank 0
1706 14:44:03.015455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1707 14:44:03.015509 ==
1708 14:44:03.015586 RX Vref Scan: 1
1709 14:44:03.015641
1710 14:44:03.015694 Set Vref Range= 32 -> 127
1711 14:44:03.015747
1712 14:44:03.015800 RX Vref 32 -> 127, step: 1
1713 14:44:03.015852
1714 14:44:03.015906 RX Delay -95 -> 252, step: 8
1715 14:44:03.015960
1716 14:44:03.016013 Set Vref, RX VrefLevel [Byte0]: 32
1717 14:44:03.016084 [Byte1]: 32
1718 14:44:03.016143
1719 14:44:03.016196 Set Vref, RX VrefLevel [Byte0]: 33
1720 14:44:03.016249 [Byte1]: 33
1721 14:44:03.016302
1722 14:44:03.016354 Set Vref, RX VrefLevel [Byte0]: 34
1723 14:44:03.016407 [Byte1]: 34
1724 14:44:03.016460
1725 14:44:03.016512 Set Vref, RX VrefLevel [Byte0]: 35
1726 14:44:03.016567 [Byte1]: 35
1727 14:44:03.016639
1728 14:44:03.016692 Set Vref, RX VrefLevel [Byte0]: 36
1729 14:44:03.016746 [Byte1]: 36
1730 14:44:03.016798
1731 14:44:03.016850 Set Vref, RX VrefLevel [Byte0]: 37
1732 14:44:03.016903 [Byte1]: 37
1733 14:44:03.016956
1734 14:44:03.017008 Set Vref, RX VrefLevel [Byte0]: 38
1735 14:44:03.017062 [Byte1]: 38
1736 14:44:03.017129
1737 14:44:03.017188 Set Vref, RX VrefLevel [Byte0]: 39
1738 14:44:03.017241 [Byte1]: 39
1739 14:44:03.017294
1740 14:44:03.017347 Set Vref, RX VrefLevel [Byte0]: 40
1741 14:44:03.017400 [Byte1]: 40
1742 14:44:03.017452
1743 14:44:03.017505 Set Vref, RX VrefLevel [Byte0]: 41
1744 14:44:03.017558 [Byte1]: 41
1745 14:44:03.017611
1746 14:44:03.017685 Set Vref, RX VrefLevel [Byte0]: 42
1747 14:44:03.017740 [Byte1]: 42
1748 14:44:03.017793
1749 14:44:03.017846 Set Vref, RX VrefLevel [Byte0]: 43
1750 14:44:03.017899 [Byte1]: 43
1751 14:44:03.017952
1752 14:44:03.018005 Set Vref, RX VrefLevel [Byte0]: 44
1753 14:44:03.018058 [Byte1]: 44
1754 14:44:03.018111
1755 14:44:03.018186 Set Vref, RX VrefLevel [Byte0]: 45
1756 14:44:03.018246 [Byte1]: 45
1757 14:44:03.018301
1758 14:44:03.018355 Set Vref, RX VrefLevel [Byte0]: 46
1759 14:44:03.018408 [Byte1]: 46
1760 14:44:03.018461
1761 14:44:03.018514 Set Vref, RX VrefLevel [Byte0]: 47
1762 14:44:03.018764 [Byte1]: 47
1763 14:44:03.018827
1764 14:44:03.018882 Set Vref, RX VrefLevel [Byte0]: 48
1765 14:44:03.018937 [Byte1]: 48
1766 14:44:03.018991
1767 14:44:03.019044 Set Vref, RX VrefLevel [Byte0]: 49
1768 14:44:03.019097 [Byte1]: 49
1769 14:44:03.019151
1770 14:44:03.019228 Set Vref, RX VrefLevel [Byte0]: 50
1771 14:44:03.019285 [Byte1]: 50
1772 14:44:03.019339
1773 14:44:03.019391 Set Vref, RX VrefLevel [Byte0]: 51
1774 14:44:03.019444 [Byte1]: 51
1775 14:44:03.019498
1776 14:44:03.019551 Set Vref, RX VrefLevel [Byte0]: 52
1777 14:44:03.019604 [Byte1]: 52
1778 14:44:03.019657
1779 14:44:03.019733 Set Vref, RX VrefLevel [Byte0]: 53
1780 14:44:03.019790 [Byte1]: 53
1781 14:44:03.019844
1782 14:44:03.019898 Set Vref, RX VrefLevel [Byte0]: 54
1783 14:44:03.019952 [Byte1]: 54
1784 14:44:03.020005
1785 14:44:03.020058 Set Vref, RX VrefLevel [Byte0]: 55
1786 14:44:03.020111 [Byte1]: 55
1787 14:44:03.020164
1788 14:44:03.020224 Set Vref, RX VrefLevel [Byte0]: 56
1789 14:44:03.020291 [Byte1]: 56
1790 14:44:03.020346
1791 14:44:03.020399 Set Vref, RX VrefLevel [Byte0]: 57
1792 14:44:03.020452 [Byte1]: 57
1793 14:44:03.020505
1794 14:44:03.020558 Set Vref, RX VrefLevel [Byte0]: 58
1795 14:44:03.020612 [Byte1]: 58
1796 14:44:03.020665
1797 14:44:03.020717 Set Vref, RX VrefLevel [Byte0]: 59
1798 14:44:03.020793 [Byte1]: 59
1799 14:44:03.020850
1800 14:44:03.020903 Set Vref, RX VrefLevel [Byte0]: 60
1801 14:44:03.020956 [Byte1]: 60
1802 14:44:03.021009
1803 14:44:03.021062 Set Vref, RX VrefLevel [Byte0]: 61
1804 14:44:03.021115 [Byte1]: 61
1805 14:44:03.021168
1806 14:44:03.021221 Set Vref, RX VrefLevel [Byte0]: 62
1807 14:44:03.021284 [Byte1]: 62
1808 14:44:03.021349
1809 14:44:03.021403 Set Vref, RX VrefLevel [Byte0]: 63
1810 14:44:03.021456 [Byte1]: 63
1811 14:44:03.021509
1812 14:44:03.021562 Set Vref, RX VrefLevel [Byte0]: 64
1813 14:44:03.021615 [Byte1]: 64
1814 14:44:03.021668
1815 14:44:03.021721 Set Vref, RX VrefLevel [Byte0]: 65
1816 14:44:03.021773 [Byte1]: 65
1817 14:44:03.021851
1818 14:44:03.021935 Set Vref, RX VrefLevel [Byte0]: 66
1819 14:44:03.022019 [Byte1]: 66
1820 14:44:03.022101
1821 14:44:03.022187 Set Vref, RX VrefLevel [Byte0]: 67
1822 14:44:03.022243 [Byte1]: 67
1823 14:44:03.022297
1824 14:44:03.022374 Set Vref, RX VrefLevel [Byte0]: 68
1825 14:44:03.022430 [Byte1]: 68
1826 14:44:03.022484
1827 14:44:03.022538 Set Vref, RX VrefLevel [Byte0]: 69
1828 14:44:03.022591 [Byte1]: 69
1829 14:44:03.022644
1830 14:44:03.022697 Set Vref, RX VrefLevel [Byte0]: 70
1831 14:44:03.022751 [Byte1]: 70
1832 14:44:03.022804
1833 14:44:03.022868 Set Vref, RX VrefLevel [Byte0]: 71
1834 14:44:03.022930 [Byte1]: 71
1835 14:44:03.022984
1836 14:44:03.023037 Set Vref, RX VrefLevel [Byte0]: 72
1837 14:44:03.023090 [Byte1]: 72
1838 14:44:03.023143
1839 14:44:03.023196 Set Vref, RX VrefLevel [Byte0]: 73
1840 14:44:03.023249 [Byte1]: 73
1841 14:44:03.023303
1842 14:44:03.023356 Set Vref, RX VrefLevel [Byte0]: 74
1843 14:44:03.023431 [Byte1]: 74
1844 14:44:03.023488
1845 14:44:03.023541 Set Vref, RX VrefLevel [Byte0]: 75
1846 14:44:03.023595 [Byte1]: 75
1847 14:44:03.023647
1848 14:44:03.023700 Set Vref, RX VrefLevel [Byte0]: 76
1849 14:44:03.023753 [Byte1]: 76
1850 14:44:03.023806
1851 14:44:03.023859 Final RX Vref Byte 0 = 52 to rank0
1852 14:44:03.023933 Final RX Vref Byte 1 = 65 to rank0
1853 14:44:03.023992 Final RX Vref Byte 0 = 52 to rank1
1854 14:44:03.024046 Final RX Vref Byte 1 = 65 to rank1==
1855 14:44:03.024100 Dram Type= 6, Freq= 0, CH_1, rank 0
1856 14:44:03.024153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 14:44:03.024207 ==
1858 14:44:03.024260 DQS Delay:
1859 14:44:03.024313 DQS0 = 0, DQS1 = 0
1860 14:44:03.024366 DQM Delay:
1861 14:44:03.024433 DQM0 = 86, DQM1 = 78
1862 14:44:03.024494 DQ Delay:
1863 14:44:03.024547 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1864 14:44:03.024601 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1865 14:44:03.024655 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1866 14:44:03.024708 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1867 14:44:03.024761
1868 14:44:03.024814
1869 14:44:03.024866 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1870 14:44:03.024921 CH1 RK0: MR19=606, MR18=3622
1871 14:44:03.024997 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1872 14:44:03.025055
1873 14:44:03.025108 ----->DramcWriteLeveling(PI) begin...
1874 14:44:03.025163 ==
1875 14:44:03.025217 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 14:44:03.025270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 14:44:03.025324 ==
1878 14:44:03.025377 Write leveling (Byte 0): 25 => 25
1879 14:44:03.025430 Write leveling (Byte 1): 31 => 31
1880 14:44:03.025494 DramcWriteLeveling(PI) end<-----
1881 14:44:03.025557
1882 14:44:03.025612 ==
1883 14:44:03.025665 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 14:44:03.025718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 14:44:03.025772 ==
1886 14:44:03.025825 [Gating] SW mode calibration
1887 14:44:03.025879 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1888 14:44:03.025933 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1889 14:44:03.025987 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1890 14:44:03.026080 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1891 14:44:03.026169 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 14:44:03.026227 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 14:44:03.026281 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 14:44:03.026335 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 14:44:03.026389 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 14:44:03.026442 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 14:44:03.026495 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 14:44:03.026567 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 14:44:03.026625 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 14:44:03.026679 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 14:44:03.026733 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 14:44:03.026978 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 14:44:03.027038 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 14:44:03.027113 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 14:44:03.027172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 14:44:03.027225 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1907 14:44:03.027279 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1908 14:44:03.027332 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 14:44:03.027386 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 14:44:03.027439 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 14:44:03.027492 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 14:44:03.027545 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 14:44:03.027602 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 14:44:03.027686 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 14:44:03.027770 0 9 8 | B1->B0 | 2f2f 2424 | 0 1 | (0 0) (1 1)
1916 14:44:03.027854 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 14:44:03.027939 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 14:44:03.028023 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 14:44:03.028107 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 14:44:03.028203 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 14:44:03.028287 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 14:44:03.028371 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (0 1) (1 1)
1923 14:44:03.028454 0 10 8 | B1->B0 | 2929 2e2e | 0 1 | (0 0) (1 0)
1924 14:44:03.028538 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 14:44:03.028622 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 14:44:03.028718 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 14:44:03.028802 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 14:44:03.028886 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 14:44:03.028970 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 14:44:03.029053 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1931 14:44:03.029137 0 11 8 | B1->B0 | 4040 3838 | 0 0 | (1 1) (0 0)
1932 14:44:03.029227 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 14:44:03.029287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 14:44:03.029340 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 14:44:03.029393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 14:44:03.029446 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 14:44:03.029499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 14:44:03.029552 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1939 14:44:03.029605 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 14:44:03.029658 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 14:44:03.029712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 14:44:03.029807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 14:44:03.029891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 14:44:03.029975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 14:44:03.030059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 14:44:03.030142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 14:44:03.030221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 14:44:03.030298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 14:44:03.030355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 14:44:03.030410 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 14:44:03.030463 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 14:44:03.030517 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 14:44:03.030570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 14:44:03.030623 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1955 14:44:03.030677 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 14:44:03.030731 Total UI for P1: 0, mck2ui 16
1957 14:44:03.030795 best dqsien dly found for B0: ( 0, 14, 4)
1958 14:44:03.030860 Total UI for P1: 0, mck2ui 16
1959 14:44:03.030915 best dqsien dly found for B1: ( 0, 14, 4)
1960 14:44:03.030969 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1961 14:44:03.031022 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1962 14:44:03.031075
1963 14:44:03.031128 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 14:44:03.031181 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1965 14:44:03.031234 [Gating] SW calibration Done
1966 14:44:03.031287 ==
1967 14:44:03.031356 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 14:44:03.031443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 14:44:03.031526 ==
1970 14:44:03.031609 RX Vref Scan: 0
1971 14:44:03.031691
1972 14:44:03.031774 RX Vref 0 -> 0, step: 1
1973 14:44:03.031863
1974 14:44:03.031953 RX Delay -130 -> 252, step: 16
1975 14:44:03.032037 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1976 14:44:03.032120 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1977 14:44:03.032204 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1978 14:44:03.032288 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1979 14:44:03.032372 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1980 14:44:03.032468 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1981 14:44:03.032552 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1982 14:44:03.032635 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1983 14:44:03.032719 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1984 14:44:03.032802 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1985 14:44:03.032886 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1986 14:44:03.032981 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1987 14:44:03.033066 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1988 14:44:03.188423 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1989 14:44:03.188978 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1990 14:44:03.189388 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1991 14:44:03.189719 ==
1992 14:44:03.190189 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 14:44:03.190555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 14:44:03.190915 ==
1995 14:44:03.191291 DQS Delay:
1996 14:44:03.192017 DQS0 = 0, DQS1 = 0
1997 14:44:03.192351 DQM Delay:
1998 14:44:03.192755 DQM0 = 87, DQM1 = 78
1999 14:44:03.193081 DQ Delay:
2000 14:44:03.193428 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
2001 14:44:03.193766 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2002 14:44:03.194088 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2003 14:44:03.194516 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2004 14:44:03.194814
2005 14:44:03.195202
2006 14:44:03.195488 ==
2007 14:44:03.195881 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 14:44:03.196170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 14:44:03.196548 ==
2010 14:44:03.196862
2011 14:44:03.197194
2012 14:44:03.197502 TX Vref Scan disable
2013 14:44:03.197833 == TX Byte 0 ==
2014 14:44:03.198182 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2015 14:44:03.198499 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2016 14:44:03.198853 == TX Byte 1 ==
2017 14:44:03.199143 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2018 14:44:03.199493 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2019 14:44:03.199784 ==
2020 14:44:03.200132 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 14:44:03.200423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 14:44:03.200771 ==
2023 14:44:03.201064 TX Vref=22, minBit 1, minWin=27, winSum=443
2024 14:44:03.201417 TX Vref=24, minBit 1, minWin=27, winSum=444
2025 14:44:03.201710 TX Vref=26, minBit 1, minWin=27, winSum=445
2026 14:44:03.202098 TX Vref=28, minBit 1, minWin=27, winSum=448
2027 14:44:03.202434 TX Vref=30, minBit 8, minWin=27, winSum=451
2028 14:44:03.202820 TX Vref=32, minBit 8, minWin=27, winSum=450
2029 14:44:03.203105 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 30
2030 14:44:03.203487
2031 14:44:03.203782 Final TX Range 1 Vref 30
2032 14:44:03.204133
2033 14:44:03.204429 ==
2034 14:44:03.204764 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 14:44:03.205079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 14:44:03.205406 ==
2037 14:44:03.205721
2038 14:44:03.206039
2039 14:44:03.206426 TX Vref Scan disable
2040 14:44:03.206722 == TX Byte 0 ==
2041 14:44:03.207074 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2042 14:44:03.207370 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2043 14:44:03.207744 == TX Byte 1 ==
2044 14:44:03.208031 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2045 14:44:03.208416 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2046 14:44:03.208696
2047 14:44:03.209084 [DATLAT]
2048 14:44:03.209361 Freq=800, CH1 RK1
2049 14:44:03.209745
2050 14:44:03.210023 DATLAT Default: 0xa
2051 14:44:03.210430 0, 0xFFFF, sum = 0
2052 14:44:03.210772 1, 0xFFFF, sum = 0
2053 14:44:03.211089 2, 0xFFFF, sum = 0
2054 14:44:03.211444 3, 0xFFFF, sum = 0
2055 14:44:03.211759 4, 0xFFFF, sum = 0
2056 14:44:03.212144 5, 0xFFFF, sum = 0
2057 14:44:03.212437 6, 0xFFFF, sum = 0
2058 14:44:03.212795 7, 0xFFFF, sum = 0
2059 14:44:03.212998 8, 0xFFFF, sum = 0
2060 14:44:03.213210 9, 0x0, sum = 1
2061 14:44:03.213461 10, 0x0, sum = 2
2062 14:44:03.213658 11, 0x0, sum = 3
2063 14:44:03.213910 12, 0x0, sum = 4
2064 14:44:03.214119 best_step = 10
2065 14:44:03.214350
2066 14:44:03.214624 ==
2067 14:44:03.214824 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 14:44:03.215060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 14:44:03.215284 ==
2070 14:44:03.215479 RX Vref Scan: 0
2071 14:44:03.215746
2072 14:44:03.215951 RX Vref 0 -> 0, step: 1
2073 14:44:03.216146
2074 14:44:03.216422 RX Delay -95 -> 252, step: 8
2075 14:44:03.216624 iDelay=217, Bit 0, Center 92 (-15 ~ 200) 216
2076 14:44:03.216865 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2077 14:44:03.217085 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2078 14:44:03.217281 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2079 14:44:03.217559 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2080 14:44:03.217759 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2081 14:44:03.217907 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2082 14:44:03.218134 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2083 14:44:03.218314 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2084 14:44:03.218461 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2085 14:44:03.218652 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2086 14:44:03.218810 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2087 14:44:03.218955 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2088 14:44:03.219100 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2089 14:44:03.219310 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2090 14:44:03.219461 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2091 14:44:03.219607 ==
2092 14:44:03.219783 Dram Type= 6, Freq= 0, CH_1, rank 1
2093 14:44:03.219952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2094 14:44:03.220101 ==
2095 14:44:03.220246 DQS Delay:
2096 14:44:03.220445 DQS0 = 0, DQS1 = 0
2097 14:44:03.220599 DQM Delay:
2098 14:44:03.220746 DQM0 = 87, DQM1 = 78
2099 14:44:03.220891 DQ Delay:
2100 14:44:03.221099 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2101 14:44:03.221250 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2102 14:44:03.221396 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
2103 14:44:03.221580 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2104 14:44:03.221742
2105 14:44:03.221888
2106 14:44:03.222033 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2107 14:44:03.222257 CH1 RK1: MR19=606, MR18=1A13
2108 14:44:03.222413 CH1_RK1: MR19=0x606, MR18=0x1A13, DQSOSC=403, MR23=63, INC=90, DEC=60
2109 14:44:03.222561 [RxdqsGatingPostProcess] freq 800
2110 14:44:03.222733 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2111 14:44:03.222884 Pre-setting of DQS Precalculation
2112 14:44:03.223002 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2113 14:44:03.223121 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2114 14:44:03.223239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2115 14:44:03.223407
2116 14:44:03.223529
2117 14:44:03.223644 [Calibration Summary] 1600 Mbps
2118 14:44:03.223762 CH 0, Rank 0
2119 14:44:03.223907 SW Impedance : PASS
2120 14:44:03.224040 DUTY Scan : NO K
2121 14:44:03.224158 ZQ Calibration : PASS
2122 14:44:03.224276 Jitter Meter : NO K
2123 14:44:03.224393 CBT Training : PASS
2124 14:44:03.224559 Write leveling : PASS
2125 14:44:03.224681 RX DQS gating : PASS
2126 14:44:03.224799 RX DQ/DQS(RDDQC) : PASS
2127 14:44:03.224915 TX DQ/DQS : PASS
2128 14:44:03.225063 RX DATLAT : PASS
2129 14:44:03.225193 RX DQ/DQS(Engine): PASS
2130 14:44:03.225309 TX OE : NO K
2131 14:44:03.225428 All Pass.
2132 14:44:03.225544
2133 14:44:03.225710 CH 0, Rank 1
2134 14:44:03.225831 SW Impedance : PASS
2135 14:44:03.225950 DUTY Scan : NO K
2136 14:44:03.226067 ZQ Calibration : PASS
2137 14:44:03.226238 Jitter Meter : NO K
2138 14:44:03.226366 CBT Training : PASS
2139 14:44:03.226484 Write leveling : PASS
2140 14:44:03.226602 RX DQS gating : PASS
2141 14:44:03.226722 RX DQ/DQS(RDDQC) : PASS
2142 14:44:03.226881 TX DQ/DQS : PASS
2143 14:44:03.227257 RX DATLAT : PASS
2144 14:44:03.227438 RX DQ/DQS(Engine): PASS
2145 14:44:03.227563 TX OE : NO K
2146 14:44:03.227696 All Pass.
2147 14:44:03.227796
2148 14:44:03.227931 CH 1, Rank 0
2149 14:44:03.228035 SW Impedance : PASS
2150 14:44:03.228136 DUTY Scan : NO K
2151 14:44:03.228235 ZQ Calibration : PASS
2152 14:44:03.228333 Jitter Meter : NO K
2153 14:44:03.228467 CBT Training : PASS
2154 14:44:03.228572 Write leveling : PASS
2155 14:44:03.228670 RX DQS gating : PASS
2156 14:44:03.228766 RX DQ/DQS(RDDQC) : PASS
2157 14:44:03.228863 TX DQ/DQS : PASS
2158 14:44:03.228982 RX DATLAT : PASS
2159 14:44:03.229096 RX DQ/DQS(Engine): PASS
2160 14:44:03.229193 TX OE : NO K
2161 14:44:03.229292 All Pass.
2162 14:44:03.229389
2163 14:44:03.229487 CH 1, Rank 1
2164 14:44:03.229620 SW Impedance : PASS
2165 14:44:03.229720 DUTY Scan : NO K
2166 14:44:03.229818 ZQ Calibration : PASS
2167 14:44:03.229916 Jitter Meter : NO K
2168 14:44:03.230013 CBT Training : PASS
2169 14:44:03.230194 Write leveling : PASS
2170 14:44:03.230300 RX DQS gating : PASS
2171 14:44:03.230400 RX DQ/DQS(RDDQC) : PASS
2172 14:44:03.230497 TX DQ/DQS : PASS
2173 14:44:03.230616 RX DATLAT : PASS
2174 14:44:03.230728 RX DQ/DQS(Engine): PASS
2175 14:44:03.230826 TX OE : NO K
2176 14:44:03.230924 All Pass.
2177 14:44:03.231021
2178 14:44:03.231121 DramC Write-DBI off
2179 14:44:03.231254 PER_BANK_REFRESH: Hybrid Mode
2180 14:44:03.231354 TX_TRACKING: ON
2181 14:44:03.231452 [GetDramInforAfterCalByMRR] Vendor 6.
2182 14:44:03.231550 [GetDramInforAfterCalByMRR] Revision 606.
2183 14:44:03.231648 [GetDramInforAfterCalByMRR] Revision 2 0.
2184 14:44:03.231788 MR0 0x3b3b
2185 14:44:03.231888 MR8 0x5151
2186 14:44:03.231986 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 14:44:03.232084
2188 14:44:03.232180 MR0 0x3b3b
2189 14:44:03.232319 MR8 0x5151
2190 14:44:03.232420 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 14:44:03.232518
2192 14:44:03.232616 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2193 14:44:03.232722 [FAST_K] Save calibration result to emmc
2194 14:44:03.232839 [FAST_K] Save calibration result to emmc
2195 14:44:03.232928 dram_init: config_dvfs: 1
2196 14:44:03.233012 dramc_set_vcore_voltage set vcore to 662500
2197 14:44:03.233096 Read voltage for 1200, 2
2198 14:44:03.233179 Vio18 = 0
2199 14:44:03.233262 Vcore = 662500
2200 14:44:03.233368 Vdram = 0
2201 14:44:03.233459 Vddq = 0
2202 14:44:03.233542 Vmddr = 0
2203 14:44:03.233626 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2204 14:44:03.233710 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2205 14:44:03.233794 MEM_TYPE=3, freq_sel=15
2206 14:44:03.233898 sv_algorithm_assistance_LP4_1600
2207 14:44:03.234034 ============ PULL DRAM RESETB DOWN ============
2208 14:44:03.234178 ========== PULL DRAM RESETB DOWN end =========
2209 14:44:03.234314 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2210 14:44:03.234462 ===================================
2211 14:44:03.234596 LPDDR4 DRAM CONFIGURATION
2212 14:44:03.234727 ===================================
2213 14:44:03.234857 EX_ROW_EN[0] = 0x0
2214 14:44:03.235003 EX_ROW_EN[1] = 0x0
2215 14:44:03.235137 LP4Y_EN = 0x0
2216 14:44:03.235268 WORK_FSP = 0x0
2217 14:44:03.235398 WL = 0x4
2218 14:44:03.235544 RL = 0x4
2219 14:44:03.235677 BL = 0x2
2220 14:44:03.235806 RPST = 0x0
2221 14:44:03.235935 RD_PRE = 0x0
2222 14:44:03.236082 WR_PRE = 0x1
2223 14:44:03.236215 WR_PST = 0x0
2224 14:44:03.236344 DBI_WR = 0x0
2225 14:44:03.236474 DBI_RD = 0x0
2226 14:44:03.236615 OTF = 0x1
2227 14:44:03.236710 ===================================
2228 14:44:03.236795 ===================================
2229 14:44:03.236880 ANA top config
2230 14:44:03.236963 ===================================
2231 14:44:03.237046 DLL_ASYNC_EN = 0
2232 14:44:03.237153 ALL_SLAVE_EN = 0
2233 14:44:03.237247 NEW_RANK_MODE = 1
2234 14:44:03.237332 DLL_IDLE_MODE = 1
2235 14:44:03.237416 LP45_APHY_COMB_EN = 1
2236 14:44:03.237499 TX_ODT_DIS = 1
2237 14:44:03.237583 NEW_8X_MODE = 1
2238 14:44:03.237696 ===================================
2239 14:44:03.237778 ===================================
2240 14:44:03.237852 data_rate = 2400
2241 14:44:03.237925 CKR = 1
2242 14:44:03.237998 DQ_P2S_RATIO = 8
2243 14:44:03.238071 ===================================
2244 14:44:03.238145 CA_P2S_RATIO = 8
2245 14:44:03.238256 DQ_CA_OPEN = 0
2246 14:44:03.238334 DQ_SEMI_OPEN = 0
2247 14:44:03.238408 CA_SEMI_OPEN = 0
2248 14:44:03.238482 CA_FULL_RATE = 0
2249 14:44:03.238556 DQ_CKDIV4_EN = 0
2250 14:44:03.238629 CA_CKDIV4_EN = 0
2251 14:44:03.238702 CA_PREDIV_EN = 0
2252 14:44:03.238806 PH8_DLY = 17
2253 14:44:03.238883 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2254 14:44:03.238957 DQ_AAMCK_DIV = 4
2255 14:44:03.239031 CA_AAMCK_DIV = 4
2256 14:44:03.239104 CA_ADMCK_DIV = 4
2257 14:44:03.239177 DQ_TRACK_CA_EN = 0
2258 14:44:03.239250 CA_PICK = 1200
2259 14:44:03.239375 CA_MCKIO = 1200
2260 14:44:03.239490 MCKIO_SEMI = 0
2261 14:44:03.239605 PLL_FREQ = 2366
2262 14:44:03.239719 DQ_UI_PI_RATIO = 32
2263 14:44:03.239847 CA_UI_PI_RATIO = 0
2264 14:44:03.239965 ===================================
2265 14:44:03.240080 ===================================
2266 14:44:03.240195 memory_type:LPDDR4
2267 14:44:03.240310 GP_NUM : 10
2268 14:44:03.240427 SRAM_EN : 1
2269 14:44:03.240506 MD32_EN : 0
2270 14:44:03.240580 ===================================
2271 14:44:03.240654 [ANA_INIT] >>>>>>>>>>>>>>
2272 14:44:03.240727 <<<<<< [CONFIGURE PHASE]: ANA_TX
2273 14:44:03.240801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2274 14:44:03.240874 ===================================
2275 14:44:03.240980 data_rate = 2400,PCW = 0X5b00
2276 14:44:03.241056 ===================================
2277 14:44:03.241129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2278 14:44:03.241203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 14:44:03.241277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 14:44:03.241351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2281 14:44:03.241432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2282 14:44:03.241527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2283 14:44:03.241602 [ANA_INIT] flow start
2284 14:44:03.241884 [ANA_INIT] PLL >>>>>>>>
2285 14:44:03.241980 [ANA_INIT] PLL <<<<<<<<
2286 14:44:03.242104 [ANA_INIT] MIDPI >>>>>>>>
2287 14:44:03.242219 [ANA_INIT] MIDPI <<<<<<<<
2288 14:44:03.242296 [ANA_INIT] DLL >>>>>>>>
2289 14:44:03.242371 [ANA_INIT] DLL <<<<<<<<
2290 14:44:03.242443 [ANA_INIT] flow end
2291 14:44:03.242548 ============ LP4 DIFF to SE enter ============
2292 14:44:03.242628 ============ LP4 DIFF to SE exit ============
2293 14:44:03.242714 [ANA_INIT] <<<<<<<<<<<<<
2294 14:44:03.242780 [Flow] Enable top DCM control >>>>>
2295 14:44:03.242846 [Flow] Enable top DCM control <<<<<
2296 14:44:03.242912 Enable DLL master slave shuffle
2297 14:44:03.242977 ==============================================================
2298 14:44:03.243070 Gating Mode config
2299 14:44:03.243140 ==============================================================
2300 14:44:03.243206 Config description:
2301 14:44:03.243271 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2302 14:44:03.243339 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2303 14:44:03.243405 SELPH_MODE 0: By rank 1: By Phase
2304 14:44:03.243471 ==============================================================
2305 14:44:03.243538 GAT_TRACK_EN = 1
2306 14:44:03.243629 RX_GATING_MODE = 2
2307 14:44:03.243696 RX_GATING_TRACK_MODE = 2
2308 14:44:03.243761 SELPH_MODE = 1
2309 14:44:03.243827 PICG_EARLY_EN = 1
2310 14:44:03.243893 VALID_LAT_VALUE = 1
2311 14:44:03.243958 ==============================================================
2312 14:44:03.244024 Enter into Gating configuration >>>>
2313 14:44:03.244107 Exit from Gating configuration <<<<
2314 14:44:03.244214 Enter into DVFS_PRE_config >>>>>
2315 14:44:03.244319 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2316 14:44:03.244422 Exit from DVFS_PRE_config <<<<<
2317 14:44:03.244524 Enter into PICG configuration >>>>
2318 14:44:03.244637 Exit from PICG configuration <<<<
2319 14:44:03.244744 [RX_INPUT] configuration >>>>>
2320 14:44:03.244845 [RX_INPUT] configuration <<<<<
2321 14:44:03.244948 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2322 14:44:03.245051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2323 14:44:03.245165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 14:44:03.245240 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 14:44:03.245307 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 14:44:03.245373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 14:44:03.245439 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2328 14:44:03.245505 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2329 14:44:03.245571 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2330 14:44:03.245637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2331 14:44:03.245739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2332 14:44:03.245843 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 14:44:03.245945 ===================================
2334 14:44:03.246046 LPDDR4 DRAM CONFIGURATION
2335 14:44:03.246148 ===================================
2336 14:44:03.246258 EX_ROW_EN[0] = 0x0
2337 14:44:03.246327 EX_ROW_EN[1] = 0x0
2338 14:44:03.246393 LP4Y_EN = 0x0
2339 14:44:03.246459 WORK_FSP = 0x0
2340 14:44:03.246524 WL = 0x4
2341 14:44:03.246589 RL = 0x4
2342 14:44:03.246654 BL = 0x2
2343 14:44:03.246719 RPST = 0x0
2344 14:44:03.246827 RD_PRE = 0x0
2345 14:44:03.246929 WR_PRE = 0x1
2346 14:44:03.247030 WR_PST = 0x0
2347 14:44:03.247131 DBI_WR = 0x0
2348 14:44:03.247231 DBI_RD = 0x0
2349 14:44:03.247347 OTF = 0x1
2350 14:44:03.247451 ===================================
2351 14:44:03.247553 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2352 14:44:03.247667 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2353 14:44:03.247760 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2354 14:44:03.247866 ===================================
2355 14:44:03.247959 LPDDR4 DRAM CONFIGURATION
2356 14:44:03.248051 ===================================
2357 14:44:03.248143 EX_ROW_EN[0] = 0x10
2358 14:44:03.248234 EX_ROW_EN[1] = 0x0
2359 14:44:03.248330 LP4Y_EN = 0x0
2360 14:44:03.248404 WORK_FSP = 0x0
2361 14:44:03.248463 WL = 0x4
2362 14:44:03.248522 RL = 0x4
2363 14:44:03.248581 BL = 0x2
2364 14:44:03.248639 RPST = 0x0
2365 14:44:03.248697 RD_PRE = 0x0
2366 14:44:03.248755 WR_PRE = 0x1
2367 14:44:03.248813 WR_PST = 0x0
2368 14:44:03.248888 DBI_WR = 0x0
2369 14:44:03.248983 DBI_RD = 0x0
2370 14:44:03.249079 OTF = 0x1
2371 14:44:03.249185 ===================================
2372 14:44:03.249250 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2373 14:44:03.249310 ==
2374 14:44:03.249368 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 14:44:03.249456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 14:44:03.249518 ==
2377 14:44:03.249578 [Duty_Offset_Calibration]
2378 14:44:03.249636 B0:1 B1:-1 CA:0
2379 14:44:03.249695
2380 14:44:03.249753 [DutyScan_Calibration_Flow] k_type=0
2381 14:44:03.249811
2382 14:44:03.249869 ==CLK 0==
2383 14:44:03.249944 Final CLK duty delay cell = 0
2384 14:44:03.250042 [0] MAX Duty = 5125%(X100), DQS PI = 24
2385 14:44:03.250134 [0] MIN Duty = 4875%(X100), DQS PI = 8
2386 14:44:03.250224 [0] AVG Duty = 5000%(X100)
2387 14:44:03.250284
2388 14:44:03.250342 CH0 CLK Duty spec in!! Max-Min= 250%
2389 14:44:03.250401 [DutyScan_Calibration_Flow] ====Done====
2390 14:44:03.250474
2391 14:44:03.250540 [DutyScan_Calibration_Flow] k_type=1
2392 14:44:03.250599
2393 14:44:03.250658 ==DQS 0 ==
2394 14:44:03.250717 Final DQS duty delay cell = -4
2395 14:44:03.250776 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2396 14:44:03.250835 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2397 14:44:03.250893 [-4] AVG Duty = 4968%(X100)
2398 14:44:03.250952
2399 14:44:03.251039 ==DQS 1 ==
2400 14:44:03.251132 Final DQS duty delay cell = 0
2401 14:44:03.251224 [0] MAX Duty = 5124%(X100), DQS PI = 6
2402 14:44:03.251316 [0] MIN Duty = 5000%(X100), DQS PI = 22
2403 14:44:03.251611 [0] AVG Duty = 5062%(X100)
2404 14:44:03.251718
2405 14:44:03.251813 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2406 14:44:03.251905
2407 14:44:03.251997 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2408 14:44:03.252089 [DutyScan_Calibration_Flow] ====Done====
2409 14:44:03.252151
2410 14:44:03.252211 [DutyScan_Calibration_Flow] k_type=3
2411 14:44:03.252271
2412 14:44:03.252330 ==DQM 0 ==
2413 14:44:03.252389 Final DQM duty delay cell = 0
2414 14:44:03.252449 [0] MAX Duty = 5062%(X100), DQS PI = 24
2415 14:44:03.252509 [0] MIN Duty = 4844%(X100), DQS PI = 8
2416 14:44:03.252586 [0] AVG Duty = 4953%(X100)
2417 14:44:03.252692
2418 14:44:03.252775 ==DQM 1 ==
2419 14:44:03.252859 Final DQM duty delay cell = 4
2420 14:44:03.252943 [4] MAX Duty = 5187%(X100), DQS PI = 14
2421 14:44:03.253030 [4] MIN Duty = 5000%(X100), DQS PI = 22
2422 14:44:03.253127 [4] AVG Duty = 5093%(X100)
2423 14:44:03.253214
2424 14:44:03.253298 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2425 14:44:03.253381
2426 14:44:03.253464 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2427 14:44:03.253548 [DutyScan_Calibration_Flow] ====Done====
2428 14:44:03.253637
2429 14:44:03.253719 [DutyScan_Calibration_Flow] k_type=2
2430 14:44:03.253802
2431 14:44:03.253885 ==DQ 0 ==
2432 14:44:03.253968 Final DQ duty delay cell = -4
2433 14:44:03.254053 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2434 14:44:03.254140 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2435 14:44:03.254217 [-4] AVG Duty = 4937%(X100)
2436 14:44:03.254272
2437 14:44:03.254327 ==DQ 1 ==
2438 14:44:03.254381 Final DQ duty delay cell = -4
2439 14:44:03.254435 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2440 14:44:03.254488 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2441 14:44:03.254542 [-4] AVG Duty = 4922%(X100)
2442 14:44:03.254595
2443 14:44:03.254648 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2444 14:44:03.254702
2445 14:44:03.254778 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2446 14:44:03.254835 [DutyScan_Calibration_Flow] ====Done====
2447 14:44:03.254890 ==
2448 14:44:03.254944 Dram Type= 6, Freq= 0, CH_1, rank 0
2449 14:44:03.254998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 14:44:03.255052 ==
2451 14:44:03.255106 [Duty_Offset_Calibration]
2452 14:44:03.255159 B0:-1 B1:1 CA:1
2453 14:44:03.255213
2454 14:44:03.255279 [DutyScan_Calibration_Flow] k_type=0
2455 14:44:03.255341
2456 14:44:03.255395 ==CLK 0==
2457 14:44:03.255449 Final CLK duty delay cell = 0
2458 14:44:03.255504 [0] MAX Duty = 5156%(X100), DQS PI = 22
2459 14:44:03.255558 [0] MIN Duty = 4969%(X100), DQS PI = 60
2460 14:44:03.255610 [0] AVG Duty = 5062%(X100)
2461 14:44:03.255663
2462 14:44:03.255716 CH1 CLK Duty spec in!! Max-Min= 187%
2463 14:44:03.255769 [DutyScan_Calibration_Flow] ====Done====
2464 14:44:03.255849
2465 14:44:03.255934 [DutyScan_Calibration_Flow] k_type=1
2466 14:44:03.256016
2467 14:44:03.256099 ==DQS 0 ==
2468 14:44:03.256182 Final DQS duty delay cell = 0
2469 14:44:03.256267 [0] MAX Duty = 5125%(X100), DQS PI = 48
2470 14:44:03.256361 [0] MIN Duty = 4875%(X100), DQS PI = 6
2471 14:44:03.256447 [0] AVG Duty = 5000%(X100)
2472 14:44:03.256529
2473 14:44:03.256611 ==DQS 1 ==
2474 14:44:03.256695 Final DQS duty delay cell = 0
2475 14:44:03.256779 [0] MAX Duty = 5062%(X100), DQS PI = 10
2476 14:44:03.256871 [0] MIN Duty = 4969%(X100), DQS PI = 54
2477 14:44:03.256959 [0] AVG Duty = 5015%(X100)
2478 14:44:03.257041
2479 14:44:03.257124 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2480 14:44:03.257207
2481 14:44:03.257290 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2482 14:44:03.257374 [DutyScan_Calibration_Flow] ====Done====
2483 14:44:03.257449
2484 14:44:03.257504 [DutyScan_Calibration_Flow] k_type=3
2485 14:44:03.257558
2486 14:44:03.257611 ==DQM 0 ==
2487 14:44:03.257677 Final DQM duty delay cell = -4
2488 14:44:03.257730 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2489 14:44:03.257782 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2490 14:44:03.257835 [-4] AVG Duty = 4937%(X100)
2491 14:44:03.257888
2492 14:44:03.257975 ==DQM 1 ==
2493 14:44:03.258058 Final DQM duty delay cell = 0
2494 14:44:03.258141 [0] MAX Duty = 5187%(X100), DQS PI = 6
2495 14:44:03.258244 [0] MIN Duty = 4969%(X100), DQS PI = 30
2496 14:44:03.258297 [0] AVG Duty = 5078%(X100)
2497 14:44:03.258350
2498 14:44:03.258401 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2499 14:44:03.258467
2500 14:44:03.258527 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2501 14:44:03.258581 [DutyScan_Calibration_Flow] ====Done====
2502 14:44:03.258633
2503 14:44:03.258685 [DutyScan_Calibration_Flow] k_type=2
2504 14:44:03.258737
2505 14:44:03.258789 ==DQ 0 ==
2506 14:44:03.258841 Final DQ duty delay cell = 0
2507 14:44:03.258893 [0] MAX Duty = 5156%(X100), DQS PI = 28
2508 14:44:03.258946 [0] MIN Duty = 4876%(X100), DQS PI = 8
2509 14:44:03.259021 [0] AVG Duty = 5016%(X100)
2510 14:44:03.259075
2511 14:44:03.259128 ==DQ 1 ==
2512 14:44:03.259180 Final DQ duty delay cell = 0
2513 14:44:03.259233 [0] MAX Duty = 5124%(X100), DQS PI = 10
2514 14:44:03.259285 [0] MIN Duty = 4969%(X100), DQS PI = 0
2515 14:44:03.259338 [0] AVG Duty = 5046%(X100)
2516 14:44:03.259390
2517 14:44:03.259442 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2518 14:44:03.259496
2519 14:44:03.259566 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2520 14:44:03.259620 [DutyScan_Calibration_Flow] ====Done====
2521 14:44:03.259673 nWR fixed to 30
2522 14:44:03.259727 [ModeRegInit_LP4] CH0 RK0
2523 14:44:03.259779 [ModeRegInit_LP4] CH0 RK1
2524 14:44:03.259831 [ModeRegInit_LP4] CH1 RK0
2525 14:44:03.259883 [ModeRegInit_LP4] CH1 RK1
2526 14:44:03.259935 match AC timing 7
2527 14:44:03.259987 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2528 14:44:03.260057 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2529 14:44:03.260143 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2530 14:44:03.260226 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2531 14:44:03.260309 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2532 14:44:03.260390 ==
2533 14:44:03.260472 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 14:44:03.260558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 14:44:03.260648 ==
2536 14:44:03.260731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 14:44:03.260813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2538 14:44:03.260895 [CA 0] Center 39 (9~70) winsize 62
2539 14:44:03.260977 [CA 1] Center 39 (9~70) winsize 62
2540 14:44:03.261058 [CA 2] Center 35 (5~66) winsize 62
2541 14:44:03.261183 [CA 3] Center 35 (5~66) winsize 62
2542 14:44:03.261297 [CA 4] Center 33 (4~63) winsize 60
2543 14:44:03.261379 [CA 5] Center 33 (3~63) winsize 61
2544 14:44:03.261459
2545 14:44:03.261541 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2546 14:44:03.261630
2547 14:44:03.261714 [CATrainingPosCal] consider 1 rank data
2548 14:44:03.261795 u2DelayCellTimex100 = 270/100 ps
2549 14:44:03.261877 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 14:44:03.261958 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 14:44:03.262040 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 14:44:03.262121 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 14:44:03.262438 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2554 14:44:03.262498 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2555 14:44:03.262552
2556 14:44:03.262605 CA PerBit enable=1, Macro0, CA PI delay=33
2557 14:44:03.262669
2558 14:44:03.262732 [CBTSetCACLKResult] CA Dly = 33
2559 14:44:03.262786 CS Dly: 8 (0~39)
2560 14:44:03.262839 ==
2561 14:44:03.262891 Dram Type= 6, Freq= 0, CH_0, rank 1
2562 14:44:03.262944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 14:44:03.262997 ==
2564 14:44:03.263049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2565 14:44:03.263102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2566 14:44:03.263155 [CA 0] Center 39 (8~70) winsize 63
2567 14:44:03.263221 [CA 1] Center 39 (9~70) winsize 62
2568 14:44:03.263280 [CA 2] Center 35 (5~66) winsize 62
2569 14:44:03.263334 [CA 3] Center 34 (4~65) winsize 62
2570 14:44:03.263386 [CA 4] Center 33 (3~64) winsize 62
2571 14:44:03.263439 [CA 5] Center 33 (3~63) winsize 61
2572 14:44:03.263491
2573 14:44:03.263543 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2574 14:44:03.263595
2575 14:44:03.263646 [CATrainingPosCal] consider 2 rank data
2576 14:44:03.263698 u2DelayCellTimex100 = 270/100 ps
2577 14:44:03.263773 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2578 14:44:03.263828 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2579 14:44:03.263880 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2580 14:44:03.263933 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2581 14:44:03.263985 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2582 14:44:03.264037 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2583 14:44:03.264089
2584 14:44:03.264141 CA PerBit enable=1, Macro0, CA PI delay=33
2585 14:44:03.264193
2586 14:44:03.264248 [CBTSetCACLKResult] CA Dly = 33
2587 14:44:03.264341 CS Dly: 9 (0~41)
2588 14:44:03.264423
2589 14:44:03.264504 ----->DramcWriteLeveling(PI) begin...
2590 14:44:03.264587 ==
2591 14:44:03.264669 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 14:44:03.264751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 14:44:03.264845 ==
2594 14:44:03.264928 Write leveling (Byte 0): 32 => 32
2595 14:44:03.265010 Write leveling (Byte 1): 30 => 30
2596 14:44:03.265091 DramcWriteLeveling(PI) end<-----
2597 14:44:03.265172
2598 14:44:03.265252 ==
2599 14:44:03.265340 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 14:44:03.265396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 14:44:03.265449 ==
2602 14:44:03.265502 [Gating] SW mode calibration
2603 14:44:03.265554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2604 14:44:03.265608 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2605 14:44:03.265660 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2606 14:44:03.265712 0 15 4 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
2607 14:44:03.265764 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 14:44:03.265817 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 14:44:03.265910 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 14:44:03.265994 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 14:44:03.266077 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 14:44:03.266159 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 1)
2613 14:44:03.266259 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2614 14:44:03.266313 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2615 14:44:03.266379 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 14:44:03.266440 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 14:44:03.266493 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 14:44:03.266545 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 14:44:03.266598 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 14:44:03.266650 1 0 28 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
2621 14:44:03.266702 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2622 14:44:03.266754 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2623 14:44:03.266807 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 14:44:03.266859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 14:44:03.266933 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 14:44:03.266989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 14:44:03.267041 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 14:44:03.267093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2629 14:44:03.267145 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2630 14:44:03.267198 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2631 14:44:03.267250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 14:44:03.267302 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 14:44:03.267354 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 14:44:03.267409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 14:44:03.267480 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 14:44:03.267534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 14:44:03.267586 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 14:44:03.267638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 14:44:03.267691 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 14:44:03.267743 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 14:44:03.267795 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 14:44:03.267847 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 14:44:03.267900 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 14:44:03.267972 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2645 14:44:03.268029 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2646 14:44:03.268082 Total UI for P1: 0, mck2ui 16
2647 14:44:03.268135 best dqsien dly found for B0: ( 1, 3, 28)
2648 14:44:03.268188 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2649 14:44:03.268241 Total UI for P1: 0, mck2ui 16
2650 14:44:03.268294 best dqsien dly found for B1: ( 1, 4, 0)
2651 14:44:03.268346 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2652 14:44:03.268398 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2653 14:44:03.268450
2654 14:44:03.268502 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2655 14:44:03.268576 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2656 14:44:03.268631 [Gating] SW calibration Done
2657 14:44:03.268684 ==
2658 14:44:03.268928 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 14:44:03.268989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 14:44:03.269048 ==
2661 14:44:03.269117 RX Vref Scan: 0
2662 14:44:03.269170
2663 14:44:03.269222 RX Vref 0 -> 0, step: 1
2664 14:44:03.269274
2665 14:44:03.269326 RX Delay -40 -> 252, step: 8
2666 14:44:03.269378 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2667 14:44:03.269431 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2668 14:44:03.269483 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2669 14:44:03.269535 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2670 14:44:03.269601 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2671 14:44:03.269660 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2672 14:44:03.269712 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2673 14:44:03.269763 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2674 14:44:03.269815 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2675 14:44:03.269868 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2676 14:44:03.269920 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2677 14:44:03.269971 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2678 14:44:03.270023 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2679 14:44:03.270075 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2680 14:44:03.270184 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2681 14:44:03.270256 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2682 14:44:03.270310 ==
2683 14:44:03.270362 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 14:44:03.270415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 14:44:03.270467 ==
2686 14:44:03.270518 DQS Delay:
2687 14:44:03.270570 DQS0 = 0, DQS1 = 0
2688 14:44:03.270625 DQM Delay:
2689 14:44:03.270695 DQM0 = 119, DQM1 = 107
2690 14:44:03.270749 DQ Delay:
2691 14:44:03.270802 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2692 14:44:03.270854 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2693 14:44:03.270906 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2694 14:44:03.270958 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2695 14:44:03.271010
2696 14:44:03.271062
2697 14:44:03.271113 ==
2698 14:44:03.271179 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 14:44:03.271238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 14:44:03.271291 ==
2701 14:44:03.271342
2702 14:44:03.271393
2703 14:44:03.271445 TX Vref Scan disable
2704 14:44:03.271497 == TX Byte 0 ==
2705 14:44:03.271549 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2706 14:44:03.271601 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2707 14:44:03.271653 == TX Byte 1 ==
2708 14:44:03.271718 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2709 14:44:03.271779 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2710 14:44:03.271831 ==
2711 14:44:03.271883 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 14:44:03.271935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 14:44:03.271987 ==
2714 14:44:03.272039 TX Vref=22, minBit 5, minWin=25, winSum=417
2715 14:44:03.272092 TX Vref=24, minBit 13, minWin=25, winSum=424
2716 14:44:03.272144 TX Vref=26, minBit 4, minWin=26, winSum=434
2717 14:44:03.272196 TX Vref=28, minBit 1, minWin=26, winSum=435
2718 14:44:03.272271 TX Vref=30, minBit 4, minWin=26, winSum=436
2719 14:44:03.272327 TX Vref=32, minBit 5, minWin=26, winSum=434
2720 14:44:03.272380 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 30
2721 14:44:03.272432
2722 14:44:03.272485 Final TX Range 1 Vref 30
2723 14:44:03.272538
2724 14:44:03.272590 ==
2725 14:44:03.272642 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 14:44:03.272695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 14:44:03.272749 ==
2728 14:44:03.272819
2729 14:44:03.272872
2730 14:44:03.272925 TX Vref Scan disable
2731 14:44:03.272977 == TX Byte 0 ==
2732 14:44:03.273029 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2733 14:44:03.273082 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2734 14:44:03.273134 == TX Byte 1 ==
2735 14:44:03.273186 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2736 14:44:03.273238 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2737 14:44:03.273306
2738 14:44:03.273364 [DATLAT]
2739 14:44:03.273416 Freq=1200, CH0 RK0
2740 14:44:03.273469
2741 14:44:03.273520 DATLAT Default: 0xd
2742 14:44:03.273572 0, 0xFFFF, sum = 0
2743 14:44:03.273626 1, 0xFFFF, sum = 0
2744 14:44:03.273679 2, 0xFFFF, sum = 0
2745 14:44:03.273732 3, 0xFFFF, sum = 0
2746 14:44:03.273785 4, 0xFFFF, sum = 0
2747 14:44:03.273877 5, 0xFFFF, sum = 0
2748 14:44:03.273961 6, 0xFFFF, sum = 0
2749 14:44:03.274044 7, 0xFFFF, sum = 0
2750 14:44:03.274127 8, 0xFFFF, sum = 0
2751 14:44:03.274231 9, 0xFFFF, sum = 0
2752 14:44:03.274286 10, 0xFFFF, sum = 0
2753 14:44:03.274348 11, 0xFFFF, sum = 0
2754 14:44:03.274414 12, 0x0, sum = 1
2755 14:44:03.274468 13, 0x0, sum = 2
2756 14:44:03.274521 14, 0x0, sum = 3
2757 14:44:03.274574 15, 0x0, sum = 4
2758 14:44:03.274626 best_step = 13
2759 14:44:03.274678
2760 14:44:03.274730 ==
2761 14:44:03.274782 Dram Type= 6, Freq= 0, CH_0, rank 0
2762 14:44:03.274834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2763 14:44:03.274909 ==
2764 14:44:03.274964 RX Vref Scan: 1
2765 14:44:03.275017
2766 14:44:03.275068 Set Vref Range= 32 -> 127
2767 14:44:03.275121
2768 14:44:03.275174 RX Vref 32 -> 127, step: 1
2769 14:44:03.275226
2770 14:44:03.275277 RX Delay -21 -> 252, step: 4
2771 14:44:03.275329
2772 14:44:03.275381 Set Vref, RX VrefLevel [Byte0]: 32
2773 14:44:03.275454 [Byte1]: 32
2774 14:44:03.275508
2775 14:44:03.275560 Set Vref, RX VrefLevel [Byte0]: 33
2776 14:44:03.275613 [Byte1]: 33
2777 14:44:03.275664
2778 14:44:03.275716 Set Vref, RX VrefLevel [Byte0]: 34
2779 14:44:03.275768 [Byte1]: 34
2780 14:44:03.275820
2781 14:44:03.275872 Set Vref, RX VrefLevel [Byte0]: 35
2782 14:44:03.275937 [Byte1]: 35
2783 14:44:03.275996
2784 14:44:03.276048 Set Vref, RX VrefLevel [Byte0]: 36
2785 14:44:03.276100 [Byte1]: 36
2786 14:44:03.276152
2787 14:44:03.276204 Set Vref, RX VrefLevel [Byte0]: 37
2788 14:44:03.276256 [Byte1]: 37
2789 14:44:03.276308
2790 14:44:03.276360 Set Vref, RX VrefLevel [Byte0]: 38
2791 14:44:03.276412 [Byte1]: 38
2792 14:44:03.276481
2793 14:44:03.276538 Set Vref, RX VrefLevel [Byte0]: 39
2794 14:44:03.276591 [Byte1]: 39
2795 14:44:03.276643
2796 14:44:03.276695 Set Vref, RX VrefLevel [Byte0]: 40
2797 14:44:03.276747 [Byte1]: 40
2798 14:44:03.276799
2799 14:44:03.276850 Set Vref, RX VrefLevel [Byte0]: 41
2800 14:44:03.276902 [Byte1]: 41
2801 14:44:03.276954
2802 14:44:03.277043 Set Vref, RX VrefLevel [Byte0]: 42
2803 14:44:03.277126 [Byte1]: 42
2804 14:44:03.277206
2805 14:44:03.277287 Set Vref, RX VrefLevel [Byte0]: 43
2806 14:44:03.277369 [Byte1]: 43
2807 14:44:03.277449
2808 14:44:03.277539 Set Vref, RX VrefLevel [Byte0]: 44
2809 14:44:03.277596 [Byte1]: 44
2810 14:44:03.277649
2811 14:44:03.277701 Set Vref, RX VrefLevel [Byte0]: 45
2812 14:44:03.277753 [Byte1]: 45
2813 14:44:03.277805
2814 14:44:03.278058 Set Vref, RX VrefLevel [Byte0]: 46
2815 14:44:03.278147 [Byte1]: 46
2816 14:44:03.278247
2817 14:44:03.278301 Set Vref, RX VrefLevel [Byte0]: 47
2818 14:44:03.278355 [Byte1]: 47
2819 14:44:03.278407
2820 14:44:03.278460 Set Vref, RX VrefLevel [Byte0]: 48
2821 14:44:03.278574 [Byte1]: 48
2822 14:44:03.278679
2823 14:44:03.278733 Set Vref, RX VrefLevel [Byte0]: 49
2824 14:44:03.278785 [Byte1]: 49
2825 14:44:03.278838
2826 14:44:03.278890 Set Vref, RX VrefLevel [Byte0]: 50
2827 14:44:03.278942 [Byte1]: 50
2828 14:44:03.278994
2829 14:44:03.279046 Set Vref, RX VrefLevel [Byte0]: 51
2830 14:44:03.279107 [Byte1]: 51
2831 14:44:03.279172
2832 14:44:03.279224 Set Vref, RX VrefLevel [Byte0]: 52
2833 14:44:03.279277 [Byte1]: 52
2834 14:44:03.279329
2835 14:44:03.279381 Set Vref, RX VrefLevel [Byte0]: 53
2836 14:44:03.279433 [Byte1]: 53
2837 14:44:03.279485
2838 14:44:03.279537 Set Vref, RX VrefLevel [Byte0]: 54
2839 14:44:03.279590 [Byte1]: 54
2840 14:44:03.279660
2841 14:44:03.279716 Set Vref, RX VrefLevel [Byte0]: 55
2842 14:44:03.279768 [Byte1]: 55
2843 14:44:03.279820
2844 14:44:03.279872 Set Vref, RX VrefLevel [Byte0]: 56
2845 14:44:03.279924 [Byte1]: 56
2846 14:44:03.279976
2847 14:44:03.280046 Set Vref, RX VrefLevel [Byte0]: 57
2848 14:44:03.280112 [Byte1]: 57
2849 14:44:03.280177
2850 14:44:03.280235 Set Vref, RX VrefLevel [Byte0]: 58
2851 14:44:03.280288 [Byte1]: 58
2852 14:44:03.280342
2853 14:44:03.280394 Set Vref, RX VrefLevel [Byte0]: 59
2854 14:44:03.280447 [Byte1]: 59
2855 14:44:03.280499
2856 14:44:03.280551 Set Vref, RX VrefLevel [Byte0]: 60
2857 14:44:03.280603 [Byte1]: 60
2858 14:44:03.280655
2859 14:44:03.280729 Set Vref, RX VrefLevel [Byte0]: 61
2860 14:44:03.280784 [Byte1]: 61
2861 14:44:03.280836
2862 14:44:03.280888 Set Vref, RX VrefLevel [Byte0]: 62
2863 14:44:03.280940 [Byte1]: 62
2864 14:44:03.280991
2865 14:44:03.281043 Set Vref, RX VrefLevel [Byte0]: 63
2866 14:44:03.281095 [Byte1]: 63
2867 14:44:03.281147
2868 14:44:03.281202 Set Vref, RX VrefLevel [Byte0]: 64
2869 14:44:03.281272 [Byte1]: 64
2870 14:44:03.281325
2871 14:44:03.281377 Set Vref, RX VrefLevel [Byte0]: 65
2872 14:44:03.281429 [Byte1]: 65
2873 14:44:03.281481
2874 14:44:03.281533 Set Vref, RX VrefLevel [Byte0]: 66
2875 14:44:03.281586 [Byte1]: 66
2876 14:44:03.281638
2877 14:44:03.281689 Set Vref, RX VrefLevel [Byte0]: 67
2878 14:44:03.281755 [Byte1]: 67
2879 14:44:03.281813
2880 14:44:03.281865 Set Vref, RX VrefLevel [Byte0]: 68
2881 14:44:03.281918 [Byte1]: 68
2882 14:44:03.281969
2883 14:44:03.282021 Set Vref, RX VrefLevel [Byte0]: 69
2884 14:44:03.282073 [Byte1]: 69
2885 14:44:03.282126
2886 14:44:03.282187 Set Vref, RX VrefLevel [Byte0]: 70
2887 14:44:03.282241 [Byte1]: 70
2888 14:44:03.282317
2889 14:44:03.282371 Set Vref, RX VrefLevel [Byte0]: 71
2890 14:44:03.282423 [Byte1]: 71
2891 14:44:03.282476
2892 14:44:03.282528 Set Vref, RX VrefLevel [Byte0]: 72
2893 14:44:03.282580 [Byte1]: 72
2894 14:44:03.282634
2895 14:44:03.282686 Set Vref, RX VrefLevel [Byte0]: 73
2896 14:44:03.282739 [Byte1]: 73
2897 14:44:03.282804
2898 14:44:03.282864 Set Vref, RX VrefLevel [Byte0]: 74
2899 14:44:03.282917 [Byte1]: 74
2900 14:44:03.282969
2901 14:44:03.283021 Set Vref, RX VrefLevel [Byte0]: 75
2902 14:44:03.283074 [Byte1]: 75
2903 14:44:03.283126
2904 14:44:03.283178 Set Vref, RX VrefLevel [Byte0]: 76
2905 14:44:03.283230 [Byte1]: 76
2906 14:44:03.283283
2907 14:44:03.283347 Set Vref, RX VrefLevel [Byte0]: 77
2908 14:44:03.283406 [Byte1]: 77
2909 14:44:03.283459
2910 14:44:03.283510 Final RX Vref Byte 0 = 59 to rank0
2911 14:44:03.283563 Final RX Vref Byte 1 = 58 to rank0
2912 14:44:03.283615 Final RX Vref Byte 0 = 59 to rank1
2913 14:44:03.283668 Final RX Vref Byte 1 = 58 to rank1==
2914 14:44:03.283721 Dram Type= 6, Freq= 0, CH_0, rank 0
2915 14:44:03.283773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 14:44:03.283826 ==
2917 14:44:03.283899 DQS Delay:
2918 14:44:03.283952 DQS0 = 0, DQS1 = 0
2919 14:44:03.284005 DQM Delay:
2920 14:44:03.284057 DQM0 = 118, DQM1 = 107
2921 14:44:03.284109 DQ Delay:
2922 14:44:03.284161 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2923 14:44:03.284213 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2924 14:44:03.284266 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2925 14:44:03.284318 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2926 14:44:03.284385
2927 14:44:03.284443
2928 14:44:03.284495 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2929 14:44:03.284548 CH0 RK0: MR19=403, MR18=DF9
2930 14:44:03.284601 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2931 14:44:03.284654
2932 14:44:03.284705 ----->DramcWriteLeveling(PI) begin...
2933 14:44:03.284759 ==
2934 14:44:03.284812 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 14:44:03.284878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 14:44:03.284939 ==
2937 14:44:03.284992 Write leveling (Byte 0): 30 => 30
2938 14:44:03.285045 Write leveling (Byte 1): 28 => 28
2939 14:44:03.285097 DramcWriteLeveling(PI) end<-----
2940 14:44:03.285149
2941 14:44:03.285201 ==
2942 14:44:03.285253 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 14:44:03.285305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 14:44:03.285358 ==
2945 14:44:03.285433 [Gating] SW mode calibration
2946 14:44:03.285488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2947 14:44:03.285542 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2948 14:44:03.285595 0 15 0 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
2949 14:44:03.285647 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2950 14:44:03.285700 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2951 14:44:03.285752 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 14:44:03.285804 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 14:44:03.285857 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 14:44:03.285919 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 14:44:03.285982 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2956 14:44:03.286035 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2957 14:44:03.286088 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 14:44:03.286332 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 14:44:03.286391 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 14:44:03.286457 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 14:44:03.286522 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 14:44:03.286591 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 14:44:03.286657 1 0 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2964 14:44:03.286710 1 1 0 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
2965 14:44:03.286762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 14:44:03.286814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 14:44:03.286865 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 14:44:03.286917 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 14:44:03.286979 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 14:44:03.287043 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 14:44:03.287097 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2972 14:44:03.287149 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2973 14:44:03.287201 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 14:44:03.287253 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 14:44:03.287305 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 14:44:03.287356 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 14:44:03.287408 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 14:44:03.287460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 14:44:03.287531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 14:44:03.287587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 14:44:03.287640 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 14:44:03.287692 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 14:44:03.287743 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 14:44:03.287795 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 14:44:03.287847 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 14:44:03.287899 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 14:44:03.287950 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2988 14:44:03.288002 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2989 14:44:03.288077 Total UI for P1: 0, mck2ui 16
2990 14:44:03.288132 best dqsien dly found for B0: ( 1, 3, 28)
2991 14:44:03.288185 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 14:44:03.288237 Total UI for P1: 0, mck2ui 16
2993 14:44:03.288289 best dqsien dly found for B1: ( 1, 3, 30)
2994 14:44:03.288342 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2995 14:44:03.288394 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2996 14:44:03.288446
2997 14:44:03.288498 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2998 14:44:03.288562 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2999 14:44:03.288623 [Gating] SW calibration Done
3000 14:44:03.288676 ==
3001 14:44:03.288729 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 14:44:03.288781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 14:44:03.288833 ==
3004 14:44:03.288885 RX Vref Scan: 0
3005 14:44:03.288937
3006 14:44:03.571940 RX Vref 0 -> 0, step: 1
3007 14:44:03.572595
3008 14:44:03.573145 RX Delay -40 -> 252, step: 8
3009 14:44:03.573659 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3010 14:44:03.574187 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3011 14:44:03.574550 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3012 14:44:03.574996 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3013 14:44:03.575505 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3014 14:44:03.575996 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3015 14:44:03.576527 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3016 14:44:03.577017 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3017 14:44:03.577454 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3018 14:44:03.577765 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3019 14:44:03.578079 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3020 14:44:03.578434 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3021 14:44:03.578738 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3022 14:44:03.579037 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3023 14:44:03.579314 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3024 14:44:03.579625 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3025 14:44:03.579903 ==
3026 14:44:03.580290 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 14:44:03.580732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 14:44:03.581168 ==
3029 14:44:03.581540 DQS Delay:
3030 14:44:03.581820 DQS0 = 0, DQS1 = 0
3031 14:44:03.582139 DQM Delay:
3032 14:44:03.582473 DQM0 = 117, DQM1 = 108
3033 14:44:03.582768 DQ Delay:
3034 14:44:03.583062 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3035 14:44:03.583358 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3036 14:44:03.583652 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3037 14:44:03.583925 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3038 14:44:03.584255
3039 14:44:03.584686
3040 14:44:03.585111 ==
3041 14:44:03.585471 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 14:44:03.585747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 14:44:03.586119 ==
3044 14:44:03.586448
3045 14:44:03.586756
3046 14:44:03.587030 TX Vref Scan disable
3047 14:44:03.587342 == TX Byte 0 ==
3048 14:44:03.587618 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3049 14:44:03.587935 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3050 14:44:03.588214 == TX Byte 1 ==
3051 14:44:03.588520 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3052 14:44:03.588806 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3053 14:44:03.589098 ==
3054 14:44:03.589390 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 14:44:03.589685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 14:44:03.589983 ==
3057 14:44:03.590309 TX Vref=22, minBit 4, minWin=25, winSum=417
3058 14:44:03.590613 TX Vref=24, minBit 2, minWin=25, winSum=421
3059 14:44:03.590892 TX Vref=26, minBit 0, minWin=26, winSum=425
3060 14:44:03.591207 TX Vref=28, minBit 1, minWin=26, winSum=426
3061 14:44:03.591494 TX Vref=30, minBit 1, minWin=27, winSum=435
3062 14:44:03.591836 TX Vref=32, minBit 0, minWin=26, winSum=431
3063 14:44:03.592112 [TxChooseVref] Worse bit 1, Min win 27, Win sum 435, Final Vref 30
3064 14:44:03.592424
3065 14:44:03.592706 Final TX Range 1 Vref 30
3066 14:44:03.592933
3067 14:44:03.593129 ==
3068 14:44:03.593319 Dram Type= 6, Freq= 0, CH_0, rank 1
3069 14:44:03.593908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 14:44:03.594311 ==
3071 14:44:03.594636
3072 14:44:03.594862
3073 14:44:03.595065 TX Vref Scan disable
3074 14:44:03.595278 == TX Byte 0 ==
3075 14:44:03.595494 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3076 14:44:03.595691 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3077 14:44:03.595902 == TX Byte 1 ==
3078 14:44:03.596111 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3079 14:44:03.596307 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3080 14:44:03.596516
3081 14:44:03.596722 [DATLAT]
3082 14:44:03.596913 Freq=1200, CH0 RK1
3083 14:44:03.597132
3084 14:44:03.597336 DATLAT Default: 0xd
3085 14:44:03.597533 0, 0xFFFF, sum = 0
3086 14:44:03.597747 1, 0xFFFF, sum = 0
3087 14:44:03.597900 2, 0xFFFF, sum = 0
3088 14:44:03.598048 3, 0xFFFF, sum = 0
3089 14:44:03.598207 4, 0xFFFF, sum = 0
3090 14:44:03.598376 5, 0xFFFF, sum = 0
3091 14:44:03.598527 6, 0xFFFF, sum = 0
3092 14:44:03.598673 7, 0xFFFF, sum = 0
3093 14:44:03.598825 8, 0xFFFF, sum = 0
3094 14:44:03.598990 9, 0xFFFF, sum = 0
3095 14:44:03.599138 10, 0xFFFF, sum = 0
3096 14:44:03.599286 11, 0xFFFF, sum = 0
3097 14:44:03.599441 12, 0x0, sum = 1
3098 14:44:03.599602 13, 0x0, sum = 2
3099 14:44:03.599749 14, 0x0, sum = 3
3100 14:44:03.599894 15, 0x0, sum = 4
3101 14:44:03.600053 best_step = 13
3102 14:44:03.600210
3103 14:44:03.600354 ==
3104 14:44:03.600498 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 14:44:03.600656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 14:44:03.600816 ==
3107 14:44:03.600961 RX Vref Scan: 0
3108 14:44:03.601105
3109 14:44:03.601262 RX Vref 0 -> 0, step: 1
3110 14:44:03.601417
3111 14:44:03.601561 RX Delay -21 -> 252, step: 4
3112 14:44:03.601705 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3113 14:44:03.601874 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3114 14:44:03.602024 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3115 14:44:03.602187 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3116 14:44:03.602336 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3117 14:44:03.602510 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3118 14:44:03.602659 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3119 14:44:03.602803 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3120 14:44:03.602920 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3121 14:44:03.603055 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3122 14:44:03.603173 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3123 14:44:03.603290 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3124 14:44:03.603408 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3125 14:44:03.603534 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3126 14:44:03.603659 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3127 14:44:03.603776 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3128 14:44:03.603892 ==
3129 14:44:03.604009 Dram Type= 6, Freq= 0, CH_0, rank 1
3130 14:44:03.604133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 14:44:03.604261 ==
3132 14:44:03.604378 DQS Delay:
3133 14:44:03.604495 DQS0 = 0, DQS1 = 0
3134 14:44:03.604611 DQM Delay:
3135 14:44:03.604741 DQM0 = 116, DQM1 = 109
3136 14:44:03.604868 DQ Delay:
3137 14:44:03.604986 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3138 14:44:03.605103 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3139 14:44:03.605220 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =102
3140 14:44:03.605351 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =116
3141 14:44:03.605479
3142 14:44:03.605596
3143 14:44:03.605713 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3144 14:44:03.605833 CH0 RK1: MR19=403, MR18=10EA
3145 14:44:03.605968 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3146 14:44:03.606091 [RxdqsGatingPostProcess] freq 1200
3147 14:44:03.606220 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3148 14:44:03.606338 best DQS0 dly(2T, 0.5T) = (0, 11)
3149 14:44:03.606457 best DQS1 dly(2T, 0.5T) = (0, 12)
3150 14:44:03.606591 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3151 14:44:03.606711 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3152 14:44:03.606828 best DQS0 dly(2T, 0.5T) = (0, 11)
3153 14:44:03.606944 best DQS1 dly(2T, 0.5T) = (0, 11)
3154 14:44:03.607070 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3155 14:44:03.607196 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3156 14:44:03.607313 Pre-setting of DQS Precalculation
3157 14:44:03.607429 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3158 14:44:03.607544 ==
3159 14:44:03.607687 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 14:44:03.607788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 14:44:03.607887 ==
3162 14:44:03.607984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3163 14:44:03.608083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3164 14:44:03.608198 [CA 0] Center 38 (8~68) winsize 61
3165 14:44:03.608300 [CA 1] Center 37 (7~68) winsize 62
3166 14:44:03.608398 [CA 2] Center 34 (4~64) winsize 61
3167 14:44:03.608495 [CA 3] Center 33 (3~64) winsize 62
3168 14:44:03.608592 [CA 4] Center 34 (4~64) winsize 61
3169 14:44:03.608692 [CA 5] Center 33 (3~64) winsize 62
3170 14:44:03.608802
3171 14:44:03.608900 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3172 14:44:03.608997
3173 14:44:03.609094 [CATrainingPosCal] consider 1 rank data
3174 14:44:03.609192 u2DelayCellTimex100 = 270/100 ps
3175 14:44:03.609304 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3176 14:44:03.609404 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3177 14:44:03.609501 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 14:44:03.609598 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3179 14:44:03.609695 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 14:44:03.609799 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3181 14:44:03.609904
3182 14:44:03.610002 CA PerBit enable=1, Macro0, CA PI delay=33
3183 14:44:03.610100
3184 14:44:03.610204 [CBTSetCACLKResult] CA Dly = 33
3185 14:44:03.610303 CS Dly: 6 (0~37)
3186 14:44:03.610417 ==
3187 14:44:03.610515 Dram Type= 6, Freq= 0, CH_1, rank 1
3188 14:44:03.610612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 14:44:03.610710 ==
3190 14:44:03.610808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3191 14:44:03.610920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3192 14:44:03.611020 [CA 0] Center 37 (7~68) winsize 62
3193 14:44:03.611118 [CA 1] Center 38 (8~68) winsize 61
3194 14:44:03.611215 [CA 2] Center 34 (4~65) winsize 62
3195 14:44:03.611311 [CA 3] Center 33 (3~64) winsize 62
3196 14:44:03.611416 [CA 4] Center 34 (4~65) winsize 62
3197 14:44:03.611524 [CA 5] Center 33 (3~64) winsize 62
3198 14:44:03.611621
3199 14:44:03.611717 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3200 14:44:03.611815
3201 14:44:03.611912 [CATrainingPosCal] consider 2 rank data
3202 14:44:03.612257 u2DelayCellTimex100 = 270/100 ps
3203 14:44:03.612372 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3204 14:44:03.612476 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3205 14:44:03.612594 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3206 14:44:03.612707 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3207 14:44:03.612791 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3208 14:44:03.612876 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3209 14:44:03.612961
3210 14:44:03.613053 CA PerBit enable=1, Macro0, CA PI delay=33
3211 14:44:03.613144
3212 14:44:03.613228 [CBTSetCACLKResult] CA Dly = 33
3213 14:44:03.613312 CS Dly: 7 (0~40)
3214 14:44:03.613395
3215 14:44:03.613478 ----->DramcWriteLeveling(PI) begin...
3216 14:44:03.613565 ==
3217 14:44:03.613662 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 14:44:03.613747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 14:44:03.613832 ==
3220 14:44:03.613916 Write leveling (Byte 0): 25 => 25
3221 14:44:03.614001 Write leveling (Byte 1): 28 => 28
3222 14:44:03.614085 DramcWriteLeveling(PI) end<-----
3223 14:44:03.614189
3224 14:44:03.614276 ==
3225 14:44:03.614360 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 14:44:03.614445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 14:44:03.614529 ==
3228 14:44:03.614612 [Gating] SW mode calibration
3229 14:44:03.614714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3230 14:44:03.614802 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3231 14:44:03.614886 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3232 14:44:03.614970 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3233 14:44:03.615054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3234 14:44:03.615138 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3235 14:44:03.615235 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 14:44:03.615321 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 14:44:03.615405 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3238 14:44:03.615489 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3239 14:44:03.615573 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 14:44:03.615657 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 14:44:03.615749 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3242 14:44:03.615839 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 14:44:03.615923 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 14:44:03.616008 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 14:44:03.616092 1 0 24 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
3246 14:44:03.616176 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3247 14:44:03.616265 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 14:44:03.616356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 14:44:03.616442 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 14:44:03.616527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 14:44:03.616610 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 14:44:03.616694 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 14:44:03.616778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3254 14:44:03.616875 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3255 14:44:03.616961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 14:44:03.617045 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 14:44:03.617128 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 14:44:03.617212 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 14:44:03.617296 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 14:44:03.617387 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 14:44:03.617477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 14:44:03.617561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 14:44:03.617645 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 14:44:03.617736 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 14:44:03.617810 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 14:44:03.617887 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 14:44:03.617969 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 14:44:03.618042 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 14:44:03.618116 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3270 14:44:03.618195 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3271 14:44:03.618270 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 14:44:03.618343 Total UI for P1: 0, mck2ui 16
3273 14:44:03.618422 best dqsien dly found for B0: ( 1, 3, 26)
3274 14:44:03.618504 Total UI for P1: 0, mck2ui 16
3275 14:44:03.618579 best dqsien dly found for B1: ( 1, 3, 26)
3276 14:44:03.618653 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3277 14:44:03.618726 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3278 14:44:03.618800
3279 14:44:03.618873 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3280 14:44:03.618952 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3281 14:44:03.619033 [Gating] SW calibration Done
3282 14:44:03.619108 ==
3283 14:44:03.619182 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 14:44:03.619256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 14:44:03.619330 ==
3286 14:44:03.619403 RX Vref Scan: 0
3287 14:44:03.619478
3288 14:44:03.619561 RX Vref 0 -> 0, step: 1
3289 14:44:03.619636
3290 14:44:03.619709 RX Delay -40 -> 252, step: 8
3291 14:44:03.619783 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3292 14:44:03.619857 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3293 14:44:03.619930 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3294 14:44:03.620004 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3295 14:44:03.620088 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3296 14:44:03.620162 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3297 14:44:03.620236 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3298 14:44:03.620309 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3299 14:44:03.620383 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3300 14:44:03.620456 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3301 14:44:03.620530 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3302 14:44:03.620614 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3303 14:44:03.620689 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3304 14:44:03.620974 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3305 14:44:03.621058 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3306 14:44:03.621143 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3307 14:44:03.621219 ==
3308 14:44:03.621293 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 14:44:03.621368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 14:44:03.621442 ==
3311 14:44:03.621516 DQS Delay:
3312 14:44:03.621590 DQS0 = 0, DQS1 = 0
3313 14:44:03.621675 DQM Delay:
3314 14:44:03.621750 DQM0 = 117, DQM1 = 109
3315 14:44:03.621869 DQ Delay:
3316 14:44:03.621984 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3317 14:44:03.622116 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3318 14:44:03.622259 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3319 14:44:03.622380 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3320 14:44:03.622497
3321 14:44:03.622613
3322 14:44:03.622721 ==
3323 14:44:03.622827 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 14:44:03.622930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 14:44:03.623033 ==
3326 14:44:03.623135
3327 14:44:03.623230
3328 14:44:03.623301 TX Vref Scan disable
3329 14:44:03.623368 == TX Byte 0 ==
3330 14:44:03.623434 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3331 14:44:03.623501 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3332 14:44:03.623567 == TX Byte 1 ==
3333 14:44:03.623633 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3334 14:44:03.623699 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3335 14:44:03.623777 ==
3336 14:44:03.623845 Dram Type= 6, Freq= 0, CH_1, rank 0
3337 14:44:03.623911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3338 14:44:03.623978 ==
3339 14:44:03.624043 TX Vref=22, minBit 10, minWin=25, winSum=416
3340 14:44:03.624110 TX Vref=24, minBit 9, minWin=25, winSum=421
3341 14:44:03.624176 TX Vref=26, minBit 8, minWin=25, winSum=431
3342 14:44:03.624241 TX Vref=28, minBit 10, minWin=26, winSum=435
3343 14:44:03.624316 TX Vref=30, minBit 7, minWin=26, winSum=433
3344 14:44:03.624383 TX Vref=32, minBit 9, minWin=25, winSum=429
3345 14:44:03.624449 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
3346 14:44:03.624515
3347 14:44:03.624580 Final TX Range 1 Vref 28
3348 14:44:03.624646
3349 14:44:03.624711 ==
3350 14:44:03.624779 Dram Type= 6, Freq= 0, CH_1, rank 0
3351 14:44:03.624854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3352 14:44:03.624920 ==
3353 14:44:03.624986
3354 14:44:03.625051
3355 14:44:03.625116 TX Vref Scan disable
3356 14:44:03.625181 == TX Byte 0 ==
3357 14:44:03.625247 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3358 14:44:03.625314 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3359 14:44:03.625389 == TX Byte 1 ==
3360 14:44:03.625455 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3361 14:44:03.625521 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3362 14:44:03.625586
3363 14:44:03.625651 [DATLAT]
3364 14:44:03.625715 Freq=1200, CH1 RK0
3365 14:44:03.625781
3366 14:44:03.625845 DATLAT Default: 0xd
3367 14:44:03.625919 0, 0xFFFF, sum = 0
3368 14:44:03.625986 1, 0xFFFF, sum = 0
3369 14:44:03.626052 2, 0xFFFF, sum = 0
3370 14:44:03.626118 3, 0xFFFF, sum = 0
3371 14:44:03.626190 4, 0xFFFF, sum = 0
3372 14:44:03.626256 5, 0xFFFF, sum = 0
3373 14:44:03.626322 6, 0xFFFF, sum = 0
3374 14:44:03.626392 7, 0xFFFF, sum = 0
3375 14:44:03.626465 8, 0xFFFF, sum = 0
3376 14:44:03.626532 9, 0xFFFF, sum = 0
3377 14:44:03.626598 10, 0xFFFF, sum = 0
3378 14:44:03.626664 11, 0xFFFF, sum = 0
3379 14:44:03.626729 12, 0x0, sum = 1
3380 14:44:03.626795 13, 0x0, sum = 2
3381 14:44:03.626860 14, 0x0, sum = 3
3382 14:44:03.626931 15, 0x0, sum = 4
3383 14:44:03.627002 best_step = 13
3384 14:44:03.627067
3385 14:44:03.627132 ==
3386 14:44:03.627197 Dram Type= 6, Freq= 0, CH_1, rank 0
3387 14:44:03.627263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3388 14:44:03.627328 ==
3389 14:44:03.627393 RX Vref Scan: 1
3390 14:44:03.627461
3391 14:44:03.627531 Set Vref Range= 32 -> 127
3392 14:44:03.627597
3393 14:44:03.627661 RX Vref 32 -> 127, step: 1
3394 14:44:03.627734
3395 14:44:03.627791 RX Delay -21 -> 252, step: 4
3396 14:44:03.627849
3397 14:44:03.627907 Set Vref, RX VrefLevel [Byte0]: 32
3398 14:44:03.627965 [Byte1]: 32
3399 14:44:03.628032
3400 14:44:03.628092 Set Vref, RX VrefLevel [Byte0]: 33
3401 14:44:03.628150 [Byte1]: 33
3402 14:44:03.628209
3403 14:44:03.628267 Set Vref, RX VrefLevel [Byte0]: 34
3404 14:44:03.628325 [Byte1]: 34
3405 14:44:03.628384
3406 14:44:03.628443 Set Vref, RX VrefLevel [Byte0]: 35
3407 14:44:03.628506 [Byte1]: 35
3408 14:44:03.628571
3409 14:44:03.628630 Set Vref, RX VrefLevel [Byte0]: 36
3410 14:44:03.628689 [Byte1]: 36
3411 14:44:03.628748
3412 14:44:03.628806 Set Vref, RX VrefLevel [Byte0]: 37
3413 14:44:03.628864 [Byte1]: 37
3414 14:44:03.628922
3415 14:44:03.628980 Set Vref, RX VrefLevel [Byte0]: 38
3416 14:44:03.629044 [Byte1]: 38
3417 14:44:03.629107
3418 14:44:03.629166 Set Vref, RX VrefLevel [Byte0]: 39
3419 14:44:03.629224 [Byte1]: 39
3420 14:44:03.629282
3421 14:44:03.629341 Set Vref, RX VrefLevel [Byte0]: 40
3422 14:44:03.629399 [Byte1]: 40
3423 14:44:03.629458
3424 14:44:03.629516 Set Vref, RX VrefLevel [Byte0]: 41
3425 14:44:03.629578 [Byte1]: 41
3426 14:44:03.629642
3427 14:44:03.629700 Set Vref, RX VrefLevel [Byte0]: 42
3428 14:44:03.629759 [Byte1]: 42
3429 14:44:03.629817
3430 14:44:03.629874 Set Vref, RX VrefLevel [Byte0]: 43
3431 14:44:03.629933 [Byte1]: 43
3432 14:44:03.629991
3433 14:44:03.630049 Set Vref, RX VrefLevel [Byte0]: 44
3434 14:44:03.630116 [Byte1]: 44
3435 14:44:03.630204
3436 14:44:03.630264 Set Vref, RX VrefLevel [Byte0]: 45
3437 14:44:03.630323 [Byte1]: 45
3438 14:44:03.630381
3439 14:44:03.630439 Set Vref, RX VrefLevel [Byte0]: 46
3440 14:44:03.630498 [Byte1]: 46
3441 14:44:03.630556
3442 14:44:03.630619 Set Vref, RX VrefLevel [Byte0]: 47
3443 14:44:03.630682 [Byte1]: 47
3444 14:44:03.630741
3445 14:44:03.630799 Set Vref, RX VrefLevel [Byte0]: 48
3446 14:44:03.630857 [Byte1]: 48
3447 14:44:03.630915
3448 14:44:03.630973 Set Vref, RX VrefLevel [Byte0]: 49
3449 14:44:03.631033 [Byte1]: 49
3450 14:44:03.631092
3451 14:44:03.631149 Set Vref, RX VrefLevel [Byte0]: 50
3452 14:44:03.631212 [Byte1]: 50
3453 14:44:03.631276
3454 14:44:03.631334 Set Vref, RX VrefLevel [Byte0]: 51
3455 14:44:03.631392 [Byte1]: 51
3456 14:44:03.631451
3457 14:44:03.631508 Set Vref, RX VrefLevel [Byte0]: 52
3458 14:44:03.631567 [Byte1]: 52
3459 14:44:03.631624
3460 14:44:03.631683 Set Vref, RX VrefLevel [Byte0]: 53
3461 14:44:03.631740 [Byte1]: 53
3462 14:44:03.631798
3463 14:44:03.631867 Set Vref, RX VrefLevel [Byte0]: 54
3464 14:44:03.631927 [Byte1]: 54
3465 14:44:03.631985
3466 14:44:03.632044 Set Vref, RX VrefLevel [Byte0]: 55
3467 14:44:03.632102 [Byte1]: 55
3468 14:44:03.632160
3469 14:44:03.632218 Set Vref, RX VrefLevel [Byte0]: 56
3470 14:44:03.632473 [Byte1]: 56
3471 14:44:03.632540
3472 14:44:03.632600 Set Vref, RX VrefLevel [Byte0]: 57
3473 14:44:03.632659 [Byte1]: 57
3474 14:44:03.632728
3475 14:44:03.632781 Set Vref, RX VrefLevel [Byte0]: 58
3476 14:44:03.632835 [Byte1]: 58
3477 14:44:03.632895
3478 14:44:03.632952 Set Vref, RX VrefLevel [Byte0]: 59
3479 14:44:03.633005 [Byte1]: 59
3480 14:44:03.633059
3481 14:44:03.633112 Set Vref, RX VrefLevel [Byte0]: 60
3482 14:44:03.633165 [Byte1]: 60
3483 14:44:03.633218
3484 14:44:03.633271 Set Vref, RX VrefLevel [Byte0]: 61
3485 14:44:03.633324 [Byte1]: 61
3486 14:44:03.633377
3487 14:44:03.633438 Set Vref, RX VrefLevel [Byte0]: 62
3488 14:44:03.633491 [Byte1]: 62
3489 14:44:03.633545
3490 14:44:03.633597 Set Vref, RX VrefLevel [Byte0]: 63
3491 14:44:03.633651 [Byte1]: 63
3492 14:44:03.633704
3493 14:44:03.633756 Set Vref, RX VrefLevel [Byte0]: 64
3494 14:44:03.633810 [Byte1]: 64
3495 14:44:03.633863
3496 14:44:03.633919 Set Vref, RX VrefLevel [Byte0]: 65
3497 14:44:03.633977 [Byte1]: 65
3498 14:44:03.634031
3499 14:44:03.634083 Set Vref, RX VrefLevel [Byte0]: 66
3500 14:44:03.634136 [Byte1]: 66
3501 14:44:03.634196
3502 14:44:03.634249 Set Vref, RX VrefLevel [Byte0]: 67
3503 14:44:03.634302 [Byte1]: 67
3504 14:44:03.634356
3505 14:44:03.634408 Set Vref, RX VrefLevel [Byte0]: 68
3506 14:44:03.634468 [Byte1]: 68
3507 14:44:03.634526
3508 14:44:03.634580 Set Vref, RX VrefLevel [Byte0]: 69
3509 14:44:03.634633 [Byte1]: 69
3510 14:44:03.634686
3511 14:44:03.634739 Final RX Vref Byte 0 = 51 to rank0
3512 14:44:03.634792 Final RX Vref Byte 1 = 55 to rank0
3513 14:44:03.634845 Final RX Vref Byte 0 = 51 to rank1
3514 14:44:03.634898 Final RX Vref Byte 1 = 55 to rank1==
3515 14:44:03.634952 Dram Type= 6, Freq= 0, CH_1, rank 0
3516 14:44:03.635013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 14:44:03.635067 ==
3518 14:44:03.635121 DQS Delay:
3519 14:44:03.635174 DQS0 = 0, DQS1 = 0
3520 14:44:03.635227 DQM Delay:
3521 14:44:03.635280 DQM0 = 116, DQM1 = 110
3522 14:44:03.635332 DQ Delay:
3523 14:44:03.635385 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3524 14:44:03.635438 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3525 14:44:03.635495 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3526 14:44:03.635551 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3527 14:44:03.635605
3528 14:44:03.635658
3529 14:44:03.635711 [DQSOSCAuto] RK0, (LSB)MR18= 0x6fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3530 14:44:03.635765 CH1 RK0: MR19=403, MR18=6FA
3531 14:44:03.635818 CH1_RK0: MR19=0x403, MR18=0x6FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3532 14:44:03.635872
3533 14:44:03.635925 ----->DramcWriteLeveling(PI) begin...
3534 14:44:03.635980 ==
3535 14:44:03.636039 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 14:44:03.636096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 14:44:03.636150 ==
3538 14:44:03.636203 Write leveling (Byte 0): 25 => 25
3539 14:44:03.636256 Write leveling (Byte 1): 29 => 29
3540 14:44:03.636309 DramcWriteLeveling(PI) end<-----
3541 14:44:03.636362
3542 14:44:03.636414 ==
3543 14:44:03.636466 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 14:44:03.636523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 14:44:03.636581 ==
3546 14:44:03.636635 [Gating] SW mode calibration
3547 14:44:03.636691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3548 14:44:03.636746 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3549 14:44:03.636800 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 14:44:03.636853 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 14:44:03.636906 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 14:44:03.636959 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 14:44:03.637012 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3554 14:44:03.637072 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3555 14:44:03.637131 0 15 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 1)
3556 14:44:03.637184 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
3557 14:44:03.637238 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 14:44:03.637291 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 14:44:03.637344 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 14:44:03.637397 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 14:44:03.637450 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3562 14:44:03.637503 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3563 14:44:03.637556 1 0 24 | B1->B0 | 3535 2323 | 0 0 | (0 0) (0 0)
3564 14:44:03.637617 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3565 14:44:03.637671 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 14:44:03.637736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 14:44:03.637788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 14:44:03.637840 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 14:44:03.637893 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 14:44:03.637945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 14:44:03.637997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3572 14:44:03.638048 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3573 14:44:03.638108 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 14:44:03.638229 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 14:44:03.638284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 14:44:03.638336 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 14:44:03.638389 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 14:44:03.638441 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 14:44:03.638493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 14:44:03.638546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 14:44:03.638598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 14:44:03.638657 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 14:44:03.638710 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 14:44:03.638762 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 14:44:03.638815 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 14:44:03.639057 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 14:44:03.639115 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3588 14:44:03.639176 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3589 14:44:03.639230 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3590 14:44:03.639282 Total UI for P1: 0, mck2ui 16
3591 14:44:03.639334 best dqsien dly found for B0: ( 1, 3, 26)
3592 14:44:03.639387 Total UI for P1: 0, mck2ui 16
3593 14:44:03.639439 best dqsien dly found for B1: ( 1, 3, 26)
3594 14:44:03.639491 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3595 14:44:03.639543 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3596 14:44:03.639595
3597 14:44:03.639646 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3598 14:44:03.639706 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3599 14:44:03.639759 [Gating] SW calibration Done
3600 14:44:03.639811 ==
3601 14:44:03.639862 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 14:44:03.639914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 14:44:03.639967 ==
3604 14:44:03.640019 RX Vref Scan: 0
3605 14:44:03.640071
3606 14:44:03.640123 RX Vref 0 -> 0, step: 1
3607 14:44:03.640174
3608 14:44:03.640235 RX Delay -40 -> 252, step: 8
3609 14:44:03.640289 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3610 14:44:03.640341 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3611 14:44:03.640393 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3612 14:44:03.640445 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3613 14:44:03.640496 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3614 14:44:03.640548 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3615 14:44:03.640600 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3616 14:44:03.640652 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3617 14:44:03.640703 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3618 14:44:03.640763 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3619 14:44:03.640817 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3620 14:44:03.640868 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3621 14:44:03.640920 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3622 14:44:03.640972 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3623 14:44:03.641024 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3624 14:44:03.641075 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3625 14:44:03.641127 ==
3626 14:44:03.641178 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 14:44:03.641230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 14:44:03.641290 ==
3629 14:44:03.641343 DQS Delay:
3630 14:44:03.641394 DQS0 = 0, DQS1 = 0
3631 14:44:03.641446 DQM Delay:
3632 14:44:03.641497 DQM0 = 116, DQM1 = 110
3633 14:44:03.641548 DQ Delay:
3634 14:44:03.641600 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3635 14:44:03.641652 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3636 14:44:03.641703 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3637 14:44:03.641755 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3638 14:44:03.641814
3639 14:44:03.641867
3640 14:44:03.641918 ==
3641 14:44:03.641969 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 14:44:03.642021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 14:44:03.642074 ==
3644 14:44:03.642126
3645 14:44:03.642214
3646 14:44:03.642267 TX Vref Scan disable
3647 14:44:03.642325 == TX Byte 0 ==
3648 14:44:03.642383 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3649 14:44:03.642436 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3650 14:44:03.642488 == TX Byte 1 ==
3651 14:44:03.642540 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3652 14:44:03.642592 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3653 14:44:03.642644 ==
3654 14:44:03.642696 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 14:44:03.642748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 14:44:03.642800 ==
3657 14:44:03.642855 TX Vref=22, minBit 8, minWin=25, winSum=420
3658 14:44:03.642909 TX Vref=24, minBit 1, minWin=26, winSum=426
3659 14:44:03.642967 TX Vref=26, minBit 9, minWin=26, winSum=433
3660 14:44:03.643020 TX Vref=28, minBit 8, minWin=26, winSum=434
3661 14:44:03.643072 TX Vref=30, minBit 8, minWin=26, winSum=436
3662 14:44:03.643123 TX Vref=32, minBit 8, minWin=26, winSum=431
3663 14:44:03.643175 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3664 14:44:03.643227
3665 14:44:03.643279 Final TX Range 1 Vref 30
3666 14:44:03.643331
3667 14:44:03.643382 ==
3668 14:44:03.643440 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 14:44:03.643493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 14:44:03.643549 ==
3671 14:44:03.643601
3672 14:44:03.643652
3673 14:44:03.643704 TX Vref Scan disable
3674 14:44:03.643755 == TX Byte 0 ==
3675 14:44:03.643807 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3676 14:44:03.643859 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3677 14:44:03.643911 == TX Byte 1 ==
3678 14:44:03.643962 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3679 14:44:03.644020 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3680 14:44:03.644073
3681 14:44:03.644129 [DATLAT]
3682 14:44:03.644180 Freq=1200, CH1 RK1
3683 14:44:03.644232
3684 14:44:03.644285 DATLAT Default: 0xd
3685 14:44:03.644337 0, 0xFFFF, sum = 0
3686 14:44:03.644390 1, 0xFFFF, sum = 0
3687 14:44:03.644443 2, 0xFFFF, sum = 0
3688 14:44:03.644495 3, 0xFFFF, sum = 0
3689 14:44:03.644547 4, 0xFFFF, sum = 0
3690 14:44:03.644607 5, 0xFFFF, sum = 0
3691 14:44:03.644664 6, 0xFFFF, sum = 0
3692 14:44:03.644718 7, 0xFFFF, sum = 0
3693 14:44:03.644771 8, 0xFFFF, sum = 0
3694 14:44:03.644823 9, 0xFFFF, sum = 0
3695 14:44:03.644875 10, 0xFFFF, sum = 0
3696 14:44:03.644928 11, 0xFFFF, sum = 0
3697 14:44:03.644980 12, 0x0, sum = 1
3698 14:44:03.645032 13, 0x0, sum = 2
3699 14:44:03.645085 14, 0x0, sum = 3
3700 14:44:03.645141 15, 0x0, sum = 4
3701 14:44:03.645198 best_step = 13
3702 14:44:03.645249
3703 14:44:03.645301 ==
3704 14:44:03.645352 Dram Type= 6, Freq= 0, CH_1, rank 1
3705 14:44:03.645404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3706 14:44:03.645456 ==
3707 14:44:03.645507 RX Vref Scan: 0
3708 14:44:03.645558
3709 14:44:03.645610 RX Vref 0 -> 0, step: 1
3710 14:44:03.645661
3711 14:44:03.645719 RX Delay -21 -> 252, step: 4
3712 14:44:03.645776 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3713 14:44:03.645828 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3714 14:44:03.645880 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3715 14:44:03.645932 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3716 14:44:03.645983 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3717 14:44:03.646035 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3718 14:44:03.646086 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3719 14:44:03.646138 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3720 14:44:03.646223 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3721 14:44:03.646294 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3722 14:44:03.646349 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3723 14:44:03.646401 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3724 14:44:03.646647 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3725 14:44:03.646725 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3726 14:44:03.646794 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3727 14:44:03.646852 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3728 14:44:03.646906 ==
3729 14:44:03.646963 Dram Type= 6, Freq= 0, CH_1, rank 1
3730 14:44:03.647015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3731 14:44:03.647069 ==
3732 14:44:03.647121 DQS Delay:
3733 14:44:03.647173 DQS0 = 0, DQS1 = 0
3734 14:44:03.647224 DQM Delay:
3735 14:44:03.647276 DQM0 = 116, DQM1 = 110
3736 14:44:03.647327 DQ Delay:
3737 14:44:03.647379 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3738 14:44:03.647435 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =114
3739 14:44:03.647488 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3740 14:44:03.647545 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3741 14:44:03.647597
3742 14:44:03.647648
3743 14:44:03.647700 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3744 14:44:03.647754 CH1 RK1: MR19=303, MR18=F7F2
3745 14:44:03.647806 CH1_RK1: MR19=0x303, MR18=0xF7F2, DQSOSC=413, MR23=63, INC=38, DEC=25
3746 14:44:03.647858 [RxdqsGatingPostProcess] freq 1200
3747 14:44:03.647910 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3748 14:44:03.647963 best DQS0 dly(2T, 0.5T) = (0, 11)
3749 14:44:03.648020 best DQS1 dly(2T, 0.5T) = (0, 11)
3750 14:44:03.648073 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3751 14:44:03.648128 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3752 14:44:03.648180 best DQS0 dly(2T, 0.5T) = (0, 11)
3753 14:44:03.648232 best DQS1 dly(2T, 0.5T) = (0, 11)
3754 14:44:03.648284 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3755 14:44:03.648336 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3756 14:44:03.648387 Pre-setting of DQS Precalculation
3757 14:44:03.648439 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3758 14:44:03.648491 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3759 14:44:03.648544 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3760 14:44:03.648615
3761 14:44:03.648699
3762 14:44:03.648780 [Calibration Summary] 2400 Mbps
3763 14:44:03.648861 CH 0, Rank 0
3764 14:44:03.648942 SW Impedance : PASS
3765 14:44:03.649024 DUTY Scan : NO K
3766 14:44:03.649105 ZQ Calibration : PASS
3767 14:44:03.649189 Jitter Meter : NO K
3768 14:44:03.649261 CBT Training : PASS
3769 14:44:03.649315 Write leveling : PASS
3770 14:44:03.649367 RX DQS gating : PASS
3771 14:44:03.649419 RX DQ/DQS(RDDQC) : PASS
3772 14:44:03.649470 TX DQ/DQS : PASS
3773 14:44:03.649523 RX DATLAT : PASS
3774 14:44:03.649574 RX DQ/DQS(Engine): PASS
3775 14:44:03.649626 TX OE : NO K
3776 14:44:03.649679 All Pass.
3777 14:44:03.649736
3778 14:44:03.649788 CH 0, Rank 1
3779 14:44:03.649869 SW Impedance : PASS
3780 14:44:03.649950 DUTY Scan : NO K
3781 14:44:03.650031 ZQ Calibration : PASS
3782 14:44:03.650111 Jitter Meter : NO K
3783 14:44:03.650226 CBT Training : PASS
3784 14:44:03.650325 Write leveling : PASS
3785 14:44:03.650409 RX DQS gating : PASS
3786 14:44:03.650503 RX DQ/DQS(RDDQC) : PASS
3787 14:44:03.650571 TX DQ/DQS : PASS
3788 14:44:03.650625 RX DATLAT : PASS
3789 14:44:03.650677 RX DQ/DQS(Engine): PASS
3790 14:44:03.650729 TX OE : NO K
3791 14:44:03.650781 All Pass.
3792 14:44:03.650834
3793 14:44:03.650893 CH 1, Rank 0
3794 14:44:03.650951 SW Impedance : PASS
3795 14:44:03.651005 DUTY Scan : NO K
3796 14:44:03.651057 ZQ Calibration : PASS
3797 14:44:03.651109 Jitter Meter : NO K
3798 14:44:03.651161 CBT Training : PASS
3799 14:44:03.651213 Write leveling : PASS
3800 14:44:03.651265 RX DQS gating : PASS
3801 14:44:03.651340 RX DQ/DQS(RDDQC) : PASS
3802 14:44:03.651406 TX DQ/DQS : PASS
3803 14:44:03.651463 RX DATLAT : PASS
3804 14:44:03.651516 RX DQ/DQS(Engine): PASS
3805 14:44:03.651597 TX OE : NO K
3806 14:44:03.651679 All Pass.
3807 14:44:03.651759
3808 14:44:03.651841 CH 1, Rank 1
3809 14:44:03.651922 SW Impedance : PASS
3810 14:44:03.652003 DUTY Scan : NO K
3811 14:44:03.652087 ZQ Calibration : PASS
3812 14:44:03.652170 Jitter Meter : NO K
3813 14:44:03.652251 CBT Training : PASS
3814 14:44:03.652332 Write leveling : PASS
3815 14:44:03.652413 RX DQS gating : PASS
3816 14:44:03.652494 RX DQ/DQS(RDDQC) : PASS
3817 14:44:03.652574 TX DQ/DQS : PASS
3818 14:44:03.652659 RX DATLAT : PASS
3819 14:44:03.652742 RX DQ/DQS(Engine): PASS
3820 14:44:03.652823 TX OE : NO K
3821 14:44:03.652904 All Pass.
3822 14:44:03.652984
3823 14:44:03.653065 DramC Write-DBI off
3824 14:44:03.653146 PER_BANK_REFRESH: Hybrid Mode
3825 14:44:03.653213 TX_TRACKING: ON
3826 14:44:03.653271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3827 14:44:03.653354 [FAST_K] Save calibration result to emmc
3828 14:44:03.653436 dramc_set_vcore_voltage set vcore to 650000
3829 14:44:03.653518 Read voltage for 600, 5
3830 14:44:03.653598 Vio18 = 0
3831 14:44:03.653679 Vcore = 650000
3832 14:44:03.653751 Vdram = 0
3833 14:44:03.653835 Vddq = 0
3834 14:44:03.653918 Vmddr = 0
3835 14:44:03.654000 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3836 14:44:03.654082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3837 14:44:03.654168 MEM_TYPE=3, freq_sel=19
3838 14:44:03.654265 sv_algorithm_assistance_LP4_1600
3839 14:44:03.654318 ============ PULL DRAM RESETB DOWN ============
3840 14:44:03.654377 ========== PULL DRAM RESETB DOWN end =========
3841 14:44:03.654431 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3842 14:44:03.654514 ===================================
3843 14:44:03.654595 LPDDR4 DRAM CONFIGURATION
3844 14:44:03.654677 ===================================
3845 14:44:03.654758 EX_ROW_EN[0] = 0x0
3846 14:44:03.654839 EX_ROW_EN[1] = 0x0
3847 14:44:03.654921 LP4Y_EN = 0x0
3848 14:44:03.654978 WORK_FSP = 0x0
3849 14:44:03.655033 WL = 0x2
3850 14:44:03.655086 RL = 0x2
3851 14:44:03.655137 BL = 0x2
3852 14:44:03.655189 RPST = 0x0
3853 14:44:03.655241 RD_PRE = 0x0
3854 14:44:03.655292 WR_PRE = 0x1
3855 14:44:03.655344 WR_PST = 0x0
3856 14:44:03.655395 DBI_WR = 0x0
3857 14:44:03.655446 DBI_RD = 0x0
3858 14:44:03.655504 OTF = 0x1
3859 14:44:03.655559 ===================================
3860 14:44:03.655613 ===================================
3861 14:44:03.655666 ANA top config
3862 14:44:03.655717 ===================================
3863 14:44:03.655769 DLL_ASYNC_EN = 0
3864 14:44:03.655821 ALL_SLAVE_EN = 1
3865 14:44:03.655873 NEW_RANK_MODE = 1
3866 14:44:03.655926 DLL_IDLE_MODE = 1
3867 14:44:03.655978 LP45_APHY_COMB_EN = 1
3868 14:44:03.656030 TX_ODT_DIS = 1
3869 14:44:03.656283 NEW_8X_MODE = 1
3870 14:44:03.656372 ===================================
3871 14:44:03.656456 ===================================
3872 14:44:03.656538 data_rate = 1200
3873 14:44:03.656619 CKR = 1
3874 14:44:03.656704 DQ_P2S_RATIO = 8
3875 14:44:03.656788 ===================================
3876 14:44:03.656869 CA_P2S_RATIO = 8
3877 14:44:03.656950 DQ_CA_OPEN = 0
3878 14:44:03.657031 DQ_SEMI_OPEN = 0
3879 14:44:03.657112 CA_SEMI_OPEN = 0
3880 14:44:03.657193 CA_FULL_RATE = 0
3881 14:44:03.657259 DQ_CKDIV4_EN = 1
3882 14:44:03.657315 CA_CKDIV4_EN = 1
3883 14:44:03.657368 CA_PREDIV_EN = 0
3884 14:44:03.657419 PH8_DLY = 0
3885 14:44:03.657472 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3886 14:44:03.657523 DQ_AAMCK_DIV = 4
3887 14:44:03.657575 CA_AAMCK_DIV = 4
3888 14:44:03.657626 CA_ADMCK_DIV = 4
3889 14:44:03.657678 DQ_TRACK_CA_EN = 0
3890 14:44:03.657731 CA_PICK = 600
3891 14:44:03.657788 CA_MCKIO = 600
3892 14:44:03.657870 MCKIO_SEMI = 0
3893 14:44:03.657953 PLL_FREQ = 2288
3894 14:44:03.658034 DQ_UI_PI_RATIO = 32
3895 14:44:03.658115 CA_UI_PI_RATIO = 0
3896 14:44:03.658256 ===================================
3897 14:44:03.658332 ===================================
3898 14:44:03.658391 memory_type:LPDDR4
3899 14:44:03.658445 GP_NUM : 10
3900 14:44:03.658500 SRAM_EN : 1
3901 14:44:03.658552 MD32_EN : 0
3902 14:44:03.658605 ===================================
3903 14:44:03.658657 [ANA_INIT] >>>>>>>>>>>>>>
3904 14:44:03.658709 <<<<<< [CONFIGURE PHASE]: ANA_TX
3905 14:44:03.658762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3906 14:44:03.658814 ===================================
3907 14:44:03.658866 data_rate = 1200,PCW = 0X5800
3908 14:44:03.658918 ===================================
3909 14:44:03.658977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3910 14:44:03.659035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3911 14:44:03.659118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3912 14:44:03.659200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3913 14:44:03.659282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3914 14:44:03.659406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3915 14:44:03.659488 [ANA_INIT] flow start
3916 14:44:03.659572 [ANA_INIT] PLL >>>>>>>>
3917 14:44:03.659656 [ANA_INIT] PLL <<<<<<<<
3918 14:44:03.659736 [ANA_INIT] MIDPI >>>>>>>>
3919 14:44:03.659818 [ANA_INIT] MIDPI <<<<<<<<
3920 14:44:03.659898 [ANA_INIT] DLL >>>>>>>>
3921 14:44:03.659979 [ANA_INIT] flow end
3922 14:44:03.660061 ============ LP4 DIFF to SE enter ============
3923 14:44:03.660130 ============ LP4 DIFF to SE exit ============
3924 14:44:03.660185 [ANA_INIT] <<<<<<<<<<<<<
3925 14:44:03.660238 [Flow] Enable top DCM control >>>>>
3926 14:44:03.660290 [Flow] Enable top DCM control <<<<<
3927 14:44:03.660342 Enable DLL master slave shuffle
3928 14:44:03.660396 ==============================================================
3929 14:44:03.660448 Gating Mode config
3930 14:44:03.660500 ==============================================================
3931 14:44:03.660553 Config description:
3932 14:44:03.660605 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3933 14:44:03.660659 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3934 14:44:03.660744 SELPH_MODE 0: By rank 1: By Phase
3935 14:44:03.660829 ==============================================================
3936 14:44:03.660911 GAT_TRACK_EN = 1
3937 14:44:03.660992 RX_GATING_MODE = 2
3938 14:44:03.661078 RX_GATING_TRACK_MODE = 2
3939 14:44:03.661161 SELPH_MODE = 1
3940 14:44:03.661242 PICG_EARLY_EN = 1
3941 14:44:03.661303 VALID_LAT_VALUE = 1
3942 14:44:03.661358 ==============================================================
3943 14:44:03.661412 Enter into Gating configuration >>>>
3944 14:44:03.661464 Exit from Gating configuration <<<<
3945 14:44:03.661516 Enter into DVFS_PRE_config >>>>>
3946 14:44:03.661568 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3947 14:44:03.661622 Exit from DVFS_PRE_config <<<<<
3948 14:44:03.661673 Enter into PICG configuration >>>>
3949 14:44:03.661725 Exit from PICG configuration <<<<
3950 14:44:03.661777 [RX_INPUT] configuration >>>>>
3951 14:44:03.661829 [RX_INPUT] configuration <<<<<
3952 14:44:03.661911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3953 14:44:03.661996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3954 14:44:03.662078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 14:44:03.662165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 14:44:03.662276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3957 14:44:03.662329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3958 14:44:03.662396 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3959 14:44:03.662680 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3960 14:44:03.669530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3961 14:44:03.672733 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3962 14:44:03.675987 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3963 14:44:03.682522 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3964 14:44:03.685988 ===================================
3965 14:44:03.686088 LPDDR4 DRAM CONFIGURATION
3966 14:44:03.689283 ===================================
3967 14:44:03.692469 EX_ROW_EN[0] = 0x0
3968 14:44:03.695627 EX_ROW_EN[1] = 0x0
3969 14:44:03.695699 LP4Y_EN = 0x0
3970 14:44:03.699196 WORK_FSP = 0x0
3971 14:44:03.699270 WL = 0x2
3972 14:44:03.702396 RL = 0x2
3973 14:44:03.702464 BL = 0x2
3974 14:44:03.705679 RPST = 0x0
3975 14:44:03.705753 RD_PRE = 0x0
3976 14:44:03.709235 WR_PRE = 0x1
3977 14:44:03.709344 WR_PST = 0x0
3978 14:44:03.712290 DBI_WR = 0x0
3979 14:44:03.712407 DBI_RD = 0x0
3980 14:44:03.715461 OTF = 0x1
3981 14:44:03.719341 ===================================
3982 14:44:03.722158 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3983 14:44:03.725517 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3984 14:44:03.731980 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3985 14:44:03.735763 ===================================
3986 14:44:03.735914 LPDDR4 DRAM CONFIGURATION
3987 14:44:03.738574 ===================================
3988 14:44:03.741959 EX_ROW_EN[0] = 0x10
3989 14:44:03.745239 EX_ROW_EN[1] = 0x0
3990 14:44:03.745439 LP4Y_EN = 0x0
3991 14:44:03.748785 WORK_FSP = 0x0
3992 14:44:03.749024 WL = 0x2
3993 14:44:03.752035 RL = 0x2
3994 14:44:03.752274 BL = 0x2
3995 14:44:03.755346 RPST = 0x0
3996 14:44:03.755643 RD_PRE = 0x0
3997 14:44:03.758990 WR_PRE = 0x1
3998 14:44:03.759373 WR_PST = 0x0
3999 14:44:03.762227 DBI_WR = 0x0
4000 14:44:03.762614 DBI_RD = 0x0
4001 14:44:03.765123 OTF = 0x1
4002 14:44:03.915633 ===================================
4003 14:44:03.916100 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4004 14:44:03.916440 nWR fixed to 30
4005 14:44:03.916770 [ModeRegInit_LP4] CH0 RK0
4006 14:44:03.917080 [ModeRegInit_LP4] CH0 RK1
4007 14:44:03.917379 [ModeRegInit_LP4] CH1 RK0
4008 14:44:03.917888 [ModeRegInit_LP4] CH1 RK1
4009 14:44:03.918403 match AC timing 17
4010 14:44:03.918721 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4011 14:44:03.919021 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4012 14:44:03.919374 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4013 14:44:03.919758 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4014 14:44:03.920052 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4015 14:44:03.920340 ==
4016 14:44:03.920624 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 14:44:03.921055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 14:44:03.921351 ==
4019 14:44:03.921636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4020 14:44:03.921935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4021 14:44:03.922251 [CA 0] Center 36 (6~66) winsize 61
4022 14:44:03.922538 [CA 1] Center 36 (6~66) winsize 61
4023 14:44:03.922890 [CA 2] Center 34 (4~65) winsize 62
4024 14:44:03.923223 [CA 3] Center 34 (4~65) winsize 62
4025 14:44:03.923509 [CA 4] Center 33 (3~64) winsize 62
4026 14:44:03.923788 [CA 5] Center 33 (3~64) winsize 62
4027 14:44:03.924063
4028 14:44:03.924339 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4029 14:44:03.924618
4030 14:44:03.924893 [CATrainingPosCal] consider 1 rank data
4031 14:44:03.925172 u2DelayCellTimex100 = 270/100 ps
4032 14:44:03.925448 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4033 14:44:03.925726 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4034 14:44:03.926003 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4035 14:44:03.926370 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4036 14:44:03.926656 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4037 14:44:03.926935 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 14:44:03.927212
4039 14:44:03.927488 CA PerBit enable=1, Macro0, CA PI delay=33
4040 14:44:03.927763
4041 14:44:03.928039 [CBTSetCACLKResult] CA Dly = 33
4042 14:44:03.928326 CS Dly: 6 (0~37)
4043 14:44:03.928660 ==
4044 14:44:03.928942 Dram Type= 6, Freq= 0, CH_0, rank 1
4045 14:44:03.929224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 14:44:03.929563 ==
4047 14:44:03.929860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4048 14:44:03.930141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4049 14:44:03.930496 [CA 0] Center 36 (6~66) winsize 61
4050 14:44:03.931031 [CA 1] Center 36 (6~66) winsize 61
4051 14:44:03.931349 [CA 2] Center 33 (3~64) winsize 62
4052 14:44:03.931744 [CA 3] Center 33 (3~64) winsize 62
4053 14:44:03.932035 [CA 4] Center 33 (3~64) winsize 62
4054 14:44:03.932316 [CA 5] Center 33 (2~64) winsize 63
4055 14:44:03.932599
4056 14:44:03.932943 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4057 14:44:03.933238
4058 14:44:03.936138 [CATrainingPosCal] consider 2 rank data
4059 14:44:03.939531 u2DelayCellTimex100 = 270/100 ps
4060 14:44:03.942576 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4061 14:44:03.948928 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4062 14:44:03.952563 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4063 14:44:03.955989 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4064 14:44:03.959135 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4065 14:44:03.962211 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4066 14:44:03.962394
4067 14:44:03.966085 CA PerBit enable=1, Macro0, CA PI delay=33
4068 14:44:03.966303
4069 14:44:03.968997 [CBTSetCACLKResult] CA Dly = 33
4070 14:44:03.972181 CS Dly: 6 (0~38)
4071 14:44:03.972362
4072 14:44:03.975478 ----->DramcWriteLeveling(PI) begin...
4073 14:44:03.975663 ==
4074 14:44:03.979048 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 14:44:03.982104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 14:44:03.982316 ==
4077 14:44:03.985477 Write leveling (Byte 0): 31 => 31
4078 14:44:03.988931 Write leveling (Byte 1): 30 => 30
4079 14:44:03.991975 DramcWriteLeveling(PI) end<-----
4080 14:44:03.992232
4081 14:44:03.992437 ==
4082 14:44:03.995097 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 14:44:03.998572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 14:44:03.999029 ==
4085 14:44:04.001698 [Gating] SW mode calibration
4086 14:44:04.008246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4087 14:44:04.014769 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4088 14:44:04.018222 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 14:44:04.024712 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4090 14:44:04.028138 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4091 14:44:04.031672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4092 14:44:04.037755 0 9 16 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
4093 14:44:04.041664 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 14:44:04.044957 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 14:44:04.051024 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 14:44:04.054276 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 14:44:04.057790 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4098 14:44:04.064349 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4099 14:44:04.067446 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4100 14:44:04.070940 0 10 16 | B1->B0 | 3333 4444 | 0 1 | (0 0) (0 0)
4101 14:44:04.077854 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 14:44:04.080953 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 14:44:04.084126 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 14:44:04.090837 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 14:44:04.093835 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 14:44:04.097778 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 14:44:04.104026 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4108 14:44:04.107620 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4109 14:44:04.110561 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 14:44:04.116895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 14:44:04.120541 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 14:44:04.123817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 14:44:04.130352 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 14:44:04.133604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 14:44:04.137217 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 14:44:04.143591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 14:44:04.146626 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 14:44:04.150117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 14:44:04.156649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 14:44:04.159882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 14:44:04.163114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 14:44:04.169700 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 14:44:04.173075 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4124 14:44:04.176257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4125 14:44:04.179700 Total UI for P1: 0, mck2ui 16
4126 14:44:04.183023 best dqsien dly found for B0: ( 0, 13, 12)
4127 14:44:04.186298 Total UI for P1: 0, mck2ui 16
4128 14:44:04.189931 best dqsien dly found for B1: ( 0, 13, 12)
4129 14:44:04.192821 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4130 14:44:04.196149 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4131 14:44:04.196576
4132 14:44:04.203009 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4133 14:44:04.206211 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4134 14:44:04.206659 [Gating] SW calibration Done
4135 14:44:04.209291 ==
4136 14:44:04.212595 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 14:44:04.216158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 14:44:04.216587 ==
4139 14:44:04.216921 RX Vref Scan: 0
4140 14:44:04.217233
4141 14:44:04.219382 RX Vref 0 -> 0, step: 1
4142 14:44:04.219808
4143 14:44:04.222584 RX Delay -230 -> 252, step: 16
4144 14:44:04.225930 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4145 14:44:04.229047 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4146 14:44:04.235957 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4147 14:44:04.239202 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4148 14:44:04.242234 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4149 14:44:04.245352 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4150 14:44:04.252260 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4151 14:44:04.255382 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4152 14:44:04.258797 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4153 14:44:04.262109 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4154 14:44:04.268893 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4155 14:44:04.271813 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4156 14:44:04.275326 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4157 14:44:04.278378 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4158 14:44:04.284802 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4159 14:44:04.289014 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4160 14:44:04.289437 ==
4161 14:44:04.291733 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 14:44:04.295545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 14:44:04.295972 ==
4164 14:44:04.298258 DQS Delay:
4165 14:44:04.298677 DQS0 = 0, DQS1 = 0
4166 14:44:04.299084 DQM Delay:
4167 14:44:04.302059 DQM0 = 44, DQM1 = 34
4168 14:44:04.302535 DQ Delay:
4169 14:44:04.305126 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4170 14:44:04.308468 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4171 14:44:04.311692 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4172 14:44:04.315230 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4173 14:44:04.315651
4174 14:44:04.315981
4175 14:44:04.316292 ==
4176 14:44:04.318146 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 14:44:04.324502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 14:44:04.324922 ==
4179 14:44:04.325255
4180 14:44:04.325563
4181 14:44:04.325859 TX Vref Scan disable
4182 14:44:04.328167 == TX Byte 0 ==
4183 14:44:04.331752 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4184 14:44:04.338358 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4185 14:44:04.338779 == TX Byte 1 ==
4186 14:44:04.341704 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4187 14:44:04.347953 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4188 14:44:04.348377 ==
4189 14:44:04.351223 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 14:44:04.354917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 14:44:04.355480 ==
4192 14:44:04.355826
4193 14:44:04.356139
4194 14:44:04.358078 TX Vref Scan disable
4195 14:44:04.361348 == TX Byte 0 ==
4196 14:44:04.364658 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4197 14:44:04.367892 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4198 14:44:04.371572 == TX Byte 1 ==
4199 14:44:04.374816 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4200 14:44:04.377951 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4201 14:44:04.378422
4202 14:44:04.378763 [DATLAT]
4203 14:44:04.381057 Freq=600, CH0 RK0
4204 14:44:04.381477
4205 14:44:04.384764 DATLAT Default: 0x9
4206 14:44:04.385182 0, 0xFFFF, sum = 0
4207 14:44:04.388173 1, 0xFFFF, sum = 0
4208 14:44:04.388598 2, 0xFFFF, sum = 0
4209 14:44:04.391201 3, 0xFFFF, sum = 0
4210 14:44:04.391626 4, 0xFFFF, sum = 0
4211 14:44:04.394453 5, 0xFFFF, sum = 0
4212 14:44:04.394984 6, 0xFFFF, sum = 0
4213 14:44:04.398084 7, 0xFFFF, sum = 0
4214 14:44:04.398556 8, 0x0, sum = 1
4215 14:44:04.401093 9, 0x0, sum = 2
4216 14:44:04.401516 10, 0x0, sum = 3
4217 14:44:04.404471 11, 0x0, sum = 4
4218 14:44:04.404896 best_step = 9
4219 14:44:04.405227
4220 14:44:04.405537 ==
4221 14:44:04.407416 Dram Type= 6, Freq= 0, CH_0, rank 0
4222 14:44:04.410893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 14:44:04.411324 ==
4224 14:44:04.413979 RX Vref Scan: 1
4225 14:44:04.414449
4226 14:44:04.417313 RX Vref 0 -> 0, step: 1
4227 14:44:04.417738
4228 14:44:04.418076 RX Delay -195 -> 252, step: 8
4229 14:44:04.420521
4230 14:44:04.420940 Set Vref, RX VrefLevel [Byte0]: 59
4231 14:44:04.423824 [Byte1]: 58
4232 14:44:04.428995
4233 14:44:04.429418 Final RX Vref Byte 0 = 59 to rank0
4234 14:44:04.432272 Final RX Vref Byte 1 = 58 to rank0
4235 14:44:04.435615 Final RX Vref Byte 0 = 59 to rank1
4236 14:44:04.438745 Final RX Vref Byte 1 = 58 to rank1==
4237 14:44:04.442134 Dram Type= 6, Freq= 0, CH_0, rank 0
4238 14:44:04.448820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 14:44:04.449248 ==
4240 14:44:04.449586 DQS Delay:
4241 14:44:04.451841 DQS0 = 0, DQS1 = 0
4242 14:44:04.452361 DQM Delay:
4243 14:44:04.452708 DQM0 = 44, DQM1 = 31
4244 14:44:04.455281 DQ Delay:
4245 14:44:04.458943 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4246 14:44:04.461875 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4247 14:44:04.465225 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4248 14:44:04.468791 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4249 14:44:04.469218
4250 14:44:04.469551
4251 14:44:04.475276 [DQSOSCAuto] RK0, (LSB)MR18= 0x633a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4252 14:44:04.478777 CH0 RK0: MR19=808, MR18=633A
4253 14:44:04.485173 CH0_RK0: MR19=0x808, MR18=0x633A, DQSOSC=391, MR23=63, INC=171, DEC=114
4254 14:44:04.485658
4255 14:44:04.488648 ----->DramcWriteLeveling(PI) begin...
4256 14:44:04.489148 ==
4257 14:44:04.491419 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 14:44:04.495375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 14:44:04.495813 ==
4260 14:44:04.498311 Write leveling (Byte 0): 35 => 35
4261 14:44:04.501492 Write leveling (Byte 1): 30 => 30
4262 14:44:04.504721 DramcWriteLeveling(PI) end<-----
4263 14:44:04.505192
4264 14:44:04.505524 ==
4265 14:44:04.508131 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 14:44:04.511111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 14:44:04.514435 ==
4268 14:44:04.514903 [Gating] SW mode calibration
4269 14:44:04.524381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4270 14:44:04.527477 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4271 14:44:04.531539 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 14:44:04.537830 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4273 14:44:04.540840 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4274 14:44:04.544158 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
4275 14:44:04.550765 0 9 16 | B1->B0 | 3030 2a2a | 1 1 | (1 1) (1 1)
4276 14:44:04.554108 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 14:44:04.557266 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 14:44:04.563998 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 14:44:04.567592 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 14:44:04.570703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 14:44:04.577228 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 14:44:04.580429 0 10 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4283 14:44:04.583736 0 10 16 | B1->B0 | 3a3a 4040 | 1 0 | (0 0) (0 0)
4284 14:44:04.590515 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 14:44:04.593795 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 14:44:04.596672 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 14:44:04.604237 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 14:44:04.606683 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 14:44:04.610274 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 14:44:04.616878 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4291 14:44:04.619887 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4292 14:44:04.623102 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 14:44:04.629868 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 14:44:04.633540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 14:44:04.636575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 14:44:04.642846 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 14:44:04.646110 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 14:44:04.649444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 14:44:04.656379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 14:44:04.659485 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 14:44:04.663043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 14:44:04.669695 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 14:44:04.672665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 14:44:04.676054 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 14:44:04.682783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 14:44:04.685804 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4307 14:44:04.689134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 14:44:04.692651 Total UI for P1: 0, mck2ui 16
4309 14:44:04.696078 best dqsien dly found for B0: ( 0, 13, 14)
4310 14:44:04.699086 Total UI for P1: 0, mck2ui 16
4311 14:44:04.702256 best dqsien dly found for B1: ( 0, 13, 12)
4312 14:44:04.705469 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4313 14:44:04.712563 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4314 14:44:04.712988
4315 14:44:04.715462 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4316 14:44:04.719073 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4317 14:44:04.722379 [Gating] SW calibration Done
4318 14:44:04.722806 ==
4319 14:44:04.725733 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 14:44:04.729038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 14:44:04.729471 ==
4322 14:44:04.732405 RX Vref Scan: 0
4323 14:44:04.732832
4324 14:44:04.733173 RX Vref 0 -> 0, step: 1
4325 14:44:04.733489
4326 14:44:04.735453 RX Delay -230 -> 252, step: 16
4327 14:44:04.738846 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4328 14:44:04.745644 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4329 14:44:04.748706 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4330 14:44:04.751604 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4331 14:44:04.754957 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4332 14:44:04.761784 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4333 14:44:04.764954 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4334 14:44:04.768840 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4335 14:44:04.771517 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4336 14:44:04.778049 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4337 14:44:04.781342 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4338 14:44:04.784647 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4339 14:44:04.788433 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4340 14:44:04.794407 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4341 14:44:04.798130 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4342 14:44:04.801356 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4343 14:44:04.801799 ==
4344 14:44:04.804435 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 14:44:04.808158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 14:44:04.808582 ==
4347 14:44:04.811413 DQS Delay:
4348 14:44:04.811860 DQS0 = 0, DQS1 = 0
4349 14:44:04.814520 DQM Delay:
4350 14:44:04.814940 DQM0 = 45, DQM1 = 38
4351 14:44:04.815277 DQ Delay:
4352 14:44:04.817908 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4353 14:44:04.820830 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4354 14:44:04.824304 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =41
4355 14:44:04.827716 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4356 14:44:04.828149
4357 14:44:04.831008
4358 14:44:04.831429 ==
4359 14:44:04.834113 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 14:44:04.837348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 14:44:04.837830 ==
4362 14:44:04.838232
4363 14:44:04.838572
4364 14:44:04.840852 TX Vref Scan disable
4365 14:44:04.841274 == TX Byte 0 ==
4366 14:44:04.847325 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4367 14:44:04.850653 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4368 14:44:04.851075 == TX Byte 1 ==
4369 14:44:04.857079 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4370 14:44:04.860421 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4371 14:44:04.860846 ==
4372 14:44:04.863869 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 14:44:04.867799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 14:44:04.868101 ==
4375 14:44:04.868344
4376 14:44:04.868567
4377 14:44:04.870571 TX Vref Scan disable
4378 14:44:04.873974 == TX Byte 0 ==
4379 14:44:04.877010 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4380 14:44:04.883598 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4381 14:44:04.883901 == TX Byte 1 ==
4382 14:44:04.886746 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4383 14:44:04.893579 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4384 14:44:04.893982
4385 14:44:04.894262 [DATLAT]
4386 14:44:04.894491 Freq=600, CH0 RK1
4387 14:44:04.894714
4388 14:44:04.896759 DATLAT Default: 0x9
4389 14:44:04.897059 0, 0xFFFF, sum = 0
4390 14:44:04.900027 1, 0xFFFF, sum = 0
4391 14:44:04.903341 2, 0xFFFF, sum = 0
4392 14:44:04.903739 3, 0xFFFF, sum = 0
4393 14:44:04.906763 4, 0xFFFF, sum = 0
4394 14:44:04.907067 5, 0xFFFF, sum = 0
4395 14:44:04.909954 6, 0xFFFF, sum = 0
4396 14:44:04.910276 7, 0xFFFF, sum = 0
4397 14:44:04.913909 8, 0x0, sum = 1
4398 14:44:04.914246 9, 0x0, sum = 2
4399 14:44:04.914528 10, 0x0, sum = 3
4400 14:44:04.916349 11, 0x0, sum = 4
4401 14:44:04.916793 best_step = 9
4402 14:44:04.917136
4403 14:44:04.920058 ==
4404 14:44:04.920430 Dram Type= 6, Freq= 0, CH_0, rank 1
4405 14:44:04.926834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 14:44:04.927135 ==
4407 14:44:04.927373 RX Vref Scan: 0
4408 14:44:04.927597
4409 14:44:04.930057 RX Vref 0 -> 0, step: 1
4410 14:44:04.930400
4411 14:44:04.933147 RX Delay -195 -> 252, step: 8
4412 14:44:04.936499 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4413 14:44:04.943048 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4414 14:44:04.946592 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4415 14:44:04.949722 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4416 14:44:04.953020 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4417 14:44:04.959707 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4418 14:44:04.963315 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4419 14:44:04.966136 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4420 14:44:04.969760 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4421 14:44:04.976209 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4422 14:44:04.979498 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4423 14:44:04.982779 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4424 14:44:04.986022 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4425 14:44:04.992789 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4426 14:44:04.995748 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4427 14:44:04.999326 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4428 14:44:04.999743 ==
4429 14:44:05.002893 Dram Type= 6, Freq= 0, CH_0, rank 1
4430 14:44:05.005829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 14:44:05.006290 ==
4432 14:44:05.008999 DQS Delay:
4433 14:44:05.009532 DQS0 = 0, DQS1 = 0
4434 14:44:05.012278 DQM Delay:
4435 14:44:05.012885 DQM0 = 42, DQM1 = 36
4436 14:44:05.013409 DQ Delay:
4437 14:44:05.015874 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4438 14:44:05.019340 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4439 14:44:05.022865 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4440 14:44:05.026119 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =44
4441 14:44:05.026654
4442 14:44:05.026994
4443 14:44:05.035530 [DQSOSCAuto] RK1, (LSB)MR18= 0x6014, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4444 14:44:05.038785 CH0 RK1: MR19=808, MR18=6014
4445 14:44:05.045509 CH0_RK1: MR19=0x808, MR18=0x6014, DQSOSC=391, MR23=63, INC=171, DEC=114
4446 14:44:05.049083 [RxdqsGatingPostProcess] freq 600
4447 14:44:05.052534 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4448 14:44:05.055739 Pre-setting of DQS Precalculation
4449 14:44:05.062364 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4450 14:44:05.062832 ==
4451 14:44:05.065139 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 14:44:05.068620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 14:44:05.069048 ==
4454 14:44:05.075207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 14:44:05.078222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4456 14:44:05.082566 [CA 0] Center 35 (5~66) winsize 62
4457 14:44:05.086307 [CA 1] Center 35 (5~66) winsize 62
4458 14:44:05.088998 [CA 2] Center 34 (4~65) winsize 62
4459 14:44:05.092735 [CA 3] Center 33 (3~64) winsize 62
4460 14:44:05.096120 [CA 4] Center 34 (4~65) winsize 62
4461 14:44:05.099204 [CA 5] Center 33 (3~64) winsize 62
4462 14:44:05.099628
4463 14:44:05.102426 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4464 14:44:05.102849
4465 14:44:05.105710 [CATrainingPosCal] consider 1 rank data
4466 14:44:05.109003 u2DelayCellTimex100 = 270/100 ps
4467 14:44:05.112338 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 14:44:05.118751 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4469 14:44:05.122199 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 14:44:05.125315 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 14:44:05.128807 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4472 14:44:05.132103 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 14:44:05.132674
4474 14:44:05.135088 CA PerBit enable=1, Macro0, CA PI delay=33
4475 14:44:05.135515
4476 14:44:05.138683 [CBTSetCACLKResult] CA Dly = 33
4477 14:44:05.142470 CS Dly: 5 (0~36)
4478 14:44:05.142893 ==
4479 14:44:05.145774 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 14:44:05.148412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 14:44:05.148838 ==
4482 14:44:05.155397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4483 14:44:05.158083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4484 14:44:05.162652 [CA 0] Center 35 (5~66) winsize 62
4485 14:44:05.165805 [CA 1] Center 36 (6~66) winsize 61
4486 14:44:05.169264 [CA 2] Center 34 (3~65) winsize 63
4487 14:44:05.172777 [CA 3] Center 34 (3~65) winsize 63
4488 14:44:05.175899 [CA 4] Center 34 (4~65) winsize 62
4489 14:44:05.179659 [CA 5] Center 34 (4~65) winsize 62
4490 14:44:05.180081
4491 14:44:05.182482 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4492 14:44:05.182923
4493 14:44:05.186020 [CATrainingPosCal] consider 2 rank data
4494 14:44:05.189474 u2DelayCellTimex100 = 270/100 ps
4495 14:44:05.192517 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4496 14:44:05.199384 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4497 14:44:05.202371 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4498 14:44:05.205639 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4499 14:44:05.208864 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4500 14:44:05.212313 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4501 14:44:05.212741
4502 14:44:05.215850 CA PerBit enable=1, Macro0, CA PI delay=33
4503 14:44:05.216275
4504 14:44:05.219378 [CBTSetCACLKResult] CA Dly = 33
4505 14:44:05.219801 CS Dly: 5 (0~37)
4506 14:44:05.222397
4507 14:44:05.225773 ----->DramcWriteLeveling(PI) begin...
4508 14:44:05.226261 ==
4509 14:44:05.228921 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 14:44:05.232222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 14:44:05.232726 ==
4512 14:44:05.235622 Write leveling (Byte 0): 29 => 29
4513 14:44:05.239071 Write leveling (Byte 1): 29 => 29
4514 14:44:05.242301 DramcWriteLeveling(PI) end<-----
4515 14:44:05.242781
4516 14:44:05.243120 ==
4517 14:44:05.245304 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 14:44:05.248939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 14:44:05.249370 ==
4520 14:44:05.252311 [Gating] SW mode calibration
4521 14:44:05.258561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4522 14:44:05.265643 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4523 14:44:05.268701 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 14:44:05.271735 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4525 14:44:05.278646 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4526 14:44:05.281722 0 9 12 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (1 0)
4527 14:44:05.284979 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4528 14:44:05.291438 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 14:44:05.294812 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 14:44:05.298338 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 14:44:05.304932 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 14:44:05.308423 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 14:44:05.311322 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4534 14:44:05.318192 0 10 12 | B1->B0 | 2e2e 3838 | 0 1 | (0 0) (0 0)
4535 14:44:05.321508 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4536 14:44:05.324238 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 14:44:05.331086 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 14:44:05.334283 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 14:44:05.337765 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 14:44:05.344276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 14:44:05.347352 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 14:44:05.350975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4543 14:44:05.357660 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4544 14:44:05.361001 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 14:44:05.364139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 14:44:05.370761 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 14:44:05.374255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 14:44:05.377327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 14:44:05.383650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 14:44:05.386931 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 14:44:05.390403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 14:44:05.397386 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 14:44:05.400361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 14:44:05.403457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 14:44:05.410566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 14:44:05.413416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 14:44:05.416526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 14:44:05.423413 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4559 14:44:05.426357 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4560 14:44:05.429790 Total UI for P1: 0, mck2ui 16
4561 14:44:05.432911 best dqsien dly found for B0: ( 0, 13, 12)
4562 14:44:05.436504 Total UI for P1: 0, mck2ui 16
4563 14:44:05.439501 best dqsien dly found for B1: ( 0, 13, 14)
4564 14:44:05.442872 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4565 14:44:05.446456 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4566 14:44:05.446592
4567 14:44:05.449154 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4568 14:44:05.452749 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4569 14:44:05.455749 [Gating] SW calibration Done
4570 14:44:05.455863 ==
4571 14:44:05.459063 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 14:44:05.465756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 14:44:05.465871 ==
4574 14:44:05.465941 RX Vref Scan: 0
4575 14:44:05.466004
4576 14:44:05.468924 RX Vref 0 -> 0, step: 1
4577 14:44:05.469011
4578 14:44:05.472350 RX Delay -230 -> 252, step: 16
4579 14:44:05.475752 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4580 14:44:05.478761 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4581 14:44:05.482442 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4582 14:44:05.488939 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4583 14:44:05.492560 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4584 14:44:05.495489 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4585 14:44:05.498626 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4586 14:44:05.505216 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4587 14:44:05.508843 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4588 14:44:05.512320 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4589 14:44:05.515250 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4590 14:44:05.521857 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4591 14:44:05.525143 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4592 14:44:05.528769 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4593 14:44:05.531555 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4594 14:44:05.538419 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4595 14:44:05.538511 ==
4596 14:44:05.541449 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 14:44:05.544995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 14:44:05.545083 ==
4599 14:44:05.545150 DQS Delay:
4600 14:44:05.547944 DQS0 = 0, DQS1 = 0
4601 14:44:05.548028 DQM Delay:
4602 14:44:05.552001 DQM0 = 46, DQM1 = 38
4603 14:44:05.552088 DQ Delay:
4604 14:44:05.554734 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4605 14:44:05.557788 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4606 14:44:05.561566 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4607 14:44:05.564403 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4608 14:44:05.564487
4609 14:44:05.564553
4610 14:44:05.564613 ==
4611 14:44:05.568261 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 14:44:05.571415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 14:44:05.574695 ==
4614 14:44:05.574799
4615 14:44:05.574892
4616 14:44:05.574981 TX Vref Scan disable
4617 14:44:05.577842 == TX Byte 0 ==
4618 14:44:05.581195 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4619 14:44:05.584236 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4620 14:44:05.587647 == TX Byte 1 ==
4621 14:44:05.590981 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4622 14:44:05.594409 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4623 14:44:05.597467 ==
4624 14:44:05.600703 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 14:44:05.604521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 14:44:05.604630 ==
4627 14:44:05.604722
4628 14:44:05.604811
4629 14:44:05.607731 TX Vref Scan disable
4630 14:44:05.610739 == TX Byte 0 ==
4631 14:44:05.614027 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4632 14:44:05.617576 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4633 14:44:05.620607 == TX Byte 1 ==
4634 14:44:05.623784 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4635 14:44:05.627011 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4636 14:44:05.627105
4637 14:44:05.627232 [DATLAT]
4638 14:44:05.630718 Freq=600, CH1 RK0
4639 14:44:05.630791
4640 14:44:05.634020 DATLAT Default: 0x9
4641 14:44:05.634117 0, 0xFFFF, sum = 0
4642 14:44:05.637214 1, 0xFFFF, sum = 0
4643 14:44:05.637315 2, 0xFFFF, sum = 0
4644 14:44:05.640337 3, 0xFFFF, sum = 0
4645 14:44:05.640438 4, 0xFFFF, sum = 0
4646 14:44:05.643825 5, 0xFFFF, sum = 0
4647 14:44:05.643923 6, 0xFFFF, sum = 0
4648 14:44:05.647462 7, 0xFFFF, sum = 0
4649 14:44:05.647565 8, 0x0, sum = 1
4650 14:44:05.650458 9, 0x0, sum = 2
4651 14:44:05.650547 10, 0x0, sum = 3
4652 14:44:05.653724 11, 0x0, sum = 4
4653 14:44:05.653810 best_step = 9
4654 14:44:05.653876
4655 14:44:05.653937 ==
4656 14:44:05.657082 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 14:44:05.660116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 14:44:05.660232 ==
4659 14:44:05.664197 RX Vref Scan: 1
4660 14:44:05.664311
4661 14:44:05.666586 RX Vref 0 -> 0, step: 1
4662 14:44:05.666669
4663 14:44:05.666762 RX Delay -179 -> 252, step: 8
4664 14:44:05.666828
4665 14:44:05.669982 Set Vref, RX VrefLevel [Byte0]: 51
4666 14:44:05.673555 [Byte1]: 55
4667 14:44:05.677928
4668 14:44:05.678009 Final RX Vref Byte 0 = 51 to rank0
4669 14:44:05.681084 Final RX Vref Byte 1 = 55 to rank0
4670 14:44:05.685094 Final RX Vref Byte 0 = 51 to rank1
4671 14:44:05.687936 Final RX Vref Byte 1 = 55 to rank1==
4672 14:44:05.691460 Dram Type= 6, Freq= 0, CH_1, rank 0
4673 14:44:05.697928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 14:44:05.698011 ==
4675 14:44:05.698105 DQS Delay:
4676 14:44:05.700930 DQS0 = 0, DQS1 = 0
4677 14:44:05.701012 DQM Delay:
4678 14:44:05.701077 DQM0 = 46, DQM1 = 37
4679 14:44:05.704575 DQ Delay:
4680 14:44:05.707928 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4681 14:44:05.711118 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4682 14:44:05.714469 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4683 14:44:05.717334 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4684 14:44:05.717406
4685 14:44:05.717469
4686 14:44:05.723609 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d32, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4687 14:44:05.727438 CH1 RK0: MR19=808, MR18=4D32
4688 14:44:05.733912 CH1_RK0: MR19=0x808, MR18=0x4D32, DQSOSC=395, MR23=63, INC=168, DEC=112
4689 14:44:05.733992
4690 14:44:05.737100 ----->DramcWriteLeveling(PI) begin...
4691 14:44:05.737182 ==
4692 14:44:05.740566 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 14:44:05.744064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 14:44:05.744146 ==
4695 14:44:05.747372 Write leveling (Byte 0): 29 => 29
4696 14:44:05.750287 Write leveling (Byte 1): 32 => 32
4697 14:44:05.753597 DramcWriteLeveling(PI) end<-----
4698 14:44:05.753678
4699 14:44:05.753741 ==
4700 14:44:05.756959 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 14:44:05.763482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 14:44:05.763564 ==
4703 14:44:05.763629 [Gating] SW mode calibration
4704 14:44:05.773490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4705 14:44:05.776910 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4706 14:44:05.780133 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 14:44:05.786888 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4708 14:44:05.790016 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4709 14:44:05.792989 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (1 1) (0 0)
4710 14:44:05.799756 0 9 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4711 14:44:05.803001 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 14:44:05.809604 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 14:44:05.812706 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 14:44:05.816311 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 14:44:05.823031 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 14:44:05.825746 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 14:44:05.828971 0 10 12 | B1->B0 | 2c2c 2e2e | 0 1 | (0 0) (0 0)
4718 14:44:05.836052 0 10 16 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
4719 14:44:05.839024 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 14:44:05.842447 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 14:44:05.849274 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 14:44:05.852182 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 14:44:05.855894 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 14:44:05.862490 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 14:44:05.865447 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4726 14:44:05.869037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 14:44:05.875413 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 14:44:05.878874 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 14:44:05.882129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 14:44:05.888788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 14:44:05.891736 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 14:44:05.894992 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 14:44:05.901919 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 14:44:05.905040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 14:44:05.908141 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 14:44:05.914883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 14:44:05.918058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 14:44:05.921401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 14:44:05.927898 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 14:44:05.931663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 14:44:05.934995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4742 14:44:05.938423 Total UI for P1: 0, mck2ui 16
4743 14:44:05.941404 best dqsien dly found for B1: ( 0, 13, 10)
4744 14:44:05.944791 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4745 14:44:05.947904 Total UI for P1: 0, mck2ui 16
4746 14:44:05.951421 best dqsien dly found for B0: ( 0, 13, 12)
4747 14:44:05.958000 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4748 14:44:05.961215 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4749 14:44:05.961296
4750 14:44:05.964233 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4751 14:44:05.967400 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4752 14:44:05.971272 [Gating] SW calibration Done
4753 14:44:05.971353 ==
4754 14:44:05.974469 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 14:44:05.977075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 14:44:05.977156 ==
4757 14:44:05.980610 RX Vref Scan: 0
4758 14:44:05.980690
4759 14:44:05.980754 RX Vref 0 -> 0, step: 1
4760 14:44:05.983807
4761 14:44:05.983887 RX Delay -230 -> 252, step: 16
4762 14:44:05.990118 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4763 14:44:05.994066 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4764 14:44:05.997165 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4765 14:44:06.000219 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4766 14:44:06.006661 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4767 14:44:06.010121 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4768 14:44:06.013374 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4769 14:44:06.016846 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4770 14:44:06.023404 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4771 14:44:06.026563 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4772 14:44:06.029695 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4773 14:44:06.033064 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4774 14:44:06.036552 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4775 14:44:06.043175 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4776 14:44:06.046290 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4777 14:44:06.049560 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4778 14:44:06.049634 ==
4779 14:44:06.052745 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 14:44:06.059282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 14:44:06.059359 ==
4782 14:44:06.059423 DQS Delay:
4783 14:44:06.062830 DQS0 = 0, DQS1 = 0
4784 14:44:06.062914 DQM Delay:
4785 14:44:06.062980 DQM0 = 45, DQM1 = 38
4786 14:44:06.065772 DQ Delay:
4787 14:44:06.069445 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4788 14:44:06.072673 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4789 14:44:06.075579 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4790 14:44:06.078903 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4791 14:44:06.078987
4792 14:44:06.079051
4793 14:44:06.079111 ==
4794 14:44:06.082758 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 14:44:06.086159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 14:44:06.086312 ==
4797 14:44:06.086395
4798 14:44:06.086458
4799 14:44:06.088995 TX Vref Scan disable
4800 14:44:06.092596 == TX Byte 0 ==
4801 14:44:06.095810 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4802 14:44:06.098780 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4803 14:44:06.102505 == TX Byte 1 ==
4804 14:44:06.105590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4805 14:44:06.108820 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4806 14:44:06.108894 ==
4807 14:44:06.112159 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 14:44:06.115843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 14:44:06.118568 ==
4810 14:44:06.118642
4811 14:44:06.118704
4812 14:44:06.118763 TX Vref Scan disable
4813 14:44:06.122635 == TX Byte 0 ==
4814 14:44:06.125900 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4815 14:44:06.132611 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4816 14:44:06.132698 == TX Byte 1 ==
4817 14:44:06.135836 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4818 14:44:06.142235 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4819 14:44:06.142317
4820 14:44:06.142381 [DATLAT]
4821 14:44:06.142518 Freq=600, CH1 RK1
4822 14:44:06.142655
4823 14:44:06.145916 DATLAT Default: 0x9
4824 14:44:06.149409 0, 0xFFFF, sum = 0
4825 14:44:06.149512 1, 0xFFFF, sum = 0
4826 14:44:06.152061 2, 0xFFFF, sum = 0
4827 14:44:06.152150 3, 0xFFFF, sum = 0
4828 14:44:06.155481 4, 0xFFFF, sum = 0
4829 14:44:06.155564 5, 0xFFFF, sum = 0
4830 14:44:06.158576 6, 0xFFFF, sum = 0
4831 14:44:06.158662 7, 0xFFFF, sum = 0
4832 14:44:06.162061 8, 0x0, sum = 1
4833 14:44:06.162144 9, 0x0, sum = 2
4834 14:44:06.165298 10, 0x0, sum = 3
4835 14:44:06.165381 11, 0x0, sum = 4
4836 14:44:06.165447 best_step = 9
4837 14:44:06.165506
4838 14:44:06.168780 ==
4839 14:44:06.171881 Dram Type= 6, Freq= 0, CH_1, rank 1
4840 14:44:06.175116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4841 14:44:06.175194 ==
4842 14:44:06.175257 RX Vref Scan: 0
4843 14:44:06.175336
4844 14:44:06.178433 RX Vref 0 -> 0, step: 1
4845 14:44:06.178514
4846 14:44:06.181777 RX Delay -195 -> 252, step: 8
4847 14:44:06.188533 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4848 14:44:06.191459 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4849 14:44:06.194657 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4850 14:44:06.198141 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4851 14:44:06.204796 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4852 14:44:06.207880 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4853 14:44:06.211183 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4854 14:44:06.214405 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4855 14:44:06.218088 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4856 14:44:06.224727 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4857 14:44:06.227932 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4858 14:44:06.231362 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4859 14:44:06.234574 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4860 14:44:06.240794 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4861 14:44:06.244729 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4862 14:44:06.247829 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4863 14:44:06.247910 ==
4864 14:44:06.250990 Dram Type= 6, Freq= 0, CH_1, rank 1
4865 14:44:06.254575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4866 14:44:06.257565 ==
4867 14:44:06.257646 DQS Delay:
4868 14:44:06.257710 DQS0 = 0, DQS1 = 0
4869 14:44:06.260735 DQM Delay:
4870 14:44:06.260816 DQM0 = 45, DQM1 = 37
4871 14:44:06.264523 DQ Delay:
4872 14:44:06.267128 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4873 14:44:06.270429 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4874 14:44:06.273665 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4875 14:44:06.277012 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4876 14:44:06.277094
4877 14:44:06.277158
4878 14:44:06.283706 [DQSOSCAuto] RK1, (LSB)MR18= 0x291f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4879 14:44:06.287108 CH1 RK1: MR19=808, MR18=291F
4880 14:44:06.293589 CH1_RK1: MR19=0x808, MR18=0x291F, DQSOSC=402, MR23=63, INC=162, DEC=108
4881 14:44:06.296842 [RxdqsGatingPostProcess] freq 600
4882 14:44:06.300060 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4883 14:44:06.303646 Pre-setting of DQS Precalculation
4884 14:44:06.310418 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4885 14:44:06.316858 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4886 14:44:06.323731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4887 14:44:06.323813
4888 14:44:06.323878
4889 14:44:06.327018 [Calibration Summary] 1200 Mbps
4890 14:44:06.327102 CH 0, Rank 0
4891 14:44:06.330013 SW Impedance : PASS
4892 14:44:06.333670 DUTY Scan : NO K
4893 14:44:06.333752 ZQ Calibration : PASS
4894 14:44:06.336893 Jitter Meter : NO K
4895 14:44:06.340495 CBT Training : PASS
4896 14:44:06.340577 Write leveling : PASS
4897 14:44:06.343368 RX DQS gating : PASS
4898 14:44:06.347399 RX DQ/DQS(RDDQC) : PASS
4899 14:44:06.347480 TX DQ/DQS : PASS
4900 14:44:06.350064 RX DATLAT : PASS
4901 14:44:06.353275 RX DQ/DQS(Engine): PASS
4902 14:44:06.353355 TX OE : NO K
4903 14:44:06.357123 All Pass.
4904 14:44:06.357203
4905 14:44:06.357267 CH 0, Rank 1
4906 14:44:06.360009 SW Impedance : PASS
4907 14:44:06.360134 DUTY Scan : NO K
4908 14:44:06.363181 ZQ Calibration : PASS
4909 14:44:06.366651 Jitter Meter : NO K
4910 14:44:06.366732 CBT Training : PASS
4911 14:44:06.369965 Write leveling : PASS
4912 14:44:06.370075 RX DQS gating : PASS
4913 14:44:06.372863 RX DQ/DQS(RDDQC) : PASS
4914 14:44:06.376243 TX DQ/DQS : PASS
4915 14:44:06.376325 RX DATLAT : PASS
4916 14:44:06.379515 RX DQ/DQS(Engine): PASS
4917 14:44:06.383530 TX OE : NO K
4918 14:44:06.383629 All Pass.
4919 14:44:06.383698
4920 14:44:06.383758 CH 1, Rank 0
4921 14:44:06.386311 SW Impedance : PASS
4922 14:44:06.389334 DUTY Scan : NO K
4923 14:44:06.389440 ZQ Calibration : PASS
4924 14:44:06.392717 Jitter Meter : NO K
4925 14:44:06.396057 CBT Training : PASS
4926 14:44:06.396138 Write leveling : PASS
4927 14:44:06.399294 RX DQS gating : PASS
4928 14:44:06.402435 RX DQ/DQS(RDDQC) : PASS
4929 14:44:06.402516 TX DQ/DQS : PASS
4930 14:44:06.406123 RX DATLAT : PASS
4931 14:44:06.409135 RX DQ/DQS(Engine): PASS
4932 14:44:06.409215 TX OE : NO K
4933 14:44:06.412916 All Pass.
4934 14:44:06.412998
4935 14:44:06.413062 CH 1, Rank 1
4936 14:44:06.415994 SW Impedance : PASS
4937 14:44:06.416075 DUTY Scan : NO K
4938 14:44:06.419273 ZQ Calibration : PASS
4939 14:44:06.422443 Jitter Meter : NO K
4940 14:44:06.422524 CBT Training : PASS
4941 14:44:06.425967 Write leveling : PASS
4942 14:44:06.428915 RX DQS gating : PASS
4943 14:44:06.428996 RX DQ/DQS(RDDQC) : PASS
4944 14:44:06.432685 TX DQ/DQS : PASS
4945 14:44:06.435653 RX DATLAT : PASS
4946 14:44:06.435734 RX DQ/DQS(Engine): PASS
4947 14:44:06.439184 TX OE : NO K
4948 14:44:06.439266 All Pass.
4949 14:44:06.439330
4950 14:44:06.442279 DramC Write-DBI off
4951 14:44:06.445665 PER_BANK_REFRESH: Hybrid Mode
4952 14:44:06.445747 TX_TRACKING: ON
4953 14:44:06.455630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4954 14:44:06.458814 [FAST_K] Save calibration result to emmc
4955 14:44:06.462318 dramc_set_vcore_voltage set vcore to 662500
4956 14:44:06.465431 Read voltage for 933, 3
4957 14:44:06.465537 Vio18 = 0
4958 14:44:06.465635 Vcore = 662500
4959 14:44:06.468653 Vdram = 0
4960 14:44:06.468733 Vddq = 0
4961 14:44:06.468797 Vmddr = 0
4962 14:44:06.475283 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4963 14:44:06.478297 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4964 14:44:06.481944 MEM_TYPE=3, freq_sel=17
4965 14:44:06.485238 sv_algorithm_assistance_LP4_1600
4966 14:44:06.488427 ============ PULL DRAM RESETB DOWN ============
4967 14:44:06.491801 ========== PULL DRAM RESETB DOWN end =========
4968 14:44:06.498390 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 14:44:06.501632 ===================================
4970 14:44:06.501740 LPDDR4 DRAM CONFIGURATION
4971 14:44:06.504674 ===================================
4972 14:44:06.508079 EX_ROW_EN[0] = 0x0
4973 14:44:06.511354 EX_ROW_EN[1] = 0x0
4974 14:44:06.511435 LP4Y_EN = 0x0
4975 14:44:06.514726 WORK_FSP = 0x0
4976 14:44:06.514807 WL = 0x3
4977 14:44:06.518016 RL = 0x3
4978 14:44:06.518123 BL = 0x2
4979 14:44:06.521316 RPST = 0x0
4980 14:44:06.521397 RD_PRE = 0x0
4981 14:44:06.524621 WR_PRE = 0x1
4982 14:44:06.524702 WR_PST = 0x0
4983 14:44:06.527729 DBI_WR = 0x0
4984 14:44:06.527812 DBI_RD = 0x0
4985 14:44:06.531344 OTF = 0x1
4986 14:44:06.534574 ===================================
4987 14:44:06.537912 ===================================
4988 14:44:06.538008 ANA top config
4989 14:44:06.541366 ===================================
4990 14:44:06.544284 DLL_ASYNC_EN = 0
4991 14:44:06.548177 ALL_SLAVE_EN = 1
4992 14:44:06.551111 NEW_RANK_MODE = 1
4993 14:44:06.554581 DLL_IDLE_MODE = 1
4994 14:44:06.554688 LP45_APHY_COMB_EN = 1
4995 14:44:06.557663 TX_ODT_DIS = 1
4996 14:44:06.560972 NEW_8X_MODE = 1
4997 14:44:06.564601 ===================================
4998 14:44:06.567361 ===================================
4999 14:44:06.570691 data_rate = 1866
5000 14:44:06.573968 CKR = 1
5001 14:44:06.574057 DQ_P2S_RATIO = 8
5002 14:44:06.577592 ===================================
5003 14:44:06.580954 CA_P2S_RATIO = 8
5004 14:44:06.584414 DQ_CA_OPEN = 0
5005 14:44:06.587107 DQ_SEMI_OPEN = 0
5006 14:44:06.590649 CA_SEMI_OPEN = 0
5007 14:44:06.593866 CA_FULL_RATE = 0
5008 14:44:06.593967 DQ_CKDIV4_EN = 1
5009 14:44:06.597535 CA_CKDIV4_EN = 1
5010 14:44:06.600676 CA_PREDIV_EN = 0
5011 14:44:06.604328 PH8_DLY = 0
5012 14:44:06.607148 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5013 14:44:06.610055 DQ_AAMCK_DIV = 4
5014 14:44:06.610165 CA_AAMCK_DIV = 4
5015 14:44:06.613735 CA_ADMCK_DIV = 4
5016 14:44:06.616838 DQ_TRACK_CA_EN = 0
5017 14:44:06.620120 CA_PICK = 933
5018 14:44:06.623517 CA_MCKIO = 933
5019 14:44:06.627168 MCKIO_SEMI = 0
5020 14:44:06.630435 PLL_FREQ = 3732
5021 14:44:06.633099 DQ_UI_PI_RATIO = 32
5022 14:44:06.633170 CA_UI_PI_RATIO = 0
5023 14:44:06.636692 ===================================
5024 14:44:06.639904 ===================================
5025 14:44:06.643117 memory_type:LPDDR4
5026 14:44:06.646599 GP_NUM : 10
5027 14:44:06.646672 SRAM_EN : 1
5028 14:44:06.649994 MD32_EN : 0
5029 14:44:06.653010 ===================================
5030 14:44:06.656488 [ANA_INIT] >>>>>>>>>>>>>>
5031 14:44:06.659402 <<<<<< [CONFIGURE PHASE]: ANA_TX
5032 14:44:06.662838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5033 14:44:06.665992 ===================================
5034 14:44:06.666095 data_rate = 1866,PCW = 0X8f00
5035 14:44:06.669848 ===================================
5036 14:44:06.673268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5037 14:44:06.679569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5038 14:44:06.686416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5039 14:44:06.689856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5040 14:44:06.692526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5041 14:44:06.696214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5042 14:44:06.699022 [ANA_INIT] flow start
5043 14:44:06.702922 [ANA_INIT] PLL >>>>>>>>
5044 14:44:06.703002 [ANA_INIT] PLL <<<<<<<<
5045 14:44:06.706009 [ANA_INIT] MIDPI >>>>>>>>
5046 14:44:06.708974 [ANA_INIT] MIDPI <<<<<<<<
5047 14:44:06.709049 [ANA_INIT] DLL >>>>>>>>
5048 14:44:06.712362 [ANA_INIT] flow end
5049 14:44:06.715730 ============ LP4 DIFF to SE enter ============
5050 14:44:06.722652 ============ LP4 DIFF to SE exit ============
5051 14:44:06.722731 [ANA_INIT] <<<<<<<<<<<<<
5052 14:44:06.725536 [Flow] Enable top DCM control >>>>>
5053 14:44:06.728779 [Flow] Enable top DCM control <<<<<
5054 14:44:06.732327 Enable DLL master slave shuffle
5055 14:44:06.738528 ==============================================================
5056 14:44:06.738617 Gating Mode config
5057 14:44:06.745827 ==============================================================
5058 14:44:06.748655 Config description:
5059 14:44:06.755066 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5060 14:44:06.761958 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5061 14:44:06.768955 SELPH_MODE 0: By rank 1: By Phase
5062 14:44:06.774998 ==============================================================
5063 14:44:06.778278 GAT_TRACK_EN = 1
5064 14:44:06.778353 RX_GATING_MODE = 2
5065 14:44:06.781564 RX_GATING_TRACK_MODE = 2
5066 14:44:06.784999 SELPH_MODE = 1
5067 14:44:06.788818 PICG_EARLY_EN = 1
5068 14:44:06.791713 VALID_LAT_VALUE = 1
5069 14:44:06.798278 ==============================================================
5070 14:44:06.801414 Enter into Gating configuration >>>>
5071 14:44:06.804434 Exit from Gating configuration <<<<
5072 14:44:06.807989 Enter into DVFS_PRE_config >>>>>
5073 14:44:06.817825 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5074 14:44:06.821160 Exit from DVFS_PRE_config <<<<<
5075 14:44:06.824540 Enter into PICG configuration >>>>
5076 14:44:06.827832 Exit from PICG configuration <<<<
5077 14:44:06.831548 [RX_INPUT] configuration >>>>>
5078 14:44:06.834462 [RX_INPUT] configuration <<<<<
5079 14:44:06.837919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5080 14:44:06.844573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5081 14:44:06.850788 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 14:44:06.857750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 14:44:06.861121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5084 14:44:06.867769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5085 14:44:06.874628 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5086 14:44:06.877257 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5087 14:44:06.881042 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5088 14:44:06.883849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5089 14:44:06.890641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5090 14:44:06.894032 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5091 14:44:06.896988 ===================================
5092 14:44:06.900873 LPDDR4 DRAM CONFIGURATION
5093 14:44:06.903695 ===================================
5094 14:44:06.903777 EX_ROW_EN[0] = 0x0
5095 14:44:06.907108 EX_ROW_EN[1] = 0x0
5096 14:44:06.907189 LP4Y_EN = 0x0
5097 14:44:06.910389 WORK_FSP = 0x0
5098 14:44:06.910471 WL = 0x3
5099 14:44:06.913686 RL = 0x3
5100 14:44:06.913767 BL = 0x2
5101 14:44:06.917237 RPST = 0x0
5102 14:44:06.917318 RD_PRE = 0x0
5103 14:44:06.920257 WR_PRE = 0x1
5104 14:44:06.923720 WR_PST = 0x0
5105 14:44:06.923815 DBI_WR = 0x0
5106 14:44:06.927023 DBI_RD = 0x0
5107 14:44:06.927104 OTF = 0x1
5108 14:44:06.930096 ===================================
5109 14:44:06.933310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5110 14:44:06.939692 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5111 14:44:06.943156 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5112 14:44:06.946366 ===================================
5113 14:44:06.950085 LPDDR4 DRAM CONFIGURATION
5114 14:44:06.952946 ===================================
5115 14:44:06.953028 EX_ROW_EN[0] = 0x10
5116 14:44:06.956390 EX_ROW_EN[1] = 0x0
5117 14:44:06.956471 LP4Y_EN = 0x0
5118 14:44:06.959629 WORK_FSP = 0x0
5119 14:44:06.959710 WL = 0x3
5120 14:44:06.962844 RL = 0x3
5121 14:44:06.966297 BL = 0x2
5122 14:44:06.966379 RPST = 0x0
5123 14:44:06.969470 RD_PRE = 0x0
5124 14:44:06.969551 WR_PRE = 0x1
5125 14:44:06.973040 WR_PST = 0x0
5126 14:44:06.973124 DBI_WR = 0x0
5127 14:44:06.975955 DBI_RD = 0x0
5128 14:44:06.976037 OTF = 0x1
5129 14:44:06.979298 ===================================
5130 14:44:06.985808 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5131 14:44:06.989904 nWR fixed to 30
5132 14:44:06.993640 [ModeRegInit_LP4] CH0 RK0
5133 14:44:06.993722 [ModeRegInit_LP4] CH0 RK1
5134 14:44:06.996981 [ModeRegInit_LP4] CH1 RK0
5135 14:44:06.999867 [ModeRegInit_LP4] CH1 RK1
5136 14:44:06.999948 match AC timing 9
5137 14:44:07.006530 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5138 14:44:07.009768 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5139 14:44:07.012943 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5140 14:44:07.019474 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5141 14:44:07.023051 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5142 14:44:07.023132 ==
5143 14:44:07.025994 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 14:44:07.029566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 14:44:07.029649 ==
5146 14:44:07.035857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 14:44:07.042515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5148 14:44:07.046051 [CA 0] Center 37 (7~68) winsize 62
5149 14:44:07.048760 [CA 1] Center 37 (7~68) winsize 62
5150 14:44:07.052132 [CA 2] Center 34 (4~65) winsize 62
5151 14:44:07.055609 [CA 3] Center 34 (4~65) winsize 62
5152 14:44:07.058809 [CA 4] Center 33 (3~64) winsize 62
5153 14:44:07.062097 [CA 5] Center 33 (3~63) winsize 61
5154 14:44:07.062221
5155 14:44:07.065237 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5156 14:44:07.065319
5157 14:44:07.069305 [CATrainingPosCal] consider 1 rank data
5158 14:44:07.072481 u2DelayCellTimex100 = 270/100 ps
5159 14:44:07.075360 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5160 14:44:07.078902 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 14:44:07.081673 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5162 14:44:07.088634 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5163 14:44:07.091866 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 14:44:07.095309 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5165 14:44:07.095392
5166 14:44:07.098579 CA PerBit enable=1, Macro0, CA PI delay=33
5167 14:44:07.098664
5168 14:44:07.101994 [CBTSetCACLKResult] CA Dly = 33
5169 14:44:07.102076 CS Dly: 7 (0~38)
5170 14:44:07.102140 ==
5171 14:44:07.105630 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 14:44:07.111525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 14:44:07.111607 ==
5174 14:44:07.114983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5175 14:44:07.121748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5176 14:44:07.125396 [CA 0] Center 37 (7~68) winsize 62
5177 14:44:07.127983 [CA 1] Center 37 (7~68) winsize 62
5178 14:44:07.131221 [CA 2] Center 34 (4~65) winsize 62
5179 14:44:07.134816 [CA 3] Center 35 (5~65) winsize 61
5180 14:44:07.137969 [CA 4] Center 33 (3~64) winsize 62
5181 14:44:07.141511 [CA 5] Center 33 (3~63) winsize 61
5182 14:44:07.141592
5183 14:44:07.145105 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5184 14:44:07.145187
5185 14:44:07.148551 [CATrainingPosCal] consider 2 rank data
5186 14:44:07.151685 u2DelayCellTimex100 = 270/100 ps
5187 14:44:07.154994 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5188 14:44:07.160938 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5189 14:44:07.164671 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5190 14:44:07.167572 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5191 14:44:07.170979 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5192 14:44:07.174515 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5193 14:44:07.174592
5194 14:44:07.177307 CA PerBit enable=1, Macro0, CA PI delay=33
5195 14:44:07.177412
5196 14:44:07.181244 [CBTSetCACLKResult] CA Dly = 33
5197 14:44:07.184068 CS Dly: 7 (0~39)
5198 14:44:07.184168
5199 14:44:07.187320 ----->DramcWriteLeveling(PI) begin...
5200 14:44:07.187421 ==
5201 14:44:07.191294 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 14:44:07.193919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 14:44:07.194019 ==
5204 14:44:07.197300 Write leveling (Byte 0): 33 => 33
5205 14:44:07.200619 Write leveling (Byte 1): 28 => 28
5206 14:44:07.204151 DramcWriteLeveling(PI) end<-----
5207 14:44:07.204227
5208 14:44:07.204290 ==
5209 14:44:07.207266 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 14:44:07.210602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 14:44:07.210702 ==
5212 14:44:07.213615 [Gating] SW mode calibration
5213 14:44:07.220086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5214 14:44:07.226797 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5215 14:44:07.230129 0 14 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
5216 14:44:07.236714 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5217 14:44:07.240143 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 14:44:07.243587 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 14:44:07.249737 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 14:44:07.253098 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 14:44:07.256749 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5222 14:44:07.262913 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5223 14:44:07.266492 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5224 14:44:07.269800 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5225 14:44:07.276483 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 14:44:07.279322 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 14:44:07.283083 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 14:44:07.289720 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 14:44:07.293059 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 14:44:07.296141 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5231 14:44:07.302534 1 0 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5232 14:44:07.306137 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 14:44:07.309131 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 14:44:07.316076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 14:44:07.319420 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 14:44:07.322591 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 14:44:07.329064 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 14:44:07.332444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5239 14:44:07.335814 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5240 14:44:07.342548 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 14:44:07.346008 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 14:44:07.348769 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 14:44:07.355593 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 14:44:07.358868 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 14:44:07.361911 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 14:44:07.368899 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 14:44:07.371994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 14:44:07.375408 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 14:44:07.381794 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 14:44:07.384953 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 14:44:07.388246 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 14:44:07.394803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 14:44:07.398139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 14:44:07.401841 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5255 14:44:07.407908 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5256 14:44:07.407992 Total UI for P1: 0, mck2ui 16
5257 14:44:07.414543 best dqsien dly found for B0: ( 1, 2, 28)
5258 14:44:07.417951 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5259 14:44:07.421250 Total UI for P1: 0, mck2ui 16
5260 14:44:07.424799 best dqsien dly found for B1: ( 1, 2, 30)
5261 14:44:07.428098 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5262 14:44:07.431681 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5263 14:44:07.431762
5264 14:44:07.434331 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5265 14:44:07.437773 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5266 14:44:07.441601 [Gating] SW calibration Done
5267 14:44:07.441684 ==
5268 14:44:07.444390 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 14:44:07.447997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 14:44:07.450833 ==
5271 14:44:07.450942 RX Vref Scan: 0
5272 14:44:07.451034
5273 14:44:07.454415 RX Vref 0 -> 0, step: 1
5274 14:44:07.454496
5275 14:44:07.457912 RX Delay -80 -> 252, step: 8
5276 14:44:07.460683 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5277 14:44:07.464081 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5278 14:44:07.467481 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5279 14:44:07.471018 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5280 14:44:07.473955 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5281 14:44:07.480383 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5282 14:44:07.484143 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5283 14:44:07.487392 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5284 14:44:07.490704 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5285 14:44:07.493747 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5286 14:44:07.500400 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5287 14:44:07.503663 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5288 14:44:07.506610 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5289 14:44:07.509875 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5290 14:44:07.513174 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5291 14:44:07.519851 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5292 14:44:07.519933 ==
5293 14:44:07.523437 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 14:44:07.526916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 14:44:07.526998 ==
5296 14:44:07.527063 DQS Delay:
5297 14:44:07.530477 DQS0 = 0, DQS1 = 0
5298 14:44:07.530558 DQM Delay:
5299 14:44:07.533566 DQM0 = 97, DQM1 = 85
5300 14:44:07.533647 DQ Delay:
5301 14:44:07.536635 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5302 14:44:07.539828 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5303 14:44:07.543067 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5304 14:44:07.546128 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5305 14:44:07.546273
5306 14:44:07.546367
5307 14:44:07.546473 ==
5308 14:44:07.549697 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 14:44:07.552945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 14:44:07.556172 ==
5311 14:44:07.556254
5312 14:44:07.556318
5313 14:44:07.556376 TX Vref Scan disable
5314 14:44:07.559391 == TX Byte 0 ==
5315 14:44:07.562905 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5316 14:44:07.565883 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5317 14:44:07.569554 == TX Byte 1 ==
5318 14:44:07.572766 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5319 14:44:07.579516 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5320 14:44:07.579598 ==
5321 14:44:07.582885 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 14:44:07.586025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 14:44:07.586107 ==
5324 14:44:07.586210
5325 14:44:07.586272
5326 14:44:07.588976 TX Vref Scan disable
5327 14:44:07.589057 == TX Byte 0 ==
5328 14:44:07.595738 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5329 14:44:07.599101 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5330 14:44:07.599183 == TX Byte 1 ==
5331 14:44:07.606281 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5332 14:44:07.609037 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5333 14:44:07.609119
5334 14:44:07.609183 [DATLAT]
5335 14:44:07.612424 Freq=933, CH0 RK0
5336 14:44:07.612506
5337 14:44:07.612570 DATLAT Default: 0xd
5338 14:44:07.615871 0, 0xFFFF, sum = 0
5339 14:44:07.615954 1, 0xFFFF, sum = 0
5340 14:44:07.619116 2, 0xFFFF, sum = 0
5341 14:44:07.622422 3, 0xFFFF, sum = 0
5342 14:44:07.622505 4, 0xFFFF, sum = 0
5343 14:44:07.625379 5, 0xFFFF, sum = 0
5344 14:44:07.625461 6, 0xFFFF, sum = 0
5345 14:44:07.628681 7, 0xFFFF, sum = 0
5346 14:44:07.628764 8, 0xFFFF, sum = 0
5347 14:44:07.632099 9, 0xFFFF, sum = 0
5348 14:44:07.632196 10, 0x0, sum = 1
5349 14:44:07.635541 11, 0x0, sum = 2
5350 14:44:07.635619 12, 0x0, sum = 3
5351 14:44:07.638854 13, 0x0, sum = 4
5352 14:44:07.638928 best_step = 11
5353 14:44:07.638991
5354 14:44:07.639050 ==
5355 14:44:07.641999 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 14:44:07.645270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 14:44:07.645344 ==
5358 14:44:07.648603 RX Vref Scan: 1
5359 14:44:07.648675
5360 14:44:07.651885 RX Vref 0 -> 0, step: 1
5361 14:44:07.651954
5362 14:44:07.652022 RX Delay -69 -> 252, step: 4
5363 14:44:07.652087
5364 14:44:07.655075 Set Vref, RX VrefLevel [Byte0]: 59
5365 14:44:07.658628 [Byte1]: 58
5366 14:44:07.663475
5367 14:44:07.663561 Final RX Vref Byte 0 = 59 to rank0
5368 14:44:07.666683 Final RX Vref Byte 1 = 58 to rank0
5369 14:44:07.670276 Final RX Vref Byte 0 = 59 to rank1
5370 14:44:07.673131 Final RX Vref Byte 1 = 58 to rank1==
5371 14:44:07.676704 Dram Type= 6, Freq= 0, CH_0, rank 0
5372 14:44:07.683068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 14:44:07.683195 ==
5374 14:44:07.683292 DQS Delay:
5375 14:44:07.686262 DQS0 = 0, DQS1 = 0
5376 14:44:07.686367 DQM Delay:
5377 14:44:07.686469 DQM0 = 96, DQM1 = 86
5378 14:44:07.689992 DQ Delay:
5379 14:44:07.692891 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5380 14:44:07.696409 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =106
5381 14:44:07.699545 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =84
5382 14:44:07.703142 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5383 14:44:07.703358
5384 14:44:07.703573
5385 14:44:07.709868 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5386 14:44:07.712705 CH0 RK0: MR19=505, MR18=2C13
5387 14:44:07.719524 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5388 14:44:07.719901
5389 14:44:07.723325 ----->DramcWriteLeveling(PI) begin...
5390 14:44:07.723747 ==
5391 14:44:07.726338 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 14:44:07.729190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 14:44:07.729604 ==
5394 14:44:07.732606 Write leveling (Byte 0): 32 => 32
5395 14:44:07.735764 Write leveling (Byte 1): 32 => 32
5396 14:44:07.739282 DramcWriteLeveling(PI) end<-----
5397 14:44:07.739694
5398 14:44:07.740015 ==
5399 14:44:07.742338 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 14:44:07.749247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 14:44:07.749661 ==
5402 14:44:07.749986 [Gating] SW mode calibration
5403 14:44:07.759048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5404 14:44:07.762032 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5405 14:44:07.769119 0 14 0 | B1->B0 | 2929 2e2e | 1 0 | (0 0) (0 0)
5406 14:44:07.772368 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 14:44:07.775588 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 14:44:07.782568 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 14:44:07.785396 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 14:44:07.788497 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 14:44:07.795074 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 14:44:07.798757 0 14 28 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (0 0)
5413 14:44:07.802045 0 15 0 | B1->B0 | 2c2c 2a2a | 1 1 | (1 0) (1 0)
5414 14:44:07.808509 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 14:44:07.811838 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 14:44:07.815216 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 14:44:07.821583 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 14:44:07.825027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 14:44:07.828264 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 14:44:07.835050 0 15 28 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5421 14:44:07.838054 1 0 0 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
5422 14:44:07.841213 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 14:44:07.847888 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 14:44:07.851168 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 14:44:07.854910 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 14:44:07.860589 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 14:44:07.863969 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 14:44:07.868120 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5429 14:44:07.874290 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5430 14:44:07.877076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5431 14:44:07.880570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 14:44:07.887172 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 14:44:07.890529 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 14:44:07.893999 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 14:44:07.900484 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 14:44:07.903866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 14:44:07.906992 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 14:44:07.913512 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 14:44:07.917063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 14:44:07.920390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 14:44:07.926975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 14:44:07.929941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 14:44:07.933505 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 14:44:07.940123 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5445 14:44:07.943185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5446 14:44:07.946798 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 14:44:07.949848 Total UI for P1: 0, mck2ui 16
5448 14:44:07.953345 best dqsien dly found for B0: ( 1, 2, 30)
5449 14:44:07.956418 Total UI for P1: 0, mck2ui 16
5450 14:44:07.959808 best dqsien dly found for B1: ( 1, 3, 0)
5451 14:44:07.963064 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5452 14:44:07.966293 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5453 14:44:07.966736
5454 14:44:07.973037 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5455 14:44:07.976333 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5456 14:44:07.976772 [Gating] SW calibration Done
5457 14:44:07.979332 ==
5458 14:44:07.979768 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 14:44:07.985741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 14:44:07.985829 ==
5461 14:44:07.985917 RX Vref Scan: 0
5462 14:44:07.986000
5463 14:44:07.988905 RX Vref 0 -> 0, step: 1
5464 14:44:07.988993
5465 14:44:07.992272 RX Delay -80 -> 252, step: 8
5466 14:44:07.995922 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5467 14:44:07.998627 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5468 14:44:08.002033 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5469 14:44:08.009074 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 14:44:08.012200 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5471 14:44:08.015126 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5472 14:44:08.018585 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5473 14:44:08.021683 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5474 14:44:08.025128 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5475 14:44:08.031730 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5476 14:44:08.035342 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5477 14:44:08.038626 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5478 14:44:08.041462 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5479 14:44:08.045006 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5480 14:44:08.051963 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5481 14:44:08.055029 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5482 14:44:08.055114 ==
5483 14:44:08.058320 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 14:44:08.061373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 14:44:08.061457 ==
5486 14:44:08.064897 DQS Delay:
5487 14:44:08.064981 DQS0 = 0, DQS1 = 0
5488 14:44:08.065047 DQM Delay:
5489 14:44:08.067978 DQM0 = 96, DQM1 = 89
5490 14:44:08.068061 DQ Delay:
5491 14:44:08.070930 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5492 14:44:08.074524 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =107
5493 14:44:08.077462 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5494 14:44:08.080929 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5495 14:44:08.081011
5496 14:44:08.081075
5497 14:44:08.084666 ==
5498 14:44:08.084748 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 14:44:08.090920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 14:44:08.091003 ==
5501 14:44:08.091068
5502 14:44:08.091127
5503 14:44:08.094271 TX Vref Scan disable
5504 14:44:08.094353 == TX Byte 0 ==
5505 14:44:08.097596 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5506 14:44:08.104106 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5507 14:44:08.104189 == TX Byte 1 ==
5508 14:44:08.107178 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5509 14:44:08.113716 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5510 14:44:08.113798 ==
5511 14:44:08.117527 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 14:44:08.120494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 14:44:08.120576 ==
5514 14:44:08.120641
5515 14:44:08.120701
5516 14:44:08.123850 TX Vref Scan disable
5517 14:44:08.127095 == TX Byte 0 ==
5518 14:44:08.130539 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5519 14:44:08.133685 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5520 14:44:08.136711 == TX Byte 1 ==
5521 14:44:08.140267 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5522 14:44:08.143474 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5523 14:44:08.143585
5524 14:44:08.146848 [DATLAT]
5525 14:44:08.146932 Freq=933, CH0 RK1
5526 14:44:08.147020
5527 14:44:08.149869 DATLAT Default: 0xb
5528 14:44:08.149954 0, 0xFFFF, sum = 0
5529 14:44:08.153074 1, 0xFFFF, sum = 0
5530 14:44:08.153180 2, 0xFFFF, sum = 0
5531 14:44:08.156748 3, 0xFFFF, sum = 0
5532 14:44:08.156834 4, 0xFFFF, sum = 0
5533 14:44:08.160245 5, 0xFFFF, sum = 0
5534 14:44:08.160331 6, 0xFFFF, sum = 0
5535 14:44:08.163258 7, 0xFFFF, sum = 0
5536 14:44:08.163344 8, 0xFFFF, sum = 0
5537 14:44:08.166826 9, 0xFFFF, sum = 0
5538 14:44:08.166912 10, 0x0, sum = 1
5539 14:44:08.169687 11, 0x0, sum = 2
5540 14:44:08.169773 12, 0x0, sum = 3
5541 14:44:08.173310 13, 0x0, sum = 4
5542 14:44:08.173396 best_step = 11
5543 14:44:08.173482
5544 14:44:08.173562 ==
5545 14:44:08.176426 Dram Type= 6, Freq= 0, CH_0, rank 1
5546 14:44:08.182824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 14:44:08.182911 ==
5548 14:44:08.182997 RX Vref Scan: 0
5549 14:44:08.183078
5550 14:44:08.186128 RX Vref 0 -> 0, step: 1
5551 14:44:08.186254
5552 14:44:08.190299 RX Delay -61 -> 252, step: 4
5553 14:44:08.192923 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5554 14:44:08.199293 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5555 14:44:08.202607 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5556 14:44:08.206049 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5557 14:44:08.209447 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5558 14:44:08.212985 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5559 14:44:08.216375 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5560 14:44:08.222577 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5561 14:44:08.225971 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5562 14:44:08.229199 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5563 14:44:08.232500 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5564 14:44:08.235743 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5565 14:44:08.242663 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5566 14:44:08.245405 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5567 14:44:08.248855 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5568 14:44:08.252298 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5569 14:44:08.252380 ==
5570 14:44:08.255723 Dram Type= 6, Freq= 0, CH_0, rank 1
5571 14:44:08.261947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 14:44:08.262051 ==
5573 14:44:08.262159 DQS Delay:
5574 14:44:08.262265 DQS0 = 0, DQS1 = 0
5575 14:44:08.265860 DQM Delay:
5576 14:44:08.265944 DQM0 = 95, DQM1 = 88
5577 14:44:08.268929 DQ Delay:
5578 14:44:08.272103 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5579 14:44:08.275465 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5580 14:44:08.278752 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5581 14:44:08.282180 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =94
5582 14:44:08.282278
5583 14:44:08.282342
5584 14:44:08.288509 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5585 14:44:08.291883 CH0 RK1: MR19=504, MR18=27F8
5586 14:44:08.298570 CH0_RK1: MR19=0x504, MR18=0x27F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5587 14:44:08.301989 [RxdqsGatingPostProcess] freq 933
5588 14:44:08.305591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5589 14:44:08.308572 best DQS0 dly(2T, 0.5T) = (0, 10)
5590 14:44:08.311648 best DQS1 dly(2T, 0.5T) = (0, 10)
5591 14:44:08.314852 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5592 14:44:08.318283 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5593 14:44:08.321790 best DQS0 dly(2T, 0.5T) = (0, 10)
5594 14:44:08.325024 best DQS1 dly(2T, 0.5T) = (0, 11)
5595 14:44:08.328344 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5596 14:44:08.331663 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5597 14:44:08.334925 Pre-setting of DQS Precalculation
5598 14:44:08.338512 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5599 14:44:08.338595 ==
5600 14:44:08.341450 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 14:44:08.348027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 14:44:08.348109 ==
5603 14:44:08.351152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5604 14:44:08.358103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5605 14:44:08.361469 [CA 0] Center 37 (7~67) winsize 61
5606 14:44:08.365141 [CA 1] Center 37 (7~68) winsize 62
5607 14:44:08.368078 [CA 2] Center 34 (4~65) winsize 62
5608 14:44:08.371461 [CA 3] Center 33 (3~64) winsize 62
5609 14:44:08.374741 [CA 4] Center 34 (4~65) winsize 62
5610 14:44:08.378077 [CA 5] Center 33 (3~64) winsize 62
5611 14:44:08.378159
5612 14:44:08.381583 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5613 14:44:08.381665
5614 14:44:08.384354 [CATrainingPosCal] consider 1 rank data
5615 14:44:08.387728 u2DelayCellTimex100 = 270/100 ps
5616 14:44:08.391029 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5617 14:44:08.397723 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5618 14:44:08.401050 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5619 14:44:08.404389 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5620 14:44:08.407497 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5621 14:44:08.411055 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5622 14:44:08.411138
5623 14:44:08.414411 CA PerBit enable=1, Macro0, CA PI delay=33
5624 14:44:08.414493
5625 14:44:08.417271 [CBTSetCACLKResult] CA Dly = 33
5626 14:44:08.420845 CS Dly: 6 (0~37)
5627 14:44:08.420927 ==
5628 14:44:08.423993 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 14:44:08.427122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 14:44:08.427204 ==
5631 14:44:08.434168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5632 14:44:08.436965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5633 14:44:08.441529 [CA 0] Center 37 (7~67) winsize 61
5634 14:44:08.444539 [CA 1] Center 37 (7~68) winsize 62
5635 14:44:08.447886 [CA 2] Center 34 (4~65) winsize 62
5636 14:44:08.451337 [CA 3] Center 34 (4~65) winsize 62
5637 14:44:08.455019 [CA 4] Center 34 (3~65) winsize 63
5638 14:44:08.458048 [CA 5] Center 33 (3~64) winsize 62
5639 14:44:08.458130
5640 14:44:08.461268 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5641 14:44:08.461349
5642 14:44:08.464465 [CATrainingPosCal] consider 2 rank data
5643 14:44:08.467727 u2DelayCellTimex100 = 270/100 ps
5644 14:44:08.471340 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5645 14:44:08.477965 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5646 14:44:08.480909 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5647 14:44:08.484499 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5648 14:44:08.487763 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5649 14:44:08.490792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5650 14:44:08.490874
5651 14:44:08.494105 CA PerBit enable=1, Macro0, CA PI delay=33
5652 14:44:08.494199
5653 14:44:08.497494 [CBTSetCACLKResult] CA Dly = 33
5654 14:44:08.500824 CS Dly: 7 (0~39)
5655 14:44:08.500905
5656 14:44:08.503936 ----->DramcWriteLeveling(PI) begin...
5657 14:44:08.504020 ==
5658 14:44:08.507154 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 14:44:08.510885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 14:44:08.510967 ==
5661 14:44:08.513904 Write leveling (Byte 0): 28 => 28
5662 14:44:08.517364 Write leveling (Byte 1): 28 => 28
5663 14:44:08.520229 DramcWriteLeveling(PI) end<-----
5664 14:44:08.520311
5665 14:44:08.520376 ==
5666 14:44:08.524026 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 14:44:08.527295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 14:44:08.527378 ==
5669 14:44:08.530216 [Gating] SW mode calibration
5670 14:44:08.537002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5671 14:44:08.543498 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5672 14:44:08.546941 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 14:44:08.550454 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 14:44:08.556980 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 14:44:08.559850 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 14:44:08.563198 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 14:44:08.570005 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 14:44:08.573441 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
5679 14:44:08.576766 0 14 28 | B1->B0 | 2d2d 2c2c | 0 0 | (1 1) (1 1)
5680 14:44:08.583053 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5681 14:44:08.586493 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 14:44:08.590088 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 14:44:08.596114 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 14:44:08.599560 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 14:44:08.602762 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 14:44:08.609755 0 15 24 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
5687 14:44:08.612903 0 15 28 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
5688 14:44:08.616368 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 14:44:08.622525 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 14:44:08.626157 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 14:44:08.629917 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 14:44:08.636157 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 14:44:08.639341 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 14:44:08.642596 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5695 14:44:08.648828 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 14:44:08.652180 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 14:44:08.655492 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 14:44:08.662347 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 14:44:08.665635 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 14:44:08.668929 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 14:44:08.675997 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 14:44:08.679000 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 14:44:08.681904 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 14:44:08.688484 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 14:44:08.691899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 14:44:08.695274 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 14:44:08.702053 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 14:44:08.705299 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 14:44:08.708240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 14:44:08.715195 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5711 14:44:08.718130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5712 14:44:08.721528 Total UI for P1: 0, mck2ui 16
5713 14:44:08.724762 best dqsien dly found for B0: ( 1, 2, 24)
5714 14:44:08.727931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5715 14:44:08.731387 Total UI for P1: 0, mck2ui 16
5716 14:44:08.735003 best dqsien dly found for B1: ( 1, 2, 28)
5717 14:44:08.741289 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5718 14:44:08.744562 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5719 14:44:08.744644
5720 14:44:08.748028 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5721 14:44:08.751045 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5722 14:44:08.754128 [Gating] SW calibration Done
5723 14:44:08.754219 ==
5724 14:44:08.757876 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 14:44:08.760627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 14:44:08.760709 ==
5727 14:44:08.764022 RX Vref Scan: 0
5728 14:44:08.764103
5729 14:44:08.764168 RX Vref 0 -> 0, step: 1
5730 14:44:08.764229
5731 14:44:08.767449 RX Delay -80 -> 252, step: 8
5732 14:44:08.771008 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5733 14:44:08.777529 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5734 14:44:08.780666 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5735 14:44:08.784149 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5736 14:44:08.787698 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5737 14:44:08.790921 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5738 14:44:08.794014 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5739 14:44:08.800357 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5740 14:44:08.804030 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5741 14:44:08.807333 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5742 14:44:08.810614 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5743 14:44:08.813560 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5744 14:44:08.820392 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5745 14:44:08.823383 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5746 14:44:08.826577 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5747 14:44:08.829882 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5748 14:44:08.829964 ==
5749 14:44:08.833183 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 14:44:08.836570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 14:44:08.839810 ==
5752 14:44:08.839892 DQS Delay:
5753 14:44:08.839956 DQS0 = 0, DQS1 = 0
5754 14:44:08.843009 DQM Delay:
5755 14:44:08.843091 DQM0 = 102, DQM1 = 91
5756 14:44:08.846346 DQ Delay:
5757 14:44:08.850031 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5758 14:44:08.852795 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5759 14:44:08.856247 DQ8 =75, DQ9 =83, DQ10 =95, DQ11 =79
5760 14:44:08.859644 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5761 14:44:08.859726
5762 14:44:08.859791
5763 14:44:08.859851 ==
5764 14:44:08.862791 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 14:44:08.866149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 14:44:08.866269 ==
5767 14:44:08.866335
5768 14:44:08.866396
5769 14:44:08.869533 TX Vref Scan disable
5770 14:44:08.872713 == TX Byte 0 ==
5771 14:44:08.875884 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5772 14:44:08.879687 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5773 14:44:08.882439 == TX Byte 1 ==
5774 14:44:08.886365 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5775 14:44:08.889211 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5776 14:44:08.889293 ==
5777 14:44:08.892645 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 14:44:08.895899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 14:44:08.899527 ==
5780 14:44:08.899609
5781 14:44:08.899673
5782 14:44:08.899733 TX Vref Scan disable
5783 14:44:08.902988 == TX Byte 0 ==
5784 14:44:08.906013 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5785 14:44:08.912651 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5786 14:44:08.912739 == TX Byte 1 ==
5787 14:44:08.916272 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5788 14:44:08.922575 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5789 14:44:08.922657
5790 14:44:08.922722 [DATLAT]
5791 14:44:08.922782 Freq=933, CH1 RK0
5792 14:44:08.922841
5793 14:44:08.925948 DATLAT Default: 0xd
5794 14:44:08.928966 0, 0xFFFF, sum = 0
5795 14:44:08.929050 1, 0xFFFF, sum = 0
5796 14:44:08.932306 2, 0xFFFF, sum = 0
5797 14:44:08.932389 3, 0xFFFF, sum = 0
5798 14:44:08.935541 4, 0xFFFF, sum = 0
5799 14:44:08.935624 5, 0xFFFF, sum = 0
5800 14:44:08.938913 6, 0xFFFF, sum = 0
5801 14:44:08.938996 7, 0xFFFF, sum = 0
5802 14:44:08.942432 8, 0xFFFF, sum = 0
5803 14:44:08.942516 9, 0xFFFF, sum = 0
5804 14:44:08.945439 10, 0x0, sum = 1
5805 14:44:08.945523 11, 0x0, sum = 2
5806 14:44:08.948586 12, 0x0, sum = 3
5807 14:44:08.948669 13, 0x0, sum = 4
5808 14:44:08.952319 best_step = 11
5809 14:44:08.952401
5810 14:44:08.952466 ==
5811 14:44:08.955522 Dram Type= 6, Freq= 0, CH_1, rank 0
5812 14:44:08.959025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 14:44:08.959109 ==
5814 14:44:08.959174 RX Vref Scan: 1
5815 14:44:08.962144
5816 14:44:08.962262 RX Vref 0 -> 0, step: 1
5817 14:44:08.962328
5818 14:44:08.965224 RX Delay -69 -> 252, step: 4
5819 14:44:08.965307
5820 14:44:08.968422 Set Vref, RX VrefLevel [Byte0]: 51
5821 14:44:08.971989 [Byte1]: 55
5822 14:44:08.975427
5823 14:44:08.975509 Final RX Vref Byte 0 = 51 to rank0
5824 14:44:08.978515 Final RX Vref Byte 1 = 55 to rank0
5825 14:44:08.981773 Final RX Vref Byte 0 = 51 to rank1
5826 14:44:08.985051 Final RX Vref Byte 1 = 55 to rank1==
5827 14:44:08.988591 Dram Type= 6, Freq= 0, CH_1, rank 0
5828 14:44:08.994960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 14:44:08.995043 ==
5830 14:44:08.995108 DQS Delay:
5831 14:44:08.998214 DQS0 = 0, DQS1 = 0
5832 14:44:08.998297 DQM Delay:
5833 14:44:08.998362 DQM0 = 101, DQM1 = 94
5834 14:44:09.001451 DQ Delay:
5835 14:44:09.004927 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5836 14:44:09.008297 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5837 14:44:09.011879 DQ8 =80, DQ9 =86, DQ10 =94, DQ11 =86
5838 14:44:09.014550 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =104
5839 14:44:09.014632
5840 14:44:09.014697
5841 14:44:09.021365 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5842 14:44:09.024430 CH1 RK0: MR19=505, MR18=1A0A
5843 14:44:09.031156 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5844 14:44:09.031239
5845 14:44:09.034610 ----->DramcWriteLeveling(PI) begin...
5846 14:44:09.034694 ==
5847 14:44:09.037571 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 14:44:09.041170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 14:44:09.044735 ==
5850 14:44:09.047640 Write leveling (Byte 0): 25 => 25
5851 14:44:09.047723 Write leveling (Byte 1): 27 => 27
5852 14:44:09.050898 DramcWriteLeveling(PI) end<-----
5853 14:44:09.050981
5854 14:44:09.051046 ==
5855 14:44:09.054380 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 14:44:09.060788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 14:44:09.060878 ==
5858 14:44:09.064419 [Gating] SW mode calibration
5859 14:44:09.070497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5860 14:44:09.073975 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5861 14:44:09.080381 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5862 14:44:09.083412 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 14:44:09.086772 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 14:44:09.093713 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 14:44:09.097041 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 14:44:09.100345 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 14:44:09.106935 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5868 14:44:09.110375 0 14 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 0)
5869 14:44:09.113376 0 15 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5870 14:44:09.120017 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 14:44:09.123273 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 14:44:09.127130 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 14:44:09.133487 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 14:44:09.137032 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5875 14:44:09.140358 0 15 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5876 14:44:09.146528 0 15 28 | B1->B0 | 3e3e 3030 | 0 0 | (0 0) (0 0)
5877 14:44:09.150066 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5878 14:44:09.153265 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 14:44:09.160311 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 14:44:09.162874 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 14:44:09.166207 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 14:44:09.173084 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 14:44:09.176279 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5884 14:44:09.179360 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 14:44:09.186427 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 14:44:09.189605 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 14:44:09.192666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 14:44:09.199519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 14:44:09.202793 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 14:44:09.206255 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 14:44:09.213006 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 14:44:09.216125 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 14:44:09.219031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 14:44:09.225728 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 14:44:09.228855 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 14:44:09.232211 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 14:44:09.238752 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 14:44:09.242403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5899 14:44:09.245482 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5900 14:44:09.252112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5901 14:44:09.252193 Total UI for P1: 0, mck2ui 16
5902 14:44:09.258829 best dqsien dly found for B0: ( 1, 2, 24)
5903 14:44:09.258911 Total UI for P1: 0, mck2ui 16
5904 14:44:09.265232 best dqsien dly found for B1: ( 1, 2, 22)
5905 14:44:09.268821 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5906 14:44:09.271848 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5907 14:44:09.271935
5908 14:44:09.274970 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5909 14:44:09.278175 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5910 14:44:09.281683 [Gating] SW calibration Done
5911 14:44:09.281765 ==
5912 14:44:09.284866 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 14:44:09.288275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 14:44:09.288358 ==
5915 14:44:09.291652 RX Vref Scan: 0
5916 14:44:09.291733
5917 14:44:09.291797 RX Vref 0 -> 0, step: 1
5918 14:44:09.291858
5919 14:44:09.295247 RX Delay -80 -> 252, step: 8
5920 14:44:09.298659 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5921 14:44:09.304764 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5922 14:44:09.308027 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5923 14:44:09.311497 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5924 14:44:09.314690 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5925 14:44:09.317836 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5926 14:44:09.324346 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5927 14:44:09.327706 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5928 14:44:09.331064 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5929 14:44:09.334465 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5930 14:44:09.337731 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5931 14:44:09.344388 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5932 14:44:09.347418 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5933 14:44:09.350916 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5934 14:44:09.353989 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5935 14:44:09.357331 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5936 14:44:09.357413 ==
5937 14:44:09.360591 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 14:44:09.367590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 14:44:09.367671 ==
5940 14:44:09.367737 DQS Delay:
5941 14:44:09.370887 DQS0 = 0, DQS1 = 0
5942 14:44:09.370968 DQM Delay:
5943 14:44:09.371033 DQM0 = 100, DQM1 = 90
5944 14:44:09.374030 DQ Delay:
5945 14:44:09.377202 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5946 14:44:09.380297 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =99
5947 14:44:09.384106 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5948 14:44:09.387359 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5949 14:44:09.387440
5950 14:44:09.387504
5951 14:44:09.387563 ==
5952 14:44:09.390299 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 14:44:09.393675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 14:44:09.393757 ==
5955 14:44:09.393822
5956 14:44:09.393881
5957 14:44:09.397555 TX Vref Scan disable
5958 14:44:09.400340 == TX Byte 0 ==
5959 14:44:09.403749 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5960 14:44:09.407156 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5961 14:44:09.410767 == TX Byte 1 ==
5962 14:44:09.413416 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5963 14:44:09.416799 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5964 14:44:09.416913 ==
5965 14:44:09.420269 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 14:44:09.423891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 14:44:09.426674 ==
5968 14:44:09.426754
5969 14:44:09.426818
5970 14:44:09.426876 TX Vref Scan disable
5971 14:44:09.430428 == TX Byte 0 ==
5972 14:44:09.433856 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5973 14:44:09.440814 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5974 14:44:09.440896 == TX Byte 1 ==
5975 14:44:09.443857 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5976 14:44:09.450464 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5977 14:44:09.450546
5978 14:44:09.450611 [DATLAT]
5979 14:44:09.450671 Freq=933, CH1 RK1
5980 14:44:09.450731
5981 14:44:09.453578 DATLAT Default: 0xb
5982 14:44:09.453660 0, 0xFFFF, sum = 0
5983 14:44:09.457041 1, 0xFFFF, sum = 0
5984 14:44:09.460287 2, 0xFFFF, sum = 0
5985 14:44:09.460370 3, 0xFFFF, sum = 0
5986 14:44:09.463419 4, 0xFFFF, sum = 0
5987 14:44:09.463502 5, 0xFFFF, sum = 0
5988 14:44:09.466671 6, 0xFFFF, sum = 0
5989 14:44:09.466755 7, 0xFFFF, sum = 0
5990 14:44:09.469911 8, 0xFFFF, sum = 0
5991 14:44:09.469993 9, 0xFFFF, sum = 0
5992 14:44:09.473443 10, 0x0, sum = 1
5993 14:44:09.473527 11, 0x0, sum = 2
5994 14:44:09.476678 12, 0x0, sum = 3
5995 14:44:09.476761 13, 0x0, sum = 4
5996 14:44:09.476827 best_step = 11
5997 14:44:09.480073
5998 14:44:09.480154 ==
5999 14:44:09.483689 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 14:44:09.486599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 14:44:09.486680 ==
6002 14:44:09.486744 RX Vref Scan: 0
6003 14:44:09.486804
6004 14:44:09.490062 RX Vref 0 -> 0, step: 1
6005 14:44:09.490193
6006 14:44:09.493234 RX Delay -61 -> 252, step: 4
6007 14:44:09.499791 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6008 14:44:09.503020 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
6009 14:44:09.506413 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6010 14:44:09.509447 iDelay=207, Bit 3, Center 100 (15 ~ 186) 172
6011 14:44:09.513197 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6012 14:44:09.519116 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6013 14:44:09.522900 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6014 14:44:09.526052 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6015 14:44:09.529196 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6016 14:44:09.532745 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6017 14:44:09.535893 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6018 14:44:09.542197 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6019 14:44:09.545824 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6020 14:44:09.548981 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6021 14:44:09.552296 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6022 14:44:09.559054 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6023 14:44:09.559136 ==
6024 14:44:09.562150 Dram Type= 6, Freq= 0, CH_1, rank 1
6025 14:44:09.565686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6026 14:44:09.565771 ==
6027 14:44:09.565837 DQS Delay:
6028 14:44:09.568726 DQS0 = 0, DQS1 = 0
6029 14:44:09.568808 DQM Delay:
6030 14:44:09.572212 DQM0 = 101, DQM1 = 92
6031 14:44:09.572294 DQ Delay:
6032 14:44:09.575867 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =100
6033 14:44:09.578525 DQ4 =98, DQ5 =112, DQ6 =112, DQ7 =98
6034 14:44:09.582033 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =82
6035 14:44:09.585177 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
6036 14:44:09.585259
6037 14:44:09.585324
6038 14:44:09.595397 [DQSOSCAuto] RK1, (LSB)MR18= 0xb05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6039 14:44:09.595480 CH1 RK1: MR19=505, MR18=B05
6040 14:44:09.601796 CH1_RK1: MR19=0x505, MR18=0xB05, DQSOSC=418, MR23=63, INC=62, DEC=41
6041 14:44:09.605291 [RxdqsGatingPostProcess] freq 933
6042 14:44:09.611747 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6043 14:44:09.615315 best DQS0 dly(2T, 0.5T) = (0, 10)
6044 14:44:09.618460 best DQS1 dly(2T, 0.5T) = (0, 10)
6045 14:44:09.621712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6046 14:44:09.625206 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6047 14:44:09.628344 best DQS0 dly(2T, 0.5T) = (0, 10)
6048 14:44:09.628426 best DQS1 dly(2T, 0.5T) = (0, 10)
6049 14:44:09.631690 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6050 14:44:09.635193 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6051 14:44:09.638474 Pre-setting of DQS Precalculation
6052 14:44:09.644684 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6053 14:44:09.651535 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6054 14:44:09.658071 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6055 14:44:09.658152
6056 14:44:09.658223
6057 14:44:09.661439 [Calibration Summary] 1866 Mbps
6058 14:44:09.664970 CH 0, Rank 0
6059 14:44:09.665051 SW Impedance : PASS
6060 14:44:09.668292 DUTY Scan : NO K
6061 14:44:09.671563 ZQ Calibration : PASS
6062 14:44:09.671645 Jitter Meter : NO K
6063 14:44:09.674589 CBT Training : PASS
6064 14:44:09.674670 Write leveling : PASS
6065 14:44:09.678197 RX DQS gating : PASS
6066 14:44:09.681117 RX DQ/DQS(RDDQC) : PASS
6067 14:44:09.681199 TX DQ/DQS : PASS
6068 14:44:09.684153 RX DATLAT : PASS
6069 14:44:09.687719 RX DQ/DQS(Engine): PASS
6070 14:44:09.687801 TX OE : NO K
6071 14:44:09.691197 All Pass.
6072 14:44:09.691277
6073 14:44:09.691341 CH 0, Rank 1
6074 14:44:09.694360 SW Impedance : PASS
6075 14:44:09.694441 DUTY Scan : NO K
6076 14:44:09.697465 ZQ Calibration : PASS
6077 14:44:09.700884 Jitter Meter : NO K
6078 14:44:09.700966 CBT Training : PASS
6079 14:44:09.704113 Write leveling : PASS
6080 14:44:09.707780 RX DQS gating : PASS
6081 14:44:09.707862 RX DQ/DQS(RDDQC) : PASS
6082 14:44:09.710752 TX DQ/DQS : PASS
6083 14:44:09.714278 RX DATLAT : PASS
6084 14:44:09.714358 RX DQ/DQS(Engine): PASS
6085 14:44:09.717678 TX OE : NO K
6086 14:44:09.717759 All Pass.
6087 14:44:09.717823
6088 14:44:09.721517 CH 1, Rank 0
6089 14:44:09.721597 SW Impedance : PASS
6090 14:44:09.724264 DUTY Scan : NO K
6091 14:44:09.727837 ZQ Calibration : PASS
6092 14:44:09.727917 Jitter Meter : NO K
6093 14:44:09.730990 CBT Training : PASS
6094 14:44:09.731072 Write leveling : PASS
6095 14:44:09.734238 RX DQS gating : PASS
6096 14:44:09.737580 RX DQ/DQS(RDDQC) : PASS
6097 14:44:09.737661 TX DQ/DQS : PASS
6098 14:44:09.740896 RX DATLAT : PASS
6099 14:44:09.743887 RX DQ/DQS(Engine): PASS
6100 14:44:09.743968 TX OE : NO K
6101 14:44:09.747385 All Pass.
6102 14:44:09.747466
6103 14:44:09.747529 CH 1, Rank 1
6104 14:44:09.751168 SW Impedance : PASS
6105 14:44:09.751250 DUTY Scan : NO K
6106 14:44:09.753942 ZQ Calibration : PASS
6107 14:44:09.757197 Jitter Meter : NO K
6108 14:44:09.757278 CBT Training : PASS
6109 14:44:09.760545 Write leveling : PASS
6110 14:44:09.763826 RX DQS gating : PASS
6111 14:44:09.763919 RX DQ/DQS(RDDQC) : PASS
6112 14:44:09.767364 TX DQ/DQS : PASS
6113 14:44:09.770534 RX DATLAT : PASS
6114 14:44:09.770615 RX DQ/DQS(Engine): PASS
6115 14:44:09.774072 TX OE : NO K
6116 14:44:09.774153 All Pass.
6117 14:44:09.774254
6118 14:44:09.777146 DramC Write-DBI off
6119 14:44:09.781035 PER_BANK_REFRESH: Hybrid Mode
6120 14:44:09.781116 TX_TRACKING: ON
6121 14:44:09.790469 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6122 14:44:09.793689 [FAST_K] Save calibration result to emmc
6123 14:44:09.796550 dramc_set_vcore_voltage set vcore to 650000
6124 14:44:09.800328 Read voltage for 400, 6
6125 14:44:09.800409 Vio18 = 0
6126 14:44:09.800473 Vcore = 650000
6127 14:44:09.803554 Vdram = 0
6128 14:44:09.803634 Vddq = 0
6129 14:44:09.803698 Vmddr = 0
6130 14:44:09.810063 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6131 14:44:09.813065 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6132 14:44:09.816420 MEM_TYPE=3, freq_sel=20
6133 14:44:09.820010 sv_algorithm_assistance_LP4_800
6134 14:44:09.822777 ============ PULL DRAM RESETB DOWN ============
6135 14:44:09.829542 ========== PULL DRAM RESETB DOWN end =========
6136 14:44:09.832811 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6137 14:44:09.835987 ===================================
6138 14:44:09.839669 LPDDR4 DRAM CONFIGURATION
6139 14:44:09.842955 ===================================
6140 14:44:09.843037 EX_ROW_EN[0] = 0x0
6141 14:44:09.845958 EX_ROW_EN[1] = 0x0
6142 14:44:09.846066 LP4Y_EN = 0x0
6143 14:44:09.849561 WORK_FSP = 0x0
6144 14:44:09.849643 WL = 0x2
6145 14:44:09.852593 RL = 0x2
6146 14:44:09.852675 BL = 0x2
6147 14:44:09.855867 RPST = 0x0
6148 14:44:09.859164 RD_PRE = 0x0
6149 14:44:09.859246 WR_PRE = 0x1
6150 14:44:09.862562 WR_PST = 0x0
6151 14:44:09.862643 DBI_WR = 0x0
6152 14:44:09.866607 DBI_RD = 0x0
6153 14:44:09.866690 OTF = 0x1
6154 14:44:09.869449 ===================================
6155 14:44:09.872512 ===================================
6156 14:44:09.876087 ANA top config
6157 14:44:09.879316 ===================================
6158 14:44:09.879399 DLL_ASYNC_EN = 0
6159 14:44:09.882283 ALL_SLAVE_EN = 1
6160 14:44:09.885626 NEW_RANK_MODE = 1
6161 14:44:09.889143 DLL_IDLE_MODE = 1
6162 14:44:09.889225 LP45_APHY_COMB_EN = 1
6163 14:44:09.892309 TX_ODT_DIS = 1
6164 14:44:09.895651 NEW_8X_MODE = 1
6165 14:44:09.899152 ===================================
6166 14:44:09.902408 ===================================
6167 14:44:09.905678 data_rate = 800
6168 14:44:09.908761 CKR = 1
6169 14:44:09.912274 DQ_P2S_RATIO = 4
6170 14:44:09.915510 ===================================
6171 14:44:09.915591 CA_P2S_RATIO = 4
6172 14:44:09.918574 DQ_CA_OPEN = 0
6173 14:44:09.921811 DQ_SEMI_OPEN = 1
6174 14:44:09.925140 CA_SEMI_OPEN = 1
6175 14:44:09.928593 CA_FULL_RATE = 0
6176 14:44:09.931872 DQ_CKDIV4_EN = 0
6177 14:44:09.931959 CA_CKDIV4_EN = 1
6178 14:44:09.935024 CA_PREDIV_EN = 0
6179 14:44:09.938485 PH8_DLY = 0
6180 14:44:09.941993 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6181 14:44:09.944672 DQ_AAMCK_DIV = 0
6182 14:44:09.948250 CA_AAMCK_DIV = 0
6183 14:44:09.948332 CA_ADMCK_DIV = 4
6184 14:44:09.951316 DQ_TRACK_CA_EN = 0
6185 14:44:09.954590 CA_PICK = 800
6186 14:44:09.957995 CA_MCKIO = 400
6187 14:44:09.961299 MCKIO_SEMI = 400
6188 14:44:09.964851 PLL_FREQ = 3016
6189 14:44:09.968453 DQ_UI_PI_RATIO = 32
6190 14:44:09.971067 CA_UI_PI_RATIO = 32
6191 14:44:09.974318 ===================================
6192 14:44:09.977534 ===================================
6193 14:44:09.977616 memory_type:LPDDR4
6194 14:44:09.981162 GP_NUM : 10
6195 14:44:09.984215 SRAM_EN : 1
6196 14:44:09.984296 MD32_EN : 0
6197 14:44:09.987562 ===================================
6198 14:44:09.991011 [ANA_INIT] >>>>>>>>>>>>>>
6199 14:44:09.994106 <<<<<< [CONFIGURE PHASE]: ANA_TX
6200 14:44:09.997572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6201 14:44:10.000736 ===================================
6202 14:44:10.004111 data_rate = 800,PCW = 0X7400
6203 14:44:10.007379 ===================================
6204 14:44:10.010266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6205 14:44:10.013733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6206 14:44:10.027015 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6207 14:44:10.030351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6208 14:44:10.033662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6209 14:44:10.036685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6210 14:44:10.040496 [ANA_INIT] flow start
6211 14:44:10.043678 [ANA_INIT] PLL >>>>>>>>
6212 14:44:10.043759 [ANA_INIT] PLL <<<<<<<<
6213 14:44:10.046500 [ANA_INIT] MIDPI >>>>>>>>
6214 14:44:10.050136 [ANA_INIT] MIDPI <<<<<<<<
6215 14:44:10.053484 [ANA_INIT] DLL >>>>>>>>
6216 14:44:10.053564 [ANA_INIT] flow end
6217 14:44:10.056609 ============ LP4 DIFF to SE enter ============
6218 14:44:10.063299 ============ LP4 DIFF to SE exit ============
6219 14:44:10.063383 [ANA_INIT] <<<<<<<<<<<<<
6220 14:44:10.066576 [Flow] Enable top DCM control >>>>>
6221 14:44:10.069470 [Flow] Enable top DCM control <<<<<
6222 14:44:10.073236 Enable DLL master slave shuffle
6223 14:44:10.079649 ==============================================================
6224 14:44:10.079755 Gating Mode config
6225 14:44:10.086156 ==============================================================
6226 14:44:10.089988 Config description:
6227 14:44:10.099526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6228 14:44:10.106423 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6229 14:44:10.109365 SELPH_MODE 0: By rank 1: By Phase
6230 14:44:10.116072 ==============================================================
6231 14:44:10.119287 GAT_TRACK_EN = 0
6232 14:44:10.122295 RX_GATING_MODE = 2
6233 14:44:10.122368 RX_GATING_TRACK_MODE = 2
6234 14:44:10.126047 SELPH_MODE = 1
6235 14:44:10.128952 PICG_EARLY_EN = 1
6236 14:44:10.132375 VALID_LAT_VALUE = 1
6237 14:44:10.139183 ==============================================================
6238 14:44:10.142581 Enter into Gating configuration >>>>
6239 14:44:10.145773 Exit from Gating configuration <<<<
6240 14:44:10.148861 Enter into DVFS_PRE_config >>>>>
6241 14:44:10.158954 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6242 14:44:10.162195 Exit from DVFS_PRE_config <<<<<
6243 14:44:10.165402 Enter into PICG configuration >>>>
6244 14:44:10.168526 Exit from PICG configuration <<<<
6245 14:44:10.172026 [RX_INPUT] configuration >>>>>
6246 14:44:10.175109 [RX_INPUT] configuration <<<<<
6247 14:44:10.178750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6248 14:44:10.185170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6249 14:44:10.191971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 14:44:10.198376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 14:44:10.204907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6252 14:44:10.211751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6253 14:44:10.215162 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6254 14:44:10.218325 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6255 14:44:10.221201 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6256 14:44:10.228093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6257 14:44:10.231242 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6258 14:44:10.234634 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6259 14:44:10.238001 ===================================
6260 14:44:10.241199 LPDDR4 DRAM CONFIGURATION
6261 14:44:10.244693 ===================================
6262 14:44:10.244776 EX_ROW_EN[0] = 0x0
6263 14:44:10.248246 EX_ROW_EN[1] = 0x0
6264 14:44:10.248352 LP4Y_EN = 0x0
6265 14:44:10.251039 WORK_FSP = 0x0
6266 14:44:10.254266 WL = 0x2
6267 14:44:10.254335 RL = 0x2
6268 14:44:10.257500 BL = 0x2
6269 14:44:10.257614 RPST = 0x0
6270 14:44:10.260906 RD_PRE = 0x0
6271 14:44:10.261001 WR_PRE = 0x1
6272 14:44:10.264269 WR_PST = 0x0
6273 14:44:10.264391 DBI_WR = 0x0
6274 14:44:10.267896 DBI_RD = 0x0
6275 14:44:10.268053 OTF = 0x1
6276 14:44:10.270841 ===================================
6277 14:44:10.274144 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6278 14:44:10.280754 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6279 14:44:10.284223 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6280 14:44:10.287298 ===================================
6281 14:44:10.290513 LPDDR4 DRAM CONFIGURATION
6282 14:44:10.294205 ===================================
6283 14:44:10.294438 EX_ROW_EN[0] = 0x10
6284 14:44:10.297963 EX_ROW_EN[1] = 0x0
6285 14:44:10.298197 LP4Y_EN = 0x0
6286 14:44:10.300839 WORK_FSP = 0x0
6287 14:44:10.304028 WL = 0x2
6288 14:44:10.304239 RL = 0x2
6289 14:44:10.307004 BL = 0x2
6290 14:44:10.307152 RPST = 0x0
6291 14:44:10.310655 RD_PRE = 0x0
6292 14:44:10.310840 WR_PRE = 0x1
6293 14:44:10.314122 WR_PST = 0x0
6294 14:44:10.314728 DBI_WR = 0x0
6295 14:44:10.317144 DBI_RD = 0x0
6296 14:44:10.317701 OTF = 0x1
6297 14:44:10.320742 ===================================
6298 14:44:10.327444 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6299 14:44:10.331380 nWR fixed to 30
6300 14:44:10.334930 [ModeRegInit_LP4] CH0 RK0
6301 14:44:10.335362 [ModeRegInit_LP4] CH0 RK1
6302 14:44:10.338061 [ModeRegInit_LP4] CH1 RK0
6303 14:44:10.341280 [ModeRegInit_LP4] CH1 RK1
6304 14:44:10.341725 match AC timing 19
6305 14:44:10.347920 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6306 14:44:10.351352 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6307 14:44:10.354575 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6308 14:44:10.361436 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6309 14:44:10.364555 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6310 14:44:10.365111 ==
6311 14:44:10.367564 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 14:44:10.371148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 14:44:10.371584 ==
6314 14:44:10.377732 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 14:44:10.384445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6316 14:44:10.387480 [CA 0] Center 36 (8~64) winsize 57
6317 14:44:10.390916 [CA 1] Center 36 (8~64) winsize 57
6318 14:44:10.394076 [CA 2] Center 36 (8~64) winsize 57
6319 14:44:10.397721 [CA 3] Center 36 (8~64) winsize 57
6320 14:44:10.400733 [CA 4] Center 36 (8~64) winsize 57
6321 14:44:10.403954 [CA 5] Center 36 (8~64) winsize 57
6322 14:44:10.404457
6323 14:44:10.407521 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6324 14:44:10.408108
6325 14:44:10.410778 [CATrainingPosCal] consider 1 rank data
6326 14:44:10.414105 u2DelayCellTimex100 = 270/100 ps
6327 14:44:10.417724 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 14:44:10.420649 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 14:44:10.423864 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 14:44:10.427240 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 14:44:10.430277 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 14:44:10.433271 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 14:44:10.433700
6334 14:44:10.439946 CA PerBit enable=1, Macro0, CA PI delay=36
6335 14:44:10.440465
6336 14:44:10.440838 [CBTSetCACLKResult] CA Dly = 36
6337 14:44:10.443680 CS Dly: 1 (0~32)
6338 14:44:10.444208 ==
6339 14:44:10.446731 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 14:44:10.449947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 14:44:10.450431 ==
6342 14:44:10.456362 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6343 14:44:10.462866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6344 14:44:10.466404 [CA 0] Center 36 (8~64) winsize 57
6345 14:44:10.469950 [CA 1] Center 36 (8~64) winsize 57
6346 14:44:10.473239 [CA 2] Center 36 (8~64) winsize 57
6347 14:44:10.476646 [CA 3] Center 36 (8~64) winsize 57
6348 14:44:10.477215 [CA 4] Center 36 (8~64) winsize 57
6349 14:44:10.479588 [CA 5] Center 36 (8~64) winsize 57
6350 14:44:10.480024
6351 14:44:10.486297 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6352 14:44:10.486782
6353 14:44:10.489419 [CATrainingPosCal] consider 2 rank data
6354 14:44:10.492947 u2DelayCellTimex100 = 270/100 ps
6355 14:44:10.496192 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 14:44:10.499300 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 14:44:10.502907 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 14:44:10.506358 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 14:44:10.509284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 14:44:10.512531 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 14:44:10.512949
6362 14:44:10.515931 CA PerBit enable=1, Macro0, CA PI delay=36
6363 14:44:10.516366
6364 14:44:10.518946 [CBTSetCACLKResult] CA Dly = 36
6365 14:44:10.522800 CS Dly: 1 (0~32)
6366 14:44:10.523333
6367 14:44:10.525579 ----->DramcWriteLeveling(PI) begin...
6368 14:44:10.526136 ==
6369 14:44:10.529170 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 14:44:10.532279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 14:44:10.532697 ==
6372 14:44:10.536090 Write leveling (Byte 0): 40 => 8
6373 14:44:10.538705 Write leveling (Byte 1): 32 => 0
6374 14:44:10.542082 DramcWriteLeveling(PI) end<-----
6375 14:44:10.542401
6376 14:44:10.542632 ==
6377 14:44:10.545819 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 14:44:10.549054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 14:44:10.549351 ==
6380 14:44:10.552272 [Gating] SW mode calibration
6381 14:44:10.558398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6382 14:44:10.565260 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6383 14:44:10.568248 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6384 14:44:10.574761 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6385 14:44:10.578134 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6386 14:44:10.581438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6387 14:44:10.588306 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 14:44:10.591444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 14:44:10.594812 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6390 14:44:10.601417 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 14:44:10.604342 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6392 14:44:10.607677 Total UI for P1: 0, mck2ui 16
6393 14:44:10.611037 best dqsien dly found for B0: ( 0, 14, 24)
6394 14:44:10.614390 Total UI for P1: 0, mck2ui 16
6395 14:44:10.617677 best dqsien dly found for B1: ( 0, 14, 24)
6396 14:44:10.621195 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6397 14:44:10.624462 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6398 14:44:10.624899
6399 14:44:10.627716 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6400 14:44:10.633945 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6401 14:44:10.634351 [Gating] SW calibration Done
6402 14:44:10.634701 ==
6403 14:44:10.637353 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 14:44:10.644105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 14:44:10.644562 ==
6406 14:44:10.644905 RX Vref Scan: 0
6407 14:44:10.645223
6408 14:44:10.647550 RX Vref 0 -> 0, step: 1
6409 14:44:10.648017
6410 14:44:10.650610 RX Delay -410 -> 252, step: 16
6411 14:44:10.654102 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6412 14:44:10.657732 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6413 14:44:10.664388 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6414 14:44:10.667242 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6415 14:44:10.670723 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6416 14:44:10.674114 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6417 14:44:10.680427 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6418 14:44:10.683768 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6419 14:44:10.686734 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6420 14:44:10.690348 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6421 14:44:10.697066 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6422 14:44:10.700607 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6423 14:44:10.703238 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6424 14:44:10.710465 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6425 14:44:10.713126 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6426 14:44:10.716321 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6427 14:44:10.716735 ==
6428 14:44:10.719605 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 14:44:10.722982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 14:44:10.726483 ==
6431 14:44:10.727032 DQS Delay:
6432 14:44:10.727374 DQS0 = 43, DQS1 = 59
6433 14:44:10.729730 DQM Delay:
6434 14:44:10.730146 DQM0 = 10, DQM1 = 11
6435 14:44:10.733128 DQ Delay:
6436 14:44:10.733543 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6437 14:44:10.736571 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6438 14:44:10.739322 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6439 14:44:10.742864 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6440 14:44:10.743280
6441 14:44:10.743644
6442 14:44:10.746277 ==
6443 14:44:10.749532 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 14:44:10.752673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 14:44:10.753115 ==
6446 14:44:10.753544
6447 14:44:10.753863
6448 14:44:10.756111 TX Vref Scan disable
6449 14:44:10.756523 == TX Byte 0 ==
6450 14:44:10.759731 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6451 14:44:10.765987 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6452 14:44:10.766468 == TX Byte 1 ==
6453 14:44:10.769170 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6454 14:44:10.775608 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6455 14:44:10.776033 ==
6456 14:44:10.778999 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 14:44:10.782201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 14:44:10.782627 ==
6459 14:44:10.782957
6460 14:44:10.783263
6461 14:44:10.785470 TX Vref Scan disable
6462 14:44:10.785955 == TX Byte 0 ==
6463 14:44:10.792135 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6464 14:44:10.795451 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6465 14:44:10.795872 == TX Byte 1 ==
6466 14:44:10.802207 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6467 14:44:10.805498 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6468 14:44:10.805916
6469 14:44:10.806290 [DATLAT]
6470 14:44:10.808745 Freq=400, CH0 RK0
6471 14:44:10.809161
6472 14:44:10.809488 DATLAT Default: 0xf
6473 14:44:10.811955 0, 0xFFFF, sum = 0
6474 14:44:10.812382 1, 0xFFFF, sum = 0
6475 14:44:10.815135 2, 0xFFFF, sum = 0
6476 14:44:10.815557 3, 0xFFFF, sum = 0
6477 14:44:10.818680 4, 0xFFFF, sum = 0
6478 14:44:10.819105 5, 0xFFFF, sum = 0
6479 14:44:10.822331 6, 0xFFFF, sum = 0
6480 14:44:10.822758 7, 0xFFFF, sum = 0
6481 14:44:10.825486 8, 0xFFFF, sum = 0
6482 14:44:10.825912 9, 0xFFFF, sum = 0
6483 14:44:10.828706 10, 0xFFFF, sum = 0
6484 14:44:10.831791 11, 0xFFFF, sum = 0
6485 14:44:10.832218 12, 0xFFFF, sum = 0
6486 14:44:10.835503 13, 0x0, sum = 1
6487 14:44:10.835929 14, 0x0, sum = 2
6488 14:44:10.838605 15, 0x0, sum = 3
6489 14:44:10.839030 16, 0x0, sum = 4
6490 14:44:10.839366 best_step = 14
6491 14:44:10.839698
6492 14:44:10.841967 ==
6493 14:44:10.845330 Dram Type= 6, Freq= 0, CH_0, rank 0
6494 14:44:10.848399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 14:44:10.848821 ==
6496 14:44:10.849150 RX Vref Scan: 1
6497 14:44:10.849458
6498 14:44:10.851816 RX Vref 0 -> 0, step: 1
6499 14:44:10.852233
6500 14:44:10.854920 RX Delay -359 -> 252, step: 8
6501 14:44:10.855337
6502 14:44:10.858446 Set Vref, RX VrefLevel [Byte0]: 59
6503 14:44:10.861537 [Byte1]: 58
6504 14:44:10.865166
6505 14:44:10.865584 Final RX Vref Byte 0 = 59 to rank0
6506 14:44:10.868390 Final RX Vref Byte 1 = 58 to rank0
6507 14:44:10.872005 Final RX Vref Byte 0 = 59 to rank1
6508 14:44:10.875195 Final RX Vref Byte 1 = 58 to rank1==
6509 14:44:10.878780 Dram Type= 6, Freq= 0, CH_0, rank 0
6510 14:44:10.885447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 14:44:10.885871 ==
6512 14:44:10.886249 DQS Delay:
6513 14:44:10.888429 DQS0 = 48, DQS1 = 60
6514 14:44:10.888845 DQM Delay:
6515 14:44:10.889177 DQM0 = 11, DQM1 = 11
6516 14:44:10.891663 DQ Delay:
6517 14:44:10.894871 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6518 14:44:10.898445 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6519 14:44:10.899139 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6520 14:44:10.904948 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6521 14:44:10.905587
6522 14:44:10.906120
6523 14:44:10.911487 [DQSOSCAuto] RK0, (LSB)MR18= 0xbc80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6524 14:44:10.914961 CH0 RK0: MR19=C0C, MR18=BC80
6525 14:44:10.921614 CH0_RK0: MR19=0xC0C, MR18=0xBC80, DQSOSC=386, MR23=63, INC=396, DEC=264
6526 14:44:10.921967 ==
6527 14:44:10.924287 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 14:44:10.927786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 14:44:10.927986 ==
6530 14:44:10.930965 [Gating] SW mode calibration
6531 14:44:10.937512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6532 14:44:10.944393 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6533 14:44:10.947603 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6534 14:44:10.950954 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6535 14:44:10.957144 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6536 14:44:10.960896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6537 14:44:10.964284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 14:44:10.970263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 14:44:10.974102 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6540 14:44:10.977355 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6541 14:44:10.983591 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6542 14:44:10.987003 Total UI for P1: 0, mck2ui 16
6543 14:44:10.990728 best dqsien dly found for B0: ( 0, 14, 24)
6544 14:44:10.990822 Total UI for P1: 0, mck2ui 16
6545 14:44:10.996758 best dqsien dly found for B1: ( 0, 14, 24)
6546 14:44:11.000360 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6547 14:44:11.003724 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6548 14:44:11.003842
6549 14:44:11.006886 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6550 14:44:11.010082 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6551 14:44:11.013659 [Gating] SW calibration Done
6552 14:44:11.013801 ==
6553 14:44:11.017005 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 14:44:11.020107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 14:44:11.020267 ==
6556 14:44:11.023686 RX Vref Scan: 0
6557 14:44:11.023868
6558 14:44:11.027045 RX Vref 0 -> 0, step: 1
6559 14:44:11.027227
6560 14:44:11.027370 RX Delay -410 -> 252, step: 16
6561 14:44:11.033546 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6562 14:44:11.036637 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6563 14:44:11.040103 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6564 14:44:11.047060 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6565 14:44:11.050407 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6566 14:44:11.053515 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6567 14:44:11.056588 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6568 14:44:11.063285 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6569 14:44:11.066541 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6570 14:44:11.069510 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6571 14:44:11.073147 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6572 14:44:11.079947 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6573 14:44:11.083082 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6574 14:44:11.086339 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6575 14:44:11.089092 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6576 14:44:11.095845 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6577 14:44:11.096101 ==
6578 14:44:11.099000 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 14:44:11.102442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 14:44:11.102641 ==
6581 14:44:11.102811 DQS Delay:
6582 14:44:11.106138 DQS0 = 43, DQS1 = 59
6583 14:44:11.106323 DQM Delay:
6584 14:44:11.108881 DQM0 = 10, DQM1 = 13
6585 14:44:11.109034 DQ Delay:
6586 14:44:11.112098 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6587 14:44:11.115479 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6588 14:44:11.118909 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6589 14:44:11.122197 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6590 14:44:11.122289
6591 14:44:11.122361
6592 14:44:11.122428 ==
6593 14:44:11.125276 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 14:44:11.128758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 14:44:11.128842 ==
6596 14:44:11.132123
6597 14:44:11.132206
6598 14:44:11.132272 TX Vref Scan disable
6599 14:44:11.135254 == TX Byte 0 ==
6600 14:44:11.138838 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6601 14:44:11.142144 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6602 14:44:11.145472 == TX Byte 1 ==
6603 14:44:11.148737 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6604 14:44:11.151987 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6605 14:44:11.152070 ==
6606 14:44:11.155039 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 14:44:11.158517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 14:44:11.162183 ==
6609 14:44:11.162279
6610 14:44:11.162354
6611 14:44:11.162423 TX Vref Scan disable
6612 14:44:11.165198 == TX Byte 0 ==
6613 14:44:11.168582 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6614 14:44:11.171613 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6615 14:44:11.174892 == TX Byte 1 ==
6616 14:44:11.178703 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6617 14:44:11.181662 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6618 14:44:11.181801
6619 14:44:11.185165 [DATLAT]
6620 14:44:11.185322 Freq=400, CH0 RK1
6621 14:44:11.185447
6622 14:44:11.188158 DATLAT Default: 0xe
6623 14:44:11.188339 0, 0xFFFF, sum = 0
6624 14:44:11.191527 1, 0xFFFF, sum = 0
6625 14:44:11.191710 2, 0xFFFF, sum = 0
6626 14:44:11.195517 3, 0xFFFF, sum = 0
6627 14:44:11.195733 4, 0xFFFF, sum = 0
6628 14:44:11.198194 5, 0xFFFF, sum = 0
6629 14:44:11.198456 6, 0xFFFF, sum = 0
6630 14:44:11.201698 7, 0xFFFF, sum = 0
6631 14:44:11.201956 8, 0xFFFF, sum = 0
6632 14:44:11.205198 9, 0xFFFF, sum = 0
6633 14:44:11.205526 10, 0xFFFF, sum = 0
6634 14:44:11.208343 11, 0xFFFF, sum = 0
6635 14:44:11.208767 12, 0xFFFF, sum = 0
6636 14:44:11.211813 13, 0x0, sum = 1
6637 14:44:11.212241 14, 0x0, sum = 2
6638 14:44:11.215435 15, 0x0, sum = 3
6639 14:44:11.215916 16, 0x0, sum = 4
6640 14:44:11.218778 best_step = 14
6641 14:44:11.219195
6642 14:44:11.219527 ==
6643 14:44:11.222085 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 14:44:11.225040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 14:44:11.225461 ==
6646 14:44:11.228667 RX Vref Scan: 0
6647 14:44:11.229084
6648 14:44:11.229419 RX Vref 0 -> 0, step: 1
6649 14:44:11.229732
6650 14:44:11.231573 RX Delay -359 -> 252, step: 8
6651 14:44:11.239875 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6652 14:44:11.243567 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6653 14:44:11.246568 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6654 14:44:11.249698 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6655 14:44:11.256328 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6656 14:44:11.259630 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6657 14:44:11.262866 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6658 14:44:11.269236 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6659 14:44:11.272810 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6660 14:44:11.276252 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6661 14:44:11.279725 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6662 14:44:11.286462 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6663 14:44:11.289210 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6664 14:44:11.292454 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6665 14:44:11.296004 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6666 14:44:11.302729 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6667 14:44:11.303150 ==
6668 14:44:11.305771 Dram Type= 6, Freq= 0, CH_0, rank 1
6669 14:44:11.309112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 14:44:11.309534 ==
6671 14:44:11.309866 DQS Delay:
6672 14:44:11.312340 DQS0 = 44, DQS1 = 60
6673 14:44:11.312758 DQM Delay:
6674 14:44:11.315685 DQM0 = 7, DQM1 = 14
6675 14:44:11.316103 DQ Delay:
6676 14:44:11.318849 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6677 14:44:11.322766 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6678 14:44:11.326025 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6679 14:44:11.329370 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6680 14:44:11.329787
6681 14:44:11.330116
6682 14:44:11.335767 [DQSOSCAuto] RK1, (LSB)MR18= 0xb340, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6683 14:44:11.338946 CH0 RK1: MR19=C0C, MR18=B340
6684 14:44:11.345361 CH0_RK1: MR19=0xC0C, MR18=0xB340, DQSOSC=387, MR23=63, INC=394, DEC=262
6685 14:44:11.348576 [RxdqsGatingPostProcess] freq 400
6686 14:44:11.355477 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6687 14:44:11.358655 best DQS0 dly(2T, 0.5T) = (0, 10)
6688 14:44:11.359314 best DQS1 dly(2T, 0.5T) = (0, 10)
6689 14:44:11.361737 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6690 14:44:11.365016 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6691 14:44:11.368325 best DQS0 dly(2T, 0.5T) = (0, 10)
6692 14:44:11.372055 best DQS1 dly(2T, 0.5T) = (0, 10)
6693 14:44:11.375080 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6694 14:44:11.378475 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6695 14:44:11.381869 Pre-setting of DQS Precalculation
6696 14:44:11.388254 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6697 14:44:11.388735 ==
6698 14:44:11.391743 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 14:44:11.394989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 14:44:11.395498 ==
6701 14:44:11.401872 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 14:44:11.408107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6703 14:44:11.411367 [CA 0] Center 36 (8~64) winsize 57
6704 14:44:11.411784 [CA 1] Center 36 (8~64) winsize 57
6705 14:44:11.414878 [CA 2] Center 36 (8~64) winsize 57
6706 14:44:11.417543 [CA 3] Center 36 (8~64) winsize 57
6707 14:44:11.421133 [CA 4] Center 36 (8~64) winsize 57
6708 14:44:11.424235 [CA 5] Center 36 (8~64) winsize 57
6709 14:44:11.424653
6710 14:44:11.427672 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6711 14:44:11.428220
6712 14:44:11.434803 [CATrainingPosCal] consider 1 rank data
6713 14:44:11.435302 u2DelayCellTimex100 = 270/100 ps
6714 14:44:11.440772 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 14:44:11.444337 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 14:44:11.447560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 14:44:11.450728 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 14:44:11.454511 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 14:44:11.457426 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 14:44:11.458144
6721 14:44:11.460779 CA PerBit enable=1, Macro0, CA PI delay=36
6722 14:44:11.461199
6723 14:44:11.463952 [CBTSetCACLKResult] CA Dly = 36
6724 14:44:11.467001 CS Dly: 1 (0~32)
6725 14:44:11.467646 ==
6726 14:44:11.470435 Dram Type= 6, Freq= 0, CH_1, rank 1
6727 14:44:11.474138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 14:44:11.474625 ==
6729 14:44:11.481040 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6730 14:44:11.484410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6731 14:44:11.487428 [CA 0] Center 36 (8~64) winsize 57
6732 14:44:11.490938 [CA 1] Center 36 (8~64) winsize 57
6733 14:44:11.493826 [CA 2] Center 36 (8~64) winsize 57
6734 14:44:11.497170 [CA 3] Center 36 (8~64) winsize 57
6735 14:44:11.500786 [CA 4] Center 36 (8~64) winsize 57
6736 14:44:11.503679 [CA 5] Center 36 (8~64) winsize 57
6737 14:44:11.504098
6738 14:44:11.507276 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6739 14:44:11.507695
6740 14:44:11.510549 [CATrainingPosCal] consider 2 rank data
6741 14:44:11.513662 u2DelayCellTimex100 = 270/100 ps
6742 14:44:11.516949 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 14:44:11.523628 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 14:44:11.526936 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 14:44:11.529783 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 14:44:11.533435 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 14:44:11.536753 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 14:44:11.537169
6749 14:44:11.539935 CA PerBit enable=1, Macro0, CA PI delay=36
6750 14:44:11.540352
6751 14:44:11.543381 [CBTSetCACLKResult] CA Dly = 36
6752 14:44:11.543840 CS Dly: 1 (0~32)
6753 14:44:11.546519
6754 14:44:11.550118 ----->DramcWriteLeveling(PI) begin...
6755 14:44:11.550735 ==
6756 14:44:11.553498 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 14:44:11.556482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 14:44:11.556924 ==
6759 14:44:11.559869 Write leveling (Byte 0): 40 => 8
6760 14:44:11.562991 Write leveling (Byte 1): 40 => 8
6761 14:44:11.566156 DramcWriteLeveling(PI) end<-----
6762 14:44:11.566610
6763 14:44:11.566956 ==
6764 14:44:11.569807 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 14:44:11.573047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 14:44:11.573563 ==
6767 14:44:11.576316 [Gating] SW mode calibration
6768 14:44:11.583069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6769 14:44:11.589424 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6770 14:44:11.592513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6771 14:44:11.596302 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6772 14:44:11.602857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6773 14:44:11.606340 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6774 14:44:11.609136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 14:44:11.615794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 14:44:11.619242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6777 14:44:11.622427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6778 14:44:11.628983 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6779 14:44:11.629400 Total UI for P1: 0, mck2ui 16
6780 14:44:11.635512 best dqsien dly found for B0: ( 0, 14, 24)
6781 14:44:11.635972 Total UI for P1: 0, mck2ui 16
6782 14:44:11.642292 best dqsien dly found for B1: ( 0, 14, 24)
6783 14:44:11.645400 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6784 14:44:11.648370 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6785 14:44:11.648789
6786 14:44:11.651831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6787 14:44:11.655591 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6788 14:44:11.658865 [Gating] SW calibration Done
6789 14:44:11.659291 ==
6790 14:44:11.661690 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 14:44:11.665051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 14:44:11.665483 ==
6793 14:44:11.668792 RX Vref Scan: 0
6794 14:44:11.669219
6795 14:44:11.671410 RX Vref 0 -> 0, step: 1
6796 14:44:11.671941
6797 14:44:11.672495 RX Delay -410 -> 252, step: 16
6798 14:44:11.678253 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6799 14:44:11.681915 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6800 14:44:11.684881 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6801 14:44:11.688731 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6802 14:44:11.694962 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6803 14:44:11.698132 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6804 14:44:11.701316 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6805 14:44:11.704804 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6806 14:44:11.711596 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6807 14:44:11.715246 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6808 14:44:11.718384 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6809 14:44:11.724884 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6810 14:44:11.728155 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6811 14:44:11.731125 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6812 14:44:11.734486 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6813 14:44:11.741131 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6814 14:44:11.741549 ==
6815 14:44:11.744403 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 14:44:11.747752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 14:44:11.748174 ==
6818 14:44:11.748694 DQS Delay:
6819 14:44:11.750911 DQS0 = 43, DQS1 = 51
6820 14:44:11.751330 DQM Delay:
6821 14:44:11.754520 DQM0 = 12, DQM1 = 14
6822 14:44:11.754948 DQ Delay:
6823 14:44:11.757752 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6824 14:44:11.760897 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6825 14:44:11.764478 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6826 14:44:11.767214 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6827 14:44:11.767652
6828 14:44:11.767989
6829 14:44:11.768298 ==
6830 14:44:11.770836 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 14:44:11.774314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 14:44:11.774813 ==
6833 14:44:11.775157
6834 14:44:11.776980
6835 14:44:11.777395 TX Vref Scan disable
6836 14:44:11.780680 == TX Byte 0 ==
6837 14:44:11.783558 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6838 14:44:11.787457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6839 14:44:11.790352 == TX Byte 1 ==
6840 14:44:11.794363 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 14:44:11.797573 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 14:44:11.798087 ==
6843 14:44:11.800248 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 14:44:11.803400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 14:44:11.806898 ==
6846 14:44:11.807316
6847 14:44:11.807647
6848 14:44:11.807957 TX Vref Scan disable
6849 14:44:11.809912 == TX Byte 0 ==
6850 14:44:11.813679 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6851 14:44:11.816430 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6852 14:44:11.820540 == TX Byte 1 ==
6853 14:44:11.823217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 14:44:11.826491 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 14:44:11.826946
6856 14:44:11.830053 [DATLAT]
6857 14:44:11.830520 Freq=400, CH1 RK0
6858 14:44:11.830856
6859 14:44:11.833190 DATLAT Default: 0xf
6860 14:44:11.833608 0, 0xFFFF, sum = 0
6861 14:44:11.836638 1, 0xFFFF, sum = 0
6862 14:44:11.837061 2, 0xFFFF, sum = 0
6863 14:44:11.840349 3, 0xFFFF, sum = 0
6864 14:44:11.840775 4, 0xFFFF, sum = 0
6865 14:44:11.843147 5, 0xFFFF, sum = 0
6866 14:44:11.843630 6, 0xFFFF, sum = 0
6867 14:44:11.846590 7, 0xFFFF, sum = 0
6868 14:44:11.847014 8, 0xFFFF, sum = 0
6869 14:44:11.849644 9, 0xFFFF, sum = 0
6870 14:44:11.850067 10, 0xFFFF, sum = 0
6871 14:44:11.852966 11, 0xFFFF, sum = 0
6872 14:44:11.856598 12, 0xFFFF, sum = 0
6873 14:44:11.857023 13, 0x0, sum = 1
6874 14:44:11.857367 14, 0x0, sum = 2
6875 14:44:11.859392 15, 0x0, sum = 3
6876 14:44:11.859924 16, 0x0, sum = 4
6877 14:44:11.863039 best_step = 14
6878 14:44:11.863481
6879 14:44:11.863812 ==
6880 14:44:11.866428 Dram Type= 6, Freq= 0, CH_1, rank 0
6881 14:44:11.869416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 14:44:11.869833 ==
6883 14:44:11.873103 RX Vref Scan: 1
6884 14:44:11.873521
6885 14:44:11.873870 RX Vref 0 -> 0, step: 1
6886 14:44:11.876104
6887 14:44:11.876536 RX Delay -343 -> 252, step: 8
6888 14:44:11.876870
6889 14:44:11.879541 Set Vref, RX VrefLevel [Byte0]: 51
6890 14:44:11.882493 [Byte1]: 55
6891 14:44:11.887976
6892 14:44:11.888390 Final RX Vref Byte 0 = 51 to rank0
6893 14:44:11.891155 Final RX Vref Byte 1 = 55 to rank0
6894 14:44:11.894482 Final RX Vref Byte 0 = 51 to rank1
6895 14:44:11.897975 Final RX Vref Byte 1 = 55 to rank1==
6896 14:44:11.901001 Dram Type= 6, Freq= 0, CH_1, rank 0
6897 14:44:11.907580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 14:44:11.908000 ==
6899 14:44:11.908333 DQS Delay:
6900 14:44:11.910866 DQS0 = 44, DQS1 = 56
6901 14:44:11.911313 DQM Delay:
6902 14:44:11.911653 DQM0 = 7, DQM1 = 12
6903 14:44:11.914306 DQ Delay:
6904 14:44:11.917394 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6905 14:44:11.917814 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6906 14:44:11.920683 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6907 14:44:11.924062 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6908 14:44:11.924479
6909 14:44:11.927470
6910 14:44:11.934268 [DQSOSCAuto] RK0, (LSB)MR18= 0x956c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6911 14:44:11.937044 CH1 RK0: MR19=C0C, MR18=956C
6912 14:44:11.944110 CH1_RK0: MR19=0xC0C, MR18=0x956C, DQSOSC=391, MR23=63, INC=386, DEC=257
6913 14:44:11.944528 ==
6914 14:44:11.947018 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 14:44:11.950345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 14:44:11.950764 ==
6917 14:44:11.953774 [Gating] SW mode calibration
6918 14:44:11.960088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6919 14:44:11.966961 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6920 14:44:11.970024 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6921 14:44:11.973347 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6922 14:44:11.980179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6923 14:44:11.983339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6924 14:44:11.986813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 14:44:11.993300 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 14:44:11.996395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6927 14:44:11.999946 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6928 14:44:12.006301 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6929 14:44:12.006721 Total UI for P1: 0, mck2ui 16
6930 14:44:12.012784 best dqsien dly found for B0: ( 0, 14, 24)
6931 14:44:12.013207 Total UI for P1: 0, mck2ui 16
6932 14:44:12.019443 best dqsien dly found for B1: ( 0, 14, 24)
6933 14:44:12.023049 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6934 14:44:12.026022 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6935 14:44:12.026482
6936 14:44:12.029710 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6937 14:44:12.032831 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6938 14:44:12.035946 [Gating] SW calibration Done
6939 14:44:12.036365 ==
6940 14:44:12.039388 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 14:44:12.042974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 14:44:12.043442 ==
6943 14:44:12.045898 RX Vref Scan: 0
6944 14:44:12.046353
6945 14:44:12.046691 RX Vref 0 -> 0, step: 1
6946 14:44:12.049122
6947 14:44:12.049539 RX Delay -410 -> 252, step: 16
6948 14:44:12.055910 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6949 14:44:12.059171 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6950 14:44:12.062711 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6951 14:44:12.065695 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6952 14:44:12.072451 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6953 14:44:12.075493 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6954 14:44:12.078875 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6955 14:44:12.085281 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6956 14:44:12.088839 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6957 14:44:12.092021 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6958 14:44:12.095096 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6959 14:44:12.101863 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6960 14:44:12.105323 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6961 14:44:12.108730 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6962 14:44:12.111777 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6963 14:44:12.118427 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6964 14:44:12.118849 ==
6965 14:44:12.121623 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 14:44:12.125042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 14:44:12.125476 ==
6968 14:44:12.125809 DQS Delay:
6969 14:44:12.128463 DQS0 = 43, DQS1 = 59
6970 14:44:12.128883 DQM Delay:
6971 14:44:12.131543 DQM0 = 12, DQM1 = 22
6972 14:44:12.131964 DQ Delay:
6973 14:44:12.135006 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6974 14:44:12.137944 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6975 14:44:12.141456 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6976 14:44:12.144583 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6977 14:44:12.145017
6978 14:44:12.145350
6979 14:44:12.145660 ==
6980 14:44:12.148575 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 14:44:12.151161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 14:44:12.154823 ==
6983 14:44:12.155239
6984 14:44:12.155563
6985 14:44:12.155870 TX Vref Scan disable
6986 14:44:12.158065 == TX Byte 0 ==
6987 14:44:12.161412 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6988 14:44:12.164683 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6989 14:44:12.168247 == TX Byte 1 ==
6990 14:44:12.171198 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6991 14:44:12.174871 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6992 14:44:12.175544 ==
6993 14:44:12.177410 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 14:44:12.184384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 14:44:12.184491 ==
6996 14:44:12.184583
6997 14:44:12.184721
6998 14:44:12.184823 TX Vref Scan disable
6999 14:44:12.186884 == TX Byte 0 ==
7000 14:44:12.190620 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7001 14:44:12.193508 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7002 14:44:12.197132 == TX Byte 1 ==
7003 14:44:12.200213 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7004 14:44:12.203461 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7005 14:44:12.203573
7006 14:44:12.206878 [DATLAT]
7007 14:44:12.206991 Freq=400, CH1 RK1
7008 14:44:12.207091
7009 14:44:12.209999 DATLAT Default: 0xe
7010 14:44:12.210130 0, 0xFFFF, sum = 0
7011 14:44:12.213440 1, 0xFFFF, sum = 0
7012 14:44:12.213549 2, 0xFFFF, sum = 0
7013 14:44:12.216945 3, 0xFFFF, sum = 0
7014 14:44:12.217046 4, 0xFFFF, sum = 0
7015 14:44:12.220002 5, 0xFFFF, sum = 0
7016 14:44:12.220080 6, 0xFFFF, sum = 0
7017 14:44:12.223870 7, 0xFFFF, sum = 0
7018 14:44:12.223979 8, 0xFFFF, sum = 0
7019 14:44:12.227014 9, 0xFFFF, sum = 0
7020 14:44:12.227126 10, 0xFFFF, sum = 0
7021 14:44:12.229923 11, 0xFFFF, sum = 0
7022 14:44:12.233297 12, 0xFFFF, sum = 0
7023 14:44:12.233408 13, 0x0, sum = 1
7024 14:44:12.236678 14, 0x0, sum = 2
7025 14:44:12.236784 15, 0x0, sum = 3
7026 14:44:12.236877 16, 0x0, sum = 4
7027 14:44:12.240086 best_step = 14
7028 14:44:12.240168
7029 14:44:12.240231 ==
7030 14:44:12.243277 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 14:44:12.246795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 14:44:12.246878 ==
7033 14:44:12.249812 RX Vref Scan: 0
7034 14:44:12.249894
7035 14:44:12.252944 RX Vref 0 -> 0, step: 1
7036 14:44:12.253025
7037 14:44:12.253089 RX Delay -359 -> 252, step: 8
7038 14:44:12.261509 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7039 14:44:12.265130 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7040 14:44:12.268441 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7041 14:44:12.271881 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7042 14:44:12.278229 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7043 14:44:12.281417 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7044 14:44:12.284667 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7045 14:44:12.291579 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7046 14:44:12.295139 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7047 14:44:12.298064 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7048 14:44:12.301357 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7049 14:44:12.308439 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7050 14:44:12.311916 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7051 14:44:12.314913 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7052 14:44:12.318097 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7053 14:44:12.324616 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7054 14:44:12.324698 ==
7055 14:44:12.327873 Dram Type= 6, Freq= 0, CH_1, rank 1
7056 14:44:12.331326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7057 14:44:12.331408 ==
7058 14:44:12.331472 DQS Delay:
7059 14:44:12.334836 DQS0 = 44, DQS1 = 56
7060 14:44:12.334918 DQM Delay:
7061 14:44:12.337792 DQM0 = 9, DQM1 = 10
7062 14:44:12.337872 DQ Delay:
7063 14:44:12.341102 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7064 14:44:12.344955 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
7065 14:44:12.347603 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7066 14:44:12.351357 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7067 14:44:12.351442
7068 14:44:12.351506
7069 14:44:12.357842 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7070 14:44:12.361143 CH1 RK1: MR19=C0C, MR18=6B5A
7071 14:44:12.367418 CH1_RK1: MR19=0xC0C, MR18=0x6B5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7072 14:44:12.370677 [RxdqsGatingPostProcess] freq 400
7073 14:44:12.377465 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7074 14:44:12.380532 best DQS0 dly(2T, 0.5T) = (0, 10)
7075 14:44:12.380614 best DQS1 dly(2T, 0.5T) = (0, 10)
7076 14:44:12.384229 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7077 14:44:12.387208 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7078 14:44:12.390731 best DQS0 dly(2T, 0.5T) = (0, 10)
7079 14:44:12.394325 best DQS1 dly(2T, 0.5T) = (0, 10)
7080 14:44:12.397499 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7081 14:44:12.400406 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7082 14:44:12.403718 Pre-setting of DQS Precalculation
7083 14:44:12.410297 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7084 14:44:12.416753 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7085 14:44:12.423737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7086 14:44:12.423848
7087 14:44:12.423942
7088 14:44:12.426743 [Calibration Summary] 800 Mbps
7089 14:44:12.426815 CH 0, Rank 0
7090 14:44:12.430154 SW Impedance : PASS
7091 14:44:12.433825 DUTY Scan : NO K
7092 14:44:12.433895 ZQ Calibration : PASS
7093 14:44:12.437186 Jitter Meter : NO K
7094 14:44:12.440291 CBT Training : PASS
7095 14:44:12.440372 Write leveling : PASS
7096 14:44:12.443786 RX DQS gating : PASS
7097 14:44:12.446893 RX DQ/DQS(RDDQC) : PASS
7098 14:44:12.446976 TX DQ/DQS : PASS
7099 14:44:12.450025 RX DATLAT : PASS
7100 14:44:12.453606 RX DQ/DQS(Engine): PASS
7101 14:44:12.453687 TX OE : NO K
7102 14:44:12.453752 All Pass.
7103 14:44:12.456912
7104 14:44:12.456993 CH 0, Rank 1
7105 14:44:12.459728 SW Impedance : PASS
7106 14:44:12.459811 DUTY Scan : NO K
7107 14:44:12.463180 ZQ Calibration : PASS
7108 14:44:12.466767 Jitter Meter : NO K
7109 14:44:12.466869 CBT Training : PASS
7110 14:44:12.470060 Write leveling : NO K
7111 14:44:12.470158 RX DQS gating : PASS
7112 14:44:12.473078 RX DQ/DQS(RDDQC) : PASS
7113 14:44:12.476247 TX DQ/DQS : PASS
7114 14:44:12.476355 RX DATLAT : PASS
7115 14:44:12.479584 RX DQ/DQS(Engine): PASS
7116 14:44:12.482727 TX OE : NO K
7117 14:44:12.482828 All Pass.
7118 14:44:12.482916
7119 14:44:12.483011 CH 1, Rank 0
7120 14:44:12.486323 SW Impedance : PASS
7121 14:44:12.489180 DUTY Scan : NO K
7122 14:44:12.489252 ZQ Calibration : PASS
7123 14:44:12.492810 Jitter Meter : NO K
7124 14:44:12.496341 CBT Training : PASS
7125 14:44:12.496418 Write leveling : PASS
7126 14:44:12.499494 RX DQS gating : PASS
7127 14:44:12.502540 RX DQ/DQS(RDDQC) : PASS
7128 14:44:12.502621 TX DQ/DQS : PASS
7129 14:44:12.506332 RX DATLAT : PASS
7130 14:44:12.509051 RX DQ/DQS(Engine): PASS
7131 14:44:12.509161 TX OE : NO K
7132 14:44:12.512367 All Pass.
7133 14:44:12.512474
7134 14:44:12.512566 CH 1, Rank 1
7135 14:44:12.515662 SW Impedance : PASS
7136 14:44:12.515774 DUTY Scan : NO K
7137 14:44:12.519048 ZQ Calibration : PASS
7138 14:44:12.522035 Jitter Meter : NO K
7139 14:44:12.522144 CBT Training : PASS
7140 14:44:12.525668 Write leveling : NO K
7141 14:44:12.529223 RX DQS gating : PASS
7142 14:44:12.529322 RX DQ/DQS(RDDQC) : PASS
7143 14:44:12.532049 TX DQ/DQS : PASS
7144 14:44:12.535329 RX DATLAT : PASS
7145 14:44:12.535405 RX DQ/DQS(Engine): PASS
7146 14:44:12.539002 TX OE : NO K
7147 14:44:12.539077 All Pass.
7148 14:44:12.539154
7149 14:44:12.542046 DramC Write-DBI off
7150 14:44:12.545497 PER_BANK_REFRESH: Hybrid Mode
7151 14:44:12.545570 TX_TRACKING: ON
7152 14:44:12.555173 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7153 14:44:12.558428 [FAST_K] Save calibration result to emmc
7154 14:44:12.561914 dramc_set_vcore_voltage set vcore to 725000
7155 14:44:12.564916 Read voltage for 1600, 0
7156 14:44:12.564998 Vio18 = 0
7157 14:44:12.565103 Vcore = 725000
7158 14:44:12.568392 Vdram = 0
7159 14:44:12.568474 Vddq = 0
7160 14:44:12.568538 Vmddr = 0
7161 14:44:12.574843 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7162 14:44:12.578295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7163 14:44:12.581532 MEM_TYPE=3, freq_sel=13
7164 14:44:12.584947 sv_algorithm_assistance_LP4_3733
7165 14:44:12.588196 ============ PULL DRAM RESETB DOWN ============
7166 14:44:12.594725 ========== PULL DRAM RESETB DOWN end =========
7167 14:44:12.598141 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 14:44:12.601418 ===================================
7169 14:44:12.605075 LPDDR4 DRAM CONFIGURATION
7170 14:44:12.607886 ===================================
7171 14:44:12.607963 EX_ROW_EN[0] = 0x0
7172 14:44:12.611280 EX_ROW_EN[1] = 0x0
7173 14:44:12.611356 LP4Y_EN = 0x0
7174 14:44:12.614552 WORK_FSP = 0x1
7175 14:44:12.614651 WL = 0x5
7176 14:44:12.617822 RL = 0x5
7177 14:44:12.617918 BL = 0x2
7178 14:44:12.621071 RPST = 0x0
7179 14:44:12.624580 RD_PRE = 0x0
7180 14:44:12.624657 WR_PRE = 0x1
7181 14:44:12.627589 WR_PST = 0x1
7182 14:44:12.627660 DBI_WR = 0x0
7183 14:44:12.630843 DBI_RD = 0x0
7184 14:44:12.630939 OTF = 0x1
7185 14:44:12.634069 ===================================
7186 14:44:12.637922 ===================================
7187 14:44:12.641286 ANA top config
7188 14:44:12.644082 ===================================
7189 14:44:12.644167 DLL_ASYNC_EN = 0
7190 14:44:12.647576 ALL_SLAVE_EN = 0
7191 14:44:12.651302 NEW_RANK_MODE = 1
7192 14:44:12.654381 DLL_IDLE_MODE = 1
7193 14:44:12.654452 LP45_APHY_COMB_EN = 1
7194 14:44:12.657211 TX_ODT_DIS = 0
7195 14:44:12.660700 NEW_8X_MODE = 1
7196 14:44:12.663949 ===================================
7197 14:44:12.667540 ===================================
7198 14:44:12.670897 data_rate = 3200
7199 14:44:12.673865 CKR = 1
7200 14:44:12.677528 DQ_P2S_RATIO = 8
7201 14:44:12.680576 ===================================
7202 14:44:12.680660 CA_P2S_RATIO = 8
7203 14:44:12.683713 DQ_CA_OPEN = 0
7204 14:44:12.687018 DQ_SEMI_OPEN = 0
7205 14:44:12.690650 CA_SEMI_OPEN = 0
7206 14:44:12.693750 CA_FULL_RATE = 0
7207 14:44:12.697059 DQ_CKDIV4_EN = 0
7208 14:44:12.697156 CA_CKDIV4_EN = 0
7209 14:44:12.700228 CA_PREDIV_EN = 0
7210 14:44:12.703689 PH8_DLY = 12
7211 14:44:12.707023 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7212 14:44:12.710438 DQ_AAMCK_DIV = 4
7213 14:44:12.713512 CA_AAMCK_DIV = 4
7214 14:44:12.713594 CA_ADMCK_DIV = 4
7215 14:44:12.716917 DQ_TRACK_CA_EN = 0
7216 14:44:12.720121 CA_PICK = 1600
7217 14:44:12.723392 CA_MCKIO = 1600
7218 14:44:12.727135 MCKIO_SEMI = 0
7219 14:44:12.730002 PLL_FREQ = 3068
7220 14:44:12.733209 DQ_UI_PI_RATIO = 32
7221 14:44:12.736649 CA_UI_PI_RATIO = 0
7222 14:44:12.740206 ===================================
7223 14:44:12.743620 ===================================
7224 14:44:12.743702 memory_type:LPDDR4
7225 14:44:12.746663 GP_NUM : 10
7226 14:44:12.750122 SRAM_EN : 1
7227 14:44:12.750259 MD32_EN : 0
7228 14:44:12.753194 ===================================
7229 14:44:12.756459 [ANA_INIT] >>>>>>>>>>>>>>
7230 14:44:12.759879 <<<<<< [CONFIGURE PHASE]: ANA_TX
7231 14:44:12.762818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7232 14:44:12.766391 ===================================
7233 14:44:12.769513 data_rate = 3200,PCW = 0X7600
7234 14:44:12.772726 ===================================
7235 14:44:12.776150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7236 14:44:12.780089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7237 14:44:12.786434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7238 14:44:12.789201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7239 14:44:12.792757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7240 14:44:12.795958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7241 14:44:12.799689 [ANA_INIT] flow start
7242 14:44:12.802966 [ANA_INIT] PLL >>>>>>>>
7243 14:44:12.803048 [ANA_INIT] PLL <<<<<<<<
7244 14:44:12.805994 [ANA_INIT] MIDPI >>>>>>>>
7245 14:44:12.809082 [ANA_INIT] MIDPI <<<<<<<<
7246 14:44:12.812723 [ANA_INIT] DLL >>>>>>>>
7247 14:44:12.812804 [ANA_INIT] DLL <<<<<<<<
7248 14:44:12.815847 [ANA_INIT] flow end
7249 14:44:12.819026 ============ LP4 DIFF to SE enter ============
7250 14:44:12.822739 ============ LP4 DIFF to SE exit ============
7251 14:44:12.825587 [ANA_INIT] <<<<<<<<<<<<<
7252 14:44:12.829001 [Flow] Enable top DCM control >>>>>
7253 14:44:12.832302 [Flow] Enable top DCM control <<<<<
7254 14:44:12.835798 Enable DLL master slave shuffle
7255 14:44:12.842629 ==============================================================
7256 14:44:12.842710 Gating Mode config
7257 14:44:12.848662 ==============================================================
7258 14:44:12.848744 Config description:
7259 14:44:12.859021 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7260 14:44:12.865113 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7261 14:44:12.871936 SELPH_MODE 0: By rank 1: By Phase
7262 14:44:12.875135 ==============================================================
7263 14:44:12.878316 GAT_TRACK_EN = 1
7264 14:44:12.881845 RX_GATING_MODE = 2
7265 14:44:12.884956 RX_GATING_TRACK_MODE = 2
7266 14:44:12.888259 SELPH_MODE = 1
7267 14:44:12.891502 PICG_EARLY_EN = 1
7268 14:44:12.895059 VALID_LAT_VALUE = 1
7269 14:44:12.901439 ==============================================================
7270 14:44:12.904754 Enter into Gating configuration >>>>
7271 14:44:12.908166 Exit from Gating configuration <<<<
7272 14:44:12.911714 Enter into DVFS_PRE_config >>>>>
7273 14:44:12.921109 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7274 14:44:12.924567 Exit from DVFS_PRE_config <<<<<
7275 14:44:12.927868 Enter into PICG configuration >>>>
7276 14:44:12.931008 Exit from PICG configuration <<<<
7277 14:44:12.935151 [RX_INPUT] configuration >>>>>
7278 14:44:12.937800 [RX_INPUT] configuration <<<<<
7279 14:44:12.940716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7280 14:44:12.947491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7281 14:44:12.954010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 14:44:12.957922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 14:44:12.964124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7284 14:44:12.970806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7285 14:44:12.973803 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7286 14:44:12.980609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7287 14:44:12.984003 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7288 14:44:12.986861 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7289 14:44:12.990303 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7290 14:44:12.996790 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7291 14:44:13.000163 ===================================
7292 14:44:13.003518 LPDDR4 DRAM CONFIGURATION
7293 14:44:13.003601 ===================================
7294 14:44:13.007306 EX_ROW_EN[0] = 0x0
7295 14:44:13.010432 EX_ROW_EN[1] = 0x0
7296 14:44:13.010514 LP4Y_EN = 0x0
7297 14:44:13.013707 WORK_FSP = 0x1
7298 14:44:13.013788 WL = 0x5
7299 14:44:13.016604 RL = 0x5
7300 14:44:13.016685 BL = 0x2
7301 14:44:13.019818 RPST = 0x0
7302 14:44:13.019899 RD_PRE = 0x0
7303 14:44:13.023035 WR_PRE = 0x1
7304 14:44:13.023132 WR_PST = 0x1
7305 14:44:13.027049 DBI_WR = 0x0
7306 14:44:13.027129 DBI_RD = 0x0
7307 14:44:13.030264 OTF = 0x1
7308 14:44:13.033123 ===================================
7309 14:44:13.036359 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7310 14:44:13.039767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7311 14:44:13.046635 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7312 14:44:13.049852 ===================================
7313 14:44:13.049933 LPDDR4 DRAM CONFIGURATION
7314 14:44:13.053134 ===================================
7315 14:44:13.056375 EX_ROW_EN[0] = 0x10
7316 14:44:13.059474 EX_ROW_EN[1] = 0x0
7317 14:44:13.059598 LP4Y_EN = 0x0
7318 14:44:13.063034 WORK_FSP = 0x1
7319 14:44:13.063115 WL = 0x5
7320 14:44:13.066688 RL = 0x5
7321 14:44:13.066769 BL = 0x2
7322 14:44:13.069842 RPST = 0x0
7323 14:44:13.069923 RD_PRE = 0x0
7324 14:44:13.072905 WR_PRE = 0x1
7325 14:44:13.072986 WR_PST = 0x1
7326 14:44:13.076286 DBI_WR = 0x0
7327 14:44:13.076381 DBI_RD = 0x0
7328 14:44:13.079287 OTF = 0x1
7329 14:44:13.083058 ===================================
7330 14:44:13.089445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7331 14:44:13.089528 ==
7332 14:44:13.092343 Dram Type= 6, Freq= 0, CH_0, rank 0
7333 14:44:13.095753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 14:44:13.095841 ==
7335 14:44:13.099132 [Duty_Offset_Calibration]
7336 14:44:13.099214 B0:1 B1:-1 CA:0
7337 14:44:13.099280
7338 14:44:13.102414 [DutyScan_Calibration_Flow] k_type=0
7339 14:44:13.114130
7340 14:44:13.114229 ==CLK 0==
7341 14:44:13.117253 Final CLK duty delay cell = 0
7342 14:44:13.120248 [0] MAX Duty = 5093%(X100), DQS PI = 18
7343 14:44:13.123869 [0] MIN Duty = 4875%(X100), DQS PI = 10
7344 14:44:13.126994 [0] AVG Duty = 4984%(X100)
7345 14:44:13.127077
7346 14:44:13.130359 CH0 CLK Duty spec in!! Max-Min= 218%
7347 14:44:13.133506 [DutyScan_Calibration_Flow] ====Done====
7348 14:44:13.133589
7349 14:44:13.136575 [DutyScan_Calibration_Flow] k_type=1
7350 14:44:13.153418
7351 14:44:13.153504 ==DQS 0 ==
7352 14:44:13.156010 Final DQS duty delay cell = -4
7353 14:44:13.159516 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7354 14:44:13.162827 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7355 14:44:13.165955 [-4] AVG Duty = 4906%(X100)
7356 14:44:13.166038
7357 14:44:13.166103 ==DQS 1 ==
7358 14:44:13.169244 Final DQS duty delay cell = 0
7359 14:44:13.173138 [0] MAX Duty = 5156%(X100), DQS PI = 2
7360 14:44:13.176204 [0] MIN Duty = 5000%(X100), DQS PI = 18
7361 14:44:13.179207 [0] AVG Duty = 5078%(X100)
7362 14:44:13.179311
7363 14:44:13.182832 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7364 14:44:13.182952
7365 14:44:13.185833 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7366 14:44:13.189593 [DutyScan_Calibration_Flow] ====Done====
7367 14:44:13.189679
7368 14:44:13.192436 [DutyScan_Calibration_Flow] k_type=3
7369 14:44:13.210416
7370 14:44:13.210506 ==DQM 0 ==
7371 14:44:13.214095 Final DQM duty delay cell = 0
7372 14:44:13.216851 [0] MAX Duty = 5093%(X100), DQS PI = 18
7373 14:44:13.220303 [0] MIN Duty = 4875%(X100), DQS PI = 10
7374 14:44:13.223495 [0] AVG Duty = 4984%(X100)
7375 14:44:13.223602
7376 14:44:13.223695 ==DQM 1 ==
7377 14:44:13.227053 Final DQM duty delay cell = 0
7378 14:44:13.230506 [0] MAX Duty = 5000%(X100), DQS PI = 4
7379 14:44:13.233884 [0] MIN Duty = 4782%(X100), DQS PI = 22
7380 14:44:13.236926 [0] AVG Duty = 4891%(X100)
7381 14:44:13.237008
7382 14:44:13.240279 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7383 14:44:13.240360
7384 14:44:13.243733 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7385 14:44:13.247213 [DutyScan_Calibration_Flow] ====Done====
7386 14:44:13.247294
7387 14:44:13.249873 [DutyScan_Calibration_Flow] k_type=2
7388 14:44:13.267074
7389 14:44:13.267157 ==DQ 0 ==
7390 14:44:13.269925 Final DQ duty delay cell = -4
7391 14:44:13.273547 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7392 14:44:13.276754 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7393 14:44:13.280203 [-4] AVG Duty = 4953%(X100)
7394 14:44:13.280286
7395 14:44:13.280353 ==DQ 1 ==
7396 14:44:13.283433 Final DQ duty delay cell = 0
7397 14:44:13.286934 [0] MAX Duty = 5125%(X100), DQS PI = 4
7398 14:44:13.290369 [0] MIN Duty = 5000%(X100), DQS PI = 36
7399 14:44:13.293496 [0] AVG Duty = 5062%(X100)
7400 14:44:13.293570
7401 14:44:13.296793 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7402 14:44:13.296876
7403 14:44:13.299951 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7404 14:44:13.302834 [DutyScan_Calibration_Flow] ====Done====
7405 14:44:13.302911 ==
7406 14:44:13.306638 Dram Type= 6, Freq= 0, CH_1, rank 0
7407 14:44:13.309904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7408 14:44:13.309976 ==
7409 14:44:13.312731 [Duty_Offset_Calibration]
7410 14:44:13.312802 B0:-1 B1:1 CA:2
7411 14:44:13.315829
7412 14:44:13.319131 [DutyScan_Calibration_Flow] k_type=0
7413 14:44:13.327769
7414 14:44:13.327860 ==CLK 0==
7415 14:44:13.330670 Final CLK duty delay cell = 0
7416 14:44:13.334291 [0] MAX Duty = 5187%(X100), DQS PI = 22
7417 14:44:13.337112 [0] MIN Duty = 4969%(X100), DQS PI = 0
7418 14:44:13.337207 [0] AVG Duty = 5078%(X100)
7419 14:44:13.340735
7420 14:44:13.343707 CH1 CLK Duty spec in!! Max-Min= 218%
7421 14:44:13.347220 [DutyScan_Calibration_Flow] ====Done====
7422 14:44:13.347295
7423 14:44:13.351003 [DutyScan_Calibration_Flow] k_type=1
7424 14:44:13.367017
7425 14:44:13.367104 ==DQS 0 ==
7426 14:44:13.370462 Final DQS duty delay cell = 0
7427 14:44:13.373740 [0] MAX Duty = 5124%(X100), DQS PI = 18
7428 14:44:13.376895 [0] MIN Duty = 4907%(X100), DQS PI = 8
7429 14:44:13.380290 [0] AVG Duty = 5015%(X100)
7430 14:44:13.380373
7431 14:44:13.380462 ==DQS 1 ==
7432 14:44:13.383254 Final DQS duty delay cell = 0
7433 14:44:13.386632 [0] MAX Duty = 5093%(X100), DQS PI = 26
7434 14:44:13.390016 [0] MIN Duty = 4938%(X100), DQS PI = 56
7435 14:44:13.393606 [0] AVG Duty = 5015%(X100)
7436 14:44:13.393689
7437 14:44:13.396548 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7438 14:44:13.396629
7439 14:44:13.399831 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7440 14:44:13.402916 [DutyScan_Calibration_Flow] ====Done====
7441 14:44:13.402996
7442 14:44:13.406244 [DutyScan_Calibration_Flow] k_type=3
7443 14:44:13.423797
7444 14:44:13.423880 ==DQM 0 ==
7445 14:44:13.427079 Final DQM duty delay cell = 0
7446 14:44:13.430288 [0] MAX Duty = 5218%(X100), DQS PI = 18
7447 14:44:13.433661 [0] MIN Duty = 5031%(X100), DQS PI = 6
7448 14:44:13.436803 [0] AVG Duty = 5124%(X100)
7449 14:44:13.436882
7450 14:44:13.436948 ==DQM 1 ==
7451 14:44:13.440521 Final DQM duty delay cell = 0
7452 14:44:13.443732 [0] MAX Duty = 5156%(X100), DQS PI = 2
7453 14:44:13.447259 [0] MIN Duty = 4969%(X100), DQS PI = 28
7454 14:44:13.450028 [0] AVG Duty = 5062%(X100)
7455 14:44:13.450104
7456 14:44:13.454041 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7457 14:44:13.454127
7458 14:44:13.457088 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7459 14:44:13.460331 [DutyScan_Calibration_Flow] ====Done====
7460 14:44:13.460406
7461 14:44:13.463379 [DutyScan_Calibration_Flow] k_type=2
7462 14:44:13.480498
7463 14:44:13.480587 ==DQ 0 ==
7464 14:44:13.483928 Final DQ duty delay cell = 0
7465 14:44:13.487397 [0] MAX Duty = 5187%(X100), DQS PI = 32
7466 14:44:13.490600 [0] MIN Duty = 4906%(X100), DQS PI = 8
7467 14:44:13.490671 [0] AVG Duty = 5046%(X100)
7468 14:44:13.493998
7469 14:44:13.494072 ==DQ 1 ==
7470 14:44:13.496924 Final DQ duty delay cell = 0
7471 14:44:13.500442 [0] MAX Duty = 5156%(X100), DQS PI = 8
7472 14:44:13.503851 [0] MIN Duty = 4969%(X100), DQS PI = 56
7473 14:44:13.503929 [0] AVG Duty = 5062%(X100)
7474 14:44:13.506956
7475 14:44:13.510189 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7476 14:44:13.510276
7477 14:44:13.513435 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7478 14:44:13.517422 [DutyScan_Calibration_Flow] ====Done====
7479 14:44:13.519969 nWR fixed to 30
7480 14:44:13.520045 [ModeRegInit_LP4] CH0 RK0
7481 14:44:13.523398 [ModeRegInit_LP4] CH0 RK1
7482 14:44:13.526697 [ModeRegInit_LP4] CH1 RK0
7483 14:44:13.530140 [ModeRegInit_LP4] CH1 RK1
7484 14:44:13.530261 match AC timing 5
7485 14:44:13.536977 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7486 14:44:13.540141 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7487 14:44:13.543510 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7488 14:44:13.550137 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7489 14:44:13.553560 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7490 14:44:13.553632 [MiockJmeterHQA]
7491 14:44:13.553694
7492 14:44:13.556813 [DramcMiockJmeter] u1RxGatingPI = 0
7493 14:44:13.559652 0 : 4253, 4026
7494 14:44:13.559725 4 : 4252, 4027
7495 14:44:13.563072 8 : 4255, 4029
7496 14:44:13.563172 12 : 4252, 4027
7497 14:44:13.566559 16 : 4252, 4027
7498 14:44:13.566647 20 : 4253, 4026
7499 14:44:13.566724 24 : 4252, 4027
7500 14:44:13.569669 28 : 4363, 4137
7501 14:44:13.569752 32 : 4253, 4027
7502 14:44:13.573238 36 : 4253, 4026
7503 14:44:13.573337 40 : 4255, 4029
7504 14:44:13.576063 44 : 4252, 4027
7505 14:44:13.576146 48 : 4253, 4026
7506 14:44:13.579480 52 : 4363, 4140
7507 14:44:13.579563 56 : 4360, 4137
7508 14:44:13.579629 60 : 4250, 4027
7509 14:44:13.583100 64 : 4250, 4027
7510 14:44:13.583184 68 : 4250, 4026
7511 14:44:13.585986 72 : 4250, 4027
7512 14:44:13.586096 76 : 4250, 4027
7513 14:44:13.589229 80 : 4361, 4137
7514 14:44:13.589323 84 : 4250, 4027
7515 14:44:13.592642 88 : 4250, 4026
7516 14:44:13.592729 92 : 4250, 955
7517 14:44:13.592795 96 : 4363, 0
7518 14:44:13.595699 100 : 4250, 0
7519 14:44:13.595783 104 : 4250, 0
7520 14:44:13.599063 108 : 4250, 0
7521 14:44:13.599146 112 : 4255, 0
7522 14:44:13.599220 116 : 4360, 0
7523 14:44:13.602556 120 : 4250, 0
7524 14:44:13.602640 124 : 4250, 0
7525 14:44:13.605490 128 : 4250, 0
7526 14:44:13.605572 132 : 4361, 0
7527 14:44:13.605638 136 : 4360, 0
7528 14:44:13.608669 140 : 4250, 0
7529 14:44:13.608765 144 : 4250, 0
7530 14:44:13.608862 148 : 4250, 0
7531 14:44:13.612476 152 : 4250, 0
7532 14:44:13.612559 156 : 4250, 0
7533 14:44:13.615722 160 : 4250, 0
7534 14:44:13.615805 164 : 4249, 0
7535 14:44:13.615870 168 : 4360, 0
7536 14:44:13.619020 172 : 4250, 0
7537 14:44:13.619103 176 : 4360, 0
7538 14:44:13.622180 180 : 4250, 0
7539 14:44:13.622316 184 : 4360, 0
7540 14:44:13.622428 188 : 4361, 0
7541 14:44:13.625252 192 : 4250, 0
7542 14:44:13.625335 196 : 4250, 0
7543 14:44:13.628558 200 : 4250, 0
7544 14:44:13.628641 204 : 4250, 0
7545 14:44:13.628707 208 : 4250, 0
7546 14:44:13.632095 212 : 4250, 0
7547 14:44:13.632178 216 : 4250, 0
7548 14:44:13.635650 220 : 4360, 0
7549 14:44:13.635733 224 : 4250, 59
7550 14:44:13.635840 228 : 4250, 3337
7551 14:44:13.638580 232 : 4361, 4137
7552 14:44:13.638663 236 : 4361, 4138
7553 14:44:13.642165 240 : 4250, 4026
7554 14:44:13.642249 244 : 4250, 4027
7555 14:44:13.645398 248 : 4360, 4137
7556 14:44:13.645481 252 : 4250, 4026
7557 14:44:13.648979 256 : 4250, 4027
7558 14:44:13.649062 260 : 4250, 4027
7559 14:44:13.651729 264 : 4250, 4027
7560 14:44:13.651813 268 : 4250, 4026
7561 14:44:13.655444 272 : 4250, 4027
7562 14:44:13.655526 276 : 4360, 4138
7563 14:44:13.658595 280 : 4250, 4027
7564 14:44:13.658679 284 : 4250, 4026
7565 14:44:13.658745 288 : 4361, 4137
7566 14:44:13.661612 292 : 4250, 4027
7567 14:44:13.661694 296 : 4250, 4027
7568 14:44:13.665191 300 : 4361, 4137
7569 14:44:13.665307 304 : 4250, 4026
7570 14:44:13.668556 308 : 4250, 4027
7571 14:44:13.668640 312 : 4250, 4027
7572 14:44:13.671711 316 : 4250, 4027
7573 14:44:13.671805 320 : 4250, 4026
7574 14:44:13.674802 324 : 4250, 4027
7575 14:44:13.674886 328 : 4360, 4138
7576 14:44:13.677904 332 : 4250, 4027
7577 14:44:13.678029 336 : 4250, 3796
7578 14:44:13.682040 340 : 4361, 2073
7579 14:44:13.682125
7580 14:44:13.682239 MIOCK jitter meter ch=0
7581 14:44:13.682301
7582 14:44:13.684680 1T = (340-92) = 248 dly cells
7583 14:44:13.691886 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7584 14:44:13.691965 ==
7585 14:44:13.694634 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 14:44:13.698065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 14:44:13.698150 ==
7588 14:44:13.704749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7589 14:44:13.707842 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7590 14:44:13.711441 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7591 14:44:13.717751 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7592 14:44:13.727432 [CA 0] Center 43 (13~74) winsize 62
7593 14:44:13.730746 [CA 1] Center 42 (12~73) winsize 62
7594 14:44:13.734958 [CA 2] Center 38 (9~68) winsize 60
7595 14:44:13.737597 [CA 3] Center 38 (8~68) winsize 61
7596 14:44:13.740653 [CA 4] Center 36 (7~66) winsize 60
7597 14:44:13.744618 [CA 5] Center 35 (6~65) winsize 60
7598 14:44:13.744703
7599 14:44:13.747215 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7600 14:44:13.747296
7601 14:44:13.750917 [CATrainingPosCal] consider 1 rank data
7602 14:44:13.753902 u2DelayCellTimex100 = 262/100 ps
7603 14:44:13.757564 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7604 14:44:13.763958 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7605 14:44:13.767161 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7606 14:44:13.770744 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7607 14:44:13.773957 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7608 14:44:13.776913 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7609 14:44:13.776992
7610 14:44:13.780484 CA PerBit enable=1, Macro0, CA PI delay=35
7611 14:44:13.780566
7612 14:44:13.783637 [CBTSetCACLKResult] CA Dly = 35
7613 14:44:13.787051 CS Dly: 11 (0~42)
7614 14:44:13.790138 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7615 14:44:13.793815 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7616 14:44:13.793898 ==
7617 14:44:13.796637 Dram Type= 6, Freq= 0, CH_0, rank 1
7618 14:44:13.803476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 14:44:13.803560 ==
7620 14:44:13.806905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7621 14:44:13.813541 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7622 14:44:13.816773 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7623 14:44:13.823247 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7624 14:44:13.831221 [CA 0] Center 43 (13~74) winsize 62
7625 14:44:13.834587 [CA 1] Center 44 (14~74) winsize 61
7626 14:44:13.838010 [CA 2] Center 38 (9~68) winsize 60
7627 14:44:13.841202 [CA 3] Center 38 (9~68) winsize 60
7628 14:44:13.844246 [CA 4] Center 36 (7~66) winsize 60
7629 14:44:13.847650 [CA 5] Center 36 (6~66) winsize 61
7630 14:44:13.847733
7631 14:44:13.850697 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7632 14:44:13.850778
7633 14:44:13.857445 [CATrainingPosCal] consider 2 rank data
7634 14:44:13.857528 u2DelayCellTimex100 = 262/100 ps
7635 14:44:13.864098 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7636 14:44:13.867335 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7637 14:44:13.870620 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7638 14:44:13.874078 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7639 14:44:13.877387 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7640 14:44:13.880593 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7641 14:44:13.880697
7642 14:44:13.883889 CA PerBit enable=1, Macro0, CA PI delay=35
7643 14:44:13.883982
7644 14:44:13.887142 [CBTSetCACLKResult] CA Dly = 35
7645 14:44:13.890756 CS Dly: 12 (0~44)
7646 14:44:13.894015 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7647 14:44:13.897236 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7648 14:44:13.897317
7649 14:44:13.900488 ----->DramcWriteLeveling(PI) begin...
7650 14:44:13.900563 ==
7651 14:44:13.903712 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 14:44:13.910231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 14:44:13.910316 ==
7654 14:44:13.913939 Write leveling (Byte 0): 35 => 35
7655 14:44:13.916999 Write leveling (Byte 1): 27 => 27
7656 14:44:13.917074 DramcWriteLeveling(PI) end<-----
7657 14:44:13.920332
7658 14:44:13.920403 ==
7659 14:44:13.923683 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 14:44:13.926756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 14:44:13.926846 ==
7662 14:44:13.930135 [Gating] SW mode calibration
7663 14:44:13.937193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7664 14:44:13.940271 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7665 14:44:13.946593 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 14:44:13.949964 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 14:44:13.956432 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 14:44:13.959854 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7669 14:44:13.963612 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7670 14:44:13.969310 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7671 14:44:13.973204 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7672 14:44:13.976403 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 14:44:13.982977 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7674 14:44:13.986644 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7675 14:44:13.989723 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7676 14:44:13.995886 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7677 14:44:13.999279 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7678 14:44:14.002366 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7679 14:44:14.009065 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7680 14:44:14.012693 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 14:44:14.016337 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 14:44:14.022268 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 14:44:14.025679 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 14:44:14.029163 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7685 14:44:14.035557 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7686 14:44:14.038644 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7687 14:44:14.041786 1 6 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7688 14:44:14.048718 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 14:44:14.052094 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 14:44:14.055193 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7691 14:44:14.062019 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 14:44:14.065434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7693 14:44:14.068601 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7694 14:44:14.074902 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7695 14:44:14.078129 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7696 14:44:14.081284 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 14:44:14.088295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 14:44:14.091232 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 14:44:14.094689 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 14:44:14.101407 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 14:44:14.104483 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 14:44:14.107800 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 14:44:14.114373 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 14:44:14.118361 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 14:44:14.121812 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 14:44:14.127651 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 14:44:14.131012 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7708 14:44:14.134077 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7709 14:44:14.140984 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7710 14:44:14.141068 Total UI for P1: 0, mck2ui 16
7711 14:44:14.147240 best dqsien dly found for B0: ( 1, 9, 10)
7712 14:44:14.150706 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7713 14:44:14.153942 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7714 14:44:14.160239 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7715 14:44:14.160318 Total UI for P1: 0, mck2ui 16
7716 14:44:14.166853 best dqsien dly found for B1: ( 1, 9, 22)
7717 14:44:14.170475 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7718 14:44:14.173703 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7719 14:44:14.173774
7720 14:44:14.176716 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7721 14:44:14.180258 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7722 14:44:14.183646 [Gating] SW calibration Done
7723 14:44:14.183751 ==
7724 14:44:14.186912 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 14:44:14.190486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 14:44:14.190568 ==
7727 14:44:14.193146 RX Vref Scan: 0
7728 14:44:14.193235
7729 14:44:14.193300 RX Vref 0 -> 0, step: 1
7730 14:44:14.196597
7731 14:44:14.196709 RX Delay 0 -> 252, step: 8
7732 14:44:14.200508 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7733 14:44:14.206429 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7734 14:44:14.209791 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7735 14:44:14.213135 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7736 14:44:14.216496 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7737 14:44:14.219808 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7738 14:44:14.226581 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7739 14:44:14.229282 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7740 14:44:14.232908 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7741 14:44:14.236368 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7742 14:44:14.242659 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7743 14:44:14.245892 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7744 14:44:14.249788 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7745 14:44:14.252340 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7746 14:44:14.255755 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7747 14:44:14.262529 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7748 14:44:14.262611 ==
7749 14:44:14.266154 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 14:44:14.269111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 14:44:14.269196 ==
7752 14:44:14.269287 DQS Delay:
7753 14:44:14.272232 DQS0 = 0, DQS1 = 0
7754 14:44:14.272308 DQM Delay:
7755 14:44:14.275669 DQM0 = 137, DQM1 = 126
7756 14:44:14.275750 DQ Delay:
7757 14:44:14.278783 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7758 14:44:14.282462 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7759 14:44:14.285330 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7760 14:44:14.288826 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7761 14:44:14.292344
7762 14:44:14.292418
7763 14:44:14.292481 ==
7764 14:44:14.295479 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 14:44:14.298586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 14:44:14.298660 ==
7767 14:44:14.298729
7768 14:44:14.298792
7769 14:44:14.302341 TX Vref Scan disable
7770 14:44:14.302412 == TX Byte 0 ==
7771 14:44:14.308620 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7772 14:44:14.312119 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7773 14:44:14.312191 == TX Byte 1 ==
7774 14:44:14.319036 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7775 14:44:14.321930 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7776 14:44:14.322012 ==
7777 14:44:14.324741 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 14:44:14.328253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 14:44:14.328336 ==
7780 14:44:14.342715
7781 14:44:14.346134 TX Vref early break, caculate TX vref
7782 14:44:14.349295 TX Vref=16, minBit 4, minWin=22, winSum=371
7783 14:44:14.353177 TX Vref=18, minBit 4, minWin=22, winSum=377
7784 14:44:14.355893 TX Vref=20, minBit 6, minWin=23, winSum=391
7785 14:44:14.359796 TX Vref=22, minBit 1, minWin=23, winSum=402
7786 14:44:14.362510 TX Vref=24, minBit 0, minWin=25, winSum=410
7787 14:44:14.369321 TX Vref=26, minBit 5, minWin=24, winSum=413
7788 14:44:14.372268 TX Vref=28, minBit 4, minWin=24, winSum=416
7789 14:44:14.375899 TX Vref=30, minBit 2, minWin=25, winSum=413
7790 14:44:14.378883 TX Vref=32, minBit 7, minWin=23, winSum=400
7791 14:44:14.382715 TX Vref=34, minBit 4, minWin=22, winSum=387
7792 14:44:14.389225 [TxChooseVref] Worse bit 2, Min win 25, Win sum 413, Final Vref 30
7793 14:44:14.389310
7794 14:44:14.392032 Final TX Range 0 Vref 30
7795 14:44:14.392141
7796 14:44:14.392243 ==
7797 14:44:14.396505 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 14:44:14.398727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 14:44:14.398811 ==
7800 14:44:14.398897
7801 14:44:14.398977
7802 14:44:14.402199 TX Vref Scan disable
7803 14:44:14.408728 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7804 14:44:14.408813 == TX Byte 0 ==
7805 14:44:14.411897 u2DelayCellOfst[0]=14 cells (4 PI)
7806 14:44:14.415085 u2DelayCellOfst[1]=18 cells (5 PI)
7807 14:44:14.418559 u2DelayCellOfst[2]=14 cells (4 PI)
7808 14:44:14.421825 u2DelayCellOfst[3]=18 cells (5 PI)
7809 14:44:14.425242 u2DelayCellOfst[4]=11 cells (3 PI)
7810 14:44:14.428729 u2DelayCellOfst[5]=0 cells (0 PI)
7811 14:44:14.431622 u2DelayCellOfst[6]=22 cells (6 PI)
7812 14:44:14.435095 u2DelayCellOfst[7]=18 cells (5 PI)
7813 14:44:14.438600 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7814 14:44:14.441541 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7815 14:44:14.444878 == TX Byte 1 ==
7816 14:44:14.448392 u2DelayCellOfst[8]=0 cells (0 PI)
7817 14:44:14.451337 u2DelayCellOfst[9]=3 cells (1 PI)
7818 14:44:14.455045 u2DelayCellOfst[10]=11 cells (3 PI)
7819 14:44:14.458661 u2DelayCellOfst[11]=3 cells (1 PI)
7820 14:44:14.461588 u2DelayCellOfst[12]=11 cells (3 PI)
7821 14:44:14.461687 u2DelayCellOfst[13]=14 cells (4 PI)
7822 14:44:14.465240 u2DelayCellOfst[14]=18 cells (5 PI)
7823 14:44:14.468122 u2DelayCellOfst[15]=11 cells (3 PI)
7824 14:44:14.474665 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7825 14:44:14.477849 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7826 14:44:14.481160 DramC Write-DBI on
7827 14:44:14.481244 ==
7828 14:44:14.484882 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 14:44:14.487715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 14:44:14.487800 ==
7831 14:44:14.487885
7832 14:44:14.487964
7833 14:44:14.490840 TX Vref Scan disable
7834 14:44:14.490924 == TX Byte 0 ==
7835 14:44:14.497690 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7836 14:44:14.497772 == TX Byte 1 ==
7837 14:44:14.501086 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7838 14:44:14.504308 DramC Write-DBI off
7839 14:44:14.504389
7840 14:44:14.504453 [DATLAT]
7841 14:44:14.507626 Freq=1600, CH0 RK0
7842 14:44:14.507708
7843 14:44:14.507774 DATLAT Default: 0xf
7844 14:44:14.510807 0, 0xFFFF, sum = 0
7845 14:44:14.510890 1, 0xFFFF, sum = 0
7846 14:44:14.513988 2, 0xFFFF, sum = 0
7847 14:44:14.517708 3, 0xFFFF, sum = 0
7848 14:44:14.517791 4, 0xFFFF, sum = 0
7849 14:44:14.520535 5, 0xFFFF, sum = 0
7850 14:44:14.520619 6, 0xFFFF, sum = 0
7851 14:44:14.523860 7, 0xFFFF, sum = 0
7852 14:44:14.523943 8, 0xFFFF, sum = 0
7853 14:44:14.527539 9, 0xFFFF, sum = 0
7854 14:44:14.527622 10, 0xFFFF, sum = 0
7855 14:44:14.530833 11, 0xFFFF, sum = 0
7856 14:44:14.530923 12, 0xFFFF, sum = 0
7857 14:44:14.534413 13, 0xFFFF, sum = 0
7858 14:44:14.534496 14, 0x0, sum = 1
7859 14:44:14.537024 15, 0x0, sum = 2
7860 14:44:14.537107 16, 0x0, sum = 3
7861 14:44:14.540567 17, 0x0, sum = 4
7862 14:44:14.540651 best_step = 15
7863 14:44:14.540715
7864 14:44:14.540775 ==
7865 14:44:14.544458 Dram Type= 6, Freq= 0, CH_0, rank 0
7866 14:44:14.550144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7867 14:44:14.550265 ==
7868 14:44:14.550331 RX Vref Scan: 1
7869 14:44:14.550391
7870 14:44:14.553527 Set Vref Range= 24 -> 127
7871 14:44:14.553609
7872 14:44:14.556974 RX Vref 24 -> 127, step: 1
7873 14:44:14.557055
7874 14:44:14.557120 RX Delay 19 -> 252, step: 4
7875 14:44:14.560030
7876 14:44:14.560111 Set Vref, RX VrefLevel [Byte0]: 24
7877 14:44:14.563516 [Byte1]: 24
7878 14:44:14.567800
7879 14:44:14.567881 Set Vref, RX VrefLevel [Byte0]: 25
7880 14:44:14.570890 [Byte1]: 25
7881 14:44:14.575254
7882 14:44:14.575335 Set Vref, RX VrefLevel [Byte0]: 26
7883 14:44:14.578865 [Byte1]: 26
7884 14:44:14.582761
7885 14:44:14.582846 Set Vref, RX VrefLevel [Byte0]: 27
7886 14:44:14.586600 [Byte1]: 27
7887 14:44:14.590771
7888 14:44:14.590868 Set Vref, RX VrefLevel [Byte0]: 28
7889 14:44:14.593682 [Byte1]: 28
7890 14:44:14.597963
7891 14:44:14.598061 Set Vref, RX VrefLevel [Byte0]: 29
7892 14:44:14.601242 [Byte1]: 29
7893 14:44:14.605698
7894 14:44:14.605782 Set Vref, RX VrefLevel [Byte0]: 30
7895 14:44:14.609058 [Byte1]: 30
7896 14:44:14.613609
7897 14:44:14.613711 Set Vref, RX VrefLevel [Byte0]: 31
7898 14:44:14.616459 [Byte1]: 31
7899 14:44:14.620713
7900 14:44:14.620849 Set Vref, RX VrefLevel [Byte0]: 32
7901 14:44:14.624571 [Byte1]: 32
7902 14:44:14.628260
7903 14:44:14.628343 Set Vref, RX VrefLevel [Byte0]: 33
7904 14:44:14.631730 [Byte1]: 33
7905 14:44:14.635721
7906 14:44:14.635805 Set Vref, RX VrefLevel [Byte0]: 34
7907 14:44:14.639660 [Byte1]: 34
7908 14:44:14.643196
7909 14:44:14.643280 Set Vref, RX VrefLevel [Byte0]: 35
7910 14:44:14.646772 [Byte1]: 35
7911 14:44:14.651291
7912 14:44:14.651372 Set Vref, RX VrefLevel [Byte0]: 36
7913 14:44:14.654004 [Byte1]: 36
7914 14:44:14.658560
7915 14:44:14.658641 Set Vref, RX VrefLevel [Byte0]: 37
7916 14:44:14.661688 [Byte1]: 37
7917 14:44:14.666021
7918 14:44:14.666102 Set Vref, RX VrefLevel [Byte0]: 38
7919 14:44:14.669416 [Byte1]: 38
7920 14:44:14.673677
7921 14:44:14.673758 Set Vref, RX VrefLevel [Byte0]: 39
7922 14:44:14.676969 [Byte1]: 39
7923 14:44:14.681580
7924 14:44:14.681661 Set Vref, RX VrefLevel [Byte0]: 40
7925 14:44:14.688101 [Byte1]: 40
7926 14:44:14.688182
7927 14:44:14.690758 Set Vref, RX VrefLevel [Byte0]: 41
7928 14:44:14.694267 [Byte1]: 41
7929 14:44:14.694348
7930 14:44:14.697519 Set Vref, RX VrefLevel [Byte0]: 42
7931 14:44:14.701535 [Byte1]: 42
7932 14:44:14.701616
7933 14:44:14.704123 Set Vref, RX VrefLevel [Byte0]: 43
7934 14:44:14.707742 [Byte1]: 43
7935 14:44:14.711815
7936 14:44:14.711891 Set Vref, RX VrefLevel [Byte0]: 44
7937 14:44:14.715296 [Byte1]: 44
7938 14:44:14.719503
7939 14:44:14.719577 Set Vref, RX VrefLevel [Byte0]: 45
7940 14:44:14.722409 [Byte1]: 45
7941 14:44:14.726552
7942 14:44:14.726633 Set Vref, RX VrefLevel [Byte0]: 46
7943 14:44:14.730016 [Byte1]: 46
7944 14:44:14.734154
7945 14:44:14.734257 Set Vref, RX VrefLevel [Byte0]: 47
7946 14:44:14.737365 [Byte1]: 47
7947 14:44:14.742413
7948 14:44:14.742493 Set Vref, RX VrefLevel [Byte0]: 48
7949 14:44:14.745355 [Byte1]: 48
7950 14:44:14.749120
7951 14:44:14.749200 Set Vref, RX VrefLevel [Byte0]: 49
7952 14:44:14.752626 [Byte1]: 49
7953 14:44:14.757003
7954 14:44:14.757083 Set Vref, RX VrefLevel [Byte0]: 50
7955 14:44:14.760302 [Byte1]: 50
7956 14:44:14.764644
7957 14:44:14.764725 Set Vref, RX VrefLevel [Byte0]: 51
7958 14:44:14.767704 [Byte1]: 51
7959 14:44:14.772206
7960 14:44:14.772318 Set Vref, RX VrefLevel [Byte0]: 52
7961 14:44:14.775565 [Byte1]: 52
7962 14:44:14.779985
7963 14:44:14.780067 Set Vref, RX VrefLevel [Byte0]: 53
7964 14:44:14.782901 [Byte1]: 53
7965 14:44:14.787227
7966 14:44:14.787301 Set Vref, RX VrefLevel [Byte0]: 54
7967 14:44:14.790478 [Byte1]: 54
7968 14:44:14.794987
7969 14:44:14.795063 Set Vref, RX VrefLevel [Byte0]: 55
7970 14:44:14.798396 [Byte1]: 55
7971 14:44:14.802662
7972 14:44:14.802737 Set Vref, RX VrefLevel [Byte0]: 56
7973 14:44:14.805901 [Byte1]: 56
7974 14:44:14.810034
7975 14:44:14.810110 Set Vref, RX VrefLevel [Byte0]: 57
7976 14:44:14.813296 [Byte1]: 57
7977 14:44:14.817512
7978 14:44:14.817596 Set Vref, RX VrefLevel [Byte0]: 58
7979 14:44:14.821145 [Byte1]: 58
7980 14:44:14.825301
7981 14:44:14.825385 Set Vref, RX VrefLevel [Byte0]: 59
7982 14:44:14.828659 [Byte1]: 59
7983 14:44:14.833097
7984 14:44:14.833193 Set Vref, RX VrefLevel [Byte0]: 60
7985 14:44:14.836304 [Byte1]: 60
7986 14:44:14.840169
7987 14:44:14.840349 Set Vref, RX VrefLevel [Byte0]: 61
7988 14:44:14.843720 [Byte1]: 61
7989 14:44:14.847996
7990 14:44:14.848077 Set Vref, RX VrefLevel [Byte0]: 62
7991 14:44:14.851336 [Byte1]: 62
7992 14:44:14.855457
7993 14:44:14.855540 Set Vref, RX VrefLevel [Byte0]: 63
7994 14:44:14.859001 [Byte1]: 63
7995 14:44:14.862768
7996 14:44:14.862849 Set Vref, RX VrefLevel [Byte0]: 64
7997 14:44:14.866491 [Byte1]: 64
7998 14:44:14.870425
7999 14:44:14.870508 Set Vref, RX VrefLevel [Byte0]: 65
8000 14:44:14.873772 [Byte1]: 65
8001 14:44:14.878267
8002 14:44:14.878343 Set Vref, RX VrefLevel [Byte0]: 66
8003 14:44:14.881592 [Byte1]: 66
8004 14:44:14.885784
8005 14:44:14.885860 Set Vref, RX VrefLevel [Byte0]: 67
8006 14:44:14.889184 [Byte1]: 67
8007 14:44:14.893416
8008 14:44:14.893492 Set Vref, RX VrefLevel [Byte0]: 68
8009 14:44:14.896698 [Byte1]: 68
8010 14:44:14.900963
8011 14:44:14.901037 Set Vref, RX VrefLevel [Byte0]: 69
8012 14:44:14.903947 [Byte1]: 69
8013 14:44:14.908680
8014 14:44:14.908755 Set Vref, RX VrefLevel [Byte0]: 70
8015 14:44:14.911582 [Byte1]: 70
8016 14:44:14.915787
8017 14:44:14.919021 Set Vref, RX VrefLevel [Byte0]: 71
8018 14:44:14.922857 [Byte1]: 71
8019 14:44:14.922935
8020 14:44:14.925616 Set Vref, RX VrefLevel [Byte0]: 72
8021 14:44:14.929219 [Byte1]: 72
8022 14:44:14.929295
8023 14:44:14.932174 Set Vref, RX VrefLevel [Byte0]: 73
8024 14:44:14.935749 [Byte1]: 73
8025 14:44:14.935830
8026 14:44:14.938855 Set Vref, RX VrefLevel [Byte0]: 74
8027 14:44:14.942311 [Byte1]: 74
8028 14:44:14.946441
8029 14:44:14.946551 Set Vref, RX VrefLevel [Byte0]: 75
8030 14:44:14.949651 [Byte1]: 75
8031 14:44:14.953632
8032 14:44:14.953749 Set Vref, RX VrefLevel [Byte0]: 76
8033 14:44:14.957109 [Byte1]: 76
8034 14:44:14.961306
8035 14:44:14.961386 Set Vref, RX VrefLevel [Byte0]: 77
8036 14:44:14.964803 [Byte1]: 77
8037 14:44:14.968831
8038 14:44:14.968912 Set Vref, RX VrefLevel [Byte0]: 78
8039 14:44:14.972450 [Byte1]: 78
8040 14:44:14.976419
8041 14:44:14.976505 Set Vref, RX VrefLevel [Byte0]: 79
8042 14:44:14.979785 [Byte1]: 79
8043 14:44:14.984195
8044 14:44:14.984277 Final RX Vref Byte 0 = 66 to rank0
8045 14:44:14.987415 Final RX Vref Byte 1 = 59 to rank0
8046 14:44:14.990973 Final RX Vref Byte 0 = 66 to rank1
8047 14:44:14.994189 Final RX Vref Byte 1 = 59 to rank1==
8048 14:44:14.997441 Dram Type= 6, Freq= 0, CH_0, rank 0
8049 14:44:15.004220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 14:44:15.004303 ==
8051 14:44:15.004367 DQS Delay:
8052 14:44:15.007523 DQS0 = 0, DQS1 = 0
8053 14:44:15.007604 DQM Delay:
8054 14:44:15.007668 DQM0 = 133, DQM1 = 122
8055 14:44:15.010539 DQ Delay:
8056 14:44:15.013610 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8057 14:44:15.017350 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8058 14:44:15.020677 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8059 14:44:15.023584 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8060 14:44:15.023658
8061 14:44:15.023720
8062 14:44:15.023778
8063 14:44:15.026832 [DramC_TX_OE_Calibration] TA2
8064 14:44:15.030040 Original DQ_B0 (3 6) =30, OEN = 27
8065 14:44:15.033471 Original DQ_B1 (3 6) =30, OEN = 27
8066 14:44:15.036807 24, 0x0, End_B0=24 End_B1=24
8067 14:44:15.040283 25, 0x0, End_B0=25 End_B1=25
8068 14:44:15.040365 26, 0x0, End_B0=26 End_B1=26
8069 14:44:15.043622 27, 0x0, End_B0=27 End_B1=27
8070 14:44:15.046957 28, 0x0, End_B0=28 End_B1=28
8071 14:44:15.050362 29, 0x0, End_B0=29 End_B1=29
8072 14:44:15.050434 30, 0x0, End_B0=30 End_B1=30
8073 14:44:15.053271 31, 0x4141, End_B0=30 End_B1=30
8074 14:44:15.056596 Byte0 end_step=30 best_step=27
8075 14:44:15.060412 Byte1 end_step=30 best_step=27
8076 14:44:15.063378 Byte0 TX OE(2T, 0.5T) = (3, 3)
8077 14:44:15.066726 Byte1 TX OE(2T, 0.5T) = (3, 3)
8078 14:44:15.066798
8079 14:44:15.066858
8080 14:44:15.073421 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8081 14:44:15.076258 CH0 RK0: MR19=303, MR18=2112
8082 14:44:15.082989 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8083 14:44:15.083072
8084 14:44:15.086348 ----->DramcWriteLeveling(PI) begin...
8085 14:44:15.086427 ==
8086 14:44:15.089716 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 14:44:15.092905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 14:44:15.092983 ==
8089 14:44:15.096410 Write leveling (Byte 0): 36 => 36
8090 14:44:15.099660 Write leveling (Byte 1): 30 => 30
8091 14:44:15.102769 DramcWriteLeveling(PI) end<-----
8092 14:44:15.102850
8093 14:44:15.102914 ==
8094 14:44:15.106186 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 14:44:15.109754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 14:44:15.112534 ==
8097 14:44:15.112615 [Gating] SW mode calibration
8098 14:44:15.122925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8099 14:44:15.125897 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8100 14:44:15.129190 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 14:44:15.135605 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 14:44:15.139537 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 14:44:15.142322 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8104 14:44:15.149188 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8105 14:44:15.152698 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8106 14:44:15.155830 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 14:44:15.162145 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 14:44:15.165251 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8109 14:44:15.168996 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8110 14:44:15.175627 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8111 14:44:15.178994 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8112 14:44:15.181578 1 5 16 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
8113 14:44:15.188457 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8114 14:44:15.191768 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 14:44:15.194742 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 14:44:15.201490 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 14:44:15.204901 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8118 14:44:15.208102 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 14:44:15.215116 1 6 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8120 14:44:15.218853 1 6 16 | B1->B0 | 2525 4444 | 0 1 | (0 0) (0 0)
8121 14:44:15.221189 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
8122 14:44:15.227903 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 14:44:15.231451 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 14:44:15.234838 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 14:44:15.241703 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 14:44:15.244464 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8127 14:44:15.248095 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 14:44:15.254476 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8129 14:44:15.257692 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8130 14:44:15.261235 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8131 14:44:15.267548 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 14:44:15.270685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 14:44:15.274106 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 14:44:15.280702 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 14:44:15.284149 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 14:44:15.287830 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 14:44:15.293771 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 14:44:15.297291 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 14:44:15.303816 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 14:44:15.307433 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 14:44:15.310426 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 14:44:15.314000 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8143 14:44:15.320529 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8144 14:44:15.323770 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8145 14:44:15.326732 Total UI for P1: 0, mck2ui 16
8146 14:44:15.330059 best dqsien dly found for B0: ( 1, 9, 10)
8147 14:44:15.333556 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 14:44:15.336786 Total UI for P1: 0, mck2ui 16
8149 14:44:15.339849 best dqsien dly found for B1: ( 1, 9, 16)
8150 14:44:15.343494 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8151 14:44:15.350254 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8152 14:44:15.350363
8153 14:44:15.353362 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8154 14:44:15.356516 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8155 14:44:15.359521 [Gating] SW calibration Done
8156 14:44:15.359629 ==
8157 14:44:15.362776 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 14:44:15.366437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 14:44:15.366546 ==
8160 14:44:15.369631 RX Vref Scan: 0
8161 14:44:15.369712
8162 14:44:15.369776 RX Vref 0 -> 0, step: 1
8163 14:44:15.369835
8164 14:44:15.372751 RX Delay 0 -> 252, step: 8
8165 14:44:15.375948 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8166 14:44:15.382911 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8167 14:44:15.386197 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8168 14:44:15.389516 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8169 14:44:15.393066 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8170 14:44:15.396064 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8171 14:44:15.402526 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8172 14:44:15.405983 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8173 14:44:15.409067 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8174 14:44:15.412484 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8175 14:44:15.415822 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8176 14:44:15.422470 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8177 14:44:15.425782 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8178 14:44:15.428665 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8179 14:44:15.432674 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8180 14:44:15.438966 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8181 14:44:15.439048 ==
8182 14:44:15.442110 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 14:44:15.445345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 14:44:15.445428 ==
8185 14:44:15.445491 DQS Delay:
8186 14:44:15.448626 DQS0 = 0, DQS1 = 0
8187 14:44:15.448707 DQM Delay:
8188 14:44:15.452113 DQM0 = 133, DQM1 = 129
8189 14:44:15.452194 DQ Delay:
8190 14:44:15.455441 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8191 14:44:15.458687 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8192 14:44:15.461768 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8193 14:44:15.465002 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8194 14:44:15.468100
8195 14:44:15.468180
8196 14:44:15.468244 ==
8197 14:44:15.471464 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 14:44:15.474803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 14:44:15.474885 ==
8200 14:44:15.474948
8201 14:44:15.475007
8202 14:44:15.478460 TX Vref Scan disable
8203 14:44:15.478541 == TX Byte 0 ==
8204 14:44:15.485178 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8205 14:44:15.488662 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8206 14:44:15.488743 == TX Byte 1 ==
8207 14:44:15.494625 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8208 14:44:15.497956 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8209 14:44:15.498035 ==
8210 14:44:15.501194 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 14:44:15.504572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 14:44:15.504651 ==
8213 14:44:15.518504
8214 14:44:15.521994 TX Vref early break, caculate TX vref
8215 14:44:15.525112 TX Vref=16, minBit 2, minWin=22, winSum=377
8216 14:44:15.528735 TX Vref=18, minBit 0, minWin=23, winSum=390
8217 14:44:15.531711 TX Vref=20, minBit 0, minWin=23, winSum=395
8218 14:44:15.535211 TX Vref=22, minBit 1, minWin=23, winSum=399
8219 14:44:15.538070 TX Vref=24, minBit 1, minWin=24, winSum=409
8220 14:44:15.544849 TX Vref=26, minBit 3, minWin=24, winSum=415
8221 14:44:15.548408 TX Vref=28, minBit 1, minWin=24, winSum=417
8222 14:44:15.551275 TX Vref=30, minBit 1, minWin=24, winSum=407
8223 14:44:15.554642 TX Vref=32, minBit 5, minWin=23, winSum=397
8224 14:44:15.557995 TX Vref=34, minBit 1, minWin=23, winSum=389
8225 14:44:15.564839 [TxChooseVref] Worse bit 1, Min win 24, Win sum 417, Final Vref 28
8226 14:44:15.564908
8227 14:44:15.567576 Final TX Range 0 Vref 28
8228 14:44:15.567649
8229 14:44:15.567709 ==
8230 14:44:15.571271 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 14:44:15.574557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 14:44:15.574639 ==
8233 14:44:15.574703
8234 14:44:15.577625
8235 14:44:15.577706 TX Vref Scan disable
8236 14:44:15.584357 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8237 14:44:15.584440 == TX Byte 0 ==
8238 14:44:15.587428 u2DelayCellOfst[0]=14 cells (4 PI)
8239 14:44:15.590866 u2DelayCellOfst[1]=18 cells (5 PI)
8240 14:44:15.594024 u2DelayCellOfst[2]=14 cells (4 PI)
8241 14:44:15.597615 u2DelayCellOfst[3]=14 cells (4 PI)
8242 14:44:15.600602 u2DelayCellOfst[4]=11 cells (3 PI)
8243 14:44:15.604196 u2DelayCellOfst[5]=0 cells (0 PI)
8244 14:44:15.607655 u2DelayCellOfst[6]=18 cells (5 PI)
8245 14:44:15.611075 u2DelayCellOfst[7]=22 cells (6 PI)
8246 14:44:15.613965 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8247 14:44:15.617084 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8248 14:44:15.621023 == TX Byte 1 ==
8249 14:44:15.623853 u2DelayCellOfst[8]=0 cells (0 PI)
8250 14:44:15.627224 u2DelayCellOfst[9]=3 cells (1 PI)
8251 14:44:15.630811 u2DelayCellOfst[10]=7 cells (2 PI)
8252 14:44:15.633803 u2DelayCellOfst[11]=3 cells (1 PI)
8253 14:44:15.636943 u2DelayCellOfst[12]=14 cells (4 PI)
8254 14:44:15.637025 u2DelayCellOfst[13]=14 cells (4 PI)
8255 14:44:15.640385 u2DelayCellOfst[14]=18 cells (5 PI)
8256 14:44:15.643806 u2DelayCellOfst[15]=14 cells (4 PI)
8257 14:44:15.650393 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8258 14:44:15.653885 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8259 14:44:15.656813 DramC Write-DBI on
8260 14:44:15.656894 ==
8261 14:44:15.659916 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 14:44:15.663518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 14:44:15.663600 ==
8264 14:44:15.663664
8265 14:44:15.663723
8266 14:44:15.666752 TX Vref Scan disable
8267 14:44:15.666833 == TX Byte 0 ==
8268 14:44:15.672988 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8269 14:44:15.673070 == TX Byte 1 ==
8270 14:44:15.676385 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8271 14:44:15.679795 DramC Write-DBI off
8272 14:44:15.679876
8273 14:44:15.679940 [DATLAT]
8274 14:44:15.683093 Freq=1600, CH0 RK1
8275 14:44:15.683174
8276 14:44:15.683239 DATLAT Default: 0xf
8277 14:44:15.686574 0, 0xFFFF, sum = 0
8278 14:44:15.689576 1, 0xFFFF, sum = 0
8279 14:44:15.689658 2, 0xFFFF, sum = 0
8280 14:44:15.693030 3, 0xFFFF, sum = 0
8281 14:44:15.693112 4, 0xFFFF, sum = 0
8282 14:44:15.696608 5, 0xFFFF, sum = 0
8283 14:44:15.696690 6, 0xFFFF, sum = 0
8284 14:44:15.699698 7, 0xFFFF, sum = 0
8285 14:44:15.699781 8, 0xFFFF, sum = 0
8286 14:44:15.703403 9, 0xFFFF, sum = 0
8287 14:44:15.703495 10, 0xFFFF, sum = 0
8288 14:44:15.706622 11, 0xFFFF, sum = 0
8289 14:44:15.706704 12, 0xFFFF, sum = 0
8290 14:44:15.709341 13, 0xFFFF, sum = 0
8291 14:44:15.709423 14, 0x0, sum = 1
8292 14:44:15.712748 15, 0x0, sum = 2
8293 14:44:15.712830 16, 0x0, sum = 3
8294 14:44:15.716196 17, 0x0, sum = 4
8295 14:44:15.716279 best_step = 15
8296 14:44:15.716343
8297 14:44:15.716404 ==
8298 14:44:15.719348 Dram Type= 6, Freq= 0, CH_0, rank 1
8299 14:44:15.725765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 14:44:15.725847 ==
8301 14:44:15.725911 RX Vref Scan: 0
8302 14:44:15.725971
8303 14:44:15.729277 RX Vref 0 -> 0, step: 1
8304 14:44:15.729359
8305 14:44:15.732321 RX Delay 11 -> 252, step: 4
8306 14:44:15.735755 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8307 14:44:15.739193 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8308 14:44:15.745475 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8309 14:44:15.749159 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8310 14:44:15.752682 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8311 14:44:15.755974 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8312 14:44:15.759175 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8313 14:44:15.765371 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8314 14:44:15.768653 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8315 14:44:15.771995 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8316 14:44:15.775239 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8317 14:44:15.779144 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8318 14:44:15.785183 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8319 14:44:15.788586 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8320 14:44:15.791612 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8321 14:44:15.795067 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8322 14:44:15.795149 ==
8323 14:44:15.798011 Dram Type= 6, Freq= 0, CH_0, rank 1
8324 14:44:15.804679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 14:44:15.804762 ==
8326 14:44:15.804828 DQS Delay:
8327 14:44:15.808304 DQS0 = 0, DQS1 = 0
8328 14:44:15.808385 DQM Delay:
8329 14:44:15.811484 DQM0 = 130, DQM1 = 125
8330 14:44:15.811565 DQ Delay:
8331 14:44:15.815003 DQ0 =128, DQ1 =136, DQ2 =124, DQ3 =128
8332 14:44:15.817965 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8333 14:44:15.821197 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8334 14:44:15.824702 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8335 14:44:15.824783
8336 14:44:15.824847
8337 14:44:15.824906
8338 14:44:15.828051 [DramC_TX_OE_Calibration] TA2
8339 14:44:15.831500 Original DQ_B0 (3 6) =30, OEN = 27
8340 14:44:15.834557 Original DQ_B1 (3 6) =30, OEN = 27
8341 14:44:15.838127 24, 0x0, End_B0=24 End_B1=24
8342 14:44:15.841542 25, 0x0, End_B0=25 End_B1=25
8343 14:44:15.841625 26, 0x0, End_B0=26 End_B1=26
8344 14:44:15.844393 27, 0x0, End_B0=27 End_B1=27
8345 14:44:15.847624 28, 0x0, End_B0=28 End_B1=28
8346 14:44:15.851130 29, 0x0, End_B0=29 End_B1=29
8347 14:44:15.854024 30, 0x0, End_B0=30 End_B1=30
8348 14:44:15.854166 31, 0x4141, End_B0=30 End_B1=30
8349 14:44:15.857438 Byte0 end_step=30 best_step=27
8350 14:44:15.861044 Byte1 end_step=30 best_step=27
8351 14:44:15.864424 Byte0 TX OE(2T, 0.5T) = (3, 3)
8352 14:44:15.867471 Byte1 TX OE(2T, 0.5T) = (3, 3)
8353 14:44:15.867552
8354 14:44:15.867616
8355 14:44:15.873991 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8356 14:44:15.877343 CH0 RK1: MR19=303, MR18=1C00
8357 14:44:15.883770 CH0_RK1: MR19=0x303, MR18=0x1C00, DQSOSC=395, MR23=63, INC=23, DEC=15
8358 14:44:15.886843 [RxdqsGatingPostProcess] freq 1600
8359 14:44:15.893331 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8360 14:44:15.897028 best DQS0 dly(2T, 0.5T) = (1, 1)
8361 14:44:15.897110 best DQS1 dly(2T, 0.5T) = (1, 1)
8362 14:44:15.900520 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8363 14:44:15.903755 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8364 14:44:15.906570 best DQS0 dly(2T, 0.5T) = (1, 1)
8365 14:44:15.909921 best DQS1 dly(2T, 0.5T) = (1, 1)
8366 14:44:15.913231 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8367 14:44:15.916621 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8368 14:44:15.919860 Pre-setting of DQS Precalculation
8369 14:44:15.926460 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8370 14:44:15.926566 ==
8371 14:44:15.929924 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 14:44:15.933424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 14:44:15.933505 ==
8374 14:44:15.939934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8375 14:44:15.942910 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8376 14:44:15.946279 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8377 14:44:15.952654 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8378 14:44:15.961355 [CA 0] Center 41 (12~71) winsize 60
8379 14:44:15.964742 [CA 1] Center 41 (12~71) winsize 60
8380 14:44:15.968217 [CA 2] Center 37 (8~66) winsize 59
8381 14:44:15.971574 [CA 3] Center 36 (7~65) winsize 59
8382 14:44:15.974924 [CA 4] Center 37 (7~67) winsize 61
8383 14:44:15.978106 [CA 5] Center 36 (7~66) winsize 60
8384 14:44:15.978212
8385 14:44:15.981531 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8386 14:44:15.981612
8387 14:44:15.984379 [CATrainingPosCal] consider 1 rank data
8388 14:44:15.987854 u2DelayCellTimex100 = 262/100 ps
8389 14:44:15.994401 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8390 14:44:15.997838 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8391 14:44:16.000954 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8392 14:44:16.004785 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8393 14:44:16.007976 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8394 14:44:16.012178 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8395 14:44:16.012303
8396 14:44:16.014065 CA PerBit enable=1, Macro0, CA PI delay=36
8397 14:44:16.014153
8398 14:44:16.017865 [CBTSetCACLKResult] CA Dly = 36
8399 14:44:16.020876 CS Dly: 9 (0~40)
8400 14:44:16.023993 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8401 14:44:16.027165 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8402 14:44:16.027246 ==
8403 14:44:16.030581 Dram Type= 6, Freq= 0, CH_1, rank 1
8404 14:44:16.037383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 14:44:16.037466 ==
8406 14:44:16.040722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8407 14:44:16.047210 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8408 14:44:16.051007 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8409 14:44:16.057214 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8410 14:44:16.064549 [CA 0] Center 42 (12~72) winsize 61
8411 14:44:16.067631 [CA 1] Center 42 (13~72) winsize 60
8412 14:44:16.071309 [CA 2] Center 37 (8~67) winsize 60
8413 14:44:16.074155 [CA 3] Center 36 (7~66) winsize 60
8414 14:44:16.077375 [CA 4] Center 37 (8~67) winsize 60
8415 14:44:16.080934 [CA 5] Center 37 (8~67) winsize 60
8416 14:44:16.081015
8417 14:44:16.084222 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8418 14:44:16.084298
8419 14:44:16.090638 [CATrainingPosCal] consider 2 rank data
8420 14:44:16.090721 u2DelayCellTimex100 = 262/100 ps
8421 14:44:16.097454 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8422 14:44:16.100847 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8423 14:44:16.104016 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8424 14:44:16.107416 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8425 14:44:16.110741 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8426 14:44:16.114034 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8427 14:44:16.114115
8428 14:44:16.117315 CA PerBit enable=1, Macro0, CA PI delay=36
8429 14:44:16.117396
8430 14:44:16.120237 [CBTSetCACLKResult] CA Dly = 36
8431 14:44:16.123776 CS Dly: 10 (0~43)
8432 14:44:16.127264 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8433 14:44:16.130513 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8434 14:44:16.130595
8435 14:44:16.133714 ----->DramcWriteLeveling(PI) begin...
8436 14:44:16.133797 ==
8437 14:44:16.136979 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 14:44:16.143454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 14:44:16.143538 ==
8440 14:44:16.146870 Write leveling (Byte 0): 24 => 24
8441 14:44:16.149919 Write leveling (Byte 1): 26 => 26
8442 14:44:16.150001 DramcWriteLeveling(PI) end<-----
8443 14:44:16.153501
8444 14:44:16.153582 ==
8445 14:44:16.156706 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 14:44:16.160162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 14:44:16.160245 ==
8448 14:44:16.163283 [Gating] SW mode calibration
8449 14:44:16.170048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8450 14:44:16.173411 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8451 14:44:16.179912 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 14:44:16.183687 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 14:44:16.186589 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
8454 14:44:16.193142 1 4 12 | B1->B0 | 2e2e 3434 | 1 0 | (1 1) (0 0)
8455 14:44:16.196535 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 14:44:16.199983 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 14:44:16.206452 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 14:44:16.209940 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 14:44:16.213400 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 14:44:16.219549 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8461 14:44:16.223115 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 14:44:16.226024 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8463 14:44:16.232820 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 14:44:16.236134 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 14:44:16.239356 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 14:44:16.246144 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 14:44:16.249625 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 14:44:16.252853 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 14:44:16.258875 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 14:44:16.262387 1 6 12 | B1->B0 | 3737 3d3d | 1 0 | (0 0) (0 0)
8471 14:44:16.265698 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 14:44:16.272486 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 14:44:16.275712 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 14:44:16.279019 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 14:44:16.285309 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 14:44:16.288907 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 14:44:16.292238 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8478 14:44:16.298950 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8479 14:44:16.301995 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8480 14:44:16.305290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 14:44:16.312251 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 14:44:16.315521 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 14:44:16.318755 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 14:44:16.325509 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 14:44:16.328681 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 14:44:16.331864 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 14:44:16.338443 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 14:44:16.341839 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 14:44:16.344821 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 14:44:16.351422 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 14:44:16.354950 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 14:44:16.358368 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 14:44:16.364579 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8494 14:44:16.368142 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8495 14:44:16.371075 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 14:44:16.374581 Total UI for P1: 0, mck2ui 16
8497 14:44:16.377613 best dqsien dly found for B0: ( 1, 9, 10)
8498 14:44:16.380917 Total UI for P1: 0, mck2ui 16
8499 14:44:16.384622 best dqsien dly found for B1: ( 1, 9, 12)
8500 14:44:16.387740 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8501 14:44:16.390908 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8502 14:44:16.394496
8503 14:44:16.397302 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8504 14:44:16.401180 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8505 14:44:16.404214 [Gating] SW calibration Done
8506 14:44:16.404288 ==
8507 14:44:16.407671 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 14:44:16.410983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 14:44:16.411061 ==
8510 14:44:16.414482 RX Vref Scan: 0
8511 14:44:16.414556
8512 14:44:16.414618 RX Vref 0 -> 0, step: 1
8513 14:44:16.414676
8514 14:44:16.417234 RX Delay 0 -> 252, step: 8
8515 14:44:16.420935 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8516 14:44:16.424141 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8517 14:44:16.430781 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8518 14:44:16.433825 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8519 14:44:16.437267 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8520 14:44:16.440418 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8521 14:44:16.443981 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8522 14:44:16.450692 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8523 14:44:16.453893 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8524 14:44:16.457006 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8525 14:44:16.460681 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8526 14:44:16.467252 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8527 14:44:16.470040 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8528 14:44:16.473373 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8529 14:44:16.476613 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8530 14:44:16.480558 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8531 14:44:16.480640 ==
8532 14:44:16.483458 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 14:44:16.490125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 14:44:16.490248 ==
8535 14:44:16.490313 DQS Delay:
8536 14:44:16.493296 DQS0 = 0, DQS1 = 0
8537 14:44:16.493377 DQM Delay:
8538 14:44:16.496805 DQM0 = 137, DQM1 = 129
8539 14:44:16.496887 DQ Delay:
8540 14:44:16.500341 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8541 14:44:16.503325 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8542 14:44:16.506931 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8543 14:44:16.510417 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8544 14:44:16.510499
8545 14:44:16.510563
8546 14:44:16.510623 ==
8547 14:44:16.513555 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 14:44:16.519932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 14:44:16.520014 ==
8550 14:44:16.520078
8551 14:44:16.520137
8552 14:44:16.520194 TX Vref Scan disable
8553 14:44:16.523639 == TX Byte 0 ==
8554 14:44:16.526776 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8555 14:44:16.533309 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8556 14:44:16.533391 == TX Byte 1 ==
8557 14:44:16.536654 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8558 14:44:16.543008 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8559 14:44:16.543144 ==
8560 14:44:16.546923 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 14:44:16.549609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 14:44:16.549691 ==
8563 14:44:16.562117
8564 14:44:16.565567 TX Vref early break, caculate TX vref
8565 14:44:16.568510 TX Vref=16, minBit 6, minWin=21, winSum=377
8566 14:44:16.572021 TX Vref=18, minBit 0, minWin=22, winSum=386
8567 14:44:16.575293 TX Vref=20, minBit 0, minWin=22, winSum=394
8568 14:44:16.578675 TX Vref=22, minBit 0, minWin=23, winSum=405
8569 14:44:16.581922 TX Vref=24, minBit 6, minWin=24, winSum=417
8570 14:44:16.588437 TX Vref=26, minBit 0, minWin=25, winSum=420
8571 14:44:16.591855 TX Vref=28, minBit 1, minWin=25, winSum=423
8572 14:44:16.594994 TX Vref=30, minBit 0, minWin=25, winSum=415
8573 14:44:16.598600 TX Vref=32, minBit 0, minWin=24, winSum=410
8574 14:44:16.601456 TX Vref=34, minBit 0, minWin=23, winSum=393
8575 14:44:16.608365 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
8576 14:44:16.608447
8577 14:44:16.611520 Final TX Range 0 Vref 28
8578 14:44:16.611628
8579 14:44:16.611720 ==
8580 14:44:16.614609 Dram Type= 6, Freq= 0, CH_1, rank 0
8581 14:44:16.618107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8582 14:44:16.618213 ==
8583 14:44:16.618292
8584 14:44:16.618353
8585 14:44:16.621599 TX Vref Scan disable
8586 14:44:16.627746 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8587 14:44:16.627828 == TX Byte 0 ==
8588 14:44:16.631225 u2DelayCellOfst[0]=18 cells (5 PI)
8589 14:44:16.634654 u2DelayCellOfst[1]=14 cells (4 PI)
8590 14:44:16.637688 u2DelayCellOfst[2]=0 cells (0 PI)
8591 14:44:16.641407 u2DelayCellOfst[3]=7 cells (2 PI)
8592 14:44:16.644696 u2DelayCellOfst[4]=7 cells (2 PI)
8593 14:44:16.647992 u2DelayCellOfst[5]=22 cells (6 PI)
8594 14:44:16.651110 u2DelayCellOfst[6]=18 cells (5 PI)
8595 14:44:16.654293 u2DelayCellOfst[7]=7 cells (2 PI)
8596 14:44:16.657977 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8597 14:44:16.661247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8598 14:44:16.664155 == TX Byte 1 ==
8599 14:44:16.667373 u2DelayCellOfst[8]=0 cells (0 PI)
8600 14:44:16.670830 u2DelayCellOfst[9]=3 cells (1 PI)
8601 14:44:16.673916 u2DelayCellOfst[10]=11 cells (3 PI)
8602 14:44:16.673997 u2DelayCellOfst[11]=3 cells (1 PI)
8603 14:44:16.677450 u2DelayCellOfst[12]=14 cells (4 PI)
8604 14:44:16.680826 u2DelayCellOfst[13]=18 cells (5 PI)
8605 14:44:16.683924 u2DelayCellOfst[14]=18 cells (5 PI)
8606 14:44:16.687064 u2DelayCellOfst[15]=18 cells (5 PI)
8607 14:44:16.693846 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8608 14:44:16.697078 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8609 14:44:16.697160 DramC Write-DBI on
8610 14:44:16.700817 ==
8611 14:44:16.703964 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 14:44:16.707233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 14:44:16.707315 ==
8614 14:44:16.707380
8615 14:44:16.707440
8616 14:44:16.710507 TX Vref Scan disable
8617 14:44:16.710589 == TX Byte 0 ==
8618 14:44:16.716779 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8619 14:44:16.716861 == TX Byte 1 ==
8620 14:44:16.720140 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8621 14:44:16.723283 DramC Write-DBI off
8622 14:44:16.723367
8623 14:44:16.723465 [DATLAT]
8624 14:44:16.726680 Freq=1600, CH1 RK0
8625 14:44:16.726761
8626 14:44:16.726825 DATLAT Default: 0xf
8627 14:44:16.729915 0, 0xFFFF, sum = 0
8628 14:44:16.729998 1, 0xFFFF, sum = 0
8629 14:44:16.733025 2, 0xFFFF, sum = 0
8630 14:44:16.733137 3, 0xFFFF, sum = 0
8631 14:44:16.736276 4, 0xFFFF, sum = 0
8632 14:44:16.736359 5, 0xFFFF, sum = 0
8633 14:44:16.739754 6, 0xFFFF, sum = 0
8634 14:44:16.743267 7, 0xFFFF, sum = 0
8635 14:44:16.743351 8, 0xFFFF, sum = 0
8636 14:44:16.746340 9, 0xFFFF, sum = 0
8637 14:44:16.746422 10, 0xFFFF, sum = 0
8638 14:44:16.749447 11, 0xFFFF, sum = 0
8639 14:44:16.749529 12, 0xFFFF, sum = 0
8640 14:44:16.752885 13, 0xFFFF, sum = 0
8641 14:44:16.752968 14, 0x0, sum = 1
8642 14:44:16.756187 15, 0x0, sum = 2
8643 14:44:16.756299 16, 0x0, sum = 3
8644 14:44:16.759252 17, 0x0, sum = 4
8645 14:44:16.759335 best_step = 15
8646 14:44:16.759400
8647 14:44:16.759460 ==
8648 14:44:16.762684 Dram Type= 6, Freq= 0, CH_1, rank 0
8649 14:44:16.769111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8650 14:44:16.769194 ==
8651 14:44:16.769258 RX Vref Scan: 1
8652 14:44:16.769318
8653 14:44:16.772651 Set Vref Range= 24 -> 127
8654 14:44:16.772732
8655 14:44:16.776076 RX Vref 24 -> 127, step: 1
8656 14:44:16.776158
8657 14:44:16.776222 RX Delay 11 -> 252, step: 4
8658 14:44:16.776282
8659 14:44:16.779158 Set Vref, RX VrefLevel [Byte0]: 24
8660 14:44:16.782041 [Byte1]: 24
8661 14:44:16.786772
8662 14:44:16.786853 Set Vref, RX VrefLevel [Byte0]: 25
8663 14:44:16.789751 [Byte1]: 25
8664 14:44:16.794087
8665 14:44:16.794187 Set Vref, RX VrefLevel [Byte0]: 26
8666 14:44:16.797324 [Byte1]: 26
8667 14:44:16.801786
8668 14:44:16.801867 Set Vref, RX VrefLevel [Byte0]: 27
8669 14:44:16.805335 [Byte1]: 27
8670 14:44:16.809570
8671 14:44:16.809651 Set Vref, RX VrefLevel [Byte0]: 28
8672 14:44:16.812552 [Byte1]: 28
8673 14:44:16.816803
8674 14:44:16.816885 Set Vref, RX VrefLevel [Byte0]: 29
8675 14:44:16.820113 [Byte1]: 29
8676 14:44:16.824589
8677 14:44:16.824674 Set Vref, RX VrefLevel [Byte0]: 30
8678 14:44:16.827996 [Byte1]: 30
8679 14:44:16.832025
8680 14:44:16.832106 Set Vref, RX VrefLevel [Byte0]: 31
8681 14:44:16.835327 [Byte1]: 31
8682 14:44:16.839885
8683 14:44:16.839966 Set Vref, RX VrefLevel [Byte0]: 32
8684 14:44:16.843008 [Byte1]: 32
8685 14:44:16.847138
8686 14:44:16.847219 Set Vref, RX VrefLevel [Byte0]: 33
8687 14:44:16.850500 [Byte1]: 33
8688 14:44:16.855032
8689 14:44:16.855113 Set Vref, RX VrefLevel [Byte0]: 34
8690 14:44:16.858378 [Byte1]: 34
8691 14:44:16.862679
8692 14:44:16.862760 Set Vref, RX VrefLevel [Byte0]: 35
8693 14:44:16.865624 [Byte1]: 35
8694 14:44:16.870062
8695 14:44:16.870143 Set Vref, RX VrefLevel [Byte0]: 36
8696 14:44:16.873994 [Byte1]: 36
8697 14:44:16.877970
8698 14:44:16.878051 Set Vref, RX VrefLevel [Byte0]: 37
8699 14:44:16.881285 [Byte1]: 37
8700 14:44:16.885537
8701 14:44:16.885618 Set Vref, RX VrefLevel [Byte0]: 38
8702 14:44:16.888747 [Byte1]: 38
8703 14:44:16.893224
8704 14:44:16.893304 Set Vref, RX VrefLevel [Byte0]: 39
8705 14:44:16.896720 [Byte1]: 39
8706 14:44:16.900450
8707 14:44:16.900527 Set Vref, RX VrefLevel [Byte0]: 40
8708 14:44:16.904455 [Byte1]: 40
8709 14:44:16.908241
8710 14:44:16.908313 Set Vref, RX VrefLevel [Byte0]: 41
8711 14:44:16.911323 [Byte1]: 41
8712 14:44:16.915773
8713 14:44:16.915845 Set Vref, RX VrefLevel [Byte0]: 42
8714 14:44:16.919109 [Byte1]: 42
8715 14:44:16.923842
8716 14:44:16.923915 Set Vref, RX VrefLevel [Byte0]: 43
8717 14:44:16.929733 [Byte1]: 43
8718 14:44:16.929809
8719 14:44:16.933219 Set Vref, RX VrefLevel [Byte0]: 44
8720 14:44:16.936638 [Byte1]: 44
8721 14:44:16.936727
8722 14:44:16.939805 Set Vref, RX VrefLevel [Byte0]: 45
8723 14:44:16.943028 [Byte1]: 45
8724 14:44:16.946299
8725 14:44:16.946372 Set Vref, RX VrefLevel [Byte0]: 46
8726 14:44:16.950001 [Byte1]: 46
8727 14:44:16.954096
8728 14:44:16.954217 Set Vref, RX VrefLevel [Byte0]: 47
8729 14:44:16.957507 [Byte1]: 47
8730 14:44:16.961416
8731 14:44:16.961486 Set Vref, RX VrefLevel [Byte0]: 48
8732 14:44:16.964524 [Byte1]: 48
8733 14:44:16.969218
8734 14:44:16.969299 Set Vref, RX VrefLevel [Byte0]: 49
8735 14:44:16.972673 [Byte1]: 49
8736 14:44:16.976764
8737 14:44:16.976846 Set Vref, RX VrefLevel [Byte0]: 50
8738 14:44:16.980273 [Byte1]: 50
8739 14:44:16.984769
8740 14:44:16.984850 Set Vref, RX VrefLevel [Byte0]: 51
8741 14:44:16.987563 [Byte1]: 51
8742 14:44:16.992317
8743 14:44:16.992398 Set Vref, RX VrefLevel [Byte0]: 52
8744 14:44:16.995164 [Byte1]: 52
8745 14:44:16.999969
8746 14:44:17.000051 Set Vref, RX VrefLevel [Byte0]: 53
8747 14:44:17.003072 [Byte1]: 53
8748 14:44:17.007031
8749 14:44:17.007113 Set Vref, RX VrefLevel [Byte0]: 54
8750 14:44:17.010307 [Byte1]: 54
8751 14:44:17.015014
8752 14:44:17.015124 Set Vref, RX VrefLevel [Byte0]: 55
8753 14:44:17.018234 [Byte1]: 55
8754 14:44:17.022152
8755 14:44:17.022271 Set Vref, RX VrefLevel [Byte0]: 56
8756 14:44:17.028888 [Byte1]: 56
8757 14:44:17.028969
8758 14:44:17.031974 Set Vref, RX VrefLevel [Byte0]: 57
8759 14:44:17.035537 [Byte1]: 57
8760 14:44:17.035618
8761 14:44:17.038606 Set Vref, RX VrefLevel [Byte0]: 58
8762 14:44:17.042447 [Byte1]: 58
8763 14:44:17.045189
8764 14:44:17.045270 Set Vref, RX VrefLevel [Byte0]: 59
8765 14:44:17.048778 [Byte1]: 59
8766 14:44:17.053124
8767 14:44:17.053205 Set Vref, RX VrefLevel [Byte0]: 60
8768 14:44:17.055933 [Byte1]: 60
8769 14:44:17.060513
8770 14:44:17.060594 Set Vref, RX VrefLevel [Byte0]: 61
8771 14:44:17.063777 [Byte1]: 61
8772 14:44:17.068421
8773 14:44:17.068502 Set Vref, RX VrefLevel [Byte0]: 62
8774 14:44:17.071187 [Byte1]: 62
8775 14:44:17.075706
8776 14:44:17.075812 Set Vref, RX VrefLevel [Byte0]: 63
8777 14:44:17.079181 [Byte1]: 63
8778 14:44:17.083328
8779 14:44:17.083409 Set Vref, RX VrefLevel [Byte0]: 64
8780 14:44:17.086670 [Byte1]: 64
8781 14:44:17.090942
8782 14:44:17.091023 Set Vref, RX VrefLevel [Byte0]: 65
8783 14:44:17.094158 [Byte1]: 65
8784 14:44:17.098844
8785 14:44:17.098925 Set Vref, RX VrefLevel [Byte0]: 66
8786 14:44:17.101900 [Byte1]: 66
8787 14:44:17.106524
8788 14:44:17.106605 Set Vref, RX VrefLevel [Byte0]: 67
8789 14:44:17.109770 [Byte1]: 67
8790 14:44:17.114002
8791 14:44:17.114084 Set Vref, RX VrefLevel [Byte0]: 68
8792 14:44:17.116942 [Byte1]: 68
8793 14:44:17.121272
8794 14:44:17.121353 Set Vref, RX VrefLevel [Byte0]: 69
8795 14:44:17.128015 [Byte1]: 69
8796 14:44:17.128101
8797 14:44:17.131295 Set Vref, RX VrefLevel [Byte0]: 70
8798 14:44:17.134566 [Byte1]: 70
8799 14:44:17.134640
8800 14:44:17.137547 Set Vref, RX VrefLevel [Byte0]: 71
8801 14:44:17.140722 [Byte1]: 71
8802 14:44:17.144119
8803 14:44:17.144195 Final RX Vref Byte 0 = 53 to rank0
8804 14:44:17.147367 Final RX Vref Byte 1 = 60 to rank0
8805 14:44:17.150810 Final RX Vref Byte 0 = 53 to rank1
8806 14:44:17.154038 Final RX Vref Byte 1 = 60 to rank1==
8807 14:44:17.157809 Dram Type= 6, Freq= 0, CH_1, rank 0
8808 14:44:17.164145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 14:44:17.164229 ==
8810 14:44:17.164296 DQS Delay:
8811 14:44:17.167285 DQS0 = 0, DQS1 = 0
8812 14:44:17.167358 DQM Delay:
8813 14:44:17.167418 DQM0 = 133, DQM1 = 127
8814 14:44:17.170896 DQ Delay:
8815 14:44:17.173795 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8816 14:44:17.177571 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8817 14:44:17.180607 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8818 14:44:17.184105 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =136
8819 14:44:17.184182
8820 14:44:17.184253
8821 14:44:17.184316
8822 14:44:17.187560 [DramC_TX_OE_Calibration] TA2
8823 14:44:17.190768 Original DQ_B0 (3 6) =30, OEN = 27
8824 14:44:17.194040 Original DQ_B1 (3 6) =30, OEN = 27
8825 14:44:17.197199 24, 0x0, End_B0=24 End_B1=24
8826 14:44:17.197270 25, 0x0, End_B0=25 End_B1=25
8827 14:44:17.200581 26, 0x0, End_B0=26 End_B1=26
8828 14:44:17.203910 27, 0x0, End_B0=27 End_B1=27
8829 14:44:17.207421 28, 0x0, End_B0=28 End_B1=28
8830 14:44:17.210338 29, 0x0, End_B0=29 End_B1=29
8831 14:44:17.210416 30, 0x0, End_B0=30 End_B1=30
8832 14:44:17.213959 31, 0x4141, End_B0=30 End_B1=30
8833 14:44:17.217140 Byte0 end_step=30 best_step=27
8834 14:44:17.220125 Byte1 end_step=30 best_step=27
8835 14:44:17.223833 Byte0 TX OE(2T, 0.5T) = (3, 3)
8836 14:44:17.227214 Byte1 TX OE(2T, 0.5T) = (3, 3)
8837 14:44:17.227296
8838 14:44:17.227360
8839 14:44:17.233702 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8840 14:44:17.237204 CH1 RK0: MR19=303, MR18=180E
8841 14:44:17.243550 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8842 14:44:17.243633
8843 14:44:17.246670 ----->DramcWriteLeveling(PI) begin...
8844 14:44:17.246752 ==
8845 14:44:17.249835 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 14:44:17.253507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 14:44:17.253589 ==
8848 14:44:17.256331 Write leveling (Byte 0): 25 => 25
8849 14:44:17.259835 Write leveling (Byte 1): 26 => 26
8850 14:44:17.262941 DramcWriteLeveling(PI) end<-----
8851 14:44:17.263013
8852 14:44:17.263107 ==
8853 14:44:17.266182 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 14:44:17.269824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 14:44:17.272829 ==
8856 14:44:17.272906 [Gating] SW mode calibration
8857 14:44:17.282722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8858 14:44:17.286368 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8859 14:44:17.289531 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 14:44:17.296115 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 14:44:17.298966 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8862 14:44:17.302530 1 4 12 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8863 14:44:17.308852 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 14:44:17.312566 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 14:44:17.315559 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 14:44:17.322330 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 14:44:17.325649 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 14:44:17.329302 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 14:44:17.335835 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8870 14:44:17.338728 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8871 14:44:17.342005 1 5 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8872 14:44:17.348593 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 14:44:17.352007 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 14:44:17.355485 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 14:44:17.361961 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 14:44:17.365617 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 14:44:17.368471 1 6 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8878 14:44:17.375256 1 6 12 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8879 14:44:17.378400 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 14:44:17.381939 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 14:44:17.388362 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 14:44:17.391861 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 14:44:17.394833 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 14:44:17.401938 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 14:44:17.405064 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8886 14:44:17.408282 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8887 14:44:17.414601 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8888 14:44:17.418374 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 14:44:17.421664 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 14:44:17.428093 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 14:44:17.431456 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 14:44:17.434490 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 14:44:17.441593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 14:44:17.444227 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 14:44:17.447560 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 14:44:17.454116 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 14:44:17.457767 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 14:44:17.460828 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 14:44:17.467483 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 14:44:17.470521 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8901 14:44:17.474082 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8902 14:44:17.480842 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8903 14:44:17.484080 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8904 14:44:17.487496 Total UI for P1: 0, mck2ui 16
8905 14:44:17.490584 best dqsien dly found for B1: ( 1, 9, 8)
8906 14:44:17.493929 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8907 14:44:17.497533 Total UI for P1: 0, mck2ui 16
8908 14:44:17.500382 best dqsien dly found for B0: ( 1, 9, 14)
8909 14:44:17.503736 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8910 14:44:17.506845 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8911 14:44:17.506926
8912 14:44:17.513508 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8913 14:44:17.516750 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8914 14:44:17.520313 [Gating] SW calibration Done
8915 14:44:17.520420 ==
8916 14:44:17.523519 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 14:44:17.526974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 14:44:17.527055 ==
8919 14:44:17.527119 RX Vref Scan: 0
8920 14:44:17.530382
8921 14:44:17.530462 RX Vref 0 -> 0, step: 1
8922 14:44:17.530526
8923 14:44:17.533686 RX Delay 0 -> 252, step: 8
8924 14:44:17.536649 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8925 14:44:17.540141 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8926 14:44:17.546796 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8927 14:44:17.549715 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8928 14:44:17.553300 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8929 14:44:17.556278 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8930 14:44:17.559720 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8931 14:44:17.566470 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8932 14:44:17.570094 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8933 14:44:17.573187 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8934 14:44:17.576336 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8935 14:44:17.579290 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8936 14:44:17.585970 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8937 14:44:17.589433 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8938 14:44:17.592464 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8939 14:44:17.595725 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8940 14:44:17.599403 ==
8941 14:44:17.602400 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 14:44:17.605886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 14:44:17.606010 ==
8944 14:44:17.606104 DQS Delay:
8945 14:44:17.609437 DQS0 = 0, DQS1 = 0
8946 14:44:17.609517 DQM Delay:
8947 14:44:17.612415 DQM0 = 136, DQM1 = 130
8948 14:44:17.612496 DQ Delay:
8949 14:44:17.615702 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8950 14:44:17.619021 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8951 14:44:17.621933 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8952 14:44:17.625535 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8953 14:44:17.625617
8954 14:44:17.625680
8955 14:44:17.628518 ==
8956 14:44:17.628598 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 14:44:17.635513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 14:44:17.635595 ==
8959 14:44:17.635658
8960 14:44:17.635716
8961 14:44:17.638755 TX Vref Scan disable
8962 14:44:17.638836 == TX Byte 0 ==
8963 14:44:17.641779 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8964 14:44:17.648369 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8965 14:44:17.648450 == TX Byte 1 ==
8966 14:44:17.651788 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8967 14:44:17.658694 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8968 14:44:17.658800 ==
8969 14:44:17.661704 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 14:44:17.665053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 14:44:17.665160 ==
8972 14:44:17.678003
8973 14:44:17.681319 TX Vref early break, caculate TX vref
8974 14:44:17.684649 TX Vref=16, minBit 0, minWin=23, winSum=385
8975 14:44:17.687920 TX Vref=18, minBit 0, minWin=24, winSum=398
8976 14:44:17.691711 TX Vref=20, minBit 1, minWin=24, winSum=408
8977 14:44:17.694870 TX Vref=22, minBit 3, minWin=25, winSum=416
8978 14:44:17.698018 TX Vref=24, minBit 1, minWin=25, winSum=425
8979 14:44:17.704498 TX Vref=26, minBit 0, minWin=25, winSum=429
8980 14:44:17.707727 TX Vref=28, minBit 0, minWin=25, winSum=428
8981 14:44:17.711427 TX Vref=30, minBit 0, minWin=25, winSum=422
8982 14:44:17.714461 TX Vref=32, minBit 0, minWin=25, winSum=415
8983 14:44:17.717642 TX Vref=34, minBit 0, minWin=24, winSum=399
8984 14:44:17.724313 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 26
8985 14:44:17.724427
8986 14:44:17.727462 Final TX Range 0 Vref 26
8987 14:44:17.727543
8988 14:44:17.727606 ==
8989 14:44:17.730664 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 14:44:17.733979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 14:44:17.734085 ==
8992 14:44:17.734220
8993 14:44:17.734304
8994 14:44:17.737732 TX Vref Scan disable
8995 14:44:17.743946 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8996 14:44:17.744056 == TX Byte 0 ==
8997 14:44:17.747428 u2DelayCellOfst[0]=18 cells (5 PI)
8998 14:44:17.750442 u2DelayCellOfst[1]=14 cells (4 PI)
8999 14:44:17.753733 u2DelayCellOfst[2]=0 cells (0 PI)
9000 14:44:17.756777 u2DelayCellOfst[3]=7 cells (2 PI)
9001 14:44:17.760355 u2DelayCellOfst[4]=7 cells (2 PI)
9002 14:44:17.763575 u2DelayCellOfst[5]=22 cells (6 PI)
9003 14:44:17.766951 u2DelayCellOfst[6]=22 cells (6 PI)
9004 14:44:17.769988 u2DelayCellOfst[7]=7 cells (2 PI)
9005 14:44:17.773357 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9006 14:44:17.776749 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9007 14:44:17.780289 == TX Byte 1 ==
9008 14:44:17.783143 u2DelayCellOfst[8]=0 cells (0 PI)
9009 14:44:17.786444 u2DelayCellOfst[9]=7 cells (2 PI)
9010 14:44:17.789776 u2DelayCellOfst[10]=11 cells (3 PI)
9011 14:44:17.792854 u2DelayCellOfst[11]=7 cells (2 PI)
9012 14:44:17.792929 u2DelayCellOfst[12]=14 cells (4 PI)
9013 14:44:17.796451 u2DelayCellOfst[13]=18 cells (5 PI)
9014 14:44:17.799705 u2DelayCellOfst[14]=18 cells (5 PI)
9015 14:44:17.802910 u2DelayCellOfst[15]=18 cells (5 PI)
9016 14:44:17.809464 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9017 14:44:17.812941 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9018 14:44:17.813022 DramC Write-DBI on
9019 14:44:17.816253 ==
9020 14:44:17.819224 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 14:44:17.822608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 14:44:17.822689 ==
9023 14:44:17.822752
9024 14:44:17.822810
9025 14:44:17.825867 TX Vref Scan disable
9026 14:44:17.825947 == TX Byte 0 ==
9027 14:44:17.832538 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9028 14:44:17.832649 == TX Byte 1 ==
9029 14:44:17.835850 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9030 14:44:17.839014 DramC Write-DBI off
9031 14:44:17.839096
9032 14:44:17.839159 [DATLAT]
9033 14:44:17.843078 Freq=1600, CH1 RK1
9034 14:44:17.843159
9035 14:44:17.843222 DATLAT Default: 0xf
9036 14:44:17.845528 0, 0xFFFF, sum = 0
9037 14:44:17.845610 1, 0xFFFF, sum = 0
9038 14:44:17.849208 2, 0xFFFF, sum = 0
9039 14:44:17.852297 3, 0xFFFF, sum = 0
9040 14:44:17.852379 4, 0xFFFF, sum = 0
9041 14:44:17.855428 5, 0xFFFF, sum = 0
9042 14:44:17.855510 6, 0xFFFF, sum = 0
9043 14:44:17.858663 7, 0xFFFF, sum = 0
9044 14:44:17.858744 8, 0xFFFF, sum = 0
9045 14:44:17.862082 9, 0xFFFF, sum = 0
9046 14:44:17.862222 10, 0xFFFF, sum = 0
9047 14:44:17.865426 11, 0xFFFF, sum = 0
9048 14:44:17.865528 12, 0xFFFF, sum = 0
9049 14:44:17.868808 13, 0xFFFF, sum = 0
9050 14:44:17.868890 14, 0x0, sum = 1
9051 14:44:17.872246 15, 0x0, sum = 2
9052 14:44:17.872335 16, 0x0, sum = 3
9053 14:44:17.875195 17, 0x0, sum = 4
9054 14:44:17.875277 best_step = 15
9055 14:44:17.875340
9056 14:44:17.875399 ==
9057 14:44:17.878533 Dram Type= 6, Freq= 0, CH_1, rank 1
9058 14:44:17.885086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9059 14:44:17.885167 ==
9060 14:44:17.885230 RX Vref Scan: 0
9061 14:44:17.885289
9062 14:44:17.888452 RX Vref 0 -> 0, step: 1
9063 14:44:17.888532
9064 14:44:17.891691 RX Delay 11 -> 252, step: 4
9065 14:44:17.895167 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9066 14:44:17.898344 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9067 14:44:17.904581 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9068 14:44:17.908292 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9069 14:44:17.911443 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9070 14:44:17.914612 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9071 14:44:17.917767 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9072 14:44:17.924339 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9073 14:44:17.928043 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9074 14:44:17.931431 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9075 14:44:17.934322 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9076 14:44:17.937720 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9077 14:44:17.944668 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9078 14:44:17.947617 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9079 14:44:17.951106 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9080 14:44:17.954152 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9081 14:44:17.954271 ==
9082 14:44:17.957524 Dram Type= 6, Freq= 0, CH_1, rank 1
9083 14:44:17.964359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9084 14:44:17.964440 ==
9085 14:44:17.964504 DQS Delay:
9086 14:44:17.967441 DQS0 = 0, DQS1 = 0
9087 14:44:17.967522 DQM Delay:
9088 14:44:17.967585 DQM0 = 133, DQM1 = 126
9089 14:44:17.970714 DQ Delay:
9090 14:44:17.973939 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9091 14:44:17.977736 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9092 14:44:17.980914 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9093 14:44:17.984223 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9094 14:44:17.984303
9095 14:44:17.984367
9096 14:44:17.984425
9097 14:44:17.987345 [DramC_TX_OE_Calibration] TA2
9098 14:44:17.990707 Original DQ_B0 (3 6) =30, OEN = 27
9099 14:44:17.994108 Original DQ_B1 (3 6) =30, OEN = 27
9100 14:44:17.997314 24, 0x0, End_B0=24 End_B1=24
9101 14:44:18.000556 25, 0x0, End_B0=25 End_B1=25
9102 14:44:18.000639 26, 0x0, End_B0=26 End_B1=26
9103 14:44:18.003860 27, 0x0, End_B0=27 End_B1=27
9104 14:44:18.007048 28, 0x0, End_B0=28 End_B1=28
9105 14:44:18.010292 29, 0x0, End_B0=29 End_B1=29
9106 14:44:18.010371 30, 0x0, End_B0=30 End_B1=30
9107 14:44:18.013760 31, 0x4141, End_B0=30 End_B1=30
9108 14:44:18.016748 Byte0 end_step=30 best_step=27
9109 14:44:18.019979 Byte1 end_step=30 best_step=27
9110 14:44:18.023483 Byte0 TX OE(2T, 0.5T) = (3, 3)
9111 14:44:18.026638 Byte1 TX OE(2T, 0.5T) = (3, 3)
9112 14:44:18.026710
9113 14:44:18.026787
9114 14:44:18.033476 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9115 14:44:18.036605 CH1 RK1: MR19=303, MR18=C0A
9116 14:44:18.043309 CH1_RK1: MR19=0x303, MR18=0xC0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9117 14:44:18.046423 [RxdqsGatingPostProcess] freq 1600
9118 14:44:18.052869 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9119 14:44:18.052951 best DQS0 dly(2T, 0.5T) = (1, 1)
9120 14:44:18.056503 best DQS1 dly(2T, 0.5T) = (1, 1)
9121 14:44:18.059798 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9122 14:44:18.063084 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9123 14:44:18.066071 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 14:44:18.069474 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 14:44:18.072820 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 14:44:18.076293 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 14:44:18.079582 Pre-setting of DQS Precalculation
9128 14:44:18.082676 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9129 14:44:18.092692 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9130 14:44:18.099283 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 14:44:18.099367
9132 14:44:18.099431
9133 14:44:18.102537 [Calibration Summary] 3200 Mbps
9134 14:44:18.102634 CH 0, Rank 0
9135 14:44:18.105733 SW Impedance : PASS
9136 14:44:18.105815 DUTY Scan : NO K
9137 14:44:18.109107 ZQ Calibration : PASS
9138 14:44:18.112544 Jitter Meter : NO K
9139 14:44:18.112625 CBT Training : PASS
9140 14:44:18.115674 Write leveling : PASS
9141 14:44:18.118930 RX DQS gating : PASS
9142 14:44:18.119036 RX DQ/DQS(RDDQC) : PASS
9143 14:44:18.122458 TX DQ/DQS : PASS
9144 14:44:18.125814 RX DATLAT : PASS
9145 14:44:18.125897 RX DQ/DQS(Engine): PASS
9146 14:44:18.128879 TX OE : PASS
9147 14:44:18.128963 All Pass.
9148 14:44:18.129029
9149 14:44:18.132005 CH 0, Rank 1
9150 14:44:18.132087 SW Impedance : PASS
9151 14:44:18.135288 DUTY Scan : NO K
9152 14:44:18.138732 ZQ Calibration : PASS
9153 14:44:18.138813 Jitter Meter : NO K
9154 14:44:18.141945 CBT Training : PASS
9155 14:44:18.145211 Write leveling : PASS
9156 14:44:18.145357 RX DQS gating : PASS
9157 14:44:18.148618 RX DQ/DQS(RDDQC) : PASS
9158 14:44:18.152025 TX DQ/DQS : PASS
9159 14:44:18.152107 RX DATLAT : PASS
9160 14:44:18.155440 RX DQ/DQS(Engine): PASS
9161 14:44:18.155521 TX OE : PASS
9162 14:44:18.158562 All Pass.
9163 14:44:18.158643
9164 14:44:18.158707 CH 1, Rank 0
9165 14:44:18.162020 SW Impedance : PASS
9166 14:44:18.162101 DUTY Scan : NO K
9167 14:44:18.164881 ZQ Calibration : PASS
9168 14:44:18.168800 Jitter Meter : NO K
9169 14:44:18.168906 CBT Training : PASS
9170 14:44:18.171481 Write leveling : PASS
9171 14:44:18.174899 RX DQS gating : PASS
9172 14:44:18.175010 RX DQ/DQS(RDDQC) : PASS
9173 14:44:18.178187 TX DQ/DQS : PASS
9174 14:44:18.181923 RX DATLAT : PASS
9175 14:44:18.182020 RX DQ/DQS(Engine): PASS
9176 14:44:18.184942 TX OE : PASS
9177 14:44:18.185025 All Pass.
9178 14:44:18.185089
9179 14:44:18.188563 CH 1, Rank 1
9180 14:44:18.188644 SW Impedance : PASS
9181 14:44:18.191385 DUTY Scan : NO K
9182 14:44:18.194539 ZQ Calibration : PASS
9183 14:44:18.194649 Jitter Meter : NO K
9184 14:44:18.197758 CBT Training : PASS
9185 14:44:18.201336 Write leveling : PASS
9186 14:44:18.201434 RX DQS gating : PASS
9187 14:44:18.204577 RX DQ/DQS(RDDQC) : PASS
9188 14:44:18.207573 TX DQ/DQS : PASS
9189 14:44:18.207699 RX DATLAT : PASS
9190 14:44:18.211052 RX DQ/DQS(Engine): PASS
9191 14:44:18.214377 TX OE : PASS
9192 14:44:18.214459 All Pass.
9193 14:44:18.214523
9194 14:44:18.214597 DramC Write-DBI on
9195 14:44:18.217716 PER_BANK_REFRESH: Hybrid Mode
9196 14:44:18.221193 TX_TRACKING: ON
9197 14:44:18.227851 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9198 14:44:18.237563 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9199 14:44:18.244450 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9200 14:44:18.247376 [FAST_K] Save calibration result to emmc
9201 14:44:18.250736 sync common calibartion params.
9202 14:44:18.253733 sync cbt_mode0:1, 1:1
9203 14:44:18.253816 dram_init: ddr_geometry: 2
9204 14:44:18.257544 dram_init: ddr_geometry: 2
9205 14:44:18.260455 dram_init: ddr_geometry: 2
9206 14:44:18.263709 0:dram_rank_size:100000000
9207 14:44:18.263792 1:dram_rank_size:100000000
9208 14:44:18.270303 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9209 14:44:18.273690 DFS_SHUFFLE_HW_MODE: ON
9210 14:44:18.276963 dramc_set_vcore_voltage set vcore to 725000
9211 14:44:18.280220 Read voltage for 1600, 0
9212 14:44:18.280304 Vio18 = 0
9213 14:44:18.280370 Vcore = 725000
9214 14:44:18.283915 Vdram = 0
9215 14:44:18.284001 Vddq = 0
9216 14:44:18.284068 Vmddr = 0
9217 14:44:18.287053 switch to 3200 Mbps bootup
9218 14:44:18.287137 [DramcRunTimeConfig]
9219 14:44:18.290368 PHYPLL
9220 14:44:18.290452 DPM_CONTROL_AFTERK: ON
9221 14:44:18.293356 PER_BANK_REFRESH: ON
9222 14:44:18.296617 REFRESH_OVERHEAD_REDUCTION: ON
9223 14:44:18.296700 CMD_PICG_NEW_MODE: OFF
9224 14:44:18.299967 XRTWTW_NEW_MODE: ON
9225 14:44:18.300051 XRTRTR_NEW_MODE: ON
9226 14:44:18.303337 TX_TRACKING: ON
9227 14:44:18.303420 RDSEL_TRACKING: OFF
9228 14:44:18.306551 DQS Precalculation for DVFS: ON
9229 14:44:18.310208 RX_TRACKING: OFF
9230 14:44:18.310293 HW_GATING DBG: ON
9231 14:44:18.313396 ZQCS_ENABLE_LP4: ON
9232 14:44:18.313478 RX_PICG_NEW_MODE: ON
9233 14:44:18.316515 TX_PICG_NEW_MODE: ON
9234 14:44:18.316598 ENABLE_RX_DCM_DPHY: ON
9235 14:44:18.320265 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9236 14:44:18.323351 DUMMY_READ_FOR_TRACKING: OFF
9237 14:44:18.326628 !!! SPM_CONTROL_AFTERK: OFF
9238 14:44:18.329983 !!! SPM could not control APHY
9239 14:44:18.330067 IMPEDANCE_TRACKING: ON
9240 14:44:18.332910 TEMP_SENSOR: ON
9241 14:44:18.332993 HW_SAVE_FOR_SR: OFF
9242 14:44:18.336264 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9243 14:44:18.339922 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9244 14:44:18.342789 Read ODT Tracking: ON
9245 14:44:18.346506 Refresh Rate DeBounce: ON
9246 14:44:18.346589 DFS_NO_QUEUE_FLUSH: ON
9247 14:44:18.349702 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9248 14:44:18.352883 ENABLE_DFS_RUNTIME_MRW: OFF
9249 14:44:18.356157 DDR_RESERVE_NEW_MODE: ON
9250 14:44:18.356240 MR_CBT_SWITCH_FREQ: ON
9251 14:44:18.359649 =========================
9252 14:44:18.378713 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9253 14:44:18.381719 dram_init: ddr_geometry: 2
9254 14:44:18.400087 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9255 14:44:18.403545 dram_init: dram init end (result: 0)
9256 14:44:18.409993 DRAM-K: Full calibration passed in 24606 msecs
9257 14:44:18.413624 MRC: failed to locate region type 0.
9258 14:44:18.413707 DRAM rank0 size:0x100000000,
9259 14:44:18.416640 DRAM rank1 size=0x100000000
9260 14:44:18.426717 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9261 14:44:18.433602 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9262 14:44:18.440289 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9263 14:44:18.449774 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9264 14:44:18.449860 DRAM rank0 size:0x100000000,
9265 14:44:18.453028 DRAM rank1 size=0x100000000
9266 14:44:18.453111 CBMEM:
9267 14:44:18.456623 IMD: root @ 0xfffff000 254 entries.
9268 14:44:18.459864 IMD: root @ 0xffffec00 62 entries.
9269 14:44:18.462763 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9270 14:44:18.469574 WARNING: RO_VPD is uninitialized or empty.
9271 14:44:18.472809 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9272 14:44:18.483276 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9273 14:44:18.493124 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9274 14:44:18.504450 BS: romstage times (exec / console): total (unknown) / 24100 ms
9275 14:44:18.504539
9276 14:44:18.504604
9277 14:44:18.514668 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9278 14:44:18.518130 ARM64: Exception handlers installed.
9279 14:44:18.521662 ARM64: Testing exception
9280 14:44:18.524138 ARM64: Done test exception
9281 14:44:18.524219 Enumerating buses...
9282 14:44:18.528059 Show all devs... Before device enumeration.
9283 14:44:18.530935 Root Device: enabled 1
9284 14:44:18.534087 CPU_CLUSTER: 0: enabled 1
9285 14:44:18.534196 CPU: 00: enabled 1
9286 14:44:18.537791 Compare with tree...
9287 14:44:18.537873 Root Device: enabled 1
9288 14:44:18.540933 CPU_CLUSTER: 0: enabled 1
9289 14:44:18.543924 CPU: 00: enabled 1
9290 14:44:18.544006 Root Device scanning...
9291 14:44:18.547589 scan_static_bus for Root Device
9292 14:44:18.550622 CPU_CLUSTER: 0 enabled
9293 14:44:18.553898 scan_static_bus for Root Device done
9294 14:44:18.557195 scan_bus: bus Root Device finished in 8 msecs
9295 14:44:18.557316 done
9296 14:44:18.563832 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9297 14:44:18.567446 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9298 14:44:18.574225 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9299 14:44:18.577018 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9300 14:44:18.580684 Allocating resources...
9301 14:44:18.583623 Reading resources...
9302 14:44:18.587079 Root Device read_resources bus 0 link: 0
9303 14:44:18.590350 DRAM rank0 size:0x100000000,
9304 14:44:18.590432 DRAM rank1 size=0x100000000
9305 14:44:18.593754 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9306 14:44:18.596926 CPU: 00 missing read_resources
9307 14:44:18.603757 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9308 14:44:18.606939 Root Device read_resources bus 0 link: 0 done
9309 14:44:18.610016 Done reading resources.
9310 14:44:18.613422 Show resources in subtree (Root Device)...After reading.
9311 14:44:18.616704 Root Device child on link 0 CPU_CLUSTER: 0
9312 14:44:18.620148 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 14:44:18.629940 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 14:44:18.630023 CPU: 00
9315 14:44:18.633680 Root Device assign_resources, bus 0 link: 0
9316 14:44:18.636864 CPU_CLUSTER: 0 missing set_resources
9317 14:44:18.643017 Root Device assign_resources, bus 0 link: 0 done
9318 14:44:18.643098 Done setting resources.
9319 14:44:18.649942 Show resources in subtree (Root Device)...After assigning values.
9320 14:44:18.653188 Root Device child on link 0 CPU_CLUSTER: 0
9321 14:44:18.656411 CPU_CLUSTER: 0 child on link 0 CPU: 00
9322 14:44:18.666589 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9323 14:44:18.666672 CPU: 00
9324 14:44:18.669687 Done allocating resources.
9325 14:44:18.676385 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9326 14:44:18.676467 Enabling resources...
9327 14:44:18.676532 done.
9328 14:44:18.682897 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9329 14:44:18.686888 Initializing devices...
9330 14:44:18.686970 Root Device init
9331 14:44:18.689613 init hardware done!
9332 14:44:18.689694 0x00000018: ctrlr->caps
9333 14:44:18.692867 52.000 MHz: ctrlr->f_max
9334 14:44:18.696428 0.400 MHz: ctrlr->f_min
9335 14:44:18.696511 0x40ff8080: ctrlr->voltages
9336 14:44:18.699694 sclk: 390625
9337 14:44:18.699774 Bus Width = 1
9338 14:44:18.699839 sclk: 390625
9339 14:44:18.702995 Bus Width = 1
9340 14:44:18.703078 Early init status = 3
9341 14:44:18.709600 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9342 14:44:18.713056 in-header: 03 fc 00 00 01 00 00 00
9343 14:44:18.716552 in-data: 00
9344 14:44:18.719549 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9345 14:44:18.723431 in-header: 03 fd 00 00 00 00 00 00
9346 14:44:18.726599 in-data:
9347 14:44:18.730011 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9348 14:44:18.733377 in-header: 03 fc 00 00 01 00 00 00
9349 14:44:18.737031 in-data: 00
9350 14:44:18.739623 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9351 14:44:18.744866 in-header: 03 fd 00 00 00 00 00 00
9352 14:44:18.747917 in-data:
9353 14:44:18.751176 [SSUSB] Setting up USB HOST controller...
9354 14:44:18.754368 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9355 14:44:18.757553 [SSUSB] phy power-on done.
9356 14:44:18.760906 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9357 14:44:18.767890 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9358 14:44:18.771103 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9359 14:44:18.777677 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9360 14:44:18.784099 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9361 14:44:18.790928 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9362 14:44:18.797274 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9363 14:44:18.803815 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9364 14:44:18.807082 SPM: binary array size = 0x9dc
9365 14:44:18.810495 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9366 14:44:18.817391 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9367 14:44:18.824045 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9368 14:44:18.830068 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9369 14:44:18.833365 configure_display: Starting display init
9370 14:44:18.868103 anx7625_power_on_init: Init interface.
9371 14:44:18.871670 anx7625_disable_pd_protocol: Disabled PD feature.
9372 14:44:18.874817 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9373 14:44:18.901976 anx7625_start_dp_work: Secure OCM version=00
9374 14:44:18.904974 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9375 14:44:18.920369 sp_tx_get_edid_block: EDID Block = 1
9376 14:44:19.022540 Extracted contents:
9377 14:44:19.026604 header: 00 ff ff ff ff ff ff 00
9378 14:44:19.029481 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9379 14:44:19.032658 version: 01 04
9380 14:44:19.036227 basic params: 95 1f 11 78 0a
9381 14:44:19.039570 chroma info: 76 90 94 55 54 90 27 21 50 54
9382 14:44:19.042502 established: 00 00 00
9383 14:44:19.049144 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9384 14:44:19.052486 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9385 14:44:19.059060 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9386 14:44:19.065846 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9387 14:44:19.072336 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9388 14:44:19.076314 extensions: 00
9389 14:44:19.076395 checksum: fb
9390 14:44:19.076459
9391 14:44:19.078802 Manufacturer: IVO Model 57d Serial Number 0
9392 14:44:19.082104 Made week 0 of 2020
9393 14:44:19.085645 EDID version: 1.4
9394 14:44:19.085727 Digital display
9395 14:44:19.088760 6 bits per primary color channel
9396 14:44:19.088843 DisplayPort interface
9397 14:44:19.092112 Maximum image size: 31 cm x 17 cm
9398 14:44:19.095218 Gamma: 220%
9399 14:44:19.095299 Check DPMS levels
9400 14:44:19.101919 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9401 14:44:19.105448 First detailed timing is preferred timing
9402 14:44:19.105531 Established timings supported:
9403 14:44:19.108648 Standard timings supported:
9404 14:44:19.111982 Detailed timings
9405 14:44:19.114999 Hex of detail: 383680a07038204018303c0035ae10000019
9406 14:44:19.121398 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9407 14:44:19.125242 0780 0798 07c8 0820 hborder 0
9408 14:44:19.127955 0438 043b 0447 0458 vborder 0
9409 14:44:19.131606 -hsync -vsync
9410 14:44:19.131688 Did detailed timing
9411 14:44:19.138062 Hex of detail: 000000000000000000000000000000000000
9412 14:44:19.141400 Manufacturer-specified data, tag 0
9413 14:44:19.144640 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9414 14:44:19.147933 ASCII string: InfoVision
9415 14:44:19.151205 Hex of detail: 000000fe00523134304e574635205248200a
9416 14:44:19.154723 ASCII string: R140NWF5 RH
9417 14:44:19.154818 Checksum
9418 14:44:19.158317 Checksum: 0xfb (valid)
9419 14:44:19.161568 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9420 14:44:19.164399 DSI data_rate: 832800000 bps
9421 14:44:19.171256 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9422 14:44:19.174475 anx7625_parse_edid: pixelclock(138800).
9423 14:44:19.177763 hactive(1920), hsync(48), hfp(24), hbp(88)
9424 14:44:19.180896 vactive(1080), vsync(12), vfp(3), vbp(17)
9425 14:44:19.184330 anx7625_dsi_config: config dsi.
9426 14:44:19.191271 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9427 14:44:19.204698 anx7625_dsi_config: success to config DSI
9428 14:44:19.207851 anx7625_dp_start: MIPI phy setup OK.
9429 14:44:19.211424 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9430 14:44:19.215136 mtk_ddp_mode_set invalid vrefresh 60
9431 14:44:19.218428 main_disp_path_setup
9432 14:44:19.218510 ovl_layer_smi_id_en
9433 14:44:19.221673 ovl_layer_smi_id_en
9434 14:44:19.221754 ccorr_config
9435 14:44:19.221818 aal_config
9436 14:44:19.224759 gamma_config
9437 14:44:19.224840 postmask_config
9438 14:44:19.228108 dither_config
9439 14:44:19.231630 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9440 14:44:19.237993 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9441 14:44:19.240941 Root Device init finished in 551 msecs
9442 14:44:19.245042 CPU_CLUSTER: 0 init
9443 14:44:19.251174 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9444 14:44:19.257488 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9445 14:44:19.257569 APU_MBOX 0x190000b0 = 0x10001
9446 14:44:19.260884 APU_MBOX 0x190001b0 = 0x10001
9447 14:44:19.264437 APU_MBOX 0x190005b0 = 0x10001
9448 14:44:19.267640 APU_MBOX 0x190006b0 = 0x10001
9449 14:44:19.273790 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9450 14:44:19.283921 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9451 14:44:19.296128 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9452 14:44:19.303159 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9453 14:44:19.314762 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9454 14:44:19.323859 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9455 14:44:19.327039 CPU_CLUSTER: 0 init finished in 81 msecs
9456 14:44:19.330477 Devices initialized
9457 14:44:19.333417 Show all devs... After init.
9458 14:44:19.333498 Root Device: enabled 1
9459 14:44:19.336880 CPU_CLUSTER: 0: enabled 1
9460 14:44:19.339927 CPU: 00: enabled 1
9461 14:44:19.343664 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9462 14:44:19.346764 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9463 14:44:19.349933 ELOG: NV offset 0x57f000 size 0x1000
9464 14:44:19.356829 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9465 14:44:19.363398 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9466 14:44:19.367083 ELOG: Event(17) added with size 13 at 2024-06-04 14:44:19 UTC
9467 14:44:19.372996 out: cmd=0x121: 03 db 21 01 00 00 00 00
9468 14:44:19.376956 in-header: 03 4c 00 00 2c 00 00 00
9469 14:44:19.386509 in-data: f1 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9470 14:44:19.393009 ELOG: Event(A1) added with size 10 at 2024-06-04 14:44:19 UTC
9471 14:44:19.399532 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9472 14:44:19.406029 ELOG: Event(A0) added with size 9 at 2024-06-04 14:44:19 UTC
9473 14:44:19.409503 elog_add_boot_reason: Logged dev mode boot
9474 14:44:19.415914 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9475 14:44:19.415996 Finalize devices...
9476 14:44:19.419339 Devices finalized
9477 14:44:19.422797 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9478 14:44:19.425984 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9479 14:44:19.429149 in-header: 03 07 00 00 08 00 00 00
9480 14:44:19.433263 in-data: aa e4 47 04 13 02 00 00
9481 14:44:19.435928 Chrome EC: UHEPI supported
9482 14:44:19.442653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9483 14:44:19.446048 in-header: 03 a9 00 00 08 00 00 00
9484 14:44:19.449513 in-data: 84 60 60 08 00 00 00 00
9485 14:44:19.455632 ELOG: Event(91) added with size 10 at 2024-06-04 14:44:19 UTC
9486 14:44:19.458942 Chrome EC: clear events_b mask to 0x0000000020004000
9487 14:44:19.465626 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9488 14:44:19.469397 in-header: 03 fd 00 00 00 00 00 00
9489 14:44:19.472790 in-data:
9490 14:44:19.475970 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9491 14:44:19.479321 Writing coreboot table at 0xffe64000
9492 14:44:19.486085 0. 000000000010a000-0000000000113fff: RAMSTAGE
9493 14:44:19.489504 1. 0000000040000000-00000000400fffff: RAM
9494 14:44:19.492727 2. 0000000040100000-000000004032afff: RAMSTAGE
9495 14:44:19.495702 3. 000000004032b000-00000000545fffff: RAM
9496 14:44:19.499335 4. 0000000054600000-000000005465ffff: BL31
9497 14:44:19.506044 5. 0000000054660000-00000000ffe63fff: RAM
9498 14:44:19.509134 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9499 14:44:19.512146 7. 0000000100000000-000000023fffffff: RAM
9500 14:44:19.515418 Passing 5 GPIOs to payload:
9501 14:44:19.518773 NAME | PORT | POLARITY | VALUE
9502 14:44:19.525747 EC in RW | 0x000000aa | low | undefined
9503 14:44:19.528612 EC interrupt | 0x00000005 | low | undefined
9504 14:44:19.535261 TPM interrupt | 0x000000ab | high | undefined
9505 14:44:19.538514 SD card detect | 0x00000011 | high | undefined
9506 14:44:19.545184 speaker enable | 0x00000093 | high | undefined
9507 14:44:19.548685 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9508 14:44:19.551787 in-header: 03 f9 00 00 02 00 00 00
9509 14:44:19.551869 in-data: 02 00
9510 14:44:19.555197 ADC[4]: Raw value=901922 ID=7
9511 14:44:19.558623 ADC[3]: Raw value=214021 ID=1
9512 14:44:19.558704 RAM Code: 0x71
9513 14:44:19.562397 ADC[6]: Raw value=75036 ID=0
9514 14:44:19.564890 ADC[5]: Raw value=213652 ID=1
9515 14:44:19.564971 SKU Code: 0x1
9516 14:44:19.571722 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3031
9517 14:44:19.574756 coreboot table: 964 bytes.
9518 14:44:19.578016 IMD ROOT 0. 0xfffff000 0x00001000
9519 14:44:19.581543 IMD SMALL 1. 0xffffe000 0x00001000
9520 14:44:19.584907 RO MCACHE 2. 0xffffc000 0x00001104
9521 14:44:19.587960 CONSOLE 3. 0xfff7c000 0x00080000
9522 14:44:19.591740 FMAP 4. 0xfff7b000 0x00000452
9523 14:44:19.594801 TIME STAMP 5. 0xfff7a000 0x00000910
9524 14:44:19.598294 VBOOT WORK 6. 0xfff66000 0x00014000
9525 14:44:19.601628 RAMOOPS 7. 0xffe66000 0x00100000
9526 14:44:19.601710 COREBOOT 8. 0xffe64000 0x00002000
9527 14:44:19.604839 IMD small region:
9528 14:44:19.608370 IMD ROOT 0. 0xffffec00 0x00000400
9529 14:44:19.611077 VPD 1. 0xffffeb80 0x0000006c
9530 14:44:19.614619 MMC STATUS 2. 0xffffeb60 0x00000004
9531 14:44:19.621203 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9532 14:44:19.627459 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9533 14:44:19.666871 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9534 14:44:19.670028 Checking segment from ROM address 0x40100000
9535 14:44:19.673680 Checking segment from ROM address 0x4010001c
9536 14:44:19.679710 Loading segment from ROM address 0x40100000
9537 14:44:19.679793 code (compression=0)
9538 14:44:19.689604 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9539 14:44:19.696289 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9540 14:44:19.696376 it's not compressed!
9541 14:44:19.703102 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9542 14:44:19.709692 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9543 14:44:19.727146 Loading segment from ROM address 0x4010001c
9544 14:44:19.727269 Entry Point 0x80000000
9545 14:44:19.730271 Loaded segments
9546 14:44:19.733474 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9547 14:44:19.739910 Jumping to boot code at 0x80000000(0xffe64000)
9548 14:44:19.746855 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9549 14:44:19.753992 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9550 14:44:19.761156 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9551 14:44:19.764889 Checking segment from ROM address 0x40100000
9552 14:44:19.767897 Checking segment from ROM address 0x4010001c
9553 14:44:19.774751 Loading segment from ROM address 0x40100000
9554 14:44:19.774834 code (compression=1)
9555 14:44:19.781230 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9556 14:44:19.790992 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9557 14:44:19.791078 using LZMA
9558 14:44:19.800075 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9559 14:44:19.806199 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9560 14:44:19.809493 Loading segment from ROM address 0x4010001c
9561 14:44:19.809574 Entry Point 0x54601000
9562 14:44:19.812908 Loaded segments
9563 14:44:19.816389 NOTICE: MT8192 bl31_setup
9564 14:44:19.823573 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9565 14:44:19.826837 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9566 14:44:19.830461 WARNING: region 0:
9567 14:44:19.833238 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9568 14:44:19.833319 WARNING: region 1:
9569 14:44:19.839974 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9570 14:44:19.843041 WARNING: region 2:
9571 14:44:19.846713 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9572 14:44:19.849682 WARNING: region 3:
9573 14:44:19.853225 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9574 14:44:19.856906 WARNING: region 4:
9575 14:44:19.862715 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9576 14:44:19.862797 WARNING: region 5:
9577 14:44:19.866142 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 14:44:19.869591 WARNING: region 6:
9579 14:44:19.872887 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 14:44:19.876241 WARNING: region 7:
9581 14:44:19.879703 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9582 14:44:19.885943 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9583 14:44:19.889529 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9584 14:44:19.895691 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9585 14:44:19.899154 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9586 14:44:19.902298 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9587 14:44:19.909129 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9588 14:44:19.911921 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9589 14:44:19.915348 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9590 14:44:19.922597 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9591 14:44:19.925276 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9592 14:44:19.932254 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9593 14:44:19.935183 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9594 14:44:19.938643 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9595 14:44:19.945544 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9596 14:44:19.948765 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9597 14:44:19.952293 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9598 14:44:19.958739 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9599 14:44:19.961791 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9600 14:44:19.968510 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9601 14:44:19.971988 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9602 14:44:19.974956 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9603 14:44:19.982104 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9604 14:44:19.985343 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9605 14:44:19.992128 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9606 14:44:19.994843 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9607 14:44:20.001382 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9608 14:44:20.005545 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9609 14:44:20.008336 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9610 14:44:20.014739 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9611 14:44:20.018047 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9612 14:44:20.024553 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9613 14:44:20.027735 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9614 14:44:20.030985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9615 14:44:20.034822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9616 14:44:20.040932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9617 14:44:20.044188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9618 14:44:20.047517 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9619 14:44:20.050837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9620 14:44:20.058016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9621 14:44:20.060912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9622 14:44:20.064096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9623 14:44:20.067630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9624 14:44:20.074546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9625 14:44:20.077631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9626 14:44:20.081269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9627 14:44:20.087921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9628 14:44:20.090912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9629 14:44:20.093953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9630 14:44:20.100837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9631 14:44:20.103960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9632 14:44:20.106918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9633 14:44:20.114030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9634 14:44:20.116885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9635 14:44:20.123817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9636 14:44:20.127330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9637 14:44:20.133548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9638 14:44:20.137546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9639 14:44:20.140371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9640 14:44:20.147137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9641 14:44:20.150075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9642 14:44:20.156841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9643 14:44:20.160299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9644 14:44:20.167269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9645 14:44:20.170186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9646 14:44:20.176579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9647 14:44:20.180162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9648 14:44:20.186681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9649 14:44:20.190152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9650 14:44:20.193111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9651 14:44:20.199562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9652 14:44:20.202971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9653 14:44:20.209560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9654 14:44:20.213011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9655 14:44:20.219703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9656 14:44:20.222869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9657 14:44:20.229562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9658 14:44:20.232549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9659 14:44:20.236040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9660 14:44:20.242532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9661 14:44:20.245775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9662 14:44:20.252635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9663 14:44:20.256197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9664 14:44:20.262632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9665 14:44:20.265769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9666 14:44:20.272066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9667 14:44:20.275554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9668 14:44:20.278695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9669 14:44:20.285675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9670 14:44:20.288814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9671 14:44:20.295669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9672 14:44:20.299048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9673 14:44:20.305018 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9674 14:44:20.308378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9675 14:44:20.315401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9676 14:44:20.318799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9677 14:44:20.324813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9678 14:44:20.328214 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9679 14:44:20.331613 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9680 14:44:20.334782 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9681 14:44:20.341552 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9682 14:44:20.344826 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9683 14:44:20.348464 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9684 14:44:20.354568 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9685 14:44:20.358038 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9686 14:44:20.364904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9687 14:44:20.367822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9688 14:44:20.371376 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9689 14:44:20.378060 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9690 14:44:20.381089 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9691 14:44:20.388244 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9692 14:44:20.391096 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9693 14:44:20.394384 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9694 14:44:20.401428 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9695 14:44:20.404215 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9696 14:44:20.411232 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9697 14:44:20.414376 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9698 14:44:20.417765 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9699 14:44:20.421027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9700 14:44:20.427598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9701 14:44:20.431241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9702 14:44:20.433951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9703 14:44:20.440712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9704 14:44:20.444027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9705 14:44:20.447340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9706 14:44:20.453651 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9707 14:44:20.457040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9708 14:44:20.460176 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9709 14:44:20.466773 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9710 14:44:20.470593 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9711 14:44:20.476753 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9712 14:44:20.479893 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9713 14:44:20.483252 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9714 14:44:20.490287 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9715 14:44:20.493495 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9716 14:44:20.499698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9717 14:44:20.503224 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9718 14:44:20.506987 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9719 14:44:20.513502 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9720 14:44:20.516445 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9721 14:44:20.523169 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9722 14:44:20.526647 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9723 14:44:20.530081 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9724 14:44:20.536173 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9725 14:44:20.539471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9726 14:44:20.543164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9727 14:44:20.549756 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9728 14:44:20.553255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9729 14:44:20.559500 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9730 14:44:20.562893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9731 14:44:20.569457 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9732 14:44:20.573048 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9733 14:44:20.576266 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9734 14:44:20.582583 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9735 14:44:20.585845 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9736 14:44:20.589135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9737 14:44:20.596084 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9738 14:44:20.599693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9739 14:44:20.605645 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9740 14:44:20.609235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9741 14:44:20.612268 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9742 14:44:20.618941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9743 14:44:20.622858 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9744 14:44:20.629026 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9745 14:44:20.632650 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9746 14:44:20.635888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9747 14:44:20.642568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9748 14:44:20.645734 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9749 14:44:20.652431 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9750 14:44:20.655538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9751 14:44:20.659164 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9752 14:44:20.665594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9753 14:44:20.669140 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9754 14:44:20.672391 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9755 14:44:20.678953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9756 14:44:20.682048 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9757 14:44:20.689145 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9758 14:44:20.692286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9759 14:44:20.695362 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9760 14:44:20.702434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9761 14:44:20.705332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9762 14:44:20.711945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9763 14:44:20.715181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9764 14:44:20.718539 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9765 14:44:20.725322 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9766 14:44:20.728630 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9767 14:44:20.735279 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9768 14:44:20.738488 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9769 14:44:20.741846 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9770 14:44:20.748787 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9771 14:44:20.751602 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9772 14:44:20.758393 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9773 14:44:20.761871 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9774 14:44:20.768439 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9775 14:44:20.771597 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9776 14:44:20.774705 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9777 14:44:20.781222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9778 14:44:20.784754 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9779 14:44:20.791358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9780 14:44:20.794683 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9781 14:44:20.801389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9782 14:44:20.804361 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9783 14:44:20.807981 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9784 14:44:20.814447 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9785 14:44:20.818098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9786 14:44:20.824795 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9787 14:44:20.827920 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9788 14:44:20.831240 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9789 14:44:20.837802 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9790 14:44:20.840843 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9791 14:44:20.847334 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9792 14:44:20.850658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9793 14:44:20.857703 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9794 14:44:20.861236 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9795 14:44:20.864198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9796 14:44:20.870722 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9797 14:44:20.874392 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9798 14:44:20.880397 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9799 14:44:20.884246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9800 14:44:20.890531 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9801 14:44:20.894222 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9802 14:44:20.897083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9803 14:44:20.903582 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9804 14:44:20.907134 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9805 14:44:20.913882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9806 14:44:20.917067 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9807 14:44:20.920388 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9808 14:44:20.926881 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9809 14:44:20.930279 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9810 14:44:20.937254 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9811 14:44:20.940623 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9812 14:44:20.943418 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9813 14:44:20.946953 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9814 14:44:20.953431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9815 14:44:20.956789 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9816 14:44:20.959952 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9817 14:44:20.966454 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9818 14:44:20.969903 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9819 14:44:20.974293 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9820 14:44:20.979661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9821 14:44:20.983174 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9822 14:44:20.989448 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9823 14:44:20.992905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9824 14:44:20.996397 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9825 14:44:21.003099 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9826 14:44:21.006321 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9827 14:44:21.009474 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9828 14:44:21.016414 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9829 14:44:21.019102 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9830 14:44:21.022791 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9831 14:44:21.029412 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9832 14:44:21.032262 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9833 14:44:21.038896 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9834 14:44:21.042593 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9835 14:44:21.045589 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9836 14:44:21.052374 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9837 14:44:21.055459 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9838 14:44:21.059204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9839 14:44:21.065534 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9840 14:44:21.069238 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9841 14:44:21.075953 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9842 14:44:21.078820 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9843 14:44:21.082034 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9844 14:44:21.088718 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9845 14:44:21.092515 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9846 14:44:21.095184 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9847 14:44:21.101884 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9848 14:44:21.105352 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9849 14:44:21.112297 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9850 14:44:21.115433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9851 14:44:21.118334 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9852 14:44:21.121883 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9853 14:44:21.128094 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9854 14:44:21.131772 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9855 14:44:21.135009 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9856 14:44:21.138468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9857 14:44:21.145376 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9858 14:44:21.148408 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9859 14:44:21.151398 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9860 14:44:21.155259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9861 14:44:21.161630 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9862 14:44:21.164774 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9863 14:44:21.168040 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9864 14:44:21.174861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9865 14:44:21.177700 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9866 14:44:21.181226 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9867 14:44:21.187815 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9868 14:44:21.191064 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9869 14:44:21.197823 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9870 14:44:21.201243 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9871 14:44:21.204755 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9872 14:44:21.210956 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9873 14:44:21.214512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9874 14:44:21.220895 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9875 14:44:21.223992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9876 14:44:21.230684 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9877 14:44:21.234171 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9878 14:44:21.240541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9879 14:44:21.243570 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9880 14:44:21.247001 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9881 14:44:21.253727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9882 14:44:21.256888 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9883 14:44:21.263320 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9884 14:44:21.266860 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9885 14:44:21.273292 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9886 14:44:21.276607 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9887 14:44:21.280158 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9888 14:44:21.286562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9889 14:44:21.290278 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9890 14:44:21.293397 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9891 14:44:21.300405 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9892 14:44:21.303144 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9893 14:44:21.309901 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9894 14:44:21.313378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9895 14:44:21.319871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9896 14:44:21.323083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9897 14:44:21.326348 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9898 14:44:21.333254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9899 14:44:21.336400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9900 14:44:21.343184 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9901 14:44:21.346024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9902 14:44:21.352605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9903 14:44:21.355947 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9904 14:44:21.359233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9905 14:44:21.366331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9906 14:44:21.369437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9907 14:44:21.376124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9908 14:44:21.379445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9909 14:44:21.382826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9910 14:44:21.389029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9911 14:44:21.392618 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9912 14:44:21.398900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9913 14:44:21.402474 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9914 14:44:21.405924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9915 14:44:21.412245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9916 14:44:21.415630 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9917 14:44:21.422007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9918 14:44:21.425594 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9919 14:44:21.429317 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9920 14:44:21.435193 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9921 14:44:21.438673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9922 14:44:21.445072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9923 14:44:21.448704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9924 14:44:21.454986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9925 14:44:21.458467 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9926 14:44:21.464874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9927 14:44:21.468121 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9928 14:44:21.471317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9929 14:44:21.478529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9930 14:44:21.481407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9931 14:44:21.488383 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9932 14:44:21.492173 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9933 14:44:21.495167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9934 14:44:21.501541 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9935 14:44:21.504961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9936 14:44:21.511498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9937 14:44:21.514918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9938 14:44:21.517888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9939 14:44:21.524339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9940 14:44:21.527687 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9941 14:44:21.534844 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9942 14:44:21.537899 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9943 14:44:21.544478 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9944 14:44:21.547483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9945 14:44:21.554320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9946 14:44:21.557502 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9947 14:44:21.561187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9948 14:44:21.567415 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9949 14:44:21.571239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9950 14:44:21.577312 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9951 14:44:21.580627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9952 14:44:21.587128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9953 14:44:21.590445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9954 14:44:21.597348 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9955 14:44:21.600686 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9956 14:44:21.603695 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9957 14:44:21.610658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9958 14:44:21.613920 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9959 14:44:21.620903 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9960 14:44:21.623598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9961 14:44:21.630511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9962 14:44:21.633866 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9963 14:44:21.636838 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9964 14:44:21.643535 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9965 14:44:21.646901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9966 14:44:21.653647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9967 14:44:21.657140 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9968 14:44:21.663420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9969 14:44:21.666730 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9970 14:44:21.673242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9971 14:44:21.676705 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9972 14:44:21.683623 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9973 14:44:21.686557 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9974 14:44:21.689578 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9975 14:44:21.696409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9976 14:44:21.699871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9977 14:44:21.706195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9978 14:44:21.710154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9979 14:44:21.716444 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9980 14:44:21.719404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9981 14:44:21.722993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9982 14:44:21.729998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9983 14:44:21.733035 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9984 14:44:21.739920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9985 14:44:21.742681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9986 14:44:21.746489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9987 14:44:21.752799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9988 14:44:21.756401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9989 14:44:21.762782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9990 14:44:21.766281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9991 14:44:21.772903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9992 14:44:21.776201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9993 14:44:21.782958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9994 14:44:21.786253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9995 14:44:21.792564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9996 14:44:21.796432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9997 14:44:21.802931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9998 14:44:21.805934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9999 14:44:21.812677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10000 14:44:21.815693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10001 14:44:21.822845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10002 14:44:21.825652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10003 14:44:21.832537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10004 14:44:21.835656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10005 14:44:21.842157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10006 14:44:21.845903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10007 14:44:21.852007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10008 14:44:21.855154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10009 14:44:21.861660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10010 14:44:21.865021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10011 14:44:21.871845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10012 14:44:21.874903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10013 14:44:21.881687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10014 14:44:21.884796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10015 14:44:21.891715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10016 14:44:21.894890 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10017 14:44:21.898155 INFO: [APUAPC] vio 0
10018 14:44:21.901325 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10019 14:44:21.908230 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10020 14:44:21.911346 INFO: [APUAPC] D0_APC_0: 0x400510
10021 14:44:21.914307 INFO: [APUAPC] D0_APC_1: 0x0
10022 14:44:21.914389 INFO: [APUAPC] D0_APC_2: 0x1540
10023 14:44:21.918054 INFO: [APUAPC] D0_APC_3: 0x0
10024 14:44:21.921229 INFO: [APUAPC] D1_APC_0: 0xffffffff
10025 14:44:21.924638 INFO: [APUAPC] D1_APC_1: 0xffffffff
10026 14:44:21.927571 INFO: [APUAPC] D1_APC_2: 0x3fffff
10027 14:44:21.931448 INFO: [APUAPC] D1_APC_3: 0x0
10028 14:44:21.934276 INFO: [APUAPC] D2_APC_0: 0xffffffff
10029 14:44:21.937583 INFO: [APUAPC] D2_APC_1: 0xffffffff
10030 14:44:21.941109 INFO: [APUAPC] D2_APC_2: 0x3fffff
10031 14:44:21.944177 INFO: [APUAPC] D2_APC_3: 0x0
10032 14:44:21.947440 INFO: [APUAPC] D3_APC_0: 0xffffffff
10033 14:44:21.950689 INFO: [APUAPC] D3_APC_1: 0xffffffff
10034 14:44:21.954468 INFO: [APUAPC] D3_APC_2: 0x3fffff
10035 14:44:21.957889 INFO: [APUAPC] D3_APC_3: 0x0
10036 14:44:21.961310 INFO: [APUAPC] D4_APC_0: 0xffffffff
10037 14:44:21.964392 INFO: [APUAPC] D4_APC_1: 0xffffffff
10038 14:44:21.967531 INFO: [APUAPC] D4_APC_2: 0x3fffff
10039 14:44:21.970677 INFO: [APUAPC] D4_APC_3: 0x0
10040 14:44:21.974127 INFO: [APUAPC] D5_APC_0: 0xffffffff
10041 14:44:21.977208 INFO: [APUAPC] D5_APC_1: 0xffffffff
10042 14:44:21.980728 INFO: [APUAPC] D5_APC_2: 0x3fffff
10043 14:44:21.983786 INFO: [APUAPC] D5_APC_3: 0x0
10044 14:44:21.987132 INFO: [APUAPC] D6_APC_0: 0xffffffff
10045 14:44:21.990273 INFO: [APUAPC] D6_APC_1: 0xffffffff
10046 14:44:21.993691 INFO: [APUAPC] D6_APC_2: 0x3fffff
10047 14:44:21.997173 INFO: [APUAPC] D6_APC_3: 0x0
10048 14:44:22.000307 INFO: [APUAPC] D7_APC_0: 0xffffffff
10049 14:44:22.003855 INFO: [APUAPC] D7_APC_1: 0xffffffff
10050 14:44:22.006792 INFO: [APUAPC] D7_APC_2: 0x3fffff
10051 14:44:22.010000 INFO: [APUAPC] D7_APC_3: 0x0
10052 14:44:22.013200 INFO: [APUAPC] D8_APC_0: 0xffffffff
10053 14:44:22.016519 INFO: [APUAPC] D8_APC_1: 0xffffffff
10054 14:44:22.019874 INFO: [APUAPC] D8_APC_2: 0x3fffff
10055 14:44:22.023725 INFO: [APUAPC] D8_APC_3: 0x0
10056 14:44:22.026917 INFO: [APUAPC] D9_APC_0: 0xffffffff
10057 14:44:22.030123 INFO: [APUAPC] D9_APC_1: 0xffffffff
10058 14:44:22.033969 INFO: [APUAPC] D9_APC_2: 0x3fffff
10059 14:44:22.036426 INFO: [APUAPC] D9_APC_3: 0x0
10060 14:44:22.039933 INFO: [APUAPC] D10_APC_0: 0xffffffff
10061 14:44:22.043334 INFO: [APUAPC] D10_APC_1: 0xffffffff
10062 14:44:22.046389 INFO: [APUAPC] D10_APC_2: 0x3fffff
10063 14:44:22.049744 INFO: [APUAPC] D10_APC_3: 0x0
10064 14:44:22.053392 INFO: [APUAPC] D11_APC_0: 0xffffffff
10065 14:44:22.056439 INFO: [APUAPC] D11_APC_1: 0xffffffff
10066 14:44:22.059780 INFO: [APUAPC] D11_APC_2: 0x3fffff
10067 14:44:22.062872 INFO: [APUAPC] D11_APC_3: 0x0
10068 14:44:22.066646 INFO: [APUAPC] D12_APC_0: 0xffffffff
10069 14:44:22.069802 INFO: [APUAPC] D12_APC_1: 0xffffffff
10070 14:44:22.072958 INFO: [APUAPC] D12_APC_2: 0x3fffff
10071 14:44:22.076522 INFO: [APUAPC] D12_APC_3: 0x0
10072 14:44:22.079440 INFO: [APUAPC] D13_APC_0: 0xffffffff
10073 14:44:22.082856 INFO: [APUAPC] D13_APC_1: 0xffffffff
10074 14:44:22.086111 INFO: [APUAPC] D13_APC_2: 0x3fffff
10075 14:44:22.089572 INFO: [APUAPC] D13_APC_3: 0x0
10076 14:44:22.092586 INFO: [APUAPC] D14_APC_0: 0xffffffff
10077 14:44:22.096234 INFO: [APUAPC] D14_APC_1: 0xffffffff
10078 14:44:22.099429 INFO: [APUAPC] D14_APC_2: 0x3fffff
10079 14:44:22.102937 INFO: [APUAPC] D14_APC_3: 0x0
10080 14:44:22.105992 INFO: [APUAPC] D15_APC_0: 0xffffffff
10081 14:44:22.108969 INFO: [APUAPC] D15_APC_1: 0xffffffff
10082 14:44:22.112337 INFO: [APUAPC] D15_APC_2: 0x3fffff
10083 14:44:22.115980 INFO: [APUAPC] D15_APC_3: 0x0
10084 14:44:22.119094 INFO: [APUAPC] APC_CON: 0x4
10085 14:44:22.122764 INFO: [NOCDAPC] D0_APC_0: 0x0
10086 14:44:22.126065 INFO: [NOCDAPC] D0_APC_1: 0x0
10087 14:44:22.129377 INFO: [NOCDAPC] D1_APC_0: 0x0
10088 14:44:22.132527 INFO: [NOCDAPC] D1_APC_1: 0xfff
10089 14:44:22.132608 INFO: [NOCDAPC] D2_APC_0: 0x0
10090 14:44:22.135611 INFO: [NOCDAPC] D2_APC_1: 0xfff
10091 14:44:22.139169 INFO: [NOCDAPC] D3_APC_0: 0x0
10092 14:44:22.142291 INFO: [NOCDAPC] D3_APC_1: 0xfff
10093 14:44:22.145382 INFO: [NOCDAPC] D4_APC_0: 0x0
10094 14:44:22.149205 INFO: [NOCDAPC] D4_APC_1: 0xfff
10095 14:44:22.152561 INFO: [NOCDAPC] D5_APC_0: 0x0
10096 14:44:22.155279 INFO: [NOCDAPC] D5_APC_1: 0xfff
10097 14:44:22.158646 INFO: [NOCDAPC] D6_APC_0: 0x0
10098 14:44:22.161976 INFO: [NOCDAPC] D6_APC_1: 0xfff
10099 14:44:22.165585 INFO: [NOCDAPC] D7_APC_0: 0x0
10100 14:44:22.165665 INFO: [NOCDAPC] D7_APC_1: 0xfff
10101 14:44:22.168719 INFO: [NOCDAPC] D8_APC_0: 0x0
10102 14:44:22.172032 INFO: [NOCDAPC] D8_APC_1: 0xfff
10103 14:44:22.175371 INFO: [NOCDAPC] D9_APC_0: 0x0
10104 14:44:22.178580 INFO: [NOCDAPC] D9_APC_1: 0xfff
10105 14:44:22.181859 INFO: [NOCDAPC] D10_APC_0: 0x0
10106 14:44:22.185443 INFO: [NOCDAPC] D10_APC_1: 0xfff
10107 14:44:22.188763 INFO: [NOCDAPC] D11_APC_0: 0x0
10108 14:44:22.191857 INFO: [NOCDAPC] D11_APC_1: 0xfff
10109 14:44:22.195366 INFO: [NOCDAPC] D12_APC_0: 0x0
10110 14:44:22.198677 INFO: [NOCDAPC] D12_APC_1: 0xfff
10111 14:44:22.202064 INFO: [NOCDAPC] D13_APC_0: 0x0
10112 14:44:22.205285 INFO: [NOCDAPC] D13_APC_1: 0xfff
10113 14:44:22.208925 INFO: [NOCDAPC] D14_APC_0: 0x0
10114 14:44:22.209032 INFO: [NOCDAPC] D14_APC_1: 0xfff
10115 14:44:22.211957 INFO: [NOCDAPC] D15_APC_0: 0x0
10116 14:44:22.214933 INFO: [NOCDAPC] D15_APC_1: 0xfff
10117 14:44:22.218272 INFO: [NOCDAPC] APC_CON: 0x4
10118 14:44:22.221732 INFO: [APUAPC] set_apusys_apc done
10119 14:44:22.225071 INFO: [DEVAPC] devapc_init done
10120 14:44:22.228555 INFO: GICv3 without legacy support detected.
10121 14:44:22.234937 INFO: ARM GICv3 driver initialized in EL3
10122 14:44:22.238420 INFO: Maximum SPI INTID supported: 639
10123 14:44:22.241351 INFO: BL31: Initializing runtime services
10124 14:44:22.247951 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10125 14:44:22.251907 INFO: SPM: enable CPC mode
10126 14:44:22.254564 INFO: mcdi ready for mcusys-off-idle and system suspend
10127 14:44:22.261568 INFO: BL31: Preparing for EL3 exit to normal world
10128 14:44:22.264562 INFO: Entry point address = 0x80000000
10129 14:44:22.264644 INFO: SPSR = 0x8
10130 14:44:22.271726
10131 14:44:22.271807
10132 14:44:22.271870
10133 14:44:22.274285 Starting depthcharge on Spherion...
10134 14:44:22.274366
10135 14:44:22.274430 Wipe memory regions:
10136 14:44:22.274490
10137 14:44:22.275116 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10138 14:44:22.275245 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10139 14:44:22.275341 Setting prompt string to ['asurada:']
10140 14:44:22.275420 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10141 14:44:22.277908 [0x00000040000000, 0x00000054600000)
10142 14:44:22.399862
10143 14:44:22.399993 [0x00000054660000, 0x00000080000000)
10144 14:44:22.660539
10145 14:44:22.660684 [0x000000821a7280, 0x000000ffe64000)
10146 14:44:23.404274
10147 14:44:23.404456 [0x00000100000000, 0x00000240000000)
10148 14:44:25.291789
10149 14:44:25.295012 Initializing XHCI USB controller at 0x11200000.
10150 14:44:26.333279
10151 14:44:26.336729 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10152 14:44:26.336821
10153 14:44:26.336886
10154 14:44:26.337172 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10156 14:44:26.437465 asurada: tftpboot 192.168.201.1 14166996/tftp-deploy-z467xwy8/kernel/image.itb 14166996/tftp-deploy-z467xwy8/kernel/cmdline
10157 14:44:26.437608 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10158 14:44:26.437720 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10159 14:44:26.441791 tftpboot 192.168.201.1 14166996/tftp-deploy-z467xwy8/kernel/image.ittp-deploy-z467xwy8/kernel/cmdline
10160 14:44:26.441875
10161 14:44:26.441945 Waiting for link
10162 14:44:26.600091
10163 14:44:26.600226 R8152: Initializing
10164 14:44:26.600295
10165 14:44:26.603135 Version 6 (ocp_data = 5c30)
10166 14:44:26.603213
10167 14:44:26.606804 R8152: Done initializing
10168 14:44:26.606885
10169 14:44:26.606949 Adding net device
10170 14:44:28.512272
10171 14:44:28.512420 done.
10172 14:44:28.512485
10173 14:44:28.512545 MAC: 00:e0:4c:68:02:81
10174 14:44:28.512603
10175 14:44:28.515519 Sending DHCP discover... done.
10176 14:44:28.515601
10177 14:44:38.491312 Waiting for reply... R8152: Bulk read error 0xffffffbf
10178 14:44:38.491803
10179 14:44:38.494591 Receive failed.
10180 14:44:38.495005
10181 14:44:38.495332 done.
10182 14:44:38.495744
10183 14:44:38.497902 Sending DHCP request... done.
10184 14:44:38.498436
10185 14:44:38.501129 Waiting for reply... done.
10186 14:44:38.501543
10187 14:44:38.501994 My ip is 192.168.201.14
10188 14:44:38.504454
10189 14:44:38.504944 The DHCP server ip is 192.168.201.1
10190 14:44:38.507708
10191 14:44:38.511020 TFTP server IP predefined by user: 192.168.201.1
10192 14:44:38.511532
10193 14:44:38.517451 Bootfile predefined by user: 14166996/tftp-deploy-z467xwy8/kernel/image.itb
10194 14:44:38.517873
10195 14:44:38.520681 Sending tftp read request... done.
10196 14:44:38.521099
10197 14:44:38.528058 Waiting for the transfer...
10198 14:44:38.528481
10199 14:44:39.141181 00000000 ################################################################
10200 14:44:39.141324
10201 14:44:39.727603 00080000 ################################################################
10202 14:44:39.727736
10203 14:44:40.307111 00100000 ################################################################
10204 14:44:40.307242
10205 14:44:40.936042 00180000 ################################################################
10206 14:44:40.936181
10207 14:44:41.586457 00200000 ################################################################
10208 14:44:41.586978
10209 14:44:42.276369 00280000 ################################################################
10210 14:44:42.277025
10211 14:44:42.906531 00300000 ################################################################
10212 14:44:42.907051
10213 14:44:43.505599 00380000 ################################################################
10214 14:44:43.505835
10215 14:44:44.053324 00400000 ################################################################
10216 14:44:44.053476
10217 14:44:44.597209 00480000 ################################################################
10218 14:44:44.597355
10219 14:44:45.130033 00500000 ################################################################
10220 14:44:45.130196
10221 14:44:45.711936 00580000 ################################################################
10222 14:44:45.712448
10223 14:44:46.384685 00600000 ################################################################
10224 14:44:46.385426
10225 14:44:47.022597 00680000 ################################################################
10226 14:44:47.023128
10227 14:44:47.687409 00700000 ################################################################
10228 14:44:47.687931
10229 14:44:48.272543 00780000 ################################################################
10230 14:44:48.272688
10231 14:44:48.916092 00800000 ################################################################
10232 14:44:48.916267
10233 14:44:49.576841 00880000 ################################################################
10234 14:44:49.576989
10235 14:44:50.178688 00900000 ################################################################
10236 14:44:50.178834
10237 14:44:50.745750 00980000 ################################################################
10238 14:44:50.745903
10239 14:44:51.311260 00a00000 ################################################################
10240 14:44:51.311398
10241 14:44:51.868490 00a80000 ################################################################
10242 14:44:51.868631
10243 14:44:52.457018 00b00000 ################################################################
10244 14:44:52.457168
10245 14:44:53.072355 00b80000 ################################################################
10246 14:44:53.072871
10247 14:44:53.736897 00c00000 ################################################################
10248 14:44:53.737589
10249 14:44:54.325698 00c80000 ################################################################
10250 14:44:54.325835
10251 14:44:54.867737 00d00000 ################################################################
10252 14:44:54.867906
10253 14:44:55.455154 00d80000 ################################################################
10254 14:44:55.455318
10255 14:44:56.058452 00e00000 ################################################################
10256 14:44:56.059174
10257 14:44:56.718964 00e80000 ################################################################
10258 14:44:56.719545
10259 14:44:57.418687 00f00000 ################################################################
10260 14:44:57.419240
10261 14:44:58.125364 00f80000 ################################################################
10262 14:44:58.125913
10263 14:44:58.823720 01000000 ################################################################
10264 14:44:58.824235
10265 14:44:59.537900 01080000 ################################################################
10266 14:44:59.538926
10267 14:45:00.242857 01100000 ################################################################
10268 14:45:00.243364
10269 14:45:00.934809 01180000 ################################################################
10270 14:45:00.935407
10271 14:45:01.629744 01200000 ################################################################
10272 14:45:01.630378
10273 14:45:02.341641 01280000 ################################################################
10274 14:45:02.342135
10275 14:45:03.048217 01300000 ################################################################
10276 14:45:03.048505
10277 14:45:03.711240 01380000 ################################################################
10278 14:45:03.711617
10279 14:45:04.343391 01400000 ################################################################
10280 14:45:04.343541
10281 14:45:04.892791 01480000 ################################################################
10282 14:45:04.892928
10283 14:45:05.466968 01500000 ################################################################
10284 14:45:05.467143
10285 14:45:06.126537 01580000 ################################################################
10286 14:45:06.127052
10287 14:45:06.833961 01600000 ################################################################
10288 14:45:06.834545
10289 14:45:07.549913 01680000 ################################################################
10290 14:45:07.550458
10291 14:45:08.239047 01700000 ################################################################
10292 14:45:08.239725
10293 14:45:08.940776 01780000 ################################################################
10294 14:45:08.941365
10295 14:45:09.638994 01800000 ################################################################
10296 14:45:09.639497
10297 14:45:10.343543 01880000 ################################################################
10298 14:45:10.344065
10299 14:45:11.034141 01900000 ################################################################
10300 14:45:11.034700
10301 14:45:11.736483 01980000 ################################################################
10302 14:45:11.737114
10303 14:45:12.450423 01a00000 ################################################################
10304 14:45:12.450935
10305 14:45:13.140995 01a80000 ################################################################
10306 14:45:13.141494
10307 14:45:13.813885 01b00000 ################################################################
10308 14:45:13.814535
10309 14:45:14.520817 01b80000 ################################################################
10310 14:45:14.521337
10311 14:45:15.211255 01c00000 ################################################################
10312 14:45:15.211899
10313 14:45:15.880617 01c80000 ################################################################
10314 14:45:15.881152
10315 14:45:16.586956 01d00000 ################################################################
10316 14:45:16.587485
10317 14:45:17.287233 01d80000 ################################################################
10318 14:45:17.287746
10319 14:45:17.786439 01e00000 ################################################ done.
10320 14:45:17.786977
10321 14:45:17.790422 The bootfile was 31843762 bytes long.
10322 14:45:17.790814
10323 14:45:17.792834 Sending tftp read request... done.
10324 14:45:17.793314
10325 14:45:17.795949 Waiting for the transfer...
10326 14:45:17.796516
10327 14:45:17.799465 00000000 # done.
10328 14:45:17.799892
10329 14:45:17.806108 Command line loaded dynamically from TFTP file: 14166996/tftp-deploy-z467xwy8/kernel/cmdline
10330 14:45:17.806819
10331 14:45:17.829092 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10332 14:45:17.829534
10333 14:45:17.829826 Loading FIT.
10334 14:45:17.830250
10335 14:45:17.832342 Image ramdisk-1 has 18733849 bytes.
10336 14:45:17.832777
10337 14:45:17.835473 Image fdt-1 has 47258 bytes.
10338 14:45:17.835716
10339 14:45:17.838934 Image kernel-1 has 13060619 bytes.
10340 14:45:17.839130
10341 14:45:17.848890 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 14:45:17.849151
10343 14:45:17.865388 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 14:45:17.865591
10345 14:45:17.868548 Choosing best match conf-1 for compat google,spherion-rev2.
10346 14:45:17.874105
10347 14:45:17.878232 Connected to device vid:did:rid of 1ae0:0028:00
10348 14:45:17.885495
10349 14:45:17.888705 tpm_get_response: command 0x17b, return code 0x0
10350 14:45:17.888809
10351 14:45:17.891901 ec_init: CrosEC protocol v3 supported (256, 248)
10352 14:45:17.896010
10353 14:45:17.899447 tpm_cleanup: add release locality here.
10354 14:45:17.899522
10355 14:45:17.899584 Shutting down all USB controllers.
10356 14:45:17.902738
10357 14:45:17.902807 Removing current net device
10358 14:45:17.902866
10359 14:45:17.909318 Exiting depthcharge with code 4 at timestamp: 85059652
10360 14:45:17.909391
10361 14:45:17.912757 LZMA decompressing kernel-1 to 0x821a6718
10362 14:45:17.912854
10363 14:45:17.915571 LZMA decompressing kernel-1 to 0x40000000
10364 14:45:19.528198
10365 14:45:19.528755 jumping to kernel
10366 14:45:19.531078 end: 2.2.4 bootloader-commands (duration 00:00:57) [common]
10367 14:45:19.531611 start: 2.2.5 auto-login-action (timeout 00:03:29) [common]
10368 14:45:19.532016 Setting prompt string to ['Linux version [0-9]']
10369 14:45:19.532388 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 14:45:19.532760 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 14:45:19.609976
10372 14:45:19.613633 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 14:45:19.617451 start: 2.2.5.1 login-action (timeout 00:03:29) [common]
10374 14:45:19.618123 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 14:45:19.618599 Setting prompt string to []
10376 14:45:19.619014 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 14:45:19.619432 Using line separator: #'\n'#
10378 14:45:19.619730 No login prompt set.
10379 14:45:19.620041 Parsing kernel messages
10380 14:45:19.620322 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 14:45:19.620840 [login-action] Waiting for messages, (timeout 00:03:29)
10382 14:45:19.621174 Waiting using forced prompt support (timeout 00:01:45)
10383 14:45:19.636534 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10384 14:45:19.639975 [ 0.000000] random: crng init done
10385 14:45:19.646536 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10386 14:45:19.649959 [ 0.000000] efi: UEFI not found.
10387 14:45:19.656527 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10388 14:45:19.663020 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10389 14:45:19.672974 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10390 14:45:19.682708 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10391 14:45:19.688996 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10392 14:45:19.695752 [ 0.000000] printk: bootconsole [mtk8250] enabled
10393 14:45:19.702134 [ 0.000000] NUMA: No NUMA configuration found
10394 14:45:19.708945 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10395 14:45:19.715681 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10396 14:45:19.716125 [ 0.000000] Zone ranges:
10397 14:45:19.722284 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10398 14:45:19.725257 [ 0.000000] DMA32 empty
10399 14:45:19.732044 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10400 14:45:19.735738 [ 0.000000] Movable zone start for each node
10401 14:45:19.738491 [ 0.000000] Early memory node ranges
10402 14:45:19.745333 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10403 14:45:19.752018 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10404 14:45:19.758597 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10405 14:45:19.765152 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10406 14:45:19.771721 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10407 14:45:19.777954 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10408 14:45:19.835387 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10409 14:45:19.841335 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10410 14:45:19.847802 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10411 14:45:19.851367 [ 0.000000] psci: probing for conduit method from DT.
10412 14:45:19.857741 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10413 14:45:19.861098 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10414 14:45:19.867517 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10415 14:45:19.870886 [ 0.000000] psci: SMC Calling Convention v1.2
10416 14:45:19.877540 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10417 14:45:19.880994 [ 0.000000] Detected VIPT I-cache on CPU0
10418 14:45:19.887252 [ 0.000000] CPU features: detected: GIC system register CPU interface
10419 14:45:19.894278 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10420 14:45:19.900375 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10421 14:45:19.906919 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10422 14:45:19.916832 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10423 14:45:19.923426 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10424 14:45:19.926589 [ 0.000000] alternatives: applying boot alternatives
10425 14:45:19.933467 [ 0.000000] Fallback order for Node 0: 0
10426 14:45:19.940221 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10427 14:45:19.943198 [ 0.000000] Policy zone: Normal
10428 14:45:19.966641 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10429 14:45:19.976510 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10430 14:45:19.987329 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10431 14:45:19.997309 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10432 14:45:20.004118 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10433 14:45:20.007288 <6>[ 0.000000] software IO TLB: area num 8.
10434 14:45:20.063874 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10435 14:45:20.213705 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10436 14:45:20.219986 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10437 14:45:20.226494 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10438 14:45:20.230124 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10439 14:45:20.237012 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10440 14:45:20.243025 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10441 14:45:20.250064 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10442 14:45:20.255799 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10443 14:45:20.262984 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10444 14:45:20.269245 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10445 14:45:20.275859 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10446 14:45:20.279114 <6>[ 0.000000] GICv3: 608 SPIs implemented
10447 14:45:20.282083 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10448 14:45:20.289480 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10449 14:45:20.292212 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10450 14:45:20.299152 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10451 14:45:20.311863 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10452 14:45:20.325616 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10453 14:45:20.331986 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10454 14:45:20.339926 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10455 14:45:20.353360 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10456 14:45:20.359478 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10457 14:45:20.366452 <6>[ 0.009183] Console: colour dummy device 80x25
10458 14:45:20.376549 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10459 14:45:20.383573 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10460 14:45:20.386282 <6>[ 0.029224] LSM: Security Framework initializing
10461 14:45:20.392990 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 14:45:20.402919 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 14:45:20.412821 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10464 14:45:20.415962 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 14:45:20.425735 <6>[ 0.065225] cblist_init_generic: Setting adjustable number of callback queues.
10466 14:45:20.432546 <6>[ 0.072652] cblist_init_generic: Setting shift to 3 and lim to 1.
10467 14:45:20.435786 <6>[ 0.079053] rcu: Hierarchical SRCU implementation.
10468 14:45:20.442197 <6>[ 0.084069] rcu: Max phase no-delay instances is 1000.
10469 14:45:20.449150 <6>[ 0.091107] EFI services will not be available.
10470 14:45:20.452596 <6>[ 0.096061] smp: Bringing up secondary CPUs ...
10471 14:45:20.461176 <6>[ 0.101110] Detected VIPT I-cache on CPU1
10472 14:45:20.467538 <6>[ 0.101181] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10473 14:45:20.474113 <6>[ 0.101212] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10474 14:45:20.477311 <6>[ 0.101552] Detected VIPT I-cache on CPU2
10475 14:45:20.487341 <6>[ 0.101607] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10476 14:45:20.493347 <6>[ 0.101626] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10477 14:45:20.496602 <6>[ 0.101883] Detected VIPT I-cache on CPU3
10478 14:45:20.503593 <6>[ 0.101929] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10479 14:45:20.509994 <6>[ 0.101943] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10480 14:45:20.516469 <6>[ 0.102248] CPU features: detected: Spectre-v4
10481 14:45:20.519802 <6>[ 0.102254] CPU features: detected: Spectre-BHB
10482 14:45:20.523569 <6>[ 0.102259] Detected PIPT I-cache on CPU4
10483 14:45:20.529849 <6>[ 0.102316] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10484 14:45:20.539892 <6>[ 0.102333] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10485 14:45:20.543022 <6>[ 0.102623] Detected PIPT I-cache on CPU5
10486 14:45:20.549865 <6>[ 0.102687] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10487 14:45:20.556040 <6>[ 0.102702] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10488 14:45:20.559808 <6>[ 0.102983] Detected PIPT I-cache on CPU6
10489 14:45:20.566316 <6>[ 0.103050] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10490 14:45:20.576119 <6>[ 0.103067] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10491 14:45:20.579854 <6>[ 0.103365] Detected PIPT I-cache on CPU7
10492 14:45:20.586031 <6>[ 0.103427] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10493 14:45:20.592474 <6>[ 0.103443] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10494 14:45:20.595736 <6>[ 0.103489] smp: Brought up 1 node, 8 CPUs
10495 14:45:20.602591 <6>[ 0.244764] SMP: Total of 8 processors activated.
10496 14:45:20.605794 <6>[ 0.249716] CPU features: detected: 32-bit EL0 Support
10497 14:45:20.615452 <6>[ 0.255079] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10498 14:45:20.622349 <6>[ 0.263880] CPU features: detected: Common not Private translations
10499 14:45:20.629518 <6>[ 0.270396] CPU features: detected: CRC32 instructions
10500 14:45:20.635479 <6>[ 0.275747] CPU features: detected: RCpc load-acquire (LDAPR)
10501 14:45:20.638590 <6>[ 0.281744] CPU features: detected: LSE atomic instructions
10502 14:45:20.645743 <6>[ 0.287525] CPU features: detected: Privileged Access Never
10503 14:45:20.651607 <6>[ 0.293341] CPU features: detected: RAS Extension Support
10504 14:45:20.658204 <6>[ 0.298950] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10505 14:45:20.661479 <6>[ 0.306174] CPU: All CPU(s) started at EL2
10506 14:45:20.668342 <6>[ 0.310491] alternatives: applying system-wide alternatives
10507 14:45:20.678302 <6>[ 0.321345] devtmpfs: initialized
10508 14:45:20.694196 <6>[ 0.330358] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10509 14:45:20.700859 <6>[ 0.340315] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10510 14:45:20.707200 <6>[ 0.348338] pinctrl core: initialized pinctrl subsystem
10511 14:45:20.710873 <6>[ 0.354988] DMI not present or invalid.
10512 14:45:20.717541 <6>[ 0.359399] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10513 14:45:20.727459 <6>[ 0.366265] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10514 14:45:20.733999 <6>[ 0.373858] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10515 14:45:20.743473 <6>[ 0.382080] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10516 14:45:20.746632 <6>[ 0.390322] audit: initializing netlink subsys (disabled)
10517 14:45:20.756697 <5>[ 0.396012] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10518 14:45:20.763139 <6>[ 0.396714] thermal_sys: Registered thermal governor 'step_wise'
10519 14:45:20.770147 <6>[ 0.403974] thermal_sys: Registered thermal governor 'power_allocator'
10520 14:45:20.773396 <6>[ 0.410230] cpuidle: using governor menu
10521 14:45:20.779564 <6>[ 0.421187] NET: Registered PF_QIPCRTR protocol family
10522 14:45:20.786510 <6>[ 0.426668] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10523 14:45:20.793012 <6>[ 0.433771] ASID allocator initialised with 32768 entries
10524 14:45:20.796178 <6>[ 0.440351] Serial: AMBA PL011 UART driver
10525 14:45:20.806626 <4>[ 0.449084] Trying to register duplicate clock ID: 134
10526 14:45:20.866212 <6>[ 0.512206] KASLR enabled
10527 14:45:20.880307 <6>[ 0.520007] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10528 14:45:20.887131 <6>[ 0.527021] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10529 14:45:20.893862 <6>[ 0.533506] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10530 14:45:20.900928 <6>[ 0.540510] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10531 14:45:20.906854 <6>[ 0.546997] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10532 14:45:20.913480 <6>[ 0.553998] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10533 14:45:20.919806 <6>[ 0.560481] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10534 14:45:20.926814 <6>[ 0.567484] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10535 14:45:20.929836 <6>[ 0.575017] ACPI: Interpreter disabled.
10536 14:45:20.939085 <6>[ 0.581460] iommu: Default domain type: Translated
10537 14:45:20.945356 <6>[ 0.586574] iommu: DMA domain TLB invalidation policy: strict mode
10538 14:45:20.948583 <5>[ 0.593238] SCSI subsystem initialized
10539 14:45:20.955053 <6>[ 0.597400] usbcore: registered new interface driver usbfs
10540 14:45:20.962304 <6>[ 0.603137] usbcore: registered new interface driver hub
10541 14:45:20.965229 <6>[ 0.608682] usbcore: registered new device driver usb
10542 14:45:20.972254 <6>[ 0.614793] pps_core: LinuxPPS API ver. 1 registered
10543 14:45:20.982102 <6>[ 0.619982] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10544 14:45:20.984954 <6>[ 0.629327] PTP clock support registered
10545 14:45:20.988503 <6>[ 0.633570] EDAC MC: Ver: 3.0.0
10546 14:45:20.995918 <6>[ 0.638717] FPGA manager framework
10547 14:45:21.002521 <6>[ 0.642404] Advanced Linux Sound Architecture Driver Initialized.
10548 14:45:21.005444 <6>[ 0.649197] vgaarb: loaded
10549 14:45:21.011911 <6>[ 0.652356] clocksource: Switched to clocksource arch_sys_counter
10550 14:45:21.015255 <5>[ 0.658799] VFS: Disk quotas dquot_6.6.0
10551 14:45:21.021992 <6>[ 0.662982] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10552 14:45:21.025406 <6>[ 0.670177] pnp: PnP ACPI: disabled
10553 14:45:21.033664 <6>[ 0.676856] NET: Registered PF_INET protocol family
10554 14:45:21.043931 <6>[ 0.682449] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10555 14:45:21.055066 <6>[ 0.694786] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10556 14:45:21.065154 <6>[ 0.703600] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10557 14:45:21.071928 <6>[ 0.711572] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10558 14:45:21.081506 <6>[ 0.720268] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10559 14:45:21.088240 <6>[ 0.730020] TCP: Hash tables configured (established 65536 bind 65536)
10560 14:45:21.094609 <6>[ 0.736886] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 14:45:21.104512 <6>[ 0.744082] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 14:45:21.110953 <6>[ 0.751778] NET: Registered PF_UNIX/PF_LOCAL protocol family
10563 14:45:21.117606 <6>[ 0.757933] RPC: Registered named UNIX socket transport module.
10564 14:45:21.120796 <6>[ 0.764089] RPC: Registered udp transport module.
10565 14:45:21.128117 <6>[ 0.769025] RPC: Registered tcp transport module.
10566 14:45:21.133931 <6>[ 0.773957] RPC: Registered tcp NFSv4.1 backchannel transport module.
10567 14:45:21.137169 <6>[ 0.780622] PCI: CLS 0 bytes, default 64
10568 14:45:21.140640 <6>[ 0.784925] Unpacking initramfs...
10569 14:45:21.150137 <6>[ 0.788984] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10570 14:45:21.157143 <6>[ 0.797589] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10571 14:45:21.163590 <6>[ 0.806394] kvm [1]: IPA Size Limit: 40 bits
10572 14:45:21.166763 <6>[ 0.810923] kvm [1]: GICv3: no GICV resource entry
10573 14:45:21.173531 <6>[ 0.815946] kvm [1]: disabling GICv2 emulation
10574 14:45:21.179840 <6>[ 0.820632] kvm [1]: GIC system register CPU interface enabled
10575 14:45:21.183329 <6>[ 0.826797] kvm [1]: vgic interrupt IRQ18
10576 14:45:21.190046 <6>[ 0.831142] kvm [1]: VHE mode initialized successfully
10577 14:45:21.193480 <5>[ 0.837568] Initialise system trusted keyrings
10578 14:45:21.199589 <6>[ 0.842365] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10579 14:45:21.209378 <6>[ 0.852472] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10580 14:45:21.215889 <5>[ 0.858926] NFS: Registering the id_resolver key type
10581 14:45:21.219522 <5>[ 0.864227] Key type id_resolver registered
10582 14:45:21.226268 <5>[ 0.868642] Key type id_legacy registered
10583 14:45:21.232309 <6>[ 0.872937] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10584 14:45:21.239128 <6>[ 0.879860] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10585 14:45:21.245657 <6>[ 0.887608] 9p: Installing v9fs 9p2000 file system support
10586 14:45:21.283557 <5>[ 0.926206] Key type asymmetric registered
10587 14:45:21.286346 <5>[ 0.930536] Asymmetric key parser 'x509' registered
10588 14:45:21.296405 <6>[ 0.935674] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10589 14:45:21.300257 <6>[ 0.943288] io scheduler mq-deadline registered
10590 14:45:21.303032 <6>[ 0.948045] io scheduler kyber registered
10591 14:45:21.322629 <6>[ 0.965456] EINJ: ACPI disabled.
10592 14:45:21.355631 <4>[ 0.992104] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 14:45:21.365672 <4>[ 1.002741] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 14:45:21.380664 <6>[ 1.023829] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10595 14:45:21.388879 <6>[ 1.031874] printk: console [ttyS0] disabled
10596 14:45:21.416790 <6>[ 1.056506] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10597 14:45:21.423255 <6>[ 1.065972] printk: console [ttyS0] enabled
10598 14:45:21.426836 <6>[ 1.065972] printk: console [ttyS0] enabled
10599 14:45:21.433200 <6>[ 1.074867] printk: bootconsole [mtk8250] disabled
10600 14:45:21.436627 <6>[ 1.074867] printk: bootconsole [mtk8250] disabled
10601 14:45:21.443925 <6>[ 1.085912] SuperH (H)SCI(F) driver initialized
10602 14:45:21.446305 <6>[ 1.091182] msm_serial: driver initialized
10603 14:45:21.460648 <6>[ 1.100124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10604 14:45:21.470514 <6>[ 1.108674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10605 14:45:21.476732 <6>[ 1.117220] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10606 14:45:21.486392 <6>[ 1.125848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10607 14:45:21.496626 <6>[ 1.134556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10608 14:45:21.503064 <6>[ 1.143270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10609 14:45:21.513163 <6>[ 1.151810] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10610 14:45:21.519569 <6>[ 1.160612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10611 14:45:21.529894 <6>[ 1.169162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10612 14:45:21.541283 <6>[ 1.184594] loop: module loaded
10613 14:45:21.548105 <6>[ 1.190467] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10614 14:45:21.570893 <4>[ 1.213663] mtk-pmic-keys: Failed to locate of_node [id: -1]
10615 14:45:21.577842 <6>[ 1.220514] megasas: 07.719.03.00-rc1
10616 14:45:21.587220 <6>[ 1.230166] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10617 14:45:21.596944 <6>[ 1.239739] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10618 14:45:21.613521 <6>[ 1.256287] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10619 14:45:21.674258 <6>[ 1.310107] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10620 14:45:21.974594 <6>[ 1.617627] Freeing initrd memory: 18292K
10621 14:45:21.986346 <6>[ 1.629319] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10622 14:45:21.997978 <6>[ 1.640187] tun: Universal TUN/TAP device driver, 1.6
10623 14:45:22.000706 <6>[ 1.646240] thunder_xcv, ver 1.0
10624 14:45:22.003881 <6>[ 1.649748] thunder_bgx, ver 1.0
10625 14:45:22.007785 <6>[ 1.653244] nicpf, ver 1.0
10626 14:45:22.018286 <6>[ 1.657258] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10627 14:45:22.021798 <6>[ 1.664734] hns3: Copyright (c) 2017 Huawei Corporation.
10628 14:45:22.027806 <6>[ 1.670325] hclge is initializing
10629 14:45:22.031000 <6>[ 1.673907] e1000: Intel(R) PRO/1000 Network Driver
10630 14:45:22.037678 <6>[ 1.679036] e1000: Copyright (c) 1999-2006 Intel Corporation.
10631 14:45:22.040959 <6>[ 1.685048] e1000e: Intel(R) PRO/1000 Network Driver
10632 14:45:22.047575 <6>[ 1.690264] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10633 14:45:22.054414 <6>[ 1.696448] igb: Intel(R) Gigabit Ethernet Network Driver
10634 14:45:22.060644 <6>[ 1.702098] igb: Copyright (c) 2007-2014 Intel Corporation.
10635 14:45:22.067223 <6>[ 1.707934] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10636 14:45:22.073782 <6>[ 1.714452] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10637 14:45:22.077251 <6>[ 1.720919] sky2: driver version 1.30
10638 14:45:22.083858 <6>[ 1.725856] usbcore: registered new device driver r8152-cfgselector
10639 14:45:22.090447 <6>[ 1.732394] usbcore: registered new interface driver r8152
10640 14:45:22.096592 <6>[ 1.738206] VFIO - User Level meta-driver version: 0.3
10641 14:45:22.103365 <6>[ 1.746439] usbcore: registered new interface driver usb-storage
10642 14:45:22.110363 <6>[ 1.752881] usbcore: registered new device driver onboard-usb-hub
10643 14:45:22.119439 <6>[ 1.762031] mt6397-rtc mt6359-rtc: registered as rtc0
10644 14:45:22.128516 <6>[ 1.767493] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:45:21 UTC (1717512321)
10645 14:45:22.131873 <6>[ 1.777059] i2c_dev: i2c /dev entries driver
10646 14:45:22.149873 <6>[ 1.788925] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10647 14:45:22.156005 <4>[ 1.797647] cpu cpu0: supply cpu not found, using dummy regulator
10648 14:45:22.162221 <4>[ 1.804070] cpu cpu1: supply cpu not found, using dummy regulator
10649 14:45:22.169215 <4>[ 1.810475] cpu cpu2: supply cpu not found, using dummy regulator
10650 14:45:22.175928 <4>[ 1.816876] cpu cpu3: supply cpu not found, using dummy regulator
10651 14:45:22.182258 <4>[ 1.823273] cpu cpu4: supply cpu not found, using dummy regulator
10652 14:45:22.188812 <4>[ 1.829686] cpu cpu5: supply cpu not found, using dummy regulator
10653 14:45:22.195324 <4>[ 1.836085] cpu cpu6: supply cpu not found, using dummy regulator
10654 14:45:22.202136 <4>[ 1.842478] cpu cpu7: supply cpu not found, using dummy regulator
10655 14:45:22.220376 <6>[ 1.863116] cpu cpu0: EM: created perf domain
10656 14:45:22.223217 <6>[ 1.868059] cpu cpu4: EM: created perf domain
10657 14:45:22.230542 <6>[ 1.873676] sdhci: Secure Digital Host Controller Interface driver
10658 14:45:22.237570 <6>[ 1.880119] sdhci: Copyright(c) Pierre Ossman
10659 14:45:22.244189 <6>[ 1.885076] Synopsys Designware Multimedia Card Interface Driver
10660 14:45:22.250507 <6>[ 1.891716] sdhci-pltfm: SDHCI platform and OF driver helper
10661 14:45:22.254034 <6>[ 1.891877] mmc0: CQHCI version 5.10
10662 14:45:22.260898 <6>[ 1.901723] ledtrig-cpu: registered to indicate activity on CPUs
10663 14:45:22.267119 <6>[ 1.908795] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 14:45:22.274155 <6>[ 1.915842] usbcore: registered new interface driver usbhid
10665 14:45:22.277783 <6>[ 1.921665] usbhid: USB HID core driver
10666 14:45:22.283680 <6>[ 1.925862] spi_master spi0: will run message pump with realtime priority
10667 14:45:22.327952 <6>[ 1.964302] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 14:45:22.346578 <6>[ 1.979304] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 14:45:22.353833 <6>[ 1.994762] cros-ec-spi spi0.0: Chrome EC device registered
10670 14:45:22.356651 <6>[ 2.000842] mmc0: Command Queue Engine enabled
10671 14:45:22.363532 <6>[ 2.005592] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10672 14:45:22.370389 <6>[ 2.013225] mmcblk0: mmc0:0001 DA4128 116 GiB
10673 14:45:22.388591 <6>[ 2.027778] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10674 14:45:22.394868 <6>[ 2.029530] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10675 14:45:22.401366 <6>[ 2.038386] NET: Registered PF_PACKET protocol family
10676 14:45:22.404425 <6>[ 2.044246] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10677 14:45:22.411650 <6>[ 2.048422] 9pnet: Installing 9P2000 support
10678 14:45:22.414540 <6>[ 2.054212] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10679 14:45:22.420976 <5>[ 2.058101] Key type dns_resolver registered
10680 14:45:22.427607 <6>[ 2.063925] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10681 14:45:22.431078 <6>[ 2.068297] registered taskstats version 1
10682 14:45:22.434535 <5>[ 2.078811] Loading compiled-in X.509 certificates
10683 14:45:22.465945 <4>[ 2.101393] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 14:45:22.474785 <4>[ 2.112143] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 14:45:22.489839 <6>[ 2.133084] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10686 14:45:22.496622 <6>[ 2.139908] xhci-mtk 11200000.usb: xHCI Host Controller
10687 14:45:22.503398 <6>[ 2.145464] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10688 14:45:22.513763 <6>[ 2.153331] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10689 14:45:22.519884 <6>[ 2.162765] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10690 14:45:22.526950 <6>[ 2.168990] xhci-mtk 11200000.usb: xHCI Host Controller
10691 14:45:22.533450 <6>[ 2.174492] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10692 14:45:22.539790 <6>[ 2.182149] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10693 14:45:22.547078 <6>[ 2.189939] hub 1-0:1.0: USB hub found
10694 14:45:22.550232 <6>[ 2.193979] hub 1-0:1.0: 1 port detected
10695 14:45:22.560337 <6>[ 2.198265] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10696 14:45:22.563866 <6>[ 2.207000] hub 2-0:1.0: USB hub found
10697 14:45:22.566281 <6>[ 2.211048] hub 2-0:1.0: 1 port detected
10698 14:45:22.574836 <6>[ 2.218065] mtk-msdc 11f70000.mmc: Got CD GPIO
10699 14:45:22.587445 <6>[ 2.227100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10700 14:45:22.594202 <6>[ 2.235123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10701 14:45:22.603877 <4>[ 2.243046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10702 14:45:22.613760 <6>[ 2.252592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10703 14:45:22.620408 <6>[ 2.260670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10704 14:45:22.627023 <6>[ 2.268688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10705 14:45:22.636963 <6>[ 2.276616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10706 14:45:22.644063 <6>[ 2.284438] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10707 14:45:22.653188 <6>[ 2.292256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10708 14:45:22.663203 <6>[ 2.302613] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10709 14:45:22.670553 <6>[ 2.311004] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10710 14:45:22.680211 <6>[ 2.319353] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10711 14:45:22.689908 <6>[ 2.327692] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10712 14:45:22.696199 <6>[ 2.336030] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10713 14:45:22.706278 <6>[ 2.344370] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10714 14:45:22.713116 <6>[ 2.352708] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10715 14:45:22.722463 <6>[ 2.361045] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10716 14:45:22.729658 <6>[ 2.369383] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10717 14:45:22.739302 <6>[ 2.377721] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10718 14:45:22.745793 <6>[ 2.386059] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10719 14:45:22.755601 <6>[ 2.394397] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10720 14:45:22.762139 <6>[ 2.402734] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10721 14:45:22.772099 <6>[ 2.411074] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10722 14:45:22.779247 <6>[ 2.419414] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10723 14:45:22.785228 <6>[ 2.428150] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10724 14:45:22.792423 <6>[ 2.435312] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10725 14:45:22.798895 <6>[ 2.442096] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10726 14:45:22.808850 <6>[ 2.448863] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10727 14:45:22.815775 <6>[ 2.455796] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10728 14:45:22.822654 <6>[ 2.462645] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10729 14:45:22.832131 <6>[ 2.471775] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10730 14:45:22.842281 <6>[ 2.480894] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10731 14:45:22.852485 <6>[ 2.490189] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10732 14:45:22.862157 <6>[ 2.499656] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10733 14:45:22.872149 <6>[ 2.509124] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10734 14:45:22.878539 <6>[ 2.518244] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10735 14:45:22.888266 <6>[ 2.527710] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10736 14:45:22.898305 <6>[ 2.536829] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10737 14:45:22.908289 <6>[ 2.546124] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10738 14:45:22.918331 <6>[ 2.556289] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10739 14:45:22.928486 <6>[ 2.567844] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10740 14:45:22.934770 <6>[ 2.577433] Trying to probe devices needed for running init ...
10741 14:45:22.980516 <6>[ 2.620629] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10742 14:45:23.135855 <6>[ 2.778823] hub 1-1:1.0: USB hub found
10743 14:45:23.139097 <6>[ 2.783372] hub 1-1:1.0: 4 ports detected
10744 14:45:23.149247 <6>[ 2.791883] hub 1-1:1.0: USB hub found
10745 14:45:23.151971 <6>[ 2.796210] hub 1-1:1.0: 4 ports detected
10746 14:45:23.260789 <6>[ 2.900818] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10747 14:45:23.287554 <6>[ 2.930824] hub 2-1:1.0: USB hub found
10748 14:45:23.291119 <6>[ 2.935366] hub 2-1:1.0: 3 ports detected
10749 14:45:23.300341 <6>[ 2.943474] hub 2-1:1.0: USB hub found
10750 14:45:23.304576 <6>[ 2.947956] hub 2-1:1.0: 3 ports detected
10751 14:45:23.476784 <6>[ 3.116685] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10752 14:45:23.609428 <6>[ 3.252724] hub 1-1.4:1.0: USB hub found
10753 14:45:23.613016 <6>[ 3.257415] hub 1-1.4:1.0: 2 ports detected
10754 14:45:23.622949 <6>[ 3.266312] hub 1-1.4:1.0: USB hub found
10755 14:45:23.626458 <6>[ 3.270954] hub 1-1.4:1.0: 2 ports detected
10756 14:45:23.697227 <6>[ 3.336896] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10757 14:45:23.805795 <6>[ 3.445333] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10758 14:45:23.842524 <4>[ 3.482626] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10759 14:45:23.852543 <4>[ 3.491784] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10760 14:45:23.891207 <6>[ 3.534118] r8152 2-1.3:1.0 eth0: v1.12.13
10761 14:45:23.925096 <6>[ 3.564670] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 14:45:24.116560 <6>[ 3.756675] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 14:45:25.620695 <6>[ 5.264214] r8152 2-1.3:1.0 eth0: carrier on
10764 14:45:27.996870 <5>[ 5.288463] Sending DHCP requests .., OK
10765 14:45:28.003283 <6>[ 7.644840] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10766 14:45:28.006700 <6>[ 7.653166] IP-Config: Complete:
10767 14:45:28.020360 <6>[ 7.656662] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10768 14:45:28.026583 <6>[ 7.667375] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10769 14:45:28.033212 <6>[ 7.675995] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10770 14:45:28.040013 <6>[ 7.676006] nameserver0=192.168.201.1
10771 14:45:28.043630 <6>[ 7.688164] clk: Disabling unused clocks
10772 14:45:28.046712 <6>[ 7.693765] ALSA device list:
10773 14:45:28.053226 <6>[ 7.697029] No soundcards found.
10774 14:45:28.061626 <6>[ 7.704494] Freeing unused kernel memory: 8512K
10775 14:45:28.063962 <6>[ 7.709422] Run /init as init process
10776 14:45:28.074107 Loading, please wait...
10777 14:45:28.099131 Starting systemd-udevd version 252.22-1~deb12u1
10778 14:45:28.366986 <6>[ 8.007403] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10779 14:45:28.376853 <6>[ 8.016986] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10780 14:45:28.387248 <6>[ 8.026176] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10781 14:45:28.390704 <6>[ 8.035260] mc: Linux media interface: v0.10
10782 14:45:28.431727 <4>[ 8.072073] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10783 14:45:28.457774 <4>[ 8.098114] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10784 14:45:28.477897 <6>[ 8.118340] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10785 14:45:28.501601 <4>[ 8.142140] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10786 14:45:28.508154 <4>[ 8.142140] Fallback method does not support PEC.
10787 14:45:28.523859 <3>[ 8.164262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 14:45:28.533688 <3>[ 8.172718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 14:45:28.540182 <3>[ 8.181115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 14:45:28.552735 <6>[ 8.192166] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10791 14:45:28.562552 <3>[ 8.197065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 14:45:28.568621 <6>[ 8.205555] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10793 14:45:28.575123 <6>[ 8.217986] pci_bus 0000:00: root bus resource [bus 00-ff]
10794 14:45:28.582077 <6>[ 8.223888] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10795 14:45:28.591827 <6>[ 8.223921] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10796 14:45:28.602493 <6>[ 8.231023] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10797 14:45:28.609170 <6>[ 8.231065] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10798 14:45:28.615753 <3>[ 8.249141] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 14:45:28.625514 <6>[ 8.250501] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10800 14:45:28.632055 <3>[ 8.250519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 14:45:28.638799 <3>[ 8.250568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 14:45:28.649163 <3>[ 8.250579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 14:45:28.655664 <3>[ 8.250598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 14:45:28.665315 <3>[ 8.250614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10805 14:45:28.671863 <3>[ 8.255061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 14:45:28.682298 <6>[ 8.258752] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10807 14:45:28.685393 <6>[ 8.265587] pci 0000:00:00.0: supports D1 D2
10808 14:45:28.695028 <3>[ 8.284038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 14:45:28.701851 <6>[ 8.289000] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10810 14:45:28.708850 <3>[ 8.350106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 14:45:28.718249 <3>[ 8.358581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 14:45:28.727997 <3>[ 8.368188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 14:45:28.738047 <3>[ 8.378043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10814 14:45:28.744341 <6>[ 8.383069] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10815 14:45:28.754352 <3>[ 8.386186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 14:45:28.761431 <6>[ 8.386700] videodev: Linux video capture interface: v2.00
10817 14:45:28.767738 <6>[ 8.387573] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10818 14:45:28.771183 <6>[ 8.390359] remoteproc remoteproc0: scp is available
10819 14:45:28.777933 <6>[ 8.390456] remoteproc remoteproc0: powering up scp
10820 14:45:28.784677 <6>[ 8.390464] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10821 14:45:28.790761 <6>[ 8.390485] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10822 14:45:28.797472 <6>[ 8.407714] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10823 14:45:28.803989 <3>[ 8.408271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 14:45:28.814034 <6>[ 8.416588] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10825 14:45:28.820514 <3>[ 8.421022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 14:45:28.823850 <6>[ 8.422200] Bluetooth: Core ver 2.22
10827 14:45:28.830443 <6>[ 8.422377] NET: Registered PF_BLUETOOTH protocol family
10828 14:45:28.836893 <6>[ 8.422382] Bluetooth: HCI device and connection manager initialized
10829 14:45:28.844264 <6>[ 8.422432] Bluetooth: HCI socket layer initialized
10830 14:45:28.847158 <6>[ 8.422447] Bluetooth: L2CAP socket layer initialized
10831 14:45:28.853411 <6>[ 8.422468] Bluetooth: SCO socket layer initialized
10832 14:45:28.860326 <6>[ 8.428485] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10833 14:45:28.867380 <3>[ 8.434569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 14:45:28.877839 <6>[ 8.440200] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10835 14:45:28.883414 <6>[ 8.455720] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10836 14:45:28.886914 <6>[ 8.462062] pci 0000:01:00.0: supports D1 D2
10837 14:45:28.893303 <6>[ 8.462775] usbcore: registered new interface driver btusb
10838 14:45:28.903616 <4>[ 8.463771] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10839 14:45:28.909677 <3>[ 8.463778] Bluetooth: hci0: Failed to load firmware file (-2)
10840 14:45:28.916740 <3>[ 8.463780] Bluetooth: hci0: Failed to set up firmware (-2)
10841 14:45:28.926308 <4>[ 8.463784] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10842 14:45:28.939102 <6>[ 8.471083] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10843 14:45:28.946150 <6>[ 8.473830] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10844 14:45:28.952539 <6>[ 8.474521] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10845 14:45:28.959343 <6>[ 8.479597] usbcore: registered new interface driver uvcvideo
10846 14:45:28.965584 <6>[ 8.484521] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10847 14:45:28.972193 <6>[ 8.484552] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10848 14:45:28.982249 <6>[ 8.484556] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10849 14:45:28.989026 <6>[ 8.484563] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10850 14:45:28.995498 <6>[ 8.484576] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10851 14:45:29.005571 <6>[ 8.484589] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10852 14:45:29.008718 <6>[ 8.484601] pci 0000:00:00.0: PCI bridge to [bus 01]
10853 14:45:29.018452 <6>[ 8.484606] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10854 14:45:29.025133 <6>[ 8.486120] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10855 14:45:29.031698 <6>[ 8.517828] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10856 14:45:29.038005 <6>[ 8.525084] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10857 14:45:29.045384 <6>[ 8.531753] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10858 14:45:29.051967 <6>[ 8.536699] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10859 14:45:29.058119 <6>[ 8.542027] remoteproc remoteproc0: remote processor scp is now up
10860 14:45:29.068315 <5>[ 8.566263] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10861 14:45:29.074615 <6>[ 8.575737] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10862 14:45:29.081691 <5>[ 8.599607] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10863 14:45:29.091163 <6>[ 8.604371] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10864 14:45:29.097731 <5>[ 8.607159] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10865 14:45:29.107471 <4>[ 8.746834] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10866 14:45:29.110557 <6>[ 8.755724] cfg80211: failed to load regulatory.db
10867 14:45:29.153454 <6>[ 8.793739] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10868 14:45:29.159599 <6>[ 8.801272] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10869 14:45:29.184261 <6>[ 8.828080] mt7921e 0000:01:00.0: ASIC revision: 79610010
10870 14:45:29.287157 <6>[ 8.927931] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10871 14:45:29.290645 <6>[ 8.927931]
10872 14:45:29.293941 Begin: Loading essential drivers ... done.
10873 14:45:29.297551 Begin: Running /scripts/init-premount ... done.
10874 14:45:29.303694 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10875 14:45:29.313635 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10876 14:45:29.317083 Device /sys/class/net/eth0 found
10877 14:45:29.317646 done.
10878 14:45:29.344376 Begin: Waiting up to 180 secs for any network device to become available ... done.
10879 14:45:29.396640 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10880 14:45:29.404963 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10881 14:45:29.411228 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10882 14:45:29.417758 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10883 14:45:29.424655 host : mt8192-asurada-spherion-r0-cbg-9
10884 14:45:29.430973 domain : lava-rack
10885 14:45:29.433876 rootserver: 192.168.201.1 rootpath:
10886 14:45:29.437587 filename :
10887 14:45:29.553683 <6>[ 9.194718] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10888 14:45:29.573283 done.
10889 14:45:29.582628 Begin: Running /scripts/nfs-bottom ... done.
10890 14:45:29.598859 Begin: Running /scripts/init-bottom ... done.
10891 14:45:31.028243 <6>[ 10.672421] NET: Registered PF_INET6 protocol family
10892 14:45:31.036446 <6>[ 10.680413] Segment Routing with IPv6
10893 14:45:31.039478 <6>[ 10.684379] In-situ OAM (IOAM) with IPv6
10894 14:45:31.231098 <30>[ 10.848295] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10895 14:45:31.237227 <30>[ 10.881452] systemd[1]: Detected architecture arm64.
10896 14:45:31.248101
10897 14:45:31.251233 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10898 14:45:31.251654
10899 14:45:31.279035 <30>[ 10.923210] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10900 14:45:32.594349 <30>[ 12.235295] systemd[1]: Queued start job for default target graphical.target.
10901 14:45:32.649783 <30>[ 12.290561] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10902 14:45:32.656430 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10903 14:45:32.677883 <30>[ 12.318690] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10904 14:45:32.687720 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10905 14:45:32.706099 <30>[ 12.346659] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10906 14:45:32.716224 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10907 14:45:32.733852 <30>[ 12.374272] systemd[1]: Created slice user.slice - User and Session Slice.
10908 14:45:32.740004 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10909 14:45:32.763920 <30>[ 12.401489] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10910 14:45:32.774067 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10911 14:45:32.791705 <30>[ 12.428952] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10912 14:45:32.797922 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10913 14:45:32.826644 <30>[ 12.457364] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10914 14:45:32.836814 <30>[ 12.477285] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10915 14:45:32.842735 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10916 14:45:32.860829 <30>[ 12.501080] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10917 14:45:32.870108 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10918 14:45:32.887918 <30>[ 12.528763] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10919 14:45:32.897920 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10920 14:45:32.912925 <30>[ 12.557274] systemd[1]: Reached target paths.target - Path Units.
10921 14:45:32.923339 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10922 14:45:32.940038 <30>[ 12.581127] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10923 14:45:32.946845 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10924 14:45:32.960680 <30>[ 12.604679] systemd[1]: Reached target slices.target - Slice Units.
10925 14:45:32.970434 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10926 14:45:32.984940 <30>[ 12.629167] systemd[1]: Reached target swap.target - Swaps.
10927 14:45:32.992139 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10928 14:45:33.012244 <30>[ 12.653209] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10929 14:45:33.021918 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10930 14:45:33.040576 <30>[ 12.681753] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10931 14:45:33.050492 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10932 14:45:33.071081 <30>[ 12.711983] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10933 14:45:33.080655 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10934 14:45:33.097629 <30>[ 12.738576] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10935 14:45:33.107431 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10936 14:45:33.124839 <30>[ 12.765468] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10937 14:45:33.131064 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10938 14:45:33.149975 <30>[ 12.790719] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10939 14:45:33.159359 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10940 14:45:33.179876 <30>[ 12.820733] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10941 14:45:33.189450 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10942 14:45:33.209369 <30>[ 12.849880] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10943 14:45:33.218861 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10944 14:45:33.272069 <30>[ 12.913155] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10945 14:45:33.278794 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10946 14:45:33.290207 <30>[ 12.931422] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10947 14:45:33.297252 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10948 14:45:33.319169 <30>[ 12.960386] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10949 14:45:33.325816 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10950 14:45:33.350487 <30>[ 12.984863] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10951 14:45:33.425114 <30>[ 13.065492] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10952 14:45:33.434403 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10953 14:45:33.457977 <30>[ 13.098835] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10954 14:45:33.468145 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10955 14:45:33.489949 <30>[ 13.130878] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10956 14:45:33.496941 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10957 14:45:33.519793 <30>[ 13.160861] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10958 14:45:33.526633 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10959 14:45:33.537555 <6>[ 13.178650] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10960 14:45:33.551898 <30>[ 13.192848] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10961 14:45:33.561675 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10962 14:45:33.586361 <30>[ 13.226914] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10963 14:45:33.592664 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10964 14:45:33.615818 <30>[ 13.257043] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10965 14:45:33.622614 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10966 14:45:33.630490 <6>[ 13.274866] fuse: init (API version 7.37)
10967 14:45:33.649488 <30>[ 13.289903] systemd[1]: Starting systemd-journald.service - Journal Service...
10968 14:45:33.656127 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10969 14:45:33.689681 <30>[ 13.331006] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10970 14:45:33.696157 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10971 14:45:33.724262 <30>[ 13.361896] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10972 14:45:33.730154 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10973 14:45:33.801081 <30>[ 13.442296] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10974 14:45:33.810838 <3>[ 13.452015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 14:45:33.817635 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10976 14:45:33.843548 <3>[ 13.484585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 14:45:33.884564 <30>[ 13.525448] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10978 14:45:33.891047 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10979 14:45:33.905331 <3>[ 13.546620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 14:45:33.921880 <30>[ 13.563106] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10981 14:45:33.929025 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10982 14:45:33.941943 <3>[ 13.583077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 14:45:33.952137 <30>[ 13.593318] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10984 14:45:33.961867 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10985 14:45:33.973988 <3>[ 13.615190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 14:45:33.983852 <30>[ 13.625003] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10987 14:45:33.990369 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10988 14:45:34.005801 <3>[ 13.646886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 14:45:34.016289 <30>[ 13.657299] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10990 14:45:34.025985 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10991 14:45:34.045697 <30>[ 13.686347] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10992 14:45:34.052539 <30>[ 13.694183] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10993 14:45:34.061814 <3>[ 13.694223] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 14:45:34.071815 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10995 14:45:34.088554 <30>[ 13.729513] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10996 14:45:34.095552 <30>[ 13.737231] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10997 14:45:34.105625 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10998 14:45:34.112714 <3>[ 13.753242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 14:45:34.124516 <30>[ 13.765663] systemd[1]: modprobe@drm.service: Deactivated successfully.
11000 14:45:34.132035 <30>[ 13.773286] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11001 14:45:34.145281 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.785253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 14:45:34.148176 rm.service[0m - Load Kernel Module drm.
11003 14:45:34.168932 <30>[ 13.809531] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11004 14:45:34.175416 <3>[ 13.817043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 14:45:34.185905 <30>[ 13.817753] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11006 14:45:34.195666 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11007 14:45:34.213392 <30>[ 13.854376] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11008 14:45:34.220258 <30>[ 13.861936] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11009 14:45:34.227256 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11010 14:45:34.250317 <30>[ 13.891220] systemd[1]: Started systemd-journald.service - Journal Service.
11011 14:45:34.257370 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11012 14:45:34.283356 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11013 14:45:34.301636 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11014 14:45:34.335048 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk uni<4>[ 13.966537] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11015 14:45:34.340953 <3>[ 13.983564] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11016 14:45:34.344538 ts from Kernel command line.
11017 14:45:34.367753 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11018 14:45:34.385492 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11019 14:45:34.407287 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11020 14:45:34.448550 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11021 14:45:34.473723 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11022 14:45:34.498407 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11023 14:45:34.521665 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11024 14:45:34.549016 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11025 14:45:34.579710 <46>[ 14.221458] systemd-journald[312]: Received client request to flush runtime journal.
11026 14:45:34.608453 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11027 14:45:34.898296 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11028 14:45:34.916479 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11029 14:45:34.937354 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11030 14:45:34.957691 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11031 14:45:35.814087 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11032 14:45:35.881337 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11033 14:45:35.982039 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11034 14:45:36.102979 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11035 14:45:36.124315 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11036 14:45:36.143186 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11037 14:45:36.191164 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11038 14:45:36.213423 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11039 14:45:36.486769 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11040 14:45:36.549751 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11041 14:45:36.586848 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11042 14:45:36.908095 <6>[ 16.553024] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11043 14:45:36.920924 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11044 14:45:36.983131 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11045 14:45:37.003501 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11046 14:45:37.053830 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11047 14:45:37.139995 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11048 14:45:37.158713 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11049 14:45:37.180746 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11050 14:45:37.201031 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11051 14:45:37.244916 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11052 14:45:37.264322 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11053 14:45:37.328724 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11054 14:45:37.360295 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11055 14:45:37.379823 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11056 14:45:37.400320 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11057 14:45:37.424108 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11058 14:45:37.448146 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11059 14:45:37.463249 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11060 14:45:37.516129 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11061 14:45:37.539689 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11062 14:45:37.555546 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11063 14:45:37.576456 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11064 14:45:37.600602 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11065 14:45:37.619703 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11066 14:45:37.638275 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11067 14:45:37.655390 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11068 14:45:37.671818 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11069 14:45:37.712783 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11070 14:45:37.751857 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11071 14:45:37.860337 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11072 14:45:37.890152 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11073 14:45:37.938047 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11074 14:45:37.988214 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11075 14:45:38.035479 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11076 14:45:38.055379 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11077 14:45:38.099623 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11078 14:45:38.192480 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11079 14:45:38.214530 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11080 14:45:38.240703 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11081 14:45:38.265739 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11082 14:45:38.314532 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11083 14:45:38.372516 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11084 14:45:38.471145
11085 14:45:38.474422 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11086 14:45:38.474941
11087 14:45:38.477672 debian-bookworm-arm64 login: root (automatic login)
11088 14:45:38.478220
11089 14:45:38.820530 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11090 14:45:38.821028
11091 14:45:38.827105 The programs included with the Debian GNU/Linux system are free software;
11092 14:45:38.833634 the exact distribution terms for each program are described in the
11093 14:45:38.836766 individual files in /usr/share/doc/*/copyright.
11094 14:45:38.837196
11095 14:45:38.843224 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11096 14:45:38.846964 permitted by applicable law.
11097 14:45:40.057420 Matched prompt #10: / #
11099 14:45:40.059117 Setting prompt string to ['/ #']
11100 14:45:40.059816 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11102 14:45:40.061627 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11103 14:45:40.062372 start: 2.2.6 expect-shell-connection (timeout 00:03:09) [common]
11104 14:45:40.063036 Setting prompt string to ['/ #']
11105 14:45:40.063505 Forcing a shell prompt, looking for ['/ #']
11107 14:45:40.114548 / #
11108 14:45:40.115135 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11109 14:45:40.115587 Waiting using forced prompt support (timeout 00:02:30)
11110 14:45:40.120249
11111 14:45:40.121269 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11112 14:45:40.121939 start: 2.2.7 export-device-env (timeout 00:03:09) [common]
11114 14:45:40.223247 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b'
11115 14:45:40.229767 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166996/extract-nfsrootfs-zo0omn5b'
11117 14:45:40.331209 / # export NFS_SERVER_IP='192.168.201.1'
11118 14:45:40.337261 export NFS_SERVER_IP='192.168.201.1'
11119 14:45:40.338050 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11120 14:45:40.338630 end: 2.2 depthcharge-retry (duration 00:01:52) [common]
11121 14:45:40.339160 end: 2 depthcharge-action (duration 00:01:52) [common]
11122 14:45:40.339696 start: 3 lava-test-retry (timeout 00:07:25) [common]
11123 14:45:40.340220 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11124 14:45:40.340658 Using namespace: common
11126 14:45:40.441879 / # #
11127 14:45:40.442097 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11128 14:45:40.447672 #
11129 14:45:40.448073 Using /lava-14166996
11131 14:45:40.548751 / # export SHELL=/bin/bash
11132 14:45:40.555116 export SHELL=/bin/bash
11134 14:45:40.656736 / # . /lava-14166996/environment
11135 14:45:40.663447 . /lava-14166996/environment
11137 14:45:40.772151 / # /lava-14166996/bin/lava-test-runner /lava-14166996/0
11138 14:45:40.772789 Test shell timeout: 10s (minimum of the action and connection timeout)
11139 14:45:40.778359 /lava-14166996/bin/lava-test-runner /lava-14166996/0
11140 14:45:41.084477 + export TESTRUN_ID=0_timesync-off
11141 14:45:41.087927 + TESTRUN_ID=0_timesync-off
11142 14:45:41.090915 + cd /lava-14166996/0/tests/0_timesync-off
11143 14:45:41.094243 ++ cat uuid
11144 14:45:41.102591 + UUID=14166996_1.6.2.3.1
11145 14:45:41.103011 + set +x
11146 14:45:41.108437 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14166996_1.6.2.3.1>
11147 14:45:41.109126 Received signal: <STARTRUN> 0_timesync-off 14166996_1.6.2.3.1
11148 14:45:41.109486 Starting test lava.0_timesync-off (14166996_1.6.2.3.1)
11149 14:45:41.109893 Skipping test definition patterns.
11150 14:45:41.111787 + systemctl stop systemd-timesyncd
11151 14:45:41.193882 + set +x
11152 14:45:41.197009 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14166996_1.6.2.3.1>
11153 14:45:41.197704 Received signal: <ENDRUN> 0_timesync-off 14166996_1.6.2.3.1
11154 14:45:41.198147 Ending use of test pattern.
11155 14:45:41.198584 Ending test lava.0_timesync-off (14166996_1.6.2.3.1), duration 0.09
11157 14:45:41.291789 + export TESTRUN_ID=1_kselftest-alsa
11158 14:45:41.294920 + TESTRUN_ID=1_kselftest-alsa
11159 14:45:41.301615 + cd /lava-14166996/0/tests/1_kselftest-alsa
11160 14:45:41.302050 ++ cat uuid
11161 14:45:41.310231 + UUID=14166996_1.6.2.3.5
11162 14:45:41.310669 + set +x
11163 14:45:41.317139 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14166996_1.6.2.3.5>
11164 14:45:41.317878 Received signal: <STARTRUN> 1_kselftest-alsa 14166996_1.6.2.3.5
11165 14:45:41.318350 Starting test lava.1_kselftest-alsa (14166996_1.6.2.3.5)
11166 14:45:41.318755 Skipping test definition patterns.
11167 14:45:41.320618 + cd ./automated/linux/kselftest/
11168 14:45:41.346779 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11169 14:45:41.405972 INFO: install_deps skipped
11170 14:45:41.927863 --2024-06-04 14:45:41-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11171 14:45:41.936131 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11172 14:45:42.066118 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11173 14:45:42.195947 HTTP request sent, awaiting response... 200 OK
11174 14:45:42.199325 Length: 1647736 (1.6M) [application/octet-stream]
11175 14:45:42.203152 Saving to: 'kselftest_armhf.tar.gz'
11176 14:45:42.203616
11177 14:45:42.203981
11178 14:45:42.465005 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11179 14:45:42.715110 kselftest_armhf.tar 3%[ ] 50.15K 187KB/s
11180 14:45:42.999497 kselftest_armhf.tar 13%[=> ] 216.08K 417KB/s
11181 14:45:43.132475 kselftest_armhf.tar 36%[======> ] 586.57K 730KB/s
11182 14:45:43.138591 kselftest_armhf.tar 100%[===================>] 1.57M 1.68MB/s in 0.9s
11183 14:45:43.138682
11184 14:45:43.285030 2024-06-04 14:45:43 (1.68 MB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736]
11185 14:45:43.285425
11186 14:45:48.450349 skiplist:
11187 14:45:48.453501 ========================================
11188 14:45:48.457594 ========================================
11189 14:45:48.510095 alsa:mixer-test
11190 14:45:48.532840 ============== Tests to run ===============
11191 14:45:48.536566 alsa:mixer-test
11192 14:45:48.539441 ===========End Tests to run ===============
11193 14:45:48.542612 shardfile-alsa pass
11194 14:45:48.658092 <12>[ 28.304439] kselftest: Running tests in alsa
11195 14:45:48.668399 TAP version 13
11196 14:45:48.684144 1..1
11197 14:45:48.700987 # selftests: alsa: mixer-test
11198 14:45:49.224559 # TAP version 13
11199 14:45:49.224710 # 1..0
11200 14:45:49.231035 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11201 14:45:49.234405 ok 1 selftests: alsa: mixer-test
11202 14:45:50.802069 alsa_mixer-test pass
11203 14:45:50.882231 + ../../utils/send-to-lava.sh ./output/result.txt
11204 14:45:50.963226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11205 14:45:50.963568 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11207 14:45:51.021148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11208 14:45:51.021294 + set +x
11209 14:45:51.021538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11211 14:45:51.027776 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14166996_1.6.2.3.5>
11212 14:45:51.028030 Received signal: <ENDRUN> 1_kselftest-alsa 14166996_1.6.2.3.5
11213 14:45:51.028103 Ending use of test pattern.
11214 14:45:51.028164 Ending test lava.1_kselftest-alsa (14166996_1.6.2.3.5), duration 9.71
11216 14:45:51.030945 <LAVA_TEST_RUNNER EXIT>
11217 14:45:51.031197 ok: lava_test_shell seems to have completed
11218 14:45:51.031296 alsa_mixer-test: pass
shardfile-alsa: pass
11219 14:45:51.031385 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11220 14:45:51.031468 end: 3 lava-test-retry (duration 00:00:11) [common]
11221 14:45:51.031552 start: 4 finalize (timeout 00:07:14) [common]
11222 14:45:51.031641 start: 4.1 power-off (timeout 00:00:30) [common]
11223 14:45:51.031791 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11224 14:45:51.233486 >> Command sent successfully.
11225 14:45:51.235856 Returned 0 in 0 seconds
11226 14:45:51.336240 end: 4.1 power-off (duration 00:00:00) [common]
11228 14:45:51.336572 start: 4.2 read-feedback (timeout 00:07:14) [common]
11229 14:45:51.336826 Listened to connection for namespace 'common' for up to 1s
11230 14:45:52.337804 Finalising connection for namespace 'common'
11231 14:45:52.338007 Disconnecting from shell: Finalise
11232 14:45:52.338089 / #
11233 14:45:52.438319 end: 4.2 read-feedback (duration 00:00:01) [common]
11234 14:45:52.438494 end: 4 finalize (duration 00:00:01) [common]
11235 14:45:52.438605 Cleaning after the job
11236 14:45:52.438700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/ramdisk
11237 14:45:52.440809 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/kernel
11238 14:45:52.451595 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/dtb
11239 14:45:52.451793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/nfsrootfs
11240 14:45:52.515190 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166996/tftp-deploy-z467xwy8/modules
11241 14:45:52.520818 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14166996
11242 14:45:53.075749 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14166996
11243 14:45:53.075922 Job finished correctly