[Enter `^Ec?' for help] F0: 102B 0000 F3: 1001 0000 [0200] F3: 1001 0000 F7: 102D 0000 F1: 0000 0000 V0: 0000 0000 [0001] 00: 0007 8000 01: 0000 0000 BP: 0C00 0209 [0000] G0: 1182 0000 EC: 0000 0021 [4000] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 0040 [010F] Jump to BL coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal Backing address range [0x00000000:0x40000000) with new page table @0x0010f000 Backing address range [0x00000000:0x00200000) with new page table @0x00110000 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal Backing address range [0x00200000:0x00400000) with new page table @0x00111000 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal WDT: Last reset was cold boot SPI1(PAD0) initialized at 2873684 Hz SPI5(PAD0) initialized at 992727 Hz VBOOT: Loading verstage. SF: Detected 00 0000 with sector size 0x1000, total 0x800000 FMAP: Found "FLASH" version 1.1 at 0x20000. FMAP: base = 0x0 size = 0x800000 #areas = 25 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception FMAP: area RW_NVRAM found @ 57b000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 Phase 1 FMAP: area GBB found @ 3f5000 (12032 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps BS: bootblock times (exec / console): total (unknown) / 148 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception pmic_efuse_setting: Set efuses in 11 msecs pmwrap_interface_init: Select PMIF_VLD_RDY [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2 [RTC]rtc_osc_init,62: osc32con val = 0xde70 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a [RTC]rtc_get_frequency_meter,154: input=15, output=764 [RTC]rtc_get_frequency_meter,154: input=23, output=948 [RTC]rtc_get_frequency_meter,154: input=19, output=857 [RTC]rtc_get_frequency_meter,154: input=17, output=811 [RTC]rtc_get_frequency_meter,154: input=16, output=787 [RTC]rtc_get_frequency_meter,154: input=16, output=786 [RTC]rtc_get_frequency_meter,154: input=17, output=811 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81 ADC[4]: Raw value=670432 ID=5 ADC[3]: Raw value=212917 ID=1 RAM Code: 0x51 FMAP: area COREBOOT found @ 21000 (4014080 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 MRC: failed to locate region type 0. DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0) DRAM-K: Running full calibration DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2 header.status = 0x0 header.version = 0x6 (expected: 0x6) header.size = 0xd00 (expected: 0xd00) header.flags = 0x0 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6 dram_init: ddr_geometry: 0 [EMI] MDL number = 0 [EMI] Get MDL freq = 0 dram_init: ddr_type: 0 is_discrete_lpddr4: 1 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0 [Bian_co] ETT version 0.0.0.1 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6 dramc_set_vcore_voltage set vcore to 650000 Read voltage for 800, 4 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 dram_init: config_dvfs: 1 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9 MEM_TYPE=3, freq_sel=18 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1600 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 800 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1600,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 40 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 12 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) [EMI DOE] emi_dcm 0 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~64) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 3 PI (21 cell) CA1 delay=37 (7~68),Diff = 3 PI (21 cell) CA2 delay=35 (5~66),Diff = 1 PI (7 cell) CA3 delay=35 (4~66),Diff = 1 PI (7 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 35 (4~66) winsize 63 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 3 PI (21 cell) CA1 delay=37 (7~68),Diff = 3 PI (21 cell) CA2 delay=35 (5~66),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 0 PI (0 cell) CA4 delay=34 (4~64),Diff = 0 PI (0 cell) CA5 delay=34 (4~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 27 => 27 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 0) 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1) 0 7 4 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 0) 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 2) best DQS0 dly(MCK, UI, PI) = (0, 10, 2) best DQS1 dly(MCK, UI, PI) = (0, 10, 0) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 82, DQM1 = 74 DQ Delay: DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=27, winSum=439 TX Vref=24, minBit 2, minWin=27, winSum=445 TX Vref=26, minBit 4, minWin=27, winSum=449 TX Vref=28, minBit 3, minWin=28, winSum=453 TX Vref=30, minBit 11, minWin=27, winSum=451 TX Vref=32, minBit 0, minWin=28, winSum=450 [TxChooseVref] Worse bit 3, Min win 28, Win sum 453, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -111 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Final RX Vref Byte 0 = 49 to rank0 Final RX Vref Byte 1 = 55 to rank0 Final RX Vref Byte 0 = 49 to rank1 Final RX Vref Byte 1 = 55 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 84, DQM1 = 74 DQ Delay: DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps CH0 RK0: MR19=606, MR18=3434 CH0_RK0: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 31 => 31 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3131 3030 | 0 0 | (1 0) (1 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2828 3030 | 1 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 0) best DQS0 dly(MCK, UI, PI) = (0, 10, 0) best DQS1 dly(MCK, UI, PI) = (0, 10, 0) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 82, DQM1 = 74 DQ Delay: DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6) Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 12, minWin=27, winSum=447 TX Vref=24, minBit 0, minWin=28, winSum=453 TX Vref=26, minBit 14, minWin=27, winSum=450 TX Vref=28, minBit 2, minWin=28, winSum=457 TX Vref=30, minBit 2, minWin=28, winSum=459 TX Vref=32, minBit 0, minWin=28, winSum=458 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -111 -> 252, step: 8 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 86, DQM1 = 74 DQ Delay: DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84 [DQSOSCAuto] RK1, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps CH0 RK1: MR19=606, MR18=4848 CH0_RK1: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (28 cell) CA1 delay=37 (6~68),Diff = 4 PI (28 cell) CA2 delay=34 (4~65),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 1 PI (7 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 36 (6~67) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 3 PI (21 cell) CA1 delay=37 (6~68),Diff = 4 PI (28 cell) CA2 delay=34 (4~65),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 1 PI (7 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 24 => 24 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1) 0 7 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 30) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 0) best DQS0 dly(MCK, UI, PI) = (0, 10, 0) best DQS1 dly(MCK, UI, PI) = (0, 9, 30) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 81, DQM1 = 72 DQ Delay: DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77 DQ4 =77, DQ5 =101, DQ6 =85, DQ7 =77 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 3, minWin=27, winSum=444 TX Vref=24, minBit 9, minWin=27, winSum=448 TX Vref=26, minBit 0, minWin=28, winSum=452 TX Vref=28, minBit 0, minWin=28, winSum=455 TX Vref=30, minBit 0, minWin=28, winSum=459 TX Vref=32, minBit 9, minWin=27, winSum=458 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -111 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Set Vref, RX VrefLevel [Byte0]: 76 [Byte1]: 76 Final RX Vref Byte 0 = 59 to rank0 Final RX Vref Byte 1 = 56 to rank0 Final RX Vref Byte 0 = 59 to rank1 Final RX Vref Byte 1 = 56 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 81, DQM1 = 75 DQ Delay: DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps CH1 RK0: MR19=606, MR18=5454 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 24 => 24 Write leveling (Byte 1): 23 => 23 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 28) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 2) best DQS0 dly(MCK, UI, PI) = (0, 9, 28) best DQS1 dly(MCK, UI, PI) = (0, 10, 2) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 84, DQM1 = 72 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=28, winSum=452 TX Vref=24, minBit 0, minWin=28, winSum=453 TX Vref=26, minBit 0, minWin=28, winSum=457 TX Vref=28, minBit 0, minWin=28, winSum=457 TX Vref=30, minBit 0, minWin=28, winSum=458 TX Vref=32, minBit 0, minWin=28, winSum=456 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -111 -> 252, step: 8 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 83, DQM1 = 74 DQ Delay: DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =80 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps CH1 RK1: MR19=606, MR18=3A3A CH1_RK1: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1600 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Revision 606. [GetDramInforAfterCalByMRR] Revision 2 0. MR0 0x3939 MR8 0x1111 RK0, DieNum 1, Density 16Gb, RKsize 16Gb. MR0 0x3939 MR8 0x1111 RK1, DieNum 1, Density 16Gb, RKsize 16Gb. [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc [FAST_K] Save calibration result to emmc dram_init: config_dvfs: 1 dramc_set_vcore_voltage set vcore to 662500 Read voltage for 1200, 2 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=15 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 2400 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 17 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1200 CA_MCKIO = 1200 MCKIO_SEMI = 0 PLL_FREQ = 2366 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 2400,PCW = 0X5b00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:2 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 12 [0] MIN Duty = 4938%(X100), DQS PI = 52 [0] AVG Duty = 5015%(X100) CH0 CLK Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 30 [0] MIN Duty = 5031%(X100), DQS PI = 4 [0] AVG Duty = 5078%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 52 [0] MIN Duty = 4906%(X100), DQS PI = 14 [0] AVG Duty = 4968%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 94% CH0 DQS 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5124%(X100), DQS PI = 20 [0] MIN Duty = 4969%(X100), DQS PI = 40 [0] AVG Duty = 5046%(X100) ==DQM 1 == Final DQM duty delay cell = 4 [4] MAX Duty = 5187%(X100), DQS PI = 54 [4] MIN Duty = 5000%(X100), DQS PI = 18 [4] AVG Duty = 5093%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 155% CH0 DQM 1 Duty spec in!! Max-Min= 187% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 16 [-4] MIN Duty = 4813%(X100), DQS PI = 8 [-4] AVG Duty = 4937%(X100) ==DQ 1 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 6 [-4] MIN Duty = 4876%(X100), DQS PI = 38 [-4] AVG Duty = 4969%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 249% CH0 DQ 1 Duty spec in!! Max-Min= 186% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:5 CA:-5 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5094%(X100), DQS PI = 24 [0] MIN Duty = 4876%(X100), DQS PI = 52 [0] AVG Duty = 4985%(X100) CH1 CLK Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 16 [0] MIN Duty = 4875%(X100), DQS PI = 40 [0] AVG Duty = 5000%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 18 [-4] MIN Duty = 4907%(X100), DQS PI = 56 [-4] AVG Duty = 4953%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 250% CH1 DQS 1 Duty spec in!! Max-Min= 93% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5093%(X100), DQS PI = 32 [-4] MIN Duty = 4844%(X100), DQS PI = 40 [-4] AVG Duty = 4968%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5094%(X100), DQS PI = 20 [-4] MIN Duty = 4906%(X100), DQS PI = 44 [-4] AVG Duty = 5000%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 249% CH1 DQM 1 Duty spec in!! Max-Min= 188% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5062%(X100), DQS PI = 0 [0] MIN Duty = 4969%(X100), DQS PI = 42 [0] AVG Duty = 5015%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5000%(X100), DQS PI = 6 [0] MIN Duty = 4876%(X100), DQS PI = 16 [0] AVG Duty = 4938%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 93% CH1 DQ 1 Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 6 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37 [CA 0] Center 39 (9~70) winsize 62 [CA 1] Center 39 (9~70) winsize 62 [CA 2] Center 36 (5~67) winsize 63 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 34 (3~65) winsize 63 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (9~70),Diff = 6 PI (28 cell) CA1 delay=39 (9~70),Diff = 6 PI (28 cell) CA2 delay=36 (5~67),Diff = 3 PI (14 cell) CA3 delay=35 (4~66),Diff = 2 PI (9 cell) CA4 delay=34 (3~65),Diff = 1 PI (4 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37 [CA 0] Center 39 (8~70) winsize 63 [CA 1] Center 39 (8~70) winsize 63 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (9~70),Diff = 6 PI (28 cell) CA1 delay=39 (9~70),Diff = 6 PI (28 cell) CA2 delay=35 (5~66),Diff = 2 PI (9 cell) CA3 delay=35 (4~66),Diff = 2 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~39) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 20 | B1->B0 | 2e2e 2b2b | 0 0 | (1 0) (1 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 18) best DQS0 dly(MCK, UI, PI) = (0, 15, 16) best DQS1 dly(MCK, UI, PI) = (0, 15, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 106 DQ Delay: DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7) Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6) Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 8, minWin=25, winSum=415 TX Vref=24, minBit 9, minWin=25, winSum=421 TX Vref=26, minBit 8, minWin=25, winSum=426 TX Vref=28, minBit 8, minWin=26, winSum=434 TX Vref=30, minBit 8, minWin=26, winSum=432 TX Vref=32, minBit 10, minWin=26, winSum=434 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7) Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6) Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -21 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Final RX Vref Byte 0 = 49 to rank0 Final RX Vref Byte 1 = 51 to rank0 Final RX Vref Byte 0 = 49 to rank1 Final RX Vref Byte 1 = 51 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 114, DQM1 = 105 DQ Delay: DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =122 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps CH0 RK0: MR19=404, MR18=606 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 11 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0) 0 11 20 | B1->B0 | 3131 2828 | 1 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0) 0 12 20 | B1->B0 | 3b3b 4545 | 1 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 16) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 22) best DQS0 dly(MCK, UI, PI) = (0, 15, 16) best DQS1 dly(MCK, UI, PI) = (0, 15, 22) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 116, DQM1 = 106 DQ Delay: DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =107 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7) Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7) Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 8, minWin=25, winSum=417 TX Vref=24, minBit 1, minWin=26, winSum=427 TX Vref=26, minBit 8, minWin=26, winSum=429 TX Vref=28, minBit 10, minWin=25, winSum=434 TX Vref=30, minBit 12, minWin=26, winSum=436 TX Vref=32, minBit 8, minWin=26, winSum=437 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 32 Final TX Range 1 Vref 32 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7) Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7) Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH0 RK1 DATLAT Default: 0xc 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -21 -> 252, step: 4 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 106 DQ Delay: DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps CH0 RK1: MR19=404, MR18=1111 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (1~63) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 5 PI (24 cell) CA1 delay=37 (7~68),Diff = 5 PI (24 cell) CA2 delay=34 (4~65),Diff = 2 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (4 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (1~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 34 (3~65) winsize 63 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 31 (1~62) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 6 PI (28 cell) CA1 delay=37 (7~68),Diff = 6 PI (28 cell) CA2 delay=34 (4~65),Diff = 3 PI (14 cell) CA3 delay=33 (3~64),Diff = 2 PI (9 cell) CA4 delay=32 (2~63),Diff = 1 PI (4 cell) CA5 delay=31 (1~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=31 [CBTSetCACLKResult] CA Dly = 31 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 21 => 21 Write leveling (Byte 1): 21 => 21 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 0) (1 0) 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 3131 4242 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 14) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 20) best DQS0 dly(MCK, UI, PI) = (0, 15, 14) best DQS1 dly(MCK, UI, PI) = (0, 15, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 116, DQM1 = 107 DQ Delay: DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =99 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6) Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 7, minWin=25, winSum=413 TX Vref=24, minBit 8, minWin=25, winSum=420 TX Vref=26, minBit 0, minWin=26, winSum=423 TX Vref=28, minBit 0, minWin=26, winSum=427 TX Vref=30, minBit 0, minWin=26, winSum=428 TX Vref=32, minBit 10, minWin=25, winSum=427 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6) Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -29 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 49 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 49 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 105 DQ Delay: DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps CH1 RK0: MR19=404, MR18=1313 CH1_RK0: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 22 => 22 Write leveling (Byte 1): 22 => 22 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0) 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0) 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 12) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 14) best DQS0 dly(MCK, UI, PI) = (0, 15, 12) best DQS1 dly(MCK, UI, PI) = (0, 15, 14) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 117, DQM1 = 105 DQ Delay: DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 3, minWin=25, winSum=419 TX Vref=24, minBit 9, minWin=25, winSum=427 TX Vref=26, minBit 3, minWin=26, winSum=431 TX Vref=28, minBit 8, minWin=26, winSum=431 TX Vref=30, minBit 9, minWin=26, winSum=431 TX Vref=32, minBit 0, minWin=26, winSum=430 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 26 Final TX Range 1 Vref 26 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH1 RK1 DATLAT Default: 0xc 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -29 -> 252, step: 4 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 114, DQM1 = 103 DQ Delay: DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =110 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps CH1 RK1: MR19=404, MR18=808 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 2400 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 600, 5 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=19 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 600 CA_MCKIO = 600 MCKIO_SEMI = 0 PLL_FREQ = 2288 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1200,PCW = 0X5800 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 16 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (6~66) winsize 61 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~66),Diff = 3 PI (28 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 31 => 31 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 8 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0) 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2929 3333 | 0 0 | (0 0) (1 1) 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 10) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 12) best DQS0 dly(MCK, UI, PI) = (0, 9, 10) best DQS1 dly(MCK, UI, PI) = (0, 9, 12) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 39, DQM1 = 33 DQ Delay: DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 51 Final RX Vref Byte 0 = 49 to rank0 Final RX Vref Byte 1 = 51 to rank0 Final RX Vref Byte 0 = 49 to rank1 Final RX Vref Byte 1 = 51 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 39, DQM1 = 30 DQ Delay: DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps CH0 RK0: MR19=808, MR18=5050 CH0_RK0: MR19=0x808, MR18=0x5050, DQSOSC=394, MR23=63, INC=168, DEC=112 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 32 => 32 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (1 0) (1 1) 0 5 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 10) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 6) best DQS0 dly(MCK, UI, PI) = (0, 9, 10) best DQS1 dly(MCK, UI, PI) = (0, 9, 6) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 41, DQM1 = 33 DQ Delay: DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK1 DATLAT Default: 0x8 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 42, DQM1 = 31 DQ Delay: DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps CH0 RK1: MR19=808, MR18=6262 CH0_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=33 (3~64),Diff = 0 PI (0 cell) CA3 delay=33 (3~64),Diff = 0 PI (0 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 4 (0~35) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 34 (4~65) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 3 PI (28 cell) CA1 delay=35 (5~65),Diff = 3 PI (28 cell) CA2 delay=33 (3~64),Diff = 1 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (9 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 4 (0~35) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 27 => 27 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1) 0 5 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0) 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3535 4343 | 0 1 | (1 1) (0 0) 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 4) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 6) best DQS0 dly(MCK, UI, PI) = (0, 9, 4) best DQS1 dly(MCK, UI, PI) = (0, 9, 6) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 39, DQM1 = 31 DQ Delay: DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6) Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6) Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 49 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 49 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 49 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 38, DQM1 = 30 DQ Delay: DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps CH1 RK0: MR19=808, MR18=6F6F CH1_RK0: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0) 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0) 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3636 4545 | 1 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 2) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 8) best DQS0 dly(MCK, UI, PI) = (0, 9, 2) best DQS1 dly(MCK, UI, PI) = (0, 9, 8) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 39, DQM1 = 33 DQ Delay: DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK1 DATLAT Default: 0x8 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 37, DQM1 = 29 DQ Delay: DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps CH1 RK1: MR19=808, MR18=5454 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 662500 Read voltage for 933, 3 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=17 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1866 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 933 CA_MCKIO = 933 MCKIO_SEMI = 0 PLL_FREQ = 3732 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1866,PCW = 0X8f00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 8 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 38 (8~69) winsize 62 [CA 1] Center 38 (7~69) winsize 63 [CA 2] Center 36 (6~67) winsize 62 [CA 3] Center 36 (6~66) winsize 61 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=38 (8~69),Diff = 4 PI (24 cell) CA1 delay=38 (7~69),Diff = 4 PI (24 cell) CA2 delay=36 (6~67),Diff = 2 PI (12 cell) CA3 delay=36 (6~66),Diff = 2 PI (12 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 38 (8~69) winsize 62 [CA 1] Center 38 (7~69) winsize 63 [CA 2] Center 36 (6~67) winsize 62 [CA 3] Center 35 (5~66) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=38 (8~69),Diff = 4 PI (24 cell) CA1 delay=38 (7~69),Diff = 4 PI (24 cell) CA2 delay=36 (6~67),Diff = 2 PI (12 cell) CA3 delay=36 (6~66),Diff = 2 PI (12 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~39) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 29 => 29 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 20 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0) 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 22) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 22) best DQS0 dly(MCK, UI, PI) = (0, 14, 22) best DQS1 dly(MCK, UI, PI) = (0, 14, 22) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 86 DQ Delay: DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =91 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2) Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 51 Final RX Vref Byte 0 = 49 to rank0 Final RX Vref Byte 1 = 51 to rank0 Final RX Vref Byte 0 = 49 to rank1 Final RX Vref Byte 1 = 51 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 87 DQ Delay: DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps CH0 RK0: MR19=505, MR18=2424 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 20 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1) 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 2c2c 3636 | 1 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 22) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 22) best DQS0 dly(MCK, UI, PI) = (0, 14, 22) best DQS1 dly(MCK, UI, PI) = (0, 14, 22) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 84 DQ Delay: DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 98, DQM1 = 86 DQ Delay: DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =108 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps CH0 RK1: MR19=505, MR18=2929 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 35 (5~65) winsize 61 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 4 PI (24 cell) CA1 delay=37 (6~68),Diff = 4 PI (24 cell) CA2 delay=35 (5~65),Diff = 2 PI (12 cell) CA3 delay=34 (4~65),Diff = 1 PI (6 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~64) winsize 61 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 4 PI (24 cell) CA1 delay=37 (6~68),Diff = 4 PI (24 cell) CA2 delay=35 (5~65),Diff = 2 PI (12 cell) CA3 delay=34 (4~64),Diff = 1 PI (6 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~37) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 24 => 24 Write leveling (Byte 1): 24 => 24 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0) 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0) 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1) 0 11 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 18) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 18) best DQS0 dly(MCK, UI, PI) = (0, 14, 18) best DQS1 dly(MCK, UI, PI) = (0, 14, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 87 DQ Delay: DQ0 =103, DQ1 =87, DQ2 =87, DQ3 =91 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79 DQ12 =91, DQ13 =103, DQ14 =91, DQ15 =99 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 49 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 49 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 49 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 94, DQM1 = 88 DQ Delay: DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90 DQ4 =94, DQ5 =106, DQ6 =102, DQ7 =92 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80 DQ12 =96, DQ13 =100, DQ14 =98, DQ15 =98 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps CH1 RK0: MR19=505, MR18=3131 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0) 0 10 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0) 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 16) best DQS0 dly(MCK, UI, PI) = (0, 14, 16) best DQS1 dly(MCK, UI, PI) = (0, 14, 16) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 87 DQ Delay: DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =91 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 87 DQ Delay: DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80 DQ12 =98, DQ13 =96, DQ14 =94, DQ15 =96 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps CH1 RK1: MR19=505, MR18=1F1F CH1_RK1: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1866 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 400, 6 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=20 sv_algorithm_assistance_LP4_800 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 800 CKR = 1 DQ_P2S_RATIO = 4 =================================== CA_P2S_RATIO = 4 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 1 CA_SEMI_OPEN = 1 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 4 DQ_AAMCK_DIV = 0 CA_AAMCK_DIV = 0 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 400 MCKIO_SEMI = 400 PLL_FREQ = 3016 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 32 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 800,PCW = 0X7400 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 0 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 18 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == Write leveling (Byte 0): 32 => 0 Write leveling (Byte 1): 32 => 0 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 51, DQS1 = 59 DQM Delay: DQM0 = 12, DQM1 = 13 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) [DATLAT] Freq=400, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 51 Final RX Vref Byte 0 = 49 to rank0 Final RX Vref Byte 1 = 51 to rank0 Final RX Vref Byte 0 = 49 to rank1 Final RX Vref Byte 1 = 51 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 52, DQS1 = 68 DQM Delay: DQM0 = 9, DQM1 = 18 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps CH0 RK0: MR19=C0C, MR18=ADAD CH0_RK0: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 24) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 24) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 51, DQS1 = 59 DQM Delay: DQM0 = 14, DQM1 = 14 DQ Delay: DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =0 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH0 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 52, DQS1 = 64 DQM Delay: DQM0 = 11, DQM1 = 14 DQ Delay: DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps CH0 RK1: MR19=C0C, MR18=CCCC CH0_RK1: MR19=0xC0C, MR18=0xCCCC, DQSOSC=384, MR23=63, INC=400, DEC=267 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == Write leveling (Byte 0): 32 => 0 Write leveling (Byte 1): 32 => 0 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 6, DQM1 = 15 DQ Delay: DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) [DATLAT] Freq=400, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 49 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 49 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 49 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 48, DQS1 = 64 DQM Delay: DQM0 = 8, DQM1 = 16 DQ Delay: DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps CH1 RK0: MR19=C0C, MR18=D4D4 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 10, DQM1 = 18 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3) Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH1 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 48, DQS1 = 64 DQM Delay: DQM0 = 9, DQM1 = 15 DQ Delay: DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK1, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps CH1 RK1: MR19=C0C, MR18=A3A3 CH1_RK1: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 800 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=13 sv_algorithm_assistance_LP4_3733 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 0 NEW_8X_MODE = 1 =================================== =================================== data_rate = 3200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 12 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1600 CA_MCKIO = 1600 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 3200,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:2 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 24 [0] MIN Duty = 4938%(X100), DQS PI = 54 [0] AVG Duty = 5062%(X100) CH0 CLK Duty spec in!! Max-Min= 249% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 34 [0] MIN Duty = 5000%(X100), DQS PI = 8 [0] AVG Duty = 5078%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 6 [0] MIN Duty = 4876%(X100), DQS PI = 18 [0] AVG Duty = 4953%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 156% CH0 DQS 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 22 [0] MIN Duty = 4907%(X100), DQS PI = 42 [0] AVG Duty = 5047%(X100) ==DQM 1 == Final DQM duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 50 [0] MIN Duty = 4782%(X100), DQS PI = 16 [0] AVG Duty = 4906%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 280% CH0 DQM 1 Duty spec in!! Max-Min= 249% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5218%(X100), DQS PI = 18 [0] MIN Duty = 4938%(X100), DQS PI = 54 [0] AVG Duty = 5078%(X100) ==DQ 1 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 4 [-4] MIN Duty = 4844%(X100), DQS PI = 34 [-4] AVG Duty = 4953%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 280% CH0 DQ 1 Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:4 CA:-5 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 20 [0] MIN Duty = 4906%(X100), DQS PI = 50 [0] AVG Duty = 5031%(X100) CH1 CLK Duty spec in!! Max-Min= 250% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 20 [0] MIN Duty = 4876%(X100), DQS PI = 44 [0] AVG Duty = 5031%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 18 [-4] MIN Duty = 4875%(X100), DQS PI = 38 [-4] AVG Duty = 4937%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 311% CH1 DQS 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 34 [-4] MIN Duty = 4782%(X100), DQS PI = 44 [-4] AVG Duty = 4922%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5093%(X100), DQS PI = 16 [-4] MIN Duty = 4907%(X100), DQS PI = 38 [-4] AVG Duty = 5000%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 280% CH1 DQM 1 Duty spec in!! Max-Min= 186% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 18 [0] MIN Duty = 4938%(X100), DQS PI = 46 [0] AVG Duty = 5015%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 4 [0] MIN Duty = 4876%(X100), DQS PI = 28 [0] AVG Duty = 4953%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 155% CH1 DQ 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 4 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2) [MiockJmeterHQA] [DramcMiockJmeter] u1RxGatingPI = 0 0 : 4363, 4138 4 : 4257, 4030 8 : 4253, 4026 12 : 4253, 4027 16 : 4253, 4026 20 : 4362, 4137 24 : 4252, 4026 28 : 4366, 4140 32 : 4363, 4137 36 : 4250, 4025 40 : 4253, 4027 44 : 4253, 4027 48 : 4252, 4026 52 : 4253, 4027 56 : 4252, 4027 60 : 4252, 4027 64 : 4253, 4026 68 : 4252, 4027 72 : 4255, 4030 76 : 4252, 4027 80 : 4252, 4027 84 : 4249, 4027 88 : 4258, 4031 92 : 4253, 4029 96 : 4250, 4026 100 : 4253, 1628 104 : 4360, 0 108 : 4253, 0 112 : 4250, 0 116 : 4250, 0 120 : 4258, 0 124 : 4255, 0 128 : 4250, 0 132 : 4360, 0 136 : 4250, 0 140 : 4250, 0 144 : 4360, 0 148 : 4250, 0 152 : 4360, 0 156 : 4250, 0 160 : 4250, 0 164 : 4361, 0 168 : 4249, 0 172 : 4250, 0 176 : 4252, 0 180 : 4249, 0 184 : 4365, 0 188 : 4250, 0 192 : 4252, 0 196 : 4249, 0 200 : 4255, 0 204 : 4250, 0 208 : 4361, 0 212 : 4253, 0 216 : 4250, 0 220 : 4360, 818 224 : 4250, 4008 228 : 4250, 4026 232 : 4250, 4027 236 : 4249, 4027 240 : 4250, 4027 244 : 4253, 4029 248 : 4250, 4027 252 : 4360, 4138 256 : 4365, 4139 260 : 4248, 4024 264 : 4250, 4027 268 : 4252, 4030 272 : 4250, 4026 276 : 4250, 4026 280 : 4250, 4027 284 : 4360, 4138 288 : 4360, 4137 292 : 4250, 4027 296 : 4250, 4027 300 : 4360, 4138 304 : 4363, 4139 308 : 4250, 4026 312 : 4253, 4029 316 : 4363, 4140 320 : 4250, 4027 324 : 4254, 4029 328 : 4250, 4027 332 : 4253, 4029 336 : 4360, 3807 340 : 4360, 1881 MIOCK jitter meter ch=0 1T = (340-100) = 240 dly cells Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (11~72) winsize 62 [CA 1] Center 41 (11~72) winsize 62 [CA 2] Center 37 (7~68) winsize 62 [CA 3] Center 37 (7~67) winsize 61 [CA 4] Center 35 (5~66) winsize 62 [CA 5] Center 35 (5~65) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=41 (11~72),Diff = 6 PI (21 cell) CA1 delay=41 (11~72),Diff = 6 PI (21 cell) CA2 delay=37 (7~68),Diff = 2 PI (7 cell) CA3 delay=37 (7~67),Diff = 2 PI (7 cell) CA4 delay=35 (5~66),Diff = 0 PI (0 cell) CA5 delay=35 (5~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=35 [CBTSetCACLKResult] CA Dly = 35 CS Dly: 11 (0~42) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~73) winsize 62 [CA 1] Center 42 (12~73) winsize 62 [CA 2] Center 38 (9~68) winsize 60 [CA 3] Center 38 (8~68) winsize 61 [CA 4] Center 36 (6~66) winsize 61 [CA 5] Center 36 (6~66) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=42 (12~72),Diff = 7 PI (25 cell) CA1 delay=42 (12~72),Diff = 7 PI (25 cell) CA2 delay=38 (9~68),Diff = 3 PI (10 cell) CA3 delay=37 (8~67),Diff = 2 PI (7 cell) CA4 delay=36 (6~66),Diff = 1 PI (3 cell) CA5 delay=35 (6~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=35 [CBTSetCACLKResult] CA Dly = 35 CS Dly: 11 (0~42) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1) 0 12 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1) 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0) 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 1, 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 4) best DQS0 dly(MCK, UI, PI) = (1, 1, 0) best DQS1 dly(MCK, UI, PI) = (1, 1, 4) best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 123 DQ Delay: DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3) Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3) Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 8, minWin=22, winSum=372 TX Vref=18, minBit 9, minWin=22, winSum=377 TX Vref=20, minBit 8, minWin=23, winSum=390 TX Vref=22, minBit 8, minWin=23, winSum=395 TX Vref=24, minBit 8, minWin=24, winSum=411 TX Vref=26, minBit 8, minWin=24, winSum=413 TX Vref=28, minBit 8, minWin=25, winSum=417 TX Vref=30, minBit 0, minWin=25, winSum=412 TX Vref=32, minBit 1, minWin=24, winSum=403 TX Vref=34, minBit 8, minWin=23, winSum=388 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=14 cells (4 PI) u2DelayCellOfst[1]=18 cells (5 PI) u2DelayCellOfst[2]=14 cells (4 PI) u2DelayCellOfst[3]=10 cells (3 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=18 cells (5 PI) u2DelayCellOfst[7]=18 cells (5 PI) Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3) Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=3 cells (1 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=18 cells (5 PI) u2DelayCellOfst[13]=18 cells (5 PI) u2DelayCellOfst[14]=18 cells (5 PI) u2DelayCellOfst[15]=14 cells (4 PI) Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 11 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Final RX Vref Byte 0 = 55 to rank0 Final RX Vref Byte 1 = 56 to rank0 Final RX Vref Byte 0 = 55 to rank1 Final RX Vref Byte 1 = 56 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 126, DQM1 = 120 DQ Delay: DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps CH0 RK0: MR19=303, MR18=1E1E CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0) 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0) 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 30) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 2) best DQS0 dly(MCK, UI, PI) = (1, 0, 30) best DQS1 dly(MCK, UI, PI) = (1, 1, 2) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 124 DQ Delay: DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3) Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3) Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 1, minWin=22, winSum=380 TX Vref=18, minBit 11, minWin=22, winSum=385 TX Vref=20, minBit 9, minWin=23, winSum=391 TX Vref=22, minBit 8, minWin=23, winSum=398 TX Vref=24, minBit 8, minWin=24, winSum=407 TX Vref=26, minBit 1, minWin=24, winSum=413 TX Vref=28, minBit 8, minWin=24, winSum=413 TX Vref=30, minBit 8, minWin=24, winSum=406 TX Vref=32, minBit 1, minWin=24, winSum=400 TX Vref=34, minBit 8, minWin=23, winSum=390 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26 Final TX Range 0 Vref 26 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=14 cells (4 PI) u2DelayCellOfst[1]=18 cells (5 PI) u2DelayCellOfst[2]=10 cells (3 PI) u2DelayCellOfst[3]=14 cells (4 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=18 cells (5 PI) u2DelayCellOfst[7]=18 cells (5 PI) Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=14 cells (4 PI) u2DelayCellOfst[13]=14 cells (4 PI) u2DelayCellOfst[14]=18 cells (5 PI) u2DelayCellOfst[15]=14 cells (4 PI) Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3) Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8FFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 11 -> 252, step: 4 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 128, DQM1 = 120 DQ Delay: DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps CH0 RK1: MR19=303, MR18=2020 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (12~71) winsize 60 [CA 1] Center 41 (11~72) winsize 62 [CA 2] Center 37 (8~67) winsize 60 [CA 3] Center 36 (7~66) winsize 60 [CA 4] Center 34 (5~64) winsize 60 [CA 5] Center 34 (5~64) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=41 (12~71),Diff = 7 PI (25 cell) CA1 delay=41 (11~72),Diff = 7 PI (25 cell) CA2 delay=37 (8~67),Diff = 3 PI (10 cell) CA3 delay=36 (7~66),Diff = 2 PI (7 cell) CA4 delay=34 (5~64),Diff = 0 PI (0 cell) CA5 delay=34 (5~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 8 (0~39) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (11~71) winsize 61 [CA 1] Center 41 (11~71) winsize 61 [CA 2] Center 36 (7~66) winsize 60 [CA 3] Center 35 (6~65) winsize 60 [CA 4] Center 34 (5~64) winsize 60 [CA 5] Center 33 (4~63) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=41 (12~71),Diff = 7 PI (25 cell) CA1 delay=41 (11~71),Diff = 7 PI (25 cell) CA2 delay=37 (8~66),Diff = 3 PI (10 cell) CA3 delay=36 (7~65),Diff = 2 PI (7 cell) CA4 delay=34 (5~64),Diff = 0 PI (0 cell) CA5 delay=34 (5~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 8 (0~40) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 21 => 21 Write leveling (Byte 1): 21 => 21 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0) 0 13 0 | B1->B0 | 3333 2424 | 1 0 | (1 1) (1 0) 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 26) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 2) best DQS0 dly(MCK, UI, PI) = (1, 0, 26) best DQS1 dly(MCK, UI, PI) = (1, 1, 2) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112 iDelay=200, Bit 8, Center 103 (48 ~ 159) 112 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 129, DQM1 = 125 DQ Delay: DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127 DQ8 =103, DQ9 =115, DQ10 =127, DQ11 =115 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 3, minWin=21, winSum=369 TX Vref=18, minBit 3, minWin=22, winSum=378 TX Vref=20, minBit 3, minWin=22, winSum=384 TX Vref=22, minBit 1, minWin=23, winSum=393 TX Vref=24, minBit 4, minWin=23, winSum=404 TX Vref=26, minBit 1, minWin=24, winSum=413 TX Vref=28, minBit 3, minWin=24, winSum=413 TX Vref=30, minBit 7, minWin=24, winSum=407 TX Vref=32, minBit 3, minWin=23, winSum=398 TX Vref=34, minBit 3, minWin=23, winSum=394 TX Vref=36, minBit 3, minWin=21, winSum=379 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26 Final TX Range 0 Vref 26 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=14 cells (4 PI) u2DelayCellOfst[1]=10 cells (3 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=3 cells (1 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=18 cells (5 PI) u2DelayCellOfst[6]=14 cells (4 PI) u2DelayCellOfst[7]=3 cells (1 PI) Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=3 cells (1 PI) u2DelayCellOfst[10]=7 cells (2 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=14 cells (4 PI) u2DelayCellOfst[13]=18 cells (5 PI) u2DelayCellOfst[14]=18 cells (5 PI) u2DelayCellOfst[15]=18 cells (5 PI) Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8FFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 3 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Final RX Vref Byte 0 = 62 to rank0 Final RX Vref Byte 1 = 55 to rank0 Final RX Vref Byte 0 = 62 to rank1 Final RX Vref Byte 1 = 55 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 128, DQM1 = 124 DQ Delay: DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps CH1 RK0: MR19=303, MR18=2828 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 22 => 22 Write leveling (Byte 1): 22 => 22 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1) 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0) 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0) 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0) 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 24) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 0, 30) best DQS0 dly(MCK, UI, PI) = (1, 0, 24) best DQS1 dly(MCK, UI, PI) = (1, 0, 30) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24) best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 131, DQM1 = 125 DQ Delay: DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3) Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 4, minWin=22, winSum=374 TX Vref=18, minBit 5, minWin=22, winSum=385 TX Vref=20, minBit 3, minWin=23, winSum=393 TX Vref=22, minBit 1, minWin=24, winSum=400 TX Vref=24, minBit 2, minWin=24, winSum=410 TX Vref=26, minBit 0, minWin=25, winSum=417 TX Vref=28, minBit 0, minWin=25, winSum=421 TX Vref=30, minBit 0, minWin=24, winSum=414 TX Vref=32, minBit 0, minWin=24, winSum=408 TX Vref=34, minBit 0, minWin=23, winSum=398 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=18 cells (5 PI) u2DelayCellOfst[1]=10 cells (3 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=7 cells (2 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=18 cells (5 PI) u2DelayCellOfst[6]=18 cells (5 PI) u2DelayCellOfst[7]=7 cells (2 PI) Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=7 cells (2 PI) u2DelayCellOfst[10]=14 cells (4 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=18 cells (5 PI) u2DelayCellOfst[13]=21 cells (6 PI) u2DelayCellOfst[14]=21 cells (6 PI) u2DelayCellOfst[15]=21 cells (6 PI) Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xF7F, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 3 -> 252, step: 4 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 127, DQM1 = 123 DQ Delay: DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =114 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps CH1 RK1: MR19=303, MR18=1F1F CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 3200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. DramC Write-DBI on PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [FAST_K] Save calibration result to emmc sync common calibartion params. sync cbt_mode0:0, 1:0 dram_init: ddr_geometry: 0 dram_init: ddr_geometry: 0 dram_init: ddr_geometry: 0 0:dram_rank_size:80000000 1:dram_rank_size:80000000 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000 DFS_SHUFFLE_HW_MODE: ON dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 switch to 3200 Mbps bootup [DramcRunTimeConfig] PHYPLL DPM_CONTROL_AFTERK: ON PER_BANK_REFRESH: ON REFRESH_OVERHEAD_REDUCTION: ON CMD_PICG_NEW_MODE: OFF XRTWTW_NEW_MODE: ON XRTRTR_NEW_MODE: ON TX_TRACKING: ON RDSEL_TRACKING: OFF DQS Precalculation for DVFS: ON RX_TRACKING: OFF HW_GATING DBG: ON ZQCS_ENABLE_LP4: ON RX_PICG_NEW_MODE: ON TX_PICG_NEW_MODE: ON ENABLE_RX_DCM_DPHY: ON LOWPOWER_GOLDEN_SETTINGS(DCM): ON DUMMY_READ_FOR_TRACKING: OFF !!! SPM_CONTROL_AFTERK: OFF !!! SPM could not control APHY IMPEDANCE_TRACKING: ON TEMP_SENSOR: ON HW_SAVE_FOR_SR: OFF CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF Read ODT Tracking: ON Refresh Rate DeBounce: ON DFS_NO_QUEUE_FLUSH: ON DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF ENABLE_DFS_RUNTIME_MRW: OFF DDR_RESERVE_NEW_MODE: ON MR_CBT_SWITCH_FREQ: ON ========================= [MEM] 1st complex R/W mem test pass (start addr:0x4c400000) dram_init: ddr_geometry: 0 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1) dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 23425 msecs MRC: failed to locate region type 0. DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal Backing address range [0x40000000:0x80000000) with new page table @0x00112000 Backing address range [0x40000000:0x40200000) with new page table @0x00113000 DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 CBMEM: IMD: root @ 0xfffff000 254 entries. IMD: root @ 0xffffec00 62 entries. FMAP: area RO_VPD found @ 3f8000 (32768 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 577000 (16384 bytes) CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps BS: romstage times (exec / console): total (unknown) / 22962 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled scan_static_bus for Root Device done scan_bus: bus Root Device finished in 8 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 done Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms Enabling resources... done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms Initializing devices... Root Device init init hardware done! 0x00000018: ctrlr->caps 52.000 MHz: ctrlr->f_max 0.400 MHz: ctrlr->f_min 0x40ff8080: ctrlr->voltages sclk: 390625 Bus Width = 1 sclk: 390625 Bus Width = 1 Early init status = 3 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: [SSUSB] Setting up USB HOST controller... [SSUSB] u3phy_ports_enable u2p:1, u3p:1 [SSUSB] phy power-on done. FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes) CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes) CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps SPM: binary array size = 0x9dc SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16) spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes) SPM: spm_init done in 34 msecs, spm pc = 0x3f4 configure_display: Starting display init anx7625_power_on_init: Init interface. anx7625_disable_pd_protocol: Disabled PD feature. anx7625_power_on_init: Firmware: ver 0x13, rev 0x0. anx7625_start_dp_work: Secure OCM version=00 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91 sp_tx_get_edid_block: EDID Block = 1 Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 Digital display 6 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4, YCrCb 4:2:2 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: 383680a07038204018303c0035ae10000019 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm 0780 0798 07c8 0820 hborder 0 0438 043b 0447 0458 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 000000000000000000000000000000000000 Manufacturer-specified data, tag 0 Hex of detail: 000000fe00496e666f566973696f6e0a2020 ASCII string: InfoVision Hex of detail: 000000fe00523134304e574635205248200a ASCII string: R140NWF5 RH Checksum Checksum: 0xfb (valid) configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz DSI data_rate: 832800000 bps anx7625_parse_edid: detected IVO panel, use k value 0x3b anx7625_parse_edid: pixelclock(138800). hactive(1920), hsync(48), hfp(24), hbp(88) vactive(1080), vsync(12), vfp(3), vbp(17) anx7625_dsi_config: config dsi. anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4). anx7625_dsi_config: success to config DSI anx7625_dp_start: MIPI phy setup OK. mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4 mtk_ddp_mode_set invalid vrefresh 60 main_disp_path_setup ovl_layer_smi_id_en ovl_layer_smi_id_en ccorr_config aal_config gamma_config postmask_config dither_config framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0 Root Device init finished in 551 msecs CPU_CLUSTER: 0 init Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff APU_MBOX 0x190000b0 = 0x10001 APU_MBOX 0x190001b0 = 0x10001 APU_MBOX 0x190005b0 = 0x10001 APU_MBOX 0x190006b0 = 0x10001 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes) CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes) CPU_CLUSTER: 0 init finished in 81 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms FMAP: area RW_ELOG found @ 57f000 (4096 bytes) ELOG: NV offset 0x57f000 size 0x1000 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-06-04 14:47:25 UTC out: cmd=0x121: 03 db 21 01 00 00 00 00 in-header: 03 f0 00 00 2c 00 00 00 in-data: 73 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ELOG: Event(A1) added with size 10 at 2024-06-04 14:47:25 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2024-06-04 14:47:25 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms Writing coreboot table at 0xffe64000 0. 000000000010a000-0000000000113fff: RAMSTAGE 1. 0000000040000000-00000000400fffff: RAM 2. 0000000040100000-000000004032afff: RAMSTAGE 3. 000000004032b000-00000000545fffff: RAM 4. 0000000054600000-000000005465ffff: BL31 5. 0000000054660000-00000000ffe63fff: RAM 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES 7. 0000000100000000-000000013fffffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE EC in RW | 0x000000aa | low | undefined EC interrupt | 0x00000005 | low | undefined TPM interrupt | 0x000000ab | high | undefined SD card detect | 0x00000011 | high | undefined speaker enable | 0x00000093 | high | undefined out: cmd=0x6: 03 f7 06 00 00 00 00 00 in-header: 03 f8 00 00 02 00 00 00 in-data: 03 00 ADC[4]: Raw value=668958 ID=5 ADC[3]: Raw value=212917 ID=1 RAM Code: 0x51 ADC[6]: Raw value=74778 ID=0 ADC[5]: Raw value=211444 ID=1 SKU Code: 0x1 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 15c8 coreboot table: 964 bytes. IMD ROOT 0. 0xfffff000 0x00001000 IMD SMALL 1. 0xffffe000 0x00001000 RO MCACHE 2. 0xffffc000 0x00001104 CONSOLE 3. 0xfff7c000 0x00080000 FMAP 4. 0xfff7b000 0x00000452 TIME STAMP 5. 0xfff7a000 0x00000910 VBOOT WORK 6. 0xfff66000 0x00014000 RAMOOPS 7. 0xffe66000 0x00100000 COREBOOT 8. 0xffe64000 0x00002000 IMD small region: IMD ROOT 0. 0xffffec00 0x00000400 VPD 1. 0xffffeb80 0x0000006c MMC STATUS 2. 0xffffeb60 0x00000004 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6 Initialized TPM device CR50 revision 0 Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=0) New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178 it's not compressed! [ 0x80000000, 8004f178, 0x821a7280) <- 40100038 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108 Loading segment from ROM address 0x4010001c Entry Point 0x80000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms Jumping to boot code at 0x80000000(0xffe64000) CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=1) New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470 using LZMA [ 0x54600000, 54614abc, 0x5462e000) <- 40100038 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544 Loading segment from ROM address 0x4010001c Entry Point 0x54601000 Loaded segments NOTICE: MT8192 bl31_setup NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021 WARNING: region 0: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 1: WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d WARNING: region 2: WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d WARNING: region 3: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 4: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 5: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 6: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 7: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0 INFO: [APUAPC] vio 0 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS! INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS! INFO: [APUAPC] D0_APC_0: 0x400510 INFO: [APUAPC] D0_APC_1: 0x0 INFO: [APUAPC] D0_APC_2: 0x1540 INFO: [APUAPC] D0_APC_3: 0x0 INFO: [APUAPC] D1_APC_0: 0xffffffff INFO: [APUAPC] D1_APC_1: 0xffffffff INFO: [APUAPC] D1_APC_2: 0x3fffff INFO: [APUAPC] D1_APC_3: 0x0 INFO: [APUAPC] D2_APC_0: 0xffffffff INFO: [APUAPC] D2_APC_1: 0xffffffff INFO: [APUAPC] D2_APC_2: 0x3fffff INFO: [APUAPC] D2_APC_3: 0x0 INFO: [APUAPC] D3_APC_0: 0xffffffff INFO: [APUAPC] D3_APC_1: 0xffffffff INFO: [APUAPC] D3_APC_2: 0x3fffff INFO: [APUAPC] D3_APC_3: 0x0 INFO: [APUAPC] D4_APC_0: 0xffffffff INFO: [APUAPC] D4_APC_1: 0xffffffff INFO: [APUAPC] D4_APC_2: 0x3fffff INFO: [APUAPC] D4_APC_3: 0x0 INFO: [APUAPC] D5_APC_0: 0xffffffff INFO: [APUAPC] D5_APC_1: 0xffffffff INFO: [APUAPC] D5_APC_2: 0x3fffff INFO: [APUAPC] D5_APC_3: 0x0 INFO: [APUAPC] D6_APC_0: 0xffffffff INFO: [APUAPC] D6_APC_1: 0xffffffff INFO: [APUAPC] D6_APC_2: 0x3fffff INFO: [APUAPC] D6_APC_3: 0x0 INFO: [APUAPC] D7_APC_0: 0xffffffff INFO: [APUAPC] D7_APC_1: 0xffffffff INFO: [APUAPC] D7_APC_2: 0x3fffff INFO: [APUAPC] D7_APC_3: 0x0 INFO: [APUAPC] D8_APC_0: 0xffffffff INFO: [APUAPC] D8_APC_1: 0xffffffff INFO: [APUAPC] D8_APC_2: 0x3fffff INFO: [APUAPC] D8_APC_3: 0x0 INFO: [APUAPC] D9_APC_0: 0xffffffff INFO: [APUAPC] D9_APC_1: 0xffffffff INFO: [APUAPC] D9_APC_2: 0x3fffff INFO: [APUAPC] D9_APC_3: 0x0 INFO: [APUAPC] D10_APC_0: 0xffffffff INFO: [APUAPC] D10_APC_1: 0xffffffff INFO: [APUAPC] D10_APC_2: 0x3fffff INFO: [APUAPC] D10_APC_3: 0x0 INFO: [APUAPC] D11_APC_0: 0xffffffff INFO: [APUAPC] D11_APC_1: 0xffffffff INFO: [APUAPC] D11_APC_2: 0x3fffff INFO: [APUAPC] D11_APC_3: 0x0 INFO: [APUAPC] D12_APC_0: 0xffffffff INFO: [APUAPC] D12_APC_1: 0xffffffff INFO: [APUAPC] D12_APC_2: 0x3fffff INFO: [APUAPC] D12_APC_3: 0x0 INFO: [APUAPC] D13_APC_0: 0xffffffff INFO: [APUAPC] D13_APC_1: 0xffffffff INFO: [APUAPC] D13_APC_2: 0x3fffff INFO: [APUAPC] D13_APC_3: 0x0 INFO: [APUAPC] D14_APC_0: 0xffffffff INFO: [APUAPC] D14_APC_1: 0xffffffff INFO: [APUAPC] D14_APC_2: 0x3fffff INFO: [APUAPC] D14_APC_3: 0x0 INFO: [APUAPC] D15_APC_0: 0xffffffff INFO: [APUAPC] D15_APC_1: 0xffffffff INFO: [APUAPC] D15_APC_2: 0x3fffff INFO: [APUAPC] D15_APC_3: 0x0 INFO: [APUAPC] APC_CON: 0x4 INFO: [NOCDAPC] D0_APC_0: 0x0 INFO: [NOCDAPC] D0_APC_1: 0x0 INFO: [NOCDAPC] D1_APC_0: 0x0 INFO: [NOCDAPC] D1_APC_1: 0xfff INFO: [NOCDAPC] D2_APC_0: 0x0 INFO: [NOCDAPC] D2_APC_1: 0xfff INFO: [NOCDAPC] D3_APC_0: 0x0 INFO: [NOCDAPC] D3_APC_1: 0xfff INFO: [NOCDAPC] D4_APC_0: 0x0 INFO: [NOCDAPC] D4_APC_1: 0xfff INFO: [NOCDAPC] D5_APC_0: 0x0 INFO: [NOCDAPC] D5_APC_1: 0xfff INFO: [NOCDAPC] D6_APC_0: 0x0 INFO: [NOCDAPC] D6_APC_1: 0xfff INFO: [NOCDAPC] D7_APC_0: 0x0 INFO: [NOCDAPC] D7_APC_1: 0xfff INFO: [NOCDAPC] D8_APC_0: 0x0 INFO: [NOCDAPC] D8_APC_1: 0xfff INFO: [NOCDAPC] D9_APC_0: 0x0 INFO: [NOCDAPC] D9_APC_1: 0xfff INFO: [NOCDAPC] D10_APC_0: 0x0 INFO: [NOCDAPC] D10_APC_1: 0xfff INFO: [NOCDAPC] D11_APC_0: 0x0 INFO: [NOCDAPC] D11_APC_1: 0xfff INFO: [NOCDAPC] D12_APC_0: 0x0 INFO: [NOCDAPC] D12_APC_1: 0xfff INFO: [NOCDAPC] D13_APC_0: 0x0 INFO: [NOCDAPC] D13_APC_1: 0xfff INFO: [NOCDAPC] D14_APC_0: 0x0 INFO: [NOCDAPC] D14_APC_1: 0xfff INFO: [NOCDAPC] D15_APC_0: 0x0 INFO: [NOCDAPC] D15_APC_1: 0xfff INFO: [NOCDAPC] APC_CON: 0x4 INFO: [APUAPC] set_apusys_apc done INFO: [DEVAPC] devapc_init done INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 639 INFO: BL31: Initializing runtime services WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing! INFO: SPM: enable CPC mode INFO: mcdi ready for mcusys-off-idle and system suspend INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x80000000 INFO: SPSR = 0x8 Starting depthcharge on Spherion... Wipe memory regions: [0x00000040000000, 0x00000054600000) [0x00000054660000, 0x00000080000000) [0x000000821a7280, 0x000000ffe64000) [0x00000100000000, 0x00000140000000) Initializing XHCI USB controller at 0x11200000. [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38 asurada: tftpboot 192.168.201.1 14167017/tftp-deploy-lmyx8m5s/kernel/image.itb 14167017/tftp-deploy-lmyx8m5s/kernel/cmdline tftpboot 192.168.201.1 14167017/tftp-deploy-lmyx8m5s/kernel/image.ittp-deploy-lmyx8m5s/kernel/cmdline Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device done. MAC: 00:e0:4c:68:03:bd Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.16 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 14167017/tftp-deploy-lmyx8m5s/kernel/image.itb Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ################################################################ 00d80000 ################################################################ 00e00000 ################################################################ 00e80000 ################################################################ 00f00000 ################################################################ 00f80000 ################################################################ 01000000 ################################################################ 01080000 ################################################################ 01100000 ################################################################ 01180000 ################################################################ 01200000 ################################################################ 01280000 ################################################################ 01300000 ################################################################ 01380000 ################################################################ 01400000 ################################################################ 01480000 ################################################################ 01500000 ################################################################ 01580000 ################################################################ 01600000 ################################################################ 01680000 ################################################################ 01700000 ################################################################ 01780000 ################################################################ 01800000 ################################################################ 01880000 ################################################################ 01900000 ################################################################ 01980000 ################################################################ 01a00000 ################################################################ 01a80000 ################################################################ 01b00000 ################################################################ 01b80000 ################################################################ 01c00000 ################################################################ 01c80000 ################################################################ 01d00000 ################################################################ 01d80000 ################################################################ 01e00000 ############################################### done. The bootfile was 31839918 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 14167017/tftp-deploy-lmyx8m5s/kernel/cmdline The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1 Loading FIT. Image ramdisk-1 has 18730005 bytes. Image fdt-1 has 47258 bytes. Image kernel-1 has 13060619 bytes. Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192 Choosing best match conf-1 for compat google,spherion-rev3. Connected to device vid:did:rid of 1ae0:0028:00 tpm_get_response: command 0x17b, return code 0x0 ec_init: CrosEC protocol v3 supported (256, 248) tpm_cleanup: add release locality here. Shutting down all USB controllers. Removing current net device Exiting depthcharge with code 4 at timestamp: 52343763 LZMA decompressing kernel-1 to 0x821a6718 LZMA decompressing kernel-1 to 0x40000000 jumping to kernel [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 [ 0.000000] random: crng init done [ 0.000000] Machine model: Google Spherion (rev0 - 3) [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8') [ 0.000000] printk: bootconsole [mtk8250] enabled [ 0.000000] NUMA: No NUMA configuration found [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff] [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff] [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.2 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: Virtualization Host Extensions [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space. <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: area num 8. <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB) <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode <6>[ 0.000000] GICv3: 608 SPIs implemented <6>[ 0.000000] GICv3: 0 Extended SPIs implemented <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] } <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] } <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns <6>[ 0.009225] Console: colour dummy device 80x25 <6>[ 0.013952] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000) <6>[ 0.024394] pid_max: default: 32768 minimum: 301 <6>[ 0.029264] LSM: Security Framework initializing <6>[ 0.034175] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.041782] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.051019] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.058509] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.064848] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.072321] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.078721] rcu: Hierarchical SRCU implementation. <6>[ 0.083768] rcu: Max phase no-delay instances is 1000. <6>[ 0.090834] EFI services will not be available. <6>[ 0.095821] smp: Bringing up secondary CPUs ... <6>[ 0.100869] Detected VIPT I-cache on CPU1 <6>[ 0.100936] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000 <6>[ 0.100967] CPU1: Booted secondary processor 0x0000000100 [0x412fd050] <6>[ 0.101299] Detected VIPT I-cache on CPU2 <6>[ 0.101346] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000 <6>[ 0.101363] CPU2: Booted secondary processor 0x0000000200 [0x412fd050] <6>[ 0.101619] Detected VIPT I-cache on CPU3 <6>[ 0.101666] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000 <6>[ 0.101680] CPU3: Booted secondary processor 0x0000000300 [0x412fd050] <6>[ 0.101983] CPU features: detected: Spectre-v4 <6>[ 0.101989] CPU features: detected: Spectre-BHB <6>[ 0.101995] Detected PIPT I-cache on CPU4 <6>[ 0.102051] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000 <6>[ 0.102067] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0] <6>[ 0.102358] Detected PIPT I-cache on CPU5 <6>[ 0.102420] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000 <6>[ 0.102436] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0] <6>[ 0.102715] Detected PIPT I-cache on CPU6 <6>[ 0.102775] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000 <6>[ 0.102791] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0] <6>[ 0.103091] Detected PIPT I-cache on CPU7 <6>[ 0.103155] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000 <6>[ 0.103171] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0] <6>[ 0.103219] smp: Brought up 1 node, 8 CPUs <6>[ 0.244631] SMP: Total of 8 processors activated. <6>[ 0.249552] CPU features: detected: 32-bit EL0 Support <6>[ 0.254915] CPU features: detected: Data cache clean to the PoU not required for I/D coherence <6>[ 0.263715] CPU features: detected: Common not Private translations <6>[ 0.270231] CPU features: detected: CRC32 instructions <6>[ 0.275583] CPU features: detected: RCpc load-acquire (LDAPR) <6>[ 0.281580] CPU features: detected: LSE atomic instructions <6>[ 0.287397] CPU features: detected: Privileged Access Never <6>[ 0.293212] CPU features: detected: RAS Extension Support <6>[ 0.298821] CPU features: detected: Speculative Store Bypassing Safe (SSBS) <6>[ 0.306083] CPU: All CPU(s) started at EL2 <6>[ 0.310400] alternatives: applying system-wide alternatives <6>[ 0.320393] devtmpfs: initialized <6>[ 0.328613] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns <6>[ 0.338574] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) <6>[ 0.346492] pinctrl core: initialized pinctrl subsystem <6>[ 0.353146] DMI not present or invalid. <6>[ 0.357546] NET: Registered PF_NETLINK/PF_ROUTE protocol family <6>[ 0.364382] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations <6>[ 0.371831] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations <6>[ 0.379923] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations <6>[ 0.388078] audit: initializing netlink subsys (disabled) <5>[ 0.393774] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1 <6>[ 0.394470] thermal_sys: Registered thermal governor 'step_wise' <6>[ 0.401741] thermal_sys: Registered thermal governor 'power_allocator' <6>[ 0.407997] cpuidle: using governor menu <6>[ 0.418951] NET: Registered PF_QIPCRTR protocol family <6>[ 0.424436] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. <6>[ 0.431538] ASID allocator initialised with 32768 entries <6>[ 0.438089] Serial: AMBA PL011 UART driver <4>[ 0.446822] Trying to register duplicate clock ID: 134 <6>[ 0.508355] KASLR enabled <6>[ 0.516054] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages <6>[ 0.523068] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page <6>[ 0.529558] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages <6>[ 0.536564] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page <6>[ 0.543050] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages <6>[ 0.550053] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page <6>[ 0.556539] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages <6>[ 0.563543] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page <6>[ 0.571052] ACPI: Interpreter disabled. <6>[ 0.577468] iommu: Default domain type: Translated <6>[ 0.582581] iommu: DMA domain TLB invalidation policy: strict mode <5>[ 0.589237] SCSI subsystem initialized <6>[ 0.593401] usbcore: registered new interface driver usbfs <6>[ 0.599131] usbcore: registered new interface driver hub <6>[ 0.604683] usbcore: registered new device driver usb <6>[ 0.610773] pps_core: LinuxPPS API ver. 1 registered <6>[ 0.615966] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <6>[ 0.625310] PTP clock support registered <6>[ 0.629551] EDAC MC: Ver: 3.0.0 <6>[ 0.634701] FPGA manager framework <6>[ 0.638386] Advanced Linux Sound Architecture Driver Initialized. <6>[ 0.645154] vgaarb: loaded <6>[ 0.648308] clocksource: Switched to clocksource arch_sys_counter <5>[ 0.654748] VFS: Disk quotas dquot_6.6.0 <6>[ 0.658931] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) <6>[ 0.666119] pnp: PnP ACPI: disabled <6>[ 0.672756] NET: Registered PF_INET protocol family <6>[ 0.678137] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) <6>[ 0.688150] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) <6>[ 0.696933] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) <6>[ 0.704898] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) <6>[ 0.713302] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) <6>[ 0.721958] TCP: Hash tables configured (established 32768 bind 32768) <6>[ 0.728814] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.735834] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.743354] NET: Registered PF_UNIX/PF_LOCAL protocol family <6>[ 0.749495] RPC: Registered named UNIX socket transport module. <6>[ 0.755647] RPC: Registered udp transport module. <6>[ 0.760579] RPC: Registered tcp transport module. <6>[ 0.765509] RPC: Registered tcp NFSv4.1 backchannel transport module. <6>[ 0.772178] PCI: CLS 0 bytes, default 64 <6>[ 0.776467] Unpacking initramfs... <6>[ 0.780520] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available <6>[ 0.789139] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available <6>[ 0.797910] kvm [1]: IPA Size Limit: 40 bits <6>[ 0.802436] kvm [1]: GICv3: no GICV resource entry <6>[ 0.807456] kvm [1]: disabling GICv2 emulation <6>[ 0.812141] kvm [1]: GIC system register CPU interface enabled <6>[ 0.818292] kvm [1]: vgic interrupt IRQ18 <6>[ 0.822665] kvm [1]: VHE mode initialized successfully <5>[ 0.829151] Initialise system trusted keyrings <6>[ 0.833975] workingset: timestamp_bits=42 max_order=20 bucket_order=0 <6>[ 0.843960] squashfs: version 4.0 (2009/01/31) Phillip Lougher <5>[ 0.850332] NFS: Registering the id_resolver key type <5>[ 0.855634] Key type id_resolver registered <5>[ 0.860046] Key type id_legacy registered <6>[ 0.864332] nfs4filelayout_init: NFSv4 File Layout Driver Registering... <6>[ 0.871254] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... <6>[ 0.878973] 9p: Installing v9fs 9p2000 file system support <5>[ 0.917065] Key type asymmetric registered <5>[ 0.921396] Asymmetric key parser 'x509' registered <6>[ 0.926536] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243) <6>[ 0.934149] io scheduler mq-deadline registered <6>[ 0.938908] io scheduler kyber registered <6>[ 0.955917] EINJ: ACPI disabled. <4>[ 0.981870] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <4>[ 0.992509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <6>[ 1.013364] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled <6>[ 1.021327] printk: console [ttyS0] disabled <6>[ 1.045968] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2 <6>[ 1.055449] printk: console [ttyS0] enabled <6>[ 1.055449] printk: console [ttyS0] enabled <6>[ 1.064347] printk: bootconsole [mtk8250] disabled <6>[ 1.064347] printk: bootconsole [mtk8250] disabled <6>[ 1.075418] SuperH (H)SCI(F) driver initialized <6>[ 1.080704] msm_serial: driver initialized <6>[ 1.089602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000 <6>[ 1.098150] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000 <6>[ 1.106692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000 <6>[ 1.115319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000 <6>[ 1.124026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000 <6>[ 1.132748] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000 <6>[ 1.141291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000 <6>[ 1.150084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000 <6>[ 1.158627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000 <6>[ 1.174128] loop: module loaded <6>[ 1.180022] vgpu11_sshub: Bringing 400000uV into 575000-575000uV <4>[ 1.203262] mtk-pmic-keys: Failed to locate of_node [id: -1] <6>[ 1.210062] megasas: 07.719.03.00-rc1 <6>[ 1.219408] spi-nor spi2.0: w25q64jwm (8192 Kbytes) <6>[ 1.227693] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2 <6>[ 1.244287] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0) <6>[ 1.293682] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2 <6>[ 1.605848] Freeing initrd memory: 18288K <6>[ 1.617494] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz <6>[ 1.628639] tun: Universal TUN/TAP device driver, 1.6 <6>[ 1.634713] thunder_xcv, ver 1.0 <6>[ 1.638220] thunder_bgx, ver 1.0 <6>[ 1.641714] nicpf, ver 1.0 <6>[ 1.645733] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version <6>[ 1.653213] hns3: Copyright (c) 2017 Huawei Corporation. <6>[ 1.658804] hclge is initializing <6>[ 1.662386] e1000: Intel(R) PRO/1000 Network Driver <6>[ 1.667515] e1000: Copyright (c) 1999-2006 Intel Corporation. <6>[ 1.673526] e1000e: Intel(R) PRO/1000 Network Driver <6>[ 1.678741] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. <6>[ 1.684927] igb: Intel(R) Gigabit Ethernet Network Driver <6>[ 1.690576] igb: Copyright (c) 2007-2014 Intel Corporation. <6>[ 1.696416] igbvf: Intel(R) Gigabit Virtual Function Network Driver <6>[ 1.702934] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. <6>[ 1.709394] sky2: driver version 1.30 <6>[ 1.714326] usbcore: registered new device driver r8152-cfgselector <6>[ 1.720861] usbcore: registered new interface driver r8152 <6>[ 1.726678] VFIO - User Level meta-driver version: 0.3 <6>[ 1.734894] usbcore: registered new interface driver usb-storage <6>[ 1.741339] usbcore: registered new device driver onboard-usb-hub <6>[ 1.750487] mt6397-rtc mt6359-rtc: registered as rtc0 <6>[ 1.755948] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:47:56 UTC (1717512476) <6>[ 1.765511] i2c_dev: i2c /dev entries driver <6>[ 1.777254] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0) <4>[ 1.785975] cpu cpu0: supply cpu not found, using dummy regulator <4>[ 1.792396] cpu cpu1: supply cpu not found, using dummy regulator <4>[ 1.798800] cpu cpu2: supply cpu not found, using dummy regulator <4>[ 1.805201] cpu cpu3: supply cpu not found, using dummy regulator <4>[ 1.811615] cpu cpu4: supply cpu not found, using dummy regulator <4>[ 1.818013] cpu cpu5: supply cpu not found, using dummy regulator <4>[ 1.824408] cpu cpu6: supply cpu not found, using dummy regulator <4>[ 1.830803] cpu cpu7: supply cpu not found, using dummy regulator <6>[ 1.851427] cpu cpu0: EM: created perf domain <6>[ 1.856341] cpu cpu4: EM: created perf domain <6>[ 1.861904] sdhci: Secure Digital Host Controller Interface driver <6>[ 1.868338] sdhci: Copyright(c) Pierre Ossman <6>[ 1.873255] Synopsys Designware Multimedia Card Interface Driver <6>[ 1.879851] sdhci-pltfm: SDHCI platform and OF driver helper <6>[ 1.879906] mmc0: CQHCI version 5.10 <6>[ 1.890199] ledtrig-cpu: registered to indicate activity on CPUs <6>[ 1.897195] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000 <6>[ 1.904189] usbcore: registered new interface driver usbhid <6>[ 1.910011] usbhid: USB HID core driver <6>[ 1.914210] spi_master spi0: will run message pump with realtime priority <6>[ 1.951334] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0 <6>[ 1.966439] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1 <6>[ 1.981406] cros-ec-spi spi0.0: Chrome EC device registered <6>[ 1.987442] mmc0: Command Queue Engine enabled <6>[ 1.992193] mmc0: new HS400 Enhanced strobe MMC card at address 0001 <6>[ 1.999406] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0) <6>[ 1.999498] mmcblk0: mmc0:0001 DA4064 58.2 GiB <6>[ 2.009641] NET: Registered PF_PACKET protocol family <6>[ 2.018197] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 <6>[ 2.018886] 9pnet: Installing 9P2000 support <6>[ 2.026071] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB <5>[ 2.029277] Key type dns_resolver registered <6>[ 2.035095] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB <6>[ 2.039420] registered taskstats version 1 <6>[ 2.044872] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0) <5>[ 2.048584] Loading compiled-in X.509 certificates <4>[ 2.076734] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <4>[ 2.087430] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <6>[ 2.107064] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102 <6>[ 2.113803] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.119303] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1 <6>[ 2.127160] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010 <6>[ 2.136587] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000 <6>[ 2.142743] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.148234] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2 <6>[ 2.155909] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed <6>[ 2.163738] hub 1-0:1.0: USB hub found <6>[ 2.167767] hub 1-0:1.0: 1 port detected <6>[ 2.172067] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. <6>[ 2.180876] hub 2-0:1.0: USB hub found <6>[ 2.184903] hub 2-0:1.0: 1 port detected <6>[ 2.192699] mtk-msdc 11f70000.mmc: Got CD GPIO <6>[ 2.201962] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume() <6>[ 2.209987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock() <4>[ 2.217931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW <6>[ 2.227504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend() <6>[ 2.235585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock() <6>[ 2.243605] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register() <6>[ 2.251523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register() <6>[ 2.259342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register() <6>[ 2.267159] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39 <6>[ 2.277570] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.285933] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.294280] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.302618] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.310955] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.319293] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.327631] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.335968] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.344306] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.352644] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.360981] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.369319] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.377657] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.385995] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.394332] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.403064] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0 <6>[ 2.410201] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0 <6>[ 2.416957] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0 <6>[ 2.423678] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0 <6>[ 2.430601] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0 <6>[ 2.437441] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.446571] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.455691] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.464984] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops) <6>[ 2.474451] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops) <6>[ 2.483917] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops) <6>[ 2.493036] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops) <6>[ 2.502503] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.511622] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.520916] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing <6>[ 2.531076] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing <6>[ 2.542939] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0 <6>[ 2.552656] Trying to probe devices needed for running init ... <6>[ 2.588580] usb 1-1: new high-speed USB device number 2 using xhci-mtk <6>[ 2.746365] hub 1-1:1.0: USB hub found <6>[ 2.750747] hub 1-1:1.0: 4 ports detected <6>[ 2.758702] hub 1-1:1.0: USB hub found <6>[ 2.763125] hub 1-1:1.0: 4 ports detected <6>[ 2.868929] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk <6>[ 2.898469] hub 2-1:1.0: USB hub found <6>[ 2.903002] hub 2-1:1.0: 3 ports detected <6>[ 2.911101] hub 2-1:1.0: USB hub found <6>[ 2.915547] hub 2-1:1.0: 3 ports detected <6>[ 3.084607] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk <6>[ 3.220090] hub 1-1.4:1.0: USB hub found <6>[ 3.224668] hub 1-1.4:1.0: 2 ports detected <6>[ 3.231337] hub 1-1.4:1.0: USB hub found <6>[ 3.235820] hub 1-1.4:1.0: 2 ports detected <6>[ 3.300713] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk <6>[ 3.409201] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk <4>[ 3.444817] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2 <4>[ 3.453928] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2) <6>[ 3.498134] r8152 2-1.3:1.0 eth0: v1.12.13 <6>[ 3.532624] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk <6>[ 3.724463] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk <6>[ 5.112249] r8152 2-1.3:1.0 eth0: carrier on <5>[ 5.132360] Sending DHCP requests ., OK <6>[ 5.152744] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16 <6>[ 5.161014] IP-Config: Complete: <6>[ 5.164497] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1 <6>[ 5.175190] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none) <6>[ 5.183796] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath= <6>[ 5.183801] nameserver0=192.168.201.1 <6>[ 5.195872] clk: Disabling unused clocks <6>[ 5.200966] ALSA device list: <6>[ 5.204242] No soundcards found. <6>[ 5.211461] Freeing unused kernel memory: 8512K <6>[ 5.216654] Run /init as init process Loading, please wait... Starting systemd-udevd version 252.22-1~deb12u1 <6>[ 5.451999] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges: <6>[ 5.463862] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000 <6>[ 5.473795] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000 <6>[ 5.498632] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000 <6>[ 5.501456] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered <3>[ 5.502889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.502981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 5.503003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 5.503040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <6>[ 5.522389] mc: Linux media interface: v0.10 <6>[ 5.523670] remoteproc remoteproc0: scp is available <6>[ 5.523757] remoteproc remoteproc0: powering up scp <6>[ 5.523762] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164 <6>[ 5.523793] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0 <4>[ 5.540777] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator <6>[ 5.555005] videodev: Linux video capture interface: v2.00 <4>[ 5.564685] elants_i2c 4-0010: supply vccio not found, using dummy regulator <4>[ 5.573857] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA. <4>[ 5.573857] Fallback method does not support PEC. <6>[ 5.601694] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00 <3>[ 5.620810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <6>[ 5.628648] pci_bus 0000:00: root bus resource [bus 00-ff] <6>[ 5.637306] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003 <6>[ 5.644859] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff] <6>[ 5.644862] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff]) <6>[ 5.644903] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 <6>[ 5.649533] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd <6>[ 5.653612] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2 <3>[ 5.656554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <6>[ 5.661047] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e <6>[ 5.661055] remoteproc remoteproc0: remote processor scp is now up <6>[ 5.661291] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref] <6>[ 5.717105] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3 <6>[ 5.724095] pci 0000:00:00.0: supports D1 D2 <6>[ 5.747613] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected <6>[ 5.755545] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold <6>[ 5.756392] Bluetooth: Core ver 2.22 <6>[ 5.756491] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring <6>[ 5.756631] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 <6>[ 5.756664] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref] <6>[ 5.756682] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref] <6>[ 5.756699] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref] <6>[ 5.756810] pci 0000:01:00.0: supports D1 D2 <6>[ 5.756811] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold <6>[ 5.764611] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered <6>[ 5.772651] NET: Registered PF_BLUETOOTH protocol family <6>[ 5.779065] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 <6>[ 5.785895] Bluetooth: HCI device and connection manager initialized <6>[ 5.785923] Bluetooth: HCI socket layer initialized <6>[ 5.787180] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741) <6>[ 5.788185] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4 <6>[ 5.788284] usbcore: registered new interface driver uvcvideo <6>[ 5.794980] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref] <6>[ 5.803710] Bluetooth: L2CAP socket layer initialized <6>[ 5.812217] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref] <6>[ 5.818654] Bluetooth: SCO socket layer initialized <6>[ 5.826123] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref] <6>[ 5.836242] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0 <6>[ 5.839935] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref] <6>[ 5.881386] usbcore: registered new interface driver btusb <4>[ 5.882356] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2 <3>[ 5.882370] Bluetooth: hci0: Failed to load firmware file (-2) <3>[ 5.882376] Bluetooth: hci0: Failed to set up firmware (-2) <4>[ 5.882383] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported. <6>[ 5.888320] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref] <6>[ 6.060503] pci 0000:00:00.0: PCI bridge to [bus 01] <6>[ 6.065727] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref] <6>[ 6.073853] pcieport 0000:00:00.0: enabling device (0000 -> 0002) <6>[ 6.080800] pcieport 0000:00:00.0: PME: Signaling with IRQ 283 <6>[ 6.087211] pcieport 0000:00:00.0: AER: enabled with IRQ 283 <5>[ 6.100287] cfg80211: Loading compiled-in X.509 certificates for regulatory database <5>[ 6.125559] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' <5>[ 6.132652] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600' <4>[ 6.141059] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 <6>[ 6.149929] cfg80211: failed to load regulatory.db <6>[ 6.194173] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000 <6>[ 6.201676] mt7921e 0000:01:00.0: enabling device (0000 -> 0002) <6>[ 6.228356] mt7921e 0000:01:00.0: ASIC revision: 79610010 <6>[ 6.327982] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a <6>[ 6.327982] Begin: Loading essential drivers ... done. Begin: Running /scripts/init-premount ... done. Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done. Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available Device /sys/class/net/eth0 found done. Begin: Waiting up to 180 secs for any network device to become available ... done. IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP IP-Config: eth0 complete (dhcp from 192.168.201.1): address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0 host : mt8192-asurada-spherion-r0-cbg-4 domain : lava-rack rootserver: 192.168.201.1 rootpath: filename : done. Begin: Running /scripts/nfs-bottom ... done. Begin: Running /scripts/init-bottom ... done. <6>[ 6.598164] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038 <6>[ 7.944504] NET: Registered PF_INET6 protocol family <6>[ 7.952145] Segment Routing with IPv6 <6>[ 7.956099] In-situ OAM (IOAM) with IPv6 <30>[ 8.093856] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified) <30>[ 8.126992] systemd[1]: Detected architecture arm64. Welcome to Debian GNU/Linux 12 (bookworm)! <30>[ 8.166057] systemd[1]: Hostname set to . <30>[ 9.282911] systemd[1]: Queued start job for default target graphical.target. <30>[ 9.329556] systemd[1]: Created slice system-getty.slice - Slice /system/getty. [ OK ] Created slice system-getty.slice - Slice /system/getty. <30>[ 9.358326] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe. [ OK ] Created slice system-modpr…lice - Slice /system/modprobe. <30>[ 9.386317] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty. [ OK ] Created slice system-seria… - Slice /system/serial-getty. <30>[ 9.414045] systemd[1]: Created slice user.slice - User and Session Slice. [ OK ] Created slice user.slice - User and Session Slice. <30>[ 9.440892] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch. [ OK ] Started systemd-ask-passwo…quests to Console Directory Watch. <30>[ 9.468829] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch. [ OK ] Started systemd-ask-passwo… Requests to Wall Directory Watch. <30>[ 9.496750] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc). <30>[ 9.516561] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0... Expecting device dev-ttyS0.device - /dev/ttyS0... <30>[ 9.540632] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes. [ OK ] Reached target cryptsetup.…get - Local Encrypted Volumes. <30>[ 9.564658] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes. [ OK ] Reached target integrityse…Local Integrity Protected Volumes. <30>[ 9.592697] systemd[1]: Reached target paths.target - Path Units. [ OK ] Reached target paths.target - Path Units. <30>[ 9.617104] systemd[1]: Reached target remote-fs.target - Remote File Systems. [ OK ] Reached target remote-fs.target - Remote File Systems. <30>[ 9.640594] systemd[1]: Reached target slices.target - Slice Units. [ OK ] Reached target slices.target - Slice Units. <30>[ 9.665120] systemd[1]: Reached target swap.target - Swaps. [ OK ] Reached target swap.target - Swaps. <30>[ 9.688676] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes. [ OK ] Reached target veritysetup… - Local Verity Protected Volumes. <30>[ 9.717518] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe. [ OK ] Listening on systemd-initc… initctl Compatibility Named Pipe. <30>[ 9.747425] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket. [ OK ] Listening on systemd-journ…socket - Journal Audit Socket. <30>[ 9.774152] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log). [ OK ] Listening on systemd-journ…t - Journal Socket (/dev/log). <30>[ 9.801952] systemd[1]: Listening on systemd-journald.socket - Journal Socket. [ OK ] Listening on systemd-journald.socket - Journal Socket. <30>[ 9.830599] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket. [ OK ] Listening on systemd-netwo… - Network Service Netlink Socket. <30>[ 9.861179] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket. [ OK ] Listening on systemd-udevd….socket - udev Control Socket. <30>[ 9.889106] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket. [ OK ] Listening on systemd-udevd…l.socket - udev Kernel Socket. <30>[ 9.956775] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System... Mounting dev-hugepages.mount - Huge Pages File System... <30>[ 9.985344] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System... Mounting dev-mqueue.mount…POSIX Message Queue File System... <30>[ 10.017342] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System... Mounting sys-kernel-debug.… - Kernel Debug File System... <30>[ 10.045163] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing). <30>[ 10.067024] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes... Starting kmod-static-nodes…ate List of Static Device Nodes... <30>[ 10.098432] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs... Starting modprobe@configfs…m - Load Kernel Module configfs... <30>[ 10.130254] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod... Starting modprobe@dm_mod.s…[0m - Load Kernel Module dm_mod... <30>[ 10.162386] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm... Starting modpr<6>[ 10.172787] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com obe@drm.service - Load Kernel Module drm... <30>[ 10.202430] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore... Starting modprobe@efi_psto…- Load Kernel Module efi_pstore... <30>[ 10.234114] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse... Starting modprobe@fuse.ser…e - Load Kernel Module fuse... <30>[ 10.266266] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop... Startin<6>[ 10.274998] fuse: init (API version 7.37) g modprobe@loop.ser…e - Load Kernel Module loop... <30>[ 10.341448] systemd[1]: Starting systemd-journald.service - Journal Service... Starting systemd-journald.service - Journal Service... <30>[ 10.381720] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules... Starting systemd-modules-l…rvice - Load Kernel Modules... <30>[ 10.411960] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line... Starting systemd-network-g… units from Kernel command line... <30>[ 10.481682] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems... Starting systemd-remount-f…nt Root and Kernel File Systems... <3>[ 10.509668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.512808] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices... Starting systemd-udev-trig…[0m - Coldplug All udev Devices... <3>[ 10.541833] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.558630] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System. [ OK ] Mounted dev-hugepages.mount - Huge Pages File System. <30>[ 10.585097] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System. <3>[ 10.585507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 [ OK ] Mounted dev-mqueue.mount[…- POSIX Message Queue File System. <30>[ 10.621404] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System. <3>[ 10.622594] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 [ OK ] Mounted sys-kernel-debug.m…nt - Kernel Debug File System. <30>[ 10.657628] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes. <3>[ 10.659325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 [ OK ] Finished kmod-static-nodes…reate List of Static Device Nodes. <30>[ 10.693547] systemd[1]: modprobe@configfs.service: Deactivated successfully. <3>[ 10.698130] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.701322] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs. [ OK ] Finished modprobe@configfs…[0m - Load Kernel Module configfs. <3>[ 10.732702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.743042] systemd[1]: modprobe@dm_mod.service: Deactivated successfully. <30>[ 10.750888] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod. [ OK ] Finished modprobe@d<3>[ 10.763554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 m_mod.s…e - Load Kernel Module dm_mod. <30>[ 10.785680] systemd[1]: modprobe@drm.service: Deactivated successfully. <3>[ 10.793051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.793155] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm. [ OK ] Finished modprobe@drm.service - Load Kernel Module drm. <3>[ 10.822297] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.832853] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully. <30>[ 10.841296] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore. [ OK ] Finished [0<3>[ 10.851873] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore. <3>[ 10.881373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <30>[ 10.881890] systemd[1]: modprobe@fuse.service: Deactivated successfully. <30>[ 10.897893] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse. [ OK ] Finished modprobe@fuse.service - Load Kernel Module fuse. <3>[ 10.920951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <3>[ 10.921749] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6 <4>[ 10.938036] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent <30>[ 10.939027] systemd[1]: modprobe@loop.service: Deactivated successfully. <3>[ 10.953675] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6 <30>[ 10.969264] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop. [ OK ] Finished modprobe@loop.service - Load Kernel Module loop. <30>[ 10.997617] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules. [ OK ] Finished systemd-modules-l…service - Load Kernel Modules. <30>[ 11.025016] systemd[1]: Started systemd-journald.service - Journal Service. [ OK ] Started systemd-journald.service - Journal Service. [ OK ] Finished systemd-network-g…rk units from Kernel command line. [ OK ] Finished systemd-remount-f…ount Root and Kernel File Systems. [ OK ] Finished systemd-udev-trig…e - Coldplug All udev Devices. [ OK ] Reached target network-pre…get - Preparation for Network. Mounting sys-fs-fuse-conne… - FUSE Control File System... Mounting sys-kernel-config…ernel Configuration File System... Starting systemd-journal-f…h Journal to Persistent Storage... Starting systemd-random-se…ice - Load/Save Random Seed... <46>[ 11.257151] systemd-journald[298]: Received client request to flush runtime journal. Starting systemd-sysctl.se…ce - Apply Kernel Variables... Starting systemd-sysusers.…rvice - Create System Users... [ OK ] Mounted sys-fs-fuse-connec…nt - FUSE Control File System. [ OK ] Mounted sys-kernel-config.… Kernel Configuration File System. [ OK ] Finished systemd-random-se…rvice - Load/Save Random Seed. [ OK ] Finished systemd-sysctl.service - Apply Kernel Variables. [ OK ] Finished systemd-sysusers.service - Create System Users. [ OK ] Finished systemd-journal-f…ush Journal to Persistent Storage. Starting systemd-tmpfiles-…ate Static Device Nodes in /dev... [ OK ] Finished systemd-tmpfiles-…reate Static Device Nodes in /dev. [ OK ] Reached target local-fs-pr…reparation for Local File Systems. [ OK ] Reached target local-fs.target - Local File Systems. Starting systemd-tmpfiles-… Volatile Files and Directories... Starting systemd-udevd.ser…ger for Device Events and Files... [ OK ] Started systemd-udevd.serv…nager for Device Events and Files. Starting systemd-networkd.…ice - Network Configuration... [ OK ] Found device dev-ttyS0.device - /dev/ttyS0. [ OK ] Finished systemd-tmpfiles-…te Volatile Files and Directories. Starting systemd-timesyncd… - Network Time Synchronization..<6>[ 13.592646] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0 . Starting systemd-update-ut…rd System Boot/Shutdown in UTMP... [ OK ] Created slice system-syste…- Slice /system/systemd-backlight. [ OK ] Reached target bluetooth.target - Bluetooth Support. [ OK ] Listening on systemd-rfkil…l Switch Status /dev/rfkill Watch. Starting systemd-backlight…ess of leds:white:kbd_backlight... [ OK ] Started systemd-networkd.service - Network Configuration. [ OK ] Started systemd-timesyncd.…0m - Network Time Synchronization. [ OK ] Finished systemd-backlight…tness of leds:white:kbd_backlight. [ OK ] Reached target network.target - Network. [ OK ] Reached target time-set.target - System Time Set. Starting systemd-rfkill.se…Load/Save RF Kill Switch Status... [ OK ] Finished systemd-update-ut…cord System Boot/Shutdown in UTMP. [ OK ] Reached target sysinit.target - System Initialization. [ OK ] Started apt-daily.timer - Daily apt download activities. [ OK ] Started apt-daily-upgrade.… apt upgrade and clean activities. [ OK ] Started dpkg-db-backup.tim… Daily dpkg database backup timer. [ OK ] Started e2scrub_all.timer…etadata Check for All Filesystems. [ OK ] Started fstrim.timer - Discard unused blocks once a week. [ OK ] Started systemd-tmpfiles-c… Cleanup of Temporary Directories. [ OK ] Reached target timers.target - Timer Units. [ OK ] Listening on dbus.socket[…- D-Bus System Message Bus Socket. [ OK ] Reached target sockets.target - Socket Units. [ OK ] Reached target basic.target - Basic System. Starting dbus.service - D-Bus System Message Bus... Starting e2scrub_reap.serv…e ext4 Metadata Check Snapshots... Starting systemd-logind.se…ice - User Login Management... Starting systemd-user-sess…vice - Permit User Sessions... [ OK ] Started systemd-rfkill.ser…- Load/Save RF Kill Switch Status. [ OK ] Finished systemd-user-sess…ervice - Permit User Sessions. [ OK ] Started getty@tty1.service - Getty on tty1. [ OK ] Started serial-getty@ttyS0…rvice - Serial Getty on ttyS0. [ OK ] Reached target getty.target - Login Prompts. [ OK ] Started dbus.service - D-Bus System Message Bus. [ OK ] Started systemd-logind.service - User Login Management. [ OK ] Finished e2scrub_reap.serv…ine ext4 Metadata Check Snapshots. [ OK ] Reached target multi-user.target - Multi-User System. [ OK ] Reached target graphical.target - Graphical Interface. Starting systemd-update-ut… Record Runlevel Change in UTMP... [ OK ] Finished systemd-update-ut… - Record Runlevel Change in UTMP. Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0 debian-bookworm-arm64 login: root (automatic login) Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64 The programs included with the Debian GNU/Linux system are free software; the exact distribution terms for each program are described in the individual files in /usr/share/doc/*/copyright. Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent permitted by applicable law. / # / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g' export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167017/extract-nfsrootfs-oz49gv4g' / # export NFS_SERVER_IP='192.168.201.1' export NFS_SERVER_IP='192.168.201.1' / # # # / # export SHELL=/bin/bash export SHELL=/bin/bash / # . /lava-14167017/environment . /lava-14167017/environment / # /lava-14167017/bin/lava-test-runner /lava-14167017/0 /lava-14167017/bin/lava-test-runner /lava-14167017/0 + export TESTRUN_ID=0_timesync-off + TESTRUN_ID=0_timesync-off + cd /lava-14167017/0/tests/0_timesync-off ++ cat uuid + UUID=14167017_1.6.2.3.1 + set +x + systemctl stop systemd-timesyncd + set +x + export TESTRUN_ID=1_kselftest-arm64 + TESTRUN_ID=1_kselftest-arm64 + cd /lava-14167017/0/tests/1_kselftest-arm64 ++ cat uuid + UUID=14167017_1.6.2.3.5 + set +x + cd ./automated/linux/kselftest/ + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 INFO: install_deps skipped --2024-06-04 14:48:12-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected. HTTP request sent, awaiting response... 200 OK Length: 1647736 (1.6M) [application/octet-stream] Saving to: 'kselftest_armhf.tar.gz' kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 3%[ ] 49.22K 190KB/s kselftest_armhf.tar 13%[=> ] 218.91K 421KB/s kselftest_armhf.tar 51%[=========> ] 825.54K 960KB/s kselftest_armhf.tar 100%[===================>] 1.57M 1.49MB/s in 1.1s 2024-06-04 14:48:14 (1.49 MB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736] skiplist: ======================================== ======================================== arm64:tags_test arm64:run_tags_test.sh arm64:fake_sigreturn_bad_magic arm64:fake_sigreturn_bad_size arm64:fake_sigreturn_bad_size_for_magic0 arm64:fake_sigreturn_duplicated_fpsimd arm64:fake_sigreturn_misaligned_sp arm64:fake_sigreturn_missing_fpsimd arm64:fake_sigreturn_sme_change_vl arm64:fake_sigreturn_sve_change_vl arm64:mangle_pstate_invalid_compat_toggle arm64:mangle_pstate_invalid_daif_bits arm64:mangle_pstate_invalid_mode_el1h arm64:mangle_pstate_invalid_mode_el1t arm64:mangle_pstate_invalid_mode_el2h arm64:mangle_pstate_invalid_mode_el2t arm64:mangle_pstate_invalid_mode_el3h arm64:mangle_pstate_invalid_mode_el3t arm64:sme_trap_no_sm arm64:sme_trap_non_streaming arm64:sme_trap_za arm64:sme_vl arm64:ssve_regs arm64:sve_regs arm64:sve_vl arm64:za_no_regs arm64:za_regs arm64:pac arm64:fp-stress arm64:sve-ptrace arm64:sve-probe-vls arm64:vec-syscfg arm64:za-fork arm64:za-ptrace arm64:check_buffer_fill arm64:check_child_memory arm64:check_gcr_el1_cswitch arm64:check_ksm_options arm64:check_mmap_options arm64:check_prctl arm64:check_tags_inclusion arm64:check_user_mem arm64:btitest arm64:nobtitest arm64:hwcap arm64:ptrace arm64:syscall-abi arm64:tpidr2 ============== Tests to run =============== arm64:tags_test arm64:run_tags_test.sh arm64:fake_sigreturn_bad_magic arm64:fake_sigreturn_bad_size arm64:fake_sigreturn_bad_size_for_magic0 arm64:fake_sigreturn_duplicated_fpsimd arm64:fake_sigreturn_misaligned_sp arm64:fake_sigreturn_missing_fpsimd arm64:fake_sigreturn_sme_change_vl arm64:fake_sigreturn_sve_change_vl arm64:mangle_pstate_invalid_compat_toggle arm64:mangle_pstate_invalid_daif_bits arm64:mangle_pstate_invalid_mode_el1h arm64:mangle_pstate_invalid_mode_el1t arm64:mangle_pstate_invalid_mode_el2h arm64:mangle_pstate_invalid_mode_el2t arm64:mangle_pstate_invalid_mode_el3h arm64:mangle_pstate_invalid_mode_el3t arm64:sme_trap_no_sm arm64:sme_trap_non_streaming arm64:sme_trap_za arm64:sme_vl arm64:ssve_regs arm64:sve_regs arm64:sve_vl arm64:za_no_regs arm64:za_regs arm64:pac arm64:fp-stress arm64:sve-ptrace arm64:sve-probe-vls arm64:vec-syscfg arm64:za-fork arm64:za-ptrace arm64:check_buffer_fill arm64:check_child_memory arm64:check_gcr_el1_cswitch arm64:check_ksm_options arm64:check_mmap_options arm64:check_prctl arm64:check_tags_inclusion arm64:check_user_mem arm64:btitest arm64:nobtitest arm64:hwcap arm64:ptrace arm64:syscall-abi arm64:tpidr2 ===========End Tests to run =============== shardfile-arm64 pass <12>[ 24.545963] kselftest: Running tests in arm64 TAP version 13 1..48 # selftests: arm64: tags_test ok 1 selftests: arm64: tags_test # selftests: arm64: run_tags_test.sh # -------------------- # running tags test # -------------------- # [PASS] ok 2 selftests: arm64: run_tags_test.sh # selftests: arm64: fake_sigreturn_bad_magic # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler # Handled SIG_COPYCTX # Available space:3568 # Using badly built context - ERR: BAD MAGIC ! # SIG_OK -- SP:0xFFFFE96144A0 si_addr@:0xffffe96144a0 si_code:2 token@:0xffffe9613240 offset:-4704 # ==>> completed. PASS(1) # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE9613240 ok 3 selftests: arm64: fake_sigreturn_bad_magic # selftests: arm64: fake_sigreturn_bad_size # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler # Handled SIG_COPYCTX # Available space:3568 # uc context validated. # Using badly built context - ERR: Bad size for esr_context # SIG_OK -- SP:0xFFFFC04E3840 si_addr@:0xffffc04e3840 si_code:2 token@:0xffffc04e25e0 offset:-4704 # ==>> completed. PASS(1) # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC04E25E0 ok 4 selftests: arm64: fake_sigreturn_bad_size # selftests: arm64: fake_sigreturn_bad_size_for_magic0 # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler # Handled SIG_COPYCTX # Available space:3568 # Using badly built context - ERR: Bad size for terminator # SIG_OK -- SP:0xFFFFED768300 si_addr@:0xffffed768300 si_code:2 token@:0xffffed7670a0 offset:-4704 # ==>> completed. PASS(1) # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFED7670A0 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0 # selftests: arm64: fake_sigreturn_duplicated_fpsimd # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler # Handled SIG_COPYCTX # Available space:3568 # Using badly built context - ERR: Multiple FPSIMD_MAGIC # SIG_OK -- SP:0xFFFFE0D7F2B0 si_addr@:0xffffe0d7f2b0 si_code:2 token@:0xffffe0d7e050 offset:-4704 # ==>> completed. PASS(1) # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0D7E050 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd # selftests: arm64: fake_sigreturn_misaligned_sp # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler # Handled SIG_COPYCTX # SIG_OK -- SP:0xFFFFECC5B393 si_addr@:0xffffecc5b393 si_code:2 token@:0xffffecc5b393 offset:0 # ==>> completed. PASS(1) # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFECC5B393 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp # selftests: arm64: fake_sigreturn_missing_fpsimd # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler # Handled SIG_COPYCTX # Mangling template header. Spare space:4096 # Using badly built context - ERR: Missing FPSIMD # SIG_OK -- SP:0xFFFFF7E79A10 si_addr@:0xfffff7e79a10 si_code:2 token@:0xfffff7e787b0 offset:-4704 # ==>> completed. PASS(1) # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF7E787B0 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd # selftests: arm64: fake_sigreturn_sme_change_vl # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP # selftests: arm64: fake_sigreturn_sve_change_vl # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP # selftests: arm64: mangle_pstate_invalid_compat_toggle # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFEE3FF050 si_addr@:0xffffee3ff050 si_code:2 token@:(nil) offset:-281474678911056 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle # selftests: arm64: mangle_pstate_invalid_daif_bits # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFD7096AA0 si_addr@:0xffffd7096aa0 si_code:2 token@:(nil) offset:-281474289461920 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits # selftests: arm64: mangle_pstate_invalid_mode_el1h # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFD6C2F4F0 si_addr@:0xffffd6c2f4f0 si_code:2 token@:(nil) offset:-281474284844272 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h # selftests: arm64: mangle_pstate_invalid_mode_el1t # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFEBC5C240 si_addr@:0xffffebc5c240 si_code:2 token@:(nil) offset:-281474637349440 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t # selftests: arm64: mangle_pstate_invalid_mode_el2h # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFC53B7250 si_addr@:0xffffc53b7250 si_code:2 token@:(nil) offset:-281473990750800 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h # selftests: arm64: mangle_pstate_invalid_mode_el2t # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFCCA494C0 si_addr@:0xffffcca494c0 si_code:2 token@:(nil) offset:-281474115081408 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t # selftests: arm64: mangle_pstate_invalid_mode_el3h # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFD2668290 si_addr@:0xffffd2668290 si_code:2 token@:(nil) offset:-281474211676816 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h # selftests: arm64: mangle_pstate_invalid_mode_el3t # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # uc context validated. # Handled SIG_TRIG # SIG_OK -- SP:0xFFFFD27FCAA0 si_addr@:0xffffd27fcaa0 si_code:2 token@:(nil) offset:-281474213333664 # ==>> completed. PASS(1) # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t # selftests: arm64: sme_trap_no_sm # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it ok 19 selftests: arm64: sme_trap_no_sm # SKIP # selftests: arm64: sme_trap_non_streaming # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode ok 20 selftests: arm64: sme_trap_non_streaming # SKIP # selftests: arm64: sme_trap_za # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # Testcase initialized. # SIG_OK -- SP:0xFFFFC253D750 si_addr@:0xaaaab8bf2510 si_code:1 token@:(nil) offset:-187650220696848 # ==>> completed. PASS(1) # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling ok 21 selftests: arm64: sme_trap_za # selftests: arm64: sme_vl # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # SME VL :: Check that we get the right SME VL reported ok 22 selftests: arm64: sme_vl # SKIP # selftests: arm64: ssve_regs # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported ok 23 selftests: arm64: ssve_regs # SKIP # selftests: arm64: sve_regs # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # SVE registers :: Check that we get the right SVE registers reported ok 24 selftests: arm64: sve_regs # SKIP # selftests: arm64: sve_vl # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # SVE VL :: Check that we get the right SVE VL reported ok 25 selftests: arm64: sve_vl # SKIP # selftests: arm64: za_no_regs # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # ZA registers - ZA disabled :: Check ZA context with ZA disabled ok 26 selftests: arm64: za_no_regs # SKIP # selftests: arm64: za_regs # Registered handlers for all signals. # Detected MINSTKSIGSZ:4720 # ==>> completed. SKIP. # # ZA register :: Check that we get the right ZA registers reported ok 27 selftests: arm64: za_regs # SKIP # selftests: arm64: pac # TAP version 13 # 1..7 # # Starting 7 tests from 1 test cases. # # RUN global.corrupt_pac ... # # SKIP PAUTH not enabled # # OK global.corrupt_pac # ok 1 # SKIP PAUTH not enabled # # RUN global.pac_instructions_not_nop ... # # SKIP PAUTH not enabled # # OK global.pac_instructions_not_nop # ok 2 # SKIP PAUTH not enabled # # RUN global.pac_instructions_not_nop_generic ... # # SKIP Generic PAUTH not enabled # # OK global.pac_instructions_not_nop_generic # ok 3 # SKIP Generic PAUTH not enabled # # RUN global.single_thread_different_keys ... # # SKIP PAUTH not enabled # # OK global.single_thread_different_keys # ok 4 # SKIP PAUTH not enabled # # RUN global.exec_changed_keys ... # # SKIP PAUTH not enabled # # OK global.exec_changed_keys # ok 5 # SKIP PAUTH not enabled # # RUN global.context_switch_keep_keys ... # # SKIP PAUTH not enabled # # OK global.context_switch_keep_keys # ok 6 # SKIP PAUTH not enabled # # RUN global.context_switch_keep_keys_generic ... # # SKIP Generic PAUTH not enabled # # OK global.context_switch_keep_keys_generic # ok 7 # SKIP Generic PAUTH not enabled # # PASSED: 7 / 7 tests passed. # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0 ok 28 selftests: arm64: pac # selftests: arm64: fp-stress <6>[ 35.924400] vpu: disabling <6>[ 35.927453] vproc2: disabling <6>[ 35.931018] vproc1: disabling <6>[ 35.934299] vaud18: disabling <6>[ 35.937732] vsram_others: disabling <6>[ 35.941625] va09: disabling <6>[ 35.944742] vsram_md: disabling <6>[ 35.948241] Vgpu: disabling # TAP version 13 # 1..16 # # 8 CPUs, 0 SVE VLs, 0 SME VLs # # Will run for 10s # # Started FPSIMD-0-0 # # Started FPSIMD-0-1 # # Started FPSIMD-1-0 # # Started FPSIMD-1-1 # # Started FPSIMD-2-0 # # Started FPSIMD-2-1 # # Started FPSIMD-3-0 # # Started FPSIMD-3-1 # # Started FPSIMD-4-0 # # Started FPSIMD-4-1 # # Started FPSIMD-5-0 # # Started FPSIMD-5-1 # # Started FPSIMD-6-0 # # Started FPSIMD-6-1 # # Started FPSIMD-7-0 # # Started FPSIMD-7-1 # # FPSIMD-0-0: Vector length: 128 bits # # FPSIMD-0-0: PID: 1155 # # FPSIMD-0-1: Vector length: 128 bits # # FPSIMD-0-1: PID: 1156 # # FPSIMD-2-1: Vector length: 128 bits # # FPSIMD-2-1: PID: 1160 # # FPSIMD-1-0: Vector length: 128 bits # # FPSIMD-1-0: PID: 1157 # # FPSIMD-1-1: Vector length: 128 bits # # FPSIMD-1-1: PID: 1158 # # FPSIMD-2-0: Vector length: 128 bits # # FPSIMD-2-0: PID: 1159 # # FPSIMD-5-0: Vector length: 128 bits # # FPSIMD-5-0: PID: 1165 # # FPSIMD-7-1: Vector length: 128 bits # # FPSIMD-7-1: PID: 1170 # # FPSIMD-6-1: Vector length: 128 bits # # FPSIMD-6-1: PID: 1168 # # FPSIMD-6-0: Vector length: 128 bits # # FPSIMD-6-0: PID: 1167 # # FPSIMD-4-1: Vector length: 128 bits # # FPSIMD-4-1: PID: 1164 # # FPSIMD-3-0: Vector length: 128 bits # # FPSIMD-3-0: PID: 1161 # # FPSIMD-7-0: Vector length: 128 bits # # FPSIMD-7-0: PID: 1169 # # FPSIMD-3-1: Vector length: 128 bits # # FPSIMD-3-1: PID: 1162 # # FPSIMD-5-1: Vector length: 128 bits # # FPSIMD-5-1: PID: 1166 # # FPSIMD-4-0: Vector length: 128 bits # # FPSIMD-4-0: PID: 1163 # # Finishing up... # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=986033, signals=10 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1047647, signals=10 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=2128684, signals=10 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=989823, signals=10 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2180869, signals=10 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=2127926, signals=10 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=2186374, signals=10 # ok 1 FPSIMD-0-0 # ok 2 FPSIMD-0-1 # ok 3 FPSIMD-1-0 # ok 4 FPSIMD-1-1 # ok 5 FPSIMD-2-0 # ok 6 FPSIMD-2-1 # ok 7 FPSIMD-3-0 # ok 8 FPSIMD-3-1 # ok 9 FPSIMD-4-0 # ok 10 FPSIMD-4-1 # ok 11 FPSIMD-5-0 # ok 12 FPSIMD-5-1 # ok 13 FPSIMD-6-0 # ok 14 FPSIMD-6-1 # ok 15 FPSIMD-7-0 # ok 16 FPSIMD-7-1 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1117721, signals=9 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1048005, signals=10 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=978442, signals=10 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=988338, signals=10 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=986425, signals=9 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1052952, signals=10 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=985127, signals=10 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=976124, signals=10 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1160768, signals=9 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0 ok 29 selftests: arm64: fp-stress # selftests: arm64: sve-ptrace # TAP version 13 # 1..4104 # ok 2 # SKIP SVE not available # # Planned tests != run tests (4104 != 1) # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0 ok 30 selftests: arm64: sve-ptrace # SKIP # selftests: arm64: sve-probe-vls # TAP version 13 # 1..2 # ok 2 # SKIP SVE not available # # Planned tests != run tests (2 != 1) # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0 ok 31 selftests: arm64: sve-probe-vls # SKIP # selftests: arm64: vec-syscfg # TAP version 13 # 1..20 # ok 1 # SKIP SVE not supported # ok 2 # SKIP SVE not supported # ok 3 # SKIP SVE not supported # ok 4 # SKIP SVE not supported # ok 5 # SKIP SVE not supported # ok 6 # SKIP SVE not supported # ok 7 # SKIP SVE not supported # ok 8 # SKIP SVE not supported # ok 9 # SKIP SVE not supported # ok 10 # SKIP SVE not supported # ok 11 # SKIP SME not supported # ok 12 # SKIP SME not supported # ok 13 # SKIP SME not supported # ok 14 # SKIP SME not supported # ok 15 # SKIP SME not supported # ok 16 # SKIP SME not supported # ok 17 # SKIP SME not supported # ok 18 # SKIP SME not supported # ok 19 # SKIP SME not supported # ok 20 # SKIP SME not supported # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0 ok 32 selftests: arm64: vec-syscfg # selftests: arm64: za-fork # TAP version 13 # 1..1 # # PID: 1247 # # SME support not present # ok 0 skipped # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0 ok 33 selftests: arm64: za-fork # selftests: arm64: za-ptrace # TAP version 13 # 1..1 # ok 2 # SKIP SME not available # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0 ok 34 selftests: arm64: za-ptrace # SKIP # selftests: arm64: check_buffer_fill # # SKIP: MTE features unavailable ok 35 selftests: arm64: check_buffer_fill # SKIP # selftests: arm64: check_child_memory # # SKIP: MTE features unavailable ok 36 selftests: arm64: check_child_memory # SKIP # selftests: arm64: check_gcr_el1_cswitch # # SKIP: MTE features unavailable ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP # selftests: arm64: check_ksm_options # # SKIP: MTE features unavailable ok 38 selftests: arm64: check_ksm_options # SKIP # selftests: arm64: check_mmap_options # # SKIP: MTE features unavailable ok 39 selftests: arm64: check_mmap_options # SKIP # selftests: arm64: check_prctl # TAP version 13 # 1..5 # ok 1 check_basic_read # ok 2 NONE # ok 3 # SKIP SYNC # ok 4 # SKIP ASYNC # ok 5 # SKIP SYNC+ASYNC # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0 ok 40 selftests: arm64: check_prctl # selftests: arm64: check_tags_inclusion # # SKIP: MTE features unavailable ok 41 selftests: arm64: check_tags_inclusion # SKIP # selftests: arm64: check_user_mem # # SKIP: MTE features unavailable ok 42 selftests: arm64: check_user_mem # SKIP # selftests: arm64: btitest # TAP version 13 # 1..18 # # HWCAP_PACA not present # # HWCAP2_BTI not present # # Test binary built for BTI # ok 1 nohint_func/call_using_br_x0 # SKIP # ok 1 nohint_func/call_using_br_x16 # SKIP # ok 1 nohint_func/call_using_blr # SKIP # ok 1 bti_none_func/call_using_br_x0 # SKIP # ok 1 bti_none_func/call_using_br_x16 # SKIP # ok 1 bti_none_func/call_using_blr # SKIP # ok 1 bti_c_func/call_using_br_x0 # SKIP # ok 1 bti_c_func/call_using_br_x16 # SKIP # ok 1 bti_c_func/call_using_blr # SKIP # ok 1 bti_j_func/call_using_br_x0 # SKIP # ok 1 bti_j_func/call_using_br_x16 # SKIP # ok 1 bti_j_func/call_using_blr # SKIP # ok 1 bti_jc_func/call_using_br_x0 # SKIP # ok 1 bti_jc_func/call_using_br_x16 # SKIP # ok 1 bti_jc_func/call_using_blr # SKIP # ok 1 paciasp_func/call_using_br_x0 # SKIP # ok 1 paciasp_func/call_using_br_x16 # SKIP # ok 1 paciasp_func/call_using_blr # SKIP # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0 # # WARNING - EXPECTED TEST COUNT WRONG ok 43 selftests: arm64: btitest # selftests: arm64: nobtitest # TAP version 13 # 1..18 # # HWCAP_PACA not present # # HWCAP2_BTI not present # # Test binary not built for BTI # ok 1 nohint_func/call_using_br_x0 # SKIP # ok 1 nohint_func/call_using_br_x16 # SKIP # ok 1 nohint_func/call_using_blr # SKIP # ok 1 bti_none_func/call_using_br_x0 # SKIP # ok 1 bti_none_func/call_using_br_x16 # SKIP # ok 1 bti_none_func/call_using_blr # SKIP # ok 1 bti_c_func/call_using_br_x0 # SKIP # ok 1 bti_c_func/call_using_br_x16 # SKIP # ok 1 bti_c_func/call_using_blr # SKIP # ok 1 bti_j_func/call_using_br_x0 # SKIP # ok 1 bti_j_func/call_using_br_x16 # SKIP # ok 1 bti_j_func/call_using_blr # SKIP # ok 1 bti_jc_func/call_using_br_x0 # SKIP # ok 1 bti_jc_func/call_using_br_x16 # SKIP # ok 1 bti_jc_func/call_using_blr # SKIP # ok 1 paciasp_func/call_using_br_x0 # SKIP # ok 1 paciasp_func/call_using_br_x16 # SKIP # ok 1 paciasp_func/call_using_blr # SKIP # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0 # # WARNING - EXPECTED TEST COUNT WRONG ok 44 selftests: arm64: nobtitest # selftests: arm64: hwcap # TAP version 13 # 1..28 # ok 1 cpuinfo_match_RNG # # SIGILL reported for RNG # ok 2 # SKIP sigill_RNG # ok 3 cpuinfo_match_SME # ok 4 sigill_SME # ok 5 cpuinfo_match_SVE # ok 6 sigill_SVE # ok 7 cpuinfo_match_SVE 2 # # SIGILL reported for SVE 2 # ok 8 # SKIP sigill_SVE 2 # ok 9 cpuinfo_match_SVE AES # # SIGILL reported for SVE AES # ok 10 # SKIP sigill_SVE AES # ok 11 cpuinfo_match_SVE2 PMULL # # SIGILL reported for SVE2 PMULL # ok 12 # SKIP sigill_SVE2 PMULL # ok 13 cpuinfo_match_SVE2 BITPERM # # SIGILL reported for SVE2 BITPERM # ok 14 # SKIP sigill_SVE2 BITPERM # ok 15 cpuinfo_match_SVE2 SHA3 # # SIGILL reported for SVE2 SHA3 # ok 16 # SKIP sigill_SVE2 SHA3 # ok 17 cpuinfo_match_SVE2 SM4 # # SIGILL reported for SVE2 SM4 # ok 18 # SKIP sigill_SVE2 SM4 # ok 19 cpuinfo_match_SVE2 I8MM # # SIGILL reported for SVE2 I8MM # ok 20 # SKIP sigill_SVE2 I8MM # ok 21 cpuinfo_match_SVE2 F32MM # # SIGILL reported for SVE2 F32MM # ok 22 # SKIP sigill_SVE2 F32MM # ok 23 cpuinfo_match_SVE2 F64MM # # SIGILL reported for SVE2 F64MM # ok 24 # SKIP sigill_SVE2 F64MM # ok 25 cpuinfo_match_SVE2 BF16 # # SIGILL reported for SVE2 BF16 # ok 26 # SKIP sigill_SVE2 BF16 # ok 27 cpuinfo_match_SVE2 EBF16 # ok 28 # SKIP sigill_SVE2 EBF16 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0 ok 45 selftests: arm64: hwcap # selftests: arm64: ptrace # TAP version 13 # 1..7 # # Parent is 1489, child is 1490 # ok 1 read_tpidr_one # ok 2 write_tpidr_one # ok 3 verify_tpidr_one # ok 4 count_tpidrs # ok 5 tpidr2_write # ok 6 tpidr2_read # ok 7 write_tpidr_only # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0 ok 46 selftests: arm64: ptrace # selftests: arm64: syscall-abi # TAP version 13 # 1..2 # ok 1 getpid() FPSIMD # ok 2 sched_yield() FPSIMD # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0 ok 47 selftests: arm64: syscall-abi # selftests: arm64: tpidr2 # TAP version 13 # 1..5 # # PID: 1526 # # SME support not present # ok 0 skipped, TPIDR2 not supported # ok 1 skipped, TPIDR2 not supported # ok 2 skipped, TPIDR2 not supported # ok 3 skipped, TPIDR2 not supported # ok 4 skipped, TPIDR2 not supported # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0 ok 48 selftests: arm64: tpidr2 arm64_tags_test pass arm64_run_tags_test_sh pass arm64_fake_sigreturn_bad_magic pass arm64_fake_sigreturn_bad_size pass arm64_fake_sigreturn_bad_size_for_magic0 pass arm64_fake_sigreturn_duplicated_fpsimd pass arm64_fake_sigreturn_misaligned_sp pass arm64_fake_sigreturn_missing_fpsimd pass arm64_fake_sigreturn_sme_change_vl skip arm64_fake_sigreturn_sve_change_vl skip arm64_mangle_pstate_invalid_compat_toggle pass arm64_mangle_pstate_invalid_daif_bits pass arm64_mangle_pstate_invalid_mode_el1h pass arm64_mangle_pstate_invalid_mode_el1t pass arm64_mangle_pstate_invalid_mode_el2h pass arm64_mangle_pstate_invalid_mode_el2t pass arm64_mangle_pstate_invalid_mode_el3h pass arm64_mangle_pstate_invalid_mode_el3t pass arm64_sme_trap_no_sm skip arm64_sme_trap_non_streaming skip arm64_sme_trap_za pass arm64_sme_vl skip arm64_ssve_regs skip arm64_sve_regs skip arm64_sve_vl skip arm64_za_no_regs skip arm64_za_regs skip arm64_pac_PAUTH_not_enabled skip arm64_pac_PAUTH_not_enabled_dup2 skip arm64_pac_Generic_PAUTH_not_enabled skip arm64_pac_PAUTH_not_enabled_dup3 skip arm64_pac_PAUTH_not_enabled_dup4 skip arm64_pac_PAUTH_not_enabled_dup5 skip arm64_pac_Generic_PAUTH_not_enabled_dup2 skip arm64_pac pass arm64_fp-stress_FPSIMD-0-0 pass arm64_fp-stress_FPSIMD-0-1 pass arm64_fp-stress_FPSIMD-1-0 pass arm64_fp-stress_FPSIMD-1-1 pass arm64_fp-stress_FPSIMD-2-0 pass arm64_fp-stress_FPSIMD-2-1 pass arm64_fp-stress_FPSIMD-3-0 pass arm64_fp-stress_FPSIMD-3-1 pass arm64_fp-stress_FPSIMD-4-0 pass arm64_fp-stress_FPSIMD-4-1 pass arm64_fp-stress_FPSIMD-5-0 pass arm64_fp-stress_FPSIMD-5-1 pass arm64_fp-stress_FPSIMD-6-0 pass arm64_fp-stress_FPSIMD-6-1 pass arm64_fp-stress_FPSIMD-7-0 pass arm64_fp-stress_FPSIMD-7-1 pass arm64_fp-stress pass arm64_sve-ptrace_SVE_not_available skip arm64_sve-ptrace skip arm64_sve-probe-vls_SVE_not_available skip arm64_sve-probe-vls skip arm64_vec-syscfg_SVE_not_supported skip arm64_vec-syscfg_SVE_not_supported_dup2 skip arm64_vec-syscfg_SVE_not_supported_dup3 skip arm64_vec-syscfg_SVE_not_supported_dup4 skip arm64_vec-syscfg_SVE_not_supported_dup5 skip arm64_vec-syscfg_SVE_not_supported_dup6 skip arm64_vec-syscfg_SVE_not_supported_dup7 skip arm64_vec-syscfg_SVE_not_supported_dup8 skip arm64_vec-syscfg_SVE_not_supported_dup9 skip arm64_vec-syscfg_SVE_not_supported_dup10 skip arm64_vec-syscfg_SME_not_supported skip arm64_vec-syscfg_SME_not_supported_dup2 skip arm64_vec-syscfg_SME_not_supported_dup3 skip arm64_vec-syscfg_SME_not_supported_dup4 skip arm64_vec-syscfg_SME_not_supported_dup5 skip arm64_vec-syscfg_SME_not_supported_dup6 skip arm64_vec-syscfg_SME_not_supported_dup7 skip arm64_vec-syscfg_SME_not_supported_dup8 skip arm64_vec-syscfg_SME_not_supported_dup9 skip arm64_vec-syscfg_SME_not_supported_dup10 skip arm64_vec-syscfg pass arm64_za-fork_skipped pass arm64_za-fork pass arm64_za-ptrace_SME_not_available skip arm64_za-ptrace skip arm64_check_buffer_fill skip arm64_check_child_memory skip arm64_check_gcr_el1_cswitch skip arm64_check_ksm_options skip arm64_check_mmap_options skip arm64_check_prctl_check_basic_read pass arm64_check_prctl_NONE pass arm64_check_prctl_SYNC skip arm64_check_prctl_ASYNC skip arm64_check_prctl_SYNC_ASYNC skip arm64_check_prctl pass arm64_check_tags_inclusion skip arm64_check_user_mem skip arm64_btitest_nohint_func_call_using_br_x0 skip arm64_btitest_nohint_func_call_using_br_x16 skip arm64_btitest_nohint_func_call_using_blr skip arm64_btitest_bti_none_func_call_using_br_x0 skip arm64_btitest_bti_none_func_call_using_br_x16 skip arm64_btitest_bti_none_func_call_using_blr skip arm64_btitest_bti_c_func_call_using_br_x0 skip arm64_btitest_bti_c_func_call_using_br_x16 skip arm64_btitest_bti_c_func_call_using_blr skip arm64_btitest_bti_j_func_call_using_br_x0 skip arm64_btitest_bti_j_func_call_using_br_x16 skip arm64_btitest_bti_j_func_call_using_blr skip arm64_btitest_bti_jc_func_call_using_br_x0 skip arm64_btitest_bti_jc_func_call_using_br_x16 skip arm64_btitest_bti_jc_func_call_using_blr skip arm64_btitest_paciasp_func_call_using_br_x0 skip arm64_btitest_paciasp_func_call_using_br_x16 skip arm64_btitest_paciasp_func_call_using_blr skip arm64_btitest pass arm64_nobtitest_nohint_func_call_using_br_x0 skip arm64_nobtitest_nohint_func_call_using_br_x16 skip arm64_nobtitest_nohint_func_call_using_blr skip arm64_nobtitest_bti_none_func_call_using_br_x0 skip arm64_nobtitest_bti_none_func_call_using_br_x16 skip arm64_nobtitest_bti_none_func_call_using_blr skip arm64_nobtitest_bti_c_func_call_using_br_x0 skip arm64_nobtitest_bti_c_func_call_using_br_x16 skip arm64_nobtitest_bti_c_func_call_using_blr skip arm64_nobtitest_bti_j_func_call_using_br_x0 skip arm64_nobtitest_bti_j_func_call_using_br_x16 skip arm64_nobtitest_bti_j_func_call_using_blr skip arm64_nobtitest_bti_jc_func_call_using_br_x0 skip arm64_nobtitest_bti_jc_func_call_using_br_x16 skip arm64_nobtitest_bti_jc_func_call_using_blr skip arm64_nobtitest_paciasp_func_call_using_br_x0 skip arm64_nobtitest_paciasp_func_call_using_br_x16 skip arm64_nobtitest_paciasp_func_call_using_blr skip arm64_nobtitest pass arm64_hwcap_cpuinfo_match_RNG pass arm64_hwcap_sigill_RNG skip arm64_hwcap_cpuinfo_match_SME pass arm64_hwcap_sigill_SME pass arm64_hwcap_cpuinfo_match_SVE pass arm64_hwcap_sigill_SVE pass arm64_hwcap_cpuinfo_match_SVE_2 pass arm64_hwcap_sigill_SVE_2 skip arm64_hwcap_cpuinfo_match_SVE_AES pass arm64_hwcap_sigill_SVE_AES skip arm64_hwcap_cpuinfo_match_SVE2_PMULL pass arm64_hwcap_sigill_SVE2_PMULL skip arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass arm64_hwcap_sigill_SVE2_BITPERM skip arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass arm64_hwcap_sigill_SVE2_SHA3 skip arm64_hwcap_cpuinfo_match_SVE2_SM4 pass arm64_hwcap_sigill_SVE2_SM4 skip arm64_hwcap_cpuinfo_match_SVE2_I8MM pass arm64_hwcap_sigill_SVE2_I8MM skip arm64_hwcap_cpuinfo_match_SVE2_F32MM pass arm64_hwcap_sigill_SVE2_F32MM skip arm64_hwcap_cpuinfo_match_SVE2_F64MM pass arm64_hwcap_sigill_SVE2_F64MM skip arm64_hwcap_cpuinfo_match_SVE2_BF16 pass arm64_hwcap_sigill_SVE2_BF16 skip arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass arm64_hwcap_sigill_SVE2_EBF16 skip arm64_hwcap pass arm64_ptrace_read_tpidr_one pass arm64_ptrace_write_tpidr_one pass arm64_ptrace_verify_tpidr_one pass arm64_ptrace_count_tpidrs pass arm64_ptrace_tpidr2_write pass arm64_ptrace_tpidr2_read pass arm64_ptrace_write_tpidr_only pass arm64_ptrace pass arm64_syscall-abi_getpid_FPSIMD pass arm64_syscall-abi_sched_yield_FPSIMD pass arm64_syscall-abi pass arm64_tpidr2_skipped_TPIDR2_not_supported pass arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass arm64_tpidr2 pass + ../../utils/send-to-lava.sh ./output/result.txt + set +x / #