Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 87
1 13:39:43.608559 lava-dispatcher, installed at version: 2024.03
2 13:39:43.608824 start: 0 validate
3 13:39:43.609008 Start time: 2024-05-28 13:39:43.608999+00:00 (UTC)
4 13:39:43.609200 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:39:43.609412 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 13:39:43.869664 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:39:43.869900 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:39:44.127676 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:39:44.127875 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 13:39:44.384902 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:39:44.385109 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:39:44.909788 validate duration: 1.30
14 13:39:44.910089 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:39:44.910217 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:39:44.910323 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:39:44.910459 Not decompressing ramdisk as can be used compressed.
18 13:39:44.910552 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 13:39:44.910627 saving as /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/ramdisk/rootfs.cpio.gz
20 13:39:44.910698 total size: 8181887 (7 MB)
21 13:39:44.911883 progress 0 % (0 MB)
22 13:39:44.914533 progress 5 % (0 MB)
23 13:39:44.916930 progress 10 % (0 MB)
24 13:39:44.919561 progress 15 % (1 MB)
25 13:39:44.921972 progress 20 % (1 MB)
26 13:39:44.924504 progress 25 % (1 MB)
27 13:39:44.926855 progress 30 % (2 MB)
28 13:39:44.929505 progress 35 % (2 MB)
29 13:39:44.931818 progress 40 % (3 MB)
30 13:39:44.934376 progress 45 % (3 MB)
31 13:39:44.936819 progress 50 % (3 MB)
32 13:39:44.939355 progress 55 % (4 MB)
33 13:39:44.941688 progress 60 % (4 MB)
34 13:39:44.944316 progress 65 % (5 MB)
35 13:39:44.946657 progress 70 % (5 MB)
36 13:39:44.949225 progress 75 % (5 MB)
37 13:39:44.951520 progress 80 % (6 MB)
38 13:39:44.954067 progress 85 % (6 MB)
39 13:39:44.956407 progress 90 % (7 MB)
40 13:39:44.958993 progress 95 % (7 MB)
41 13:39:44.961270 progress 100 % (7 MB)
42 13:39:44.961505 7 MB downloaded in 0.05 s (153.58 MB/s)
43 13:39:44.961695 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:39:44.962001 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:39:44.962119 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:39:44.962230 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:39:44.962392 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:39:44.962475 saving as /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/kernel/Image
50 13:39:44.962588 total size: 54682112 (52 MB)
51 13:39:44.962699 No compression specified
52 13:39:44.964445 progress 0 % (0 MB)
53 13:39:44.980528 progress 5 % (2 MB)
54 13:39:44.996485 progress 10 % (5 MB)
55 13:39:45.012651 progress 15 % (7 MB)
56 13:39:45.028681 progress 20 % (10 MB)
57 13:39:45.044741 progress 25 % (13 MB)
58 13:39:45.060926 progress 30 % (15 MB)
59 13:39:45.076940 progress 35 % (18 MB)
60 13:39:45.092906 progress 40 % (20 MB)
61 13:39:45.108590 progress 45 % (23 MB)
62 13:39:45.124170 progress 50 % (26 MB)
63 13:39:45.139501 progress 55 % (28 MB)
64 13:39:45.154991 progress 60 % (31 MB)
65 13:39:45.170373 progress 65 % (33 MB)
66 13:39:45.186316 progress 70 % (36 MB)
67 13:39:45.202270 progress 75 % (39 MB)
68 13:39:45.218541 progress 80 % (41 MB)
69 13:39:45.234643 progress 85 % (44 MB)
70 13:39:45.250775 progress 90 % (46 MB)
71 13:39:45.266778 progress 95 % (49 MB)
72 13:39:45.282455 progress 100 % (52 MB)
73 13:39:45.282755 52 MB downloaded in 0.32 s (162.88 MB/s)
74 13:39:45.282948 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:39:45.283343 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:39:45.283487 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:39:45.283601 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:39:45.283765 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 13:39:45.283848 saving as /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 13:39:45.283957 total size: 57695 (0 MB)
82 13:39:45.284068 No compression specified
83 13:39:45.285852 progress 56 % (0 MB)
84 13:39:45.286195 progress 100 % (0 MB)
85 13:39:45.286433 0 MB downloaded in 0.00 s (22.25 MB/s)
86 13:39:45.286600 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:39:45.287025 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:39:45.287127 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:39:45.287220 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:39:45.287344 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:39:45.287429 saving as /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/modules/modules.tar
93 13:39:45.287497 total size: 8607916 (8 MB)
94 13:39:45.287565 Using unxz to decompress xz
95 13:39:45.292043 progress 0 % (0 MB)
96 13:39:45.313945 progress 5 % (0 MB)
97 13:39:45.341121 progress 10 % (0 MB)
98 13:39:45.369570 progress 15 % (1 MB)
99 13:39:45.397052 progress 20 % (1 MB)
100 13:39:45.425595 progress 25 % (2 MB)
101 13:39:45.453403 progress 30 % (2 MB)
102 13:39:45.479631 progress 35 % (2 MB)
103 13:39:45.508775 progress 40 % (3 MB)
104 13:39:45.536778 progress 45 % (3 MB)
105 13:39:45.563595 progress 50 % (4 MB)
106 13:39:45.592089 progress 55 % (4 MB)
107 13:39:45.620301 progress 60 % (4 MB)
108 13:39:45.647739 progress 65 % (5 MB)
109 13:39:45.677504 progress 70 % (5 MB)
110 13:39:45.707837 progress 75 % (6 MB)
111 13:39:45.734114 progress 80 % (6 MB)
112 13:39:45.760436 progress 85 % (7 MB)
113 13:39:45.786980 progress 90 % (7 MB)
114 13:39:45.820377 progress 95 % (7 MB)
115 13:39:45.852709 progress 100 % (8 MB)
116 13:39:45.859234 8 MB downloaded in 0.57 s (14.36 MB/s)
117 13:39:45.859537 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:39:45.859841 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:39:45.859950 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:39:45.860060 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:39:45.860153 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:39:45.860252 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:39:45.860516 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp
125 13:39:45.860736 makedir: /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin
126 13:39:45.860882 makedir: /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/tests
127 13:39:45.860997 makedir: /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/results
128 13:39:45.861130 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-add-keys
129 13:39:45.861295 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-add-sources
130 13:39:45.861441 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-background-process-start
131 13:39:45.861589 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-background-process-stop
132 13:39:45.861731 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-common-functions
133 13:39:45.861872 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-echo-ipv4
134 13:39:45.862012 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-install-packages
135 13:39:45.862153 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-installed-packages
136 13:39:45.862291 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-os-build
137 13:39:45.862431 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-probe-channel
138 13:39:45.862572 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-probe-ip
139 13:39:45.862712 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-target-ip
140 13:39:45.862851 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-target-mac
141 13:39:45.862990 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-target-storage
142 13:39:45.863140 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-case
143 13:39:45.863281 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-event
144 13:39:45.863426 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-feedback
145 13:39:45.863568 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-raise
146 13:39:45.863708 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-reference
147 13:39:45.863848 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-runner
148 13:39:45.863986 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-set
149 13:39:45.864128 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-test-shell
150 13:39:45.864272 Updating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-install-packages (oe)
151 13:39:45.864438 Updating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/bin/lava-installed-packages (oe)
152 13:39:45.864575 Creating /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/environment
153 13:39:45.864687 LAVA metadata
154 13:39:45.864807 - LAVA_JOB_ID=14063110
155 13:39:45.864927 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:39:45.865108 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:39:45.865191 skipped lava-vland-overlay
158 13:39:45.865278 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:39:45.865383 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:39:45.865458 skipped lava-multinode-overlay
161 13:39:45.865540 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:39:45.865645 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:39:45.865730 Loading test definitions
164 13:39:45.865833 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:39:45.865914 Using /lava-14063110 at stage 0
166 13:39:45.866285 uuid=14063110_1.5.2.3.1 testdef=None
167 13:39:45.866386 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:39:45.866485 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:39:45.867109 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:39:45.867369 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:39:45.868193 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:39:45.868472 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:39:45.869163 runner path: /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/0/tests/0_dmesg test_uuid 14063110_1.5.2.3.1
176 13:39:45.869339 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:39:45.869575 Creating lava-test-runner.conf files
179 13:39:45.869646 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063110/lava-overlay-03uo9tzp/lava-14063110/0 for stage 0
180 13:39:45.869745 - 0_dmesg
181 13:39:45.869853 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:39:45.869949 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:39:45.878179 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:39:45.878316 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:39:45.878416 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:39:45.878513 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:39:45.878608 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:39:46.145444 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 13:39:46.145877 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 13:39:46.146043 extracting modules file /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063110/extract-overlay-ramdisk-fgnuv0k_/ramdisk
191 13:39:46.393156 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:39:46.393335 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 13:39:46.393440 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063110/compress-overlay-j2l8cbzn/overlay-1.5.2.4.tar.gz to ramdisk
194 13:39:46.393521 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063110/compress-overlay-j2l8cbzn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063110/extract-overlay-ramdisk-fgnuv0k_/ramdisk
195 13:39:46.401113 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:39:46.401256 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 13:39:46.401355 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:39:46.401451 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 13:39:46.401538 Building ramdisk /var/lib/lava/dispatcher/tmp/14063110/extract-overlay-ramdisk-fgnuv0k_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063110/extract-overlay-ramdisk-fgnuv0k_/ramdisk
200 13:39:46.793560 >> 145117 blocks
201 13:39:49.356701 rename /var/lib/lava/dispatcher/tmp/14063110/extract-overlay-ramdisk-fgnuv0k_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/ramdisk/ramdisk.cpio.gz
202 13:39:49.357207 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 13:39:49.357381 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 13:39:49.357520 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 13:39:49.357679 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/kernel/Image']
206 13:40:04.315985 Returned 0 in 14 seconds
207 13:40:04.416628 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/kernel/image.itb
208 13:40:04.842837 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:40:04.843292 output: Created: Tue May 28 14:40:04 2024
210 13:40:04.843422 output: Image 0 (kernel-1)
211 13:40:04.843497 output: Description:
212 13:40:04.843569 output: Created: Tue May 28 14:40:04 2024
213 13:40:04.843639 output: Type: Kernel Image
214 13:40:04.843706 output: Compression: lzma compressed
215 13:40:04.843772 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:40:04.843835 output: Architecture: AArch64
217 13:40:04.843895 output: OS: Linux
218 13:40:04.843954 output: Load Address: 0x00000000
219 13:40:04.844014 output: Entry Point: 0x00000000
220 13:40:04.844073 output: Hash algo: crc32
221 13:40:04.844136 output: Hash value: 0578ee26
222 13:40:04.844195 output: Image 1 (fdt-1)
223 13:40:04.844255 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 13:40:04.844348 output: Created: Tue May 28 14:40:04 2024
225 13:40:04.844446 output: Type: Flat Device Tree
226 13:40:04.844538 output: Compression: uncompressed
227 13:40:04.844628 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 13:40:04.844718 output: Architecture: AArch64
229 13:40:04.844810 output: Hash algo: crc32
230 13:40:04.844874 output: Hash value: a9713552
231 13:40:04.844964 output: Image 2 (ramdisk-1)
232 13:40:04.845054 output: Description: unavailable
233 13:40:04.845145 output: Created: Tue May 28 14:40:04 2024
234 13:40:04.845246 output: Type: RAMDisk Image
235 13:40:04.845338 output: Compression: Unknown Compression
236 13:40:04.845427 output: Data Size: 21361549 Bytes = 20860.89 KiB = 20.37 MiB
237 13:40:04.845489 output: Architecture: AArch64
238 13:40:04.845546 output: OS: Linux
239 13:40:04.845604 output: Load Address: unavailable
240 13:40:04.845661 output: Entry Point: unavailable
241 13:40:04.845717 output: Hash algo: crc32
242 13:40:04.845774 output: Hash value: fec30ca0
243 13:40:04.845831 output: Default Configuration: 'conf-1'
244 13:40:04.845894 output: Configuration 0 (conf-1)
245 13:40:04.845955 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 13:40:04.846013 output: Kernel: kernel-1
247 13:40:04.846070 output: Init Ramdisk: ramdisk-1
248 13:40:04.846126 output: FDT: fdt-1
249 13:40:04.846183 output: Loadables: kernel-1
250 13:40:04.846239 output:
251 13:40:04.846473 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:40:04.846615 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:40:04.846765 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 13:40:04.846901 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 13:40:04.847011 No LXC device requested
256 13:40:04.847133 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:40:04.847258 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 13:40:04.847396 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:40:04.847486 Checking files for TFTP limit of 4294967296 bytes.
260 13:40:04.848046 end: 1 tftp-deploy (duration 00:00:20) [common]
261 13:40:04.848167 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:40:04.848270 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:40:04.848404 substitutions:
264 13:40:04.848479 - {DTB}: 14063110/tftp-deploy-d74aqu_f/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 13:40:04.848550 - {INITRD}: 14063110/tftp-deploy-d74aqu_f/ramdisk/ramdisk.cpio.gz
266 13:40:04.848616 - {KERNEL}: 14063110/tftp-deploy-d74aqu_f/kernel/Image
267 13:40:04.848679 - {LAVA_MAC}: None
268 13:40:04.848740 - {PRESEED_CONFIG}: None
269 13:40:04.848800 - {PRESEED_LOCAL}: None
270 13:40:04.848858 - {RAMDISK}: 14063110/tftp-deploy-d74aqu_f/ramdisk/ramdisk.cpio.gz
271 13:40:04.848917 - {ROOT_PART}: None
272 13:40:04.848982 - {ROOT}: None
273 13:40:04.849041 - {SERVER_IP}: 192.168.201.1
274 13:40:04.849098 - {TEE}: None
275 13:40:04.849158 Parsed boot commands:
276 13:40:04.849219 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:40:04.849409 Parsed boot commands: tftpboot 192.168.201.1 14063110/tftp-deploy-d74aqu_f/kernel/image.itb 14063110/tftp-deploy-d74aqu_f/kernel/cmdline
278 13:40:04.849511 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:40:04.849605 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:40:04.849701 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:40:04.849793 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:40:04.849871 Not connected, no need to disconnect.
283 13:40:04.849954 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:40:04.850056 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:40:04.850161 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
286 13:40:04.854371 Setting prompt string to ['lava-test: # ']
287 13:40:04.854844 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:40:04.854975 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:40:04.855088 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:40:04.855221 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:40:04.855518 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-0']
292 13:40:15.163645 Returned 0 in 10 seconds
293 13:40:15.264622 end: 2.2.2.1 pdu-reboot (duration 00:00:10) [common]
295 13:40:15.265107 end: 2.2.2 reset-device (duration 00:00:10) [common]
296 13:40:15.265260 start: 2.2.3 depthcharge-start (timeout 00:04:50) [common]
297 13:40:15.265395 Setting prompt string to 'Starting depthcharge on Juniper...'
298 13:40:15.265508 Changing prompt to 'Starting depthcharge on Juniper...'
299 13:40:15.265616 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
300 13:40:15.266274 [Enter `^Ec?' for help]
301 13:40:15.266411 [DL] 00000000 00000000 010701
302 13:40:15.266518
303 13:40:15.266620
304 13:40:15.266722 F0: 102B 0000
305 13:40:15.266820
306 13:40:15.266926 F3: 1006 0033 [0200]
307 13:40:15.267024
308 13:40:15.267119 F3: 4001 00E0 [0200]
309 13:40:15.267213
310 13:40:15.267304 F3: 0000 0000
311 13:40:15.267416
312 13:40:15.267512 V0: 0000 0000 [0001]
313 13:40:15.267604
314 13:40:15.267697 00: 1027 0002
315 13:40:15.267794
316 13:40:15.267886 01: 0000 0000
317 13:40:15.267990
318 13:40:15.268082 BP: 0C00 0251 [0000]
319 13:40:15.268174
320 13:40:15.268265 G0: 1182 0000
321 13:40:15.268357
322 13:40:15.268455 EC: 0004 0000 [0001]
323 13:40:15.268517
324 13:40:15.268576 S7: 0000 0000 [0000]
325 13:40:15.268635
326 13:40:15.268720 CC: 0000 0000 [0001]
327 13:40:15.268824
328 13:40:15.268928 T0: 0000 00DB [000F]
329 13:40:15.269029
330 13:40:15.269127 Jump to BL
331 13:40:15.269219
332 13:40:15.269314
333 13:40:15.269383
334 13:40:15.269462 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
335 13:40:15.269528 ARM64: Exception handlers installed.
336 13:40:15.269606 ARM64: Testing exception
337 13:40:15.269704 ARM64: Done test exception
338 13:40:15.269798 WDT: Last reset was cold boot
339 13:40:15.269891 SPI0(PAD0) initialized at 992727 Hz
340 13:40:15.269996 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
341 13:40:15.270090 Manufacturer: ef
342 13:40:15.270183 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
343 13:40:15.270275 Probing TPM: . done!
344 13:40:15.270367 TPM ready after 0 ms
345 13:40:15.270462 Connected to device vid:did:rid of 1ae0:0028:00
346 13:40:15.270525 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
347 13:40:15.270586 Initialized TPM device CR50 revision 0
348 13:40:15.270645 tlcl_send_startup: Startup return code is 0
349 13:40:15.270704 TPM: setup succeeded
350 13:40:15.270763 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
351 13:40:15.270822 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
352 13:40:15.270881 in-header: 03 19 00 00 08 00 00 00
353 13:40:15.270957 in-data: a2 e0 47 00 13 00 00 00
354 13:40:15.271050 Chrome EC: UHEPI supported
355 13:40:15.271143 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
356 13:40:15.271236 in-header: 03 a1 00 00 08 00 00 00
357 13:40:15.271332 in-data: 84 60 60 10 00 00 00 00
358 13:40:15.271437 Phase 1
359 13:40:15.271521 FMAP: area GBB found @ 3f5000 (12032 bytes)
360 13:40:15.271584 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
361 13:40:15.271662 VB2:vb2_check_recovery() Recovery was requested manually
362 13:40:15.271830 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
363 13:40:15.271960 Recovery requested (1009000e)
364 13:40:15.272037 tlcl_extend: response is 0
365 13:40:15.272105 tlcl_extend: response is 0
366 13:40:15.272168
367 13:40:15.272264
368 13:40:15.272357 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
369 13:40:15.272450 ARM64: Exception handlers installed.
370 13:40:15.272549 ARM64: Testing exception
371 13:40:15.272642 ARM64: Done test exception
372 13:40:15.272735 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x2000
373 13:40:15.272834 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
374 13:40:15.272929 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
375 13:40:15.273026 [RTC]rtc_get_frequency_meter,134: input=0xf, output=916
376 13:40:15.273121 [RTC]rtc_get_frequency_meter,134: input=0x7, output=779
377 13:40:15.273214 [RTC]rtc_get_frequency_meter,134: input=0xb, output=847
378 13:40:15.273307 [RTC]rtc_get_frequency_meter,134: input=0x9, output=813
379 13:40:15.273399 [RTC]rtc_get_frequency_meter,134: input=0x8, output=796
380 13:40:15.273491 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
381 13:40:15.273583 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
382 13:40:15.273675 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
383 13:40:15.273766 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
384 13:40:15.273858 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
385 13:40:15.273950 in-header: 03 19 00 00 08 00 00 00
386 13:40:15.274042 in-data: a2 e0 47 00 13 00 00 00
387 13:40:15.274133 Chrome EC: UHEPI supported
388 13:40:15.274226 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
389 13:40:15.274318 in-header: 03 a1 00 00 08 00 00 00
390 13:40:15.274411 in-data: 84 60 60 10 00 00 00 00
391 13:40:15.274502 Skip loading cached calibration data
392 13:40:15.274594 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
393 13:40:15.274687 in-header: 03 a1 00 00 08 00 00 00
394 13:40:15.274748 in-data: 84 60 60 10 00 00 00 00
395 13:40:15.274806 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
396 13:40:15.274865 in-header: 03 a1 00 00 08 00 00 00
397 13:40:15.274922 in-data: 84 60 60 10 00 00 00 00
398 13:40:15.274980 ADC[3]: Raw value=215860 ID=1
399 13:40:15.275061 Manufacturer: ef
400 13:40:15.275218 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
401 13:40:15.275351 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
402 13:40:15.275456 CBFS @ 21000 size 3d4000
403 13:40:15.275519 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
404 13:40:15.275584 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
405 13:40:15.275644 CBFS: Found @ offset 3c700 size 44
406 13:40:15.275704 DRAM-K: Full Calibration
407 13:40:15.275762 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
408 13:40:15.275821 CBFS @ 21000 size 3d4000
409 13:40:15.275879 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
410 13:40:15.275938 CBFS: Locating 'fallback/dram'
411 13:40:15.276001 CBFS: Found @ offset 24b00 size 12268
412 13:40:15.276059 read SPI 0x45b44 0x1224c: 22775 us, 3263 KB/s, 26.104 Mbps
413 13:40:15.276118 ddr_geometry: 1, config: 0x0
414 13:40:15.276176 header.status = 0x0
415 13:40:15.276240 header.magic = 0x44524d4b (expected: 0x44524d4b)
416 13:40:15.276338 header.version = 0x5 (expected: 0x5)
417 13:40:15.276435 header.size = 0x8f0 (expected: 0x8f0)
418 13:40:15.276515 header.config = 0x0
419 13:40:15.276577 header.flags = 0x0
420 13:40:15.276665 header.checksum = 0x0
421 13:40:15.276999 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
422 13:40:15.277125 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
423 13:40:15.277231 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
424 13:40:15.277336 ddr_geometry:1
425 13:40:15.277432 [EMI] new MDL number = 1
426 13:40:15.277526 dram_cbt_mode_extern: 0
427 13:40:15.277618 dram_cbt_mode [RK0]: 0, [RK1]: 0
428 13:40:15.277710 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
429 13:40:15.277802
430 13:40:15.277896
431 13:40:15.277988 [Bianco] ETT version 0.0.0.1
432 13:40:15.278080 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
433 13:40:15.278172
434 13:40:15.278263 vSetVcoreByFreq with vcore:762500, freq=1600
435 13:40:15.278357
436 13:40:15.278448 [DramcInit]
437 13:40:15.278539 AutoRefreshCKEOff AutoREF OFF
438 13:40:15.278630 DDRPhyPLLSetting-CKEOFF
439 13:40:15.278721 DDRPhyPLLSetting-CKEON
440 13:40:15.278811
441 13:40:15.278902 Enable WDQS
442 13:40:15.278992 [ModeRegInit_LP4] CH0 RK0
443 13:40:15.279083 Write Rank0 MR13 =0x18
444 13:40:15.279173 Write Rank0 MR12 =0x5d
445 13:40:15.279264 Write Rank0 MR1 =0x56
446 13:40:15.279354 Write Rank0 MR2 =0x1a
447 13:40:15.279472 Write Rank0 MR11 =0x0
448 13:40:15.279565 Write Rank0 MR22 =0x38
449 13:40:15.279656 Write Rank0 MR14 =0x5d
450 13:40:15.279747 Write Rank0 MR3 =0x30
451 13:40:15.279838 Write Rank0 MR13 =0x58
452 13:40:15.279928 Write Rank0 MR12 =0x5d
453 13:40:15.280019 Write Rank0 MR1 =0x56
454 13:40:15.280109 Write Rank0 MR2 =0x2d
455 13:40:15.280200 Write Rank0 MR11 =0x23
456 13:40:15.280290 Write Rank0 MR22 =0x34
457 13:40:15.280381 Write Rank0 MR14 =0x10
458 13:40:15.280473 Write Rank0 MR3 =0x30
459 13:40:15.280544 Write Rank0 MR13 =0xd8
460 13:40:15.280603 [ModeRegInit_LP4] CH0 RK1
461 13:40:15.280706 Write Rank1 MR13 =0x18
462 13:40:15.280802 Write Rank1 MR12 =0x5d
463 13:40:15.280894 Write Rank1 MR1 =0x56
464 13:40:15.280969 Write Rank1 MR2 =0x1a
465 13:40:15.281030 Write Rank1 MR11 =0x0
466 13:40:15.281088 Write Rank1 MR22 =0x38
467 13:40:15.281162 Write Rank1 MR14 =0x5d
468 13:40:15.281223 Write Rank1 MR3 =0x30
469 13:40:15.281291 Write Rank1 MR13 =0x58
470 13:40:15.281385 Write Rank1 MR12 =0x5d
471 13:40:15.281512 Write Rank1 MR1 =0x56
472 13:40:15.281670 Write Rank1 MR2 =0x2d
473 13:40:15.281780 Write Rank1 MR11 =0x23
474 13:40:15.281874 Write Rank1 MR22 =0x34
475 13:40:15.281970 Write Rank1 MR14 =0x10
476 13:40:15.282062 Write Rank1 MR3 =0x30
477 13:40:15.282153 Write Rank1 MR13 =0xd8
478 13:40:15.282245 [ModeRegInit_LP4] CH1 RK0
479 13:40:15.282336 Write Rank0 MR13 =0x18
480 13:40:15.282426 Write Rank0 MR12 =0x5d
481 13:40:15.282518 Write Rank0 MR1 =0x56
482 13:40:15.282608 Write Rank0 MR2 =0x1a
483 13:40:15.282699 Write Rank0 MR11 =0x0
484 13:40:15.282790 Write Rank0 MR22 =0x38
485 13:40:15.282873 Write Rank0 MR14 =0x5d
486 13:40:15.283058 Write Rank0 MR3 =0x30
487 13:40:15.283169 Write Rank0 MR13 =0x58
488 13:40:15.283264 Write Rank0 MR12 =0x5d
489 13:40:15.283361 Write Rank0 MR1 =0x56
490 13:40:15.283456 Write Rank0 MR2 =0x2d
491 13:40:15.283521 Write Rank0 MR11 =0x23
492 13:40:15.283581 Write Rank0 MR22 =0x34
493 13:40:15.283649 Write Rank0 MR14 =0x10
494 13:40:15.283747 Write Rank0 MR3 =0x30
495 13:40:15.283841 Write Rank0 MR13 =0xd8
496 13:40:15.283935 [ModeRegInit_LP4] CH1 RK1
497 13:40:15.284029 Write Rank1 MR13 =0x18
498 13:40:15.284125 Write Rank1 MR12 =0x5d
499 13:40:15.284221 Write Rank1 MR1 =0x56
500 13:40:15.284313 Write Rank1 MR2 =0x1a
501 13:40:15.284475 Write Rank1 MR11 =0x0
502 13:40:15.284602 Write Rank1 MR22 =0x38
503 13:40:15.284708 Write Rank1 MR14 =0x5d
504 13:40:15.284801 Write Rank1 MR3 =0x30
505 13:40:15.284893 Write Rank1 MR13 =0x58
506 13:40:15.284984 Write Rank1 MR12 =0x5d
507 13:40:15.285075 Write Rank1 MR1 =0x56
508 13:40:15.285167 Write Rank1 MR2 =0x2d
509 13:40:15.285258 Write Rank1 MR11 =0x23
510 13:40:15.285352 Write Rank1 MR22 =0x34
511 13:40:15.285447 Write Rank1 MR14 =0x10
512 13:40:15.285541 Write Rank1 MR3 =0x30
513 13:40:15.285633 Write Rank1 MR13 =0xd8
514 13:40:15.285724 match AC timing 3
515 13:40:15.285819 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
516 13:40:15.285915 [MiockJmeterHQA]
517 13:40:15.286011 vSetVcoreByFreq with vcore:762500, freq=1600
518 13:40:15.286102
519 13:40:15.286194 MIOCK jitter meter ch=0
520 13:40:15.286285
521 13:40:15.286378 1T = (102-17) = 85 dly cells
522 13:40:15.286473 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
523 13:40:15.286565 vSetVcoreByFreq with vcore:725000, freq=1200
524 13:40:15.286632
525 13:40:15.286690 MIOCK jitter meter ch=0
526 13:40:15.286749
527 13:40:15.286816 1T = (97-17) = 80 dly cells
528 13:40:15.286941 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
529 13:40:15.287109 vSetVcoreByFreq with vcore:725000, freq=800
530 13:40:15.287219
531 13:40:15.287313 MIOCK jitter meter ch=0
532 13:40:15.287409
533 13:40:15.287474 1T = (97-17) = 80 dly cells
534 13:40:15.287534 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
535 13:40:15.287593 vSetVcoreByFreq with vcore:762500, freq=1600
536 13:40:15.287688 vSetVcoreByFreq with vcore:762500, freq=1600
537 13:40:15.287779
538 13:40:15.287869 K DRVP
539 13:40:15.287960 1. OCD DRVP=0 CALOUT=0
540 13:40:15.288061 1. OCD DRVP=1 CALOUT=0
541 13:40:15.288161 1. OCD DRVP=2 CALOUT=0
542 13:40:15.288269 1. OCD DRVP=3 CALOUT=0
543 13:40:15.288364 1. OCD DRVP=4 CALOUT=0
544 13:40:15.288458 1. OCD DRVP=5 CALOUT=0
545 13:40:15.288554 1. OCD DRVP=6 CALOUT=0
546 13:40:15.288650 1. OCD DRVP=7 CALOUT=0
547 13:40:15.288750 1. OCD DRVP=8 CALOUT=0
548 13:40:15.288850 1. OCD DRVP=9 CALOUT=1
549 13:40:15.288944
550 13:40:15.289035 1. OCD DRVP calibration OK! DRVP=9
551 13:40:15.289128
552 13:40:15.289218
553 13:40:15.289308
554 13:40:15.289401 K ODTN
555 13:40:15.289495 3. OCD ODTN=0 ,CALOUT=1
556 13:40:15.289589 3. OCD ODTN=1 ,CALOUT=1
557 13:40:15.289684 3. OCD ODTN=2 ,CALOUT=1
558 13:40:15.289837 3. OCD ODTN=3 ,CALOUT=1
559 13:40:15.289985 3. OCD ODTN=4 ,CALOUT=1
560 13:40:15.290094 3. OCD ODTN=5 ,CALOUT=1
561 13:40:15.290190 3. OCD ODTN=6 ,CALOUT=1
562 13:40:15.290288 3. OCD ODTN=7 ,CALOUT=0
563 13:40:15.290382
564 13:40:15.290473 3. OCD ODTN calibration OK! ODTN=7
565 13:40:15.290539
566 13:40:15.290597 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
567 13:40:15.290656 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
568 13:40:15.290754 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
569 13:40:15.290848
570 13:40:15.290939 K DRVP
571 13:40:15.291035 1. OCD DRVP=0 CALOUT=0
572 13:40:15.291204 1. OCD DRVP=1 CALOUT=0
573 13:40:15.291330 1. OCD DRVP=2 CALOUT=0
574 13:40:15.291436 1. OCD DRVP=3 CALOUT=0
575 13:40:15.291500 1. OCD DRVP=4 CALOUT=0
576 13:40:15.291563 1. OCD DRVP=5 CALOUT=0
577 13:40:15.291627 1. OCD DRVP=6 CALOUT=0
578 13:40:15.291717 1. OCD DRVP=7 CALOUT=0
579 13:40:15.291812 1. OCD DRVP=8 CALOUT=0
580 13:40:15.291906 1. OCD DRVP=9 CALOUT=0
581 13:40:15.291999 1. OCD DRVP=10 CALOUT=0
582 13:40:15.292092 1. OCD DRVP=11 CALOUT=1
583 13:40:15.292185
584 13:40:15.292276 1. OCD DRVP calibration OK! DRVP=11
585 13:40:15.292369
586 13:40:15.292459
587 13:40:15.292553
588 13:40:15.292653 K ODTN
589 13:40:15.292748 3. OCD ODTN=0 ,CALOUT=1
590 13:40:15.293054 3. OCD ODTN=1 ,CALOUT=1
591 13:40:15.293242 3. OCD ODTN=2 ,CALOUT=1
592 13:40:15.293357 3. OCD ODTN=3 ,CALOUT=1
593 13:40:15.293462 3. OCD ODTN=4 ,CALOUT=1
594 13:40:15.293570 3. OCD ODTN=5 ,CALOUT=1
595 13:40:15.293667 3. OCD ODTN=6 ,CALOUT=1
596 13:40:15.293762 3. OCD ODTN=7 ,CALOUT=1
597 13:40:15.293856 3. OCD ODTN=8 ,CALOUT=1
598 13:40:15.293951 3. OCD ODTN=9 ,CALOUT=1
599 13:40:15.294045 3. OCD ODTN=10 ,CALOUT=1
600 13:40:15.294139 3. OCD ODTN=11 ,CALOUT=1
601 13:40:15.294233 3. OCD ODTN=12 ,CALOUT=1
602 13:40:15.294327 3. OCD ODTN=13 ,CALOUT=1
603 13:40:15.294423 3. OCD ODTN=14 ,CALOUT=1
604 13:40:15.294516 3. OCD ODTN=15 ,CALOUT=0
605 13:40:15.294616
606 13:40:15.294710 3. OCD ODTN calibration OK! ODTN=15
607 13:40:15.294803
608 13:40:15.294898 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
609 13:40:15.294992 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
610 13:40:15.295086 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
611 13:40:15.295178
612 13:40:15.295272 [DramcInit]
613 13:40:15.295363 AutoRefreshCKEOff AutoREF OFF
614 13:40:15.295454 DDRPhyPLLSetting-CKEOFF
615 13:40:15.295515 DDRPhyPLLSetting-CKEON
616 13:40:15.295573
617 13:40:15.295631 Enable WDQS
618 13:40:15.295689 ==
619 13:40:15.295747 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
620 13:40:15.295805 fsp= 1, odt_onoff= 1, Byte mode= 0
621 13:40:15.295863 ==
622 13:40:15.295921 [Duty_Offset_Calibration]
623 13:40:15.295979
624 13:40:15.296036 ===========================
625 13:40:15.296093 B0:1 B1:1 CA:1
626 13:40:15.296150 ==
627 13:40:15.296207 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
628 13:40:15.296265 fsp= 1, odt_onoff= 1, Byte mode= 0
629 13:40:15.296323 ==
630 13:40:15.296395 [Duty_Offset_Calibration]
631 13:40:15.296455
632 13:40:15.296512 ===========================
633 13:40:15.296570 B0:1 B1:0 CA:2
634 13:40:15.296627 [ModeRegInit_LP4] CH0 RK0
635 13:40:15.296684 Write Rank0 MR13 =0x18
636 13:40:15.296741 Write Rank0 MR12 =0x5d
637 13:40:15.296797 Write Rank0 MR1 =0x56
638 13:40:15.296854 Write Rank0 MR2 =0x1a
639 13:40:15.296912 Write Rank0 MR11 =0x0
640 13:40:15.296969 Write Rank0 MR22 =0x38
641 13:40:15.297026 Write Rank0 MR14 =0x5d
642 13:40:15.297083 Write Rank0 MR3 =0x30
643 13:40:15.297140 Write Rank0 MR13 =0x58
644 13:40:15.297197 Write Rank0 MR12 =0x5d
645 13:40:15.297254 Write Rank0 MR1 =0x56
646 13:40:15.297310 Write Rank0 MR2 =0x2d
647 13:40:15.297367 Write Rank0 MR11 =0x23
648 13:40:15.297424 Write Rank0 MR22 =0x34
649 13:40:15.297482 Write Rank0 MR14 =0x10
650 13:40:15.297539 Write Rank0 MR3 =0x30
651 13:40:15.297597 Write Rank0 MR13 =0xd8
652 13:40:15.297654 [ModeRegInit_LP4] CH0 RK1
653 13:40:15.297712 Write Rank1 MR13 =0x18
654 13:40:15.297769 Write Rank1 MR12 =0x5d
655 13:40:15.297827 Write Rank1 MR1 =0x56
656 13:40:15.297884 Write Rank1 MR2 =0x1a
657 13:40:15.297941 Write Rank1 MR11 =0x0
658 13:40:15.297998 Write Rank1 MR22 =0x38
659 13:40:15.298055 Write Rank1 MR14 =0x5d
660 13:40:15.298112 Write Rank1 MR3 =0x30
661 13:40:15.298169 Write Rank1 MR13 =0x58
662 13:40:15.298226 Write Rank1 MR12 =0x5d
663 13:40:15.298282 Write Rank1 MR1 =0x56
664 13:40:15.298339 Write Rank1 MR2 =0x2d
665 13:40:15.298396 Write Rank1 MR11 =0x23
666 13:40:15.298462 Write Rank1 MR22 =0x34
667 13:40:15.298562 Write Rank1 MR14 =0x10
668 13:40:15.298627 Write Rank1 MR3 =0x30
669 13:40:15.298686 Write Rank1 MR13 =0xd8
670 13:40:15.298744 [ModeRegInit_LP4] CH1 RK0
671 13:40:15.298801 Write Rank0 MR13 =0x18
672 13:40:15.298858 Write Rank0 MR12 =0x5d
673 13:40:15.298915 Write Rank0 MR1 =0x56
674 13:40:15.298972 Write Rank0 MR2 =0x1a
675 13:40:15.299029 Write Rank0 MR11 =0x0
676 13:40:15.299087 Write Rank0 MR22 =0x38
677 13:40:15.299143 Write Rank0 MR14 =0x5d
678 13:40:15.299201 Write Rank0 MR3 =0x30
679 13:40:15.299258 Write Rank0 MR13 =0x58
680 13:40:15.299315 Write Rank0 MR12 =0x5d
681 13:40:15.299372 Write Rank0 MR1 =0x56
682 13:40:15.299444 Write Rank0 MR2 =0x2d
683 13:40:15.299504 Write Rank0 MR11 =0x23
684 13:40:15.299562 Write Rank0 MR22 =0x34
685 13:40:15.299618 Write Rank0 MR14 =0x10
686 13:40:15.299676 Write Rank0 MR3 =0x30
687 13:40:15.299733 Write Rank0 MR13 =0xd8
688 13:40:15.299791 [ModeRegInit_LP4] CH1 RK1
689 13:40:15.299848 Write Rank1 MR13 =0x18
690 13:40:15.299906 Write Rank1 MR12 =0x5d
691 13:40:15.299963 Write Rank1 MR1 =0x56
692 13:40:15.300021 Write Rank1 MR2 =0x1a
693 13:40:15.300077 Write Rank1 MR11 =0x0
694 13:40:15.300134 Write Rank1 MR22 =0x38
695 13:40:15.300191 Write Rank1 MR14 =0x5d
696 13:40:15.300248 Write Rank1 MR3 =0x30
697 13:40:15.300305 Write Rank1 MR13 =0x58
698 13:40:15.300362 Write Rank1 MR12 =0x5d
699 13:40:15.300418 Write Rank1 MR1 =0x56
700 13:40:15.300474 Write Rank1 MR2 =0x2d
701 13:40:15.300530 Write Rank1 MR11 =0x23
702 13:40:15.300586 Write Rank1 MR22 =0x34
703 13:40:15.300643 Write Rank1 MR14 =0x10
704 13:40:15.300699 Write Rank1 MR3 =0x30
705 13:40:15.300755 Write Rank1 MR13 =0xd8
706 13:40:15.300812 match AC timing 3
707 13:40:15.300870 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
708 13:40:15.300928 DramC Write-DBI off
709 13:40:15.300985 DramC Read-DBI off
710 13:40:15.301043 Write Rank0 MR13 =0x59
711 13:40:15.301100 ==
712 13:40:15.301158 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
713 13:40:15.301215 fsp= 1, odt_onoff= 1, Byte mode= 0
714 13:40:15.301273 ==
715 13:40:15.301330 === u2Vref_new: 0x56 --> 0x2d
716 13:40:15.301388 === u2Vref_new: 0x58 --> 0x38
717 13:40:15.301445 === u2Vref_new: 0x5a --> 0x39
718 13:40:15.301503 === u2Vref_new: 0x5c --> 0x3c
719 13:40:15.301561 === u2Vref_new: 0x5e --> 0x3d
720 13:40:15.301619 === u2Vref_new: 0x60 --> 0xa0
721 13:40:15.301676 [CA 0] Center 34 (6~63) winsize 58
722 13:40:15.301734 [CA 1] Center 36 (9~63) winsize 55
723 13:40:15.301792 [CA 2] Center 29 (0~58) winsize 59
724 13:40:15.301849 [CA 3] Center 24 (-3~52) winsize 56
725 13:40:15.301906 [CA 4] Center 25 (-3~54) winsize 58
726 13:40:15.301964 [CA 5] Center 29 (0~59) winsize 60
727 13:40:15.302020
728 13:40:15.302078 [CATrainingPosCal] consider 1 rank data
729 13:40:15.302135 u2DelayCellTimex100 = 735/100 ps
730 13:40:15.302193 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
731 13:40:15.302250 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
732 13:40:15.302307 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
733 13:40:15.302364 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
734 13:40:15.302422 CA4 delay=25 (-3~54),Diff = 1 PI (1 cell)
735 13:40:15.302480 CA5 delay=29 (0~59),Diff = 5 PI (6 cell)
736 13:40:15.302537
737 13:40:15.302593 CA PerBit enable=1, Macro0, CA PI delay=24
738 13:40:15.302651 === u2Vref_new: 0x5e --> 0x3d
739 13:40:15.302709
740 13:40:15.302765 Vref(ca) range 1: 30
741 13:40:15.302822
742 13:40:15.302879 CS Dly= 9 (40-0-32)
743 13:40:15.302936 Write Rank0 MR13 =0xd8
744 13:40:15.302994 Write Rank0 MR13 =0xd8
745 13:40:15.303050 Write Rank0 MR12 =0x5e
746 13:40:15.303107 Write Rank1 MR13 =0x59
747 13:40:15.303164 ==
748 13:40:15.303222 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
749 13:40:15.303467 fsp= 1, odt_onoff= 1, Byte mode= 0
750 13:40:15.303536 ==
751 13:40:15.303597 === u2Vref_new: 0x56 --> 0x2d
752 13:40:15.303655 === u2Vref_new: 0x58 --> 0x38
753 13:40:15.303714 === u2Vref_new: 0x5a --> 0x39
754 13:40:15.303772 === u2Vref_new: 0x5c --> 0x3c
755 13:40:15.303830 === u2Vref_new: 0x5e --> 0x3d
756 13:40:15.303887 === u2Vref_new: 0x60 --> 0xa0
757 13:40:15.303945 [CA 0] Center 35 (8~63) winsize 56
758 13:40:15.304003 [CA 1] Center 36 (9~63) winsize 55
759 13:40:15.304060 [CA 2] Center 31 (3~60) winsize 58
760 13:40:15.304118 [CA 3] Center 26 (-2~54) winsize 57
761 13:40:15.304175 [CA 4] Center 26 (-2~55) winsize 58
762 13:40:15.304233 [CA 5] Center 32 (3~61) winsize 59
763 13:40:15.304290
764 13:40:15.304348 [CATrainingPosCal] consider 2 rank data
765 13:40:15.304406 u2DelayCellTimex100 = 735/100 ps
766 13:40:15.304463 CA0 delay=35 (8~63),Diff = 10 PI (13 cell)
767 13:40:15.304521 CA1 delay=36 (9~63),Diff = 11 PI (14 cell)
768 13:40:15.304579 CA2 delay=30 (3~58),Diff = 5 PI (6 cell)
769 13:40:15.304636 CA3 delay=25 (-2~52),Diff = 0 PI (0 cell)
770 13:40:15.304693 CA4 delay=26 (-2~54),Diff = 1 PI (1 cell)
771 13:40:15.304751 CA5 delay=31 (3~59),Diff = 6 PI (7 cell)
772 13:40:15.304808
773 13:40:15.304865 CA PerBit enable=1, Macro0, CA PI delay=25
774 13:40:15.304923 === u2Vref_new: 0x60 --> 0xa0
775 13:40:15.304980
776 13:40:15.305037 Vref(ca) range 1: 32
777 13:40:15.305094
778 13:40:15.305150 CS Dly= 8 (39-0-32)
779 13:40:15.305208 Write Rank1 MR13 =0xd8
780 13:40:15.305265 Write Rank1 MR13 =0xd8
781 13:40:15.305322 Write Rank1 MR12 =0x60
782 13:40:15.305379 [RankSwap] Rank num 2, (Multi 1), Rank 0
783 13:40:15.305437 Write Rank0 MR2 =0xad
784 13:40:15.305493 [Write Leveling]
785 13:40:15.305551 delay byte0 byte1 byte2 byte3
786 13:40:15.305608
787 13:40:15.305665 10 0 0
788 13:40:15.305723 11 0 0
789 13:40:15.305781 12 0 0
790 13:40:15.305839 13 0 0
791 13:40:15.305899 14 0 0
792 13:40:15.305956 15 0 0
793 13:40:15.306015 16 0 0
794 13:40:15.306073 17 0 0
795 13:40:15.306131 18 0 0
796 13:40:15.306189 19 0 0
797 13:40:15.306247 20 0 0
798 13:40:15.306304 21 0 0
799 13:40:15.306362 22 0 0
800 13:40:15.306435 23 0 0
801 13:40:15.306497 24 0 ff
802 13:40:15.306555 25 0 ff
803 13:40:15.306613 26 0 ff
804 13:40:15.306671 27 0 ff
805 13:40:15.306729 28 0 ff
806 13:40:15.306786 29 0 ff
807 13:40:15.306845 30 0 ff
808 13:40:15.306904 31 0 ff
809 13:40:15.306962 32 0 ff
810 13:40:15.307020 33 ff ff
811 13:40:15.307079 34 ff ff
812 13:40:15.307137 35 ff ff
813 13:40:15.307195 36 ff ff
814 13:40:15.307253 37 ff ff
815 13:40:15.307312 38 ff ff
816 13:40:15.307369 39 ff ff
817 13:40:15.307444 pass bytecount = 0xff (0xff: all bytes pass)
818 13:40:15.307505
819 13:40:15.307563 DQS0 dly: 33
820 13:40:15.307620 DQS1 dly: 24
821 13:40:15.307678 Write Rank0 MR2 =0x2d
822 13:40:15.307735 [RankSwap] Rank num 2, (Multi 1), Rank 0
823 13:40:15.307794 Write Rank0 MR1 =0xd6
824 13:40:15.307850 [Gating]
825 13:40:15.307907 ==
826 13:40:15.307963 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
827 13:40:15.308021 fsp= 1, odt_onoff= 1, Byte mode= 0
828 13:40:15.308079 ==
829 13:40:15.308137 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
830 13:40:15.308196 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
831 13:40:15.308254 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
832 13:40:15.308312 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
833 13:40:15.308372 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
834 13:40:15.308430 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
835 13:40:15.308488 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
836 13:40:15.308547 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
837 13:40:15.308606 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
838 13:40:15.308665 3 2 4 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
839 13:40:15.308723 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
840 13:40:15.308782 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
841 13:40:15.308840 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
842 13:40:15.308898 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
843 13:40:15.308957 3 2 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
844 13:40:15.309016 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
845 13:40:15.309074 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
846 13:40:15.309133 3 3 4 |3534 1010 |(11 11)(11 11) |(0 0)(1 1)| 0
847 13:40:15.309192 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
848 13:40:15.309251 [Byte 1] Lead/lag falling Transition (3, 3, 8)
849 13:40:15.309309 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
850 13:40:15.309368 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
851 13:40:15.309426 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
852 13:40:15.309484 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
853 13:40:15.309542 3 3 28 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
854 13:40:15.309601 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
855 13:40:15.309660 3 4 4 |3d3d a09 |(11 11)(11 11) |(1 1)(1 1)| 0
856 13:40:15.309719 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
857 13:40:15.309777 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
858 13:40:15.309836 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
859 13:40:15.309895 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
860 13:40:15.309954 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 13:40:15.310012 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 13:40:15.310070 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 13:40:15.310129 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 13:40:15.310188 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 13:40:15.310246 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 13:40:15.310304 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
867 13:40:15.310363 [Byte 0] Lead/lag falling Transition (3, 5, 16)
868 13:40:15.310427 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
869 13:40:15.310486 [Byte 0] Lead/lag Transition tap number (2)
870 13:40:15.310543 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
871 13:40:15.310601 [Byte 1] Lead/lag falling Transition (3, 5, 24)
872 13:40:15.310659 3 5 28 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
873 13:40:15.310717 [Byte 0]First pass (3, 5, 28)
874 13:40:15.310984 [Byte 1] Lead/lag Transition tap number (2)
875 13:40:15.311050 3 6 0 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
876 13:40:15.311144 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
877 13:40:15.311241 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
878 13:40:15.311336 [Byte 1]First pass (3, 6, 8)
879 13:40:15.311439 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
880 13:40:15.311503 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
881 13:40:15.311563 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
882 13:40:15.311622 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
883 13:40:15.311682 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 13:40:15.311741 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 13:40:15.311799 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
886 13:40:15.311858 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
887 13:40:15.311917 All bytes gating window > 1UI, Early break!
888 13:40:15.311975
889 13:40:15.312032 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
890 13:40:15.312090
891 13:40:15.312148 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
892 13:40:15.312205
893 13:40:15.312261
894 13:40:15.312318
895 13:40:15.312376 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
896 13:40:15.312451
897 13:40:15.312511 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
898 13:40:15.312570
899 13:40:15.312627
900 13:40:15.312684 Write Rank0 MR1 =0x56
901 13:40:15.312741
902 13:40:15.312798 best RODT dly(2T, 0.5T) = (2, 2)
903 13:40:15.312855
904 13:40:15.312912 best RODT dly(2T, 0.5T) = (2, 2)
905 13:40:15.312969 ==
906 13:40:15.313027 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
907 13:40:15.313084 fsp= 1, odt_onoff= 1, Byte mode= 0
908 13:40:15.313142 ==
909 13:40:15.313199 Start DQ dly to find pass range UseTestEngine =0
910 13:40:15.313257 x-axis: bit #, y-axis: DQ dly (-127~63)
911 13:40:15.313315 RX Vref Scan = 0
912 13:40:15.313373 -26, [0] xxxxxxxx xxxxxxxx [MSB]
913 13:40:15.313431 -25, [0] xxxxxxxx xxxxxxxx [MSB]
914 13:40:15.313491 -24, [0] xxxxxxxx xxxxxxxx [MSB]
915 13:40:15.313549 -23, [0] xxxxxxxx xxxxxxxx [MSB]
916 13:40:15.313607 -22, [0] xxxxxxxx xxxxxxxx [MSB]
917 13:40:15.313666 -21, [0] xxxxxxxx xxxxxxxx [MSB]
918 13:40:15.313725 -20, [0] xxxxxxxx xxxxxxxx [MSB]
919 13:40:15.313784 -19, [0] xxxxxxxx xxxxxxxx [MSB]
920 13:40:15.313842 -18, [0] xxxxxxxx xxxxxxxx [MSB]
921 13:40:15.313902 -17, [0] xxxxxxxx xxxxxxxx [MSB]
922 13:40:15.313960 -16, [0] xxxxxxxx xxxxxxxx [MSB]
923 13:40:15.314018 -15, [0] xxxxxxxx xxxxxxxx [MSB]
924 13:40:15.314077 -14, [0] xxxxxxxx xxxxxxxx [MSB]
925 13:40:15.314135 -13, [0] xxxxxxxx xxxxxxxx [MSB]
926 13:40:15.314193 -12, [0] xxxxxxxx xxxxxxxx [MSB]
927 13:40:15.314252 -11, [0] xxxxxxxx xxxxxxxx [MSB]
928 13:40:15.314310 -10, [0] xxxxxxxx xxxxxxxx [MSB]
929 13:40:15.314369 -9, [0] xxxxxxxx xxxxxxxx [MSB]
930 13:40:15.314438 -8, [0] xxxxxxxx xxxxxxxx [MSB]
931 13:40:15.314498 -7, [0] xxxxxxxx xxxxxxxx [MSB]
932 13:40:15.314556 -6, [0] xxxxxxxx xxxxxxxx [MSB]
933 13:40:15.314615 -5, [0] xxxxxxxx xxxxxxxx [MSB]
934 13:40:15.314673 -4, [0] xxxxxxxx xxxxxxxx [MSB]
935 13:40:15.314732 -3, [0] xxxxxxxx xxxxxxxx [MSB]
936 13:40:15.314791 -2, [0] xxxoxxxx oxxxxxxx [MSB]
937 13:40:15.314850 -1, [0] xxxoxxxx ooxxxxxx [MSB]
938 13:40:15.314909 0, [0] xxxoxoxx ooxoxxxx [MSB]
939 13:40:15.314968 1, [0] xxxoxoox ooxoxoxx [MSB]
940 13:40:15.315026 2, [0] xxxoxoox ooxoooxx [MSB]
941 13:40:15.315084 3, [0] xxxoxoox ooxoooox [MSB]
942 13:40:15.315143 4, [0] xoxoxooo ooxooooo [MSB]
943 13:40:15.315205 5, [0] xooooooo ooxooooo [MSB]
944 13:40:15.315265 6, [0] oooooooo ooxooooo [MSB]
945 13:40:15.315323 7, [0] oooooooo ooxooooo [MSB]
946 13:40:15.315383 32, [0] oooxoooo oooooooo [MSB]
947 13:40:15.315461 33, [0] oooxoooo xooooooo [MSB]
948 13:40:15.315521 34, [0] oooxoooo xooooooo [MSB]
949 13:40:15.315580 35, [0] oooxoooo xooooooo [MSB]
950 13:40:15.315638 36, [0] oooxoxox xooxoooo [MSB]
951 13:40:15.315696 37, [0] oooxoxxx xxoxoooo [MSB]
952 13:40:15.315755 38, [0] oooxoxxx xxoxxoxo [MSB]
953 13:40:15.315813 39, [0] oooxxxxx xxoxxxxo [MSB]
954 13:40:15.315871 40, [0] xooxxxxx xxoxxxxo [MSB]
955 13:40:15.315928 41, [0] xxxxxxxx xxoxxxxo [MSB]
956 13:40:15.315986 42, [0] xxxxxxxx xxoxxxxx [MSB]
957 13:40:15.316044 43, [0] xxxxxxxx xxoxxxxx [MSB]
958 13:40:15.316103 44, [0] xxxxxxxx xxxxxxxx [MSB]
959 13:40:15.316162 iDelay=44, Bit 0, Center 22 (6 ~ 39) 34
960 13:40:15.316220 iDelay=44, Bit 1, Center 22 (4 ~ 40) 37
961 13:40:15.316277 iDelay=44, Bit 2, Center 22 (5 ~ 40) 36
962 13:40:15.316334 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
963 13:40:15.316391 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
964 13:40:15.316455 iDelay=44, Bit 5, Center 17 (0 ~ 35) 36
965 13:40:15.316513 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
966 13:40:15.316570 iDelay=44, Bit 7, Center 19 (4 ~ 35) 32
967 13:40:15.316628 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
968 13:40:15.316686 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
969 13:40:15.316743 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
970 13:40:15.316799 iDelay=44, Bit 11, Center 17 (0 ~ 35) 36
971 13:40:15.316856 iDelay=44, Bit 12, Center 19 (2 ~ 37) 36
972 13:40:15.316913 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
973 13:40:15.316970 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
974 13:40:15.317027 iDelay=44, Bit 15, Center 22 (4 ~ 41) 38
975 13:40:15.317084 ==
976 13:40:15.317142 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
977 13:40:15.317199 fsp= 1, odt_onoff= 1, Byte mode= 0
978 13:40:15.317256 ==
979 13:40:15.317314 DQS Delay:
980 13:40:15.317371 DQS0 = 0, DQS1 = 0
981 13:40:15.317428 DQM Delay:
982 13:40:15.317485 DQM0 = 19, DQM1 = 19
983 13:40:15.317542 DQ Delay:
984 13:40:15.317600 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
985 13:40:15.317657 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
986 13:40:15.317715 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =17
987 13:40:15.317772 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =22
988 13:40:15.317830
989 13:40:15.317886
990 13:40:15.317944 DramC Write-DBI off
991 13:40:15.318001 ==
992 13:40:15.318058 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
993 13:40:15.318116 fsp= 1, odt_onoff= 1, Byte mode= 0
994 13:40:15.318173 ==
995 13:40:15.318231 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
996 13:40:15.318288
997 13:40:15.318346 Begin, DQ Scan Range 920~1176
998 13:40:15.318409
999 13:40:15.318474
1000 13:40:15.318533 TX Vref Scan disable
1001 13:40:15.318591 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1002 13:40:15.318650 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1003 13:40:15.318709 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1004 13:40:15.318768 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1005 13:40:15.319022 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1006 13:40:15.319090 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1007 13:40:15.319151 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1008 13:40:15.319211 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1009 13:40:15.319270 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1010 13:40:15.319329 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1011 13:40:15.319387 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1012 13:40:15.319458 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1013 13:40:15.319518 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1014 13:40:15.319577 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1015 13:40:15.319635 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1016 13:40:15.319694 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1017 13:40:15.319764 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1018 13:40:15.319834 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1019 13:40:15.319894 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1020 13:40:15.319953 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1021 13:40:15.320013 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1022 13:40:15.320072 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1023 13:40:15.320131 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1024 13:40:15.320190 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1025 13:40:15.320256 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1026 13:40:15.320318 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1027 13:40:15.320379 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1028 13:40:15.320439 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1029 13:40:15.320498 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1030 13:40:15.320557 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1031 13:40:15.320615 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1032 13:40:15.320674 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1033 13:40:15.320731 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1034 13:40:15.320790 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1035 13:40:15.320848 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1036 13:40:15.320907 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1037 13:40:15.320965 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1038 13:40:15.321024 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1039 13:40:15.321082 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1040 13:40:15.321141 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1041 13:40:15.321200 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1042 13:40:15.321258 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1043 13:40:15.321317 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1044 13:40:15.321376 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1045 13:40:15.321435 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1046 13:40:15.321493 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1047 13:40:15.321551 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1048 13:40:15.321609 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1049 13:40:15.321667 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1050 13:40:15.321725 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1051 13:40:15.321784 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1052 13:40:15.321842 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1053 13:40:15.321901 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1054 13:40:15.321959 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1055 13:40:15.322017 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1056 13:40:15.322076 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1057 13:40:15.322134 976 |3 6 16|[0] xxxoxoox oooooooo [MSB]
1058 13:40:15.322192 977 |3 6 17|[0] xooooooo oooooooo [MSB]
1059 13:40:15.322250 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1060 13:40:15.322309 986 |3 6 26|[0] oooooooo xooooooo [MSB]
1061 13:40:15.322367 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1062 13:40:15.322425 988 |3 6 28|[0] oooooooo xxoxoooo [MSB]
1063 13:40:15.322484 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1064 13:40:15.322542 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1065 13:40:15.322599 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1066 13:40:15.322657 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1067 13:40:15.322715 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1068 13:40:15.322774 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1069 13:40:15.322832 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1070 13:40:15.322891 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1071 13:40:15.322949 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1072 13:40:15.323007 998 |3 6 38|[0] oooxoxxx xxxxxxxx [MSB]
1073 13:40:15.323066 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1074 13:40:15.323124 Byte0, DQ PI dly=986, DQM PI dly= 986
1075 13:40:15.323182 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1076 13:40:15.323239
1077 13:40:15.323296 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1078 13:40:15.323354
1079 13:40:15.323438 Byte1, DQ PI dly=977, DQM PI dly= 977
1080 13:40:15.323500 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1081 13:40:15.323558
1082 13:40:15.323615 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1083 13:40:15.323673
1084 13:40:15.323730 ==
1085 13:40:15.323787 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1086 13:40:15.323845 fsp= 1, odt_onoff= 1, Byte mode= 0
1087 13:40:15.323903 ==
1088 13:40:15.323960 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1089 13:40:15.324019
1090 13:40:15.324076 Begin, DQ Scan Range 953~1017
1091 13:40:15.324133 Write Rank0 MR14 =0x0
1092 13:40:15.324191
1093 13:40:15.324248 CH=0, VrefRange= 0, VrefLevel = 0
1094 13:40:15.324305 TX Bit0 (980~994) 15 987, Bit8 (967~978) 12 972,
1095 13:40:15.324364 TX Bit1 (978~993) 16 985, Bit9 (969~984) 16 976,
1096 13:40:15.324435 TX Bit2 (980~994) 15 987, Bit10 (975~988) 14 981,
1097 13:40:15.324533 TX Bit3 (976~987) 12 981, Bit11 (968~982) 15 975,
1098 13:40:15.324598 TX Bit4 (978~992) 15 985, Bit12 (971~983) 13 977,
1099 13:40:15.324658 TX Bit5 (976~991) 16 983, Bit13 (970~984) 15 977,
1100 13:40:15.324716 TX Bit6 (978~991) 14 984, Bit14 (969~984) 16 976,
1101 13:40:15.324775 TX Bit7 (978~992) 15 985, Bit15 (974~985) 12 979,
1102 13:40:15.324833
1103 13:40:15.324891 Write Rank0 MR14 =0x2
1104 13:40:15.324948
1105 13:40:15.325005 CH=0, VrefRange= 0, VrefLevel = 2
1106 13:40:15.325063 TX Bit0 (979~995) 17 987, Bit8 (967~980) 14 973,
1107 13:40:15.325121 TX Bit1 (978~994) 17 986, Bit9 (969~984) 16 976,
1108 13:40:15.325178 TX Bit2 (979~994) 16 986, Bit10 (975~988) 14 981,
1109 13:40:15.325236 TX Bit3 (975~987) 13 981, Bit11 (968~982) 15 975,
1110 13:40:15.325293 TX Bit4 (978~993) 16 985, Bit12 (970~984) 15 977,
1111 13:40:15.325549 TX Bit5 (976~992) 17 984, Bit13 (969~984) 16 976,
1112 13:40:15.325615 TX Bit6 (978~992) 15 985, Bit14 (969~985) 17 977,
1113 13:40:15.325674 TX Bit7 (978~992) 15 985, Bit15 (974~986) 13 980,
1114 13:40:15.325732
1115 13:40:15.325790 Write Rank0 MR14 =0x4
1116 13:40:15.325848
1117 13:40:15.325905 CH=0, VrefRange= 0, VrefLevel = 4
1118 13:40:15.325963 TX Bit0 (979~996) 18 987, Bit8 (967~981) 15 974,
1119 13:40:15.326022 TX Bit1 (978~994) 17 986, Bit9 (968~984) 17 976,
1120 13:40:15.326080 TX Bit2 (979~995) 17 987, Bit10 (975~989) 15 982,
1121 13:40:15.326138 TX Bit3 (975~989) 15 982, Bit11 (968~983) 16 975,
1122 13:40:15.326195 TX Bit4 (978~993) 16 985, Bit12 (970~984) 15 977,
1123 13:40:15.326253 TX Bit5 (976~992) 17 984, Bit13 (969~985) 17 977,
1124 13:40:15.326310 TX Bit6 (977~992) 16 984, Bit14 (969~986) 18 977,
1125 13:40:15.326368 TX Bit7 (978~993) 16 985, Bit15 (974~987) 14 980,
1126 13:40:15.326425
1127 13:40:15.326483 Write Rank0 MR14 =0x6
1128 13:40:15.326540
1129 13:40:15.326596 CH=0, VrefRange= 0, VrefLevel = 6
1130 13:40:15.326654 TX Bit0 (979~996) 18 987, Bit8 (967~982) 16 974,
1131 13:40:15.326713 TX Bit1 (978~995) 18 986, Bit9 (968~985) 18 976,
1132 13:40:15.326770 TX Bit2 (978~996) 19 987, Bit10 (974~989) 16 981,
1133 13:40:15.326828 TX Bit3 (975~990) 16 982, Bit11 (968~983) 16 975,
1134 13:40:15.326886 TX Bit4 (978~994) 17 986, Bit12 (970~985) 16 977,
1135 13:40:15.326943 TX Bit5 (976~992) 17 984, Bit13 (969~985) 17 977,
1136 13:40:15.327001 TX Bit6 (977~993) 17 985, Bit14 (968~986) 19 977,
1137 13:40:15.327058 TX Bit7 (978~994) 17 986, Bit15 (974~989) 16 981,
1138 13:40:15.327115
1139 13:40:15.327172 Write Rank0 MR14 =0x8
1140 13:40:15.327230
1141 13:40:15.327286 CH=0, VrefRange= 0, VrefLevel = 8
1142 13:40:15.327344 TX Bit0 (978~998) 21 988, Bit8 (967~982) 16 974,
1143 13:40:15.327401 TX Bit1 (977~995) 19 986, Bit9 (968~985) 18 976,
1144 13:40:15.327476 TX Bit2 (978~997) 20 987, Bit10 (974~990) 17 982,
1145 13:40:15.327534 TX Bit3 (974~991) 18 982, Bit11 (967~984) 18 975,
1146 13:40:15.327592 TX Bit4 (978~994) 17 986, Bit12 (969~985) 17 977,
1147 13:40:15.327650 TX Bit5 (976~993) 18 984, Bit13 (969~986) 18 977,
1148 13:40:15.327708 TX Bit6 (977~993) 17 985, Bit14 (968~987) 20 977,
1149 13:40:15.327765 TX Bit7 (978~994) 17 986, Bit15 (973~990) 18 981,
1150 13:40:15.327823
1151 13:40:15.327880 Write Rank0 MR14 =0xa
1152 13:40:15.327937
1153 13:40:15.327993 CH=0, VrefRange= 0, VrefLevel = 10
1154 13:40:15.328051 TX Bit0 (978~998) 21 988, Bit8 (966~983) 18 974,
1155 13:40:15.328129 TX Bit1 (977~996) 20 986, Bit9 (968~986) 19 977,
1156 13:40:15.328192 TX Bit2 (978~998) 21 988, Bit10 (974~991) 18 982,
1157 13:40:15.328251 TX Bit3 (974~991) 18 982, Bit11 (967~984) 18 975,
1158 13:40:15.328309 TX Bit4 (977~995) 19 986, Bit12 (969~986) 18 977,
1159 13:40:15.328367 TX Bit5 (975~993) 19 984, Bit13 (969~986) 18 977,
1160 13:40:15.328426 TX Bit6 (977~994) 18 985, Bit14 (968~988) 21 978,
1161 13:40:15.328484 TX Bit7 (977~995) 19 986, Bit15 (973~990) 18 981,
1162 13:40:15.328542
1163 13:40:15.328600 Write Rank0 MR14 =0xc
1164 13:40:15.328657
1165 13:40:15.328714 CH=0, VrefRange= 0, VrefLevel = 12
1166 13:40:15.328771 TX Bit0 (978~998) 21 988, Bit8 (966~983) 18 974,
1167 13:40:15.328829 TX Bit1 (977~996) 20 986, Bit9 (968~986) 19 977,
1168 13:40:15.328887 TX Bit2 (977~998) 22 987, Bit10 (974~991) 18 982,
1169 13:40:15.328944 TX Bit3 (974~992) 19 983, Bit11 (967~984) 18 975,
1170 13:40:15.329002 TX Bit4 (977~995) 19 986, Bit12 (968~987) 20 977,
1171 13:40:15.329059 TX Bit5 (975~994) 20 984, Bit13 (968~987) 20 977,
1172 13:40:15.329118 TX Bit6 (977~994) 18 985, Bit14 (968~988) 21 978,
1173 13:40:15.329176 TX Bit7 (978~996) 19 987, Bit15 (973~990) 18 981,
1174 13:40:15.329232
1175 13:40:15.329289 Write Rank0 MR14 =0xe
1176 13:40:15.329346
1177 13:40:15.329403 CH=0, VrefRange= 0, VrefLevel = 14
1178 13:40:15.329460 TX Bit0 (978~999) 22 988, Bit8 (966~984) 19 975,
1179 13:40:15.329518 TX Bit1 (977~998) 22 987, Bit9 (967~987) 21 977,
1180 13:40:15.329576 TX Bit2 (977~999) 23 988, Bit10 (973~991) 19 982,
1181 13:40:15.329634 TX Bit3 (973~992) 20 982, Bit11 (967~985) 19 976,
1182 13:40:15.329691 TX Bit4 (977~996) 20 986, Bit12 (968~987) 20 977,
1183 13:40:15.329749 TX Bit5 (975~994) 20 984, Bit13 (968~988) 21 978,
1184 13:40:15.329807 TX Bit6 (976~994) 19 985, Bit14 (968~989) 22 978,
1185 13:40:15.329864 TX Bit7 (977~996) 20 986, Bit15 (972~991) 20 981,
1186 13:40:15.329922
1187 13:40:15.329979 Write Rank0 MR14 =0x10
1188 13:40:15.330036
1189 13:40:15.330093 CH=0, VrefRange= 0, VrefLevel = 16
1190 13:40:15.330151 TX Bit0 (977~999) 23 988, Bit8 (966~984) 19 975,
1191 13:40:15.330210 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
1192 13:40:15.330268 TX Bit2 (977~999) 23 988, Bit10 (972~992) 21 982,
1193 13:40:15.330326 TX Bit3 (973~993) 21 983, Bit11 (967~986) 20 976,
1194 13:40:15.330384 TX Bit4 (977~997) 21 987, Bit12 (968~988) 21 978,
1195 13:40:15.330442 TX Bit5 (975~995) 21 985, Bit13 (968~989) 22 978,
1196 13:40:15.330500 TX Bit6 (976~996) 21 986, Bit14 (968~990) 23 979,
1197 13:40:15.330558 TX Bit7 (977~997) 21 987, Bit15 (972~991) 20 981,
1198 13:40:15.330616
1199 13:40:15.330673 Write Rank0 MR14 =0x12
1200 13:40:15.330729
1201 13:40:15.330786 CH=0, VrefRange= 0, VrefLevel = 18
1202 13:40:15.330842 TX Bit0 (977~999) 23 988, Bit8 (966~985) 20 975,
1203 13:40:15.330900 TX Bit1 (976~999) 24 987, Bit9 (967~988) 22 977,
1204 13:40:15.330958 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
1205 13:40:15.331015 TX Bit3 (972~993) 22 982, Bit11 (967~986) 20 976,
1206 13:40:15.331073 TX Bit4 (977~998) 22 987, Bit12 (968~989) 22 978,
1207 13:40:15.331131 TX Bit5 (974~995) 22 984, Bit13 (968~989) 22 978,
1208 13:40:15.331188 TX Bit6 (976~996) 21 986, Bit14 (967~990) 24 978,
1209 13:40:15.331246 TX Bit7 (977~998) 22 987, Bit15 (971~991) 21 981,
1210 13:40:15.331303
1211 13:40:15.331360 Write Rank0 MR14 =0x14
1212 13:40:15.331426
1213 13:40:15.331684 CH=0, VrefRange= 0, VrefLevel = 20
1214 13:40:15.331754 TX Bit0 (977~1000) 24 988, Bit8 (965~985) 21 975,
1215 13:40:15.331814 TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978,
1216 13:40:15.331873 TX Bit2 (977~999) 23 988, Bit10 (971~993) 23 982,
1217 13:40:15.331932 TX Bit3 (972~993) 22 982, Bit11 (966~987) 22 976,
1218 13:40:15.331990 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1219 13:40:15.332048 TX Bit5 (974~996) 23 985, Bit13 (968~989) 22 978,
1220 13:40:15.332106 TX Bit6 (976~997) 22 986, Bit14 (968~990) 23 979,
1221 13:40:15.332165 TX Bit7 (977~999) 23 988, Bit15 (971~992) 22 981,
1222 13:40:15.332222
1223 13:40:15.332280 Write Rank0 MR14 =0x16
1224 13:40:15.332338
1225 13:40:15.332394 CH=0, VrefRange= 0, VrefLevel = 22
1226 13:40:15.332452 TX Bit0 (977~1000) 24 988, Bit8 (965~986) 22 975,
1227 13:40:15.332510 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1228 13:40:15.332567 TX Bit2 (977~1000) 24 988, Bit10 (971~993) 23 982,
1229 13:40:15.332624 TX Bit3 (971~993) 23 982, Bit11 (966~988) 23 977,
1230 13:40:15.332682 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1231 13:40:15.332740 TX Bit5 (973~997) 25 985, Bit13 (968~990) 23 979,
1232 13:40:15.332797 TX Bit6 (975~998) 24 986, Bit14 (967~990) 24 978,
1233 13:40:15.332855 TX Bit7 (977~999) 23 988, Bit15 (970~992) 23 981,
1234 13:40:15.332913
1235 13:40:15.332969 Write Rank0 MR14 =0x18
1236 13:40:15.333026
1237 13:40:15.333083 CH=0, VrefRange= 0, VrefLevel = 24
1238 13:40:15.333141 TX Bit0 (977~1000) 24 988, Bit8 (965~986) 22 975,
1239 13:40:15.333199 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1240 13:40:15.333257 TX Bit2 (977~1000) 24 988, Bit10 (970~994) 25 982,
1241 13:40:15.333314 TX Bit3 (971~993) 23 982, Bit11 (966~988) 23 977,
1242 13:40:15.333372 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1243 13:40:15.333430 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1244 13:40:15.333487 TX Bit6 (975~998) 24 986, Bit14 (967~991) 25 979,
1245 13:40:15.333544 TX Bit7 (976~999) 24 987, Bit15 (970~993) 24 981,
1246 13:40:15.333602
1247 13:40:15.333659 Write Rank0 MR14 =0x1a
1248 13:40:15.333715
1249 13:40:15.333771 CH=0, VrefRange= 0, VrefLevel = 26
1250 13:40:15.333829 TX Bit0 (976~1000) 25 988, Bit8 (965~987) 23 976,
1251 13:40:15.333886 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1252 13:40:15.333944 TX Bit2 (976~1000) 25 988, Bit10 (970~993) 24 981,
1253 13:40:15.334001 TX Bit3 (970~994) 25 982, Bit11 (966~989) 24 977,
1254 13:40:15.334058 TX Bit4 (976~999) 24 987, Bit12 (967~990) 24 978,
1255 13:40:15.334115 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1256 13:40:15.334172 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1257 13:40:15.334230 TX Bit7 (977~1000) 24 988, Bit15 (969~993) 25 981,
1258 13:40:15.334287
1259 13:40:15.334345 Write Rank0 MR14 =0x1c
1260 13:40:15.334402
1261 13:40:15.334459 CH=0, VrefRange= 0, VrefLevel = 28
1262 13:40:15.334516 TX Bit0 (977~1001) 25 989, Bit8 (964~987) 24 975,
1263 13:40:15.334573 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1264 13:40:15.334631 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
1265 13:40:15.334688 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1266 13:40:15.334746 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1267 13:40:15.334803 TX Bit5 (972~998) 27 985, Bit13 (967~991) 25 979,
1268 13:40:15.334861 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1269 13:40:15.334918 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1270 13:40:15.334975
1271 13:40:15.335031 Write Rank0 MR14 =0x1e
1272 13:40:15.335088
1273 13:40:15.335145 CH=0, VrefRange= 0, VrefLevel = 30
1274 13:40:15.335202 TX Bit0 (977~1001) 25 989, Bit8 (964~987) 24 975,
1275 13:40:15.335259 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1276 13:40:15.335317 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
1277 13:40:15.335374 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1278 13:40:15.335444 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1279 13:40:15.335502 TX Bit5 (972~998) 27 985, Bit13 (967~991) 25 979,
1280 13:40:15.335560 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1281 13:40:15.335618 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1282 13:40:15.335676
1283 13:40:15.335732 Write Rank0 MR14 =0x20
1284 13:40:15.335790
1285 13:40:15.335846 CH=0, VrefRange= 0, VrefLevel = 32
1286 13:40:15.335904 TX Bit0 (977~1001) 25 989, Bit8 (964~987) 24 975,
1287 13:40:15.335962 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1288 13:40:15.336019 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
1289 13:40:15.336077 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1290 13:40:15.336135 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1291 13:40:15.336192 TX Bit5 (972~998) 27 985, Bit13 (967~991) 25 979,
1292 13:40:15.336249 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1293 13:40:15.336308 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1294 13:40:15.336365
1295 13:40:15.336422 Write Rank0 MR14 =0x22
1296 13:40:15.336500
1297 13:40:15.336558 CH=0, VrefRange= 0, VrefLevel = 34
1298 13:40:15.336616 TX Bit0 (977~1001) 25 989, Bit8 (964~987) 24 975,
1299 13:40:15.336674 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1300 13:40:15.336731 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
1301 13:40:15.336789 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1302 13:40:15.336846 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1303 13:40:15.336907 TX Bit5 (972~998) 27 985, Bit13 (967~991) 25 979,
1304 13:40:15.336964 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1305 13:40:15.337020 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1306 13:40:15.337077
1307 13:40:15.337134 Write Rank0 MR14 =0x24
1308 13:40:15.337190
1309 13:40:15.337246 CH=0, VrefRange= 0, VrefLevel = 36
1310 13:40:15.337303 TX Bit0 (977~1001) 25 989, Bit8 (964~987) 24 975,
1311 13:40:15.337360 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1312 13:40:15.337613 TX Bit2 (976~1001) 26 988, Bit10 (970~994) 25 982,
1313 13:40:15.337683 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1314 13:40:15.337742 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1315 13:40:15.337799 TX Bit5 (972~998) 27 985, Bit13 (967~991) 25 979,
1316 13:40:15.337857 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1317 13:40:15.337915 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1318 13:40:15.337971
1319 13:40:15.338028
1320 13:40:15.338084 TX Vref found, early break! 370< 381
1321 13:40:15.338141 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1322 13:40:15.338198 u1DelayCellOfst[0]=9 cells (7 PI)
1323 13:40:15.338283 u1DelayCellOfst[1]=7 cells (6 PI)
1324 13:40:15.338376 u1DelayCellOfst[2]=7 cells (6 PI)
1325 13:40:15.338469 u1DelayCellOfst[3]=0 cells (0 PI)
1326 13:40:15.338533 u1DelayCellOfst[4]=7 cells (6 PI)
1327 13:40:15.338591 u1DelayCellOfst[5]=3 cells (3 PI)
1328 13:40:15.338648 u1DelayCellOfst[6]=6 cells (5 PI)
1329 13:40:15.338705 u1DelayCellOfst[7]=7 cells (6 PI)
1330 13:40:15.338763 Byte0, DQ PI dly=982, DQM PI dly= 985
1331 13:40:15.338822 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1332 13:40:15.338880
1333 13:40:15.338937 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1334 13:40:15.338994
1335 13:40:15.339050 u1DelayCellOfst[8]=0 cells (0 PI)
1336 13:40:15.339106 u1DelayCellOfst[9]=3 cells (3 PI)
1337 13:40:15.339163 u1DelayCellOfst[10]=9 cells (7 PI)
1338 13:40:15.339219 u1DelayCellOfst[11]=2 cells (2 PI)
1339 13:40:15.339276 u1DelayCellOfst[12]=5 cells (4 PI)
1340 13:40:15.339331 u1DelayCellOfst[13]=5 cells (4 PI)
1341 13:40:15.339388 u1DelayCellOfst[14]=5 cells (4 PI)
1342 13:40:15.339461 u1DelayCellOfst[15]=7 cells (6 PI)
1343 13:40:15.339519 Byte1, DQ PI dly=975, DQM PI dly= 978
1344 13:40:15.339576 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1345 13:40:15.339633
1346 13:40:15.339690 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1347 13:40:15.339747
1348 13:40:15.339804 Write Rank0 MR14 =0x1c
1349 13:40:15.339860
1350 13:40:15.339917 Final TX Range 0 Vref 28
1351 13:40:15.339976
1352 13:40:15.340041 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1353 13:40:15.340098
1354 13:40:15.340155 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1355 13:40:15.340212 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1356 13:40:15.340269 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1357 13:40:15.340326 Write Rank0 MR3 =0xb0
1358 13:40:15.340383 DramC Write-DBI on
1359 13:40:15.340439 ==
1360 13:40:15.340496 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1361 13:40:15.340553 fsp= 1, odt_onoff= 1, Byte mode= 0
1362 13:40:15.340610 ==
1363 13:40:15.340667 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1364 13:40:15.340724
1365 13:40:15.340781 Begin, DQ Scan Range 698~762
1366 13:40:15.340837
1367 13:40:15.340893
1368 13:40:15.340949 TX Vref Scan disable
1369 13:40:15.341006 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1370 13:40:15.341065 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1371 13:40:15.341124 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1372 13:40:15.341182 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1373 13:40:15.341240 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1374 13:40:15.341297 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1375 13:40:15.341355 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1376 13:40:15.341413 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1377 13:40:15.341470 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1378 13:40:15.341528 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1379 13:40:15.341586 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1380 13:40:15.341644 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1381 13:40:15.341701 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1382 13:40:15.341758 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1383 13:40:15.341815 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1384 13:40:15.341873 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1385 13:40:15.341931 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1386 13:40:15.341988 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1387 13:40:15.342046 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1388 13:40:15.342104 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1389 13:40:15.342161 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1390 13:40:15.342219 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1391 13:40:15.342277 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1392 13:40:15.342334 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1393 13:40:15.342393 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1394 13:40:15.342450 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1395 13:40:15.342508 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1396 13:40:15.342566 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1397 13:40:15.342624 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1398 13:40:15.342681 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1399 13:40:15.342754 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1400 13:40:15.342850 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1401 13:40:15.342946 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1402 13:40:15.343019 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1403 13:40:15.343079 Byte0, DQ PI dly=732, DQM PI dly= 732
1404 13:40:15.343137 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1405 13:40:15.343194
1406 13:40:15.343251 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1407 13:40:15.343308
1408 13:40:15.343365 Byte1, DQ PI dly=722, DQM PI dly= 722
1409 13:40:15.343430 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
1410 13:40:15.343489
1411 13:40:15.343546 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
1412 13:40:15.343604
1413 13:40:15.343661 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1414 13:40:15.343718 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1415 13:40:15.343775 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1416 13:40:15.343832 Write Rank0 MR3 =0x30
1417 13:40:15.343889 DramC Write-DBI off
1418 13:40:15.343945
1419 13:40:15.344003 [DATLAT]
1420 13:40:15.344064 Freq=1600, CH0 RK0, use_rxtx_scan=0
1421 13:40:15.344129
1422 13:40:15.344192 DATLAT Default: 0xf
1423 13:40:15.344260 7, 0xFFFF, sum=0
1424 13:40:15.344319 8, 0xFFFF, sum=0
1425 13:40:15.344377 9, 0xFFFF, sum=0
1426 13:40:15.344439 10, 0xFFFF, sum=0
1427 13:40:15.344497 11, 0xFFFF, sum=0
1428 13:40:15.344555 12, 0xFFFF, sum=0
1429 13:40:15.344617 13, 0xFFFF, sum=0
1430 13:40:15.344675 14, 0x0, sum=1
1431 13:40:15.344733 15, 0x0, sum=2
1432 13:40:15.344794 16, 0x0, sum=3
1433 13:40:15.344852 17, 0x0, sum=4
1434 13:40:15.345123 pattern=2 first_step=14 total pass=5 best_step=16
1435 13:40:15.345191 ==
1436 13:40:15.345251 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1437 13:40:15.345309 fsp= 1, odt_onoff= 1, Byte mode= 0
1438 13:40:15.345366 ==
1439 13:40:15.345424 Start DQ dly to find pass range UseTestEngine =1
1440 13:40:15.345482 x-axis: bit #, y-axis: DQ dly (-127~63)
1441 13:40:15.345539 RX Vref Scan = 1
1442 13:40:15.345596
1443 13:40:15.345653 RX Vref found, early break!
1444 13:40:15.345709
1445 13:40:15.345765 Final RX Vref 12, apply to both rank0 and 1
1446 13:40:15.345822 ==
1447 13:40:15.345879 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1448 13:40:15.345936 fsp= 1, odt_onoff= 1, Byte mode= 0
1449 13:40:15.345993 ==
1450 13:40:15.346050 DQS Delay:
1451 13:40:15.346108 DQS0 = 0, DQS1 = 0
1452 13:40:15.346164 DQM Delay:
1453 13:40:15.346220 DQM0 = 19, DQM1 = 18
1454 13:40:15.346276 DQ Delay:
1455 13:40:15.346332 DQ0 =22, DQ1 =21, DQ2 =21, DQ3 =15
1456 13:40:15.346389 DQ4 =21, DQ5 =17, DQ6 =19, DQ7 =20
1457 13:40:15.346446 DQ8 =14, DQ9 =16, DQ10 =25, DQ11 =16
1458 13:40:15.346502 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =21
1459 13:40:15.346559
1460 13:40:15.346615
1461 13:40:15.346671
1462 13:40:15.346761 [DramC_TX_OE_Calibration] TA2
1463 13:40:15.346853 Original DQ_B0 (3 6) =30, OEN = 27
1464 13:40:15.346946 Original DQ_B1 (3 6) =30, OEN = 27
1465 13:40:15.347008 23, 0x0, End_B0=23 End_B1=23
1466 13:40:15.347067 24, 0x0, End_B0=24 End_B1=24
1467 13:40:15.347126 25, 0x0, End_B0=25 End_B1=25
1468 13:40:15.347183 26, 0x0, End_B0=26 End_B1=26
1469 13:40:15.347242 27, 0x0, End_B0=27 End_B1=27
1470 13:40:15.347299 28, 0x0, End_B0=28 End_B1=28
1471 13:40:15.347357 29, 0x0, End_B0=29 End_B1=29
1472 13:40:15.347428 30, 0x0, End_B0=30 End_B1=30
1473 13:40:15.347490 31, 0xFFFF, End_B0=30 End_B1=30
1474 13:40:15.347548 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1475 13:40:15.347607 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1476 13:40:15.347664
1477 13:40:15.347721
1478 13:40:15.347777 Write Rank0 MR23 =0x3f
1479 13:40:15.347834 [DQSOSC]
1480 13:40:15.347891 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1481 13:40:15.347950 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=15, DEC=23
1482 13:40:15.348007 Write Rank0 MR23 =0x3f
1483 13:40:15.348064 [DQSOSC]
1484 13:40:15.348121 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1485 13:40:15.348178 CH0 RK0: MR19=303, MR18=1010
1486 13:40:15.348234 [RankSwap] Rank num 2, (Multi 1), Rank 1
1487 13:40:15.348290 Write Rank0 MR2 =0xad
1488 13:40:15.348346 [Write Leveling]
1489 13:40:15.348402 delay byte0 byte1 byte2 byte3
1490 13:40:15.348458
1491 13:40:15.348516 10 0 0
1492 13:40:15.348575 11 0 0
1493 13:40:15.348633 12 0 0
1494 13:40:15.348691 13 0 0
1495 13:40:15.348747 14 0 0
1496 13:40:15.348805 15 0 0
1497 13:40:15.348863 16 0 0
1498 13:40:15.348919 17 0 0
1499 13:40:15.348977 18 0 0
1500 13:40:15.349034 19 0 0
1501 13:40:15.349092 20 0 0
1502 13:40:15.349148 21 0 0
1503 13:40:15.349206 22 0 0
1504 13:40:15.349263 23 0 0
1505 13:40:15.349320 24 0 ff
1506 13:40:15.349377 25 0 ff
1507 13:40:15.349434 26 ff ff
1508 13:40:15.349492 27 ff ff
1509 13:40:15.349549 28 ff ff
1510 13:40:15.349606 29 ff ff
1511 13:40:15.349663 30 ff ff
1512 13:40:15.349720 31 ff ff
1513 13:40:15.349778 32 ff ff
1514 13:40:15.349835 pass bytecount = 0xff (0xff: all bytes pass)
1515 13:40:15.349892
1516 13:40:15.349949 DQS0 dly: 26
1517 13:40:15.350007 DQS1 dly: 24
1518 13:40:15.350062 Write Rank0 MR2 =0x2d
1519 13:40:15.350119 [RankSwap] Rank num 2, (Multi 1), Rank 0
1520 13:40:15.350176 Write Rank1 MR1 =0xd6
1521 13:40:15.350232 [Gating]
1522 13:40:15.350288 ==
1523 13:40:15.350345 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1524 13:40:15.350403 fsp= 1, odt_onoff= 1, Byte mode= 0
1525 13:40:15.350460 ==
1526 13:40:15.350517 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1527 13:40:15.350576 3 1 4 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1528 13:40:15.350656 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1529 13:40:15.350751 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1530 13:40:15.350848 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1531 13:40:15.350915 3 1 20 |2c2c 3534 |(0 0)(11 11) |(1 0)(0 1)| 0
1532 13:40:15.350975 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1533 13:40:15.351034 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1534 13:40:15.351093 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1535 13:40:15.351152 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1536 13:40:15.351210 3 2 8 |2c2c 3534 |(11 10)(11 11) |(0 0)(0 1)| 0
1537 13:40:15.351268 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1538 13:40:15.351327 3 2 16 |3534 1a1a |(11 11)(11 11) |(0 0)(1 1)| 0
1539 13:40:15.351385 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1540 13:40:15.351453 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1541 13:40:15.351513 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1542 13:40:15.351571 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1543 13:40:15.351630 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1544 13:40:15.351688 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1545 13:40:15.351745 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1546 13:40:15.351803 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1547 13:40:15.351861 3 3 20 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
1548 13:40:15.351919 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1549 13:40:15.351976 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1550 13:40:15.352034 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1551 13:40:15.352091 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1552 13:40:15.352149 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1553 13:40:15.352207 3 4 8 |b0a 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1554 13:40:15.352265 3 4 12 |3d3d 3534 |(10 10)(11 11) |(1 1)(1 1)| 0
1555 13:40:15.352323 3 4 16 |3d3d 1c1c |(11 11)(11 11) |(1 1)(1 1)| 0
1556 13:40:15.352381 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1557 13:40:15.352439 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1558 13:40:15.352496 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1559 13:40:15.352555 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1560 13:40:15.352613 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1561 13:40:15.352869 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1562 13:40:15.352938 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1563 13:40:15.352998 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1564 13:40:15.353056 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1565 13:40:15.353114 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1566 13:40:15.353172 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1567 13:40:15.353231 [Byte 0] Lead/lag falling Transition (3, 5, 28)
1568 13:40:15.353288 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1569 13:40:15.353346 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1570 13:40:15.353404 [Byte 0] Lead/lag Transition tap number (3)
1571 13:40:15.353466 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1572 13:40:15.353538 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1573 13:40:15.353597 [Byte 1] Lead/lag Transition tap number (2)
1574 13:40:15.353654 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
1575 13:40:15.353712 [Byte 0]First pass (3, 6, 12)
1576 13:40:15.353768 3 6 16 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
1577 13:40:15.353826 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1578 13:40:15.353884 [Byte 1]First pass (3, 6, 20)
1579 13:40:15.353941 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1580 13:40:15.353998 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1581 13:40:15.354056 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1582 13:40:15.354114 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1583 13:40:15.354172 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1584 13:40:15.354229 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1585 13:40:15.354291 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1586 13:40:15.354349 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1587 13:40:15.354406 All bytes gating window > 1UI, Early break!
1588 13:40:15.354477
1589 13:40:15.354537 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 2)
1590 13:40:15.354595
1591 13:40:15.354656 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1592 13:40:15.354714
1593 13:40:15.354771
1594 13:40:15.354833
1595 13:40:15.354892 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 2)
1596 13:40:15.354949
1597 13:40:15.355015 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1598 13:40:15.355108
1599 13:40:15.355208
1600 13:40:15.355303 Write Rank1 MR1 =0x56
1601 13:40:15.355401
1602 13:40:15.355501 best RODT dly(2T, 0.5T) = (2, 3)
1603 13:40:15.355594
1604 13:40:15.355684 best RODT dly(2T, 0.5T) = (2, 3)
1605 13:40:15.355763 ==
1606 13:40:15.355823 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1607 13:40:15.355882 fsp= 1, odt_onoff= 1, Byte mode= 0
1608 13:40:15.355940 ==
1609 13:40:15.355998 Start DQ dly to find pass range UseTestEngine =0
1610 13:40:15.356055 x-axis: bit #, y-axis: DQ dly (-127~63)
1611 13:40:15.356112 RX Vref Scan = 0
1612 13:40:15.356169 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1613 13:40:15.356227 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1614 13:40:15.356285 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1615 13:40:15.356342 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1616 13:40:15.356400 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1617 13:40:15.356458 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1618 13:40:15.356516 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1619 13:40:15.356573 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1620 13:40:15.356630 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1621 13:40:15.356688 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1622 13:40:15.356745 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1623 13:40:15.356802 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1624 13:40:15.356860 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1625 13:40:15.356917 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1626 13:40:15.356974 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1627 13:40:15.357031 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1628 13:40:15.357088 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1629 13:40:15.357146 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1630 13:40:15.357203 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1631 13:40:15.357262 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1632 13:40:15.357319 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1633 13:40:15.357377 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1634 13:40:15.357434 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1635 13:40:15.357492 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1636 13:40:15.357549 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1637 13:40:15.357606 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1638 13:40:15.357663 0, [0] xxxoxoxx oxxoxxxx [MSB]
1639 13:40:15.357722 1, [0] xxxoxoox ooxoooxx [MSB]
1640 13:40:15.357780 2, [0] xxxoxooo ooxoooxx [MSB]
1641 13:40:15.357837 3, [0] xoxooooo ooxoooox [MSB]
1642 13:40:15.357894 4, [0] oooooooo ooxoooox [MSB]
1643 13:40:15.357952 5, [0] oooooooo ooxooooo [MSB]
1644 13:40:15.358009 6, [0] oooooooo ooxooooo [MSB]
1645 13:40:15.358066 33, [0] oooooooo xooooooo [MSB]
1646 13:40:15.358125 34, [0] oooxoooo xooooooo [MSB]
1647 13:40:15.358182 35, [0] oooxoooo xooooooo [MSB]
1648 13:40:15.358243 36, [0] oooxoooo xooxoooo [MSB]
1649 13:40:15.358301 37, [0] oooxoxoo xxoxoxoo [MSB]
1650 13:40:15.358358 38, [0] oooxoxoo xxoxoxxo [MSB]
1651 13:40:15.358415 39, [0] oooxoxxx xxoxxxxo [MSB]
1652 13:40:15.358473 40, [0] oooxoxxx xxoxxxxo [MSB]
1653 13:40:15.358530 41, [0] oxxxoxxx xxoxxxxx [MSB]
1654 13:40:15.358588 42, [0] oxxxxxxx xxoxxxxx [MSB]
1655 13:40:15.358646 43, [0] xxxxxxxx xxoxxxxx [MSB]
1656 13:40:15.358703 44, [0] xxxxxxxx xxoxxxxx [MSB]
1657 13:40:15.358760 45, [0] xxxxxxxx xxxxxxxx [MSB]
1658 13:40:15.358818 iDelay=45, Bit 0, Center 23 (4 ~ 42) 39
1659 13:40:15.358874 iDelay=45, Bit 1, Center 21 (3 ~ 40) 38
1660 13:40:15.358930 iDelay=45, Bit 2, Center 22 (4 ~ 40) 37
1661 13:40:15.358987 iDelay=45, Bit 3, Center 15 (-2 ~ 33) 36
1662 13:40:15.359050 iDelay=45, Bit 4, Center 22 (3 ~ 41) 39
1663 13:40:15.359146 iDelay=45, Bit 5, Center 18 (0 ~ 36) 37
1664 13:40:15.359240 iDelay=45, Bit 6, Center 19 (1 ~ 38) 38
1665 13:40:15.359337 iDelay=45, Bit 7, Center 20 (2 ~ 38) 37
1666 13:40:15.359431 iDelay=45, Bit 8, Center 15 (-2 ~ 32) 35
1667 13:40:15.359493 iDelay=45, Bit 9, Center 18 (1 ~ 36) 36
1668 13:40:15.359551 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1669 13:40:15.359608 iDelay=45, Bit 11, Center 16 (-2 ~ 35) 38
1670 13:40:15.359665 iDelay=45, Bit 12, Center 19 (1 ~ 38) 38
1671 13:40:15.359721 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1672 13:40:15.359778 iDelay=45, Bit 14, Center 20 (3 ~ 37) 35
1673 13:40:15.359834 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1674 13:40:15.359890 ==
1675 13:40:15.359947 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1676 13:40:15.360004 fsp= 1, odt_onoff= 1, Byte mode= 0
1677 13:40:15.360061 ==
1678 13:40:15.360118 DQS Delay:
1679 13:40:15.360174 DQS0 = 0, DQS1 = 0
1680 13:40:15.360231 DQM Delay:
1681 13:40:15.360287 DQM0 = 20, DQM1 = 19
1682 13:40:15.360344 DQ Delay:
1683 13:40:15.360595 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =15
1684 13:40:15.360661 DQ4 =22, DQ5 =18, DQ6 =19, DQ7 =20
1685 13:40:15.360719 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
1686 13:40:15.360776 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1687 13:40:15.360833
1688 13:40:15.360890
1689 13:40:15.360947 DramC Write-DBI off
1690 13:40:15.361003 ==
1691 13:40:15.361061 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1692 13:40:15.361117 fsp= 1, odt_onoff= 1, Byte mode= 0
1693 13:40:15.361182 ==
1694 13:40:15.361250 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1695 13:40:15.361308
1696 13:40:15.361364 Begin, DQ Scan Range 920~1176
1697 13:40:15.361421
1698 13:40:15.361477
1699 13:40:15.361533 TX Vref Scan disable
1700 13:40:15.361590 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1701 13:40:15.361648 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1702 13:40:15.361707 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1703 13:40:15.361765 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1704 13:40:15.361822 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1705 13:40:15.361880 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1706 13:40:15.361938 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1707 13:40:15.361996 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1708 13:40:15.362053 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1709 13:40:15.362111 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1710 13:40:15.362169 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1711 13:40:15.362227 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1712 13:40:15.362284 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1713 13:40:15.362342 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1714 13:40:15.362400 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1715 13:40:15.362457 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1716 13:40:15.362515 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1717 13:40:15.362572 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1718 13:40:15.362630 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1719 13:40:15.362687 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1720 13:40:15.362745 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1721 13:40:15.362802 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1722 13:40:15.362859 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1723 13:40:15.362918 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1724 13:40:15.362976 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1725 13:40:15.363033 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1726 13:40:15.363091 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1727 13:40:15.363149 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1728 13:40:15.363207 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1729 13:40:15.363264 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1730 13:40:15.363322 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1731 13:40:15.363380 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1732 13:40:15.363453 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1733 13:40:15.363511 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1734 13:40:15.363570 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1735 13:40:15.363649 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1736 13:40:15.363744 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1737 13:40:15.363842 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1738 13:40:15.363907 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1739 13:40:15.363966 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1740 13:40:15.364024 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1741 13:40:15.364083 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1742 13:40:15.364141 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1743 13:40:15.364199 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1744 13:40:15.364257 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1745 13:40:15.364315 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1746 13:40:15.364373 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1747 13:40:15.364431 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1748 13:40:15.364489 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1749 13:40:15.364549 969 |3 6 9|[0] xxxxxxxx ooxoxxxx [MSB]
1750 13:40:15.364608 970 |3 6 10|[0] xxxxxxxx ooxooxox [MSB]
1751 13:40:15.364666 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1752 13:40:15.364732 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1753 13:40:15.364827 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1754 13:40:15.364924 974 |3 6 14|[0] xxxooooo ooxooooo [MSB]
1755 13:40:15.365017 975 |3 6 15|[0] xoxooooo oooooooo [MSB]
1756 13:40:15.365113 988 |3 6 28|[0] oooooooo xooooooo [MSB]
1757 13:40:15.365175 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1758 13:40:15.365234 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1759 13:40:15.365297 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1760 13:40:15.365356 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1761 13:40:15.365415 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1762 13:40:15.365483 Byte0, DQ PI dly=982, DQM PI dly= 982
1763 13:40:15.365574 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1764 13:40:15.365661
1765 13:40:15.365720 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1766 13:40:15.365778
1767 13:40:15.365845 Byte1, DQ PI dly=979, DQM PI dly= 979
1768 13:40:15.365937 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1769 13:40:15.366028
1770 13:40:15.366119 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1771 13:40:15.366205
1772 13:40:15.366264 ==
1773 13:40:15.366322 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1774 13:40:15.366380 fsp= 1, odt_onoff= 1, Byte mode= 0
1775 13:40:15.366438 ==
1776 13:40:15.366494 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1777 13:40:15.366551
1778 13:40:15.366608 Begin, DQ Scan Range 955~1019
1779 13:40:15.366665 Write Rank1 MR14 =0x0
1780 13:40:15.366721
1781 13:40:15.366777 CH=0, VrefRange= 0, VrefLevel = 0
1782 13:40:15.366834 TX Bit0 (977~991) 15 984, Bit8 (970~982) 13 976,
1783 13:40:15.366891 TX Bit1 (976~987) 12 981, Bit9 (971~985) 15 978,
1784 13:40:15.366948 TX Bit2 (977~990) 14 983, Bit10 (977~989) 13 983,
1785 13:40:15.367005 TX Bit3 (971~983) 13 977, Bit11 (971~983) 13 977,
1786 13:40:15.367063 TX Bit4 (976~989) 14 982, Bit12 (973~985) 13 979,
1787 13:40:15.367120 TX Bit5 (973~985) 13 979, Bit13 (975~983) 9 979,
1788 13:40:15.367177 TX Bit6 (975~988) 14 981, Bit14 (974~985) 12 979,
1789 13:40:15.367234 TX Bit7 (976~989) 14 982, Bit15 (976~989) 14 982,
1790 13:40:15.367291
1791 13:40:15.367347 Write Rank1 MR14 =0x2
1792 13:40:15.367422
1793 13:40:15.367490 CH=0, VrefRange= 0, VrefLevel = 2
1794 13:40:15.367548 TX Bit0 (977~991) 15 984, Bit8 (969~983) 15 976,
1795 13:40:15.367605 TX Bit1 (977~988) 12 982, Bit9 (971~985) 15 978,
1796 13:40:15.367663 TX Bit2 (977~990) 14 983, Bit10 (976~990) 15 983,
1797 13:40:15.367915 TX Bit3 (970~983) 14 976, Bit11 (971~983) 13 977,
1798 13:40:15.367982 TX Bit4 (976~990) 15 983, Bit12 (973~985) 13 979,
1799 13:40:15.368042 TX Bit5 (973~987) 15 980, Bit13 (974~983) 10 978,
1800 13:40:15.368100 TX Bit6 (974~989) 16 981, Bit14 (974~986) 13 980,
1801 13:40:15.368157 TX Bit7 (975~990) 16 982, Bit15 (975~990) 16 982,
1802 13:40:15.368214
1803 13:40:15.368270 Write Rank1 MR14 =0x4
1804 13:40:15.368327
1805 13:40:15.368403 CH=0, VrefRange= 0, VrefLevel = 4
1806 13:40:15.368495 TX Bit0 (977~992) 16 984, Bit8 (969~983) 15 976,
1807 13:40:15.368592 TX Bit1 (976~989) 14 982, Bit9 (971~986) 16 978,
1808 13:40:15.368660 TX Bit2 (977~991) 15 984, Bit10 (976~990) 15 983,
1809 13:40:15.368718 TX Bit3 (970~984) 15 977, Bit11 (969~984) 16 976,
1810 13:40:15.368776 TX Bit4 (975~990) 16 982, Bit12 (972~986) 15 979,
1811 13:40:15.368833 TX Bit5 (972~987) 16 979, Bit13 (974~984) 11 979,
1812 13:40:15.368891 TX Bit6 (974~989) 16 981, Bit14 (973~986) 14 979,
1813 13:40:15.368947 TX Bit7 (975~991) 17 983, Bit15 (975~990) 16 982,
1814 13:40:15.369004
1815 13:40:15.369077 Write Rank1 MR14 =0x6
1816 13:40:15.369138
1817 13:40:15.369195 CH=0, VrefRange= 0, VrefLevel = 6
1818 13:40:15.369252 TX Bit0 (977~992) 16 984, Bit8 (969~984) 16 976,
1819 13:40:15.369310 TX Bit1 (976~990) 15 983, Bit9 (971~987) 17 979,
1820 13:40:15.369367 TX Bit2 (977~991) 15 984, Bit10 (976~991) 16 983,
1821 13:40:15.369425 TX Bit3 (970~985) 16 977, Bit11 (969~984) 16 976,
1822 13:40:15.369493 TX Bit4 (975~991) 17 983, Bit12 (972~987) 16 979,
1823 13:40:15.369551 TX Bit5 (971~989) 19 980, Bit13 (973~985) 13 979,
1824 13:40:15.369609 TX Bit6 (973~990) 18 981, Bit14 (973~988) 16 980,
1825 13:40:15.369666 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1826 13:40:15.369723
1827 13:40:15.369779 Write Rank1 MR14 =0x8
1828 13:40:15.369835
1829 13:40:15.369892 CH=0, VrefRange= 0, VrefLevel = 8
1830 13:40:15.369948 TX Bit0 (976~992) 17 984, Bit8 (969~984) 16 976,
1831 13:40:15.370006 TX Bit1 (976~991) 16 983, Bit9 (970~986) 17 978,
1832 13:40:15.370063 TX Bit2 (976~991) 16 983, Bit10 (976~992) 17 984,
1833 13:40:15.370120 TX Bit3 (970~986) 17 978, Bit11 (969~985) 17 977,
1834 13:40:15.370177 TX Bit4 (975~991) 17 983, Bit12 (971~988) 18 979,
1835 13:40:15.370235 TX Bit5 (971~989) 19 980, Bit13 (973~986) 14 979,
1836 13:40:15.370291 TX Bit6 (973~990) 18 981, Bit14 (972~989) 18 980,
1837 13:40:15.370348 TX Bit7 (974~991) 18 982, Bit15 (975~991) 17 983,
1838 13:40:15.370404
1839 13:40:15.370460 wait MRW command Rank1 MR14 =0xa fired (1)
1840 13:40:15.370517 Write Rank1 MR14 =0xa
1841 13:40:15.370574
1842 13:40:15.370630 CH=0, VrefRange= 0, VrefLevel = 10
1843 13:40:15.370687 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1844 13:40:15.370744 TX Bit1 (975~991) 17 983, Bit9 (970~988) 19 979,
1845 13:40:15.370801 TX Bit2 (976~992) 17 984, Bit10 (975~992) 18 983,
1846 13:40:15.370858 TX Bit3 (969~987) 19 978, Bit11 (969~985) 17 977,
1847 13:40:15.370914 TX Bit4 (974~992) 19 983, Bit12 (971~989) 19 980,
1848 13:40:15.370971 TX Bit5 (971~990) 20 980, Bit13 (973~986) 14 979,
1849 13:40:15.371028 TX Bit6 (973~991) 19 982, Bit14 (972~989) 18 980,
1850 13:40:15.371085 TX Bit7 (973~992) 20 982, Bit15 (975~992) 18 983,
1851 13:40:15.371142
1852 13:40:15.371198 Write Rank1 MR14 =0xc
1853 13:40:15.371254
1854 13:40:15.371310 CH=0, VrefRange= 0, VrefLevel = 12
1855 13:40:15.371367 TX Bit0 (976~993) 18 984, Bit8 (968~985) 18 976,
1856 13:40:15.371443 TX Bit1 (975~991) 17 983, Bit9 (969~989) 21 979,
1857 13:40:15.371502 TX Bit2 (976~992) 17 984, Bit10 (975~993) 19 984,
1858 13:40:15.371559 TX Bit3 (969~988) 20 978, Bit11 (969~986) 18 977,
1859 13:40:15.371617 TX Bit4 (974~992) 19 983, Bit12 (970~989) 20 979,
1860 13:40:15.371673 TX Bit5 (971~990) 20 980, Bit13 (972~987) 16 979,
1861 13:40:15.371730 TX Bit6 (972~991) 20 981, Bit14 (971~990) 20 980,
1862 13:40:15.371786 TX Bit7 (973~992) 20 982, Bit15 (974~992) 19 983,
1863 13:40:15.371843
1864 13:40:15.371899 Write Rank1 MR14 =0xe
1865 13:40:15.371955
1866 13:40:15.372011 CH=0, VrefRange= 0, VrefLevel = 14
1867 13:40:15.372067 TX Bit0 (976~994) 19 985, Bit8 (968~986) 19 977,
1868 13:40:15.372124 TX Bit1 (975~992) 18 983, Bit9 (969~989) 21 979,
1869 13:40:15.372181 TX Bit2 (976~993) 18 984, Bit10 (975~993) 19 984,
1870 13:40:15.372238 TX Bit3 (969~988) 20 978, Bit11 (968~986) 19 977,
1871 13:40:15.372296 TX Bit4 (973~992) 20 982, Bit12 (970~990) 21 980,
1872 13:40:15.372353 TX Bit5 (971~991) 21 981, Bit13 (972~987) 16 979,
1873 13:40:15.372410 TX Bit6 (972~991) 20 981, Bit14 (971~990) 20 980,
1874 13:40:15.372467 TX Bit7 (973~993) 21 983, Bit15 (974~993) 20 983,
1875 13:40:15.372523
1876 13:40:15.372579 Write Rank1 MR14 =0x10
1877 13:40:15.372654
1878 13:40:15.372746 CH=0, VrefRange= 0, VrefLevel = 16
1879 13:40:15.372840 TX Bit0 (976~995) 20 985, Bit8 (967~986) 20 976,
1880 13:40:15.372910 TX Bit1 (974~993) 20 983, Bit9 (969~989) 21 979,
1881 13:40:15.372969 TX Bit2 (976~994) 19 985, Bit10 (975~993) 19 984,
1882 13:40:15.373027 TX Bit3 (969~989) 21 979, Bit11 (968~988) 21 978,
1883 13:40:15.373085 TX Bit4 (974~993) 20 983, Bit12 (970~990) 21 980,
1884 13:40:15.373143 TX Bit5 (970~991) 22 980, Bit13 (971~989) 19 980,
1885 13:40:15.373201 TX Bit6 (971~992) 22 981, Bit14 (970~990) 21 980,
1886 13:40:15.373258 TX Bit7 (973~993) 21 983, Bit15 (974~993) 20 983,
1887 13:40:15.373315
1888 13:40:15.373372 Write Rank1 MR14 =0x12
1889 13:40:15.373429
1890 13:40:15.373485 CH=0, VrefRange= 0, VrefLevel = 18
1891 13:40:15.373542 TX Bit0 (975~995) 21 985, Bit8 (967~987) 21 977,
1892 13:40:15.373599 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1893 13:40:15.373669 TX Bit2 (976~994) 19 985, Bit10 (975~994) 20 984,
1894 13:40:15.373732 TX Bit3 (968~990) 23 979, Bit11 (968~988) 21 978,
1895 13:40:15.373790 TX Bit4 (973~993) 21 983, Bit12 (969~990) 22 979,
1896 13:40:15.373847 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1897 13:40:15.374099 TX Bit6 (971~992) 22 981, Bit14 (970~991) 22 980,
1898 13:40:15.374168 TX Bit7 (972~993) 22 982, Bit15 (974~993) 20 983,
1899 13:40:15.374227
1900 13:40:15.374284 Write Rank1 MR14 =0x14
1901 13:40:15.374341
1902 13:40:15.374397 CH=0, VrefRange= 0, VrefLevel = 20
1903 13:40:15.374455 TX Bit0 (975~996) 22 985, Bit8 (967~988) 22 977,
1904 13:40:15.374511 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1905 13:40:15.374569 TX Bit2 (976~994) 19 985, Bit10 (974~994) 21 984,
1906 13:40:15.374626 TX Bit3 (968~990) 23 979, Bit11 (968~989) 22 978,
1907 13:40:15.607590 TX Bit4 (973~993) 21 983, Bit12 (969~991) 23 980,
1908 13:40:15.607730 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1909 13:40:15.607801 TX Bit6 (971~992) 22 981, Bit14 (970~991) 22 980,
1910 13:40:15.607867 TX Bit7 (972~993) 22 982, Bit15 (974~993) 20 983,
1911 13:40:15.607930
1912 13:40:15.607993 Write Rank1 MR14 =0x16
1913 13:40:15.608054
1914 13:40:15.608113 CH=0, VrefRange= 0, VrefLevel = 22
1915 13:40:15.608173 TX Bit0 (975~997) 23 986, Bit8 (967~989) 23 978,
1916 13:40:15.608233 TX Bit1 (974~994) 21 984, Bit9 (968~991) 24 979,
1917 13:40:15.608292 TX Bit2 (975~996) 22 985, Bit10 (974~995) 22 984,
1918 13:40:15.608351 TX Bit3 (968~990) 23 979, Bit11 (968~989) 22 978,
1919 13:40:15.608409 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1920 13:40:15.608468 TX Bit5 (969~992) 24 980, Bit13 (970~990) 21 980,
1921 13:40:15.608527 TX Bit6 (970~993) 24 981, Bit14 (969~991) 23 980,
1922 13:40:15.608584 TX Bit7 (971~994) 24 982, Bit15 (973~994) 22 983,
1923 13:40:15.608642
1924 13:40:15.608699 Write Rank1 MR14 =0x18
1925 13:40:15.608756
1926 13:40:15.608813 CH=0, VrefRange= 0, VrefLevel = 24
1927 13:40:15.608870 TX Bit0 (975~997) 23 986, Bit8 (967~990) 24 978,
1928 13:40:15.608928 TX Bit1 (973~994) 22 983, Bit9 (968~991) 24 979,
1929 13:40:15.608985 TX Bit2 (975~996) 22 985, Bit10 (974~996) 23 985,
1930 13:40:15.609042 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1931 13:40:15.609100 TX Bit4 (971~995) 25 983, Bit12 (969~991) 23 980,
1932 13:40:15.609157 TX Bit5 (970~992) 23 981, Bit13 (969~990) 22 979,
1933 13:40:15.609215 TX Bit6 (970~993) 24 981, Bit14 (969~992) 24 980,
1934 13:40:15.609271 TX Bit7 (971~995) 25 983, Bit15 (972~996) 25 984,
1935 13:40:15.609328
1936 13:40:15.609385 Write Rank1 MR14 =0x1a
1937 13:40:15.609442
1938 13:40:15.609498 CH=0, VrefRange= 0, VrefLevel = 26
1939 13:40:15.609555 TX Bit0 (974~997) 24 985, Bit8 (967~990) 24 978,
1940 13:40:15.609613 TX Bit1 (972~995) 24 983, Bit9 (968~991) 24 979,
1941 13:40:15.609670 TX Bit2 (975~996) 22 985, Bit10 (973~997) 25 985,
1942 13:40:15.609727 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1943 13:40:15.609784 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
1944 13:40:15.609841 TX Bit5 (969~992) 24 980, Bit13 (969~991) 23 980,
1945 13:40:15.609897 TX Bit6 (970~993) 24 981, Bit14 (969~992) 24 980,
1946 13:40:15.609954 TX Bit7 (971~996) 26 983, Bit15 (972~996) 25 984,
1947 13:40:15.610011
1948 13:40:15.610068 Write Rank1 MR14 =0x1c
1949 13:40:15.610124
1950 13:40:15.610180 CH=0, VrefRange= 0, VrefLevel = 28
1951 13:40:15.610237 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
1952 13:40:15.610294 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1953 13:40:15.610351 TX Bit2 (974~997) 24 985, Bit10 (973~997) 25 985,
1954 13:40:15.610408 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
1955 13:40:15.610477 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
1956 13:40:15.610573 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1957 13:40:15.610634 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
1958 13:40:15.610693 TX Bit7 (970~996) 27 983, Bit15 (972~996) 25 984,
1959 13:40:15.610751
1960 13:40:15.610809 Write Rank1 MR14 =0x1e
1961 13:40:15.610866
1962 13:40:15.610923 CH=0, VrefRange= 0, VrefLevel = 30
1963 13:40:15.610981 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
1964 13:40:15.611039 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
1965 13:40:15.611097 TX Bit2 (974~997) 24 985, Bit10 (973~997) 25 985,
1966 13:40:15.611154 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
1967 13:40:15.611212 TX Bit4 (970~997) 28 983, Bit12 (968~992) 25 980,
1968 13:40:15.611269 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
1969 13:40:15.611327 TX Bit6 (969~995) 27 982, Bit14 (969~993) 25 981,
1970 13:40:15.611383 TX Bit7 (970~996) 27 983, Bit15 (972~996) 25 984,
1971 13:40:15.611451
1972 13:40:15.611509 Write Rank1 MR14 =0x20
1973 13:40:15.611566
1974 13:40:15.611623 CH=0, VrefRange= 0, VrefLevel = 32
1975 13:40:15.611679 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
1976 13:40:15.611737 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
1977 13:40:15.611794 TX Bit2 (974~998) 25 986, Bit10 (972~998) 27 985,
1978 13:40:15.611852 TX Bit3 (968~991) 24 979, Bit11 (967~991) 25 979,
1979 13:40:15.611909 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
1980 13:40:15.611967 TX Bit5 (968~993) 26 980, Bit13 (968~992) 25 980,
1981 13:40:15.612025 TX Bit6 (969~995) 27 982, Bit14 (968~993) 26 980,
1982 13:40:15.612082 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
1983 13:40:15.612139
1984 13:40:15.612195 Write Rank1 MR14 =0x22
1985 13:40:15.612252
1986 13:40:15.612308 CH=0, VrefRange= 0, VrefLevel = 34
1987 13:40:15.612364 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
1988 13:40:15.612421 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
1989 13:40:15.612478 TX Bit2 (974~998) 25 986, Bit10 (972~998) 27 985,
1990 13:40:15.612535 TX Bit3 (968~991) 24 979, Bit11 (967~991) 25 979,
1991 13:40:15.612591 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
1992 13:40:15.612649 TX Bit5 (968~993) 26 980, Bit13 (968~992) 25 980,
1993 13:40:15.612706 TX Bit6 (969~995) 27 982, Bit14 (968~993) 26 980,
1994 13:40:15.612764 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
1995 13:40:15.612820
1996 13:40:15.612876 Write Rank1 MR14 =0x24
1997 13:40:15.612933
1998 13:40:15.612989 CH=0, VrefRange= 0, VrefLevel = 36
1999 13:40:15.613255 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2000 13:40:15.613326 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
2001 13:40:15.613385 TX Bit2 (974~998) 25 986, Bit10 (972~998) 27 985,
2002 13:40:15.613443 TX Bit3 (968~991) 24 979, Bit11 (967~991) 25 979,
2003 13:40:15.613501 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2004 13:40:15.613558 TX Bit5 (968~993) 26 980, Bit13 (968~992) 25 980,
2005 13:40:15.613616 TX Bit6 (969~995) 27 982, Bit14 (968~993) 26 980,
2006 13:40:15.613673 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
2007 13:40:15.613729
2008 13:40:15.613787 Write Rank1 MR14 =0x26
2009 13:40:15.613844
2010 13:40:15.613901 CH=0, VrefRange= 0, VrefLevel = 38
2011 13:40:15.613958 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2012 13:40:15.614015 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
2013 13:40:15.614073 TX Bit2 (974~998) 25 986, Bit10 (972~998) 27 985,
2014 13:40:15.614130 TX Bit3 (968~991) 24 979, Bit11 (967~991) 25 979,
2015 13:40:15.614187 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2016 13:40:15.614244 TX Bit5 (968~993) 26 980, Bit13 (968~992) 25 980,
2017 13:40:15.614301 TX Bit6 (969~995) 27 982, Bit14 (968~993) 26 980,
2018 13:40:15.614358 TX Bit7 (971~997) 27 984, Bit15 (971~995) 25 983,
2019 13:40:15.614415
2020 13:40:15.614472
2021 13:40:15.614528 TX Vref found, early break! 375< 385
2022 13:40:15.614586 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2023 13:40:15.614643 u1DelayCellOfst[0]=9 cells (7 PI)
2024 13:40:15.614700 u1DelayCellOfst[1]=6 cells (5 PI)
2025 13:40:15.614756 u1DelayCellOfst[2]=9 cells (7 PI)
2026 13:40:15.614813 u1DelayCellOfst[3]=0 cells (0 PI)
2027 13:40:15.614870 u1DelayCellOfst[4]=5 cells (4 PI)
2028 13:40:15.614926 u1DelayCellOfst[5]=1 cells (1 PI)
2029 13:40:15.614982 u1DelayCellOfst[6]=3 cells (3 PI)
2030 13:40:15.615066 u1DelayCellOfst[7]=6 cells (5 PI)
2031 13:40:15.615126 Byte0, DQ PI dly=979, DQM PI dly= 982
2032 13:40:15.615183 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2033 13:40:15.615241
2034 13:40:15.615298 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2035 13:40:15.615356
2036 13:40:15.615424 u1DelayCellOfst[8]=0 cells (0 PI)
2037 13:40:15.615484 u1DelayCellOfst[9]=1 cells (1 PI)
2038 13:40:15.615541 u1DelayCellOfst[10]=9 cells (7 PI)
2039 13:40:15.615598 u1DelayCellOfst[11]=1 cells (1 PI)
2040 13:40:15.615655 u1DelayCellOfst[12]=2 cells (2 PI)
2041 13:40:15.615712 u1DelayCellOfst[13]=2 cells (2 PI)
2042 13:40:15.615769 u1DelayCellOfst[14]=2 cells (2 PI)
2043 13:40:15.615826 u1DelayCellOfst[15]=6 cells (5 PI)
2044 13:40:15.615882 Byte1, DQ PI dly=978, DQM PI dly= 981
2045 13:40:15.615939 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2046 13:40:15.615997
2047 13:40:15.616054 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2048 13:40:15.616112
2049 13:40:15.616169 Write Rank1 MR14 =0x20
2050 13:40:15.616225
2051 13:40:15.616282 Final TX Range 0 Vref 32
2052 13:40:15.616339
2053 13:40:15.616396 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2054 13:40:15.616453
2055 13:40:15.616510 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2056 13:40:15.616567 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2057 13:40:15.616625 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2058 13:40:15.616682 Write Rank1 MR3 =0xb0
2059 13:40:15.616738 DramC Write-DBI on
2060 13:40:15.616795 ==
2061 13:40:15.616853 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2062 13:40:15.616910 fsp= 1, odt_onoff= 1, Byte mode= 0
2063 13:40:15.616968 ==
2064 13:40:15.617025 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2065 13:40:15.617083
2066 13:40:15.617140 Begin, DQ Scan Range 701~765
2067 13:40:15.617198
2068 13:40:15.617255
2069 13:40:15.617312 TX Vref Scan disable
2070 13:40:15.617370 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2071 13:40:15.617429 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2072 13:40:15.617488 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2073 13:40:15.617547 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2074 13:40:15.617605 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2075 13:40:15.617664 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2076 13:40:15.617721 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2077 13:40:15.617780 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2078 13:40:15.617838 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2079 13:40:15.617895 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2080 13:40:15.617954 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2081 13:40:15.618012 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2082 13:40:15.618070 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2083 13:40:15.618129 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2084 13:40:15.618187 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2085 13:40:15.618245 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2086 13:40:15.618302 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2087 13:40:15.618361 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2088 13:40:15.618418 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2089 13:40:15.618476 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2090 13:40:15.618534 742 |2 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
2091 13:40:15.618593 Byte0, DQ PI dly=728, DQM PI dly= 728
2092 13:40:15.618650 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2093 13:40:15.618708
2094 13:40:15.618766 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2095 13:40:15.618824
2096 13:40:15.618880 Byte1, DQ PI dly=723, DQM PI dly= 723
2097 13:40:15.618938 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2098 13:40:15.618995
2099 13:40:15.619052 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2100 13:40:15.619110
2101 13:40:15.619168 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2102 13:40:15.619225 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2103 13:40:15.619283 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2104 13:40:15.619341 wait MRW command Rank1 MR3 =0x30 fired (1)
2105 13:40:15.619398 Write Rank1 MR3 =0x30
2106 13:40:15.619465 DramC Write-DBI off
2107 13:40:15.619523
2108 13:40:15.619580 [DATLAT]
2109 13:40:15.619637 Freq=1600, CH0 RK1, use_rxtx_scan=0
2110 13:40:15.619695
2111 13:40:15.619753 DATLAT Default: 0x10
2112 13:40:15.619810 7, 0xFFFF, sum=0
2113 13:40:15.619869 8, 0xFFFF, sum=0
2114 13:40:15.619927 9, 0xFFFF, sum=0
2115 13:40:15.619985 10, 0xFFFF, sum=0
2116 13:40:15.620043 11, 0xFFFF, sum=0
2117 13:40:15.620101 12, 0xFFFF, sum=0
2118 13:40:15.620361 13, 0xFFFF, sum=0
2119 13:40:15.620430 14, 0x0, sum=1
2120 13:40:15.620491 15, 0x0, sum=2
2121 13:40:15.620551 16, 0x0, sum=3
2122 13:40:15.620609 17, 0x0, sum=4
2123 13:40:15.620668 pattern=2 first_step=14 total pass=5 best_step=16
2124 13:40:15.620726 ==
2125 13:40:15.620784 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2126 13:40:15.620842 fsp= 1, odt_onoff= 1, Byte mode= 0
2127 13:40:15.620900 ==
2128 13:40:15.620957 Start DQ dly to find pass range UseTestEngine =1
2129 13:40:15.621015 x-axis: bit #, y-axis: DQ dly (-127~63)
2130 13:40:15.621072 RX Vref Scan = 0
2131 13:40:15.621129 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2132 13:40:15.621189 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2133 13:40:15.621248 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2134 13:40:15.621306 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2135 13:40:15.621364 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2136 13:40:15.621422 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2137 13:40:15.621480 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2138 13:40:15.621538 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2139 13:40:15.621596 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2140 13:40:15.621654 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2141 13:40:15.621713 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2142 13:40:15.621771 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2143 13:40:15.621829 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2144 13:40:15.622077 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2145 13:40:15.622144 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2146 13:40:15.625766 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2147 13:40:15.628815 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2148 13:40:15.632527 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2149 13:40:15.635721 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2150 13:40:15.638848 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2151 13:40:15.642451 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2152 13:40:15.642574 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2153 13:40:15.645440 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2154 13:40:15.648934 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2155 13:40:15.652108 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2156 13:40:15.656064 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2157 13:40:15.658756 0, [0] xxxoxxxx oxxoxxxx [MSB]
2158 13:40:15.658850 1, [0] xxxoxoxx ooxooxxx [MSB]
2159 13:40:15.662379 2, [0] xxxoxoxx ooxoooxx [MSB]
2160 13:40:15.665486 3, [0] xxxoxooo ooxoooox [MSB]
2161 13:40:15.669082 4, [0] xxxoxooo ooxoooox [MSB]
2162 13:40:15.672582 5, [0] ooxooooo ooxoooox [MSB]
2163 13:40:15.675791 6, [0] oooooooo ooxooooo [MSB]
2164 13:40:15.679243 33, [0] oooooooo xooooooo [MSB]
2165 13:40:15.682521 34, [0] oooxoooo xooooooo [MSB]
2166 13:40:15.685745 35, [0] oooxoxoo xooxoooo [MSB]
2167 13:40:15.689061 36, [0] oooxoxoo xooxoxoo [MSB]
2168 13:40:15.692322 37, [0] oooxoxoo xxoxoxoo [MSB]
2169 13:40:15.692415 38, [0] oooxoxxx xxoxxxxo [MSB]
2170 13:40:15.695533 39, [0] oxxxoxxx xxoxxxxo [MSB]
2171 13:40:15.698931 40, [0] oxxxxxxx xxoxxxxx [MSB]
2172 13:40:15.702163 41, [0] xxxxxxxx xxoxxxxx [MSB]
2173 13:40:15.705453 42, [0] xxxxxxxx xxoxxxxx [MSB]
2174 13:40:15.709296 43, [0] xxxxxxxx xxoxxxxx [MSB]
2175 13:40:15.709399 44, [0] xxxxxxxx xxxxxxxx [MSB]
2176 13:40:15.715684 iDelay=44, Bit 0, Center 22 (5 ~ 40) 36
2177 13:40:15.719247 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2178 13:40:15.722781 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2179 13:40:15.726113 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2180 13:40:15.729473 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2181 13:40:15.732754 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2182 13:40:15.735927 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2183 13:40:15.738967 iDelay=44, Bit 7, Center 20 (3 ~ 37) 35
2184 13:40:15.742855 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2185 13:40:15.746007 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2186 13:40:15.749062 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2187 13:40:15.752341 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2188 13:40:15.755819 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2189 13:40:15.759319 iDelay=44, Bit 13, Center 18 (2 ~ 35) 34
2190 13:40:15.765918 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
2191 13:40:15.769126 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2192 13:40:15.769218 ==
2193 13:40:15.772554 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2194 13:40:15.775725 fsp= 1, odt_onoff= 1, Byte mode= 0
2195 13:40:15.775818 ==
2196 13:40:15.779305 DQS Delay:
2197 13:40:15.779427 DQS0 = 0, DQS1 = 0
2198 13:40:15.779548 DQM Delay:
2199 13:40:15.782665 DQM0 = 19, DQM1 = 19
2200 13:40:15.782781 DQ Delay:
2201 13:40:15.785827 DQ0 =22, DQ1 =21, DQ2 =22, DQ3 =15
2202 13:40:15.789851 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2203 13:40:15.793208 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2204 13:40:15.796397 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
2205 13:40:15.796492
2206 13:40:15.796563
2207 13:40:15.796630
2208 13:40:15.799787 [DramC_TX_OE_Calibration] TA2
2209 13:40:15.802959 Original DQ_B0 (3 6) =30, OEN = 27
2210 13:40:15.806244 Original DQ_B1 (3 6) =30, OEN = 27
2211 13:40:15.809483 23, 0x0, End_B0=23 End_B1=23
2212 13:40:15.809605 24, 0x0, End_B0=24 End_B1=24
2213 13:40:15.812619 25, 0x0, End_B0=25 End_B1=25
2214 13:40:15.816304 26, 0x0, End_B0=26 End_B1=26
2215 13:40:15.819530 27, 0x0, End_B0=27 End_B1=27
2216 13:40:15.819620 28, 0x0, End_B0=28 End_B1=28
2217 13:40:15.823394 29, 0x0, End_B0=29 End_B1=29
2218 13:40:15.826390 30, 0x0, End_B0=30 End_B1=30
2219 13:40:15.829369 31, 0xFFFF, End_B0=30 End_B1=30
2220 13:40:15.836245 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2221 13:40:15.839342 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2222 13:40:15.839480
2223 13:40:15.839585
2224 13:40:15.843082 Write Rank1 MR23 =0x3f
2225 13:40:15.843175 [DQSOSC]
2226 13:40:15.853155 [DQSOSCAuto] RK1, (LSB)MR18= 0xd6d6, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
2227 13:40:15.856458 CH0_RK1: MR19=0x202, MR18=0xD6D6, DQSOSC=433, MR23=63, INC=13, DEC=19
2228 13:40:15.859705 Write Rank1 MR23 =0x3f
2229 13:40:15.859798 [DQSOSC]
2230 13:40:15.869535 [DQSOSCAuto] RK1, (LSB)MR18= 0xd9d9, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2231 13:40:15.873013 CH0 RK1: MR19=202, MR18=D9D9
2232 13:40:15.873106 [RxdqsGatingPostProcess] freq 1600
2233 13:40:15.879525 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2234 13:40:15.879620 Rank: 0
2235 13:40:15.882889 best DQS0 dly(2T, 0.5T) = (2, 5)
2236 13:40:15.886151 best DQS1 dly(2T, 0.5T) = (2, 5)
2237 13:40:15.889263 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2238 13:40:15.892649 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2239 13:40:15.892742 Rank: 1
2240 13:40:15.895932 best DQS0 dly(2T, 0.5T) = (2, 6)
2241 13:40:15.899831 best DQS1 dly(2T, 0.5T) = (2, 6)
2242 13:40:15.903189 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2243 13:40:15.906468 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2244 13:40:15.909707 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2245 13:40:15.913010 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2246 13:40:15.919789 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2247 13:40:15.919890 Write Rank0 MR13 =0x59
2248 13:40:15.923129 ==
2249 13:40:15.926198 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2250 13:40:15.929482 fsp= 1, odt_onoff= 1, Byte mode= 0
2251 13:40:15.929606 ==
2252 13:40:15.933285 === u2Vref_new: 0x56 --> 0x3a
2253 13:40:15.936356 === u2Vref_new: 0x58 --> 0x58
2254 13:40:15.939516 === u2Vref_new: 0x5a --> 0x5a
2255 13:40:15.942850 === u2Vref_new: 0x5c --> 0x78
2256 13:40:15.942944 === u2Vref_new: 0x5e --> 0x7a
2257 13:40:15.946579 === u2Vref_new: 0x60 --> 0x90
2258 13:40:15.950511 [CA 0] Center 37 (12~63) winsize 52
2259 13:40:15.953424 [CA 1] Center 37 (11~63) winsize 53
2260 13:40:15.957058 [CA 2] Center 34 (6~63) winsize 58
2261 13:40:15.960179 [CA 3] Center 34 (6~63) winsize 58
2262 13:40:15.963326 [CA 4] Center 34 (6~63) winsize 58
2263 13:40:15.966578 [CA 5] Center 28 (-1~58) winsize 60
2264 13:40:15.966698
2265 13:40:15.970403 [CATrainingPosCal] consider 1 rank data
2266 13:40:15.973711 u2DelayCellTimex100 = 735/100 ps
2267 13:40:15.976890 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2268 13:40:15.979909 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2269 13:40:15.983366 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2270 13:40:15.990199 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2271 13:40:15.993504 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2272 13:40:15.996801 CA5 delay=28 (-1~58),Diff = 0 PI (0 cell)
2273 13:40:15.996918
2274 13:40:16.000427 CA PerBit enable=1, Macro0, CA PI delay=28
2275 13:40:16.003537 === u2Vref_new: 0x60 --> 0x90
2276 13:40:16.003654
2277 13:40:16.003751 Vref(ca) range 1: 32
2278 13:40:16.003821
2279 13:40:16.006953 CS Dly= 12 (43-0-32)
2280 13:40:16.010368 Write Rank0 MR13 =0xd8
2281 13:40:16.010470 Write Rank0 MR13 =0xd8
2282 13:40:16.013705 Write Rank0 MR12 =0x60
2283 13:40:16.013819 Write Rank1 MR13 =0x59
2284 13:40:16.016886 ==
2285 13:40:16.020104 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2286 13:40:16.023708 fsp= 1, odt_onoff= 1, Byte mode= 0
2287 13:40:16.023798 ==
2288 13:40:16.026941 === u2Vref_new: 0x56 --> 0x3a
2289 13:40:16.030122 === u2Vref_new: 0x58 --> 0x58
2290 13:40:16.033508 === u2Vref_new: 0x5a --> 0x5a
2291 13:40:16.037134 === u2Vref_new: 0x5c --> 0x78
2292 13:40:16.040302 === u2Vref_new: 0x5e --> 0x7a
2293 13:40:16.040420 === u2Vref_new: 0x60 --> 0x90
2294 13:40:16.044137 [CA 0] Center 37 (12~63) winsize 52
2295 13:40:16.047376 [CA 1] Center 37 (12~63) winsize 52
2296 13:40:16.050659 [CA 2] Center 34 (6~63) winsize 58
2297 13:40:16.053903 [CA 3] Center 34 (6~63) winsize 58
2298 13:40:16.057047 [CA 4] Center 34 (6~63) winsize 58
2299 13:40:16.060708 [CA 5] Center 28 (-2~58) winsize 61
2300 13:40:16.060823
2301 13:40:16.063762 [CATrainingPosCal] consider 2 rank data
2302 13:40:16.067474 u2DelayCellTimex100 = 735/100 ps
2303 13:40:16.070755 CA0 delay=37 (12~63),Diff = 9 PI (11 cell)
2304 13:40:16.074084 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2305 13:40:16.080797 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2306 13:40:16.084021 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2307 13:40:16.087300 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2308 13:40:16.090324 CA5 delay=28 (-1~58),Diff = 0 PI (0 cell)
2309 13:40:16.090438
2310 13:40:16.093994 CA PerBit enable=1, Macro0, CA PI delay=28
2311 13:40:16.096936 === u2Vref_new: 0x60 --> 0x90
2312 13:40:16.097025
2313 13:40:16.097126 Vref(ca) range 1: 32
2314 13:40:16.100593
2315 13:40:16.100713 CS Dly= 11 (42-0-32)
2316 13:40:16.103882 Write Rank1 MR13 =0xd8
2317 13:40:16.103974 Write Rank1 MR13 =0xd8
2318 13:40:16.107164 Write Rank1 MR12 =0x60
2319 13:40:16.110402 [RankSwap] Rank num 2, (Multi 1), Rank 0
2320 13:40:16.114094 Write Rank0 MR2 =0xad
2321 13:40:16.114209 [Write Leveling]
2322 13:40:16.117094 delay byte0 byte1 byte2 byte3
2323 13:40:16.117207
2324 13:40:16.117307 10 0 0
2325 13:40:16.120465 11 0 0
2326 13:40:16.120590 12 0 0
2327 13:40:16.123648 13 0 0
2328 13:40:16.123765 14 0 0
2329 13:40:16.123852 15 0 0
2330 13:40:16.127422 16 0 0
2331 13:40:16.127512 17 0 0
2332 13:40:16.130612 18 0 0
2333 13:40:16.130715 19 0 0
2334 13:40:16.133845 20 0 0
2335 13:40:16.133961 21 0 0
2336 13:40:16.134068 22 0 0
2337 13:40:16.137059 23 0 0
2338 13:40:16.137186 24 0 ff
2339 13:40:16.140104 25 0 ff
2340 13:40:16.140194 26 0 ff
2341 13:40:16.143399 27 0 ff
2342 13:40:16.143495 28 0 ff
2343 13:40:16.143571 29 0 ff
2344 13:40:16.147268 30 0 ff
2345 13:40:16.147393 31 0 ff
2346 13:40:16.150629 32 0 ff
2347 13:40:16.150721 33 0 ff
2348 13:40:16.153911 34 ff ff
2349 13:40:16.154035 35 ff ff
2350 13:40:16.157198 36 ff ff
2351 13:40:16.157289 37 ff ff
2352 13:40:16.160406 38 ff ff
2353 13:40:16.160500 39 ff ff
2354 13:40:16.163629 40 ff ff
2355 13:40:16.166877 pass bytecount = 0xff (0xff: all bytes pass)
2356 13:40:16.166993
2357 13:40:16.167094 DQS0 dly: 34
2358 13:40:16.167192 DQS1 dly: 24
2359 13:40:16.170664 Write Rank0 MR2 =0x2d
2360 13:40:16.173697 [RankSwap] Rank num 2, (Multi 1), Rank 0
2361 13:40:16.176862 Write Rank0 MR1 =0xd6
2362 13:40:16.176953 [Gating]
2363 13:40:16.177024 ==
2364 13:40:16.183392 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2365 13:40:16.186706 fsp= 1, odt_onoff= 1, Byte mode= 0
2366 13:40:16.186798 ==
2367 13:40:16.189987 3 1 0 |3635 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2368 13:40:16.193812 3 1 4 |3535 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2369 13:40:16.200156 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2370 13:40:16.203261 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2371 13:40:16.206982 3 1 16 |3535 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2372 13:40:16.210434 [Byte 1] Lead/lag Transition tap number (1)
2373 13:40:16.216840 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2374 13:40:16.220169 3 1 24 |1d1c 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2375 13:40:16.223502 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2376 13:40:16.230334 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2377 13:40:16.233747 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2378 13:40:16.236651 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2379 13:40:16.243503 3 2 12 |a09 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2380 13:40:16.246407 3 2 16 |e0d 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2381 13:40:16.250184 [Byte 0] Lead/lag Transition tap number (1)
2382 13:40:16.253481 3 2 20 |3d3c 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2383 13:40:16.259999 3 2 24 |3130 302 |(11 11)(11 1) |(1 1)(0 0)| 0
2384 13:40:16.263282 3 2 28 |909 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2385 13:40:16.266522 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2386 13:40:16.273342 3 3 4 |1918 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2387 13:40:16.276416 3 3 8 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2388 13:40:16.280084 3 3 12 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2389 13:40:16.283317 3 3 16 |3a39 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2390 13:40:16.289841 3 3 20 |1110 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2391 13:40:16.293138 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2392 13:40:16.296518 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2393 13:40:16.302878 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2394 13:40:16.306110 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2395 13:40:16.309877 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2396 13:40:16.316067 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2397 13:40:16.319826 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2398 13:40:16.323289 3 4 16 |2322 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2399 13:40:16.329538 3 4 20 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2400 13:40:16.332718 3 4 24 |3d3d 1a19 |(11 11)(11 11) |(1 1)(1 1)| 0
2401 13:40:16.336077 3 4 28 |3d3d b0a |(11 11)(11 11) |(1 1)(1 1)| 0
2402 13:40:16.339467 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2403 13:40:16.346279 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2404 13:40:16.349301 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2405 13:40:16.352655 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2406 13:40:16.359539 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2407 13:40:16.362625 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2408 13:40:16.366105 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2409 13:40:16.372894 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2410 13:40:16.376224 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2411 13:40:16.379400 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2412 13:40:16.386079 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2413 13:40:16.389267 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2414 13:40:16.392576 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2415 13:40:16.395856 [Byte 0] Lead/lag Transition tap number (2)
2416 13:40:16.402304 3 6 16 |1010 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2417 13:40:16.405872 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2418 13:40:16.409111 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2419 13:40:16.412471 [Byte 1] Lead/lag Transition tap number (2)
2420 13:40:16.418933 3 6 24 |4646 1413 |(0 0)(11 11) |(0 0)(0 0)| 0
2421 13:40:16.422061 [Byte 0]First pass (3, 6, 24)
2422 13:40:16.425307 3 6 28 |4646 2020 |(0 0)(11 11) |(0 0)(0 0)| 0
2423 13:40:16.429122 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2424 13:40:16.432340 [Byte 1]First pass (3, 7, 0)
2425 13:40:16.435823 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2426 13:40:16.439053 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2427 13:40:16.442421 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2428 13:40:16.448767 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2429 13:40:16.452137 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2430 13:40:16.455436 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2431 13:40:16.458637 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2432 13:40:16.462337 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2433 13:40:16.468580 All bytes gating window > 1UI, Early break!
2434 13:40:16.468674
2435 13:40:16.472071 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2436 13:40:16.472164
2437 13:40:16.475515 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2438 13:40:16.475608
2439 13:40:16.475687
2440 13:40:16.475755
2441 13:40:16.478761 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2442 13:40:16.478852
2443 13:40:16.481970 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2444 13:40:16.484955
2445 13:40:16.485056
2446 13:40:16.485129 Write Rank0 MR1 =0x56
2447 13:40:16.485197
2448 13:40:16.488583 best RODT dly(2T, 0.5T) = (2, 3)
2449 13:40:16.488675
2450 13:40:16.491677 best RODT dly(2T, 0.5T) = (2, 3)
2451 13:40:16.491770 ==
2452 13:40:16.498446 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2453 13:40:16.502083 fsp= 1, odt_onoff= 1, Byte mode= 0
2454 13:40:16.502176 ==
2455 13:40:16.505361 Start DQ dly to find pass range UseTestEngine =0
2456 13:40:16.508466 x-axis: bit #, y-axis: DQ dly (-127~63)
2457 13:40:16.508560 RX Vref Scan = 0
2458 13:40:16.511755 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2459 13:40:16.515646 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2460 13:40:16.518344 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2461 13:40:16.522125 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2462 13:40:16.525384 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2463 13:40:16.528402 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2464 13:40:16.531675 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2465 13:40:16.531770 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2466 13:40:16.535446 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2467 13:40:16.538675 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2468 13:40:16.541708 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2469 13:40:16.545377 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2470 13:40:16.548684 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2471 13:40:16.551835 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2472 13:40:16.555142 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2473 13:40:16.558416 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2474 13:40:16.558511 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2475 13:40:16.561677 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2476 13:40:16.564850 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2477 13:40:16.568643 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2478 13:40:16.571435 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2479 13:40:16.575340 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2480 13:40:16.578646 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2481 13:40:16.578740 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2482 13:40:16.582030 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2483 13:40:16.585265 -1, [0] xxxxxxxx xoxxxxxo [MSB]
2484 13:40:16.588527 0, [0] xxxoxxxx ooxxxxxo [MSB]
2485 13:40:16.591663 1, [0] xxxoxxxx ooxxxxxo [MSB]
2486 13:40:16.595203 2, [0] xxooxxxx ooxxxxxo [MSB]
2487 13:40:16.595298 3, [0] oxooxxxo oooxxxxo [MSB]
2488 13:40:16.598684 4, [0] xxooxxxo oooxxxxo [MSB]
2489 13:40:16.601748 5, [0] oooooxoo ooooooxo [MSB]
2490 13:40:16.604878 32, [0] oooooooo ooooooox [MSB]
2491 13:40:16.608298 33, [0] oooooooo ooooooox [MSB]
2492 13:40:16.611602 34, [0] oooooooo ooooooox [MSB]
2493 13:40:16.614943 35, [0] oooxoooo xxooooox [MSB]
2494 13:40:16.615037 36, [0] oooxoooo xxooooox [MSB]
2495 13:40:16.618579 37, [0] ooxxoooo xxooooox [MSB]
2496 13:40:16.621503 38, [0] ooxxoooo xxooooox [MSB]
2497 13:40:16.624949 39, [0] ooxxooox xxooooox [MSB]
2498 13:40:16.628056 40, [0] oxxxxoox xxxoooox [MSB]
2499 13:40:16.631466 41, [0] xxxxxoox xxxxxxxx [MSB]
2500 13:40:16.634630 42, [0] xxxxxxxx xxxxxxxx [MSB]
2501 13:40:16.637944 iDelay=42, Bit 0, Center 22 (5 ~ 40) 36
2502 13:40:16.641277 iDelay=42, Bit 1, Center 22 (5 ~ 39) 35
2503 13:40:16.644609 iDelay=42, Bit 2, Center 19 (2 ~ 36) 35
2504 13:40:16.647902 iDelay=42, Bit 3, Center 17 (0 ~ 34) 35
2505 13:40:16.651137 iDelay=42, Bit 4, Center 22 (5 ~ 39) 35
2506 13:40:16.654931 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
2507 13:40:16.657945 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
2508 13:40:16.661579 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
2509 13:40:16.664799 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
2510 13:40:16.668142 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
2511 13:40:16.671352 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
2512 13:40:16.674635 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
2513 13:40:16.681309 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
2514 13:40:16.684496 iDelay=42, Bit 13, Center 22 (5 ~ 40) 36
2515 13:40:16.687854 iDelay=42, Bit 14, Center 23 (6 ~ 40) 35
2516 13:40:16.691126 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
2517 13:40:16.691218 ==
2518 13:40:16.694490 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2519 13:40:16.697792 fsp= 1, odt_onoff= 1, Byte mode= 0
2520 13:40:16.697884 ==
2521 13:40:16.701054 DQS Delay:
2522 13:40:16.701146 DQS0 = 0, DQS1 = 0
2523 13:40:16.704655 DQM Delay:
2524 13:40:16.704747 DQM0 = 21, DQM1 = 19
2525 13:40:16.704819 DQ Delay:
2526 13:40:16.707665 DQ0 =22, DQ1 =22, DQ2 =19, DQ3 =17
2527 13:40:16.711067 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =20
2528 13:40:16.714363 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
2529 13:40:16.717671 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =14
2530 13:40:16.717788
2531 13:40:16.717889
2532 13:40:16.721551 DramC Write-DBI off
2533 13:40:16.721666 ==
2534 13:40:16.727899 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2535 13:40:16.728016 fsp= 1, odt_onoff= 1, Byte mode= 0
2536 13:40:16.730892 ==
2537 13:40:16.734670 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2538 13:40:16.734785
2539 13:40:16.737939 Begin, DQ Scan Range 920~1176
2540 13:40:16.738051
2541 13:40:16.738153
2542 13:40:16.738252 TX Vref Scan disable
2543 13:40:16.740969 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2544 13:40:16.747901 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2545 13:40:16.751220 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2546 13:40:16.754102 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2547 13:40:16.757824 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2548 13:40:16.761106 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2549 13:40:16.764245 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2550 13:40:16.767915 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2551 13:40:16.770942 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2552 13:40:16.774347 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2553 13:40:16.777484 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2554 13:40:16.780697 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2555 13:40:16.784032 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2556 13:40:16.787259 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2557 13:40:16.791208 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2558 13:40:16.794441 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2559 13:40:16.800845 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2560 13:40:16.804103 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2561 13:40:16.807299 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2562 13:40:16.810962 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2563 13:40:16.814419 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2564 13:40:16.817705 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2565 13:40:16.821032 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2566 13:40:16.824264 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2567 13:40:16.827164 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2568 13:40:16.830491 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2569 13:40:16.833711 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2570 13:40:16.837043 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2571 13:40:16.840344 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2572 13:40:16.843710 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2573 13:40:16.847352 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2574 13:40:16.853648 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2575 13:40:16.857098 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2576 13:40:16.860671 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2577 13:40:16.863665 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2578 13:40:16.866967 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2579 13:40:16.870388 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2580 13:40:16.873567 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2581 13:40:16.876805 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2582 13:40:16.880404 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2583 13:40:16.883558 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2584 13:40:16.887091 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2585 13:40:16.890400 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2586 13:40:16.893674 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2587 13:40:16.897494 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2588 13:40:16.901064 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2589 13:40:16.903503 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2590 13:40:16.907369 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2591 13:40:16.910664 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2592 13:40:16.913985 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2593 13:40:16.917246 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2594 13:40:16.920321 971 |3 6 11|[0] xxxxxxxx oooxxxxo [MSB]
2595 13:40:16.927327 972 |3 6 12|[0] xxxxxxxx oooxoxoo [MSB]
2596 13:40:16.930577 973 |3 6 13|[0] xxxxxxxx oooooxoo [MSB]
2597 13:40:16.933811 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2598 13:40:16.937131 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2599 13:40:16.940468 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2600 13:40:16.943785 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2601 13:40:16.947100 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2602 13:40:16.950408 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2603 13:40:16.953692 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2604 13:40:16.956707 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
2605 13:40:16.960557 982 |3 6 22|[0] xooooxoo oooooooo [MSB]
2606 13:40:16.963537 986 |3 6 26|[0] oooooooo ooooooox [MSB]
2607 13:40:16.966978 987 |3 6 27|[0] oooooooo oxooooox [MSB]
2608 13:40:16.973887 988 |3 6 28|[0] oooooooo oxooooox [MSB]
2609 13:40:16.976993 989 |3 6 29|[0] oooooooo xxooooox [MSB]
2610 13:40:16.980152 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
2611 13:40:16.983581 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2612 13:40:16.987356 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2613 13:40:16.990420 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2614 13:40:16.993653 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2615 13:40:16.996527 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2616 13:40:17.000251 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2617 13:40:17.003578 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2618 13:40:17.006710 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2619 13:40:17.009913 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2620 13:40:17.013322 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2621 13:40:17.016506 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2622 13:40:17.020398 1002 |3 6 42|[0] ooxxoooo xxxxxxxx [MSB]
2623 13:40:17.026632 1003 |3 6 43|[0] oxxxxoxx xxxxxxxx [MSB]
2624 13:40:17.030061 1004 |3 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
2625 13:40:17.033258 Byte0, DQ PI dly=991, DQM PI dly= 991
2626 13:40:17.036519 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
2627 13:40:17.036614
2628 13:40:17.039766 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
2629 13:40:17.039861
2630 13:40:17.043019 Byte1, DQ PI dly=979, DQM PI dly= 979
2631 13:40:17.050072 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2632 13:40:17.050167
2633 13:40:17.053150 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2634 13:40:17.053244
2635 13:40:17.053316 ==
2636 13:40:17.060133 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2637 13:40:17.063458 fsp= 1, odt_onoff= 1, Byte mode= 0
2638 13:40:17.063552 ==
2639 13:40:17.066518 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2640 13:40:17.066610
2641 13:40:17.069694 Begin, DQ Scan Range 955~1019
2642 13:40:17.069787 Write Rank0 MR14 =0x0
2643 13:40:17.079950
2644 13:40:17.080045 CH=1, VrefRange= 0, VrefLevel = 0
2645 13:40:17.086959 TX Bit0 (984~1000) 17 992, Bit8 (972~984) 13 978,
2646 13:40:17.089928 TX Bit1 (984~997) 14 990, Bit9 (974~983) 10 978,
2647 13:40:17.096968 TX Bit2 (982~997) 16 989, Bit10 (975~986) 12 980,
2648 13:40:17.100035 TX Bit3 (981~993) 13 987, Bit11 (976~986) 11 981,
2649 13:40:17.103155 TX Bit4 (984~999) 16 991, Bit12 (975~986) 12 980,
2650 13:40:17.109878 TX Bit5 (985~999) 15 992, Bit13 (976~987) 12 981,
2651 13:40:17.113226 TX Bit6 (984~998) 15 991, Bit14 (975~986) 12 980,
2652 13:40:17.116436 TX Bit7 (984~997) 14 990, Bit15 (969~979) 11 974,
2653 13:40:17.119723
2654 13:40:17.119838 Write Rank0 MR14 =0x2
2655 13:40:17.129621
2656 13:40:17.129744 CH=1, VrefRange= 0, VrefLevel = 2
2657 13:40:17.135981 TX Bit0 (984~1001) 18 992, Bit8 (972~984) 13 978,
2658 13:40:17.139468 TX Bit1 (984~998) 15 991, Bit9 (972~983) 12 977,
2659 13:40:17.146602 TX Bit2 (982~997) 16 989, Bit10 (975~986) 12 980,
2660 13:40:17.149846 TX Bit3 (980~994) 15 987, Bit11 (976~987) 12 981,
2661 13:40:17.152980 TX Bit4 (983~999) 17 991, Bit12 (975~987) 13 981,
2662 13:40:17.159712 TX Bit5 (985~999) 15 992, Bit13 (976~988) 13 982,
2663 13:40:17.162828 TX Bit6 (984~999) 16 991, Bit14 (975~987) 13 981,
2664 13:40:17.166044 TX Bit7 (984~998) 15 991, Bit15 (969~980) 12 974,
2665 13:40:17.166138
2666 13:40:17.169211 Write Rank0 MR14 =0x4
2667 13:40:17.178648
2668 13:40:17.178779 CH=1, VrefRange= 0, VrefLevel = 4
2669 13:40:17.185460 TX Bit0 (984~1002) 19 993, Bit8 (971~985) 15 978,
2670 13:40:17.189063 TX Bit1 (983~998) 16 990, Bit9 (971~984) 14 977,
2671 13:40:17.195488 TX Bit2 (982~998) 17 990, Bit10 (974~987) 14 980,
2672 13:40:17.198732 TX Bit3 (979~995) 17 987, Bit11 (975~988) 14 981,
2673 13:40:17.201881 TX Bit4 (983~999) 17 991, Bit12 (974~988) 15 981,
2674 13:40:17.208475 TX Bit5 (985~999) 15 992, Bit13 (976~989) 14 982,
2675 13:40:17.212386 TX Bit6 (984~999) 16 991, Bit14 (974~988) 15 981,
2676 13:40:17.215316 TX Bit7 (984~999) 16 991, Bit15 (969~982) 14 975,
2677 13:40:17.218907
2678 13:40:17.219028 Write Rank0 MR14 =0x6
2679 13:40:17.227994
2680 13:40:17.228125 CH=1, VrefRange= 0, VrefLevel = 6
2681 13:40:17.235092 TX Bit0 (984~1002) 19 993, Bit8 (971~985) 15 978,
2682 13:40:17.238426 TX Bit1 (983~999) 17 991, Bit9 (971~984) 14 977,
2683 13:40:17.244687 TX Bit2 (981~999) 19 990, Bit10 (974~987) 14 980,
2684 13:40:17.248116 TX Bit3 (979~996) 18 987, Bit11 (975~989) 15 982,
2685 13:40:17.251671 TX Bit4 (983~1000) 18 991, Bit12 (975~989) 15 982,
2686 13:40:17.258368 TX Bit5 (985~1000) 16 992, Bit13 (976~989) 14 982,
2687 13:40:17.261629 TX Bit6 (984~1000) 17 992, Bit14 (974~988) 15 981,
2688 13:40:17.267948 TX Bit7 (984~999) 16 991, Bit15 (969~983) 15 976,
2689 13:40:17.268077
2690 13:40:17.268200 Write Rank0 MR14 =0x8
2691 13:40:17.278477
2692 13:40:17.278604 CH=1, VrefRange= 0, VrefLevel = 8
2693 13:40:17.284742 TX Bit0 (984~1003) 20 993, Bit8 (971~985) 15 978,
2694 13:40:17.288016 TX Bit1 (983~999) 17 991, Bit9 (971~984) 14 977,
2695 13:40:17.294482 TX Bit2 (981~999) 19 990, Bit10 (973~989) 17 981,
2696 13:40:17.298098 TX Bit3 (979~997) 19 988, Bit11 (975~990) 16 982,
2697 13:40:17.301531 TX Bit4 (983~1000) 18 991, Bit12 (974~990) 17 982,
2698 13:40:17.307792 TX Bit5 (984~1001) 18 992, Bit13 (976~990) 15 983,
2699 13:40:17.310862 TX Bit6 (983~1000) 18 991, Bit14 (973~990) 18 981,
2700 13:40:17.317947 TX Bit7 (983~999) 17 991, Bit15 (969~984) 16 976,
2701 13:40:17.318046
2702 13:40:17.318119 Write Rank0 MR14 =0xa
2703 13:40:17.328109
2704 13:40:17.331344 CH=1, VrefRange= 0, VrefLevel = 10
2705 13:40:17.334680 TX Bit0 (984~1003) 20 993, Bit8 (970~986) 17 978,
2706 13:40:17.337928 TX Bit1 (982~1000) 19 991, Bit9 (970~985) 16 977,
2707 13:40:17.344853 TX Bit2 (980~1000) 21 990, Bit10 (972~990) 19 981,
2708 13:40:17.348213 TX Bit3 (978~998) 21 988, Bit11 (975~991) 17 983,
2709 13:40:17.351309 TX Bit4 (982~1001) 20 991, Bit12 (973~991) 19 982,
2710 13:40:17.357819 TX Bit5 (984~1002) 19 993, Bit13 (975~991) 17 983,
2711 13:40:17.361082 TX Bit6 (983~1001) 19 992, Bit14 (974~991) 18 982,
2712 13:40:17.367719 TX Bit7 (983~1000) 18 991, Bit15 (968~984) 17 976,
2713 13:40:17.367821
2714 13:40:17.367895 Write Rank0 MR14 =0xc
2715 13:40:17.378169
2716 13:40:17.381457 CH=1, VrefRange= 0, VrefLevel = 12
2717 13:40:17.384822 TX Bit0 (984~1004) 21 994, Bit8 (970~987) 18 978,
2718 13:40:17.388445 TX Bit1 (982~1001) 20 991, Bit9 (970~985) 16 977,
2719 13:40:17.394851 TX Bit2 (979~1000) 22 989, Bit10 (972~990) 19 981,
2720 13:40:17.397812 TX Bit3 (978~998) 21 988, Bit11 (973~991) 19 982,
2721 13:40:17.401555 TX Bit4 (982~1002) 21 992, Bit12 (974~992) 19 983,
2722 13:40:17.407941 TX Bit5 (984~1002) 19 993, Bit13 (974~991) 18 982,
2723 13:40:17.411784 TX Bit6 (983~1001) 19 992, Bit14 (973~991) 19 982,
2724 13:40:17.418505 TX Bit7 (982~1000) 19 991, Bit15 (968~984) 17 976,
2725 13:40:17.418599
2726 13:40:17.418671 Write Rank0 MR14 =0xe
2727 13:40:17.428919
2728 13:40:17.432021 CH=1, VrefRange= 0, VrefLevel = 14
2729 13:40:17.435502 TX Bit0 (983~1004) 22 993, Bit8 (970~987) 18 978,
2730 13:40:17.438473 TX Bit1 (981~1001) 21 991, Bit9 (970~985) 16 977,
2731 13:40:17.445479 TX Bit2 (979~1000) 22 989, Bit10 (972~991) 20 981,
2732 13:40:17.448816 TX Bit3 (978~998) 21 988, Bit11 (973~991) 19 982,
2733 13:40:17.451981 TX Bit4 (981~1002) 22 991, Bit12 (972~992) 21 982,
2734 13:40:17.458802 TX Bit5 (984~1003) 20 993, Bit13 (974~992) 19 983,
2735 13:40:17.462011 TX Bit6 (982~1002) 21 992, Bit14 (972~992) 21 982,
2736 13:40:17.468570 TX Bit7 (982~1001) 20 991, Bit15 (968~985) 18 976,
2737 13:40:17.468665
2738 13:40:17.468737 Write Rank0 MR14 =0x10
2739 13:40:17.479461
2740 13:40:17.482682 CH=1, VrefRange= 0, VrefLevel = 16
2741 13:40:17.486020 TX Bit0 (983~1005) 23 994, Bit8 (969~988) 20 978,
2742 13:40:17.489330 TX Bit1 (981~1002) 22 991, Bit9 (970~986) 17 978,
2743 13:40:17.496037 TX Bit2 (979~1001) 23 990, Bit10 (971~991) 21 981,
2744 13:40:17.499356 TX Bit3 (978~999) 22 988, Bit11 (974~992) 19 983,
2745 13:40:17.502643 TX Bit4 (981~1003) 23 992, Bit12 (972~992) 21 982,
2746 13:40:17.508869 TX Bit5 (983~1003) 21 993, Bit13 (974~992) 19 983,
2747 13:40:17.512514 TX Bit6 (982~1002) 21 992, Bit14 (972~992) 21 982,
2748 13:40:17.519017 TX Bit7 (982~1002) 21 992, Bit15 (967~985) 19 976,
2749 13:40:17.519151
2750 13:40:17.519257 Write Rank0 MR14 =0x12
2751 13:40:17.529914
2752 13:40:17.533005 CH=1, VrefRange= 0, VrefLevel = 18
2753 13:40:17.536555 TX Bit0 (982~1005) 24 993, Bit8 (969~989) 21 979,
2754 13:40:17.540030 TX Bit1 (980~1002) 23 991, Bit9 (970~987) 18 978,
2755 13:40:17.546719 TX Bit2 (979~1001) 23 990, Bit10 (972~992) 21 982,
2756 13:40:17.549594 TX Bit3 (978~999) 22 988, Bit11 (972~992) 21 982,
2757 13:40:17.553267 TX Bit4 (981~1004) 24 992, Bit12 (972~993) 22 982,
2758 13:40:17.559702 TX Bit5 (983~1004) 22 993, Bit13 (973~992) 20 982,
2759 13:40:17.563069 TX Bit6 (981~1003) 23 992, Bit14 (971~992) 22 981,
2760 13:40:17.569637 TX Bit7 (982~1002) 21 992, Bit15 (967~986) 20 976,
2761 13:40:17.569782
2762 13:40:17.569886 Write Rank0 MR14 =0x14
2763 13:40:17.580850
2764 13:40:17.584045 CH=1, VrefRange= 0, VrefLevel = 20
2765 13:40:17.587625 TX Bit0 (982~1006) 25 994, Bit8 (969~989) 21 979,
2766 13:40:17.590301 TX Bit1 (980~1003) 24 991, Bit9 (969~988) 20 978,
2767 13:40:17.597421 TX Bit2 (979~1002) 24 990, Bit10 (970~992) 23 981,
2768 13:40:17.600193 TX Bit3 (978~999) 22 988, Bit11 (972~992) 21 982,
2769 13:40:17.603913 TX Bit4 (980~1004) 25 992, Bit12 (971~993) 23 982,
2770 13:40:17.610526 TX Bit5 (983~1004) 22 993, Bit13 (973~992) 20 982,
2771 13:40:17.613561 TX Bit6 (981~1003) 23 992, Bit14 (971~993) 23 982,
2772 13:40:17.620435 TX Bit7 (981~1003) 23 992, Bit15 (967~986) 20 976,
2773 13:40:17.620550
2774 13:40:17.620627 Write Rank0 MR14 =0x16
2775 13:40:17.631525
2776 13:40:17.634690 CH=1, VrefRange= 0, VrefLevel = 22
2777 13:40:17.638088 TX Bit0 (982~1006) 25 994, Bit8 (969~990) 22 979,
2778 13:40:17.641263 TX Bit1 (979~1003) 25 991, Bit9 (969~988) 20 978,
2779 13:40:17.648021 TX Bit2 (978~1003) 26 990, Bit10 (970~992) 23 981,
2780 13:40:17.650898 TX Bit3 (977~1000) 24 988, Bit11 (971~992) 22 981,
2781 13:40:17.657507 TX Bit4 (980~1005) 26 992, Bit12 (971~993) 23 982,
2782 13:40:17.661037 TX Bit5 (983~1005) 23 994, Bit13 (973~992) 20 982,
2783 13:40:17.664512 TX Bit6 (980~1004) 25 992, Bit14 (971~993) 23 982,
2784 13:40:17.671109 TX Bit7 (980~1004) 25 992, Bit15 (966~987) 22 976,
2785 13:40:17.671208
2786 13:40:17.671282 Write Rank0 MR14 =0x18
2787 13:40:17.682061
2788 13:40:17.685372 CH=1, VrefRange= 0, VrefLevel = 24
2789 13:40:17.688563 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2790 13:40:17.692376 TX Bit1 (980~1004) 25 992, Bit9 (968~989) 22 978,
2791 13:40:17.698536 TX Bit2 (978~1003) 26 990, Bit10 (970~992) 23 981,
2792 13:40:17.702354 TX Bit3 (977~1000) 24 988, Bit11 (971~993) 23 982,
2793 13:40:17.705210 TX Bit4 (979~1005) 27 992, Bit12 (971~994) 24 982,
2794 13:40:17.712043 TX Bit5 (982~1006) 25 994, Bit13 (972~993) 22 982,
2795 13:40:17.715598 TX Bit6 (980~1005) 26 992, Bit14 (970~993) 24 981,
2796 13:40:17.721690 TX Bit7 (981~1004) 24 992, Bit15 (967~987) 21 977,
2797 13:40:17.721786
2798 13:40:17.721860 Write Rank0 MR14 =0x1a
2799 13:40:17.733290
2800 13:40:17.736627 CH=1, VrefRange= 0, VrefLevel = 26
2801 13:40:17.739945 TX Bit0 (981~1006) 26 993, Bit8 (969~991) 23 980,
2802 13:40:17.743250 TX Bit1 (979~1004) 26 991, Bit9 (969~990) 22 979,
2803 13:40:17.749924 TX Bit2 (978~1004) 27 991, Bit10 (970~993) 24 981,
2804 13:40:17.753088 TX Bit3 (977~1000) 24 988, Bit11 (971~993) 23 982,
2805 13:40:17.756118 TX Bit4 (979~1006) 28 992, Bit12 (970~994) 25 982,
2806 13:40:17.762822 TX Bit5 (982~1006) 25 994, Bit13 (972~993) 22 982,
2807 13:40:17.766355 TX Bit6 (980~1005) 26 992, Bit14 (970~993) 24 981,
2808 13:40:17.772584 TX Bit7 (980~1004) 25 992, Bit15 (966~988) 23 977,
2809 13:40:17.772678
2810 13:40:17.772749 Write Rank0 MR14 =0x1c
2811 13:40:17.783744
2812 13:40:17.787034 CH=1, VrefRange= 0, VrefLevel = 28
2813 13:40:17.790867 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2814 13:40:17.793542 TX Bit1 (979~1006) 28 992, Bit9 (969~990) 22 979,
2815 13:40:17.800644 TX Bit2 (978~1003) 26 990, Bit10 (970~993) 24 981,
2816 13:40:17.803739 TX Bit3 (977~1001) 25 989, Bit11 (971~994) 24 982,
2817 13:40:17.807149 TX Bit4 (980~1006) 27 993, Bit12 (970~994) 25 982,
2818 13:40:17.813633 TX Bit5 (981~1006) 26 993, Bit13 (972~994) 23 983,
2819 13:40:17.817203 TX Bit6 (980~1006) 27 993, Bit14 (970~994) 25 982,
2820 13:40:17.823689 TX Bit7 (979~1005) 27 992, Bit15 (965~988) 24 976,
2821 13:40:17.823791
2822 13:40:17.823867 Write Rank0 MR14 =0x1e
2823 13:40:17.835023
2824 13:40:17.838149 CH=1, VrefRange= 0, VrefLevel = 30
2825 13:40:17.841478 TX Bit0 (980~1007) 28 993, Bit8 (968~992) 25 980,
2826 13:40:17.844647 TX Bit1 (979~1006) 28 992, Bit9 (969~990) 22 979,
2827 13:40:17.851090 TX Bit2 (978~1003) 26 990, Bit10 (970~994) 25 982,
2828 13:40:17.854442 TX Bit3 (977~1001) 25 989, Bit11 (970~994) 25 982,
2829 13:40:17.858257 TX Bit4 (980~1006) 27 993, Bit12 (970~994) 25 982,
2830 13:40:17.864503 TX Bit5 (981~1006) 26 993, Bit13 (971~994) 24 982,
2831 13:40:17.868231 TX Bit6 (979~1006) 28 992, Bit14 (970~993) 24 981,
2832 13:40:17.874710 TX Bit7 (979~1006) 28 992, Bit15 (965~987) 23 976,
2833 13:40:17.874800
2834 13:40:17.874870 Write Rank0 MR14 =0x20
2835 13:40:17.885925
2836 13:40:17.889030 CH=1, VrefRange= 0, VrefLevel = 32
2837 13:40:17.892279 TX Bit0 (981~1007) 27 994, Bit8 (968~992) 25 980,
2838 13:40:17.895532 TX Bit1 (979~1006) 28 992, Bit9 (968~991) 24 979,
2839 13:40:17.902553 TX Bit2 (978~1003) 26 990, Bit10 (970~993) 24 981,
2840 13:40:17.905736 TX Bit3 (977~1000) 24 988, Bit11 (970~994) 25 982,
2841 13:40:17.909114 TX Bit4 (980~1006) 27 993, Bit12 (970~993) 24 981,
2842 13:40:17.915677 TX Bit5 (980~1006) 27 993, Bit13 (971~994) 24 982,
2843 13:40:17.918797 TX Bit6 (979~1006) 28 992, Bit14 (970~993) 24 981,
2844 13:40:17.925330 TX Bit7 (979~1006) 28 992, Bit15 (965~987) 23 976,
2845 13:40:17.925477
2846 13:40:17.925550 Write Rank0 MR14 =0x22
2847 13:40:17.937185
2848 13:40:17.940028 CH=1, VrefRange= 0, VrefLevel = 34
2849 13:40:17.943399 TX Bit0 (981~1007) 27 994, Bit8 (968~992) 25 980,
2850 13:40:17.946826 TX Bit1 (979~1006) 28 992, Bit9 (968~991) 24 979,
2851 13:40:17.953457 TX Bit2 (978~1003) 26 990, Bit10 (970~993) 24 981,
2852 13:40:17.956760 TX Bit3 (977~1000) 24 988, Bit11 (970~994) 25 982,
2853 13:40:17.960141 TX Bit4 (980~1006) 27 993, Bit12 (970~993) 24 981,
2854 13:40:17.966770 TX Bit5 (980~1006) 27 993, Bit13 (971~994) 24 982,
2855 13:40:17.970035 TX Bit6 (979~1006) 28 992, Bit14 (970~993) 24 981,
2856 13:40:17.976522 TX Bit7 (979~1006) 28 992, Bit15 (965~987) 23 976,
2857 13:40:17.976621
2858 13:40:17.976693 Write Rank0 MR14 =0x24
2859 13:40:17.987630
2860 13:40:17.991274 CH=1, VrefRange= 0, VrefLevel = 36
2861 13:40:17.994418 TX Bit0 (981~1007) 27 994, Bit8 (968~992) 25 980,
2862 13:40:17.997387 TX Bit1 (979~1006) 28 992, Bit9 (968~991) 24 979,
2863 13:40:18.004537 TX Bit2 (978~1003) 26 990, Bit10 (970~993) 24 981,
2864 13:40:18.007741 TX Bit3 (977~1000) 24 988, Bit11 (970~994) 25 982,
2865 13:40:18.010868 TX Bit4 (980~1006) 27 993, Bit12 (970~993) 24 981,
2866 13:40:18.017509 TX Bit5 (980~1006) 27 993, Bit13 (971~994) 24 982,
2867 13:40:18.020802 TX Bit6 (979~1006) 28 992, Bit14 (970~993) 24 981,
2868 13:40:18.027070 TX Bit7 (979~1006) 28 992, Bit15 (965~987) 23 976,
2869 13:40:18.027161
2870 13:40:18.027233 Write Rank0 MR14 =0x26
2871 13:40:18.038637
2872 13:40:18.041819 CH=1, VrefRange= 0, VrefLevel = 38
2873 13:40:18.045120 TX Bit0 (981~1007) 27 994, Bit8 (968~992) 25 980,
2874 13:40:18.048420 TX Bit1 (979~1006) 28 992, Bit9 (968~991) 24 979,
2875 13:40:18.055011 TX Bit2 (978~1003) 26 990, Bit10 (970~993) 24 981,
2876 13:40:18.058501 TX Bit3 (977~1000) 24 988, Bit11 (970~994) 25 982,
2877 13:40:18.064798 TX Bit4 (980~1006) 27 993, Bit12 (970~993) 24 981,
2878 13:40:18.067981 TX Bit5 (980~1006) 27 993, Bit13 (971~994) 24 982,
2879 13:40:18.071736 TX Bit6 (979~1006) 28 992, Bit14 (970~993) 24 981,
2880 13:40:18.078455 TX Bit7 (979~1006) 28 992, Bit15 (965~987) 23 976,
2881 13:40:18.078558
2882 13:40:18.078638
2883 13:40:18.081579 TX Vref found, early break! 384< 387
2884 13:40:18.084868 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2885 13:40:18.088036 u1DelayCellOfst[0]=7 cells (6 PI)
2886 13:40:18.091408 u1DelayCellOfst[1]=5 cells (4 PI)
2887 13:40:18.094984 u1DelayCellOfst[2]=2 cells (2 PI)
2888 13:40:18.097919 u1DelayCellOfst[3]=0 cells (0 PI)
2889 13:40:18.101628 u1DelayCellOfst[4]=6 cells (5 PI)
2890 13:40:18.104607 u1DelayCellOfst[5]=6 cells (5 PI)
2891 13:40:18.108246 u1DelayCellOfst[6]=5 cells (4 PI)
2892 13:40:18.108339 u1DelayCellOfst[7]=5 cells (4 PI)
2893 13:40:18.111681 Byte0, DQ PI dly=988, DQM PI dly= 991
2894 13:40:18.117865 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2895 13:40:18.117987
2896 13:40:18.121172 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2897 13:40:18.121287
2898 13:40:18.124963 u1DelayCellOfst[8]=5 cells (4 PI)
2899 13:40:18.128307 u1DelayCellOfst[9]=3 cells (3 PI)
2900 13:40:18.131552 u1DelayCellOfst[10]=6 cells (5 PI)
2901 13:40:18.134724 u1DelayCellOfst[11]=7 cells (6 PI)
2902 13:40:18.137886 u1DelayCellOfst[12]=6 cells (5 PI)
2903 13:40:18.141530 u1DelayCellOfst[13]=7 cells (6 PI)
2904 13:40:18.144778 u1DelayCellOfst[14]=6 cells (5 PI)
2905 13:40:18.148083 u1DelayCellOfst[15]=0 cells (0 PI)
2906 13:40:18.151304 Byte1, DQ PI dly=976, DQM PI dly= 979
2907 13:40:18.154548 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
2908 13:40:18.154634
2909 13:40:18.157655 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
2910 13:40:18.157748
2911 13:40:18.161088 Write Rank0 MR14 =0x20
2912 13:40:18.161196
2913 13:40:18.164169 Final TX Range 0 Vref 32
2914 13:40:18.164285
2915 13:40:18.170801 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2916 13:40:18.170905
2917 13:40:18.177888 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2918 13:40:18.184253 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2919 13:40:18.190671 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2920 13:40:18.194570 Write Rank0 MR3 =0xb0
2921 13:40:18.194653 DramC Write-DBI on
2922 13:40:18.194729 ==
2923 13:40:18.200813 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2924 13:40:18.204499 fsp= 1, odt_onoff= 1, Byte mode= 0
2925 13:40:18.204579 ==
2926 13:40:18.207812 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2927 13:40:18.207903
2928 13:40:18.210877 Begin, DQ Scan Range 699~763
2929 13:40:18.210957
2930 13:40:18.211024
2931 13:40:18.211098 TX Vref Scan disable
2932 13:40:18.217382 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2933 13:40:18.220978 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2934 13:40:18.224556 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2935 13:40:18.227346 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2936 13:40:18.230673 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2937 13:40:18.234289 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2938 13:40:18.237408 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2939 13:40:18.240809 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2940 13:40:18.244653 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2941 13:40:18.247318 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2942 13:40:18.251139 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2943 13:40:18.254500 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2944 13:40:18.257770 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2945 13:40:18.261123 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2946 13:40:18.264236 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2947 13:40:18.267474 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2948 13:40:18.271304 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2949 13:40:18.274474 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2950 13:40:18.277594 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2951 13:40:18.280620 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2952 13:40:18.284162 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2953 13:40:18.290752 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2954 13:40:18.294124 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2955 13:40:18.297692 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2956 13:40:18.300972 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2957 13:40:18.304042 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2958 13:40:18.311024 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2959 13:40:18.314155 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2960 13:40:18.317720 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2961 13:40:18.320802 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2962 13:40:18.323970 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2963 13:40:18.327310 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2964 13:40:18.330533 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2965 13:40:18.334137 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2966 13:40:18.337093 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2967 13:40:18.340529 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2968 13:40:18.344291 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2969 13:40:18.347188 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
2970 13:40:18.350746 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
2971 13:40:18.353670 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
2972 13:40:18.357579 Byte0, DQ PI dly=737, DQM PI dly= 737
2973 13:40:18.363897 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
2974 13:40:18.363992
2975 13:40:18.367208 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
2976 13:40:18.367318
2977 13:40:18.370415 Byte1, DQ PI dly=724, DQM PI dly= 724
2978 13:40:18.374172 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2979 13:40:18.374256
2980 13:40:18.380708 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2981 13:40:18.380802
2982 13:40:18.387787 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2983 13:40:18.394470 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2984 13:40:18.400856 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2985 13:40:18.400941 Write Rank0 MR3 =0x30
2986 13:40:18.404387 DramC Write-DBI off
2987 13:40:18.404479
2988 13:40:18.404549 [DATLAT]
2989 13:40:18.407841 Freq=1600, CH1 RK0, use_rxtx_scan=0
2990 13:40:18.407923
2991 13:40:18.410982 DATLAT Default: 0xf
2992 13:40:18.411076 7, 0xFFFF, sum=0
2993 13:40:18.414358 8, 0xFFFF, sum=0
2994 13:40:18.414457 9, 0xFFFF, sum=0
2995 13:40:18.417706 10, 0xFFFF, sum=0
2996 13:40:18.417800 11, 0xFFFF, sum=0
2997 13:40:18.420740 12, 0xFFFF, sum=0
2998 13:40:18.420831 13, 0xFFFF, sum=0
2999 13:40:18.423819 14, 0x0, sum=1
3000 13:40:18.423901 15, 0x0, sum=2
3001 13:40:18.423975 16, 0x0, sum=3
3002 13:40:18.427388 17, 0x0, sum=4
3003 13:40:18.431009 pattern=2 first_step=14 total pass=5 best_step=16
3004 13:40:18.431092 ==
3005 13:40:18.437436 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3006 13:40:18.440650 fsp= 1, odt_onoff= 1, Byte mode= 0
3007 13:40:18.440749 ==
3008 13:40:18.443786 Start DQ dly to find pass range UseTestEngine =1
3009 13:40:18.447446 x-axis: bit #, y-axis: DQ dly (-127~63)
3010 13:40:18.450160 RX Vref Scan = 1
3011 13:40:18.556789
3012 13:40:18.556930 RX Vref found, early break!
3013 13:40:18.557003
3014 13:40:18.563330 Final RX Vref 11, apply to both rank0 and 1
3015 13:40:18.563445 ==
3016 13:40:18.566590 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3017 13:40:18.569841 fsp= 1, odt_onoff= 1, Byte mode= 0
3018 13:40:18.569923 ==
3019 13:40:18.569991 DQS Delay:
3020 13:40:18.573319 DQS0 = 0, DQS1 = 0
3021 13:40:18.573397 DQM Delay:
3022 13:40:18.576887 DQM0 = 21, DQM1 = 19
3023 13:40:18.576995 DQ Delay:
3024 13:40:18.580239 DQ0 =22, DQ1 =22, DQ2 =19, DQ3 =16
3025 13:40:18.584009 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
3026 13:40:18.586833 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3027 13:40:18.590164 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
3028 13:40:18.590248
3029 13:40:18.590316
3030 13:40:18.590380
3031 13:40:18.593506 [DramC_TX_OE_Calibration] TA2
3032 13:40:18.596640 Original DQ_B0 (3 6) =30, OEN = 27
3033 13:40:18.599992 Original DQ_B1 (3 6) =30, OEN = 27
3034 13:40:18.603311 23, 0x0, End_B0=23 End_B1=23
3035 13:40:18.603426 24, 0x0, End_B0=24 End_B1=24
3036 13:40:18.606696 25, 0x0, End_B0=25 End_B1=25
3037 13:40:18.609904 26, 0x0, End_B0=26 End_B1=26
3038 13:40:18.613129 27, 0x0, End_B0=27 End_B1=27
3039 13:40:18.616769 28, 0x0, End_B0=28 End_B1=28
3040 13:40:18.616881 29, 0x0, End_B0=29 End_B1=29
3041 13:40:18.619637 30, 0x0, End_B0=30 End_B1=30
3042 13:40:18.623295 31, 0xFFFF, End_B0=30 End_B1=30
3043 13:40:18.629735 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3044 13:40:18.633059 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3045 13:40:18.633152
3046 13:40:18.633223
3047 13:40:18.636460 Write Rank0 MR23 =0x3f
3048 13:40:18.636541 [DQSOSC]
3049 13:40:18.646050 [DQSOSCAuto] RK0, (LSB)MR18= 0xbcbc, (MSB)MR19= 0x202, tDQSOscB0 = 450 ps tDQSOscB1 = 450 ps
3050 13:40:18.653155 CH1_RK0: MR19=0x202, MR18=0xBCBC, DQSOSC=450, MR23=63, INC=12, DEC=18
3051 13:40:18.653253 Write Rank0 MR23 =0x3f
3052 13:40:18.653325 [DQSOSC]
3053 13:40:18.662792 [DQSOSCAuto] RK0, (LSB)MR18= 0xbebe, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3054 13:40:18.666030 CH1 RK0: MR19=202, MR18=BEBE
3055 13:40:18.669304 [RankSwap] Rank num 2, (Multi 1), Rank 1
3056 13:40:18.669422 Write Rank0 MR2 =0xad
3057 13:40:18.672567 [Write Leveling]
3058 13:40:18.676493 delay byte0 byte1 byte2 byte3
3059 13:40:18.676573
3060 13:40:18.676640 10 0 0
3061 13:40:18.679754 11 0 0
3062 13:40:18.679836 12 0 0
3063 13:40:18.679905 13 0 0
3064 13:40:18.683017 14 0 0
3065 13:40:18.683109 15 0 0
3066 13:40:18.686157 16 0 0
3067 13:40:18.686252 17 0 0
3068 13:40:18.689255 18 0 0
3069 13:40:18.689346 19 0 0
3070 13:40:18.689418 20 0 0
3071 13:40:18.692710 21 0 0
3072 13:40:18.692813 22 0 0
3073 13:40:18.696195 23 0 0
3074 13:40:18.696287 24 0 ff
3075 13:40:18.696358 25 0 ff
3076 13:40:18.699559 26 0 ff
3077 13:40:18.699652 27 0 ff
3078 13:40:18.702431 28 0 ff
3079 13:40:18.702521 29 0 ff
3080 13:40:18.706234 30 0 ff
3081 13:40:18.706327 31 0 ff
3082 13:40:18.709483 32 0 ff
3083 13:40:18.709566 33 0 ff
3084 13:40:18.709635 34 ff ff
3085 13:40:18.712724 35 ff ff
3086 13:40:18.712807 36 ff ff
3087 13:40:18.715847 37 ff ff
3088 13:40:18.715926 38 ff ff
3089 13:40:18.719176 39 ff ff
3090 13:40:18.719264 40 ff ff
3091 13:40:18.726017 pass bytecount = 0xff (0xff: all bytes pass)
3092 13:40:18.726099
3093 13:40:18.726175 DQS0 dly: 34
3094 13:40:18.726244 DQS1 dly: 24
3095 13:40:18.729305 Write Rank0 MR2 =0x2d
3096 13:40:18.732439 [RankSwap] Rank num 2, (Multi 1), Rank 0
3097 13:40:18.736172 Write Rank1 MR1 =0xd6
3098 13:40:18.736256 [Gating]
3099 13:40:18.736345 ==
3100 13:40:18.739380 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3101 13:40:18.742657 fsp= 1, odt_onoff= 1, Byte mode= 0
3102 13:40:18.742746 ==
3103 13:40:18.749266 3 1 0 |3636 2c2b |(10 10)(11 11) |(0 0)(1 1)| 0
3104 13:40:18.752575 3 1 4 |1413 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3105 13:40:18.755762 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3106 13:40:18.762318 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3107 13:40:18.765687 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3108 13:40:18.769259 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3109 13:40:18.775675 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3110 13:40:18.778834 3 1 28 |b0a 2c2b |(1 1)(11 11) |(0 1)(1 0)| 0
3111 13:40:18.782002 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3112 13:40:18.785799 3 2 4 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3113 13:40:18.792353 3 2 8 |3737 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3114 13:40:18.795593 3 2 12 |3d3d 2c2c |(11 11)(11 10) |(1 1)(0 0)| 0
3115 13:40:18.798749 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3116 13:40:18.805755 3 2 20 |3d3d 3534 |(0 0)(11 11) |(1 1)(0 0)| 0
3117 13:40:18.808679 3 2 24 |3c3b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3118 13:40:18.812246 3 2 28 |3c3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3119 13:40:18.818623 3 3 0 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3120 13:40:18.822251 3 3 4 |3c3c 3534 |(10 10)(11 11) |(1 1)(0 0)| 0
3121 13:40:18.825383 3 3 8 |505 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3122 13:40:18.831881 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3123 13:40:18.835178 [Byte 0] Lead/lag falling Transition (3, 3, 12)
3124 13:40:18.838364 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3125 13:40:18.845064 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3126 13:40:18.848335 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3127 13:40:18.851370 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3128 13:40:18.858539 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3129 13:40:18.861578 3 4 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3130 13:40:18.864639 3 4 8 |1211 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3131 13:40:18.867910 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3132 13:40:18.874515 3 4 16 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3133 13:40:18.877931 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3134 13:40:18.881451 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3135 13:40:18.887718 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3136 13:40:18.890970 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3137 13:40:18.894838 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3138 13:40:18.901434 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3139 13:40:18.904604 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3140 13:40:18.907776 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3141 13:40:18.914305 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3142 13:40:18.917503 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3143 13:40:18.920732 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3144 13:40:18.927376 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3145 13:40:18.931138 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3146 13:40:18.934437 [Byte 0] Lead/lag Transition tap number (3)
3147 13:40:18.937834 3 6 4 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3148 13:40:18.944124 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3149 13:40:18.947319 3 6 8 |c0c 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3150 13:40:18.950865 [Byte 1] Lead/lag Transition tap number (2)
3151 13:40:18.954043 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
3152 13:40:18.957287 [Byte 0]First pass (3, 6, 12)
3153 13:40:18.960584 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3154 13:40:18.967720 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3155 13:40:18.967826 [Byte 1]First pass (3, 6, 20)
3156 13:40:18.973990 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3157 13:40:18.977268 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3158 13:40:18.980471 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3159 13:40:18.984170 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3160 13:40:18.987651 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3161 13:40:18.993970 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3162 13:40:18.997523 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3163 13:40:19.000975 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3164 13:40:19.004220 All bytes gating window > 1UI, Early break!
3165 13:40:19.004308
3166 13:40:19.007323 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 30)
3167 13:40:19.007413
3168 13:40:19.013860 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3169 13:40:19.013947
3170 13:40:19.014021
3171 13:40:19.014090
3172 13:40:19.017099 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3173 13:40:19.017187
3174 13:40:19.020148 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3175 13:40:19.020232
3176 13:40:19.020328
3177 13:40:19.024123 Write Rank1 MR1 =0x56
3178 13:40:19.024205
3179 13:40:19.027331 best RODT dly(2T, 0.5T) = (2, 2)
3180 13:40:19.027445
3181 13:40:19.030737 best RODT dly(2T, 0.5T) = (2, 3)
3182 13:40:19.030839 ==
3183 13:40:19.033965 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3184 13:40:19.037238 fsp= 1, odt_onoff= 1, Byte mode= 0
3185 13:40:19.037330 ==
3186 13:40:19.043567 Start DQ dly to find pass range UseTestEngine =0
3187 13:40:19.047167 x-axis: bit #, y-axis: DQ dly (-127~63)
3188 13:40:19.047256 RX Vref Scan = 0
3189 13:40:19.050759 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3190 13:40:19.053742 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3191 13:40:19.057188 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3192 13:40:19.060530 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3193 13:40:19.060616 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3194 13:40:19.063640 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3195 13:40:19.066981 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3196 13:40:19.070443 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3197 13:40:19.073753 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3198 13:40:19.077108 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3199 13:40:19.080384 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3200 13:40:19.083637 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3201 13:40:19.086887 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3202 13:40:19.087010 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3203 13:40:19.090012 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3204 13:40:19.093735 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3205 13:40:19.096991 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3206 13:40:19.100077 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3207 13:40:19.103748 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3208 13:40:19.106683 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3209 13:40:19.106786 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3210 13:40:19.110125 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3211 13:40:19.113664 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3212 13:40:19.116829 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3213 13:40:19.119989 -2, [0] xxxxxxxx xxxxxxxo [MSB]
3214 13:40:19.123803 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3215 13:40:19.126989 0, [0] xxooxxxx ooxxxxxo [MSB]
3216 13:40:19.127075 1, [0] xxooxxxx ooxxxxxo [MSB]
3217 13:40:19.130364 2, [0] xxooxxxo ooxxxxxo [MSB]
3218 13:40:19.133638 3, [0] xxooxxxo ooxxxxxo [MSB]
3219 13:40:19.136824 4, [0] oxoooxxo oooxoxxo [MSB]
3220 13:40:19.140087 32, [0] oooooooo ooooooox [MSB]
3221 13:40:19.143374 33, [0] oooooooo ooooooox [MSB]
3222 13:40:19.147119 34, [0] oooooooo ooooooox [MSB]
3223 13:40:19.147207 35, [0] oooxoooo xxooooox [MSB]
3224 13:40:19.150356 36, [0] oooxoooo xxooooox [MSB]
3225 13:40:19.153508 37, [0] ooxxoooo xxooooox [MSB]
3226 13:40:19.156643 38, [0] ooxxoooo xxooooox [MSB]
3227 13:40:19.159968 39, [0] oxxxxoox xxooooox [MSB]
3228 13:40:19.163227 40, [0] oxxxxoox xxxoooox [MSB]
3229 13:40:19.166360 41, [0] oxxxxoox xxxxxoox [MSB]
3230 13:40:19.166481 42, [0] oxxxxxxx xxxxxxxx [MSB]
3231 13:40:19.170018 43, [0] xxxxxxxx xxxxxxxx [MSB]
3232 13:40:19.172966 iDelay=43, Bit 0, Center 23 (4 ~ 42) 39
3233 13:40:19.176420 iDelay=43, Bit 1, Center 21 (5 ~ 38) 34
3234 13:40:19.179769 iDelay=43, Bit 2, Center 18 (0 ~ 36) 37
3235 13:40:19.186529 iDelay=43, Bit 3, Center 16 (-1 ~ 34) 36
3236 13:40:19.189686 iDelay=43, Bit 4, Center 21 (4 ~ 38) 35
3237 13:40:19.192846 iDelay=43, Bit 5, Center 23 (5 ~ 41) 37
3238 13:40:19.196609 iDelay=43, Bit 6, Center 23 (5 ~ 41) 37
3239 13:40:19.199758 iDelay=43, Bit 7, Center 20 (2 ~ 38) 37
3240 13:40:19.202957 iDelay=43, Bit 8, Center 17 (0 ~ 34) 35
3241 13:40:19.206409 iDelay=43, Bit 9, Center 16 (-1 ~ 34) 36
3242 13:40:19.209580 iDelay=43, Bit 10, Center 21 (4 ~ 39) 36
3243 13:40:19.213122 iDelay=43, Bit 11, Center 22 (5 ~ 40) 36
3244 13:40:19.216260 iDelay=43, Bit 12, Center 22 (4 ~ 40) 37
3245 13:40:19.219734 iDelay=43, Bit 13, Center 23 (5 ~ 41) 37
3246 13:40:19.223118 iDelay=43, Bit 14, Center 23 (5 ~ 41) 37
3247 13:40:19.226384 iDelay=43, Bit 15, Center 14 (-3 ~ 31) 35
3248 13:40:19.229552 ==
3249 13:40:19.233341 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3250 13:40:19.236605 fsp= 1, odt_onoff= 1, Byte mode= 0
3251 13:40:19.236701 ==
3252 13:40:19.236815 DQS Delay:
3253 13:40:19.239884 DQS0 = 0, DQS1 = 0
3254 13:40:19.239973 DQM Delay:
3255 13:40:19.243110 DQM0 = 20, DQM1 = 19
3256 13:40:19.243224 DQ Delay:
3257 13:40:19.246494 DQ0 =23, DQ1 =21, DQ2 =18, DQ3 =16
3258 13:40:19.249790 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3259 13:40:19.252999 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3260 13:40:19.256320 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =14
3261 13:40:19.256428
3262 13:40:19.256499
3263 13:40:19.260030 DramC Write-DBI off
3264 13:40:19.260150 ==
3265 13:40:19.263081 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3266 13:40:19.266446 fsp= 1, odt_onoff= 1, Byte mode= 0
3267 13:40:19.266543 ==
3268 13:40:19.269558 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3269 13:40:19.273451
3270 13:40:19.273551 Begin, DQ Scan Range 920~1176
3271 13:40:19.273627
3272 13:40:19.273693
3273 13:40:19.276652 TX Vref Scan disable
3274 13:40:19.279739 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
3275 13:40:19.283627 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3276 13:40:19.286523 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3277 13:40:19.289757 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3278 13:40:19.293144 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3279 13:40:19.296500 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3280 13:40:19.299383 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3281 13:40:19.306187 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3282 13:40:19.309433 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3283 13:40:19.312665 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3284 13:40:19.315937 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3285 13:40:19.319858 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3286 13:40:19.322971 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3287 13:40:19.326023 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3288 13:40:19.329518 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3289 13:40:19.332776 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3290 13:40:19.336093 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3291 13:40:19.339504 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3292 13:40:19.342599 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3293 13:40:19.345879 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3294 13:40:19.349107 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3295 13:40:19.355534 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3296 13:40:19.359361 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3297 13:40:19.362524 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3298 13:40:19.365669 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3299 13:40:19.368898 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3300 13:40:19.372278 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3301 13:40:19.375487 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3302 13:40:19.378900 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3303 13:40:19.382122 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3304 13:40:19.385317 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3305 13:40:19.388936 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3306 13:40:19.392009 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3307 13:40:19.395813 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3308 13:40:19.399066 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3309 13:40:19.402231 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3310 13:40:19.408770 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3311 13:40:19.412061 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3312 13:40:19.415542 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3313 13:40:19.418628 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3314 13:40:19.421805 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3315 13:40:19.425060 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3316 13:40:19.428372 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3317 13:40:19.432316 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3318 13:40:19.435474 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3319 13:40:19.438655 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3320 13:40:19.441632 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3321 13:40:19.445126 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3322 13:40:19.448577 968 |3 6 8|[0] xxxxxxxx oxxxxxxo [MSB]
3323 13:40:19.451948 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3324 13:40:19.455218 970 |3 6 10|[0] xxxxxxxx oooxoxoo [MSB]
3325 13:40:19.458683 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3326 13:40:19.461749 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3327 13:40:19.464965 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3328 13:40:19.468815 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3329 13:40:19.475039 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3330 13:40:19.478457 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3331 13:40:19.481663 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3332 13:40:19.485022 978 |3 6 18|[0] xxoooxxx oooooooo [MSB]
3333 13:40:19.488758 979 |3 6 19|[0] xooooxox oooooooo [MSB]
3334 13:40:19.491931 985 |3 6 25|[0] oooooooo ooooooox [MSB]
3335 13:40:19.495343 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3336 13:40:19.498396 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3337 13:40:19.501626 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
3338 13:40:19.505516 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
3339 13:40:19.508626 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3340 13:40:19.511876 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3341 13:40:19.514881 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3342 13:40:19.521859 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3343 13:40:19.524844 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3344 13:40:19.527975 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3345 13:40:19.531848 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3346 13:40:19.535016 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
3347 13:40:19.538442 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3348 13:40:19.541722 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3349 13:40:19.544869 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
3350 13:40:19.547986 1001 |3 6 41|[0] oxxxxoxx xxxxxxxx [MSB]
3351 13:40:19.551198 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
3352 13:40:19.554546 Byte0, DQ PI dly=988, DQM PI dly= 988
3353 13:40:19.561468 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3354 13:40:19.561583
3355 13:40:19.564626 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3356 13:40:19.564712
3357 13:40:19.567814 Byte1, DQ PI dly=977, DQM PI dly= 977
3358 13:40:19.570847 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3359 13:40:19.570962
3360 13:40:19.577452 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3361 13:40:19.577546
3362 13:40:19.577617 ==
3363 13:40:19.580980 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3364 13:40:19.584739 fsp= 1, odt_onoff= 1, Byte mode= 0
3365 13:40:19.584859 ==
3366 13:40:19.591255 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3367 13:40:19.591373
3368 13:40:19.594517 Begin, DQ Scan Range 953~1017
3369 13:40:19.594633 Write Rank1 MR14 =0x0
3370 13:40:19.603906
3371 13:40:19.604022 CH=1, VrefRange= 0, VrefLevel = 0
3372 13:40:19.610444 TX Bit0 (982~998) 17 990, Bit8 (970~984) 15 977,
3373 13:40:19.613627 TX Bit1 (981~996) 16 988, Bit9 (970~984) 15 977,
3374 13:40:19.620361 TX Bit2 (979~993) 15 986, Bit10 (973~985) 13 979,
3375 13:40:19.623549 TX Bit3 (978~991) 14 984, Bit11 (975~986) 12 980,
3376 13:40:19.626854 TX Bit4 (981~996) 16 988, Bit12 (975~984) 10 979,
3377 13:40:19.633471 TX Bit5 (983~998) 16 990, Bit13 (975~986) 12 980,
3378 13:40:19.636423 TX Bit6 (981~997) 17 989, Bit14 (975~984) 10 979,
3379 13:40:19.639668 TX Bit7 (983~994) 12 988, Bit15 (969~978) 10 973,
3380 13:40:19.642863
3381 13:40:19.642953 Write Rank1 MR14 =0x2
3382 13:40:19.652601
3383 13:40:19.652689 CH=1, VrefRange= 0, VrefLevel = 2
3384 13:40:19.659682 TX Bit0 (982~998) 17 990, Bit8 (970~984) 15 977,
3385 13:40:19.662852 TX Bit1 (981~997) 17 989, Bit9 (970~984) 15 977,
3386 13:40:19.669304 TX Bit2 (978~994) 17 986, Bit10 (973~985) 13 979,
3387 13:40:19.672488 TX Bit3 (978~991) 14 984, Bit11 (974~986) 13 980,
3388 13:40:19.676214 TX Bit4 (981~996) 16 988, Bit12 (973~985) 13 979,
3389 13:40:19.682504 TX Bit5 (982~998) 17 990, Bit13 (974~987) 14 980,
3390 13:40:19.686002 TX Bit6 (982~997) 16 989, Bit14 (973~985) 13 979,
3391 13:40:19.689502 TX Bit7 (983~995) 13 989, Bit15 (968~978) 11 973,
3392 13:40:19.689623
3393 13:40:19.692354 Write Rank1 MR14 =0x4
3394 13:40:19.701732
3395 13:40:19.701820 CH=1, VrefRange= 0, VrefLevel = 4
3396 13:40:19.708811 TX Bit0 (982~999) 18 990, Bit8 (969~985) 17 977,
3397 13:40:19.712041 TX Bit1 (981~998) 18 989, Bit9 (970~984) 15 977,
3398 13:40:19.718398 TX Bit2 (978~995) 18 986, Bit10 (972~986) 15 979,
3399 13:40:19.721721 TX Bit3 (978~992) 15 985, Bit11 (974~987) 14 980,
3400 13:40:19.725015 TX Bit4 (980~997) 18 988, Bit12 (973~986) 14 979,
3401 13:40:19.731874 TX Bit5 (982~999) 18 990, Bit13 (974~988) 15 981,
3402 13:40:19.735052 TX Bit6 (980~998) 19 989, Bit14 (972~985) 14 978,
3403 13:40:19.738698 TX Bit7 (983~997) 15 990, Bit15 (968~980) 13 974,
3404 13:40:19.738785
3405 13:40:19.741754 Write Rank1 MR14 =0x6
3406 13:40:19.751445
3407 13:40:19.751534 CH=1, VrefRange= 0, VrefLevel = 6
3408 13:40:19.757983 TX Bit0 (981~999) 19 990, Bit8 (969~985) 17 977,
3409 13:40:19.761054 TX Bit1 (980~998) 19 989, Bit9 (970~985) 16 977,
3410 13:40:19.767597 TX Bit2 (978~996) 19 987, Bit10 (971~986) 16 978,
3411 13:40:19.770897 TX Bit3 (978~992) 15 985, Bit11 (974~988) 15 981,
3412 13:40:19.774697 TX Bit4 (980~998) 19 989, Bit12 (973~987) 15 980,
3413 13:40:19.781012 TX Bit5 (981~999) 19 990, Bit13 (973~989) 17 981,
3414 13:40:19.784093 TX Bit6 (980~999) 20 989, Bit14 (972~986) 15 979,
3415 13:40:19.787873 TX Bit7 (982~997) 16 989, Bit15 (967~981) 15 974,
3416 13:40:19.787962
3417 13:40:19.791101 Write Rank1 MR14 =0x8
3418 13:40:19.800719
3419 13:40:19.800823 CH=1, VrefRange= 0, VrefLevel = 8
3420 13:40:19.807292 TX Bit0 (981~1000) 20 990, Bit8 (969~985) 17 977,
3421 13:40:19.810753 TX Bit1 (980~998) 19 989, Bit9 (969~985) 17 977,
3422 13:40:19.817337 TX Bit2 (978~997) 20 987, Bit10 (972~987) 16 979,
3423 13:40:19.820434 TX Bit3 (977~993) 17 985, Bit11 (973~988) 16 980,
3424 13:40:19.824107 TX Bit4 (979~998) 20 988, Bit12 (973~987) 15 980,
3425 13:40:19.830445 TX Bit5 (981~1000) 20 990, Bit13 (972~990) 19 981,
3426 13:40:19.833595 TX Bit6 (980~999) 20 989, Bit14 (971~987) 17 979,
3427 13:40:19.837371 TX Bit7 (982~998) 17 990, Bit15 (967~982) 16 974,
3428 13:40:19.840427
3429 13:40:19.840539 Write Rank1 MR14 =0xa
3430 13:40:19.849962
3431 13:40:19.853195 CH=1, VrefRange= 0, VrefLevel = 10
3432 13:40:19.856422 TX Bit0 (980~1000) 21 990, Bit8 (969~986) 18 977,
3433 13:40:19.860357 TX Bit1 (980~999) 20 989, Bit9 (970~985) 16 977,
3434 13:40:19.866660 TX Bit2 (978~998) 21 988, Bit10 (971~988) 18 979,
3435 13:40:19.869901 TX Bit3 (977~994) 18 985, Bit11 (972~990) 19 981,
3436 13:40:19.873191 TX Bit4 (979~998) 20 988, Bit12 (972~988) 17 980,
3437 13:40:19.880221 TX Bit5 (981~1000) 20 990, Bit13 (972~990) 19 981,
3438 13:40:19.883394 TX Bit6 (980~999) 20 989, Bit14 (971~987) 17 979,
3439 13:40:19.889880 TX Bit7 (981~998) 18 989, Bit15 (967~983) 17 975,
3440 13:40:19.889989
3441 13:40:19.890063 Write Rank1 MR14 =0xc
3442 13:40:19.899944
3443 13:40:19.903298 CH=1, VrefRange= 0, VrefLevel = 12
3444 13:40:19.906393 TX Bit0 (980~1001) 22 990, Bit8 (969~986) 18 977,
3445 13:40:19.909674 TX Bit1 (979~999) 21 989, Bit9 (969~986) 18 977,
3446 13:40:19.916613 TX Bit2 (978~998) 21 988, Bit10 (971~988) 18 979,
3447 13:40:19.919842 TX Bit3 (977~995) 19 986, Bit11 (971~990) 20 980,
3448 13:40:19.923180 TX Bit4 (978~999) 22 988, Bit12 (971~989) 19 980,
3449 13:40:19.930121 TX Bit5 (980~1000) 21 990, Bit13 (972~991) 20 981,
3450 13:40:19.932875 TX Bit6 (980~999) 20 989, Bit14 (971~988) 18 979,
3451 13:40:19.939409 TX Bit7 (981~999) 19 990, Bit15 (966~983) 18 974,
3452 13:40:19.939502
3453 13:40:19.939573 Write Rank1 MR14 =0xe
3454 13:40:19.949709
3455 13:40:19.953471 CH=1, VrefRange= 0, VrefLevel = 14
3456 13:40:19.956778 TX Bit0 (980~1001) 22 990, Bit8 (968~986) 19 977,
3457 13:40:19.960046 TX Bit1 (979~1000) 22 989, Bit9 (969~986) 18 977,
3458 13:40:19.966564 TX Bit2 (978~998) 21 988, Bit10 (970~989) 20 979,
3459 13:40:19.969599 TX Bit3 (976~995) 20 985, Bit11 (971~991) 21 981,
3460 13:40:19.973401 TX Bit4 (978~999) 22 988, Bit12 (971~990) 20 980,
3461 13:40:19.979817 TX Bit5 (980~1001) 22 990, Bit13 (972~991) 20 981,
3462 13:40:19.983033 TX Bit6 (979~1000) 22 989, Bit14 (971~989) 19 980,
3463 13:40:19.989461 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3464 13:40:19.989558
3465 13:40:19.989636 Write Rank1 MR14 =0x10
3466 13:40:20.000099
3467 13:40:20.003346 CH=1, VrefRange= 0, VrefLevel = 16
3468 13:40:20.006584 TX Bit0 (979~1002) 24 990, Bit8 (968~987) 20 977,
3469 13:40:20.009797 TX Bit1 (978~1000) 23 989, Bit9 (969~987) 19 978,
3470 13:40:20.017096 TX Bit2 (977~999) 23 988, Bit10 (970~989) 20 979,
3471 13:40:20.020050 TX Bit3 (976~997) 22 986, Bit11 (971~991) 21 981,
3472 13:40:20.023284 TX Bit4 (978~999) 22 988, Bit12 (971~990) 20 980,
3473 13:40:20.029768 TX Bit5 (979~1001) 23 990, Bit13 (971~991) 21 981,
3474 13:40:20.033368 TX Bit6 (978~1000) 23 989, Bit14 (970~989) 20 979,
3475 13:40:20.040029 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
3476 13:40:20.040119
3477 13:40:20.040191 Write Rank1 MR14 =0x12
3478 13:40:20.050282
3479 13:40:20.053722 CH=1, VrefRange= 0, VrefLevel = 18
3480 13:40:20.057014 TX Bit0 (979~1002) 24 990, Bit8 (968~988) 21 978,
3481 13:40:20.060400 TX Bit1 (978~1000) 23 989, Bit9 (969~987) 19 978,
3482 13:40:20.067233 TX Bit2 (977~999) 23 988, Bit10 (970~990) 21 980,
3483 13:40:20.069879 TX Bit3 (976~997) 22 986, Bit11 (971~991) 21 981,
3484 13:40:20.073654 TX Bit4 (978~1000) 23 989, Bit12 (970~991) 22 980,
3485 13:40:20.080098 TX Bit5 (979~1002) 24 990, Bit13 (971~991) 21 981,
3486 13:40:20.083318 TX Bit6 (978~1001) 24 989, Bit14 (970~990) 21 980,
3487 13:40:20.089968 TX Bit7 (980~1000) 21 990, Bit15 (965~985) 21 975,
3488 13:40:20.090072
3489 13:40:20.090146 Write Rank1 MR14 =0x14
3490 13:40:20.100730
3491 13:40:20.104545 CH=1, VrefRange= 0, VrefLevel = 20
3492 13:40:20.107332 TX Bit0 (979~1003) 25 991, Bit8 (968~988) 21 978,
3493 13:40:20.111030 TX Bit1 (978~1001) 24 989, Bit9 (968~988) 21 978,
3494 13:40:20.117669 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
3495 13:40:20.120871 TX Bit3 (976~998) 23 987, Bit11 (970~991) 22 980,
3496 13:40:20.123977 TX Bit4 (978~1001) 24 989, Bit12 (970~991) 22 980,
3497 13:40:20.130467 TX Bit5 (979~1002) 24 990, Bit13 (971~992) 22 981,
3498 13:40:20.134467 TX Bit6 (978~1001) 24 989, Bit14 (970~991) 22 980,
3499 13:40:20.140734 TX Bit7 (979~1000) 22 989, Bit15 (965~985) 21 975,
3500 13:40:20.140824
3501 13:40:20.140896 Write Rank1 MR14 =0x16
3502 13:40:20.151336
3503 13:40:20.154751 CH=1, VrefRange= 0, VrefLevel = 22
3504 13:40:20.158479 TX Bit0 (979~1003) 25 991, Bit8 (967~989) 23 978,
3505 13:40:20.161552 TX Bit1 (978~1001) 24 989, Bit9 (968~989) 22 978,
3506 13:40:20.168385 TX Bit2 (977~1000) 24 988, Bit10 (969~991) 23 980,
3507 13:40:20.171438 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3508 13:40:20.174858 TX Bit4 (978~1001) 24 989, Bit12 (971~991) 21 981,
3509 13:40:20.181308 TX Bit5 (979~1003) 25 991, Bit13 (971~992) 22 981,
3510 13:40:20.184897 TX Bit6 (978~1002) 25 990, Bit14 (970~991) 22 980,
3511 13:40:20.191486 TX Bit7 (979~1000) 22 989, Bit15 (964~985) 22 974,
3512 13:40:20.191611
3513 13:40:20.191716 Write Rank1 MR14 =0x18
3514 13:40:20.202270
3515 13:40:20.205450 CH=1, VrefRange= 0, VrefLevel = 24
3516 13:40:20.208789 TX Bit0 (978~1003) 26 990, Bit8 (967~990) 24 978,
3517 13:40:20.211868 TX Bit1 (978~1002) 25 990, Bit9 (968~989) 22 978,
3518 13:40:20.218853 TX Bit2 (977~1000) 24 988, Bit10 (969~991) 23 980,
3519 13:40:20.222099 TX Bit3 (975~998) 24 986, Bit11 (970~992) 23 981,
3520 13:40:20.225264 TX Bit4 (977~1002) 26 989, Bit12 (970~992) 23 981,
3521 13:40:20.232115 TX Bit5 (978~1003) 26 990, Bit13 (970~992) 23 981,
3522 13:40:20.235549 TX Bit6 (978~1002) 25 990, Bit14 (969~991) 23 980,
3523 13:40:20.241819 TX Bit7 (979~1001) 23 990, Bit15 (963~986) 24 974,
3524 13:40:20.241936
3525 13:40:20.242028 Write Rank1 MR14 =0x1a
3526 13:40:20.253385
3527 13:40:20.256586 CH=1, VrefRange= 0, VrefLevel = 26
3528 13:40:20.259646 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3529 13:40:20.263363 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
3530 13:40:20.269957 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
3531 13:40:20.272794 TX Bit3 (975~999) 25 987, Bit11 (970~992) 23 981,
3532 13:40:20.279893 TX Bit4 (978~1002) 25 990, Bit12 (970~992) 23 981,
3533 13:40:20.283042 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3534 13:40:20.286108 TX Bit6 (978~1002) 25 990, Bit14 (969~992) 24 980,
3535 13:40:20.293138 TX Bit7 (979~1002) 24 990, Bit15 (964~986) 23 975,
3536 13:40:20.293256
3537 13:40:20.293362 Write Rank1 MR14 =0x1c
3538 13:40:20.304351
3539 13:40:20.304467 CH=1, VrefRange= 0, VrefLevel = 28
3540 13:40:20.310767 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
3541 13:40:20.314054 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3542 13:40:20.320932 TX Bit2 (976~1001) 26 988, Bit10 (969~992) 24 980,
3543 13:40:20.324099 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3544 13:40:20.327442 TX Bit4 (978~1003) 26 990, Bit12 (970~992) 23 981,
3545 13:40:20.333851 TX Bit5 (978~1004) 27 991, Bit13 (970~993) 24 981,
3546 13:40:20.337202 TX Bit6 (977~1003) 27 990, Bit14 (969~992) 24 980,
3547 13:40:20.343477 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3548 13:40:20.343597
3549 13:40:20.343700 Write Rank1 MR14 =0x1e
3550 13:40:20.355574
3551 13:40:20.358721 CH=1, VrefRange= 0, VrefLevel = 30
3552 13:40:20.362016 TX Bit0 (978~1005) 28 991, Bit8 (968~990) 23 979,
3553 13:40:20.365262 TX Bit1 (977~1003) 27 990, Bit9 (967~990) 24 978,
3554 13:40:20.371569 TX Bit2 (976~1001) 26 988, Bit10 (969~992) 24 980,
3555 13:40:20.375026 TX Bit3 (974~999) 26 986, Bit11 (969~993) 25 981,
3556 13:40:20.378402 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
3557 13:40:20.384793 TX Bit5 (978~1004) 27 991, Bit13 (969~993) 25 981,
3558 13:40:20.388705 TX Bit6 (978~1004) 27 991, Bit14 (969~992) 24 980,
3559 13:40:20.395075 TX Bit7 (978~1002) 25 990, Bit15 (962~987) 26 974,
3560 13:40:20.395194
3561 13:40:20.395296 Write Rank1 MR14 =0x20
3562 13:40:20.406075
3563 13:40:20.409610 CH=1, VrefRange= 0, VrefLevel = 32
3564 13:40:20.412606 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3565 13:40:20.416011 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
3566 13:40:20.422924 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3567 13:40:20.426105 TX Bit3 (974~998) 25 986, Bit11 (969~992) 24 980,
3568 13:40:20.429469 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
3569 13:40:20.435878 TX Bit5 (979~1003) 25 991, Bit13 (969~993) 25 981,
3570 13:40:20.439646 TX Bit6 (978~1003) 26 990, Bit14 (969~993) 25 981,
3571 13:40:20.446024 TX Bit7 (978~1003) 26 990, Bit15 (962~987) 26 974,
3572 13:40:20.446145
3573 13:40:20.446247 Write Rank1 MR14 =0x22
3574 13:40:20.457033
3575 13:40:20.460058 CH=1, VrefRange= 0, VrefLevel = 34
3576 13:40:20.463842 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3577 13:40:20.467091 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
3578 13:40:20.473624 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3579 13:40:20.476861 TX Bit3 (974~998) 25 986, Bit11 (969~992) 24 980,
3580 13:40:20.480095 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
3581 13:40:20.487050 TX Bit5 (979~1003) 25 991, Bit13 (969~993) 25 981,
3582 13:40:20.489941 TX Bit6 (978~1003) 26 990, Bit14 (969~993) 25 981,
3583 13:40:20.496490 TX Bit7 (978~1003) 26 990, Bit15 (962~987) 26 974,
3584 13:40:20.496615
3585 13:40:20.496719 Write Rank1 MR14 =0x24
3586 13:40:20.507804
3587 13:40:20.510908 CH=1, VrefRange= 0, VrefLevel = 36
3588 13:40:20.514505 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3589 13:40:20.517530 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
3590 13:40:20.524528 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3591 13:40:20.527416 TX Bit3 (974~998) 25 986, Bit11 (969~992) 24 980,
3592 13:40:20.531247 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
3593 13:40:20.537703 TX Bit5 (979~1003) 25 991, Bit13 (969~993) 25 981,
3594 13:40:20.540910 TX Bit6 (978~1003) 26 990, Bit14 (969~993) 25 981,
3595 13:40:20.547397 TX Bit7 (978~1003) 26 990, Bit15 (962~987) 26 974,
3596 13:40:20.547636
3597 13:40:20.547788 Write Rank1 MR14 =0x26
3598 13:40:20.558948
3599 13:40:20.562152 CH=1, VrefRange= 0, VrefLevel = 38
3600 13:40:20.565223 TX Bit0 (978~1005) 28 991, Bit8 (967~990) 24 978,
3601 13:40:20.568376 TX Bit1 (978~1003) 26 990, Bit9 (967~990) 24 978,
3602 13:40:20.575285 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3603 13:40:20.578564 TX Bit3 (974~998) 25 986, Bit11 (969~992) 24 980,
3604 13:40:20.581753 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
3605 13:40:20.588689 TX Bit5 (979~1003) 25 991, Bit13 (969~993) 25 981,
3606 13:40:20.591781 TX Bit6 (978~1003) 26 990, Bit14 (969~993) 25 981,
3607 13:40:20.598200 TX Bit7 (978~1003) 26 990, Bit15 (962~987) 26 974,
3608 13:40:20.598322
3609 13:40:20.598425
3610 13:40:20.601784 TX Vref found, early break! 378< 383
3611 13:40:20.605205 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3612 13:40:20.608611 u1DelayCellOfst[0]=6 cells (5 PI)
3613 13:40:20.611587 u1DelayCellOfst[1]=5 cells (4 PI)
3614 13:40:20.615463 u1DelayCellOfst[2]=3 cells (3 PI)
3615 13:40:20.618702 u1DelayCellOfst[3]=0 cells (0 PI)
3616 13:40:20.621708 u1DelayCellOfst[4]=5 cells (4 PI)
3617 13:40:20.624941 u1DelayCellOfst[5]=6 cells (5 PI)
3618 13:40:20.628745 u1DelayCellOfst[6]=5 cells (4 PI)
3619 13:40:20.628873 u1DelayCellOfst[7]=5 cells (4 PI)
3620 13:40:20.631866 Byte0, DQ PI dly=986, DQM PI dly= 988
3621 13:40:20.638465 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3622 13:40:20.638597
3623 13:40:20.641994 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3624 13:40:20.642111
3625 13:40:20.644918 u1DelayCellOfst[8]=5 cells (4 PI)
3626 13:40:20.648152 u1DelayCellOfst[9]=5 cells (4 PI)
3627 13:40:20.651876 u1DelayCellOfst[10]=7 cells (6 PI)
3628 13:40:20.655046 u1DelayCellOfst[11]=7 cells (6 PI)
3629 13:40:20.658354 u1DelayCellOfst[12]=9 cells (7 PI)
3630 13:40:20.661619 u1DelayCellOfst[13]=9 cells (7 PI)
3631 13:40:20.664926 u1DelayCellOfst[14]=9 cells (7 PI)
3632 13:40:20.668124 u1DelayCellOfst[15]=0 cells (0 PI)
3633 13:40:20.671875 Byte1, DQ PI dly=974, DQM PI dly= 977
3634 13:40:20.675018 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
3635 13:40:20.675141
3636 13:40:20.678284 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
3637 13:40:20.678402
3638 13:40:20.681600 Write Rank1 MR14 =0x20
3639 13:40:20.681715
3640 13:40:20.684731 Final TX Range 0 Vref 32
3641 13:40:20.684841
3642 13:40:20.691398 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3643 13:40:20.691499
3644 13:40:20.698419 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3645 13:40:20.704852 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3646 13:40:20.711322 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3647 13:40:20.711450 Write Rank1 MR3 =0xb0
3648 13:40:20.714946 DramC Write-DBI on
3649 13:40:20.715062 ==
3650 13:40:20.721256 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3651 13:40:20.721376 fsp= 1, odt_onoff= 1, Byte mode= 0
3652 13:40:20.724818 ==
3653 13:40:20.727871 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3654 13:40:20.727989
3655 13:40:20.731384 Begin, DQ Scan Range 697~761
3656 13:40:20.731483
3657 13:40:20.731554
3658 13:40:20.731635 TX Vref Scan disable
3659 13:40:20.734981 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3660 13:40:20.738242 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3661 13:40:20.745043 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3662 13:40:20.747898 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3663 13:40:20.751467 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3664 13:40:20.754472 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3665 13:40:20.757926 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3666 13:40:20.761687 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3667 13:40:20.764871 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3668 13:40:20.768145 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3669 13:40:20.771255 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3670 13:40:20.774412 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3671 13:40:20.777555 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3672 13:40:20.781160 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3673 13:40:20.784284 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3674 13:40:20.788043 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3675 13:40:20.791429 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3676 13:40:20.794632 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3677 13:40:20.797352 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3678 13:40:20.800697 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3679 13:40:20.804044 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3680 13:40:20.811197 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3681 13:40:20.814414 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3682 13:40:20.817597 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3683 13:40:20.820784 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3684 13:40:20.824271 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3685 13:40:20.827732 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3686 13:40:20.834218 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3687 13:40:20.837588 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3688 13:40:20.841029 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3689 13:40:20.844095 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3690 13:40:20.847872 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3691 13:40:20.851094 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3692 13:40:20.854098 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3693 13:40:20.857669 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3694 13:40:20.860819 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3695 13:40:20.864465 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3696 13:40:20.867601 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3697 13:40:20.870650 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3698 13:40:20.873895 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3699 13:40:20.877761 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3700 13:40:20.880972 Byte0, DQ PI dly=736, DQM PI dly= 736
3701 13:40:20.887799 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3702 13:40:20.887922
3703 13:40:20.890647 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3704 13:40:20.890763
3705 13:40:20.893831 Byte1, DQ PI dly=723, DQM PI dly= 723
3706 13:40:20.897552 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3707 13:40:20.897669
3708 13:40:20.904048 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3709 13:40:20.904141
3710 13:40:20.910476 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3711 13:40:20.917405 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3712 13:40:20.923984 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3713 13:40:20.927197 Write Rank1 MR3 =0x30
3714 13:40:20.927315 DramC Write-DBI off
3715 13:40:20.927434
3716 13:40:20.927541 [DATLAT]
3717 13:40:20.930368 Freq=1600, CH1 RK1, use_rxtx_scan=0
3718 13:40:20.930483
3719 13:40:20.934078 DATLAT Default: 0x10
3720 13:40:20.937058 7, 0xFFFF, sum=0
3721 13:40:20.937144 8, 0xFFFF, sum=0
3722 13:40:20.937222 9, 0xFFFF, sum=0
3723 13:40:20.940781 10, 0xFFFF, sum=0
3724 13:40:20.940876 11, 0xFFFF, sum=0
3725 13:40:20.943829 12, 0xFFFF, sum=0
3726 13:40:20.943951 13, 0xFFFF, sum=0
3727 13:40:20.946916 14, 0x0, sum=1
3728 13:40:20.947036 15, 0x0, sum=2
3729 13:40:20.950400 16, 0x0, sum=3
3730 13:40:20.950490 17, 0x0, sum=4
3731 13:40:20.953954 pattern=2 first_step=14 total pass=5 best_step=16
3732 13:40:20.954068 ==
3733 13:40:20.960512 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3734 13:40:20.963438 fsp= 1, odt_onoff= 1, Byte mode= 0
3735 13:40:20.963557 ==
3736 13:40:20.966867 Start DQ dly to find pass range UseTestEngine =1
3737 13:40:20.970651 x-axis: bit #, y-axis: DQ dly (-127~63)
3738 13:40:20.973711 RX Vref Scan = 0
3739 13:40:20.977338 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3740 13:40:20.980478 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3741 13:40:20.980599 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3742 13:40:20.983821 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3743 13:40:20.987191 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3744 13:40:20.990494 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3745 13:40:20.993706 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3746 13:40:20.997392 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3747 13:40:21.000310 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3748 13:40:21.003845 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3749 13:40:21.003933 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3750 13:40:21.006921 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3751 13:40:21.010280 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3752 13:40:21.013472 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3753 13:40:21.016712 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3754 13:40:21.020602 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3755 13:40:21.023846 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3756 13:40:21.027093 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3757 13:40:21.030376 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3758 13:40:21.030496 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3759 13:40:21.033675 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3760 13:40:21.036962 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3761 13:40:21.040088 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3762 13:40:21.043721 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3763 13:40:21.047223 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3764 13:40:21.050364 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3765 13:40:21.050486 0, [0] xxooxxxx ooxxxxxo [MSB]
3766 13:40:21.053374 1, [0] xxooxxxx ooxxxxxo [MSB]
3767 13:40:21.056534 2, [0] xxooxxxx ooxxxxxo [MSB]
3768 13:40:21.060312 3, [0] xxooxxxo ooxxxxxo [MSB]
3769 13:40:21.063384 4, [0] oooooxxo ooooooxo [MSB]
3770 13:40:21.066417 5, [0] ooooooxo oooooooo [MSB]
3771 13:40:21.070026 32, [0] oooooooo ooooooox [MSB]
3772 13:40:21.073078 33, [0] oooooooo ooooooox [MSB]
3773 13:40:21.076672 34, [0] oooooooo ooooooox [MSB]
3774 13:40:21.079997 35, [0] oooxoooo xxooooox [MSB]
3775 13:40:21.080116 36, [0] oooxoooo xxooooox [MSB]
3776 13:40:21.083716 37, [0] ooxxoooo xxooooox [MSB]
3777 13:40:21.086719 38, [0] ooxxoooo xxooooox [MSB]
3778 13:40:21.089897 39, [0] ooxxooox xxxoooox [MSB]
3779 13:40:21.093196 40, [0] oxxxxoox xxxoooox [MSB]
3780 13:40:21.096486 41, [0] xxxxxxox xxxxxxxx [MSB]
3781 13:40:21.099719 42, [0] xxxxxxxx xxxxxxxx [MSB]
3782 13:40:21.103726 iDelay=42, Bit 0, Center 22 (4 ~ 40) 37
3783 13:40:21.106772 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
3784 13:40:21.109748 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3785 13:40:21.113513 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3786 13:40:21.116670 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3787 13:40:21.119947 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3788 13:40:21.123315 iDelay=42, Bit 6, Center 23 (6 ~ 41) 36
3789 13:40:21.126458 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3790 13:40:21.129784 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
3791 13:40:21.133725 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3792 13:40:21.136846 iDelay=42, Bit 10, Center 21 (4 ~ 38) 35
3793 13:40:21.139973 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3794 13:40:21.143306 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3795 13:40:21.150359 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3796 13:40:21.153197 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3797 13:40:21.156728 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3798 13:40:21.156845 ==
3799 13:40:21.159975 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3800 13:40:21.163184 fsp= 1, odt_onoff= 1, Byte mode= 0
3801 13:40:21.163300 ==
3802 13:40:21.166437 DQS Delay:
3803 13:40:21.166548 DQS0 = 0, DQS1 = 0
3804 13:40:21.166654 DQM Delay:
3805 13:40:21.170093 DQM0 = 20, DQM1 = 19
3806 13:40:21.170183 DQ Delay:
3807 13:40:21.173682 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3808 13:40:21.176858 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3809 13:40:21.179786 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3810 13:40:21.183652 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
3811 13:40:21.183772
3812 13:40:21.183877
3813 13:40:21.183981
3814 13:40:21.186662 [DramC_TX_OE_Calibration] TA2
3815 13:40:21.189998 Original DQ_B0 (3 6) =30, OEN = 27
3816 13:40:21.193287 Original DQ_B1 (3 6) =30, OEN = 27
3817 13:40:21.196584 23, 0x0, End_B0=23 End_B1=23
3818 13:40:21.199689 24, 0x0, End_B0=24 End_B1=24
3819 13:40:21.199809 25, 0x0, End_B0=25 End_B1=25
3820 13:40:21.203495 26, 0x0, End_B0=26 End_B1=26
3821 13:40:21.206697 27, 0x0, End_B0=27 End_B1=27
3822 13:40:21.209856 28, 0x0, End_B0=28 End_B1=28
3823 13:40:21.209969 29, 0x0, End_B0=29 End_B1=29
3824 13:40:21.213191 30, 0x0, End_B0=30 End_B1=30
3825 13:40:21.216975 31, 0xFFFF, End_B0=30 End_B1=30
3826 13:40:21.223728 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3827 13:40:21.226476 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3828 13:40:21.226595
3829 13:40:21.229668
3830 13:40:21.229784 Write Rank1 MR23 =0x3f
3831 13:40:21.229890 [DQSOSC]
3832 13:40:21.239695 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3833 13:40:21.246739 CH1_RK1: MR19=0x202, MR18=0xCCCC, DQSOSC=439, MR23=63, INC=12, DEC=19
3834 13:40:21.246854 Write Rank1 MR23 =0x3f
3835 13:40:21.249416 [DQSOSC]
3836 13:40:21.256498 [DQSOSCAuto] RK1, (LSB)MR18= 0xcbcb, (MSB)MR19= 0x202, tDQSOscB0 = 440 ps tDQSOscB1 = 440 ps
3837 13:40:21.259531 CH1 RK1: MR19=202, MR18=CBCB
3838 13:40:21.263170 [RxdqsGatingPostProcess] freq 1600
3839 13:40:21.266465 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3840 13:40:21.269700 Rank: 0
3841 13:40:21.272886 best DQS0 dly(2T, 0.5T) = (2, 6)
3842 13:40:21.272996 best DQS1 dly(2T, 0.5T) = (2, 6)
3843 13:40:21.276515 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3844 13:40:21.279547 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3845 13:40:21.282989 Rank: 1
3846 13:40:21.283108 best DQS0 dly(2T, 0.5T) = (2, 5)
3847 13:40:21.286012 best DQS1 dly(2T, 0.5T) = (2, 6)
3848 13:40:21.289247 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3849 13:40:21.292896 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3850 13:40:21.299605 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3851 13:40:21.303078 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3852 13:40:21.306503 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3853 13:40:21.306620
3854 13:40:21.306725
3855 13:40:21.309707 [Calibration Summary] Freqency 1600
3856 13:40:21.312854 CH 0, Rank 0
3857 13:40:21.312951 All Pass.
3858 13:40:21.313023
3859 13:40:21.313089 CH 0, Rank 1
3860 13:40:21.316048 All Pass.
3861 13:40:21.316132
3862 13:40:21.316215 CH 1, Rank 0
3863 13:40:21.316315 All Pass.
3864 13:40:21.316412
3865 13:40:21.319242 CH 1, Rank 1
3866 13:40:21.319347 All Pass.
3867 13:40:21.319445
3868 13:40:21.326184 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3869 13:40:21.332961 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3870 13:40:21.339408 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3871 13:40:21.342782 Write Rank0 MR3 =0xb0
3872 13:40:21.349393 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3873 13:40:21.356414 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3874 13:40:21.362712 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3875 13:40:21.366031 Write Rank1 MR3 =0xb0
3876 13:40:21.372718 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3877 13:40:21.379273 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3878 13:40:21.386088 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3879 13:40:21.386208 Write Rank0 MR3 =0xb0
3880 13:40:21.392635 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3881 13:40:21.399028 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3882 13:40:21.409177 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3883 13:40:21.409296 Write Rank1 MR3 =0xb0
3884 13:40:21.412700 DramC Write-DBI on
3885 13:40:21.415722 [GetDramInforAfterCalByMRR] Vendor 6.
3886 13:40:21.419236 [GetDramInforAfterCalByMRR] Revision 505.
3887 13:40:21.419357 MR8 1111
3888 13:40:21.422224 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3889 13:40:21.426095 MR8 1111
3890 13:40:21.429527 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3891 13:40:21.429640 MR8 1111
3892 13:40:21.435692 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3893 13:40:21.435809 MR8 1111
3894 13:40:21.442211 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3895 13:40:21.449331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3896 13:40:21.451973 Write Rank0 MR13 =0xd0
3897 13:40:21.455766 Write Rank1 MR13 =0xd0
3898 13:40:21.455857 Write Rank0 MR13 =0xd0
3899 13:40:21.458924 Write Rank1 MR13 =0xd0
3900 13:40:21.462197 Save calibration result to emmc
3901 13:40:21.462313
3902 13:40:21.462414
3903 13:40:21.465566 [DramcModeReg_Check] Freq_1600, FSP_1
3904 13:40:21.465682 FSP_1, CH_0, RK0
3905 13:40:21.468826 Write Rank0 MR13 =0xd8
3906 13:40:21.472670 MR12 = 0x5e (global = 0x5e) match
3907 13:40:21.475341 MR14 = 0x1c (global = 0x1c) match
3908 13:40:21.475458 FSP_1, CH_0, RK1
3909 13:40:21.479077 Write Rank1 MR13 =0xd8
3910 13:40:21.482203 MR12 = 0x60 (global = 0x60) match
3911 13:40:21.485784 MR14 = 0x20 (global = 0x20) match
3912 13:40:21.485905 FSP_1, CH_1, RK0
3913 13:40:21.488634 Write Rank0 MR13 =0xd8
3914 13:40:21.492210 MR12 = 0x60 (global = 0x60) match
3915 13:40:21.495329 MR14 = 0x20 (global = 0x20) match
3916 13:40:21.495446 FSP_1, CH_1, RK1
3917 13:40:21.499077 Write Rank1 MR13 =0xd8
3918 13:40:21.501958 MR12 = 0x60 (global = 0x60) match
3919 13:40:21.505685 MR14 = 0x20 (global = 0x20) match
3920 13:40:21.505799
3921 13:40:21.508949 [MEM_TEST] 02: After DFS, before run time config
3922 13:40:21.520012 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3923 13:40:21.520135
3924 13:40:21.520238 [TA2_TEST]
3925 13:40:21.520338 === TA2 HW
3926 13:40:21.523197 TA2 PAT: XTALK
3927 13:40:21.526847 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3928 13:40:21.533340 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3929 13:40:21.536371 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3930 13:40:21.540056 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3931 13:40:21.543035
3932 13:40:21.543150
3933 13:40:21.543252 Settings after calibration
3934 13:40:21.543355
3935 13:40:21.546972 [DramcRunTimeConfig]
3936 13:40:21.550118 TransferPLLToSPMControl - MODE SW PHYPLL
3937 13:40:21.550232 TX_TRACKING: ON
3938 13:40:21.553319 RX_TRACKING: ON
3939 13:40:21.553431 HW_GATING: ON
3940 13:40:21.556543 HW_GATING DBG: OFF
3941 13:40:21.556652 ddr_geometry:1
3942 13:40:21.560453 ddr_geometry:1
3943 13:40:21.560567 ddr_geometry:1
3944 13:40:21.560670 ddr_geometry:1
3945 13:40:21.563677 ddr_geometry:1
3946 13:40:21.563788 ddr_geometry:1
3947 13:40:21.566909 ddr_geometry:1
3948 13:40:21.567016 ddr_geometry:1
3949 13:40:21.570200 High Freq DUMMY_READ_FOR_TRACKING: ON
3950 13:40:21.573516 ZQCS_ENABLE_LP4: OFF
3951 13:40:21.576710 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3952 13:40:21.580092 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3953 13:40:21.580211 SPM_CONTROL_AFTERK: ON
3954 13:40:21.583359 IMPEDANCE_TRACKING: ON
3955 13:40:21.583480 TEMP_SENSOR: ON
3956 13:40:21.586628 PER_BANK_REFRESH: ON
3957 13:40:21.586753 HW_SAVE_FOR_SR: ON
3958 13:40:21.589814 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 13:40:21.593358 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3960 13:40:21.596335 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3961 13:40:21.599884 Read ODT Tracking: ON
3962 13:40:21.603044 =========================
3963 13:40:21.603174
3964 13:40:21.603296 [TA2_TEST]
3965 13:40:21.603424 === TA2 HW
3966 13:40:21.609915 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3967 13:40:21.612849 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3968 13:40:21.619632 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3969 13:40:21.623095 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3970 13:40:21.623231
3971 13:40:21.626146 [MEM_TEST] 03: After run time config
3972 13:40:21.637847 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3973 13:40:21.640924 [complex_mem_test] start addr:0x40024000, len:131072
3974 13:40:21.845356 1st complex R/W mem test pass
3975 13:40:21.852078 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3976 13:40:21.855611 sync preloader write leveling
3977 13:40:21.858653 sync preloader cbt_mr12
3978 13:40:21.861933 sync preloader cbt_clk_dly
3979 13:40:21.862056 sync preloader cbt_cmd_dly
3980 13:40:21.865596 sync preloader cbt_cs
3981 13:40:21.868495 sync preloader cbt_ca_perbit_delay
3982 13:40:21.868588 sync preloader clk_delay
3983 13:40:21.871920 sync preloader dqs_delay
3984 13:40:21.875137 sync preloader u1Gating2T_Save
3985 13:40:21.879023 sync preloader u1Gating05T_Save
3986 13:40:21.882316 sync preloader u1Gatingfine_tune_Save
3987 13:40:21.885533 sync preloader u1Gatingucpass_count_Save
3988 13:40:21.888675 sync preloader u1TxWindowPerbitVref_Save
3989 13:40:21.891960 sync preloader u1TxCenter_min_Save
3990 13:40:21.895205 sync preloader u1TxCenter_max_Save
3991 13:40:21.898412 sync preloader u1Txwin_center_Save
3992 13:40:21.902367 sync preloader u1Txfirst_pass_Save
3993 13:40:21.905437 sync preloader u1Txlast_pass_Save
3994 13:40:21.905557 sync preloader u1RxDatlat_Save
3995 13:40:21.908583 sync preloader u1RxWinPerbitVref_Save
3996 13:40:21.915013 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3997 13:40:21.918825 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3998 13:40:21.921790 sync preloader delay_cell_unit
3999 13:40:21.928795 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4000 13:40:21.932099 sync preloader write leveling
4001 13:40:21.932220 sync preloader cbt_mr12
4002 13:40:21.935363 sync preloader cbt_clk_dly
4003 13:40:21.938461 sync preloader cbt_cmd_dly
4004 13:40:21.938580 sync preloader cbt_cs
4005 13:40:21.942199 sync preloader cbt_ca_perbit_delay
4006 13:40:21.945302 sync preloader clk_delay
4007 13:40:21.948317 sync preloader dqs_delay
4008 13:40:21.948449 sync preloader u1Gating2T_Save
4009 13:40:21.952098 sync preloader u1Gating05T_Save
4010 13:40:21.955240 sync preloader u1Gatingfine_tune_Save
4011 13:40:21.958757 sync preloader u1Gatingucpass_count_Save
4012 13:40:21.961721 sync preloader u1TxWindowPerbitVref_Save
4013 13:40:21.965259 sync preloader u1TxCenter_min_Save
4014 13:40:21.968086 sync preloader u1TxCenter_max_Save
4015 13:40:21.971817 sync preloader u1Txwin_center_Save
4016 13:40:21.975043 sync preloader u1Txfirst_pass_Save
4017 13:40:21.978220 sync preloader u1Txlast_pass_Save
4018 13:40:21.981794 sync preloader u1RxDatlat_Save
4019 13:40:21.985247 sync preloader u1RxWinPerbitVref_Save
4020 13:40:21.988384 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4021 13:40:21.991555 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4022 13:40:21.995336 sync preloader delay_cell_unit
4023 13:40:22.001751 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4024 13:40:22.004915 sync preloader write leveling
4025 13:40:22.007987 sync preloader cbt_mr12
4026 13:40:22.011742 sync preloader cbt_clk_dly
4027 13:40:22.011824 sync preloader cbt_cmd_dly
4028 13:40:22.014804 sync preloader cbt_cs
4029 13:40:22.017940 sync preloader cbt_ca_perbit_delay
4030 13:40:22.018049 sync preloader clk_delay
4031 13:40:22.021819 sync preloader dqs_delay
4032 13:40:22.025094 sync preloader u1Gating2T_Save
4033 13:40:22.028245 sync preloader u1Gating05T_Save
4034 13:40:22.031298 sync preloader u1Gatingfine_tune_Save
4035 13:40:22.034823 sync preloader u1Gatingucpass_count_Save
4036 13:40:22.037895 sync preloader u1TxWindowPerbitVref_Save
4037 13:40:22.041268 sync preloader u1TxCenter_min_Save
4038 13:40:22.045218 sync preloader u1TxCenter_max_Save
4039 13:40:22.048291 sync preloader u1Txwin_center_Save
4040 13:40:22.051396 sync preloader u1Txfirst_pass_Save
4041 13:40:22.054610 sync preloader u1Txlast_pass_Save
4042 13:40:22.054693 sync preloader u1RxDatlat_Save
4043 13:40:22.058287 sync preloader u1RxWinPerbitVref_Save
4044 13:40:22.064760 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4045 13:40:22.068109 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4046 13:40:22.071881 sync preloader delay_cell_unit
4047 13:40:22.074806 just_for_test_dump_coreboot_params dump all params
4048 13:40:22.078359 dump source = 0x0
4049 13:40:22.078442 dump params frequency:1600
4050 13:40:22.081227 dump params rank number:2
4051 13:40:22.081319
4052 13:40:22.085004 dump params write leveling
4053 13:40:22.088180 write leveling[0][0][0] = 0x21
4054 13:40:22.088301 write leveling[0][0][1] = 0x18
4055 13:40:22.091119 write leveling[0][1][0] = 0x1a
4056 13:40:22.094810 write leveling[0][1][1] = 0x18
4057 13:40:22.098285 write leveling[1][0][0] = 0x22
4058 13:40:22.101413 write leveling[1][0][1] = 0x18
4059 13:40:22.104692 write leveling[1][1][0] = 0x22
4060 13:40:22.104782 write leveling[1][1][1] = 0x18
4061 13:40:22.107916 dump params cbt_cs
4062 13:40:22.111094 cbt_cs[0][0] = 0x8
4063 13:40:22.111216 cbt_cs[0][1] = 0x8
4064 13:40:22.114288 cbt_cs[1][0] = 0xb
4065 13:40:22.114385 cbt_cs[1][1] = 0xb
4066 13:40:22.117967 dump params cbt_mr12
4067 13:40:22.118087 cbt_mr12[0][0] = 0x1e
4068 13:40:22.121286 cbt_mr12[0][1] = 0x20
4069 13:40:22.121406 cbt_mr12[1][0] = 0x20
4070 13:40:22.124647 cbt_mr12[1][1] = 0x20
4071 13:40:22.127806 dump params tx window
4072 13:40:22.127921 tx_center_min[0][0][0] = 982
4073 13:40:22.131069 tx_center_max[0][0][0] = 989
4074 13:40:22.134310 tx_center_min[0][0][1] = 975
4075 13:40:22.137535 tx_center_max[0][0][1] = 982
4076 13:40:22.141356 tx_center_min[0][1][0] = 979
4077 13:40:22.141478 tx_center_max[0][1][0] = 986
4078 13:40:22.144326 tx_center_min[0][1][1] = 978
4079 13:40:22.147807 tx_center_max[0][1][1] = 985
4080 13:40:22.151010 tx_center_min[1][0][0] = 988
4081 13:40:22.154096 tx_center_max[1][0][0] = 994
4082 13:40:22.154231 tx_center_min[1][0][1] = 976
4083 13:40:22.157367 tx_center_max[1][0][1] = 982
4084 13:40:22.161051 tx_center_min[1][1][0] = 986
4085 13:40:22.164398 tx_center_max[1][1][0] = 991
4086 13:40:22.167611 tx_center_min[1][1][1] = 974
4087 13:40:22.167716 tx_center_max[1][1][1] = 981
4088 13:40:22.170966 dump params tx window
4089 13:40:22.174302 tx_win_center[0][0][0] = 989
4090 13:40:22.177569 tx_first_pass[0][0][0] = 977
4091 13:40:22.177665 tx_last_pass[0][0][0] = 1001
4092 13:40:22.180704 tx_win_center[0][0][1] = 988
4093 13:40:22.184292 tx_first_pass[0][0][1] = 976
4094 13:40:22.187244 tx_last_pass[0][0][1] = 1000
4095 13:40:22.187371 tx_win_center[0][0][2] = 988
4096 13:40:22.190862 tx_first_pass[0][0][2] = 976
4097 13:40:22.193939 tx_last_pass[0][0][2] = 1001
4098 13:40:22.197690 tx_win_center[0][0][3] = 982
4099 13:40:22.200957 tx_first_pass[0][0][3] = 970
4100 13:40:22.201061 tx_last_pass[0][0][3] = 995
4101 13:40:22.204050 tx_win_center[0][0][4] = 988
4102 13:40:22.207679 tx_first_pass[0][0][4] = 976
4103 13:40:22.210520 tx_last_pass[0][0][4] = 1000
4104 13:40:22.210615 tx_win_center[0][0][5] = 985
4105 13:40:22.214236 tx_first_pass[0][0][5] = 972
4106 13:40:22.217485 tx_last_pass[0][0][5] = 998
4107 13:40:22.220667 tx_win_center[0][0][6] = 987
4108 13:40:22.224449 tx_first_pass[0][0][6] = 975
4109 13:40:22.224565 tx_last_pass[0][0][6] = 999
4110 13:40:22.227763 tx_win_center[0][0][7] = 988
4111 13:40:22.230883 tx_first_pass[0][0][7] = 976
4112 13:40:22.234100 tx_last_pass[0][0][7] = 1000
4113 13:40:22.237324 tx_win_center[0][0][8] = 975
4114 13:40:22.237419 tx_first_pass[0][0][8] = 964
4115 13:40:22.240402 tx_last_pass[0][0][8] = 987
4116 13:40:22.244387 tx_win_center[0][0][9] = 978
4117 13:40:22.247518 tx_first_pass[0][0][9] = 967
4118 13:40:22.247607 tx_last_pass[0][0][9] = 990
4119 13:40:22.250501 tx_win_center[0][0][10] = 982
4120 13:40:22.254086 tx_first_pass[0][0][10] = 970
4121 13:40:22.257550 tx_last_pass[0][0][10] = 994
4122 13:40:22.260468 tx_win_center[0][0][11] = 977
4123 13:40:22.260587 tx_first_pass[0][0][11] = 965
4124 13:40:22.263667 tx_last_pass[0][0][11] = 989
4125 13:40:22.267382 tx_win_center[0][0][12] = 979
4126 13:40:22.270356 tx_first_pass[0][0][12] = 967
4127 13:40:22.273585 tx_last_pass[0][0][12] = 991
4128 13:40:22.273703 tx_win_center[0][0][13] = 979
4129 13:40:22.276804 tx_first_pass[0][0][13] = 967
4130 13:40:22.280132 tx_last_pass[0][0][13] = 991
4131 13:40:22.283400 tx_win_center[0][0][14] = 979
4132 13:40:22.287232 tx_first_pass[0][0][14] = 967
4133 13:40:22.290432 tx_last_pass[0][0][14] = 991
4134 13:40:22.290555 tx_win_center[0][0][15] = 981
4135 13:40:22.293477 tx_first_pass[0][0][15] = 969
4136 13:40:22.296748 tx_last_pass[0][0][15] = 993
4137 13:40:22.300332 tx_win_center[0][1][0] = 986
4138 13:40:22.303574 tx_first_pass[0][1][0] = 974
4139 13:40:22.303673 tx_last_pass[0][1][0] = 998
4140 13:40:22.306862 tx_win_center[0][1][1] = 984
4141 13:40:22.310092 tx_first_pass[0][1][1] = 973
4142 13:40:22.313391 tx_last_pass[0][1][1] = 996
4143 13:40:22.313510 tx_win_center[0][1][2] = 986
4144 13:40:22.316986 tx_first_pass[0][1][2] = 974
4145 13:40:22.320108 tx_last_pass[0][1][2] = 998
4146 13:40:22.323664 tx_win_center[0][1][3] = 979
4147 13:40:22.326751 tx_first_pass[0][1][3] = 968
4148 13:40:22.326868 tx_last_pass[0][1][3] = 991
4149 13:40:22.330468 tx_win_center[0][1][4] = 983
4150 13:40:22.333093 tx_first_pass[0][1][4] = 971
4151 13:40:22.337069 tx_last_pass[0][1][4] = 996
4152 13:40:22.337186 tx_win_center[0][1][5] = 980
4153 13:40:22.340113 tx_first_pass[0][1][5] = 968
4154 13:40:22.343209 tx_last_pass[0][1][5] = 993
4155 13:40:22.346575 tx_win_center[0][1][6] = 982
4156 13:40:22.349820 tx_first_pass[0][1][6] = 969
4157 13:40:22.349939 tx_last_pass[0][1][6] = 995
4158 13:40:22.353092 tx_win_center[0][1][7] = 984
4159 13:40:22.356443 tx_first_pass[0][1][7] = 971
4160 13:40:22.360185 tx_last_pass[0][1][7] = 997
4161 13:40:22.360307 tx_win_center[0][1][8] = 978
4162 13:40:22.363699 tx_first_pass[0][1][8] = 966
4163 13:40:22.367031 tx_last_pass[0][1][8] = 990
4164 13:40:22.369887 tx_win_center[0][1][9] = 979
4165 13:40:22.373286 tx_first_pass[0][1][9] = 968
4166 13:40:22.373408 tx_last_pass[0][1][9] = 991
4167 13:40:22.376843 tx_win_center[0][1][10] = 985
4168 13:40:22.379813 tx_first_pass[0][1][10] = 972
4169 13:40:22.383560 tx_last_pass[0][1][10] = 998
4170 13:40:22.383678 tx_win_center[0][1][11] = 979
4171 13:40:22.386687 tx_first_pass[0][1][11] = 967
4172 13:40:22.389937 tx_last_pass[0][1][11] = 991
4173 13:40:22.393358 tx_win_center[0][1][12] = 980
4174 13:40:22.396556 tx_first_pass[0][1][12] = 968
4175 13:40:22.396644 tx_last_pass[0][1][12] = 992
4176 13:40:22.400338 tx_win_center[0][1][13] = 980
4177 13:40:22.403365 tx_first_pass[0][1][13] = 968
4178 13:40:22.406592 tx_last_pass[0][1][13] = 992
4179 13:40:22.409870 tx_win_center[0][1][14] = 980
4180 13:40:22.413667 tx_first_pass[0][1][14] = 968
4181 13:40:22.413783 tx_last_pass[0][1][14] = 993
4182 13:40:22.416921 tx_win_center[0][1][15] = 983
4183 13:40:22.420085 tx_first_pass[0][1][15] = 971
4184 13:40:22.423291 tx_last_pass[0][1][15] = 995
4185 13:40:22.426583 tx_win_center[1][0][0] = 994
4186 13:40:22.426704 tx_first_pass[1][0][0] = 981
4187 13:40:22.429778 tx_last_pass[1][0][0] = 1007
4188 13:40:22.433551 tx_win_center[1][0][1] = 992
4189 13:40:22.436339 tx_first_pass[1][0][1] = 979
4190 13:40:22.436457 tx_last_pass[1][0][1] = 1006
4191 13:40:22.439778 tx_win_center[1][0][2] = 990
4192 13:40:22.442983 tx_first_pass[1][0][2] = 978
4193 13:40:22.446647 tx_last_pass[1][0][2] = 1003
4194 13:40:22.449852 tx_win_center[1][0][3] = 988
4195 13:40:22.449970 tx_first_pass[1][0][3] = 977
4196 13:40:22.453193 tx_last_pass[1][0][3] = 1000
4197 13:40:22.456324 tx_win_center[1][0][4] = 993
4198 13:40:22.459539 tx_first_pass[1][0][4] = 980
4199 13:40:22.462713 tx_last_pass[1][0][4] = 1006
4200 13:40:22.462827 tx_win_center[1][0][5] = 993
4201 13:40:22.466597 tx_first_pass[1][0][5] = 980
4202 13:40:22.469820 tx_last_pass[1][0][5] = 1006
4203 13:40:22.473148 tx_win_center[1][0][6] = 992
4204 13:40:22.476113 tx_first_pass[1][0][6] = 979
4205 13:40:22.476232 tx_last_pass[1][0][6] = 1006
4206 13:40:22.479744 tx_win_center[1][0][7] = 992
4207 13:40:22.482672 tx_first_pass[1][0][7] = 979
4208 13:40:22.486423 tx_last_pass[1][0][7] = 1006
4209 13:40:22.486534 tx_win_center[1][0][8] = 980
4210 13:40:22.489370 tx_first_pass[1][0][8] = 968
4211 13:40:22.492896 tx_last_pass[1][0][8] = 992
4212 13:40:22.496105 tx_win_center[1][0][9] = 979
4213 13:40:22.499338 tx_first_pass[1][0][9] = 968
4214 13:40:22.499463 tx_last_pass[1][0][9] = 991
4215 13:40:22.502459 tx_win_center[1][0][10] = 981
4216 13:40:22.506192 tx_first_pass[1][0][10] = 970
4217 13:40:22.509381 tx_last_pass[1][0][10] = 993
4218 13:40:22.512465 tx_win_center[1][0][11] = 982
4219 13:40:22.512582 tx_first_pass[1][0][11] = 970
4220 13:40:22.516191 tx_last_pass[1][0][11] = 994
4221 13:40:22.519398 tx_win_center[1][0][12] = 981
4222 13:40:22.522547 tx_first_pass[1][0][12] = 970
4223 13:40:22.525919 tx_last_pass[1][0][12] = 993
4224 13:40:22.526033 tx_win_center[1][0][13] = 982
4225 13:40:22.529083 tx_first_pass[1][0][13] = 971
4226 13:40:22.532377 tx_last_pass[1][0][13] = 994
4227 13:40:22.536216 tx_win_center[1][0][14] = 981
4228 13:40:22.539479 tx_first_pass[1][0][14] = 970
4229 13:40:22.539601 tx_last_pass[1][0][14] = 993
4230 13:40:22.542715 tx_win_center[1][0][15] = 976
4231 13:40:22.545869 tx_first_pass[1][0][15] = 965
4232 13:40:22.549412 tx_last_pass[1][0][15] = 987
4233 13:40:22.552552 tx_win_center[1][1][0] = 991
4234 13:40:22.552675 tx_first_pass[1][1][0] = 978
4235 13:40:22.556065 tx_last_pass[1][1][0] = 1005
4236 13:40:22.558889 tx_win_center[1][1][1] = 990
4237 13:40:22.562344 tx_first_pass[1][1][1] = 978
4238 13:40:22.565704 tx_last_pass[1][1][1] = 1003
4239 13:40:22.565817 tx_win_center[1][1][2] = 989
4240 13:40:22.568911 tx_first_pass[1][1][2] = 977
4241 13:40:22.572318 tx_last_pass[1][1][2] = 1001
4242 13:40:22.575367 tx_win_center[1][1][3] = 986
4243 13:40:22.579249 tx_first_pass[1][1][3] = 974
4244 13:40:22.579365 tx_last_pass[1][1][3] = 998
4245 13:40:22.582458 tx_win_center[1][1][4] = 990
4246 13:40:22.585611 tx_first_pass[1][1][4] = 978
4247 13:40:22.588695 tx_last_pass[1][1][4] = 1003
4248 13:40:22.588811 tx_win_center[1][1][5] = 991
4249 13:40:22.592231 tx_first_pass[1][1][5] = 979
4250 13:40:22.595614 tx_last_pass[1][1][5] = 1003
4251 13:40:22.599023 tx_win_center[1][1][6] = 990
4252 13:40:22.601883 tx_first_pass[1][1][6] = 978
4253 13:40:22.602000 tx_last_pass[1][1][6] = 1003
4254 13:40:22.605486 tx_win_center[1][1][7] = 990
4255 13:40:22.608588 tx_first_pass[1][1][7] = 978
4256 13:40:22.612023 tx_last_pass[1][1][7] = 1003
4257 13:40:22.615024 tx_win_center[1][1][8] = 978
4258 13:40:22.615139 tx_first_pass[1][1][8] = 967
4259 13:40:22.618793 tx_last_pass[1][1][8] = 990
4260 13:40:22.621962 tx_win_center[1][1][9] = 978
4261 13:40:22.625238 tx_first_pass[1][1][9] = 967
4262 13:40:22.625360 tx_last_pass[1][1][9] = 990
4263 13:40:22.628538 tx_win_center[1][1][10] = 980
4264 13:40:22.631831 tx_first_pass[1][1][10] = 969
4265 13:40:22.635043 tx_last_pass[1][1][10] = 992
4266 13:40:22.638374 tx_win_center[1][1][11] = 980
4267 13:40:22.641628 tx_first_pass[1][1][11] = 969
4268 13:40:22.641746 tx_last_pass[1][1][11] = 992
4269 13:40:22.644954 tx_win_center[1][1][12] = 981
4270 13:40:22.648192 tx_first_pass[1][1][12] = 969
4271 13:40:22.651718 tx_last_pass[1][1][12] = 993
4272 13:40:22.654738 tx_win_center[1][1][13] = 981
4273 13:40:22.654859 tx_first_pass[1][1][13] = 969
4274 13:40:22.658592 tx_last_pass[1][1][13] = 993
4275 13:40:22.661821 tx_win_center[1][1][14] = 981
4276 13:40:22.664901 tx_first_pass[1][1][14] = 969
4277 13:40:22.668554 tx_last_pass[1][1][14] = 993
4278 13:40:22.668717 tx_win_center[1][1][15] = 974
4279 13:40:22.671447 tx_first_pass[1][1][15] = 962
4280 13:40:22.674852 tx_last_pass[1][1][15] = 987
4281 13:40:22.678092 dump params rx window
4282 13:40:22.678213 rx_firspass[0][0][0] = 5
4283 13:40:22.681396 rx_lastpass[0][0][0] = 38
4284 13:40:22.685101 rx_firspass[0][0][1] = 5
4285 13:40:22.685212 rx_lastpass[0][0][1] = 36
4286 13:40:22.688339 rx_firspass[0][0][2] = 6
4287 13:40:22.691611 rx_lastpass[0][0][2] = 36
4288 13:40:22.691721 rx_firspass[0][0][3] = -2
4289 13:40:22.694863 rx_lastpass[0][0][3] = 31
4290 13:40:22.697887 rx_firspass[0][0][4] = 5
4291 13:40:22.701733 rx_lastpass[0][0][4] = 37
4292 13:40:22.701857 rx_firspass[0][0][5] = 1
4293 13:40:22.704725 rx_lastpass[0][0][5] = 31
4294 13:40:22.708411 rx_firspass[0][0][6] = 3
4295 13:40:22.708531 rx_lastpass[0][0][6] = 34
4296 13:40:22.711217 rx_firspass[0][0][7] = 5
4297 13:40:22.714820 rx_lastpass[0][0][7] = 36
4298 13:40:22.718575 rx_firspass[0][0][8] = -3
4299 13:40:22.718692 rx_lastpass[0][0][8] = 33
4300 13:40:22.721492 rx_firspass[0][0][9] = 0
4301 13:40:22.724775 rx_lastpass[0][0][9] = 32
4302 13:40:22.724895 rx_firspass[0][0][10] = 8
4303 13:40:22.728258 rx_lastpass[0][0][10] = 41
4304 13:40:22.731644 rx_firspass[0][0][11] = 1
4305 13:40:22.734820 rx_lastpass[0][0][11] = 32
4306 13:40:22.734935 rx_firspass[0][0][12] = 2
4307 13:40:22.737999 rx_lastpass[0][0][12] = 36
4308 13:40:22.741196 rx_firspass[0][0][13] = 3
4309 13:40:22.741305 rx_lastpass[0][0][13] = 33
4310 13:40:22.745053 rx_firspass[0][0][14] = 2
4311 13:40:22.748460 rx_lastpass[0][0][14] = 37
4312 13:40:22.751747 rx_firspass[0][0][15] = 6
4313 13:40:22.751856 rx_lastpass[0][0][15] = 37
4314 13:40:22.755032 rx_firspass[0][1][0] = 5
4315 13:40:22.758267 rx_lastpass[0][1][0] = 40
4316 13:40:22.758379 rx_firspass[0][1][1] = 5
4317 13:40:22.761413 rx_lastpass[0][1][1] = 38
4318 13:40:22.764719 rx_firspass[0][1][2] = 6
4319 13:40:22.767880 rx_lastpass[0][1][2] = 38
4320 13:40:22.767996 rx_firspass[0][1][3] = -2
4321 13:40:22.771553 rx_lastpass[0][1][3] = 33
4322 13:40:22.774811 rx_firspass[0][1][4] = 5
4323 13:40:22.774921 rx_lastpass[0][1][4] = 39
4324 13:40:22.777959 rx_firspass[0][1][5] = 1
4325 13:40:22.781726 rx_lastpass[0][1][5] = 34
4326 13:40:22.781839 rx_firspass[0][1][6] = 3
4327 13:40:22.784669 rx_lastpass[0][1][6] = 37
4328 13:40:22.788117 rx_firspass[0][1][7] = 3
4329 13:40:22.791313 rx_lastpass[0][1][7] = 37
4330 13:40:22.791442 rx_firspass[0][1][8] = -2
4331 13:40:22.794659 rx_lastpass[0][1][8] = 32
4332 13:40:22.797994 rx_firspass[0][1][9] = 1
4333 13:40:22.798076 rx_lastpass[0][1][9] = 36
4334 13:40:22.801137 rx_firspass[0][1][10] = 7
4335 13:40:22.804343 rx_lastpass[0][1][10] = 43
4336 13:40:22.807611 rx_firspass[0][1][11] = -2
4337 13:40:22.807729 rx_lastpass[0][1][11] = 34
4338 13:40:22.811428 rx_firspass[0][1][12] = 1
4339 13:40:22.814595 rx_lastpass[0][1][12] = 37
4340 13:40:22.814723 rx_firspass[0][1][13] = 2
4341 13:40:22.817604 rx_lastpass[0][1][13] = 35
4342 13:40:22.821373 rx_firspass[0][1][14] = 3
4343 13:40:22.824612 rx_lastpass[0][1][14] = 37
4344 13:40:22.824700 rx_firspass[0][1][15] = 6
4345 13:40:22.827819 rx_lastpass[0][1][15] = 39
4346 13:40:22.830932 rx_firspass[1][0][0] = 5
4347 13:40:22.834648 rx_lastpass[1][0][0] = 39
4348 13:40:22.834764 rx_firspass[1][0][1] = 5
4349 13:40:22.837558 rx_lastpass[1][0][1] = 38
4350 13:40:22.841085 rx_firspass[1][0][2] = 2
4351 13:40:22.841168 rx_lastpass[1][0][2] = 36
4352 13:40:22.844488 rx_firspass[1][0][3] = -1
4353 13:40:22.847948 rx_lastpass[1][0][3] = 34
4354 13:40:22.848060 rx_firspass[1][0][4] = 5
4355 13:40:22.851150 rx_lastpass[1][0][4] = 38
4356 13:40:22.854357 rx_firspass[1][0][5] = 7
4357 13:40:22.857658 rx_lastpass[1][0][5] = 39
4358 13:40:22.857772 rx_firspass[1][0][6] = 7
4359 13:40:22.860939 rx_lastpass[1][0][6] = 40
4360 13:40:22.864041 rx_firspass[1][0][7] = 4
4361 13:40:22.864156 rx_lastpass[1][0][7] = 38
4362 13:40:22.867793 rx_firspass[1][0][8] = 1
4363 13:40:22.870958 rx_lastpass[1][0][8] = 34
4364 13:40:22.871070 rx_firspass[1][0][9] = 0
4365 13:40:22.874198 rx_lastpass[1][0][9] = 32
4366 13:40:22.877338 rx_firspass[1][0][10] = 5
4367 13:40:22.881195 rx_lastpass[1][0][10] = 35
4368 13:40:22.881326 rx_firspass[1][0][11] = 5
4369 13:40:22.884359 rx_lastpass[1][0][11] = 38
4370 13:40:22.887613 rx_firspass[1][0][12] = 5
4371 13:40:22.890848 rx_lastpass[1][0][12] = 38
4372 13:40:22.890956 rx_firspass[1][0][13] = 5
4373 13:40:22.894595 rx_lastpass[1][0][13] = 38
4374 13:40:22.897616 rx_firspass[1][0][14] = 6
4375 13:40:22.897738 rx_lastpass[1][0][14] = 38
4376 13:40:22.900732 rx_firspass[1][0][15] = -3
4377 13:40:22.903993 rx_lastpass[1][0][15] = 30
4378 13:40:22.907579 rx_firspass[1][1][0] = 4
4379 13:40:22.907711 rx_lastpass[1][1][0] = 40
4380 13:40:22.910614 rx_firspass[1][1][1] = 4
4381 13:40:22.914485 rx_lastpass[1][1][1] = 39
4382 13:40:22.914581 rx_firspass[1][1][2] = 0
4383 13:40:22.917661 rx_lastpass[1][1][2] = 36
4384 13:40:22.920771 rx_firspass[1][1][3] = -2
4385 13:40:22.924303 rx_lastpass[1][1][3] = 34
4386 13:40:22.924394 rx_firspass[1][1][4] = 4
4387 13:40:22.927424 rx_lastpass[1][1][4] = 39
4388 13:40:22.930648 rx_firspass[1][1][5] = 5
4389 13:40:22.930761 rx_lastpass[1][1][5] = 40
4390 13:40:22.934039 rx_firspass[1][1][6] = 6
4391 13:40:22.937277 rx_lastpass[1][1][6] = 41
4392 13:40:22.937359 rx_firspass[1][1][7] = 3
4393 13:40:22.940298 rx_lastpass[1][1][7] = 38
4394 13:40:22.944040 rx_firspass[1][1][8] = 0
4395 13:40:22.947094 rx_lastpass[1][1][8] = 34
4396 13:40:22.947215 rx_firspass[1][1][9] = -1
4397 13:40:22.950719 rx_lastpass[1][1][9] = 34
4398 13:40:22.954073 rx_firspass[1][1][10] = 4
4399 13:40:22.954187 rx_lastpass[1][1][10] = 38
4400 13:40:22.957020 rx_firspass[1][1][11] = 4
4401 13:40:22.960723 rx_lastpass[1][1][11] = 40
4402 13:40:22.964062 rx_firspass[1][1][12] = 4
4403 13:40:22.964187 rx_lastpass[1][1][12] = 40
4404 13:40:22.967253 rx_firspass[1][1][13] = 4
4405 13:40:22.970779 rx_lastpass[1][1][13] = 40
4406 13:40:22.973936 rx_firspass[1][1][14] = 5
4407 13:40:22.974058 rx_lastpass[1][1][14] = 40
4408 13:40:22.977175 rx_firspass[1][1][15] = -3
4409 13:40:22.980534 rx_lastpass[1][1][15] = 31
4410 13:40:22.980665 dump params clk_delay
4411 13:40:22.983597 clk_delay[0] = 1
4412 13:40:22.983708 clk_delay[1] = 0
4413 13:40:22.986880 dump params dqs_delay
4414 13:40:22.986995 dqs_delay[0][0] = -2
4415 13:40:22.990266 dqs_delay[0][1] = 0
4416 13:40:22.993566 dqs_delay[1][0] = 0
4417 13:40:22.993691 dqs_delay[1][1] = 0
4418 13:40:22.997095 dump params delay_cell_unit = 735
4419 13:40:22.997193 dump source = 0x0
4420 13:40:23.000318 dump params frequency:1200
4421 13:40:23.003449 dump params rank number:2
4422 13:40:23.003572
4423 13:40:23.007194 dump params write leveling
4424 13:40:23.007308 write leveling[0][0][0] = 0x0
4425 13:40:23.010294 write leveling[0][0][1] = 0x0
4426 13:40:23.013440 write leveling[0][1][0] = 0x0
4427 13:40:23.016786 write leveling[0][1][1] = 0x0
4428 13:40:23.020557 write leveling[1][0][0] = 0x0
4429 13:40:23.024050 write leveling[1][0][1] = 0x0
4430 13:40:23.024164 write leveling[1][1][0] = 0x0
4431 13:40:23.027114 write leveling[1][1][1] = 0x0
4432 13:40:23.030286 dump params cbt_cs
4433 13:40:23.030416 cbt_cs[0][0] = 0x0
4434 13:40:23.033460 cbt_cs[0][1] = 0x0
4435 13:40:23.033575 cbt_cs[1][0] = 0x0
4436 13:40:23.036556 cbt_cs[1][1] = 0x0
4437 13:40:23.036686 dump params cbt_mr12
4438 13:40:23.040487 cbt_mr12[0][0] = 0x0
4439 13:40:23.040600 cbt_mr12[0][1] = 0x0
4440 13:40:23.043672 cbt_mr12[1][0] = 0x0
4441 13:40:23.046806 cbt_mr12[1][1] = 0x0
4442 13:40:23.046928 dump params tx window
4443 13:40:23.049855 tx_center_min[0][0][0] = 0
4444 13:40:23.053755 tx_center_max[0][0][0] = 0
4445 13:40:23.053884 tx_center_min[0][0][1] = 0
4446 13:40:23.056984 tx_center_max[0][0][1] = 0
4447 13:40:23.060095 tx_center_min[0][1][0] = 0
4448 13:40:23.063189 tx_center_max[0][1][0] = 0
4449 13:40:23.063315 tx_center_min[0][1][1] = 0
4450 13:40:23.066615 tx_center_max[0][1][1] = 0
4451 13:40:23.070012 tx_center_min[1][0][0] = 0
4452 13:40:23.073100 tx_center_max[1][0][0] = 0
4453 13:40:23.073232 tx_center_min[1][0][1] = 0
4454 13:40:23.076192 tx_center_max[1][0][1] = 0
4455 13:40:23.079961 tx_center_min[1][1][0] = 0
4456 13:40:23.083170 tx_center_max[1][1][0] = 0
4457 13:40:23.083286 tx_center_min[1][1][1] = 0
4458 13:40:23.086513 tx_center_max[1][1][1] = 0
4459 13:40:23.089793 dump params tx window
4460 13:40:23.089906 tx_win_center[0][0][0] = 0
4461 13:40:23.093063 tx_first_pass[0][0][0] = 0
4462 13:40:23.096417 tx_last_pass[0][0][0] = 0
4463 13:40:23.099474 tx_win_center[0][0][1] = 0
4464 13:40:23.099604 tx_first_pass[0][0][1] = 0
4465 13:40:23.102465 tx_last_pass[0][0][1] = 0
4466 13:40:23.106366 tx_win_center[0][0][2] = 0
4467 13:40:23.109592 tx_first_pass[0][0][2] = 0
4468 13:40:23.109714 tx_last_pass[0][0][2] = 0
4469 13:40:23.112943 tx_win_center[0][0][3] = 0
4470 13:40:23.116095 tx_first_pass[0][0][3] = 0
4471 13:40:23.119209 tx_last_pass[0][0][3] = 0
4472 13:40:23.119326 tx_win_center[0][0][4] = 0
4473 13:40:23.122329 tx_first_pass[0][0][4] = 0
4474 13:40:23.126118 tx_last_pass[0][0][4] = 0
4475 13:40:23.126230 tx_win_center[0][0][5] = 0
4476 13:40:23.129232 tx_first_pass[0][0][5] = 0
4477 13:40:23.132557 tx_last_pass[0][0][5] = 0
4478 13:40:23.135873 tx_win_center[0][0][6] = 0
4479 13:40:23.135984 tx_first_pass[0][0][6] = 0
4480 13:40:23.139143 tx_last_pass[0][0][6] = 0
4481 13:40:23.142359 tx_win_center[0][0][7] = 0
4482 13:40:23.146050 tx_first_pass[0][0][7] = 0
4483 13:40:23.146169 tx_last_pass[0][0][7] = 0
4484 13:40:23.149189 tx_win_center[0][0][8] = 0
4485 13:40:23.152259 tx_first_pass[0][0][8] = 0
4486 13:40:23.152376 tx_last_pass[0][0][8] = 0
4487 13:40:23.156147 tx_win_center[0][0][9] = 0
4488 13:40:23.159467 tx_first_pass[0][0][9] = 0
4489 13:40:23.162540 tx_last_pass[0][0][9] = 0
4490 13:40:23.162656 tx_win_center[0][0][10] = 0
4491 13:40:23.165654 tx_first_pass[0][0][10] = 0
4492 13:40:23.169001 tx_last_pass[0][0][10] = 0
4493 13:40:23.172799 tx_win_center[0][0][11] = 0
4494 13:40:23.172916 tx_first_pass[0][0][11] = 0
4495 13:40:23.175964 tx_last_pass[0][0][11] = 0
4496 13:40:23.179031 tx_win_center[0][0][12] = 0
4497 13:40:23.182580 tx_first_pass[0][0][12] = 0
4498 13:40:23.182694 tx_last_pass[0][0][12] = 0
4499 13:40:23.185932 tx_win_center[0][0][13] = 0
4500 13:40:23.189409 tx_first_pass[0][0][13] = 0
4501 13:40:23.192435 tx_last_pass[0][0][13] = 0
4502 13:40:23.192520 tx_win_center[0][0][14] = 0
4503 13:40:23.195664 tx_first_pass[0][0][14] = 0
4504 13:40:23.198901 tx_last_pass[0][0][14] = 0
4505 13:40:23.202098 tx_win_center[0][0][15] = 0
4506 13:40:23.202207 tx_first_pass[0][0][15] = 0
4507 13:40:23.205944 tx_last_pass[0][0][15] = 0
4508 13:40:23.209113 tx_win_center[0][1][0] = 0
4509 13:40:23.212409 tx_first_pass[0][1][0] = 0
4510 13:40:23.212528 tx_last_pass[0][1][0] = 0
4511 13:40:23.215605 tx_win_center[0][1][1] = 0
4512 13:40:23.218903 tx_first_pass[0][1][1] = 0
4513 13:40:23.219025 tx_last_pass[0][1][1] = 0
4514 13:40:23.222097 tx_win_center[0][1][2] = 0
4515 13:40:23.225293 tx_first_pass[0][1][2] = 0
4516 13:40:23.229211 tx_last_pass[0][1][2] = 0
4517 13:40:23.229329 tx_win_center[0][1][3] = 0
4518 13:40:23.232484 tx_first_pass[0][1][3] = 0
4519 13:40:23.235772 tx_last_pass[0][1][3] = 0
4520 13:40:23.239061 tx_win_center[0][1][4] = 0
4521 13:40:23.239184 tx_first_pass[0][1][4] = 0
4522 13:40:23.242127 tx_last_pass[0][1][4] = 0
4523 13:40:23.245388 tx_win_center[0][1][5] = 0
4524 13:40:23.248657 tx_first_pass[0][1][5] = 0
4525 13:40:23.248774 tx_last_pass[0][1][5] = 0
4526 13:40:23.252001 tx_win_center[0][1][6] = 0
4527 13:40:23.255714 tx_first_pass[0][1][6] = 0
4528 13:40:23.255807 tx_last_pass[0][1][6] = 0
4529 13:40:23.258913 tx_win_center[0][1][7] = 0
4530 13:40:23.261792 tx_first_pass[0][1][7] = 0
4531 13:40:23.265264 tx_last_pass[0][1][7] = 0
4532 13:40:23.265398 tx_win_center[0][1][8] = 0
4533 13:40:23.269002 tx_first_pass[0][1][8] = 0
4534 13:40:23.271984 tx_last_pass[0][1][8] = 0
4535 13:40:23.272121 tx_win_center[0][1][9] = 0
4536 13:40:23.275118 tx_first_pass[0][1][9] = 0
4537 13:40:23.278868 tx_last_pass[0][1][9] = 0
4538 13:40:23.282185 tx_win_center[0][1][10] = 0
4539 13:40:23.282299 tx_first_pass[0][1][10] = 0
4540 13:40:23.285357 tx_last_pass[0][1][10] = 0
4541 13:40:23.288479 tx_win_center[0][1][11] = 0
4542 13:40:23.291664 tx_first_pass[0][1][11] = 0
4543 13:40:23.291790 tx_last_pass[0][1][11] = 0
4544 13:40:23.295327 tx_win_center[0][1][12] = 0
4545 13:40:23.298316 tx_first_pass[0][1][12] = 0
4546 13:40:23.301585 tx_last_pass[0][1][12] = 0
4547 13:40:23.301708 tx_win_center[0][1][13] = 0
4548 13:40:23.305492 tx_first_pass[0][1][13] = 0
4549 13:40:23.308694 tx_last_pass[0][1][13] = 0
4550 13:40:23.311826 tx_win_center[0][1][14] = 0
4551 13:40:23.315000 tx_first_pass[0][1][14] = 0
4552 13:40:23.315117 tx_last_pass[0][1][14] = 0
4553 13:40:23.318910 tx_win_center[0][1][15] = 0
4554 13:40:23.321522 tx_first_pass[0][1][15] = 0
4555 13:40:23.325427 tx_last_pass[0][1][15] = 0
4556 13:40:23.325546 tx_win_center[1][0][0] = 0
4557 13:40:23.328745 tx_first_pass[1][0][0] = 0
4558 13:40:23.331981 tx_last_pass[1][0][0] = 0
4559 13:40:23.332061 tx_win_center[1][0][1] = 0
4560 13:40:23.335328 tx_first_pass[1][0][1] = 0
4561 13:40:23.338640 tx_last_pass[1][0][1] = 0
4562 13:40:23.341866 tx_win_center[1][0][2] = 0
4563 13:40:23.341987 tx_first_pass[1][0][2] = 0
4564 13:40:23.345051 tx_last_pass[1][0][2] = 0
4565 13:40:23.348285 tx_win_center[1][0][3] = 0
4566 13:40:23.351518 tx_first_pass[1][0][3] = 0
4567 13:40:23.351635 tx_last_pass[1][0][3] = 0
4568 13:40:23.355283 tx_win_center[1][0][4] = 0
4569 13:40:23.358412 tx_first_pass[1][0][4] = 0
4570 13:40:23.358529 tx_last_pass[1][0][4] = 0
4571 13:40:23.361443 tx_win_center[1][0][5] = 0
4572 13:40:23.364987 tx_first_pass[1][0][5] = 0
4573 13:40:23.368025 tx_last_pass[1][0][5] = 0
4574 13:40:23.368113 tx_win_center[1][0][6] = 0
4575 13:40:23.371592 tx_first_pass[1][0][6] = 0
4576 13:40:23.374955 tx_last_pass[1][0][6] = 0
4577 13:40:23.375043 tx_win_center[1][0][7] = 0
4578 13:40:23.378340 tx_first_pass[1][0][7] = 0
4579 13:40:23.381483 tx_last_pass[1][0][7] = 0
4580 13:40:23.384604 tx_win_center[1][0][8] = 0
4581 13:40:23.384719 tx_first_pass[1][0][8] = 0
4582 13:40:23.387887 tx_last_pass[1][0][8] = 0
4583 13:40:23.391716 tx_win_center[1][0][9] = 0
4584 13:40:23.395098 tx_first_pass[1][0][9] = 0
4585 13:40:23.395214 tx_last_pass[1][0][9] = 0
4586 13:40:23.398382 tx_win_center[1][0][10] = 0
4587 13:40:23.401566 tx_first_pass[1][0][10] = 0
4588 13:40:23.404842 tx_last_pass[1][0][10] = 0
4589 13:40:23.404966 tx_win_center[1][0][11] = 0
4590 13:40:23.407903 tx_first_pass[1][0][11] = 0
4591 13:40:23.411603 tx_last_pass[1][0][11] = 0
4592 13:40:23.415006 tx_win_center[1][0][12] = 0
4593 13:40:23.415134 tx_first_pass[1][0][12] = 0
4594 13:40:23.417788 tx_last_pass[1][0][12] = 0
4595 13:40:23.421320 tx_win_center[1][0][13] = 0
4596 13:40:23.425059 tx_first_pass[1][0][13] = 0
4597 13:40:23.425182 tx_last_pass[1][0][13] = 0
4598 13:40:23.428360 tx_win_center[1][0][14] = 0
4599 13:40:23.431380 tx_first_pass[1][0][14] = 0
4600 13:40:23.434652 tx_last_pass[1][0][14] = 0
4601 13:40:23.434762 tx_win_center[1][0][15] = 0
4602 13:40:23.437814 tx_first_pass[1][0][15] = 0
4603 13:40:23.441246 tx_last_pass[1][0][15] = 0
4604 13:40:23.444591 tx_win_center[1][1][0] = 0
4605 13:40:23.444676 tx_first_pass[1][1][0] = 0
4606 13:40:23.448332 tx_last_pass[1][1][0] = 0
4607 13:40:23.450946 tx_win_center[1][1][1] = 0
4608 13:40:23.454823 tx_first_pass[1][1][1] = 0
4609 13:40:23.454942 tx_last_pass[1][1][1] = 0
4610 13:40:23.457981 tx_win_center[1][1][2] = 0
4611 13:40:23.461369 tx_first_pass[1][1][2] = 0
4612 13:40:23.461459 tx_last_pass[1][1][2] = 0
4613 13:40:23.464564 tx_win_center[1][1][3] = 0
4614 13:40:23.467809 tx_first_pass[1][1][3] = 0
4615 13:40:23.471584 tx_last_pass[1][1][3] = 0
4616 13:40:23.471676 tx_win_center[1][1][4] = 0
4617 13:40:23.474589 tx_first_pass[1][1][4] = 0
4618 13:40:23.477813 tx_last_pass[1][1][4] = 0
4619 13:40:23.477928 tx_win_center[1][1][5] = 0
4620 13:40:23.481054 tx_first_pass[1][1][5] = 0
4621 13:40:23.484272 tx_last_pass[1][1][5] = 0
4622 13:40:23.487892 tx_win_center[1][1][6] = 0
4623 13:40:23.487981 tx_first_pass[1][1][6] = 0
4624 13:40:23.490945 tx_last_pass[1][1][6] = 0
4625 13:40:23.494308 tx_win_center[1][1][7] = 0
4626 13:40:23.498100 tx_first_pass[1][1][7] = 0
4627 13:40:23.498188 tx_last_pass[1][1][7] = 0
4628 13:40:23.501008 tx_win_center[1][1][8] = 0
4629 13:40:23.504355 tx_first_pass[1][1][8] = 0
4630 13:40:23.504483 tx_last_pass[1][1][8] = 0
4631 13:40:23.507781 tx_win_center[1][1][9] = 0
4632 13:40:23.510829 tx_first_pass[1][1][9] = 0
4633 13:40:23.514653 tx_last_pass[1][1][9] = 0
4634 13:40:23.514756 tx_win_center[1][1][10] = 0
4635 13:40:23.517869 tx_first_pass[1][1][10] = 0
4636 13:40:23.521416 tx_last_pass[1][1][10] = 0
4637 13:40:23.524314 tx_win_center[1][1][11] = 0
4638 13:40:23.524406 tx_first_pass[1][1][11] = 0
4639 13:40:23.527351 tx_last_pass[1][1][11] = 0
4640 13:40:23.530898 tx_win_center[1][1][12] = 0
4641 13:40:23.534474 tx_first_pass[1][1][12] = 0
4642 13:40:23.534593 tx_last_pass[1][1][12] = 0
4643 13:40:23.537237 tx_win_center[1][1][13] = 0
4644 13:40:23.540795 tx_first_pass[1][1][13] = 0
4645 13:40:23.543926 tx_last_pass[1][1][13] = 0
4646 13:40:23.544020 tx_win_center[1][1][14] = 0
4647 13:40:23.547211 tx_first_pass[1][1][14] = 0
4648 13:40:23.550545 tx_last_pass[1][1][14] = 0
4649 13:40:23.554394 tx_win_center[1][1][15] = 0
4650 13:40:23.557562 tx_first_pass[1][1][15] = 0
4651 13:40:23.557656 tx_last_pass[1][1][15] = 0
4652 13:40:23.560824 dump params rx window
4653 13:40:23.564103 rx_firspass[0][0][0] = 0
4654 13:40:23.564226 rx_lastpass[0][0][0] = 0
4655 13:40:23.567317 rx_firspass[0][0][1] = 0
4656 13:40:23.570601 rx_lastpass[0][0][1] = 0
4657 13:40:23.570695 rx_firspass[0][0][2] = 0
4658 13:40:23.573885 rx_lastpass[0][0][2] = 0
4659 13:40:23.577084 rx_firspass[0][0][3] = 0
4660 13:40:23.577176 rx_lastpass[0][0][3] = 0
4661 13:40:23.580239 rx_firspass[0][0][4] = 0
4662 13:40:23.584077 rx_lastpass[0][0][4] = 0
4663 13:40:23.584202 rx_firspass[0][0][5] = 0
4664 13:40:23.587345 rx_lastpass[0][0][5] = 0
4665 13:40:23.590689 rx_firspass[0][0][6] = 0
4666 13:40:23.590818 rx_lastpass[0][0][6] = 0
4667 13:40:23.593964 rx_firspass[0][0][7] = 0
4668 13:40:23.597102 rx_lastpass[0][0][7] = 0
4669 13:40:23.600184 rx_firspass[0][0][8] = 0
4670 13:40:23.600274 rx_lastpass[0][0][8] = 0
4671 13:40:23.603756 rx_firspass[0][0][9] = 0
4672 13:40:23.607201 rx_lastpass[0][0][9] = 0
4673 13:40:23.607287 rx_firspass[0][0][10] = 0
4674 13:40:23.610048 rx_lastpass[0][0][10] = 0
4675 13:40:23.613437 rx_firspass[0][0][11] = 0
4676 13:40:23.613522 rx_lastpass[0][0][11] = 0
4677 13:40:23.616911 rx_firspass[0][0][12] = 0
4678 13:40:23.620451 rx_lastpass[0][0][12] = 0
4679 13:40:23.623752 rx_firspass[0][0][13] = 0
4680 13:40:23.623835 rx_lastpass[0][0][13] = 0
4681 13:40:23.626687 rx_firspass[0][0][14] = 0
4682 13:40:23.629949 rx_lastpass[0][0][14] = 0
4683 13:40:23.630035 rx_firspass[0][0][15] = 0
4684 13:40:23.633636 rx_lastpass[0][0][15] = 0
4685 13:40:23.636819 rx_firspass[0][1][0] = 0
4686 13:40:23.639908 rx_lastpass[0][1][0] = 0
4687 13:40:23.640029 rx_firspass[0][1][1] = 0
4688 13:40:23.643556 rx_lastpass[0][1][1] = 0
4689 13:40:23.646829 rx_firspass[0][1][2] = 0
4690 13:40:23.646930 rx_lastpass[0][1][2] = 0
4691 13:40:23.650362 rx_firspass[0][1][3] = 0
4692 13:40:23.653239 rx_lastpass[0][1][3] = 0
4693 13:40:23.653335 rx_firspass[0][1][4] = 0
4694 13:40:23.656475 rx_lastpass[0][1][4] = 0
4695 13:40:23.659789 rx_firspass[0][1][5] = 0
4696 13:40:23.659874 rx_lastpass[0][1][5] = 0
4697 13:40:23.663668 rx_firspass[0][1][6] = 0
4698 13:40:23.667056 rx_lastpass[0][1][6] = 0
4699 13:40:23.670329 rx_firspass[0][1][7] = 0
4700 13:40:23.670411 rx_lastpass[0][1][7] = 0
4701 13:40:23.673587 rx_firspass[0][1][8] = 0
4702 13:40:23.676764 rx_lastpass[0][1][8] = 0
4703 13:40:23.676860 rx_firspass[0][1][9] = 0
4704 13:40:23.680110 rx_lastpass[0][1][9] = 0
4705 13:40:23.683223 rx_firspass[0][1][10] = 0
4706 13:40:23.683355 rx_lastpass[0][1][10] = 0
4707 13:40:23.686842 rx_firspass[0][1][11] = 0
4708 13:40:23.690063 rx_lastpass[0][1][11] = 0
4709 13:40:23.690191 rx_firspass[0][1][12] = 0
4710 13:40:23.693462 rx_lastpass[0][1][12] = 0
4711 13:40:23.696588 rx_firspass[0][1][13] = 0
4712 13:40:23.699935 rx_lastpass[0][1][13] = 0
4713 13:40:23.700045 rx_firspass[0][1][14] = 0
4714 13:40:23.703704 rx_lastpass[0][1][14] = 0
4715 13:40:23.706906 rx_firspass[0][1][15] = 0
4716 13:40:23.710112 rx_lastpass[0][1][15] = 0
4717 13:40:23.710224 rx_firspass[1][0][0] = 0
4718 13:40:23.713301 rx_lastpass[1][0][0] = 0
4719 13:40:23.716773 rx_firspass[1][0][1] = 0
4720 13:40:23.716871 rx_lastpass[1][0][1] = 0
4721 13:40:23.720020 rx_firspass[1][0][2] = 0
4722 13:40:23.723290 rx_lastpass[1][0][2] = 0
4723 13:40:23.723390 rx_firspass[1][0][3] = 0
4724 13:40:23.726438 rx_lastpass[1][0][3] = 0
4725 13:40:23.730176 rx_firspass[1][0][4] = 0
4726 13:40:23.730299 rx_lastpass[1][0][4] = 0
4727 13:40:23.732962 rx_firspass[1][0][5] = 0
4728 13:40:23.736609 rx_lastpass[1][0][5] = 0
4729 13:40:23.736711 rx_firspass[1][0][6] = 0
4730 13:40:23.739522 rx_lastpass[1][0][6] = 0
4731 13:40:23.743042 rx_firspass[1][0][7] = 0
4732 13:40:23.746542 rx_lastpass[1][0][7] = 0
4733 13:40:23.746666 rx_firspass[1][0][8] = 0
4734 13:40:23.749448 rx_lastpass[1][0][8] = 0
4735 13:40:23.753328 rx_firspass[1][0][9] = 0
4736 13:40:23.753447 rx_lastpass[1][0][9] = 0
4737 13:40:23.756395 rx_firspass[1][0][10] = 0
4738 13:40:23.759423 rx_lastpass[1][0][10] = 0
4739 13:40:23.759520 rx_firspass[1][0][11] = 0
4740 13:40:23.762971 rx_lastpass[1][0][11] = 0
4741 13:40:23.766352 rx_firspass[1][0][12] = 0
4742 13:40:23.769537 rx_lastpass[1][0][12] = 0
4743 13:40:23.769625 rx_firspass[1][0][13] = 0
4744 13:40:23.772750 rx_lastpass[1][0][13] = 0
4745 13:40:23.775953 rx_firspass[1][0][14] = 0
4746 13:40:23.776036 rx_lastpass[1][0][14] = 0
4747 13:40:23.779314 rx_firspass[1][0][15] = 0
4748 13:40:23.782549 rx_lastpass[1][0][15] = 0
4749 13:40:23.785827 rx_firspass[1][1][0] = 0
4750 13:40:23.785911 rx_lastpass[1][1][0] = 0
4751 13:40:23.789780 rx_firspass[1][1][1] = 0
4752 13:40:23.792946 rx_lastpass[1][1][1] = 0
4753 13:40:23.793036 rx_firspass[1][1][2] = 0
4754 13:40:23.796243 rx_lastpass[1][1][2] = 0
4755 13:40:23.799459 rx_firspass[1][1][3] = 0
4756 13:40:23.799546 rx_lastpass[1][1][3] = 0
4757 13:40:23.802659 rx_firspass[1][1][4] = 0
4758 13:40:23.805789 rx_lastpass[1][1][4] = 0
4759 13:40:23.805893 rx_firspass[1][1][5] = 0
4760 13:40:23.809047 rx_lastpass[1][1][5] = 0
4761 13:40:23.812309 rx_firspass[1][1][6] = 0
4762 13:40:23.816282 rx_lastpass[1][1][6] = 0
4763 13:40:23.816373 rx_firspass[1][1][7] = 0
4764 13:40:23.819172 rx_lastpass[1][1][7] = 0
4765 13:40:23.822759 rx_firspass[1][1][8] = 0
4766 13:40:23.822879 rx_lastpass[1][1][8] = 0
4767 13:40:23.826007 rx_firspass[1][1][9] = 0
4768 13:40:23.829024 rx_lastpass[1][1][9] = 0
4769 13:40:23.829145 rx_firspass[1][1][10] = 0
4770 13:40:23.832298 rx_lastpass[1][1][10] = 0
4771 13:40:23.835514 rx_firspass[1][1][11] = 0
4772 13:40:23.838775 rx_lastpass[1][1][11] = 0
4773 13:40:23.838897 rx_firspass[1][1][12] = 0
4774 13:40:23.842513 rx_lastpass[1][1][12] = 0
4775 13:40:23.845590 rx_firspass[1][1][13] = 0
4776 13:40:23.845706 rx_lastpass[1][1][13] = 0
4777 13:40:23.848705 rx_firspass[1][1][14] = 0
4778 13:40:23.852387 rx_lastpass[1][1][14] = 0
4779 13:40:23.855411 rx_firspass[1][1][15] = 0
4780 13:40:23.855525 rx_lastpass[1][1][15] = 0
4781 13:40:23.858827 dump params clk_delay
4782 13:40:23.858904 clk_delay[0] = 0
4783 13:40:23.862472 clk_delay[1] = 0
4784 13:40:23.862568 dump params dqs_delay
4785 13:40:23.865534 dqs_delay[0][0] = 0
4786 13:40:23.865623 dqs_delay[0][1] = 0
4787 13:40:23.868575 dqs_delay[1][0] = 0
4788 13:40:23.872450 dqs_delay[1][1] = 0
4789 13:40:23.875616 dump params delay_cell_unit = 735
4790 13:40:23.875732 dump source = 0x0
4791 13:40:23.878670 dump params frequency:800
4792 13:40:23.878791 dump params rank number:2
4793 13:40:23.878911
4794 13:40:23.882256 dump params write leveling
4795 13:40:23.885483 write leveling[0][0][0] = 0x0
4796 13:40:23.888682 write leveling[0][0][1] = 0x0
4797 13:40:23.891940 write leveling[0][1][0] = 0x0
4798 13:40:23.892055 write leveling[0][1][1] = 0x0
4799 13:40:23.895329 write leveling[1][0][0] = 0x0
4800 13:40:23.898493 write leveling[1][0][1] = 0x0
4801 13:40:23.902370 write leveling[1][1][0] = 0x0
4802 13:40:23.905567 write leveling[1][1][1] = 0x0
4803 13:40:23.905656 dump params cbt_cs
4804 13:40:23.908744 cbt_cs[0][0] = 0x0
4805 13:40:23.908833 cbt_cs[0][1] = 0x0
4806 13:40:23.912054 cbt_cs[1][0] = 0x0
4807 13:40:23.912141 cbt_cs[1][1] = 0x0
4808 13:40:23.915233 dump params cbt_mr12
4809 13:40:23.915365 cbt_mr12[0][0] = 0x0
4810 13:40:23.918440 cbt_mr12[0][1] = 0x0
4811 13:40:23.921653 cbt_mr12[1][0] = 0x0
4812 13:40:23.921776 cbt_mr12[1][1] = 0x0
4813 13:40:23.925262 dump params tx window
4814 13:40:23.925386 tx_center_min[0][0][0] = 0
4815 13:40:23.928951 tx_center_max[0][0][0] = 0
4816 13:40:23.932025 tx_center_min[0][0][1] = 0
4817 13:40:23.935222 tx_center_max[0][0][1] = 0
4818 13:40:23.935347 tx_center_min[0][1][0] = 0
4819 13:40:23.938445 tx_center_max[0][1][0] = 0
4820 13:40:23.941639 tx_center_min[0][1][1] = 0
4821 13:40:23.944883 tx_center_max[0][1][1] = 0
4822 13:40:23.945003 tx_center_min[1][0][0] = 0
4823 13:40:23.948641 tx_center_max[1][0][0] = 0
4824 13:40:23.951846 tx_center_min[1][0][1] = 0
4825 13:40:23.955175 tx_center_max[1][0][1] = 0
4826 13:40:23.955306 tx_center_min[1][1][0] = 0
4827 13:40:23.958456 tx_center_max[1][1][0] = 0
4828 13:40:23.961623 tx_center_min[1][1][1] = 0
4829 13:40:23.965283 tx_center_max[1][1][1] = 0
4830 13:40:23.965408 dump params tx window
4831 13:40:23.968151 tx_win_center[0][0][0] = 0
4832 13:40:23.971561 tx_first_pass[0][0][0] = 0
4833 13:40:23.971687 tx_last_pass[0][0][0] = 0
4834 13:40:23.975428 tx_win_center[0][0][1] = 0
4835 13:40:23.978734 tx_first_pass[0][0][1] = 0
4836 13:40:23.978858 tx_last_pass[0][0][1] = 0
4837 13:40:23.981880 tx_win_center[0][0][2] = 0
4838 13:40:23.984971 tx_first_pass[0][0][2] = 0
4839 13:40:23.988582 tx_last_pass[0][0][2] = 0
4840 13:40:23.988710 tx_win_center[0][0][3] = 0
4841 13:40:23.992015 tx_first_pass[0][0][3] = 0
4842 13:40:23.995176 tx_last_pass[0][0][3] = 0
4843 13:40:23.998429 tx_win_center[0][0][4] = 0
4844 13:40:23.998545 tx_first_pass[0][0][4] = 0
4845 13:40:24.001742 tx_last_pass[0][0][4] = 0
4846 13:40:24.004932 tx_win_center[0][0][5] = 0
4847 13:40:24.005039 tx_first_pass[0][0][5] = 0
4848 13:40:24.008814 tx_last_pass[0][0][5] = 0
4849 13:40:24.012063 tx_win_center[0][0][6] = 0
4850 13:40:24.015360 tx_first_pass[0][0][6] = 0
4851 13:40:24.015468 tx_last_pass[0][0][6] = 0
4852 13:40:24.018654 tx_win_center[0][0][7] = 0
4853 13:40:24.021294 tx_first_pass[0][0][7] = 0
4854 13:40:24.025229 tx_last_pass[0][0][7] = 0
4855 13:40:24.025320 tx_win_center[0][0][8] = 0
4856 13:40:24.028439 tx_first_pass[0][0][8] = 0
4857 13:40:24.031374 tx_last_pass[0][0][8] = 0
4858 13:40:24.031491 tx_win_center[0][0][9] = 0
4859 13:40:24.035020 tx_first_pass[0][0][9] = 0
4860 13:40:24.038097 tx_last_pass[0][0][9] = 0
4861 13:40:24.041383 tx_win_center[0][0][10] = 0
4862 13:40:24.041475 tx_first_pass[0][0][10] = 0
4863 13:40:24.044501 tx_last_pass[0][0][10] = 0
4864 13:40:24.048321 tx_win_center[0][0][11] = 0
4865 13:40:24.051346 tx_first_pass[0][0][11] = 0
4866 13:40:24.051477 tx_last_pass[0][0][11] = 0
4867 13:40:24.054954 tx_win_center[0][0][12] = 0
4868 13:40:24.058189 tx_first_pass[0][0][12] = 0
4869 13:40:24.061598 tx_last_pass[0][0][12] = 0
4870 13:40:24.061710 tx_win_center[0][0][13] = 0
4871 13:40:24.064802 tx_first_pass[0][0][13] = 0
4872 13:40:24.067812 tx_last_pass[0][0][13] = 0
4873 13:40:24.070957 tx_win_center[0][0][14] = 0
4874 13:40:24.074716 tx_first_pass[0][0][14] = 0
4875 13:40:24.074798 tx_last_pass[0][0][14] = 0
4876 13:40:24.077737 tx_win_center[0][0][15] = 0
4877 13:40:24.080920 tx_first_pass[0][0][15] = 0
4878 13:40:24.084658 tx_last_pass[0][0][15] = 0
4879 13:40:24.084741 tx_win_center[0][1][0] = 0
4880 13:40:24.087892 tx_first_pass[0][1][0] = 0
4881 13:40:24.091004 tx_last_pass[0][1][0] = 0
4882 13:40:24.091094 tx_win_center[0][1][1] = 0
4883 13:40:24.094861 tx_first_pass[0][1][1] = 0
4884 13:40:24.098002 tx_last_pass[0][1][1] = 0
4885 13:40:24.101226 tx_win_center[0][1][2] = 0
4886 13:40:24.101346 tx_first_pass[0][1][2] = 0
4887 13:40:24.104092 tx_last_pass[0][1][2] = 0
4888 13:40:24.107782 tx_win_center[0][1][3] = 0
4889 13:40:24.110760 tx_first_pass[0][1][3] = 0
4890 13:40:24.110842 tx_last_pass[0][1][3] = 0
4891 13:40:24.114671 tx_win_center[0][1][4] = 0
4892 13:40:24.117855 tx_first_pass[0][1][4] = 0
4893 13:40:24.117940 tx_last_pass[0][1][4] = 0
4894 13:40:24.121154 tx_win_center[0][1][5] = 0
4895 13:40:24.124393 tx_first_pass[0][1][5] = 0
4896 13:40:24.127676 tx_last_pass[0][1][5] = 0
4897 13:40:24.127771 tx_win_center[0][1][6] = 0
4898 13:40:24.130776 tx_first_pass[0][1][6] = 0
4899 13:40:24.134120 tx_last_pass[0][1][6] = 0
4900 13:40:24.134237 tx_win_center[0][1][7] = 0
4901 13:40:24.137763 tx_first_pass[0][1][7] = 0
4902 13:40:24.140721 tx_last_pass[0][1][7] = 0
4903 13:40:24.144460 tx_win_center[0][1][8] = 0
4904 13:40:24.144548 tx_first_pass[0][1][8] = 0
4905 13:40:24.147538 tx_last_pass[0][1][8] = 0
4906 13:40:24.151234 tx_win_center[0][1][9] = 0
4907 13:40:24.154420 tx_first_pass[0][1][9] = 0
4908 13:40:24.154536 tx_last_pass[0][1][9] = 0
4909 13:40:24.157477 tx_win_center[0][1][10] = 0
4910 13:40:24.160691 tx_first_pass[0][1][10] = 0
4911 13:40:24.164448 tx_last_pass[0][1][10] = 0
4912 13:40:24.164542 tx_win_center[0][1][11] = 0
4913 13:40:24.167801 tx_first_pass[0][1][11] = 0
4914 13:40:24.170901 tx_last_pass[0][1][11] = 0
4915 13:40:24.174094 tx_win_center[0][1][12] = 0
4916 13:40:24.174220 tx_first_pass[0][1][12] = 0
4917 13:40:24.177387 tx_last_pass[0][1][12] = 0
4918 13:40:24.181005 tx_win_center[0][1][13] = 0
4919 13:40:24.184020 tx_first_pass[0][1][13] = 0
4920 13:40:24.184104 tx_last_pass[0][1][13] = 0
4921 13:40:24.187166 tx_win_center[0][1][14] = 0
4922 13:40:24.190686 tx_first_pass[0][1][14] = 0
4923 13:40:24.193895 tx_last_pass[0][1][14] = 0
4924 13:40:24.193982 tx_win_center[0][1][15] = 0
4925 13:40:24.197195 tx_first_pass[0][1][15] = 0
4926 13:40:24.200401 tx_last_pass[0][1][15] = 0
4927 13:40:24.203600 tx_win_center[1][0][0] = 0
4928 13:40:24.203686 tx_first_pass[1][0][0] = 0
4929 13:40:24.207420 tx_last_pass[1][0][0] = 0
4930 13:40:24.210560 tx_win_center[1][0][1] = 0
4931 13:40:24.213659 tx_first_pass[1][0][1] = 0
4932 13:40:24.213747 tx_last_pass[1][0][1] = 0
4933 13:40:24.217069 tx_win_center[1][0][2] = 0
4934 13:40:24.220580 tx_first_pass[1][0][2] = 0
4935 13:40:24.220665 tx_last_pass[1][0][2] = 0
4936 13:40:24.224098 tx_win_center[1][0][3] = 0
4937 13:40:24.227456 tx_first_pass[1][0][3] = 0
4938 13:40:24.230650 tx_last_pass[1][0][3] = 0
4939 13:40:24.230731 tx_win_center[1][0][4] = 0
4940 13:40:24.234028 tx_first_pass[1][0][4] = 0
4941 13:40:24.237380 tx_last_pass[1][0][4] = 0
4942 13:40:24.237468 tx_win_center[1][0][5] = 0
4943 13:40:24.240572 tx_first_pass[1][0][5] = 0
4944 13:40:24.243667 tx_last_pass[1][0][5] = 0
4945 13:40:24.247555 tx_win_center[1][0][6] = 0
4946 13:40:24.247681 tx_first_pass[1][0][6] = 0
4947 13:40:24.250597 tx_last_pass[1][0][6] = 0
4948 13:40:24.253602 tx_win_center[1][0][7] = 0
4949 13:40:24.257070 tx_first_pass[1][0][7] = 0
4950 13:40:24.257192 tx_last_pass[1][0][7] = 0
4951 13:40:24.260670 tx_win_center[1][0][8] = 0
4952 13:40:24.263791 tx_first_pass[1][0][8] = 0
4953 13:40:24.263877 tx_last_pass[1][0][8] = 0
4954 13:40:24.266873 tx_win_center[1][0][9] = 0
4955 13:40:24.270291 tx_first_pass[1][0][9] = 0
4956 13:40:24.274090 tx_last_pass[1][0][9] = 0
4957 13:40:24.274211 tx_win_center[1][0][10] = 0
4958 13:40:24.277193 tx_first_pass[1][0][10] = 0
4959 13:40:24.280450 tx_last_pass[1][0][10] = 0
4960 13:40:24.283701 tx_win_center[1][0][11] = 0
4961 13:40:24.283788 tx_first_pass[1][0][11] = 0
4962 13:40:24.286890 tx_last_pass[1][0][11] = 0
4963 13:40:24.290757 tx_win_center[1][0][12] = 0
4964 13:40:24.293957 tx_first_pass[1][0][12] = 0
4965 13:40:24.294073 tx_last_pass[1][0][12] = 0
4966 13:40:24.297237 tx_win_center[1][0][13] = 0
4967 13:40:24.300261 tx_first_pass[1][0][13] = 0
4968 13:40:24.303979 tx_last_pass[1][0][13] = 0
4969 13:40:24.304069 tx_win_center[1][0][14] = 0
4970 13:40:24.307173 tx_first_pass[1][0][14] = 0
4971 13:40:24.310516 tx_last_pass[1][0][14] = 0
4972 13:40:24.313718 tx_win_center[1][0][15] = 0
4973 13:40:24.313798 tx_first_pass[1][0][15] = 0
4974 13:40:24.316968 tx_last_pass[1][0][15] = 0
4975 13:40:24.320307 tx_win_center[1][1][0] = 0
4976 13:40:24.323366 tx_first_pass[1][1][0] = 0
4977 13:40:24.323474 tx_last_pass[1][1][0] = 0
4978 13:40:24.327048 tx_win_center[1][1][1] = 0
4979 13:40:24.330005 tx_first_pass[1][1][1] = 0
4980 13:40:24.333290 tx_last_pass[1][1][1] = 0
4981 13:40:24.333412 tx_win_center[1][1][2] = 0
4982 13:40:24.337313 tx_first_pass[1][1][2] = 0
4983 13:40:24.340569 tx_last_pass[1][1][2] = 0
4984 13:40:24.340654 tx_win_center[1][1][3] = 0
4985 13:40:24.343844 tx_first_pass[1][1][3] = 0
4986 13:40:24.346983 tx_last_pass[1][1][3] = 0
4987 13:40:24.350292 tx_win_center[1][1][4] = 0
4988 13:40:24.350377 tx_first_pass[1][1][4] = 0
4989 13:40:24.353522 tx_last_pass[1][1][4] = 0
4990 13:40:24.356760 tx_win_center[1][1][5] = 0
4991 13:40:24.359936 tx_first_pass[1][1][5] = 0
4992 13:40:24.360056 tx_last_pass[1][1][5] = 0
4993 13:40:24.363496 tx_win_center[1][1][6] = 0
4994 13:40:24.366896 tx_first_pass[1][1][6] = 0
4995 13:40:24.366987 tx_last_pass[1][1][6] = 0
4996 13:40:24.369768 tx_win_center[1][1][7] = 0
4997 13:40:24.373444 tx_first_pass[1][1][7] = 0
4998 13:40:24.376834 tx_last_pass[1][1][7] = 0
4999 13:40:24.376930 tx_win_center[1][1][8] = 0
5000 13:40:24.379970 tx_first_pass[1][1][8] = 0
5001 13:40:24.383309 tx_last_pass[1][1][8] = 0
5002 13:40:24.386605 tx_win_center[1][1][9] = 0
5003 13:40:24.386695 tx_first_pass[1][1][9] = 0
5004 13:40:24.389713 tx_last_pass[1][1][9] = 0
5005 13:40:24.393591 tx_win_center[1][1][10] = 0
5006 13:40:24.396672 tx_first_pass[1][1][10] = 0
5007 13:40:24.396764 tx_last_pass[1][1][10] = 0
5008 13:40:24.399880 tx_win_center[1][1][11] = 0
5009 13:40:24.403020 tx_first_pass[1][1][11] = 0
5010 13:40:24.406316 tx_last_pass[1][1][11] = 0
5011 13:40:24.406423 tx_win_center[1][1][12] = 0
5012 13:40:24.410208 tx_first_pass[1][1][12] = 0
5013 13:40:24.413450 tx_last_pass[1][1][12] = 0
5014 13:40:24.416762 tx_win_center[1][1][13] = 0
5015 13:40:24.416852 tx_first_pass[1][1][13] = 0
5016 13:40:24.419923 tx_last_pass[1][1][13] = 0
5017 13:40:24.423281 tx_win_center[1][1][14] = 0
5018 13:40:24.423395 tx_first_pass[1][1][14] = 0
5019 13:40:24.426586 tx_last_pass[1][1][14] = 0
5020 13:40:24.429848 tx_win_center[1][1][15] = 0
5021 13:40:24.433069 tx_first_pass[1][1][15] = 0
5022 13:40:24.436390 tx_last_pass[1][1][15] = 0
5023 13:40:24.436508 dump params rx window
5024 13:40:24.439687 rx_firspass[0][0][0] = 0
5025 13:40:24.439804 rx_lastpass[0][0][0] = 0
5026 13:40:24.443360 rx_firspass[0][0][1] = 0
5027 13:40:24.446309 rx_lastpass[0][0][1] = 0
5028 13:40:24.449750 rx_firspass[0][0][2] = 0
5029 13:40:24.449841 rx_lastpass[0][0][2] = 0
5030 13:40:24.452890 rx_firspass[0][0][3] = 0
5031 13:40:24.456589 rx_lastpass[0][0][3] = 0
5032 13:40:24.456683 rx_firspass[0][0][4] = 0
5033 13:40:24.459759 rx_lastpass[0][0][4] = 0
5034 13:40:24.463032 rx_firspass[0][0][5] = 0
5035 13:40:24.463115 rx_lastpass[0][0][5] = 0
5036 13:40:24.466443 rx_firspass[0][0][6] = 0
5037 13:40:24.469673 rx_lastpass[0][0][6] = 0
5038 13:40:24.469787 rx_firspass[0][0][7] = 0
5039 13:40:24.473180 rx_lastpass[0][0][7] = 0
5040 13:40:24.476236 rx_firspass[0][0][8] = 0
5041 13:40:24.476318 rx_lastpass[0][0][8] = 0
5042 13:40:24.479854 rx_firspass[0][0][9] = 0
5043 13:40:24.483119 rx_lastpass[0][0][9] = 0
5044 13:40:24.486251 rx_firspass[0][0][10] = 0
5045 13:40:24.486370 rx_lastpass[0][0][10] = 0
5046 13:40:24.489638 rx_firspass[0][0][11] = 0
5047 13:40:24.493169 rx_lastpass[0][0][11] = 0
5048 13:40:24.493287 rx_firspass[0][0][12] = 0
5049 13:40:24.496538 rx_lastpass[0][0][12] = 0
5050 13:40:24.499511 rx_firspass[0][0][13] = 0
5051 13:40:24.502716 rx_lastpass[0][0][13] = 0
5052 13:40:24.502830 rx_firspass[0][0][14] = 0
5053 13:40:24.506563 rx_lastpass[0][0][14] = 0
5054 13:40:24.509704 rx_firspass[0][0][15] = 0
5055 13:40:24.509830 rx_lastpass[0][0][15] = 0
5056 13:40:24.512799 rx_firspass[0][1][0] = 0
5057 13:40:24.516043 rx_lastpass[0][1][0] = 0
5058 13:40:24.516158 rx_firspass[0][1][1] = 0
5059 13:40:24.519440 rx_lastpass[0][1][1] = 0
5060 13:40:24.522734 rx_firspass[0][1][2] = 0
5061 13:40:24.522821 rx_lastpass[0][1][2] = 0
5062 13:40:24.526023 rx_firspass[0][1][3] = 0
5063 13:40:24.529950 rx_lastpass[0][1][3] = 0
5064 13:40:24.533274 rx_firspass[0][1][4] = 0
5065 13:40:24.533393 rx_lastpass[0][1][4] = 0
5066 13:40:24.536573 rx_firspass[0][1][5] = 0
5067 13:40:24.539742 rx_lastpass[0][1][5] = 0
5068 13:40:24.539851 rx_firspass[0][1][6] = 0
5069 13:40:24.543030 rx_lastpass[0][1][6] = 0
5070 13:40:24.546291 rx_firspass[0][1][7] = 0
5071 13:40:24.546403 rx_lastpass[0][1][7] = 0
5072 13:40:24.549566 rx_firspass[0][1][8] = 0
5073 13:40:24.552765 rx_lastpass[0][1][8] = 0
5074 13:40:24.552885 rx_firspass[0][1][9] = 0
5075 13:40:24.556026 rx_lastpass[0][1][9] = 0
5076 13:40:24.559288 rx_firspass[0][1][10] = 0
5077 13:40:24.562835 rx_lastpass[0][1][10] = 0
5078 13:40:24.562949 rx_firspass[0][1][11] = 0
5079 13:40:24.565812 rx_lastpass[0][1][11] = 0
5080 13:40:24.569609 rx_firspass[0][1][12] = 0
5081 13:40:24.569732 rx_lastpass[0][1][12] = 0
5082 13:40:24.572750 rx_firspass[0][1][13] = 0
5083 13:40:24.576090 rx_lastpass[0][1][13] = 0
5084 13:40:24.579179 rx_firspass[0][1][14] = 0
5085 13:40:24.579299 rx_lastpass[0][1][14] = 0
5086 13:40:24.582620 rx_firspass[0][1][15] = 0
5087 13:40:24.585699 rx_lastpass[0][1][15] = 0
5088 13:40:24.585821 rx_firspass[1][0][0] = 0
5089 13:40:24.589479 rx_lastpass[1][0][0] = 0
5090 13:40:24.592522 rx_firspass[1][0][1] = 0
5091 13:40:24.592643 rx_lastpass[1][0][1] = 0
5092 13:40:24.596400 rx_firspass[1][0][2] = 0
5093 13:40:24.599472 rx_lastpass[1][0][2] = 0
5094 13:40:24.602506 rx_firspass[1][0][3] = 0
5095 13:40:24.602605 rx_lastpass[1][0][3] = 0
5096 13:40:24.605897 rx_firspass[1][0][4] = 0
5097 13:40:24.609197 rx_lastpass[1][0][4] = 0
5098 13:40:24.609324 rx_firspass[1][0][5] = 0
5099 13:40:24.612556 rx_lastpass[1][0][5] = 0
5100 13:40:24.615692 rx_firspass[1][0][6] = 0
5101 13:40:24.615783 rx_lastpass[1][0][6] = 0
5102 13:40:24.619567 rx_firspass[1][0][7] = 0
5103 13:40:24.622069 rx_lastpass[1][0][7] = 0
5104 13:40:24.622188 rx_firspass[1][0][8] = 0
5105 13:40:24.626024 rx_lastpass[1][0][8] = 0
5106 13:40:24.629301 rx_firspass[1][0][9] = 0
5107 13:40:24.632689 rx_lastpass[1][0][9] = 0
5108 13:40:24.632784 rx_firspass[1][0][10] = 0
5109 13:40:24.635886 rx_lastpass[1][0][10] = 0
5110 13:40:24.639065 rx_firspass[1][0][11] = 0
5111 13:40:24.639149 rx_lastpass[1][0][11] = 0
5112 13:40:24.642379 rx_firspass[1][0][12] = 0
5113 13:40:24.645704 rx_lastpass[1][0][12] = 0
5114 13:40:24.645786 rx_firspass[1][0][13] = 0
5115 13:40:24.649060 rx_lastpass[1][0][13] = 0
5116 13:40:24.652427 rx_firspass[1][0][14] = 0
5117 13:40:24.655752 rx_lastpass[1][0][14] = 0
5118 13:40:24.655852 rx_firspass[1][0][15] = 0
5119 13:40:24.659122 rx_lastpass[1][0][15] = 0
5120 13:40:24.661871 rx_firspass[1][1][0] = 0
5121 13:40:24.661981 rx_lastpass[1][1][0] = 0
5122 13:40:24.665241 rx_firspass[1][1][1] = 0
5123 13:40:24.669147 rx_lastpass[1][1][1] = 0
5124 13:40:24.672440 rx_firspass[1][1][2] = 0
5125 13:40:24.672521 rx_lastpass[1][1][2] = 0
5126 13:40:24.675613 rx_firspass[1][1][3] = 0
5127 13:40:24.678633 rx_lastpass[1][1][3] = 0
5128 13:40:24.678712 rx_firspass[1][1][4] = 0
5129 13:40:24.682097 rx_lastpass[1][1][4] = 0
5130 13:40:24.685433 rx_firspass[1][1][5] = 0
5131 13:40:24.685514 rx_lastpass[1][1][5] = 0
5132 13:40:24.688655 rx_firspass[1][1][6] = 0
5133 13:40:24.692082 rx_lastpass[1][1][6] = 0
5134 13:40:24.692163 rx_firspass[1][1][7] = 0
5135 13:40:24.695439 rx_lastpass[1][1][7] = 0
5136 13:40:24.698774 rx_firspass[1][1][8] = 0
5137 13:40:24.698906 rx_lastpass[1][1][8] = 0
5138 13:40:24.702110 rx_firspass[1][1][9] = 0
5139 13:40:24.705552 rx_lastpass[1][1][9] = 0
5140 13:40:24.708455 rx_firspass[1][1][10] = 0
5141 13:40:24.708539 rx_lastpass[1][1][10] = 0
5142 13:40:24.711995 rx_firspass[1][1][11] = 0
5143 13:40:24.715227 rx_lastpass[1][1][11] = 0
5144 13:40:24.715340 rx_firspass[1][1][12] = 0
5145 13:40:24.718676 rx_lastpass[1][1][12] = 0
5146 13:40:24.721975 rx_firspass[1][1][13] = 0
5147 13:40:24.725355 rx_lastpass[1][1][13] = 0
5148 13:40:24.725435 rx_firspass[1][1][14] = 0
5149 13:40:24.728695 rx_lastpass[1][1][14] = 0
5150 13:40:24.731590 rx_firspass[1][1][15] = 0
5151 13:40:24.731685 rx_lastpass[1][1][15] = 0
5152 13:40:24.734831 dump params clk_delay
5153 13:40:24.738246 clk_delay[0] = 0
5154 13:40:24.738346 clk_delay[1] = 0
5155 13:40:24.741534 dump params dqs_delay
5156 13:40:24.741617 dqs_delay[0][0] = 0
5157 13:40:24.744752 dqs_delay[0][1] = 0
5158 13:40:24.744870 dqs_delay[1][0] = 0
5159 13:40:24.748097 dqs_delay[1][1] = 0
5160 13:40:24.751440 dump params delay_cell_unit = 735
5161 13:40:24.751585 mt_set_emi_preloader end
5162 13:40:24.758158 [mt_mem_init] dram size: 0x100000000, rank number: 2
5163 13:40:24.761509 [complex_mem_test] start addr:0x40000000, len:20480
5164 13:40:24.798782 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5165 13:40:24.805325 [complex_mem_test] start addr:0x80000000, len:20480
5166 13:40:24.840974 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5167 13:40:24.847298 [complex_mem_test] start addr:0xc0000000, len:20480
5168 13:40:24.883192 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5169 13:40:24.889745 [complex_mem_test] start addr:0x56000000, len:8192
5170 13:40:24.906400 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5171 13:40:24.906498 ddr_geometry:1
5172 13:40:24.913253 [complex_mem_test] start addr:0x80000000, len:8192
5173 13:40:24.930476 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5174 13:40:24.933480 dram_init: dram init end (result: 0)
5175 13:40:24.940309 Successfully loaded DRAM blobs and ran DRAM calibration
5176 13:40:24.950183 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5177 13:40:24.950279 CBMEM:
5178 13:40:24.953602 IMD: root @ 00000000fffff000 254 entries.
5179 13:40:24.956998 IMD: root @ 00000000ffffec00 62 entries.
5180 13:40:24.963476 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5181 13:40:24.970652 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5182 13:40:24.973892 in-header: 03 a1 00 00 08 00 00 00
5183 13:40:24.977270 in-data: 84 60 60 10 00 00 00 00
5184 13:40:24.980488 Chrome EC: clear events_b mask to 0x0000000020004000
5185 13:40:24.987642 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5186 13:40:24.990898 in-header: 03 fd 00 00 00 00 00 00
5187 13:40:24.990984 in-data:
5188 13:40:24.997300 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5189 13:40:24.997393 CBFS @ 21000 size 3d4000
5190 13:40:25.004075 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5191 13:40:25.007222 CBFS: Locating 'fallback/ramstage'
5192 13:40:25.010446 CBFS: Found @ offset 10d40 size d563
5193 13:40:25.032425 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5194 13:40:25.044396 Accumulated console time in romstage 13650 ms
5195 13:40:25.044504
5196 13:40:25.044578
5197 13:40:25.054213 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5198 13:40:25.057218 ARM64: Exception handlers installed.
5199 13:40:25.057303 ARM64: Testing exception
5200 13:40:25.060862 ARM64: Done test exception
5201 13:40:25.063922 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5202 13:40:25.067448 Manufacturer: ef
5203 13:40:25.070946 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5204 13:40:25.077533 WARNING: RO_VPD is uninitialized or empty.
5205 13:40:25.080875 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5206 13:40:25.084103 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5207 13:40:25.093928 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5208 13:40:25.097298 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5209 13:40:25.104379 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5210 13:40:25.104471 Enumerating buses...
5211 13:40:25.110864 Show all devs... Before device enumeration.
5212 13:40:25.110959 Root Device: enabled 1
5213 13:40:25.114090 CPU_CLUSTER: 0: enabled 1
5214 13:40:25.114208 CPU: 00: enabled 1
5215 13:40:25.117348 Compare with tree...
5216 13:40:25.120551 Root Device: enabled 1
5217 13:40:25.120644 CPU_CLUSTER: 0: enabled 1
5218 13:40:25.124259 CPU: 00: enabled 1
5219 13:40:25.127240 Root Device scanning...
5220 13:40:25.127361 root_dev_scan_bus for Root Device
5221 13:40:25.130884 CPU_CLUSTER: 0 enabled
5222 13:40:25.134246 root_dev_scan_bus for Root Device done
5223 13:40:25.141109 scan_bus: scanning of bus Root Device took 10689 usecs
5224 13:40:25.141210 done
5225 13:40:25.143756 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5226 13:40:25.147141 Allocating resources...
5227 13:40:25.147229 Reading resources...
5228 13:40:25.150537 Root Device read_resources bus 0 link: 0
5229 13:40:25.157210 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5230 13:40:25.157298 CPU: 00 missing read_resources
5231 13:40:25.163869 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5232 13:40:25.167190 Root Device read_resources bus 0 link: 0 done
5233 13:40:25.170735 Done reading resources.
5234 13:40:25.173702 Show resources in subtree (Root Device)...After reading.
5235 13:40:25.177379 Root Device child on link 0 CPU_CLUSTER: 0
5236 13:40:25.180877 CPU_CLUSTER: 0 child on link 0 CPU: 00
5237 13:40:25.190253 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5238 13:40:25.190352 CPU: 00
5239 13:40:25.193532 Setting resources...
5240 13:40:25.196840 Root Device assign_resources, bus 0 link: 0
5241 13:40:25.200171 CPU_CLUSTER: 0 missing set_resources
5242 13:40:25.203244 Root Device assign_resources, bus 0 link: 0
5243 13:40:25.206780 Done setting resources.
5244 13:40:25.213349 Show resources in subtree (Root Device)...After assigning values.
5245 13:40:25.216564 Root Device child on link 0 CPU_CLUSTER: 0
5246 13:40:25.219841 CPU_CLUSTER: 0 child on link 0 CPU: 00
5247 13:40:25.230276 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5248 13:40:25.230372 CPU: 00
5249 13:40:25.233493 Done allocating resources.
5250 13:40:25.236505 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5251 13:40:25.239907 Enabling resources...
5252 13:40:25.240001 done.
5253 13:40:25.243058 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5254 13:40:25.246707 Initializing devices...
5255 13:40:25.249982 Root Device init ...
5256 13:40:25.253326 mainboard_init: Starting display init.
5257 13:40:25.253431 ADC[4]: Raw value=75746 ID=0
5258 13:40:25.276802 anx7625_power_on_init: Init interface.
5259 13:40:25.280530 anx7625_disable_pd_protocol: Disabled PD feature.
5260 13:40:25.286947 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5261 13:40:25.333579 anx7625_start_dp_work: Secure OCM version=00
5262 13:40:25.336854 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5263 13:40:25.353675 sp_tx_get_edid_block: EDID Block = 1
5264 13:40:25.471485 Extracted contents:
5265 13:40:25.474571 header: 00 ff ff ff ff ff ff 00
5266 13:40:25.477833 serial number: 06 af 5c 14 00 00 00 00 00 1a
5267 13:40:25.481165 version: 01 04
5268 13:40:25.484434 basic params: 95 1a 0e 78 02
5269 13:40:25.487706 chroma info: 99 85 95 55 56 92 28 22 50 54
5270 13:40:25.491629 established: 00 00 00
5271 13:40:25.497644 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5272 13:40:25.501025 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5273 13:40:25.507848 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5274 13:40:25.514188 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5275 13:40:25.520925 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5276 13:40:25.524815 extensions: 00
5277 13:40:25.524910 checksum: ae
5278 13:40:25.524983
5279 13:40:25.528027 Manufacturer: AUO Model 145c Serial Number 0
5280 13:40:25.531028 Made week 0 of 2016
5281 13:40:25.531121 EDID version: 1.4
5282 13:40:25.534738 Digital display
5283 13:40:25.537752 6 bits per primary color channel
5284 13:40:25.537858 DisplayPort interface
5285 13:40:25.541068 Maximum image size: 26 cm x 14 cm
5286 13:40:25.544421 Gamma: 220%
5287 13:40:25.544542 Check DPMS levels
5288 13:40:25.547749 Supported color formats: RGB 4:4:4
5289 13:40:25.551001 First detailed timing is preferred timing
5290 13:40:25.554398 Established timings supported:
5291 13:40:25.557634 Standard timings supported:
5292 13:40:25.557750 Detailed timings
5293 13:40:25.564244 Hex of detail: ce1d56ea50001a3030204600009010000018
5294 13:40:25.567333 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5295 13:40:25.571130 0556 0586 05a6 0640 hborder 0
5296 13:40:25.574434 0300 0304 030a 031a vborder 0
5297 13:40:25.577829 -hsync -vsync
5298 13:40:25.581075 Did detailed timing
5299 13:40:25.584448 Hex of detail: 0000000f0000000000000000000000000020
5300 13:40:25.587586 Manufacturer-specified data, tag 15
5301 13:40:25.590853 Hex of detail: 000000fe0041554f0a202020202020202020
5302 13:40:25.594257 ASCII string: AUO
5303 13:40:25.597551 Hex of detail: 000000fe004231313658414230312e34200a
5304 13:40:25.600764 ASCII string: B116XAB01.4
5305 13:40:25.600848 Checksum
5306 13:40:25.603939 Checksum: 0xae (valid)
5307 13:40:25.610874 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5308 13:40:25.610976 DSI data_rate: 457800000 bps
5309 13:40:25.618513 anx7625_parse_edid: set default k value to 0x3d for panel
5310 13:40:25.621329 anx7625_parse_edid: pixelclock(76300).
5311 13:40:25.624614 hactive(1366), hsync(32), hfp(48), hbp(154)
5312 13:40:25.628438 vactive(768), vsync(6), vfp(4), vbp(16)
5313 13:40:25.631416 anx7625_dsi_config: config dsi.
5314 13:40:25.639326 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5315 13:40:25.660573 anx7625_dsi_config: success to config DSI
5316 13:40:25.663799 anx7625_dp_start: MIPI phy setup OK.
5317 13:40:25.666926 [SSUSB] Setting up USB HOST controller...
5318 13:40:25.670088 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5319 13:40:25.673934 [SSUSB] phy power-on done.
5320 13:40:25.677753 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5321 13:40:25.681128 in-header: 03 fc 01 00 00 00 00 00
5322 13:40:25.681244 in-data:
5323 13:40:25.684463 handle_proto3_response: EC response with error code: 1
5324 13:40:25.687811 SPM: pcm index = 1
5325 13:40:25.691044 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5326 13:40:25.694359 CBFS @ 21000 size 3d4000
5327 13:40:25.700950 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5328 13:40:25.703968 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5329 13:40:25.707285 CBFS: Found @ offset 1e7c0 size 1026
5330 13:40:25.714347 read SPI 0x3f808 0x1026: 1270 us, 3255 KB/s, 26.040 Mbps
5331 13:40:25.717531 SPM: binary array size = 2988
5332 13:40:25.720731 SPM: version = pcm_allinone_v1.17.2_20180829
5333 13:40:25.724314 SPM binary loaded in 32 msecs
5334 13:40:25.731740 spm_kick_im_to_fetch: ptr = 000000004021eec2
5335 13:40:25.734979 spm_kick_im_to_fetch: len = 2988
5336 13:40:25.735094 SPM: spm_kick_pcm_to_run
5337 13:40:25.738262 SPM: spm_kick_pcm_to_run done
5338 13:40:25.741350 SPM: spm_init done in 52 msecs
5339 13:40:25.744902 Root Device init finished in 494991 usecs
5340 13:40:25.748405 CPU_CLUSTER: 0 init ...
5341 13:40:25.757955 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5342 13:40:25.761526 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5343 13:40:25.764503 CBFS @ 21000 size 3d4000
5344 13:40:25.768428 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5345 13:40:25.771685 CBFS: Locating 'sspm.bin'
5346 13:40:25.774621 CBFS: Found @ offset 208c0 size 41cb
5347 13:40:25.784694 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5348 13:40:25.792370 CPU_CLUSTER: 0 init finished in 42806 usecs
5349 13:40:25.792511 Devices initialized
5350 13:40:25.795673 Show all devs... After init.
5351 13:40:25.799030 Root Device: enabled 1
5352 13:40:25.799150 CPU_CLUSTER: 0: enabled 1
5353 13:40:25.802449 CPU: 00: enabled 1
5354 13:40:25.806354 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5355 13:40:25.809500 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5356 13:40:25.812675 ELOG: NV offset 0x558000 size 0x1000
5357 13:40:25.820376 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5358 13:40:25.826874 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5359 13:40:25.830228 ELOG: Event(17) added with size 13 at 2024-05-28 13:39:28 UTC
5360 13:40:25.836439 out: cmd=0x121: 03 db 21 01 00 00 00 00
5361 13:40:25.839959 in-header: 03 0a 00 00 2c 00 00 00
5362 13:40:25.849969 in-data: 5b 4c 00 00 00 00 00 00 02 10 00 00 06 80 00 00 13 87 03 00 06 80 00 00 5c fe 00 00 06 80 00 00 29 e9 09 00 06 80 00 00 b0 29 0b 00
5363 13:40:25.853339 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5364 13:40:25.856283 in-header: 03 19 00 00 08 00 00 00
5365 13:40:25.859814 in-data: a2 e0 47 00 13 00 00 00
5366 13:40:25.862867 Chrome EC: UHEPI supported
5367 13:40:25.869666 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5368 13:40:25.873168 in-header: 03 e1 00 00 08 00 00 00
5369 13:40:25.876441 in-data: 84 20 60 10 00 00 00 00
5370 13:40:25.879591 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5371 13:40:25.886734 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5372 13:40:25.889939 in-header: 03 e1 00 00 08 00 00 00
5373 13:40:25.893042 in-data: 84 20 60 10 00 00 00 00
5374 13:40:25.899732 ELOG: Event(A1) added with size 10 at 2024-05-28 13:39:28 UTC
5375 13:40:25.906410 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5376 13:40:25.909621 ELOG: Event(A0) added with size 9 at 2024-05-28 13:39:28 UTC
5377 13:40:25.916211 elog_add_boot_reason: Logged dev mode boot
5378 13:40:25.916303 Finalize devices...
5379 13:40:25.919538 Devices finalized
5380 13:40:25.922983 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5381 13:40:25.929499 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5382 13:40:25.932733 ELOG: Event(91) added with size 10 at 2024-05-28 13:39:28 UTC
5383 13:40:25.935947 Writing coreboot table at 0xffeda000
5384 13:40:25.939257 0. 0000000000114000-000000000011efff: RAMSTAGE
5385 13:40:25.946002 1. 0000000040000000-000000004023cfff: RAMSTAGE
5386 13:40:25.949602 2. 000000004023d000-00000000545fffff: RAM
5387 13:40:25.952655 3. 0000000054600000-000000005465ffff: BL31
5388 13:40:25.956228 4. 0000000054660000-00000000ffed9fff: RAM
5389 13:40:25.962498 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5390 13:40:25.966217 6. 0000000100000000-000000013fffffff: RAM
5391 13:40:25.969101 Passing 5 GPIOs to payload:
5392 13:40:25.972836 NAME | PORT | POLARITY | VALUE
5393 13:40:25.975789 write protect | 0x00000096 | low | high
5394 13:40:25.982956 EC in RW | 0x000000b1 | high | undefined
5395 13:40:25.985848 EC interrupt | 0x00000097 | low | undefined
5396 13:40:25.992573 TPM interrupt | 0x00000099 | high | undefined
5397 13:40:25.995936 speaker enable | 0x000000af | high | undefined
5398 13:40:25.999192 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5399 13:40:26.003006 in-header: 03 f7 00 00 02 00 00 00
5400 13:40:26.006100 in-data: 04 00
5401 13:40:26.006193 Board ID: 4
5402 13:40:26.009172 ADC[3]: Raw value=215504 ID=1
5403 13:40:26.009289 RAM code: 1
5404 13:40:26.009390 SKU ID: 16
5405 13:40:26.016224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5406 13:40:26.016351 CBFS @ 21000 size 3d4000
5407 13:40:26.022737 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5408 13:40:26.029474 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 8003
5409 13:40:26.032602 coreboot table: 940 bytes.
5410 13:40:26.035875 IMD ROOT 0. 00000000fffff000 00001000
5411 13:40:26.039169 IMD SMALL 1. 00000000ffffe000 00001000
5412 13:40:26.042626 CONSOLE 2. 00000000fffde000 00020000
5413 13:40:26.045832 FMAP 3. 00000000fffdd000 0000047c
5414 13:40:26.049064 TIME STAMP 4. 00000000fffdc000 00000910
5415 13:40:26.052235 RAMOOPS 5. 00000000ffedc000 00100000
5416 13:40:26.055690 COREBOOT 6. 00000000ffeda000 00002000
5417 13:40:26.058913 IMD small region:
5418 13:40:26.062137 IMD ROOT 0. 00000000ffffec00 00000400
5419 13:40:26.065830 VBOOT WORK 1. 00000000ffffeb00 00000100
5420 13:40:26.069406 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5421 13:40:26.072494 VPD 3. 00000000ffffea60 0000006c
5422 13:40:26.078843 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5423 13:40:26.085639 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5424 13:40:26.088768 in-header: 03 e1 00 00 08 00 00 00
5425 13:40:26.091936 in-data: 84 20 60 10 00 00 00 00
5426 13:40:26.095587 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5427 13:40:26.098646 CBFS @ 21000 size 3d4000
5428 13:40:26.102266 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5429 13:40:26.105446 CBFS: Locating 'fallback/payload'
5430 13:40:26.111350 CBFS: Found @ offset dc040 size 439a0
5431 13:40:26.202548 read SPI 0xfd078 0x439a0: 84444 us, 3279 KB/s, 26.232 Mbps
5432 13:40:26.205530 Checking segment from ROM address 0x0000000040003a00
5433 13:40:26.212300 Checking segment from ROM address 0x0000000040003a1c
5434 13:40:26.215361 Loading segment from ROM address 0x0000000040003a00
5435 13:40:26.218704 code (compression=0)
5436 13:40:26.228574 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5437 13:40:26.235397 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5438 13:40:26.239004 it's not compressed!
5439 13:40:26.242263 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5440 13:40:26.248280 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5441 13:40:26.256756 Loading segment from ROM address 0x0000000040003a1c
5442 13:40:26.260011 Entry Point 0x0000000080000000
5443 13:40:26.260130 Loaded segments
5444 13:40:26.266300 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5445 13:40:26.269497 Jumping to boot code at 0000000080000000(00000000ffeda000)
5446 13:40:26.279339 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5447 13:40:26.282997 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5448 13:40:26.286085 CBFS @ 21000 size 3d4000
5449 13:40:26.293155 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5450 13:40:26.296246 CBFS: Locating 'fallback/bl31'
5451 13:40:26.299443 CBFS: Found @ offset 36dc0 size 5820
5452 13:40:26.310401 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5453 13:40:26.313571 Checking segment from ROM address 0x0000000040003a00
5454 13:40:26.320678 Checking segment from ROM address 0x0000000040003a1c
5455 13:40:26.323993 Loading segment from ROM address 0x0000000040003a00
5456 13:40:26.327014 code (compression=1)
5457 13:40:26.333684 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5458 13:40:26.343448 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5459 13:40:26.343581 using LZMA
5460 13:40:26.352243 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5461 13:40:26.358942 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5462 13:40:26.362370 Loading segment from ROM address 0x0000000040003a1c
5463 13:40:26.365835 Entry Point 0x0000000054601000
5464 13:40:26.365957 Loaded segments
5465 13:40:26.369054 NOTICE: MT8183 bl31_setup
5466 13:40:26.376438 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5467 13:40:26.379370 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5468 13:40:26.382348 INFO: [DEVAPC] dump DEVAPC registers:
5469 13:40:26.392413 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5470 13:40:26.399451 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5471 13:40:26.409336 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5472 13:40:26.415744 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5473 13:40:26.425739 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5474 13:40:26.432784 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5475 13:40:26.442400 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5476 13:40:26.449044 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5477 13:40:26.455709 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5478 13:40:26.465663 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5479 13:40:26.472337 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5480 13:40:26.482721 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5481 13:40:26.489195 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5482 13:40:26.495738 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5483 13:40:26.505902 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5484 13:40:26.512251 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5485 13:40:26.519169 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5486 13:40:26.525946 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5487 13:40:26.535258 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5488 13:40:26.542249 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5489 13:40:26.548956 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5490 13:40:26.555733 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5491 13:40:26.558864 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5492 13:40:26.562088 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5493 13:40:26.565376 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5494 13:40:26.568760 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5495 13:40:26.572108 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5496 13:40:26.578676 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5497 13:40:26.585140 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5498 13:40:26.585234 WARNING: region 0:
5499 13:40:26.588410 WARNING: apc:0x168, sa:0x0, ea:0xfff
5500 13:40:26.591566 WARNING: region 1:
5501 13:40:26.595239 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5502 13:40:26.595330 WARNING: region 2:
5503 13:40:26.598248 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5504 13:40:26.601644 WARNING: region 3:
5505 13:40:26.605250 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5506 13:40:26.608294 WARNING: region 4:
5507 13:40:26.611595 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5508 13:40:26.611715 WARNING: region 5:
5509 13:40:26.615159 WARNING: apc:0x0, sa:0x0, ea:0x0
5510 13:40:26.618719 WARNING: region 6:
5511 13:40:26.621785 WARNING: apc:0x0, sa:0x0, ea:0x0
5512 13:40:26.621910 WARNING: region 7:
5513 13:40:26.625428 WARNING: apc:0x0, sa:0x0, ea:0x0
5514 13:40:26.631924 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5515 13:40:26.634907 INFO: SPM: enable SPMC mode
5516 13:40:26.638599 NOTICE: spm_boot_init() start
5517 13:40:26.641843 NOTICE: spm_boot_init() end
5518 13:40:26.645168 INFO: BL31: Initializing runtime services
5519 13:40:26.651368 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5520 13:40:26.654898 INFO: BL31: Preparing for EL3 exit to normal world
5521 13:40:26.657862 INFO: Entry point address = 0x80000000
5522 13:40:26.661184 INFO: SPSR = 0x8
5523 13:40:26.682784
5524 13:40:26.682887
5525 13:40:26.682962
5526 13:40:26.683447 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5527 13:40:26.683567 start: 2.2.4 bootloader-commands (timeout 00:04:38) [common]
5528 13:40:26.683659 Setting prompt string to ['jacuzzi:']
5529 13:40:26.683752 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:38)
5530 13:40:26.686041 Starting depthcharge on Juniper...
5531 13:40:26.686126
5532 13:40:26.689275 vboot_handoff: creating legacy vboot_handoff structure
5533 13:40:26.689359
5534 13:40:26.692636 ec_init(0): CrosEC protocol v3 supported (544, 544)
5535 13:40:26.692721
5536 13:40:26.695990 Wipe memory regions:
5537 13:40:26.696075
5538 13:40:26.699206 [0x00000040000000, 0x00000054600000)
5539 13:40:26.741902
5540 13:40:26.742047 [0x00000054660000, 0x00000080000000)
5541 13:40:26.833649
5542 13:40:26.833829 [0x000000811994a0, 0x000000ffeda000)
5543 13:40:27.093471
5544 13:40:27.093614 [0x00000100000000, 0x00000140000000)
5545 13:40:27.226516
5546 13:40:27.229738 Initializing XHCI USB controller at 0x11200000.
5547 13:40:27.252833
5548 13:40:27.255893 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5549 13:40:27.255991
5550 13:40:27.256068
5551 13:40:27.256364 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5553 13:40:27.356694 jacuzzi: tftpboot 192.168.201.1 14063110/tftp-deploy-d74aqu_f/kernel/image.itb 14063110/tftp-deploy-d74aqu_f/kernel/cmdline
5554 13:40:27.356861 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5555 13:40:27.356957 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:37)
5556 13:40:27.360979 tftpboot 192.168.201.1 14063110/tftp-deploy-d74aqu_f/kernel/image.itp-deploy-d74aqu_f/kernel/cmdline
5557 13:40:27.361074
5558 13:40:27.361151 Waiting for link
5559 13:40:27.766898
5560 13:40:27.767078 R8152: Initializing
5561 13:40:27.767189
5562 13:40:27.769861 Version 9 (ocp_data = 6010)
5563 13:40:27.769987
5564 13:40:27.773306 R8152: Done initializing
5565 13:40:27.773432
5566 13:40:27.773534 Adding net device
5567 13:40:28.158707
5568 13:40:28.158855 done.
5569 13:40:28.158931
5570 13:40:28.159000 MAC: 00:e0:4c:68:0b:b9
5571 13:40:28.159069
5572 13:40:28.162262 Sending DHCP discover... done.
5573 13:40:28.162365
5574 13:40:28.165382 Waiting for reply... done.
5575 13:40:28.165472
5576 13:40:28.168602 Sending DHCP request... done.
5577 13:40:28.168693
5578 13:40:28.168763 Waiting for reply... done.
5579 13:40:28.168829
5580 13:40:28.171875 My ip is 192.168.201.13
5581 13:40:28.171961
5582 13:40:28.175013 The DHCP server ip is 192.168.201.1
5583 13:40:28.175101
5584 13:40:28.178577 TFTP server IP predefined by user: 192.168.201.1
5585 13:40:28.178658
5586 13:40:28.185202 Bootfile predefined by user: 14063110/tftp-deploy-d74aqu_f/kernel/image.itb
5587 13:40:28.185292
5588 13:40:28.188340 Sending tftp read request... done.
5589 13:40:28.188431
5590 13:40:28.191353 Waiting for the transfer...
5591 13:40:28.191456
5592 13:40:28.438561 00000000 ################################################################
5593 13:40:28.438746
5594 13:40:28.675796 00080000 ################################################################
5595 13:40:28.675944
5596 13:40:28.919970 00100000 ################################################################
5597 13:40:28.920112
5598 13:40:29.188435 00180000 ################################################################
5599 13:40:29.188577
5600 13:40:29.443681 00200000 ################################################################
5601 13:40:29.443827
5602 13:40:29.693580 00280000 ################################################################
5603 13:40:29.693778
5604 13:40:29.942317 00300000 ################################################################
5605 13:40:29.942464
5606 13:40:30.188555 00380000 ################################################################
5607 13:40:30.188696
5608 13:40:30.438725 00400000 ################################################################
5609 13:40:30.438869
5610 13:40:30.694374 00480000 ################################################################
5611 13:40:30.694514
5612 13:40:30.955603 00500000 ################################################################
5613 13:40:30.955751
5614 13:40:31.211588 00580000 ################################################################
5615 13:40:31.211741
5616 13:40:31.469872 00600000 ################################################################
5617 13:40:31.470050
5618 13:40:31.720439 00680000 ################################################################
5619 13:40:31.720587
5620 13:40:31.967157 00700000 ################################################################
5621 13:40:31.967342
5622 13:40:32.225609 00780000 ################################################################
5623 13:40:32.225750
5624 13:40:32.473239 00800000 ################################################################
5625 13:40:32.473380
5626 13:40:32.749191 00880000 ################################################################
5627 13:40:32.749369
5628 13:40:33.012984 00900000 ################################################################
5629 13:40:33.013122
5630 13:40:33.276427 00980000 ################################################################
5631 13:40:33.276606
5632 13:40:33.558698 00a00000 ################################################################
5633 13:40:33.558866
5634 13:40:33.847946 00a80000 ################################################################
5635 13:40:33.848115
5636 13:40:34.131881 00b00000 ################################################################
5637 13:40:34.132055
5638 13:40:34.396428 00b80000 ################################################################
5639 13:40:34.396605
5640 13:40:34.660985 00c00000 ################################################################
5641 13:40:34.661129
5642 13:40:34.932187 00c80000 ################################################################
5643 13:40:34.932324
5644 13:40:35.194537 00d00000 ################################################################
5645 13:40:35.194687
5646 13:40:35.458687 00d80000 ################################################################
5647 13:40:35.458860
5648 13:40:35.733646 00e00000 ################################################################
5649 13:40:35.733828
5650 13:40:36.004858 00e80000 ################################################################
5651 13:40:36.005000
5652 13:40:36.276719 00f00000 ################################################################
5653 13:40:36.276871
5654 13:40:36.571143 00f80000 ################################################################
5655 13:40:36.571324
5656 13:40:36.885178 01000000 ################################################################
5657 13:40:36.885343
5658 13:40:37.209566 01080000 ################################################################
5659 13:40:37.209743
5660 13:40:37.539430 01100000 ################################################################
5661 13:40:37.539577
5662 13:40:37.855491 01180000 ################################################################
5663 13:40:37.855636
5664 13:40:38.123397 01200000 ################################################################
5665 13:40:38.123549
5666 13:40:38.399143 01280000 ################################################################
5667 13:40:38.399319
5668 13:40:38.681006 01300000 ################################################################
5669 13:40:38.681158
5670 13:40:38.980260 01380000 ################################################################
5671 13:40:38.980403
5672 13:40:39.317827 01400000 ################################################################
5673 13:40:39.317969
5674 13:40:39.656744 01480000 ################################################################
5675 13:40:39.656919
5676 13:40:39.997861 01500000 ################################################################
5677 13:40:39.998040
5678 13:40:40.320451 01580000 ################################################################
5679 13:40:40.320625
5680 13:40:40.618928 01600000 ################################################################
5681 13:40:40.619100
5682 13:40:40.903308 01680000 ################################################################
5683 13:40:40.903488
5684 13:40:41.185302 01700000 ################################################################
5685 13:40:41.185450
5686 13:40:41.459601 01780000 ################################################################
5687 13:40:41.459777
5688 13:40:41.726552 01800000 ################################################################
5689 13:40:41.726726
5690 13:40:42.004408 01880000 ################################################################
5691 13:40:42.004581
5692 13:40:42.285278 01900000 ################################################################
5693 13:40:42.285454
5694 13:40:42.568505 01980000 ################################################################
5695 13:40:42.568650
5696 13:40:42.840692 01a00000 ################################################################
5697 13:40:42.840842
5698 13:40:43.121299 01a80000 ################################################################
5699 13:40:43.121493
5700 13:40:43.390210 01b00000 ################################################################
5701 13:40:43.390387
5702 13:40:43.659975 01b80000 ################################################################
5703 13:40:43.660115
5704 13:40:43.927644 01c00000 ################################################################
5705 13:40:43.927782
5706 13:40:44.192474 01c80000 ################################################################
5707 13:40:44.192622
5708 13:40:44.461536 01d00000 ################################################################
5709 13:40:44.461681
5710 13:40:44.734950 01d80000 ################################################################
5711 13:40:44.735124
5712 13:40:44.997828 01e00000 ################################################################
5713 13:40:44.997992
5714 13:40:45.267770 01e80000 ################################################################
5715 13:40:45.267964
5716 13:40:45.539864 01f00000 ################################################################
5717 13:40:45.540016
5718 13:40:45.815574 01f80000 ################################################################
5719 13:40:45.815768
5720 13:40:46.084178 02000000 ################################################################
5721 13:40:46.084319
5722 13:40:46.295044 02080000 ################################################## done.
5723 13:40:46.295237
5724 13:40:46.298877 The bootfile was 34482598 bytes long.
5725 13:40:46.298967
5726 13:40:46.301798 Sending tftp read request... done.
5727 13:40:46.301924
5728 13:40:46.305464 Waiting for the transfer...
5729 13:40:46.305586
5730 13:40:46.305687 00000000 # done.
5731 13:40:46.305787
5732 13:40:46.314843 Command line loaded dynamically from TFTP file: 14063110/tftp-deploy-d74aqu_f/kernel/cmdline
5733 13:40:46.314980
5734 13:40:46.331585 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5735 13:40:46.331743
5736 13:40:46.331851 Loading FIT.
5737 13:40:46.331956
5738 13:40:46.334818 Image ramdisk-1 has 21361549 bytes.
5739 13:40:46.334905
5740 13:40:46.338125 Image fdt-1 has 57695 bytes.
5741 13:40:46.338215
5742 13:40:46.341391 Image kernel-1 has 13061303 bytes.
5743 13:40:46.341479
5744 13:40:46.351211 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5745 13:40:46.351305
5746 13:40:46.361472 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5747 13:40:46.361608
5748 13:40:46.367518 Choosing best match conf-1 for compat google,juniper-sku16.
5749 13:40:46.371138
5750 13:40:46.376298 Connected to device vid:did:rid of 1ae0:0028:00
5751 13:40:46.384305
5752 13:40:46.387521 tpm_get_response: command 0x17b, return code 0x0
5753 13:40:46.387622
5754 13:40:46.390592 tpm_cleanup: add release locality here.
5755 13:40:46.390680
5756 13:40:46.393887 Shutting down all USB controllers.
5757 13:40:46.393976
5758 13:40:46.397699 Removing current net device
5759 13:40:46.397787
5760 13:40:46.400923 Exiting depthcharge with code 4 at timestamp: 37019010
5761 13:40:46.401005
5762 13:40:46.404247 LZMA decompressing kernel-1 to 0x80193568
5763 13:40:46.404329
5764 13:40:46.407269 LZMA decompressing kernel-1 to 0x40000000
5765 13:40:48.267897
5766 13:40:48.268041 jumping to kernel
5767 13:40:48.268777 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
5768 13:40:48.268899 start: 2.2.5 auto-login-action (timeout 00:04:17) [common]
5769 13:40:48.268987 Setting prompt string to ['Linux version [0-9]']
5770 13:40:48.269071 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5771 13:40:48.269150 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5772 13:40:48.342691
5773 13:40:48.346211 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5774 13:40:48.349506 start: 2.2.5.1 login-action (timeout 00:04:16) [common]
5775 13:40:48.349619 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5776 13:40:48.349700 Setting prompt string to []
5777 13:40:48.349783 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5778 13:40:48.349863 Using line separator: #'\n'#
5779 13:40:48.349928 No login prompt set.
5780 13:40:48.349994 Parsing kernel messages
5781 13:40:48.350079 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5782 13:40:48.350266 [login-action] Waiting for messages, (timeout 00:04:16)
5783 13:40:48.350367 Waiting using forced prompt support (timeout 00:02:08)
5784 13:40:48.369065 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
5785 13:40:48.372698 [ 0.000000] random: crng init done
5786 13:40:48.378974 [ 0.000000] Machine model: Google juniper sku16 board
5787 13:40:48.382609 [ 0.000000] efi: UEFI not found.
5788 13:40:48.389497 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5789 13:40:48.395913 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5790 13:40:48.405810 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5791 13:40:48.408956 [ 0.000000] printk: bootconsole [mtk8250] enabled
5792 13:40:48.417417 [ 0.000000] NUMA: No NUMA configuration found
5793 13:40:48.424200 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5794 13:40:48.430685 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5795 13:40:48.430787 [ 0.000000] Zone ranges:
5796 13:40:48.437895 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5797 13:40:48.441043 [ 0.000000] DMA32 empty
5798 13:40:48.447465 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5799 13:40:48.451212 [ 0.000000] Movable zone start for each node
5800 13:40:48.454246 [ 0.000000] Early memory node ranges
5801 13:40:48.461053 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5802 13:40:48.467529 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5803 13:40:48.473917 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5804 13:40:48.480795 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5805 13:40:48.487362 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5806 13:40:48.494192 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5807 13:40:48.510236 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5808 13:40:48.516648 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5809 13:40:48.523524 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5810 13:40:48.526686 [ 0.000000] psci: probing for conduit method from DT.
5811 13:40:48.533273 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5812 13:40:48.536559 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5813 13:40:48.543074 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5814 13:40:48.546439 [ 0.000000] psci: SMC Calling Convention v1.1
5815 13:40:48.552931 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5816 13:40:48.556571 [ 0.000000] Detected VIPT I-cache on CPU0
5817 13:40:48.563050 [ 0.000000] CPU features: detected: GIC system register CPU interface
5818 13:40:48.569557 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5819 13:40:48.576417 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5820 13:40:48.583033 [ 0.000000] CPU features: detected: ARM erratum 845719
5821 13:40:48.586147 [ 0.000000] alternatives: applying boot alternatives
5822 13:40:48.589331 [ 0.000000] Fallback order for Node 0: 0
5823 13:40:48.596534 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5824 13:40:48.599612 [ 0.000000] Policy zone: Normal
5825 13:40:48.619748 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5826 13:40:48.632965 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5827 13:40:48.639610 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5828 13:40:48.649317 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5829 13:40:48.656403 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5830 13:40:48.659111 <6>[ 0.000000] software IO TLB: area num 8.
5831 13:40:48.684801 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5832 13:40:48.742553 <6>[ 0.000000] Memory: 3894344K/4191232K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 264120K reserved, 32768K cma-reserved)
5833 13:40:48.749349 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5834 13:40:48.755657 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5835 13:40:48.758990 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5836 13:40:48.766145 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5837 13:40:48.772449 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5838 13:40:48.775570 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5839 13:40:48.785748 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5840 13:40:48.792535 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5841 13:40:48.795743 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5842 13:40:48.807815 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5843 13:40:48.814381 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5844 13:40:48.817604 <6>[ 0.000000] GICv3: 640 SPIs implemented
5845 13:40:48.820846 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5846 13:40:48.827807 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5847 13:40:48.831320 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5848 13:40:48.837505 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5849 13:40:48.850731 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5850 13:40:48.861000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5851 13:40:48.867730 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5852 13:40:48.879521 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5853 13:40:48.892928 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5854 13:40:48.899280 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5855 13:40:48.906358 <6>[ 0.009478] Console: colour dummy device 80x25
5856 13:40:48.909588 <6>[ 0.014514] printk: console [tty1] enabled
5857 13:40:48.919471 <6>[ 0.018900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5858 13:40:48.926451 <6>[ 0.029363] pid_max: default: 32768 minimum: 301
5859 13:40:48.929700 <6>[ 0.034245] LSM: Security Framework initializing
5860 13:40:48.939692 <6>[ 0.039160] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5861 13:40:48.946271 <6>[ 0.046783] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5862 13:40:48.952675 <4>[ 0.055659] cacheinfo: Unable to detect cache hierarchy for CPU 0
5863 13:40:48.962978 <6>[ 0.062291] cblist_init_generic: Setting adjustable number of callback queues.
5864 13:40:48.969444 <6>[ 0.069737] cblist_init_generic: Setting shift to 3 and lim to 1.
5865 13:40:48.976304 <6>[ 0.076090] cblist_init_generic: Setting adjustable number of callback queues.
5866 13:40:48.982926 <6>[ 0.083534] cblist_init_generic: Setting shift to 3 and lim to 1.
5867 13:40:48.986322 <6>[ 0.089934] rcu: Hierarchical SRCU implementation.
5868 13:40:48.993092 <6>[ 0.094959] rcu: Max phase no-delay instances is 1000.
5869 13:40:48.999470 <6>[ 0.102895] EFI services will not be available.
5870 13:40:49.002845 <6>[ 0.107845] smp: Bringing up secondary CPUs ...
5871 13:40:49.013717 <6>[ 0.113100] Detected VIPT I-cache on CPU1
5872 13:40:49.020073 <4>[ 0.113145] cacheinfo: Unable to detect cache hierarchy for CPU 1
5873 13:40:49.026535 <6>[ 0.113154] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5874 13:40:49.033650 <6>[ 0.113187] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5875 13:40:49.037108 <6>[ 0.113671] Detected VIPT I-cache on CPU2
5876 13:40:49.043599 <4>[ 0.113703] cacheinfo: Unable to detect cache hierarchy for CPU 2
5877 13:40:49.049841 <6>[ 0.113709] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5878 13:40:49.056452 <6>[ 0.113721] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5879 13:40:49.059774 <6>[ 0.114165] Detected VIPT I-cache on CPU3
5880 13:40:49.066759 <4>[ 0.114195] cacheinfo: Unable to detect cache hierarchy for CPU 3
5881 13:40:49.076377 <6>[ 0.114200] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5882 13:40:49.083375 <6>[ 0.114211] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5883 13:40:49.086559 <6>[ 0.114786] CPU features: detected: Spectre-v2
5884 13:40:49.089870 <6>[ 0.114796] CPU features: detected: Spectre-BHB
5885 13:40:49.096193 <6>[ 0.114800] CPU features: detected: ARM erratum 858921
5886 13:40:49.099380 <6>[ 0.114805] Detected VIPT I-cache on CPU4
5887 13:40:49.106365 <4>[ 0.114854] cacheinfo: Unable to detect cache hierarchy for CPU 4
5888 13:40:49.112953 <6>[ 0.114861] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5889 13:40:49.119481 <6>[ 0.114869] arch_timer: Enabling local workaround for ARM erratum 858921
5890 13:40:49.126372 <6>[ 0.114880] arch_timer: CPU4: Trapping CNTVCT access
5891 13:40:49.132880 <6>[ 0.114888] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5892 13:40:49.136112 <6>[ 0.115373] Detected VIPT I-cache on CPU5
5893 13:40:49.142652 <4>[ 0.115413] cacheinfo: Unable to detect cache hierarchy for CPU 5
5894 13:40:49.149787 <6>[ 0.115419] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5895 13:40:49.155976 <6>[ 0.115425] arch_timer: Enabling local workaround for ARM erratum 858921
5896 13:40:49.162522 <6>[ 0.115432] arch_timer: CPU5: Trapping CNTVCT access
5897 13:40:49.169609 <6>[ 0.115437] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5898 13:40:49.172475 <6>[ 0.115972] Detected VIPT I-cache on CPU6
5899 13:40:49.179363 <4>[ 0.116018] cacheinfo: Unable to detect cache hierarchy for CPU 6
5900 13:40:49.186207 <6>[ 0.116024] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5901 13:40:49.195952 <6>[ 0.116031] arch_timer: Enabling local workaround for ARM erratum 858921
5902 13:40:49.199205 <6>[ 0.116037] arch_timer: CPU6: Trapping CNTVCT access
5903 13:40:49.205676 <6>[ 0.116042] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5904 13:40:49.208874 <6>[ 0.116573] Detected VIPT I-cache on CPU7
5905 13:40:49.215732 <4>[ 0.116618] cacheinfo: Unable to detect cache hierarchy for CPU 7
5906 13:40:49.222646 <6>[ 0.116623] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5907 13:40:49.232711 <6>[ 0.116630] arch_timer: Enabling local workaround for ARM erratum 858921
5908 13:40:49.235853 <6>[ 0.116637] arch_timer: CPU7: Trapping CNTVCT access
5909 13:40:49.242782 <6>[ 0.116643] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5910 13:40:49.246030 <6>[ 0.116690] smp: Brought up 1 node, 8 CPUs
5911 13:40:49.252422 <6>[ 0.355561] SMP: Total of 8 processors activated.
5912 13:40:49.258807 <6>[ 0.360497] CPU features: detected: 32-bit EL0 Support
5913 13:40:49.262045 <6>[ 0.365868] CPU features: detected: 32-bit EL1 Support
5914 13:40:49.269406 <6>[ 0.371234] CPU features: detected: CRC32 instructions
5915 13:40:49.272431 <6>[ 0.376661] CPU: All CPU(s) started at EL2
5916 13:40:49.279035 <6>[ 0.380999] alternatives: applying system-wide alternatives
5917 13:40:49.285769 <6>[ 0.389187] devtmpfs: initialized
5918 13:40:49.298687 <6>[ 0.398118] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5919 13:40:49.308467 <6>[ 0.408067] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5920 13:40:49.311584 <6>[ 0.415789] pinctrl core: initialized pinctrl subsystem
5921 13:40:49.319505 <6>[ 0.422893] DMI not present or invalid.
5922 13:40:49.326327 <6>[ 0.427263] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5923 13:40:49.332889 <6>[ 0.434158] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5924 13:40:49.342904 <6>[ 0.441686] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5925 13:40:49.349378 <6>[ 0.449938] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5926 13:40:49.356457 <6>[ 0.458113] audit: initializing netlink subsys (disabled)
5927 13:40:49.362846 <5>[ 0.463816] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5928 13:40:49.369444 <6>[ 0.464786] thermal_sys: Registered thermal governor 'step_wise'
5929 13:40:49.375926 <6>[ 0.471783] thermal_sys: Registered thermal governor 'power_allocator'
5930 13:40:49.379132 <6>[ 0.478080] cpuidle: using governor menu
5931 13:40:49.386131 <6>[ 0.489044] NET: Registered PF_QIPCRTR protocol family
5932 13:40:49.392837 <6>[ 0.494529] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5933 13:40:49.399176 <6>[ 0.501624] ASID allocator initialised with 32768 entries
5934 13:40:49.406044 <6>[ 0.508402] Serial: AMBA PL011 UART driver
5935 13:40:49.415283 <4>[ 0.518810] Trying to register duplicate clock ID: 113
5936 13:40:49.475925 <6>[ 0.575619] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5937 13:40:49.490367 <6>[ 0.589973] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5938 13:40:49.493608 <6>[ 0.599713] KASLR enabled
5939 13:40:49.507611 <6>[ 0.607720] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5940 13:40:49.514282 <6>[ 0.614721] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5941 13:40:49.520821 <6>[ 0.621197] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5942 13:40:49.527647 <6>[ 0.628188] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5943 13:40:49.534099 <6>[ 0.634662] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5944 13:40:49.540789 <6>[ 0.641651] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5945 13:40:49.547925 <6>[ 0.648125] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5946 13:40:49.554411 <6>[ 0.655114] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5947 13:40:49.557925 <6>[ 0.662676] ACPI: Interpreter disabled.
5948 13:40:49.567633 <6>[ 0.670660] iommu: Default domain type: Translated
5949 13:40:49.574170 <6>[ 0.675766] iommu: DMA domain TLB invalidation policy: strict mode
5950 13:40:49.577217 <5>[ 0.682396] SCSI subsystem initialized
5951 13:40:49.584331 <6>[ 0.686813] usbcore: registered new interface driver usbfs
5952 13:40:49.590888 <6>[ 0.692540] usbcore: registered new interface driver hub
5953 13:40:49.594161 <6>[ 0.698082] usbcore: registered new device driver usb
5954 13:40:49.601377 <6>[ 0.704384] pps_core: LinuxPPS API ver. 1 registered
5955 13:40:49.611411 <6>[ 0.709568] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5956 13:40:49.614592 <6>[ 0.718893] PTP clock support registered
5957 13:40:49.617952 <6>[ 0.723144] EDAC MC: Ver: 3.0.0
5958 13:40:49.625663 <6>[ 0.728806] FPGA manager framework
5959 13:40:49.632088 <6>[ 0.732494] Advanced Linux Sound Architecture Driver Initialized.
5960 13:40:49.635477 <6>[ 0.739239] vgaarb: loaded
5961 13:40:49.638617 <6>[ 0.742358] clocksource: Switched to clocksource arch_sys_counter
5962 13:40:49.645757 <5>[ 0.748787] VFS: Disk quotas dquot_6.6.0
5963 13:40:49.652581 <6>[ 0.752961] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5964 13:40:49.655981 <6>[ 0.760136] pnp: PnP ACPI: disabled
5965 13:40:49.663662 <6>[ 0.767004] NET: Registered PF_INET protocol family
5966 13:40:49.670873 <6>[ 0.772237] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5967 13:40:49.682365 <6>[ 0.782126] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5968 13:40:49.692165 <6>[ 0.790881] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5969 13:40:49.698670 <6>[ 0.798831] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5970 13:40:49.705256 <6>[ 0.807063] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5971 13:40:49.715475 <6>[ 0.815156] TCP: Hash tables configured (established 32768 bind 32768)
5972 13:40:49.722003 <6>[ 0.821985] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5973 13:40:49.728397 <6>[ 0.828957] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5974 13:40:49.734970 <6>[ 0.836439] NET: Registered PF_UNIX/PF_LOCAL protocol family
5975 13:40:49.741727 <6>[ 0.842530] RPC: Registered named UNIX socket transport module.
5976 13:40:49.745096 <6>[ 0.848675] RPC: Registered udp transport module.
5977 13:40:49.751532 <6>[ 0.853599] RPC: Registered tcp transport module.
5978 13:40:49.758789 <6>[ 0.858522] RPC: Registered tcp NFSv4.1 backchannel transport module.
5979 13:40:49.761997 <6>[ 0.865173] PCI: CLS 0 bytes, default 64
5980 13:40:49.765226 <6>[ 0.869459] Unpacking initramfs...
5981 13:40:49.779026 <6>[ 0.878970] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5982 13:40:49.789405 <6>[ 0.887611] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5983 13:40:49.792453 <6>[ 0.896455] kvm [1]: IPA Size Limit: 40 bits
5984 13:40:49.799719 <6>[ 0.902771] kvm [1]: vgic-v2@c420000
5985 13:40:49.802927 <6>[ 0.906586] kvm [1]: GIC system register CPU interface enabled
5986 13:40:49.809393 <6>[ 0.912764] kvm [1]: vgic interrupt IRQ18
5987 13:40:49.812755 <6>[ 0.917130] kvm [1]: Hyp mode initialized successfully
5988 13:40:49.820131 <5>[ 0.923383] Initialise system trusted keyrings
5989 13:40:49.826604 <6>[ 0.928220] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5990 13:40:49.834850 <6>[ 0.938190] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5991 13:40:49.841832 <5>[ 0.944627] NFS: Registering the id_resolver key type
5992 13:40:49.845367 <5>[ 0.949933] Key type id_resolver registered
5993 13:40:49.851922 <5>[ 0.954345] Key type id_legacy registered
5994 13:40:49.858480 <6>[ 0.958660] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5995 13:40:49.865183 <6>[ 0.965581] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5996 13:40:49.871755 <6>[ 0.973335] 9p: Installing v9fs 9p2000 file system support
5997 13:40:49.899044 <5>[ 1.002422] Key type asymmetric registered
5998 13:40:49.902905 <5>[ 1.006767] Asymmetric key parser 'x509' registered
5999 13:40:49.912629 <6>[ 1.011927] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6000 13:40:49.915825 <6>[ 1.019541] io scheduler mq-deadline registered
6001 13:40:49.919088 <6>[ 1.024298] io scheduler kyber registered
6002 13:40:49.942073 <6>[ 1.045082] EINJ: ACPI disabled.
6003 13:40:49.948532 <4>[ 1.048842] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6004 13:40:49.986455 <6>[ 1.089580] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6005 13:40:49.994547 <6>[ 1.098068] printk: console [ttyS0] disabled
6006 13:40:50.022918 <6>[ 1.122723] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6007 13:40:50.029399 <6>[ 1.132197] printk: console [ttyS0] enabled
6008 13:40:50.032592 <6>[ 1.132197] printk: console [ttyS0] enabled
6009 13:40:50.039558 <6>[ 1.141116] printk: bootconsole [mtk8250] disabled
6010 13:40:50.042543 <6>[ 1.141116] printk: bootconsole [mtk8250] disabled
6011 13:40:50.052919 <3>[ 1.151652] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6012 13:40:50.059362 <3>[ 1.160036] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6013 13:40:50.088804 <6>[ 1.188449] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6014 13:40:50.095375 <6>[ 1.198105] serial serial0: tty port ttyS1 registered
6015 13:40:50.102051 <6>[ 1.204653] SuperH (H)SCI(F) driver initialized
6016 13:40:50.104950 <6>[ 1.210125] msm_serial: driver initialized
6017 13:40:50.120564 <6>[ 1.220449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6018 13:40:50.130352 <6>[ 1.229050] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6019 13:40:50.137290 <6>[ 1.237625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6020 13:40:50.146840 <6>[ 1.246193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6021 13:40:50.154018 <6>[ 1.254843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6022 13:40:50.163949 <6>[ 1.263498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6023 13:40:50.174178 <6>[ 1.272237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6024 13:40:50.180702 <6>[ 1.280975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6025 13:40:50.190451 <6>[ 1.289536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6026 13:40:50.200235 <6>[ 1.298337] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6027 13:40:50.207870 <4>[ 1.310749] cacheinfo: Unable to detect cache hierarchy for CPU 0
6028 13:40:50.216653 <6>[ 1.320127] loop: module loaded
6029 13:40:50.229061 <6>[ 1.332064] vsim1: Bringing 1800000uV into 2700000-2700000uV
6030 13:40:50.246640 <6>[ 1.349986] megasas: 07.719.03.00-rc1
6031 13:40:50.255527 <6>[ 1.358776] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6032 13:40:50.262883 <6>[ 1.365770] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6033 13:40:50.279737 <6>[ 1.382606] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6034 13:40:50.336382 <6>[ 1.432858] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6035 13:40:50.464045 <6>[ 1.567452] Freeing initrd memory: 20856K
6036 13:40:50.483946 <4>[ 1.583304] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6037 13:40:50.490302 <4>[ 1.592532] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.91-cip21 #1
6038 13:40:50.496811 <4>[ 1.599230] Hardware name: Google juniper sku16 board (DT)
6039 13:40:50.500063 <4>[ 1.604969] Call trace:
6040 13:40:50.503348 <4>[ 1.607669] dump_backtrace.part.0+0xe0/0xf0
6041 13:40:50.506564 <4>[ 1.612206] show_stack+0x18/0x30
6042 13:40:50.510257 <4>[ 1.615778] dump_stack_lvl+0x68/0x84
6043 13:40:50.516853 <4>[ 1.619698] dump_stack+0x18/0x34
6044 13:40:50.519897 <4>[ 1.623268] sysfs_warn_dup+0x64/0x80
6045 13:40:50.523691 <4>[ 1.627190] sysfs_do_create_link_sd+0xf0/0x100
6046 13:40:50.527025 <4>[ 1.631977] sysfs_create_link+0x20/0x40
6047 13:40:50.533380 <4>[ 1.636157] bus_add_device+0x68/0x10c
6048 13:40:50.536535 <4>[ 1.640163] device_add+0x340/0x7ac
6049 13:40:50.540084 <4>[ 1.643906] of_device_add+0x44/0x60
6050 13:40:50.546512 <4>[ 1.647740] of_platform_device_create_pdata+0x90/0x120
6051 13:40:50.549838 <4>[ 1.653221] of_platform_bus_create+0x170/0x370
6052 13:40:50.553777 <4>[ 1.658007] of_platform_populate+0x50/0xfc
6053 13:40:50.560063 <4>[ 1.662446] parse_mtd_partitions+0x1dc/0x510
6054 13:40:50.563356 <4>[ 1.667059] mtd_device_parse_register+0xf8/0x2e0
6055 13:40:50.566781 <4>[ 1.672017] spi_nor_probe+0x21c/0x2f0
6056 13:40:50.570232 <4>[ 1.676022] spi_mem_probe+0x6c/0xb0
6057 13:40:50.576744 <4>[ 1.679855] spi_probe+0x84/0xe4
6058 13:40:50.580399 <4>[ 1.683337] really_probe+0xbc/0x2e0
6059 13:40:50.583343 <4>[ 1.687167] __driver_probe_device+0x78/0x11c
6060 13:40:50.586908 <4>[ 1.691778] driver_probe_device+0xd8/0x160
6061 13:40:50.593206 <4>[ 1.696216] __device_attach_driver+0xb8/0x134
6062 13:40:50.596885 <4>[ 1.700914] bus_for_each_drv+0x78/0xd0
6063 13:40:50.600153 <4>[ 1.705004] __device_attach+0xa8/0x1c0
6064 13:40:50.606663 <4>[ 1.709094] device_initial_probe+0x14/0x20
6065 13:40:50.609917 <4>[ 1.713532] bus_probe_device+0x9c/0xa4
6066 13:40:50.613041 <4>[ 1.717622] device_add+0x3ac/0x7ac
6067 13:40:50.616915 <4>[ 1.721364] __spi_add_device+0x78/0x120
6068 13:40:50.620125 <4>[ 1.725542] spi_add_device+0x40/0x7c
6069 13:40:50.626340 <4>[ 1.729459] spi_register_controller+0x610/0xad0
6070 13:40:50.630090 <4>[ 1.734331] devm_spi_register_controller+0x4c/0xa4
6071 13:40:50.636631 <4>[ 1.739464] mtk_spi_probe+0x3f8/0x650
6072 13:40:50.639843 <4>[ 1.743468] platform_probe+0x68/0xe0
6073 13:40:50.643082 <4>[ 1.747386] really_probe+0xbc/0x2e0
6074 13:40:50.646844 <4>[ 1.751216] __driver_probe_device+0x78/0x11c
6075 13:40:50.653745 <4>[ 1.755827] driver_probe_device+0xd8/0x160
6076 13:40:50.656968 <4>[ 1.760264] __driver_attach+0x94/0x19c
6077 13:40:50.660233 <4>[ 1.764355] bus_for_each_dev+0x70/0xd0
6078 13:40:50.663680 <4>[ 1.768444] driver_attach+0x24/0x30
6079 13:40:50.666846 <4>[ 1.772274] bus_add_driver+0x154/0x20c
6080 13:40:50.673313 <4>[ 1.776364] driver_register+0x78/0x130
6081 13:40:50.677103 <4>[ 1.780454] __platform_driver_register+0x28/0x34
6082 13:40:50.680197 <4>[ 1.785414] mtk_spi_driver_init+0x1c/0x28
6083 13:40:50.687229 <4>[ 1.789768] do_one_initcall+0x50/0x1d0
6084 13:40:50.690205 <4>[ 1.793859] kernel_init_freeable+0x21c/0x288
6085 13:40:50.693596 <4>[ 1.798472] kernel_init+0x24/0x12c
6086 13:40:50.697090 <4>[ 1.802217] ret_from_fork+0x10/0x20
6087 13:40:50.708185 <6>[ 1.811084] tun: Universal TUN/TAP device driver, 1.6
6088 13:40:50.711740 <6>[ 1.817368] thunder_xcv, ver 1.0
6089 13:40:50.715171 <6>[ 1.820883] thunder_bgx, ver 1.0
6090 13:40:50.718266 <6>[ 1.824388] nicpf, ver 1.0
6091 13:40:50.729125 <6>[ 1.828753] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6092 13:40:50.732313 <6>[ 1.836238] hns3: Copyright (c) 2017 Huawei Corporation.
6093 13:40:50.735499 <6>[ 1.841835] hclge is initializing
6094 13:40:50.742561 <6>[ 1.845423] e1000: Intel(R) PRO/1000 Network Driver
6095 13:40:50.748858 <6>[ 1.850559] e1000: Copyright (c) 1999-2006 Intel Corporation.
6096 13:40:50.752215 <6>[ 1.856581] e1000e: Intel(R) PRO/1000 Network Driver
6097 13:40:50.759119 <6>[ 1.861802] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6098 13:40:50.765801 <6>[ 1.867998] igb: Intel(R) Gigabit Ethernet Network Driver
6099 13:40:50.772490 <6>[ 1.873654] igb: Copyright (c) 2007-2014 Intel Corporation.
6100 13:40:50.778944 <6>[ 1.879497] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6101 13:40:50.785468 <6>[ 1.886021] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6102 13:40:50.789114 <6>[ 1.892572] sky2: driver version 1.30
6103 13:40:50.795365 <6>[ 1.897825] usbcore: registered new device driver r8152-cfgselector
6104 13:40:50.802106 <6>[ 1.904369] usbcore: registered new interface driver r8152
6105 13:40:50.808924 <6>[ 1.910200] VFIO - User Level meta-driver version: 0.3
6106 13:40:50.815620 <6>[ 1.917991] mtu3 11201000.usb: uwk - reg:0x420, version:101
6107 13:40:50.822051 <4>[ 1.923867] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6108 13:40:50.828752 <6>[ 1.931164] mtu3 11201000.usb: dr_mode: 1, drd: auto
6109 13:40:50.835702 <6>[ 1.936393] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6110 13:40:50.839061 <6>[ 1.942584] mtu3 11201000.usb: usb3-drd: 0
6111 13:40:50.845654 <6>[ 1.948139] mtu3 11201000.usb: xHCI platform device register success...
6112 13:40:50.857333 <4>[ 1.956797] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6113 13:40:50.860490 <6>[ 1.964733] xhci-mtk 11200000.usb: xHCI Host Controller
6114 13:40:50.870756 <6>[ 1.970238] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6115 13:40:50.877314 <6>[ 1.977966] xhci-mtk 11200000.usb: USB3 root hub has no ports
6116 13:40:50.884400 <6>[ 1.983974] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6117 13:40:50.890770 <6>[ 1.993394] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6118 13:40:50.897132 <6>[ 1.999460] xhci-mtk 11200000.usb: xHCI Host Controller
6119 13:40:50.904215 <6>[ 2.004947] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6120 13:40:50.910967 <6>[ 2.012605] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6121 13:40:50.913940 <6>[ 2.019420] hub 1-0:1.0: USB hub found
6122 13:40:50.920866 <6>[ 2.023449] hub 1-0:1.0: 1 port detected
6123 13:40:50.927703 <6>[ 2.028783] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6124 13:40:50.934417 <6>[ 2.037400] hub 2-0:1.0: USB hub found
6125 13:40:50.940854 <3>[ 2.041427] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6126 13:40:50.947938 <6>[ 2.049309] usbcore: registered new interface driver usb-storage
6127 13:40:50.954444 <6>[ 2.055917] usbcore: registered new device driver onboard-usb-hub
6128 13:40:50.970965 <4>[ 2.070474] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6129 13:40:50.979549 <6>[ 2.082797] mt6397-rtc mt6358-rtc: registered as rtc0
6130 13:40:50.990062 <6>[ 2.088275] mt6397-rtc mt6358-rtc: setting system clock to 2024-05-28T13:39:53 UTC (1716903593)
6131 13:40:50.993308 <6>[ 2.098165] i2c_dev: i2c /dev entries driver
6132 13:40:51.004709 <6>[ 2.104602] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6133 13:40:51.014950 <6>[ 2.112919] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6134 13:40:51.017968 <6>[ 2.121823] i2c 4-0058: Fixed dependency cycle(s) with /panel
6135 13:40:51.028300 <6>[ 2.127853] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6136 13:40:51.034765 <3>[ 2.135320] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6137 13:40:51.052471 <6>[ 2.152327] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6138 13:40:51.060412 <6>[ 2.163793] cpu cpu0: EM: created perf domain
6139 13:40:51.070418 <6>[ 2.169276] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6140 13:40:51.077494 <6>[ 2.180569] cpu cpu4: EM: created perf domain
6141 13:40:51.084396 <6>[ 2.187484] sdhci: Secure Digital Host Controller Interface driver
6142 13:40:51.091378 <6>[ 2.193940] sdhci: Copyright(c) Pierre Ossman
6143 13:40:51.098122 <6>[ 2.199338] Synopsys Designware Multimedia Card Interface Driver
6144 13:40:51.104299 <6>[ 2.199829] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6145 13:40:51.107511 <6>[ 2.206430] sdhci-pltfm: SDHCI platform and OF driver helper
6146 13:40:51.116967 <6>[ 2.220130] ledtrig-cpu: registered to indicate activity on CPUs
6147 13:40:51.124591 <6>[ 2.227910] usbcore: registered new interface driver usbhid
6148 13:40:51.127930 <6>[ 2.233760] usbhid: USB HID core driver
6149 13:40:51.138651 <6>[ 2.238048] spi_master spi2: will run message pump with realtime priority
6150 13:40:51.143099 <4>[ 2.238058] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6151 13:40:51.153073 <4>[ 2.252322] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6152 13:40:51.163174 <6>[ 2.258142] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6153 13:40:51.182569 <6>[ 2.275649] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6154 13:40:51.189275 <4>[ 2.287379] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6155 13:40:51.192384 <6>[ 2.290916] cros-ec-spi spi2.0: Chrome EC device registered
6156 13:40:51.205599 <4>[ 2.305631] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6157 13:40:51.217571 <4>[ 2.317034] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6158 13:40:51.224318 <4>[ 2.325974] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6159 13:40:51.230759 <6>[ 2.331259] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6160 13:40:51.237533 <6>[ 2.340174] mmc0: new HS400 MMC card at address 0001
6161 13:40:51.244435 <6>[ 2.346223] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6162 13:40:51.250661 <6>[ 2.346312] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6163 13:40:51.260402 <6>[ 2.363377] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6164 13:40:51.269892 <6>[ 2.372772] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6165 13:40:51.276327 <6>[ 2.379428] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6166 13:40:51.286385 <6>[ 2.380643] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6167 13:40:51.293161 <6>[ 2.393969] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6168 13:40:51.303303 <6>[ 2.397304] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6169 13:40:51.316930 <6>[ 2.404865] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6170 13:40:51.320153 <6>[ 2.413006] NET: Registered PF_PACKET protocol family
6171 13:40:51.329862 <6>[ 2.428881] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6172 13:40:51.336328 <6>[ 2.429232] 9pnet: Installing 9P2000 support
6173 13:40:51.339680 <5>[ 2.443613] Key type dns_resolver registered
6174 13:40:51.346178 <6>[ 2.448825] registered taskstats version 1
6175 13:40:51.353209 <6>[ 2.450476] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6176 13:40:51.356240 <5>[ 2.453195] Loading compiled-in X.509 certificates
6177 13:40:51.397641 <3>[ 2.497268] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6178 13:40:51.423390 <4>[ 2.523180] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6179 13:40:51.434015 <6>[ 2.533770] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6180 13:40:51.449167 <6>[ 2.545500] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6181 13:40:51.462340 <3>[ 2.556763] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6182 13:40:51.476452 <3>[ 2.572456] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6183 13:40:51.486333 <3>[ 2.585334] debugfs: File 'Playback' in directory 'dapm' already present!
6184 13:40:51.492710 <3>[ 2.592413] debugfs: File 'Capture' in directory 'dapm' already present!
6185 13:40:51.506338 <6>[ 2.602553] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input4
6186 13:40:51.516151 <6>[ 2.616155] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6187 13:40:51.526469 <6>[ 2.624785] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6188 13:40:51.532869 <6>[ 2.633336] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6189 13:40:51.543117 <6>[ 2.641872] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6190 13:40:51.549603 <6>[ 2.650411] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6191 13:40:51.559901 <6>[ 2.658942] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6192 13:40:51.569471 <6>[ 2.667534] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6193 13:40:51.573117 <6>[ 2.676612] hub 1-1:1.0: USB hub found
6194 13:40:51.576200 <6>[ 2.680946] hub 1-1:1.0: 3 ports detected
6195 13:40:51.583046 <6>[ 2.685298] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6196 13:40:51.592946 <6>[ 2.692911] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6197 13:40:51.599562 <6>[ 2.700385] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6198 13:40:51.606559 <6>[ 2.707837] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6199 13:40:51.613049 <6>[ 2.715324] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6200 13:40:51.620317 <6>[ 2.723669] panfrost 13040000.gpu: clock rate = 511999970
6201 13:40:51.630789 <6>[ 2.729370] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6202 13:40:51.640444 <6>[ 2.739640] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6203 13:40:51.646994 <6>[ 2.747660] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6204 13:40:51.660685 <6>[ 2.756092] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6205 13:40:51.666577 <6>[ 2.768169] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6206 13:40:51.679624 <6>[ 2.779284] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6207 13:40:51.689328 <6>[ 2.788184] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6208 13:40:51.699483 <6>[ 2.797329] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6209 13:40:51.706243 <6>[ 2.806457] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6210 13:40:51.715991 <6>[ 2.815584] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6211 13:40:51.726281 <6>[ 2.824883] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6212 13:40:51.735951 <6>[ 2.834182] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6213 13:40:51.745790 <6>[ 2.843653] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6214 13:40:51.755637 <6>[ 2.853127] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6215 13:40:51.762124 <6>[ 2.862251] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6216 13:40:51.836054 <6>[ 2.935477] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6217 13:40:51.845537 <6>[ 2.944337] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6218 13:40:51.857008 <6>[ 2.956451] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6219 13:40:51.894662 <6>[ 2.994381] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6220 13:40:52.536656 <6>[ 3.182590] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6221 13:40:52.546921 <4>[ 3.299547] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6222 13:40:52.553225 <4>[ 3.299566] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6223 13:40:52.560099 <6>[ 3.339699] r8152 1-1.2:1.0 eth0: v1.12.13
6224 13:40:52.566500 <6>[ 3.418386] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6225 13:40:52.573192 <6>[ 3.619972] Console: switching to colour frame buffer device 170x48
6226 13:40:52.583319 <6>[ 3.681847] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6227 13:40:52.600129 <6>[ 3.699745] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input5
6228 13:40:52.606363 <6>[ 3.708100] input: volume-buttons as /devices/platform/volume-buttons/input/input6
6229 13:40:53.993253 <6>[ 5.096379] r8152 1-1.2:1.0 eth0: carrier on
6230 13:40:56.919354 <5>[ 5.126392] Sending DHCP requests .., OK
6231 13:40:56.926252 <6>[ 8.026773] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6232 13:40:56.929287 <6>[ 8.035215] IP-Config: Complete:
6233 13:40:56.943045 <6>[ 8.038785] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6234 13:40:56.952760 <6>[ 8.049684] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6235 13:40:56.959527 <6>[ 8.059168] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6236 13:40:56.962685 <6>[ 8.059177] nameserver0=192.168.201.1
6237 13:40:56.969478 <6>[ 8.071548] clk: Disabling unused clocks
6238 13:40:56.972590 <6>[ 8.076629] ALSA device list:
6239 13:40:56.980371 <6>[ 8.083234] #0: mt8183_mt6358_ts3a227_max98357
6240 13:40:56.991545 <6>[ 8.094426] Freeing unused kernel memory: 8512K
6241 13:40:56.998992 <6>[ 8.101837] Run /init as init process
6242 13:40:57.037493 Starting syslogd: OK
6243 13:40:57.040680 Starting klogd: OK
6244 13:40:57.049891 Running sysctl: OK
6245 13:40:57.056264 Populating /dev using udev: <30>[ 8.160942] udevd[209]: starting version 3.2.9
6246 13:40:57.067051 <27>[ 8.169486] udevd[209]: specified user 'tss' unknown
6247 13:40:57.073100 <27>[ 8.175864] udevd[209]: specified group 'tss' unknown
6248 13:40:57.080525 <30>[ 8.183166] udevd[210]: starting eudev-3.2.9
6249 13:40:57.117963 <27>[ 8.220561] udevd[210]: specified user 'tss' unknown
6250 13:40:57.125153 <27>[ 8.227798] udevd[210]: specified group 'tss' unknown
6251 13:40:57.257563 <3>[ 8.360245] mtk-scp 10500000.scp: invalid resource
6252 13:40:57.267339 <6>[ 8.366080] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6253 13:40:57.277187 <6>[ 8.380109] remoteproc remoteproc0: scp is available
6254 13:40:57.283997 <3>[ 8.383643] thermal_sys: Failed to find 'trips' node
6255 13:40:57.290454 <4>[ 8.385520] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6256 13:40:57.297210 <3>[ 8.390585] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6257 13:40:57.307188 <3>[ 8.390594] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6258 13:40:57.314064 <4>[ 8.390598] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6259 13:40:57.320304 <3>[ 8.393376] thermal_sys: Failed to find 'trips' node
6260 13:40:57.323838 <6>[ 8.399398] remoteproc remoteproc0: powering up scp
6261 13:40:57.334273 <3>[ 8.408247] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6262 13:40:57.340650 <4>[ 8.414891] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6263 13:40:57.343817 <6>[ 8.415005] mc: Linux media interface: v0.10
6264 13:40:57.353577 <3>[ 8.422766] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6265 13:40:57.365288 <3>[ 8.423468] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6266 13:40:57.372250 <4>[ 8.423476] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6267 13:40:57.378646 <3>[ 8.427886] remoteproc remoteproc0: request_firmware failed: -2
6268 13:40:57.385616 <3>[ 8.432844] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6269 13:40:57.399051 <3>[ 8.432852] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6270 13:40:57.405346 <3>[ 8.432857] elan_i2c 2-0015: Error applying setting, reverse things back
6271 13:40:57.412215 <4>[ 8.437941] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6272 13:40:57.416088 <6>[ 8.440597] videodev: Linux video capture interface: v2.00
6273 13:40:57.426645 <4>[ 8.449006] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6274 13:40:57.432681 <5>[ 8.467113] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6275 13:40:57.442867 <3>[ 8.473669] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6276 13:40:57.449157 <6>[ 8.488492] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6277 13:40:57.459670 <3>[ 8.494776] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6278 13:40:57.466165 <5>[ 8.506859] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6279 13:40:57.472248 <3>[ 8.512645] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6280 13:40:57.483151 <5>[ 8.520437] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6281 13:40:57.492502 <3>[ 8.525895] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6282 13:40:57.502661 <4>[ 8.533216] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6283 13:40:57.509318 <3>[ 8.541039] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6284 13:40:57.519319 <3>[ 8.541049] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6285 13:40:57.529618 <3>[ 8.541056] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6286 13:40:57.532449 <6>[ 8.549681] cfg80211: failed to load regulatory.db
6287 13:40:57.542868 <6>[ 8.550155] cs_system_cfg: CoreSight Configuration manager initialised
6288 13:40:57.549491 <3>[ 8.557306] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6289 13:40:57.559877 <3>[ 8.557353] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6290 13:40:57.569726 <6>[ 8.627401] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6291 13:40:57.595563 <6>[ 8.695298] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6292 13:40:57.605735 <6>[ 8.704320] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6293 13:40:57.612731 <6>[ 8.705053] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6294 13:40:57.615538 <6>[ 8.705378] Bluetooth: Core ver 2.22
6295 13:40:57.619200 <6>[ 8.705421] NET: Registered PF_BLUETOOTH protocol family
6296 13:40:57.630957 <6>[ 8.705423] Bluetooth: HCI device and connection manager initialized
6297 13:40:57.634050 <6>[ 8.705434] Bluetooth: HCI socket layer initialized
6298 13:40:57.641034 <6>[ 8.705440] Bluetooth: L2CAP socket layer initialized
6299 13:40:57.644820 <6>[ 8.705447] Bluetooth: SCO socket layer initialized
6300 13:40:57.651681 <6>[ 8.712430] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6301 13:40:57.658443 <6>[ 8.719901] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6302 13:40:57.664661 <6>[ 8.728549] Bluetooth: HCI UART driver ver 2.3
6303 13:40:57.671236 <6>[ 8.730572] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6304 13:40:57.678015 <6>[ 8.730626] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6305 13:40:57.687604 <6>[ 8.731162] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6306 13:40:57.694379 <6>[ 8.731316] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6307 13:40:57.701337 <6>[ 8.737132] Bluetooth: HCI UART protocol H4 registered
6308 13:40:57.714831 <6>[ 8.737164] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6309 13:40:57.721201 <6>[ 8.737398] usbcore: registered new interface driver uvcvideo
6310 13:40:57.727485 <6>[ 8.742407] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6311 13:40:57.734447 <6>[ 8.747649] Bluetooth: HCI UART protocol LL registered
6312 13:40:57.744794 <6>[ 8.752866] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6313 13:40:57.751049 <6>[ 8.760644] Bluetooth: HCI UART protocol Three-wire (H5) registered
6314 13:40:57.757995 <6>[ 8.771491] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6315 13:40:57.765043 <6>[ 8.772536] Bluetooth: HCI UART protocol Broadcom registered
6316 13:40:57.774985 <6>[ 8.780244] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6317 13:40:57.784936 <6>[ 8.783647] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6318 13:40:57.795428 <6>[ 8.783653] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6319 13:40:57.805576 <6>[ 8.783741] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6320 13:40:57.808925 <6>[ 8.786929] Bluetooth: HCI UART protocol QCA registered
6321 13:40:57.815847 <6>[ 8.787854] Bluetooth: hci0: setting up ROME/QCA6390
6322 13:40:57.825708 <4>[ 8.884908] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6323 13:40:57.829421 <4>[ 8.884908] Fallback method does not support PEC.
6324 13:40:57.835990 <6>[ 8.892916] Bluetooth: HCI UART protocol Marvell registered
6325 13:40:57.849055 <3>[ 8.904513] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6326 13:40:57.861577 <6>[ 8.932006] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6327 13:40:57.951233 <3>[ 9.050773] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6328 13:40:57.964081 done
6329 13:40:57.974848 Saving random seed: OK
6330 13:40:57.988708 Starting network: ip: RTNETLINK answers: File exists
6331 13:40:57.993531 FAIL
6332 13:40:58.001700 <3>[ 9.103962] Bluetooth: hci0: Frame reassembly failed (-84)
6333 13:40:58.033177 Starting dropbear sshd: <6>[ 9.135470] NET: Registered PF_INET6 protocol family
6334 13:40:58.039651 <6>[ 9.142292] Segment Routing with IPv6
6335 13:40:58.043070 <6>[ 9.147121] In-situ OAM (IOAM) with IPv6
6336 13:40:58.048280 OK
6337 13:40:58.058631 /bin/sh: can't access tty; job control turned off
6338 13:40:58.059591 Matched prompt #10: / #
6340 13:40:58.060455 Setting prompt string to ['/ #']
6341 13:40:58.060815 end: 2.2.5.1 login-action (duration 00:00:10) [common]
6343 13:40:58.061624 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
6344 13:40:58.061991 start: 2.2.6 expect-shell-connection (timeout 00:04:07) [common]
6345 13:40:58.062280 Setting prompt string to ['/ #']
6346 13:40:58.062536 Forcing a shell prompt, looking for ['/ #']
6348 13:40:58.113184 / #
6349 13:40:58.113716 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6350 13:40:58.114038 Waiting using forced prompt support (timeout 00:02:30)
6351 13:40:58.118566
6352 13:40:58.119281 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6353 13:40:58.119909 start: 2.2.7 export-device-env (timeout 00:04:07) [common]
6354 13:40:58.120555 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6355 13:40:58.121103 end: 2.2 depthcharge-retry (duration 00:00:53) [common]
6356 13:40:58.121624 end: 2 depthcharge-action (duration 00:00:53) [common]
6357 13:40:58.122055 start: 3 lava-test-retry (timeout 00:01:00) [common]
6358 13:40:58.122425 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
6359 13:40:58.122750 Using namespace: common
6361 13:40:58.223647 / # #
6362 13:40:58.224147 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
6363 13:40:58.229391 #
6364 13:40:58.230041 Using /lava-14063110
6366 13:40:58.330860 / # export SHELL=/bin/sh
6367 13:40:58.331282 <6>[ 9.383672] Bluetooth: hci0: QCA Product ID :0x00000008
6368 13:40:58.331533 export SHELL=/bin/sh<6>[ 9.393839] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6369 13:40:58.331701 <6>[ 9.393848] Bluetooth: hci0: QCA SOC Version :0x00000044
6370 13:40:58.331945 <6>[ 9.393857] Bluetooth: hci0: QCA ROM Version :0x00000302
6371 13:40:58.332187 <6>[ 9.428354] Bluetooth: hci0: QCA Patch Version:0x00000111
6372 13:40:58.371582 <6>[ 9.437491] Bluetooth: hci0: QCA controller version 0x00440302
6373 13:40:58.371730
6374 13:40:58.371807 / # <6>[ 9.446690] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6375 13:40:58.371876 <4>[ 9.456192] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6377 13:40:58.472390 <3>[ 9.467793] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_. /lava-14063110/environment
6378 13:40:58.472615 00440302.bin (-2)
6379 13:40:58.472698 <3>[ 9.478140] Bluetooth: hci0: QCA Failed to download patch (-2)
6380 13:40:58.472768 <4>[ 9.479414] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6381 13:40:58.472861 <4>[ 9.508172] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6382 13:40:58.472962 <4>[ 9.524522] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6383 13:40:58.473072 . /lava-14063110/environment<4>[ 9.537896] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6384 13:40:58.477678
6386 13:40:58.578255 / # /lava-14063110/bin/lava-test-runner /lava-14063110/0
6387 13:40:58.578424 Test shell timeout: 10s (minimum of the action and connection timeout)
6388 13:40:58.583238 /lava-14063110/bin/lava-test-runner /lava-14063110/0
6389 13:40:58.605178 + export 'TESTRUN_ID=0_dmesg'
6390 13:40:58.614942 + cd /lava-140631<8>[ 9.714247] <LAVA_SIGNAL_STARTRUN 0_dmesg 14063110_1.5.2.3.1>
6391 13:40:58.615242 10/0/tests/0_dmesg
6392 13:40:58.615498 + cat uuid
6393 13:40:58.615942 Received signal: <STARTRUN> 0_dmesg 14063110_1.5.2.3.1
6394 13:40:58.616165 Starting test lava.0_dmesg (14063110_1.5.2.3.1)
6395 13:40:58.616414 Skipping test definition patterns.
6396 13:40:58.618123 + UUID=14063110_1.5.2.3.1
6397 13:40:58.621924 + set +x
6398 13:40:58.625146 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
6399 13:40:58.639815 <8>[ 9.739059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
6400 13:40:58.640422 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
6402 13:40:58.664944 <8>[ 9.764129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
6403 13:40:58.665681 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
6405 13:40:58.692243 <8>[ 9.791597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
6406 13:40:58.692895 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
6408 13:40:58.697947 + set +x
6409 13:40:58.701103 Received signal: <ENDRUN> 0_dmesg 14063110_1.5.2.3.1
6410 13:40:58.701585 Ending use of test pattern.
6411 13:40:58.701987 Ending test lava.0_dmesg (14063110_1.5.2.3.1), duration 0.09
6413 13:40:58.703998 <8>[ 9.803712] <LAVA_SIGNAL_ENDRUN 0_dmesg 14063110_1.5.2.3.1>
6414 13:40:58.708401 <LAVA_TEST_RUNNER EXIT>
6415 13:40:58.709137 ok: lava_test_shell seems to have completed
6416 13:40:58.709807 alert: pass
crit: pass
emerg: pass
6417 13:40:58.710189 end: 3.1 lava-test-shell (duration 00:00:01) [common]
6418 13:40:58.710591 end: 3 lava-test-retry (duration 00:00:01) [common]
6419 13:40:58.710970 start: 4 finalize (timeout 00:08:46) [common]
6420 13:40:58.711552 start: 4.1 power-off (timeout 00:00:30) [common]
6421 13:40:58.712274 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
6422 13:40:58.926460 >> Command sent successfully.
6423 13:40:58.936217 Returned 0 in 0 seconds
6424 13:40:59.037507 end: 4.1 power-off (duration 00:00:00) [common]
6426 13:40:59.038988 start: 4.2 read-feedback (timeout 00:08:46) [common]
6427 13:40:59.040190 Listened to connection for namespace 'common' for up to 1s
6428 13:41:00.040794 Finalising connection for namespace 'common'
6429 13:41:00.041034 Disconnecting from shell: Finalise
6430 13:41:00.041182 / #
6431 13:41:00.141551 end: 4.2 read-feedback (duration 00:00:01) [common]
6432 13:41:00.141725 end: 4 finalize (duration 00:00:01) [common]
6433 13:41:00.141858 Cleaning after the job
6434 13:41:00.141984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/ramdisk
6435 13:41:00.144817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/kernel
6436 13:41:00.154852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/dtb
6437 13:41:00.155089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063110/tftp-deploy-d74aqu_f/modules
6438 13:41:00.162803 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063110
6439 13:41:00.212521 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063110
6440 13:41:00.212696 Job finished correctly