Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:41:06.796329 lava-dispatcher, installed at version: 2024.03
2 13:41:06.796566 start: 0 validate
3 13:41:06.796705 Start time: 2024-05-28 13:41:06.796697+00:00 (UTC)
4 13:41:06.796823 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:41:06.796964 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:41:07.055416 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:41:07.055610 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:41:20.816646 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:41:20.817325 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:41:21.073194 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:41:21.073829 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:41:21.576113 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:41:21.576819 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:41:24.590738 validate duration: 17.79
16 13:41:24.592450 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:41:24.593286 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:41:24.593967 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:41:24.594848 Not decompressing ramdisk as can be used compressed.
20 13:41:24.595351 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 13:41:24.595769 saving as /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/ramdisk/initrd.cpio.gz
22 13:41:24.596117 total size: 5628182 (5 MB)
23 13:41:24.856963 progress 0 % (0 MB)
24 13:41:24.858616 progress 5 % (0 MB)
25 13:41:24.860241 progress 10 % (0 MB)
26 13:41:24.861687 progress 15 % (0 MB)
27 13:41:24.863266 progress 20 % (1 MB)
28 13:41:24.864760 progress 25 % (1 MB)
29 13:41:24.866327 progress 30 % (1 MB)
30 13:41:24.867870 progress 35 % (1 MB)
31 13:41:24.869308 progress 40 % (2 MB)
32 13:41:24.870886 progress 45 % (2 MB)
33 13:41:24.872379 progress 50 % (2 MB)
34 13:41:24.873928 progress 55 % (2 MB)
35 13:41:24.875524 progress 60 % (3 MB)
36 13:41:24.877316 progress 65 % (3 MB)
37 13:41:24.879179 progress 70 % (3 MB)
38 13:41:24.880660 progress 75 % (4 MB)
39 13:41:24.882264 progress 80 % (4 MB)
40 13:41:24.884116 progress 85 % (4 MB)
41 13:41:24.885719 progress 90 % (4 MB)
42 13:41:24.887241 progress 95 % (5 MB)
43 13:41:24.888654 progress 100 % (5 MB)
44 13:41:24.888862 5 MB downloaded in 0.29 s (18.33 MB/s)
45 13:41:24.889019 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:41:24.889254 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:41:24.889340 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:41:24.889431 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:41:24.889569 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:41:24.889637 saving as /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/kernel/Image
52 13:41:24.889703 total size: 54682112 (52 MB)
53 13:41:24.889766 No compression specified
54 13:41:24.890918 progress 0 % (0 MB)
55 13:41:24.905687 progress 5 % (2 MB)
56 13:41:24.919487 progress 10 % (5 MB)
57 13:41:24.933568 progress 15 % (7 MB)
58 13:41:24.947281 progress 20 % (10 MB)
59 13:41:24.961312 progress 25 % (13 MB)
60 13:41:24.976566 progress 30 % (15 MB)
61 13:41:24.990559 progress 35 % (18 MB)
62 13:41:25.005466 progress 40 % (20 MB)
63 13:41:25.019810 progress 45 % (23 MB)
64 13:41:25.034943 progress 50 % (26 MB)
65 13:41:25.049090 progress 55 % (28 MB)
66 13:41:25.063598 progress 60 % (31 MB)
67 13:41:25.080235 progress 65 % (33 MB)
68 13:41:25.096750 progress 70 % (36 MB)
69 13:41:25.110727 progress 75 % (39 MB)
70 13:41:25.125555 progress 80 % (41 MB)
71 13:41:25.140485 progress 85 % (44 MB)
72 13:41:25.155162 progress 90 % (46 MB)
73 13:41:25.169289 progress 95 % (49 MB)
74 13:41:25.183400 progress 100 % (52 MB)
75 13:41:25.183675 52 MB downloaded in 0.29 s (177.40 MB/s)
76 13:41:25.183832 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:41:25.184080 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:41:25.184197 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:41:25.184332 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:41:25.184518 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:41:25.184616 saving as /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/dtb/mt8192-asurada-spherion-r0.dtb
83 13:41:25.184707 total size: 47258 (0 MB)
84 13:41:25.184799 No compression specified
85 13:41:25.186180 progress 69 % (0 MB)
86 13:41:25.186536 progress 100 % (0 MB)
87 13:41:25.186698 0 MB downloaded in 0.00 s (22.66 MB/s)
88 13:41:25.186825 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:41:25.187054 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:41:25.187143 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:41:25.187229 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:41:25.187345 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 13:41:25.187414 saving as /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/nfsrootfs/full.rootfs.tar
95 13:41:25.187477 total size: 107552908 (102 MB)
96 13:41:25.187540 Using unxz to decompress xz
97 13:41:25.191558 progress 0 % (0 MB)
98 13:41:25.483466 progress 5 % (5 MB)
99 13:41:25.815785 progress 10 % (10 MB)
100 13:41:26.146594 progress 15 % (15 MB)
101 13:41:26.479107 progress 20 % (20 MB)
102 13:41:26.752052 progress 25 % (25 MB)
103 13:41:27.044987 progress 30 % (30 MB)
104 13:41:27.364203 progress 35 % (35 MB)
105 13:41:27.531624 progress 40 % (41 MB)
106 13:41:27.730602 progress 45 % (46 MB)
107 13:41:28.042963 progress 50 % (51 MB)
108 13:41:28.347616 progress 55 % (56 MB)
109 13:41:28.684686 progress 60 % (61 MB)
110 13:41:29.031022 progress 65 % (66 MB)
111 13:41:29.364909 progress 70 % (71 MB)
112 13:41:29.725715 progress 75 % (76 MB)
113 13:41:30.050793 progress 80 % (82 MB)
114 13:41:30.385115 progress 85 % (87 MB)
115 13:41:30.696044 progress 90 % (92 MB)
116 13:41:31.020255 progress 95 % (97 MB)
117 13:41:31.360496 progress 100 % (102 MB)
118 13:41:31.365786 102 MB downloaded in 6.18 s (16.60 MB/s)
119 13:41:31.366075 end: 1.4.1 http-download (duration 00:00:06) [common]
121 13:41:31.366506 end: 1.4 download-retry (duration 00:00:06) [common]
122 13:41:31.366636 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:41:31.366757 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:41:31.366942 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:41:31.367040 saving as /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/modules/modules.tar
126 13:41:31.367133 total size: 8607916 (8 MB)
127 13:41:31.367228 Using unxz to decompress xz
128 13:41:31.372028 progress 0 % (0 MB)
129 13:41:31.393363 progress 5 % (0 MB)
130 13:41:31.419743 progress 10 % (0 MB)
131 13:41:31.447370 progress 15 % (1 MB)
132 13:41:31.475654 progress 20 % (1 MB)
133 13:41:31.504798 progress 25 % (2 MB)
134 13:41:31.532860 progress 30 % (2 MB)
135 13:41:31.557713 progress 35 % (2 MB)
136 13:41:31.585621 progress 40 % (3 MB)
137 13:41:31.611949 progress 45 % (3 MB)
138 13:41:31.638412 progress 50 % (4 MB)
139 13:41:31.665004 progress 55 % (4 MB)
140 13:41:31.691640 progress 60 % (4 MB)
141 13:41:31.717074 progress 65 % (5 MB)
142 13:41:31.744367 progress 70 % (5 MB)
143 13:41:31.774107 progress 75 % (6 MB)
144 13:41:31.801033 progress 80 % (6 MB)
145 13:41:31.826648 progress 85 % (7 MB)
146 13:41:31.851416 progress 90 % (7 MB)
147 13:41:31.881509 progress 95 % (7 MB)
148 13:41:31.910396 progress 100 % (8 MB)
149 13:41:31.916261 8 MB downloaded in 0.55 s (14.95 MB/s)
150 13:41:31.916534 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:41:31.916837 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:41:31.916952 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:41:31.917090 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:41:34.250462 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew
156 13:41:34.250675 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:41:34.250783 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 13:41:34.250982 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud
159 13:41:34.251117 makedir: /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin
160 13:41:34.251220 makedir: /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/tests
161 13:41:34.251319 makedir: /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/results
162 13:41:34.251431 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-add-keys
163 13:41:34.251582 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-add-sources
164 13:41:34.251711 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-background-process-start
165 13:41:34.251839 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-background-process-stop
166 13:41:34.251978 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-common-functions
167 13:41:34.252106 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-echo-ipv4
168 13:41:34.252231 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-install-packages
169 13:41:34.252494 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-installed-packages
170 13:41:34.252680 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-os-build
171 13:41:34.252810 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-probe-channel
172 13:41:34.252943 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-probe-ip
173 13:41:34.253069 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-target-ip
174 13:41:34.253194 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-target-mac
175 13:41:34.253319 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-target-storage
176 13:41:34.253445 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-case
177 13:41:34.253575 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-event
178 13:41:34.253698 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-feedback
179 13:41:34.253822 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-raise
180 13:41:34.253943 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-reference
181 13:41:34.254072 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-runner
182 13:41:34.254221 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-set
183 13:41:34.254354 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-test-shell
184 13:41:34.254481 Updating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-install-packages (oe)
185 13:41:34.254644 Updating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/bin/lava-installed-packages (oe)
186 13:41:34.254767 Creating /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/environment
187 13:41:34.254865 LAVA metadata
188 13:41:34.254932 - LAVA_JOB_ID=14063033
189 13:41:34.254994 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:41:34.255118 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 13:41:34.255187 skipped lava-vland-overlay
192 13:41:34.255263 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:41:34.255343 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 13:41:34.255405 skipped lava-multinode-overlay
195 13:41:34.255477 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:41:34.255561 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 13:41:34.255640 Loading test definitions
198 13:41:34.255738 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 13:41:34.255810 Using /lava-14063033 at stage 0
200 13:41:34.256126 uuid=14063033_1.6.2.3.1 testdef=None
201 13:41:34.256216 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:41:34.256301 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 13:41:34.256855 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:41:34.257085 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 13:41:34.257739 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:41:34.257971 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 13:41:34.258598 runner path: /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/0/tests/0_dmesg test_uuid 14063033_1.6.2.3.1
210 13:41:34.258760 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:41:34.258966 Creating lava-test-runner.conf files
213 13:41:34.259030 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063033/lava-overlay-eo7xmiud/lava-14063033/0 for stage 0
214 13:41:34.259128 - 0_dmesg
215 13:41:34.259226 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 13:41:34.259311 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
217 13:41:34.265542 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 13:41:34.265701 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
219 13:41:34.265794 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 13:41:34.265890 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 13:41:34.265976 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
222 13:41:34.438179 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 13:41:34.438676 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 13:41:34.438853 extracting modules file /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew
225 13:41:34.703931 extracting modules file /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063033/extract-overlay-ramdisk-kq92_c_o/ramdisk
226 13:41:34.946432 end: 1.6.4 extract-modules (duration 00:00:01) [common]
227 13:41:34.946613 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 13:41:34.946710 [common] Applying overlay to NFS
229 13:41:34.946780 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063033/compress-overlay-i6gqko5e/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew
230 13:41:34.954717 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 13:41:34.954903 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 13:41:34.955005 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 13:41:34.955098 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 13:41:34.955184 Building ramdisk /var/lib/lava/dispatcher/tmp/14063033/extract-overlay-ramdisk-kq92_c_o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063033/extract-overlay-ramdisk-kq92_c_o/ramdisk
235 13:41:35.275844 >> 130335 blocks
236 13:41:37.379368 rename /var/lib/lava/dispatcher/tmp/14063033/extract-overlay-ramdisk-kq92_c_o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/ramdisk/ramdisk.cpio.gz
237 13:41:37.379866 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 13:41:37.380003 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
239 13:41:37.380123 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
240 13:41:37.380233 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/kernel/Image']
241 13:41:52.039403 Returned 0 in 14 seconds
242 13:41:52.140364 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/kernel/image.itb
243 13:41:52.495215 output: FIT description: Kernel Image image with one or more FDT blobs
244 13:41:52.495569 output: Created: Tue May 28 14:41:52 2024
245 13:41:52.495644 output: Image 0 (kernel-1)
246 13:41:52.495709 output: Description:
247 13:41:52.495769 output: Created: Tue May 28 14:41:52 2024
248 13:41:52.495827 output: Type: Kernel Image
249 13:41:52.495886 output: Compression: lzma compressed
250 13:41:52.495946 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
251 13:41:52.496003 output: Architecture: AArch64
252 13:41:52.496061 output: OS: Linux
253 13:41:52.496117 output: Load Address: 0x00000000
254 13:41:52.496178 output: Entry Point: 0x00000000
255 13:41:52.496233 output: Hash algo: crc32
256 13:41:52.496288 output: Hash value: 0578ee26
257 13:41:52.496353 output: Image 1 (fdt-1)
258 13:41:52.496447 output: Description: mt8192-asurada-spherion-r0
259 13:41:52.496504 output: Created: Tue May 28 14:41:52 2024
260 13:41:52.496563 output: Type: Flat Device Tree
261 13:41:52.496617 output: Compression: uncompressed
262 13:41:52.496678 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 13:41:52.496768 output: Architecture: AArch64
264 13:41:52.496860 output: Hash algo: crc32
265 13:41:52.496945 output: Hash value: 0f8e4d2e
266 13:41:52.497031 output: Image 2 (ramdisk-1)
267 13:41:52.497118 output: Description: unavailable
268 13:41:52.497178 output: Created: Tue May 28 14:41:52 2024
269 13:41:52.497234 output: Type: RAMDisk Image
270 13:41:52.497289 output: Compression: Unknown Compression
271 13:41:52.497343 output: Data Size: 18731765 Bytes = 18292.74 KiB = 17.86 MiB
272 13:41:52.497397 output: Architecture: AArch64
273 13:41:52.497450 output: OS: Linux
274 13:41:52.497503 output: Load Address: unavailable
275 13:41:52.497556 output: Entry Point: unavailable
276 13:41:52.497608 output: Hash algo: crc32
277 13:41:52.497660 output: Hash value: 88aa0a61
278 13:41:52.497712 output: Default Configuration: 'conf-1'
279 13:41:52.497765 output: Configuration 0 (conf-1)
280 13:41:52.497817 output: Description: mt8192-asurada-spherion-r0
281 13:41:52.497870 output: Kernel: kernel-1
282 13:41:52.497922 output: Init Ramdisk: ramdisk-1
283 13:41:52.497974 output: FDT: fdt-1
284 13:41:52.498026 output: Loadables: kernel-1
285 13:41:52.498078 output:
286 13:41:52.498280 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 13:41:52.498374 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 13:41:52.498481 end: 1.6 prepare-tftp-overlay (duration 00:00:21) [common]
289 13:41:52.498569 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
290 13:41:52.498649 No LXC device requested
291 13:41:52.498741 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 13:41:52.498833 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
293 13:41:52.498910 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 13:41:52.498979 Checking files for TFTP limit of 4294967296 bytes.
295 13:41:52.499482 end: 1 tftp-deploy (duration 00:00:28) [common]
296 13:41:52.499586 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 13:41:52.499680 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 13:41:52.499801 substitutions:
299 13:41:52.499866 - {DTB}: 14063033/tftp-deploy-qws1jlf3/dtb/mt8192-asurada-spherion-r0.dtb
300 13:41:52.499931 - {INITRD}: 14063033/tftp-deploy-qws1jlf3/ramdisk/ramdisk.cpio.gz
301 13:41:52.499989 - {KERNEL}: 14063033/tftp-deploy-qws1jlf3/kernel/Image
302 13:41:52.500057 - {LAVA_MAC}: None
303 13:41:52.500146 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew
304 13:41:52.500238 - {NFS_SERVER_IP}: 192.168.201.1
305 13:41:52.500323 - {PRESEED_CONFIG}: None
306 13:41:52.500441 - {PRESEED_LOCAL}: None
307 13:41:52.500499 - {RAMDISK}: 14063033/tftp-deploy-qws1jlf3/ramdisk/ramdisk.cpio.gz
308 13:41:52.500555 - {ROOT_PART}: None
309 13:41:52.500610 - {ROOT}: None
310 13:41:52.500664 - {SERVER_IP}: 192.168.201.1
311 13:41:52.500718 - {TEE}: None
312 13:41:52.500772 Parsed boot commands:
313 13:41:52.500825 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 13:41:52.501006 Parsed boot commands: tftpboot 192.168.201.1 14063033/tftp-deploy-qws1jlf3/kernel/image.itb 14063033/tftp-deploy-qws1jlf3/kernel/cmdline
315 13:41:52.501093 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 13:41:52.501182 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 13:41:52.501274 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 13:41:52.501358 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 13:41:52.501429 Not connected, no need to disconnect.
320 13:41:52.501502 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 13:41:52.501582 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 13:41:52.501649 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 13:41:52.505411 Setting prompt string to ['lava-test: # ']
324 13:41:52.505776 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 13:41:52.505883 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 13:41:52.505980 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 13:41:52.506069 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 13:41:52.506267 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
329 13:41:57.638967 >> Command sent successfully.
330 13:41:57.641505 Returned 0 in 5 seconds
331 13:41:57.741909 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 13:41:57.742235 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 13:41:57.742334 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 13:41:57.742421 Setting prompt string to 'Starting depthcharge on Spherion...'
336 13:41:57.742526 Changing prompt to 'Starting depthcharge on Spherion...'
337 13:41:57.742593 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 13:41:57.742983 [Enter `^Ec?' for help]
339 13:41:57.917781
340 13:41:57.917930
341 13:41:57.918005 F0: 102B 0000
342 13:41:57.918105
343 13:41:57.920883 F3: 1001 0000 [0200]
344 13:41:57.920970
345 13:41:57.921037 F3: 1001 0000
346 13:41:57.921102
347 13:41:57.921161 F7: 102D 0000
348 13:41:57.921220
349 13:41:57.923956 F1: 0000 0000
350 13:41:57.924039
351 13:41:57.924105 V0: 0000 0000 [0001]
352 13:41:57.924167
353 13:41:57.928020 00: 0007 8000
354 13:41:57.928108
355 13:41:57.928202 01: 0000 0000
356 13:41:57.928323
357 13:41:57.930816 BP: 0C00 0209 [0000]
358 13:41:57.930925
359 13:41:57.931020 G0: 1182 0000
360 13:41:57.931131
361 13:41:57.933880 EC: 0000 0021 [4000]
362 13:41:57.933969
363 13:41:57.934035 S7: 0000 0000 [0000]
364 13:41:57.934096
365 13:41:57.937545 CC: 0000 0000 [0001]
366 13:41:57.937625
367 13:41:57.937717 T0: 0000 0040 [010F]
368 13:41:57.937851
369 13:41:57.941331 Jump to BL
370 13:41:57.941432
371 13:41:57.964712
372 13:41:57.964830
373 13:41:57.972230 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 13:41:57.975839 ARM64: Exception handlers installed.
375 13:41:57.980424 ARM64: Testing exception
376 13:41:57.980543 ARM64: Done test exception
377 13:41:57.989947 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 13:41:58.000865 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 13:41:58.007581 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 13:41:58.017159 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 13:41:58.023890 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 13:41:58.031117 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 13:41:58.042290 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 13:41:58.048126 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 13:41:58.067605 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 13:41:58.071212 WDT: Last reset was cold boot
387 13:41:58.074307 SPI1(PAD0) initialized at 2873684 Hz
388 13:41:58.078141 SPI5(PAD0) initialized at 992727 Hz
389 13:41:58.081051 VBOOT: Loading verstage.
390 13:41:58.088048 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 13:41:58.091117 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 13:41:58.094845 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 13:41:58.097881 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 13:41:58.104941 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 13:41:58.111729 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 13:41:58.122727 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
397 13:41:58.122826
398 13:41:58.122896
399 13:41:58.133346 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 13:41:58.136764 ARM64: Exception handlers installed.
401 13:41:58.136847 ARM64: Testing exception
402 13:41:58.140171 ARM64: Done test exception
403 13:41:58.143709 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 13:41:58.149813 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 13:41:58.163812 Probing TPM: . done!
406 13:41:58.163897 TPM ready after 0 ms
407 13:41:58.171164 Connected to device vid:did:rid of 1ae0:0028:00
408 13:41:58.178165 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 13:41:58.235802 Initialized TPM device CR50 revision 0
410 13:41:58.247921 tlcl_send_startup: Startup return code is 0
411 13:41:58.248055 TPM: setup succeeded
412 13:41:58.259232 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 13:41:58.267673 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 13:41:58.279815 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 13:41:58.290522 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 13:41:58.294344 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 13:41:58.297359 in-header: 03 07 00 00 08 00 00 00
418 13:41:58.301213 in-data: aa e4 47 04 13 02 00 00
419 13:41:58.301328 Chrome EC: UHEPI supported
420 13:41:58.308197 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 13:41:58.313187 in-header: 03 95 00 00 08 00 00 00
422 13:41:58.316853 in-data: 18 20 20 08 00 00 00 00
423 13:41:58.320691 Phase 1
424 13:41:58.324477 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 13:41:58.327383 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 13:41:58.335753 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 13:41:58.335875 Recovery requested (1009000e)
428 13:41:58.345709 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 13:41:58.351861 tlcl_extend: response is 0
430 13:41:58.363397 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 13:41:58.366749 tlcl_extend: response is 0
432 13:41:58.373869 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 13:41:58.393425 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 13:41:58.400061 BS: bootblock times (exec / console): total (unknown) / 149 ms
435 13:41:58.400153
436 13:41:58.400239
437 13:41:58.410075 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 13:41:58.413730 ARM64: Exception handlers installed.
439 13:41:58.416749 ARM64: Testing exception
440 13:41:58.416833 ARM64: Done test exception
441 13:41:58.439175 pmic_efuse_setting: Set efuses in 11 msecs
442 13:41:58.442147 pmwrap_interface_init: Select PMIF_VLD_RDY
443 13:41:58.448776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 13:41:58.452263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 13:41:58.459538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 13:41:58.463330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 13:41:58.466894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 13:41:58.470669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 13:41:58.478274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 13:41:58.482103 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 13:41:58.485179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 13:41:58.493147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 13:41:58.496678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 13:41:58.501120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 13:41:58.505323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 13:41:58.512730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 13:41:58.516221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 13:41:58.523790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 13:41:58.527507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 13:41:58.535029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 13:41:58.538850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 13:41:58.546403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 13:41:58.550177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 13:41:58.557777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 13:41:58.561413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 13:41:58.568614 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 13:41:58.572233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 13:41:58.579871 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 13:41:58.583675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 13:41:58.587413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 13:41:58.595154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 13:41:58.598943 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 13:41:58.601766 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 13:41:58.609190 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 13:41:58.612786 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 13:41:58.616357 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 13:41:58.624318 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 13:41:58.627773 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 13:41:58.631353 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 13:41:58.639158 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 13:41:58.642579 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 13:41:58.646357 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 13:41:58.649999 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 13:41:58.657702 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 13:41:58.660680 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 13:41:58.664668 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 13:41:58.668168 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 13:41:58.672558 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 13:41:58.675498 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 13:41:58.683208 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 13:41:58.687158 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 13:41:58.690782 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 13:41:58.694109 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 13:41:58.701534 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 13:41:58.709104 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 13:41:58.716373 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 13:41:58.723880 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 13:41:58.731427 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 13:41:58.735032 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 13:41:58.742104 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 13:41:58.745648 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 13:41:58.752719 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x14
503 13:41:58.756350 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 13:41:58.764346 [RTC]rtc_osc_init,62: osc32con val = 0xde71
505 13:41:58.767338 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 13:41:58.776261 [RTC]rtc_get_frequency_meter,154: input=15, output=758
507 13:41:58.785661 [RTC]rtc_get_frequency_meter,154: input=23, output=941
508 13:41:58.795666 [RTC]rtc_get_frequency_meter,154: input=19, output=851
509 13:41:58.804856 [RTC]rtc_get_frequency_meter,154: input=17, output=805
510 13:41:58.814820 [RTC]rtc_get_frequency_meter,154: input=16, output=782
511 13:41:58.824223 [RTC]rtc_get_frequency_meter,154: input=16, output=782
512 13:41:58.834397 [RTC]rtc_get_frequency_meter,154: input=17, output=806
513 13:41:58.838112 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
514 13:41:58.841866 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
515 13:41:58.845720 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 13:41:58.852821 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
517 13:41:58.856528 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 13:41:58.860301 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
519 13:41:58.863867 ADC[4]: Raw value=906203 ID=7
520 13:41:58.863954 ADC[3]: Raw value=213441 ID=1
521 13:41:58.868296 RAM Code: 0x71
522 13:41:58.871806 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 13:41:58.875502 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 13:41:58.883797 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 13:41:58.890540 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 13:41:58.894066 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 13:41:58.898429 in-header: 03 07 00 00 08 00 00 00
528 13:41:58.901545 in-data: aa e4 47 04 13 02 00 00
529 13:41:58.905478 Chrome EC: UHEPI supported
530 13:41:58.912242 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 13:41:58.916130 in-header: 03 95 00 00 08 00 00 00
532 13:41:58.916235 in-data: 18 20 20 08 00 00 00 00
533 13:41:58.919806 MRC: failed to locate region type 0.
534 13:41:58.927374 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 13:41:58.931074 DRAM-K: Running full calibration
536 13:41:58.938346 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 13:41:58.938493 header.status = 0x0
538 13:41:58.942115 header.version = 0x6 (expected: 0x6)
539 13:41:58.945810 header.size = 0xd00 (expected: 0xd00)
540 13:41:58.945916 header.flags = 0x0
541 13:41:58.953306 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 13:41:58.972046 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 13:41:58.979115 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 13:41:58.979205 dram_init: ddr_geometry: 2
545 13:41:58.982847 [EMI] MDL number = 2
546 13:41:58.982928 [EMI] Get MDL freq = 0
547 13:41:58.986576 dram_init: ddr_type: 0
548 13:41:58.990333 is_discrete_lpddr4: 1
549 13:41:58.990415 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 13:41:58.990480
551 13:41:58.990557
552 13:41:58.993898 [Bian_co] ETT version 0.0.0.1
553 13:41:58.998427 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 13:41:58.998533
555 13:41:59.002099 dramc_set_vcore_voltage set vcore to 650000
556 13:41:59.006253 Read voltage for 800, 4
557 13:41:59.006334 Vio18 = 0
558 13:41:59.009311 Vcore = 650000
559 13:41:59.009406 Vdram = 0
560 13:41:59.009471 Vddq = 0
561 13:41:59.009534 Vmddr = 0
562 13:41:59.013832 dram_init: config_dvfs: 1
563 13:41:59.017686 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 13:41:59.024895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 13:41:59.028021 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
566 13:41:59.031868 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
567 13:41:59.035578 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
568 13:41:59.039243 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
569 13:41:59.042970 MEM_TYPE=3, freq_sel=18
570 13:41:59.043083 sv_algorithm_assistance_LP4_1600
571 13:41:59.049428 ============ PULL DRAM RESETB DOWN ============
572 13:41:59.052745 ========== PULL DRAM RESETB DOWN end =========
573 13:41:59.055783 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 13:41:59.059491 ===================================
575 13:41:59.063074 LPDDR4 DRAM CONFIGURATION
576 13:41:59.066244 ===================================
577 13:41:59.066328 EX_ROW_EN[0] = 0x0
578 13:41:59.069761 EX_ROW_EN[1] = 0x0
579 13:41:59.069836 LP4Y_EN = 0x0
580 13:41:59.073464 WORK_FSP = 0x0
581 13:41:59.073565 WL = 0x2
582 13:41:59.077620 RL = 0x2
583 13:41:59.077701 BL = 0x2
584 13:41:59.081146 RPST = 0x0
585 13:41:59.081221 RD_PRE = 0x0
586 13:41:59.084453 WR_PRE = 0x1
587 13:41:59.084529 WR_PST = 0x0
588 13:41:59.088126 DBI_WR = 0x0
589 13:41:59.088203 DBI_RD = 0x0
590 13:41:59.091731 OTF = 0x1
591 13:41:59.094682 ===================================
592 13:41:59.098480 ===================================
593 13:41:59.098588 ANA top config
594 13:41:59.101529 ===================================
595 13:41:59.105284 DLL_ASYNC_EN = 0
596 13:41:59.108220 ALL_SLAVE_EN = 1
597 13:41:59.108345 NEW_RANK_MODE = 1
598 13:41:59.111771 DLL_IDLE_MODE = 1
599 13:41:59.114700 LP45_APHY_COMB_EN = 1
600 13:41:59.118443 TX_ODT_DIS = 1
601 13:41:59.122145 NEW_8X_MODE = 1
602 13:41:59.122225 ===================================
603 13:41:59.125946 ===================================
604 13:41:59.128851 data_rate = 1600
605 13:41:59.132619 CKR = 1
606 13:41:59.135582 DQ_P2S_RATIO = 8
607 13:41:59.138641 ===================================
608 13:41:59.142447 CA_P2S_RATIO = 8
609 13:41:59.142528 DQ_CA_OPEN = 0
610 13:41:59.145545 DQ_SEMI_OPEN = 0
611 13:41:59.149266 CA_SEMI_OPEN = 0
612 13:41:59.152214 CA_FULL_RATE = 0
613 13:41:59.156048 DQ_CKDIV4_EN = 1
614 13:41:59.158897 CA_CKDIV4_EN = 1
615 13:41:59.158974 CA_PREDIV_EN = 0
616 13:41:59.162540 PH8_DLY = 0
617 13:41:59.165510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 13:41:59.169015 DQ_AAMCK_DIV = 4
619 13:41:59.172475 CA_AAMCK_DIV = 4
620 13:41:59.175344 CA_ADMCK_DIV = 4
621 13:41:59.175424 DQ_TRACK_CA_EN = 0
622 13:41:59.179105 CA_PICK = 800
623 13:41:59.182786 CA_MCKIO = 800
624 13:41:59.185810 MCKIO_SEMI = 0
625 13:41:59.190154 PLL_FREQ = 3068
626 13:41:59.190237 DQ_UI_PI_RATIO = 32
627 13:41:59.193522 CA_UI_PI_RATIO = 0
628 13:41:59.197297 ===================================
629 13:41:59.200704 ===================================
630 13:41:59.204495 memory_type:LPDDR4
631 13:41:59.204582 GP_NUM : 10
632 13:41:59.208621 SRAM_EN : 1
633 13:41:59.208757 MD32_EN : 0
634 13:41:59.211589 ===================================
635 13:41:59.215316 [ANA_INIT] >>>>>>>>>>>>>>
636 13:41:59.219762 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 13:41:59.222548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 13:41:59.226275 ===================================
639 13:41:59.226402 data_rate = 1600,PCW = 0X7600
640 13:41:59.229294 ===================================
641 13:41:59.233012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 13:41:59.239893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 13:41:59.245895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 13:41:59.249623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 13:41:59.252650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 13:41:59.256411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 13:41:59.259497 [ANA_INIT] flow start
648 13:41:59.259600 [ANA_INIT] PLL >>>>>>>>
649 13:41:59.262550 [ANA_INIT] PLL <<<<<<<<
650 13:41:59.266147 [ANA_INIT] MIDPI >>>>>>>>
651 13:41:59.266262 [ANA_INIT] MIDPI <<<<<<<<
652 13:41:59.269768 [ANA_INIT] DLL >>>>>>>>
653 13:41:59.272768 [ANA_INIT] flow end
654 13:41:59.276288 ============ LP4 DIFF to SE enter ============
655 13:41:59.279812 ============ LP4 DIFF to SE exit ============
656 13:41:59.282869 [ANA_INIT] <<<<<<<<<<<<<
657 13:41:59.286677 [Flow] Enable top DCM control >>>>>
658 13:41:59.289946 [Flow] Enable top DCM control <<<<<
659 13:41:59.292968 Enable DLL master slave shuffle
660 13:41:59.296850 ==============================================================
661 13:41:59.299646 Gating Mode config
662 13:41:59.306132 ==============================================================
663 13:41:59.306226 Config description:
664 13:41:59.316648 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 13:41:59.323135 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 13:41:59.326690 SELPH_MODE 0: By rank 1: By Phase
667 13:41:59.333387 ==============================================================
668 13:41:59.336447 GAT_TRACK_EN = 1
669 13:41:59.340106 RX_GATING_MODE = 2
670 13:41:59.343159 RX_GATING_TRACK_MODE = 2
671 13:41:59.346249 SELPH_MODE = 1
672 13:41:59.350077 PICG_EARLY_EN = 1
673 13:41:59.350163 VALID_LAT_VALUE = 1
674 13:41:59.356745 ==============================================================
675 13:41:59.359721 Enter into Gating configuration >>>>
676 13:41:59.362842 Exit from Gating configuration <<<<
677 13:41:59.366659 Enter into DVFS_PRE_config >>>>>
678 13:41:59.376345 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 13:41:59.380103 Exit from DVFS_PRE_config <<<<<
680 13:41:59.383036 Enter into PICG configuration >>>>
681 13:41:59.386829 Exit from PICG configuration <<<<
682 13:41:59.389866 [RX_INPUT] configuration >>>>>
683 13:41:59.393344 [RX_INPUT] configuration <<<<<
684 13:41:59.396216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 13:41:59.403098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 13:41:59.409769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 13:41:59.416388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 13:41:59.423412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 13:41:59.426993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 13:41:59.433605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 13:41:59.437021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 13:41:59.440255 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 13:41:59.443743 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 13:41:59.446546 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 13:41:59.453373 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 13:41:59.457276 ===================================
697 13:41:59.457365 LPDDR4 DRAM CONFIGURATION
698 13:41:59.460140 ===================================
699 13:41:59.463728 EX_ROW_EN[0] = 0x0
700 13:41:59.466862 EX_ROW_EN[1] = 0x0
701 13:41:59.466968 LP4Y_EN = 0x0
702 13:41:59.470596 WORK_FSP = 0x0
703 13:41:59.470685 WL = 0x2
704 13:41:59.473479 RL = 0x2
705 13:41:59.473605 BL = 0x2
706 13:41:59.477193 RPST = 0x0
707 13:41:59.477303 RD_PRE = 0x0
708 13:41:59.480151 WR_PRE = 0x1
709 13:41:59.480229 WR_PST = 0x0
710 13:41:59.483728 DBI_WR = 0x0
711 13:41:59.483812 DBI_RD = 0x0
712 13:41:59.486852 OTF = 0x1
713 13:41:59.490608 ===================================
714 13:41:59.493667 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 13:41:59.497172 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 13:41:59.504069 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 13:41:59.507138 ===================================
718 13:41:59.507236 LPDDR4 DRAM CONFIGURATION
719 13:41:59.510846 ===================================
720 13:41:59.513874 EX_ROW_EN[0] = 0x10
721 13:41:59.513963 EX_ROW_EN[1] = 0x0
722 13:41:59.517391 LP4Y_EN = 0x0
723 13:41:59.517477 WORK_FSP = 0x0
724 13:41:59.520196 WL = 0x2
725 13:41:59.523684 RL = 0x2
726 13:41:59.523770 BL = 0x2
727 13:41:59.526974 RPST = 0x0
728 13:41:59.527061 RD_PRE = 0x0
729 13:41:59.530817 WR_PRE = 0x1
730 13:41:59.530903 WR_PST = 0x0
731 13:41:59.534054 DBI_WR = 0x0
732 13:41:59.534142 DBI_RD = 0x0
733 13:41:59.537455 OTF = 0x1
734 13:41:59.541092 ===================================
735 13:41:59.543805 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 13:41:59.549579 nWR fixed to 40
737 13:41:59.552548 [ModeRegInit_LP4] CH0 RK0
738 13:41:59.552643 [ModeRegInit_LP4] CH0 RK1
739 13:41:59.555824 [ModeRegInit_LP4] CH1 RK0
740 13:41:59.559226 [ModeRegInit_LP4] CH1 RK1
741 13:41:59.559341 match AC timing 13
742 13:41:59.565634 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 13:41:59.569409 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 13:41:59.572493 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 13:41:59.579390 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 13:41:59.582359 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 13:41:59.582445 [EMI DOE] emi_dcm 0
748 13:41:59.589632 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 13:41:59.589720 ==
750 13:41:59.592841 Dram Type= 6, Freq= 0, CH_0, rank 0
751 13:41:59.595663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 13:41:59.595749 ==
753 13:41:59.602327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 13:41:59.608876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 13:41:59.616752 [CA 0] Center 36 (6~67) winsize 62
756 13:41:59.620257 [CA 1] Center 36 (6~67) winsize 62
757 13:41:59.623309 [CA 2] Center 34 (4~65) winsize 62
758 13:41:59.626364 [CA 3] Center 34 (4~64) winsize 61
759 13:41:59.630204 [CA 4] Center 33 (2~64) winsize 63
760 13:41:59.633153 [CA 5] Center 32 (2~62) winsize 61
761 13:41:59.633239
762 13:41:59.636702 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 13:41:59.636815
764 13:41:59.639634 [CATrainingPosCal] consider 1 rank data
765 13:41:59.643159 u2DelayCellTimex100 = 270/100 ps
766 13:41:59.646463 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
767 13:41:59.650062 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
768 13:41:59.657047 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
769 13:41:59.660127 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
770 13:41:59.663030 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
771 13:41:59.666529 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
772 13:41:59.666655
773 13:41:59.669832 CA PerBit enable=1, Macro0, CA PI delay=32
774 13:41:59.669924
775 13:41:59.673128 [CBTSetCACLKResult] CA Dly = 32
776 13:41:59.673219 CS Dly: 4 (0~35)
777 13:41:59.676850 ==
778 13:41:59.676941 Dram Type= 6, Freq= 0, CH_0, rank 1
779 13:41:59.683205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 13:41:59.683293 ==
781 13:41:59.686646 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 13:41:59.693377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 13:41:59.702901 [CA 0] Center 36 (6~67) winsize 62
784 13:41:59.706035 [CA 1] Center 36 (6~67) winsize 62
785 13:41:59.709898 [CA 2] Center 34 (4~65) winsize 62
786 13:41:59.713152 [CA 3] Center 34 (4~65) winsize 62
787 13:41:59.716127 [CA 4] Center 33 (3~64) winsize 62
788 13:41:59.719870 [CA 5] Center 32 (2~63) winsize 62
789 13:41:59.719953
790 13:41:59.722926 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 13:41:59.723006
792 13:41:59.726656 [CATrainingPosCal] consider 2 rank data
793 13:41:59.729598 u2DelayCellTimex100 = 270/100 ps
794 13:41:59.733630 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
795 13:41:59.736252 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
796 13:41:59.743117 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
797 13:41:59.746317 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
798 13:41:59.749898 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
799 13:41:59.753621 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
800 13:41:59.753707
801 13:41:59.756478 CA PerBit enable=1, Macro0, CA PI delay=32
802 13:41:59.756565
803 13:41:59.760136 [CBTSetCACLKResult] CA Dly = 32
804 13:41:59.760256 CS Dly: 5 (0~37)
805 13:41:59.760327
806 13:41:59.763083 ----->DramcWriteLeveling(PI) begin...
807 13:41:59.767081 ==
808 13:41:59.767270 Dram Type= 6, Freq= 0, CH_0, rank 0
809 13:41:59.771158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 13:41:59.774758 ==
811 13:41:59.774926 Write leveling (Byte 0): 32 => 32
812 13:41:59.778676 Write leveling (Byte 1): 31 => 31
813 13:41:59.781700 DramcWriteLeveling(PI) end<-----
814 13:41:59.781805
815 13:41:59.781875 ==
816 13:41:59.785163 Dram Type= 6, Freq= 0, CH_0, rank 0
817 13:41:59.788746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 13:41:59.788852 ==
819 13:41:59.791904 [Gating] SW mode calibration
820 13:41:59.799624 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 13:41:59.803311 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 13:41:59.809743 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 13:41:59.813176 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 13:41:59.816698 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
825 13:41:59.823329 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 13:41:59.826446 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:41:59.829474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:41:59.836463 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:41:59.839439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:41:59.843221 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 13:41:59.849978 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:41:59.852762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:41:59.856712 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 13:41:59.863354 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 13:41:59.866240 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 13:41:59.869862 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 13:41:59.876598 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 13:41:59.879235 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 13:41:59.882739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 13:41:59.889763 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
841 13:41:59.892884 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 13:41:59.895885 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 13:41:59.902779 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:41:59.906290 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:41:59.909022 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:41:59.915694 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:41:59.919195 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:41:59.922618 0 9 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
849 13:41:59.925968 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
850 13:41:59.933078 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 13:41:59.935715 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 13:41:59.939076 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 13:41:59.945804 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 13:41:59.949621 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 13:41:59.952642 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
856 13:41:59.959563 0 10 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 1) (1 0)
857 13:41:59.962733 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:41:59.965873 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:41:59.972475 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:41:59.976166 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:41:59.979267 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:41:59.985840 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:41:59.989620 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
864 13:41:59.992698 0 11 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
865 13:41:59.996085 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
866 13:42:00.002967 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 13:42:00.005969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:42:00.009612 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 13:42:00.016486 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 13:42:00.019528 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 13:42:00.023088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 13:42:00.029560 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 13:42:00.032641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 13:42:00.036147 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:42:00.043316 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:42:00.046023 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:42:00.049528 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:42:00.056136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:42:00.059378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:42:00.063139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:42:00.069886 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:42:00.072841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:42:00.076559 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:42:00.079443 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 13:42:00.086322 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 13:42:00.089925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 13:42:00.093007 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 13:42:00.099729 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 13:42:00.102621 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 13:42:00.106195 Total UI for P1: 0, mck2ui 16
891 13:42:00.109847 best dqsien dly found for B0: ( 0, 14, 8)
892 13:42:00.112829 Total UI for P1: 0, mck2ui 16
893 13:42:00.115888 best dqsien dly found for B1: ( 0, 14, 10)
894 13:42:00.120270 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
895 13:42:00.124024 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
896 13:42:00.124130
897 13:42:00.126928 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
898 13:42:00.130453 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
899 13:42:00.134062 [Gating] SW calibration Done
900 13:42:00.134153 ==
901 13:42:00.136989 Dram Type= 6, Freq= 0, CH_0, rank 0
902 13:42:00.140632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 13:42:00.140717 ==
904 13:42:00.143817 RX Vref Scan: 0
905 13:42:00.143930
906 13:42:00.143996 RX Vref 0 -> 0, step: 1
907 13:42:00.147500
908 13:42:00.147583 RX Delay -130 -> 252, step: 16
909 13:42:00.154152 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
910 13:42:00.157057 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
911 13:42:00.160695 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 13:42:00.164165 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 13:42:00.166918 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
914 13:42:00.174447 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
915 13:42:00.177352 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
916 13:42:00.180621 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
917 13:42:00.184116 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
918 13:42:00.186903 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
919 13:42:00.190469 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
920 13:42:00.197203 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
921 13:42:00.200197 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
922 13:42:00.203982 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
923 13:42:00.207527 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
924 13:42:00.213682 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
925 13:42:00.213790 ==
926 13:42:00.217364 Dram Type= 6, Freq= 0, CH_0, rank 0
927 13:42:00.220331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 13:42:00.220459 ==
929 13:42:00.220554 DQS Delay:
930 13:42:00.223841 DQS0 = 0, DQS1 = 0
931 13:42:00.223948 DQM Delay:
932 13:42:00.227482 DQM0 = 91, DQM1 = 82
933 13:42:00.227597 DQ Delay:
934 13:42:00.230631 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
935 13:42:00.233414 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =109
936 13:42:00.237243 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
937 13:42:00.240854 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
938 13:42:00.240942
939 13:42:00.241015
940 13:42:00.241082 ==
941 13:42:00.243741 Dram Type= 6, Freq= 0, CH_0, rank 0
942 13:42:00.247400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 13:42:00.247531 ==
944 13:42:00.247656
945 13:42:00.250402
946 13:42:00.250486 TX Vref Scan disable
947 13:42:00.254400 == TX Byte 0 ==
948 13:42:00.257399 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
949 13:42:00.260377 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
950 13:42:00.264191 == TX Byte 1 ==
951 13:42:00.266928 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
952 13:42:00.270760 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
953 13:42:00.270844 ==
954 13:42:00.274220 Dram Type= 6, Freq= 0, CH_0, rank 0
955 13:42:00.280708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 13:42:00.280819 ==
957 13:42:00.291958 TX Vref=22, minBit 8, minWin=27, winSum=447
958 13:42:00.295482 TX Vref=24, minBit 8, minWin=27, winSum=450
959 13:42:00.298839 TX Vref=26, minBit 0, minWin=28, winSum=457
960 13:42:00.301696 TX Vref=28, minBit 0, minWin=28, winSum=457
961 13:42:00.305487 TX Vref=30, minBit 0, minWin=28, winSum=459
962 13:42:00.312175 TX Vref=32, minBit 5, minWin=28, winSum=456
963 13:42:00.315080 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
964 13:42:00.315190
965 13:42:00.318630 Final TX Range 1 Vref 30
966 13:42:00.318747
967 13:42:00.318856 ==
968 13:42:00.322398 Dram Type= 6, Freq= 0, CH_0, rank 0
969 13:42:00.325465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 13:42:00.325542 ==
971 13:42:00.325607
972 13:42:00.328453
973 13:42:00.328529 TX Vref Scan disable
974 13:42:00.332204 == TX Byte 0 ==
975 13:42:00.335022 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
976 13:42:00.338804 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
977 13:42:00.342278 == TX Byte 1 ==
978 13:42:00.345080 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
979 13:42:00.348885 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
980 13:42:00.348967
981 13:42:00.352540 [DATLAT]
982 13:42:00.352634 Freq=800, CH0 RK0
983 13:42:00.352704
984 13:42:00.355088 DATLAT Default: 0xa
985 13:42:00.355191 0, 0xFFFF, sum = 0
986 13:42:00.358756 1, 0xFFFF, sum = 0
987 13:42:00.358870 2, 0xFFFF, sum = 0
988 13:42:00.361829 3, 0xFFFF, sum = 0
989 13:42:00.361937 4, 0xFFFF, sum = 0
990 13:42:00.365720 5, 0xFFFF, sum = 0
991 13:42:00.365827 6, 0xFFFF, sum = 0
992 13:42:00.369216 7, 0xFFFF, sum = 0
993 13:42:00.369323 8, 0xFFFF, sum = 0
994 13:42:00.372260 9, 0x0, sum = 1
995 13:42:00.372396 10, 0x0, sum = 2
996 13:42:00.375447 11, 0x0, sum = 3
997 13:42:00.375553 12, 0x0, sum = 4
998 13:42:00.379090 best_step = 10
999 13:42:00.379195
1000 13:42:00.379296 ==
1001 13:42:00.381998 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 13:42:00.385613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 13:42:00.385720 ==
1004 13:42:00.389301 RX Vref Scan: 1
1005 13:42:00.389379
1006 13:42:00.389465 Set Vref Range= 32 -> 127
1007 13:42:00.389576
1008 13:42:00.392069 RX Vref 32 -> 127, step: 1
1009 13:42:00.392170
1010 13:42:00.395849 RX Delay -79 -> 252, step: 8
1011 13:42:00.395956
1012 13:42:00.398871 Set Vref, RX VrefLevel [Byte0]: 32
1013 13:42:00.402607 [Byte1]: 32
1014 13:42:00.402710
1015 13:42:00.405489 Set Vref, RX VrefLevel [Byte0]: 33
1016 13:42:00.409102 [Byte1]: 33
1017 13:42:00.412489
1018 13:42:00.412607 Set Vref, RX VrefLevel [Byte0]: 34
1019 13:42:00.415451 [Byte1]: 34
1020 13:42:00.419955
1021 13:42:00.420059 Set Vref, RX VrefLevel [Byte0]: 35
1022 13:42:00.423124 [Byte1]: 35
1023 13:42:00.427664
1024 13:42:00.427769 Set Vref, RX VrefLevel [Byte0]: 36
1025 13:42:00.430753 [Byte1]: 36
1026 13:42:00.435212
1027 13:42:00.435316 Set Vref, RX VrefLevel [Byte0]: 37
1028 13:42:00.438111 [Byte1]: 37
1029 13:42:00.442637
1030 13:42:00.442741 Set Vref, RX VrefLevel [Byte0]: 38
1031 13:42:00.445674 [Byte1]: 38
1032 13:42:00.450105
1033 13:42:00.450188 Set Vref, RX VrefLevel [Byte0]: 39
1034 13:42:00.453706 [Byte1]: 39
1035 13:42:00.457562
1036 13:42:00.457642 Set Vref, RX VrefLevel [Byte0]: 40
1037 13:42:00.461229 [Byte1]: 40
1038 13:42:00.465135
1039 13:42:00.465216 Set Vref, RX VrefLevel [Byte0]: 41
1040 13:42:00.468828 [Byte1]: 41
1041 13:42:00.472589
1042 13:42:00.472670 Set Vref, RX VrefLevel [Byte0]: 42
1043 13:42:00.475671 [Byte1]: 42
1044 13:42:00.480191
1045 13:42:00.480299 Set Vref, RX VrefLevel [Byte0]: 43
1046 13:42:00.483333 [Byte1]: 43
1047 13:42:00.487798
1048 13:42:00.487880 Set Vref, RX VrefLevel [Byte0]: 44
1049 13:42:00.490684 [Byte1]: 44
1050 13:42:00.495235
1051 13:42:00.495337 Set Vref, RX VrefLevel [Byte0]: 45
1052 13:42:00.498678 [Byte1]: 45
1053 13:42:00.503018
1054 13:42:00.503123 Set Vref, RX VrefLevel [Byte0]: 46
1055 13:42:00.505866 [Byte1]: 46
1056 13:42:00.510453
1057 13:42:00.510554 Set Vref, RX VrefLevel [Byte0]: 47
1058 13:42:00.513505 [Byte1]: 47
1059 13:42:00.517873
1060 13:42:00.517971 Set Vref, RX VrefLevel [Byte0]: 48
1061 13:42:00.521498 [Byte1]: 48
1062 13:42:00.525083
1063 13:42:00.525172 Set Vref, RX VrefLevel [Byte0]: 49
1064 13:42:00.528434 [Byte1]: 49
1065 13:42:00.532725
1066 13:42:00.532828 Set Vref, RX VrefLevel [Byte0]: 50
1067 13:42:00.536200 [Byte1]: 50
1068 13:42:00.540978
1069 13:42:00.541062 Set Vref, RX VrefLevel [Byte0]: 51
1070 13:42:00.543910 [Byte1]: 51
1071 13:42:00.548262
1072 13:42:00.548406 Set Vref, RX VrefLevel [Byte0]: 52
1073 13:42:00.551324 [Byte1]: 52
1074 13:42:00.555759
1075 13:42:00.555840 Set Vref, RX VrefLevel [Byte0]: 53
1076 13:42:00.558625 [Byte1]: 53
1077 13:42:00.563045
1078 13:42:00.563125 Set Vref, RX VrefLevel [Byte0]: 54
1079 13:42:00.566860 [Byte1]: 54
1080 13:42:00.570936
1081 13:42:00.571090 Set Vref, RX VrefLevel [Byte0]: 55
1082 13:42:00.573867 [Byte1]: 55
1083 13:42:00.578239
1084 13:42:00.578327 Set Vref, RX VrefLevel [Byte0]: 56
1085 13:42:00.581274 [Byte1]: 56
1086 13:42:00.585885
1087 13:42:00.585962 Set Vref, RX VrefLevel [Byte0]: 57
1088 13:42:00.588923 [Byte1]: 57
1089 13:42:00.593537
1090 13:42:00.593716 Set Vref, RX VrefLevel [Byte0]: 58
1091 13:42:00.596536 [Byte1]: 58
1092 13:42:00.601217
1093 13:42:00.601290 Set Vref, RX VrefLevel [Byte0]: 59
1094 13:42:00.604139 [Byte1]: 59
1095 13:42:00.608266
1096 13:42:00.608388 Set Vref, RX VrefLevel [Byte0]: 60
1097 13:42:00.611881 [Byte1]: 60
1098 13:42:00.616283
1099 13:42:00.616412 Set Vref, RX VrefLevel [Byte0]: 61
1100 13:42:00.619282 [Byte1]: 61
1101 13:42:00.623817
1102 13:42:00.623924 Set Vref, RX VrefLevel [Byte0]: 62
1103 13:42:00.626738 [Byte1]: 62
1104 13:42:00.631139
1105 13:42:00.631244 Set Vref, RX VrefLevel [Byte0]: 63
1106 13:42:00.634182 [Byte1]: 63
1107 13:42:00.638425
1108 13:42:00.638532 Set Vref, RX VrefLevel [Byte0]: 64
1109 13:42:00.642311 [Byte1]: 64
1110 13:42:00.646379
1111 13:42:00.646478 Set Vref, RX VrefLevel [Byte0]: 65
1112 13:42:00.649835 [Byte1]: 65
1113 13:42:00.653666
1114 13:42:00.653747 Set Vref, RX VrefLevel [Byte0]: 66
1115 13:42:00.656737 [Byte1]: 66
1116 13:42:00.661119
1117 13:42:00.661223 Set Vref, RX VrefLevel [Byte0]: 67
1118 13:42:00.664783 [Byte1]: 67
1119 13:42:00.669066
1120 13:42:00.669145 Set Vref, RX VrefLevel [Byte0]: 68
1121 13:42:00.672155 [Byte1]: 68
1122 13:42:00.676542
1123 13:42:00.676623 Set Vref, RX VrefLevel [Byte0]: 69
1124 13:42:00.679968 [Byte1]: 69
1125 13:42:00.684072
1126 13:42:00.684153 Set Vref, RX VrefLevel [Byte0]: 70
1127 13:42:00.686958 [Byte1]: 70
1128 13:42:00.691536
1129 13:42:00.691643 Set Vref, RX VrefLevel [Byte0]: 71
1130 13:42:00.694642 [Byte1]: 71
1131 13:42:00.699146
1132 13:42:00.699249 Set Vref, RX VrefLevel [Byte0]: 72
1133 13:42:00.702150 [Byte1]: 72
1134 13:42:00.706865
1135 13:42:00.706970 Set Vref, RX VrefLevel [Byte0]: 73
1136 13:42:00.709882 [Byte1]: 73
1137 13:42:00.714364
1138 13:42:00.714439 Set Vref, RX VrefLevel [Byte0]: 74
1139 13:42:00.717809 [Byte1]: 74
1140 13:42:00.721578
1141 13:42:00.721652 Set Vref, RX VrefLevel [Byte0]: 75
1142 13:42:00.725118 [Byte1]: 75
1143 13:42:00.729483
1144 13:42:00.729565 Set Vref, RX VrefLevel [Byte0]: 76
1145 13:42:00.732526 [Byte1]: 76
1146 13:42:00.737075
1147 13:42:00.737159 Set Vref, RX VrefLevel [Byte0]: 77
1148 13:42:00.739856 [Byte1]: 77
1149 13:42:00.744367
1150 13:42:00.744462 Final RX Vref Byte 0 = 53 to rank0
1151 13:42:00.748161 Final RX Vref Byte 1 = 62 to rank0
1152 13:42:00.750955 Final RX Vref Byte 0 = 53 to rank1
1153 13:42:00.754509 Final RX Vref Byte 1 = 62 to rank1==
1154 13:42:00.757947 Dram Type= 6, Freq= 0, CH_0, rank 0
1155 13:42:00.761619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 13:42:00.764376 ==
1157 13:42:00.764492 DQS Delay:
1158 13:42:00.764585 DQS0 = 0, DQS1 = 0
1159 13:42:00.767483 DQM Delay:
1160 13:42:00.767565 DQM0 = 91, DQM1 = 85
1161 13:42:00.771270 DQ Delay:
1162 13:42:00.774210 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1163 13:42:00.777861 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1164 13:42:00.777958 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1165 13:42:00.784683 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =92
1166 13:42:00.784792
1167 13:42:00.784884
1168 13:42:00.791086 [DQSOSCAuto] RK0, (LSB)MR18= 0x5046, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1169 13:42:00.794502 CH0 RK0: MR19=606, MR18=5046
1170 13:42:00.801382 CH0_RK0: MR19=0x606, MR18=0x5046, DQSOSC=389, MR23=63, INC=97, DEC=65
1171 13:42:00.801504
1172 13:42:00.804464 ----->DramcWriteLeveling(PI) begin...
1173 13:42:00.804559 ==
1174 13:42:00.808282 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 13:42:00.811362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 13:42:00.811445 ==
1177 13:42:00.814302 Write leveling (Byte 0): 32 => 32
1178 13:42:00.818076 Write leveling (Byte 1): 30 => 30
1179 13:42:00.821167 DramcWriteLeveling(PI) end<-----
1180 13:42:00.821250
1181 13:42:00.821330 ==
1182 13:42:00.824765 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 13:42:00.828170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 13:42:00.828308 ==
1185 13:42:00.831133 [Gating] SW mode calibration
1186 13:42:00.878473 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1187 13:42:00.878831 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1188 13:42:00.878975 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1189 13:42:00.879104 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 13:42:00.879210 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1191 13:42:00.879943 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:42:00.880254 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:42:00.880386 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:42:00.880450 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:42:00.880542 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:42:00.922859 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:42:00.923731 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 13:42:00.924031 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 13:42:00.924136 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 13:42:00.924215 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 13:42:00.924278 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 13:42:00.924358 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:42:00.924421 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:42:00.924479 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:42:00.924536 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1206 13:42:00.933803 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1207 13:42:00.934734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:42:00.937447 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:42:00.940330 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:42:00.943909 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:42:00.947482 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:42:00.954205 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:42:00.957230 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:42:00.960916 0 9 8 | B1->B0 | 2b2b 2b2b | 0 1 | (0 0) (1 1)
1215 13:42:00.967621 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 13:42:00.970711 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 13:42:00.974333 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 13:42:00.980701 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 13:42:00.984041 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 13:42:00.987673 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 13:42:00.994039 0 10 4 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 0)
1222 13:42:00.997584 0 10 8 | B1->B0 | 2525 2828 | 0 0 | (1 1) (0 1)
1223 13:42:01.000651 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:42:01.008117 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:42:01.011678 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:42:01.015596 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:42:01.019410 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:42:01.022586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:42:01.029424 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1230 13:42:01.033170 0 11 8 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (1 1)
1231 13:42:01.036379 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 13:42:01.040032 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 13:42:01.046439 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 13:42:01.050531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 13:42:01.053491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 13:42:01.059806 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 13:42:01.063238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 13:42:01.066826 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1239 13:42:01.073582 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 13:42:01.076655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 13:42:01.080320 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 13:42:01.083344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 13:42:01.090096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 13:42:01.093716 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 13:42:01.096746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 13:42:01.103384 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 13:42:01.107183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 13:42:01.110301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 13:42:01.116809 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 13:42:01.120397 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 13:42:01.124076 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 13:42:01.130847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:42:01.133871 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1254 13:42:01.137061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1255 13:42:01.144346 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 13:42:01.144433 Total UI for P1: 0, mck2ui 16
1257 13:42:01.147267 best dqsien dly found for B0: ( 0, 14, 6)
1258 13:42:01.150484 Total UI for P1: 0, mck2ui 16
1259 13:42:01.154111 best dqsien dly found for B1: ( 0, 14, 6)
1260 13:42:01.156861 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1261 13:42:01.163818 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1262 13:42:01.163930
1263 13:42:01.167256 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1264 13:42:01.170722 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1265 13:42:01.173427 [Gating] SW calibration Done
1266 13:42:01.173542 ==
1267 13:42:01.177007 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 13:42:01.180711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 13:42:01.180789 ==
1270 13:42:01.180854 RX Vref Scan: 0
1271 13:42:01.180915
1272 13:42:01.183459 RX Vref 0 -> 0, step: 1
1273 13:42:01.183538
1274 13:42:01.186767 RX Delay -130 -> 252, step: 16
1275 13:42:01.190361 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1276 13:42:01.193710 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1277 13:42:01.200287 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1278 13:42:01.204068 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1279 13:42:01.206964 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1280 13:42:01.210497 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1281 13:42:01.214181 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1282 13:42:01.220149 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1283 13:42:01.223787 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1284 13:42:01.227356 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1285 13:42:01.230252 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1286 13:42:01.233994 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1287 13:42:01.240375 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1288 13:42:01.244043 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1289 13:42:01.247166 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1290 13:42:01.250780 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1291 13:42:01.250867 ==
1292 13:42:01.253776 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 13:42:01.260770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 13:42:01.260856 ==
1295 13:42:01.260923 DQS Delay:
1296 13:42:01.260986 DQS0 = 0, DQS1 = 0
1297 13:42:01.263787 DQM Delay:
1298 13:42:01.263870 DQM0 = 90, DQM1 = 81
1299 13:42:01.267228 DQ Delay:
1300 13:42:01.270790 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1301 13:42:01.270875 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1302 13:42:01.273804 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1303 13:42:01.280361 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =77
1304 13:42:01.280447
1305 13:42:01.280512
1306 13:42:01.280574 ==
1307 13:42:01.284034 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 13:42:01.287368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 13:42:01.287463 ==
1310 13:42:01.287530
1311 13:42:01.287591
1312 13:42:01.290686 TX Vref Scan disable
1313 13:42:01.290769 == TX Byte 0 ==
1314 13:42:01.297121 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1315 13:42:01.300470 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1316 13:42:01.300601 == TX Byte 1 ==
1317 13:42:01.307023 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1318 13:42:01.310432 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1319 13:42:01.310517 ==
1320 13:42:01.313988 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 13:42:01.317500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 13:42:01.317615 ==
1323 13:42:01.331489 TX Vref=22, minBit 8, minWin=27, winSum=447
1324 13:42:01.334330 TX Vref=24, minBit 11, minWin=27, winSum=453
1325 13:42:01.338022 TX Vref=26, minBit 11, minWin=27, winSum=455
1326 13:42:01.341122 TX Vref=28, minBit 5, minWin=28, winSum=458
1327 13:42:01.344918 TX Vref=30, minBit 7, minWin=28, winSum=460
1328 13:42:01.352414 TX Vref=32, minBit 4, minWin=28, winSum=457
1329 13:42:01.354403 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 30
1330 13:42:01.354539
1331 13:42:01.358204 Final TX Range 1 Vref 30
1332 13:42:01.358323
1333 13:42:01.358417 ==
1334 13:42:01.361419 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 13:42:01.364280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 13:42:01.364400 ==
1337 13:42:01.364496
1338 13:42:01.368212
1339 13:42:01.368331 TX Vref Scan disable
1340 13:42:01.371099 == TX Byte 0 ==
1341 13:42:01.374572 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1342 13:42:01.378487 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1343 13:42:01.381515 == TX Byte 1 ==
1344 13:42:01.384601 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1345 13:42:01.388288 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1346 13:42:01.391323
1347 13:42:01.391431 [DATLAT]
1348 13:42:01.391535 Freq=800, CH0 RK1
1349 13:42:01.391631
1350 13:42:01.394829 DATLAT Default: 0xa
1351 13:42:01.394944 0, 0xFFFF, sum = 0
1352 13:42:01.398428 1, 0xFFFF, sum = 0
1353 13:42:01.398537 2, 0xFFFF, sum = 0
1354 13:42:01.401137 3, 0xFFFF, sum = 0
1355 13:42:01.401233 4, 0xFFFF, sum = 0
1356 13:42:01.404622 5, 0xFFFF, sum = 0
1357 13:42:01.404730 6, 0xFFFF, sum = 0
1358 13:42:01.418299 7, 0xFFFF, sum = 0
1359 13:42:01.418415 8, 0xFFFF, sum = 0
1360 13:42:01.418514 9, 0x0, sum = 1
1361 13:42:01.418610 10, 0x0, sum = 2
1362 13:42:01.418702 11, 0x0, sum = 3
1363 13:42:01.418791 12, 0x0, sum = 4
1364 13:42:01.419070 best_step = 10
1365 13:42:01.419173
1366 13:42:01.419277 ==
1367 13:42:01.421652 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 13:42:01.424801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 13:42:01.424906 ==
1370 13:42:01.427863 RX Vref Scan: 0
1371 13:42:01.427968
1372 13:42:01.428063 RX Vref 0 -> 0, step: 1
1373 13:42:01.428159
1374 13:42:01.431546 RX Delay -79 -> 252, step: 8
1375 13:42:01.437726 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1376 13:42:01.441449 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1377 13:42:01.444565 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1378 13:42:01.447888 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1379 13:42:01.451557 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1380 13:42:01.457894 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1381 13:42:01.461546 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1382 13:42:01.464499 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1383 13:42:01.468245 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1384 13:42:01.471115 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1385 13:42:01.474765 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1386 13:42:01.481877 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1387 13:42:01.484794 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1388 13:42:01.488451 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1389 13:42:01.491446 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1390 13:42:01.498455 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1391 13:42:01.498560 ==
1392 13:42:01.501298 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 13:42:01.504866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 13:42:01.504967 ==
1395 13:42:01.505060 DQS Delay:
1396 13:42:01.508503 DQS0 = 0, DQS1 = 0
1397 13:42:01.508605 DQM Delay:
1398 13:42:01.511960 DQM0 = 92, DQM1 = 84
1399 13:42:01.512066 DQ Delay:
1400 13:42:01.514668 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =88
1401 13:42:01.518126 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1402 13:42:01.521816 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1403 13:42:01.524738 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1404 13:42:01.524843
1405 13:42:01.524936
1406 13:42:01.531390 [DQSOSCAuto] RK1, (LSB)MR18= 0x4213, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1407 13:42:01.534840 CH0 RK1: MR19=606, MR18=4213
1408 13:42:01.541489 CH0_RK1: MR19=0x606, MR18=0x4213, DQSOSC=393, MR23=63, INC=95, DEC=63
1409 13:42:01.545138 [RxdqsGatingPostProcess] freq 800
1410 13:42:01.551485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 13:42:01.551574 Pre-setting of DQS Precalculation
1412 13:42:01.558405 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 13:42:01.558510 ==
1414 13:42:01.561694 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 13:42:01.564812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 13:42:01.564895 ==
1417 13:42:01.571814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 13:42:01.578142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 13:42:01.586074 [CA 0] Center 36 (6~67) winsize 62
1420 13:42:01.589688 [CA 1] Center 36 (6~67) winsize 62
1421 13:42:01.593112 [CA 2] Center 34 (4~65) winsize 62
1422 13:42:01.596689 [CA 3] Center 35 (5~65) winsize 61
1423 13:42:01.599541 [CA 4] Center 35 (5~65) winsize 61
1424 13:42:01.603251 [CA 5] Center 34 (4~64) winsize 61
1425 13:42:01.603355
1426 13:42:01.606806 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1427 13:42:01.606910
1428 13:42:01.609729 [CATrainingPosCal] consider 1 rank data
1429 13:42:01.613462 u2DelayCellTimex100 = 270/100 ps
1430 13:42:01.616383 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 13:42:01.619832 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 13:42:01.623338 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 13:42:01.630206 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1434 13:42:01.633313 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1435 13:42:01.636853 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1436 13:42:01.636957
1437 13:42:01.640259 CA PerBit enable=1, Macro0, CA PI delay=34
1438 13:42:01.640394
1439 13:42:01.643192 [CBTSetCACLKResult] CA Dly = 34
1440 13:42:01.643270 CS Dly: 6 (0~37)
1441 13:42:01.643340 ==
1442 13:42:01.646600 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 13:42:01.653171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 13:42:01.653251 ==
1445 13:42:01.656917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 13:42:01.663263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 13:42:01.672519 [CA 0] Center 36 (6~67) winsize 62
1448 13:42:01.676259 [CA 1] Center 37 (6~68) winsize 63
1449 13:42:01.680229 [CA 2] Center 35 (5~66) winsize 62
1450 13:42:01.683552 [CA 3] Center 34 (4~65) winsize 62
1451 13:42:01.687829 [CA 4] Center 35 (4~66) winsize 63
1452 13:42:01.691686 [CA 5] Center 34 (4~65) winsize 62
1453 13:42:01.691821
1454 13:42:01.694889 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 13:42:01.694990
1456 13:42:01.699092 [CATrainingPosCal] consider 2 rank data
1457 13:42:01.699202 u2DelayCellTimex100 = 270/100 ps
1458 13:42:01.702629 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 13:42:01.706410 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 13:42:01.710480 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 13:42:01.713550 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1462 13:42:01.717268 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 13:42:01.720148 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 13:42:01.720248
1465 13:42:01.726814 CA PerBit enable=1, Macro0, CA PI delay=34
1466 13:42:01.726919
1467 13:42:01.730112 [CBTSetCACLKResult] CA Dly = 34
1468 13:42:01.730193 CS Dly: 7 (0~39)
1469 13:42:01.730254
1470 13:42:01.733696 ----->DramcWriteLeveling(PI) begin...
1471 13:42:01.733772 ==
1472 13:42:01.737167 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 13:42:01.740085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 13:42:01.740192 ==
1475 13:42:01.743435 Write leveling (Byte 0): 27 => 27
1476 13:42:01.747009 Write leveling (Byte 1): 27 => 27
1477 13:42:01.750711 DramcWriteLeveling(PI) end<-----
1478 13:42:01.750792
1479 13:42:01.750855 ==
1480 13:42:01.753613 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 13:42:01.760183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 13:42:01.760322 ==
1483 13:42:01.760437 [Gating] SW mode calibration
1484 13:42:01.770539 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 13:42:01.773429 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 13:42:01.776840 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1487 13:42:01.783342 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1488 13:42:01.787043 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:42:01.790787 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:42:01.797138 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:42:01.800591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:42:01.803615 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:42:01.810841 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:42:01.814027 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:42:01.817388 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 13:42:01.823603 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:42:01.826909 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 13:42:01.830875 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 13:42:01.834093 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 13:42:01.840913 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:42:01.843665 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:42:01.847131 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:42:01.853994 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1504 13:42:01.857154 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:42:01.860574 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:42:01.867328 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:42:01.870375 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:42:01.874156 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:42:01.880628 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:42:01.884100 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:42:01.887074 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1512 13:42:01.893577 0 9 8 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
1513 13:42:01.897215 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 13:42:01.900125 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 13:42:01.907339 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 13:42:01.910243 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 13:42:01.914089 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 13:42:01.920719 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1519 13:42:01.923487 0 10 4 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 1)
1520 13:42:01.927132 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1521 13:42:01.930278 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:42:01.937290 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:42:01.940671 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:42:01.943967 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:42:01.950670 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:42:01.953915 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:42:01.957249 0 11 4 | B1->B0 | 2929 3b3b | 1 0 | (0 0) (0 0)
1528 13:42:01.963628 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1529 13:42:01.967042 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 13:42:01.970447 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 13:42:01.977170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 13:42:01.980120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 13:42:01.983813 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 13:42:01.990128 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1535 13:42:01.993683 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1536 13:42:01.997359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 13:42:02.003818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 13:42:02.007495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 13:42:02.010457 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 13:42:02.017134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 13:42:02.020059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 13:42:02.023723 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 13:42:02.027331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 13:42:02.033661 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 13:42:02.037414 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 13:42:02.040301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 13:42:02.047477 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 13:42:02.050345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 13:42:02.053967 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 13:42:02.060273 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:42:02.063700 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1552 13:42:02.067231 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 13:42:02.070619 Total UI for P1: 0, mck2ui 16
1554 13:42:02.073938 best dqsien dly found for B0: ( 0, 14, 4)
1555 13:42:02.077394 Total UI for P1: 0, mck2ui 16
1556 13:42:02.080512 best dqsien dly found for B1: ( 0, 14, 4)
1557 13:42:02.083716 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1558 13:42:02.087635 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1559 13:42:02.087717
1560 13:42:02.090787 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1561 13:42:02.097195 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1562 13:42:02.097298 [Gating] SW calibration Done
1563 13:42:02.097377 ==
1564 13:42:02.100834 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 13:42:02.107259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 13:42:02.107341 ==
1567 13:42:02.107405 RX Vref Scan: 0
1568 13:42:02.107479
1569 13:42:02.110967 RX Vref 0 -> 0, step: 1
1570 13:42:02.111046
1571 13:42:02.114591 RX Delay -130 -> 252, step: 16
1572 13:42:02.117469 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1573 13:42:02.121220 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1574 13:42:02.124122 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1575 13:42:02.127705 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1576 13:42:02.134195 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1577 13:42:02.137725 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1578 13:42:02.140639 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1579 13:42:02.144261 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1580 13:42:02.148118 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1581 13:42:02.154613 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1582 13:42:02.157499 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1583 13:42:02.161141 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1584 13:42:02.164077 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1585 13:42:02.167627 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1586 13:42:02.174342 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1587 13:42:02.177304 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1588 13:42:02.177385 ==
1589 13:42:02.180927 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 13:42:02.184401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 13:42:02.184485 ==
1592 13:42:02.187745 DQS Delay:
1593 13:42:02.187843 DQS0 = 0, DQS1 = 0
1594 13:42:02.187907 DQM Delay:
1595 13:42:02.190772 DQM0 = 92, DQM1 = 87
1596 13:42:02.190853 DQ Delay:
1597 13:42:02.194338 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1598 13:42:02.197920 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1599 13:42:02.200724 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1600 13:42:02.204221 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1601 13:42:02.204307
1602 13:42:02.204411
1603 13:42:02.204473 ==
1604 13:42:02.207358 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 13:42:02.214288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 13:42:02.214371 ==
1607 13:42:02.214435
1608 13:42:02.214494
1609 13:42:02.214551 TX Vref Scan disable
1610 13:42:02.218043 == TX Byte 0 ==
1611 13:42:02.221222 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1612 13:42:02.227838 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1613 13:42:02.227920 == TX Byte 1 ==
1614 13:42:02.231459 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 13:42:02.234373 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 13:42:02.237989 ==
1617 13:42:02.241426 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 13:42:02.244284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 13:42:02.244389 ==
1620 13:42:02.257357 TX Vref=22, minBit 1, minWin=26, winSum=435
1621 13:42:02.261182 TX Vref=24, minBit 0, minWin=27, winSum=440
1622 13:42:02.263894 TX Vref=26, minBit 2, minWin=27, winSum=448
1623 13:42:02.267576 TX Vref=28, minBit 1, minWin=27, winSum=449
1624 13:42:02.270937 TX Vref=30, minBit 1, minWin=27, winSum=450
1625 13:42:02.274624 TX Vref=32, minBit 1, minWin=27, winSum=448
1626 13:42:02.281145 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1627 13:42:02.281226
1628 13:42:02.284114 Final TX Range 1 Vref 30
1629 13:42:02.284195
1630 13:42:02.284258 ==
1631 13:42:02.287223 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 13:42:02.290773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 13:42:02.290853 ==
1634 13:42:02.290916
1635 13:42:02.290975
1636 13:42:02.294402 TX Vref Scan disable
1637 13:42:02.297818 == TX Byte 0 ==
1638 13:42:02.300645 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1639 13:42:02.304090 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1640 13:42:02.307647 == TX Byte 1 ==
1641 13:42:02.311201 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1642 13:42:02.314071 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1643 13:42:02.314152
1644 13:42:02.314215 [DATLAT]
1645 13:42:02.317767 Freq=800, CH1 RK0
1646 13:42:02.317877
1647 13:42:02.320686 DATLAT Default: 0xa
1648 13:42:02.320766 0, 0xFFFF, sum = 0
1649 13:42:02.324004 1, 0xFFFF, sum = 0
1650 13:42:02.324085 2, 0xFFFF, sum = 0
1651 13:42:02.327348 3, 0xFFFF, sum = 0
1652 13:42:02.327429 4, 0xFFFF, sum = 0
1653 13:42:02.330548 5, 0xFFFF, sum = 0
1654 13:42:02.330630 6, 0xFFFF, sum = 0
1655 13:42:02.334302 7, 0xFFFF, sum = 0
1656 13:42:02.334383 8, 0xFFFF, sum = 0
1657 13:42:02.337513 9, 0x0, sum = 1
1658 13:42:02.337594 10, 0x0, sum = 2
1659 13:42:02.340710 11, 0x0, sum = 3
1660 13:42:02.340792 12, 0x0, sum = 4
1661 13:42:02.340859 best_step = 10
1662 13:42:02.344051
1663 13:42:02.344132 ==
1664 13:42:02.347504 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 13:42:02.351310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 13:42:02.351393 ==
1667 13:42:02.351459 RX Vref Scan: 1
1668 13:42:02.351519
1669 13:42:02.354305 Set Vref Range= 32 -> 127
1670 13:42:02.354386
1671 13:42:02.357926 RX Vref 32 -> 127, step: 1
1672 13:42:02.358008
1673 13:42:02.360835 RX Delay -79 -> 252, step: 8
1674 13:42:02.360916
1675 13:42:02.364379 Set Vref, RX VrefLevel [Byte0]: 32
1676 13:42:02.367382 [Byte1]: 32
1677 13:42:02.367464
1678 13:42:02.371079 Set Vref, RX VrefLevel [Byte0]: 33
1679 13:42:02.374621 [Byte1]: 33
1680 13:42:02.374711
1681 13:42:02.377417 Set Vref, RX VrefLevel [Byte0]: 34
1682 13:42:02.380865 [Byte1]: 34
1683 13:42:02.384552
1684 13:42:02.384632 Set Vref, RX VrefLevel [Byte0]: 35
1685 13:42:02.387534 [Byte1]: 35
1686 13:42:02.391961
1687 13:42:02.392043 Set Vref, RX VrefLevel [Byte0]: 36
1688 13:42:02.395535 [Byte1]: 36
1689 13:42:02.399077
1690 13:42:02.399158 Set Vref, RX VrefLevel [Byte0]: 37
1691 13:42:02.402628 [Byte1]: 37
1692 13:42:02.407074
1693 13:42:02.407155 Set Vref, RX VrefLevel [Byte0]: 38
1694 13:42:02.409965 [Byte1]: 38
1695 13:42:02.414196
1696 13:42:02.414277 Set Vref, RX VrefLevel [Byte0]: 39
1697 13:42:02.417706 [Byte1]: 39
1698 13:42:02.422092
1699 13:42:02.422173 Set Vref, RX VrefLevel [Byte0]: 40
1700 13:42:02.425692 [Byte1]: 40
1701 13:42:02.429293
1702 13:42:02.429381 Set Vref, RX VrefLevel [Byte0]: 41
1703 13:42:02.433048 [Byte1]: 41
1704 13:42:02.437287
1705 13:42:02.437368 Set Vref, RX VrefLevel [Byte0]: 42
1706 13:42:02.440172 [Byte1]: 42
1707 13:42:02.444918
1708 13:42:02.444999 Set Vref, RX VrefLevel [Byte0]: 43
1709 13:42:02.447640 [Byte1]: 43
1710 13:42:02.452193
1711 13:42:02.452303 Set Vref, RX VrefLevel [Byte0]: 44
1712 13:42:02.455479 [Byte1]: 44
1713 13:42:02.460029
1714 13:42:02.460110 Set Vref, RX VrefLevel [Byte0]: 45
1715 13:42:02.463195 [Byte1]: 45
1716 13:42:02.467170
1717 13:42:02.467252 Set Vref, RX VrefLevel [Byte0]: 46
1718 13:42:02.470356 [Byte1]: 46
1719 13:42:02.474714
1720 13:42:02.474795 Set Vref, RX VrefLevel [Byte0]: 47
1721 13:42:02.478511 [Byte1]: 47
1722 13:42:02.482138
1723 13:42:02.482219 Set Vref, RX VrefLevel [Byte0]: 48
1724 13:42:02.485563 [Byte1]: 48
1725 13:42:02.489780
1726 13:42:02.489860 Set Vref, RX VrefLevel [Byte0]: 49
1727 13:42:02.493193 [Byte1]: 49
1728 13:42:02.497571
1729 13:42:02.497651 Set Vref, RX VrefLevel [Byte0]: 50
1730 13:42:02.500439 [Byte1]: 50
1731 13:42:02.504762
1732 13:42:02.504844 Set Vref, RX VrefLevel [Byte0]: 51
1733 13:42:02.508381 [Byte1]: 51
1734 13:42:02.512520
1735 13:42:02.512619 Set Vref, RX VrefLevel [Byte0]: 52
1736 13:42:02.516281 [Byte1]: 52
1737 13:42:02.519805
1738 13:42:02.519885 Set Vref, RX VrefLevel [Byte0]: 53
1739 13:42:02.523316 [Byte1]: 53
1740 13:42:02.527435
1741 13:42:02.527518 Set Vref, RX VrefLevel [Byte0]: 54
1742 13:42:02.531206 [Byte1]: 54
1743 13:42:02.535576
1744 13:42:02.535688 Set Vref, RX VrefLevel [Byte0]: 55
1745 13:42:02.538478 [Byte1]: 55
1746 13:42:02.542808
1747 13:42:02.542890 Set Vref, RX VrefLevel [Byte0]: 56
1748 13:42:02.546397 [Byte1]: 56
1749 13:42:02.550011
1750 13:42:02.553740 Set Vref, RX VrefLevel [Byte0]: 57
1751 13:42:02.556641 [Byte1]: 57
1752 13:42:02.556722
1753 13:42:02.560242 Set Vref, RX VrefLevel [Byte0]: 58
1754 13:42:02.563758 [Byte1]: 58
1755 13:42:02.563840
1756 13:42:02.567245 Set Vref, RX VrefLevel [Byte0]: 59
1757 13:42:02.569981 [Byte1]: 59
1758 13:42:02.570067
1759 13:42:02.573464 Set Vref, RX VrefLevel [Byte0]: 60
1760 13:42:02.576817 [Byte1]: 60
1761 13:42:02.580806
1762 13:42:02.580914 Set Vref, RX VrefLevel [Byte0]: 61
1763 13:42:02.583867 [Byte1]: 61
1764 13:42:02.587787
1765 13:42:02.587870 Set Vref, RX VrefLevel [Byte0]: 62
1766 13:42:02.591406 [Byte1]: 62
1767 13:42:02.595872
1768 13:42:02.595970 Set Vref, RX VrefLevel [Byte0]: 63
1769 13:42:02.598567 [Byte1]: 63
1770 13:42:02.602837
1771 13:42:02.602965 Set Vref, RX VrefLevel [Byte0]: 64
1772 13:42:02.606511 [Byte1]: 64
1773 13:42:02.610905
1774 13:42:02.610988 Set Vref, RX VrefLevel [Byte0]: 65
1775 13:42:02.613709 [Byte1]: 65
1776 13:42:02.617951
1777 13:42:02.618033 Set Vref, RX VrefLevel [Byte0]: 66
1778 13:42:02.621516 [Byte1]: 66
1779 13:42:02.625996
1780 13:42:02.626077 Set Vref, RX VrefLevel [Byte0]: 67
1781 13:42:02.628903 [Byte1]: 67
1782 13:42:02.633085
1783 13:42:02.633172 Set Vref, RX VrefLevel [Byte0]: 68
1784 13:42:02.636347 [Byte1]: 68
1785 13:42:02.641005
1786 13:42:02.641093 Set Vref, RX VrefLevel [Byte0]: 69
1787 13:42:02.643729 [Byte1]: 69
1788 13:42:02.648731
1789 13:42:02.648809 Set Vref, RX VrefLevel [Byte0]: 70
1790 13:42:02.651660 [Byte1]: 70
1791 13:42:02.655973
1792 13:42:02.656047 Set Vref, RX VrefLevel [Byte0]: 71
1793 13:42:02.659134 [Byte1]: 71
1794 13:42:02.663526
1795 13:42:02.663600 Set Vref, RX VrefLevel [Byte0]: 72
1796 13:42:02.666445 [Byte1]: 72
1797 13:42:02.670697
1798 13:42:02.670774 Set Vref, RX VrefLevel [Byte0]: 73
1799 13:42:02.674329 [Byte1]: 73
1800 13:42:02.678844
1801 13:42:02.678920 Final RX Vref Byte 0 = 58 to rank0
1802 13:42:02.681667 Final RX Vref Byte 1 = 54 to rank0
1803 13:42:02.685403 Final RX Vref Byte 0 = 58 to rank1
1804 13:42:02.688275 Final RX Vref Byte 1 = 54 to rank1==
1805 13:42:02.691682 Dram Type= 6, Freq= 0, CH_1, rank 0
1806 13:42:02.695083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 13:42:02.698396 ==
1808 13:42:02.698502 DQS Delay:
1809 13:42:02.698597 DQS0 = 0, DQS1 = 0
1810 13:42:02.701667 DQM Delay:
1811 13:42:02.701744 DQM0 = 96, DQM1 = 90
1812 13:42:02.705427 DQ Delay:
1813 13:42:02.708856 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1814 13:42:02.712175 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1815 13:42:02.712278 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1816 13:42:02.718862 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1817 13:42:02.718985
1818 13:42:02.719079
1819 13:42:02.725238 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1820 13:42:02.728772 CH1 RK0: MR19=606, MR18=2E4B
1821 13:42:02.735412 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1822 13:42:02.735496
1823 13:42:02.738970 ----->DramcWriteLeveling(PI) begin...
1824 13:42:02.739055 ==
1825 13:42:02.741964 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 13:42:02.745687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 13:42:02.745772 ==
1828 13:42:02.748579 Write leveling (Byte 0): 26 => 26
1829 13:42:02.752091 Write leveling (Byte 1): 26 => 26
1830 13:42:02.755471 DramcWriteLeveling(PI) end<-----
1831 13:42:02.755554
1832 13:42:02.755619 ==
1833 13:42:02.759003 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 13:42:02.762052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 13:42:02.762135 ==
1836 13:42:02.765616 [Gating] SW mode calibration
1837 13:42:02.772234 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1838 13:42:02.778883 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1839 13:42:02.782547 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1840 13:42:02.785415 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1841 13:42:02.792643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1842 13:42:02.795526 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:42:02.799207 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:42:02.805684 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:42:02.809237 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:42:02.812665 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:42:02.818876 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:42:02.822419 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:42:02.825837 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:42:02.829129 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:42:02.835645 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:42:02.839000 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:42:02.842536 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:42:02.848739 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:42:02.852293 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 13:42:02.855257 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:42:02.862286 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:42:02.865515 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:42:02.869176 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:42:02.875759 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:42:02.879421 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:42:02.882306 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:42:02.889531 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:42:02.892359 0 9 4 | B1->B0 | 2525 2323 | 1 1 | (1 1) (1 1)
1865 13:42:02.896035 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1866 13:42:02.902586 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 13:42:02.906210 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 13:42:02.909255 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 13:42:02.912137 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 13:42:02.919393 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 13:42:02.922269 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 13:42:02.926005 0 10 4 | B1->B0 | 2b2b 2f2f | 1 1 | (1 0) (1 0)
1873 13:42:02.932570 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:42:02.936081 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:42:02.938928 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:42:02.946072 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:42:02.949544 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:42:02.952216 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:42:02.959116 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1880 13:42:02.962540 0 11 4 | B1->B0 | 3636 2f2f | 0 0 | (0 0) (0 0)
1881 13:42:02.965635 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1882 13:42:02.972731 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 13:42:02.976353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 13:42:02.979331 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 13:42:02.985846 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 13:42:02.989422 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 13:42:02.992329 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1888 13:42:02.995811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1889 13:42:03.002416 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1890 13:42:03.006108 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 13:42:03.009063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 13:42:03.016313 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 13:42:03.019306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 13:42:03.022899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 13:42:03.029515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 13:42:03.039153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 13:42:03.039344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 13:42:03.043025 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 13:42:03.045978 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 13:42:03.049508 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 13:42:03.056270 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 13:42:03.059328 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 13:42:03.062885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 13:42:03.069795 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1905 13:42:03.069879 Total UI for P1: 0, mck2ui 16
1906 13:42:03.072643 best dqsien dly found for B1: ( 0, 14, 2)
1907 13:42:03.079515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 13:42:03.082632 Total UI for P1: 0, mck2ui 16
1909 13:42:03.085845 best dqsien dly found for B0: ( 0, 14, 4)
1910 13:42:03.089474 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1911 13:42:03.092871 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1912 13:42:03.092953
1913 13:42:03.096321 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1914 13:42:03.099826 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1915 13:42:03.102741 [Gating] SW calibration Done
1916 13:42:03.102822 ==
1917 13:42:03.106338 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 13:42:03.109317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 13:42:03.109398 ==
1920 13:42:03.113025 RX Vref Scan: 0
1921 13:42:03.113106
1922 13:42:03.113170 RX Vref 0 -> 0, step: 1
1923 13:42:03.113230
1924 13:42:03.116129 RX Delay -130 -> 252, step: 16
1925 13:42:03.122804 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1926 13:42:03.126358 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1927 13:42:03.129255 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1928 13:42:03.132816 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1929 13:42:03.136510 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1930 13:42:03.139374 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1931 13:42:03.146622 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1932 13:42:03.149567 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1933 13:42:03.153106 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1934 13:42:03.155911 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1935 13:42:03.159688 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1936 13:42:03.166346 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1937 13:42:03.170005 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1938 13:42:03.173000 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1939 13:42:03.176578 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1940 13:42:03.179454 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1941 13:42:03.183045 ==
1942 13:42:03.186487 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 13:42:03.189232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 13:42:03.189314 ==
1945 13:42:03.189377 DQS Delay:
1946 13:42:03.192843 DQS0 = 0, DQS1 = 0
1947 13:42:03.192923 DQM Delay:
1948 13:42:03.196357 DQM0 = 92, DQM1 = 88
1949 13:42:03.196452 DQ Delay:
1950 13:42:03.199790 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1951 13:42:03.203116 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1952 13:42:03.206249 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1953 13:42:03.209467 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1954 13:42:03.209548
1955 13:42:03.209611
1956 13:42:03.209669 ==
1957 13:42:03.213053 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 13:42:03.216049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 13:42:03.216130 ==
1960 13:42:03.216192
1961 13:42:03.216251
1962 13:42:03.219651 TX Vref Scan disable
1963 13:42:03.223076 == TX Byte 0 ==
1964 13:42:03.226218 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1965 13:42:03.229741 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1966 13:42:03.233078 == TX Byte 1 ==
1967 13:42:03.236536 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1968 13:42:03.240166 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1969 13:42:03.240272 ==
1970 13:42:03.243143 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 13:42:03.246465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 13:42:03.249938 ==
1973 13:42:03.260684 TX Vref=22, minBit 1, minWin=26, winSum=436
1974 13:42:03.264277 TX Vref=24, minBit 0, minWin=27, winSum=438
1975 13:42:03.267184 TX Vref=26, minBit 0, minWin=27, winSum=446
1976 13:42:03.270935 TX Vref=28, minBit 0, minWin=27, winSum=444
1977 13:42:03.274585 TX Vref=30, minBit 0, minWin=27, winSum=447
1978 13:42:03.277575 TX Vref=32, minBit 0, minWin=27, winSum=446
1979 13:42:03.284115 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 30
1980 13:42:03.284196
1981 13:42:03.287680 Final TX Range 1 Vref 30
1982 13:42:03.287786
1983 13:42:03.287877 ==
1984 13:42:03.290626 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 13:42:03.294058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 13:42:03.294164 ==
1987 13:42:03.294256
1988 13:42:03.297648
1989 13:42:03.297727 TX Vref Scan disable
1990 13:42:03.300710 == TX Byte 0 ==
1991 13:42:03.304493 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 13:42:03.307425 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 13:42:03.311330 == TX Byte 1 ==
1994 13:42:03.314696 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1995 13:42:03.317562 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1996 13:42:03.317660
1997 13:42:03.321090 [DATLAT]
1998 13:42:03.321171 Freq=800, CH1 RK1
1999 13:42:03.321236
2000 13:42:03.324525 DATLAT Default: 0xa
2001 13:42:03.324633 0, 0xFFFF, sum = 0
2002 13:42:03.327818 1, 0xFFFF, sum = 0
2003 13:42:03.327926 2, 0xFFFF, sum = 0
2004 13:42:03.331468 3, 0xFFFF, sum = 0
2005 13:42:03.331578 4, 0xFFFF, sum = 0
2006 13:42:03.334835 5, 0xFFFF, sum = 0
2007 13:42:03.334961 6, 0xFFFF, sum = 0
2008 13:42:03.338059 7, 0xFFFF, sum = 0
2009 13:42:03.338144 8, 0xFFFF, sum = 0
2010 13:42:03.341324 9, 0x0, sum = 1
2011 13:42:03.341407 10, 0x0, sum = 2
2012 13:42:03.344643 11, 0x0, sum = 3
2013 13:42:03.344751 12, 0x0, sum = 4
2014 13:42:03.347814 best_step = 10
2015 13:42:03.347919
2016 13:42:03.348009 ==
2017 13:42:03.350920 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 13:42:03.354136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 13:42:03.354231 ==
2020 13:42:03.358179 RX Vref Scan: 0
2021 13:42:03.358260
2022 13:42:03.358324 RX Vref 0 -> 0, step: 1
2023 13:42:03.358383
2024 13:42:03.361479 RX Delay -79 -> 252, step: 8
2025 13:42:03.364755 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2026 13:42:03.370870 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2027 13:42:03.374544 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2028 13:42:03.378301 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2029 13:42:03.381334 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2030 13:42:03.385033 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2031 13:42:03.387902 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2032 13:42:03.395137 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2033 13:42:03.398080 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2034 13:42:03.401658 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2035 13:42:03.405122 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2036 13:42:03.408583 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2037 13:42:03.415177 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2038 13:42:03.418015 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2039 13:42:03.421534 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2040 13:42:03.425200 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2041 13:42:03.425300 ==
2042 13:42:03.428081 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 13:42:03.431464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 13:42:03.435171 ==
2045 13:42:03.435254 DQS Delay:
2046 13:42:03.435319 DQS0 = 0, DQS1 = 0
2047 13:42:03.438266 DQM Delay:
2048 13:42:03.438348 DQM0 = 97, DQM1 = 91
2049 13:42:03.441818 DQ Delay:
2050 13:42:03.441902 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2051 13:42:03.444809 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2052 13:42:03.448396 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2053 13:42:03.454715 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2054 13:42:03.454798
2055 13:42:03.454865
2056 13:42:03.461667 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2057 13:42:03.465203 CH1 RK1: MR19=606, MR18=460F
2058 13:42:03.471929 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2059 13:42:03.475229 [RxdqsGatingPostProcess] freq 800
2060 13:42:03.478569 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2061 13:42:03.481796 Pre-setting of DQS Precalculation
2062 13:42:03.488436 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2063 13:42:03.495200 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2064 13:42:03.501684 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2065 13:42:03.501768
2066 13:42:03.501844
2067 13:42:03.504704 [Calibration Summary] 1600 Mbps
2068 13:42:03.504810 CH 0, Rank 0
2069 13:42:03.508318 SW Impedance : PASS
2070 13:42:03.511908 DUTY Scan : NO K
2071 13:42:03.511991 ZQ Calibration : PASS
2072 13:42:03.514810 Jitter Meter : NO K
2073 13:42:03.514894 CBT Training : PASS
2074 13:42:03.518281 Write leveling : PASS
2075 13:42:03.521819 RX DQS gating : PASS
2076 13:42:03.521902 RX DQ/DQS(RDDQC) : PASS
2077 13:42:03.525378 TX DQ/DQS : PASS
2078 13:42:03.528206 RX DATLAT : PASS
2079 13:42:03.528289 RX DQ/DQS(Engine): PASS
2080 13:42:03.531686 TX OE : NO K
2081 13:42:03.531767 All Pass.
2082 13:42:03.531831
2083 13:42:03.535277 CH 0, Rank 1
2084 13:42:03.535358 SW Impedance : PASS
2085 13:42:03.538256 DUTY Scan : NO K
2086 13:42:03.541815 ZQ Calibration : PASS
2087 13:42:03.541896 Jitter Meter : NO K
2088 13:42:03.545379 CBT Training : PASS
2089 13:42:03.548228 Write leveling : PASS
2090 13:42:03.548333 RX DQS gating : PASS
2091 13:42:03.552022 RX DQ/DQS(RDDQC) : PASS
2092 13:42:03.554840 TX DQ/DQS : PASS
2093 13:42:03.554948 RX DATLAT : PASS
2094 13:42:03.558596 RX DQ/DQS(Engine): PASS
2095 13:42:03.558702 TX OE : NO K
2096 13:42:03.561274 All Pass.
2097 13:42:03.561355
2098 13:42:03.561417 CH 1, Rank 0
2099 13:42:03.564799 SW Impedance : PASS
2100 13:42:03.564879 DUTY Scan : NO K
2101 13:42:03.568567 ZQ Calibration : PASS
2102 13:42:03.571160 Jitter Meter : NO K
2103 13:42:03.571241 CBT Training : PASS
2104 13:42:03.574887 Write leveling : PASS
2105 13:42:03.578575 RX DQS gating : PASS
2106 13:42:03.578655 RX DQ/DQS(RDDQC) : PASS
2107 13:42:03.581471 TX DQ/DQS : PASS
2108 13:42:03.585125 RX DATLAT : PASS
2109 13:42:03.585206 RX DQ/DQS(Engine): PASS
2110 13:42:03.587906 TX OE : NO K
2111 13:42:03.587987 All Pass.
2112 13:42:03.588063
2113 13:42:03.591414 CH 1, Rank 1
2114 13:42:03.591494 SW Impedance : PASS
2115 13:42:03.594927 DUTY Scan : NO K
2116 13:42:03.598073 ZQ Calibration : PASS
2117 13:42:03.598154 Jitter Meter : NO K
2118 13:42:03.601287 CBT Training : PASS
2119 13:42:03.604544 Write leveling : PASS
2120 13:42:03.604624 RX DQS gating : PASS
2121 13:42:03.608271 RX DQ/DQS(RDDQC) : PASS
2122 13:42:03.608402 TX DQ/DQS : PASS
2123 13:42:03.611791 RX DATLAT : PASS
2124 13:42:03.614727 RX DQ/DQS(Engine): PASS
2125 13:42:03.614834 TX OE : NO K
2126 13:42:03.618179 All Pass.
2127 13:42:03.618259
2128 13:42:03.618322 DramC Write-DBI off
2129 13:42:03.621607 PER_BANK_REFRESH: Hybrid Mode
2130 13:42:03.624600 TX_TRACKING: ON
2131 13:42:03.628052 [GetDramInforAfterCalByMRR] Vendor 6.
2132 13:42:03.631073 [GetDramInforAfterCalByMRR] Revision 606.
2133 13:42:03.634730 [GetDramInforAfterCalByMRR] Revision 2 0.
2134 13:42:03.634836 MR0 0x3b3b
2135 13:42:03.634928 MR8 0x5151
2136 13:42:03.641691 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 13:42:03.641772
2138 13:42:03.641835 MR0 0x3b3b
2139 13:42:03.641899 MR8 0x5151
2140 13:42:03.644897 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 13:42:03.644978
2142 13:42:03.654746 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2143 13:42:03.658196 [FAST_K] Save calibration result to emmc
2144 13:42:03.661810 [FAST_K] Save calibration result to emmc
2145 13:42:03.664967 dram_init: config_dvfs: 1
2146 13:42:03.668449 dramc_set_vcore_voltage set vcore to 662500
2147 13:42:03.671359 Read voltage for 1200, 2
2148 13:42:03.671438 Vio18 = 0
2149 13:42:03.671502 Vcore = 662500
2150 13:42:03.674754 Vdram = 0
2151 13:42:03.674834 Vddq = 0
2152 13:42:03.674897 Vmddr = 0
2153 13:42:03.681383 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2154 13:42:03.684946 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2155 13:42:03.688015 MEM_TYPE=3, freq_sel=15
2156 13:42:03.691602 sv_algorithm_assistance_LP4_1600
2157 13:42:03.695152 ============ PULL DRAM RESETB DOWN ============
2158 13:42:03.698060 ========== PULL DRAM RESETB DOWN end =========
2159 13:42:03.704610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2160 13:42:03.708313 ===================================
2161 13:42:03.708461 LPDDR4 DRAM CONFIGURATION
2162 13:42:03.711501 ===================================
2163 13:42:03.714917 EX_ROW_EN[0] = 0x0
2164 13:42:03.718529 EX_ROW_EN[1] = 0x0
2165 13:42:03.718609 LP4Y_EN = 0x0
2166 13:42:03.721452 WORK_FSP = 0x0
2167 13:42:03.721533 WL = 0x4
2168 13:42:03.725127 RL = 0x4
2169 13:42:03.725207 BL = 0x2
2170 13:42:03.728784 RPST = 0x0
2171 13:42:03.728890 RD_PRE = 0x0
2172 13:42:03.731519 WR_PRE = 0x1
2173 13:42:03.731598 WR_PST = 0x0
2174 13:42:03.735217 DBI_WR = 0x0
2175 13:42:03.735297 DBI_RD = 0x0
2176 13:42:03.738150 OTF = 0x1
2177 13:42:03.741858 ===================================
2178 13:42:03.744858 ===================================
2179 13:42:03.744939 ANA top config
2180 13:42:03.748504 ===================================
2181 13:42:03.751991 DLL_ASYNC_EN = 0
2182 13:42:03.755510 ALL_SLAVE_EN = 0
2183 13:42:03.755592 NEW_RANK_MODE = 1
2184 13:42:03.758306 DLL_IDLE_MODE = 1
2185 13:42:03.761497 LP45_APHY_COMB_EN = 1
2186 13:42:03.765054 TX_ODT_DIS = 1
2187 13:42:03.768848 NEW_8X_MODE = 1
2188 13:42:03.771777 ===================================
2189 13:42:03.775257 ===================================
2190 13:42:03.775337 data_rate = 2400
2191 13:42:03.778699 CKR = 1
2192 13:42:03.782307 DQ_P2S_RATIO = 8
2193 13:42:03.785360 ===================================
2194 13:42:03.788189 CA_P2S_RATIO = 8
2195 13:42:03.791712 DQ_CA_OPEN = 0
2196 13:42:03.795322 DQ_SEMI_OPEN = 0
2197 13:42:03.795404 CA_SEMI_OPEN = 0
2198 13:42:03.798927 CA_FULL_RATE = 0
2199 13:42:03.801826 DQ_CKDIV4_EN = 0
2200 13:42:03.805459 CA_CKDIV4_EN = 0
2201 13:42:03.808305 CA_PREDIV_EN = 0
2202 13:42:03.811934 PH8_DLY = 17
2203 13:42:03.812041 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2204 13:42:03.814842 DQ_AAMCK_DIV = 4
2205 13:42:03.818573 CA_AAMCK_DIV = 4
2206 13:42:03.822063 CA_ADMCK_DIV = 4
2207 13:42:03.825577 DQ_TRACK_CA_EN = 0
2208 13:42:03.828851 CA_PICK = 1200
2209 13:42:03.828932 CA_MCKIO = 1200
2210 13:42:03.832333 MCKIO_SEMI = 0
2211 13:42:03.835210 PLL_FREQ = 2366
2212 13:42:03.838790 DQ_UI_PI_RATIO = 32
2213 13:42:03.841869 CA_UI_PI_RATIO = 0
2214 13:42:03.845445 ===================================
2215 13:42:03.848287 ===================================
2216 13:42:03.852109 memory_type:LPDDR4
2217 13:42:03.852189 GP_NUM : 10
2218 13:42:03.855075 SRAM_EN : 1
2219 13:42:03.855155 MD32_EN : 0
2220 13:42:03.858611 ===================================
2221 13:42:03.862439 [ANA_INIT] >>>>>>>>>>>>>>
2222 13:42:03.865260 <<<<<< [CONFIGURE PHASE]: ANA_TX
2223 13:42:03.868780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2224 13:42:03.872255 ===================================
2225 13:42:03.875168 data_rate = 2400,PCW = 0X5b00
2226 13:42:03.878864 ===================================
2227 13:42:03.881861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2228 13:42:03.885377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 13:42:03.892228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 13:42:03.895171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2231 13:42:03.898895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2232 13:42:03.902405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2233 13:42:03.905481 [ANA_INIT] flow start
2234 13:42:03.909219 [ANA_INIT] PLL >>>>>>>>
2235 13:42:03.909300 [ANA_INIT] PLL <<<<<<<<
2236 13:42:03.912105 [ANA_INIT] MIDPI >>>>>>>>
2237 13:42:03.915791 [ANA_INIT] MIDPI <<<<<<<<
2238 13:42:03.918724 [ANA_INIT] DLL >>>>>>>>
2239 13:42:03.918805 [ANA_INIT] DLL <<<<<<<<
2240 13:42:03.921822 [ANA_INIT] flow end
2241 13:42:03.925545 ============ LP4 DIFF to SE enter ============
2242 13:42:03.928559 ============ LP4 DIFF to SE exit ============
2243 13:42:03.932222 [ANA_INIT] <<<<<<<<<<<<<
2244 13:42:03.935730 [Flow] Enable top DCM control >>>>>
2245 13:42:03.939185 [Flow] Enable top DCM control <<<<<
2246 13:42:03.942532 Enable DLL master slave shuffle
2247 13:42:03.945729 ==============================================================
2248 13:42:03.949030 Gating Mode config
2249 13:42:03.955350 ==============================================================
2250 13:42:03.955430 Config description:
2251 13:42:03.965284 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2252 13:42:03.972629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2253 13:42:03.975448 SELPH_MODE 0: By rank 1: By Phase
2254 13:42:03.982100 ==============================================================
2255 13:42:03.985588 GAT_TRACK_EN = 1
2256 13:42:03.989321 RX_GATING_MODE = 2
2257 13:42:03.992332 RX_GATING_TRACK_MODE = 2
2258 13:42:03.995993 SELPH_MODE = 1
2259 13:42:03.998741 PICG_EARLY_EN = 1
2260 13:42:04.002143 VALID_LAT_VALUE = 1
2261 13:42:04.005499 ==============================================================
2262 13:42:04.008736 Enter into Gating configuration >>>>
2263 13:42:04.012413 Exit from Gating configuration <<<<
2264 13:42:04.016102 Enter into DVFS_PRE_config >>>>>
2265 13:42:04.025487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2266 13:42:04.029335 Exit from DVFS_PRE_config <<<<<
2267 13:42:04.032862 Enter into PICG configuration >>>>
2268 13:42:04.035904 Exit from PICG configuration <<<<
2269 13:42:04.039560 [RX_INPUT] configuration >>>>>
2270 13:42:04.042446 [RX_INPUT] configuration <<<<<
2271 13:42:04.046130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2272 13:42:04.052652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2273 13:42:04.059138 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2274 13:42:04.066189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2275 13:42:04.072414 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2276 13:42:04.079205 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2277 13:42:04.082857 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2278 13:42:04.085812 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2279 13:42:04.089165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2280 13:42:04.092742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2281 13:42:04.099218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2282 13:42:04.102826 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 13:42:04.106400 ===================================
2284 13:42:04.109148 LPDDR4 DRAM CONFIGURATION
2285 13:42:04.112684 ===================================
2286 13:42:04.112766 EX_ROW_EN[0] = 0x0
2287 13:42:04.116237 EX_ROW_EN[1] = 0x0
2288 13:42:04.116322 LP4Y_EN = 0x0
2289 13:42:04.119556 WORK_FSP = 0x0
2290 13:42:04.119637 WL = 0x4
2291 13:42:04.122914 RL = 0x4
2292 13:42:04.122996 BL = 0x2
2293 13:42:04.126255 RPST = 0x0
2294 13:42:04.126337 RD_PRE = 0x0
2295 13:42:04.129888 WR_PRE = 0x1
2296 13:42:04.129972 WR_PST = 0x0
2297 13:42:04.132831 DBI_WR = 0x0
2298 13:42:04.132914 DBI_RD = 0x0
2299 13:42:04.136417 OTF = 0x1
2300 13:42:04.139396 ===================================
2301 13:42:04.143059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2302 13:42:04.146608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2303 13:42:04.153293 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 13:42:04.156058 ===================================
2305 13:42:04.156136 LPDDR4 DRAM CONFIGURATION
2306 13:42:04.159770 ===================================
2307 13:42:04.162896 EX_ROW_EN[0] = 0x10
2308 13:42:04.166464 EX_ROW_EN[1] = 0x0
2309 13:42:04.166547 LP4Y_EN = 0x0
2310 13:42:04.169932 WORK_FSP = 0x0
2311 13:42:04.170042 WL = 0x4
2312 13:42:04.172935 RL = 0x4
2313 13:42:04.173021 BL = 0x2
2314 13:42:04.176573 RPST = 0x0
2315 13:42:04.176684 RD_PRE = 0x0
2316 13:42:04.179521 WR_PRE = 0x1
2317 13:42:04.179605 WR_PST = 0x0
2318 13:42:04.182899 DBI_WR = 0x0
2319 13:42:04.182978 DBI_RD = 0x0
2320 13:42:04.186497 OTF = 0x1
2321 13:42:04.189393 ===================================
2322 13:42:04.196746 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2323 13:42:04.196830 ==
2324 13:42:04.199885 Dram Type= 6, Freq= 0, CH_0, rank 0
2325 13:42:04.203486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2326 13:42:04.203596 ==
2327 13:42:04.206559 [Duty_Offset_Calibration]
2328 13:42:04.206642 B0:2 B1:1 CA:1
2329 13:42:04.206708
2330 13:42:04.209977 [DutyScan_Calibration_Flow] k_type=0
2331 13:42:04.219218
2332 13:42:04.219332 ==CLK 0==
2333 13:42:04.222835 Final CLK duty delay cell = 0
2334 13:42:04.226357 [0] MAX Duty = 5187%(X100), DQS PI = 24
2335 13:42:04.229869 [0] MIN Duty = 4875%(X100), DQS PI = 0
2336 13:42:04.229952 [0] AVG Duty = 5031%(X100)
2337 13:42:04.230019
2338 13:42:04.232848 CH0 CLK Duty spec in!! Max-Min= 312%
2339 13:42:04.239938 [DutyScan_Calibration_Flow] ====Done====
2340 13:42:04.240021
2341 13:42:04.242724 [DutyScan_Calibration_Flow] k_type=1
2342 13:42:04.257987
2343 13:42:04.258072 ==DQS 0 ==
2344 13:42:04.261608 Final DQS duty delay cell = -4
2345 13:42:04.264626 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2346 13:42:04.268192 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2347 13:42:04.271093 [-4] AVG Duty = 4937%(X100)
2348 13:42:04.271176
2349 13:42:04.271242 ==DQS 1 ==
2350 13:42:04.274769 Final DQS duty delay cell = 0
2351 13:42:04.278255 [0] MAX Duty = 5187%(X100), DQS PI = 62
2352 13:42:04.281218 [0] MIN Duty = 5000%(X100), DQS PI = 34
2353 13:42:04.284960 [0] AVG Duty = 5093%(X100)
2354 13:42:04.285069
2355 13:42:04.288468 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2356 13:42:04.288577
2357 13:42:04.291329 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2358 13:42:04.294915 [DutyScan_Calibration_Flow] ====Done====
2359 13:42:04.294999
2360 13:42:04.297778 [DutyScan_Calibration_Flow] k_type=3
2361 13:42:04.314609
2362 13:42:04.314720 ==DQM 0 ==
2363 13:42:04.318039 Final DQM duty delay cell = 0
2364 13:42:04.322050 [0] MAX Duty = 5156%(X100), DQS PI = 30
2365 13:42:04.325481 [0] MIN Duty = 4906%(X100), DQS PI = 52
2366 13:42:04.325591 [0] AVG Duty = 5031%(X100)
2367 13:42:04.328083
2368 13:42:04.328192 ==DQM 1 ==
2369 13:42:04.331502 Final DQM duty delay cell = 0
2370 13:42:04.334722 [0] MAX Duty = 5093%(X100), DQS PI = 0
2371 13:42:04.338574 [0] MIN Duty = 5031%(X100), DQS PI = 14
2372 13:42:04.338677 [0] AVG Duty = 5062%(X100)
2373 13:42:04.341666
2374 13:42:04.344769 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2375 13:42:04.344878
2376 13:42:04.348622 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2377 13:42:04.352103 [DutyScan_Calibration_Flow] ====Done====
2378 13:42:04.352207
2379 13:42:04.355356 [DutyScan_Calibration_Flow] k_type=2
2380 13:42:04.371553
2381 13:42:04.371665 ==DQ 0 ==
2382 13:42:04.374527 Final DQ duty delay cell = 0
2383 13:42:04.378073 [0] MAX Duty = 5031%(X100), DQS PI = 24
2384 13:42:04.381120 [0] MIN Duty = 4875%(X100), DQS PI = 62
2385 13:42:04.381230 [0] AVG Duty = 4953%(X100)
2386 13:42:04.384955
2387 13:42:04.385064 ==DQ 1 ==
2388 13:42:04.387799 Final DQ duty delay cell = 0
2389 13:42:04.391285 [0] MAX Duty = 5093%(X100), DQS PI = 24
2390 13:42:04.394772 [0] MIN Duty = 4907%(X100), DQS PI = 36
2391 13:42:04.394853 [0] AVG Duty = 5000%(X100)
2392 13:42:04.394917
2393 13:42:04.398386 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2394 13:42:04.401415
2395 13:42:04.404558 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2396 13:42:04.407979 [DutyScan_Calibration_Flow] ====Done====
2397 13:42:04.408095 ==
2398 13:42:04.411016 Dram Type= 6, Freq= 0, CH_1, rank 0
2399 13:42:04.414692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2400 13:42:04.414803 ==
2401 13:42:04.418156 [Duty_Offset_Calibration]
2402 13:42:04.418270 B0:1 B1:0 CA:0
2403 13:42:04.418383
2404 13:42:04.421067 [DutyScan_Calibration_Flow] k_type=0
2405 13:42:04.430585
2406 13:42:04.430692 ==CLK 0==
2407 13:42:04.434181 Final CLK duty delay cell = -4
2408 13:42:04.437109 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2409 13:42:04.440819 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2410 13:42:04.443752 [-4] AVG Duty = 4969%(X100)
2411 13:42:04.443837
2412 13:42:04.447199 CH1 CLK Duty spec in!! Max-Min= 124%
2413 13:42:04.450634 [DutyScan_Calibration_Flow] ====Done====
2414 13:42:04.450716
2415 13:42:04.453971 [DutyScan_Calibration_Flow] k_type=1
2416 13:42:04.470631
2417 13:42:04.470715 ==DQS 0 ==
2418 13:42:04.473527 Final DQS duty delay cell = 0
2419 13:42:04.477229 [0] MAX Duty = 5094%(X100), DQS PI = 26
2420 13:42:04.480355 [0] MIN Duty = 4875%(X100), DQS PI = 0
2421 13:42:04.480499 [0] AVG Duty = 4984%(X100)
2422 13:42:04.480611
2423 13:42:04.483734 ==DQS 1 ==
2424 13:42:04.487526 Final DQS duty delay cell = 0
2425 13:42:04.490434 [0] MAX Duty = 5218%(X100), DQS PI = 20
2426 13:42:04.493999 [0] MIN Duty = 4938%(X100), DQS PI = 12
2427 13:42:04.494081 [0] AVG Duty = 5078%(X100)
2428 13:42:04.494146
2429 13:42:04.497679 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2430 13:42:04.500509
2431 13:42:04.504133 CH1 DQS 1 Duty spec in!! Max-Min= 280%
2432 13:42:04.507659 [DutyScan_Calibration_Flow] ====Done====
2433 13:42:04.507757
2434 13:42:04.510609 [DutyScan_Calibration_Flow] k_type=3
2435 13:42:04.526577
2436 13:42:04.526664 ==DQM 0 ==
2437 13:42:04.530091 Final DQM duty delay cell = 0
2438 13:42:04.533747 [0] MAX Duty = 5156%(X100), DQS PI = 4
2439 13:42:04.536708 [0] MIN Duty = 5031%(X100), DQS PI = 0
2440 13:42:04.536790 [0] AVG Duty = 5093%(X100)
2441 13:42:04.540285
2442 13:42:04.540391 ==DQM 1 ==
2443 13:42:04.543745 Final DQM duty delay cell = 0
2444 13:42:04.546736 [0] MAX Duty = 5031%(X100), DQS PI = 16
2445 13:42:04.550335 [0] MIN Duty = 4907%(X100), DQS PI = 34
2446 13:42:04.550467 [0] AVG Duty = 4969%(X100)
2447 13:42:04.553281
2448 13:42:04.556769 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2449 13:42:04.556852
2450 13:42:04.560372 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2451 13:42:04.563209 [DutyScan_Calibration_Flow] ====Done====
2452 13:42:04.563292
2453 13:42:04.566730 [DutyScan_Calibration_Flow] k_type=2
2454 13:42:04.582854
2455 13:42:04.582965 ==DQ 0 ==
2456 13:42:04.585731 Final DQ duty delay cell = -4
2457 13:42:04.589343 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2458 13:42:04.592636 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2459 13:42:04.592745 [-4] AVG Duty = 4984%(X100)
2460 13:42:04.596814
2461 13:42:04.596930 ==DQ 1 ==
2462 13:42:04.599789 Final DQ duty delay cell = 0
2463 13:42:04.603049 [0] MAX Duty = 5125%(X100), DQS PI = 20
2464 13:42:04.606420 [0] MIN Duty = 4969%(X100), DQS PI = 12
2465 13:42:04.606538 [0] AVG Duty = 5047%(X100)
2466 13:42:04.606638
2467 13:42:04.609364 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2468 13:42:04.612808
2469 13:42:04.616255 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2470 13:42:04.619750 [DutyScan_Calibration_Flow] ====Done====
2471 13:42:04.622678 nWR fixed to 30
2472 13:42:04.622784 [ModeRegInit_LP4] CH0 RK0
2473 13:42:04.626209 [ModeRegInit_LP4] CH0 RK1
2474 13:42:04.629224 [ModeRegInit_LP4] CH1 RK0
2475 13:42:04.629332 [ModeRegInit_LP4] CH1 RK1
2476 13:42:04.632678 match AC timing 7
2477 13:42:04.636330 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2478 13:42:04.639365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2479 13:42:04.646542 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2480 13:42:04.649360 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2481 13:42:04.656647 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2482 13:42:04.656735 ==
2483 13:42:04.659606 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 13:42:04.663235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 13:42:04.663348 ==
2486 13:42:04.669907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 13:42:04.672824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 13:42:04.682648 [CA 0] Center 39 (8~70) winsize 63
2489 13:42:04.686201 [CA 1] Center 39 (8~70) winsize 63
2490 13:42:04.689844 [CA 2] Center 35 (5~66) winsize 62
2491 13:42:04.692657 [CA 3] Center 34 (4~65) winsize 62
2492 13:42:04.696478 [CA 4] Center 33 (3~64) winsize 62
2493 13:42:04.699334 [CA 5] Center 32 (3~62) winsize 60
2494 13:42:04.699446
2495 13:42:04.702843 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2496 13:42:04.702947
2497 13:42:04.706313 [CATrainingPosCal] consider 1 rank data
2498 13:42:04.709845 u2DelayCellTimex100 = 270/100 ps
2499 13:42:04.712650 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2500 13:42:04.716630 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2501 13:42:04.722766 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2502 13:42:04.726650 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2503 13:42:04.730005 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2504 13:42:04.733492 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2505 13:42:04.733605
2506 13:42:04.736710 CA PerBit enable=1, Macro0, CA PI delay=32
2507 13:42:04.736818
2508 13:42:04.739951 [CBTSetCACLKResult] CA Dly = 32
2509 13:42:04.740064 CS Dly: 6 (0~37)
2510 13:42:04.740161 ==
2511 13:42:04.743490 Dram Type= 6, Freq= 0, CH_0, rank 1
2512 13:42:04.749494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 13:42:04.749606 ==
2514 13:42:04.753028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 13:42:04.759533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2516 13:42:04.768438 [CA 0] Center 38 (8~69) winsize 62
2517 13:42:04.772076 [CA 1] Center 38 (8~69) winsize 62
2518 13:42:04.775036 [CA 2] Center 35 (4~66) winsize 63
2519 13:42:04.778605 [CA 3] Center 34 (4~65) winsize 62
2520 13:42:04.782463 [CA 4] Center 33 (3~64) winsize 62
2521 13:42:04.784974 [CA 5] Center 32 (3~62) winsize 60
2522 13:42:04.785084
2523 13:42:04.788651 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 13:42:04.788764
2525 13:42:04.792082 [CATrainingPosCal] consider 2 rank data
2526 13:42:04.795134 u2DelayCellTimex100 = 270/100 ps
2527 13:42:04.798510 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2528 13:42:04.802155 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2529 13:42:04.808746 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2530 13:42:04.812202 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2531 13:42:04.815211 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2532 13:42:04.818761 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2533 13:42:04.818869
2534 13:42:04.822443 CA PerBit enable=1, Macro0, CA PI delay=32
2535 13:42:04.822551
2536 13:42:04.825406 [CBTSetCACLKResult] CA Dly = 32
2537 13:42:04.825519 CS Dly: 6 (0~38)
2538 13:42:04.825629
2539 13:42:04.829119 ----->DramcWriteLeveling(PI) begin...
2540 13:42:04.831932 ==
2541 13:42:04.832038 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 13:42:04.838793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 13:42:04.838904 ==
2544 13:42:04.842128 Write leveling (Byte 0): 34 => 34
2545 13:42:04.845513 Write leveling (Byte 1): 27 => 27
2546 13:42:04.845628 DramcWriteLeveling(PI) end<-----
2547 13:42:04.848975
2548 13:42:04.849083 ==
2549 13:42:04.851736 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 13:42:04.855034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 13:42:04.855147 ==
2552 13:42:04.858388 [Gating] SW mode calibration
2553 13:42:04.865339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2554 13:42:04.868654 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2555 13:42:04.875107 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2556 13:42:04.878836 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2557 13:42:04.881736 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 13:42:04.889046 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 13:42:04.892045 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 13:42:04.895579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 13:42:04.902163 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2562 13:42:04.905901 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2563 13:42:04.908692 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2564 13:42:04.915309 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 13:42:04.918937 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 13:42:04.922432 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 13:42:04.926074 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 13:42:04.932625 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 13:42:04.935628 1 0 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
2570 13:42:04.939363 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2571 13:42:04.946010 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2572 13:42:04.948846 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 13:42:04.952191 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 13:42:04.959130 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 13:42:04.962003 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 13:42:04.965338 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 13:42:04.971974 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 13:42:04.975542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2579 13:42:04.978972 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2580 13:42:04.985701 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 13:42:04.988591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 13:42:04.992214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 13:42:04.998581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 13:42:05.002023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 13:42:05.005558 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 13:42:05.012001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 13:42:05.015692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 13:42:05.019336 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 13:42:05.022188 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 13:42:05.029439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 13:42:05.032198 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 13:42:05.035861 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 13:42:05.042439 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 13:42:05.045458 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2595 13:42:05.049111 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2596 13:42:05.052657 Total UI for P1: 0, mck2ui 16
2597 13:42:05.055609 best dqsien dly found for B0: ( 1, 3, 28)
2598 13:42:05.062106 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 13:42:05.062209 Total UI for P1: 0, mck2ui 16
2600 13:42:05.068936 best dqsien dly found for B1: ( 1, 4, 0)
2601 13:42:05.072491 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2602 13:42:05.075933 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2603 13:42:05.076010
2604 13:42:05.079422 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2605 13:42:05.082166 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2606 13:42:05.085704 [Gating] SW calibration Done
2607 13:42:05.085812 ==
2608 13:42:05.089270 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 13:42:05.092601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 13:42:05.092680 ==
2611 13:42:05.095983 RX Vref Scan: 0
2612 13:42:05.096089
2613 13:42:05.096179 RX Vref 0 -> 0, step: 1
2614 13:42:05.096275
2615 13:42:05.099383 RX Delay -40 -> 252, step: 8
2616 13:42:05.102405 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2617 13:42:05.105835 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2618 13:42:05.112750 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2619 13:42:05.115993 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2620 13:42:05.119460 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2621 13:42:05.122484 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2622 13:42:05.126118 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2623 13:42:05.132360 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2624 13:42:05.136042 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2625 13:42:05.139847 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2626 13:42:05.142674 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2627 13:42:05.146335 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2628 13:42:05.152840 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2629 13:42:05.155726 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2630 13:42:05.159482 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2631 13:42:05.162420 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2632 13:42:05.162503 ==
2633 13:42:05.166104 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 13:42:05.172733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 13:42:05.172816 ==
2636 13:42:05.172881 DQS Delay:
2637 13:42:05.172943 DQS0 = 0, DQS1 = 0
2638 13:42:05.176466 DQM Delay:
2639 13:42:05.176552 DQM0 = 121, DQM1 = 113
2640 13:42:05.179750 DQ Delay:
2641 13:42:05.183110 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2642 13:42:05.185810 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2643 13:42:05.189426 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2644 13:42:05.192525 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2645 13:42:05.192604
2646 13:42:05.192667
2647 13:42:05.192757 ==
2648 13:42:05.196014 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 13:42:05.199790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 13:42:05.199899 ==
2651 13:42:05.200020
2652 13:42:05.202730
2653 13:42:05.202810 TX Vref Scan disable
2654 13:42:05.206314 == TX Byte 0 ==
2655 13:42:05.209769 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2656 13:42:05.212700 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2657 13:42:05.216456 == TX Byte 1 ==
2658 13:42:05.219328 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2659 13:42:05.222735 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2660 13:42:05.222819 ==
2661 13:42:05.226090 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 13:42:05.232824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 13:42:05.232909 ==
2664 13:42:05.243980 TX Vref=22, minBit 0, minWin=24, winSum=399
2665 13:42:05.247515 TX Vref=24, minBit 0, minWin=25, winSum=410
2666 13:42:05.250317 TX Vref=26, minBit 1, minWin=26, winSum=418
2667 13:42:05.254027 TX Vref=28, minBit 7, minWin=25, winSum=420
2668 13:42:05.256970 TX Vref=30, minBit 0, minWin=26, winSum=421
2669 13:42:05.260565 TX Vref=32, minBit 1, minWin=26, winSum=422
2670 13:42:05.267222 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 32
2671 13:42:05.267300
2672 13:42:05.271024 Final TX Range 1 Vref 32
2673 13:42:05.271124
2674 13:42:05.271221 ==
2675 13:42:05.274002 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 13:42:05.277684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 13:42:05.277760 ==
2678 13:42:05.277823
2679 13:42:05.277899
2680 13:42:05.281162 TX Vref Scan disable
2681 13:42:05.284193 == TX Byte 0 ==
2682 13:42:05.287706 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2683 13:42:05.290608 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2684 13:42:05.294236 == TX Byte 1 ==
2685 13:42:05.297650 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2686 13:42:05.301067 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2687 13:42:05.301143
2688 13:42:05.304252 [DATLAT]
2689 13:42:05.304356 Freq=1200, CH0 RK0
2690 13:42:05.304436
2691 13:42:05.307337 DATLAT Default: 0xd
2692 13:42:05.307421 0, 0xFFFF, sum = 0
2693 13:42:05.310830 1, 0xFFFF, sum = 0
2694 13:42:05.310905 2, 0xFFFF, sum = 0
2695 13:42:05.314474 3, 0xFFFF, sum = 0
2696 13:42:05.314552 4, 0xFFFF, sum = 0
2697 13:42:05.317503 5, 0xFFFF, sum = 0
2698 13:42:05.317590 6, 0xFFFF, sum = 0
2699 13:42:05.320908 7, 0xFFFF, sum = 0
2700 13:42:05.320993 8, 0xFFFF, sum = 0
2701 13:42:05.324440 9, 0xFFFF, sum = 0
2702 13:42:05.324525 10, 0xFFFF, sum = 0
2703 13:42:05.327994 11, 0xFFFF, sum = 0
2704 13:42:05.328078 12, 0x0, sum = 1
2705 13:42:05.330634 13, 0x0, sum = 2
2706 13:42:05.330719 14, 0x0, sum = 3
2707 13:42:05.334316 15, 0x0, sum = 4
2708 13:42:05.334401 best_step = 13
2709 13:42:05.334467
2710 13:42:05.334528 ==
2711 13:42:05.337876 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 13:42:05.344563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 13:42:05.344649 ==
2714 13:42:05.344716 RX Vref Scan: 1
2715 13:42:05.344778
2716 13:42:05.348252 Set Vref Range= 32 -> 127
2717 13:42:05.348335
2718 13:42:05.351169 RX Vref 32 -> 127, step: 1
2719 13:42:05.351252
2720 13:42:05.351318 RX Delay -13 -> 252, step: 4
2721 13:42:05.351380
2722 13:42:05.354050 Set Vref, RX VrefLevel [Byte0]: 32
2723 13:42:05.357403 [Byte1]: 32
2724 13:42:05.361872
2725 13:42:05.361956 Set Vref, RX VrefLevel [Byte0]: 33
2726 13:42:05.365682 [Byte1]: 33
2727 13:42:05.370120
2728 13:42:05.370204 Set Vref, RX VrefLevel [Byte0]: 34
2729 13:42:05.373104 [Byte1]: 34
2730 13:42:05.377519
2731 13:42:05.377602 Set Vref, RX VrefLevel [Byte0]: 35
2732 13:42:05.381103 [Byte1]: 35
2733 13:42:05.385487
2734 13:42:05.385569 Set Vref, RX VrefLevel [Byte0]: 36
2735 13:42:05.389199 [Byte1]: 36
2736 13:42:05.393494
2737 13:42:05.393577 Set Vref, RX VrefLevel [Byte0]: 37
2738 13:42:05.397267 [Byte1]: 37
2739 13:42:05.401634
2740 13:42:05.401717 Set Vref, RX VrefLevel [Byte0]: 38
2741 13:42:05.404502 [Byte1]: 38
2742 13:42:05.409682
2743 13:42:05.409764 Set Vref, RX VrefLevel [Byte0]: 39
2744 13:42:05.412541 [Byte1]: 39
2745 13:42:05.416936
2746 13:42:05.420416 Set Vref, RX VrefLevel [Byte0]: 40
2747 13:42:05.423857 [Byte1]: 40
2748 13:42:05.423939
2749 13:42:05.427212 Set Vref, RX VrefLevel [Byte0]: 41
2750 13:42:05.430372 [Byte1]: 41
2751 13:42:05.430452
2752 13:42:05.433514 Set Vref, RX VrefLevel [Byte0]: 42
2753 13:42:05.437047 [Byte1]: 42
2754 13:42:05.440966
2755 13:42:05.441046 Set Vref, RX VrefLevel [Byte0]: 43
2756 13:42:05.444299 [Byte1]: 43
2757 13:42:05.448731
2758 13:42:05.448811 Set Vref, RX VrefLevel [Byte0]: 44
2759 13:42:05.452031 [Byte1]: 44
2760 13:42:05.456477
2761 13:42:05.456585 Set Vref, RX VrefLevel [Byte0]: 45
2762 13:42:05.460064 [Byte1]: 45
2763 13:42:05.464235
2764 13:42:05.464363 Set Vref, RX VrefLevel [Byte0]: 46
2765 13:42:05.467694 [Byte1]: 46
2766 13:42:05.472547
2767 13:42:05.472624 Set Vref, RX VrefLevel [Byte0]: 47
2768 13:42:05.475717 [Byte1]: 47
2769 13:42:05.480392
2770 13:42:05.480489 Set Vref, RX VrefLevel [Byte0]: 48
2771 13:42:05.483424 [Byte1]: 48
2772 13:42:05.488531
2773 13:42:05.488612 Set Vref, RX VrefLevel [Byte0]: 49
2774 13:42:05.491415 [Byte1]: 49
2775 13:42:05.496504
2776 13:42:05.496585 Set Vref, RX VrefLevel [Byte0]: 50
2777 13:42:05.499429 [Byte1]: 50
2778 13:42:05.503893
2779 13:42:05.503974 Set Vref, RX VrefLevel [Byte0]: 51
2780 13:42:05.507546 [Byte1]: 51
2781 13:42:05.511898
2782 13:42:05.511980 Set Vref, RX VrefLevel [Byte0]: 52
2783 13:42:05.514971 [Byte1]: 52
2784 13:42:05.520139
2785 13:42:05.520221 Set Vref, RX VrefLevel [Byte0]: 53
2786 13:42:05.523191 [Byte1]: 53
2787 13:42:05.527457
2788 13:42:05.527548 Set Vref, RX VrefLevel [Byte0]: 54
2789 13:42:05.531207 [Byte1]: 54
2790 13:42:05.535733
2791 13:42:05.535815 Set Vref, RX VrefLevel [Byte0]: 55
2792 13:42:05.539107 [Byte1]: 55
2793 13:42:05.543395
2794 13:42:05.543476 Set Vref, RX VrefLevel [Byte0]: 56
2795 13:42:05.546788 [Byte1]: 56
2796 13:42:05.551312
2797 13:42:05.551395 Set Vref, RX VrefLevel [Byte0]: 57
2798 13:42:05.554623 [Byte1]: 57
2799 13:42:05.559250
2800 13:42:05.559331 Set Vref, RX VrefLevel [Byte0]: 58
2801 13:42:05.562777 [Byte1]: 58
2802 13:42:05.566988
2803 13:42:05.567070 Set Vref, RX VrefLevel [Byte0]: 59
2804 13:42:05.570264 [Byte1]: 59
2805 13:42:05.574751
2806 13:42:05.574849 Set Vref, RX VrefLevel [Byte0]: 60
2807 13:42:05.578616 [Byte1]: 60
2808 13:42:05.582622
2809 13:42:05.582705 Set Vref, RX VrefLevel [Byte0]: 61
2810 13:42:05.586498 [Byte1]: 61
2811 13:42:05.590884
2812 13:42:05.590966 Set Vref, RX VrefLevel [Byte0]: 62
2813 13:42:05.594496 [Byte1]: 62
2814 13:42:05.598881
2815 13:42:05.598962 Set Vref, RX VrefLevel [Byte0]: 63
2816 13:42:05.601879 [Byte1]: 63
2817 13:42:05.606875
2818 13:42:05.606977 Set Vref, RX VrefLevel [Byte0]: 64
2819 13:42:05.609745 [Byte1]: 64
2820 13:42:05.614163
2821 13:42:05.614256 Set Vref, RX VrefLevel [Byte0]: 65
2822 13:42:05.617784 [Byte1]: 65
2823 13:42:05.622145
2824 13:42:05.622250 Set Vref, RX VrefLevel [Byte0]: 66
2825 13:42:05.625651 [Byte1]: 66
2826 13:42:05.630133
2827 13:42:05.630244 Set Vref, RX VrefLevel [Byte0]: 67
2828 13:42:05.633682 [Byte1]: 67
2829 13:42:05.638084
2830 13:42:05.638159 Set Vref, RX VrefLevel [Byte0]: 68
2831 13:42:05.641136 [Byte1]: 68
2832 13:42:05.646124
2833 13:42:05.646198 Set Vref, RX VrefLevel [Byte0]: 69
2834 13:42:05.649680 [Byte1]: 69
2835 13:42:05.654020
2836 13:42:05.654094 Set Vref, RX VrefLevel [Byte0]: 70
2837 13:42:05.657549 [Byte1]: 70
2838 13:42:05.662033
2839 13:42:05.662110 Set Vref, RX VrefLevel [Byte0]: 71
2840 13:42:05.664728 [Byte1]: 71
2841 13:42:05.669661
2842 13:42:05.669741 Set Vref, RX VrefLevel [Byte0]: 72
2843 13:42:05.673475 [Byte1]: 72
2844 13:42:05.677862
2845 13:42:05.677937 Final RX Vref Byte 0 = 56 to rank0
2846 13:42:05.680859 Final RX Vref Byte 1 = 42 to rank0
2847 13:42:05.684401 Final RX Vref Byte 0 = 56 to rank1
2848 13:42:05.687259 Final RX Vref Byte 1 = 42 to rank1==
2849 13:42:05.690937 Dram Type= 6, Freq= 0, CH_0, rank 0
2850 13:42:05.697419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 13:42:05.697494 ==
2852 13:42:05.697560 DQS Delay:
2853 13:42:05.697619 DQS0 = 0, DQS1 = 0
2854 13:42:05.700889 DQM Delay:
2855 13:42:05.700985 DQM0 = 120, DQM1 = 109
2856 13:42:05.704480 DQ Delay:
2857 13:42:05.707630 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2858 13:42:05.710678 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2859 13:42:05.714040 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
2860 13:42:05.717753 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
2861 13:42:05.717829
2862 13:42:05.717923
2863 13:42:05.724053 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2864 13:42:05.727616 CH0 RK0: MR19=404, MR18=1710
2865 13:42:05.734484 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2866 13:42:05.734602
2867 13:42:05.737865 ----->DramcWriteLeveling(PI) begin...
2868 13:42:05.737942 ==
2869 13:42:05.740778 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 13:42:05.744393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 13:42:05.744476 ==
2872 13:42:05.748125 Write leveling (Byte 0): 33 => 33
2873 13:42:05.751081 Write leveling (Byte 1): 29 => 29
2874 13:42:05.754434 DramcWriteLeveling(PI) end<-----
2875 13:42:05.754510
2876 13:42:05.754574 ==
2877 13:42:05.757680 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 13:42:05.761382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 13:42:05.764958 ==
2880 13:42:05.765042 [Gating] SW mode calibration
2881 13:42:05.771432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2882 13:42:05.778014 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2883 13:42:05.781615 0 15 0 | B1->B0 | 3333 3332 | 1 1 | (1 1) (0 0)
2884 13:42:05.788260 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 13:42:05.791126 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 13:42:05.794826 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 13:42:05.801435 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 13:42:05.804375 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 13:42:05.807959 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 13:42:05.814519 0 15 28 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 0)
2891 13:42:05.818209 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 13:42:05.820993 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 13:42:05.828324 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 13:42:05.831247 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 13:42:05.834980 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 13:42:05.837708 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 13:42:05.844456 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2898 13:42:05.847996 1 0 28 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
2899 13:42:05.851030 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 13:42:05.857810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 13:42:05.861007 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 13:42:05.864915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 13:42:05.871123 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 13:42:05.874279 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 13:42:05.878242 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 13:42:05.884480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2907 13:42:05.888265 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2908 13:42:05.891655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 13:42:05.898239 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 13:42:05.901177 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 13:42:05.904768 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 13:42:05.911523 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 13:42:05.914400 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 13:42:05.918066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:42:05.924577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:42:05.928095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:42:05.931644 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:42:05.934345 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:42:05.941088 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:42:05.944718 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:42:05.947626 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:42:05.954165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2923 13:42:05.957567 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2924 13:42:05.961275 Total UI for P1: 0, mck2ui 16
2925 13:42:05.964769 best dqsien dly found for B1: ( 1, 3, 28)
2926 13:42:05.967705 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 13:42:05.971074 Total UI for P1: 0, mck2ui 16
2928 13:42:05.974654 best dqsien dly found for B0: ( 1, 3, 30)
2929 13:42:05.977963 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2930 13:42:05.981133 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2931 13:42:05.981220
2932 13:42:05.987719 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2933 13:42:05.991409 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2934 13:42:05.994641 [Gating] SW calibration Done
2935 13:42:05.994720 ==
2936 13:42:05.998141 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 13:42:06.001076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 13:42:06.001154 ==
2939 13:42:06.001238 RX Vref Scan: 0
2940 13:42:06.001318
2941 13:42:06.004538 RX Vref 0 -> 0, step: 1
2942 13:42:06.004622
2943 13:42:06.007897 RX Delay -40 -> 252, step: 8
2944 13:42:06.011193 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2945 13:42:06.014670 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2946 13:42:06.017842 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2947 13:42:06.024627 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2948 13:42:06.028254 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2949 13:42:06.031301 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2950 13:42:06.034734 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2951 13:42:06.038365 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2952 13:42:06.044743 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2953 13:42:06.048418 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2954 13:42:06.051375 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2955 13:42:06.055068 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2956 13:42:06.058061 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2957 13:42:06.064999 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2958 13:42:06.067936 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2959 13:42:06.071603 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2960 13:42:06.071690 ==
2961 13:42:06.074382 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 13:42:06.078055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 13:42:06.078171 ==
2964 13:42:06.081588 DQS Delay:
2965 13:42:06.081674 DQS0 = 0, DQS1 = 0
2966 13:42:06.081746 DQM Delay:
2967 13:42:06.085276 DQM0 = 122, DQM1 = 111
2968 13:42:06.085358 DQ Delay:
2969 13:42:06.088235 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2970 13:42:06.091822 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2971 13:42:06.098174 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
2972 13:42:06.101103 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2973 13:42:06.101185
2974 13:42:06.101251
2975 13:42:06.101310 ==
2976 13:42:06.104709 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 13:42:06.108278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 13:42:06.108400 ==
2979 13:42:06.108495
2980 13:42:06.108583
2981 13:42:06.111717 TX Vref Scan disable
2982 13:42:06.111794 == TX Byte 0 ==
2983 13:42:06.118261 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2984 13:42:06.121500 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2985 13:42:06.121577 == TX Byte 1 ==
2986 13:42:06.128331 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2987 13:42:06.131682 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2988 13:42:06.131792 ==
2989 13:42:06.135180 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 13:42:06.138126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 13:42:06.138232 ==
2992 13:42:06.151007 TX Vref=22, minBit 3, minWin=24, winSum=412
2993 13:42:06.154734 TX Vref=24, minBit 3, minWin=25, winSum=420
2994 13:42:06.157703 TX Vref=26, minBit 3, minWin=25, winSum=420
2995 13:42:06.161394 TX Vref=28, minBit 0, minWin=26, winSum=430
2996 13:42:06.164420 TX Vref=30, minBit 0, minWin=26, winSum=428
2997 13:42:06.167975 TX Vref=32, minBit 0, minWin=26, winSum=427
2998 13:42:06.174296 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
2999 13:42:06.174415
3000 13:42:06.177902 Final TX Range 1 Vref 28
3001 13:42:06.177981
3002 13:42:06.178046 ==
3003 13:42:06.181481 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 13:42:06.184359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 13:42:06.184455 ==
3006 13:42:06.184522
3007 13:42:06.187804
3008 13:42:06.187880 TX Vref Scan disable
3009 13:42:06.191592 == TX Byte 0 ==
3010 13:42:06.194453 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3011 13:42:06.198139 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3012 13:42:06.200959 == TX Byte 1 ==
3013 13:42:06.204670 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3014 13:42:06.208245 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3015 13:42:06.208360
3016 13:42:06.211101 [DATLAT]
3017 13:42:06.211202 Freq=1200, CH0 RK1
3018 13:42:06.211300
3019 13:42:06.214800 DATLAT Default: 0xd
3020 13:42:06.214885 0, 0xFFFF, sum = 0
3021 13:42:06.218495 1, 0xFFFF, sum = 0
3022 13:42:06.218582 2, 0xFFFF, sum = 0
3023 13:42:06.221335 3, 0xFFFF, sum = 0
3024 13:42:06.221417 4, 0xFFFF, sum = 0
3025 13:42:06.225037 5, 0xFFFF, sum = 0
3026 13:42:06.225119 6, 0xFFFF, sum = 0
3027 13:42:06.227874 7, 0xFFFF, sum = 0
3028 13:42:06.227957 8, 0xFFFF, sum = 0
3029 13:42:06.231573 9, 0xFFFF, sum = 0
3030 13:42:06.235157 10, 0xFFFF, sum = 0
3031 13:42:06.235242 11, 0xFFFF, sum = 0
3032 13:42:06.238504 12, 0x0, sum = 1
3033 13:42:06.238584 13, 0x0, sum = 2
3034 13:42:06.238667 14, 0x0, sum = 3
3035 13:42:06.241721 15, 0x0, sum = 4
3036 13:42:06.241822 best_step = 13
3037 13:42:06.241908
3038 13:42:06.241985 ==
3039 13:42:06.244867 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 13:42:06.251283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 13:42:06.251367 ==
3042 13:42:06.251453 RX Vref Scan: 0
3043 13:42:06.251536
3044 13:42:06.254685 RX Vref 0 -> 0, step: 1
3045 13:42:06.254767
3046 13:42:06.258201 RX Delay -13 -> 252, step: 4
3047 13:42:06.261762 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3048 13:42:06.264687 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3049 13:42:06.271851 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3050 13:42:06.274679 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3051 13:42:06.278255 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3052 13:42:06.281701 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3053 13:42:06.284543 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3054 13:42:06.291293 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3055 13:42:06.294814 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3056 13:42:06.298413 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3057 13:42:06.301345 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3058 13:42:06.305004 iDelay=195, Bit 11, Center 98 (35 ~ 162) 128
3059 13:42:06.308042 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3060 13:42:06.315092 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3061 13:42:06.318018 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3062 13:42:06.321622 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3063 13:42:06.321698 ==
3064 13:42:06.325183 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 13:42:06.328154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 13:42:06.328261 ==
3067 13:42:06.331816 DQS Delay:
3068 13:42:06.331896 DQS0 = 0, DQS1 = 0
3069 13:42:06.334787 DQM Delay:
3070 13:42:06.334869 DQM0 = 120, DQM1 = 108
3071 13:42:06.338501 DQ Delay:
3072 13:42:06.342234 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3073 13:42:06.345034 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3074 13:42:06.348667 DQ8 =98, DQ9 =96, DQ10 =110, DQ11 =98
3075 13:42:06.352253 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3076 13:42:06.352365
3077 13:42:06.352450
3078 13:42:06.358426 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3079 13:42:06.361832 CH0 RK1: MR19=403, MR18=12F3
3080 13:42:06.368766 CH0_RK1: MR19=0x403, MR18=0x12F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3081 13:42:06.371954 [RxdqsGatingPostProcess] freq 1200
3082 13:42:06.375045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3083 13:42:06.378963 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 13:42:06.381958 best DQS1 dly(2T, 0.5T) = (0, 12)
3085 13:42:06.385467 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 13:42:06.388956 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3087 13:42:06.391894 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 13:42:06.395445 best DQS1 dly(2T, 0.5T) = (0, 11)
3089 13:42:06.398309 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 13:42:06.401991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3091 13:42:06.405497 Pre-setting of DQS Precalculation
3092 13:42:06.408480 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3093 13:42:06.408561 ==
3094 13:42:06.412121 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 13:42:06.418636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 13:42:06.418722 ==
3097 13:42:06.421618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 13:42:06.428803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3099 13:42:06.437551 [CA 0] Center 37 (7~68) winsize 62
3100 13:42:06.440551 [CA 1] Center 37 (7~68) winsize 62
3101 13:42:06.444263 [CA 2] Center 35 (5~65) winsize 61
3102 13:42:06.447202 [CA 3] Center 34 (4~64) winsize 61
3103 13:42:06.450938 [CA 4] Center 34 (4~64) winsize 61
3104 13:42:06.454057 [CA 5] Center 33 (3~63) winsize 61
3105 13:42:06.454137
3106 13:42:06.457111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 13:42:06.457222
3108 13:42:06.460727 [CATrainingPosCal] consider 1 rank data
3109 13:42:06.463737 u2DelayCellTimex100 = 270/100 ps
3110 13:42:06.467478 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 13:42:06.470428 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3112 13:42:06.477267 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 13:42:06.480486 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 13:42:06.483883 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 13:42:06.487351 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3116 13:42:06.487431
3117 13:42:06.490782 CA PerBit enable=1, Macro0, CA PI delay=33
3118 13:42:06.490860
3119 13:42:06.494197 [CBTSetCACLKResult] CA Dly = 33
3120 13:42:06.494275 CS Dly: 7 (0~38)
3121 13:42:06.494359 ==
3122 13:42:06.497059 Dram Type= 6, Freq= 0, CH_1, rank 1
3123 13:42:06.504218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 13:42:06.504303 ==
3125 13:42:06.506980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 13:42:06.513724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 13:42:06.522619 [CA 0] Center 37 (7~68) winsize 62
3128 13:42:06.526119 [CA 1] Center 37 (7~68) winsize 62
3129 13:42:06.529586 [CA 2] Center 35 (5~66) winsize 62
3130 13:42:06.533086 [CA 3] Center 34 (4~65) winsize 62
3131 13:42:06.536717 [CA 4] Center 34 (4~65) winsize 62
3132 13:42:06.539689 [CA 5] Center 34 (4~64) winsize 61
3133 13:42:06.539798
3134 13:42:06.543495 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3135 13:42:06.543576
3136 13:42:06.546364 [CATrainingPosCal] consider 2 rank data
3137 13:42:06.549885 u2DelayCellTimex100 = 270/100 ps
3138 13:42:06.552901 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 13:42:06.556472 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 13:42:06.559476 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3141 13:42:06.566535 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 13:42:06.570179 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 13:42:06.573162 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3144 13:42:06.573246
3145 13:42:06.576825 CA PerBit enable=1, Macro0, CA PI delay=33
3146 13:42:06.576904
3147 13:42:06.579878 [CBTSetCACLKResult] CA Dly = 33
3148 13:42:06.579962 CS Dly: 8 (0~41)
3149 13:42:06.580032
3150 13:42:06.583361 ----->DramcWriteLeveling(PI) begin...
3151 13:42:06.583463 ==
3152 13:42:06.586872 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 13:42:06.593212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 13:42:06.593297 ==
3155 13:42:06.596739 Write leveling (Byte 0): 25 => 25
3156 13:42:06.596841 Write leveling (Byte 1): 28 => 28
3157 13:42:06.600369 DramcWriteLeveling(PI) end<-----
3158 13:42:06.600445
3159 13:42:06.603316 ==
3160 13:42:06.606823 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 13:42:06.609617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 13:42:06.609701 ==
3163 13:42:06.613578 [Gating] SW mode calibration
3164 13:42:06.620171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3165 13:42:06.622942 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3166 13:42:06.630003 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 13:42:06.633242 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 13:42:06.637012 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 13:42:06.643602 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 13:42:06.646734 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 13:42:06.649968 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 13:42:06.656654 0 15 24 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
3173 13:42:06.660288 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3174 13:42:06.663759 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 13:42:06.666679 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 13:42:06.673413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 13:42:06.677061 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 13:42:06.680121 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 13:42:06.686702 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 13:42:06.690367 1 0 24 | B1->B0 | 3333 3f3f | 1 0 | (1 1) (0 0)
3181 13:42:06.693194 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 13:42:06.700347 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 13:42:06.703252 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 13:42:06.706855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 13:42:06.713549 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 13:42:06.717262 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 13:42:06.720212 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 13:42:06.727251 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3189 13:42:06.730218 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3190 13:42:06.733823 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 13:42:06.736882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 13:42:06.743597 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 13:42:06.746542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 13:42:06.750142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 13:42:06.757037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 13:42:06.760159 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:42:06.763300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:42:06.770500 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:42:06.773573 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:42:06.776762 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:42:06.783902 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:42:06.787021 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:42:06.790182 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:42:06.797320 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 13:42:06.800457 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3206 13:42:06.803864 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 13:42:06.807395 Total UI for P1: 0, mck2ui 16
3208 13:42:06.810314 best dqsien dly found for B0: ( 1, 3, 26)
3209 13:42:06.813955 Total UI for P1: 0, mck2ui 16
3210 13:42:06.816924 best dqsien dly found for B1: ( 1, 3, 26)
3211 13:42:06.820636 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3212 13:42:06.823541 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3213 13:42:06.823624
3214 13:42:06.827260 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3215 13:42:06.833723 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 13:42:06.833828 [Gating] SW calibration Done
3217 13:42:06.833931 ==
3218 13:42:06.836676 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 13:42:06.843313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 13:42:06.843415 ==
3221 13:42:06.843488 RX Vref Scan: 0
3222 13:42:06.843551
3223 13:42:06.847048 RX Vref 0 -> 0, step: 1
3224 13:42:06.847128
3225 13:42:06.849980 RX Delay -40 -> 252, step: 8
3226 13:42:06.853743 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3227 13:42:06.857332 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3228 13:42:06.860224 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3229 13:42:06.866887 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3230 13:42:06.870385 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3231 13:42:06.873304 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3232 13:42:06.876994 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3233 13:42:06.879948 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3234 13:42:06.886564 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3235 13:42:06.890062 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3236 13:42:06.893541 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3237 13:42:06.896735 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3238 13:42:06.900127 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3239 13:42:06.906932 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3240 13:42:06.910287 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3241 13:42:06.913752 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3242 13:42:06.913832 ==
3243 13:42:06.916794 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 13:42:06.920087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 13:42:06.920168 ==
3246 13:42:06.923446 DQS Delay:
3247 13:42:06.923533 DQS0 = 0, DQS1 = 0
3248 13:42:06.926822 DQM Delay:
3249 13:42:06.926939 DQM0 = 119, DQM1 = 116
3250 13:42:06.927036 DQ Delay:
3251 13:42:06.930541 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3252 13:42:06.933487 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3253 13:42:06.940369 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3254 13:42:06.943863 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3255 13:42:06.943943
3256 13:42:06.944010
3257 13:42:06.944071 ==
3258 13:42:06.946796 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 13:42:06.950463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 13:42:06.950571 ==
3261 13:42:06.950641
3262 13:42:06.950702
3263 13:42:06.953439 TX Vref Scan disable
3264 13:42:06.953517 == TX Byte 0 ==
3265 13:42:06.960783 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3266 13:42:06.963744 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3267 13:42:06.963850 == TX Byte 1 ==
3268 13:42:06.970276 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3269 13:42:06.973882 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3270 13:42:06.973959 ==
3271 13:42:06.977357 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 13:42:06.980349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 13:42:06.980429 ==
3274 13:42:06.993453 TX Vref=22, minBit 1, minWin=25, winSum=413
3275 13:42:06.997037 TX Vref=24, minBit 11, minWin=24, winSum=416
3276 13:42:07.000025 TX Vref=26, minBit 9, minWin=25, winSum=424
3277 13:42:07.003392 TX Vref=28, minBit 1, minWin=26, winSum=429
3278 13:42:07.006851 TX Vref=30, minBit 2, minWin=26, winSum=430
3279 13:42:07.013332 TX Vref=32, minBit 2, minWin=26, winSum=426
3280 13:42:07.016998 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 30
3281 13:42:07.017079
3282 13:42:07.019963 Final TX Range 1 Vref 30
3283 13:42:07.020073
3284 13:42:07.020168 ==
3285 13:42:07.023492 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 13:42:07.026506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 13:42:07.026616 ==
3288 13:42:07.026692
3289 13:42:07.030088
3290 13:42:07.030164 TX Vref Scan disable
3291 13:42:07.033628 == TX Byte 0 ==
3292 13:42:07.036795 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3293 13:42:07.040076 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3294 13:42:07.043422 == TX Byte 1 ==
3295 13:42:07.046551 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3296 13:42:07.049957 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3297 13:42:07.050043
3298 13:42:07.053593 [DATLAT]
3299 13:42:07.053669 Freq=1200, CH1 RK0
3300 13:42:07.053754
3301 13:42:07.057236 DATLAT Default: 0xd
3302 13:42:07.057333 0, 0xFFFF, sum = 0
3303 13:42:07.059959 1, 0xFFFF, sum = 0
3304 13:42:07.060032 2, 0xFFFF, sum = 0
3305 13:42:07.063683 3, 0xFFFF, sum = 0
3306 13:42:07.063763 4, 0xFFFF, sum = 0
3307 13:42:07.066544 5, 0xFFFF, sum = 0
3308 13:42:07.066646 6, 0xFFFF, sum = 0
3309 13:42:07.070035 7, 0xFFFF, sum = 0
3310 13:42:07.070139 8, 0xFFFF, sum = 0
3311 13:42:07.073761 9, 0xFFFF, sum = 0
3312 13:42:07.076796 10, 0xFFFF, sum = 0
3313 13:42:07.076886 11, 0xFFFF, sum = 0
3314 13:42:07.079783 12, 0x0, sum = 1
3315 13:42:07.079855 13, 0x0, sum = 2
3316 13:42:07.079934 14, 0x0, sum = 3
3317 13:42:07.083410 15, 0x0, sum = 4
3318 13:42:07.083518 best_step = 13
3319 13:42:07.083673
3320 13:42:07.083779 ==
3321 13:42:07.086855 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 13:42:07.093265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 13:42:07.093422 ==
3324 13:42:07.093554 RX Vref Scan: 1
3325 13:42:07.093655
3326 13:42:07.096851 Set Vref Range= 32 -> 127
3327 13:42:07.096931
3328 13:42:07.100542 RX Vref 32 -> 127, step: 1
3329 13:42:07.100647
3330 13:42:07.100779 RX Delay -5 -> 252, step: 4
3331 13:42:07.103452
3332 13:42:07.103581 Set Vref, RX VrefLevel [Byte0]: 32
3333 13:42:07.107029 [Byte1]: 32
3334 13:42:07.111255
3335 13:42:07.111382 Set Vref, RX VrefLevel [Byte0]: 33
3336 13:42:07.114630 [Byte1]: 33
3337 13:42:07.119565
3338 13:42:07.119667 Set Vref, RX VrefLevel [Byte0]: 34
3339 13:42:07.122446 [Byte1]: 34
3340 13:42:07.127507
3341 13:42:07.127604 Set Vref, RX VrefLevel [Byte0]: 35
3342 13:42:07.130426 [Byte1]: 35
3343 13:42:07.135417
3344 13:42:07.135494 Set Vref, RX VrefLevel [Byte0]: 36
3345 13:42:07.138303 [Byte1]: 36
3346 13:42:07.142699
3347 13:42:07.142801 Set Vref, RX VrefLevel [Byte0]: 37
3348 13:42:07.146415 [Byte1]: 37
3349 13:42:07.150764
3350 13:42:07.150840 Set Vref, RX VrefLevel [Byte0]: 38
3351 13:42:07.154335 [Byte1]: 38
3352 13:42:07.158401
3353 13:42:07.158477 Set Vref, RX VrefLevel [Byte0]: 39
3354 13:42:07.161793 [Byte1]: 39
3355 13:42:07.166371
3356 13:42:07.166448 Set Vref, RX VrefLevel [Byte0]: 40
3357 13:42:07.169573 [Byte1]: 40
3358 13:42:07.174385
3359 13:42:07.174466 Set Vref, RX VrefLevel [Byte0]: 41
3360 13:42:07.177843 [Byte1]: 41
3361 13:42:07.182406
3362 13:42:07.182483 Set Vref, RX VrefLevel [Byte0]: 42
3363 13:42:07.185310 [Byte1]: 42
3364 13:42:07.190309
3365 13:42:07.190388 Set Vref, RX VrefLevel [Byte0]: 43
3366 13:42:07.193170 [Byte1]: 43
3367 13:42:07.198132
3368 13:42:07.198210 Set Vref, RX VrefLevel [Byte0]: 44
3369 13:42:07.200874 [Byte1]: 44
3370 13:42:07.206038
3371 13:42:07.206113 Set Vref, RX VrefLevel [Byte0]: 45
3372 13:42:07.208985 [Byte1]: 45
3373 13:42:07.213418
3374 13:42:07.213497 Set Vref, RX VrefLevel [Byte0]: 46
3375 13:42:07.217029 [Byte1]: 46
3376 13:42:07.221113
3377 13:42:07.221185 Set Vref, RX VrefLevel [Byte0]: 47
3378 13:42:07.224533 [Byte1]: 47
3379 13:42:07.228939
3380 13:42:07.232655 Set Vref, RX VrefLevel [Byte0]: 48
3381 13:42:07.235425 [Byte1]: 48
3382 13:42:07.235524
3383 13:42:07.239005 Set Vref, RX VrefLevel [Byte0]: 49
3384 13:42:07.242630 [Byte1]: 49
3385 13:42:07.242705
3386 13:42:07.245553 Set Vref, RX VrefLevel [Byte0]: 50
3387 13:42:07.249328 [Byte1]: 50
3388 13:42:07.253118
3389 13:42:07.253194 Set Vref, RX VrefLevel [Byte0]: 51
3390 13:42:07.255982 [Byte1]: 51
3391 13:42:07.260261
3392 13:42:07.260332 Set Vref, RX VrefLevel [Byte0]: 52
3393 13:42:07.263836 [Byte1]: 52
3394 13:42:07.268420
3395 13:42:07.268493 Set Vref, RX VrefLevel [Byte0]: 53
3396 13:42:07.272073 [Byte1]: 53
3397 13:42:07.276538
3398 13:42:07.276611 Set Vref, RX VrefLevel [Byte0]: 54
3399 13:42:07.279413 [Byte1]: 54
3400 13:42:07.284230
3401 13:42:07.284304 Set Vref, RX VrefLevel [Byte0]: 55
3402 13:42:07.287176 [Byte1]: 55
3403 13:42:07.292196
3404 13:42:07.292268 Set Vref, RX VrefLevel [Byte0]: 56
3405 13:42:07.295185 [Byte1]: 56
3406 13:42:07.300024
3407 13:42:07.300103 Set Vref, RX VrefLevel [Byte0]: 57
3408 13:42:07.303184 [Byte1]: 57
3409 13:42:07.307752
3410 13:42:07.307846 Set Vref, RX VrefLevel [Byte0]: 58
3411 13:42:07.311279 [Byte1]: 58
3412 13:42:07.315666
3413 13:42:07.315753 Set Vref, RX VrefLevel [Byte0]: 59
3414 13:42:07.318487 [Byte1]: 59
3415 13:42:07.323027
3416 13:42:07.323126 Set Vref, RX VrefLevel [Byte0]: 60
3417 13:42:07.326703 [Byte1]: 60
3418 13:42:07.330947
3419 13:42:07.331061 Set Vref, RX VrefLevel [Byte0]: 61
3420 13:42:07.334789 [Byte1]: 61
3421 13:42:07.338864
3422 13:42:07.338980 Set Vref, RX VrefLevel [Byte0]: 62
3423 13:42:07.342506 [Byte1]: 62
3424 13:42:07.346771
3425 13:42:07.346855 Set Vref, RX VrefLevel [Byte0]: 63
3426 13:42:07.350237 [Byte1]: 63
3427 13:42:07.354616
3428 13:42:07.354695 Set Vref, RX VrefLevel [Byte0]: 64
3429 13:42:07.358213 [Byte1]: 64
3430 13:42:07.362658
3431 13:42:07.362751 Set Vref, RX VrefLevel [Byte0]: 65
3432 13:42:07.366277 [Byte1]: 65
3433 13:42:07.370714
3434 13:42:07.370790 Set Vref, RX VrefLevel [Byte0]: 66
3435 13:42:07.373644 [Byte1]: 66
3436 13:42:07.378196
3437 13:42:07.378269 Set Vref, RX VrefLevel [Byte0]: 67
3438 13:42:07.381842 [Byte1]: 67
3439 13:42:07.386310
3440 13:42:07.386386 Set Vref, RX VrefLevel [Byte0]: 68
3441 13:42:07.389898 [Byte1]: 68
3442 13:42:07.394228
3443 13:42:07.394301 Final RX Vref Byte 0 = 55 to rank0
3444 13:42:07.397116 Final RX Vref Byte 1 = 48 to rank0
3445 13:42:07.400620 Final RX Vref Byte 0 = 55 to rank1
3446 13:42:07.404100 Final RX Vref Byte 1 = 48 to rank1==
3447 13:42:07.407428 Dram Type= 6, Freq= 0, CH_1, rank 0
3448 13:42:07.414226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 13:42:07.414306 ==
3450 13:42:07.414378 DQS Delay:
3451 13:42:07.414439 DQS0 = 0, DQS1 = 0
3452 13:42:07.417469 DQM Delay:
3453 13:42:07.417554 DQM0 = 120, DQM1 = 116
3454 13:42:07.420768 DQ Delay:
3455 13:42:07.424033 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3456 13:42:07.427536 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3457 13:42:07.430537 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3458 13:42:07.433953 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3459 13:42:07.434026
3460 13:42:07.434088
3461 13:42:07.441145 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3462 13:42:07.444064 CH1 RK0: MR19=404, MR18=215
3463 13:42:07.450826 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3464 13:42:07.450908
3465 13:42:07.454338 ----->DramcWriteLeveling(PI) begin...
3466 13:42:07.454416 ==
3467 13:42:07.457331 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 13:42:07.460604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 13:42:07.460685 ==
3470 13:42:07.464056 Write leveling (Byte 0): 25 => 25
3471 13:42:07.467724 Write leveling (Byte 1): 29 => 29
3472 13:42:07.470911 DramcWriteLeveling(PI) end<-----
3473 13:42:07.470980
3474 13:42:07.471040 ==
3475 13:42:07.474563 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 13:42:07.477461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 13:42:07.481247 ==
3478 13:42:07.481322 [Gating] SW mode calibration
3479 13:42:07.490736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3480 13:42:07.494488 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3481 13:42:07.497465 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 13:42:07.504107 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 13:42:07.507725 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 13:42:07.510622 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 13:42:07.517862 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 13:42:07.520746 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3487 13:42:07.524284 0 15 24 | B1->B0 | 2a2a 3333 | 0 0 | (0 1) (0 0)
3488 13:42:07.530713 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3489 13:42:07.534336 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 13:42:07.537344 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 13:42:07.544531 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 13:42:07.547774 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 13:42:07.551069 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 13:42:07.557249 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3495 13:42:07.560721 1 0 24 | B1->B0 | 4040 2727 | 0 0 | (0 0) (0 0)
3496 13:42:07.564264 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 13:42:07.570959 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 13:42:07.573995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 13:42:07.577366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 13:42:07.580448 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 13:42:07.587444 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 13:42:07.590902 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 13:42:07.594155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3504 13:42:07.600674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3505 13:42:07.603591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 13:42:07.607517 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 13:42:07.613897 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:42:07.616862 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:42:07.620276 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:42:07.627483 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:42:07.630441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 13:42:07.634285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 13:42:07.640829 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 13:42:07.643720 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 13:42:07.647369 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 13:42:07.653445 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 13:42:07.657204 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3518 13:42:07.660136 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3519 13:42:07.667149 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3520 13:42:07.669954 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3521 13:42:07.673330 Total UI for P1: 0, mck2ui 16
3522 13:42:07.676781 best dqsien dly found for B1: ( 1, 3, 20)
3523 13:42:07.680472 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 13:42:07.683306 Total UI for P1: 0, mck2ui 16
3525 13:42:07.686923 best dqsien dly found for B0: ( 1, 3, 26)
3526 13:42:07.690368 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3527 13:42:07.693571 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3528 13:42:07.693650
3529 13:42:07.700348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3530 13:42:07.703680 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3531 13:42:07.703755 [Gating] SW calibration Done
3532 13:42:07.706952 ==
3533 13:42:07.707026 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 13:42:07.713557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 13:42:07.713639 ==
3536 13:42:07.713708 RX Vref Scan: 0
3537 13:42:07.713770
3538 13:42:07.716847 RX Vref 0 -> 0, step: 1
3539 13:42:07.716924
3540 13:42:07.720307 RX Delay -40 -> 252, step: 8
3541 13:42:07.723604 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3542 13:42:07.727091 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3543 13:42:07.729976 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3544 13:42:07.736506 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3545 13:42:07.740099 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3546 13:42:07.743713 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3547 13:42:07.746663 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3548 13:42:07.750381 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3549 13:42:07.757049 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3550 13:42:07.759797 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3551 13:42:07.763433 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3552 13:42:07.766362 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3553 13:42:07.770020 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3554 13:42:07.776611 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3555 13:42:07.780000 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3556 13:42:07.783379 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3557 13:42:07.783485 ==
3558 13:42:07.786798 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 13:42:07.789751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 13:42:07.793462 ==
3561 13:42:07.793537 DQS Delay:
3562 13:42:07.793598 DQS0 = 0, DQS1 = 0
3563 13:42:07.796419 DQM Delay:
3564 13:42:07.796523 DQM0 = 120, DQM1 = 118
3565 13:42:07.799943 DQ Delay:
3566 13:42:07.803349 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3567 13:42:07.807045 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3568 13:42:07.809860 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3569 13:42:07.813444 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3570 13:42:07.813528
3571 13:42:07.813594
3572 13:42:07.813654 ==
3573 13:42:07.816415 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 13:42:07.819746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 13:42:07.819857 ==
3576 13:42:07.819956
3577 13:42:07.820049
3578 13:42:07.823160 TX Vref Scan disable
3579 13:42:07.826241 == TX Byte 0 ==
3580 13:42:07.830063 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3581 13:42:07.833445 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3582 13:42:07.836689 == TX Byte 1 ==
3583 13:42:07.839886 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3584 13:42:07.843099 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3585 13:42:07.843209 ==
3586 13:42:07.846348 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 13:42:07.849715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 13:42:07.853100 ==
3589 13:42:07.863473 TX Vref=22, minBit 1, minWin=25, winSum=419
3590 13:42:07.866430 TX Vref=24, minBit 1, minWin=26, winSum=425
3591 13:42:07.869989 TX Vref=26, minBit 2, minWin=26, winSum=428
3592 13:42:07.873377 TX Vref=28, minBit 8, minWin=26, winSum=433
3593 13:42:07.877002 TX Vref=30, minBit 9, minWin=26, winSum=437
3594 13:42:07.883516 TX Vref=32, minBit 9, minWin=26, winSum=433
3595 13:42:07.886427 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3596 13:42:07.886537
3597 13:42:07.889953 Final TX Range 1 Vref 30
3598 13:42:07.890060
3599 13:42:07.890154 ==
3600 13:42:07.893636 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 13:42:07.896443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 13:42:07.896526 ==
3603 13:42:07.900112
3604 13:42:07.900189
3605 13:42:07.900258 TX Vref Scan disable
3606 13:42:07.903139 == TX Byte 0 ==
3607 13:42:07.906681 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3608 13:42:07.909589 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3609 13:42:07.913098 == TX Byte 1 ==
3610 13:42:07.916660 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3611 13:42:07.923165 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3612 13:42:07.923253
3613 13:42:07.923319 [DATLAT]
3614 13:42:07.923379 Freq=1200, CH1 RK1
3615 13:42:07.923437
3616 13:42:07.926111 DATLAT Default: 0xd
3617 13:42:07.926184 0, 0xFFFF, sum = 0
3618 13:42:07.929656 1, 0xFFFF, sum = 0
3619 13:42:07.933067 2, 0xFFFF, sum = 0
3620 13:42:07.933148 3, 0xFFFF, sum = 0
3621 13:42:07.936498 4, 0xFFFF, sum = 0
3622 13:42:07.936580 5, 0xFFFF, sum = 0
3623 13:42:07.939330 6, 0xFFFF, sum = 0
3624 13:42:07.939405 7, 0xFFFF, sum = 0
3625 13:42:07.942734 8, 0xFFFF, sum = 0
3626 13:42:07.942808 9, 0xFFFF, sum = 0
3627 13:42:07.946053 10, 0xFFFF, sum = 0
3628 13:42:07.946163 11, 0xFFFF, sum = 0
3629 13:42:07.949423 12, 0x0, sum = 1
3630 13:42:07.949503 13, 0x0, sum = 2
3631 13:42:07.952782 14, 0x0, sum = 3
3632 13:42:07.952862 15, 0x0, sum = 4
3633 13:42:07.956320 best_step = 13
3634 13:42:07.956422
3635 13:42:07.956487 ==
3636 13:42:07.959579 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 13:42:07.962869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 13:42:07.962946 ==
3639 13:42:07.963016 RX Vref Scan: 0
3640 13:42:07.963078
3641 13:42:07.965917 RX Vref 0 -> 0, step: 1
3642 13:42:07.965994
3643 13:42:07.969150 RX Delay -5 -> 252, step: 4
3644 13:42:07.972712 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3645 13:42:07.979243 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3646 13:42:07.983077 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3647 13:42:07.986013 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3648 13:42:07.989658 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3649 13:42:07.992436 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3650 13:42:07.999538 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3651 13:42:08.002321 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3652 13:42:08.006098 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3653 13:42:08.009056 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3654 13:42:08.012608 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3655 13:42:08.019157 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3656 13:42:08.022534 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3657 13:42:08.025782 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3658 13:42:08.029673 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3659 13:42:08.032573 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3660 13:42:08.036173 ==
3661 13:42:08.039057 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 13:42:08.042664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 13:42:08.042768 ==
3664 13:42:08.042833 DQS Delay:
3665 13:42:08.045556 DQS0 = 0, DQS1 = 0
3666 13:42:08.045665 DQM Delay:
3667 13:42:08.049207 DQM0 = 120, DQM1 = 116
3668 13:42:08.049322 DQ Delay:
3669 13:42:08.052733 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3670 13:42:08.056023 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3671 13:42:08.059643 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3672 13:42:08.062646 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3673 13:42:08.062726
3674 13:42:08.062789
3675 13:42:08.072724 [DQSOSCAuto] RK1, (LSB)MR18= 0x13ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 402 ps
3676 13:42:08.076275 CH1 RK1: MR19=403, MR18=13EE
3677 13:42:08.079752 CH1_RK1: MR19=0x403, MR18=0x13EE, DQSOSC=402, MR23=63, INC=40, DEC=27
3678 13:42:08.082377 [RxdqsGatingPostProcess] freq 1200
3679 13:42:08.089290 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3680 13:42:08.092529 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 13:42:08.095724 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 13:42:08.099064 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 13:42:08.102514 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 13:42:08.105965 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 13:42:08.108910 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 13:42:08.112473 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 13:42:08.116113 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 13:42:08.116268 Pre-setting of DQS Precalculation
3689 13:42:08.122088 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3690 13:42:08.128709 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3691 13:42:08.135688 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3692 13:42:08.135806
3693 13:42:08.135881
3694 13:42:08.139271 [Calibration Summary] 2400 Mbps
3695 13:42:08.142282 CH 0, Rank 0
3696 13:42:08.142373 SW Impedance : PASS
3697 13:42:08.145251 DUTY Scan : NO K
3698 13:42:08.148913 ZQ Calibration : PASS
3699 13:42:08.148992 Jitter Meter : NO K
3700 13:42:08.152493 CBT Training : PASS
3701 13:42:08.155341 Write leveling : PASS
3702 13:42:08.155441 RX DQS gating : PASS
3703 13:42:08.158876 RX DQ/DQS(RDDQC) : PASS
3704 13:42:08.162388 TX DQ/DQS : PASS
3705 13:42:08.162490 RX DATLAT : PASS
3706 13:42:08.165158 RX DQ/DQS(Engine): PASS
3707 13:42:08.165267 TX OE : NO K
3708 13:42:08.168578 All Pass.
3709 13:42:08.168693
3710 13:42:08.168825 CH 0, Rank 1
3711 13:42:08.172261 SW Impedance : PASS
3712 13:42:08.172389 DUTY Scan : NO K
3713 13:42:08.175126 ZQ Calibration : PASS
3714 13:42:08.178954 Jitter Meter : NO K
3715 13:42:08.179053 CBT Training : PASS
3716 13:42:08.181926 Write leveling : PASS
3717 13:42:08.185645 RX DQS gating : PASS
3718 13:42:08.185740 RX DQ/DQS(RDDQC) : PASS
3719 13:42:08.188335 TX DQ/DQS : PASS
3720 13:42:08.191661 RX DATLAT : PASS
3721 13:42:08.191782 RX DQ/DQS(Engine): PASS
3722 13:42:08.195372 TX OE : NO K
3723 13:42:08.195487 All Pass.
3724 13:42:08.195576
3725 13:42:08.198714 CH 1, Rank 0
3726 13:42:08.198854 SW Impedance : PASS
3727 13:42:08.202108 DUTY Scan : NO K
3728 13:42:08.204868 ZQ Calibration : PASS
3729 13:42:08.204957 Jitter Meter : NO K
3730 13:42:08.208286 CBT Training : PASS
3731 13:42:08.212433 Write leveling : PASS
3732 13:42:08.212526 RX DQS gating : PASS
3733 13:42:08.215310 RX DQ/DQS(RDDQC) : PASS
3734 13:42:08.215415 TX DQ/DQS : PASS
3735 13:42:08.218339 RX DATLAT : PASS
3736 13:42:08.222046 RX DQ/DQS(Engine): PASS
3737 13:42:08.222126 TX OE : NO K
3738 13:42:08.225344 All Pass.
3739 13:42:08.225454
3740 13:42:08.225551 CH 1, Rank 1
3741 13:42:08.228447 SW Impedance : PASS
3742 13:42:08.228550 DUTY Scan : NO K
3743 13:42:08.231970 ZQ Calibration : PASS
3744 13:42:08.235568 Jitter Meter : NO K
3745 13:42:08.235674 CBT Training : PASS
3746 13:42:08.238495 Write leveling : PASS
3747 13:42:08.241488 RX DQS gating : PASS
3748 13:42:08.241590 RX DQ/DQS(RDDQC) : PASS
3749 13:42:08.245017 TX DQ/DQS : PASS
3750 13:42:08.248234 RX DATLAT : PASS
3751 13:42:08.248350 RX DQ/DQS(Engine): PASS
3752 13:42:08.251621 TX OE : NO K
3753 13:42:08.251724 All Pass.
3754 13:42:08.251817
3755 13:42:08.255224 DramC Write-DBI off
3756 13:42:08.258195 PER_BANK_REFRESH: Hybrid Mode
3757 13:42:08.258301 TX_TRACKING: ON
3758 13:42:08.268484 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3759 13:42:08.271987 [FAST_K] Save calibration result to emmc
3760 13:42:08.275428 dramc_set_vcore_voltage set vcore to 650000
3761 13:42:08.278230 Read voltage for 600, 5
3762 13:42:08.278333 Vio18 = 0
3763 13:42:08.278432 Vcore = 650000
3764 13:42:08.282010 Vdram = 0
3765 13:42:08.282094 Vddq = 0
3766 13:42:08.282158 Vmddr = 0
3767 13:42:08.288550 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3768 13:42:08.291528 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3769 13:42:08.295254 MEM_TYPE=3, freq_sel=19
3770 13:42:08.298122 sv_algorithm_assistance_LP4_1600
3771 13:42:08.301744 ============ PULL DRAM RESETB DOWN ============
3772 13:42:08.304661 ========== PULL DRAM RESETB DOWN end =========
3773 13:42:08.311814 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 13:42:08.314955 ===================================
3775 13:42:08.315065 LPDDR4 DRAM CONFIGURATION
3776 13:42:08.318447 ===================================
3777 13:42:08.321400 EX_ROW_EN[0] = 0x0
3778 13:42:08.324994 EX_ROW_EN[1] = 0x0
3779 13:42:08.325076 LP4Y_EN = 0x0
3780 13:42:08.328390 WORK_FSP = 0x0
3781 13:42:08.328472 WL = 0x2
3782 13:42:08.331799 RL = 0x2
3783 13:42:08.331880 BL = 0x2
3784 13:42:08.335020 RPST = 0x0
3785 13:42:08.335132 RD_PRE = 0x0
3786 13:42:08.338428 WR_PRE = 0x1
3787 13:42:08.338536 WR_PST = 0x0
3788 13:42:08.341467 DBI_WR = 0x0
3789 13:42:08.341575 DBI_RD = 0x0
3790 13:42:08.344783 OTF = 0x1
3791 13:42:08.348459 ===================================
3792 13:42:08.351301 ===================================
3793 13:42:08.351375 ANA top config
3794 13:42:08.354812 ===================================
3795 13:42:08.358180 DLL_ASYNC_EN = 0
3796 13:42:08.361447 ALL_SLAVE_EN = 1
3797 13:42:08.364748 NEW_RANK_MODE = 1
3798 13:42:08.364820 DLL_IDLE_MODE = 1
3799 13:42:08.367772 LP45_APHY_COMB_EN = 1
3800 13:42:08.371654 TX_ODT_DIS = 1
3801 13:42:08.374385 NEW_8X_MODE = 1
3802 13:42:08.378052 ===================================
3803 13:42:08.381474 ===================================
3804 13:42:08.384226 data_rate = 1200
3805 13:42:08.384308 CKR = 1
3806 13:42:08.387688 DQ_P2S_RATIO = 8
3807 13:42:08.391375 ===================================
3808 13:42:08.394860 CA_P2S_RATIO = 8
3809 13:42:08.397764 DQ_CA_OPEN = 0
3810 13:42:08.401400 DQ_SEMI_OPEN = 0
3811 13:42:08.404229 CA_SEMI_OPEN = 0
3812 13:42:08.404333 CA_FULL_RATE = 0
3813 13:42:08.408194 DQ_CKDIV4_EN = 1
3814 13:42:08.410871 CA_CKDIV4_EN = 1
3815 13:42:08.414502 CA_PREDIV_EN = 0
3816 13:42:08.417513 PH8_DLY = 0
3817 13:42:08.421099 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3818 13:42:08.421209 DQ_AAMCK_DIV = 4
3819 13:42:08.424817 CA_AAMCK_DIV = 4
3820 13:42:08.427740 CA_ADMCK_DIV = 4
3821 13:42:08.431316 DQ_TRACK_CA_EN = 0
3822 13:42:08.434338 CA_PICK = 600
3823 13:42:08.437904 CA_MCKIO = 600
3824 13:42:08.438008 MCKIO_SEMI = 0
3825 13:42:08.440763 PLL_FREQ = 2288
3826 13:42:08.444212 DQ_UI_PI_RATIO = 32
3827 13:42:08.447683 CA_UI_PI_RATIO = 0
3828 13:42:08.451104 ===================================
3829 13:42:08.454309 ===================================
3830 13:42:08.457668 memory_type:LPDDR4
3831 13:42:08.457747 GP_NUM : 10
3832 13:42:08.460808 SRAM_EN : 1
3833 13:42:08.464325 MD32_EN : 0
3834 13:42:08.467409 ===================================
3835 13:42:08.467490 [ANA_INIT] >>>>>>>>>>>>>>
3836 13:42:08.471013 <<<<<< [CONFIGURE PHASE]: ANA_TX
3837 13:42:08.473899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3838 13:42:08.477546 ===================================
3839 13:42:08.480761 data_rate = 1200,PCW = 0X5800
3840 13:42:08.484169 ===================================
3841 13:42:08.487888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3842 13:42:08.494266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 13:42:08.497894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 13:42:08.504297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3845 13:42:08.507242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3846 13:42:08.511046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3847 13:42:08.511129 [ANA_INIT] flow start
3848 13:42:08.513801 [ANA_INIT] PLL >>>>>>>>
3849 13:42:08.517590 [ANA_INIT] PLL <<<<<<<<
3850 13:42:08.520321 [ANA_INIT] MIDPI >>>>>>>>
3851 13:42:08.520414 [ANA_INIT] MIDPI <<<<<<<<
3852 13:42:08.524063 [ANA_INIT] DLL >>>>>>>>
3853 13:42:08.527514 [ANA_INIT] flow end
3854 13:42:08.530432 ============ LP4 DIFF to SE enter ============
3855 13:42:08.534219 ============ LP4 DIFF to SE exit ============
3856 13:42:08.537227 [ANA_INIT] <<<<<<<<<<<<<
3857 13:42:08.540876 [Flow] Enable top DCM control >>>>>
3858 13:42:08.544052 [Flow] Enable top DCM control <<<<<
3859 13:42:08.546789 Enable DLL master slave shuffle
3860 13:42:08.550370 ==============================================================
3861 13:42:08.554071 Gating Mode config
3862 13:42:08.557120 ==============================================================
3863 13:42:08.560405 Config description:
3864 13:42:08.570466 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3865 13:42:08.576955 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3866 13:42:08.580396 SELPH_MODE 0: By rank 1: By Phase
3867 13:42:08.586616 ==============================================================
3868 13:42:08.590075 GAT_TRACK_EN = 1
3869 13:42:08.593576 RX_GATING_MODE = 2
3870 13:42:08.596780 RX_GATING_TRACK_MODE = 2
3871 13:42:08.599930 SELPH_MODE = 1
3872 13:42:08.603713 PICG_EARLY_EN = 1
3873 13:42:08.603825 VALID_LAT_VALUE = 1
3874 13:42:08.610705 ==============================================================
3875 13:42:08.613848 Enter into Gating configuration >>>>
3876 13:42:08.616818 Exit from Gating configuration <<<<
3877 13:42:08.620576 Enter into DVFS_PRE_config >>>>>
3878 13:42:08.630530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3879 13:42:08.633915 Exit from DVFS_PRE_config <<<<<
3880 13:42:08.636971 Enter into PICG configuration >>>>
3881 13:42:08.640444 Exit from PICG configuration <<<<
3882 13:42:08.643404 [RX_INPUT] configuration >>>>>
3883 13:42:08.646985 [RX_INPUT] configuration <<<<<
3884 13:42:08.649874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3885 13:42:08.656460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3886 13:42:08.663654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 13:42:08.670488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 13:42:08.676845 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 13:42:08.683032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 13:42:08.686946 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3891 13:42:08.690253 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3892 13:42:08.693395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3893 13:42:08.699688 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3894 13:42:08.703124 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3895 13:42:08.706906 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 13:42:08.709767 ===================================
3897 13:42:08.713392 LPDDR4 DRAM CONFIGURATION
3898 13:42:08.716850 ===================================
3899 13:42:08.716941 EX_ROW_EN[0] = 0x0
3900 13:42:08.719562 EX_ROW_EN[1] = 0x0
3901 13:42:08.719688 LP4Y_EN = 0x0
3902 13:42:08.722901 WORK_FSP = 0x0
3903 13:42:08.723000 WL = 0x2
3904 13:42:08.725999 RL = 0x2
3905 13:42:08.729933 BL = 0x2
3906 13:42:08.730048 RPST = 0x0
3907 13:42:08.733040 RD_PRE = 0x0
3908 13:42:08.733113 WR_PRE = 0x1
3909 13:42:08.736580 WR_PST = 0x0
3910 13:42:08.736681 DBI_WR = 0x0
3911 13:42:08.740001 DBI_RD = 0x0
3912 13:42:08.740101 OTF = 0x1
3913 13:42:08.743344 ===================================
3914 13:42:08.746264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3915 13:42:08.752730 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3916 13:42:08.756299 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 13:42:08.760123 ===================================
3918 13:42:08.763202 LPDDR4 DRAM CONFIGURATION
3919 13:42:08.766067 ===================================
3920 13:42:08.766161 EX_ROW_EN[0] = 0x10
3921 13:42:08.769805 EX_ROW_EN[1] = 0x0
3922 13:42:08.769915 LP4Y_EN = 0x0
3923 13:42:08.772786 WORK_FSP = 0x0
3924 13:42:08.772866 WL = 0x2
3925 13:42:08.776479 RL = 0x2
3926 13:42:08.776574 BL = 0x2
3927 13:42:08.779396 RPST = 0x0
3928 13:42:08.779492 RD_PRE = 0x0
3929 13:42:08.783145 WR_PRE = 0x1
3930 13:42:08.785891 WR_PST = 0x0
3931 13:42:08.785988 DBI_WR = 0x0
3932 13:42:08.789475 DBI_RD = 0x0
3933 13:42:08.789572 OTF = 0x1
3934 13:42:08.793066 ===================================
3935 13:42:08.799432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3936 13:42:08.802918 nWR fixed to 30
3937 13:42:08.806111 [ModeRegInit_LP4] CH0 RK0
3938 13:42:08.806221 [ModeRegInit_LP4] CH0 RK1
3939 13:42:08.809624 [ModeRegInit_LP4] CH1 RK0
3940 13:42:08.812702 [ModeRegInit_LP4] CH1 RK1
3941 13:42:08.812798 match AC timing 17
3942 13:42:08.820018 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3943 13:42:08.822740 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3944 13:42:08.826440 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3945 13:42:08.833166 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3946 13:42:08.836647 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3947 13:42:08.836730 ==
3948 13:42:08.839546 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 13:42:08.843131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 13:42:08.843214 ==
3951 13:42:08.849652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 13:42:08.856123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3953 13:42:08.859403 [CA 0] Center 35 (5~66) winsize 62
3954 13:42:08.863201 [CA 1] Center 35 (5~66) winsize 62
3955 13:42:08.866427 [CA 2] Center 33 (3~64) winsize 62
3956 13:42:08.869518 [CA 3] Center 33 (2~64) winsize 63
3957 13:42:08.872498 [CA 4] Center 33 (2~64) winsize 63
3958 13:42:08.876127 [CA 5] Center 32 (2~63) winsize 62
3959 13:42:08.876209
3960 13:42:08.879799 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3961 13:42:08.879882
3962 13:42:08.882571 [CATrainingPosCal] consider 1 rank data
3963 13:42:08.886305 u2DelayCellTimex100 = 270/100 ps
3964 13:42:08.889246 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3965 13:42:08.892929 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3966 13:42:08.895865 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3967 13:42:08.899232 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3968 13:42:08.902877 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3969 13:42:08.909506 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3970 13:42:08.909588
3971 13:42:08.912484 CA PerBit enable=1, Macro0, CA PI delay=32
3972 13:42:08.912567
3973 13:42:08.915934 [CBTSetCACLKResult] CA Dly = 32
3974 13:42:08.916015 CS Dly: 5 (0~36)
3975 13:42:08.916080 ==
3976 13:42:08.919328 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 13:42:08.922656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 13:42:08.926117 ==
3979 13:42:08.929280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 13:42:08.935663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3981 13:42:08.939398 [CA 0] Center 36 (5~67) winsize 63
3982 13:42:08.942311 [CA 1] Center 35 (5~66) winsize 62
3983 13:42:08.945905 [CA 2] Center 34 (3~65) winsize 63
3984 13:42:08.948771 [CA 3] Center 33 (3~64) winsize 62
3985 13:42:08.952240 [CA 4] Center 33 (2~64) winsize 63
3986 13:42:08.955236 [CA 5] Center 32 (2~63) winsize 62
3987 13:42:08.955317
3988 13:42:08.958699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3989 13:42:08.958780
3990 13:42:08.962318 [CATrainingPosCal] consider 2 rank data
3991 13:42:08.965157 u2DelayCellTimex100 = 270/100 ps
3992 13:42:08.968735 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3993 13:42:08.972134 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3994 13:42:08.975604 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3995 13:42:08.982109 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3996 13:42:08.985346 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3997 13:42:08.988691 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3998 13:42:08.988773
3999 13:42:08.992262 CA PerBit enable=1, Macro0, CA PI delay=32
4000 13:42:08.992349
4001 13:42:08.995047 [CBTSetCACLKResult] CA Dly = 32
4002 13:42:08.995127 CS Dly: 5 (0~36)
4003 13:42:08.995190
4004 13:42:08.998757 ----->DramcWriteLeveling(PI) begin...
4005 13:42:08.998840 ==
4006 13:42:09.002331 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 13:42:09.008789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 13:42:09.008869 ==
4009 13:42:09.011738 Write leveling (Byte 0): 34 => 34
4010 13:42:09.015375 Write leveling (Byte 1): 31 => 31
4011 13:42:09.015469 DramcWriteLeveling(PI) end<-----
4012 13:42:09.015533
4013 13:42:09.018272 ==
4014 13:42:09.021922 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 13:42:09.025469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 13:42:09.025552 ==
4017 13:42:09.028333 [Gating] SW mode calibration
4018 13:42:09.035567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4019 13:42:09.039026 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4020 13:42:09.045626 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 13:42:09.048824 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 13:42:09.051857 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 13:42:09.058828 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
4024 13:42:09.062319 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
4025 13:42:09.065194 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 13:42:09.072246 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 13:42:09.075157 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 13:42:09.078778 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 13:42:09.085364 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 13:42:09.088782 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 13:42:09.092333 0 10 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
4032 13:42:09.095174 0 10 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
4033 13:42:09.102167 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 13:42:09.105514 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 13:42:09.108921 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 13:42:09.115672 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 13:42:09.118515 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 13:42:09.122398 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 13:42:09.128753 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 13:42:09.131680 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4041 13:42:09.135287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 13:42:09.141778 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 13:42:09.145232 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:42:09.148185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:42:09.155502 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:42:09.158349 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:42:09.161712 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:42:09.168535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:42:09.171796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 13:42:09.174937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 13:42:09.182041 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 13:42:09.185033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:42:09.188621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:42:09.194842 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:42:09.198593 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:42:09.201441 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4057 13:42:09.204998 Total UI for P1: 0, mck2ui 16
4058 13:42:09.208560 best dqsien dly found for B0: ( 0, 13, 14)
4059 13:42:09.211327 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:42:09.215113 Total UI for P1: 0, mck2ui 16
4061 13:42:09.218541 best dqsien dly found for B1: ( 0, 13, 16)
4062 13:42:09.225268 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4063 13:42:09.228032 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4064 13:42:09.228115
4065 13:42:09.231227 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4066 13:42:09.234924 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4067 13:42:09.238510 [Gating] SW calibration Done
4068 13:42:09.238592 ==
4069 13:42:09.241415 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 13:42:09.245136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 13:42:09.245219 ==
4072 13:42:09.248484 RX Vref Scan: 0
4073 13:42:09.248592
4074 13:42:09.248685 RX Vref 0 -> 0, step: 1
4075 13:42:09.248776
4076 13:42:09.251374 RX Delay -230 -> 252, step: 16
4077 13:42:09.255044 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4078 13:42:09.261469 iDelay=218, Bit 1, Center 65 (-86 ~ 217) 304
4079 13:42:09.265188 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4080 13:42:09.268162 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4081 13:42:09.271837 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4082 13:42:09.274591 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4083 13:42:09.281587 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4084 13:42:09.284658 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4085 13:42:09.287856 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4086 13:42:09.291366 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4087 13:42:09.294922 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4088 13:42:09.301303 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4089 13:42:09.304840 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4090 13:42:09.308398 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4091 13:42:09.311374 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4092 13:42:09.315004 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4093 13:42:09.317910 ==
4094 13:42:09.321533 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 13:42:09.324397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 13:42:09.324500 ==
4097 13:42:09.324596 DQS Delay:
4098 13:42:09.328046 DQS0 = 0, DQS1 = 0
4099 13:42:09.328170 DQM Delay:
4100 13:42:09.331529 DQM0 = 60, DQM1 = 51
4101 13:42:09.331611 DQ Delay:
4102 13:42:09.334948 DQ0 =57, DQ1 =65, DQ2 =57, DQ3 =57
4103 13:42:09.337676 DQ4 =65, DQ5 =49, DQ6 =65, DQ7 =65
4104 13:42:09.341059 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4105 13:42:09.345030 DQ12 =57, DQ13 =57, DQ14 =65, DQ15 =65
4106 13:42:09.345111
4107 13:42:09.345177
4108 13:42:09.345237 ==
4109 13:42:09.347881 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 13:42:09.351124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 13:42:09.351228 ==
4112 13:42:09.351322
4113 13:42:09.351410
4114 13:42:09.354630 TX Vref Scan disable
4115 13:42:09.357598 == TX Byte 0 ==
4116 13:42:09.361258 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4117 13:42:09.364979 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4118 13:42:09.367824 == TX Byte 1 ==
4119 13:42:09.371627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4120 13:42:09.374554 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4121 13:42:09.374658 ==
4122 13:42:09.378134 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 13:42:09.384188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 13:42:09.384305 ==
4125 13:42:09.384395
4126 13:42:09.384469
4127 13:42:09.384534 TX Vref Scan disable
4128 13:42:09.388709 == TX Byte 0 ==
4129 13:42:09.392287 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4130 13:42:09.398678 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4131 13:42:09.398765 == TX Byte 1 ==
4132 13:42:09.402056 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 13:42:09.408381 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 13:42:09.408459
4135 13:42:09.408531 [DATLAT]
4136 13:42:09.408592 Freq=600, CH0 RK0
4137 13:42:09.408651
4138 13:42:09.411975 DATLAT Default: 0x9
4139 13:42:09.412050 0, 0xFFFF, sum = 0
4140 13:42:09.415061 1, 0xFFFF, sum = 0
4141 13:42:09.415146 2, 0xFFFF, sum = 0
4142 13:42:09.418606 3, 0xFFFF, sum = 0
4143 13:42:09.421895 4, 0xFFFF, sum = 0
4144 13:42:09.421976 5, 0xFFFF, sum = 0
4145 13:42:09.425659 6, 0xFFFF, sum = 0
4146 13:42:09.425733 7, 0xFFFF, sum = 0
4147 13:42:09.428547 8, 0x0, sum = 1
4148 13:42:09.428618 9, 0x0, sum = 2
4149 13:42:09.428680 10, 0x0, sum = 3
4150 13:42:09.431716 11, 0x0, sum = 4
4151 13:42:09.431800 best_step = 9
4152 13:42:09.431863
4153 13:42:09.431922 ==
4154 13:42:09.435329 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 13:42:09.441972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 13:42:09.442075 ==
4157 13:42:09.442169 RX Vref Scan: 1
4158 13:42:09.442264
4159 13:42:09.445007 RX Vref 0 -> 0, step: 1
4160 13:42:09.445107
4161 13:42:09.448600 RX Delay -163 -> 252, step: 8
4162 13:42:09.448700
4163 13:42:09.452143 Set Vref, RX VrefLevel [Byte0]: 56
4164 13:42:09.455546 [Byte1]: 42
4165 13:42:09.455647
4166 13:42:09.458832 Final RX Vref Byte 0 = 56 to rank0
4167 13:42:09.462129 Final RX Vref Byte 1 = 42 to rank0
4168 13:42:09.465288 Final RX Vref Byte 0 = 56 to rank1
4169 13:42:09.468469 Final RX Vref Byte 1 = 42 to rank1==
4170 13:42:09.471893 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 13:42:09.475014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 13:42:09.475089 ==
4173 13:42:09.478387 DQS Delay:
4174 13:42:09.478466 DQS0 = 0, DQS1 = 0
4175 13:42:09.478531 DQM Delay:
4176 13:42:09.482074 DQM0 = 53, DQM1 = 45
4177 13:42:09.482148 DQ Delay:
4178 13:42:09.484915 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4179 13:42:09.488426 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4180 13:42:09.492037 DQ8 =36, DQ9 =32, DQ10 =44, DQ11 =40
4181 13:42:09.495153 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4182 13:42:09.495227
4183 13:42:09.495289
4184 13:42:09.505506 [DQSOSCAuto] RK0, (LSB)MR18= 0x7569, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4185 13:42:09.505584 CH0 RK0: MR19=808, MR18=7569
4186 13:42:09.511478 CH0_RK0: MR19=0x808, MR18=0x7569, DQSOSC=387, MR23=63, INC=175, DEC=116
4187 13:42:09.511563
4188 13:42:09.515063 ----->DramcWriteLeveling(PI) begin...
4189 13:42:09.518706 ==
4190 13:42:09.518785 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 13:42:09.525063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 13:42:09.525148 ==
4193 13:42:09.528564 Write leveling (Byte 0): 33 => 33
4194 13:42:09.532091 Write leveling (Byte 1): 30 => 30
4195 13:42:09.535580 DramcWriteLeveling(PI) end<-----
4196 13:42:09.535666
4197 13:42:09.535748 ==
4198 13:42:09.538825 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 13:42:09.542090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 13:42:09.542169 ==
4201 13:42:09.545115 [Gating] SW mode calibration
4202 13:42:09.551749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4203 13:42:09.555162 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4204 13:42:09.561757 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 13:42:09.565429 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 13:42:09.568281 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 13:42:09.575390 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 13:42:09.578410 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
4209 13:42:09.581772 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 13:42:09.588028 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 13:42:09.591826 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 13:42:09.595119 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 13:42:09.601779 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 13:42:09.604814 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 13:42:09.608555 0 10 12 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
4216 13:42:09.614466 0 10 16 | B1->B0 | 3e3e 4040 | 0 0 | (0 0) (0 0)
4217 13:42:09.618147 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 13:42:09.621139 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 13:42:09.628328 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 13:42:09.631176 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 13:42:09.634478 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 13:42:09.641111 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 13:42:09.644661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4224 13:42:09.648359 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4225 13:42:09.654669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 13:42:09.658138 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 13:42:09.661395 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:42:09.667975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:42:09.671358 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:42:09.674375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:42:09.681522 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 13:42:09.684438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 13:42:09.688015 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 13:42:09.691059 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 13:42:09.698140 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 13:42:09.700971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 13:42:09.704652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 13:42:09.711097 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 13:42:09.714385 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4240 13:42:09.717613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4241 13:42:09.721022 Total UI for P1: 0, mck2ui 16
4242 13:42:09.724514 best dqsien dly found for B0: ( 0, 13, 12)
4243 13:42:09.731078 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 13:42:09.734048 Total UI for P1: 0, mck2ui 16
4245 13:42:09.737688 best dqsien dly found for B1: ( 0, 13, 16)
4246 13:42:09.741141 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4247 13:42:09.744538 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4248 13:42:09.744643
4249 13:42:09.747452 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4250 13:42:09.751059 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4251 13:42:09.753978 [Gating] SW calibration Done
4252 13:42:09.754085 ==
4253 13:42:09.757659 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 13:42:09.760660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 13:42:09.760774 ==
4256 13:42:09.764371 RX Vref Scan: 0
4257 13:42:09.764460
4258 13:42:09.767054 RX Vref 0 -> 0, step: 1
4259 13:42:09.767165
4260 13:42:09.767266 RX Delay -230 -> 252, step: 16
4261 13:42:09.774347 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4262 13:42:09.777294 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4263 13:42:09.780933 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4264 13:42:09.783637 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4265 13:42:09.790799 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4266 13:42:09.794112 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4267 13:42:09.797132 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4268 13:42:09.800521 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4269 13:42:09.804210 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4270 13:42:09.810784 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4271 13:42:09.814246 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4272 13:42:09.817102 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4273 13:42:09.820844 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4274 13:42:09.827170 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4275 13:42:09.830504 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4276 13:42:09.833699 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4277 13:42:09.833806 ==
4278 13:42:09.837039 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 13:42:09.840612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 13:42:09.840724 ==
4281 13:42:09.843542 DQS Delay:
4282 13:42:09.843646 DQS0 = 0, DQS1 = 0
4283 13:42:09.847170 DQM Delay:
4284 13:42:09.847283 DQM0 = 53, DQM1 = 45
4285 13:42:09.847381 DQ Delay:
4286 13:42:09.850634 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4287 13:42:09.853524 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4288 13:42:09.857134 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4289 13:42:09.860128 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =49
4290 13:42:09.860237
4291 13:42:09.860343
4292 13:42:09.863693 ==
4293 13:42:09.863800 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 13:42:09.870097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 13:42:09.870207 ==
4296 13:42:09.870301
4297 13:42:09.870394
4298 13:42:09.873685 TX Vref Scan disable
4299 13:42:09.873788 == TX Byte 0 ==
4300 13:42:09.877248 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4301 13:42:09.883694 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4302 13:42:09.883809 == TX Byte 1 ==
4303 13:42:09.886644 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4304 13:42:09.893349 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4305 13:42:09.893461 ==
4306 13:42:09.896784 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 13:42:09.900476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 13:42:09.900561 ==
4309 13:42:09.900659
4310 13:42:09.900755
4311 13:42:09.903293 TX Vref Scan disable
4312 13:42:09.906589 == TX Byte 0 ==
4313 13:42:09.909933 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4314 13:42:09.913024 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4315 13:42:09.916902 == TX Byte 1 ==
4316 13:42:09.920071 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4317 13:42:09.923244 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4318 13:42:09.923353
4319 13:42:09.926599 [DATLAT]
4320 13:42:09.926707 Freq=600, CH0 RK1
4321 13:42:09.926802
4322 13:42:09.930344 DATLAT Default: 0x9
4323 13:42:09.930443 0, 0xFFFF, sum = 0
4324 13:42:09.933205 1, 0xFFFF, sum = 0
4325 13:42:09.933310 2, 0xFFFF, sum = 0
4326 13:42:09.937046 3, 0xFFFF, sum = 0
4327 13:42:09.937161 4, 0xFFFF, sum = 0
4328 13:42:09.939833 5, 0xFFFF, sum = 0
4329 13:42:09.939945 6, 0xFFFF, sum = 0
4330 13:42:09.943535 7, 0xFFFF, sum = 0
4331 13:42:09.943648 8, 0x0, sum = 1
4332 13:42:09.946798 9, 0x0, sum = 2
4333 13:42:09.946907 10, 0x0, sum = 3
4334 13:42:09.949511 11, 0x0, sum = 4
4335 13:42:09.949623 best_step = 9
4336 13:42:09.949721
4337 13:42:09.949812 ==
4338 13:42:09.952991 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 13:42:09.956362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 13:42:09.959517 ==
4341 13:42:09.959626 RX Vref Scan: 0
4342 13:42:09.959723
4343 13:42:09.963222 RX Vref 0 -> 0, step: 1
4344 13:42:09.963335
4345 13:42:09.966209 RX Delay -163 -> 252, step: 8
4346 13:42:09.969739 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4347 13:42:09.972674 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4348 13:42:09.979640 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4349 13:42:09.983335 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4350 13:42:09.986037 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4351 13:42:09.989559 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4352 13:42:09.993251 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4353 13:42:09.999725 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4354 13:42:10.002623 iDelay=205, Bit 8, Center 36 (-99 ~ 172) 272
4355 13:42:10.006448 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4356 13:42:10.009844 iDelay=205, Bit 10, Center 44 (-91 ~ 180) 272
4357 13:42:10.012978 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4358 13:42:10.019899 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4359 13:42:10.022664 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4360 13:42:10.026159 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4361 13:42:10.029447 iDelay=205, Bit 15, Center 56 (-83 ~ 196) 280
4362 13:42:10.029561 ==
4363 13:42:10.032611 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 13:42:10.039517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 13:42:10.039629 ==
4366 13:42:10.039728 DQS Delay:
4367 13:42:10.042677 DQS0 = 0, DQS1 = 0
4368 13:42:10.042795 DQM Delay:
4369 13:42:10.042894 DQM0 = 54, DQM1 = 45
4370 13:42:10.045833 DQ Delay:
4371 13:42:10.049513 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4372 13:42:10.053122 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4373 13:42:10.055804 DQ8 =36, DQ9 =32, DQ10 =44, DQ11 =40
4374 13:42:10.059467 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =56
4375 13:42:10.059573
4376 13:42:10.059668
4377 13:42:10.065837 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4378 13:42:10.068710 CH0 RK1: MR19=808, MR18=6425
4379 13:42:10.075847 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4380 13:42:10.079076 [RxdqsGatingPostProcess] freq 600
4381 13:42:10.082497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4382 13:42:10.085749 Pre-setting of DQS Precalculation
4383 13:42:10.091947 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4384 13:42:10.092057 ==
4385 13:42:10.095676 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 13:42:10.098539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 13:42:10.098649 ==
4388 13:42:10.105220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4389 13:42:10.111841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4390 13:42:10.115495 [CA 0] Center 36 (5~67) winsize 63
4391 13:42:10.119212 [CA 1] Center 36 (5~67) winsize 63
4392 13:42:10.122023 [CA 2] Center 35 (4~66) winsize 63
4393 13:42:10.125627 [CA 3] Center 34 (4~65) winsize 62
4394 13:42:10.129103 [CA 4] Center 34 (4~65) winsize 62
4395 13:42:10.132021 [CA 5] Center 34 (3~65) winsize 63
4396 13:42:10.132127
4397 13:42:10.135551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4398 13:42:10.135663
4399 13:42:10.139256 [CATrainingPosCal] consider 1 rank data
4400 13:42:10.142215 u2DelayCellTimex100 = 270/100 ps
4401 13:42:10.145552 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4402 13:42:10.149053 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4403 13:42:10.152178 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4404 13:42:10.155327 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 13:42:10.158824 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 13:42:10.162422 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4407 13:42:10.162533
4408 13:42:10.165145 CA PerBit enable=1, Macro0, CA PI delay=34
4409 13:42:10.169150
4410 13:42:10.169258 [CBTSetCACLKResult] CA Dly = 34
4411 13:42:10.172110 CS Dly: 5 (0~36)
4412 13:42:10.172213 ==
4413 13:42:10.175631 Dram Type= 6, Freq= 0, CH_1, rank 1
4414 13:42:10.178544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 13:42:10.178658 ==
4416 13:42:10.185476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 13:42:10.192184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4418 13:42:10.195368 [CA 0] Center 36 (5~67) winsize 63
4419 13:42:10.198801 [CA 1] Center 36 (5~67) winsize 63
4420 13:42:10.202056 [CA 2] Center 35 (4~66) winsize 63
4421 13:42:10.205359 [CA 3] Center 34 (4~65) winsize 62
4422 13:42:10.208932 [CA 4] Center 34 (4~65) winsize 62
4423 13:42:10.211674 [CA 5] Center 34 (3~65) winsize 63
4424 13:42:10.211784
4425 13:42:10.215309 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4426 13:42:10.215420
4427 13:42:10.218870 [CATrainingPosCal] consider 2 rank data
4428 13:42:10.221747 u2DelayCellTimex100 = 270/100 ps
4429 13:42:10.225418 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4430 13:42:10.228352 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4431 13:42:10.231922 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4432 13:42:10.235446 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4433 13:42:10.238404 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4434 13:42:10.242086 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4435 13:42:10.242199
4436 13:42:10.248670 CA PerBit enable=1, Macro0, CA PI delay=34
4437 13:42:10.248780
4438 13:42:10.248877 [CBTSetCACLKResult] CA Dly = 34
4439 13:42:10.251660 CS Dly: 5 (0~37)
4440 13:42:10.251732
4441 13:42:10.255307 ----->DramcWriteLeveling(PI) begin...
4442 13:42:10.255405 ==
4443 13:42:10.258735 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 13:42:10.261525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 13:42:10.261599 ==
4446 13:42:10.264878 Write leveling (Byte 0): 30 => 30
4447 13:42:10.268210 Write leveling (Byte 1): 30 => 30
4448 13:42:10.271549 DramcWriteLeveling(PI) end<-----
4449 13:42:10.271651
4450 13:42:10.271741 ==
4451 13:42:10.274938 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 13:42:10.281652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 13:42:10.281755 ==
4454 13:42:10.281840 [Gating] SW mode calibration
4455 13:42:10.291192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4456 13:42:10.294812 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4457 13:42:10.298589 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 13:42:10.305038 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 13:42:10.307843 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4460 13:42:10.311226 0 9 12 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
4461 13:42:10.318054 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 13:42:10.321446 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 13:42:10.324498 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 13:42:10.331722 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 13:42:10.334700 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 13:42:10.338267 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 13:42:10.344583 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4468 13:42:10.348172 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4469 13:42:10.351241 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 13:42:10.357816 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 13:42:10.361488 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 13:42:10.364466 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 13:42:10.371356 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:42:10.374831 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:42:10.377866 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 13:42:10.384416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4477 13:42:10.387736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4478 13:42:10.391287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:42:10.397426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:42:10.401143 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:42:10.404740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:42:10.411274 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:42:10.414292 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:42:10.417722 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:42:10.424235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:42:10.427877 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 13:42:10.430774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 13:42:10.434299 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:42:10.440971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:42:10.444256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:42:10.447752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4492 13:42:10.453895 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4493 13:42:10.457622 Total UI for P1: 0, mck2ui 16
4494 13:42:10.460367 best dqsien dly found for B1: ( 0, 13, 10)
4495 13:42:10.464032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 13:42:10.467560 Total UI for P1: 0, mck2ui 16
4497 13:42:10.470410 best dqsien dly found for B0: ( 0, 13, 10)
4498 13:42:10.474658 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4499 13:42:10.477390 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4500 13:42:10.477501
4501 13:42:10.480956 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4502 13:42:10.487398 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4503 13:42:10.487513 [Gating] SW calibration Done
4504 13:42:10.487610 ==
4505 13:42:10.490997 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 13:42:10.497103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 13:42:10.497214 ==
4508 13:42:10.497320 RX Vref Scan: 0
4509 13:42:10.497412
4510 13:42:10.500640 RX Vref 0 -> 0, step: 1
4511 13:42:10.500743
4512 13:42:10.504074 RX Delay -230 -> 252, step: 16
4513 13:42:10.507547 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4514 13:42:10.510719 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4515 13:42:10.513949 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4516 13:42:10.520979 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4517 13:42:10.523865 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4518 13:42:10.527426 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4519 13:42:10.530356 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4520 13:42:10.536953 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4521 13:42:10.540748 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4522 13:42:10.543691 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4523 13:42:10.547304 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4524 13:42:10.550531 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4525 13:42:10.557015 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4526 13:42:10.560468 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4527 13:42:10.563746 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4528 13:42:10.566885 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4529 13:42:10.570295 ==
4530 13:42:10.573882 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 13:42:10.576733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 13:42:10.576840 ==
4533 13:42:10.576936 DQS Delay:
4534 13:42:10.580330 DQS0 = 0, DQS1 = 0
4535 13:42:10.580409 DQM Delay:
4536 13:42:10.583124 DQM0 = 51, DQM1 = 48
4537 13:42:10.583200 DQ Delay:
4538 13:42:10.586695 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4539 13:42:10.589574 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4540 13:42:10.593357 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4541 13:42:10.596380 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4542 13:42:10.596455
4543 13:42:10.596518
4544 13:42:10.596580 ==
4545 13:42:10.599630 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 13:42:10.603166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 13:42:10.603252 ==
4548 13:42:10.603315
4549 13:42:10.603374
4550 13:42:10.606214 TX Vref Scan disable
4551 13:42:10.609947 == TX Byte 0 ==
4552 13:42:10.613330 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4553 13:42:10.616197 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4554 13:42:10.619678 == TX Byte 1 ==
4555 13:42:10.622953 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 13:42:10.626224 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 13:42:10.626337 ==
4558 13:42:10.629907 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 13:42:10.636604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 13:42:10.636690 ==
4561 13:42:10.636757
4562 13:42:10.636818
4563 13:42:10.636879 TX Vref Scan disable
4564 13:42:10.641062 == TX Byte 0 ==
4565 13:42:10.644131 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 13:42:10.647141 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 13:42:10.650600 == TX Byte 1 ==
4568 13:42:10.654104 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 13:42:10.657476 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 13:42:10.660449
4571 13:42:10.660523 [DATLAT]
4572 13:42:10.660587 Freq=600, CH1 RK0
4573 13:42:10.660668
4574 13:42:10.664182 DATLAT Default: 0x9
4575 13:42:10.664286 0, 0xFFFF, sum = 0
4576 13:42:10.667069 1, 0xFFFF, sum = 0
4577 13:42:10.667168 2, 0xFFFF, sum = 0
4578 13:42:10.670556 3, 0xFFFF, sum = 0
4579 13:42:10.670657 4, 0xFFFF, sum = 0
4580 13:42:10.674037 5, 0xFFFF, sum = 0
4581 13:42:10.677466 6, 0xFFFF, sum = 0
4582 13:42:10.677566 7, 0xFFFF, sum = 0
4583 13:42:10.680741 8, 0x0, sum = 1
4584 13:42:10.680816 9, 0x0, sum = 2
4585 13:42:10.680879 10, 0x0, sum = 3
4586 13:42:10.683807 11, 0x0, sum = 4
4587 13:42:10.683887 best_step = 9
4588 13:42:10.683948
4589 13:42:10.684007 ==
4590 13:42:10.687187 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 13:42:10.694048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 13:42:10.694139 ==
4593 13:42:10.694205 RX Vref Scan: 1
4594 13:42:10.694266
4595 13:42:10.697416 RX Vref 0 -> 0, step: 1
4596 13:42:10.697484
4597 13:42:10.700357 RX Delay -163 -> 252, step: 8
4598 13:42:10.700457
4599 13:42:10.703917 Set Vref, RX VrefLevel [Byte0]: 55
4600 13:42:10.707452 [Byte1]: 48
4601 13:42:10.707554
4602 13:42:10.710813 Final RX Vref Byte 0 = 55 to rank0
4603 13:42:10.713476 Final RX Vref Byte 1 = 48 to rank0
4604 13:42:10.717007 Final RX Vref Byte 0 = 55 to rank1
4605 13:42:10.720843 Final RX Vref Byte 1 = 48 to rank1==
4606 13:42:10.723577 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 13:42:10.727197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 13:42:10.727299 ==
4609 13:42:10.730703 DQS Delay:
4610 13:42:10.730802 DQS0 = 0, DQS1 = 0
4611 13:42:10.730903 DQM Delay:
4612 13:42:10.733446 DQM0 = 49, DQM1 = 45
4613 13:42:10.733543 DQ Delay:
4614 13:42:10.737504 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4615 13:42:10.740758 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4616 13:42:10.743501 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4617 13:42:10.747059 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4618 13:42:10.747162
4619 13:42:10.747255
4620 13:42:10.757328 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4621 13:42:10.757435 CH1 RK0: MR19=808, MR18=476C
4622 13:42:10.764082 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4623 13:42:10.764185
4624 13:42:10.767075 ----->DramcWriteLeveling(PI) begin...
4625 13:42:10.770776 ==
4626 13:42:10.770850 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 13:42:10.777462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 13:42:10.777539 ==
4629 13:42:10.780401 Write leveling (Byte 0): 29 => 29
4630 13:42:10.783957 Write leveling (Byte 1): 32 => 32
4631 13:42:10.786745 DramcWriteLeveling(PI) end<-----
4632 13:42:10.786843
4633 13:42:10.786935 ==
4634 13:42:10.790316 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 13:42:10.793787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 13:42:10.793891 ==
4637 13:42:10.796837 [Gating] SW mode calibration
4638 13:42:10.803539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4639 13:42:10.806649 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4640 13:42:10.813796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 13:42:10.816944 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 13:42:10.820159 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 13:42:10.827055 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4644 13:42:10.830045 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 13:42:10.833753 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 13:42:10.840302 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 13:42:10.843798 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 13:42:10.846784 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 13:42:10.853470 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 13:42:10.856975 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4651 13:42:10.859970 0 10 12 | B1->B0 | 3939 3535 | 1 0 | (0 0) (1 1)
4652 13:42:10.866632 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 13:42:10.870201 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 13:42:10.873607 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 13:42:10.880301 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 13:42:10.883413 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 13:42:10.887200 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 13:42:10.893851 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 13:42:10.896713 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4660 13:42:10.900322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:42:10.906825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:42:10.910425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:42:10.913496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:42:10.917058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:42:10.923330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:42:10.926922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 13:42:10.929749 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 13:42:10.936474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 13:42:10.940080 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 13:42:10.943056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 13:42:10.949861 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 13:42:10.953384 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 13:42:10.956873 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 13:42:10.963018 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 13:42:10.966410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 13:42:10.969880 Total UI for P1: 0, mck2ui 16
4677 13:42:10.972914 best dqsien dly found for B0: ( 0, 13, 10)
4678 13:42:10.976568 Total UI for P1: 0, mck2ui 16
4679 13:42:10.980012 best dqsien dly found for B1: ( 0, 13, 10)
4680 13:42:10.982735 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4681 13:42:10.986331 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4682 13:42:10.986411
4683 13:42:10.990049 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4684 13:42:10.992981 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4685 13:42:10.996643 [Gating] SW calibration Done
4686 13:42:10.996718 ==
4687 13:42:10.999602 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 13:42:11.006077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 13:42:11.006186 ==
4690 13:42:11.006279 RX Vref Scan: 0
4691 13:42:11.006373
4692 13:42:11.009869 RX Vref 0 -> 0, step: 1
4693 13:42:11.009963
4694 13:42:11.012678 RX Delay -230 -> 252, step: 16
4695 13:42:11.016321 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4696 13:42:11.019280 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4697 13:42:11.022924 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4698 13:42:11.029400 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4699 13:42:11.032964 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4700 13:42:11.035939 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4701 13:42:11.039597 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4702 13:42:11.042629 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4703 13:42:11.049672 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4704 13:42:11.052980 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4705 13:42:11.056212 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4706 13:42:11.059466 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4707 13:42:11.066010 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4708 13:42:11.069767 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4709 13:42:11.073108 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4710 13:42:11.075691 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4711 13:42:11.075769 ==
4712 13:42:11.078996 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 13:42:11.086000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 13:42:11.086113 ==
4715 13:42:11.086214 DQS Delay:
4716 13:42:11.089301 DQS0 = 0, DQS1 = 0
4717 13:42:11.089404 DQM Delay:
4718 13:42:11.089480 DQM0 = 52, DQM1 = 49
4719 13:42:11.092843 DQ Delay:
4720 13:42:11.096516 DQ0 =65, DQ1 =49, DQ2 =33, DQ3 =49
4721 13:42:11.099445 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =49
4722 13:42:11.103004 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4723 13:42:11.105985 DQ12 =57, DQ13 =65, DQ14 =49, DQ15 =65
4724 13:42:11.106091
4725 13:42:11.106189
4726 13:42:11.106284 ==
4727 13:42:11.109503 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 13:42:11.112371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 13:42:11.112448 ==
4730 13:42:11.112511
4731 13:42:11.112575
4732 13:42:11.115956 TX Vref Scan disable
4733 13:42:11.116060 == TX Byte 0 ==
4734 13:42:11.122464 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 13:42:11.125994 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 13:42:11.126098 == TX Byte 1 ==
4737 13:42:11.132327 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 13:42:11.135960 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 13:42:11.136070 ==
4740 13:42:11.138857 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 13:42:11.142482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 13:42:11.142572 ==
4743 13:42:11.142638
4744 13:42:11.146024
4745 13:42:11.146093 TX Vref Scan disable
4746 13:42:11.149716 == TX Byte 0 ==
4747 13:42:11.152474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4748 13:42:11.156246 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4749 13:42:11.159093 == TX Byte 1 ==
4750 13:42:11.162641 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4751 13:42:11.165976 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4752 13:42:11.169620
4753 13:42:11.169719 [DATLAT]
4754 13:42:11.169808 Freq=600, CH1 RK1
4755 13:42:11.169896
4756 13:42:11.172422 DATLAT Default: 0x9
4757 13:42:11.172533 0, 0xFFFF, sum = 0
4758 13:42:11.176422 1, 0xFFFF, sum = 0
4759 13:42:11.176517 2, 0xFFFF, sum = 0
4760 13:42:11.179734 3, 0xFFFF, sum = 0
4761 13:42:11.179836 4, 0xFFFF, sum = 0
4762 13:42:11.182948 5, 0xFFFF, sum = 0
4763 13:42:11.183090 6, 0xFFFF, sum = 0
4764 13:42:11.186321 7, 0xFFFF, sum = 0
4765 13:42:11.186402 8, 0x0, sum = 1
4766 13:42:11.189590 9, 0x0, sum = 2
4767 13:42:11.189708 10, 0x0, sum = 3
4768 13:42:11.193039 11, 0x0, sum = 4
4769 13:42:11.193148 best_step = 9
4770 13:42:11.193244
4771 13:42:11.193339 ==
4772 13:42:11.196323 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 13:42:11.199868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 13:42:11.202932 ==
4775 13:42:11.203044 RX Vref Scan: 0
4776 13:42:11.203141
4777 13:42:11.206442 RX Vref 0 -> 0, step: 1
4778 13:42:11.206543
4779 13:42:11.209429 RX Delay -163 -> 252, step: 8
4780 13:42:11.212823 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4781 13:42:11.215879 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4782 13:42:11.222710 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4783 13:42:11.225799 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4784 13:42:11.229338 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4785 13:42:11.232318 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4786 13:42:11.235999 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4787 13:42:11.242412 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4788 13:42:11.245974 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4789 13:42:11.248841 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4790 13:42:11.252421 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4791 13:42:11.259061 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4792 13:42:11.262059 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4793 13:42:11.265800 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4794 13:42:11.269310 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4795 13:42:11.272175 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4796 13:42:11.275802 ==
4797 13:42:11.275910 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 13:42:11.282395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 13:42:11.282504 ==
4800 13:42:11.282600 DQS Delay:
4801 13:42:11.285331 DQS0 = 0, DQS1 = 0
4802 13:42:11.285445 DQM Delay:
4803 13:42:11.288933 DQM0 = 48, DQM1 = 45
4804 13:42:11.289008 DQ Delay:
4805 13:42:11.292130 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4806 13:42:11.295291 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4807 13:42:11.299020 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4808 13:42:11.302671 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4809 13:42:11.302754
4810 13:42:11.302820
4811 13:42:11.309195 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4812 13:42:11.312087 CH1 RK1: MR19=808, MR18=6E24
4813 13:42:11.319073 CH1_RK1: MR19=0x808, MR18=0x6E24, DQSOSC=389, MR23=63, INC=173, DEC=115
4814 13:42:11.322489 [RxdqsGatingPostProcess] freq 600
4815 13:42:11.328855 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 13:42:11.328937 Pre-setting of DQS Precalculation
4817 13:42:11.334948 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 13:42:11.342263 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 13:42:11.348455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 13:42:11.348562
4821 13:42:11.348665
4822 13:42:11.351936 [Calibration Summary] 1200 Mbps
4823 13:42:11.355563 CH 0, Rank 0
4824 13:42:11.355643 SW Impedance : PASS
4825 13:42:11.358501 DUTY Scan : NO K
4826 13:42:11.358573 ZQ Calibration : PASS
4827 13:42:11.362126 Jitter Meter : NO K
4828 13:42:11.365018 CBT Training : PASS
4829 13:42:11.365090 Write leveling : PASS
4830 13:42:11.368625 RX DQS gating : PASS
4831 13:42:11.371486 RX DQ/DQS(RDDQC) : PASS
4832 13:42:11.371553 TX DQ/DQS : PASS
4833 13:42:11.374846 RX DATLAT : PASS
4834 13:42:11.378593 RX DQ/DQS(Engine): PASS
4835 13:42:11.378665 TX OE : NO K
4836 13:42:11.382069 All Pass.
4837 13:42:11.382139
4838 13:42:11.382203 CH 0, Rank 1
4839 13:42:11.384979 SW Impedance : PASS
4840 13:42:11.385055 DUTY Scan : NO K
4841 13:42:11.388669 ZQ Calibration : PASS
4842 13:42:11.391699 Jitter Meter : NO K
4843 13:42:11.391770 CBT Training : PASS
4844 13:42:11.394631 Write leveling : PASS
4845 13:42:11.398291 RX DQS gating : PASS
4846 13:42:11.398362 RX DQ/DQS(RDDQC) : PASS
4847 13:42:11.401594 TX DQ/DQS : PASS
4848 13:42:11.404946 RX DATLAT : PASS
4849 13:42:11.405021 RX DQ/DQS(Engine): PASS
4850 13:42:11.408402 TX OE : NO K
4851 13:42:11.408477 All Pass.
4852 13:42:11.408540
4853 13:42:11.411675 CH 1, Rank 0
4854 13:42:11.411771 SW Impedance : PASS
4855 13:42:11.414918 DUTY Scan : NO K
4856 13:42:11.415023 ZQ Calibration : PASS
4857 13:42:11.418532 Jitter Meter : NO K
4858 13:42:11.421372 CBT Training : PASS
4859 13:42:11.421483 Write leveling : PASS
4860 13:42:11.424973 RX DQS gating : PASS
4861 13:42:11.428576 RX DQ/DQS(RDDQC) : PASS
4862 13:42:11.428678 TX DQ/DQS : PASS
4863 13:42:11.431423 RX DATLAT : PASS
4864 13:42:11.435029 RX DQ/DQS(Engine): PASS
4865 13:42:11.435130 TX OE : NO K
4866 13:42:11.438526 All Pass.
4867 13:42:11.438628
4868 13:42:11.438725 CH 1, Rank 1
4869 13:42:11.442050 SW Impedance : PASS
4870 13:42:11.442153 DUTY Scan : NO K
4871 13:42:11.445476 ZQ Calibration : PASS
4872 13:42:11.448817 Jitter Meter : NO K
4873 13:42:11.448927 CBT Training : PASS
4874 13:42:11.451497 Write leveling : PASS
4875 13:42:11.451576 RX DQS gating : PASS
4876 13:42:11.455251 RX DQ/DQS(RDDQC) : PASS
4877 13:42:11.458308 TX DQ/DQS : PASS
4878 13:42:11.458411 RX DATLAT : PASS
4879 13:42:11.462097 RX DQ/DQS(Engine): PASS
4880 13:42:11.465315 TX OE : NO K
4881 13:42:11.465399 All Pass.
4882 13:42:11.465465
4883 13:42:11.468242 DramC Write-DBI off
4884 13:42:11.468364 PER_BANK_REFRESH: Hybrid Mode
4885 13:42:11.471799 TX_TRACKING: ON
4886 13:42:11.478347 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 13:42:11.485374 [FAST_K] Save calibration result to emmc
4888 13:42:11.488308 dramc_set_vcore_voltage set vcore to 662500
4889 13:42:11.488414 Read voltage for 933, 3
4890 13:42:11.491732 Vio18 = 0
4891 13:42:11.491840 Vcore = 662500
4892 13:42:11.491934 Vdram = 0
4893 13:42:11.494755 Vddq = 0
4894 13:42:11.494860 Vmddr = 0
4895 13:42:11.498645 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 13:42:11.505259 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 13:42:11.508075 MEM_TYPE=3, freq_sel=17
4898 13:42:11.511654 sv_algorithm_assistance_LP4_1600
4899 13:42:11.514588 ============ PULL DRAM RESETB DOWN ============
4900 13:42:11.518129 ========== PULL DRAM RESETB DOWN end =========
4901 13:42:11.524575 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 13:42:11.528321 ===================================
4903 13:42:11.528427 LPDDR4 DRAM CONFIGURATION
4904 13:42:11.531234 ===================================
4905 13:42:11.534710 EX_ROW_EN[0] = 0x0
4906 13:42:11.534816 EX_ROW_EN[1] = 0x0
4907 13:42:11.538333 LP4Y_EN = 0x0
4908 13:42:11.538416 WORK_FSP = 0x0
4909 13:42:11.541305 WL = 0x3
4910 13:42:11.541413 RL = 0x3
4911 13:42:11.545014 BL = 0x2
4912 13:42:11.547836 RPST = 0x0
4913 13:42:11.547918 RD_PRE = 0x0
4914 13:42:11.551478 WR_PRE = 0x1
4915 13:42:11.551561 WR_PST = 0x0
4916 13:42:11.554420 DBI_WR = 0x0
4917 13:42:11.554502 DBI_RD = 0x0
4918 13:42:11.558160 OTF = 0x1
4919 13:42:11.561099 ===================================
4920 13:42:11.564575 ===================================
4921 13:42:11.564659 ANA top config
4922 13:42:11.567841 ===================================
4923 13:42:11.571249 DLL_ASYNC_EN = 0
4924 13:42:11.574501 ALL_SLAVE_EN = 1
4925 13:42:11.574584 NEW_RANK_MODE = 1
4926 13:42:11.577817 DLL_IDLE_MODE = 1
4927 13:42:11.581215 LP45_APHY_COMB_EN = 1
4928 13:42:11.584414 TX_ODT_DIS = 1
4929 13:42:11.584526 NEW_8X_MODE = 1
4930 13:42:11.588540 ===================================
4931 13:42:11.591328 ===================================
4932 13:42:11.594736 data_rate = 1866
4933 13:42:11.597990 CKR = 1
4934 13:42:11.601687 DQ_P2S_RATIO = 8
4935 13:42:11.604605 ===================================
4936 13:42:11.608204 CA_P2S_RATIO = 8
4937 13:42:11.611782 DQ_CA_OPEN = 0
4938 13:42:11.611894 DQ_SEMI_OPEN = 0
4939 13:42:11.614696 CA_SEMI_OPEN = 0
4940 13:42:11.618209 CA_FULL_RATE = 0
4941 13:42:11.621197 DQ_CKDIV4_EN = 1
4942 13:42:11.624960 CA_CKDIV4_EN = 1
4943 13:42:11.627946 CA_PREDIV_EN = 0
4944 13:42:11.628029 PH8_DLY = 0
4945 13:42:11.631433 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 13:42:11.634833 DQ_AAMCK_DIV = 4
4947 13:42:11.638215 CA_AAMCK_DIV = 4
4948 13:42:11.641597 CA_ADMCK_DIV = 4
4949 13:42:11.644219 DQ_TRACK_CA_EN = 0
4950 13:42:11.644301 CA_PICK = 933
4951 13:42:11.647542 CA_MCKIO = 933
4952 13:42:11.651444 MCKIO_SEMI = 0
4953 13:42:11.654782 PLL_FREQ = 3732
4954 13:42:11.657798 DQ_UI_PI_RATIO = 32
4955 13:42:11.661405 CA_UI_PI_RATIO = 0
4956 13:42:11.664333 ===================================
4957 13:42:11.668092 ===================================
4958 13:42:11.671005 memory_type:LPDDR4
4959 13:42:11.671088 GP_NUM : 10
4960 13:42:11.674526 SRAM_EN : 1
4961 13:42:11.674636 MD32_EN : 0
4962 13:42:11.677526 ===================================
4963 13:42:11.680983 [ANA_INIT] >>>>>>>>>>>>>>
4964 13:42:11.684456 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 13:42:11.687233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 13:42:11.690727 ===================================
4967 13:42:11.694125 data_rate = 1866,PCW = 0X8f00
4968 13:42:11.697742 ===================================
4969 13:42:11.700600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 13:42:11.704027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 13:42:11.710775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 13:42:11.713963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 13:42:11.720673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 13:42:11.724114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 13:42:11.724199 [ANA_INIT] flow start
4976 13:42:11.727077 [ANA_INIT] PLL >>>>>>>>
4977 13:42:11.730757 [ANA_INIT] PLL <<<<<<<<
4978 13:42:11.730840 [ANA_INIT] MIDPI >>>>>>>>
4979 13:42:11.733673 [ANA_INIT] MIDPI <<<<<<<<
4980 13:42:11.737343 [ANA_INIT] DLL >>>>>>>>
4981 13:42:11.737427 [ANA_INIT] flow end
4982 13:42:11.740358 ============ LP4 DIFF to SE enter ============
4983 13:42:11.747559 ============ LP4 DIFF to SE exit ============
4984 13:42:11.747643 [ANA_INIT] <<<<<<<<<<<<<
4985 13:42:11.750603 [Flow] Enable top DCM control >>>>>
4986 13:42:11.754057 [Flow] Enable top DCM control <<<<<
4987 13:42:11.757653 Enable DLL master slave shuffle
4988 13:42:11.763577 ==============================================================
4989 13:42:11.763661 Gating Mode config
4990 13:42:11.770518 ==============================================================
4991 13:42:11.773656 Config description:
4992 13:42:11.783973 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 13:42:11.790389 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 13:42:11.794082 SELPH_MODE 0: By rank 1: By Phase
4995 13:42:11.800622 ==============================================================
4996 13:42:11.803556 GAT_TRACK_EN = 1
4997 13:42:11.807123 RX_GATING_MODE = 2
4998 13:42:11.807227 RX_GATING_TRACK_MODE = 2
4999 13:42:11.810096 SELPH_MODE = 1
5000 13:42:11.813701 PICG_EARLY_EN = 1
5001 13:42:11.817390 VALID_LAT_VALUE = 1
5002 13:42:11.823454 ==============================================================
5003 13:42:11.826755 Enter into Gating configuration >>>>
5004 13:42:11.830753 Exit from Gating configuration <<<<
5005 13:42:11.833669 Enter into DVFS_PRE_config >>>>>
5006 13:42:11.843877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 13:42:11.846883 Exit from DVFS_PRE_config <<<<<
5008 13:42:11.850491 Enter into PICG configuration >>>>
5009 13:42:11.853455 Exit from PICG configuration <<<<
5010 13:42:11.857079 [RX_INPUT] configuration >>>>>
5011 13:42:11.860002 [RX_INPUT] configuration <<<<<
5012 13:42:11.863551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 13:42:11.870145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 13:42:11.876990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 13:42:11.883584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 13:42:11.886799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 13:42:11.893547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 13:42:11.896924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 13:42:11.903230 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 13:42:11.906718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 13:42:11.910373 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 13:42:11.913193 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 13:42:11.920400 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 13:42:11.923327 ===================================
5025 13:42:11.923429 LPDDR4 DRAM CONFIGURATION
5026 13:42:11.927017 ===================================
5027 13:42:11.930046 EX_ROW_EN[0] = 0x0
5028 13:42:11.933533 EX_ROW_EN[1] = 0x0
5029 13:42:11.933634 LP4Y_EN = 0x0
5030 13:42:11.937114 WORK_FSP = 0x0
5031 13:42:11.937202 WL = 0x3
5032 13:42:11.940443 RL = 0x3
5033 13:42:11.940530 BL = 0x2
5034 13:42:11.943171 RPST = 0x0
5035 13:42:11.943290 RD_PRE = 0x0
5036 13:42:11.946684 WR_PRE = 0x1
5037 13:42:11.946794 WR_PST = 0x0
5038 13:42:11.949883 DBI_WR = 0x0
5039 13:42:11.950027 DBI_RD = 0x0
5040 13:42:11.953165 OTF = 0x1
5041 13:42:11.956927 ===================================
5042 13:42:11.960124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 13:42:11.963673 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 13:42:11.970197 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 13:42:11.973802 ===================================
5046 13:42:11.973895 LPDDR4 DRAM CONFIGURATION
5047 13:42:11.976763 ===================================
5048 13:42:11.980491 EX_ROW_EN[0] = 0x10
5049 13:42:11.980573 EX_ROW_EN[1] = 0x0
5050 13:42:11.983328 LP4Y_EN = 0x0
5051 13:42:11.986722 WORK_FSP = 0x0
5052 13:42:11.986803 WL = 0x3
5053 13:42:11.990402 RL = 0x3
5054 13:42:11.990492 BL = 0x2
5055 13:42:11.993058 RPST = 0x0
5056 13:42:11.993145 RD_PRE = 0x0
5057 13:42:11.996402 WR_PRE = 0x1
5058 13:42:11.996518 WR_PST = 0x0
5059 13:42:11.999810 DBI_WR = 0x0
5060 13:42:11.999919 DBI_RD = 0x0
5061 13:42:12.003158 OTF = 0x1
5062 13:42:12.006316 ===================================
5063 13:42:12.010155 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 13:42:12.015827 nWR fixed to 30
5065 13:42:12.018687 [ModeRegInit_LP4] CH0 RK0
5066 13:42:12.018803 [ModeRegInit_LP4] CH0 RK1
5067 13:42:12.022309 [ModeRegInit_LP4] CH1 RK0
5068 13:42:12.025919 [ModeRegInit_LP4] CH1 RK1
5069 13:42:12.026004 match AC timing 9
5070 13:42:12.032319 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 13:42:12.035300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 13:42:12.038889 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 13:42:12.045346 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 13:42:12.048996 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 13:42:12.049103 ==
5076 13:42:12.051804 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 13:42:12.055468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 13:42:12.055602 ==
5079 13:42:12.061759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 13:42:12.068632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5081 13:42:12.072285 [CA 0] Center 37 (6~68) winsize 63
5082 13:42:12.075538 [CA 1] Center 37 (6~68) winsize 63
5083 13:42:12.078732 [CA 2] Center 34 (4~65) winsize 62
5084 13:42:12.082093 [CA 3] Center 34 (3~65) winsize 63
5085 13:42:12.085081 [CA 4] Center 33 (3~63) winsize 61
5086 13:42:12.088647 [CA 5] Center 32 (2~62) winsize 61
5087 13:42:12.088734
5088 13:42:12.092255 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5089 13:42:12.092384
5090 13:42:12.095249 [CATrainingPosCal] consider 1 rank data
5091 13:42:12.098742 u2DelayCellTimex100 = 270/100 ps
5092 13:42:12.102175 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5093 13:42:12.105698 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5094 13:42:12.108638 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5095 13:42:12.112322 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5096 13:42:12.115364 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5097 13:42:12.118772 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5098 13:42:12.121988
5099 13:42:12.125384 CA PerBit enable=1, Macro0, CA PI delay=32
5100 13:42:12.125472
5101 13:42:12.128320 [CBTSetCACLKResult] CA Dly = 32
5102 13:42:12.128422 CS Dly: 5 (0~36)
5103 13:42:12.128490 ==
5104 13:42:12.132198 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 13:42:12.135415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 13:42:12.135500 ==
5107 13:42:12.142119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 13:42:12.148089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 13:42:12.151482 [CA 0] Center 37 (6~68) winsize 63
5110 13:42:12.154994 [CA 1] Center 37 (6~68) winsize 63
5111 13:42:12.158630 [CA 2] Center 34 (4~65) winsize 62
5112 13:42:12.161472 [CA 3] Center 34 (3~65) winsize 63
5113 13:42:12.165127 [CA 4] Center 33 (3~63) winsize 61
5114 13:42:12.168563 [CA 5] Center 32 (2~62) winsize 61
5115 13:42:12.168665
5116 13:42:12.171473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 13:42:12.171556
5118 13:42:12.175098 [CATrainingPosCal] consider 2 rank data
5119 13:42:12.177988 u2DelayCellTimex100 = 270/100 ps
5120 13:42:12.181739 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5121 13:42:12.184444 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5122 13:42:12.187921 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5123 13:42:12.191293 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5124 13:42:12.198163 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5125 13:42:12.201113 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5126 13:42:12.201221
5127 13:42:12.204706 CA PerBit enable=1, Macro0, CA PI delay=32
5128 13:42:12.204806
5129 13:42:12.208268 [CBTSetCACLKResult] CA Dly = 32
5130 13:42:12.208357 CS Dly: 5 (0~37)
5131 13:42:12.208451
5132 13:42:12.211096 ----->DramcWriteLeveling(PI) begin...
5133 13:42:12.211202 ==
5134 13:42:12.214584 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 13:42:12.221173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 13:42:12.221293 ==
5137 13:42:12.224926 Write leveling (Byte 0): 34 => 34
5138 13:42:12.227965 Write leveling (Byte 1): 29 => 29
5139 13:42:12.228057 DramcWriteLeveling(PI) end<-----
5140 13:42:12.228164
5141 13:42:12.231501 ==
5142 13:42:12.234372 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 13:42:12.237990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 13:42:12.238065 ==
5145 13:42:12.241287 [Gating] SW mode calibration
5146 13:42:12.247921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 13:42:12.251166 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 13:42:12.257960 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5149 13:42:12.261060 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 13:42:12.264687 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 13:42:12.270980 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 13:42:12.274604 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 13:42:12.278120 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 13:42:12.284788 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5155 13:42:12.287773 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
5156 13:42:12.291463 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5157 13:42:12.297566 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 13:42:12.300994 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 13:42:12.304566 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 13:42:12.310852 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 13:42:12.314397 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 13:42:12.317910 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5163 13:42:12.324253 0 15 28 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (0 0)
5164 13:42:12.327849 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5165 13:42:12.330808 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 13:42:12.334516 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 13:42:12.341038 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 13:42:12.344593 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 13:42:12.347385 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 13:42:12.354466 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 13:42:12.357400 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5172 13:42:12.360996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5173 13:42:12.368098 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 13:42:12.371222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:42:12.374520 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:42:12.381159 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:42:12.384568 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:42:12.387813 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:42:12.394260 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:42:12.397640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:42:12.400995 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:42:12.407494 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 13:42:12.411047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 13:42:12.414428 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 13:42:12.420669 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 13:42:12.424158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 13:42:12.427662 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5188 13:42:12.430595 Total UI for P1: 0, mck2ui 16
5189 13:42:12.434300 best dqsien dly found for B0: ( 1, 2, 26)
5190 13:42:12.437960 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 13:42:12.440847 Total UI for P1: 0, mck2ui 16
5192 13:42:12.444458 best dqsien dly found for B1: ( 1, 2, 30)
5193 13:42:12.447418 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5194 13:42:12.453970 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5195 13:42:12.454070
5196 13:42:12.457420 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5197 13:42:12.461124 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5198 13:42:12.464165 [Gating] SW calibration Done
5199 13:42:12.464274 ==
5200 13:42:12.467153 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 13:42:12.471003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 13:42:12.471118 ==
5203 13:42:12.471226 RX Vref Scan: 0
5204 13:42:12.474066
5205 13:42:12.474150 RX Vref 0 -> 0, step: 1
5206 13:42:12.474236
5207 13:42:12.477668 RX Delay -80 -> 252, step: 8
5208 13:42:12.480721 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5209 13:42:12.484367 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5210 13:42:12.490750 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5211 13:42:12.493687 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5212 13:42:12.497354 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5213 13:42:12.500789 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5214 13:42:12.504181 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5215 13:42:12.507474 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5216 13:42:12.513820 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5217 13:42:12.517036 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5218 13:42:12.521078 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5219 13:42:12.523745 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5220 13:42:12.527317 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5221 13:42:12.530696 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5222 13:42:12.537391 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5223 13:42:12.540437 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5224 13:42:12.540539 ==
5225 13:42:12.543963 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 13:42:12.546921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 13:42:12.547034 ==
5228 13:42:12.550163 DQS Delay:
5229 13:42:12.550280 DQS0 = 0, DQS1 = 0
5230 13:42:12.550374 DQM Delay:
5231 13:42:12.553707 DQM0 = 104, DQM1 = 94
5232 13:42:12.553819 DQ Delay:
5233 13:42:12.557435 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5234 13:42:12.560254 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5235 13:42:12.563764 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5236 13:42:12.566582 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5237 13:42:12.566693
5238 13:42:12.570271
5239 13:42:12.570375 ==
5240 13:42:12.573188 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 13:42:12.576821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 13:42:12.576930 ==
5243 13:42:12.577023
5244 13:42:12.577111
5245 13:42:12.579773 TX Vref Scan disable
5246 13:42:12.579873 == TX Byte 0 ==
5247 13:42:12.587127 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5248 13:42:12.590008 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5249 13:42:12.590087 == TX Byte 1 ==
5250 13:42:12.596407 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5251 13:42:12.600034 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5252 13:42:12.600140 ==
5253 13:42:12.603002 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 13:42:12.606667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 13:42:12.606778 ==
5256 13:42:12.606873
5257 13:42:12.606975
5258 13:42:12.609566 TX Vref Scan disable
5259 13:42:12.613190 == TX Byte 0 ==
5260 13:42:12.616995 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5261 13:42:12.619799 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5262 13:42:12.623525 == TX Byte 1 ==
5263 13:42:12.626512 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5264 13:42:12.630142 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5265 13:42:12.630246
5266 13:42:12.632974 [DATLAT]
5267 13:42:12.633078 Freq=933, CH0 RK0
5268 13:42:12.633171
5269 13:42:12.636689 DATLAT Default: 0xd
5270 13:42:12.636796 0, 0xFFFF, sum = 0
5271 13:42:12.639976 1, 0xFFFF, sum = 0
5272 13:42:12.640077 2, 0xFFFF, sum = 0
5273 13:42:12.643299 3, 0xFFFF, sum = 0
5274 13:42:12.643385 4, 0xFFFF, sum = 0
5275 13:42:12.646627 5, 0xFFFF, sum = 0
5276 13:42:12.646731 6, 0xFFFF, sum = 0
5277 13:42:12.650033 7, 0xFFFF, sum = 0
5278 13:42:12.650137 8, 0xFFFF, sum = 0
5279 13:42:12.653267 9, 0xFFFF, sum = 0
5280 13:42:12.653369 10, 0x0, sum = 1
5281 13:42:12.656680 11, 0x0, sum = 2
5282 13:42:12.656761 12, 0x0, sum = 3
5283 13:42:12.659807 13, 0x0, sum = 4
5284 13:42:12.659881 best_step = 11
5285 13:42:12.659943
5286 13:42:12.660017 ==
5287 13:42:12.662916 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 13:42:12.669764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 13:42:12.669860 ==
5290 13:42:12.669927 RX Vref Scan: 1
5291 13:42:12.670026
5292 13:42:12.673253 RX Vref 0 -> 0, step: 1
5293 13:42:12.673334
5294 13:42:12.676232 RX Delay -53 -> 252, step: 4
5295 13:42:12.676336
5296 13:42:12.679752 Set Vref, RX VrefLevel [Byte0]: 56
5297 13:42:12.683011 [Byte1]: 42
5298 13:42:12.683124
5299 13:42:12.686200 Final RX Vref Byte 0 = 56 to rank0
5300 13:42:12.689229 Final RX Vref Byte 1 = 42 to rank0
5301 13:42:12.692690 Final RX Vref Byte 0 = 56 to rank1
5302 13:42:12.696350 Final RX Vref Byte 1 = 42 to rank1==
5303 13:42:12.699802 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 13:42:12.702742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 13:42:12.702842 ==
5306 13:42:12.706679 DQS Delay:
5307 13:42:12.706781 DQS0 = 0, DQS1 = 0
5308 13:42:12.706871 DQM Delay:
5309 13:42:12.709298 DQM0 = 104, DQM1 = 95
5310 13:42:12.709370 DQ Delay:
5311 13:42:12.712986 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5312 13:42:12.715939 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5313 13:42:12.719663 DQ8 =86, DQ9 =82, DQ10 =98, DQ11 =90
5314 13:42:12.722622 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =100
5315 13:42:12.726344
5316 13:42:12.726420
5317 13:42:12.732915 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5318 13:42:12.736413 CH0 RK0: MR19=505, MR18=322A
5319 13:42:12.743001 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5320 13:42:12.743102
5321 13:42:12.745927 ----->DramcWriteLeveling(PI) begin...
5322 13:42:12.746026 ==
5323 13:42:12.749445 Dram Type= 6, Freq= 0, CH_0, rank 1
5324 13:42:12.752932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 13:42:12.753008 ==
5326 13:42:12.756440 Write leveling (Byte 0): 32 => 32
5327 13:42:12.759334 Write leveling (Byte 1): 29 => 29
5328 13:42:12.762952 DramcWriteLeveling(PI) end<-----
5329 13:42:12.763053
5330 13:42:12.763144 ==
5331 13:42:12.765910 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 13:42:12.769579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 13:42:12.769680 ==
5334 13:42:12.772710 [Gating] SW mode calibration
5335 13:42:12.779228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5336 13:42:12.786157 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5337 13:42:12.789592 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5338 13:42:12.793017 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 13:42:12.799647 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 13:42:12.802824 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 13:42:12.806026 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 13:42:12.812822 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 13:42:12.816337 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5344 13:42:12.819183 0 14 28 | B1->B0 | 2c2c 2e2e | 0 0 | (0 1) (0 1)
5345 13:42:12.825927 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 1)
5346 13:42:12.829439 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 13:42:12.832281 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 13:42:12.838963 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 13:42:12.842802 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 13:42:12.845554 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 13:42:12.852160 0 15 24 | B1->B0 | 2626 2525 | 1 0 | (0 0) (0 0)
5352 13:42:12.855890 0 15 28 | B1->B0 | 3b3b 3838 | 0 0 | (0 0) (1 1)
5353 13:42:12.859405 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5354 13:42:12.865923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 13:42:12.868909 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 13:42:12.872454 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 13:42:12.878993 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 13:42:12.882638 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 13:42:12.885441 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 13:42:12.888913 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5361 13:42:12.895898 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5362 13:42:12.898778 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 13:42:12.902499 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 13:42:12.908938 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:42:12.912402 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:42:12.915370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:42:12.921793 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:42:12.925324 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 13:42:12.928859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 13:42:12.935465 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 13:42:12.938712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 13:42:12.941762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 13:42:12.948577 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 13:42:12.952172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 13:42:12.955516 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 13:42:12.962029 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5377 13:42:12.965035 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 13:42:12.968522 Total UI for P1: 0, mck2ui 16
5379 13:42:12.972134 best dqsien dly found for B0: ( 1, 2, 28)
5380 13:42:12.975054 Total UI for P1: 0, mck2ui 16
5381 13:42:12.978784 best dqsien dly found for B1: ( 1, 2, 28)
5382 13:42:12.981701 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5383 13:42:12.985432 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5384 13:42:12.985535
5385 13:42:12.988422 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5386 13:42:12.991855 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5387 13:42:12.995561 [Gating] SW calibration Done
5388 13:42:12.995669 ==
5389 13:42:12.998237 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 13:42:13.001759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 13:42:13.005174 ==
5392 13:42:13.005262 RX Vref Scan: 0
5393 13:42:13.005350
5394 13:42:13.008898 RX Vref 0 -> 0, step: 1
5395 13:42:13.008996
5396 13:42:13.011730 RX Delay -80 -> 252, step: 8
5397 13:42:13.015442 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5398 13:42:13.018411 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5399 13:42:13.021648 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5400 13:42:13.025311 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5401 13:42:13.031122 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5402 13:42:13.034800 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5403 13:42:13.037793 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5404 13:42:13.041346 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5405 13:42:13.044974 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5406 13:42:13.047942 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5407 13:42:13.054954 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5408 13:42:13.058386 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5409 13:42:13.061620 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5410 13:42:13.064787 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5411 13:42:13.068229 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5412 13:42:13.071599 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5413 13:42:13.074703 ==
5414 13:42:13.074808 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 13:42:13.081088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 13:42:13.081199 ==
5417 13:42:13.081301 DQS Delay:
5418 13:42:13.084356 DQS0 = 0, DQS1 = 0
5419 13:42:13.084439 DQM Delay:
5420 13:42:13.088439 DQM0 = 105, DQM1 = 93
5421 13:42:13.088516 DQ Delay:
5422 13:42:13.091333 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5423 13:42:13.094809 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5424 13:42:13.097674 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5425 13:42:13.101474 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5426 13:42:13.101582
5427 13:42:13.101682
5428 13:42:13.101790 ==
5429 13:42:13.105047 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 13:42:13.107833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 13:42:13.107946 ==
5432 13:42:13.108042
5433 13:42:13.108149
5434 13:42:13.111167 TX Vref Scan disable
5435 13:42:13.114543 == TX Byte 0 ==
5436 13:42:13.117730 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5437 13:42:13.121433 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5438 13:42:13.124858 == TX Byte 1 ==
5439 13:42:13.127825 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 13:42:13.131346 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 13:42:13.131460 ==
5442 13:42:13.134318 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 13:42:13.141075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 13:42:13.141155 ==
5445 13:42:13.141235
5446 13:42:13.141304
5447 13:42:13.141364 TX Vref Scan disable
5448 13:42:13.145431 == TX Byte 0 ==
5449 13:42:13.148222 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5450 13:42:13.151796 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5451 13:42:13.155516 == TX Byte 1 ==
5452 13:42:13.158347 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 13:42:13.164814 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 13:42:13.164923
5455 13:42:13.165037 [DATLAT]
5456 13:42:13.165129 Freq=933, CH0 RK1
5457 13:42:13.165236
5458 13:42:13.168409 DATLAT Default: 0xb
5459 13:42:13.168493 0, 0xFFFF, sum = 0
5460 13:42:13.172110 1, 0xFFFF, sum = 0
5461 13:42:13.172226 2, 0xFFFF, sum = 0
5462 13:42:13.175008 3, 0xFFFF, sum = 0
5463 13:42:13.175120 4, 0xFFFF, sum = 0
5464 13:42:13.178661 5, 0xFFFF, sum = 0
5465 13:42:13.182106 6, 0xFFFF, sum = 0
5466 13:42:13.182211 7, 0xFFFF, sum = 0
5467 13:42:13.184906 8, 0xFFFF, sum = 0
5468 13:42:13.184984 9, 0xFFFF, sum = 0
5469 13:42:13.188416 10, 0x0, sum = 1
5470 13:42:13.188493 11, 0x0, sum = 2
5471 13:42:13.188579 12, 0x0, sum = 3
5472 13:42:13.191718 13, 0x0, sum = 4
5473 13:42:13.191827 best_step = 11
5474 13:42:13.191940
5475 13:42:13.195132 ==
5476 13:42:13.195239 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 13:42:13.201623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 13:42:13.201745 ==
5479 13:42:13.201844 RX Vref Scan: 0
5480 13:42:13.201939
5481 13:42:13.205003 RX Vref 0 -> 0, step: 1
5482 13:42:13.205088
5483 13:42:13.208610 RX Delay -53 -> 252, step: 4
5484 13:42:13.211425 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5485 13:42:13.218147 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5486 13:42:13.221645 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5487 13:42:13.225171 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5488 13:42:13.228468 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5489 13:42:13.231669 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5490 13:42:13.238022 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5491 13:42:13.241767 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5492 13:42:13.244634 iDelay=199, Bit 8, Center 82 (-1 ~ 166) 168
5493 13:42:13.248156 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5494 13:42:13.251746 iDelay=199, Bit 10, Center 94 (15 ~ 174) 160
5495 13:42:13.254650 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5496 13:42:13.262138 iDelay=199, Bit 12, Center 98 (19 ~ 178) 160
5497 13:42:13.264939 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5498 13:42:13.268694 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5499 13:42:13.271540 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5500 13:42:13.271615 ==
5501 13:42:13.275123 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 13:42:13.281756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 13:42:13.281839 ==
5504 13:42:13.281905 DQS Delay:
5505 13:42:13.281965 DQS0 = 0, DQS1 = 0
5506 13:42:13.284732 DQM Delay:
5507 13:42:13.284816 DQM0 = 105, DQM1 = 92
5508 13:42:13.288380 DQ Delay:
5509 13:42:13.291309 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5510 13:42:13.294911 DQ4 =106, DQ5 =100, DQ6 =108, DQ7 =112
5511 13:42:13.297750 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =86
5512 13:42:13.301476 DQ12 =98, DQ13 =96, DQ14 =102, DQ15 =102
5513 13:42:13.301560
5514 13:42:13.301624
5515 13:42:13.307879 [DQSOSCAuto] RK1, (LSB)MR18= 0x2800, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5516 13:42:13.311574 CH0 RK1: MR19=505, MR18=2800
5517 13:42:13.317959 CH0_RK1: MR19=0x505, MR18=0x2800, DQSOSC=409, MR23=63, INC=64, DEC=43
5518 13:42:13.321473 [RxdqsGatingPostProcess] freq 933
5519 13:42:13.328180 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 13:42:13.331128 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 13:42:13.331236 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 13:42:13.334676 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 13:42:13.337657 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 13:42:13.341193 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 13:42:13.344528 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 13:42:13.347823 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 13:42:13.351224 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 13:42:13.354258 Pre-setting of DQS Precalculation
5529 13:42:13.361047 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 13:42:13.361158 ==
5531 13:42:13.363932 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 13:42:13.367540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 13:42:13.367624 ==
5534 13:42:13.374180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 13:42:13.377721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 13:42:13.382241 [CA 0] Center 36 (6~67) winsize 62
5537 13:42:13.385243 [CA 1] Center 37 (6~68) winsize 63
5538 13:42:13.388181 [CA 2] Center 34 (4~65) winsize 62
5539 13:42:13.391664 [CA 3] Center 34 (4~65) winsize 62
5540 13:42:13.395485 [CA 4] Center 34 (4~64) winsize 61
5541 13:42:13.398436 [CA 5] Center 33 (3~64) winsize 62
5542 13:42:13.398510
5543 13:42:13.401394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 13:42:13.401465
5545 13:42:13.404950 [CATrainingPosCal] consider 1 rank data
5546 13:42:13.408841 u2DelayCellTimex100 = 270/100 ps
5547 13:42:13.411726 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 13:42:13.418120 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5549 13:42:13.421781 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5550 13:42:13.424825 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 13:42:13.428628 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 13:42:13.431488 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 13:42:13.431605
5554 13:42:13.435289 CA PerBit enable=1, Macro0, CA PI delay=33
5555 13:42:13.435401
5556 13:42:13.438169 [CBTSetCACLKResult] CA Dly = 33
5557 13:42:13.438273 CS Dly: 6 (0~37)
5558 13:42:13.441715 ==
5559 13:42:13.441793 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 13:42:13.448214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 13:42:13.448329 ==
5562 13:42:13.451818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 13:42:13.458002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 13:42:13.461872 [CA 0] Center 37 (6~68) winsize 63
5565 13:42:13.465163 [CA 1] Center 37 (7~68) winsize 62
5566 13:42:13.468205 [CA 2] Center 35 (4~66) winsize 63
5567 13:42:13.471992 [CA 3] Center 34 (4~65) winsize 62
5568 13:42:13.474767 [CA 4] Center 34 (4~65) winsize 62
5569 13:42:13.478238 [CA 5] Center 34 (4~64) winsize 61
5570 13:42:13.478346
5571 13:42:13.481793 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 13:42:13.481903
5573 13:42:13.484973 [CATrainingPosCal] consider 2 rank data
5574 13:42:13.487985 u2DelayCellTimex100 = 270/100 ps
5575 13:42:13.491442 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5576 13:42:13.498410 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5577 13:42:13.501678 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5578 13:42:13.504612 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5579 13:42:13.508075 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5580 13:42:13.511705 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 13:42:13.511808
5582 13:42:13.514587 CA PerBit enable=1, Macro0, CA PI delay=34
5583 13:42:13.514698
5584 13:42:13.518226 [CBTSetCACLKResult] CA Dly = 34
5585 13:42:13.518329 CS Dly: 7 (0~40)
5586 13:42:13.518429
5587 13:42:13.521792 ----->DramcWriteLeveling(PI) begin...
5588 13:42:13.524719 ==
5589 13:42:13.528375 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 13:42:13.531291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 13:42:13.531395 ==
5592 13:42:13.534962 Write leveling (Byte 0): 25 => 25
5593 13:42:13.538064 Write leveling (Byte 1): 26 => 26
5594 13:42:13.541631 DramcWriteLeveling(PI) end<-----
5595 13:42:13.541708
5596 13:42:13.541783 ==
5597 13:42:13.545081 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 13:42:13.548084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 13:42:13.548191 ==
5600 13:42:13.551700 [Gating] SW mode calibration
5601 13:42:13.558318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 13:42:13.565007 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 13:42:13.568113 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 13:42:13.571572 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 13:42:13.574576 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 13:42:13.581727 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 13:42:13.584721 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 13:42:13.588201 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 13:42:13.594611 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5610 13:42:13.598184 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5611 13:42:13.601417 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 13:42:13.607858 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 13:42:13.611429 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 13:42:13.614286 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 13:42:13.621216 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 13:42:13.624308 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 13:42:13.627438 0 15 24 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
5618 13:42:13.634202 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5619 13:42:13.637795 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 13:42:13.640739 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 13:42:13.647939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 13:42:13.651288 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 13:42:13.654201 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:42:13.660723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5625 13:42:13.664450 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5626 13:42:13.667444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:42:13.674001 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:42:13.677775 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:42:13.681227 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:42:13.687755 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:42:13.690607 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:42:13.694240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:42:13.700955 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:42:13.703918 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:42:13.707553 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:42:13.714175 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:42:13.717754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:42:13.720725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:42:13.727797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:42:13.730536 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5641 13:42:13.733829 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5642 13:42:13.737309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 13:42:13.740683 Total UI for P1: 0, mck2ui 16
5644 13:42:13.744040 best dqsien dly found for B0: ( 1, 2, 22)
5645 13:42:13.747353 Total UI for P1: 0, mck2ui 16
5646 13:42:13.750797 best dqsien dly found for B1: ( 1, 2, 24)
5647 13:42:13.753843 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5648 13:42:13.757474 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5649 13:42:13.761016
5650 13:42:13.763686 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5651 13:42:13.767198 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5652 13:42:13.770826 [Gating] SW calibration Done
5653 13:42:13.770931 ==
5654 13:42:13.774051 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 13:42:13.777453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 13:42:13.777541 ==
5657 13:42:13.777634 RX Vref Scan: 0
5658 13:42:13.777730
5659 13:42:13.780553 RX Vref 0 -> 0, step: 1
5660 13:42:13.780625
5661 13:42:13.784177 RX Delay -80 -> 252, step: 8
5662 13:42:13.787224 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5663 13:42:13.790838 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5664 13:42:13.797348 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5665 13:42:13.800414 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5666 13:42:13.804051 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5667 13:42:13.807040 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5668 13:42:13.810680 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5669 13:42:13.813632 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5670 13:42:13.820840 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5671 13:42:13.823773 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5672 13:42:13.827337 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5673 13:42:13.830251 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5674 13:42:13.834040 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5675 13:42:13.837489 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5676 13:42:13.843808 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5677 13:42:13.847423 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5678 13:42:13.847506 ==
5679 13:42:13.850476 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 13:42:13.853405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 13:42:13.853489 ==
5682 13:42:13.857054 DQS Delay:
5683 13:42:13.857137 DQS0 = 0, DQS1 = 0
5684 13:42:13.857202 DQM Delay:
5685 13:42:13.860546 DQM0 = 102, DQM1 = 98
5686 13:42:13.860629 DQ Delay:
5687 13:42:13.863446 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5688 13:42:13.867146 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5689 13:42:13.870102 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5690 13:42:13.873532 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5691 13:42:13.873616
5692 13:42:13.877157
5693 13:42:13.877240 ==
5694 13:42:13.880328 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 13:42:13.883893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 13:42:13.884003 ==
5697 13:42:13.884097
5698 13:42:13.884187
5699 13:42:13.886638 TX Vref Scan disable
5700 13:42:13.886747 == TX Byte 0 ==
5701 13:42:13.893394 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5702 13:42:13.896713 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5703 13:42:13.896790 == TX Byte 1 ==
5704 13:42:13.903293 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5705 13:42:13.906341 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5706 13:42:13.906417 ==
5707 13:42:13.910052 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 13:42:13.913237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 13:42:13.913337 ==
5710 13:42:13.913437
5711 13:42:13.913531
5712 13:42:13.916271 TX Vref Scan disable
5713 13:42:13.919873 == TX Byte 0 ==
5714 13:42:13.923715 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5715 13:42:13.926571 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5716 13:42:13.930075 == TX Byte 1 ==
5717 13:42:13.933625 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5718 13:42:13.936567 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5719 13:42:13.936668
5720 13:42:13.940143 [DATLAT]
5721 13:42:13.940242 Freq=933, CH1 RK0
5722 13:42:13.940348
5723 13:42:13.942966 DATLAT Default: 0xd
5724 13:42:13.943062 0, 0xFFFF, sum = 0
5725 13:42:13.946646 1, 0xFFFF, sum = 0
5726 13:42:13.946747 2, 0xFFFF, sum = 0
5727 13:42:13.949429 3, 0xFFFF, sum = 0
5728 13:42:13.949547 4, 0xFFFF, sum = 0
5729 13:42:13.953193 5, 0xFFFF, sum = 0
5730 13:42:13.953266 6, 0xFFFF, sum = 0
5731 13:42:13.956253 7, 0xFFFF, sum = 0
5732 13:42:13.956369 8, 0xFFFF, sum = 0
5733 13:42:13.959730 9, 0xFFFF, sum = 0
5734 13:42:13.959814 10, 0x0, sum = 1
5735 13:42:13.963296 11, 0x0, sum = 2
5736 13:42:13.963407 12, 0x0, sum = 3
5737 13:42:13.966204 13, 0x0, sum = 4
5738 13:42:13.966288 best_step = 11
5739 13:42:13.966362
5740 13:42:13.966435 ==
5741 13:42:13.969787 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 13:42:13.976348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 13:42:13.976429 ==
5744 13:42:13.976495 RX Vref Scan: 1
5745 13:42:13.976556
5746 13:42:13.980052 RX Vref 0 -> 0, step: 1
5747 13:42:13.980136
5748 13:42:13.982942 RX Delay -45 -> 252, step: 4
5749 13:42:13.983026
5750 13:42:13.986771 Set Vref, RX VrefLevel [Byte0]: 55
5751 13:42:13.989528 [Byte1]: 48
5752 13:42:13.989605
5753 13:42:13.993226 Final RX Vref Byte 0 = 55 to rank0
5754 13:42:13.996633 Final RX Vref Byte 1 = 48 to rank0
5755 13:42:13.999408 Final RX Vref Byte 0 = 55 to rank1
5756 13:42:14.003054 Final RX Vref Byte 1 = 48 to rank1==
5757 13:42:14.006762 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 13:42:14.009538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 13:42:14.009623 ==
5760 13:42:14.013032 DQS Delay:
5761 13:42:14.013122 DQS0 = 0, DQS1 = 0
5762 13:42:14.013187 DQM Delay:
5763 13:42:14.016581 DQM0 = 103, DQM1 = 99
5764 13:42:14.016688 DQ Delay:
5765 13:42:14.019451 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5766 13:42:14.023093 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5767 13:42:14.025837 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5768 13:42:14.029748 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5769 13:42:14.029832
5770 13:42:14.033061
5771 13:42:14.039675 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5772 13:42:14.042855 CH1 RK0: MR19=505, MR18=1C33
5773 13:42:14.049668 CH1_RK0: MR19=0x505, MR18=0x1C33, DQSOSC=405, MR23=63, INC=66, DEC=44
5774 13:42:14.049775
5775 13:42:14.052925 ----->DramcWriteLeveling(PI) begin...
5776 13:42:14.053008 ==
5777 13:42:14.056265 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 13:42:14.059725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 13:42:14.059835 ==
5780 13:42:14.062680 Write leveling (Byte 0): 28 => 28
5781 13:42:14.065992 Write leveling (Byte 1): 27 => 27
5782 13:42:14.069651 DramcWriteLeveling(PI) end<-----
5783 13:42:14.069742
5784 13:42:14.069806 ==
5785 13:42:14.073221 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 13:42:14.076068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 13:42:14.076149 ==
5788 13:42:14.079596 [Gating] SW mode calibration
5789 13:42:14.086236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5790 13:42:14.092830 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5791 13:42:14.095842 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 13:42:14.099346 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 13:42:14.105633 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 13:42:14.109085 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 13:42:14.112731 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 13:42:14.119007 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5797 13:42:14.122558 0 14 24 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 1)
5798 13:42:14.126280 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5799 13:42:14.132896 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 13:42:14.135677 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 13:42:14.139425 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 13:42:14.145652 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 13:42:14.149165 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 13:42:14.152261 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 13:42:14.155998 0 15 24 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5806 13:42:14.162278 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5807 13:42:14.165762 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 13:42:14.169527 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 13:42:14.175568 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 13:42:14.179273 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 13:42:14.182425 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:42:14.189505 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5813 13:42:14.192554 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5814 13:42:14.196218 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5815 13:42:14.202373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5816 13:42:14.206088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 13:42:14.209098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 13:42:14.215793 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:42:14.218767 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:42:14.222329 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:42:14.229038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:42:14.232711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:42:14.235606 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:42:14.242092 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 13:42:14.245828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 13:42:14.249253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 13:42:14.255573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 13:42:14.258637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 13:42:14.262345 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5830 13:42:14.269108 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 13:42:14.269193 Total UI for P1: 0, mck2ui 16
5832 13:42:14.275666 best dqsien dly found for B0: ( 1, 2, 24)
5833 13:42:14.275751 Total UI for P1: 0, mck2ui 16
5834 13:42:14.278528 best dqsien dly found for B1: ( 1, 2, 24)
5835 13:42:14.285456 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5836 13:42:14.288840 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5837 13:42:14.288917
5838 13:42:14.292129 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5839 13:42:14.295354 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5840 13:42:14.298876 [Gating] SW calibration Done
5841 13:42:14.298982 ==
5842 13:42:14.301755 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 13:42:14.305186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 13:42:14.305261 ==
5845 13:42:14.308653 RX Vref Scan: 0
5846 13:42:14.308750
5847 13:42:14.308848 RX Vref 0 -> 0, step: 1
5848 13:42:14.308936
5849 13:42:14.311751 RX Delay -80 -> 252, step: 8
5850 13:42:14.315566 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5851 13:42:14.321719 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5852 13:42:14.325201 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5853 13:42:14.328691 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5854 13:42:14.332123 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5855 13:42:14.334971 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5856 13:42:14.338606 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5857 13:42:14.342397 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5858 13:42:14.348935 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5859 13:42:14.351833 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5860 13:42:14.355392 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5861 13:42:14.358211 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5862 13:42:14.361711 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5863 13:42:14.365254 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5864 13:42:14.371929 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5865 13:42:14.374822 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5866 13:42:14.374903 ==
5867 13:42:14.378436 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 13:42:14.382127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 13:42:14.382209 ==
5870 13:42:14.385009 DQS Delay:
5871 13:42:14.385096 DQS0 = 0, DQS1 = 0
5872 13:42:14.385167 DQM Delay:
5873 13:42:14.388571 DQM0 = 102, DQM1 = 98
5874 13:42:14.388653 DQ Delay:
5875 13:42:14.391655 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5876 13:42:14.395325 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5877 13:42:14.398247 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5878 13:42:14.401782 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5879 13:42:14.401872
5880 13:42:14.401939
5881 13:42:14.405355 ==
5882 13:42:14.408221 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 13:42:14.411780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 13:42:14.411863 ==
5885 13:42:14.411931
5886 13:42:14.411993
5887 13:42:14.415106 TX Vref Scan disable
5888 13:42:14.415187 == TX Byte 0 ==
5889 13:42:14.421513 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5890 13:42:14.425188 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5891 13:42:14.425298 == TX Byte 1 ==
5892 13:42:14.431726 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5893 13:42:14.434775 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5894 13:42:14.434885 ==
5895 13:42:14.438357 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 13:42:14.441397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 13:42:14.441476 ==
5898 13:42:14.441544
5899 13:42:14.441604
5900 13:42:14.445002 TX Vref Scan disable
5901 13:42:14.448171 == TX Byte 0 ==
5902 13:42:14.451651 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5903 13:42:14.454531 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5904 13:42:14.458059 == TX Byte 1 ==
5905 13:42:14.461473 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5906 13:42:14.465006 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5907 13:42:14.465090
5908 13:42:14.468439 [DATLAT]
5909 13:42:14.468516 Freq=933, CH1 RK1
5910 13:42:14.468579
5911 13:42:14.471294 DATLAT Default: 0xb
5912 13:42:14.471369 0, 0xFFFF, sum = 0
5913 13:42:14.474793 1, 0xFFFF, sum = 0
5914 13:42:14.474898 2, 0xFFFF, sum = 0
5915 13:42:14.478470 3, 0xFFFF, sum = 0
5916 13:42:14.478545 4, 0xFFFF, sum = 0
5917 13:42:14.481453 5, 0xFFFF, sum = 0
5918 13:42:14.481531 6, 0xFFFF, sum = 0
5919 13:42:14.484389 7, 0xFFFF, sum = 0
5920 13:42:14.484466 8, 0xFFFF, sum = 0
5921 13:42:14.487986 9, 0xFFFF, sum = 0
5922 13:42:14.488058 10, 0x0, sum = 1
5923 13:42:14.491641 11, 0x0, sum = 2
5924 13:42:14.491719 12, 0x0, sum = 3
5925 13:42:14.494547 13, 0x0, sum = 4
5926 13:42:14.494619 best_step = 11
5927 13:42:14.494679
5928 13:42:14.494740 ==
5929 13:42:14.498311 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 13:42:14.501359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 13:42:14.504983 ==
5932 13:42:14.505058 RX Vref Scan: 0
5933 13:42:14.505119
5934 13:42:14.507837 RX Vref 0 -> 0, step: 1
5935 13:42:14.507907
5936 13:42:14.511410 RX Delay -45 -> 252, step: 4
5937 13:42:14.515195 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5938 13:42:14.518077 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5939 13:42:14.524857 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5940 13:42:14.528565 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5941 13:42:14.531422 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5942 13:42:14.535098 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5943 13:42:14.538419 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5944 13:42:14.541235 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5945 13:42:14.548331 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5946 13:42:14.551738 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5947 13:42:14.554631 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5948 13:42:14.558083 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5949 13:42:14.561368 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5950 13:42:14.568173 iDelay=203, Bit 13, Center 102 (19 ~ 186) 168
5951 13:42:14.571459 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5952 13:42:14.574554 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5953 13:42:14.574627 ==
5954 13:42:14.577838 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 13:42:14.580962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 13:42:14.581038 ==
5957 13:42:14.584373 DQS Delay:
5958 13:42:14.584461 DQS0 = 0, DQS1 = 0
5959 13:42:14.588147 DQM Delay:
5960 13:42:14.588220 DQM0 = 105, DQM1 = 99
5961 13:42:14.588285 DQ Delay:
5962 13:42:14.591098 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5963 13:42:14.594671 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5964 13:42:14.597706 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =92
5965 13:42:14.604836 DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =106
5966 13:42:14.604915
5967 13:42:14.604983
5968 13:42:14.611199 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5969 13:42:14.614923 CH1 RK1: MR19=504, MR18=2CFF
5970 13:42:14.621440 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5971 13:42:14.624453 [RxdqsGatingPostProcess] freq 933
5972 13:42:14.628187 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5973 13:42:14.631271 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 13:42:14.634733 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 13:42:14.637548 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 13:42:14.641118 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 13:42:14.644668 best DQS0 dly(2T, 0.5T) = (0, 10)
5978 13:42:14.648203 best DQS1 dly(2T, 0.5T) = (0, 10)
5979 13:42:14.651073 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5980 13:42:14.654562 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5981 13:42:14.657490 Pre-setting of DQS Precalculation
5982 13:42:14.661033 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5983 13:42:14.671088 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5984 13:42:14.677629 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5985 13:42:14.677709
5986 13:42:14.677772
5987 13:42:14.681169 [Calibration Summary] 1866 Mbps
5988 13:42:14.681250 CH 0, Rank 0
5989 13:42:14.684096 SW Impedance : PASS
5990 13:42:14.684169 DUTY Scan : NO K
5991 13:42:14.687746 ZQ Calibration : PASS
5992 13:42:14.690685 Jitter Meter : NO K
5993 13:42:14.690757 CBT Training : PASS
5994 13:42:14.694092 Write leveling : PASS
5995 13:42:14.697480 RX DQS gating : PASS
5996 13:42:14.697557 RX DQ/DQS(RDDQC) : PASS
5997 13:42:14.700958 TX DQ/DQS : PASS
5998 13:42:14.701030 RX DATLAT : PASS
5999 13:42:14.704244 RX DQ/DQS(Engine): PASS
6000 13:42:14.707572 TX OE : NO K
6001 13:42:14.707671 All Pass.
6002 13:42:14.707763
6003 13:42:14.707851 CH 0, Rank 1
6004 13:42:14.710826 SW Impedance : PASS
6005 13:42:14.714045 DUTY Scan : NO K
6006 13:42:14.714118 ZQ Calibration : PASS
6007 13:42:14.717715 Jitter Meter : NO K
6008 13:42:14.720802 CBT Training : PASS
6009 13:42:14.720877 Write leveling : PASS
6010 13:42:14.724049 RX DQS gating : PASS
6011 13:42:14.727671 RX DQ/DQS(RDDQC) : PASS
6012 13:42:14.727751 TX DQ/DQS : PASS
6013 13:42:14.731371 RX DATLAT : PASS
6014 13:42:14.734302 RX DQ/DQS(Engine): PASS
6015 13:42:14.734373 TX OE : NO K
6016 13:42:14.734436 All Pass.
6017 13:42:14.737952
6018 13:42:14.738029 CH 1, Rank 0
6019 13:42:14.740959 SW Impedance : PASS
6020 13:42:14.741042 DUTY Scan : NO K
6021 13:42:14.744381 ZQ Calibration : PASS
6022 13:42:14.744463 Jitter Meter : NO K
6023 13:42:14.747982 CBT Training : PASS
6024 13:42:14.750851 Write leveling : PASS
6025 13:42:14.750933 RX DQS gating : PASS
6026 13:42:14.754320 RX DQ/DQS(RDDQC) : PASS
6027 13:42:14.757460 TX DQ/DQS : PASS
6028 13:42:14.757546 RX DATLAT : PASS
6029 13:42:14.761061 RX DQ/DQS(Engine): PASS
6030 13:42:14.764593 TX OE : NO K
6031 13:42:14.764690 All Pass.
6032 13:42:14.764755
6033 13:42:14.764815 CH 1, Rank 1
6034 13:42:14.767313 SW Impedance : PASS
6035 13:42:14.770747 DUTY Scan : NO K
6036 13:42:14.770830 ZQ Calibration : PASS
6037 13:42:14.774165 Jitter Meter : NO K
6038 13:42:14.777045 CBT Training : PASS
6039 13:42:14.777127 Write leveling : PASS
6040 13:42:14.780699 RX DQS gating : PASS
6041 13:42:14.784245 RX DQ/DQS(RDDQC) : PASS
6042 13:42:14.784326 TX DQ/DQS : PASS
6043 13:42:14.787253 RX DATLAT : PASS
6044 13:42:14.790793 RX DQ/DQS(Engine): PASS
6045 13:42:14.790876 TX OE : NO K
6046 13:42:14.790941 All Pass.
6047 13:42:14.793653
6048 13:42:14.793734 DramC Write-DBI off
6049 13:42:14.797290 PER_BANK_REFRESH: Hybrid Mode
6050 13:42:14.797376 TX_TRACKING: ON
6051 13:42:14.807059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6052 13:42:14.810759 [FAST_K] Save calibration result to emmc
6053 13:42:14.813635 dramc_set_vcore_voltage set vcore to 650000
6054 13:42:14.817265 Read voltage for 400, 6
6055 13:42:14.817348 Vio18 = 0
6056 13:42:14.820591 Vcore = 650000
6057 13:42:14.820673 Vdram = 0
6058 13:42:14.820739 Vddq = 0
6059 13:42:14.820799 Vmddr = 0
6060 13:42:14.827465 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6061 13:42:14.833609 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6062 13:42:14.833689 MEM_TYPE=3, freq_sel=20
6063 13:42:14.836938 sv_algorithm_assistance_LP4_800
6064 13:42:14.840758 ============ PULL DRAM RESETB DOWN ============
6065 13:42:14.847207 ========== PULL DRAM RESETB DOWN end =========
6066 13:42:14.850125 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6067 13:42:14.853577 ===================================
6068 13:42:14.857070 LPDDR4 DRAM CONFIGURATION
6069 13:42:14.860506 ===================================
6070 13:42:14.860609 EX_ROW_EN[0] = 0x0
6071 13:42:14.864031 EX_ROW_EN[1] = 0x0
6072 13:42:14.864107 LP4Y_EN = 0x0
6073 13:42:14.867014 WORK_FSP = 0x0
6074 13:42:14.867100 WL = 0x2
6075 13:42:14.870733 RL = 0x2
6076 13:42:14.870803 BL = 0x2
6077 13:42:14.873542 RPST = 0x0
6078 13:42:14.877044 RD_PRE = 0x0
6079 13:42:14.877117 WR_PRE = 0x1
6080 13:42:14.880831 WR_PST = 0x0
6081 13:42:14.880904 DBI_WR = 0x0
6082 13:42:14.883702 DBI_RD = 0x0
6083 13:42:14.883779 OTF = 0x1
6084 13:42:14.887228 ===================================
6085 13:42:14.890183 ===================================
6086 13:42:14.893731 ANA top config
6087 13:42:14.896689 ===================================
6088 13:42:14.896774 DLL_ASYNC_EN = 0
6089 13:42:14.900531 ALL_SLAVE_EN = 1
6090 13:42:14.903347 NEW_RANK_MODE = 1
6091 13:42:14.907031 DLL_IDLE_MODE = 1
6092 13:42:14.907110 LP45_APHY_COMB_EN = 1
6093 13:42:14.909907 TX_ODT_DIS = 1
6094 13:42:14.913243 NEW_8X_MODE = 1
6095 13:42:14.917034 ===================================
6096 13:42:14.920415 ===================================
6097 13:42:14.923232 data_rate = 800
6098 13:42:14.926980 CKR = 1
6099 13:42:14.927060 DQ_P2S_RATIO = 4
6100 13:42:14.930532 ===================================
6101 13:42:14.933383 CA_P2S_RATIO = 4
6102 13:42:14.937077 DQ_CA_OPEN = 0
6103 13:42:14.940058 DQ_SEMI_OPEN = 1
6104 13:42:14.943607 CA_SEMI_OPEN = 1
6105 13:42:14.946330 CA_FULL_RATE = 0
6106 13:42:14.946402 DQ_CKDIV4_EN = 0
6107 13:42:14.949896 CA_CKDIV4_EN = 1
6108 13:42:14.953442 CA_PREDIV_EN = 0
6109 13:42:14.956684 PH8_DLY = 0
6110 13:42:14.959967 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6111 13:42:14.963036 DQ_AAMCK_DIV = 0
6112 13:42:14.963115 CA_AAMCK_DIV = 0
6113 13:42:14.966827 CA_ADMCK_DIV = 4
6114 13:42:14.969741 DQ_TRACK_CA_EN = 0
6115 13:42:14.973021 CA_PICK = 800
6116 13:42:14.976242 CA_MCKIO = 400
6117 13:42:14.980049 MCKIO_SEMI = 400
6118 13:42:14.983641 PLL_FREQ = 3016
6119 13:42:14.983724 DQ_UI_PI_RATIO = 32
6120 13:42:14.986399 CA_UI_PI_RATIO = 32
6121 13:42:14.989817 ===================================
6122 13:42:14.993243 ===================================
6123 13:42:14.996826 memory_type:LPDDR4
6124 13:42:14.999771 GP_NUM : 10
6125 13:42:14.999845 SRAM_EN : 1
6126 13:42:15.003490 MD32_EN : 0
6127 13:42:15.006368 ===================================
6128 13:42:15.010082 [ANA_INIT] >>>>>>>>>>>>>>
6129 13:42:15.010157 <<<<<< [CONFIGURE PHASE]: ANA_TX
6130 13:42:15.016599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6131 13:42:15.016700 ===================================
6132 13:42:15.020023 data_rate = 800,PCW = 0X7400
6133 13:42:15.023408 ===================================
6134 13:42:15.026371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6135 13:42:15.033442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6136 13:42:15.042735 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 13:42:15.049863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6138 13:42:15.052857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6139 13:42:15.056532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6140 13:42:15.059518 [ANA_INIT] flow start
6141 13:42:15.059591 [ANA_INIT] PLL >>>>>>>>
6142 13:42:15.063192 [ANA_INIT] PLL <<<<<<<<
6143 13:42:15.066115 [ANA_INIT] MIDPI >>>>>>>>
6144 13:42:15.066185 [ANA_INIT] MIDPI <<<<<<<<
6145 13:42:15.069389 [ANA_INIT] DLL >>>>>>>>
6146 13:42:15.072891 [ANA_INIT] flow end
6147 13:42:15.076280 ============ LP4 DIFF to SE enter ============
6148 13:42:15.079300 ============ LP4 DIFF to SE exit ============
6149 13:42:15.082711 [ANA_INIT] <<<<<<<<<<<<<
6150 13:42:15.086127 [Flow] Enable top DCM control >>>>>
6151 13:42:15.089404 [Flow] Enable top DCM control <<<<<
6152 13:42:15.092618 Enable DLL master slave shuffle
6153 13:42:15.095962 ==============================================================
6154 13:42:15.099792 Gating Mode config
6155 13:42:15.103007 ==============================================================
6156 13:42:15.106509 Config description:
6157 13:42:15.116159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6158 13:42:15.122849 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6159 13:42:15.126400 SELPH_MODE 0: By rank 1: By Phase
6160 13:42:15.132460 ==============================================================
6161 13:42:15.136046 GAT_TRACK_EN = 0
6162 13:42:15.139617 RX_GATING_MODE = 2
6163 13:42:15.142431 RX_GATING_TRACK_MODE = 2
6164 13:42:15.146077 SELPH_MODE = 1
6165 13:42:15.149736 PICG_EARLY_EN = 1
6166 13:42:15.149810 VALID_LAT_VALUE = 1
6167 13:42:15.156123 ==============================================================
6168 13:42:15.159026 Enter into Gating configuration >>>>
6169 13:42:15.162668 Exit from Gating configuration <<<<
6170 13:42:15.165572 Enter into DVFS_PRE_config >>>>>
6171 13:42:15.175655 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6172 13:42:15.179364 Exit from DVFS_PRE_config <<<<<
6173 13:42:15.182311 Enter into PICG configuration >>>>
6174 13:42:15.185861 Exit from PICG configuration <<<<
6175 13:42:15.189265 [RX_INPUT] configuration >>>>>
6176 13:42:15.192078 [RX_INPUT] configuration <<<<<
6177 13:42:15.198665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6178 13:42:15.202302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6179 13:42:15.208976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 13:42:15.215776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 13:42:15.222334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 13:42:15.229036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 13:42:15.232659 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6184 13:42:15.235581 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6185 13:42:15.239138 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6186 13:42:15.245429 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6187 13:42:15.249044 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6188 13:42:15.252028 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 13:42:15.255599 ===================================
6190 13:42:15.259120 LPDDR4 DRAM CONFIGURATION
6191 13:42:15.262041 ===================================
6192 13:42:15.262114 EX_ROW_EN[0] = 0x0
6193 13:42:15.265720 EX_ROW_EN[1] = 0x0
6194 13:42:15.265802 LP4Y_EN = 0x0
6195 13:42:15.268612 WORK_FSP = 0x0
6196 13:42:15.272216 WL = 0x2
6197 13:42:15.272296 RL = 0x2
6198 13:42:15.275122 BL = 0x2
6199 13:42:15.275203 RPST = 0x0
6200 13:42:15.278870 RD_PRE = 0x0
6201 13:42:15.278950 WR_PRE = 0x1
6202 13:42:15.281766 WR_PST = 0x0
6203 13:42:15.281846 DBI_WR = 0x0
6204 13:42:15.285368 DBI_RD = 0x0
6205 13:42:15.285449 OTF = 0x1
6206 13:42:15.288298 ===================================
6207 13:42:15.291890 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6208 13:42:15.298596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6209 13:42:15.302195 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 13:42:15.305219 ===================================
6211 13:42:15.308797 LPDDR4 DRAM CONFIGURATION
6212 13:42:15.311645 ===================================
6213 13:42:15.311725 EX_ROW_EN[0] = 0x10
6214 13:42:15.315065 EX_ROW_EN[1] = 0x0
6215 13:42:15.315145 LP4Y_EN = 0x0
6216 13:42:15.318505 WORK_FSP = 0x0
6217 13:42:15.318586 WL = 0x2
6218 13:42:15.321978 RL = 0x2
6219 13:42:15.322060 BL = 0x2
6220 13:42:15.324921 RPST = 0x0
6221 13:42:15.328499 RD_PRE = 0x0
6222 13:42:15.328572 WR_PRE = 0x1
6223 13:42:15.331971 WR_PST = 0x0
6224 13:42:15.332040 DBI_WR = 0x0
6225 13:42:15.335216 DBI_RD = 0x0
6226 13:42:15.335323 OTF = 0x1
6227 13:42:15.338610 ===================================
6228 13:42:15.345008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6229 13:42:15.348945 nWR fixed to 30
6230 13:42:15.352188 [ModeRegInit_LP4] CH0 RK0
6231 13:42:15.352258 [ModeRegInit_LP4] CH0 RK1
6232 13:42:15.355510 [ModeRegInit_LP4] CH1 RK0
6233 13:42:15.358755 [ModeRegInit_LP4] CH1 RK1
6234 13:42:15.358825 match AC timing 19
6235 13:42:15.365155 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6236 13:42:15.368799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6237 13:42:15.371721 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6238 13:42:15.378364 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6239 13:42:15.382117 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6240 13:42:15.382191 ==
6241 13:42:15.384947 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 13:42:15.388485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 13:42:15.388605 ==
6244 13:42:15.395320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 13:42:15.401700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6246 13:42:15.405217 [CA 0] Center 36 (8~64) winsize 57
6247 13:42:15.408543 [CA 1] Center 36 (8~64) winsize 57
6248 13:42:15.412134 [CA 2] Center 36 (8~64) winsize 57
6249 13:42:15.412210 [CA 3] Center 36 (8~64) winsize 57
6250 13:42:15.415017 [CA 4] Center 36 (8~64) winsize 57
6251 13:42:15.418632 [CA 5] Center 36 (8~64) winsize 57
6252 13:42:15.418710
6253 13:42:15.425549 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6254 13:42:15.425625
6255 13:42:15.428355 [CATrainingPosCal] consider 1 rank data
6256 13:42:15.428442 u2DelayCellTimex100 = 270/100 ps
6257 13:42:15.435675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 13:42:15.438687 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 13:42:15.442195 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 13:42:15.445356 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:42:15.448770 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:42:15.452220 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:42:15.452304
6264 13:42:15.455102 CA PerBit enable=1, Macro0, CA PI delay=36
6265 13:42:15.455183
6266 13:42:15.458664 [CBTSetCACLKResult] CA Dly = 36
6267 13:42:15.462280 CS Dly: 1 (0~32)
6268 13:42:15.462378 ==
6269 13:42:15.465044 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 13:42:15.468389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 13:42:15.468472 ==
6272 13:42:15.474993 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6273 13:42:15.478506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6274 13:42:15.481882 [CA 0] Center 36 (8~64) winsize 57
6275 13:42:15.484679 [CA 1] Center 36 (8~64) winsize 57
6276 13:42:15.488361 [CA 2] Center 36 (8~64) winsize 57
6277 13:42:15.491349 [CA 3] Center 36 (8~64) winsize 57
6278 13:42:15.495006 [CA 4] Center 36 (8~64) winsize 57
6279 13:42:15.498596 [CA 5] Center 36 (8~64) winsize 57
6280 13:42:15.498675
6281 13:42:15.501580 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6282 13:42:15.501663
6283 13:42:15.505266 [CATrainingPosCal] consider 2 rank data
6284 13:42:15.508309 u2DelayCellTimex100 = 270/100 ps
6285 13:42:15.511793 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:42:15.514994 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 13:42:15.518322 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 13:42:15.524808 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 13:42:15.528469 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 13:42:15.531812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 13:42:15.531896
6292 13:42:15.535215 CA PerBit enable=1, Macro0, CA PI delay=36
6293 13:42:15.535299
6294 13:42:15.538104 [CBTSetCACLKResult] CA Dly = 36
6295 13:42:15.538188 CS Dly: 1 (0~32)
6296 13:42:15.538253
6297 13:42:15.541671 ----->DramcWriteLeveling(PI) begin...
6298 13:42:15.541755 ==
6299 13:42:15.545192 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 13:42:15.551787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 13:42:15.551871 ==
6302 13:42:15.555105 Write leveling (Byte 0): 40 => 8
6303 13:42:15.557816 Write leveling (Byte 1): 40 => 8
6304 13:42:15.557925 DramcWriteLeveling(PI) end<-----
6305 13:42:15.558021
6306 13:42:15.561373 ==
6307 13:42:15.565008 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 13:42:15.568003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 13:42:15.568088 ==
6310 13:42:15.571720 [Gating] SW mode calibration
6311 13:42:15.578381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6312 13:42:15.581850 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6313 13:42:15.587941 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6314 13:42:15.591247 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 13:42:15.594501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 13:42:15.601711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 13:42:15.605196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 13:42:15.608238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 13:42:15.614696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 13:42:15.618461 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 13:42:15.621383 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 13:42:15.624868 Total UI for P1: 0, mck2ui 16
6323 13:42:15.628214 best dqsien dly found for B0: ( 0, 14, 24)
6324 13:42:15.631505 Total UI for P1: 0, mck2ui 16
6325 13:42:15.634750 best dqsien dly found for B1: ( 0, 14, 24)
6326 13:42:15.638081 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6327 13:42:15.641597 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6328 13:42:15.641694
6329 13:42:15.647694 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6330 13:42:15.651144 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 13:42:15.651253 [Gating] SW calibration Done
6332 13:42:15.654799 ==
6333 13:42:15.657746 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:42:15.661188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:42:15.661272 ==
6336 13:42:15.661338 RX Vref Scan: 0
6337 13:42:15.661400
6338 13:42:15.664595 RX Vref 0 -> 0, step: 1
6339 13:42:15.664679
6340 13:42:15.667316 RX Delay -410 -> 252, step: 16
6341 13:42:15.671139 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6342 13:42:15.673981 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6343 13:42:15.681293 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6344 13:42:15.684143 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6345 13:42:15.687761 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6346 13:42:15.690570 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6347 13:42:15.697733 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6348 13:42:15.700433 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6349 13:42:15.703865 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6350 13:42:15.707231 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6351 13:42:15.713736 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6352 13:42:15.717049 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6353 13:42:15.720497 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6354 13:42:15.727184 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6355 13:42:15.730381 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6356 13:42:15.734021 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6357 13:42:15.734103 ==
6358 13:42:15.737569 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 13:42:15.740165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 13:42:15.743482 ==
6361 13:42:15.743578 DQS Delay:
6362 13:42:15.743642 DQS0 = 27, DQS1 = 35
6363 13:42:15.746826 DQM Delay:
6364 13:42:15.746908 DQM0 = 14, DQM1 = 15
6365 13:42:15.750776 DQ Delay:
6366 13:42:15.750859 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =8
6367 13:42:15.753954 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6368 13:42:15.757399 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6369 13:42:15.760590 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6370 13:42:15.760671
6371 13:42:15.760734
6372 13:42:15.760793 ==
6373 13:42:15.764017 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 13:42:15.770550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 13:42:15.770632 ==
6376 13:42:15.770695
6377 13:42:15.770754
6378 13:42:15.770811 TX Vref Scan disable
6379 13:42:15.774049 == TX Byte 0 ==
6380 13:42:15.777144 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 13:42:15.780667 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 13:42:15.783516 == TX Byte 1 ==
6383 13:42:15.787365 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 13:42:15.790115 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 13:42:15.793757 ==
6386 13:42:15.793838 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 13:42:15.800231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 13:42:15.800311 ==
6389 13:42:15.800414
6390 13:42:15.800474
6391 13:42:15.804011 TX Vref Scan disable
6392 13:42:15.804091 == TX Byte 0 ==
6393 13:42:15.806861 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 13:42:15.813843 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 13:42:15.813925 == TX Byte 1 ==
6396 13:42:15.817286 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 13:42:15.820187 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 13:42:15.820269
6399 13:42:15.823513 [DATLAT]
6400 13:42:15.823592 Freq=400, CH0 RK0
6401 13:42:15.823663
6402 13:42:15.826954 DATLAT Default: 0xf
6403 13:42:15.827027 0, 0xFFFF, sum = 0
6404 13:42:15.830267 1, 0xFFFF, sum = 0
6405 13:42:15.830338 2, 0xFFFF, sum = 0
6406 13:42:15.833995 3, 0xFFFF, sum = 0
6407 13:42:15.834109 4, 0xFFFF, sum = 0
6408 13:42:15.836825 5, 0xFFFF, sum = 0
6409 13:42:15.836908 6, 0xFFFF, sum = 0
6410 13:42:15.840427 7, 0xFFFF, sum = 0
6411 13:42:15.843327 8, 0xFFFF, sum = 0
6412 13:42:15.843410 9, 0xFFFF, sum = 0
6413 13:42:15.846860 10, 0xFFFF, sum = 0
6414 13:42:15.846942 11, 0xFFFF, sum = 0
6415 13:42:15.850299 12, 0xFFFF, sum = 0
6416 13:42:15.850389 13, 0x0, sum = 1
6417 13:42:15.853757 14, 0x0, sum = 2
6418 13:42:15.853840 15, 0x0, sum = 3
6419 13:42:15.857253 16, 0x0, sum = 4
6420 13:42:15.857335 best_step = 14
6421 13:42:15.857400
6422 13:42:15.857459 ==
6423 13:42:15.860048 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 13:42:15.863260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 13:42:15.863342 ==
6426 13:42:15.866542 RX Vref Scan: 1
6427 13:42:15.866629
6428 13:42:15.869917 RX Vref 0 -> 0, step: 1
6429 13:42:15.869998
6430 13:42:15.870063 RX Delay -311 -> 252, step: 8
6431 13:42:15.870123
6432 13:42:15.873155 Set Vref, RX VrefLevel [Byte0]: 56
6433 13:42:15.877002 [Byte1]: 42
6434 13:42:15.882202
6435 13:42:15.882283 Final RX Vref Byte 0 = 56 to rank0
6436 13:42:15.885402 Final RX Vref Byte 1 = 42 to rank0
6437 13:42:15.888994 Final RX Vref Byte 0 = 56 to rank1
6438 13:42:15.891860 Final RX Vref Byte 1 = 42 to rank1==
6439 13:42:15.895622 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 13:42:15.902037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 13:42:15.902119 ==
6442 13:42:15.902183 DQS Delay:
6443 13:42:15.905107 DQS0 = 28, DQS1 = 36
6444 13:42:15.905188 DQM Delay:
6445 13:42:15.905253 DQM0 = 11, DQM1 = 13
6446 13:42:15.908647 DQ Delay:
6447 13:42:15.911644 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6448 13:42:15.911726 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6449 13:42:15.915162 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6450 13:42:15.918793 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6451 13:42:15.918874
6452 13:42:15.921783
6453 13:42:15.928284 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6454 13:42:15.932101 CH0 RK0: MR19=C0C, MR18=CBB6
6455 13:42:15.938592 CH0_RK0: MR19=0xC0C, MR18=0xCBB6, DQSOSC=384, MR23=63, INC=400, DEC=267
6456 13:42:15.938674 ==
6457 13:42:15.941811 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 13:42:15.945215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 13:42:15.945298 ==
6460 13:42:15.948549 [Gating] SW mode calibration
6461 13:42:15.955249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6462 13:42:15.961446 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6463 13:42:15.965158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6464 13:42:15.968131 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 13:42:15.971728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 13:42:15.978435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 13:42:15.981950 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 13:42:15.985332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 13:42:15.991823 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 13:42:15.995145 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 13:42:15.998373 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 13:42:16.001633 Total UI for P1: 0, mck2ui 16
6473 13:42:16.005081 best dqsien dly found for B0: ( 0, 14, 24)
6474 13:42:16.008737 Total UI for P1: 0, mck2ui 16
6475 13:42:16.011463 best dqsien dly found for B1: ( 0, 14, 24)
6476 13:42:16.015267 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6477 13:42:16.018041 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6478 13:42:16.021665
6479 13:42:16.024735 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6480 13:42:16.028236 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 13:42:16.031246 [Gating] SW calibration Done
6482 13:42:16.031345 ==
6483 13:42:16.034942 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 13:42:16.038612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 13:42:16.038712 ==
6486 13:42:16.038803 RX Vref Scan: 0
6487 13:42:16.038890
6488 13:42:16.041502 RX Vref 0 -> 0, step: 1
6489 13:42:16.041594
6490 13:42:16.045202 RX Delay -410 -> 252, step: 16
6491 13:42:16.047996 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6492 13:42:16.055233 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6493 13:42:16.058069 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6494 13:42:16.061598 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6495 13:42:16.064986 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6496 13:42:16.071691 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6497 13:42:16.075165 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6498 13:42:16.078390 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6499 13:42:16.081741 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6500 13:42:16.088242 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6501 13:42:16.091752 iDelay=230, Bit 10, Center -27 (-250 ~ 197) 448
6502 13:42:16.094632 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6503 13:42:16.097986 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6504 13:42:16.105149 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6505 13:42:16.108447 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6506 13:42:16.111239 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6507 13:42:16.111323 ==
6508 13:42:16.114882 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 13:42:16.118490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 13:42:16.121297 ==
6511 13:42:16.121388 DQS Delay:
6512 13:42:16.121450 DQS0 = 27, DQS1 = 35
6513 13:42:16.125048 DQM Delay:
6514 13:42:16.125160 DQM0 = 11, DQM1 = 11
6515 13:42:16.128096 DQ Delay:
6516 13:42:16.128178 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6517 13:42:16.131756 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6518 13:42:16.134690 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6519 13:42:16.138393 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6520 13:42:16.138504
6521 13:42:16.138569
6522 13:42:16.138628 ==
6523 13:42:16.141345 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 13:42:16.148129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 13:42:16.148227 ==
6526 13:42:16.148291
6527 13:42:16.148391
6528 13:42:16.148450 TX Vref Scan disable
6529 13:42:16.151555 == TX Byte 0 ==
6530 13:42:16.155061 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6531 13:42:16.157882 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6532 13:42:16.161425 == TX Byte 1 ==
6533 13:42:16.165071 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6534 13:42:16.167967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6535 13:42:16.168079 ==
6536 13:42:16.171614 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 13:42:16.177866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 13:42:16.177950 ==
6539 13:42:16.178017
6540 13:42:16.178078
6541 13:42:16.178137 TX Vref Scan disable
6542 13:42:16.181307 == TX Byte 0 ==
6543 13:42:16.184986 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6544 13:42:16.187725 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6545 13:42:16.191600 == TX Byte 1 ==
6546 13:42:16.194698 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6547 13:42:16.198272 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6548 13:42:16.198369
6549 13:42:16.201423 [DATLAT]
6550 13:42:16.201530 Freq=400, CH0 RK1
6551 13:42:16.201633
6552 13:42:16.204694 DATLAT Default: 0xe
6553 13:42:16.204795 0, 0xFFFF, sum = 0
6554 13:42:16.208147 1, 0xFFFF, sum = 0
6555 13:42:16.208255 2, 0xFFFF, sum = 0
6556 13:42:16.211646 3, 0xFFFF, sum = 0
6557 13:42:16.211745 4, 0xFFFF, sum = 0
6558 13:42:16.214798 5, 0xFFFF, sum = 0
6559 13:42:16.214881 6, 0xFFFF, sum = 0
6560 13:42:16.217769 7, 0xFFFF, sum = 0
6561 13:42:16.217855 8, 0xFFFF, sum = 0
6562 13:42:16.221294 9, 0xFFFF, sum = 0
6563 13:42:16.221379 10, 0xFFFF, sum = 0
6564 13:42:16.224686 11, 0xFFFF, sum = 0
6565 13:42:16.227439 12, 0xFFFF, sum = 0
6566 13:42:16.227523 13, 0x0, sum = 1
6567 13:42:16.231568 14, 0x0, sum = 2
6568 13:42:16.231654 15, 0x0, sum = 3
6569 13:42:16.231722 16, 0x0, sum = 4
6570 13:42:16.234522 best_step = 14
6571 13:42:16.234610
6572 13:42:16.234676 ==
6573 13:42:16.237864 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 13:42:16.241501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 13:42:16.241586 ==
6576 13:42:16.244351 RX Vref Scan: 0
6577 13:42:16.244435
6578 13:42:16.244500 RX Vref 0 -> 0, step: 1
6579 13:42:16.248051
6580 13:42:16.248134 RX Delay -311 -> 252, step: 8
6581 13:42:16.256193 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6582 13:42:16.259150 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6583 13:42:16.262843 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6584 13:42:16.266466 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6585 13:42:16.273137 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6586 13:42:16.276013 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6587 13:42:16.279644 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6588 13:42:16.283009 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6589 13:42:16.289484 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6590 13:42:16.293164 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6591 13:42:16.296014 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6592 13:42:16.299676 iDelay=217, Bit 11, Center -32 (-247 ~ 184) 432
6593 13:42:16.306229 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6594 13:42:16.309545 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6595 13:42:16.312824 iDelay=217, Bit 14, Center -16 (-231 ~ 200) 432
6596 13:42:16.318935 iDelay=217, Bit 15, Center -12 (-231 ~ 208) 440
6597 13:42:16.319019 ==
6598 13:42:16.322406 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 13:42:16.325938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 13:42:16.326022 ==
6601 13:42:16.326089 DQS Delay:
6602 13:42:16.328939 DQS0 = 24, DQS1 = 36
6603 13:42:16.329022 DQM Delay:
6604 13:42:16.332392 DQM0 = 9, DQM1 = 12
6605 13:42:16.332475 DQ Delay:
6606 13:42:16.335952 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6607 13:42:16.339235 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6608 13:42:16.342505 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6609 13:42:16.345737 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6610 13:42:16.345820
6611 13:42:16.345886
6612 13:42:16.352174 [DQSOSCAuto] RK1, (LSB)MR18= 0xc161, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6613 13:42:16.355818 CH0 RK1: MR19=C0C, MR18=C161
6614 13:42:16.362175 CH0_RK1: MR19=0xC0C, MR18=0xC161, DQSOSC=385, MR23=63, INC=398, DEC=265
6615 13:42:16.365828 [RxdqsGatingPostProcess] freq 400
6616 13:42:16.368734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6617 13:42:16.372234 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 13:42:16.375790 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 13:42:16.378735 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 13:42:16.382517 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 13:42:16.385453 best DQS0 dly(2T, 0.5T) = (0, 10)
6622 13:42:16.389025 best DQS1 dly(2T, 0.5T) = (0, 10)
6623 13:42:16.392656 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6624 13:42:16.395318 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6625 13:42:16.399090 Pre-setting of DQS Precalculation
6626 13:42:16.402051 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6627 13:42:16.405724 ==
6628 13:42:16.408926 Dram Type= 6, Freq= 0, CH_1, rank 0
6629 13:42:16.412308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 13:42:16.412406 ==
6631 13:42:16.415260 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 13:42:16.421899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6633 13:42:16.425610 [CA 0] Center 36 (8~64) winsize 57
6634 13:42:16.428541 [CA 1] Center 36 (8~64) winsize 57
6635 13:42:16.432074 [CA 2] Center 36 (8~64) winsize 57
6636 13:42:16.435706 [CA 3] Center 36 (8~64) winsize 57
6637 13:42:16.438399 [CA 4] Center 36 (8~64) winsize 57
6638 13:42:16.442048 [CA 5] Center 36 (8~64) winsize 57
6639 13:42:16.442148
6640 13:42:16.445055 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6641 13:42:16.445136
6642 13:42:16.448468 [CATrainingPosCal] consider 1 rank data
6643 13:42:16.451677 u2DelayCellTimex100 = 270/100 ps
6644 13:42:16.454973 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 13:42:16.458668 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 13:42:16.461722 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 13:42:16.465194 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:42:16.471410 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:42:16.475066 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:42:16.475195
6651 13:42:16.477929 CA PerBit enable=1, Macro0, CA PI delay=36
6652 13:42:16.478002
6653 13:42:16.481442 [CBTSetCACLKResult] CA Dly = 36
6654 13:42:16.481553 CS Dly: 1 (0~32)
6655 13:42:16.481633 ==
6656 13:42:16.484887 Dram Type= 6, Freq= 0, CH_1, rank 1
6657 13:42:16.491601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 13:42:16.491723 ==
6659 13:42:16.495206 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6660 13:42:16.501474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6661 13:42:16.505239 [CA 0] Center 36 (8~64) winsize 57
6662 13:42:16.508174 [CA 1] Center 36 (8~64) winsize 57
6663 13:42:16.511126 [CA 2] Center 36 (8~64) winsize 57
6664 13:42:16.514987 [CA 3] Center 36 (8~64) winsize 57
6665 13:42:16.517923 [CA 4] Center 36 (8~64) winsize 57
6666 13:42:16.521068 [CA 5] Center 36 (8~64) winsize 57
6667 13:42:16.521152
6668 13:42:16.524718 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6669 13:42:16.524803
6670 13:42:16.527723 [CATrainingPosCal] consider 2 rank data
6671 13:42:16.531313 u2DelayCellTimex100 = 270/100 ps
6672 13:42:16.535003 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:42:16.537963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 13:42:16.541464 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 13:42:16.545060 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 13:42:16.548284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 13:42:16.551338 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 13:42:16.551459
6679 13:42:16.557837 CA PerBit enable=1, Macro0, CA PI delay=36
6680 13:42:16.557951
6681 13:42:16.558055 [CBTSetCACLKResult] CA Dly = 36
6682 13:42:16.561570 CS Dly: 1 (0~32)
6683 13:42:16.561647
6684 13:42:16.564530 ----->DramcWriteLeveling(PI) begin...
6685 13:42:16.564603 ==
6686 13:42:16.568096 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 13:42:16.570915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 13:42:16.570994 ==
6689 13:42:16.574553 Write leveling (Byte 0): 40 => 8
6690 13:42:16.578055 Write leveling (Byte 1): 40 => 8
6691 13:42:16.581666 DramcWriteLeveling(PI) end<-----
6692 13:42:16.581744
6693 13:42:16.581809 ==
6694 13:42:16.584461 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 13:42:16.587824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 13:42:16.591253 ==
6697 13:42:16.591354 [Gating] SW mode calibration
6698 13:42:16.597723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6699 13:42:16.604038 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6700 13:42:16.607582 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6701 13:42:16.614179 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 13:42:16.617464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 13:42:16.620948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 13:42:16.627583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 13:42:16.631370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 13:42:16.634241 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 13:42:16.641179 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 13:42:16.644092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 13:42:16.647664 Total UI for P1: 0, mck2ui 16
6710 13:42:16.650594 best dqsien dly found for B0: ( 0, 14, 24)
6711 13:42:16.654216 Total UI for P1: 0, mck2ui 16
6712 13:42:16.657798 best dqsien dly found for B1: ( 0, 14, 24)
6713 13:42:16.661003 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6714 13:42:16.664718 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6715 13:42:16.664796
6716 13:42:16.667542 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6717 13:42:16.671216 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 13:42:16.674111 [Gating] SW calibration Done
6719 13:42:16.674207 ==
6720 13:42:16.677644 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:42:16.681294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:42:16.684060 ==
6723 13:42:16.684155 RX Vref Scan: 0
6724 13:42:16.684246
6725 13:42:16.687553 RX Vref 0 -> 0, step: 1
6726 13:42:16.687626
6727 13:42:16.690516 RX Delay -410 -> 252, step: 16
6728 13:42:16.694162 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6729 13:42:16.697153 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6730 13:42:16.700883 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6731 13:42:16.707303 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6732 13:42:16.711029 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6733 13:42:16.714023 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6734 13:42:16.717435 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6735 13:42:16.724186 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6736 13:42:16.727525 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6737 13:42:16.730760 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6738 13:42:16.734105 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6739 13:42:16.740820 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6740 13:42:16.744275 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6741 13:42:16.747300 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6742 13:42:16.751025 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6743 13:42:16.757617 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6744 13:42:16.757700 ==
6745 13:42:16.760646 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 13:42:16.764329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 13:42:16.764422 ==
6748 13:42:16.764487 DQS Delay:
6749 13:42:16.767094 DQS0 = 35, DQS1 = 35
6750 13:42:16.767176 DQM Delay:
6751 13:42:16.770872 DQM0 = 17, DQM1 = 13
6752 13:42:16.770956 DQ Delay:
6753 13:42:16.774199 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6754 13:42:16.777038 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6755 13:42:16.780394 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6756 13:42:16.784035 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6757 13:42:16.784119
6758 13:42:16.784183
6759 13:42:16.784244 ==
6760 13:42:16.787498 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 13:42:16.790233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 13:42:16.790316 ==
6763 13:42:16.790381
6764 13:42:16.793749
6765 13:42:16.793833 TX Vref Scan disable
6766 13:42:16.797433 == TX Byte 0 ==
6767 13:42:16.800352 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 13:42:16.803984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 13:42:16.806898 == TX Byte 1 ==
6770 13:42:16.810574 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 13:42:16.813594 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 13:42:16.813678 ==
6773 13:42:16.817091 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 13:42:16.820489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 13:42:16.820572 ==
6776 13:42:16.820637
6777 13:42:16.824055
6778 13:42:16.824137 TX Vref Scan disable
6779 13:42:16.826967 == TX Byte 0 ==
6780 13:42:16.830460 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 13:42:16.834057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 13:42:16.836862 == TX Byte 1 ==
6783 13:42:16.840588 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 13:42:16.843964 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 13:42:16.844046
6786 13:42:16.844109 [DATLAT]
6787 13:42:16.847381 Freq=400, CH1 RK0
6788 13:42:16.847462
6789 13:42:16.847526 DATLAT Default: 0xf
6790 13:42:16.850654 0, 0xFFFF, sum = 0
6791 13:42:16.850737 1, 0xFFFF, sum = 0
6792 13:42:16.854016 2, 0xFFFF, sum = 0
6793 13:42:16.857098 3, 0xFFFF, sum = 0
6794 13:42:16.857180 4, 0xFFFF, sum = 0
6795 13:42:16.860827 5, 0xFFFF, sum = 0
6796 13:42:16.860909 6, 0xFFFF, sum = 0
6797 13:42:16.863701 7, 0xFFFF, sum = 0
6798 13:42:16.863783 8, 0xFFFF, sum = 0
6799 13:42:16.867325 9, 0xFFFF, sum = 0
6800 13:42:16.867406 10, 0xFFFF, sum = 0
6801 13:42:16.870212 11, 0xFFFF, sum = 0
6802 13:42:16.870294 12, 0xFFFF, sum = 0
6803 13:42:16.873773 13, 0x0, sum = 1
6804 13:42:16.873855 14, 0x0, sum = 2
6805 13:42:16.876945 15, 0x0, sum = 3
6806 13:42:16.877027 16, 0x0, sum = 4
6807 13:42:16.880712 best_step = 14
6808 13:42:16.880807
6809 13:42:16.880870 ==
6810 13:42:16.883709 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 13:42:16.886967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 13:42:16.887062 ==
6813 13:42:16.890472 RX Vref Scan: 1
6814 13:42:16.890575
6815 13:42:16.890637 RX Vref 0 -> 0, step: 1
6816 13:42:16.890695
6817 13:42:16.893542 RX Delay -311 -> 252, step: 8
6818 13:42:16.893659
6819 13:42:16.896717 Set Vref, RX VrefLevel [Byte0]: 55
6820 13:42:16.900220 [Byte1]: 48
6821 13:42:16.904211
6822 13:42:16.904322 Final RX Vref Byte 0 = 55 to rank0
6823 13:42:16.907244 Final RX Vref Byte 1 = 48 to rank0
6824 13:42:16.910602 Final RX Vref Byte 0 = 55 to rank1
6825 13:42:16.914562 Final RX Vref Byte 1 = 48 to rank1==
6826 13:42:16.917376 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 13:42:16.924245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 13:42:16.924400 ==
6829 13:42:16.924494 DQS Delay:
6830 13:42:16.927211 DQS0 = 28, DQS1 = 32
6831 13:42:16.927381 DQM Delay:
6832 13:42:16.927468 DQM0 = 10, DQM1 = 11
6833 13:42:16.930997 DQ Delay:
6834 13:42:16.934082 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6835 13:42:16.934182 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6836 13:42:16.937337 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6837 13:42:16.940818 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6838 13:42:16.940890
6839 13:42:16.940950
6840 13:42:16.951123 [DQSOSCAuto] RK0, (LSB)MR18= 0x91ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6841 13:42:16.954227 CH1 RK0: MR19=C0C, MR18=91CA
6842 13:42:16.961212 CH1_RK0: MR19=0xC0C, MR18=0x91CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6843 13:42:16.961295 ==
6844 13:42:16.964160 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 13:42:16.967673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 13:42:16.967756 ==
6847 13:42:16.971010 [Gating] SW mode calibration
6848 13:42:16.977224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6849 13:42:16.980602 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6850 13:42:16.987151 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6851 13:42:16.990849 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 13:42:16.993747 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 13:42:17.000377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 13:42:17.003875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 13:42:17.007525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 13:42:17.014077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 13:42:17.017534 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 13:42:17.020776 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 13:42:17.024071 Total UI for P1: 0, mck2ui 16
6860 13:42:17.027210 best dqsien dly found for B0: ( 0, 14, 24)
6861 13:42:17.030253 Total UI for P1: 0, mck2ui 16
6862 13:42:17.033647 best dqsien dly found for B1: ( 0, 14, 24)
6863 13:42:17.037179 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6864 13:42:17.040673 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6865 13:42:17.040758
6866 13:42:17.047104 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6867 13:42:17.050745 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 13:42:17.053716 [Gating] SW calibration Done
6869 13:42:17.053822 ==
6870 13:42:17.056913 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 13:42:17.060547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 13:42:17.060625 ==
6873 13:42:17.060688 RX Vref Scan: 0
6874 13:42:17.060747
6875 13:42:17.063536 RX Vref 0 -> 0, step: 1
6876 13:42:17.063610
6877 13:42:17.067384 RX Delay -410 -> 252, step: 16
6878 13:42:17.070334 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6879 13:42:17.077063 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6880 13:42:17.080835 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6881 13:42:17.083783 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6882 13:42:17.087348 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6883 13:42:17.094045 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6884 13:42:17.097270 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6885 13:42:17.100178 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6886 13:42:17.103743 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6887 13:42:17.106746 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6888 13:42:17.114209 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6889 13:42:17.117244 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6890 13:42:17.120799 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6891 13:42:17.123848 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6892 13:42:17.130567 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6893 13:42:17.133661 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6894 13:42:17.133744 ==
6895 13:42:17.137252 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 13:42:17.140391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 13:42:17.140501 ==
6898 13:42:17.143762 DQS Delay:
6899 13:42:17.143876 DQS0 = 27, DQS1 = 35
6900 13:42:17.146798 DQM Delay:
6901 13:42:17.146897 DQM0 = 11, DQM1 = 13
6902 13:42:17.146995 DQ Delay:
6903 13:42:17.150586 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6904 13:42:17.153899 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6905 13:42:17.157094 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6906 13:42:17.160107 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6907 13:42:17.160190
6908 13:42:17.160255
6909 13:42:17.160315 ==
6910 13:42:17.163650 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 13:42:17.170237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 13:42:17.170320 ==
6913 13:42:17.170386
6914 13:42:17.170446
6915 13:42:17.170504 TX Vref Scan disable
6916 13:42:17.173364 == TX Byte 0 ==
6917 13:42:17.176813 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6918 13:42:17.180634 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6919 13:42:17.183565 == TX Byte 1 ==
6920 13:42:17.187163 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6921 13:42:17.190060 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6922 13:42:17.190143 ==
6923 13:42:17.193765 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 13:42:17.200351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 13:42:17.200436 ==
6926 13:42:17.200500
6927 13:42:17.200561
6928 13:42:17.200619 TX Vref Scan disable
6929 13:42:17.203326 == TX Byte 0 ==
6930 13:42:17.206700 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6931 13:42:17.210015 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6932 13:42:17.213518 == TX Byte 1 ==
6933 13:42:17.216998 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6934 13:42:17.220433 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6935 13:42:17.220542
6936 13:42:17.223479 [DATLAT]
6937 13:42:17.223588 Freq=400, CH1 RK1
6938 13:42:17.223682
6939 13:42:17.226424 DATLAT Default: 0xe
6940 13:42:17.226535 0, 0xFFFF, sum = 0
6941 13:42:17.230278 1, 0xFFFF, sum = 0
6942 13:42:17.230360 2, 0xFFFF, sum = 0
6943 13:42:17.233839 3, 0xFFFF, sum = 0
6944 13:42:17.233923 4, 0xFFFF, sum = 0
6945 13:42:17.236847 5, 0xFFFF, sum = 0
6946 13:42:17.236929 6, 0xFFFF, sum = 0
6947 13:42:17.239852 7, 0xFFFF, sum = 0
6948 13:42:17.239964 8, 0xFFFF, sum = 0
6949 13:42:17.243607 9, 0xFFFF, sum = 0
6950 13:42:17.243689 10, 0xFFFF, sum = 0
6951 13:42:17.246529 11, 0xFFFF, sum = 0
6952 13:42:17.250346 12, 0xFFFF, sum = 0
6953 13:42:17.250431 13, 0x0, sum = 1
6954 13:42:17.250524 14, 0x0, sum = 2
6955 13:42:17.253365 15, 0x0, sum = 3
6956 13:42:17.253460 16, 0x0, sum = 4
6957 13:42:17.256868 best_step = 14
6958 13:42:17.256962
6959 13:42:17.257026 ==
6960 13:42:17.259661 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 13:42:17.263198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 13:42:17.263294 ==
6963 13:42:17.266957 RX Vref Scan: 0
6964 13:42:17.267038
6965 13:42:17.267102 RX Vref 0 -> 0, step: 1
6966 13:42:17.269728
6967 13:42:17.269848 RX Delay -311 -> 252, step: 8
6968 13:42:17.278249 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6969 13:42:17.281483 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6970 13:42:17.285037 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6971 13:42:17.288260 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6972 13:42:17.294605 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6973 13:42:17.298359 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6974 13:42:17.301468 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6975 13:42:17.304609 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6976 13:42:17.311268 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6977 13:42:17.315037 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6978 13:42:17.317937 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6979 13:42:17.321796 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6980 13:42:17.328101 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6981 13:42:17.331498 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6982 13:42:17.334906 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6983 13:42:17.337853 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6984 13:42:17.341640 ==
6985 13:42:17.344704 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 13:42:17.348236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 13:42:17.348355 ==
6988 13:42:17.348446 DQS Delay:
6989 13:42:17.351390 DQS0 = 28, DQS1 = 32
6990 13:42:17.351497 DQM Delay:
6991 13:42:17.354974 DQM0 = 10, DQM1 = 11
6992 13:42:17.355081 DQ Delay:
6993 13:42:17.357833 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6994 13:42:17.361986 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6995 13:42:17.364683 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6996 13:42:17.368084 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6997 13:42:17.368197
6998 13:42:17.368292
6999 13:42:17.374724 [DQSOSCAuto] RK1, (LSB)MR18= 0xca5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7000 13:42:17.377716 CH1 RK1: MR19=C0C, MR18=CA5C
7001 13:42:17.384963 CH1_RK1: MR19=0xC0C, MR18=0xCA5C, DQSOSC=384, MR23=63, INC=400, DEC=267
7002 13:42:17.388119 [RxdqsGatingPostProcess] freq 400
7003 13:42:17.391072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7004 13:42:17.394743 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 13:42:17.398499 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 13:42:17.401223 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 13:42:17.404546 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 13:42:17.407934 best DQS0 dly(2T, 0.5T) = (0, 10)
7009 13:42:17.411279 best DQS1 dly(2T, 0.5T) = (0, 10)
7010 13:42:17.414236 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7011 13:42:17.417887 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7012 13:42:17.421435 Pre-setting of DQS Precalculation
7013 13:42:17.424395 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7014 13:42:17.434378 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7015 13:42:17.441299 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7016 13:42:17.441381
7017 13:42:17.441446
7018 13:42:17.444651 [Calibration Summary] 800 Mbps
7019 13:42:17.444736 CH 0, Rank 0
7020 13:42:17.447848 SW Impedance : PASS
7021 13:42:17.447929 DUTY Scan : NO K
7022 13:42:17.451136 ZQ Calibration : PASS
7023 13:42:17.454774 Jitter Meter : NO K
7024 13:42:17.454856 CBT Training : PASS
7025 13:42:17.457698 Write leveling : PASS
7026 13:42:17.460778 RX DQS gating : PASS
7027 13:42:17.460859 RX DQ/DQS(RDDQC) : PASS
7028 13:42:17.464454 TX DQ/DQS : PASS
7029 13:42:17.467531 RX DATLAT : PASS
7030 13:42:17.467611 RX DQ/DQS(Engine): PASS
7031 13:42:17.471104 TX OE : NO K
7032 13:42:17.471186 All Pass.
7033 13:42:17.471250
7034 13:42:17.474643 CH 0, Rank 1
7035 13:42:17.474724 SW Impedance : PASS
7036 13:42:17.477361 DUTY Scan : NO K
7037 13:42:17.477442 ZQ Calibration : PASS
7038 13:42:17.480770 Jitter Meter : NO K
7039 13:42:17.484281 CBT Training : PASS
7040 13:42:17.484387 Write leveling : NO K
7041 13:42:17.487312 RX DQS gating : PASS
7042 13:42:17.490822 RX DQ/DQS(RDDQC) : PASS
7043 13:42:17.490903 TX DQ/DQS : PASS
7044 13:42:17.494388 RX DATLAT : PASS
7045 13:42:17.497312 RX DQ/DQS(Engine): PASS
7046 13:42:17.497393 TX OE : NO K
7047 13:42:17.500999 All Pass.
7048 13:42:17.501079
7049 13:42:17.501143 CH 1, Rank 0
7050 13:42:17.503908 SW Impedance : PASS
7051 13:42:17.503990 DUTY Scan : NO K
7052 13:42:17.507717 ZQ Calibration : PASS
7053 13:42:17.510756 Jitter Meter : NO K
7054 13:42:17.510837 CBT Training : PASS
7055 13:42:17.514500 Write leveling : PASS
7056 13:42:17.517469 RX DQS gating : PASS
7057 13:42:17.517550 RX DQ/DQS(RDDQC) : PASS
7058 13:42:17.521041 TX DQ/DQS : PASS
7059 13:42:17.521138 RX DATLAT : PASS
7060 13:42:17.524278 RX DQ/DQS(Engine): PASS
7061 13:42:17.527463 TX OE : NO K
7062 13:42:17.527591 All Pass.
7063 13:42:17.527699
7064 13:42:17.527821 CH 1, Rank 1
7065 13:42:17.531199 SW Impedance : PASS
7066 13:42:17.534102 DUTY Scan : NO K
7067 13:42:17.534198 ZQ Calibration : PASS
7068 13:42:17.537781 Jitter Meter : NO K
7069 13:42:17.540835 CBT Training : PASS
7070 13:42:17.540933 Write leveling : NO K
7071 13:42:17.543883 RX DQS gating : PASS
7072 13:42:17.547600 RX DQ/DQS(RDDQC) : PASS
7073 13:42:17.547680 TX DQ/DQS : PASS
7074 13:42:17.550653 RX DATLAT : PASS
7075 13:42:17.554033 RX DQ/DQS(Engine): PASS
7076 13:42:17.554131 TX OE : NO K
7077 13:42:17.557393 All Pass.
7078 13:42:17.557516
7079 13:42:17.557651 DramC Write-DBI off
7080 13:42:17.560687 PER_BANK_REFRESH: Hybrid Mode
7081 13:42:17.560814 TX_TRACKING: ON
7082 13:42:17.570727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7083 13:42:17.573917 [FAST_K] Save calibration result to emmc
7084 13:42:17.577660 dramc_set_vcore_voltage set vcore to 725000
7085 13:42:17.580533 Read voltage for 1600, 0
7086 13:42:17.580611 Vio18 = 0
7087 13:42:17.584385 Vcore = 725000
7088 13:42:17.584479 Vdram = 0
7089 13:42:17.584570 Vddq = 0
7090 13:42:17.587293 Vmddr = 0
7091 13:42:17.590790 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7092 13:42:17.597026 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7093 13:42:17.597118 MEM_TYPE=3, freq_sel=13
7094 13:42:17.600705 sv_algorithm_assistance_LP4_3733
7095 13:42:17.603764 ============ PULL DRAM RESETB DOWN ============
7096 13:42:17.610285 ========== PULL DRAM RESETB DOWN end =========
7097 13:42:17.614023 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7098 13:42:17.617007 ===================================
7099 13:42:17.620755 LPDDR4 DRAM CONFIGURATION
7100 13:42:17.623479 ===================================
7101 13:42:17.623583 EX_ROW_EN[0] = 0x0
7102 13:42:17.627257 EX_ROW_EN[1] = 0x0
7103 13:42:17.630162 LP4Y_EN = 0x0
7104 13:42:17.630268 WORK_FSP = 0x1
7105 13:42:17.633780 WL = 0x5
7106 13:42:17.633861 RL = 0x5
7107 13:42:17.637397 BL = 0x2
7108 13:42:17.637505 RPST = 0x0
7109 13:42:17.640059 RD_PRE = 0x0
7110 13:42:17.640136 WR_PRE = 0x1
7111 13:42:17.643821 WR_PST = 0x1
7112 13:42:17.643908 DBI_WR = 0x0
7113 13:42:17.647475 DBI_RD = 0x0
7114 13:42:17.647558 OTF = 0x1
7115 13:42:17.650164 ===================================
7116 13:42:17.654083 ===================================
7117 13:42:17.657034 ANA top config
7118 13:42:17.660641 ===================================
7119 13:42:17.660730 DLL_ASYNC_EN = 0
7120 13:42:17.663612 ALL_SLAVE_EN = 0
7121 13:42:17.667415 NEW_RANK_MODE = 1
7122 13:42:17.670049 DLL_IDLE_MODE = 1
7123 13:42:17.670127 LP45_APHY_COMB_EN = 1
7124 13:42:17.673447 TX_ODT_DIS = 0
7125 13:42:17.676951 NEW_8X_MODE = 1
7126 13:42:17.680428 ===================================
7127 13:42:17.683343 ===================================
7128 13:42:17.687071 data_rate = 3200
7129 13:42:17.690129 CKR = 1
7130 13:42:17.693685 DQ_P2S_RATIO = 8
7131 13:42:17.696771 ===================================
7132 13:42:17.696877 CA_P2S_RATIO = 8
7133 13:42:17.700356 DQ_CA_OPEN = 0
7134 13:42:17.703413 DQ_SEMI_OPEN = 0
7135 13:42:17.706926 CA_SEMI_OPEN = 0
7136 13:42:17.709978 CA_FULL_RATE = 0
7137 13:42:17.713581 DQ_CKDIV4_EN = 0
7138 13:42:17.713668 CA_CKDIV4_EN = 0
7139 13:42:17.716473 CA_PREDIV_EN = 0
7140 13:42:17.720283 PH8_DLY = 12
7141 13:42:17.723226 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7142 13:42:17.726337 DQ_AAMCK_DIV = 4
7143 13:42:17.730190 CA_AAMCK_DIV = 4
7144 13:42:17.730298 CA_ADMCK_DIV = 4
7145 13:42:17.733287 DQ_TRACK_CA_EN = 0
7146 13:42:17.736311 CA_PICK = 1600
7147 13:42:17.740221 CA_MCKIO = 1600
7148 13:42:17.743234 MCKIO_SEMI = 0
7149 13:42:17.746724 PLL_FREQ = 3068
7150 13:42:17.750081 DQ_UI_PI_RATIO = 32
7151 13:42:17.750161 CA_UI_PI_RATIO = 0
7152 13:42:17.753023 ===================================
7153 13:42:17.756611 ===================================
7154 13:42:17.759924 memory_type:LPDDR4
7155 13:42:17.763345 GP_NUM : 10
7156 13:42:17.763429 SRAM_EN : 1
7157 13:42:17.766747 MD32_EN : 0
7158 13:42:17.769739 ===================================
7159 13:42:17.773404 [ANA_INIT] >>>>>>>>>>>>>>
7160 13:42:17.776449 <<<<<< [CONFIGURE PHASE]: ANA_TX
7161 13:42:17.779440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7162 13:42:17.783020 ===================================
7163 13:42:17.783099 data_rate = 3200,PCW = 0X7600
7164 13:42:17.786607 ===================================
7165 13:42:17.789393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7166 13:42:17.796328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7167 13:42:17.802857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 13:42:17.806476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7169 13:42:17.809321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7170 13:42:17.812866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7171 13:42:17.816030 [ANA_INIT] flow start
7172 13:42:17.819582 [ANA_INIT] PLL >>>>>>>>
7173 13:42:17.819662 [ANA_INIT] PLL <<<<<<<<
7174 13:42:17.822486 [ANA_INIT] MIDPI >>>>>>>>
7175 13:42:17.826114 [ANA_INIT] MIDPI <<<<<<<<
7176 13:42:17.826223 [ANA_INIT] DLL >>>>>>>>
7177 13:42:17.829211 [ANA_INIT] DLL <<<<<<<<
7178 13:42:17.833089 [ANA_INIT] flow end
7179 13:42:17.836107 ============ LP4 DIFF to SE enter ============
7180 13:42:17.839050 ============ LP4 DIFF to SE exit ============
7181 13:42:17.842701 [ANA_INIT] <<<<<<<<<<<<<
7182 13:42:17.845638 [Flow] Enable top DCM control >>>>>
7183 13:42:17.849206 [Flow] Enable top DCM control <<<<<
7184 13:42:17.852314 Enable DLL master slave shuffle
7185 13:42:17.856020 ==============================================================
7186 13:42:17.858824 Gating Mode config
7187 13:42:17.865433 ==============================================================
7188 13:42:17.865544 Config description:
7189 13:42:17.875548 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7190 13:42:17.882226 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7191 13:42:17.885739 SELPH_MODE 0: By rank 1: By Phase
7192 13:42:17.892161 ==============================================================
7193 13:42:17.895595 GAT_TRACK_EN = 1
7194 13:42:17.899317 RX_GATING_MODE = 2
7195 13:42:17.902189 RX_GATING_TRACK_MODE = 2
7196 13:42:17.905515 SELPH_MODE = 1
7197 13:42:17.908830 PICG_EARLY_EN = 1
7198 13:42:17.912042 VALID_LAT_VALUE = 1
7199 13:42:17.915318 ==============================================================
7200 13:42:17.918825 Enter into Gating configuration >>>>
7201 13:42:17.922226 Exit from Gating configuration <<<<
7202 13:42:17.925880 Enter into DVFS_PRE_config >>>>>
7203 13:42:17.938889 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7204 13:42:17.938975 Exit from DVFS_PRE_config <<<<<
7205 13:42:17.942058 Enter into PICG configuration >>>>
7206 13:42:17.945612 Exit from PICG configuration <<<<
7207 13:42:17.948564 [RX_INPUT] configuration >>>>>
7208 13:42:17.952266 [RX_INPUT] configuration <<<<<
7209 13:42:17.958841 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7210 13:42:17.961832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7211 13:42:17.968594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 13:42:17.975217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 13:42:17.982104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 13:42:17.988778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 13:42:17.992215 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7216 13:42:17.995050 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7217 13:42:17.998794 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7218 13:42:18.005160 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7219 13:42:18.008571 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7220 13:42:18.011889 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 13:42:18.015483 ===================================
7222 13:42:18.018733 LPDDR4 DRAM CONFIGURATION
7223 13:42:18.021696 ===================================
7224 13:42:18.021813 EX_ROW_EN[0] = 0x0
7225 13:42:18.025262 EX_ROW_EN[1] = 0x0
7226 13:42:18.028692 LP4Y_EN = 0x0
7227 13:42:18.028766 WORK_FSP = 0x1
7228 13:42:18.032004 WL = 0x5
7229 13:42:18.032073 RL = 0x5
7230 13:42:18.035198 BL = 0x2
7231 13:42:18.035308 RPST = 0x0
7232 13:42:18.038455 RD_PRE = 0x0
7233 13:42:18.038531 WR_PRE = 0x1
7234 13:42:18.041731 WR_PST = 0x1
7235 13:42:18.041841 DBI_WR = 0x0
7236 13:42:18.044917 DBI_RD = 0x0
7237 13:42:18.045000 OTF = 0x1
7238 13:42:18.048330 ===================================
7239 13:42:18.052197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7240 13:42:18.058162 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7241 13:42:18.061946 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 13:42:18.065029 ===================================
7243 13:42:18.068967 LPDDR4 DRAM CONFIGURATION
7244 13:42:18.071895 ===================================
7245 13:42:18.072007 EX_ROW_EN[0] = 0x10
7246 13:42:18.074662 EX_ROW_EN[1] = 0x0
7247 13:42:18.078364 LP4Y_EN = 0x0
7248 13:42:18.078466 WORK_FSP = 0x1
7249 13:42:18.081999 WL = 0x5
7250 13:42:18.082105 RL = 0x5
7251 13:42:18.084914 BL = 0x2
7252 13:42:18.085016 RPST = 0x0
7253 13:42:18.088565 RD_PRE = 0x0
7254 13:42:18.088664 WR_PRE = 0x1
7255 13:42:18.091469 WR_PST = 0x1
7256 13:42:18.091572 DBI_WR = 0x0
7257 13:42:18.095079 DBI_RD = 0x0
7258 13:42:18.095152 OTF = 0x1
7259 13:42:18.098201 ===================================
7260 13:42:18.105224 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7261 13:42:18.105334 ==
7262 13:42:18.108064 Dram Type= 6, Freq= 0, CH_0, rank 0
7263 13:42:18.111822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7264 13:42:18.111924 ==
7265 13:42:18.115009 [Duty_Offset_Calibration]
7266 13:42:18.118584 B0:2 B1:1 CA:1
7267 13:42:18.118659
7268 13:42:18.121465 [DutyScan_Calibration_Flow] k_type=0
7269 13:42:18.129954
7270 13:42:18.130063 ==CLK 0==
7271 13:42:18.133598 Final CLK duty delay cell = 0
7272 13:42:18.136581 [0] MAX Duty = 5156%(X100), DQS PI = 22
7273 13:42:18.139753 [0] MIN Duty = 4876%(X100), DQS PI = 48
7274 13:42:18.143267 [0] AVG Duty = 5016%(X100)
7275 13:42:18.143352
7276 13:42:18.146903 CH0 CLK Duty spec in!! Max-Min= 280%
7277 13:42:18.150272 [DutyScan_Calibration_Flow] ====Done====
7278 13:42:18.150345
7279 13:42:18.152964 [DutyScan_Calibration_Flow] k_type=1
7280 13:42:18.168927
7281 13:42:18.169016 ==DQS 0 ==
7282 13:42:18.172678 Final DQS duty delay cell = -4
7283 13:42:18.175622 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7284 13:42:18.179262 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7285 13:42:18.182312 [-4] AVG Duty = 4891%(X100)
7286 13:42:18.182396
7287 13:42:18.182462 ==DQS 1 ==
7288 13:42:18.186005 Final DQS duty delay cell = 0
7289 13:42:18.189016 [0] MAX Duty = 5187%(X100), DQS PI = 20
7290 13:42:18.192621 [0] MIN Duty = 5031%(X100), DQS PI = 52
7291 13:42:18.195614 [0] AVG Duty = 5109%(X100)
7292 13:42:18.195696
7293 13:42:18.199399 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7294 13:42:18.199482
7295 13:42:18.202424 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7296 13:42:18.205428 [DutyScan_Calibration_Flow] ====Done====
7297 13:42:18.205512
7298 13:42:18.209003 [DutyScan_Calibration_Flow] k_type=3
7299 13:42:18.226346
7300 13:42:18.226433 ==DQM 0 ==
7301 13:42:18.229348 Final DQM duty delay cell = 0
7302 13:42:18.232979 [0] MAX Duty = 5187%(X100), DQS PI = 26
7303 13:42:18.235793 [0] MIN Duty = 4907%(X100), DQS PI = 54
7304 13:42:18.239231 [0] AVG Duty = 5047%(X100)
7305 13:42:18.239312
7306 13:42:18.239407 ==DQM 1 ==
7307 13:42:18.242601 Final DQM duty delay cell = -4
7308 13:42:18.245838 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7309 13:42:18.249151 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7310 13:42:18.252556 [-4] AVG Duty = 4906%(X100)
7311 13:42:18.252656
7312 13:42:18.256158 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7313 13:42:18.256239
7314 13:42:18.258972 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7315 13:42:18.262752 [DutyScan_Calibration_Flow] ====Done====
7316 13:42:18.262833
7317 13:42:18.265757 [DutyScan_Calibration_Flow] k_type=2
7318 13:42:18.283842
7319 13:42:18.283928 ==DQ 0 ==
7320 13:42:18.286886 Final DQ duty delay cell = 0
7321 13:42:18.290057 [0] MAX Duty = 5062%(X100), DQS PI = 24
7322 13:42:18.293253 [0] MIN Duty = 4907%(X100), DQS PI = 0
7323 13:42:18.293335 [0] AVG Duty = 4984%(X100)
7324 13:42:18.293422
7325 13:42:18.296893 ==DQ 1 ==
7326 13:42:18.299906 Final DQ duty delay cell = 0
7327 13:42:18.303671 [0] MAX Duty = 5094%(X100), DQS PI = 4
7328 13:42:18.306645 [0] MIN Duty = 4907%(X100), DQS PI = 34
7329 13:42:18.306726 [0] AVG Duty = 5000%(X100)
7330 13:42:18.306789
7331 13:42:18.310360 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7332 13:42:18.310440
7333 13:42:18.313335 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7334 13:42:18.319944 [DutyScan_Calibration_Flow] ====Done====
7335 13:42:18.320058 ==
7336 13:42:18.323395 Dram Type= 6, Freq= 0, CH_1, rank 0
7337 13:42:18.326845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7338 13:42:18.326926 ==
7339 13:42:18.329947 [Duty_Offset_Calibration]
7340 13:42:18.330047 B0:1 B1:0 CA:0
7341 13:42:18.330137
7342 13:42:18.333584 [DutyScan_Calibration_Flow] k_type=0
7343 13:42:18.342577
7344 13:42:18.342680 ==CLK 0==
7345 13:42:18.346270 Final CLK duty delay cell = -4
7346 13:42:18.349210 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7347 13:42:18.352925 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7348 13:42:18.356203 [-4] AVG Duty = 4906%(X100)
7349 13:42:18.356303
7350 13:42:18.359434 CH1 CLK Duty spec in!! Max-Min= 125%
7351 13:42:18.362389 [DutyScan_Calibration_Flow] ====Done====
7352 13:42:18.362459
7353 13:42:18.365730 [DutyScan_Calibration_Flow] k_type=1
7354 13:42:18.382736
7355 13:42:18.382822 ==DQS 0 ==
7356 13:42:18.385806 Final DQS duty delay cell = 0
7357 13:42:18.389411 [0] MAX Duty = 5094%(X100), DQS PI = 30
7358 13:42:18.393250 [0] MIN Duty = 4844%(X100), DQS PI = 48
7359 13:42:18.393334 [0] AVG Duty = 4969%(X100)
7360 13:42:18.396139
7361 13:42:18.396208 ==DQS 1 ==
7362 13:42:18.399104 Final DQS duty delay cell = 0
7363 13:42:18.402657 [0] MAX Duty = 5249%(X100), DQS PI = 16
7364 13:42:18.405917 [0] MIN Duty = 4969%(X100), DQS PI = 6
7365 13:42:18.409411 [0] AVG Duty = 5109%(X100)
7366 13:42:18.409491
7367 13:42:18.412330 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7368 13:42:18.412444
7369 13:42:18.416063 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7370 13:42:18.419221 [DutyScan_Calibration_Flow] ====Done====
7371 13:42:18.419301
7372 13:42:18.422251 [DutyScan_Calibration_Flow] k_type=3
7373 13:42:18.439754
7374 13:42:18.439842 ==DQM 0 ==
7375 13:42:18.442796 Final DQM duty delay cell = 0
7376 13:42:18.446656 [0] MAX Duty = 5218%(X100), DQS PI = 18
7377 13:42:18.449700 [0] MIN Duty = 4969%(X100), DQS PI = 48
7378 13:42:18.453284 [0] AVG Duty = 5093%(X100)
7379 13:42:18.453390
7380 13:42:18.453482 ==DQM 1 ==
7381 13:42:18.456319 Final DQM duty delay cell = 0
7382 13:42:18.459478 [0] MAX Duty = 5093%(X100), DQS PI = 16
7383 13:42:18.463098 [0] MIN Duty = 4907%(X100), DQS PI = 34
7384 13:42:18.466032 [0] AVG Duty = 5000%(X100)
7385 13:42:18.466138
7386 13:42:18.469864 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7387 13:42:18.469972
7388 13:42:18.473051 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7389 13:42:18.476444 [DutyScan_Calibration_Flow] ====Done====
7390 13:42:18.476546
7391 13:42:18.479272 [DutyScan_Calibration_Flow] k_type=2
7392 13:42:18.496018
7393 13:42:18.496104 ==DQ 0 ==
7394 13:42:18.498829 Final DQ duty delay cell = -4
7395 13:42:18.502454 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7396 13:42:18.505516 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7397 13:42:18.508683 [-4] AVG Duty = 4968%(X100)
7398 13:42:18.508783
7399 13:42:18.508876 ==DQ 1 ==
7400 13:42:18.512372 Final DQ duty delay cell = 0
7401 13:42:18.515775 [0] MAX Duty = 5124%(X100), DQS PI = 18
7402 13:42:18.518505 [0] MIN Duty = 4938%(X100), DQS PI = 8
7403 13:42:18.522142 [0] AVG Duty = 5031%(X100)
7404 13:42:18.522243
7405 13:42:18.525658 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7406 13:42:18.525758
7407 13:42:18.528745 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7408 13:42:18.531871 [DutyScan_Calibration_Flow] ====Done====
7409 13:42:18.535577 nWR fixed to 30
7410 13:42:18.538578 [ModeRegInit_LP4] CH0 RK0
7411 13:42:18.538682 [ModeRegInit_LP4] CH0 RK1
7412 13:42:18.542293 [ModeRegInit_LP4] CH1 RK0
7413 13:42:18.545160 [ModeRegInit_LP4] CH1 RK1
7414 13:42:18.545239 match AC timing 5
7415 13:42:18.552316 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7416 13:42:18.555330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7417 13:42:18.559102 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7418 13:42:18.565054 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7419 13:42:18.568699 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7420 13:42:18.568782 [MiockJmeterHQA]
7421 13:42:18.568849
7422 13:42:18.571649 [DramcMiockJmeter] u1RxGatingPI = 0
7423 13:42:18.575486 0 : 4255, 4029
7424 13:42:18.575598 4 : 4363, 4138
7425 13:42:18.578425 8 : 4253, 4026
7426 13:42:18.578504 12 : 4363, 4138
7427 13:42:18.582136 16 : 4363, 4137
7428 13:42:18.582221 20 : 4257, 4027
7429 13:42:18.582290 24 : 4252, 4027
7430 13:42:18.585029 28 : 4363, 4138
7431 13:42:18.585132 32 : 4257, 4029
7432 13:42:18.588586 36 : 4259, 4029
7433 13:42:18.588663 40 : 4255, 4027
7434 13:42:18.591612 44 : 4255, 4026
7435 13:42:18.591714 48 : 4257, 4030
7436 13:42:18.591807 52 : 4257, 4029
7437 13:42:18.595371 56 : 4257, 4029
7438 13:42:18.595447 60 : 4254, 4027
7439 13:42:18.598401 64 : 4371, 4142
7440 13:42:18.598474 68 : 4257, 4029
7441 13:42:18.601885 72 : 4257, 4031
7442 13:42:18.601958 76 : 4252, 4026
7443 13:42:18.605364 80 : 4257, 4029
7444 13:42:18.605439 84 : 4258, 4032
7445 13:42:18.605501 88 : 4365, 133
7446 13:42:18.608188 92 : 4255, 0
7447 13:42:18.608293 96 : 4255, 0
7448 13:42:18.611603 100 : 4257, 0
7449 13:42:18.611705 104 : 4255, 0
7450 13:42:18.611797 108 : 4253, 0
7451 13:42:18.615064 112 : 4363, 0
7452 13:42:18.615146 116 : 4361, 0
7453 13:42:18.615226 120 : 4250, 0
7454 13:42:18.618715 124 : 4249, 0
7455 13:42:18.618817 128 : 4252, 0
7456 13:42:18.622250 132 : 4361, 0
7457 13:42:18.622329 136 : 4253, 0
7458 13:42:18.622394 140 : 4252, 0
7459 13:42:18.624865 144 : 4361, 0
7460 13:42:18.624966 148 : 4250, 0
7461 13:42:18.628385 152 : 4252, 0
7462 13:42:18.628464 156 : 4250, 0
7463 13:42:18.628530 160 : 4253, 0
7464 13:42:18.632121 164 : 4252, 0
7465 13:42:18.632221 168 : 4360, 0
7466 13:42:18.635121 172 : 4250, 0
7467 13:42:18.635194 176 : 4250, 0
7468 13:42:18.635255 180 : 4252, 0
7469 13:42:18.638856 184 : 4361, 0
7470 13:42:18.638930 188 : 4257, 0
7471 13:42:18.638991 192 : 4252, 0
7472 13:42:18.641823 196 : 4363, 0
7473 13:42:18.641908 200 : 4250, 0
7474 13:42:18.644763 204 : 4252, 877
7475 13:42:18.644847 208 : 4363, 4062
7476 13:42:18.648507 212 : 4250, 4027
7477 13:42:18.648590 216 : 4253, 4027
7478 13:42:18.651498 220 : 4252, 4027
7479 13:42:18.651582 224 : 4252, 4029
7480 13:42:18.651648 228 : 4250, 4027
7481 13:42:18.655163 232 : 4361, 4138
7482 13:42:18.655274 236 : 4363, 4137
7483 13:42:18.658202 240 : 4250, 4027
7484 13:42:18.658313 244 : 4250, 4027
7485 13:42:18.661623 248 : 4250, 4027
7486 13:42:18.661734 252 : 4253, 4027
7487 13:42:18.665115 256 : 4250, 4027
7488 13:42:18.665220 260 : 4363, 4140
7489 13:42:18.667929 264 : 4250, 4027
7490 13:42:18.668037 268 : 4252, 4027
7491 13:42:18.671718 272 : 4252, 4027
7492 13:42:18.671801 276 : 4252, 4029
7493 13:42:18.674602 280 : 4250, 4027
7494 13:42:18.674685 284 : 4363, 4140
7495 13:42:18.678347 288 : 4363, 4138
7496 13:42:18.678431 292 : 4250, 4027
7497 13:42:18.678498 296 : 4250, 4027
7498 13:42:18.681496 300 : 4250, 4027
7499 13:42:18.681580 304 : 4255, 4029
7500 13:42:18.684334 308 : 4253, 3970
7501 13:42:18.684426 312 : 4363, 2223
7502 13:42:18.688279 316 : 4253, 2
7503 13:42:18.688357
7504 13:42:18.688419 MIOCK jitter meter ch=0
7505 13:42:18.691402
7506 13:42:18.691484 1T = (316-88) = 228 dly cells
7507 13:42:18.698085 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7508 13:42:18.698194 ==
7509 13:42:18.701099 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 13:42:18.704857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 13:42:18.704941 ==
7512 13:42:18.711450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 13:42:18.714643 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 13:42:18.721270 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 13:42:18.725000 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 13:42:18.734635 [CA 0] Center 43 (13~74) winsize 62
7517 13:42:18.737807 [CA 1] Center 43 (13~74) winsize 62
7518 13:42:18.741051 [CA 2] Center 38 (9~68) winsize 60
7519 13:42:18.744729 [CA 3] Center 38 (8~68) winsize 61
7520 13:42:18.747820 [CA 4] Center 37 (7~67) winsize 61
7521 13:42:18.751387 [CA 5] Center 35 (6~65) winsize 60
7522 13:42:18.751463
7523 13:42:18.754853 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7524 13:42:18.754929
7525 13:42:18.757974 [CATrainingPosCal] consider 1 rank data
7526 13:42:18.761086 u2DelayCellTimex100 = 285/100 ps
7527 13:42:18.764655 CA0 delay=43 (13~74),Diff = 8 PI (27 cell)
7528 13:42:18.771453 CA1 delay=43 (13~74),Diff = 8 PI (27 cell)
7529 13:42:18.774469 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7530 13:42:18.777792 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7531 13:42:18.781016 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7532 13:42:18.784651 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7533 13:42:18.784763
7534 13:42:18.787348 CA PerBit enable=1, Macro0, CA PI delay=35
7535 13:42:18.787452
7536 13:42:18.791096 [CBTSetCACLKResult] CA Dly = 35
7537 13:42:18.794765 CS Dly: 9 (0~40)
7538 13:42:18.797727 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 13:42:18.801433 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 13:42:18.801541 ==
7541 13:42:18.804319 Dram Type= 6, Freq= 0, CH_0, rank 1
7542 13:42:18.808090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 13:42:18.810883 ==
7544 13:42:18.814518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 13:42:18.817540 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 13:42:18.824282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 13:42:18.827189 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 13:42:18.837787 [CA 0] Center 42 (12~73) winsize 62
7549 13:42:18.841452 [CA 1] Center 42 (12~73) winsize 62
7550 13:42:18.844405 [CA 2] Center 38 (8~68) winsize 61
7551 13:42:18.848077 [CA 3] Center 37 (8~67) winsize 60
7552 13:42:18.850989 [CA 4] Center 36 (6~66) winsize 61
7553 13:42:18.854321 [CA 5] Center 35 (5~65) winsize 61
7554 13:42:18.854426
7555 13:42:18.858322 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7556 13:42:18.858407
7557 13:42:18.861114 [CATrainingPosCal] consider 2 rank data
7558 13:42:18.864358 u2DelayCellTimex100 = 285/100 ps
7559 13:42:18.867832 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7560 13:42:18.874469 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7561 13:42:18.878150 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7562 13:42:18.881069 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7563 13:42:18.884643 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7564 13:42:18.888111 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7565 13:42:18.888225
7566 13:42:18.891158 CA PerBit enable=1, Macro0, CA PI delay=35
7567 13:42:18.891239
7568 13:42:18.894393 [CBTSetCACLKResult] CA Dly = 35
7569 13:42:18.897729 CS Dly: 10 (0~42)
7570 13:42:18.901500 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 13:42:18.904149 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 13:42:18.904255
7573 13:42:18.907911 ----->DramcWriteLeveling(PI) begin...
7574 13:42:18.907995 ==
7575 13:42:18.911642 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 13:42:18.914481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 13:42:18.918206 ==
7578 13:42:18.921191 Write leveling (Byte 0): 37 => 37
7579 13:42:18.921275 Write leveling (Byte 1): 28 => 28
7580 13:42:18.924102 DramcWriteLeveling(PI) end<-----
7581 13:42:18.924185
7582 13:42:18.924250 ==
7583 13:42:18.928117 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 13:42:18.934725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 13:42:18.934809 ==
7586 13:42:18.937505 [Gating] SW mode calibration
7587 13:42:18.944224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7588 13:42:18.947833 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7589 13:42:18.954374 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7590 13:42:18.957900 1 4 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7591 13:42:18.960762 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7592 13:42:18.967507 1 4 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (1 1)
7593 13:42:18.971017 1 4 16 | B1->B0 | 2424 3635 | 0 1 | (0 0) (1 1)
7594 13:42:18.974049 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7595 13:42:18.980484 1 4 24 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (0 0)
7596 13:42:18.984005 1 4 28 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7597 13:42:18.987246 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7598 13:42:18.993942 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7599 13:42:18.997545 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7600 13:42:19.000507 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7601 13:42:19.007467 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7602 13:42:19.010945 1 5 20 | B1->B0 | 2828 2727 | 0 1 | (0 1) (0 0)
7603 13:42:19.013845 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
7604 13:42:19.016969 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7605 13:42:19.023422 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7606 13:42:19.026941 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7607 13:42:19.030614 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7608 13:42:19.037225 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7609 13:42:19.040010 1 6 16 | B1->B0 | 2525 4645 | 0 1 | (0 0) (1 1)
7610 13:42:19.043647 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7611 13:42:19.050279 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 13:42:19.053760 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 13:42:19.057369 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 13:42:19.063678 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 13:42:19.067165 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 13:42:19.070061 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 13:42:19.077347 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 13:42:19.080273 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 13:42:19.083902 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 13:42:19.090460 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:42:19.093884 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:42:19.096449 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:42:19.103526 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:42:19.106669 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:42:19.110244 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:42:19.116896 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:42:19.120311 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 13:42:19.123230 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 13:42:19.129924 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 13:42:19.133350 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:42:19.136544 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 13:42:19.143413 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 13:42:19.146278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7634 13:42:19.149940 Total UI for P1: 0, mck2ui 16
7635 13:42:19.152931 best dqsien dly found for B0: ( 1, 9, 10)
7636 13:42:19.156489 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 13:42:19.160275 Total UI for P1: 0, mck2ui 16
7638 13:42:19.163236 best dqsien dly found for B1: ( 1, 9, 18)
7639 13:42:19.166805 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7640 13:42:19.169821 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7641 13:42:19.169895
7642 13:42:19.173033 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7643 13:42:19.179714 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7644 13:42:19.179819 [Gating] SW calibration Done
7645 13:42:19.179915 ==
7646 13:42:19.183461 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 13:42:19.189845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 13:42:19.189951 ==
7649 13:42:19.190043 RX Vref Scan: 0
7650 13:42:19.190129
7651 13:42:19.193461 RX Vref 0 -> 0, step: 1
7652 13:42:19.193535
7653 13:42:19.196462 RX Delay 0 -> 252, step: 8
7654 13:42:19.199954 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7655 13:42:19.203577 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7656 13:42:19.206597 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7657 13:42:19.210389 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7658 13:42:19.216717 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7659 13:42:19.219937 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7660 13:42:19.223571 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7661 13:42:19.226799 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7662 13:42:19.229886 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7663 13:42:19.236928 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7664 13:42:19.239762 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7665 13:42:19.243317 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7666 13:42:19.246767 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7667 13:42:19.249985 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7668 13:42:19.256742 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7669 13:42:19.260261 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7670 13:42:19.260389 ==
7671 13:42:19.263292 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 13:42:19.266746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 13:42:19.266828 ==
7674 13:42:19.269748 DQS Delay:
7675 13:42:19.269830 DQS0 = 0, DQS1 = 0
7676 13:42:19.269894 DQM Delay:
7677 13:42:19.273493 DQM0 = 137, DQM1 = 130
7678 13:42:19.273573 DQ Delay:
7679 13:42:19.277067 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7680 13:42:19.279651 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7681 13:42:19.283047 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7682 13:42:19.289631 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7683 13:42:19.289712
7684 13:42:19.289776
7685 13:42:19.289834 ==
7686 13:42:19.293240 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 13:42:19.296071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 13:42:19.296152 ==
7689 13:42:19.296237
7690 13:42:19.296296
7691 13:42:19.299766 TX Vref Scan disable
7692 13:42:19.299847 == TX Byte 0 ==
7693 13:42:19.306369 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7694 13:42:19.310011 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7695 13:42:19.310103 == TX Byte 1 ==
7696 13:42:19.316672 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7697 13:42:19.319565 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7698 13:42:19.319646 ==
7699 13:42:19.323363 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 13:42:19.326295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 13:42:19.326403 ==
7702 13:42:19.340136
7703 13:42:19.342869 TX Vref early break, caculate TX vref
7704 13:42:19.346393 TX Vref=16, minBit 0, minWin=23, winSum=382
7705 13:42:19.350047 TX Vref=18, minBit 3, minWin=23, winSum=385
7706 13:42:19.353062 TX Vref=20, minBit 0, minWin=23, winSum=399
7707 13:42:19.356526 TX Vref=22, minBit 0, minWin=24, winSum=406
7708 13:42:19.360019 TX Vref=24, minBit 0, minWin=25, winSum=423
7709 13:42:19.366148 TX Vref=26, minBit 2, minWin=25, winSum=423
7710 13:42:19.369513 TX Vref=28, minBit 6, minWin=24, winSum=418
7711 13:42:19.372879 TX Vref=30, minBit 0, minWin=24, winSum=408
7712 13:42:19.376367 TX Vref=32, minBit 1, minWin=24, winSum=400
7713 13:42:19.383048 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 24
7714 13:42:19.383130
7715 13:42:19.386628 Final TX Range 0 Vref 24
7716 13:42:19.386726
7717 13:42:19.386790 ==
7718 13:42:19.389468 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 13:42:19.393167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 13:42:19.393248 ==
7721 13:42:19.393312
7722 13:42:19.393371
7723 13:42:19.396715 TX Vref Scan disable
7724 13:42:19.399580 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7725 13:42:19.403505 == TX Byte 0 ==
7726 13:42:19.406346 u2DelayCellOfst[0]=10 cells (3 PI)
7727 13:42:19.409985 u2DelayCellOfst[1]=13 cells (4 PI)
7728 13:42:19.412951 u2DelayCellOfst[2]=6 cells (2 PI)
7729 13:42:19.416146 u2DelayCellOfst[3]=10 cells (3 PI)
7730 13:42:19.419765 u2DelayCellOfst[4]=6 cells (2 PI)
7731 13:42:19.419891 u2DelayCellOfst[5]=0 cells (0 PI)
7732 13:42:19.423016 u2DelayCellOfst[6]=13 cells (4 PI)
7733 13:42:19.425951 u2DelayCellOfst[7]=13 cells (4 PI)
7734 13:42:19.432740 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7735 13:42:19.436552 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7736 13:42:19.436662 == TX Byte 1 ==
7737 13:42:19.439548 u2DelayCellOfst[8]=0 cells (0 PI)
7738 13:42:19.442569 u2DelayCellOfst[9]=0 cells (0 PI)
7739 13:42:19.446506 u2DelayCellOfst[10]=6 cells (2 PI)
7740 13:42:19.449262 u2DelayCellOfst[11]=3 cells (1 PI)
7741 13:42:19.452686 u2DelayCellOfst[12]=10 cells (3 PI)
7742 13:42:19.456081 u2DelayCellOfst[13]=10 cells (3 PI)
7743 13:42:19.459589 u2DelayCellOfst[14]=17 cells (5 PI)
7744 13:42:19.462688 u2DelayCellOfst[15]=10 cells (3 PI)
7745 13:42:19.466249 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7746 13:42:19.469268 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7747 13:42:19.473135 DramC Write-DBI on
7748 13:42:19.473244 ==
7749 13:42:19.475988 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 13:42:19.479556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 13:42:19.479667 ==
7752 13:42:19.479765
7753 13:42:19.479859
7754 13:42:19.483074 TX Vref Scan disable
7755 13:42:19.486474 == TX Byte 0 ==
7756 13:42:19.489980 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7757 13:42:19.490091 == TX Byte 1 ==
7758 13:42:19.496324 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7759 13:42:19.496441 DramC Write-DBI off
7760 13:42:19.496538
7761 13:42:19.499411 [DATLAT]
7762 13:42:19.499522 Freq=1600, CH0 RK0
7763 13:42:19.499617
7764 13:42:19.503046 DATLAT Default: 0xf
7765 13:42:19.503129 0, 0xFFFF, sum = 0
7766 13:42:19.506445 1, 0xFFFF, sum = 0
7767 13:42:19.506553 2, 0xFFFF, sum = 0
7768 13:42:19.509391 3, 0xFFFF, sum = 0
7769 13:42:19.509475 4, 0xFFFF, sum = 0
7770 13:42:19.513141 5, 0xFFFF, sum = 0
7771 13:42:19.513225 6, 0xFFFF, sum = 0
7772 13:42:19.516136 7, 0xFFFF, sum = 0
7773 13:42:19.516252 8, 0xFFFF, sum = 0
7774 13:42:19.519982 9, 0xFFFF, sum = 0
7775 13:42:19.520066 10, 0xFFFF, sum = 0
7776 13:42:19.523005 11, 0xFFFF, sum = 0
7777 13:42:19.523089 12, 0xFFFF, sum = 0
7778 13:42:19.526674 13, 0xFFFF, sum = 0
7779 13:42:19.526758 14, 0x0, sum = 1
7780 13:42:19.529614 15, 0x0, sum = 2
7781 13:42:19.529699 16, 0x0, sum = 3
7782 13:42:19.533235 17, 0x0, sum = 4
7783 13:42:19.533347 best_step = 15
7784 13:42:19.533443
7785 13:42:19.533539 ==
7786 13:42:19.536349 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 13:42:19.543026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 13:42:19.543137 ==
7789 13:42:19.543235 RX Vref Scan: 1
7790 13:42:19.543316
7791 13:42:19.546260 Set Vref Range= 24 -> 127
7792 13:42:19.546371
7793 13:42:19.550038 RX Vref 24 -> 127, step: 1
7794 13:42:19.550147
7795 13:42:19.553218 RX Delay 19 -> 252, step: 4
7796 13:42:19.553301
7797 13:42:19.556390 Set Vref, RX VrefLevel [Byte0]: 24
7798 13:42:19.556472 [Byte1]: 24
7799 13:42:19.560816
7800 13:42:19.560898 Set Vref, RX VrefLevel [Byte0]: 25
7801 13:42:19.563796 [Byte1]: 25
7802 13:42:19.568117
7803 13:42:19.568199 Set Vref, RX VrefLevel [Byte0]: 26
7804 13:42:19.571348 [Byte1]: 26
7805 13:42:19.575963
7806 13:42:19.576046 Set Vref, RX VrefLevel [Byte0]: 27
7807 13:42:19.579222 [Byte1]: 27
7808 13:42:19.583617
7809 13:42:19.583732 Set Vref, RX VrefLevel [Byte0]: 28
7810 13:42:19.586604 [Byte1]: 28
7811 13:42:19.591296
7812 13:42:19.591410 Set Vref, RX VrefLevel [Byte0]: 29
7813 13:42:19.594198 [Byte1]: 29
7814 13:42:19.598362
7815 13:42:19.598477 Set Vref, RX VrefLevel [Byte0]: 30
7816 13:42:19.601950 [Byte1]: 30
7817 13:42:19.606296
7818 13:42:19.606404 Set Vref, RX VrefLevel [Byte0]: 31
7819 13:42:19.609243 [Byte1]: 31
7820 13:42:19.613654
7821 13:42:19.613738 Set Vref, RX VrefLevel [Byte0]: 32
7822 13:42:19.616590 [Byte1]: 32
7823 13:42:19.620885
7824 13:42:19.620969 Set Vref, RX VrefLevel [Byte0]: 33
7825 13:42:19.624428 [Byte1]: 33
7826 13:42:19.628864
7827 13:42:19.628976 Set Vref, RX VrefLevel [Byte0]: 34
7828 13:42:19.631980 [Byte1]: 34
7829 13:42:19.636279
7830 13:42:19.636466 Set Vref, RX VrefLevel [Byte0]: 35
7831 13:42:19.639345 [Byte1]: 35
7832 13:42:19.643828
7833 13:42:19.643942 Set Vref, RX VrefLevel [Byte0]: 36
7834 13:42:19.647561 [Byte1]: 36
7835 13:42:19.651262
7836 13:42:19.651375 Set Vref, RX VrefLevel [Byte0]: 37
7837 13:42:19.655107 [Byte1]: 37
7838 13:42:19.659425
7839 13:42:19.659528 Set Vref, RX VrefLevel [Byte0]: 38
7840 13:42:19.662491 [Byte1]: 38
7841 13:42:19.666931
7842 13:42:19.667029 Set Vref, RX VrefLevel [Byte0]: 39
7843 13:42:19.669854 [Byte1]: 39
7844 13:42:19.673876
7845 13:42:19.673961 Set Vref, RX VrefLevel [Byte0]: 40
7846 13:42:19.677567 [Byte1]: 40
7847 13:42:19.682158
7848 13:42:19.682240 Set Vref, RX VrefLevel [Byte0]: 41
7849 13:42:19.685044 [Byte1]: 41
7850 13:42:19.689077
7851 13:42:19.689160 Set Vref, RX VrefLevel [Byte0]: 42
7852 13:42:19.692307 [Byte1]: 42
7853 13:42:19.696717
7854 13:42:19.696825 Set Vref, RX VrefLevel [Byte0]: 43
7855 13:42:19.700015 [Byte1]: 43
7856 13:42:19.704750
7857 13:42:19.704835 Set Vref, RX VrefLevel [Byte0]: 44
7858 13:42:19.707540 [Byte1]: 44
7859 13:42:19.711774
7860 13:42:19.711859 Set Vref, RX VrefLevel [Byte0]: 45
7861 13:42:19.715555 [Byte1]: 45
7862 13:42:19.719539
7863 13:42:19.719627 Set Vref, RX VrefLevel [Byte0]: 46
7864 13:42:19.722949 [Byte1]: 46
7865 13:42:19.727043
7866 13:42:19.727122 Set Vref, RX VrefLevel [Byte0]: 47
7867 13:42:19.730622 [Byte1]: 47
7868 13:42:19.734762
7869 13:42:19.734867 Set Vref, RX VrefLevel [Byte0]: 48
7870 13:42:19.737742 [Byte1]: 48
7871 13:42:19.742101
7872 13:42:19.742182 Set Vref, RX VrefLevel [Byte0]: 49
7873 13:42:19.745861 [Byte1]: 49
7874 13:42:19.750387
7875 13:42:19.750471 Set Vref, RX VrefLevel [Byte0]: 50
7876 13:42:19.753216 [Byte1]: 50
7877 13:42:19.757734
7878 13:42:19.757824 Set Vref, RX VrefLevel [Byte0]: 51
7879 13:42:19.760734 [Byte1]: 51
7880 13:42:19.765208
7881 13:42:19.765297 Set Vref, RX VrefLevel [Byte0]: 52
7882 13:42:19.768122 [Byte1]: 52
7883 13:42:19.772766
7884 13:42:19.772870 Set Vref, RX VrefLevel [Byte0]: 53
7885 13:42:19.775681 [Byte1]: 53
7886 13:42:19.779857
7887 13:42:19.779940 Set Vref, RX VrefLevel [Byte0]: 54
7888 13:42:19.786599 [Byte1]: 54
7889 13:42:19.786684
7890 13:42:19.790521 Set Vref, RX VrefLevel [Byte0]: 55
7891 13:42:19.793515 [Byte1]: 55
7892 13:42:19.793599
7893 13:42:19.796570 Set Vref, RX VrefLevel [Byte0]: 56
7894 13:42:19.800364 [Byte1]: 56
7895 13:42:19.800474
7896 13:42:19.803143 Set Vref, RX VrefLevel [Byte0]: 57
7897 13:42:19.806815 [Byte1]: 57
7898 13:42:19.810219
7899 13:42:19.810302 Set Vref, RX VrefLevel [Byte0]: 58
7900 13:42:19.813586 [Byte1]: 58
7901 13:42:19.818394
7902 13:42:19.818478 Set Vref, RX VrefLevel [Byte0]: 59
7903 13:42:19.821476 [Byte1]: 59
7904 13:42:19.825695
7905 13:42:19.825778 Set Vref, RX VrefLevel [Byte0]: 60
7906 13:42:19.828818 [Byte1]: 60
7907 13:42:19.832927
7908 13:42:19.833040 Set Vref, RX VrefLevel [Byte0]: 61
7909 13:42:19.836703 [Byte1]: 61
7910 13:42:19.840928
7911 13:42:19.841013 Set Vref, RX VrefLevel [Byte0]: 62
7912 13:42:19.844372 [Byte1]: 62
7913 13:42:19.848782
7914 13:42:19.848876 Set Vref, RX VrefLevel [Byte0]: 63
7915 13:42:19.851369 [Byte1]: 63
7916 13:42:19.856156
7917 13:42:19.856268 Set Vref, RX VrefLevel [Byte0]: 64
7918 13:42:19.859641 [Byte1]: 64
7919 13:42:19.863728
7920 13:42:19.863812 Set Vref, RX VrefLevel [Byte0]: 65
7921 13:42:19.866793 [Byte1]: 65
7922 13:42:19.871234
7923 13:42:19.871321 Set Vref, RX VrefLevel [Byte0]: 66
7924 13:42:19.874270 [Byte1]: 66
7925 13:42:19.878797
7926 13:42:19.878905 Set Vref, RX VrefLevel [Byte0]: 67
7927 13:42:19.881694 [Byte1]: 67
7928 13:42:19.886126
7929 13:42:19.886209 Set Vref, RX VrefLevel [Byte0]: 68
7930 13:42:19.889869 [Byte1]: 68
7931 13:42:19.893515
7932 13:42:19.893598 Set Vref, RX VrefLevel [Byte0]: 69
7933 13:42:19.897326 [Byte1]: 69
7934 13:42:19.901097
7935 13:42:19.901180 Set Vref, RX VrefLevel [Byte0]: 70
7936 13:42:19.904791 [Byte1]: 70
7937 13:42:19.909245
7938 13:42:19.909327 Set Vref, RX VrefLevel [Byte0]: 71
7939 13:42:19.912142 [Byte1]: 71
7940 13:42:19.916661
7941 13:42:19.916744 Set Vref, RX VrefLevel [Byte0]: 72
7942 13:42:19.919425 [Byte1]: 72
7943 13:42:19.923857
7944 13:42:19.923939 Set Vref, RX VrefLevel [Byte0]: 73
7945 13:42:19.927594 [Byte1]: 73
7946 13:42:19.932070
7947 13:42:19.932181 Set Vref, RX VrefLevel [Byte0]: 74
7948 13:42:19.934614 [Byte1]: 74
7949 13:42:19.939174
7950 13:42:19.939256 Set Vref, RX VrefLevel [Byte0]: 75
7951 13:42:19.942182 [Byte1]: 75
7952 13:42:19.946567
7953 13:42:19.946653 Set Vref, RX VrefLevel [Byte0]: 76
7954 13:42:19.949876 [Byte1]: 76
7955 13:42:19.954599
7956 13:42:19.954682 Set Vref, RX VrefLevel [Byte0]: 77
7957 13:42:19.957741 [Byte1]: 77
7958 13:42:19.962129
7959 13:42:19.962214 Set Vref, RX VrefLevel [Byte0]: 78
7960 13:42:19.964961 [Byte1]: 78
7961 13:42:19.969727
7962 13:42:19.969810 Final RX Vref Byte 0 = 59 to rank0
7963 13:42:19.973005 Final RX Vref Byte 1 = 61 to rank0
7964 13:42:19.976323 Final RX Vref Byte 0 = 59 to rank1
7965 13:42:19.979234 Final RX Vref Byte 1 = 61 to rank1==
7966 13:42:19.982524 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 13:42:19.989294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 13:42:19.989380 ==
7969 13:42:19.989447 DQS Delay:
7970 13:42:19.989508 DQS0 = 0, DQS1 = 0
7971 13:42:19.993062 DQM Delay:
7972 13:42:19.993146 DQM0 = 134, DQM1 = 127
7973 13:42:19.996020 DQ Delay:
7974 13:42:19.999741 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7975 13:42:20.002803 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7976 13:42:20.006479 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7977 13:42:20.009431 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7978 13:42:20.009515
7979 13:42:20.009581
7980 13:42:20.009642
7981 13:42:20.012486 [DramC_TX_OE_Calibration] TA2
7982 13:42:20.016075 Original DQ_B0 (3 6) =30, OEN = 27
7983 13:42:20.019725 Original DQ_B1 (3 6) =30, OEN = 27
7984 13:42:20.022585 24, 0x0, End_B0=24 End_B1=24
7985 13:42:20.022670 25, 0x0, End_B0=25 End_B1=25
7986 13:42:20.026326 26, 0x0, End_B0=26 End_B1=26
7987 13:42:20.029354 27, 0x0, End_B0=27 End_B1=27
7988 13:42:20.032344 28, 0x0, End_B0=28 End_B1=28
7989 13:42:20.032444 29, 0x0, End_B0=29 End_B1=29
7990 13:42:20.036170 30, 0x0, End_B0=30 End_B1=30
7991 13:42:20.039118 31, 0x4141, End_B0=30 End_B1=30
7992 13:42:20.043051 Byte0 end_step=30 best_step=27
7993 13:42:20.045872 Byte1 end_step=30 best_step=27
7994 13:42:20.049273 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 13:42:20.052756 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 13:42:20.052866
7997 13:42:20.052956
7998 13:42:20.059023 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7999 13:42:20.062463 CH0 RK0: MR19=303, MR18=2622
8000 13:42:20.068778 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
8001 13:42:20.068875
8002 13:42:20.072192 ----->DramcWriteLeveling(PI) begin...
8003 13:42:20.072300 ==
8004 13:42:20.075679 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 13:42:20.079147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 13:42:20.079248 ==
8007 13:42:20.082737 Write leveling (Byte 0): 35 => 35
8008 13:42:20.085425 Write leveling (Byte 1): 29 => 29
8009 13:42:20.089123 DramcWriteLeveling(PI) end<-----
8010 13:42:20.089207
8011 13:42:20.089273 ==
8012 13:42:20.092524 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 13:42:20.095861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 13:42:20.095943 ==
8015 13:42:20.099333 [Gating] SW mode calibration
8016 13:42:20.105957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 13:42:20.112492 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 13:42:20.115520 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8019 13:42:20.119221 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8020 13:42:20.126173 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 13:42:20.129067 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8022 13:42:20.132110 1 4 16 | B1->B0 | 3434 3636 | 0 0 | (0 0) (1 1)
8023 13:42:20.139014 1 4 20 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
8024 13:42:20.142769 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8025 13:42:20.145778 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 13:42:20.152507 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8027 13:42:20.155345 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
8028 13:42:20.159111 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 0) (1 0)
8029 13:42:20.165720 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
8030 13:42:20.168496 1 5 16 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (1 0)
8031 13:42:20.172305 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8032 13:42:20.178575 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8033 13:42:20.182298 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8034 13:42:20.185676 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8035 13:42:20.191827 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8036 13:42:20.195579 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8037 13:42:20.198530 1 6 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8038 13:42:20.205692 1 6 16 | B1->B0 | 3e3e 4645 | 1 1 | (0 0) (0 0)
8039 13:42:20.208688 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8040 13:42:20.212186 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 13:42:20.218262 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 13:42:20.221898 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 13:42:20.225290 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 13:42:20.231899 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 13:42:20.235022 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 13:42:20.238842 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8047 13:42:20.242002 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 13:42:20.248636 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 13:42:20.251661 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 13:42:20.255064 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 13:42:20.261468 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 13:42:20.265198 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 13:42:20.268790 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 13:42:20.274770 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 13:42:20.278348 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 13:42:20.281872 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 13:42:20.288049 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 13:42:20.291527 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 13:42:20.294816 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 13:42:20.301423 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 13:42:20.304791 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8062 13:42:20.308345 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8063 13:42:20.314828 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 13:42:20.314912 Total UI for P1: 0, mck2ui 16
8065 13:42:20.321244 best dqsien dly found for B0: ( 1, 9, 12)
8066 13:42:20.321328 Total UI for P1: 0, mck2ui 16
8067 13:42:20.328256 best dqsien dly found for B1: ( 1, 9, 14)
8068 13:42:20.331969 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8069 13:42:20.334725 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8070 13:42:20.334809
8071 13:42:20.338198 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8072 13:42:20.341572 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8073 13:42:20.344755 [Gating] SW calibration Done
8074 13:42:20.344839 ==
8075 13:42:20.348471 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 13:42:20.351381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 13:42:20.351467 ==
8078 13:42:20.355254 RX Vref Scan: 0
8079 13:42:20.355337
8080 13:42:20.355402 RX Vref 0 -> 0, step: 1
8081 13:42:20.355463
8082 13:42:20.358203 RX Delay 0 -> 252, step: 8
8083 13:42:20.361831 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8084 13:42:20.368363 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8085 13:42:20.371346 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8086 13:42:20.375007 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8087 13:42:20.377789 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8088 13:42:20.381423 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8089 13:42:20.388172 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8090 13:42:20.391023 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8091 13:42:20.394725 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8092 13:42:20.398302 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8093 13:42:20.401132 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8094 13:42:20.408141 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8095 13:42:20.411615 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8096 13:42:20.414415 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8097 13:42:20.417818 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8098 13:42:20.421175 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8099 13:42:20.424895 ==
8100 13:42:20.424978 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 13:42:20.431165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 13:42:20.431249 ==
8103 13:42:20.431314 DQS Delay:
8104 13:42:20.434627 DQS0 = 0, DQS1 = 0
8105 13:42:20.434710 DQM Delay:
8106 13:42:20.437557 DQM0 = 137, DQM1 = 128
8107 13:42:20.437638 DQ Delay:
8108 13:42:20.441119 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8109 13:42:20.444716 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8110 13:42:20.447562 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8111 13:42:20.451228 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8112 13:42:20.451310
8113 13:42:20.451375
8114 13:42:20.451434 ==
8115 13:42:20.454705 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:42:20.460863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:42:20.460945 ==
8118 13:42:20.461009
8119 13:42:20.461069
8120 13:42:20.461126 TX Vref Scan disable
8121 13:42:20.464764 == TX Byte 0 ==
8122 13:42:20.468031 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8123 13:42:20.471182 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8124 13:42:20.474585 == TX Byte 1 ==
8125 13:42:20.478198 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8126 13:42:20.481095 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8127 13:42:20.484741 ==
8128 13:42:20.487653 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 13:42:20.491263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 13:42:20.491345 ==
8131 13:42:20.504277
8132 13:42:20.508073 TX Vref early break, caculate TX vref
8133 13:42:20.510764 TX Vref=16, minBit 1, minWin=22, winSum=383
8134 13:42:20.515013 TX Vref=18, minBit 0, minWin=23, winSum=394
8135 13:42:20.517905 TX Vref=20, minBit 1, minWin=24, winSum=406
8136 13:42:20.520829 TX Vref=22, minBit 0, minWin=24, winSum=407
8137 13:42:20.524336 TX Vref=24, minBit 1, minWin=25, winSum=423
8138 13:42:20.527704 TX Vref=26, minBit 1, minWin=25, winSum=425
8139 13:42:20.534303 TX Vref=28, minBit 7, minWin=25, winSum=427
8140 13:42:20.537759 TX Vref=30, minBit 1, minWin=25, winSum=419
8141 13:42:20.541395 TX Vref=32, minBit 0, minWin=25, winSum=411
8142 13:42:20.544222 TX Vref=34, minBit 1, minWin=24, winSum=401
8143 13:42:20.550887 [TxChooseVref] Worse bit 7, Min win 25, Win sum 427, Final Vref 28
8144 13:42:20.550970
8145 13:42:20.554674 Final TX Range 0 Vref 28
8146 13:42:20.554757
8147 13:42:20.554822 ==
8148 13:42:20.557463 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 13:42:20.561137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 13:42:20.561245 ==
8151 13:42:20.561338
8152 13:42:20.561426
8153 13:42:20.564193 TX Vref Scan disable
8154 13:42:20.571354 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8155 13:42:20.571436 == TX Byte 0 ==
8156 13:42:20.574287 u2DelayCellOfst[0]=13 cells (4 PI)
8157 13:42:20.577898 u2DelayCellOfst[1]=17 cells (5 PI)
8158 13:42:20.580663 u2DelayCellOfst[2]=10 cells (3 PI)
8159 13:42:20.584006 u2DelayCellOfst[3]=10 cells (3 PI)
8160 13:42:20.587773 u2DelayCellOfst[4]=6 cells (2 PI)
8161 13:42:20.590936 u2DelayCellOfst[5]=0 cells (0 PI)
8162 13:42:20.594252 u2DelayCellOfst[6]=13 cells (4 PI)
8163 13:42:20.594334 u2DelayCellOfst[7]=13 cells (4 PI)
8164 13:42:20.600581 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8165 13:42:20.604132 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8166 13:42:20.604239 == TX Byte 1 ==
8167 13:42:20.607791 u2DelayCellOfst[8]=0 cells (0 PI)
8168 13:42:20.610720 u2DelayCellOfst[9]=0 cells (0 PI)
8169 13:42:20.614285 u2DelayCellOfst[10]=6 cells (2 PI)
8170 13:42:20.617363 u2DelayCellOfst[11]=3 cells (1 PI)
8171 13:42:20.621162 u2DelayCellOfst[12]=10 cells (3 PI)
8172 13:42:20.624372 u2DelayCellOfst[13]=10 cells (3 PI)
8173 13:42:20.627291 u2DelayCellOfst[14]=13 cells (4 PI)
8174 13:42:20.630930 u2DelayCellOfst[15]=10 cells (3 PI)
8175 13:42:20.634494 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8176 13:42:20.637204 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8177 13:42:20.640633 DramC Write-DBI on
8178 13:42:20.640714 ==
8179 13:42:20.644136 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 13:42:20.647508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 13:42:20.647590 ==
8182 13:42:20.647655
8183 13:42:20.650804
8184 13:42:20.650885 TX Vref Scan disable
8185 13:42:20.654220 == TX Byte 0 ==
8186 13:42:20.657149 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8187 13:42:20.660727 == TX Byte 1 ==
8188 13:42:20.663780 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8189 13:42:20.663863 DramC Write-DBI off
8190 13:42:20.667351
8191 13:42:20.667434 [DATLAT]
8192 13:42:20.667514 Freq=1600, CH0 RK1
8193 13:42:20.667575
8194 13:42:20.670230 DATLAT Default: 0xf
8195 13:42:20.670313 0, 0xFFFF, sum = 0
8196 13:42:20.673965 1, 0xFFFF, sum = 0
8197 13:42:20.674049 2, 0xFFFF, sum = 0
8198 13:42:20.677557 3, 0xFFFF, sum = 0
8199 13:42:20.677640 4, 0xFFFF, sum = 0
8200 13:42:20.680529 5, 0xFFFF, sum = 0
8201 13:42:20.680630 6, 0xFFFF, sum = 0
8202 13:42:20.684045 7, 0xFFFF, sum = 0
8203 13:42:20.686948 8, 0xFFFF, sum = 0
8204 13:42:20.687066 9, 0xFFFF, sum = 0
8205 13:42:20.690518 10, 0xFFFF, sum = 0
8206 13:42:20.690591 11, 0xFFFF, sum = 0
8207 13:42:20.693972 12, 0xFFFF, sum = 0
8208 13:42:20.694080 13, 0xFFFF, sum = 0
8209 13:42:20.697644 14, 0x0, sum = 1
8210 13:42:20.697748 15, 0x0, sum = 2
8211 13:42:20.700498 16, 0x0, sum = 3
8212 13:42:20.700578 17, 0x0, sum = 4
8213 13:42:20.700642 best_step = 15
8214 13:42:20.704050
8215 13:42:20.704155 ==
8216 13:42:20.707500 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 13:42:20.710824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 13:42:20.710905 ==
8219 13:42:20.710969 RX Vref Scan: 0
8220 13:42:20.711029
8221 13:42:20.714219 RX Vref 0 -> 0, step: 1
8222 13:42:20.714298
8223 13:42:20.717332 RX Delay 19 -> 252, step: 4
8224 13:42:20.720950 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8225 13:42:20.723749 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8226 13:42:20.730905 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8227 13:42:20.734036 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8228 13:42:20.737470 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8229 13:42:20.740613 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8230 13:42:20.743905 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8231 13:42:20.751186 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8232 13:42:20.754059 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8233 13:42:20.757615 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8234 13:42:20.760870 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8235 13:42:20.764128 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8236 13:42:20.770863 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8237 13:42:20.773727 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8238 13:42:20.777201 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8239 13:42:20.780987 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8240 13:42:20.781068 ==
8241 13:42:20.783724 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 13:42:20.790422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 13:42:20.790504 ==
8244 13:42:20.790583 DQS Delay:
8245 13:42:20.790667 DQS0 = 0, DQS1 = 0
8246 13:42:20.794174 DQM Delay:
8247 13:42:20.794265 DQM0 = 134, DQM1 = 127
8248 13:42:20.797461 DQ Delay:
8249 13:42:20.800360 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8250 13:42:20.804048 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8251 13:42:20.807101 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8252 13:42:20.810839 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8253 13:42:20.810919
8254 13:42:20.810981
8255 13:42:20.811040
8256 13:42:20.813785 [DramC_TX_OE_Calibration] TA2
8257 13:42:20.817504 Original DQ_B0 (3 6) =30, OEN = 27
8258 13:42:20.820412 Original DQ_B1 (3 6) =30, OEN = 27
8259 13:42:20.824044 24, 0x0, End_B0=24 End_B1=24
8260 13:42:20.824152 25, 0x0, End_B0=25 End_B1=25
8261 13:42:20.827486 26, 0x0, End_B0=26 End_B1=26
8262 13:42:20.830703 27, 0x0, End_B0=27 End_B1=27
8263 13:42:20.834250 28, 0x0, End_B0=28 End_B1=28
8264 13:42:20.834332 29, 0x0, End_B0=29 End_B1=29
8265 13:42:20.837126 30, 0x0, End_B0=30 End_B1=30
8266 13:42:20.840758 31, 0x4545, End_B0=30 End_B1=30
8267 13:42:20.843498 Byte0 end_step=30 best_step=27
8268 13:42:20.847136 Byte1 end_step=30 best_step=27
8269 13:42:20.850697 Byte0 TX OE(2T, 0.5T) = (3, 3)
8270 13:42:20.853494 Byte1 TX OE(2T, 0.5T) = (3, 3)
8271 13:42:20.853574
8272 13:42:20.853637
8273 13:42:20.860084 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8274 13:42:20.863520 CH0 RK1: MR19=303, MR18=220B
8275 13:42:20.870320 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8276 13:42:20.873679 [RxdqsGatingPostProcess] freq 1600
8277 13:42:20.877408 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8278 13:42:20.880170 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 13:42:20.883799 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 13:42:20.887342 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 13:42:20.890306 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 13:42:20.893842 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 13:42:20.896883 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 13:42:20.900253 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 13:42:20.903847 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 13:42:20.906759 Pre-setting of DQS Precalculation
8287 13:42:20.910441 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8288 13:42:20.910524 ==
8289 13:42:20.914123 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 13:42:20.916930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 13:42:20.917012 ==
8292 13:42:20.923366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8293 13:42:20.927026 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8294 13:42:20.933647 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8295 13:42:20.937267 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8296 13:42:20.947148 [CA 0] Center 41 (12~71) winsize 60
8297 13:42:20.950398 [CA 1] Center 41 (12~71) winsize 60
8298 13:42:20.953610 [CA 2] Center 38 (9~68) winsize 60
8299 13:42:20.957159 [CA 3] Center 37 (9~66) winsize 58
8300 13:42:20.960109 [CA 4] Center 37 (8~67) winsize 60
8301 13:42:20.963034 [CA 5] Center 36 (7~66) winsize 60
8302 13:42:20.963118
8303 13:42:20.966661 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8304 13:42:20.966763
8305 13:42:20.969841 [CATrainingPosCal] consider 1 rank data
8306 13:42:20.973311 u2DelayCellTimex100 = 285/100 ps
8307 13:42:20.976691 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8308 13:42:20.983545 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8309 13:42:20.986194 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8310 13:42:20.989995 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8311 13:42:20.992988 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8312 13:42:20.996564 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8313 13:42:20.996645
8314 13:42:20.999495 CA PerBit enable=1, Macro0, CA PI delay=36
8315 13:42:20.999577
8316 13:42:21.003088 [CBTSetCACLKResult] CA Dly = 36
8317 13:42:21.006695 CS Dly: 10 (0~41)
8318 13:42:21.009491 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8319 13:42:21.013219 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8320 13:42:21.013302 ==
8321 13:42:21.016152 Dram Type= 6, Freq= 0, CH_1, rank 1
8322 13:42:21.019918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 13:42:21.022731 ==
8324 13:42:21.026386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 13:42:21.029276 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 13:42:21.036455 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 13:42:21.043069 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 13:42:21.049563 [CA 0] Center 42 (13~72) winsize 60
8329 13:42:21.053241 [CA 1] Center 42 (13~72) winsize 60
8330 13:42:21.056770 [CA 2] Center 39 (10~68) winsize 59
8331 13:42:21.059859 [CA 3] Center 38 (9~68) winsize 60
8332 13:42:21.063130 [CA 4] Center 39 (9~69) winsize 61
8333 13:42:21.066513 [CA 5] Center 38 (9~67) winsize 59
8334 13:42:21.066612
8335 13:42:21.069983 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8336 13:42:21.070059
8337 13:42:21.073035 [CATrainingPosCal] consider 2 rank data
8338 13:42:21.076548 u2DelayCellTimex100 = 285/100 ps
8339 13:42:21.082668 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8340 13:42:21.086672 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8341 13:42:21.089540 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8342 13:42:21.093106 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8343 13:42:21.096158 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8344 13:42:21.099499 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8345 13:42:21.099579
8346 13:42:21.102831 CA PerBit enable=1, Macro0, CA PI delay=37
8347 13:42:21.102911
8348 13:42:21.106665 [CBTSetCACLKResult] CA Dly = 37
8349 13:42:21.109854 CS Dly: 11 (0~44)
8350 13:42:21.113124 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 13:42:21.116016 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 13:42:21.116120
8353 13:42:21.119754 ----->DramcWriteLeveling(PI) begin...
8354 13:42:21.119835 ==
8355 13:42:21.123379 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 13:42:21.129997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 13:42:21.130079 ==
8358 13:42:21.132977 Write leveling (Byte 0): 26 => 26
8359 13:42:21.133061 Write leveling (Byte 1): 28 => 28
8360 13:42:21.136654 DramcWriteLeveling(PI) end<-----
8361 13:42:21.136727
8362 13:42:21.136805 ==
8363 13:42:21.139607 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 13:42:21.146141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 13:42:21.146249 ==
8366 13:42:21.149738 [Gating] SW mode calibration
8367 13:42:21.156518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8368 13:42:21.159351 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8369 13:42:21.166046 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 13:42:21.169552 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 13:42:21.173165 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8372 13:42:21.179206 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 13:42:21.182675 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 13:42:21.186078 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 13:42:21.192736 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 13:42:21.196110 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 13:42:21.199439 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 13:42:21.206150 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 13:42:21.209147 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
8380 13:42:21.212692 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8381 13:42:21.218953 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8382 13:42:21.222220 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 13:42:21.226097 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 13:42:21.232473 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 13:42:21.236097 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 13:42:21.239035 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:42:21.245663 1 6 8 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (1 1)
8388 13:42:21.249301 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 13:42:21.252260 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 13:42:21.255348 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 13:42:21.262448 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 13:42:21.265454 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 13:42:21.269073 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 13:42:21.275694 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 13:42:21.279201 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 13:42:21.282038 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 13:42:21.288741 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:42:21.292346 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:42:21.295324 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:42:21.302030 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:42:21.305409 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 13:42:21.309039 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 13:42:21.315702 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:42:21.319001 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 13:42:21.322055 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 13:42:21.329065 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:42:21.332064 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 13:42:21.335594 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 13:42:21.342416 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 13:42:21.345882 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 13:42:21.348527 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 13:42:21.352234 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8413 13:42:21.358748 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 13:42:21.362393 Total UI for P1: 0, mck2ui 16
8415 13:42:21.365352 best dqsien dly found for B0: ( 1, 9, 10)
8416 13:42:21.368363 Total UI for P1: 0, mck2ui 16
8417 13:42:21.371892 best dqsien dly found for B1: ( 1, 9, 10)
8418 13:42:21.375672 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8419 13:42:21.378578 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8420 13:42:21.378658
8421 13:42:21.382226 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8422 13:42:21.384920 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8423 13:42:21.388604 [Gating] SW calibration Done
8424 13:42:21.388685 ==
8425 13:42:21.392212 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 13:42:21.395175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 13:42:21.395256 ==
8428 13:42:21.398076 RX Vref Scan: 0
8429 13:42:21.398156
8430 13:42:21.401769 RX Vref 0 -> 0, step: 1
8431 13:42:21.401850
8432 13:42:21.401912 RX Delay 0 -> 252, step: 8
8433 13:42:21.408254 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8434 13:42:21.411756 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8435 13:42:21.414659 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8436 13:42:21.418280 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8437 13:42:21.421826 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8438 13:42:21.428370 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8439 13:42:21.431101 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8440 13:42:21.435001 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8441 13:42:21.438137 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8442 13:42:21.441348 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8443 13:42:21.448283 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8444 13:42:21.451133 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8445 13:42:21.454717 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8446 13:42:21.458206 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8447 13:42:21.461881 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8448 13:42:21.467645 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8449 13:42:21.467727 ==
8450 13:42:21.471306 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 13:42:21.474461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 13:42:21.474543 ==
8453 13:42:21.474608 DQS Delay:
8454 13:42:21.477756 DQS0 = 0, DQS1 = 0
8455 13:42:21.477838 DQM Delay:
8456 13:42:21.480690 DQM0 = 136, DQM1 = 132
8457 13:42:21.480771 DQ Delay:
8458 13:42:21.484328 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8459 13:42:21.487745 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8460 13:42:21.490685 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8461 13:42:21.494428 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8462 13:42:21.497844
8463 13:42:21.497926
8464 13:42:21.497990 ==
8465 13:42:21.500887 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 13:42:21.504470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 13:42:21.504551 ==
8468 13:42:21.504614
8469 13:42:21.504673
8470 13:42:21.508095 TX Vref Scan disable
8471 13:42:21.508232 == TX Byte 0 ==
8472 13:42:21.514639 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 13:42:21.517534 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8474 13:42:21.517614 == TX Byte 1 ==
8475 13:42:21.524559 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8476 13:42:21.527398 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8477 13:42:21.527480 ==
8478 13:42:21.530929 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 13:42:21.534609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 13:42:21.534690 ==
8481 13:42:21.547429
8482 13:42:21.550907 TX Vref early break, caculate TX vref
8483 13:42:21.554415 TX Vref=16, minBit 1, minWin=22, winSum=374
8484 13:42:21.557771 TX Vref=18, minBit 1, minWin=23, winSum=387
8485 13:42:21.560972 TX Vref=20, minBit 0, minWin=24, winSum=400
8486 13:42:21.564381 TX Vref=22, minBit 6, minWin=24, winSum=408
8487 13:42:21.567267 TX Vref=24, minBit 0, minWin=25, winSum=415
8488 13:42:21.573769 TX Vref=26, minBit 0, minWin=25, winSum=427
8489 13:42:21.577127 TX Vref=28, minBit 0, minWin=25, winSum=426
8490 13:42:21.580755 TX Vref=30, minBit 0, minWin=25, winSum=418
8491 13:42:21.584061 TX Vref=32, minBit 0, minWin=24, winSum=409
8492 13:42:21.587474 TX Vref=34, minBit 0, minWin=24, winSum=400
8493 13:42:21.594069 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8494 13:42:21.594146
8495 13:42:21.597333 Final TX Range 0 Vref 26
8496 13:42:21.597409
8497 13:42:21.597475 ==
8498 13:42:21.600609 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 13:42:21.604182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 13:42:21.604283 ==
8501 13:42:21.604397
8502 13:42:21.604472
8503 13:42:21.607155 TX Vref Scan disable
8504 13:42:21.613680 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8505 13:42:21.613781 == TX Byte 0 ==
8506 13:42:21.617311 u2DelayCellOfst[0]=20 cells (6 PI)
8507 13:42:21.620287 u2DelayCellOfst[1]=13 cells (4 PI)
8508 13:42:21.623805 u2DelayCellOfst[2]=0 cells (0 PI)
8509 13:42:21.627494 u2DelayCellOfst[3]=10 cells (3 PI)
8510 13:42:21.630311 u2DelayCellOfst[4]=10 cells (3 PI)
8511 13:42:21.633708 u2DelayCellOfst[5]=20 cells (6 PI)
8512 13:42:21.636788 u2DelayCellOfst[6]=20 cells (6 PI)
8513 13:42:21.636867 u2DelayCellOfst[7]=6 cells (2 PI)
8514 13:42:21.644071 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8515 13:42:21.647054 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 13:42:21.650505 == TX Byte 1 ==
8517 13:42:21.650587 u2DelayCellOfst[8]=0 cells (0 PI)
8518 13:42:21.653333 u2DelayCellOfst[9]=3 cells (1 PI)
8519 13:42:21.656835 u2DelayCellOfst[10]=13 cells (4 PI)
8520 13:42:21.660262 u2DelayCellOfst[11]=6 cells (2 PI)
8521 13:42:21.663906 u2DelayCellOfst[12]=17 cells (5 PI)
8522 13:42:21.667027 u2DelayCellOfst[13]=17 cells (5 PI)
8523 13:42:21.670437 u2DelayCellOfst[14]=17 cells (5 PI)
8524 13:42:21.673809 u2DelayCellOfst[15]=17 cells (5 PI)
8525 13:42:21.677198 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8526 13:42:21.683437 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8527 13:42:21.683550 DramC Write-DBI on
8528 13:42:21.683638 ==
8529 13:42:21.687122 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 13:42:21.690187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 13:42:21.693726 ==
8532 13:42:21.694021
8533 13:42:21.694206
8534 13:42:21.694314 TX Vref Scan disable
8535 13:42:21.696774 == TX Byte 0 ==
8536 13:42:21.700195 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 13:42:21.703668 == TX Byte 1 ==
8538 13:42:21.706603 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8539 13:42:21.709900 DramC Write-DBI off
8540 13:42:21.710053
8541 13:42:21.710162 [DATLAT]
8542 13:42:21.710256 Freq=1600, CH1 RK0
8543 13:42:21.710348
8544 13:42:21.713163 DATLAT Default: 0xf
8545 13:42:21.713269 0, 0xFFFF, sum = 0
8546 13:42:21.717106 1, 0xFFFF, sum = 0
8547 13:42:21.717273 2, 0xFFFF, sum = 0
8548 13:42:21.720120 3, 0xFFFF, sum = 0
8549 13:42:21.723718 4, 0xFFFF, sum = 0
8550 13:42:21.723832 5, 0xFFFF, sum = 0
8551 13:42:21.726639 6, 0xFFFF, sum = 0
8552 13:42:21.726762 7, 0xFFFF, sum = 0
8553 13:42:21.730267 8, 0xFFFF, sum = 0
8554 13:42:21.730352 9, 0xFFFF, sum = 0
8555 13:42:21.733910 10, 0xFFFF, sum = 0
8556 13:42:21.733998 11, 0xFFFF, sum = 0
8557 13:42:21.736830 12, 0xFFFF, sum = 0
8558 13:42:21.736910 13, 0xFFFF, sum = 0
8559 13:42:21.740628 14, 0x0, sum = 1
8560 13:42:21.740710 15, 0x0, sum = 2
8561 13:42:21.743265 16, 0x0, sum = 3
8562 13:42:21.743395 17, 0x0, sum = 4
8563 13:42:21.747111 best_step = 15
8564 13:42:21.747204
8565 13:42:21.747280 ==
8566 13:42:21.750023 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 13:42:21.753978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 13:42:21.754155 ==
8569 13:42:21.756788 RX Vref Scan: 1
8570 13:42:21.756950
8571 13:42:21.757050 Set Vref Range= 24 -> 127
8572 13:42:21.757139
8573 13:42:21.760466 RX Vref 24 -> 127, step: 1
8574 13:42:21.760589
8575 13:42:21.763425 RX Delay 27 -> 252, step: 4
8576 13:42:21.763547
8577 13:42:21.767293 Set Vref, RX VrefLevel [Byte0]: 24
8578 13:42:21.770055 [Byte1]: 24
8579 13:42:21.770242
8580 13:42:21.773752 Set Vref, RX VrefLevel [Byte0]: 25
8581 13:42:21.776768 [Byte1]: 25
8582 13:42:21.777020
8583 13:42:21.780414 Set Vref, RX VrefLevel [Byte0]: 26
8584 13:42:21.783343 [Byte1]: 26
8585 13:42:21.787590
8586 13:42:21.787836 Set Vref, RX VrefLevel [Byte0]: 27
8587 13:42:21.790329 [Byte1]: 27
8588 13:42:21.795005
8589 13:42:21.795306 Set Vref, RX VrefLevel [Byte0]: 28
8590 13:42:21.798418 [Byte1]: 28
8591 13:42:21.802333
8592 13:42:21.802800 Set Vref, RX VrefLevel [Byte0]: 29
8593 13:42:21.806006 [Byte1]: 29
8594 13:42:21.810204
8595 13:42:21.810626 Set Vref, RX VrefLevel [Byte0]: 30
8596 13:42:21.813124 [Byte1]: 30
8597 13:42:21.817470
8598 13:42:21.817953 Set Vref, RX VrefLevel [Byte0]: 31
8599 13:42:21.821066 [Byte1]: 31
8600 13:42:21.824972
8601 13:42:21.825390 Set Vref, RX VrefLevel [Byte0]: 32
8602 13:42:21.828725 [Byte1]: 32
8603 13:42:21.832423
8604 13:42:21.833008 Set Vref, RX VrefLevel [Byte0]: 33
8605 13:42:21.835683 [Byte1]: 33
8606 13:42:21.840530
8607 13:42:21.841082 Set Vref, RX VrefLevel [Byte0]: 34
8608 13:42:21.843853 [Byte1]: 34
8609 13:42:21.848132
8610 13:42:21.848791 Set Vref, RX VrefLevel [Byte0]: 35
8611 13:42:21.851222 [Byte1]: 35
8612 13:42:21.855672
8613 13:42:21.856457 Set Vref, RX VrefLevel [Byte0]: 36
8614 13:42:21.858453 [Byte1]: 36
8615 13:42:21.862806
8616 13:42:21.863435 Set Vref, RX VrefLevel [Byte0]: 37
8617 13:42:21.865878 [Byte1]: 37
8618 13:42:21.870271
8619 13:42:21.870682 Set Vref, RX VrefLevel [Byte0]: 38
8620 13:42:21.874397 [Byte1]: 38
8621 13:42:21.877772
8622 13:42:21.878180 Set Vref, RX VrefLevel [Byte0]: 39
8623 13:42:21.881901 [Byte1]: 39
8624 13:42:21.886191
8625 13:42:21.886713 Set Vref, RX VrefLevel [Byte0]: 40
8626 13:42:21.888712 [Byte1]: 40
8627 13:42:21.893046
8628 13:42:21.893461 Set Vref, RX VrefLevel [Byte0]: 41
8629 13:42:21.896138 [Byte1]: 41
8630 13:42:21.900761
8631 13:42:21.901319 Set Vref, RX VrefLevel [Byte0]: 42
8632 13:42:21.904114 [Byte1]: 42
8633 13:42:21.907690
8634 13:42:21.908104 Set Vref, RX VrefLevel [Byte0]: 43
8635 13:42:21.911107 [Byte1]: 43
8636 13:42:21.915806
8637 13:42:21.916225 Set Vref, RX VrefLevel [Byte0]: 44
8638 13:42:21.918790 [Byte1]: 44
8639 13:42:21.923077
8640 13:42:21.923492 Set Vref, RX VrefLevel [Byte0]: 45
8641 13:42:21.926153 [Byte1]: 45
8642 13:42:21.930291
8643 13:42:21.930711 Set Vref, RX VrefLevel [Byte0]: 46
8644 13:42:21.933820 [Byte1]: 46
8645 13:42:21.938433
8646 13:42:21.938848 Set Vref, RX VrefLevel [Byte0]: 47
8647 13:42:21.941555 [Byte1]: 47
8648 13:42:21.945612
8649 13:42:21.946032 Set Vref, RX VrefLevel [Byte0]: 48
8650 13:42:21.949009 [Byte1]: 48
8651 13:42:21.953128
8652 13:42:21.953542 Set Vref, RX VrefLevel [Byte0]: 49
8653 13:42:21.956763 [Byte1]: 49
8654 13:42:21.961154
8655 13:42:21.961571 Set Vref, RX VrefLevel [Byte0]: 50
8656 13:42:21.963791 [Byte1]: 50
8657 13:42:21.967945
8658 13:42:21.968401 Set Vref, RX VrefLevel [Byte0]: 51
8659 13:42:21.971621 [Byte1]: 51
8660 13:42:21.975890
8661 13:42:21.976311 Set Vref, RX VrefLevel [Byte0]: 52
8662 13:42:21.978791 [Byte1]: 52
8663 13:42:21.983185
8664 13:42:21.983600 Set Vref, RX VrefLevel [Byte0]: 53
8665 13:42:21.987361 [Byte1]: 53
8666 13:42:21.990621
8667 13:42:21.991044 Set Vref, RX VrefLevel [Byte0]: 54
8668 13:42:21.993905 [Byte1]: 54
8669 13:42:21.998495
8670 13:42:21.998998 Set Vref, RX VrefLevel [Byte0]: 55
8671 13:42:22.001419 [Byte1]: 55
8672 13:42:22.005715
8673 13:42:22.006133 Set Vref, RX VrefLevel [Byte0]: 56
8674 13:42:22.009441 [Byte1]: 56
8675 13:42:22.013982
8676 13:42:22.014475 Set Vref, RX VrefLevel [Byte0]: 57
8677 13:42:22.016746 [Byte1]: 57
8678 13:42:22.021256
8679 13:42:22.021744 Set Vref, RX VrefLevel [Byte0]: 58
8680 13:42:22.024149 [Byte1]: 58
8681 13:42:22.028550
8682 13:42:22.028965 Set Vref, RX VrefLevel [Byte0]: 59
8683 13:42:22.031609 [Byte1]: 59
8684 13:42:22.035838
8685 13:42:22.036259 Set Vref, RX VrefLevel [Byte0]: 60
8686 13:42:22.039468 [Byte1]: 60
8687 13:42:22.043893
8688 13:42:22.044438 Set Vref, RX VrefLevel [Byte0]: 61
8689 13:42:22.047137 [Byte1]: 61
8690 13:42:22.051762
8691 13:42:22.052278 Set Vref, RX VrefLevel [Byte0]: 62
8692 13:42:22.054673 [Byte1]: 62
8693 13:42:22.058527
8694 13:42:22.058963 Set Vref, RX VrefLevel [Byte0]: 63
8695 13:42:22.061896 [Byte1]: 63
8696 13:42:22.066777
8697 13:42:22.067285 Set Vref, RX VrefLevel [Byte0]: 64
8698 13:42:22.069698 [Byte1]: 64
8699 13:42:22.073953
8700 13:42:22.074370 Set Vref, RX VrefLevel [Byte0]: 65
8701 13:42:22.077318 [Byte1]: 65
8702 13:42:22.081244
8703 13:42:22.081665 Set Vref, RX VrefLevel [Byte0]: 66
8704 13:42:22.084393 [Byte1]: 66
8705 13:42:22.089003
8706 13:42:22.089447 Set Vref, RX VrefLevel [Byte0]: 67
8707 13:42:22.091981 [Byte1]: 67
8708 13:42:22.096799
8709 13:42:22.097308 Set Vref, RX VrefLevel [Byte0]: 68
8710 13:42:22.099614 [Byte1]: 68
8711 13:42:22.103776
8712 13:42:22.104288 Set Vref, RX VrefLevel [Byte0]: 69
8713 13:42:22.107642 [Byte1]: 69
8714 13:42:22.112050
8715 13:42:22.112690 Set Vref, RX VrefLevel [Byte0]: 70
8716 13:42:22.114617 [Byte1]: 70
8717 13:42:22.119198
8718 13:42:22.119705 Set Vref, RX VrefLevel [Byte0]: 71
8719 13:42:22.122230 [Byte1]: 71
8720 13:42:22.126268
8721 13:42:22.126762 Set Vref, RX VrefLevel [Byte0]: 72
8722 13:42:22.129936 [Byte1]: 72
8723 13:42:22.134154
8724 13:42:22.134630 Set Vref, RX VrefLevel [Byte0]: 73
8725 13:42:22.137177 [Byte1]: 73
8726 13:42:22.141690
8727 13:42:22.142296 Final RX Vref Byte 0 = 58 to rank0
8728 13:42:22.145354 Final RX Vref Byte 1 = 59 to rank0
8729 13:42:22.148445 Final RX Vref Byte 0 = 58 to rank1
8730 13:42:22.151638 Final RX Vref Byte 1 = 59 to rank1==
8731 13:42:22.154794 Dram Type= 6, Freq= 0, CH_1, rank 0
8732 13:42:22.161245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 13:42:22.161715 ==
8734 13:42:22.162078 DQS Delay:
8735 13:42:22.164959 DQS0 = 0, DQS1 = 0
8736 13:42:22.165420 DQM Delay:
8737 13:42:22.165917 DQM0 = 134, DQM1 = 131
8738 13:42:22.167633 DQ Delay:
8739 13:42:22.170975 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8740 13:42:22.174504 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8741 13:42:22.178493 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8742 13:42:22.181772 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8743 13:42:22.182287
8744 13:42:22.182621
8745 13:42:22.182928
8746 13:42:22.184624 [DramC_TX_OE_Calibration] TA2
8747 13:42:22.187980 Original DQ_B0 (3 6) =30, OEN = 27
8748 13:42:22.191178 Original DQ_B1 (3 6) =30, OEN = 27
8749 13:42:22.194211 24, 0x0, End_B0=24 End_B1=24
8750 13:42:22.194637 25, 0x0, End_B0=25 End_B1=25
8751 13:42:22.198194 26, 0x0, End_B0=26 End_B1=26
8752 13:42:22.201089 27, 0x0, End_B0=27 End_B1=27
8753 13:42:22.204080 28, 0x0, End_B0=28 End_B1=28
8754 13:42:22.207946 29, 0x0, End_B0=29 End_B1=29
8755 13:42:22.208524 30, 0x0, End_B0=30 End_B1=30
8756 13:42:22.210940 31, 0x4141, End_B0=30 End_B1=30
8757 13:42:22.214641 Byte0 end_step=30 best_step=27
8758 13:42:22.217938 Byte1 end_step=30 best_step=27
8759 13:42:22.220757 Byte0 TX OE(2T, 0.5T) = (3, 3)
8760 13:42:22.224751 Byte1 TX OE(2T, 0.5T) = (3, 3)
8761 13:42:22.225301
8762 13:42:22.225639
8763 13:42:22.231067 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8764 13:42:22.234562 CH1 RK0: MR19=303, MR18=1725
8765 13:42:22.241045 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8766 13:42:22.241469
8767 13:42:22.243874 ----->DramcWriteLeveling(PI) begin...
8768 13:42:22.244311 ==
8769 13:42:22.247843 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 13:42:22.251164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 13:42:22.251689 ==
8772 13:42:22.254215 Write leveling (Byte 0): 27 => 27
8773 13:42:22.257639 Write leveling (Byte 1): 29 => 29
8774 13:42:22.260809 DramcWriteLeveling(PI) end<-----
8775 13:42:22.261363
8776 13:42:22.261726 ==
8777 13:42:22.264145 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 13:42:22.267628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 13:42:22.268093 ==
8780 13:42:22.270954 [Gating] SW mode calibration
8781 13:42:22.277550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8782 13:42:22.284211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8783 13:42:22.288120 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 13:42:22.294476 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 13:42:22.297593 1 4 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8786 13:42:22.301371 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8787 13:42:22.303825 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 13:42:22.310424 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 13:42:22.313881 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 13:42:22.316981 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 13:42:22.324122 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 13:42:22.327558 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8793 13:42:22.330560 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8794 13:42:22.336889 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8795 13:42:22.340246 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 13:42:22.343451 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 13:42:22.350641 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 13:42:22.354069 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 13:42:22.357778 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 13:42:22.364428 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 13:42:22.367517 1 6 8 | B1->B0 | 403f 2323 | 1 0 | (0 0) (0 0)
8802 13:42:22.371094 1 6 12 | B1->B0 | 4545 3a3a | 0 0 | (0 0) (0 0)
8803 13:42:22.377363 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 13:42:22.380584 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 13:42:22.383822 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 13:42:22.390511 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 13:42:22.393344 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 13:42:22.397306 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8809 13:42:22.403888 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8810 13:42:22.407062 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8811 13:42:22.410503 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8812 13:42:22.416889 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:42:22.420332 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:42:22.423712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 13:42:22.430121 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:42:22.433766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:42:22.437222 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:42:22.439974 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:42:22.446564 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 13:42:22.450437 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 13:42:22.453750 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 13:42:22.460590 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 13:42:22.463509 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 13:42:22.467336 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8825 13:42:22.473948 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8826 13:42:22.477134 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8827 13:42:22.480507 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 13:42:22.483646 Total UI for P1: 0, mck2ui 16
8829 13:42:22.487079 best dqsien dly found for B0: ( 1, 9, 12)
8830 13:42:22.490363 Total UI for P1: 0, mck2ui 16
8831 13:42:22.493522 best dqsien dly found for B1: ( 1, 9, 8)
8832 13:42:22.497081 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8833 13:42:22.500225 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8834 13:42:22.500789
8835 13:42:22.506982 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8836 13:42:22.510665 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8837 13:42:22.511378 [Gating] SW calibration Done
8838 13:42:22.513350 ==
8839 13:42:22.517286 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 13:42:22.519846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 13:42:22.520273 ==
8842 13:42:22.520657 RX Vref Scan: 0
8843 13:42:22.521005
8844 13:42:22.523464 RX Vref 0 -> 0, step: 1
8845 13:42:22.524006
8846 13:42:22.527096 RX Delay 0 -> 252, step: 8
8847 13:42:22.529925 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8848 13:42:22.533289 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8849 13:42:22.536763 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8850 13:42:22.543572 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8851 13:42:22.547237 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8852 13:42:22.549749 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8853 13:42:22.552925 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8854 13:42:22.556964 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8855 13:42:22.562794 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8856 13:42:22.566338 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8857 13:42:22.569621 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8858 13:42:22.572985 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8859 13:42:22.576642 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8860 13:42:22.583106 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8861 13:42:22.586568 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8862 13:42:22.590158 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8863 13:42:22.590579 ==
8864 13:42:22.593015 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 13:42:22.596875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 13:42:22.599872 ==
8867 13:42:22.600446 DQS Delay:
8868 13:42:22.600814 DQS0 = 0, DQS1 = 0
8869 13:42:22.603506 DQM Delay:
8870 13:42:22.604083 DQM0 = 136, DQM1 = 133
8871 13:42:22.606110 DQ Delay:
8872 13:42:22.609746 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8873 13:42:22.613340 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8874 13:42:22.616448 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8875 13:42:22.619672 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8876 13:42:22.620090
8877 13:42:22.620466
8878 13:42:22.620779 ==
8879 13:42:22.623771 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 13:42:22.626689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 13:42:22.627205 ==
8882 13:42:22.627536
8883 13:42:22.627841
8884 13:42:22.630015 TX Vref Scan disable
8885 13:42:22.632887 == TX Byte 0 ==
8886 13:42:22.636540 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8887 13:42:22.639348 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8888 13:42:22.643126 == TX Byte 1 ==
8889 13:42:22.646072 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8890 13:42:22.649482 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8891 13:42:22.649903 ==
8892 13:42:22.653187 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 13:42:22.659333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 13:42:22.659833 ==
8895 13:42:22.672028
8896 13:42:22.675410 TX Vref early break, caculate TX vref
8897 13:42:22.679015 TX Vref=16, minBit 1, minWin=23, winSum=383
8898 13:42:22.681645 TX Vref=18, minBit 0, minWin=23, winSum=394
8899 13:42:22.685152 TX Vref=20, minBit 6, minWin=23, winSum=398
8900 13:42:22.688476 TX Vref=22, minBit 0, minWin=24, winSum=408
8901 13:42:22.691924 TX Vref=24, minBit 0, minWin=25, winSum=417
8902 13:42:22.698495 TX Vref=26, minBit 1, minWin=25, winSum=421
8903 13:42:22.702223 TX Vref=28, minBit 0, minWin=25, winSum=425
8904 13:42:22.704866 TX Vref=30, minBit 0, minWin=26, winSum=421
8905 13:42:22.708592 TX Vref=32, minBit 0, minWin=24, winSum=409
8906 13:42:22.712118 TX Vref=34, minBit 6, minWin=24, winSum=406
8907 13:42:22.715259 TX Vref=36, minBit 1, minWin=23, winSum=395
8908 13:42:22.721976 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
8909 13:42:22.722403
8910 13:42:22.724779 Final TX Range 0 Vref 30
8911 13:42:22.725262
8912 13:42:22.725597 ==
8913 13:42:22.728906 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 13:42:22.731379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 13:42:22.731874 ==
8916 13:42:22.732212
8917 13:42:22.732561
8918 13:42:22.735004 TX Vref Scan disable
8919 13:42:22.741416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8920 13:42:22.741975 == TX Byte 0 ==
8921 13:42:22.744851 u2DelayCellOfst[0]=20 cells (6 PI)
8922 13:42:22.747842 u2DelayCellOfst[1]=13 cells (4 PI)
8923 13:42:22.751437 u2DelayCellOfst[2]=0 cells (0 PI)
8924 13:42:22.755010 u2DelayCellOfst[3]=6 cells (2 PI)
8925 13:42:22.758446 u2DelayCellOfst[4]=10 cells (3 PI)
8926 13:42:22.761379 u2DelayCellOfst[5]=17 cells (5 PI)
8927 13:42:22.764942 u2DelayCellOfst[6]=17 cells (5 PI)
8928 13:42:22.768162 u2DelayCellOfst[7]=6 cells (2 PI)
8929 13:42:22.771111 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8930 13:42:22.774791 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8931 13:42:22.778378 == TX Byte 1 ==
8932 13:42:22.781108 u2DelayCellOfst[8]=0 cells (0 PI)
8933 13:42:22.781543 u2DelayCellOfst[9]=3 cells (1 PI)
8934 13:42:22.784600 u2DelayCellOfst[10]=10 cells (3 PI)
8935 13:42:22.787957 u2DelayCellOfst[11]=3 cells (1 PI)
8936 13:42:22.791176 u2DelayCellOfst[12]=13 cells (4 PI)
8937 13:42:22.794605 u2DelayCellOfst[13]=17 cells (5 PI)
8938 13:42:22.798268 u2DelayCellOfst[14]=13 cells (4 PI)
8939 13:42:22.801239 u2DelayCellOfst[15]=17 cells (5 PI)
8940 13:42:22.805162 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8941 13:42:22.811934 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8942 13:42:22.812395 DramC Write-DBI on
8943 13:42:22.812744 ==
8944 13:42:22.814715 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 13:42:22.821484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 13:42:22.822001 ==
8947 13:42:22.822337
8948 13:42:22.822649
8949 13:42:22.822943 TX Vref Scan disable
8950 13:42:22.824937 == TX Byte 0 ==
8951 13:42:22.828765 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8952 13:42:22.831609 == TX Byte 1 ==
8953 13:42:22.835179 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8954 13:42:22.838190 DramC Write-DBI off
8955 13:42:22.838625
8956 13:42:22.838957 [DATLAT]
8957 13:42:22.839270 Freq=1600, CH1 RK1
8958 13:42:22.839570
8959 13:42:22.842109 DATLAT Default: 0xf
8960 13:42:22.842622 0, 0xFFFF, sum = 0
8961 13:42:22.844898 1, 0xFFFF, sum = 0
8962 13:42:22.845344 2, 0xFFFF, sum = 0
8963 13:42:22.848882 3, 0xFFFF, sum = 0
8964 13:42:22.851418 4, 0xFFFF, sum = 0
8965 13:42:22.851846 5, 0xFFFF, sum = 0
8966 13:42:22.855051 6, 0xFFFF, sum = 0
8967 13:42:22.855536 7, 0xFFFF, sum = 0
8968 13:42:22.858070 8, 0xFFFF, sum = 0
8969 13:42:22.858500 9, 0xFFFF, sum = 0
8970 13:42:22.861518 10, 0xFFFF, sum = 0
8971 13:42:22.861945 11, 0xFFFF, sum = 0
8972 13:42:22.864395 12, 0xFFFF, sum = 0
8973 13:42:22.864824 13, 0xFFFF, sum = 0
8974 13:42:22.868154 14, 0x0, sum = 1
8975 13:42:22.868622 15, 0x0, sum = 2
8976 13:42:22.871732 16, 0x0, sum = 3
8977 13:42:22.872245 17, 0x0, sum = 4
8978 13:42:22.875030 best_step = 15
8979 13:42:22.875447
8980 13:42:22.875774 ==
8981 13:42:22.877782 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 13:42:22.881312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 13:42:22.881736 ==
8984 13:42:22.884832 RX Vref Scan: 0
8985 13:42:22.885252
8986 13:42:22.885583 RX Vref 0 -> 0, step: 1
8987 13:42:22.885893
8988 13:42:22.888442 RX Delay 19 -> 252, step: 4
8989 13:42:22.891022 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8990 13:42:22.898118 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8991 13:42:22.901171 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8992 13:42:22.904659 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8993 13:42:22.908332 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8994 13:42:22.911100 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8995 13:42:22.914534 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8996 13:42:22.921020 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8997 13:42:22.924330 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8998 13:42:22.928096 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8999 13:42:22.931379 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9000 13:42:22.937881 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9001 13:42:22.941601 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9002 13:42:22.944265 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9003 13:42:22.947860 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9004 13:42:22.951344 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9005 13:42:22.951799 ==
9006 13:42:22.954643 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 13:42:22.960992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 13:42:22.961428 ==
9009 13:42:22.961867 DQS Delay:
9010 13:42:22.964599 DQS0 = 0, DQS1 = 0
9011 13:42:22.965032 DQM Delay:
9012 13:42:22.967613 DQM0 = 134, DQM1 = 130
9013 13:42:22.968042 DQ Delay:
9014 13:42:22.971430 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9015 13:42:22.974256 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9016 13:42:22.978170 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9017 13:42:22.980962 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9018 13:42:22.981391
9019 13:42:22.981827
9020 13:42:22.982237
9021 13:42:22.984536 [DramC_TX_OE_Calibration] TA2
9022 13:42:22.988021 Original DQ_B0 (3 6) =30, OEN = 27
9023 13:42:22.991475 Original DQ_B1 (3 6) =30, OEN = 27
9024 13:42:22.994154 24, 0x0, End_B0=24 End_B1=24
9025 13:42:22.997782 25, 0x0, End_B0=25 End_B1=25
9026 13:42:22.998217 26, 0x0, End_B0=26 End_B1=26
9027 13:42:23.001552 27, 0x0, End_B0=27 End_B1=27
9028 13:42:23.004747 28, 0x0, End_B0=28 End_B1=28
9029 13:42:23.007715 29, 0x0, End_B0=29 End_B1=29
9030 13:42:23.008148 30, 0x0, End_B0=30 End_B1=30
9031 13:42:23.011437 31, 0x4141, End_B0=30 End_B1=30
9032 13:42:23.014393 Byte0 end_step=30 best_step=27
9033 13:42:23.017539 Byte1 end_step=30 best_step=27
9034 13:42:23.021500 Byte0 TX OE(2T, 0.5T) = (3, 3)
9035 13:42:23.024471 Byte1 TX OE(2T, 0.5T) = (3, 3)
9036 13:42:23.024901
9037 13:42:23.025337
9038 13:42:23.030967 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9039 13:42:23.034343 CH1 RK1: MR19=303, MR18=250A
9040 13:42:23.040801 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9041 13:42:23.044645 [RxdqsGatingPostProcess] freq 1600
9042 13:42:23.047893 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9043 13:42:23.051140 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 13:42:23.054367 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 13:42:23.057627 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 13:42:23.060805 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 13:42:23.064139 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 13:42:23.067446 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 13:42:23.071341 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 13:42:23.074052 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 13:42:23.078014 Pre-setting of DQS Precalculation
9052 13:42:23.080803 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9053 13:42:23.087642 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9054 13:42:23.097552 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9055 13:42:23.098154
9056 13:42:23.098637
9057 13:42:23.099049 [Calibration Summary] 3200 Mbps
9058 13:42:23.100822 CH 0, Rank 0
9059 13:42:23.101239 SW Impedance : PASS
9060 13:42:23.104214 DUTY Scan : NO K
9061 13:42:23.107283 ZQ Calibration : PASS
9062 13:42:23.107699 Jitter Meter : NO K
9063 13:42:23.110611 CBT Training : PASS
9064 13:42:23.114234 Write leveling : PASS
9065 13:42:23.114652 RX DQS gating : PASS
9066 13:42:23.117224 RX DQ/DQS(RDDQC) : PASS
9067 13:42:23.120891 TX DQ/DQS : PASS
9068 13:42:23.121307 RX DATLAT : PASS
9069 13:42:23.124698 RX DQ/DQS(Engine): PASS
9070 13:42:23.127718 TX OE : PASS
9071 13:42:23.128230 All Pass.
9072 13:42:23.128588
9073 13:42:23.128898 CH 0, Rank 1
9074 13:42:23.130528 SW Impedance : PASS
9075 13:42:23.134416 DUTY Scan : NO K
9076 13:42:23.134929 ZQ Calibration : PASS
9077 13:42:23.137288 Jitter Meter : NO K
9078 13:42:23.140335 CBT Training : PASS
9079 13:42:23.140783 Write leveling : PASS
9080 13:42:23.144108 RX DQS gating : PASS
9081 13:42:23.147632 RX DQ/DQS(RDDQC) : PASS
9082 13:42:23.148047 TX DQ/DQS : PASS
9083 13:42:23.150313 RX DATLAT : PASS
9084 13:42:23.150741 RX DQ/DQS(Engine): PASS
9085 13:42:23.154092 TX OE : PASS
9086 13:42:23.154629 All Pass.
9087 13:42:23.155079
9088 13:42:23.156792 CH 1, Rank 0
9089 13:42:23.157224 SW Impedance : PASS
9090 13:42:23.160302 DUTY Scan : NO K
9091 13:42:23.163734 ZQ Calibration : PASS
9092 13:42:23.164159 Jitter Meter : NO K
9093 13:42:23.167237 CBT Training : PASS
9094 13:42:23.170411 Write leveling : PASS
9095 13:42:23.170938 RX DQS gating : PASS
9096 13:42:23.173605 RX DQ/DQS(RDDQC) : PASS
9097 13:42:23.177293 TX DQ/DQS : PASS
9098 13:42:23.177724 RX DATLAT : PASS
9099 13:42:23.180450 RX DQ/DQS(Engine): PASS
9100 13:42:23.183525 TX OE : PASS
9101 13:42:23.183959 All Pass.
9102 13:42:23.184429
9103 13:42:23.184897 CH 1, Rank 1
9104 13:42:23.186769 SW Impedance : PASS
9105 13:42:23.190272 DUTY Scan : NO K
9106 13:42:23.190724 ZQ Calibration : PASS
9107 13:42:23.193267 Jitter Meter : NO K
9108 13:42:23.196902 CBT Training : PASS
9109 13:42:23.197318 Write leveling : PASS
9110 13:42:23.199816 RX DQS gating : PASS
9111 13:42:23.203397 RX DQ/DQS(RDDQC) : PASS
9112 13:42:23.203828 TX DQ/DQS : PASS
9113 13:42:23.207072 RX DATLAT : PASS
9114 13:42:23.207450 RX DQ/DQS(Engine): PASS
9115 13:42:23.209775 TX OE : PASS
9116 13:42:23.210105 All Pass.
9117 13:42:23.210371
9118 13:42:23.213100 DramC Write-DBI on
9119 13:42:23.216486 PER_BANK_REFRESH: Hybrid Mode
9120 13:42:23.216718 TX_TRACKING: ON
9121 13:42:23.226358 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9122 13:42:23.233168 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9123 13:42:23.243361 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 13:42:23.246465 [FAST_K] Save calibration result to emmc
9125 13:42:23.246823 sync common calibartion params.
9126 13:42:23.250279 sync cbt_mode0:1, 1:1
9127 13:42:23.254062 dram_init: ddr_geometry: 2
9128 13:42:23.254474 dram_init: ddr_geometry: 2
9129 13:42:23.256803 dram_init: ddr_geometry: 2
9130 13:42:23.260159 0:dram_rank_size:100000000
9131 13:42:23.263598 1:dram_rank_size:100000000
9132 13:42:23.266521 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9133 13:42:23.270013 DFS_SHUFFLE_HW_MODE: ON
9134 13:42:23.273047 dramc_set_vcore_voltage set vcore to 725000
9135 13:42:23.276859 Read voltage for 1600, 0
9136 13:42:23.277290 Vio18 = 0
9137 13:42:23.280541 Vcore = 725000
9138 13:42:23.280969 Vdram = 0
9139 13:42:23.281404 Vddq = 0
9140 13:42:23.281813 Vmddr = 0
9141 13:42:23.283308 switch to 3200 Mbps bootup
9142 13:42:23.286745 [DramcRunTimeConfig]
9143 13:42:23.287177 PHYPLL
9144 13:42:23.287603 DPM_CONTROL_AFTERK: ON
9145 13:42:23.290187 PER_BANK_REFRESH: ON
9146 13:42:23.293541 REFRESH_OVERHEAD_REDUCTION: ON
9147 13:42:23.296526 CMD_PICG_NEW_MODE: OFF
9148 13:42:23.296778 XRTWTW_NEW_MODE: ON
9149 13:42:23.299564 XRTRTR_NEW_MODE: ON
9150 13:42:23.299750 TX_TRACKING: ON
9151 13:42:23.302814 RDSEL_TRACKING: OFF
9152 13:42:23.302999 DQS Precalculation for DVFS: ON
9153 13:42:23.306138 RX_TRACKING: OFF
9154 13:42:23.306321 HW_GATING DBG: ON
9155 13:42:23.309597 ZQCS_ENABLE_LP4: ON
9156 13:42:23.312844 RX_PICG_NEW_MODE: ON
9157 13:42:23.313028 TX_PICG_NEW_MODE: ON
9158 13:42:23.316241 ENABLE_RX_DCM_DPHY: ON
9159 13:42:23.319724 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9160 13:42:23.319910 DUMMY_READ_FOR_TRACKING: OFF
9161 13:42:23.322895 !!! SPM_CONTROL_AFTERK: OFF
9162 13:42:23.326350 !!! SPM could not control APHY
9163 13:42:23.329632 IMPEDANCE_TRACKING: ON
9164 13:42:23.329817 TEMP_SENSOR: ON
9165 13:42:23.333225 HW_SAVE_FOR_SR: OFF
9166 13:42:23.333441 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9167 13:42:23.339584 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9168 13:42:23.339863 Read ODT Tracking: ON
9169 13:42:23.343333 Refresh Rate DeBounce: ON
9170 13:42:23.346422 DFS_NO_QUEUE_FLUSH: ON
9171 13:42:23.350051 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9172 13:42:23.350478 ENABLE_DFS_RUNTIME_MRW: OFF
9173 13:42:23.353023 DDR_RESERVE_NEW_MODE: ON
9174 13:42:23.356818 MR_CBT_SWITCH_FREQ: ON
9175 13:42:23.357248 =========================
9176 13:42:23.375863 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9177 13:42:23.379449 dram_init: ddr_geometry: 2
9178 13:42:23.397788 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9179 13:42:23.400501 dram_init: dram init end (result: 0)
9180 13:42:23.407427 DRAM-K: Full calibration passed in 24464 msecs
9181 13:42:23.410862 MRC: failed to locate region type 0.
9182 13:42:23.411074 DRAM rank0 size:0x100000000,
9183 13:42:23.414200 DRAM rank1 size=0x100000000
9184 13:42:23.423864 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9185 13:42:23.430528 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9186 13:42:23.437165 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9187 13:42:23.443771 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9188 13:42:23.447177 DRAM rank0 size:0x100000000,
9189 13:42:23.450387 DRAM rank1 size=0x100000000
9190 13:42:23.450490 CBMEM:
9191 13:42:23.453550 IMD: root @ 0xfffff000 254 entries.
9192 13:42:23.457337 IMD: root @ 0xffffec00 62 entries.
9193 13:42:23.460243 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9194 13:42:23.464135 WARNING: RO_VPD is uninitialized or empty.
9195 13:42:23.470405 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9196 13:42:23.477758 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9197 13:42:23.490214 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9198 13:42:23.502155 BS: romstage times (exec / console): total (unknown) / 23993 ms
9199 13:42:23.502615
9200 13:42:23.503045
9201 13:42:23.511658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9202 13:42:23.515309 ARM64: Exception handlers installed.
9203 13:42:23.518273 ARM64: Testing exception
9204 13:42:23.521900 ARM64: Done test exception
9205 13:42:23.522332 Enumerating buses...
9206 13:42:23.525262 Show all devs... Before device enumeration.
9207 13:42:23.528535 Root Device: enabled 1
9208 13:42:23.531906 CPU_CLUSTER: 0: enabled 1
9209 13:42:23.532368 CPU: 00: enabled 1
9210 13:42:23.535185 Compare with tree...
9211 13:42:23.535619 Root Device: enabled 1
9212 13:42:23.538619 CPU_CLUSTER: 0: enabled 1
9213 13:42:23.541463 CPU: 00: enabled 1
9214 13:42:23.541893 Root Device scanning...
9215 13:42:23.544889 scan_static_bus for Root Device
9216 13:42:23.548694 CPU_CLUSTER: 0 enabled
9217 13:42:23.552067 scan_static_bus for Root Device done
9218 13:42:23.555012 scan_bus: bus Root Device finished in 8 msecs
9219 13:42:23.555428 done
9220 13:42:23.561993 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9221 13:42:23.564932 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9222 13:42:23.571782 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9223 13:42:23.575130 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9224 13:42:23.578144 Allocating resources...
9225 13:42:23.582062 Reading resources...
9226 13:42:23.584637 Root Device read_resources bus 0 link: 0
9227 13:42:23.585070 DRAM rank0 size:0x100000000,
9228 13:42:23.588669 DRAM rank1 size=0x100000000
9229 13:42:23.591519 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9230 13:42:23.595423 CPU: 00 missing read_resources
9231 13:42:23.598396 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9232 13:42:23.605240 Root Device read_resources bus 0 link: 0 done
9233 13:42:23.605757 Done reading resources.
9234 13:42:23.611671 Show resources in subtree (Root Device)...After reading.
9235 13:42:23.615305 Root Device child on link 0 CPU_CLUSTER: 0
9236 13:42:23.618165 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 13:42:23.628186 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 13:42:23.628695 CPU: 00
9239 13:42:23.631375 Root Device assign_resources, bus 0 link: 0
9240 13:42:23.635219 CPU_CLUSTER: 0 missing set_resources
9241 13:42:23.637953 Root Device assign_resources, bus 0 link: 0 done
9242 13:42:23.641220 Done setting resources.
9243 13:42:23.648643 Show resources in subtree (Root Device)...After assigning values.
9244 13:42:23.651368 Root Device child on link 0 CPU_CLUSTER: 0
9245 13:42:23.654966 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 13:42:23.664951 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 13:42:23.665401 CPU: 00
9248 13:42:23.668449 Done allocating resources.
9249 13:42:23.671284 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9250 13:42:23.674306 Enabling resources...
9251 13:42:23.674733 done.
9252 13:42:23.681503 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9253 13:42:23.682030 Initializing devices...
9254 13:42:23.684329 Root Device init
9255 13:42:23.684801 init hardware done!
9256 13:42:23.687975 0x00000018: ctrlr->caps
9257 13:42:23.691098 52.000 MHz: ctrlr->f_max
9258 13:42:23.691517 0.400 MHz: ctrlr->f_min
9259 13:42:23.694540 0x40ff8080: ctrlr->voltages
9260 13:42:23.694992 sclk: 390625
9261 13:42:23.697787 Bus Width = 1
9262 13:42:23.698214 sclk: 390625
9263 13:42:23.701155 Bus Width = 1
9264 13:42:23.701581 Early init status = 3
9265 13:42:23.707788 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9266 13:42:23.711292 in-header: 03 fc 00 00 01 00 00 00
9267 13:42:23.711706 in-data: 00
9268 13:42:23.717856 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9269 13:42:23.720947 in-header: 03 fd 00 00 00 00 00 00
9270 13:42:23.724538 in-data:
9271 13:42:23.727511 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9272 13:42:23.731310 in-header: 03 fc 00 00 01 00 00 00
9273 13:42:23.734070 in-data: 00
9274 13:42:23.737824 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9275 13:42:23.742118 in-header: 03 fd 00 00 00 00 00 00
9276 13:42:23.745891 in-data:
9277 13:42:23.748539 [SSUSB] Setting up USB HOST controller...
9278 13:42:23.751872 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9279 13:42:23.755856 [SSUSB] phy power-on done.
9280 13:42:23.758536 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9281 13:42:23.764965 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9282 13:42:23.768321 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9283 13:42:23.775277 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9284 13:42:23.781439 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9285 13:42:23.788825 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9286 13:42:23.795242 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9287 13:42:23.801550 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9288 13:42:23.805211 SPM: binary array size = 0x9dc
9289 13:42:23.808608 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9290 13:42:23.814666 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9291 13:42:23.821621 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9292 13:42:23.824829 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9293 13:42:23.831228 configure_display: Starting display init
9294 13:42:23.864864 anx7625_power_on_init: Init interface.
9295 13:42:23.868679 anx7625_disable_pd_protocol: Disabled PD feature.
9296 13:42:23.871717 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9297 13:42:23.899630 anx7625_start_dp_work: Secure OCM version=00
9298 13:42:23.902466 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9299 13:42:23.917606 sp_tx_get_edid_block: EDID Block = 1
9300 13:42:24.020374 Extracted contents:
9301 13:42:24.023684 header: 00 ff ff ff ff ff ff 00
9302 13:42:24.026360 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9303 13:42:24.029836 version: 01 04
9304 13:42:24.033183 basic params: 95 1f 11 78 0a
9305 13:42:24.036546 chroma info: 76 90 94 55 54 90 27 21 50 54
9306 13:42:24.040302 established: 00 00 00
9307 13:42:24.046752 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9308 13:42:24.050220 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9309 13:42:24.056737 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9310 13:42:24.062938 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9311 13:42:24.070207 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9312 13:42:24.072905 extensions: 00
9313 13:42:24.073362 checksum: fb
9314 13:42:24.073695
9315 13:42:24.076780 Manufacturer: IVO Model 57d Serial Number 0
9316 13:42:24.079607 Made week 0 of 2020
9317 13:42:24.083130 EDID version: 1.4
9318 13:42:24.083573 Digital display
9319 13:42:24.086206 6 bits per primary color channel
9320 13:42:24.086646 DisplayPort interface
9321 13:42:24.089838 Maximum image size: 31 cm x 17 cm
9322 13:42:24.092919 Gamma: 220%
9323 13:42:24.093349 Check DPMS levels
9324 13:42:24.096619 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9325 13:42:24.102599 First detailed timing is preferred timing
9326 13:42:24.103109 Established timings supported:
9327 13:42:24.106193 Standard timings supported:
9328 13:42:24.109327 Detailed timings
9329 13:42:24.112831 Hex of detail: 383680a07038204018303c0035ae10000019
9330 13:42:24.116398 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9331 13:42:24.122813 0780 0798 07c8 0820 hborder 0
9332 13:42:24.126109 0438 043b 0447 0458 vborder 0
9333 13:42:24.129520 -hsync -vsync
9334 13:42:24.130100 Did detailed timing
9335 13:42:24.136101 Hex of detail: 000000000000000000000000000000000000
9336 13:42:24.139803 Manufacturer-specified data, tag 0
9337 13:42:24.142872 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9338 13:42:24.145772 ASCII string: InfoVision
9339 13:42:24.149100 Hex of detail: 000000fe00523134304e574635205248200a
9340 13:42:24.152435 ASCII string: R140NWF5 RH
9341 13:42:24.152909 Checksum
9342 13:42:24.155981 Checksum: 0xfb (valid)
9343 13:42:24.159004 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9344 13:42:24.162516 DSI data_rate: 832800000 bps
9345 13:42:24.168836 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9346 13:42:24.172272 anx7625_parse_edid: pixelclock(138800).
9347 13:42:24.175631 hactive(1920), hsync(48), hfp(24), hbp(88)
9348 13:42:24.178953 vactive(1080), vsync(12), vfp(3), vbp(17)
9349 13:42:24.182414 anx7625_dsi_config: config dsi.
9350 13:42:24.189062 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9351 13:42:24.202280 anx7625_dsi_config: success to config DSI
9352 13:42:24.205174 anx7625_dp_start: MIPI phy setup OK.
9353 13:42:24.208923 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9354 13:42:24.211961 mtk_ddp_mode_set invalid vrefresh 60
9355 13:42:24.215630 main_disp_path_setup
9356 13:42:24.216043 ovl_layer_smi_id_en
9357 13:42:24.218500 ovl_layer_smi_id_en
9358 13:42:24.218911 ccorr_config
9359 13:42:24.219242 aal_config
9360 13:42:24.222380 gamma_config
9361 13:42:24.222794 postmask_config
9362 13:42:24.225240 dither_config
9363 13:42:24.228783 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9364 13:42:24.235364 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9365 13:42:24.238630 Root Device init finished in 551 msecs
9366 13:42:24.242109 CPU_CLUSTER: 0 init
9367 13:42:24.249081 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9368 13:42:24.251917 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9369 13:42:24.255977 APU_MBOX 0x190000b0 = 0x10001
9370 13:42:24.259436 APU_MBOX 0x190001b0 = 0x10001
9371 13:42:24.262201 APU_MBOX 0x190005b0 = 0x10001
9372 13:42:24.265506 APU_MBOX 0x190006b0 = 0x10001
9373 13:42:24.268582 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9374 13:42:24.281083 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9375 13:42:24.293602 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9376 13:42:24.300642 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9377 13:42:24.312138 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9378 13:42:24.321324 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9379 13:42:24.324133 CPU_CLUSTER: 0 init finished in 81 msecs
9380 13:42:24.327789 Devices initialized
9381 13:42:24.330795 Show all devs... After init.
9382 13:42:24.331206 Root Device: enabled 1
9383 13:42:24.334255 CPU_CLUSTER: 0: enabled 1
9384 13:42:24.338001 CPU: 00: enabled 1
9385 13:42:24.340917 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9386 13:42:24.344080 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9387 13:42:24.347657 ELOG: NV offset 0x57f000 size 0x1000
9388 13:42:24.355124 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9389 13:42:24.361695 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9390 13:42:24.364297 ELOG: Event(17) added with size 13 at 2024-05-28 13:37:44 UTC
9391 13:42:24.367326 out: cmd=0x121: 03 db 21 01 00 00 00 00
9392 13:42:24.371685 in-header: 03 d8 00 00 2c 00 00 00
9393 13:42:24.384697 in-data: 87 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9394 13:42:24.391548 ELOG: Event(A1) added with size 10 at 2024-05-28 13:37:44 UTC
9395 13:42:24.397843 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9396 13:42:24.404666 ELOG: Event(A0) added with size 9 at 2024-05-28 13:37:44 UTC
9397 13:42:24.407929 elog_add_boot_reason: Logged dev mode boot
9398 13:42:24.411635 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9399 13:42:24.414427 Finalize devices...
9400 13:42:24.414843 Devices finalized
9401 13:42:24.421064 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9402 13:42:24.424507 Writing coreboot table at 0xffe64000
9403 13:42:24.427813 0. 000000000010a000-0000000000113fff: RAMSTAGE
9404 13:42:24.431571 1. 0000000040000000-00000000400fffff: RAM
9405 13:42:24.434431 2. 0000000040100000-000000004032afff: RAMSTAGE
9406 13:42:24.441375 3. 000000004032b000-00000000545fffff: RAM
9407 13:42:24.444330 4. 0000000054600000-000000005465ffff: BL31
9408 13:42:24.447859 5. 0000000054660000-00000000ffe63fff: RAM
9409 13:42:24.451274 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9410 13:42:24.458153 7. 0000000100000000-000000023fffffff: RAM
9411 13:42:24.458572 Passing 5 GPIOs to payload:
9412 13:42:24.464565 NAME | PORT | POLARITY | VALUE
9413 13:42:24.467468 EC in RW | 0x000000aa | low | undefined
9414 13:42:24.474501 EC interrupt | 0x00000005 | low | undefined
9415 13:42:24.477442 TPM interrupt | 0x000000ab | high | undefined
9416 13:42:24.481161 SD card detect | 0x00000011 | high | undefined
9417 13:42:24.487912 speaker enable | 0x00000093 | high | undefined
9418 13:42:24.490876 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9419 13:42:24.494182 in-header: 03 f9 00 00 02 00 00 00
9420 13:42:24.494614 in-data: 02 00
9421 13:42:24.497463 ADC[4]: Raw value=904357 ID=7
9422 13:42:24.501061 ADC[3]: Raw value=213441 ID=1
9423 13:42:24.501480 RAM Code: 0x71
9424 13:42:24.504449 ADC[6]: Raw value=75701 ID=0
9425 13:42:24.507843 ADC[5]: Raw value=212703 ID=1
9426 13:42:24.508261 SKU Code: 0x1
9427 13:42:24.514108 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cba
9428 13:42:24.517847 coreboot table: 964 bytes.
9429 13:42:24.520896 IMD ROOT 0. 0xfffff000 0x00001000
9430 13:42:24.524517 IMD SMALL 1. 0xffffe000 0x00001000
9431 13:42:24.528076 RO MCACHE 2. 0xffffc000 0x00001104
9432 13:42:24.530863 CONSOLE 3. 0xfff7c000 0x00080000
9433 13:42:24.534180 FMAP 4. 0xfff7b000 0x00000452
9434 13:42:24.537459 TIME STAMP 5. 0xfff7a000 0x00000910
9435 13:42:24.540834 VBOOT WORK 6. 0xfff66000 0x00014000
9436 13:42:24.544618 RAMOOPS 7. 0xffe66000 0x00100000
9437 13:42:24.547907 COREBOOT 8. 0xffe64000 0x00002000
9438 13:42:24.548409 IMD small region:
9439 13:42:24.551210 IMD ROOT 0. 0xffffec00 0x00000400
9440 13:42:24.554097 VPD 1. 0xffffeb80 0x0000006c
9441 13:42:24.557800 MMC STATUS 2. 0xffffeb60 0x00000004
9442 13:42:24.564736 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9443 13:42:24.565158 Probing TPM: done!
9444 13:42:24.571219 Connected to device vid:did:rid of 1ae0:0028:00
9445 13:42:24.577806 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9446 13:42:24.581547 Initialized TPM device CR50 revision 0
9447 13:42:24.585046 Checking cr50 for pending updates
9448 13:42:24.590536 Reading cr50 TPM mode
9449 13:42:24.599523 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9450 13:42:24.605898 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9451 13:42:24.646163 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9452 13:42:24.649696 Checking segment from ROM address 0x40100000
9453 13:42:24.652593 Checking segment from ROM address 0x4010001c
9454 13:42:24.659325 Loading segment from ROM address 0x40100000
9455 13:42:24.659772 code (compression=0)
9456 13:42:24.669840 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9457 13:42:24.675974 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9458 13:42:24.676444 it's not compressed!
9459 13:42:24.683113 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9460 13:42:24.686058 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9461 13:42:24.706570 Loading segment from ROM address 0x4010001c
9462 13:42:24.707067 Entry Point 0x80000000
9463 13:42:24.709661 Loaded segments
9464 13:42:24.713032 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9465 13:42:24.720045 Jumping to boot code at 0x80000000(0xffe64000)
9466 13:42:24.726646 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9467 13:42:24.732913 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9468 13:42:24.742299 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9469 13:42:24.744438 Checking segment from ROM address 0x40100000
9470 13:42:24.747387 Checking segment from ROM address 0x4010001c
9471 13:42:24.753879 Loading segment from ROM address 0x40100000
9472 13:42:24.754300 code (compression=1)
9473 13:42:24.760713 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9474 13:42:24.770794 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9475 13:42:24.771270 using LZMA
9476 13:42:24.779381 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9477 13:42:24.785693 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9478 13:42:24.789779 Loading segment from ROM address 0x4010001c
9479 13:42:24.789963 Entry Point 0x54601000
9480 13:42:24.792524 Loaded segments
9481 13:42:24.795795 NOTICE: MT8192 bl31_setup
9482 13:42:24.802715 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9483 13:42:24.805549 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9484 13:42:24.809149 WARNING: region 0:
9485 13:42:24.812992 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 13:42:24.813099 WARNING: region 1:
9487 13:42:24.819417 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9488 13:42:24.822488 WARNING: region 2:
9489 13:42:24.825728 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9490 13:42:24.828987 WARNING: region 3:
9491 13:42:24.832664 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9492 13:42:24.836246 WARNING: region 4:
9493 13:42:24.842514 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 13:42:24.842600 WARNING: region 5:
9495 13:42:24.846030 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 13:42:24.849596 WARNING: region 6:
9497 13:42:24.852437 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 13:42:24.852525 WARNING: region 7:
9499 13:42:24.859018 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 13:42:24.866179 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9501 13:42:24.869299 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9502 13:42:24.872753 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9503 13:42:24.879432 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9504 13:42:24.882939 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9505 13:42:24.885865 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9506 13:42:24.892359 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9507 13:42:24.895813 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9508 13:42:24.902502 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9509 13:42:24.905671 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9510 13:42:24.909094 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9511 13:42:24.915952 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9512 13:42:24.919562 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9513 13:42:24.922528 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9514 13:42:24.929772 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9515 13:42:24.932621 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9516 13:42:24.936096 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9517 13:42:24.942879 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9518 13:42:24.946563 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9519 13:42:24.949668 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9520 13:42:24.956163 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9521 13:42:24.959078 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9522 13:42:24.966387 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9523 13:42:24.969424 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9524 13:42:24.975842 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9525 13:42:24.979749 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9526 13:42:24.982792 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9527 13:42:24.989688 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9528 13:42:24.993503 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9529 13:42:24.996361 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9530 13:42:25.003323 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9531 13:42:25.006724 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9532 13:42:25.009563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9533 13:42:25.015998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9534 13:42:25.019905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9535 13:42:25.022621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9536 13:42:25.026217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9537 13:42:25.032710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9538 13:42:25.036371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9539 13:42:25.040046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9540 13:42:25.042818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9541 13:42:25.049636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9542 13:42:25.053119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9543 13:42:25.056566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9544 13:42:25.059983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9545 13:42:25.066600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9546 13:42:25.069400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9547 13:42:25.073188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9548 13:42:25.080018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9549 13:42:25.082794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9550 13:42:25.086500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9551 13:42:25.093058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9552 13:42:25.096677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9553 13:42:25.103396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9554 13:42:25.106367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9555 13:42:25.112833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9556 13:42:25.116184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9557 13:42:25.119897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9558 13:42:25.126300 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9559 13:42:25.130119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9560 13:42:25.136591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9561 13:42:25.140129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9562 13:42:25.146669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9563 13:42:25.150348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9564 13:42:25.153232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9565 13:42:25.160264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9566 13:42:25.163975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9567 13:42:25.170263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9568 13:42:25.173680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9569 13:42:25.177026 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9570 13:42:25.183417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9571 13:42:25.187113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9572 13:42:25.193594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9573 13:42:25.197105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9574 13:42:25.203709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9575 13:42:25.206683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9576 13:42:25.210324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9577 13:42:25.216824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9578 13:42:25.220307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9579 13:42:25.226938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9580 13:42:25.230662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9581 13:42:25.237232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9582 13:42:25.240131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9583 13:42:25.246846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9584 13:42:25.250138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9585 13:42:25.253317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9586 13:42:25.260057 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9587 13:42:25.263653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9588 13:42:25.270055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9589 13:42:25.273697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9590 13:42:25.276687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9591 13:42:25.283580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9592 13:42:25.287034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9593 13:42:25.293428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9594 13:42:25.296834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9595 13:42:25.303550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9596 13:42:25.307138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9597 13:42:25.310186 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9598 13:42:25.313825 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9599 13:42:25.320332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9600 13:42:25.323948 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9601 13:42:25.326783 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9602 13:42:25.333573 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9603 13:42:25.337213 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9604 13:42:25.343958 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9605 13:42:25.347574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9606 13:42:25.350505 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9607 13:42:25.357415 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9608 13:42:25.360273 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9609 13:42:25.363582 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9610 13:42:25.370419 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9611 13:42:25.373706 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9612 13:42:25.380387 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9613 13:42:25.383716 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9614 13:42:25.387296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9615 13:42:25.393575 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9616 13:42:25.397131 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9617 13:42:25.400768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9618 13:42:25.407124 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9619 13:42:25.410656 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9620 13:42:25.414204 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9621 13:42:25.417112 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9622 13:42:25.423744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9623 13:42:25.427469 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9624 13:42:25.430315 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9625 13:42:25.437480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9626 13:42:25.440544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9627 13:42:25.443516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9628 13:42:25.450214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9629 13:42:25.453807 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9630 13:42:25.460282 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9631 13:42:25.464058 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9632 13:42:25.466966 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9633 13:42:25.473986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9634 13:42:25.476781 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9635 13:42:25.484001 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9636 13:42:25.487484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9637 13:42:25.490848 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9638 13:42:25.497414 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9639 13:42:25.500846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9640 13:42:25.504268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9641 13:42:25.510513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9642 13:42:25.513955 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9643 13:42:25.520229 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9644 13:42:25.523893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9645 13:42:25.527370 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9646 13:42:25.534154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9647 13:42:25.537669 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9648 13:42:25.540442 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9649 13:42:25.547778 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9650 13:42:25.550700 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9651 13:42:25.557269 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9652 13:42:25.560798 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9653 13:42:25.564439 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9654 13:42:25.571163 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9655 13:42:25.574708 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9656 13:42:25.577498 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9657 13:42:25.584599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9658 13:42:25.587439 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9659 13:42:25.594004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9660 13:42:25.597622 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9661 13:42:25.601153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9662 13:42:25.607301 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9663 13:42:25.610897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9664 13:42:25.617697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9665 13:42:25.620586 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9666 13:42:25.624252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9667 13:42:25.630510 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9668 13:42:25.634099 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9669 13:42:25.640506 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9670 13:42:25.644228 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9671 13:42:25.647708 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9672 13:42:25.654491 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9673 13:42:25.657338 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9674 13:42:25.664613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9675 13:42:25.667564 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9676 13:42:25.671125 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9677 13:42:25.677695 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9678 13:42:25.681260 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9679 13:42:25.684256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9680 13:42:25.691217 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9681 13:42:25.694734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9682 13:42:25.701215 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9683 13:42:25.704864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9684 13:42:25.707584 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9685 13:42:25.714540 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9686 13:42:25.717528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9687 13:42:25.724615 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9688 13:42:25.727481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9689 13:42:25.730708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9690 13:42:25.738030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9691 13:42:25.740802 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9692 13:42:25.747658 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9693 13:42:25.750974 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9694 13:42:25.753879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9695 13:42:25.760458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9696 13:42:25.763981 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9697 13:42:25.770594 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9698 13:42:25.774326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9699 13:42:25.780791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9700 13:42:25.783555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9701 13:42:25.787482 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9702 13:42:25.794133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9703 13:42:25.797798 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9704 13:42:25.803886 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9705 13:42:25.807319 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9706 13:42:25.813872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9707 13:42:25.817491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9708 13:42:25.820447 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9709 13:42:25.827001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9710 13:42:25.830430 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9711 13:42:25.836877 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9712 13:42:25.840195 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9713 13:42:25.843714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9714 13:42:25.850203 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9715 13:42:25.853621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9716 13:42:25.859771 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9717 13:42:25.863219 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9718 13:42:25.866550 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9719 13:42:25.873073 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9720 13:42:25.876551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9721 13:42:25.883077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9722 13:42:25.886580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9723 13:42:25.893142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9724 13:42:25.896774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9725 13:42:25.899758 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9726 13:42:25.906528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9727 13:42:25.909814 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9728 13:42:25.916438 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9729 13:42:25.920017 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9730 13:42:25.923085 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9731 13:42:25.926595 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9732 13:42:25.929525 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9733 13:42:25.936574 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9734 13:42:25.940245 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9735 13:42:25.943173 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9736 13:42:25.949596 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9737 13:42:25.952867 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9738 13:42:25.956494 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9739 13:42:25.962877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9740 13:42:25.966508 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9741 13:42:25.972848 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9742 13:42:25.976246 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9743 13:42:25.979488 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9744 13:42:25.986024 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9745 13:42:25.989566 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9746 13:42:25.996194 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9747 13:42:25.999093 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9748 13:42:26.002877 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9749 13:42:26.009483 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9750 13:42:26.012300 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9751 13:42:26.015969 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9752 13:42:26.022780 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9753 13:42:26.026090 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9754 13:42:26.029633 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9755 13:42:26.036129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9756 13:42:26.039146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9757 13:42:26.046145 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9758 13:42:26.049158 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9759 13:42:26.052744 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9760 13:42:26.058951 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9761 13:42:26.062266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9762 13:42:26.065722 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9763 13:42:26.072113 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9764 13:42:26.075782 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9765 13:42:26.079318 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9766 13:42:26.085504 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9767 13:42:26.089019 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9768 13:42:26.092370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9769 13:42:26.099157 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9770 13:42:26.102600 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9771 13:42:26.105501 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9772 13:42:26.109216 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9773 13:42:26.112183 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9774 13:42:26.118767 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9775 13:42:26.122605 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9776 13:42:26.125563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9777 13:42:26.132615 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9778 13:42:26.135358 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9779 13:42:26.138686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9780 13:42:26.142166 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9781 13:42:26.148815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9782 13:42:26.152433 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9783 13:42:26.159121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9784 13:42:26.162184 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9785 13:42:26.165835 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9786 13:42:26.172178 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9787 13:42:26.175791 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9788 13:42:26.182323 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9789 13:42:26.185442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9790 13:42:26.189020 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9791 13:42:26.195448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9792 13:42:26.199121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9793 13:42:26.205304 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9794 13:42:26.208805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9795 13:42:26.211880 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9796 13:42:26.218809 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9797 13:42:26.221708 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9798 13:42:26.229128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9799 13:42:26.232189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9800 13:42:26.235482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9801 13:42:26.242092 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9802 13:42:26.245780 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9803 13:42:26.252106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9804 13:42:26.255517 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9805 13:42:26.259004 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9806 13:42:26.265445 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9807 13:42:26.268952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9808 13:42:26.275796 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9809 13:42:26.278840 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9810 13:42:26.285740 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9811 13:42:26.289179 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9812 13:42:26.291902 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9813 13:42:26.298776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9814 13:42:26.302210 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9815 13:42:26.308748 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9816 13:42:26.311692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9817 13:42:26.315505 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9818 13:42:26.321471 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9819 13:42:26.324668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9820 13:42:26.331430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9821 13:42:26.335233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9822 13:42:26.338112 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9823 13:42:26.344817 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9824 13:42:26.347965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9825 13:42:26.354695 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9826 13:42:26.358550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9827 13:42:26.365048 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9828 13:42:26.367673 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9829 13:42:26.371390 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9830 13:42:26.377846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9831 13:42:26.381286 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9832 13:42:26.387636 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9833 13:42:26.391202 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9834 13:42:26.394748 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9835 13:42:26.401175 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9836 13:42:26.404764 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9837 13:42:26.407632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9838 13:42:26.414469 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9839 13:42:26.418147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9840 13:42:26.424857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9841 13:42:26.427754 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9842 13:42:26.434143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9843 13:42:26.437730 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9844 13:42:26.441096 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9845 13:42:26.447618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9846 13:42:26.451331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9847 13:42:26.457779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9848 13:42:26.460837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9849 13:42:26.464700 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9850 13:42:26.471369 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9851 13:42:26.474284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9852 13:42:26.480926 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9853 13:42:26.484517 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9854 13:42:26.487522 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9855 13:42:26.494641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9856 13:42:26.497264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9857 13:42:26.504169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9858 13:42:26.507311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9859 13:42:26.514202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9860 13:42:26.517397 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9861 13:42:26.520921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9862 13:42:26.527517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9863 13:42:26.530548 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9864 13:42:26.537746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9865 13:42:26.540790 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9866 13:42:26.547432 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9867 13:42:26.550853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9868 13:42:26.557463 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9869 13:42:26.561166 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9870 13:42:26.564074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9871 13:42:26.570816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9872 13:42:26.573729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9873 13:42:26.580987 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9874 13:42:26.584515 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9875 13:42:26.591106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9876 13:42:26.594140 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9877 13:42:26.597661 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9878 13:42:26.604375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9879 13:42:26.607274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9880 13:42:26.614351 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9881 13:42:26.617109 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9882 13:42:26.623983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9883 13:42:26.627230 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9884 13:42:26.633580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9885 13:42:26.637247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9886 13:42:26.640939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9887 13:42:26.647506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9888 13:42:26.650792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9889 13:42:26.657478 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9890 13:42:26.660835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9891 13:42:26.667026 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9892 13:42:26.670540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9893 13:42:26.673561 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9894 13:42:26.680357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9895 13:42:26.684105 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9896 13:42:26.690547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9897 13:42:26.693631 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9898 13:42:26.700275 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9899 13:42:26.703809 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9900 13:42:26.707450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9901 13:42:26.713636 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9902 13:42:26.717571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9903 13:42:26.720600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9904 13:42:26.727697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9905 13:42:26.730507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9906 13:42:26.737254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9907 13:42:26.740610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9908 13:42:26.747504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9909 13:42:26.750864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9910 13:42:26.757397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9911 13:42:26.760968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9912 13:42:26.767672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9913 13:42:26.770593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9914 13:42:26.777520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9915 13:42:26.780903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9916 13:42:26.787083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9917 13:42:26.790730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9918 13:42:26.797297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9919 13:42:26.801081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9920 13:42:26.807399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9921 13:42:26.810270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9922 13:42:26.817357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9923 13:42:26.820314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9924 13:42:26.827422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9925 13:42:26.830343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9926 13:42:26.836951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9927 13:42:26.840516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9928 13:42:26.846851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9929 13:42:26.850296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9930 13:42:26.856879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9931 13:42:26.860298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9932 13:42:26.867132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9933 13:42:26.870499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9934 13:42:26.873759 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9935 13:42:26.877105 INFO: [APUAPC] vio 0
9936 13:42:26.883770 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9937 13:42:26.887177 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9938 13:42:26.889973 INFO: [APUAPC] D0_APC_0: 0x400510
9939 13:42:26.893428 INFO: [APUAPC] D0_APC_1: 0x0
9940 13:42:26.896833 INFO: [APUAPC] D0_APC_2: 0x1540
9941 13:42:26.900084 INFO: [APUAPC] D0_APC_3: 0x0
9942 13:42:26.902979 INFO: [APUAPC] D1_APC_0: 0xffffffff
9943 13:42:26.906774 INFO: [APUAPC] D1_APC_1: 0xffffffff
9944 13:42:26.910394 INFO: [APUAPC] D1_APC_2: 0x3fffff
9945 13:42:26.910818 INFO: [APUAPC] D1_APC_3: 0x0
9946 13:42:26.917002 INFO: [APUAPC] D2_APC_0: 0xffffffff
9947 13:42:26.919942 INFO: [APUAPC] D2_APC_1: 0xffffffff
9948 13:42:26.923444 INFO: [APUAPC] D2_APC_2: 0x3fffff
9949 13:42:26.923923 INFO: [APUAPC] D2_APC_3: 0x0
9950 13:42:26.926944 INFO: [APUAPC] D3_APC_0: 0xffffffff
9951 13:42:26.929663 INFO: [APUAPC] D3_APC_1: 0xffffffff
9952 13:42:26.936178 INFO: [APUAPC] D3_APC_2: 0x3fffff
9953 13:42:26.936653 INFO: [APUAPC] D3_APC_3: 0x0
9954 13:42:26.939781 INFO: [APUAPC] D4_APC_0: 0xffffffff
9955 13:42:26.943092 INFO: [APUAPC] D4_APC_1: 0xffffffff
9956 13:42:26.945985 INFO: [APUAPC] D4_APC_2: 0x3fffff
9957 13:42:26.949581 INFO: [APUAPC] D4_APC_3: 0x0
9958 13:42:26.953055 INFO: [APUAPC] D5_APC_0: 0xffffffff
9959 13:42:26.955894 INFO: [APUAPC] D5_APC_1: 0xffffffff
9960 13:42:26.959411 INFO: [APUAPC] D5_APC_2: 0x3fffff
9961 13:42:26.962354 INFO: [APUAPC] D5_APC_3: 0x0
9962 13:42:26.966034 INFO: [APUAPC] D6_APC_0: 0xffffffff
9963 13:42:26.968938 INFO: [APUAPC] D6_APC_1: 0xffffffff
9964 13:42:26.972298 INFO: [APUAPC] D6_APC_2: 0x3fffff
9965 13:42:26.975676 INFO: [APUAPC] D6_APC_3: 0x0
9966 13:42:26.979058 INFO: [APUAPC] D7_APC_0: 0xffffffff
9967 13:42:26.982561 INFO: [APUAPC] D7_APC_1: 0xffffffff
9968 13:42:26.986088 INFO: [APUAPC] D7_APC_2: 0x3fffff
9969 13:42:26.988842 INFO: [APUAPC] D7_APC_3: 0x0
9970 13:42:26.992250 INFO: [APUAPC] D8_APC_0: 0xffffffff
9971 13:42:26.995858 INFO: [APUAPC] D8_APC_1: 0xffffffff
9972 13:42:26.999246 INFO: [APUAPC] D8_APC_2: 0x3fffff
9973 13:42:27.002075 INFO: [APUAPC] D8_APC_3: 0x0
9974 13:42:27.005564 INFO: [APUAPC] D9_APC_0: 0xffffffff
9975 13:42:27.009078 INFO: [APUAPC] D9_APC_1: 0xffffffff
9976 13:42:27.012503 INFO: [APUAPC] D9_APC_2: 0x3fffff
9977 13:42:27.015751 INFO: [APUAPC] D9_APC_3: 0x0
9978 13:42:27.018627 INFO: [APUAPC] D10_APC_0: 0xffffffff
9979 13:42:27.022408 INFO: [APUAPC] D10_APC_1: 0xffffffff
9980 13:42:27.025371 INFO: [APUAPC] D10_APC_2: 0x3fffff
9981 13:42:27.028925 INFO: [APUAPC] D10_APC_3: 0x0
9982 13:42:27.032481 INFO: [APUAPC] D11_APC_0: 0xffffffff
9983 13:42:27.035288 INFO: [APUAPC] D11_APC_1: 0xffffffff
9984 13:42:27.038989 INFO: [APUAPC] D11_APC_2: 0x3fffff
9985 13:42:27.041879 INFO: [APUAPC] D11_APC_3: 0x0
9986 13:42:27.045411 INFO: [APUAPC] D12_APC_0: 0xffffffff
9987 13:42:27.048966 INFO: [APUAPC] D12_APC_1: 0xffffffff
9988 13:42:27.051806 INFO: [APUAPC] D12_APC_2: 0x3fffff
9989 13:42:27.055316 INFO: [APUAPC] D12_APC_3: 0x0
9990 13:42:27.058914 INFO: [APUAPC] D13_APC_0: 0xffffffff
9991 13:42:27.061953 INFO: [APUAPC] D13_APC_1: 0xffffffff
9992 13:42:27.065554 INFO: [APUAPC] D13_APC_2: 0x3fffff
9993 13:42:27.068428 INFO: [APUAPC] D13_APC_3: 0x0
9994 13:42:27.072121 INFO: [APUAPC] D14_APC_0: 0xffffffff
9995 13:42:27.075024 INFO: [APUAPC] D14_APC_1: 0xffffffff
9996 13:42:27.078701 INFO: [APUAPC] D14_APC_2: 0x3fffff
9997 13:42:27.081626 INFO: [APUAPC] D14_APC_3: 0x0
9998 13:42:27.085039 INFO: [APUAPC] D15_APC_0: 0xffffffff
9999 13:42:27.088632 INFO: [APUAPC] D15_APC_1: 0xffffffff
10000 13:42:27.092143 INFO: [APUAPC] D15_APC_2: 0x3fffff
10001 13:42:27.095201 INFO: [APUAPC] D15_APC_3: 0x0
10002 13:42:27.098886 INFO: [APUAPC] APC_CON: 0x4
10003 13:42:27.101652 INFO: [NOCDAPC] D0_APC_0: 0x0
10004 13:42:27.105118 INFO: [NOCDAPC] D0_APC_1: 0x0
10005 13:42:27.108345 INFO: [NOCDAPC] D1_APC_0: 0x0
10006 13:42:27.111692 INFO: [NOCDAPC] D1_APC_1: 0xfff
10007 13:42:27.111779 INFO: [NOCDAPC] D2_APC_0: 0x0
10008 13:42:27.115174 INFO: [NOCDAPC] D2_APC_1: 0xfff
10009 13:42:27.118632 INFO: [NOCDAPC] D3_APC_0: 0x0
10010 13:42:27.122092 INFO: [NOCDAPC] D3_APC_1: 0xfff
10011 13:42:27.124792 INFO: [NOCDAPC] D4_APC_0: 0x0
10012 13:42:27.128117 INFO: [NOCDAPC] D4_APC_1: 0xfff
10013 13:42:27.131578 INFO: [NOCDAPC] D5_APC_0: 0x0
10014 13:42:27.135260 INFO: [NOCDAPC] D5_APC_1: 0xfff
10015 13:42:27.138066 INFO: [NOCDAPC] D6_APC_0: 0x0
10016 13:42:27.141444 INFO: [NOCDAPC] D6_APC_1: 0xfff
10017 13:42:27.141535 INFO: [NOCDAPC] D7_APC_0: 0x0
10018 13:42:27.145120 INFO: [NOCDAPC] D7_APC_1: 0xfff
10019 13:42:27.148602 INFO: [NOCDAPC] D8_APC_0: 0x0
10020 13:42:27.151411 INFO: [NOCDAPC] D8_APC_1: 0xfff
10021 13:42:27.155046 INFO: [NOCDAPC] D9_APC_0: 0x0
10022 13:42:27.157894 INFO: [NOCDAPC] D9_APC_1: 0xfff
10023 13:42:27.161564 INFO: [NOCDAPC] D10_APC_0: 0x0
10024 13:42:27.165167 INFO: [NOCDAPC] D10_APC_1: 0xfff
10025 13:42:27.168104 INFO: [NOCDAPC] D11_APC_0: 0x0
10026 13:42:27.171872 INFO: [NOCDAPC] D11_APC_1: 0xfff
10027 13:42:27.174706 INFO: [NOCDAPC] D12_APC_0: 0x0
10028 13:42:27.178387 INFO: [NOCDAPC] D12_APC_1: 0xfff
10029 13:42:27.182030 INFO: [NOCDAPC] D13_APC_0: 0x0
10030 13:42:27.182114 INFO: [NOCDAPC] D13_APC_1: 0xfff
10031 13:42:27.185119 INFO: [NOCDAPC] D14_APC_0: 0x0
10032 13:42:27.188137 INFO: [NOCDAPC] D14_APC_1: 0xfff
10033 13:42:27.191603 INFO: [NOCDAPC] D15_APC_0: 0x0
10034 13:42:27.195049 INFO: [NOCDAPC] D15_APC_1: 0xfff
10035 13:42:27.198479 INFO: [NOCDAPC] APC_CON: 0x4
10036 13:42:27.201261 INFO: [APUAPC] set_apusys_apc done
10037 13:42:27.204857 INFO: [DEVAPC] devapc_init done
10038 13:42:27.208618 INFO: GICv3 without legacy support detected.
10039 13:42:27.211475 INFO: ARM GICv3 driver initialized in EL3
10040 13:42:27.218039 INFO: Maximum SPI INTID supported: 639
10041 13:42:27.221552 INFO: BL31: Initializing runtime services
10042 13:42:27.228687 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10043 13:42:27.228831 INFO: SPM: enable CPC mode
10044 13:42:27.235247 INFO: mcdi ready for mcusys-off-idle and system suspend
10045 13:42:27.238411 INFO: BL31: Preparing for EL3 exit to normal world
10046 13:42:27.241913 INFO: Entry point address = 0x80000000
10047 13:42:27.244591 INFO: SPSR = 0x8
10048 13:42:27.250786
10049 13:42:27.250970
10050 13:42:27.251130
10051 13:42:27.254200 Starting depthcharge on Spherion...
10052 13:42:27.254333
10053 13:42:27.254430 Wipe memory regions:
10054 13:42:27.254520
10055 13:42:27.255368 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10056 13:42:27.255514 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10057 13:42:27.255638 Setting prompt string to ['asurada:']
10058 13:42:27.255757 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10059 13:42:27.256921 [0x00000040000000, 0x00000054600000)
10060 13:42:27.380506
10061 13:42:27.381025 [0x00000054660000, 0x00000080000000)
10062 13:42:27.640851
10063 13:42:27.641446 [0x000000821a7280, 0x000000ffe64000)
10064 13:42:28.384916
10065 13:42:28.385064 [0x00000100000000, 0x00000240000000)
10066 13:42:30.275741
10067 13:42:30.278420 Initializing XHCI USB controller at 0x11200000.
10068 13:42:31.317696
10069 13:42:31.321090 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10070 13:42:31.321179
10071 13:42:31.321245
10072 13:42:31.321530 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 13:42:31.421880 asurada: tftpboot 192.168.201.1 14063033/tftp-deploy-qws1jlf3/kernel/image.itb 14063033/tftp-deploy-qws1jlf3/kernel/cmdline
10075 13:42:31.422339 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 13:42:31.422450 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10077 13:42:31.427206 tftpboot 192.168.201.1 14063033/tftp-deploy-qws1jlf3/kernel/image.ittp-deploy-qws1jlf3/kernel/cmdline
10078 13:42:31.427290
10079 13:42:31.427354 Waiting for link
10080 13:42:31.587443
10081 13:42:31.587600 R8152: Initializing
10082 13:42:31.587668
10083 13:42:31.590928 Version 9 (ocp_data = 6010)
10084 13:42:31.591010
10085 13:42:31.594434 R8152: Done initializing
10086 13:42:31.594515
10087 13:42:31.594629 Adding net device
10088 13:42:33.465664
10089 13:42:33.465794 done.
10090 13:42:33.465873
10091 13:42:33.465936 MAC: 00:e0:4c:78:7a:aa
10092 13:42:33.465995
10093 13:42:33.469207 Sending DHCP discover... done.
10094 13:42:33.469298
10095 13:42:33.472108 Waiting for reply... done.
10096 13:42:33.472227
10097 13:42:33.475851 Sending DHCP request... done.
10098 13:42:33.475934
10099 13:42:33.475999 Waiting for reply... done.
10100 13:42:33.476060
10101 13:42:33.478750 My ip is 192.168.201.12
10102 13:42:33.478832
10103 13:42:33.482237 The DHCP server ip is 192.168.201.1
10104 13:42:33.482327
10105 13:42:33.485592 TFTP server IP predefined by user: 192.168.201.1
10106 13:42:33.485675
10107 13:42:33.492686 Bootfile predefined by user: 14063033/tftp-deploy-qws1jlf3/kernel/image.itb
10108 13:42:33.492785
10109 13:42:33.495579 Sending tftp read request... done.
10110 13:42:33.495661
10111 13:42:33.499207 Waiting for the transfer...
10112 13:42:33.499291
10113 13:42:33.767770 00000000 ################################################################
10114 13:42:33.767929
10115 13:42:34.063283 00080000 ################################################################
10116 13:42:34.063457
10117 13:42:34.408590 00100000 ################################################################
10118 13:42:34.408727
10119 13:42:34.743128 00180000 ################################################################
10120 13:42:34.743263
10121 13:42:35.067976 00200000 ################################################################
10122 13:42:35.068116
10123 13:42:35.393152 00280000 ################################################################
10124 13:42:35.393292
10125 13:42:35.743664 00300000 ################################################################
10126 13:42:35.743843
10127 13:42:36.033503 00380000 ################################################################
10128 13:42:36.033640
10129 13:42:36.306951 00400000 ################################################################
10130 13:42:36.307085
10131 13:42:36.595460 00480000 ################################################################
10132 13:42:36.595599
10133 13:42:36.860081 00500000 ################################################################
10134 13:42:36.860252
10135 13:42:37.116380 00580000 ################################################################
10136 13:42:37.116572
10137 13:42:37.369858 00600000 ################################################################
10138 13:42:37.370029
10139 13:42:37.630217 00680000 ################################################################
10140 13:42:37.630356
10141 13:42:37.896737 00700000 ################################################################
10142 13:42:37.896905
10143 13:42:38.155216 00780000 ################################################################
10144 13:42:38.155349
10145 13:42:38.410644 00800000 ################################################################
10146 13:42:38.410776
10147 13:42:38.677033 00880000 ################################################################
10148 13:42:38.677209
10149 13:42:38.954733 00900000 ################################################################
10150 13:42:38.954878
10151 13:42:39.217061 00980000 ################################################################
10152 13:42:39.217199
10153 13:42:39.475359 00a00000 ################################################################
10154 13:42:39.475525
10155 13:42:39.740952 00a80000 ################################################################
10156 13:42:39.741136
10157 13:42:40.001982 00b00000 ################################################################
10158 13:42:40.002126
10159 13:42:40.270515 00b80000 ################################################################
10160 13:42:40.270661
10161 13:42:40.557043 00c00000 ################################################################
10162 13:42:40.557193
10163 13:42:40.840436 00c80000 ################################################################
10164 13:42:40.840620
10165 13:42:41.127567 00d00000 ################################################################
10166 13:42:41.127743
10167 13:42:41.414427 00d80000 ################################################################
10168 13:42:41.414608
10169 13:42:41.701944 00e00000 ################################################################
10170 13:42:41.702114
10171 13:42:41.978250 00e80000 ################################################################
10172 13:42:41.978438
10173 13:42:42.238021 00f00000 ################################################################
10174 13:42:42.238162
10175 13:42:42.529335 00f80000 ################################################################
10176 13:42:42.529491
10177 13:42:42.799166 01000000 ################################################################
10178 13:42:42.799309
10179 13:42:43.087221 01080000 ################################################################
10180 13:42:43.087366
10181 13:42:43.350232 01100000 ################################################################
10182 13:42:43.350378
10183 13:42:43.613320 01180000 ################################################################
10184 13:42:43.613452
10185 13:42:43.870513 01200000 ################################################################
10186 13:42:43.870652
10187 13:42:44.156761 01280000 ################################################################
10188 13:42:44.156896
10189 13:42:44.412752 01300000 ################################################################
10190 13:42:44.412882
10191 13:42:44.669242 01380000 ################################################################
10192 13:42:44.669374
10193 13:42:44.922961 01400000 ################################################################
10194 13:42:44.923095
10195 13:42:45.176249 01480000 ################################################################
10196 13:42:45.176440
10197 13:42:45.446279 01500000 ################################################################
10198 13:42:45.446425
10199 13:42:45.744625 01580000 ################################################################
10200 13:42:45.744769
10201 13:42:46.022235 01600000 ################################################################
10202 13:42:46.022380
10203 13:42:46.282153 01680000 ################################################################
10204 13:42:46.282295
10205 13:42:46.537997 01700000 ################################################################
10206 13:42:46.538132
10207 13:42:46.812170 01780000 ################################################################
10208 13:42:46.812334
10209 13:42:47.073337 01800000 ################################################################
10210 13:42:47.073469
10211 13:42:47.350101 01880000 ################################################################
10212 13:42:47.350228
10213 13:42:47.641972 01900000 ################################################################
10214 13:42:47.642120
10215 13:42:47.900937 01980000 ################################################################
10216 13:42:47.901081
10217 13:42:48.159646 01a00000 ################################################################
10218 13:42:48.159802
10219 13:42:48.423469 01a80000 ################################################################
10220 13:42:48.423599
10221 13:42:48.707712 01b00000 ################################################################
10222 13:42:48.707854
10223 13:42:48.986660 01b80000 ################################################################
10224 13:42:48.986805
10225 13:42:49.266909 01c00000 ################################################################
10226 13:42:49.267058
10227 13:42:49.555556 01c80000 ################################################################
10228 13:42:49.555700
10229 13:42:49.840263 01d00000 ################################################################
10230 13:42:49.840455
10231 13:42:50.115097 01d80000 ################################################################
10232 13:42:50.115240
10233 13:42:50.299256 01e00000 ################################################ done.
10234 13:42:50.299390
10235 13:42:50.302363 The bootfile was 31842362 bytes long.
10236 13:42:50.302454
10237 13:42:50.305944 Sending tftp read request... done.
10238 13:42:50.306140
10239 13:42:50.306283 Waiting for the transfer...
10240 13:42:50.306448
10241 13:42:50.309343 00000000 # done.
10242 13:42:50.309461
10243 13:42:50.315527 Command line loaded dynamically from TFTP file: 14063033/tftp-deploy-qws1jlf3/kernel/cmdline
10244 13:42:50.315728
10245 13:42:50.339343 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10246 13:42:50.339600
10247 13:42:50.339740 Loading FIT.
10248 13:42:50.339868
10249 13:42:50.342309 Image ramdisk-1 has 18731765 bytes.
10250 13:42:50.342507
10251 13:42:50.346258 Image fdt-1 has 47258 bytes.
10252 13:42:50.346589
10253 13:42:50.348914 Image kernel-1 has 13061303 bytes.
10254 13:42:50.349154
10255 13:42:50.359043 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10256 13:42:50.359521
10257 13:42:50.375577 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10258 13:42:50.376019
10259 13:42:50.382657 Choosing best match conf-1 for compat google,spherion-rev2.
10260 13:42:50.383367
10261 13:42:50.389849 Connected to device vid:did:rid of 1ae0:0028:00
10262 13:42:50.398089
10263 13:42:50.401748 tpm_get_response: command 0x17b, return code 0x0
10264 13:42:50.402172
10265 13:42:50.404945 ec_init: CrosEC protocol v3 supported (256, 248)
10266 13:42:50.409152
10267 13:42:50.412060 tpm_cleanup: add release locality here.
10268 13:42:50.412509
10269 13:42:50.412844 Shutting down all USB controllers.
10270 13:42:50.415538
10271 13:42:50.415950 Removing current net device
10272 13:42:50.416276
10273 13:42:50.422198 Exiting depthcharge with code 4 at timestamp: 52453039
10274 13:42:50.422619
10275 13:42:50.425191 LZMA decompressing kernel-1 to 0x821a6718
10276 13:42:50.425607
10277 13:42:50.428751 LZMA decompressing kernel-1 to 0x40000000
10278 13:42:52.039917
10279 13:42:52.040474 jumping to kernel
10280 13:42:52.042176 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10281 13:42:52.042661 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10282 13:42:52.043075 Setting prompt string to ['Linux version [0-9]']
10283 13:42:52.043418 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10284 13:42:52.043762 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10285 13:42:52.121809
10286 13:42:52.124673 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10287 13:42:52.128803 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10288 13:42:52.129591 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10289 13:42:52.130123 Setting prompt string to []
10290 13:42:52.130721 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10291 13:42:52.131399 Using line separator: #'\n'#
10292 13:42:52.131930 No login prompt set.
10293 13:42:52.132416 Parsing kernel messages
10294 13:42:52.132723 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10295 13:42:52.133341 [login-action] Waiting for messages, (timeout 00:04:00)
10296 13:42:52.133700 Waiting using forced prompt support (timeout 00:02:00)
10297 13:42:52.148117 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10298 13:42:52.151908 [ 0.000000] random: crng init done
10299 13:42:52.158367 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10300 13:42:52.161288 [ 0.000000] efi: UEFI not found.
10301 13:42:52.168009 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10302 13:42:52.174674 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10303 13:42:52.185064 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10304 13:42:52.194881 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10305 13:42:52.201211 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10306 13:42:52.207740 [ 0.000000] printk: bootconsole [mtk8250] enabled
10307 13:42:52.214885 [ 0.000000] NUMA: No NUMA configuration found
10308 13:42:52.221154 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10309 13:42:52.224380 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10310 13:42:52.228111 [ 0.000000] Zone ranges:
10311 13:42:52.234484 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10312 13:42:52.238040 [ 0.000000] DMA32 empty
10313 13:42:52.244626 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10314 13:42:52.247485 [ 0.000000] Movable zone start for each node
10315 13:42:52.251537 [ 0.000000] Early memory node ranges
10316 13:42:52.258087 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10317 13:42:52.263743 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10318 13:42:52.270394 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10319 13:42:52.276982 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10320 13:42:52.280777 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10321 13:42:52.290474 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10322 13:42:52.346794 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10323 13:42:52.352698 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10324 13:42:52.359443 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10325 13:42:52.363178 [ 0.000000] psci: probing for conduit method from DT.
10326 13:42:52.369494 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10327 13:42:52.372883 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10328 13:42:52.379396 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10329 13:42:52.382699 [ 0.000000] psci: SMC Calling Convention v1.2
10330 13:42:52.389464 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10331 13:42:52.392980 [ 0.000000] Detected VIPT I-cache on CPU0
10332 13:42:52.399545 [ 0.000000] CPU features: detected: GIC system register CPU interface
10333 13:42:52.406171 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10334 13:42:52.412884 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10335 13:42:52.419654 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10336 13:42:52.426402 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10337 13:42:52.436405 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10338 13:42:52.439185 [ 0.000000] alternatives: applying boot alternatives
10339 13:42:52.446107 [ 0.000000] Fallback order for Node 0: 0
10340 13:42:52.452605 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10341 13:42:52.456209 [ 0.000000] Policy zone: Normal
10342 13:42:52.479252 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10343 13:42:52.489190 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10344 13:42:52.499608 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10345 13:42:52.509621 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10346 13:42:52.516336 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10347 13:42:52.519583 <6>[ 0.000000] software IO TLB: area num 8.
10348 13:42:52.576083 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10349 13:42:52.725491 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10350 13:42:52.732401 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10351 13:42:52.738957 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10352 13:42:52.742241 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10353 13:42:52.749573 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10354 13:42:52.755815 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10355 13:42:52.759008 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10356 13:42:52.769182 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10357 13:42:52.775885 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10358 13:42:52.778973 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10359 13:42:52.786193 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10360 13:42:52.789753 <6>[ 0.000000] GICv3: 608 SPIs implemented
10361 13:42:52.796476 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10362 13:42:52.800048 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10363 13:42:52.803043 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10364 13:42:52.812869 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10365 13:42:52.822956 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10366 13:42:52.836499 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10367 13:42:52.842463 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10368 13:42:52.851489 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10369 13:42:52.864917 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10370 13:42:52.871520 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10371 13:42:52.878635 <6>[ 0.009190] Console: colour dummy device 80x25
10372 13:42:52.888460 <6>[ 0.013916] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10373 13:42:52.895290 <6>[ 0.024422] pid_max: default: 32768 minimum: 301
10374 13:42:52.898575 <6>[ 0.029325] LSM: Security Framework initializing
10375 13:42:52.904905 <6>[ 0.034263] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10376 13:42:52.914481 <6>[ 0.042124] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 13:42:52.924511 <6>[ 0.051538] cblist_init_generic: Setting adjustable number of callback queues.
10378 13:42:52.928163 <6>[ 0.058983] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 13:42:52.937981 <6>[ 0.065322] cblist_init_generic: Setting adjustable number of callback queues.
10380 13:42:52.944667 <6>[ 0.072748] cblist_init_generic: Setting shift to 3 and lim to 1.
10381 13:42:52.947580 <6>[ 0.079148] rcu: Hierarchical SRCU implementation.
10382 13:42:52.954199 <6>[ 0.084196] rcu: Max phase no-delay instances is 1000.
10383 13:42:52.960896 <6>[ 0.091229] EFI services will not be available.
10384 13:42:52.964136 <6>[ 0.096220] smp: Bringing up secondary CPUs ...
10385 13:42:52.973013 <6>[ 0.101268] Detected VIPT I-cache on CPU1
10386 13:42:52.979763 <6>[ 0.101340] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10387 13:42:52.985815 <6>[ 0.101370] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10388 13:42:52.989830 <6>[ 0.101713] Detected VIPT I-cache on CPU2
10389 13:42:52.995723 <6>[ 0.101764] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10390 13:42:53.002966 <6>[ 0.101781] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10391 13:42:53.009371 <6>[ 0.102041] Detected VIPT I-cache on CPU3
10392 13:42:53.016177 <6>[ 0.102088] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10393 13:42:53.022761 <6>[ 0.102102] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10394 13:42:53.025642 <6>[ 0.102409] CPU features: detected: Spectre-v4
10395 13:42:53.032583 <6>[ 0.102415] CPU features: detected: Spectre-BHB
10396 13:42:53.035427 <6>[ 0.102420] Detected PIPT I-cache on CPU4
10397 13:42:53.042196 <6>[ 0.102478] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10398 13:42:53.048694 <6>[ 0.102494] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10399 13:42:53.055868 <6>[ 0.102788] Detected PIPT I-cache on CPU5
10400 13:42:53.062584 <6>[ 0.102850] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10401 13:42:53.068869 <6>[ 0.102866] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10402 13:42:53.072476 <6>[ 0.103149] Detected PIPT I-cache on CPU6
10403 13:42:53.079167 <6>[ 0.103214] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10404 13:42:53.085122 <6>[ 0.103230] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10405 13:42:53.092446 <6>[ 0.103527] Detected PIPT I-cache on CPU7
10406 13:42:53.098911 <6>[ 0.103592] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10407 13:42:53.105238 <6>[ 0.103608] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10408 13:42:53.108473 <6>[ 0.103654] smp: Brought up 1 node, 8 CPUs
10409 13:42:53.114805 <6>[ 0.244993] SMP: Total of 8 processors activated.
10410 13:42:53.118339 <6>[ 0.249945] CPU features: detected: 32-bit EL0 Support
10411 13:42:53.128176 <6>[ 0.255308] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10412 13:42:53.134950 <6>[ 0.264108] CPU features: detected: Common not Private translations
10413 13:42:53.141318 <6>[ 0.270584] CPU features: detected: CRC32 instructions
10414 13:42:53.144970 <6>[ 0.275935] CPU features: detected: RCpc load-acquire (LDAPR)
10415 13:42:53.151681 <6>[ 0.281932] CPU features: detected: LSE atomic instructions
10416 13:42:53.157830 <6>[ 0.287714] CPU features: detected: Privileged Access Never
10417 13:42:53.164466 <6>[ 0.293493] CPU features: detected: RAS Extension Support
10418 13:42:53.171060 <6>[ 0.299101] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10419 13:42:53.174279 <6>[ 0.306318] CPU: All CPU(s) started at EL2
10420 13:42:53.180935 <6>[ 0.310635] alternatives: applying system-wide alternatives
10421 13:42:53.190324 <6>[ 0.321490] devtmpfs: initialized
10422 13:42:53.205999 <6>[ 0.330580] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10423 13:42:53.212880 <6>[ 0.340541] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10424 13:42:53.219286 <6>[ 0.348556] pinctrl core: initialized pinctrl subsystem
10425 13:42:53.223163 <6>[ 0.355209] DMI not present or invalid.
10426 13:42:53.229400 <6>[ 0.359617] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10427 13:42:53.239217 <6>[ 0.366483] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10428 13:42:53.245790 <6>[ 0.374065] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10429 13:42:53.255739 <6>[ 0.382282] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10430 13:42:53.259541 <6>[ 0.390525] audit: initializing netlink subsys (disabled)
10431 13:42:53.269073 <5>[ 0.396218] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10432 13:42:53.275887 <6>[ 0.396935] thermal_sys: Registered thermal governor 'step_wise'
10433 13:42:53.282863 <6>[ 0.404183] thermal_sys: Registered thermal governor 'power_allocator'
10434 13:42:53.285401 <6>[ 0.410440] cpuidle: using governor menu
10435 13:42:53.292206 <6>[ 0.421401] NET: Registered PF_QIPCRTR protocol family
10436 13:42:53.298854 <6>[ 0.426884] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10437 13:42:53.301896 <6>[ 0.433987] ASID allocator initialised with 32768 entries
10438 13:42:53.309537 <6>[ 0.440584] Serial: AMBA PL011 UART driver
10439 13:42:53.318233 <4>[ 0.449404] Trying to register duplicate clock ID: 134
10440 13:42:53.378362 <6>[ 0.512628] KASLR enabled
10441 13:42:53.393294 <6>[ 0.520446] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10442 13:42:53.399874 <6>[ 0.527457] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10443 13:42:53.406330 <6>[ 0.533945] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10444 13:42:53.412419 <6>[ 0.540948] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10445 13:42:53.419190 <6>[ 0.547435] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10446 13:42:53.426253 <6>[ 0.554440] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10447 13:42:53.432126 <6>[ 0.560927] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10448 13:42:53.439182 <6>[ 0.567930] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10449 13:42:53.442266 <6>[ 0.575455] ACPI: Interpreter disabled.
10450 13:42:53.451070 <6>[ 0.581903] iommu: Default domain type: Translated
10451 13:42:53.458328 <6>[ 0.587013] iommu: DMA domain TLB invalidation policy: strict mode
10452 13:42:53.461256 <5>[ 0.593672] SCSI subsystem initialized
10453 13:42:53.467406 <6>[ 0.597837] usbcore: registered new interface driver usbfs
10454 13:42:53.474108 <6>[ 0.603567] usbcore: registered new interface driver hub
10455 13:42:53.477703 <6>[ 0.609118] usbcore: registered new device driver usb
10456 13:42:53.484766 <6>[ 0.615220] pps_core: LinuxPPS API ver. 1 registered
10457 13:42:53.494732 <6>[ 0.620413] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10458 13:42:53.497847 <6>[ 0.629757] PTP clock support registered
10459 13:42:53.500615 <6>[ 0.633999] EDAC MC: Ver: 3.0.0
10460 13:42:53.508448 <6>[ 0.639161] FPGA manager framework
10461 13:42:53.515209 <6>[ 0.642848] Advanced Linux Sound Architecture Driver Initialized.
10462 13:42:53.518590 <6>[ 0.649631] vgaarb: loaded
10463 13:42:53.525265 <6>[ 0.652797] clocksource: Switched to clocksource arch_sys_counter
10464 13:42:53.528178 <5>[ 0.659234] VFS: Disk quotas dquot_6.6.0
10465 13:42:53.535059 <6>[ 0.663421] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10466 13:42:53.537752 <6>[ 0.670607] pnp: PnP ACPI: disabled
10467 13:42:53.546807 <6>[ 0.677342] NET: Registered PF_INET protocol family
10468 13:42:53.556741 <6>[ 0.682933] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10469 13:42:53.567898 <6>[ 0.695261] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10470 13:42:53.577428 <6>[ 0.704074] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10471 13:42:53.584778 <6>[ 0.712045] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10472 13:42:53.591348 <6>[ 0.720747] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10473 13:42:53.602865 <6>[ 0.730499] TCP: Hash tables configured (established 65536 bind 65536)
10474 13:42:53.609515 <6>[ 0.737360] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10475 13:42:53.615718 <6>[ 0.744556] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10476 13:42:53.622293 <6>[ 0.752254] NET: Registered PF_UNIX/PF_LOCAL protocol family
10477 13:42:53.629001 <6>[ 0.758399] RPC: Registered named UNIX socket transport module.
10478 13:42:53.632194 <6>[ 0.764552] RPC: Registered udp transport module.
10479 13:42:53.639064 <6>[ 0.769486] RPC: Registered tcp transport module.
10480 13:42:53.645489 <6>[ 0.774417] RPC: Registered tcp NFSv4.1 backchannel transport module.
10481 13:42:53.649248 <6>[ 0.781083] PCI: CLS 0 bytes, default 64
10482 13:42:53.652098 <6>[ 0.785411] Unpacking initramfs...
10483 13:42:53.674316 <6>[ 0.801338] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10484 13:42:53.683944 <6>[ 0.809987] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10485 13:42:53.687078 <6>[ 0.818805] kvm [1]: IPA Size Limit: 40 bits
10486 13:42:53.693810 <6>[ 0.823332] kvm [1]: GICv3: no GICV resource entry
10487 13:42:53.696863 <6>[ 0.828350] kvm [1]: disabling GICv2 emulation
10488 13:42:53.703547 <6>[ 0.833037] kvm [1]: GIC system register CPU interface enabled
10489 13:42:53.706632 <6>[ 0.839190] kvm [1]: vgic interrupt IRQ18
10490 13:42:53.713993 <6>[ 0.843545] kvm [1]: VHE mode initialized successfully
10491 13:42:53.720249 <5>[ 0.849852] Initialise system trusted keyrings
10492 13:42:53.726418 <6>[ 0.854617] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10493 13:42:53.734287 <6>[ 0.864717] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10494 13:42:53.740055 <5>[ 0.871118] NFS: Registering the id_resolver key type
10495 13:42:53.743973 <5>[ 0.876422] Key type id_resolver registered
10496 13:42:53.750505 <5>[ 0.880838] Key type id_legacy registered
10497 13:42:53.756810 <6>[ 0.885116] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10498 13:42:53.763572 <6>[ 0.892039] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10499 13:42:53.770256 <6>[ 0.899750] 9p: Installing v9fs 9p2000 file system support
10500 13:42:53.808027 <5>[ 0.938621] Key type asymmetric registered
10501 13:42:53.811201 <5>[ 0.942950] Asymmetric key parser 'x509' registered
10502 13:42:53.820972 <6>[ 0.948088] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10503 13:42:53.824644 <6>[ 0.955699] io scheduler mq-deadline registered
10504 13:42:53.827531 <6>[ 0.960460] io scheduler kyber registered
10505 13:42:53.846999 <6>[ 0.977518] EINJ: ACPI disabled.
10506 13:42:53.879405 <4>[ 1.003826] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10507 13:42:53.889520 <4>[ 1.014611] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10508 13:42:53.904157 <6>[ 1.035415] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10509 13:42:53.912100 <6>[ 1.043268] printk: console [ttyS0] disabled
10510 13:42:53.940432 <6>[ 1.067893] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10511 13:42:53.947194 <6>[ 1.077375] printk: console [ttyS0] enabled
10512 13:42:53.950121 <6>[ 1.077375] printk: console [ttyS0] enabled
10513 13:42:53.956901 <6>[ 1.086272] printk: bootconsole [mtk8250] disabled
10514 13:42:53.960716 <6>[ 1.086272] printk: bootconsole [mtk8250] disabled
10515 13:42:53.966621 <6>[ 1.097296] SuperH (H)SCI(F) driver initialized
10516 13:42:53.969810 <6>[ 1.102554] msm_serial: driver initialized
10517 13:42:53.984287 <6>[ 1.111468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10518 13:42:53.993719 <6>[ 1.120013] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10519 13:42:54.000925 <6>[ 1.128556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10520 13:42:54.010470 <6>[ 1.137183] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10521 13:42:54.017105 <6>[ 1.145891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10522 13:42:54.026925 <6>[ 1.154605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10523 13:42:54.037008 <6>[ 1.163145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10524 13:42:54.043386 <6>[ 1.171945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10525 13:42:54.053538 <6>[ 1.180488] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10526 13:42:54.065373 <6>[ 1.195900] loop: module loaded
10527 13:42:54.071501 <6>[ 1.201895] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10528 13:42:54.094145 <4>[ 1.225241] mtk-pmic-keys: Failed to locate of_node [id: -1]
10529 13:42:54.101008 <6>[ 1.232029] megasas: 07.719.03.00-rc1
10530 13:42:54.111142 <6>[ 1.241749] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10531 13:42:54.121775 <6>[ 1.252197] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10532 13:42:54.137394 <6>[ 1.268145] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10533 13:42:54.193083 <6>[ 1.317441] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10534 13:42:54.471301 <6>[ 1.602359] Freeing initrd memory: 18288K
10535 13:42:54.483218 <6>[ 1.614114] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10536 13:42:54.493991 <6>[ 1.625261] tun: Universal TUN/TAP device driver, 1.6
10537 13:42:54.498205 <6>[ 1.631339] thunder_xcv, ver 1.0
10538 13:42:54.500969 <6>[ 1.634853] thunder_bgx, ver 1.0
10539 13:42:54.503941 <6>[ 1.638348] nicpf, ver 1.0
10540 13:42:54.514428 <6>[ 1.642372] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10541 13:42:54.518289 <6>[ 1.649847] hns3: Copyright (c) 2017 Huawei Corporation.
10542 13:42:54.524635 <6>[ 1.655451] hclge is initializing
10543 13:42:54.528006 <6>[ 1.659032] e1000: Intel(R) PRO/1000 Network Driver
10544 13:42:54.534529 <6>[ 1.664161] e1000: Copyright (c) 1999-2006 Intel Corporation.
10545 13:42:54.538205 <6>[ 1.670175] e1000e: Intel(R) PRO/1000 Network Driver
10546 13:42:54.545004 <6>[ 1.675390] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10547 13:42:54.551151 <6>[ 1.681575] igb: Intel(R) Gigabit Ethernet Network Driver
10548 13:42:54.558345 <6>[ 1.687225] igb: Copyright (c) 2007-2014 Intel Corporation.
10549 13:42:54.565022 <6>[ 1.693064] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10550 13:42:54.571620 <6>[ 1.699581] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10551 13:42:54.575063 <6>[ 1.706045] sky2: driver version 1.30
10552 13:42:54.581209 <6>[ 1.710978] usbcore: registered new device driver r8152-cfgselector
10553 13:42:54.588125 <6>[ 1.717512] usbcore: registered new interface driver r8152
10554 13:42:54.590998 <6>[ 1.723328] VFIO - User Level meta-driver version: 0.3
10555 13:42:54.600830 <6>[ 1.731563] usbcore: registered new interface driver usb-storage
10556 13:42:54.607413 <6>[ 1.738008] usbcore: registered new device driver onboard-usb-hub
10557 13:42:54.616479 <6>[ 1.747125] mt6397-rtc mt6359-rtc: registered as rtc0
10558 13:42:54.626563 <6>[ 1.752587] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:38:14 UTC (1716903494)
10559 13:42:54.629093 <6>[ 1.762146] i2c_dev: i2c /dev entries driver
10560 13:42:54.646754 <6>[ 1.773915] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10561 13:42:54.652806 <4>[ 1.782638] cpu cpu0: supply cpu not found, using dummy regulator
10562 13:42:54.659550 <4>[ 1.789066] cpu cpu1: supply cpu not found, using dummy regulator
10563 13:42:54.666458 <4>[ 1.795474] cpu cpu2: supply cpu not found, using dummy regulator
10564 13:42:54.672943 <4>[ 1.801878] cpu cpu3: supply cpu not found, using dummy regulator
10565 13:42:54.680037 <4>[ 1.808278] cpu cpu4: supply cpu not found, using dummy regulator
10566 13:42:54.686227 <4>[ 1.814689] cpu cpu5: supply cpu not found, using dummy regulator
10567 13:42:54.692896 <4>[ 1.821087] cpu cpu6: supply cpu not found, using dummy regulator
10568 13:42:54.696237 <4>[ 1.827485] cpu cpu7: supply cpu not found, using dummy regulator
10569 13:42:54.717291 <6>[ 1.848119] cpu cpu0: EM: created perf domain
10570 13:42:54.720299 <6>[ 1.853066] cpu cpu4: EM: created perf domain
10571 13:42:54.727758 <6>[ 1.858666] sdhci: Secure Digital Host Controller Interface driver
10572 13:42:54.734599 <6>[ 1.865098] sdhci: Copyright(c) Pierre Ossman
10573 13:42:54.741104 <6>[ 1.870055] Synopsys Designware Multimedia Card Interface Driver
10574 13:42:54.747810 <6>[ 1.876687] sdhci-pltfm: SDHCI platform and OF driver helper
10575 13:42:54.751427 <6>[ 1.876737] mmc0: CQHCI version 5.10
10576 13:42:54.757786 <6>[ 1.886944] ledtrig-cpu: registered to indicate activity on CPUs
10577 13:42:54.764679 <6>[ 1.894055] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10578 13:42:54.771955 <6>[ 1.901108] usbcore: registered new interface driver usbhid
10579 13:42:54.774867 <6>[ 1.906930] usbhid: USB HID core driver
10580 13:42:54.781303 <6>[ 1.911132] spi_master spi0: will run message pump with realtime priority
10581 13:42:54.828107 <6>[ 1.952658] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10582 13:42:54.844472 <6>[ 1.968897] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10583 13:42:54.853320 <6>[ 1.984340] mmc0: Command Queue Engine enabled
10584 13:42:54.860601 <6>[ 1.984652] cros-ec-spi spi0.0: Chrome EC device registered
10585 13:42:54.866791 <6>[ 1.989078] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10586 13:42:54.870177 <6>[ 2.002454] mmcblk0: mmc0:0001 DA4128 116 GiB
10587 13:42:54.881676 <6>[ 2.009551] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10588 13:42:54.888454 <6>[ 2.012670] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10589 13:42:54.895603 <6>[ 2.019831] NET: Registered PF_PACKET protocol family
10590 13:42:54.898542 <6>[ 2.026324] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 13:42:54.904968 <6>[ 2.030148] 9pnet: Installing 9P2000 support
10592 13:42:54.908701 <6>[ 2.035939] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 13:42:54.911647 <5>[ 2.039850] Key type dns_resolver registered
10594 13:42:54.918600 <6>[ 2.045734] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10595 13:42:54.925211 <6>[ 2.050004] registered taskstats version 1
10596 13:42:54.928309 <5>[ 2.060459] Loading compiled-in X.509 certificates
10597 13:42:54.957512 <4>[ 2.081765] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 13:42:54.967136 <4>[ 2.092482] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 13:42:54.981016 <6>[ 2.112216] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10600 13:42:54.988304 <6>[ 2.119102] xhci-mtk 11200000.usb: xHCI Host Controller
10601 13:42:54.994273 <6>[ 2.124611] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10602 13:42:55.004788 <6>[ 2.132487] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10603 13:42:55.011329 <6>[ 2.141974] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10604 13:42:55.018136 <6>[ 2.148069] xhci-mtk 11200000.usb: xHCI Host Controller
10605 13:42:55.024991 <6>[ 2.153556] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10606 13:42:55.031016 <6>[ 2.161318] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10607 13:42:55.038532 <6>[ 2.169207] hub 1-0:1.0: USB hub found
10608 13:42:55.041429 <6>[ 2.173239] hub 1-0:1.0: 1 port detected
10609 13:42:55.051535 <6>[ 2.177559] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10610 13:42:55.055050 <6>[ 2.186383] hub 2-0:1.0: USB hub found
10611 13:42:55.058001 <6>[ 2.190413] hub 2-0:1.0: 1 port detected
10612 13:42:55.066282 <6>[ 2.197132] mtk-msdc 11f70000.mmc: Got CD GPIO
10613 13:42:55.080789 <6>[ 2.208043] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10614 13:42:55.087109 <6>[ 2.216082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10615 13:42:55.097012 <4>[ 2.224003] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10616 13:42:55.107061 <6>[ 2.233532] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10617 13:42:55.113494 <6>[ 2.241610] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10618 13:42:55.120124 <6>[ 2.249624] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10619 13:42:55.130212 <6>[ 2.257540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10620 13:42:55.136931 <6>[ 2.265357] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10621 13:42:55.146685 <6>[ 2.273175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10622 13:42:55.157299 <6>[ 2.283171] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10623 13:42:55.163656 <6>[ 2.291525] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10624 13:42:55.173969 <6>[ 2.299874] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10625 13:42:55.180680 <6>[ 2.308213] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10626 13:42:55.190507 <6>[ 2.316550] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10627 13:42:55.196459 <6>[ 2.324888] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10628 13:42:55.206966 <6>[ 2.333224] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10629 13:42:55.213686 <6>[ 2.341562] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10630 13:42:55.223322 <6>[ 2.349900] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10631 13:42:55.230073 <6>[ 2.358239] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10632 13:42:55.239934 <6>[ 2.366576] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10633 13:42:55.246679 <6>[ 2.374914] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10634 13:42:55.256032 <6>[ 2.383252] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10635 13:42:55.263285 <6>[ 2.391588] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10636 13:42:55.272710 <6>[ 2.399926] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10637 13:42:55.280051 <6>[ 2.408653] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10638 13:42:55.286485 <6>[ 2.415811] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10639 13:42:55.292738 <6>[ 2.422562] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10640 13:42:55.299194 <6>[ 2.429326] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10641 13:42:55.305938 <6>[ 2.436267] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10642 13:42:55.316326 <6>[ 2.443126] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10643 13:42:55.326084 <6>[ 2.452256] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10644 13:42:55.335860 <6>[ 2.461376] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10645 13:42:55.342028 <6>[ 2.470669] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10646 13:42:55.352664 <6>[ 2.480136] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10647 13:42:55.362361 <6>[ 2.489604] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10648 13:42:55.372627 <6>[ 2.498723] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10649 13:42:55.382197 <6>[ 2.508190] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10650 13:42:55.388637 <6>[ 2.517310] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10651 13:42:55.402232 <6>[ 2.526604] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10652 13:42:55.412124 <6>[ 2.536767] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10653 13:42:55.422311 <6>[ 2.548598] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10654 13:42:55.428630 <6>[ 2.558286] Trying to probe devices needed for running init ...
10655 13:42:55.473729 <6>[ 2.601014] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10656 13:42:55.627241 <6>[ 2.758131] hub 1-1:1.0: USB hub found
10657 13:42:55.630125 <6>[ 2.762588] hub 1-1:1.0: 4 ports detected
10658 13:42:55.640066 <6>[ 2.771232] hub 1-1:1.0: USB hub found
10659 13:42:55.643146 <6>[ 2.775600] hub 1-1:1.0: 4 ports detected
10660 13:42:55.753585 <6>[ 2.881449] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10661 13:42:55.780459 <6>[ 2.911240] hub 2-1:1.0: USB hub found
10662 13:42:55.783705 <6>[ 2.915776] hub 2-1:1.0: 3 ports detected
10663 13:42:55.793327 <6>[ 2.924349] hub 2-1:1.0: USB hub found
10664 13:42:55.796841 <6>[ 2.928811] hub 2-1:1.0: 3 ports detected
10665 13:42:55.969398 <6>[ 3.097125] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10666 13:42:56.102297 <6>[ 3.233107] hub 1-1.4:1.0: USB hub found
10667 13:42:56.105029 <6>[ 3.237782] hub 1-1.4:1.0: 2 ports detected
10668 13:42:56.114802 <6>[ 3.245749] hub 1-1.4:1.0: USB hub found
10669 13:42:56.117522 <6>[ 3.250301] hub 1-1.4:1.0: 2 ports detected
10670 13:42:56.181416 <6>[ 3.309230] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10671 13:42:56.289863 <6>[ 3.417802] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10672 13:42:56.326401 <4>[ 3.454348] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10673 13:42:56.336312 <4>[ 3.463472] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10674 13:42:56.379632 <6>[ 3.510751] r8152 2-1.3:1.0 eth0: v1.12.13
10675 13:42:56.413231 <6>[ 3.541124] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10676 13:42:56.605256 <6>[ 3.733122] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10677 13:42:58.002525 <6>[ 5.134175] r8152 2-1.3:1.0 eth0: carrier on
10678 13:43:00.077524 <5>[ 5.160875] Sending DHCP requests .., OK
10679 13:43:00.083312 <6>[ 7.213283] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10680 13:43:00.087015 <6>[ 7.221581] IP-Config: Complete:
10681 13:43:00.099962 <6>[ 7.225086] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10682 13:43:00.106644 <6>[ 7.235797] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10683 13:43:00.113420 <6>[ 7.244415] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10684 13:43:00.120347 <6>[ 7.244425] nameserver0=192.168.201.1
10685 13:43:00.123032 <6>[ 7.256646] clk: Disabling unused clocks
10686 13:43:00.127076 <6>[ 7.262225] ALSA device list:
10687 13:43:00.133137 <6>[ 7.265491] No soundcards found.
10688 13:43:00.140939 <6>[ 7.272730] Freeing unused kernel memory: 8512K
10689 13:43:00.143986 <6>[ 7.277694] Run /init as init process
10690 13:43:00.153631 Loading, please wait...
10691 13:43:00.181894 Starting systemd-udevd version 252.22-1~deb12u1
10692 13:43:00.451369 <6>[ 7.580054] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10693 13:43:00.457870 <6>[ 7.584054] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10694 13:43:00.464349 <3>[ 7.591030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 13:43:00.474597 <6>[ 7.591314] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10696 13:43:00.484617 <6>[ 7.591322] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10697 13:43:00.490800 <4>[ 7.596390] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10698 13:43:00.497907 <3>[ 7.603574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 13:43:00.507823 <3>[ 7.636021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 13:43:00.514411 <4>[ 7.636598] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10701 13:43:00.520796 <3>[ 7.647952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 13:43:00.527750 <6>[ 7.651931] remoteproc remoteproc0: scp is available
10703 13:43:00.534311 <3>[ 7.659523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 13:43:00.543978 <3>[ 7.659531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 13:43:00.551367 <3>[ 7.659538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 13:43:00.557441 <6>[ 7.664959] remoteproc remoteproc0: powering up scp
10707 13:43:00.563973 <3>[ 7.672836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 13:43:00.573964 <6>[ 7.680918] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10709 13:43:00.580662 <6>[ 7.685820] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10710 13:43:00.591106 <3>[ 7.689031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 13:43:00.594023 <6>[ 7.695000] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10712 13:43:00.604385 <3>[ 7.702542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 13:43:00.607155 <6>[ 7.702871] mc: Linux media interface: v0.10
10714 13:43:00.614300 <6>[ 7.707579] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10715 13:43:00.620602 <6>[ 7.707595] pci_bus 0000:00: root bus resource [bus 00-ff]
10716 13:43:00.627166 <6>[ 7.707609] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10717 13:43:00.637343 <6>[ 7.707614] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 13:43:00.644182 <6>[ 7.707648] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 13:43:00.651002 <6>[ 7.707668] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10720 13:43:00.657523 <6>[ 7.707753] pci 0000:00:00.0: supports D1 D2
10721 13:43:00.663950 <6>[ 7.707756] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 13:43:00.670607 <6>[ 7.709841] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10723 13:43:00.677454 <6>[ 7.710014] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10724 13:43:00.684096 <6>[ 7.710055] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10725 13:43:00.694202 <6>[ 7.710078] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10726 13:43:00.700177 <6>[ 7.710097] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10727 13:43:00.703769 <6>[ 7.710244] pci 0000:01:00.0: supports D1 D2
10728 13:43:00.710134 <6>[ 7.710247] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10729 13:43:00.717223 <6>[ 7.720955] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10730 13:43:00.726976 <3>[ 7.726420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 13:43:00.733632 <3>[ 7.726424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 13:43:00.743169 <3>[ 7.726471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 13:43:00.746885 <6>[ 7.729468] videodev: Linux video capture interface: v2.00
10734 13:43:00.756994 <6>[ 7.732280] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10735 13:43:00.763448 <3>[ 7.740279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 13:43:00.773604 <3>[ 7.740292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 13:43:00.780348 <3>[ 7.740301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 13:43:00.789779 <3>[ 7.740305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 13:43:00.796391 <3>[ 7.740479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 13:43:00.803078 <6>[ 7.745046] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10741 13:43:00.813518 <6>[ 7.822109] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10742 13:43:00.822806 <6>[ 7.829639] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10743 13:43:00.832841 <6>[ 7.832608] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10744 13:43:00.839610 <6>[ 7.833567] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10745 13:43:00.849375 <6>[ 7.836374] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10746 13:43:00.857376 <6>[ 7.836403] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10747 13:43:00.864110 <6>[ 7.836410] remoteproc remoteproc0: remote processor scp is now up
10748 13:43:00.870069 <6>[ 7.850532] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10749 13:43:00.880231 <6>[ 7.855162] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10750 13:43:00.886867 <6>[ 7.871147] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10751 13:43:00.897067 <6>[ 7.871308] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10752 13:43:00.900400 <6>[ 7.880203] Bluetooth: Core ver 2.22
10753 13:43:00.903842 <6>[ 7.885122] pci 0000:00:00.0: PCI bridge to [bus 01]
10754 13:43:00.910604 <6>[ 7.893725] NET: Registered PF_BLUETOOTH protocol family
10755 13:43:00.917205 <6>[ 7.894584] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10756 13:43:00.930835 <6>[ 7.895913] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10757 13:43:00.936799 <6>[ 7.896029] usbcore: registered new interface driver uvcvideo
10758 13:43:00.944150 <6>[ 7.901272] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10759 13:43:00.950121 <6>[ 7.901695] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10760 13:43:00.957140 <6>[ 7.909360] Bluetooth: HCI device and connection manager initialized
10761 13:43:00.963595 <6>[ 7.918054] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10762 13:43:00.967151 <6>[ 7.925522] Bluetooth: HCI socket layer initialized
10763 13:43:00.973808 <6>[ 7.926235] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10764 13:43:00.980360 <6>[ 7.934055] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10765 13:43:00.987110 <6>[ 7.941591] Bluetooth: L2CAP socket layer initialized
10766 13:43:00.989947 <6>[ 7.941603] Bluetooth: SCO socket layer initialized
10767 13:43:01.000386 <4>[ 7.964564] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10768 13:43:01.003759 <4>[ 7.964564] Fallback method does not support PEC.
10769 13:43:01.013309 <5>[ 7.973267] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10770 13:43:01.035137 <3>[ 8.000204] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10771 13:43:01.035273 <6>[ 8.009102] usbcore: registered new interface driver btusb
10772 13:43:01.037069 <4>[ 8.009945] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10773 13:43:01.043714 <3>[ 8.009956] Bluetooth: hci0: Failed to load firmware file (-2)
10774 13:43:01.050129 <3>[ 8.009960] Bluetooth: hci0: Failed to set up firmware (-2)
10775 13:43:01.060085 <4>[ 8.009964] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10776 13:43:01.066493 <5>[ 8.024914] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10777 13:43:01.076253 <3>[ 8.037491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 13:43:01.083241 <5>[ 8.043131] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10779 13:43:01.092985 <4>[ 8.220914] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10780 13:43:01.095926 <6>[ 8.229786] cfg80211: failed to load regulatory.db
10781 13:43:01.142102 <6>[ 8.271008] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10782 13:43:01.148713 <6>[ 8.278505] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10783 13:43:01.173214 <6>[ 8.305161] mt7921e 0000:01:00.0: ASIC revision: 79610010
10784 13:43:01.276574 <6>[ 8.405056] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10785 13:43:01.279395 <6>[ 8.405056]
10786 13:43:01.283042 Begin: Loading essential drivers ... done.
10787 13:43:01.286095 Begin: Running /scripts/init-premount ... done.
10788 13:43:01.292894 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10789 13:43:01.303285 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10790 13:43:01.306235 Device /sys/class/net/eth0 found
10791 13:43:01.306314 done.
10792 13:43:01.316923 Begin: Waiting up to 180 secs for any network device to become available ... done.
10793 13:43:01.344904 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10794 13:43:01.351282 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10795 13:43:01.358007 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10796 13:43:01.364365 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10797 13:43:01.371485 host : mt8192-asurada-spherion-r0-cbg-0
10798 13:43:01.378425 domain : lava-rack
10799 13:43:01.381409 rootserver: 192.168.201.1 rootpath:
10800 13:43:01.381487 filename :
10801 13:43:01.546802 <6>[ 8.675802] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10802 13:43:01.556205 done.
10803 13:43:01.562421 Begin: Running /scripts/nfs-bottom ... done.
10804 13:43:01.572877 Begin: Running /scripts/init-bottom ... done.
10805 13:43:02.896584 <6>[ 10.029224] NET: Registered PF_INET6 protocol family
10806 13:43:02.904942 <6>[ 10.037007] Segment Routing with IPv6
10807 13:43:02.907913 <6>[ 10.041001] In-situ OAM (IOAM) with IPv6
10808 13:43:03.072539 <30>[ 10.178434] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10809 13:43:03.079223 <30>[ 10.211549] systemd[1]: Detected architecture arm64.
10810 13:43:03.086777
10811 13:43:03.089770 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10812 13:43:03.089850
10813 13:43:03.113755 <30>[ 10.245980] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10814 13:43:04.116769 <30>[ 11.245781] systemd[1]: Queued start job for default target graphical.target.
10815 13:43:04.160930 <30>[ 11.290414] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10816 13:43:04.168136 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10817 13:43:04.190026 <30>[ 11.319146] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10818 13:43:04.199834 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10819 13:43:04.217770 <30>[ 11.347104] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10820 13:43:04.227853 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10821 13:43:04.245607 <30>[ 11.374673] systemd[1]: Created slice user.slice - User and Session Slice.
10822 13:43:04.252103 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10823 13:43:04.275642 <30>[ 11.401434] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10824 13:43:04.282338 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10825 13:43:04.303699 <30>[ 11.429382] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10826 13:43:04.310388 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10827 13:43:04.338062 <30>[ 11.457307] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10828 13:43:04.347710 <30>[ 11.477137] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10829 13:43:04.354583 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10830 13:43:04.372504 <30>[ 11.501431] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10831 13:43:04.381874 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10832 13:43:04.400125 <30>[ 11.529208] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10833 13:43:04.409958 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10834 13:43:04.425110 <30>[ 11.557708] systemd[1]: Reached target paths.target - Path Units.
10835 13:43:04.435512 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10836 13:43:04.452397 <30>[ 11.581570] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10837 13:43:04.458743 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10838 13:43:04.472462 <30>[ 11.605162] systemd[1]: Reached target slices.target - Slice Units.
10839 13:43:04.482612 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10840 13:43:04.497199 <30>[ 11.629534] systemd[1]: Reached target swap.target - Swaps.
10841 13:43:04.503618 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10842 13:43:04.524449 <30>[ 11.653646] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10843 13:43:04.533978 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10844 13:43:04.553057 <30>[ 11.682126] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10845 13:43:04.562993 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10846 13:43:04.582618 <30>[ 11.711606] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10847 13:43:04.592505 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10848 13:43:04.609616 <30>[ 11.739081] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10849 13:43:04.619719 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10850 13:43:04.637075 <30>[ 11.765912] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10851 13:43:04.643012 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10852 13:43:04.661889 <30>[ 11.790647] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10853 13:43:04.671067 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10854 13:43:04.690463 <30>[ 11.819800] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10855 13:43:04.700372 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10856 13:43:04.717182 <30>[ 11.846369] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10857 13:43:04.726906 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10858 13:43:04.783867 <30>[ 11.913260] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10859 13:43:04.790351 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10860 13:43:04.813350 <30>[ 11.942354] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10861 13:43:04.819583 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10862 13:43:04.876138 <30>[ 12.005510] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10863 13:43:04.882680 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10864 13:43:04.911292 <30>[ 12.033897] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10865 13:43:04.926924 <30>[ 12.056502] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10866 13:43:04.937210 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10867 13:43:04.962135 <30>[ 12.091630] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10868 13:43:04.969065 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10869 13:43:04.993965 <30>[ 12.123266] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10870 13:43:05.000705 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10871 13:43:05.031400 <6>[ 12.160660] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10872 13:43:05.068758 <30>[ 12.198191] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10873 13:43:05.075585 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10874 13:43:05.102258 <30>[ 12.231730] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10875 13:43:05.112055 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10876 13:43:05.134267 <30>[ 12.263316] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10877 13:43:05.140735 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10878 13:43:05.167958 <6>[ 12.300905] fuse: init (API version 7.37)
10879 13:43:05.200735 <30>[ 12.330174] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10880 13:43:05.207334 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10881 13:43:05.233527 <30>[ 12.362451] systemd[1]: Starting systemd-journald.service - Journal Service...
10882 13:43:05.239935 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10883 13:43:05.261428 <30>[ 12.390558] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10884 13:43:05.267859 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10885 13:43:05.348054 <30>[ 12.474191] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10886 13:43:05.354653 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10887 13:43:05.380163 <30>[ 12.509631] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10888 13:43:05.390267 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10889 13:43:05.415612 <30>[ 12.544587] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10890 13:43:05.425686 <3>[ 12.548207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 13:43:05.431704 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10892 13:43:05.454649 <3>[ 12.583660] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 13:43:05.468246 <30>[ 12.597474] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10894 13:43:05.474713 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10895 13:43:05.490047 <3>[ 12.619605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 13:43:05.500488 <30>[ 12.629599] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10897 13:43:05.510866 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10898 13:43:05.520876 <3>[ 12.648626] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 13:43:05.527528 <30>[ 12.658430] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10900 13:43:05.537882 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10901 13:43:05.551478 <3>[ 12.680568] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 13:43:05.562834 <30>[ 12.692083] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10903 13:43:05.573160 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10904 13:43:05.583210 <3>[ 12.712601] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 13:43:05.593626 <30>[ 12.722897] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10906 13:43:05.600578 <30>[ 12.730932] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10907 13:43:05.614443 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 12.742946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 13:43:05.617421 onfigfs…[0m - Load Kernel Module configfs.
10909 13:43:05.636954 <30>[ 12.766078] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10910 13:43:05.643624 <3>[ 12.774061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 13:43:05.653800 <30>[ 12.774323] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10912 13:43:05.660411 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10913 13:43:05.682077 <30>[ 12.811173] systemd[1]: modprobe@drm.service: Deactivated successfully.
10914 13:43:05.689047 <30>[ 12.819131] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10915 13:43:05.695554 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10916 13:43:05.716994 <30>[ 12.845914] systemd[1]: Started systemd-journald.service - Journal Service.
10917 13:43:05.723528 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10918 13:43:05.749508 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10919 13:43:05.771260 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10920 13:43:05.790744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10921 13:43:05.814979 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10922 13:43:05.845046 [[0;32m OK [0m] Finished [0;1;39msystemd-ne<4>[ 12.966952] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10923 13:43:05.854613 <3>[ 12.983499] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10924 13:43:05.858153 twork-g…rk units from Kernel command line.
10925 13:43:05.883804 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel F<4>[ 13.016416] power_supply_show_property: 3 callbacks suppressed
10926 13:43:05.887461 ile Systems.
10927 13:43:05.893989 <3>[ 13.016439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 13:43:05.906243 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10929 13:43:05.926601 <3>[ 13.055990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 13:43:05.936259 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10931 13:43:05.957122 <3>[ 13.086251] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 13:43:05.987182 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System..<3>[ 13.116005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 13:43:05.987291 .
10934 13:43:06.017456 Mounting [0;1;39msys-kernel-config…ernel Configuration File System..<3>[ 13.146089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:43:06.017573 .
10936 13:43:06.037545 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10937 13:43:06.047991 <3>[ 13.177552] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 13:43:06.063555 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10939 13:43:06.082768 <3>[ 13.212001] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 13:43:06.116679 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<3>[ 13.245447] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 13:43:06.116782 .
10942 13:43:06.149531 <3>[ 13.278637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 13:43:06.169179 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10944 13:43:06.179659 <3>[ 13.308894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 13:43:06.204610 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10946 13:43:06.214527 <46>[ 13.343639] systemd-journald[303]: Received client request to flush runtime journal.
10947 13:43:06.224109 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10948 13:43:06.242035 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10949 13:43:06.262133 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10950 13:43:06.281145 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10951 13:43:06.325199 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10952 13:43:07.661573 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10953 13:43:07.686703 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10954 13:43:07.704663 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10955 13:43:07.723891 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10956 13:43:07.772742 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10957 13:43:07.801052 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10958 13:43:07.984487 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10959 13:43:08.039108 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10960 13:43:08.058174 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10961 13:43:08.137368 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10962 13:43:08.305275 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10963 13:43:08.330958 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10964 13:43:08.430404 <6>[ 15.563124] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10965 13:43:08.459213 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10966 13:43:08.501736 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10967 13:43:08.563314 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10968 13:43:08.605952 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10969 13:43:08.634495 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10970 13:43:08.651950 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10971 13:43:08.677476 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10972 13:43:08.696355 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10973 13:43:08.745780 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10974 13:43:08.764410 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10975 13:43:08.789531 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10976 13:43:08.812030 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10977 13:43:08.828104 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10978 13:43:08.844379 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10979 13:43:08.868891 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10980 13:43:08.891367 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10981 13:43:08.907705 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10982 13:43:08.939578 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10983 13:43:08.959622 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10984 13:43:08.975716 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10985 13:43:08.994441 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10986 13:43:09.011779 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10987 13:43:09.028024 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10988 13:43:09.073495 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10989 13:43:09.107106 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10990 13:43:09.188028 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10991 13:43:09.213987 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10992 13:43:09.282349 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10993 13:43:09.343069 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10994 13:43:09.364104 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10995 13:43:09.384229 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10996 13:43:09.402527 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10997 13:43:09.432287 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10998 13:43:09.590281 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10999 13:43:09.608892 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11000 13:43:09.633083 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11001 13:43:09.693061 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11002 13:43:09.734409 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11003 13:43:09.819671
11004 13:43:09.822909 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11005 13:43:09.823518
11006 13:43:09.826561 debian-bookworm-arm64 login: root (automatic login)
11007 13:43:09.826999
11008 13:43:10.082511 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11009 13:43:10.083040
11010 13:43:10.089738 The programs included with the Debian GNU/Linux system are free software;
11011 13:43:10.096267 the exact distribution terms for each program are described in the
11012 13:43:10.099245 individual files in /usr/share/doc/*/copyright.
11013 13:43:10.099747
11014 13:43:10.105852 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11015 13:43:10.109520 permitted by applicable law.
11016 13:43:10.183854 Matched prompt #10: / #
11018 13:43:10.184104 Setting prompt string to ['/ #']
11019 13:43:10.184198 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11021 13:43:10.184446 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11022 13:43:10.184537 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
11023 13:43:10.184608 Setting prompt string to ['/ #']
11024 13:43:10.184668 Forcing a shell prompt, looking for ['/ #']
11026 13:43:10.234972 / #
11027 13:43:10.235527 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 13:43:10.235983 Waiting using forced prompt support (timeout 00:02:30)
11029 13:43:10.241397
11030 13:43:10.242155 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11031 13:43:10.242631 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
11033 13:43:10.343748 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew'
11034 13:43:10.349747 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063033/extract-nfsrootfs-dycpw4ew'
11036 13:43:10.451285 / # export NFS_SERVER_IP='192.168.201.1'
11037 13:43:10.457380 export NFS_SERVER_IP='192.168.201.1'
11038 13:43:10.458155 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11039 13:43:10.458621 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
11040 13:43:10.459068 end: 2 depthcharge-action (duration 00:01:18) [common]
11041 13:43:10.459520 start: 3 lava-test-retry (timeout 00:01:00) [common]
11042 13:43:10.459962 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11043 13:43:10.460397 Using namespace: common
11045 13:43:10.561500 / # #
11046 13:43:10.562100 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11047 13:43:10.568327 #
11048 13:43:10.569077 Using /lava-14063033
11050 13:43:10.670101 / # export SHELL=/bin/sh
11051 13:43:10.677022 export SHELL=/bin/sh
11053 13:43:10.777613 / # . /lava-14063033/environment
11054 13:43:10.785270 . /lava-14063033/environment
11056 13:43:10.891587 / # /lava-14063033/bin/lava-test-runner /lava-14063033/0
11057 13:43:10.892114 Test shell timeout: 10s (minimum of the action and connection timeout)
11058 13:43:10.898327 /lava-14063033/bin/lava-test-runner /lava-14063033/0
11059 13:43:11.091766 + export TESTRUN_ID=0_dmesg
11060 13:43:11.095220 + cd /lava-14063033/0/tests/0_dmesg
11061 13:43:11.098551 + cat uuid
11062 13:43:11.109018 + UUID=14063033_<8>[ 18.238122] <LAVA_SIGNAL_STARTRUN 0_dmesg 14063033_1.6.2.3.1>
11063 13:43:11.109104 1.6.2.3.1
11064 13:43:11.109172 + set +x
11065 13:43:11.109413 Received signal: <STARTRUN> 0_dmesg 14063033_1.6.2.3.1
11066 13:43:11.109483 Starting test lava.0_dmesg (14063033_1.6.2.3.1)
11067 13:43:11.109564 Skipping test definition patterns.
11068 13:43:11.112255 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11069 13:43:11.192803 <8>[ 18.322742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11070 13:43:11.193098 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11072 13:43:11.252434 <8>[ 18.382019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11073 13:43:11.252728 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11075 13:43:11.312303 <8>[ 18.442194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11076 13:43:11.312625 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11078 13:43:11.315807 + set +x
11079 13:43:11.318568 <8>[ 18.451837] <LAVA_SIGNAL_ENDRUN 0_dmesg 14063033_1.6.2.3.1>
11080 13:43:11.318822 Received signal: <ENDRUN> 0_dmesg 14063033_1.6.2.3.1
11081 13:43:11.318906 Ending use of test pattern.
11082 13:43:11.318969 Ending test lava.0_dmesg (14063033_1.6.2.3.1), duration 0.21
11084 13:43:11.325096 <LAVA_TEST_RUNNER EXIT>
11085 13:43:11.325349 ok: lava_test_shell seems to have completed
11086 13:43:11.325455 alert: pass
crit: pass
emerg: pass
11087 13:43:11.325543 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11088 13:43:11.325626 end: 3 lava-test-retry (duration 00:00:01) [common]
11089 13:43:11.325713 start: 4 finalize (timeout 00:08:13) [common]
11090 13:43:11.325800 start: 4.1 power-off (timeout 00:00:30) [common]
11091 13:43:11.325979 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11092 13:43:11.404013 >> Command sent successfully.
11093 13:43:11.409411 Returned 0 in 0 seconds
11094 13:43:11.510413 end: 4.1 power-off (duration 00:00:00) [common]
11096 13:43:11.511955 start: 4.2 read-feedback (timeout 00:08:13) [common]
11097 13:43:11.513240 Listened to connection for namespace 'common' for up to 1s
11098 13:43:12.513877 Finalising connection for namespace 'common'
11099 13:43:12.514484 Disconnecting from shell: Finalise
11100 13:43:12.514859 / #
11101 13:43:12.615522 end: 4.2 read-feedback (duration 00:00:01) [common]
11102 13:43:12.615676 end: 4 finalize (duration 00:00:01) [common]
11103 13:43:12.615790 Cleaning after the job
11104 13:43:12.615889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/ramdisk
11105 13:43:12.618144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/kernel
11106 13:43:12.628850 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/dtb
11107 13:43:12.629044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/nfsrootfs
11108 13:43:12.686725 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063033/tftp-deploy-qws1jlf3/modules
11109 13:43:12.692663 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063033
11110 13:43:13.012530 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063033
11111 13:43:13.012712 Job finished correctly