Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 13:36:25.873958 lava-dispatcher, installed at version: 2024.03
2 13:36:25.874148 start: 0 validate
3 13:36:25.874278 Start time: 2024-05-28 13:36:25.874271+00:00 (UTC)
4 13:36:25.874395 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:36:25.874525 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:36:26.135318 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:36:26.136041 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:37:39.702338 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:37:39.702503 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:37:39.959376 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:37:39.959530 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:37:40.475488 validate duration: 74.60
14 13:37:40.476832 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:37:40.477432 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:37:40.478222 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:37:40.478966 Not decompressing ramdisk as can be used compressed.
18 13:37:40.479457 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 13:37:40.479818 saving as /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/ramdisk/rootfs.cpio.gz
20 13:37:40.480383 total size: 47897469 (45 MB)
21 13:37:40.744502 progress 0 % (0 MB)
22 13:37:40.764828 progress 5 % (2 MB)
23 13:37:40.784659 progress 10 % (4 MB)
24 13:37:40.797862 progress 15 % (6 MB)
25 13:37:40.810376 progress 20 % (9 MB)
26 13:37:40.822540 progress 25 % (11 MB)
27 13:37:40.834693 progress 30 % (13 MB)
28 13:37:40.847203 progress 35 % (16 MB)
29 13:37:40.859571 progress 40 % (18 MB)
30 13:37:40.871885 progress 45 % (20 MB)
31 13:37:40.884399 progress 50 % (22 MB)
32 13:37:40.896976 progress 55 % (25 MB)
33 13:37:40.909813 progress 60 % (27 MB)
34 13:37:40.922647 progress 65 % (29 MB)
35 13:37:40.935846 progress 70 % (32 MB)
36 13:37:40.949155 progress 75 % (34 MB)
37 13:37:40.962212 progress 80 % (36 MB)
38 13:37:40.975451 progress 85 % (38 MB)
39 13:37:40.988651 progress 90 % (41 MB)
40 13:37:41.001548 progress 95 % (43 MB)
41 13:37:41.014188 progress 100 % (45 MB)
42 13:37:41.014446 45 MB downloaded in 0.53 s (85.53 MB/s)
43 13:37:41.014612 end: 1.1.1 http-download (duration 00:00:01) [common]
45 13:37:41.014846 end: 1.1 download-retry (duration 00:00:01) [common]
46 13:37:41.014932 start: 1.2 download-retry (timeout 00:09:59) [common]
47 13:37:41.015017 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 13:37:41.015157 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:37:41.015227 saving as /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/kernel/Image
50 13:37:41.015289 total size: 54682112 (52 MB)
51 13:37:41.015355 No compression specified
52 13:37:41.016535 progress 0 % (0 MB)
53 13:37:41.030522 progress 5 % (2 MB)
54 13:37:41.044716 progress 10 % (5 MB)
55 13:37:41.058776 progress 15 % (7 MB)
56 13:37:41.072901 progress 20 % (10 MB)
57 13:37:41.087574 progress 25 % (13 MB)
58 13:37:41.102191 progress 30 % (15 MB)
59 13:37:41.116819 progress 35 % (18 MB)
60 13:37:41.131234 progress 40 % (20 MB)
61 13:37:41.145364 progress 45 % (23 MB)
62 13:37:41.160202 progress 50 % (26 MB)
63 13:37:41.174892 progress 55 % (28 MB)
64 13:37:41.189312 progress 60 % (31 MB)
65 13:37:41.203357 progress 65 % (33 MB)
66 13:37:41.217622 progress 70 % (36 MB)
67 13:37:41.231716 progress 75 % (39 MB)
68 13:37:41.245969 progress 80 % (41 MB)
69 13:37:41.260162 progress 85 % (44 MB)
70 13:37:41.274256 progress 90 % (46 MB)
71 13:37:41.288171 progress 95 % (49 MB)
72 13:37:41.301923 progress 100 % (52 MB)
73 13:37:41.302184 52 MB downloaded in 0.29 s (181.77 MB/s)
74 13:37:41.302341 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:37:41.302572 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:37:41.302659 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:37:41.302745 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:37:41.302883 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:37:41.302952 saving as /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/dtb/mt8192-asurada-spherion-r0.dtb
81 13:37:41.303014 total size: 47258 (0 MB)
82 13:37:41.303075 No compression specified
83 13:37:41.304218 progress 69 % (0 MB)
84 13:37:41.304498 progress 100 % (0 MB)
85 13:37:41.304663 0 MB downloaded in 0.00 s (27.36 MB/s)
86 13:37:41.304788 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:37:41.305010 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:37:41.305096 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:37:41.305193 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:37:41.305318 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:37:41.305386 saving as /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/modules/modules.tar
93 13:37:41.305447 total size: 8607916 (8 MB)
94 13:37:41.305509 Using unxz to decompress xz
95 13:37:41.309460 progress 0 % (0 MB)
96 13:37:41.329575 progress 5 % (0 MB)
97 13:37:41.355384 progress 10 % (0 MB)
98 13:37:41.382503 progress 15 % (1 MB)
99 13:37:41.409090 progress 20 % (1 MB)
100 13:37:41.436292 progress 25 % (2 MB)
101 13:37:41.462921 progress 30 % (2 MB)
102 13:37:41.487939 progress 35 % (2 MB)
103 13:37:41.515805 progress 40 % (3 MB)
104 13:37:41.542115 progress 45 % (3 MB)
105 13:37:41.568111 progress 50 % (4 MB)
106 13:37:41.594812 progress 55 % (4 MB)
107 13:37:41.621008 progress 60 % (4 MB)
108 13:37:41.646323 progress 65 % (5 MB)
109 13:37:41.673962 progress 70 % (5 MB)
110 13:37:41.701769 progress 75 % (6 MB)
111 13:37:41.725465 progress 80 % (6 MB)
112 13:37:41.749407 progress 85 % (7 MB)
113 13:37:41.773398 progress 90 % (7 MB)
114 13:37:41.802921 progress 95 % (7 MB)
115 13:37:41.831312 progress 100 % (8 MB)
116 13:37:41.837075 8 MB downloaded in 0.53 s (15.44 MB/s)
117 13:37:41.837331 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:37:41.837600 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:37:41.837709 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:37:41.837834 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:37:41.837953 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:37:41.838081 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:37:41.838372 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep
125 13:37:41.838547 makedir: /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin
126 13:37:41.838688 makedir: /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/tests
127 13:37:41.838822 makedir: /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/results
128 13:37:41.838959 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-add-keys
129 13:37:41.839108 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-add-sources
130 13:37:41.839248 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-background-process-start
131 13:37:41.839417 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-background-process-stop
132 13:37:41.839581 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-common-functions
133 13:37:41.839745 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-echo-ipv4
134 13:37:41.839889 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-install-packages
135 13:37:41.840018 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-installed-packages
136 13:37:41.840146 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-os-build
137 13:37:41.840272 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-probe-channel
138 13:37:41.840421 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-probe-ip
139 13:37:41.840550 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-target-ip
140 13:37:41.840691 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-target-mac
141 13:37:41.840818 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-target-storage
142 13:37:41.840967 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-case
143 13:37:41.841098 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-event
144 13:37:41.841229 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-feedback
145 13:37:41.841369 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-raise
146 13:37:41.841501 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-reference
147 13:37:41.841629 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-runner
148 13:37:41.841756 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-set
149 13:37:41.841896 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-test-shell
150 13:37:41.842030 Updating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-install-packages (oe)
151 13:37:41.842186 Updating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/bin/lava-installed-packages (oe)
152 13:37:41.842314 Creating /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/environment
153 13:37:41.842428 LAVA metadata
154 13:37:41.842505 - LAVA_JOB_ID=14063039
155 13:37:41.842572 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:37:41.842678 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:37:41.842748 skipped lava-vland-overlay
158 13:37:41.842824 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:37:41.842916 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:37:41.842989 skipped lava-multinode-overlay
161 13:37:41.843064 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:37:41.843150 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:37:41.843228 Loading test definitions
164 13:37:41.843323 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:37:41.843415 Using /lava-14063039 at stage 0
166 13:37:41.843734 uuid=14063039_1.5.2.3.1 testdef=None
167 13:37:41.843824 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:37:41.843922 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:37:41.845157 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:37:41.845388 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:37:41.846043 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:37:41.846279 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:37:41.846909 runner path: /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/0/tests/0_igt-gpu-panfrost test_uuid 14063039_1.5.2.3.1
176 13:37:41.847084 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:37:41.847302 Creating lava-test-runner.conf files
179 13:37:41.847368 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063039/lava-overlay-qpplu2ep/lava-14063039/0 for stage 0
180 13:37:41.847461 - 0_igt-gpu-panfrost
181 13:37:41.847577 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:37:41.847683 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:37:41.854893 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:37:41.855046 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:37:41.855137 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:37:41.855238 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:37:41.855329 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:37:43.659098 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 13:37:43.659546 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 13:37:43.659657 extracting modules file /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063039/extract-overlay-ramdisk-ec95dz6p/ramdisk
191 13:37:43.889079 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:37:43.889255 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:37:43.889347 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063039/compress-overlay-26rfch5r/overlay-1.5.2.4.tar.gz to ramdisk
194 13:37:43.889422 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063039/compress-overlay-26rfch5r/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063039/extract-overlay-ramdisk-ec95dz6p/ramdisk
195 13:37:43.896433 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:37:43.896611 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:37:43.896710 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:37:43.896800 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:37:43.896885 Building ramdisk /var/lib/lava/dispatcher/tmp/14063039/extract-overlay-ramdisk-ec95dz6p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063039/extract-overlay-ramdisk-ec95dz6p/ramdisk
200 13:37:45.026290 >> 465919 blocks
201 13:37:51.443824 rename /var/lib/lava/dispatcher/tmp/14063039/extract-overlay-ramdisk-ec95dz6p/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/ramdisk/ramdisk.cpio.gz
202 13:37:51.444290 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 13:37:51.444410 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 13:37:51.444521 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 13:37:51.444678 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/kernel/Image']
206 13:38:05.866106 Returned 0 in 14 seconds
207 13:38:05.966727 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/kernel/image.itb
208 13:38:06.802188 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:38:06.802559 output: Created: Tue May 28 14:38:06 2024
210 13:38:06.802660 output: Image 0 (kernel-1)
211 13:38:06.802746 output: Description:
212 13:38:06.802832 output: Created: Tue May 28 14:38:06 2024
213 13:38:06.802917 output: Type: Kernel Image
214 13:38:06.802999 output: Compression: lzma compressed
215 13:38:06.803087 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:38:06.803189 output: Architecture: AArch64
217 13:38:06.803298 output: OS: Linux
218 13:38:06.803401 output: Load Address: 0x00000000
219 13:38:06.803503 output: Entry Point: 0x00000000
220 13:38:06.803606 output: Hash algo: crc32
221 13:38:06.803706 output: Hash value: 0578ee26
222 13:38:06.803802 output: Image 1 (fdt-1)
223 13:38:06.803915 output: Description: mt8192-asurada-spherion-r0
224 13:38:06.804021 output: Created: Tue May 28 14:38:06 2024
225 13:38:06.804115 output: Type: Flat Device Tree
226 13:38:06.804219 output: Compression: uncompressed
227 13:38:06.804313 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:38:06.804406 output: Architecture: AArch64
229 13:38:06.804504 output: Hash algo: crc32
230 13:38:06.804635 output: Hash value: 0f8e4d2e
231 13:38:06.804728 output: Image 2 (ramdisk-1)
232 13:38:06.804829 output: Description: unavailable
233 13:38:06.804921 output: Created: Tue May 28 14:38:06 2024
234 13:38:06.805014 output: Type: RAMDisk Image
235 13:38:06.805113 output: Compression: Unknown Compression
236 13:38:06.805206 output: Data Size: 60986433 Bytes = 59557.06 KiB = 58.16 MiB
237 13:38:06.805299 output: Architecture: AArch64
238 13:38:06.805397 output: OS: Linux
239 13:38:06.805489 output: Load Address: unavailable
240 13:38:06.805581 output: Entry Point: unavailable
241 13:38:06.805679 output: Hash algo: crc32
242 13:38:06.805771 output: Hash value: 42c730ac
243 13:38:06.805863 output: Default Configuration: 'conf-1'
244 13:38:06.805961 output: Configuration 0 (conf-1)
245 13:38:06.806053 output: Description: mt8192-asurada-spherion-r0
246 13:38:06.806144 output: Kernel: kernel-1
247 13:38:06.806242 output: Init Ramdisk: ramdisk-1
248 13:38:06.806334 output: FDT: fdt-1
249 13:38:06.806426 output: Loadables: kernel-1
250 13:38:06.806524 output:
251 13:38:06.806787 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:38:06.806924 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:38:06.807073 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 13:38:06.807209 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 13:38:06.807337 No LXC device requested
256 13:38:06.807518 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:38:06.807655 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 13:38:06.807775 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:38:06.807889 Checking files for TFTP limit of 4294967296 bytes.
260 13:38:06.808595 end: 1 tftp-deploy (duration 00:00:26) [common]
261 13:38:06.808757 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:38:06.808897 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:38:06.809075 substitutions:
264 13:38:06.809186 - {DTB}: 14063039/tftp-deploy-e4u_78p6/dtb/mt8192-asurada-spherion-r0.dtb
265 13:38:06.809289 - {INITRD}: 14063039/tftp-deploy-e4u_78p6/ramdisk/ramdisk.cpio.gz
266 13:38:06.809395 - {KERNEL}: 14063039/tftp-deploy-e4u_78p6/kernel/Image
267 13:38:06.809493 - {LAVA_MAC}: None
268 13:38:06.809575 - {PRESEED_CONFIG}: None
269 13:38:06.809650 - {PRESEED_LOCAL}: None
270 13:38:06.809726 - {RAMDISK}: 14063039/tftp-deploy-e4u_78p6/ramdisk/ramdisk.cpio.gz
271 13:38:06.809827 - {ROOT_PART}: None
272 13:38:06.809924 - {ROOT}: None
273 13:38:06.810019 - {SERVER_IP}: 192.168.201.1
274 13:38:06.810120 - {TEE}: None
275 13:38:06.810214 Parsed boot commands:
276 13:38:06.810312 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:38:06.810550 Parsed boot commands: tftpboot 192.168.201.1 14063039/tftp-deploy-e4u_78p6/kernel/image.itb 14063039/tftp-deploy-e4u_78p6/kernel/cmdline
278 13:38:06.810680 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:38:06.810819 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:38:06.810953 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:38:06.811090 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:38:06.811200 Not connected, no need to disconnect.
283 13:38:06.811326 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:38:06.811447 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:38:06.811559 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 13:38:06.815458 Setting prompt string to ['lava-test: # ']
287 13:38:06.815877 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:38:06.816007 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:38:06.816140 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:38:06.816253 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:38:06.816608 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
292 13:38:11.949915 >> Command sent successfully.
293 13:38:11.952141 Returned 0 in 5 seconds
294 13:38:12.052502 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:38:12.052931 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:38:12.053056 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:38:12.053180 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:38:12.053283 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:38:12.053401 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:38:12.053985 [Enter `^Ec?' for help]
302 13:38:12.227446
303 13:38:12.227600
304 13:38:12.227711 F0: 102B 0000
305 13:38:12.227804
306 13:38:12.227884 F3: 1001 0000 [0200]
307 13:38:12.227966
308 13:38:12.230681 F3: 1001 0000
309 13:38:12.230795
310 13:38:12.230905 F7: 102D 0000
311 13:38:12.230987
312 13:38:12.231086 F1: 0000 0000
313 13:38:12.231192
314 13:38:12.234777 V0: 0000 0000 [0001]
315 13:38:12.234907
316 13:38:12.235006 00: 0007 8000
317 13:38:12.235105
318 13:38:12.238067 01: 0000 0000
319 13:38:12.238146
320 13:38:12.238210 BP: 0C00 0209 [0000]
321 13:38:12.238271
322 13:38:12.242091 G0: 1182 0000
323 13:38:12.242167
324 13:38:12.242233 EC: 0000 0021 [4000]
325 13:38:12.242330
326 13:38:12.245395 S7: 0000 0000 [0000]
327 13:38:12.245468
328 13:38:12.245529 CC: 0000 0000 [0001]
329 13:38:12.245588
330 13:38:12.249171 T0: 0000 0040 [010F]
331 13:38:12.249259
332 13:38:12.249326 Jump to BL
333 13:38:12.249388
334 13:38:12.274091
335 13:38:12.274223
336 13:38:12.281049 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:38:12.284386 ARM64: Exception handlers installed.
338 13:38:12.288241 ARM64: Testing exception
339 13:38:12.291701 ARM64: Done test exception
340 13:38:12.299122 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:38:12.309505 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:38:12.316750 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:38:12.326333 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:38:12.333364 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:38:12.339610 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:38:12.350427 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:38:12.356994 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:38:12.376866 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:38:12.380071 WDT: Last reset was cold boot
350 13:38:12.383459 SPI1(PAD0) initialized at 2873684 Hz
351 13:38:12.386625 SPI5(PAD0) initialized at 992727 Hz
352 13:38:12.389951 VBOOT: Loading verstage.
353 13:38:12.396526 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:38:12.400281 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:38:12.403660 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:38:12.406503 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:38:12.413894 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:38:12.421080 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:38:12.432107 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
360 13:38:12.432192
361 13:38:12.432258
362 13:38:12.441814 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:38:12.445032 ARM64: Exception handlers installed.
364 13:38:12.448294 ARM64: Testing exception
365 13:38:12.448406 ARM64: Done test exception
366 13:38:12.456158 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:38:12.459181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:38:12.473054 Probing TPM: . done!
369 13:38:12.473141 TPM ready after 0 ms
370 13:38:12.479326 Connected to device vid:did:rid of 1ae0:0028:00
371 13:38:12.486564 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:38:12.527532 Initialized TPM device CR50 revision 0
373 13:38:12.539218 tlcl_send_startup: Startup return code is 0
374 13:38:12.539312 TPM: setup succeeded
375 13:38:12.551104 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:38:12.559762 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:38:12.572360 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:38:12.580315 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:38:12.583638 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:38:12.587683 in-header: 03 07 00 00 08 00 00 00
381 13:38:12.590856 in-data: aa e4 47 04 13 02 00 00
382 13:38:12.594238 Chrome EC: UHEPI supported
383 13:38:12.601377 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:38:12.605437 in-header: 03 9d 00 00 08 00 00 00
385 13:38:12.609003 in-data: 10 20 20 08 00 00 00 00
386 13:38:12.609085 Phase 1
387 13:38:12.612295 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:38:12.619915 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:38:12.627596 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 13:38:12.627681 Recovery requested (1009000e)
391 13:38:12.636478 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:38:12.641458 tlcl_extend: response is 0
393 13:38:12.649980 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:38:12.655246 tlcl_extend: response is 0
395 13:38:12.661922 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:38:12.682743 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 13:38:12.690161 BS: bootblock times (exec / console): total (unknown) / 149 ms
398 13:38:12.690271
399 13:38:12.690365
400 13:38:12.697421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:38:12.701355 ARM64: Exception handlers installed.
402 13:38:12.704894 ARM64: Testing exception
403 13:38:12.707880 ARM64: Done test exception
404 13:38:12.728257 pmic_efuse_setting: Set efuses in 11 msecs
405 13:38:12.732194 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:38:12.735767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:38:12.743362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:38:12.746583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:38:12.750445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:38:12.758041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:38:12.762008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:38:12.766014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:38:12.769534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:38:12.776114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:38:12.779210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:38:12.786136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:38:12.789411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:38:12.792540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:38:12.799313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:38:12.805902 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:38:12.812783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:38:12.815783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:38:12.822375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:38:12.829496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:38:12.833395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:38:12.840788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:38:12.844675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:38:12.851224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:38:12.854540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:38:12.861570 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:38:12.868316 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:38:12.871729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:38:12.877840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:38:12.881908 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:38:12.885201 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:38:12.892800 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:38:12.896845 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:38:12.900437 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:38:12.908156 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:38:12.911540 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:38:12.918263 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:38:12.922192 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:38:12.925454 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:38:12.931996 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:38:12.935614 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:38:12.939028 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:38:12.945184 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:38:12.948507 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:38:12.952389 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:38:12.958495 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:38:12.961844 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:38:12.965370 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:38:12.968673 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:38:12.975049 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:38:12.978420 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:38:12.981745 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:38:12.992212 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 13:38:12.998821 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:38:13.001984 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:38:13.012421 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:38:13.018464 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:38:13.025154 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:38:13.029011 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:38:13.032212 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:38:13.040233 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2d
466 13:38:13.047105 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 13:38:13.050432 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 13:38:13.053729 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:38:13.064974 [RTC]rtc_get_frequency_meter,154: input=15, output=793
470 13:38:13.068390 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 13:38:13.074970 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 13:38:13.078170 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
473 13:38:13.081362 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 13:38:13.085106 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
475 13:38:13.088282 ADC[4]: Raw value=898520 ID=7
476 13:38:13.091881 ADC[3]: Raw value=212700 ID=1
477 13:38:13.091996 RAM Code: 0x71
478 13:38:13.098493 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 13:38:13.101855 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 13:38:13.112325 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 13:38:13.119472 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 13:38:13.122790 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 13:38:13.126233 in-header: 03 07 00 00 08 00 00 00
484 13:38:13.128832 in-data: aa e4 47 04 13 02 00 00
485 13:38:13.128921 Chrome EC: UHEPI supported
486 13:38:13.136882 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 13:38:13.140308 in-header: 03 d5 00 00 08 00 00 00
488 13:38:13.144002 in-data: 98 20 60 08 00 00 00 00
489 13:38:13.147698 MRC: failed to locate region type 0.
490 13:38:13.154577 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 13:38:13.158397 DRAM-K: Running full calibration
492 13:38:13.161617 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 13:38:13.165250 header.status = 0x0
494 13:38:13.167958 header.version = 0x6 (expected: 0x6)
495 13:38:13.171921 header.size = 0xd00 (expected: 0xd00)
496 13:38:13.172006 header.flags = 0x0
497 13:38:13.178706 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 13:38:13.197185 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
499 13:38:13.204072 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 13:38:13.207397 dram_init: ddr_geometry: 2
501 13:38:13.207502 [EMI] MDL number = 2
502 13:38:13.210805 [EMI] Get MDL freq = 0
503 13:38:13.214276 dram_init: ddr_type: 0
504 13:38:13.214357 is_discrete_lpddr4: 1
505 13:38:13.217743 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 13:38:13.217822
507 13:38:13.217903
508 13:38:13.221593 [Bian_co] ETT version 0.0.0.1
509 13:38:13.225338 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 13:38:13.225422
511 13:38:13.228843 dramc_set_vcore_voltage set vcore to 650000
512 13:38:13.232168 Read voltage for 800, 4
513 13:38:13.232273 Vio18 = 0
514 13:38:13.235618 Vcore = 650000
515 13:38:13.235728 Vdram = 0
516 13:38:13.235830 Vddq = 0
517 13:38:13.235922 Vmddr = 0
518 13:38:13.239662 dram_init: config_dvfs: 1
519 13:38:13.243010 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 13:38:13.250801 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 13:38:13.254538 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 13:38:13.257610 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 13:38:13.261381 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 13:38:13.265119 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 13:38:13.269123 MEM_TYPE=3, freq_sel=18
526 13:38:13.269225 sv_algorithm_assistance_LP4_1600
527 13:38:13.275800 ============ PULL DRAM RESETB DOWN ============
528 13:38:13.279223 ========== PULL DRAM RESETB DOWN end =========
529 13:38:13.282645 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 13:38:13.286739 ===================================
531 13:38:13.290501 LPDDR4 DRAM CONFIGURATION
532 13:38:13.290585 ===================================
533 13:38:13.294002 EX_ROW_EN[0] = 0x0
534 13:38:13.297767 EX_ROW_EN[1] = 0x0
535 13:38:13.297883 LP4Y_EN = 0x0
536 13:38:13.301149 WORK_FSP = 0x0
537 13:38:13.301232 WL = 0x2
538 13:38:13.303883 RL = 0x2
539 13:38:13.303995 BL = 0x2
540 13:38:13.307211 RPST = 0x0
541 13:38:13.307316 RD_PRE = 0x0
542 13:38:13.311248 WR_PRE = 0x1
543 13:38:13.311369 WR_PST = 0x0
544 13:38:13.314425 DBI_WR = 0x0
545 13:38:13.314530 DBI_RD = 0x0
546 13:38:13.317817 OTF = 0x1
547 13:38:13.320547 ===================================
548 13:38:13.324008 ===================================
549 13:38:13.324121 ANA top config
550 13:38:13.327274 ===================================
551 13:38:13.330741 DLL_ASYNC_EN = 0
552 13:38:13.333934 ALL_SLAVE_EN = 1
553 13:38:13.334019 NEW_RANK_MODE = 1
554 13:38:13.337075 DLL_IDLE_MODE = 1
555 13:38:13.341106 LP45_APHY_COMB_EN = 1
556 13:38:13.344568 TX_ODT_DIS = 1
557 13:38:13.347183 NEW_8X_MODE = 1
558 13:38:13.350670 ===================================
559 13:38:13.354112 ===================================
560 13:38:13.354248 data_rate = 1600
561 13:38:13.357534 CKR = 1
562 13:38:13.360813 DQ_P2S_RATIO = 8
563 13:38:13.364104 ===================================
564 13:38:13.367400 CA_P2S_RATIO = 8
565 13:38:13.370514 DQ_CA_OPEN = 0
566 13:38:13.373719 DQ_SEMI_OPEN = 0
567 13:38:13.373838 CA_SEMI_OPEN = 0
568 13:38:13.377361 CA_FULL_RATE = 0
569 13:38:13.380400 DQ_CKDIV4_EN = 1
570 13:38:13.383845 CA_CKDIV4_EN = 1
571 13:38:13.387358 CA_PREDIV_EN = 0
572 13:38:13.390674 PH8_DLY = 0
573 13:38:13.390792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 13:38:13.393886 DQ_AAMCK_DIV = 4
575 13:38:13.397004 CA_AAMCK_DIV = 4
576 13:38:13.400197 CA_ADMCK_DIV = 4
577 13:38:13.404083 DQ_TRACK_CA_EN = 0
578 13:38:13.407359 CA_PICK = 800
579 13:38:13.407474 CA_MCKIO = 800
580 13:38:13.410763 MCKIO_SEMI = 0
581 13:38:13.414129 PLL_FREQ = 3068
582 13:38:13.417524 DQ_UI_PI_RATIO = 32
583 13:38:13.421001 CA_UI_PI_RATIO = 0
584 13:38:13.423660 ===================================
585 13:38:13.427012 ===================================
586 13:38:13.430437 memory_type:LPDDR4
587 13:38:13.430550 GP_NUM : 10
588 13:38:13.433940 SRAM_EN : 1
589 13:38:13.434051 MD32_EN : 0
590 13:38:13.437333 ===================================
591 13:38:13.440712 [ANA_INIT] >>>>>>>>>>>>>>
592 13:38:13.444023 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 13:38:13.447190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 13:38:13.450394 ===================================
595 13:38:13.453867 data_rate = 1600,PCW = 0X7600
596 13:38:13.457440 ===================================
597 13:38:13.460758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 13:38:13.464029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 13:38:13.470487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 13:38:13.473648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 13:38:13.480295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 13:38:13.484713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 13:38:13.484829 [ANA_INIT] flow start
604 13:38:13.489024 [ANA_INIT] PLL >>>>>>>>
605 13:38:13.489139 [ANA_INIT] PLL <<<<<<<<
606 13:38:13.492181 [ANA_INIT] MIDPI >>>>>>>>
607 13:38:13.492292 [ANA_INIT] MIDPI <<<<<<<<
608 13:38:13.496329 [ANA_INIT] DLL >>>>>>>>
609 13:38:13.499575 [ANA_INIT] flow end
610 13:38:13.503409 ============ LP4 DIFF to SE enter ============
611 13:38:13.507488 ============ LP4 DIFF to SE exit ============
612 13:38:13.507584 [ANA_INIT] <<<<<<<<<<<<<
613 13:38:13.510907 [Flow] Enable top DCM control >>>>>
614 13:38:13.514249 [Flow] Enable top DCM control <<<<<
615 13:38:13.518212 Enable DLL master slave shuffle
616 13:38:13.522403 ==============================================================
617 13:38:13.525675 Gating Mode config
618 13:38:13.532347 ==============================================================
619 13:38:13.532490 Config description:
620 13:38:13.542665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 13:38:13.549250 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 13:38:13.552264 SELPH_MODE 0: By rank 1: By Phase
623 13:38:13.559370 ==============================================================
624 13:38:13.562230 GAT_TRACK_EN = 1
625 13:38:13.565827 RX_GATING_MODE = 2
626 13:38:13.569181 RX_GATING_TRACK_MODE = 2
627 13:38:13.572568 SELPH_MODE = 1
628 13:38:13.575861 PICG_EARLY_EN = 1
629 13:38:13.576000 VALID_LAT_VALUE = 1
630 13:38:13.582403 ==============================================================
631 13:38:13.585803 Enter into Gating configuration >>>>
632 13:38:13.589292 Exit from Gating configuration <<<<
633 13:38:13.592487 Enter into DVFS_PRE_config >>>>>
634 13:38:13.602202 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 13:38:13.605581 Exit from DVFS_PRE_config <<<<<
636 13:38:13.609306 Enter into PICG configuration >>>>
637 13:38:13.612076 Exit from PICG configuration <<<<
638 13:38:13.615442 [RX_INPUT] configuration >>>>>
639 13:38:13.619466 [RX_INPUT] configuration <<<<<
640 13:38:13.622759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 13:38:13.628715 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 13:38:13.635452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 13:38:13.642472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 13:38:13.648884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 13:38:13.655473 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 13:38:13.659401 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 13:38:13.662621 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 13:38:13.665999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 13:38:13.668768 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 13:38:13.675382 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 13:38:13.679382 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 13:38:13.682735 ===================================
653 13:38:13.685936 LPDDR4 DRAM CONFIGURATION
654 13:38:13.689369 ===================================
655 13:38:13.689457 EX_ROW_EN[0] = 0x0
656 13:38:13.692091 EX_ROW_EN[1] = 0x0
657 13:38:13.692167 LP4Y_EN = 0x0
658 13:38:13.695714 WORK_FSP = 0x0
659 13:38:13.695800 WL = 0x2
660 13:38:13.699201 RL = 0x2
661 13:38:13.699318 BL = 0x2
662 13:38:13.702539 RPST = 0x0
663 13:38:13.702627 RD_PRE = 0x0
664 13:38:13.705709 WR_PRE = 0x1
665 13:38:13.705782 WR_PST = 0x0
666 13:38:13.709334 DBI_WR = 0x0
667 13:38:13.712169 DBI_RD = 0x0
668 13:38:13.712277 OTF = 0x1
669 13:38:13.715568 ===================================
670 13:38:13.719053 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 13:38:13.722759 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 13:38:13.730195 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 13:38:13.730283 ===================================
674 13:38:13.734073 LPDDR4 DRAM CONFIGURATION
675 13:38:13.738221 ===================================
676 13:38:13.738297 EX_ROW_EN[0] = 0x10
677 13:38:13.741546 EX_ROW_EN[1] = 0x0
678 13:38:13.741630 LP4Y_EN = 0x0
679 13:38:13.745730 WORK_FSP = 0x0
680 13:38:13.745814 WL = 0x2
681 13:38:13.749180 RL = 0x2
682 13:38:13.749267 BL = 0x2
683 13:38:13.752650 RPST = 0x0
684 13:38:13.752737 RD_PRE = 0x0
685 13:38:13.756288 WR_PRE = 0x1
686 13:38:13.756392 WR_PST = 0x0
687 13:38:13.759899 DBI_WR = 0x0
688 13:38:13.759976 DBI_RD = 0x0
689 13:38:13.763086 OTF = 0x1
690 13:38:13.766680 ===================================
691 13:38:13.770001 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 13:38:13.775860 nWR fixed to 40
693 13:38:13.779311 [ModeRegInit_LP4] CH0 RK0
694 13:38:13.779400 [ModeRegInit_LP4] CH0 RK1
695 13:38:13.782971 [ModeRegInit_LP4] CH1 RK0
696 13:38:13.783048 [ModeRegInit_LP4] CH1 RK1
697 13:38:13.786450 match AC timing 13
698 13:38:13.790450 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 13:38:13.793963 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 13:38:13.798026 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 13:38:13.805031 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 13:38:13.809377 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 13:38:13.809492 [EMI DOE] emi_dcm 0
704 13:38:13.812862 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 13:38:13.817023 ==
706 13:38:13.817135 Dram Type= 6, Freq= 0, CH_0, rank 0
707 13:38:13.821001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 13:38:13.824778 ==
709 13:38:13.827739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 13:38:13.835193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 13:38:13.843169 [CA 0] Center 38 (7~69) winsize 63
712 13:38:13.847111 [CA 1] Center 38 (7~69) winsize 63
713 13:38:13.850585 [CA 2] Center 35 (5~66) winsize 62
714 13:38:13.853909 [CA 3] Center 35 (5~66) winsize 62
715 13:38:13.858293 [CA 4] Center 34 (4~65) winsize 62
716 13:38:13.861838 [CA 5] Center 34 (4~65) winsize 62
717 13:38:13.861934
718 13:38:13.865339 [CmdBusTrainingLP45] Vref(ca) range 1: 32
719 13:38:13.865421
720 13:38:13.868771 [CATrainingPosCal] consider 1 rank data
721 13:38:13.868859 u2DelayCellTimex100 = 270/100 ps
722 13:38:13.872994 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 13:38:13.876489 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
724 13:38:13.880398 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 13:38:13.884032 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
726 13:38:13.887478 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 13:38:13.891038 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
728 13:38:13.891119
729 13:38:13.894493 CA PerBit enable=1, Macro0, CA PI delay=34
730 13:38:13.897977
731 13:38:13.898063 [CBTSetCACLKResult] CA Dly = 34
732 13:38:13.901646 CS Dly: 6 (0~37)
733 13:38:13.901723 ==
734 13:38:13.905112 Dram Type= 6, Freq= 0, CH_0, rank 1
735 13:38:13.908522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 13:38:13.908612 ==
737 13:38:13.916116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 13:38:13.919574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 13:38:13.929326 [CA 0] Center 38 (7~69) winsize 63
740 13:38:13.933031 [CA 1] Center 38 (7~69) winsize 63
741 13:38:13.937028 [CA 2] Center 35 (5~66) winsize 62
742 13:38:13.940690 [CA 3] Center 35 (5~66) winsize 62
743 13:38:13.944221 [CA 4] Center 34 (4~65) winsize 62
744 13:38:13.947669 [CA 5] Center 34 (4~65) winsize 62
745 13:38:13.947789
746 13:38:13.951505 [CmdBusTrainingLP45] Vref(ca) range 1: 32
747 13:38:13.951630
748 13:38:13.955176 [CATrainingPosCal] consider 2 rank data
749 13:38:13.955308 u2DelayCellTimex100 = 270/100 ps
750 13:38:13.958929 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 13:38:13.962867 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
752 13:38:13.966385 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 13:38:13.970509 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
754 13:38:13.974055 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 13:38:13.977622 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 13:38:13.977744
757 13:38:13.980990 CA PerBit enable=1, Macro0, CA PI delay=34
758 13:38:13.981112
759 13:38:13.984395 [CBTSetCACLKResult] CA Dly = 34
760 13:38:13.988459 CS Dly: 6 (0~38)
761 13:38:13.988586
762 13:38:13.992391 ----->DramcWriteLeveling(PI) begin...
763 13:38:13.992508 ==
764 13:38:13.996147 Dram Type= 6, Freq= 0, CH_0, rank 0
765 13:38:13.999456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 13:38:13.999577 ==
767 13:38:14.003410 Write leveling (Byte 0): 31 => 31
768 13:38:14.003529 Write leveling (Byte 1): 30 => 30
769 13:38:14.006774 DramcWriteLeveling(PI) end<-----
770 13:38:14.006894
771 13:38:14.006998 ==
772 13:38:14.010706 Dram Type= 6, Freq= 0, CH_0, rank 0
773 13:38:14.014608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 13:38:14.014724 ==
775 13:38:14.018131 [Gating] SW mode calibration
776 13:38:14.024822 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 13:38:14.031782 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 13:38:14.035243 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 13:38:14.037873 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 13:38:14.044851 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 13:38:14.048475 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
782 13:38:14.051717 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 13:38:14.058073 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 13:38:14.061336 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 13:38:14.065475 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 13:38:14.068739 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:38:14.075994 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:38:14.080088 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:38:14.083483 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:38:14.086953 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:38:14.093718 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:38:14.097315 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:38:14.100807 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:38:14.104054 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:38:14.110812 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:38:14.113776 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 13:38:14.117529 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
798 13:38:14.124328 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:38:14.127789 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:38:14.131213 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:38:14.137400 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:38:14.140844 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:38:14.144156 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:38:14.147764 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:38:14.154501 0 9 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
806 13:38:14.157800 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 13:38:14.160891 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 13:38:14.167868 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 13:38:14.171220 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 13:38:14.174552 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 13:38:14.181373 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:38:14.183938 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
813 13:38:14.187400 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
814 13:38:14.194392 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:38:14.197115 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:38:14.200547 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:38:14.207387 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:38:14.210766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:38:14.214022 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:38:14.220691 0 11 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
821 13:38:14.223753 0 11 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
822 13:38:14.227496 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 13:38:14.234064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 13:38:14.237329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 13:38:14.240128 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 13:38:14.247116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 13:38:14.250444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:38:14.253715 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
829 13:38:14.260579 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
830 13:38:14.264055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 13:38:14.267325 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 13:38:14.273799 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 13:38:14.277228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 13:38:14.280305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:38:14.287299 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:38:14.290607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:38:14.294068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:38:14.296851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:38:14.303820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:38:14.307174 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:38:14.309981 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:38:14.316903 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:38:14.320129 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:38:14.323528 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 13:38:14.330447 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 13:38:14.333612 Total UI for P1: 0, mck2ui 16
847 13:38:14.337037 best dqsien dly found for B0: ( 0, 14, 8)
848 13:38:14.340197 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 13:38:14.343716 Total UI for P1: 0, mck2ui 16
850 13:38:14.346638 best dqsien dly found for B1: ( 0, 14, 12)
851 13:38:14.349944 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 13:38:14.353288 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
853 13:38:14.353422
854 13:38:14.356624 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 13:38:14.360065 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
856 13:38:14.363483 [Gating] SW calibration Done
857 13:38:14.363609 ==
858 13:38:14.366917 Dram Type= 6, Freq= 0, CH_0, rank 0
859 13:38:14.370252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 13:38:14.373677 ==
861 13:38:14.373768 RX Vref Scan: 0
862 13:38:14.373846
863 13:38:14.377110 RX Vref 0 -> 0, step: 1
864 13:38:14.377214
865 13:38:14.380123 RX Delay -130 -> 252, step: 16
866 13:38:14.383706 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 13:38:14.387057 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 13:38:14.390210 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 13:38:14.393374 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
870 13:38:14.400021 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 13:38:14.403437 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 13:38:14.406665 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 13:38:14.410005 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 13:38:14.413977 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 13:38:14.416783 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 13:38:14.423408 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 13:38:14.426800 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 13:38:14.430141 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 13:38:14.433515 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 13:38:14.440441 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 13:38:14.443752 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 13:38:14.443859 ==
883 13:38:14.447175 Dram Type= 6, Freq= 0, CH_0, rank 0
884 13:38:14.450390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 13:38:14.450495 ==
886 13:38:14.450593 DQS Delay:
887 13:38:14.453486 DQS0 = 0, DQS1 = 0
888 13:38:14.453597 DQM Delay:
889 13:38:14.456993 DQM0 = 80, DQM1 = 70
890 13:38:14.457096 DQ Delay:
891 13:38:14.460324 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 13:38:14.463693 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 13:38:14.466879 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 13:38:14.470464 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 13:38:14.470578
896 13:38:14.470678
897 13:38:14.470777 ==
898 13:38:14.473663 Dram Type= 6, Freq= 0, CH_0, rank 0
899 13:38:14.477644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 13:38:14.477725 ==
901 13:38:14.477825
902 13:38:14.480988
903 13:38:14.481093 TX Vref Scan disable
904 13:38:14.484289 == TX Byte 0 ==
905 13:38:14.487577 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 13:38:14.491432 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 13:38:14.494725 == TX Byte 1 ==
908 13:38:14.497764 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 13:38:14.501209 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 13:38:14.501294 ==
911 13:38:14.504405 Dram Type= 6, Freq= 0, CH_0, rank 0
912 13:38:14.507551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 13:38:14.510864 ==
914 13:38:14.522279 TX Vref=22, minBit 1, minWin=27, winSum=435
915 13:38:14.525666 TX Vref=24, minBit 1, minWin=27, winSum=438
916 13:38:14.528934 TX Vref=26, minBit 2, minWin=27, winSum=439
917 13:38:14.532160 TX Vref=28, minBit 11, minWin=27, winSum=445
918 13:38:14.535461 TX Vref=30, minBit 2, minWin=27, winSum=440
919 13:38:14.538738 TX Vref=32, minBit 9, minWin=27, winSum=441
920 13:38:14.546164 [TxChooseVref] Worse bit 11, Min win 27, Win sum 445, Final Vref 28
921 13:38:14.546251
922 13:38:14.549546 Final TX Range 1 Vref 28
923 13:38:14.549632
924 13:38:14.549717 ==
925 13:38:14.552269 Dram Type= 6, Freq= 0, CH_0, rank 0
926 13:38:14.555682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 13:38:14.555768 ==
928 13:38:14.555836
929 13:38:14.558921
930 13:38:14.559015 TX Vref Scan disable
931 13:38:14.562322 == TX Byte 0 ==
932 13:38:14.565519 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 13:38:14.569260 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 13:38:14.572302 == TX Byte 1 ==
935 13:38:14.576333 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 13:38:14.579236 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 13:38:14.582186
938 13:38:14.582272 [DATLAT]
939 13:38:14.582339 Freq=800, CH0 RK0
940 13:38:14.582401
941 13:38:14.585857 DATLAT Default: 0xa
942 13:38:14.585973 0, 0xFFFF, sum = 0
943 13:38:14.588887 1, 0xFFFF, sum = 0
944 13:38:14.588972 2, 0xFFFF, sum = 0
945 13:38:14.592183 3, 0xFFFF, sum = 0
946 13:38:14.592289 4, 0xFFFF, sum = 0
947 13:38:14.595673 5, 0xFFFF, sum = 0
948 13:38:14.599247 6, 0xFFFF, sum = 0
949 13:38:14.599362 7, 0xFFFF, sum = 0
950 13:38:14.602293 8, 0xFFFF, sum = 0
951 13:38:14.602375 9, 0x0, sum = 1
952 13:38:14.602460 10, 0x0, sum = 2
953 13:38:14.605894 11, 0x0, sum = 3
954 13:38:14.605979 12, 0x0, sum = 4
955 13:38:14.609342 best_step = 10
956 13:38:14.609445
957 13:38:14.609512 ==
958 13:38:14.612420 Dram Type= 6, Freq= 0, CH_0, rank 0
959 13:38:14.615590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 13:38:14.615675 ==
961 13:38:14.618880 RX Vref Scan: 1
962 13:38:14.618964
963 13:38:14.619031 Set Vref Range= 32 -> 127
964 13:38:14.619092
965 13:38:14.622184 RX Vref 32 -> 127, step: 1
966 13:38:14.622267
967 13:38:14.625734 RX Delay -111 -> 252, step: 8
968 13:38:14.625822
969 13:38:14.628942 Set Vref, RX VrefLevel [Byte0]: 32
970 13:38:14.632269 [Byte1]: 32
971 13:38:14.632364
972 13:38:14.636080 Set Vref, RX VrefLevel [Byte0]: 33
973 13:38:14.638736 [Byte1]: 33
974 13:38:14.642706
975 13:38:14.642795 Set Vref, RX VrefLevel [Byte0]: 34
976 13:38:14.646063 [Byte1]: 34
977 13:38:14.650910
978 13:38:14.650995 Set Vref, RX VrefLevel [Byte0]: 35
979 13:38:14.654179 [Byte1]: 35
980 13:38:14.658194
981 13:38:14.658307 Set Vref, RX VrefLevel [Byte0]: 36
982 13:38:14.661483 [Byte1]: 36
983 13:38:14.666162
984 13:38:14.666269 Set Vref, RX VrefLevel [Byte0]: 37
985 13:38:14.669057 [Byte1]: 37
986 13:38:14.673341
987 13:38:14.673416 Set Vref, RX VrefLevel [Byte0]: 38
988 13:38:14.676905 [Byte1]: 38
989 13:38:14.680943
990 13:38:14.681019 Set Vref, RX VrefLevel [Byte0]: 39
991 13:38:14.684092 [Byte1]: 39
992 13:38:14.688931
993 13:38:14.689009 Set Vref, RX VrefLevel [Byte0]: 40
994 13:38:14.692152 [Byte1]: 40
995 13:38:14.696693
996 13:38:14.696780 Set Vref, RX VrefLevel [Byte0]: 41
997 13:38:14.699807 [Byte1]: 41
998 13:38:14.704395
999 13:38:14.704480 Set Vref, RX VrefLevel [Byte0]: 42
1000 13:38:14.707405 [Byte1]: 42
1001 13:38:14.711559
1002 13:38:14.711653 Set Vref, RX VrefLevel [Byte0]: 43
1003 13:38:14.715058 [Byte1]: 43
1004 13:38:14.719305
1005 13:38:14.719391 Set Vref, RX VrefLevel [Byte0]: 44
1006 13:38:14.722407 [Byte1]: 44
1007 13:38:14.727280
1008 13:38:14.727367 Set Vref, RX VrefLevel [Byte0]: 45
1009 13:38:14.730501 [Byte1]: 45
1010 13:38:14.734946
1011 13:38:14.735060 Set Vref, RX VrefLevel [Byte0]: 46
1012 13:38:14.738422 [Byte1]: 46
1013 13:38:14.742443
1014 13:38:14.742533 Set Vref, RX VrefLevel [Byte0]: 47
1015 13:38:14.745727 [Byte1]: 47
1016 13:38:14.750505
1017 13:38:14.750612 Set Vref, RX VrefLevel [Byte0]: 48
1018 13:38:14.753951 [Byte1]: 48
1019 13:38:14.757302
1020 13:38:14.757383 Set Vref, RX VrefLevel [Byte0]: 49
1021 13:38:14.761393 [Byte1]: 49
1022 13:38:14.765934
1023 13:38:14.766056 Set Vref, RX VrefLevel [Byte0]: 50
1024 13:38:14.768720 [Byte1]: 50
1025 13:38:14.772742
1026 13:38:14.772849 Set Vref, RX VrefLevel [Byte0]: 51
1027 13:38:14.776120 [Byte1]: 51
1028 13:38:14.780206
1029 13:38:14.780324 Set Vref, RX VrefLevel [Byte0]: 52
1030 13:38:14.783734 [Byte1]: 52
1031 13:38:14.788355
1032 13:38:14.788460 Set Vref, RX VrefLevel [Byte0]: 53
1033 13:38:14.791533 [Byte1]: 53
1034 13:38:14.795837
1035 13:38:14.795950 Set Vref, RX VrefLevel [Byte0]: 54
1036 13:38:14.799375 [Byte1]: 54
1037 13:38:14.803639
1038 13:38:14.803750 Set Vref, RX VrefLevel [Byte0]: 55
1039 13:38:14.806624 [Byte1]: 55
1040 13:38:14.811220
1041 13:38:14.811300 Set Vref, RX VrefLevel [Byte0]: 56
1042 13:38:14.814479 [Byte1]: 56
1043 13:38:14.818955
1044 13:38:14.819072 Set Vref, RX VrefLevel [Byte0]: 57
1045 13:38:14.822080 [Byte1]: 57
1046 13:38:14.826528
1047 13:38:14.826643 Set Vref, RX VrefLevel [Byte0]: 58
1048 13:38:14.829725 [Byte1]: 58
1049 13:38:14.834014
1050 13:38:14.834097 Set Vref, RX VrefLevel [Byte0]: 59
1051 13:38:14.837056 [Byte1]: 59
1052 13:38:14.841388
1053 13:38:14.841491 Set Vref, RX VrefLevel [Byte0]: 60
1054 13:38:14.845012 [Byte1]: 60
1055 13:38:14.849106
1056 13:38:14.849222 Set Vref, RX VrefLevel [Byte0]: 61
1057 13:38:14.852380 [Byte1]: 61
1058 13:38:14.857112
1059 13:38:14.857203 Set Vref, RX VrefLevel [Byte0]: 62
1060 13:38:14.860335 [Byte1]: 62
1061 13:38:14.864905
1062 13:38:14.864989 Set Vref, RX VrefLevel [Byte0]: 63
1063 13:38:14.868236 [Byte1]: 63
1064 13:38:14.872164
1065 13:38:14.872251 Set Vref, RX VrefLevel [Byte0]: 64
1066 13:38:14.875405 [Byte1]: 64
1067 13:38:14.880051
1068 13:38:14.880134 Set Vref, RX VrefLevel [Byte0]: 65
1069 13:38:14.883410 [Byte1]: 65
1070 13:38:14.887340
1071 13:38:14.887423 Set Vref, RX VrefLevel [Byte0]: 66
1072 13:38:14.890629 [Byte1]: 66
1073 13:38:14.895223
1074 13:38:14.895305 Set Vref, RX VrefLevel [Byte0]: 67
1075 13:38:14.898422 [Byte1]: 67
1076 13:38:14.903052
1077 13:38:14.903135 Set Vref, RX VrefLevel [Byte0]: 68
1078 13:38:14.906071 [Byte1]: 68
1079 13:38:14.910300
1080 13:38:14.910379 Set Vref, RX VrefLevel [Byte0]: 69
1081 13:38:14.913856 [Byte1]: 69
1082 13:38:14.918193
1083 13:38:14.918276 Set Vref, RX VrefLevel [Byte0]: 70
1084 13:38:14.921331 [Byte1]: 70
1085 13:38:14.925919
1086 13:38:14.926024 Set Vref, RX VrefLevel [Byte0]: 71
1087 13:38:14.929273 [Byte1]: 71
1088 13:38:14.933597
1089 13:38:14.933699 Set Vref, RX VrefLevel [Byte0]: 72
1090 13:38:14.936734 [Byte1]: 72
1091 13:38:14.941222
1092 13:38:14.941331 Set Vref, RX VrefLevel [Byte0]: 73
1093 13:38:14.944516 [Byte1]: 73
1094 13:38:14.948496
1095 13:38:14.948601 Set Vref, RX VrefLevel [Byte0]: 74
1096 13:38:14.951929 [Byte1]: 74
1097 13:38:14.956348
1098 13:38:14.956472 Set Vref, RX VrefLevel [Byte0]: 75
1099 13:38:14.959549 [Byte1]: 75
1100 13:38:14.963723
1101 13:38:14.963837 Set Vref, RX VrefLevel [Byte0]: 76
1102 13:38:14.967526 [Byte1]: 76
1103 13:38:14.971514
1104 13:38:14.971614 Set Vref, RX VrefLevel [Byte0]: 77
1105 13:38:14.974685 [Byte1]: 77
1106 13:38:14.979338
1107 13:38:14.979441 Set Vref, RX VrefLevel [Byte0]: 78
1108 13:38:14.982559 [Byte1]: 78
1109 13:38:14.987139
1110 13:38:14.987241 Set Vref, RX VrefLevel [Byte0]: 79
1111 13:38:14.990448 [Byte1]: 79
1112 13:38:14.994387
1113 13:38:14.994496 Final RX Vref Byte 0 = 57 to rank0
1114 13:38:14.997800 Final RX Vref Byte 1 = 59 to rank0
1115 13:38:15.001116 Final RX Vref Byte 0 = 57 to rank1
1116 13:38:15.004378 Final RX Vref Byte 1 = 59 to rank1==
1117 13:38:15.007791 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 13:38:15.014148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 13:38:15.014260 ==
1120 13:38:15.014351 DQS Delay:
1121 13:38:15.014444 DQS0 = 0, DQS1 = 0
1122 13:38:15.018075 DQM Delay:
1123 13:38:15.018151 DQM0 = 82, DQM1 = 68
1124 13:38:15.021260 DQ Delay:
1125 13:38:15.024806 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 13:38:15.024913 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1127 13:38:15.027842 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 13:38:15.031225 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1129 13:38:15.034787
1130 13:38:15.034892
1131 13:38:15.041111 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1132 13:38:15.044225 CH0 RK0: MR19=606, MR18=2928
1133 13:38:15.051238 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1134 13:38:15.051320
1135 13:38:15.054524 ----->DramcWriteLeveling(PI) begin...
1136 13:38:15.054610 ==
1137 13:38:15.058046 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 13:38:15.061319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 13:38:15.061403 ==
1140 13:38:15.064515 Write leveling (Byte 0): 31 => 31
1141 13:38:15.068365 Write leveling (Byte 1): 31 => 31
1142 13:38:15.071492 DramcWriteLeveling(PI) end<-----
1143 13:38:15.071602
1144 13:38:15.071695 ==
1145 13:38:15.074812 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 13:38:15.077989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 13:38:15.078094 ==
1148 13:38:15.081273 [Gating] SW mode calibration
1149 13:38:15.087824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 13:38:15.094623 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 13:38:15.097987 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 13:38:15.101340 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 13:38:15.108232 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 13:38:15.110892 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:38:15.114736 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:38:15.121470 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:38:15.124238 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:38:15.128119 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:38:15.134680 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:38:15.137831 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:38:15.140935 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:38:15.147750 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:38:15.151077 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:38:15.195467 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:38:15.195799 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:38:15.195882 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:38:15.195949 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:38:15.196022 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1169 13:38:15.196083 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1170 13:38:15.196149 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:38:15.196207 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:38:15.196776 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:38:15.197027 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:38:15.236143 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:38:15.236472 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:38:15.236548 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:38:15.236623 0 9 8 | B1->B0 | 2323 2f2f | 1 1 | (1 1) (1 1)
1178 13:38:15.236704 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1179 13:38:15.236768 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:38:15.236838 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:38:15.236935 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:38:15.236997 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:38:15.240366 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:38:15.243737 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1185 13:38:15.246995 0 10 8 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (0 0)
1186 13:38:15.250214 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1187 13:38:15.256952 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:38:15.260361 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:38:15.263515 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:38:15.270153 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:38:15.273690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:38:15.276756 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1193 13:38:15.283517 0 11 8 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
1194 13:38:15.286827 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1195 13:38:15.290208 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:38:15.297342 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:38:15.300741 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:38:15.303311 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:38:15.310696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:38:15.314771 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:38:15.318016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 13:38:15.322003 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:38:15.325381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:38:15.332079 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:38:15.336135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:38:15.339524 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:38:15.342821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:38:15.349246 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:38:15.352408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:38:15.355705 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:38:15.362357 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:38:15.366066 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:38:15.369045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:38:15.376161 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:38:15.379148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:38:15.382918 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 13:38:15.389470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 13:38:15.392683 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:38:15.395834 Total UI for P1: 0, mck2ui 16
1220 13:38:15.399106 best dqsien dly found for B0: ( 0, 14, 6)
1221 13:38:15.402352 Total UI for P1: 0, mck2ui 16
1222 13:38:15.406143 best dqsien dly found for B1: ( 0, 14, 8)
1223 13:38:15.409359 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1224 13:38:15.412662 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 13:38:15.412743
1226 13:38:15.415954 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 13:38:15.419308 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 13:38:15.422636 [Gating] SW calibration Done
1229 13:38:15.422711 ==
1230 13:38:15.426228 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 13:38:15.429261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 13:38:15.429338 ==
1233 13:38:15.432647 RX Vref Scan: 0
1234 13:38:15.432719
1235 13:38:15.432780 RX Vref 0 -> 0, step: 1
1236 13:38:15.435863
1237 13:38:15.435937 RX Delay -130 -> 252, step: 16
1238 13:38:15.442400 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1239 13:38:15.445727 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1240 13:38:15.448909 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1241 13:38:15.452725 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1242 13:38:15.455558 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1243 13:38:15.462809 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1244 13:38:15.466060 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1245 13:38:15.468851 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 13:38:15.472769 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1247 13:38:15.475956 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 13:38:15.482110 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 13:38:15.485702 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1250 13:38:15.488978 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1251 13:38:15.492289 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1252 13:38:15.495404 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1253 13:38:15.502363 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1254 13:38:15.502496 ==
1255 13:38:15.505582 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 13:38:15.508931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 13:38:15.509027 ==
1258 13:38:15.509116 DQS Delay:
1259 13:38:15.512144 DQS0 = 0, DQS1 = 0
1260 13:38:15.512217 DQM Delay:
1261 13:38:15.515647 DQM0 = 76, DQM1 = 69
1262 13:38:15.515754 DQ Delay:
1263 13:38:15.518927 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1264 13:38:15.522448 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1265 13:38:15.525815 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1266 13:38:15.529154 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1267 13:38:15.529264
1268 13:38:15.529328
1269 13:38:15.529386 ==
1270 13:38:15.532337 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 13:38:15.535716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 13:38:15.535797 ==
1273 13:38:15.535860
1274 13:38:15.538922
1275 13:38:15.539016 TX Vref Scan disable
1276 13:38:15.542189 == TX Byte 0 ==
1277 13:38:15.546195 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 13:38:15.549415 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 13:38:15.552771 == TX Byte 1 ==
1280 13:38:15.555881 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1281 13:38:15.559123 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1282 13:38:15.559233 ==
1283 13:38:15.562388 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 13:38:15.568999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 13:38:15.569080 ==
1286 13:38:15.580807 TX Vref=22, minBit 11, minWin=26, winSum=433
1287 13:38:15.584047 TX Vref=24, minBit 13, minWin=26, winSum=438
1288 13:38:15.587178 TX Vref=26, minBit 11, minWin=26, winSum=438
1289 13:38:15.590338 TX Vref=28, minBit 1, minWin=27, winSum=442
1290 13:38:15.593922 TX Vref=30, minBit 1, minWin=27, winSum=442
1291 13:38:15.600843 TX Vref=32, minBit 11, minWin=26, winSum=443
1292 13:38:15.604039 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
1293 13:38:15.604123
1294 13:38:15.607153 Final TX Range 1 Vref 28
1295 13:38:15.607236
1296 13:38:15.607299 ==
1297 13:38:15.610783 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 13:38:15.614055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 13:38:15.614141 ==
1300 13:38:15.617265
1301 13:38:15.617347
1302 13:38:15.617411 TX Vref Scan disable
1303 13:38:15.620505 == TX Byte 0 ==
1304 13:38:15.624191 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 13:38:15.627195 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 13:38:15.630527 == TX Byte 1 ==
1307 13:38:15.633891 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1308 13:38:15.637685 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1309 13:38:15.641020
1310 13:38:15.641100 [DATLAT]
1311 13:38:15.641164 Freq=800, CH0 RK1
1312 13:38:15.641265
1313 13:38:15.644417 DATLAT Default: 0xa
1314 13:38:15.644498 0, 0xFFFF, sum = 0
1315 13:38:15.647707 1, 0xFFFF, sum = 0
1316 13:38:15.647789 2, 0xFFFF, sum = 0
1317 13:38:15.650909 3, 0xFFFF, sum = 0
1318 13:38:15.654193 4, 0xFFFF, sum = 0
1319 13:38:15.654277 5, 0xFFFF, sum = 0
1320 13:38:15.657460 6, 0xFFFF, sum = 0
1321 13:38:15.657543 7, 0xFFFF, sum = 0
1322 13:38:15.660699 8, 0xFFFF, sum = 0
1323 13:38:15.660782 9, 0x0, sum = 1
1324 13:38:15.660848 10, 0x0, sum = 2
1325 13:38:15.664023 11, 0x0, sum = 3
1326 13:38:15.664106 12, 0x0, sum = 4
1327 13:38:15.667240 best_step = 10
1328 13:38:15.667320
1329 13:38:15.667384 ==
1330 13:38:15.670580 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 13:38:15.673819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 13:38:15.673901 ==
1333 13:38:15.677140 RX Vref Scan: 0
1334 13:38:15.677220
1335 13:38:15.677284 RX Vref 0 -> 0, step: 1
1336 13:38:15.677343
1337 13:38:15.680448 RX Delay -111 -> 252, step: 8
1338 13:38:15.687454 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1339 13:38:15.690892 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1340 13:38:15.694131 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1341 13:38:15.697368 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1342 13:38:15.700702 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1343 13:38:15.707294 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1344 13:38:15.711195 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1345 13:38:15.714295 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1346 13:38:15.717506 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1347 13:38:15.720721 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1348 13:38:15.727771 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1349 13:38:15.730962 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1350 13:38:15.734093 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1351 13:38:15.737344 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1352 13:38:15.741119 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1353 13:38:15.747584 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1354 13:38:15.747666 ==
1355 13:38:15.750801 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 13:38:15.754109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 13:38:15.754188 ==
1358 13:38:15.754251 DQS Delay:
1359 13:38:15.757327 DQS0 = 0, DQS1 = 0
1360 13:38:15.757398 DQM Delay:
1361 13:38:15.761163 DQM0 = 78, DQM1 = 71
1362 13:38:15.761234 DQ Delay:
1363 13:38:15.764446 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1364 13:38:15.767692 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1365 13:38:15.771136 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1366 13:38:15.774386 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1367 13:38:15.774459
1368 13:38:15.774519
1369 13:38:15.781067 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1370 13:38:15.784195 CH0 RK1: MR19=606, MR18=4924
1371 13:38:15.791205 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1372 13:38:15.794378 [RxdqsGatingPostProcess] freq 800
1373 13:38:15.800945 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 13:38:15.804277 Pre-setting of DQS Precalculation
1375 13:38:15.807477 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 13:38:15.807554 ==
1377 13:38:15.810696 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 13:38:15.814513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 13:38:15.814589 ==
1380 13:38:15.821071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 13:38:15.827653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 13:38:15.835550 [CA 0] Center 36 (6~66) winsize 61
1383 13:38:15.839387 [CA 1] Center 36 (6~67) winsize 62
1384 13:38:15.842716 [CA 2] Center 34 (5~64) winsize 60
1385 13:38:15.845844 [CA 3] Center 34 (4~64) winsize 61
1386 13:38:15.848866 [CA 4] Center 34 (4~64) winsize 61
1387 13:38:15.852593 [CA 5] Center 34 (4~64) winsize 61
1388 13:38:15.852693
1389 13:38:15.855650 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 13:38:15.855734
1391 13:38:15.859176 [CATrainingPosCal] consider 1 rank data
1392 13:38:15.862596 u2DelayCellTimex100 = 270/100 ps
1393 13:38:15.865764 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1394 13:38:15.872352 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 13:38:15.875550 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1396 13:38:15.878895 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 13:38:15.882219 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 13:38:15.885475 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 13:38:15.885556
1400 13:38:15.888735 CA PerBit enable=1, Macro0, CA PI delay=34
1401 13:38:15.888815
1402 13:38:15.892515 [CBTSetCACLKResult] CA Dly = 34
1403 13:38:15.892631 CS Dly: 5 (0~36)
1404 13:38:15.895771 ==
1405 13:38:15.899101 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 13:38:15.901871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 13:38:15.902011 ==
1408 13:38:15.905187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 13:38:15.911838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 13:38:15.922060 [CA 0] Center 36 (6~67) winsize 62
1411 13:38:15.925324 [CA 1] Center 36 (6~67) winsize 62
1412 13:38:15.928700 [CA 2] Center 35 (5~65) winsize 61
1413 13:38:15.931723 [CA 3] Center 33 (3~64) winsize 62
1414 13:38:15.934887 [CA 4] Center 34 (4~65) winsize 62
1415 13:38:15.938589 [CA 5] Center 34 (4~64) winsize 61
1416 13:38:15.938687
1417 13:38:15.941840 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 13:38:15.941922
1419 13:38:15.945332 [CATrainingPosCal] consider 2 rank data
1420 13:38:15.948823 u2DelayCellTimex100 = 270/100 ps
1421 13:38:15.952210 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1422 13:38:15.954981 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 13:38:15.962075 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1424 13:38:15.964814 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 13:38:15.969033 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 13:38:15.972151 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 13:38:15.972265
1428 13:38:15.976494 CA PerBit enable=1, Macro0, CA PI delay=34
1429 13:38:15.976643
1430 13:38:15.979899 [CBTSetCACLKResult] CA Dly = 34
1431 13:38:15.980005 CS Dly: 6 (0~38)
1432 13:38:15.980105
1433 13:38:15.983804 ----->DramcWriteLeveling(PI) begin...
1434 13:38:15.983913 ==
1435 13:38:15.987275 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 13:38:15.991390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 13:38:15.991500 ==
1438 13:38:15.994699 Write leveling (Byte 0): 29 => 29
1439 13:38:15.998046 Write leveling (Byte 1): 29 => 29
1440 13:38:16.001756 DramcWriteLeveling(PI) end<-----
1441 13:38:16.001839
1442 13:38:16.001907 ==
1443 13:38:16.005108 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 13:38:16.008638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 13:38:16.008723 ==
1446 13:38:16.011915 [Gating] SW mode calibration
1447 13:38:16.018426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 13:38:16.021679 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 13:38:16.028328 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 13:38:16.031495 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 13:38:16.035106 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1452 13:38:16.041513 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:38:16.045363 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:38:16.048539 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:38:16.055331 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:38:16.058796 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:38:16.062084 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:38:16.068635 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:38:16.071972 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:38:16.075162 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:38:16.081504 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:38:16.085103 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:38:16.088292 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:38:16.094808 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:38:16.098168 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:38:16.102070 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 13:38:16.104773 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1468 13:38:16.111833 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:38:16.115105 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:38:16.118464 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:38:16.125003 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:38:16.128126 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:38:16.132048 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:38:16.138373 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:38:16.141721 0 9 8 | B1->B0 | 2727 2525 | 1 1 | (1 1) (1 1)
1476 13:38:16.144945 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:38:16.151630 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:38:16.155280 0 9 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1479 13:38:16.158284 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:38:16.164676 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:38:16.168151 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:38:16.171420 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1483 13:38:16.178682 0 10 8 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
1484 13:38:16.181780 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:38:16.185029 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:38:16.191613 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:38:16.195237 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:38:16.198612 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:38:16.205230 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:38:16.208361 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:38:16.211729 0 11 8 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
1492 13:38:16.215044 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:38:16.222052 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:38:16.224766 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:38:16.228175 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:38:16.235274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:38:16.238253 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:38:16.242105 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 13:38:16.248767 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:38:16.251562 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:38:16.255039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:38:16.261813 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:38:16.265086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:38:16.268422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:38:16.274901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:38:16.278265 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:38:16.281514 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:38:16.288514 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:38:16.291876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:38:16.294989 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:38:16.301483 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:38:16.304796 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:38:16.308105 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:38:16.314705 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:38:16.318018 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 13:38:16.321416 Total UI for P1: 0, mck2ui 16
1517 13:38:16.324717 best dqsien dly found for B0: ( 0, 14, 6)
1518 13:38:16.328165 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 13:38:16.331586 Total UI for P1: 0, mck2ui 16
1520 13:38:16.335017 best dqsien dly found for B1: ( 0, 14, 8)
1521 13:38:16.338287 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 13:38:16.341639 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1523 13:38:16.341716
1524 13:38:16.344846 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 13:38:16.348098 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 13:38:16.351587 [Gating] SW calibration Done
1527 13:38:16.351672 ==
1528 13:38:16.354943 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 13:38:16.361757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 13:38:16.361867 ==
1531 13:38:16.361969 RX Vref Scan: 0
1532 13:38:16.362072
1533 13:38:16.365065 RX Vref 0 -> 0, step: 1
1534 13:38:16.365168
1535 13:38:16.367818 RX Delay -130 -> 252, step: 16
1536 13:38:16.371174 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1537 13:38:16.374415 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1538 13:38:16.378105 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1539 13:38:16.381348 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1540 13:38:16.388099 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1541 13:38:16.391358 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1542 13:38:16.394694 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1543 13:38:16.397924 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1544 13:38:16.401110 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1545 13:38:16.408296 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1546 13:38:16.411513 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1547 13:38:16.414665 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1548 13:38:16.418076 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1549 13:38:16.421457 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1550 13:38:16.428135 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1551 13:38:16.431514 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1552 13:38:16.431600 ==
1553 13:38:16.434936 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 13:38:16.438354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 13:38:16.438458 ==
1556 13:38:16.441097 DQS Delay:
1557 13:38:16.441208 DQS0 = 0, DQS1 = 0
1558 13:38:16.441309 DQM Delay:
1559 13:38:16.444459 DQM0 = 79, DQM1 = 71
1560 13:38:16.444570 DQ Delay:
1561 13:38:16.447695 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1562 13:38:16.451129 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1563 13:38:16.454978 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1564 13:38:16.458213 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1565 13:38:16.458307
1566 13:38:16.458388
1567 13:38:16.458450 ==
1568 13:38:16.461247 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 13:38:16.468240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 13:38:16.468349 ==
1571 13:38:16.468468
1572 13:38:16.468571
1573 13:38:16.468641 TX Vref Scan disable
1574 13:38:16.471539 == TX Byte 0 ==
1575 13:38:16.475084 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1576 13:38:16.478372 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1577 13:38:16.481701 == TX Byte 1 ==
1578 13:38:16.485042 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 13:38:16.488130 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 13:38:16.491236 ==
1581 13:38:16.495210 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 13:38:16.498321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 13:38:16.498432 ==
1584 13:38:16.510450 TX Vref=22, minBit 1, minWin=26, winSum=440
1585 13:38:16.513422 TX Vref=24, minBit 1, minWin=26, winSum=440
1586 13:38:16.516676 TX Vref=26, minBit 0, minWin=27, winSum=441
1587 13:38:16.520335 TX Vref=28, minBit 5, minWin=27, winSum=447
1588 13:38:16.523551 TX Vref=30, minBit 1, minWin=28, winSum=449
1589 13:38:16.530090 TX Vref=32, minBit 0, minWin=27, winSum=444
1590 13:38:16.533330 [TxChooseVref] Worse bit 1, Min win 28, Win sum 449, Final Vref 30
1591 13:38:16.533413
1592 13:38:16.536832 Final TX Range 1 Vref 30
1593 13:38:16.536911
1594 13:38:16.536974 ==
1595 13:38:16.540312 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 13:38:16.543889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 13:38:16.543979 ==
1598 13:38:16.547225
1599 13:38:16.547303
1600 13:38:16.547385 TX Vref Scan disable
1601 13:38:16.550641 == TX Byte 0 ==
1602 13:38:16.554021 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 13:38:16.557565 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 13:38:16.560805 == TX Byte 1 ==
1605 13:38:16.563941 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 13:38:16.567275 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 13:38:16.567389
1608 13:38:16.570567 [DATLAT]
1609 13:38:16.570692 Freq=800, CH1 RK0
1610 13:38:16.570804
1611 13:38:16.574334 DATLAT Default: 0xa
1612 13:38:16.574452 0, 0xFFFF, sum = 0
1613 13:38:16.577725 1, 0xFFFF, sum = 0
1614 13:38:16.577840 2, 0xFFFF, sum = 0
1615 13:38:16.580455 3, 0xFFFF, sum = 0
1616 13:38:16.580575 4, 0xFFFF, sum = 0
1617 13:38:16.584490 5, 0xFFFF, sum = 0
1618 13:38:16.584601 6, 0xFFFF, sum = 0
1619 13:38:16.587307 7, 0xFFFF, sum = 0
1620 13:38:16.587385 8, 0xFFFF, sum = 0
1621 13:38:16.590633 9, 0x0, sum = 1
1622 13:38:16.590714 10, 0x0, sum = 2
1623 13:38:16.594065 11, 0x0, sum = 3
1624 13:38:16.594153 12, 0x0, sum = 4
1625 13:38:16.597445 best_step = 10
1626 13:38:16.597540
1627 13:38:16.597606 ==
1628 13:38:16.600930 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 13:38:16.603843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 13:38:16.603943 ==
1631 13:38:16.607137 RX Vref Scan: 1
1632 13:38:16.607218
1633 13:38:16.607283 Set Vref Range= 32 -> 127
1634 13:38:16.607353
1635 13:38:16.610444 RX Vref 32 -> 127, step: 1
1636 13:38:16.610521
1637 13:38:16.613760 RX Delay -111 -> 252, step: 8
1638 13:38:16.613840
1639 13:38:16.617231 Set Vref, RX VrefLevel [Byte0]: 32
1640 13:38:16.620344 [Byte1]: 32
1641 13:38:16.620455
1642 13:38:16.624164 Set Vref, RX VrefLevel [Byte0]: 33
1643 13:38:16.627357 [Byte1]: 33
1644 13:38:16.630468
1645 13:38:16.630547 Set Vref, RX VrefLevel [Byte0]: 34
1646 13:38:16.634214 [Byte1]: 34
1647 13:38:16.638668
1648 13:38:16.638748 Set Vref, RX VrefLevel [Byte0]: 35
1649 13:38:16.641465 [Byte1]: 35
1650 13:38:16.646228
1651 13:38:16.646304 Set Vref, RX VrefLevel [Byte0]: 36
1652 13:38:16.649709 [Byte1]: 36
1653 13:38:16.653788
1654 13:38:16.653870 Set Vref, RX VrefLevel [Byte0]: 37
1655 13:38:16.657085 [Byte1]: 37
1656 13:38:16.661298
1657 13:38:16.661382 Set Vref, RX VrefLevel [Byte0]: 38
1658 13:38:16.664708 [Byte1]: 38
1659 13:38:16.668731
1660 13:38:16.668814 Set Vref, RX VrefLevel [Byte0]: 39
1661 13:38:16.672028 [Byte1]: 39
1662 13:38:16.676828
1663 13:38:16.676911 Set Vref, RX VrefLevel [Byte0]: 40
1664 13:38:16.680003 [Byte1]: 40
1665 13:38:16.684562
1666 13:38:16.684641 Set Vref, RX VrefLevel [Byte0]: 41
1667 13:38:16.687447 [Byte1]: 41
1668 13:38:16.692063
1669 13:38:16.692147 Set Vref, RX VrefLevel [Byte0]: 42
1670 13:38:16.695508 [Byte1]: 42
1671 13:38:16.699554
1672 13:38:16.699637 Set Vref, RX VrefLevel [Byte0]: 43
1673 13:38:16.702970 [Byte1]: 43
1674 13:38:16.707106
1675 13:38:16.707188 Set Vref, RX VrefLevel [Byte0]: 44
1676 13:38:16.710929 [Byte1]: 44
1677 13:38:16.715313
1678 13:38:16.715403 Set Vref, RX VrefLevel [Byte0]: 45
1679 13:38:16.718362 [Byte1]: 45
1680 13:38:16.722210
1681 13:38:16.722293 Set Vref, RX VrefLevel [Byte0]: 46
1682 13:38:16.725645 [Byte1]: 46
1683 13:38:16.730322
1684 13:38:16.730412 Set Vref, RX VrefLevel [Byte0]: 47
1685 13:38:16.733685 [Byte1]: 47
1686 13:38:16.738099
1687 13:38:16.738183 Set Vref, RX VrefLevel [Byte0]: 48
1688 13:38:16.741271 [Byte1]: 48
1689 13:38:16.745614
1690 13:38:16.745700 Set Vref, RX VrefLevel [Byte0]: 49
1691 13:38:16.748834 [Byte1]: 49
1692 13:38:16.753432
1693 13:38:16.753516 Set Vref, RX VrefLevel [Byte0]: 50
1694 13:38:16.756167 [Byte1]: 50
1695 13:38:16.760858
1696 13:38:16.760949 Set Vref, RX VrefLevel [Byte0]: 51
1697 13:38:16.764221 [Byte1]: 51
1698 13:38:16.768429
1699 13:38:16.768540 Set Vref, RX VrefLevel [Byte0]: 52
1700 13:38:16.771613 [Byte1]: 52
1701 13:38:16.776424
1702 13:38:16.776536 Set Vref, RX VrefLevel [Byte0]: 53
1703 13:38:16.779213 [Byte1]: 53
1704 13:38:16.784090
1705 13:38:16.784176 Set Vref, RX VrefLevel [Byte0]: 54
1706 13:38:16.790217 [Byte1]: 54
1707 13:38:16.790306
1708 13:38:16.793595 Set Vref, RX VrefLevel [Byte0]: 55
1709 13:38:16.796823 [Byte1]: 55
1710 13:38:16.796908
1711 13:38:16.800056 Set Vref, RX VrefLevel [Byte0]: 56
1712 13:38:16.803467 [Byte1]: 56
1713 13:38:16.803551
1714 13:38:16.806861 Set Vref, RX VrefLevel [Byte0]: 57
1715 13:38:16.810274 [Byte1]: 57
1716 13:38:16.814435
1717 13:38:16.814543 Set Vref, RX VrefLevel [Byte0]: 58
1718 13:38:16.817811 [Byte1]: 58
1719 13:38:16.822057
1720 13:38:16.822171 Set Vref, RX VrefLevel [Byte0]: 59
1721 13:38:16.825370 [Byte1]: 59
1722 13:38:16.829979
1723 13:38:16.830090 Set Vref, RX VrefLevel [Byte0]: 60
1724 13:38:16.833062 [Byte1]: 60
1725 13:38:16.837585
1726 13:38:16.837698 Set Vref, RX VrefLevel [Byte0]: 61
1727 13:38:16.840229 [Byte1]: 61
1728 13:38:16.844914
1729 13:38:16.845017 Set Vref, RX VrefLevel [Byte0]: 62
1730 13:38:16.848051 [Byte1]: 62
1731 13:38:16.852798
1732 13:38:16.852911 Set Vref, RX VrefLevel [Byte0]: 63
1733 13:38:16.855768 [Byte1]: 63
1734 13:38:16.859992
1735 13:38:16.860077 Set Vref, RX VrefLevel [Byte0]: 64
1736 13:38:16.863164 [Byte1]: 64
1737 13:38:16.867919
1738 13:38:16.867997 Set Vref, RX VrefLevel [Byte0]: 65
1739 13:38:16.871207 [Byte1]: 65
1740 13:38:16.875315
1741 13:38:16.875419 Set Vref, RX VrefLevel [Byte0]: 66
1742 13:38:16.878474 [Byte1]: 66
1743 13:38:16.883297
1744 13:38:16.883377 Set Vref, RX VrefLevel [Byte0]: 67
1745 13:38:16.886702 [Byte1]: 67
1746 13:38:16.890781
1747 13:38:16.890866 Set Vref, RX VrefLevel [Byte0]: 68
1748 13:38:16.893943 [Byte1]: 68
1749 13:38:16.898356
1750 13:38:16.898435 Set Vref, RX VrefLevel [Byte0]: 69
1751 13:38:16.901497 [Byte1]: 69
1752 13:38:16.906116
1753 13:38:16.906197 Set Vref, RX VrefLevel [Byte0]: 70
1754 13:38:16.909439 [Byte1]: 70
1755 13:38:16.913520
1756 13:38:16.913596 Set Vref, RX VrefLevel [Byte0]: 71
1757 13:38:16.916852 [Byte1]: 71
1758 13:38:16.921142
1759 13:38:16.921230 Set Vref, RX VrefLevel [Byte0]: 72
1760 13:38:16.924351 [Byte1]: 72
1761 13:38:16.929173
1762 13:38:16.929247 Set Vref, RX VrefLevel [Byte0]: 73
1763 13:38:16.932456 [Byte1]: 73
1764 13:38:16.936505
1765 13:38:16.936611 Set Vref, RX VrefLevel [Byte0]: 74
1766 13:38:16.939705 [Byte1]: 74
1767 13:38:16.944165
1768 13:38:16.944274 Final RX Vref Byte 0 = 63 to rank0
1769 13:38:16.947376 Final RX Vref Byte 1 = 58 to rank0
1770 13:38:16.951222 Final RX Vref Byte 0 = 63 to rank1
1771 13:38:16.954529 Final RX Vref Byte 1 = 58 to rank1==
1772 13:38:16.957723 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 13:38:16.964057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 13:38:16.964142 ==
1775 13:38:16.964207 DQS Delay:
1776 13:38:16.964288 DQS0 = 0, DQS1 = 0
1777 13:38:16.967825 DQM Delay:
1778 13:38:16.967903 DQM0 = 80, DQM1 = 70
1779 13:38:16.970927 DQ Delay:
1780 13:38:16.974304 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1781 13:38:16.974413 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1782 13:38:16.977670 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1783 13:38:16.981148 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1784 13:38:16.984388
1785 13:38:16.984490
1786 13:38:16.991205 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1787 13:38:16.994675 CH1 RK0: MR19=606, MR18=1620
1788 13:38:17.001407 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1789 13:38:17.001496
1790 13:38:17.004647 ----->DramcWriteLeveling(PI) begin...
1791 13:38:17.004732 ==
1792 13:38:17.007638 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 13:38:17.011332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 13:38:17.011413 ==
1795 13:38:17.014078 Write leveling (Byte 0): 30 => 30
1796 13:38:17.017509 Write leveling (Byte 1): 30 => 30
1797 13:38:17.020860 DramcWriteLeveling(PI) end<-----
1798 13:38:17.020941
1799 13:38:17.021006 ==
1800 13:38:17.024217 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 13:38:17.027658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 13:38:17.027759 ==
1803 13:38:17.031108 [Gating] SW mode calibration
1804 13:38:17.037616 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 13:38:17.044702 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 13:38:17.048066 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 13:38:17.051336 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1808 13:38:17.057903 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 13:38:17.061195 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:38:17.064476 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:38:17.071228 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:38:17.074354 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:38:17.077711 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:38:17.084122 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:38:17.087980 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:38:17.091166 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:38:17.094522 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:38:17.101351 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:38:17.104735 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:38:17.107460 0 7 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1821 13:38:17.114238 0 7 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1822 13:38:17.117215 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:38:17.120994 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1824 13:38:17.127841 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1825 13:38:17.131211 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:38:17.133928 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:38:17.140600 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:38:17.144044 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:38:17.147260 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:38:17.153869 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1831 13:38:17.157239 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1832 13:38:17.160348 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1833 13:38:17.167418 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:38:17.170743 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:38:17.174005 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:38:17.180684 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:38:17.184111 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 13:38:17.187409 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:38:17.193968 0 10 4 | B1->B0 | 3232 2a2a | 1 0 | (0 0) (0 1)
1840 13:38:17.197298 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1841 13:38:17.200399 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:38:17.207133 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:38:17.210767 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:38:17.214131 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:38:17.217683 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:38:17.224236 0 11 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1847 13:38:17.227320 0 11 4 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (1 1)
1848 13:38:17.231172 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1849 13:38:17.237820 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:38:17.241328 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:38:17.244652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 13:38:17.250830 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:38:17.254382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:38:17.257869 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:38:17.264394 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1856 13:38:17.267378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:38:17.271164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:38:17.277552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:38:17.280913 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:38:17.284456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:38:17.291272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:38:17.293992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:38:17.297950 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:38:17.304305 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:38:17.307490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:38:17.310524 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:38:17.314175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:38:17.320801 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:38:17.324059 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:38:17.327473 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:38:17.333982 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1872 13:38:17.337694 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 13:38:17.341088 Total UI for P1: 0, mck2ui 16
1874 13:38:17.344406 best dqsien dly found for B0: ( 0, 14, 4)
1875 13:38:17.347734 Total UI for P1: 0, mck2ui 16
1876 13:38:17.351128 best dqsien dly found for B1: ( 0, 14, 6)
1877 13:38:17.353865 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1878 13:38:17.357697 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1879 13:38:17.357786
1880 13:38:17.360866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1881 13:38:17.364069 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1882 13:38:17.367278 [Gating] SW calibration Done
1883 13:38:17.367361 ==
1884 13:38:17.371065 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 13:38:17.374109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 13:38:17.377247 ==
1887 13:38:17.377332 RX Vref Scan: 0
1888 13:38:17.377399
1889 13:38:17.381178 RX Vref 0 -> 0, step: 1
1890 13:38:17.381263
1891 13:38:17.384155 RX Delay -130 -> 252, step: 16
1892 13:38:17.387273 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1893 13:38:17.391027 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1894 13:38:17.394085 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1895 13:38:17.397374 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1896 13:38:17.400679 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1897 13:38:17.407332 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1898 13:38:17.410523 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1899 13:38:17.413889 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1900 13:38:17.417169 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1901 13:38:17.420909 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1902 13:38:17.427259 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1903 13:38:17.430737 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1904 13:38:17.434075 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1905 13:38:17.437358 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1906 13:38:17.443817 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1907 13:38:17.447775 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1908 13:38:17.447897 ==
1909 13:38:17.450475 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 13:38:17.453875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 13:38:17.453961 ==
1912 13:38:17.454027 DQS Delay:
1913 13:38:17.457224 DQS0 = 0, DQS1 = 0
1914 13:38:17.457348 DQM Delay:
1915 13:38:17.460446 DQM0 = 76, DQM1 = 71
1916 13:38:17.460550 DQ Delay:
1917 13:38:17.464354 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1918 13:38:17.467638 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1919 13:38:17.470417 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1920 13:38:17.473752 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1921 13:38:17.473839
1922 13:38:17.473932
1923 13:38:17.473999 ==
1924 13:38:17.477061 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 13:38:17.480787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 13:38:17.483837 ==
1927 13:38:17.483946
1928 13:38:17.484044
1929 13:38:17.484112 TX Vref Scan disable
1930 13:38:17.487512 == TX Byte 0 ==
1931 13:38:17.490543 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1932 13:38:17.494188 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1933 13:38:17.497326 == TX Byte 1 ==
1934 13:38:17.500477 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1935 13:38:17.504072 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1936 13:38:17.507557 ==
1937 13:38:17.507645 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 13:38:17.513521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 13:38:17.513608 ==
1940 13:38:17.525668 TX Vref=22, minBit 0, minWin=27, winSum=448
1941 13:38:17.529585 TX Vref=24, minBit 1, minWin=27, winSum=448
1942 13:38:17.532775 TX Vref=26, minBit 1, minWin=27, winSum=452
1943 13:38:17.536037 TX Vref=28, minBit 6, minWin=27, winSum=456
1944 13:38:17.539364 TX Vref=30, minBit 1, minWin=27, winSum=458
1945 13:38:17.542726 TX Vref=32, minBit 1, minWin=27, winSum=456
1946 13:38:17.549262 [TxChooseVref] Worse bit 1, Min win 27, Win sum 458, Final Vref 30
1947 13:38:17.549376
1948 13:38:17.552222 Final TX Range 1 Vref 30
1949 13:38:17.552327
1950 13:38:17.552421 ==
1951 13:38:17.556116 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 13:38:17.559405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 13:38:17.559516 ==
1954 13:38:17.559611
1955 13:38:17.562769
1956 13:38:17.562874 TX Vref Scan disable
1957 13:38:17.565913 == TX Byte 0 ==
1958 13:38:17.569251 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1959 13:38:17.572698 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1960 13:38:17.576008 == TX Byte 1 ==
1961 13:38:17.579398 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1962 13:38:17.582732 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1963 13:38:17.586018
1964 13:38:17.586123 [DATLAT]
1965 13:38:17.586217 Freq=800, CH1 RK1
1966 13:38:17.586307
1967 13:38:17.589122 DATLAT Default: 0xa
1968 13:38:17.589195 0, 0xFFFF, sum = 0
1969 13:38:17.592165 1, 0xFFFF, sum = 0
1970 13:38:17.592266 2, 0xFFFF, sum = 0
1971 13:38:17.595910 3, 0xFFFF, sum = 0
1972 13:38:17.595998 4, 0xFFFF, sum = 0
1973 13:38:17.598926 5, 0xFFFF, sum = 0
1974 13:38:17.602419 6, 0xFFFF, sum = 0
1975 13:38:17.602500 7, 0xFFFF, sum = 0
1976 13:38:17.605516 8, 0xFFFF, sum = 0
1977 13:38:17.605592 9, 0x0, sum = 1
1978 13:38:17.605657 10, 0x0, sum = 2
1979 13:38:17.609275 11, 0x0, sum = 3
1980 13:38:17.609381 12, 0x0, sum = 4
1981 13:38:17.612391 best_step = 10
1982 13:38:17.612493
1983 13:38:17.612590 ==
1984 13:38:17.615644 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 13:38:17.618956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 13:38:17.619059 ==
1987 13:38:17.622188 RX Vref Scan: 0
1988 13:38:17.622262
1989 13:38:17.622326 RX Vref 0 -> 0, step: 1
1990 13:38:17.622387
1991 13:38:17.625369 RX Delay -111 -> 252, step: 8
1992 13:38:17.632612 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1993 13:38:17.635986 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1994 13:38:17.639116 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1995 13:38:17.642445 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1996 13:38:17.645840 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
1997 13:38:17.652487 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1998 13:38:17.655774 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1999 13:38:17.659499 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2000 13:38:17.662704 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2001 13:38:17.665979 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2002 13:38:17.672531 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2003 13:38:17.676005 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2004 13:38:17.679365 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2005 13:38:17.682905 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2006 13:38:17.686092 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2007 13:38:17.692686 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2008 13:38:17.692819 ==
2009 13:38:17.696044 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 13:38:17.699288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 13:38:17.699402 ==
2012 13:38:17.699497 DQS Delay:
2013 13:38:17.702588 DQS0 = 0, DQS1 = 0
2014 13:38:17.702704 DQM Delay:
2015 13:38:17.705867 DQM0 = 77, DQM1 = 73
2016 13:38:17.705952 DQ Delay:
2017 13:38:17.708930 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2018 13:38:17.712435 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2019 13:38:17.715823 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2020 13:38:17.718997 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
2021 13:38:17.719102
2022 13:38:17.719194
2023 13:38:17.729230 [DQSOSCAuto] RK1, (LSB)MR18= 0x263e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2024 13:38:17.729318 CH1 RK1: MR19=606, MR18=263E
2025 13:38:17.735497 CH1_RK1: MR19=0x606, MR18=0x263E, DQSOSC=394, MR23=63, INC=95, DEC=63
2026 13:38:17.739152 [RxdqsGatingPostProcess] freq 800
2027 13:38:17.745495 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 13:38:17.748810 Pre-setting of DQS Precalculation
2029 13:38:17.752161 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 13:38:17.758870 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 13:38:17.765563 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 13:38:17.765681
2033 13:38:17.769326
2034 13:38:17.769442 [Calibration Summary] 1600 Mbps
2035 13:38:17.772748 CH 0, Rank 0
2036 13:38:17.772828 SW Impedance : PASS
2037 13:38:17.776163 DUTY Scan : NO K
2038 13:38:17.779455 ZQ Calibration : PASS
2039 13:38:17.779554 Jitter Meter : NO K
2040 13:38:17.782234 CBT Training : PASS
2041 13:38:17.785655 Write leveling : PASS
2042 13:38:17.785765 RX DQS gating : PASS
2043 13:38:17.789086 RX DQ/DQS(RDDQC) : PASS
2044 13:38:17.792439 TX DQ/DQS : PASS
2045 13:38:17.792549 RX DATLAT : PASS
2046 13:38:17.795756 RX DQ/DQS(Engine): PASS
2047 13:38:17.795836 TX OE : NO K
2048 13:38:17.799240 All Pass.
2049 13:38:17.799342
2050 13:38:17.799432 CH 0, Rank 1
2051 13:38:17.802545 SW Impedance : PASS
2052 13:38:17.802620 DUTY Scan : NO K
2053 13:38:17.805771 ZQ Calibration : PASS
2054 13:38:17.809042 Jitter Meter : NO K
2055 13:38:17.809157 CBT Training : PASS
2056 13:38:17.812383 Write leveling : PASS
2057 13:38:17.815756 RX DQS gating : PASS
2058 13:38:17.815837 RX DQ/DQS(RDDQC) : PASS
2059 13:38:17.819010 TX DQ/DQS : PASS
2060 13:38:17.822696 RX DATLAT : PASS
2061 13:38:17.822807 RX DQ/DQS(Engine): PASS
2062 13:38:17.825784 TX OE : NO K
2063 13:38:17.825890 All Pass.
2064 13:38:17.825994
2065 13:38:17.829056 CH 1, Rank 0
2066 13:38:17.829165 SW Impedance : PASS
2067 13:38:17.832186 DUTY Scan : NO K
2068 13:38:17.836006 ZQ Calibration : PASS
2069 13:38:17.836112 Jitter Meter : NO K
2070 13:38:17.839342 CBT Training : PASS
2071 13:38:17.839456 Write leveling : PASS
2072 13:38:17.842718 RX DQS gating : PASS
2073 13:38:17.845965 RX DQ/DQS(RDDQC) : PASS
2074 13:38:17.846079 TX DQ/DQS : PASS
2075 13:38:17.849579 RX DATLAT : PASS
2076 13:38:17.852862 RX DQ/DQS(Engine): PASS
2077 13:38:17.852969 TX OE : NO K
2078 13:38:17.856110 All Pass.
2079 13:38:17.856218
2080 13:38:17.856309 CH 1, Rank 1
2081 13:38:17.859015 SW Impedance : PASS
2082 13:38:17.859122 DUTY Scan : NO K
2083 13:38:17.862487 ZQ Calibration : PASS
2084 13:38:17.865771 Jitter Meter : NO K
2085 13:38:17.865878 CBT Training : PASS
2086 13:38:17.869220 Write leveling : PASS
2087 13:38:17.872403 RX DQS gating : PASS
2088 13:38:17.872506 RX DQ/DQS(RDDQC) : PASS
2089 13:38:17.875771 TX DQ/DQS : PASS
2090 13:38:17.879369 RX DATLAT : PASS
2091 13:38:17.879474 RX DQ/DQS(Engine): PASS
2092 13:38:17.882565 TX OE : NO K
2093 13:38:17.882670 All Pass.
2094 13:38:17.882772
2095 13:38:17.885981 DramC Write-DBI off
2096 13:38:17.888799 PER_BANK_REFRESH: Hybrid Mode
2097 13:38:17.888882 TX_TRACKING: ON
2098 13:38:17.892106 [GetDramInforAfterCalByMRR] Vendor 6.
2099 13:38:17.895552 [GetDramInforAfterCalByMRR] Revision 606.
2100 13:38:17.899037 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 13:38:17.902390 MR0 0x3b3b
2102 13:38:17.902500 MR8 0x5151
2103 13:38:17.905835 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 13:38:17.905909
2105 13:38:17.905975 MR0 0x3b3b
2106 13:38:17.909042 MR8 0x5151
2107 13:38:17.912453 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 13:38:17.912531
2109 13:38:17.918966 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 13:38:17.925638 [FAST_K] Save calibration result to emmc
2111 13:38:17.929056 [FAST_K] Save calibration result to emmc
2112 13:38:17.929139 dram_init: config_dvfs: 1
2113 13:38:17.935213 dramc_set_vcore_voltage set vcore to 662500
2114 13:38:17.935301 Read voltage for 1200, 2
2115 13:38:17.935366 Vio18 = 0
2116 13:38:17.939064 Vcore = 662500
2117 13:38:17.939206 Vdram = 0
2118 13:38:17.939316 Vddq = 0
2119 13:38:17.942330 Vmddr = 0
2120 13:38:17.945683 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 13:38:17.951754 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 13:38:17.955688 MEM_TYPE=3, freq_sel=15
2123 13:38:17.955800 sv_algorithm_assistance_LP4_1600
2124 13:38:17.961830 ============ PULL DRAM RESETB DOWN ============
2125 13:38:17.965101 ========== PULL DRAM RESETB DOWN end =========
2126 13:38:17.968453 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 13:38:17.971965 ===================================
2128 13:38:17.974893 LPDDR4 DRAM CONFIGURATION
2129 13:38:17.978263 ===================================
2130 13:38:17.981684 EX_ROW_EN[0] = 0x0
2131 13:38:17.981804 EX_ROW_EN[1] = 0x0
2132 13:38:17.984991 LP4Y_EN = 0x0
2133 13:38:17.985065 WORK_FSP = 0x0
2134 13:38:17.988744 WL = 0x4
2135 13:38:17.988817 RL = 0x4
2136 13:38:17.991838 BL = 0x2
2137 13:38:17.991917 RPST = 0x0
2138 13:38:17.995098 RD_PRE = 0x0
2139 13:38:17.995169 WR_PRE = 0x1
2140 13:38:17.998592 WR_PST = 0x0
2141 13:38:17.998661 DBI_WR = 0x0
2142 13:38:18.001987 DBI_RD = 0x0
2143 13:38:18.002056 OTF = 0x1
2144 13:38:18.005311 ===================================
2145 13:38:18.008135 ===================================
2146 13:38:18.011423 ANA top config
2147 13:38:18.015311 ===================================
2148 13:38:18.018479 DLL_ASYNC_EN = 0
2149 13:38:18.018554 ALL_SLAVE_EN = 0
2150 13:38:18.021919 NEW_RANK_MODE = 1
2151 13:38:18.025197 DLL_IDLE_MODE = 1
2152 13:38:18.028653 LP45_APHY_COMB_EN = 1
2153 13:38:18.031809 TX_ODT_DIS = 1
2154 13:38:18.031885 NEW_8X_MODE = 1
2155 13:38:18.035155 ===================================
2156 13:38:18.038444 ===================================
2157 13:38:18.041638 data_rate = 2400
2158 13:38:18.044904 CKR = 1
2159 13:38:18.047973 DQ_P2S_RATIO = 8
2160 13:38:18.051316 ===================================
2161 13:38:18.054612 CA_P2S_RATIO = 8
2162 13:38:18.054692 DQ_CA_OPEN = 0
2163 13:38:18.058081 DQ_SEMI_OPEN = 0
2164 13:38:18.061350 CA_SEMI_OPEN = 0
2165 13:38:18.064769 CA_FULL_RATE = 0
2166 13:38:18.068000 DQ_CKDIV4_EN = 0
2167 13:38:18.071318 CA_CKDIV4_EN = 0
2168 13:38:18.071446 CA_PREDIV_EN = 0
2169 13:38:18.075132 PH8_DLY = 17
2170 13:38:18.078336 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 13:38:18.081743 DQ_AAMCK_DIV = 4
2172 13:38:18.085173 CA_AAMCK_DIV = 4
2173 13:38:18.088460 CA_ADMCK_DIV = 4
2174 13:38:18.088579 DQ_TRACK_CA_EN = 0
2175 13:38:18.091736 CA_PICK = 1200
2176 13:38:18.095112 CA_MCKIO = 1200
2177 13:38:18.098101 MCKIO_SEMI = 0
2178 13:38:18.101890 PLL_FREQ = 2366
2179 13:38:18.105210 DQ_UI_PI_RATIO = 32
2180 13:38:18.108093 CA_UI_PI_RATIO = 0
2181 13:38:18.111466 ===================================
2182 13:38:18.115397 ===================================
2183 13:38:18.115500 memory_type:LPDDR4
2184 13:38:18.118685 GP_NUM : 10
2185 13:38:18.121725 SRAM_EN : 1
2186 13:38:18.121824 MD32_EN : 0
2187 13:38:18.125057 ===================================
2188 13:38:18.128431 [ANA_INIT] >>>>>>>>>>>>>>
2189 13:38:18.131785 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 13:38:18.135251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 13:38:18.138435 ===================================
2192 13:38:18.141865 data_rate = 2400,PCW = 0X5b00
2193 13:38:18.145069 ===================================
2194 13:38:18.148112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 13:38:18.151999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 13:38:18.158443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 13:38:18.161749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 13:38:18.165048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 13:38:18.168369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 13:38:18.171664 [ANA_INIT] flow start
2201 13:38:18.175039 [ANA_INIT] PLL >>>>>>>>
2202 13:38:18.175144 [ANA_INIT] PLL <<<<<<<<
2203 13:38:18.178345 [ANA_INIT] MIDPI >>>>>>>>
2204 13:38:18.181629 [ANA_INIT] MIDPI <<<<<<<<
2205 13:38:18.181750 [ANA_INIT] DLL >>>>>>>>
2206 13:38:18.185290 [ANA_INIT] DLL <<<<<<<<
2207 13:38:18.188484 [ANA_INIT] flow end
2208 13:38:18.191792 ============ LP4 DIFF to SE enter ============
2209 13:38:18.195144 ============ LP4 DIFF to SE exit ============
2210 13:38:18.198397 [ANA_INIT] <<<<<<<<<<<<<
2211 13:38:18.201712 [Flow] Enable top DCM control >>>>>
2212 13:38:18.204919 [Flow] Enable top DCM control <<<<<
2213 13:38:18.208068 Enable DLL master slave shuffle
2214 13:38:18.211695 ==============================================================
2215 13:38:18.215070 Gating Mode config
2216 13:38:18.221755 ==============================================================
2217 13:38:18.221872 Config description:
2218 13:38:18.231575 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 13:38:18.238153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 13:38:18.241510 SELPH_MODE 0: By rank 1: By Phase
2221 13:38:18.247939 ==============================================================
2222 13:38:18.251359 GAT_TRACK_EN = 1
2223 13:38:18.255080 RX_GATING_MODE = 2
2224 13:38:18.258184 RX_GATING_TRACK_MODE = 2
2225 13:38:18.261252 SELPH_MODE = 1
2226 13:38:18.265149 PICG_EARLY_EN = 1
2227 13:38:18.268362 VALID_LAT_VALUE = 1
2228 13:38:18.271860 ==============================================================
2229 13:38:18.275023 Enter into Gating configuration >>>>
2230 13:38:18.278281 Exit from Gating configuration <<<<
2231 13:38:18.281503 Enter into DVFS_PRE_config >>>>>
2232 13:38:18.294601 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 13:38:18.294698 Exit from DVFS_PRE_config <<<<<
2234 13:38:18.297960 Enter into PICG configuration >>>>
2235 13:38:18.301228 Exit from PICG configuration <<<<
2236 13:38:18.304591 [RX_INPUT] configuration >>>>>
2237 13:38:18.307915 [RX_INPUT] configuration <<<<<
2238 13:38:18.314367 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 13:38:18.318115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 13:38:18.324506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 13:38:18.330936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 13:38:18.338129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 13:38:18.344698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 13:38:18.348048 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 13:38:18.351334 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 13:38:18.354648 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 13:38:18.361066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 13:38:18.364869 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 13:38:18.367737 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 13:38:18.371015 ===================================
2251 13:38:18.374115 LPDDR4 DRAM CONFIGURATION
2252 13:38:18.378078 ===================================
2253 13:38:18.378177 EX_ROW_EN[0] = 0x0
2254 13:38:18.380695 EX_ROW_EN[1] = 0x0
2255 13:38:18.384071 LP4Y_EN = 0x0
2256 13:38:18.384173 WORK_FSP = 0x0
2257 13:38:18.388125 WL = 0x4
2258 13:38:18.388226 RL = 0x4
2259 13:38:18.390813 BL = 0x2
2260 13:38:18.390932 RPST = 0x0
2261 13:38:18.394061 RD_PRE = 0x0
2262 13:38:18.394142 WR_PRE = 0x1
2263 13:38:18.397942 WR_PST = 0x0
2264 13:38:18.398026 DBI_WR = 0x0
2265 13:38:18.401175 DBI_RD = 0x0
2266 13:38:18.401260 OTF = 0x1
2267 13:38:18.404514 ===================================
2268 13:38:18.407863 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 13:38:18.414314 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 13:38:18.417690 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 13:38:18.420912 ===================================
2272 13:38:18.424123 LPDDR4 DRAM CONFIGURATION
2273 13:38:18.427828 ===================================
2274 13:38:18.427914 EX_ROW_EN[0] = 0x10
2275 13:38:18.431078 EX_ROW_EN[1] = 0x0
2276 13:38:18.431196 LP4Y_EN = 0x0
2277 13:38:18.434221 WORK_FSP = 0x0
2278 13:38:18.434306 WL = 0x4
2279 13:38:18.437518 RL = 0x4
2280 13:38:18.440741 BL = 0x2
2281 13:38:18.440823 RPST = 0x0
2282 13:38:18.443890 RD_PRE = 0x0
2283 13:38:18.443970 WR_PRE = 0x1
2284 13:38:18.447832 WR_PST = 0x0
2285 13:38:18.447923 DBI_WR = 0x0
2286 13:38:18.451080 DBI_RD = 0x0
2287 13:38:18.451162 OTF = 0x1
2288 13:38:18.453841 ===================================
2289 13:38:18.460453 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 13:38:18.460555 ==
2291 13:38:18.464142 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 13:38:18.467536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 13:38:18.467665 ==
2294 13:38:18.470714 [Duty_Offset_Calibration]
2295 13:38:18.473968 B0:2 B1:0 CA:3
2296 13:38:18.474052
2297 13:38:18.477126 [DutyScan_Calibration_Flow] k_type=0
2298 13:38:18.484990
2299 13:38:18.485086 ==CLK 0==
2300 13:38:18.488451 Final CLK duty delay cell = 0
2301 13:38:18.491780 [0] MAX Duty = 5062%(X100), DQS PI = 20
2302 13:38:18.495608 [0] MIN Duty = 4875%(X100), DQS PI = 58
2303 13:38:18.495688 [0] AVG Duty = 4968%(X100)
2304 13:38:18.498833
2305 13:38:18.502249 CH0 CLK Duty spec in!! Max-Min= 187%
2306 13:38:18.505051 [DutyScan_Calibration_Flow] ====Done====
2307 13:38:18.505132
2308 13:38:18.508277 [DutyScan_Calibration_Flow] k_type=1
2309 13:38:18.524155
2310 13:38:18.524254 ==DQS 0 ==
2311 13:38:18.527366 Final DQS duty delay cell = 0
2312 13:38:18.530758 [0] MAX Duty = 5093%(X100), DQS PI = 28
2313 13:38:18.533925 [0] MIN Duty = 4907%(X100), DQS PI = 2
2314 13:38:18.534011 [0] AVG Duty = 5000%(X100)
2315 13:38:18.537027
2316 13:38:18.537103 ==DQS 1 ==
2317 13:38:18.540710 Final DQS duty delay cell = -4
2318 13:38:18.543970 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2319 13:38:18.547178 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2320 13:38:18.550347 [-4] AVG Duty = 4922%(X100)
2321 13:38:18.550433
2322 13:38:18.553705 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2323 13:38:18.553794
2324 13:38:18.556907 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2325 13:38:18.560243 [DutyScan_Calibration_Flow] ====Done====
2326 13:38:18.560353
2327 13:38:18.563578 [DutyScan_Calibration_Flow] k_type=3
2328 13:38:18.581657
2329 13:38:18.581768 ==DQM 0 ==
2330 13:38:18.584684 Final DQM duty delay cell = 0
2331 13:38:18.587906 [0] MAX Duty = 5124%(X100), DQS PI = 28
2332 13:38:18.591232 [0] MIN Duty = 4876%(X100), DQS PI = 0
2333 13:38:18.591367 [0] AVG Duty = 5000%(X100)
2334 13:38:18.594765
2335 13:38:18.594975 ==DQM 1 ==
2336 13:38:18.598075 Final DQM duty delay cell = 4
2337 13:38:18.601366 [4] MAX Duty = 5124%(X100), DQS PI = 50
2338 13:38:18.604550 [4] MIN Duty = 5000%(X100), DQS PI = 14
2339 13:38:18.604665 [4] AVG Duty = 5062%(X100)
2340 13:38:18.607867
2341 13:38:18.611140 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2342 13:38:18.611263
2343 13:38:18.614367 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2344 13:38:18.617721 [DutyScan_Calibration_Flow] ====Done====
2345 13:38:18.617837
2346 13:38:18.620861 [DutyScan_Calibration_Flow] k_type=2
2347 13:38:18.636108
2348 13:38:18.636258 ==DQ 0 ==
2349 13:38:18.639279 Final DQ duty delay cell = -4
2350 13:38:18.642678 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2351 13:38:18.645919 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2352 13:38:18.649585 [-4] AVG Duty = 4969%(X100)
2353 13:38:18.649672
2354 13:38:18.649735 ==DQ 1 ==
2355 13:38:18.652567 Final DQ duty delay cell = -4
2356 13:38:18.656050 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2357 13:38:18.659009 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2358 13:38:18.662707 [-4] AVG Duty = 4938%(X100)
2359 13:38:18.662803
2360 13:38:18.665867 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2361 13:38:18.665963
2362 13:38:18.669081 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2363 13:38:18.672799 [DutyScan_Calibration_Flow] ====Done====
2364 13:38:18.672895 ==
2365 13:38:18.676111 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 13:38:18.679550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 13:38:18.679658 ==
2368 13:38:18.682782 [Duty_Offset_Calibration]
2369 13:38:18.682858 B0:1 B1:-2 CA:1
2370 13:38:18.682920
2371 13:38:18.686042 [DutyScan_Calibration_Flow] k_type=0
2372 13:38:18.696970
2373 13:38:18.697095 ==CLK 0==
2374 13:38:18.700165 Final CLK duty delay cell = 0
2375 13:38:18.703470 [0] MAX Duty = 5062%(X100), DQS PI = 30
2376 13:38:18.706808 [0] MIN Duty = 4875%(X100), DQS PI = 2
2377 13:38:18.706903 [0] AVG Duty = 4968%(X100)
2378 13:38:18.710091
2379 13:38:18.710180 CH1 CLK Duty spec in!! Max-Min= 187%
2380 13:38:18.716689 [DutyScan_Calibration_Flow] ====Done====
2381 13:38:18.716829
2382 13:38:18.719861 [DutyScan_Calibration_Flow] k_type=1
2383 13:38:18.735157
2384 13:38:18.735324 ==DQS 0 ==
2385 13:38:18.738404 Final DQS duty delay cell = -4
2386 13:38:18.741798 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2387 13:38:18.745016 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2388 13:38:18.748353 [-4] AVG Duty = 4953%(X100)
2389 13:38:18.748465
2390 13:38:18.748569 ==DQS 1 ==
2391 13:38:18.751783 Final DQS duty delay cell = 0
2392 13:38:18.754931 [0] MAX Duty = 5062%(X100), DQS PI = 0
2393 13:38:18.758184 [0] MIN Duty = 4875%(X100), DQS PI = 26
2394 13:38:18.761351 [0] AVG Duty = 4968%(X100)
2395 13:38:18.761476
2396 13:38:18.764994 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2397 13:38:18.765082
2398 13:38:18.768495 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2399 13:38:18.771625 [DutyScan_Calibration_Flow] ====Done====
2400 13:38:18.771735
2401 13:38:18.774586 [DutyScan_Calibration_Flow] k_type=3
2402 13:38:18.791378
2403 13:38:18.791521 ==DQM 0 ==
2404 13:38:18.794603 Final DQM duty delay cell = 0
2405 13:38:18.797856 [0] MAX Duty = 5000%(X100), DQS PI = 22
2406 13:38:18.801776 [0] MIN Duty = 4844%(X100), DQS PI = 56
2407 13:38:18.804757 [0] AVG Duty = 4922%(X100)
2408 13:38:18.804850
2409 13:38:18.804917 ==DQM 1 ==
2410 13:38:18.807949 Final DQM duty delay cell = 0
2411 13:38:18.811636 [0] MAX Duty = 5031%(X100), DQS PI = 34
2412 13:38:18.815074 [0] MIN Duty = 4907%(X100), DQS PI = 0
2413 13:38:18.818266 [0] AVG Duty = 4969%(X100)
2414 13:38:18.818420
2415 13:38:18.821621 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2416 13:38:18.821733
2417 13:38:18.824787 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2418 13:38:18.828099 [DutyScan_Calibration_Flow] ====Done====
2419 13:38:18.828234
2420 13:38:18.831399 [DutyScan_Calibration_Flow] k_type=2
2421 13:38:18.847797
2422 13:38:18.847936 ==DQ 0 ==
2423 13:38:18.851178 Final DQ duty delay cell = 0
2424 13:38:18.854389 [0] MAX Duty = 5093%(X100), DQS PI = 20
2425 13:38:18.857903 [0] MIN Duty = 4938%(X100), DQS PI = 54
2426 13:38:18.858017 [0] AVG Duty = 5015%(X100)
2427 13:38:18.861105
2428 13:38:18.861191 ==DQ 1 ==
2429 13:38:18.864331 Final DQ duty delay cell = 0
2430 13:38:18.867757 [0] MAX Duty = 5093%(X100), DQS PI = 20
2431 13:38:18.870913 [0] MIN Duty = 4969%(X100), DQS PI = 26
2432 13:38:18.871027 [0] AVG Duty = 5031%(X100)
2433 13:38:18.874632
2434 13:38:18.877688 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2435 13:38:18.877771
2436 13:38:18.881076 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2437 13:38:18.884240 [DutyScan_Calibration_Flow] ====Done====
2438 13:38:18.887964 nWR fixed to 30
2439 13:38:18.888048 [ModeRegInit_LP4] CH0 RK0
2440 13:38:18.891322 [ModeRegInit_LP4] CH0 RK1
2441 13:38:18.894300 [ModeRegInit_LP4] CH1 RK0
2442 13:38:18.897921 [ModeRegInit_LP4] CH1 RK1
2443 13:38:18.898031 match AC timing 7
2444 13:38:18.901051 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 13:38:18.907804 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 13:38:18.910898 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 13:38:18.917877 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 13:38:18.921058 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 13:38:18.921239 ==
2450 13:38:18.924402 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 13:38:18.927653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 13:38:18.927813 ==
2453 13:38:18.934165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 13:38:18.940759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2455 13:38:18.947986 [CA 0] Center 40 (10~71) winsize 62
2456 13:38:18.951216 [CA 1] Center 40 (10~70) winsize 61
2457 13:38:18.954727 [CA 2] Center 36 (6~66) winsize 61
2458 13:38:18.957946 [CA 3] Center 35 (5~66) winsize 62
2459 13:38:18.961264 [CA 4] Center 34 (4~65) winsize 62
2460 13:38:18.964681 [CA 5] Center 33 (3~64) winsize 62
2461 13:38:18.964818
2462 13:38:18.967748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2463 13:38:18.967832
2464 13:38:18.971055 [CATrainingPosCal] consider 1 rank data
2465 13:38:18.974327 u2DelayCellTimex100 = 270/100 ps
2466 13:38:18.978343 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2467 13:38:18.984809 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2468 13:38:18.988099 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2469 13:38:18.991377 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 13:38:18.994755 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2471 13:38:18.997856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2472 13:38:18.997936
2473 13:38:19.001069 CA PerBit enable=1, Macro0, CA PI delay=33
2474 13:38:19.001146
2475 13:38:19.004589 [CBTSetCACLKResult] CA Dly = 33
2476 13:38:19.004679 CS Dly: 7 (0~38)
2477 13:38:19.008068 ==
2478 13:38:19.011053 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 13:38:19.014344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 13:38:19.014424 ==
2481 13:38:19.018124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 13:38:19.024677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2483 13:38:19.034277 [CA 0] Center 40 (10~70) winsize 61
2484 13:38:19.037635 [CA 1] Center 39 (9~70) winsize 62
2485 13:38:19.040879 [CA 2] Center 35 (5~66) winsize 62
2486 13:38:19.044664 [CA 3] Center 35 (5~66) winsize 62
2487 13:38:19.047616 [CA 4] Center 34 (4~65) winsize 62
2488 13:38:19.050789 [CA 5] Center 33 (3~63) winsize 61
2489 13:38:19.050882
2490 13:38:19.054045 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2491 13:38:19.054128
2492 13:38:19.057994 [CATrainingPosCal] consider 2 rank data
2493 13:38:19.061232 u2DelayCellTimex100 = 270/100 ps
2494 13:38:19.064421 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2495 13:38:19.070951 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2496 13:38:19.074360 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2497 13:38:19.077751 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 13:38:19.081148 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 13:38:19.084372 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 13:38:19.084500
2501 13:38:19.087578 CA PerBit enable=1, Macro0, CA PI delay=33
2502 13:38:19.087689
2503 13:38:19.091178 [CBTSetCACLKResult] CA Dly = 33
2504 13:38:19.091331 CS Dly: 8 (0~40)
2505 13:38:19.094697
2506 13:38:19.097219 ----->DramcWriteLeveling(PI) begin...
2507 13:38:19.097310 ==
2508 13:38:19.100637 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 13:38:19.103934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 13:38:19.104047 ==
2511 13:38:19.107309 Write leveling (Byte 0): 32 => 32
2512 13:38:19.110603 Write leveling (Byte 1): 28 => 28
2513 13:38:19.114247 DramcWriteLeveling(PI) end<-----
2514 13:38:19.114362
2515 13:38:19.114472 ==
2516 13:38:19.117773 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 13:38:19.120694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 13:38:19.120793 ==
2519 13:38:19.124139 [Gating] SW mode calibration
2520 13:38:19.131063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 13:38:19.137403 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 13:38:19.140714 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2523 13:38:19.144029 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2524 13:38:19.150675 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 13:38:19.154373 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 13:38:19.157498 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 13:38:19.160768 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 13:38:19.167366 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 13:38:19.170777 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2530 13:38:19.174071 1 0 0 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 0)
2531 13:38:19.180605 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2532 13:38:19.184076 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:38:19.187354 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 13:38:19.194424 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:38:19.197696 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 13:38:19.200986 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 13:38:19.207444 1 0 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2538 13:38:19.210672 1 1 0 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
2539 13:38:19.214040 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2540 13:38:19.220839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:38:19.224513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 13:38:19.227560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 13:38:19.234472 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 13:38:19.237400 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 13:38:19.241048 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 13:38:19.248056 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2547 13:38:19.251144 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 13:38:19.254357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:38:19.257560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:38:19.264109 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:38:19.267365 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:38:19.270769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:38:19.277354 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:38:19.280758 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:38:19.284054 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:38:19.290637 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:38:19.294034 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:38:19.297223 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:38:19.304412 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:38:19.307716 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:38:19.311011 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 13:38:19.317584 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2563 13:38:19.320928 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 13:38:19.324408 Total UI for P1: 0, mck2ui 16
2565 13:38:19.327700 best dqsien dly found for B0: ( 1, 3, 30)
2566 13:38:19.330882 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 13:38:19.334334 Total UI for P1: 0, mck2ui 16
2568 13:38:19.337512 best dqsien dly found for B1: ( 1, 4, 4)
2569 13:38:19.341232 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2570 13:38:19.344156 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2571 13:38:19.344234
2572 13:38:19.347857 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2573 13:38:19.354032 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2574 13:38:19.354113 [Gating] SW calibration Done
2575 13:38:19.354199 ==
2576 13:38:19.357447 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 13:38:19.364132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 13:38:19.364226 ==
2579 13:38:19.364292 RX Vref Scan: 0
2580 13:38:19.364352
2581 13:38:19.367833 RX Vref 0 -> 0, step: 1
2582 13:38:19.367911
2583 13:38:19.370738 RX Delay -40 -> 252, step: 8
2584 13:38:19.374036 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2585 13:38:19.377920 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2586 13:38:19.381142 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2587 13:38:19.384362 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2588 13:38:19.390969 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2589 13:38:19.394388 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2590 13:38:19.397856 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2591 13:38:19.400480 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2592 13:38:19.404240 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2593 13:38:19.410798 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2594 13:38:19.414031 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2595 13:38:19.417487 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2596 13:38:19.421011 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2597 13:38:19.424430 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2598 13:38:19.430493 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2599 13:38:19.433720 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2600 13:38:19.433805 ==
2601 13:38:19.437111 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 13:38:19.440264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 13:38:19.440351 ==
2604 13:38:19.444261 DQS Delay:
2605 13:38:19.444345 DQS0 = 0, DQS1 = 0
2606 13:38:19.444454 DQM Delay:
2607 13:38:19.447331 DQM0 = 112, DQM1 = 101
2608 13:38:19.447414 DQ Delay:
2609 13:38:19.450329 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2610 13:38:19.454317 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2611 13:38:19.457058 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2612 13:38:19.460912 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2613 13:38:19.463813
2614 13:38:19.463893
2615 13:38:19.463963 ==
2616 13:38:19.467705 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 13:38:19.471061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 13:38:19.471139 ==
2619 13:38:19.471210
2620 13:38:19.471271
2621 13:38:19.474069 TX Vref Scan disable
2622 13:38:19.474147 == TX Byte 0 ==
2623 13:38:19.480815 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2624 13:38:19.483800 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2625 13:38:19.483894 == TX Byte 1 ==
2626 13:38:19.490586 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2627 13:38:19.494012 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2628 13:38:19.494107 ==
2629 13:38:19.497305 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:38:19.500633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:38:19.500748 ==
2632 13:38:19.513021 TX Vref=22, minBit 5, minWin=25, winSum=415
2633 13:38:19.516267 TX Vref=24, minBit 8, minWin=25, winSum=421
2634 13:38:19.519659 TX Vref=26, minBit 11, minWin=25, winSum=428
2635 13:38:19.523089 TX Vref=28, minBit 8, minWin=26, winSum=434
2636 13:38:19.526472 TX Vref=30, minBit 8, minWin=26, winSum=434
2637 13:38:19.533054 TX Vref=32, minBit 8, minWin=25, winSum=433
2638 13:38:19.536251 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2639 13:38:19.536337
2640 13:38:19.540015 Final TX Range 1 Vref 28
2641 13:38:19.540101
2642 13:38:19.540188 ==
2643 13:38:19.543452 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 13:38:19.546113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 13:38:19.546198 ==
2646 13:38:19.549475
2647 13:38:19.549552
2648 13:38:19.549617 TX Vref Scan disable
2649 13:38:19.552787 == TX Byte 0 ==
2650 13:38:19.556045 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2651 13:38:19.562712 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2652 13:38:19.562814 == TX Byte 1 ==
2653 13:38:19.566460 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2654 13:38:19.572666 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2655 13:38:19.572783
2656 13:38:19.572884 [DATLAT]
2657 13:38:19.572954 Freq=1200, CH0 RK0
2658 13:38:19.573014
2659 13:38:19.575943 DATLAT Default: 0xd
2660 13:38:19.576023 0, 0xFFFF, sum = 0
2661 13:38:19.579832 1, 0xFFFF, sum = 0
2662 13:38:19.582998 2, 0xFFFF, sum = 0
2663 13:38:19.583080 3, 0xFFFF, sum = 0
2664 13:38:19.586021 4, 0xFFFF, sum = 0
2665 13:38:19.586101 5, 0xFFFF, sum = 0
2666 13:38:19.589193 6, 0xFFFF, sum = 0
2667 13:38:19.589273 7, 0xFFFF, sum = 0
2668 13:38:19.593059 8, 0xFFFF, sum = 0
2669 13:38:19.593140 9, 0xFFFF, sum = 0
2670 13:38:19.595991 10, 0xFFFF, sum = 0
2671 13:38:19.596071 11, 0xFFFF, sum = 0
2672 13:38:19.599250 12, 0x0, sum = 1
2673 13:38:19.599329 13, 0x0, sum = 2
2674 13:38:19.602929 14, 0x0, sum = 3
2675 13:38:19.603013 15, 0x0, sum = 4
2676 13:38:19.605963 best_step = 13
2677 13:38:19.606042
2678 13:38:19.606115 ==
2679 13:38:19.609363 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 13:38:19.612458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 13:38:19.612536 ==
2682 13:38:19.612617 RX Vref Scan: 1
2683 13:38:19.612678
2684 13:38:19.615689 Set Vref Range= 32 -> 127
2685 13:38:19.615767
2686 13:38:19.619555 RX Vref 32 -> 127, step: 1
2687 13:38:19.619635
2688 13:38:19.622816 RX Delay -37 -> 252, step: 4
2689 13:38:19.622895
2690 13:38:19.626108 Set Vref, RX VrefLevel [Byte0]: 32
2691 13:38:19.629379 [Byte1]: 32
2692 13:38:19.629466
2693 13:38:19.632884 Set Vref, RX VrefLevel [Byte0]: 33
2694 13:38:19.636126 [Byte1]: 33
2695 13:38:19.639904
2696 13:38:19.639982 Set Vref, RX VrefLevel [Byte0]: 34
2697 13:38:19.643248 [Byte1]: 34
2698 13:38:19.647982
2699 13:38:19.648065 Set Vref, RX VrefLevel [Byte0]: 35
2700 13:38:19.650708 [Byte1]: 35
2701 13:38:19.655980
2702 13:38:19.656067 Set Vref, RX VrefLevel [Byte0]: 36
2703 13:38:19.658753 [Byte1]: 36
2704 13:38:19.663872
2705 13:38:19.663961 Set Vref, RX VrefLevel [Byte0]: 37
2706 13:38:19.666962 [Byte1]: 37
2707 13:38:19.672068
2708 13:38:19.672155 Set Vref, RX VrefLevel [Byte0]: 38
2709 13:38:19.674677 [Byte1]: 38
2710 13:38:19.679762
2711 13:38:19.679845 Set Vref, RX VrefLevel [Byte0]: 39
2712 13:38:19.682815 [Byte1]: 39
2713 13:38:19.687799
2714 13:38:19.687919 Set Vref, RX VrefLevel [Byte0]: 40
2715 13:38:19.690897 [Byte1]: 40
2716 13:38:19.695461
2717 13:38:19.695573 Set Vref, RX VrefLevel [Byte0]: 41
2718 13:38:19.698741 [Byte1]: 41
2719 13:38:19.703952
2720 13:38:19.704038 Set Vref, RX VrefLevel [Byte0]: 42
2721 13:38:19.707195 [Byte1]: 42
2722 13:38:19.712056
2723 13:38:19.712173 Set Vref, RX VrefLevel [Byte0]: 43
2724 13:38:19.715240 [Byte1]: 43
2725 13:38:19.719544
2726 13:38:19.719632 Set Vref, RX VrefLevel [Byte0]: 44
2727 13:38:19.723225 [Byte1]: 44
2728 13:38:19.727893
2729 13:38:19.727981 Set Vref, RX VrefLevel [Byte0]: 45
2730 13:38:19.730687 [Byte1]: 45
2731 13:38:19.736079
2732 13:38:19.736186 Set Vref, RX VrefLevel [Byte0]: 46
2733 13:38:19.738875 [Byte1]: 46
2734 13:38:19.744009
2735 13:38:19.744122 Set Vref, RX VrefLevel [Byte0]: 47
2736 13:38:19.747329 [Byte1]: 47
2737 13:38:19.751949
2738 13:38:19.752027 Set Vref, RX VrefLevel [Byte0]: 48
2739 13:38:19.755374 [Byte1]: 48
2740 13:38:19.760051
2741 13:38:19.760133 Set Vref, RX VrefLevel [Byte0]: 49
2742 13:38:19.762848 [Byte1]: 49
2743 13:38:19.767563
2744 13:38:19.767660 Set Vref, RX VrefLevel [Byte0]: 50
2745 13:38:19.770712 [Byte1]: 50
2746 13:38:19.775736
2747 13:38:19.775819 Set Vref, RX VrefLevel [Byte0]: 51
2748 13:38:19.779468 [Byte1]: 51
2749 13:38:19.784015
2750 13:38:19.784108 Set Vref, RX VrefLevel [Byte0]: 52
2751 13:38:19.786944 [Byte1]: 52
2752 13:38:19.791414
2753 13:38:19.791535 Set Vref, RX VrefLevel [Byte0]: 53
2754 13:38:19.795287 [Byte1]: 53
2755 13:38:19.799522
2756 13:38:19.799625 Set Vref, RX VrefLevel [Byte0]: 54
2757 13:38:19.802831 [Byte1]: 54
2758 13:38:19.807510
2759 13:38:19.807622 Set Vref, RX VrefLevel [Byte0]: 55
2760 13:38:19.810635 [Byte1]: 55
2761 13:38:19.815758
2762 13:38:19.815877 Set Vref, RX VrefLevel [Byte0]: 56
2763 13:38:19.818937 [Byte1]: 56
2764 13:38:19.824034
2765 13:38:19.824119 Set Vref, RX VrefLevel [Byte0]: 57
2766 13:38:19.827182 [Byte1]: 57
2767 13:38:19.831678
2768 13:38:19.831766 Set Vref, RX VrefLevel [Byte0]: 58
2769 13:38:19.835260 [Byte1]: 58
2770 13:38:19.839952
2771 13:38:19.840054 Set Vref, RX VrefLevel [Byte0]: 59
2772 13:38:19.843159 [Byte1]: 59
2773 13:38:19.847888
2774 13:38:19.847982 Set Vref, RX VrefLevel [Byte0]: 60
2775 13:38:19.851142 [Byte1]: 60
2776 13:38:19.855777
2777 13:38:19.855857 Set Vref, RX VrefLevel [Byte0]: 61
2778 13:38:19.859113 [Byte1]: 61
2779 13:38:19.863584
2780 13:38:19.863696 Set Vref, RX VrefLevel [Byte0]: 62
2781 13:38:19.866882 [Byte1]: 62
2782 13:38:19.871391
2783 13:38:19.871478 Set Vref, RX VrefLevel [Byte0]: 63
2784 13:38:19.874707 [Byte1]: 63
2785 13:38:19.879877
2786 13:38:19.879963 Set Vref, RX VrefLevel [Byte0]: 64
2787 13:38:19.883012 [Byte1]: 64
2788 13:38:19.887493
2789 13:38:19.887580 Set Vref, RX VrefLevel [Byte0]: 65
2790 13:38:19.890659 [Byte1]: 65
2791 13:38:19.895829
2792 13:38:19.895917 Set Vref, RX VrefLevel [Byte0]: 66
2793 13:38:19.899119 [Byte1]: 66
2794 13:38:19.903672
2795 13:38:19.903761 Set Vref, RX VrefLevel [Byte0]: 67
2796 13:38:19.906858 [Byte1]: 67
2797 13:38:19.911650
2798 13:38:19.911773 Set Vref, RX VrefLevel [Byte0]: 68
2799 13:38:19.914981 [Byte1]: 68
2800 13:38:19.919767
2801 13:38:19.919853 Set Vref, RX VrefLevel [Byte0]: 69
2802 13:38:19.922933 [Byte1]: 69
2803 13:38:19.927871
2804 13:38:19.927956 Set Vref, RX VrefLevel [Byte0]: 70
2805 13:38:19.930904 [Byte1]: 70
2806 13:38:19.935495
2807 13:38:19.935580 Set Vref, RX VrefLevel [Byte0]: 71
2808 13:38:19.938783 [Byte1]: 71
2809 13:38:19.943840
2810 13:38:19.943926 Set Vref, RX VrefLevel [Byte0]: 72
2811 13:38:19.946981 [Byte1]: 72
2812 13:38:19.951683
2813 13:38:19.951768 Set Vref, RX VrefLevel [Byte0]: 73
2814 13:38:19.954759 [Byte1]: 73
2815 13:38:19.959546
2816 13:38:19.959663 Set Vref, RX VrefLevel [Byte0]: 74
2817 13:38:19.962900 [Byte1]: 74
2818 13:38:19.967502
2819 13:38:19.967616 Set Vref, RX VrefLevel [Byte0]: 75
2820 13:38:19.970965 [Byte1]: 75
2821 13:38:19.975539
2822 13:38:19.975622 Final RX Vref Byte 0 = 60 to rank0
2823 13:38:19.978690 Final RX Vref Byte 1 = 55 to rank0
2824 13:38:19.982088 Final RX Vref Byte 0 = 60 to rank1
2825 13:38:19.985313 Final RX Vref Byte 1 = 55 to rank1==
2826 13:38:19.989141 Dram Type= 6, Freq= 0, CH_0, rank 0
2827 13:38:19.995770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 13:38:19.995855 ==
2829 13:38:19.995921 DQS Delay:
2830 13:38:19.995982 DQS0 = 0, DQS1 = 0
2831 13:38:19.998916 DQM Delay:
2832 13:38:19.998999 DQM0 = 112, DQM1 = 102
2833 13:38:20.002821 DQ Delay:
2834 13:38:20.006090 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =108
2835 13:38:20.008753 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2836 13:38:20.012778 DQ8 =94, DQ9 =86, DQ10 =102, DQ11 =94
2837 13:38:20.015336 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2838 13:38:20.015440
2839 13:38:20.015507
2840 13:38:20.022289 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2841 13:38:20.025501 CH0 RK0: MR19=303, MR18=FBFA
2842 13:38:20.032653 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2843 13:38:20.032740
2844 13:38:20.035894 ----->DramcWriteLeveling(PI) begin...
2845 13:38:20.035978 ==
2846 13:38:20.038814 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 13:38:20.042489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 13:38:20.042573 ==
2849 13:38:20.045927 Write leveling (Byte 0): 33 => 33
2850 13:38:20.049033 Write leveling (Byte 1): 31 => 31
2851 13:38:20.052391 DramcWriteLeveling(PI) end<-----
2852 13:38:20.052474
2853 13:38:20.052540 ==
2854 13:38:20.055633 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 13:38:20.062209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 13:38:20.062294 ==
2857 13:38:20.062392 [Gating] SW mode calibration
2858 13:38:20.072461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2859 13:38:20.075725 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2860 13:38:20.079057 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
2861 13:38:20.085763 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 13:38:20.089077 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 13:38:20.092359 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 13:38:20.098687 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 13:38:20.102293 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 13:38:20.105782 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2867 13:38:20.112388 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2868 13:38:20.115751 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2869 13:38:20.118983 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 13:38:20.125551 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 13:38:20.128689 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 13:38:20.132429 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 13:38:20.139166 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 13:38:20.142370 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
2875 13:38:20.145512 1 0 28 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
2876 13:38:20.152107 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
2877 13:38:20.155875 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 13:38:20.159103 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 13:38:20.162382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 13:38:20.168834 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 13:38:20.172175 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 13:38:20.175341 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 13:38:20.182157 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2884 13:38:20.185493 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 13:38:20.188765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:38:20.195387 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:38:20.198779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:38:20.202135 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:38:20.208957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:38:20.211952 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:38:20.215604 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:38:20.221822 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:38:20.225495 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:38:20.228867 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:38:20.235329 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:38:20.238574 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 13:38:20.241876 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 13:38:20.248872 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 13:38:20.252242 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 13:38:20.255271 Total UI for P1: 0, mck2ui 16
2901 13:38:20.258445 best dqsien dly found for B0: ( 1, 3, 24)
2902 13:38:20.262411 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 13:38:20.268840 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 13:38:20.268934 Total UI for P1: 0, mck2ui 16
2905 13:38:20.272109 best dqsien dly found for B1: ( 1, 3, 30)
2906 13:38:20.278863 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2907 13:38:20.281927 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2908 13:38:20.282015
2909 13:38:20.285080 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2910 13:38:20.288749 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2911 13:38:20.291894 [Gating] SW calibration Done
2912 13:38:20.292010 ==
2913 13:38:20.295309 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 13:38:20.298504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 13:38:20.298586 ==
2916 13:38:20.301807 RX Vref Scan: 0
2917 13:38:20.301886
2918 13:38:20.301949 RX Vref 0 -> 0, step: 1
2919 13:38:20.302012
2920 13:38:20.305005 RX Delay -40 -> 252, step: 8
2921 13:38:20.308376 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2922 13:38:20.315312 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2923 13:38:20.318665 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2924 13:38:20.321603 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2925 13:38:20.325207 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 13:38:20.328365 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2927 13:38:20.332142 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2928 13:38:20.338728 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 13:38:20.341831 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2930 13:38:20.345003 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2931 13:38:20.348407 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 13:38:20.351593 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2933 13:38:20.358148 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2934 13:38:20.361482 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2935 13:38:20.365321 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2936 13:38:20.368551 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2937 13:38:20.368649 ==
2938 13:38:20.371919 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 13:38:20.378616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 13:38:20.378772 ==
2941 13:38:20.378881 DQS Delay:
2942 13:38:20.381978 DQS0 = 0, DQS1 = 0
2943 13:38:20.382083 DQM Delay:
2944 13:38:20.382186 DQM0 = 112, DQM1 = 101
2945 13:38:20.384739 DQ Delay:
2946 13:38:20.388319 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2947 13:38:20.391348 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2948 13:38:20.395263 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2949 13:38:20.398532 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2950 13:38:20.398655
2951 13:38:20.398759
2952 13:38:20.398862 ==
2953 13:38:20.401838 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 13:38:20.405061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 13:38:20.405186 ==
2956 13:38:20.405290
2957 13:38:20.408594
2958 13:38:20.408710 TX Vref Scan disable
2959 13:38:20.411760 == TX Byte 0 ==
2960 13:38:20.415223 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2961 13:38:20.418843 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2962 13:38:20.422082 == TX Byte 1 ==
2963 13:38:20.425185 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2964 13:38:20.428271 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2965 13:38:20.428390 ==
2966 13:38:20.431517 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 13:38:20.438117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 13:38:20.438238 ==
2969 13:38:20.448694 TX Vref=22, minBit 1, minWin=25, winSum=418
2970 13:38:20.452067 TX Vref=24, minBit 1, minWin=26, winSum=429
2971 13:38:20.455956 TX Vref=26, minBit 2, minWin=26, winSum=434
2972 13:38:20.459168 TX Vref=28, minBit 10, minWin=26, winSum=443
2973 13:38:20.462216 TX Vref=30, minBit 8, minWin=26, winSum=439
2974 13:38:20.468805 TX Vref=32, minBit 13, minWin=26, winSum=443
2975 13:38:20.472003 [TxChooseVref] Worse bit 10, Min win 26, Win sum 443, Final Vref 28
2976 13:38:20.472129
2977 13:38:20.475367 Final TX Range 1 Vref 28
2978 13:38:20.475482
2979 13:38:20.475587 ==
2980 13:38:20.478838 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 13:38:20.482149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 13:38:20.482268 ==
2983 13:38:20.485601
2984 13:38:20.485713
2985 13:38:20.485816 TX Vref Scan disable
2986 13:38:20.488777 == TX Byte 0 ==
2987 13:38:20.492093 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2988 13:38:20.495421 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2989 13:38:20.499084 == TX Byte 1 ==
2990 13:38:20.502192 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2991 13:38:20.508667 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2992 13:38:20.508789
2993 13:38:20.508902 [DATLAT]
2994 13:38:20.508999 Freq=1200, CH0 RK1
2995 13:38:20.509097
2996 13:38:20.512017 DATLAT Default: 0xd
2997 13:38:20.512134 0, 0xFFFF, sum = 0
2998 13:38:20.515539 1, 0xFFFF, sum = 0
2999 13:38:20.515649 2, 0xFFFF, sum = 0
3000 13:38:20.518933 3, 0xFFFF, sum = 0
3001 13:38:20.522256 4, 0xFFFF, sum = 0
3002 13:38:20.522376 5, 0xFFFF, sum = 0
3003 13:38:20.525648 6, 0xFFFF, sum = 0
3004 13:38:20.525769 7, 0xFFFF, sum = 0
3005 13:38:20.529010 8, 0xFFFF, sum = 0
3006 13:38:20.529126 9, 0xFFFF, sum = 0
3007 13:38:20.532263 10, 0xFFFF, sum = 0
3008 13:38:20.532375 11, 0xFFFF, sum = 0
3009 13:38:20.535414 12, 0x0, sum = 1
3010 13:38:20.535528 13, 0x0, sum = 2
3011 13:38:20.538767 14, 0x0, sum = 3
3012 13:38:20.538883 15, 0x0, sum = 4
3013 13:38:20.538996 best_step = 13
3014 13:38:20.542149
3015 13:38:20.542262 ==
3016 13:38:20.545459 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 13:38:20.548824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 13:38:20.548944 ==
3019 13:38:20.549049 RX Vref Scan: 0
3020 13:38:20.549142
3021 13:38:20.552231 RX Vref 0 -> 0, step: 1
3022 13:38:20.552341
3023 13:38:20.555259 RX Delay -29 -> 252, step: 4
3024 13:38:20.559120 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3025 13:38:20.565418 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3026 13:38:20.569014 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3027 13:38:20.572238 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3028 13:38:20.575309 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 13:38:20.579117 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3030 13:38:20.585888 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3031 13:38:20.589195 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3032 13:38:20.592082 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3033 13:38:20.595982 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3034 13:38:20.599222 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3035 13:38:20.602617 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 13:38:20.608815 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 13:38:20.612045 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3038 13:38:20.615911 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3039 13:38:20.619163 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3040 13:38:20.619287 ==
3041 13:38:20.622525 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 13:38:20.628705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 13:38:20.628826 ==
3044 13:38:20.628929 DQS Delay:
3045 13:38:20.632065 DQS0 = 0, DQS1 = 0
3046 13:38:20.632182 DQM Delay:
3047 13:38:20.632284 DQM0 = 110, DQM1 = 101
3048 13:38:20.635435 DQ Delay:
3049 13:38:20.638632 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3050 13:38:20.642490 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3051 13:38:20.645707 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3052 13:38:20.649229 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3053 13:38:20.649349
3054 13:38:20.649451
3055 13:38:20.655941 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3056 13:38:20.659048 CH0 RK1: MR19=403, MR18=10F8
3057 13:38:20.665719 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3058 13:38:20.669075 [RxdqsGatingPostProcess] freq 1200
3059 13:38:20.675713 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 13:38:20.678688 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 13:38:20.682368 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 13:38:20.682498 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 13:38:20.685624 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 13:38:20.688872 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 13:38:20.692421 best DQS1 dly(2T, 0.5T) = (0, 11)
3066 13:38:20.695772 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 13:38:20.698567 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3068 13:38:20.701874 Pre-setting of DQS Precalculation
3069 13:38:20.708972 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 13:38:20.709097 ==
3071 13:38:20.712244 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 13:38:20.715466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 13:38:20.715581 ==
3074 13:38:20.722329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 13:38:20.725481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3076 13:38:20.735383 [CA 0] Center 37 (7~67) winsize 61
3077 13:38:20.738648 [CA 1] Center 38 (8~68) winsize 61
3078 13:38:20.742118 [CA 2] Center 34 (4~64) winsize 61
3079 13:38:20.745429 [CA 3] Center 33 (3~64) winsize 62
3080 13:38:20.748609 [CA 4] Center 34 (4~64) winsize 61
3081 13:38:20.751733 [CA 5] Center 33 (3~63) winsize 61
3082 13:38:20.751843
3083 13:38:20.755188 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3084 13:38:20.755313
3085 13:38:20.758453 [CATrainingPosCal] consider 1 rank data
3086 13:38:20.761700 u2DelayCellTimex100 = 270/100 ps
3087 13:38:20.765181 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3088 13:38:20.768351 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 13:38:20.775182 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 13:38:20.778475 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3091 13:38:20.781750 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 13:38:20.784853 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3093 13:38:20.784930
3094 13:38:20.788570 CA PerBit enable=1, Macro0, CA PI delay=33
3095 13:38:20.788657
3096 13:38:20.791638 [CBTSetCACLKResult] CA Dly = 33
3097 13:38:20.791729 CS Dly: 5 (0~36)
3098 13:38:20.795018 ==
3099 13:38:20.795120 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 13:38:20.801999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 13:38:20.802097 ==
3102 13:38:20.805120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 13:38:20.811873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 13:38:20.820415 [CA 0] Center 37 (7~67) winsize 61
3105 13:38:20.824251 [CA 1] Center 37 (7~68) winsize 62
3106 13:38:20.827349 [CA 2] Center 34 (4~65) winsize 62
3107 13:38:20.830943 [CA 3] Center 33 (3~64) winsize 62
3108 13:38:20.834279 [CA 4] Center 34 (4~65) winsize 62
3109 13:38:20.837573 [CA 5] Center 33 (3~63) winsize 61
3110 13:38:20.837654
3111 13:38:20.840938 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3112 13:38:20.841022
3113 13:38:20.844298 [CATrainingPosCal] consider 2 rank data
3114 13:38:20.847142 u2DelayCellTimex100 = 270/100 ps
3115 13:38:20.850491 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3116 13:38:20.854336 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3117 13:38:20.857559 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 13:38:20.864361 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3119 13:38:20.867682 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 13:38:20.871073 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3121 13:38:20.871158
3122 13:38:20.874394 CA PerBit enable=1, Macro0, CA PI delay=33
3123 13:38:20.874479
3124 13:38:20.877717 [CBTSetCACLKResult] CA Dly = 33
3125 13:38:20.877802 CS Dly: 6 (0~39)
3126 13:38:20.877867
3127 13:38:20.881179 ----->DramcWriteLeveling(PI) begin...
3128 13:38:20.881289 ==
3129 13:38:20.884413 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 13:38:20.891140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 13:38:20.891250 ==
3132 13:38:20.894365 Write leveling (Byte 0): 26 => 26
3133 13:38:20.898060 Write leveling (Byte 1): 29 => 29
3134 13:38:20.898167 DramcWriteLeveling(PI) end<-----
3135 13:38:20.898259
3136 13:38:20.901027 ==
3137 13:38:20.904222 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 13:38:20.907479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 13:38:20.907589 ==
3140 13:38:20.911269 [Gating] SW mode calibration
3141 13:38:20.918116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 13:38:20.921441 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 13:38:20.927625 0 15 0 | B1->B0 | 2c2c 2625 | 1 1 | (0 0) (0 0)
3144 13:38:20.930905 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 13:38:20.934197 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 13:38:20.941010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 13:38:20.944325 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 13:38:20.947777 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 13:38:20.954667 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 13:38:20.958040 0 15 28 | B1->B0 | 2c2c 3030 | 1 1 | (1 0) (1 0)
3151 13:38:20.961194 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3152 13:38:20.968280 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 13:38:20.971133 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 13:38:20.974340 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 13:38:20.977680 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 13:38:20.984250 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 13:38:20.987726 1 0 24 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3158 13:38:20.991270 1 0 28 | B1->B0 | 4242 4444 | 0 0 | (1 1) (0 0)
3159 13:38:20.998127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 13:38:21.001402 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 13:38:21.004701 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 13:38:21.011484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 13:38:21.014668 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 13:38:21.017799 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 13:38:21.024690 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 13:38:21.028142 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 13:38:21.031427 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3168 13:38:21.037424 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:38:21.041379 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:38:21.044598 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:38:21.050950 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:38:21.054229 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:38:21.057435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:38:21.064024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:38:21.067859 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:38:21.070975 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:38:21.077803 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 13:38:21.080498 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 13:38:21.084419 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 13:38:21.091131 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 13:38:21.093901 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 13:38:21.097405 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 13:38:21.100840 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 13:38:21.104263 Total UI for P1: 0, mck2ui 16
3185 13:38:21.107476 best dqsien dly found for B0: ( 1, 3, 28)
3186 13:38:21.110929 Total UI for P1: 0, mck2ui 16
3187 13:38:21.114154 best dqsien dly found for B1: ( 1, 3, 28)
3188 13:38:21.117235 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3189 13:38:21.120710 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3190 13:38:21.124257
3191 13:38:21.127423 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3192 13:38:21.130658 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 13:38:21.133725 [Gating] SW calibration Done
3194 13:38:21.133803 ==
3195 13:38:21.137856 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 13:38:21.140416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 13:38:21.140507 ==
3198 13:38:21.140582 RX Vref Scan: 0
3199 13:38:21.140650
3200 13:38:21.143814 RX Vref 0 -> 0, step: 1
3201 13:38:21.143901
3202 13:38:21.147045 RX Delay -40 -> 252, step: 8
3203 13:38:21.150318 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3204 13:38:21.154212 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 13:38:21.160666 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 13:38:21.164097 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3207 13:38:21.167363 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 13:38:21.170824 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3209 13:38:21.173938 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3210 13:38:21.180382 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3211 13:38:21.183819 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3212 13:38:21.187517 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 13:38:21.190785 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3214 13:38:21.194278 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3215 13:38:21.200250 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3216 13:38:21.203837 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3217 13:38:21.207127 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3218 13:38:21.210582 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3219 13:38:21.210669 ==
3220 13:38:21.213806 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 13:38:21.220509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 13:38:21.220605 ==
3223 13:38:21.220713 DQS Delay:
3224 13:38:21.220781 DQS0 = 0, DQS1 = 0
3225 13:38:21.223834 DQM Delay:
3226 13:38:21.223921 DQM0 = 114, DQM1 = 105
3227 13:38:21.227106 DQ Delay:
3228 13:38:21.230212 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3229 13:38:21.233933 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3230 13:38:21.236993 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3231 13:38:21.240203 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3232 13:38:21.240284
3233 13:38:21.240347
3234 13:38:21.240407 ==
3235 13:38:21.243573 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 13:38:21.247166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 13:38:21.247250 ==
3238 13:38:21.247316
3239 13:38:21.250465
3240 13:38:21.250550 TX Vref Scan disable
3241 13:38:21.253655 == TX Byte 0 ==
3242 13:38:21.256921 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 13:38:21.260281 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 13:38:21.264060 == TX Byte 1 ==
3245 13:38:21.267444 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3246 13:38:21.270176 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3247 13:38:21.270288 ==
3248 13:38:21.273639 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 13:38:21.280469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 13:38:21.280553 ==
3251 13:38:21.290870 TX Vref=22, minBit 8, minWin=24, winSum=410
3252 13:38:21.294134 TX Vref=24, minBit 10, minWin=24, winSum=415
3253 13:38:21.297512 TX Vref=26, minBit 8, minWin=25, winSum=418
3254 13:38:21.300712 TX Vref=28, minBit 1, minWin=26, winSum=426
3255 13:38:21.304118 TX Vref=30, minBit 9, minWin=25, winSum=425
3256 13:38:21.310844 TX Vref=32, minBit 8, minWin=25, winSum=422
3257 13:38:21.314237 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3258 13:38:21.314320
3259 13:38:21.317608 Final TX Range 1 Vref 28
3260 13:38:21.317693
3261 13:38:21.317757 ==
3262 13:38:21.321131 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 13:38:21.324234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 13:38:21.324317 ==
3265 13:38:21.327637
3266 13:38:21.327719
3267 13:38:21.327784 TX Vref Scan disable
3268 13:38:21.331096 == TX Byte 0 ==
3269 13:38:21.333776 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3270 13:38:21.337601 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3271 13:38:21.340609 == TX Byte 1 ==
3272 13:38:21.343772 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3273 13:38:21.347562 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3274 13:38:21.347645
3275 13:38:21.350691 [DATLAT]
3276 13:38:21.350774 Freq=1200, CH1 RK0
3277 13:38:21.350839
3278 13:38:21.354001 DATLAT Default: 0xd
3279 13:38:21.354106 0, 0xFFFF, sum = 0
3280 13:38:21.357640 1, 0xFFFF, sum = 0
3281 13:38:21.357749 2, 0xFFFF, sum = 0
3282 13:38:21.360568 3, 0xFFFF, sum = 0
3283 13:38:21.360644 4, 0xFFFF, sum = 0
3284 13:38:21.363982 5, 0xFFFF, sum = 0
3285 13:38:21.364057 6, 0xFFFF, sum = 0
3286 13:38:21.367333 7, 0xFFFF, sum = 0
3287 13:38:21.370486 8, 0xFFFF, sum = 0
3288 13:38:21.370570 9, 0xFFFF, sum = 0
3289 13:38:21.374359 10, 0xFFFF, sum = 0
3290 13:38:21.374436 11, 0xFFFF, sum = 0
3291 13:38:21.377897 12, 0x0, sum = 1
3292 13:38:21.377975 13, 0x0, sum = 2
3293 13:38:21.378045 14, 0x0, sum = 3
3294 13:38:21.381206 15, 0x0, sum = 4
3295 13:38:21.381279 best_step = 13
3296 13:38:21.381338
3297 13:38:21.381395 ==
3298 13:38:21.384469 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 13:38:21.391369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 13:38:21.391456 ==
3301 13:38:21.391527 RX Vref Scan: 1
3302 13:38:21.391589
3303 13:38:21.394245 Set Vref Range= 32 -> 127
3304 13:38:21.394322
3305 13:38:21.397405 RX Vref 32 -> 127, step: 1
3306 13:38:21.397476
3307 13:38:21.400692 RX Delay -21 -> 252, step: 4
3308 13:38:21.400764
3309 13:38:21.404131 Set Vref, RX VrefLevel [Byte0]: 32
3310 13:38:21.407365 [Byte1]: 32
3311 13:38:21.407447
3312 13:38:21.410678 Set Vref, RX VrefLevel [Byte0]: 33
3313 13:38:21.414091 [Byte1]: 33
3314 13:38:21.414168
3315 13:38:21.417392 Set Vref, RX VrefLevel [Byte0]: 34
3316 13:38:21.420640 [Byte1]: 34
3317 13:38:21.424764
3318 13:38:21.424842 Set Vref, RX VrefLevel [Byte0]: 35
3319 13:38:21.428174 [Byte1]: 35
3320 13:38:21.432829
3321 13:38:21.432917 Set Vref, RX VrefLevel [Byte0]: 36
3322 13:38:21.436426 [Byte1]: 36
3323 13:38:21.440395
3324 13:38:21.444320 Set Vref, RX VrefLevel [Byte0]: 37
3325 13:38:21.444398 [Byte1]: 37
3326 13:38:21.448755
3327 13:38:21.448846 Set Vref, RX VrefLevel [Byte0]: 38
3328 13:38:21.451920 [Byte1]: 38
3329 13:38:21.456487
3330 13:38:21.456597 Set Vref, RX VrefLevel [Byte0]: 39
3331 13:38:21.459781 [Byte1]: 39
3332 13:38:21.464399
3333 13:38:21.464497 Set Vref, RX VrefLevel [Byte0]: 40
3334 13:38:21.467688 [Byte1]: 40
3335 13:38:21.472917
3336 13:38:21.472993 Set Vref, RX VrefLevel [Byte0]: 41
3337 13:38:21.475837 [Byte1]: 41
3338 13:38:21.480249
3339 13:38:21.480325 Set Vref, RX VrefLevel [Byte0]: 42
3340 13:38:21.483386 [Byte1]: 42
3341 13:38:21.488216
3342 13:38:21.488298 Set Vref, RX VrefLevel [Byte0]: 43
3343 13:38:21.491902 [Byte1]: 43
3344 13:38:21.496430
3345 13:38:21.496534 Set Vref, RX VrefLevel [Byte0]: 44
3346 13:38:21.499447 [Byte1]: 44
3347 13:38:21.504388
3348 13:38:21.504498 Set Vref, RX VrefLevel [Byte0]: 45
3349 13:38:21.507227 [Byte1]: 45
3350 13:38:21.511815
3351 13:38:21.511888 Set Vref, RX VrefLevel [Byte0]: 46
3352 13:38:21.515272 [Byte1]: 46
3353 13:38:21.519851
3354 13:38:21.519927 Set Vref, RX VrefLevel [Byte0]: 47
3355 13:38:21.523142 [Byte1]: 47
3356 13:38:21.527807
3357 13:38:21.527922 Set Vref, RX VrefLevel [Byte0]: 48
3358 13:38:21.531200 [Byte1]: 48
3359 13:38:21.535784
3360 13:38:21.535881 Set Vref, RX VrefLevel [Byte0]: 49
3361 13:38:21.539159 [Byte1]: 49
3362 13:38:21.543866
3363 13:38:21.543933 Set Vref, RX VrefLevel [Byte0]: 50
3364 13:38:21.547199 [Byte1]: 50
3365 13:38:21.551870
3366 13:38:21.551936 Set Vref, RX VrefLevel [Byte0]: 51
3367 13:38:21.555156 [Byte1]: 51
3368 13:38:21.559695
3369 13:38:21.559765 Set Vref, RX VrefLevel [Byte0]: 52
3370 13:38:21.562972 [Byte1]: 52
3371 13:38:21.567644
3372 13:38:21.567751 Set Vref, RX VrefLevel [Byte0]: 53
3373 13:38:21.570968 [Byte1]: 53
3374 13:38:21.575778
3375 13:38:21.575861 Set Vref, RX VrefLevel [Byte0]: 54
3376 13:38:21.578537 [Byte1]: 54
3377 13:38:21.583162
3378 13:38:21.583242 Set Vref, RX VrefLevel [Byte0]: 55
3379 13:38:21.586812 [Byte1]: 55
3380 13:38:21.591293
3381 13:38:21.591414 Set Vref, RX VrefLevel [Byte0]: 56
3382 13:38:21.594505 [Byte1]: 56
3383 13:38:21.598952
3384 13:38:21.599028 Set Vref, RX VrefLevel [Byte0]: 57
3385 13:38:21.602249 [Byte1]: 57
3386 13:38:21.607229
3387 13:38:21.607311 Set Vref, RX VrefLevel [Byte0]: 58
3388 13:38:21.610337 [Byte1]: 58
3389 13:38:21.614970
3390 13:38:21.615074 Set Vref, RX VrefLevel [Byte0]: 59
3391 13:38:21.618231 [Byte1]: 59
3392 13:38:21.622955
3393 13:38:21.623038 Set Vref, RX VrefLevel [Byte0]: 60
3394 13:38:21.626207 [Byte1]: 60
3395 13:38:21.630823
3396 13:38:21.630901 Set Vref, RX VrefLevel [Byte0]: 61
3397 13:38:21.634199 [Byte1]: 61
3398 13:38:21.638822
3399 13:38:21.638897 Set Vref, RX VrefLevel [Byte0]: 62
3400 13:38:21.642216 [Byte1]: 62
3401 13:38:21.647012
3402 13:38:21.647085 Set Vref, RX VrefLevel [Byte0]: 63
3403 13:38:21.649772 [Byte1]: 63
3404 13:38:21.654389
3405 13:38:21.654459 Set Vref, RX VrefLevel [Byte0]: 64
3406 13:38:21.657897 [Byte1]: 64
3407 13:38:21.662801
3408 13:38:21.662873 Set Vref, RX VrefLevel [Byte0]: 65
3409 13:38:21.666121 [Byte1]: 65
3410 13:38:21.670380
3411 13:38:21.670488 Set Vref, RX VrefLevel [Byte0]: 66
3412 13:38:21.673752 [Byte1]: 66
3413 13:38:21.678465
3414 13:38:21.678574 Final RX Vref Byte 0 = 57 to rank0
3415 13:38:21.681961 Final RX Vref Byte 1 = 54 to rank0
3416 13:38:21.685294 Final RX Vref Byte 0 = 57 to rank1
3417 13:38:21.688130 Final RX Vref Byte 1 = 54 to rank1==
3418 13:38:21.692111 Dram Type= 6, Freq= 0, CH_1, rank 0
3419 13:38:21.698614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 13:38:21.698719 ==
3421 13:38:21.698813 DQS Delay:
3422 13:38:21.698906 DQS0 = 0, DQS1 = 0
3423 13:38:21.701996 DQM Delay:
3424 13:38:21.702096 DQM0 = 114, DQM1 = 106
3425 13:38:21.704832 DQ Delay:
3426 13:38:21.708132 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =110
3427 13:38:21.711434 DQ4 =110, DQ5 =126, DQ6 =126, DQ7 =110
3428 13:38:21.714720 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =102
3429 13:38:21.718116 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =112
3430 13:38:21.718211
3431 13:38:21.718280
3432 13:38:21.725093 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3433 13:38:21.728061 CH1 RK0: MR19=303, MR18=EFF6
3434 13:38:21.734901 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3435 13:38:21.734982
3436 13:38:21.738069 ----->DramcWriteLeveling(PI) begin...
3437 13:38:21.738154 ==
3438 13:38:21.741470 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 13:38:21.744864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 13:38:21.748473 ==
3441 13:38:21.748564 Write leveling (Byte 0): 24 => 24
3442 13:38:21.751830 Write leveling (Byte 1): 27 => 27
3443 13:38:21.755145 DramcWriteLeveling(PI) end<-----
3444 13:38:21.755228
3445 13:38:21.755294 ==
3446 13:38:21.758371 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 13:38:21.765009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 13:38:21.765121 ==
3449 13:38:21.765226 [Gating] SW mode calibration
3450 13:38:21.775022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3451 13:38:21.778271 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3452 13:38:21.781617 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3453 13:38:21.788279 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 13:38:21.791728 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 13:38:21.795122 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 13:38:21.801722 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 13:38:21.805104 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3458 13:38:21.808403 0 15 24 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
3459 13:38:21.815173 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3460 13:38:21.818276 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 13:38:21.821880 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 13:38:21.828578 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 13:38:21.831972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 13:38:21.835221 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 13:38:21.841322 1 0 20 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
3466 13:38:21.845309 1 0 24 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
3467 13:38:21.848505 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3468 13:38:21.854869 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 13:38:21.858195 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 13:38:21.861562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 13:38:21.867931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:38:21.871555 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 13:38:21.874727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 13:38:21.881710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 13:38:21.884898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3476 13:38:21.888058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 13:38:21.894688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 13:38:21.897988 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 13:38:21.901349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 13:38:21.904554 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:38:21.911245 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:38:21.914483 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:38:21.917732 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:38:21.924949 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:38:21.927697 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:38:21.931070 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:38:21.937865 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:38:21.941315 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:38:21.944184 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3490 13:38:21.950907 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 13:38:21.954276 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3492 13:38:21.957659 Total UI for P1: 0, mck2ui 16
3493 13:38:21.961004 best dqsien dly found for B0: ( 1, 3, 22)
3494 13:38:21.964229 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 13:38:21.967400 Total UI for P1: 0, mck2ui 16
3496 13:38:21.970584 best dqsien dly found for B1: ( 1, 3, 26)
3497 13:38:21.974097 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3498 13:38:21.980681 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3499 13:38:21.980773
3500 13:38:21.984022 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3501 13:38:21.987376 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3502 13:38:21.990746 [Gating] SW calibration Done
3503 13:38:21.990857 ==
3504 13:38:21.993652 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 13:38:21.996887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 13:38:21.997015 ==
3507 13:38:22.000748 RX Vref Scan: 0
3508 13:38:22.000845
3509 13:38:22.000911 RX Vref 0 -> 0, step: 1
3510 13:38:22.000972
3511 13:38:22.003575 RX Delay -40 -> 252, step: 8
3512 13:38:22.007275 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3513 13:38:22.013779 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3514 13:38:22.017086 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3515 13:38:22.020282 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3516 13:38:22.023804 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3517 13:38:22.026926 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3518 13:38:22.030184 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3519 13:38:22.036794 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3520 13:38:22.040146 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3521 13:38:22.043659 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3522 13:38:22.046953 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3523 13:38:22.050297 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3524 13:38:22.057025 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3525 13:38:22.060359 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3526 13:38:22.063780 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3527 13:38:22.067043 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3528 13:38:22.067152 ==
3529 13:38:22.069724 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 13:38:22.076814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 13:38:22.076915 ==
3532 13:38:22.076986 DQS Delay:
3533 13:38:22.080177 DQS0 = 0, DQS1 = 0
3534 13:38:22.080279 DQM Delay:
3535 13:38:22.083394 DQM0 = 110, DQM1 = 109
3536 13:38:22.083494 DQ Delay:
3537 13:38:22.086235 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3538 13:38:22.089498 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3539 13:38:22.092736 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3540 13:38:22.096469 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3541 13:38:22.096581
3542 13:38:22.096648
3543 13:38:22.096709 ==
3544 13:38:22.099673 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 13:38:22.102905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 13:38:22.106625 ==
3547 13:38:22.106706
3548 13:38:22.106771
3549 13:38:22.106845 TX Vref Scan disable
3550 13:38:22.109796 == TX Byte 0 ==
3551 13:38:22.112947 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3552 13:38:22.116191 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3553 13:38:22.119171 == TX Byte 1 ==
3554 13:38:22.122659 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 13:38:22.126183 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 13:38:22.129269 ==
3557 13:38:22.132486 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 13:38:22.135781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 13:38:22.135916 ==
3560 13:38:22.147729 TX Vref=22, minBit 9, minWin=25, winSum=419
3561 13:38:22.150371 TX Vref=24, minBit 2, minWin=26, winSum=426
3562 13:38:22.154306 TX Vref=26, minBit 0, minWin=26, winSum=433
3563 13:38:22.157148 TX Vref=28, minBit 8, minWin=26, winSum=434
3564 13:38:22.160496 TX Vref=30, minBit 9, minWin=26, winSum=430
3565 13:38:22.167224 TX Vref=32, minBit 9, minWin=25, winSum=430
3566 13:38:22.170627 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3567 13:38:22.170732
3568 13:38:22.174054 Final TX Range 1 Vref 28
3569 13:38:22.174158
3570 13:38:22.174222 ==
3571 13:38:22.177414 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 13:38:22.180665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 13:38:22.183870 ==
3574 13:38:22.183974
3575 13:38:22.184066
3576 13:38:22.184154 TX Vref Scan disable
3577 13:38:22.187198 == TX Byte 0 ==
3578 13:38:22.190504 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3579 13:38:22.193918 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3580 13:38:22.197265 == TX Byte 1 ==
3581 13:38:22.200447 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3582 13:38:22.204149 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3583 13:38:22.207056
3584 13:38:22.207158 [DATLAT]
3585 13:38:22.207254 Freq=1200, CH1 RK1
3586 13:38:22.207344
3587 13:38:22.210505 DATLAT Default: 0xd
3588 13:38:22.210609 0, 0xFFFF, sum = 0
3589 13:38:22.213701 1, 0xFFFF, sum = 0
3590 13:38:22.213808 2, 0xFFFF, sum = 0
3591 13:38:22.217296 3, 0xFFFF, sum = 0
3592 13:38:22.220140 4, 0xFFFF, sum = 0
3593 13:38:22.220249 5, 0xFFFF, sum = 0
3594 13:38:22.223588 6, 0xFFFF, sum = 0
3595 13:38:22.223667 7, 0xFFFF, sum = 0
3596 13:38:22.226839 8, 0xFFFF, sum = 0
3597 13:38:22.226915 9, 0xFFFF, sum = 0
3598 13:38:22.230264 10, 0xFFFF, sum = 0
3599 13:38:22.230371 11, 0xFFFF, sum = 0
3600 13:38:22.233559 12, 0x0, sum = 1
3601 13:38:22.233666 13, 0x0, sum = 2
3602 13:38:22.236659 14, 0x0, sum = 3
3603 13:38:22.236764 15, 0x0, sum = 4
3604 13:38:22.240162 best_step = 13
3605 13:38:22.240264
3606 13:38:22.240359 ==
3607 13:38:22.243724 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 13:38:22.246568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 13:38:22.246652 ==
3610 13:38:22.246717 RX Vref Scan: 0
3611 13:38:22.246778
3612 13:38:22.250232 RX Vref 0 -> 0, step: 1
3613 13:38:22.250327
3614 13:38:22.253690 RX Delay -21 -> 252, step: 4
3615 13:38:22.256803 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3616 13:38:22.263502 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3617 13:38:22.266811 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3618 13:38:22.270230 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3619 13:38:22.273408 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3620 13:38:22.276705 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3621 13:38:22.283227 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3622 13:38:22.286437 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3623 13:38:22.290154 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3624 13:38:22.293439 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3625 13:38:22.296802 iDelay=195, Bit 10, Center 112 (43 ~ 182) 140
3626 13:38:22.302942 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3627 13:38:22.306825 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3628 13:38:22.310005 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3629 13:38:22.313143 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3630 13:38:22.319576 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3631 13:38:22.319706 ==
3632 13:38:22.323027 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 13:38:22.326405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 13:38:22.326526 ==
3635 13:38:22.326608 DQS Delay:
3636 13:38:22.329755 DQS0 = 0, DQS1 = 0
3637 13:38:22.329856 DQM Delay:
3638 13:38:22.333124 DQM0 = 112, DQM1 = 110
3639 13:38:22.333265 DQ Delay:
3640 13:38:22.336367 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =110
3641 13:38:22.339722 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3642 13:38:22.342989 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3643 13:38:22.346392 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3644 13:38:22.346480
3645 13:38:22.346545
3646 13:38:22.356497 [DQSOSCAuto] RK1, (LSB)MR18= 0xf807, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3647 13:38:22.359317 CH1 RK1: MR19=304, MR18=F807
3648 13:38:22.362627 CH1_RK1: MR19=0x304, MR18=0xF807, DQSOSC=407, MR23=63, INC=39, DEC=26
3649 13:38:22.366098 [RxdqsGatingPostProcess] freq 1200
3650 13:38:22.372406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3651 13:38:22.375919 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 13:38:22.379141 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 13:38:22.382498 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 13:38:22.385803 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 13:38:22.389210 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 13:38:22.392657 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 13:38:22.395759 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 13:38:22.399598 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 13:38:22.402864 Pre-setting of DQS Precalculation
3660 13:38:22.405563 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3661 13:38:22.412292 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3662 13:38:22.418775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3663 13:38:22.422298
3664 13:38:22.422401
3665 13:38:22.422469 [Calibration Summary] 2400 Mbps
3666 13:38:22.425474 CH 0, Rank 0
3667 13:38:22.425554 SW Impedance : PASS
3668 13:38:22.429251 DUTY Scan : NO K
3669 13:38:22.432565 ZQ Calibration : PASS
3670 13:38:22.432664 Jitter Meter : NO K
3671 13:38:22.435555 CBT Training : PASS
3672 13:38:22.439124 Write leveling : PASS
3673 13:38:22.439235 RX DQS gating : PASS
3674 13:38:22.442286 RX DQ/DQS(RDDQC) : PASS
3675 13:38:22.445704 TX DQ/DQS : PASS
3676 13:38:22.445832 RX DATLAT : PASS
3677 13:38:22.448937 RX DQ/DQS(Engine): PASS
3678 13:38:22.452307 TX OE : NO K
3679 13:38:22.452433 All Pass.
3680 13:38:22.452528
3681 13:38:22.452640 CH 0, Rank 1
3682 13:38:22.455549 SW Impedance : PASS
3683 13:38:22.459073 DUTY Scan : NO K
3684 13:38:22.459198 ZQ Calibration : PASS
3685 13:38:22.462308 Jitter Meter : NO K
3686 13:38:22.465564 CBT Training : PASS
3687 13:38:22.465676 Write leveling : PASS
3688 13:38:22.468786 RX DQS gating : PASS
3689 13:38:22.468871 RX DQ/DQS(RDDQC) : PASS
3690 13:38:22.472130 TX DQ/DQS : PASS
3691 13:38:22.475293 RX DATLAT : PASS
3692 13:38:22.475417 RX DQ/DQS(Engine): PASS
3693 13:38:22.478836 TX OE : NO K
3694 13:38:22.478962 All Pass.
3695 13:38:22.479068
3696 13:38:22.482005 CH 1, Rank 0
3697 13:38:22.482112 SW Impedance : PASS
3698 13:38:22.485949 DUTY Scan : NO K
3699 13:38:22.488748 ZQ Calibration : PASS
3700 13:38:22.488829 Jitter Meter : NO K
3701 13:38:22.492038 CBT Training : PASS
3702 13:38:22.495390 Write leveling : PASS
3703 13:38:22.495494 RX DQS gating : PASS
3704 13:38:22.498705 RX DQ/DQS(RDDQC) : PASS
3705 13:38:22.502022 TX DQ/DQS : PASS
3706 13:38:22.502127 RX DATLAT : PASS
3707 13:38:22.505010 RX DQ/DQS(Engine): PASS
3708 13:38:22.508808 TX OE : NO K
3709 13:38:22.508915 All Pass.
3710 13:38:22.509010
3711 13:38:22.509074 CH 1, Rank 1
3712 13:38:22.511621 SW Impedance : PASS
3713 13:38:22.515170 DUTY Scan : NO K
3714 13:38:22.515270 ZQ Calibration : PASS
3715 13:38:22.518467 Jitter Meter : NO K
3716 13:38:22.521766 CBT Training : PASS
3717 13:38:22.521851 Write leveling : PASS
3718 13:38:22.525141 RX DQS gating : PASS
3719 13:38:22.528414 RX DQ/DQS(RDDQC) : PASS
3720 13:38:22.528526 TX DQ/DQS : PASS
3721 13:38:22.531818 RX DATLAT : PASS
3722 13:38:22.531906 RX DQ/DQS(Engine): PASS
3723 13:38:22.535008 TX OE : NO K
3724 13:38:22.535129 All Pass.
3725 13:38:22.535222
3726 13:38:22.538340 DramC Write-DBI off
3727 13:38:22.541644 PER_BANK_REFRESH: Hybrid Mode
3728 13:38:22.541760 TX_TRACKING: ON
3729 13:38:22.551252 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3730 13:38:22.554903 [FAST_K] Save calibration result to emmc
3731 13:38:22.557962 dramc_set_vcore_voltage set vcore to 650000
3732 13:38:22.561785 Read voltage for 600, 5
3733 13:38:22.561900 Vio18 = 0
3734 13:38:22.565096 Vcore = 650000
3735 13:38:22.565215 Vdram = 0
3736 13:38:22.565317 Vddq = 0
3737 13:38:22.565409 Vmddr = 0
3738 13:38:22.571420 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3739 13:38:22.578063 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3740 13:38:22.578183 MEM_TYPE=3, freq_sel=19
3741 13:38:22.581414 sv_algorithm_assistance_LP4_1600
3742 13:38:22.584716 ============ PULL DRAM RESETB DOWN ============
3743 13:38:22.591236 ========== PULL DRAM RESETB DOWN end =========
3744 13:38:22.594583 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 13:38:22.597943 ===================================
3746 13:38:22.601269 LPDDR4 DRAM CONFIGURATION
3747 13:38:22.604613 ===================================
3748 13:38:22.604700 EX_ROW_EN[0] = 0x0
3749 13:38:22.607952 EX_ROW_EN[1] = 0x0
3750 13:38:22.608069 LP4Y_EN = 0x0
3751 13:38:22.611294 WORK_FSP = 0x0
3752 13:38:22.611405 WL = 0x2
3753 13:38:22.614430 RL = 0x2
3754 13:38:22.614542 BL = 0x2
3755 13:38:22.617625 RPST = 0x0
3756 13:38:22.620951 RD_PRE = 0x0
3757 13:38:22.621072 WR_PRE = 0x1
3758 13:38:22.624274 WR_PST = 0x0
3759 13:38:22.624385 DBI_WR = 0x0
3760 13:38:22.627697 DBI_RD = 0x0
3761 13:38:22.627776 OTF = 0x1
3762 13:38:22.630975 ===================================
3763 13:38:22.634305 ===================================
3764 13:38:22.637575 ANA top config
3765 13:38:22.637705 ===================================
3766 13:38:22.641040 DLL_ASYNC_EN = 0
3767 13:38:22.644335 ALL_SLAVE_EN = 1
3768 13:38:22.647717 NEW_RANK_MODE = 1
3769 13:38:22.651024 DLL_IDLE_MODE = 1
3770 13:38:22.651110 LP45_APHY_COMB_EN = 1
3771 13:38:22.654311 TX_ODT_DIS = 1
3772 13:38:22.657631 NEW_8X_MODE = 1
3773 13:38:22.661072 ===================================
3774 13:38:22.664145 ===================================
3775 13:38:22.667275 data_rate = 1200
3776 13:38:22.670594 CKR = 1
3777 13:38:22.674104 DQ_P2S_RATIO = 8
3778 13:38:22.677690 ===================================
3779 13:38:22.677800 CA_P2S_RATIO = 8
3780 13:38:22.680954 DQ_CA_OPEN = 0
3781 13:38:22.684036 DQ_SEMI_OPEN = 0
3782 13:38:22.687663 CA_SEMI_OPEN = 0
3783 13:38:22.691127 CA_FULL_RATE = 0
3784 13:38:22.693705 DQ_CKDIV4_EN = 1
3785 13:38:22.693793 CA_CKDIV4_EN = 1
3786 13:38:22.696959 CA_PREDIV_EN = 0
3787 13:38:22.700285 PH8_DLY = 0
3788 13:38:22.703730 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3789 13:38:22.707129 DQ_AAMCK_DIV = 4
3790 13:38:22.710441 CA_AAMCK_DIV = 4
3791 13:38:22.710547 CA_ADMCK_DIV = 4
3792 13:38:22.713879 DQ_TRACK_CA_EN = 0
3793 13:38:22.717127 CA_PICK = 600
3794 13:38:22.720343 CA_MCKIO = 600
3795 13:38:22.723616 MCKIO_SEMI = 0
3796 13:38:22.726700 PLL_FREQ = 2288
3797 13:38:22.730083 DQ_UI_PI_RATIO = 32
3798 13:38:22.730174 CA_UI_PI_RATIO = 0
3799 13:38:22.733359 ===================================
3800 13:38:22.736830 ===================================
3801 13:38:22.740025 memory_type:LPDDR4
3802 13:38:22.743245 GP_NUM : 10
3803 13:38:22.743336 SRAM_EN : 1
3804 13:38:22.746700 MD32_EN : 0
3805 13:38:22.750017 ===================================
3806 13:38:22.753412 [ANA_INIT] >>>>>>>>>>>>>>
3807 13:38:22.756684 <<<<<< [CONFIGURE PHASE]: ANA_TX
3808 13:38:22.759824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3809 13:38:22.762980 ===================================
3810 13:38:22.763056 data_rate = 1200,PCW = 0X5800
3811 13:38:22.766251 ===================================
3812 13:38:22.770150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3813 13:38:22.776490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 13:38:22.783485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 13:38:22.786540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3816 13:38:22.789584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3817 13:38:22.793073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3818 13:38:22.796760 [ANA_INIT] flow start
3819 13:38:22.800039 [ANA_INIT] PLL >>>>>>>>
3820 13:38:22.800148 [ANA_INIT] PLL <<<<<<<<
3821 13:38:22.803310 [ANA_INIT] MIDPI >>>>>>>>
3822 13:38:22.806604 [ANA_INIT] MIDPI <<<<<<<<
3823 13:38:22.806739 [ANA_INIT] DLL >>>>>>>>
3824 13:38:22.809783 [ANA_INIT] flow end
3825 13:38:22.813091 ============ LP4 DIFF to SE enter ============
3826 13:38:22.816424 ============ LP4 DIFF to SE exit ============
3827 13:38:22.819673 [ANA_INIT] <<<<<<<<<<<<<
3828 13:38:22.822874 [Flow] Enable top DCM control >>>>>
3829 13:38:22.826045 [Flow] Enable top DCM control <<<<<
3830 13:38:22.829428 Enable DLL master slave shuffle
3831 13:38:22.835906 ==============================================================
3832 13:38:22.835987 Gating Mode config
3833 13:38:22.842499 ==============================================================
3834 13:38:22.846379 Config description:
3835 13:38:22.852574 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3836 13:38:22.859313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3837 13:38:22.866286 SELPH_MODE 0: By rank 1: By Phase
3838 13:38:22.869443 ==============================================================
3839 13:38:22.872763 GAT_TRACK_EN = 1
3840 13:38:22.876064 RX_GATING_MODE = 2
3841 13:38:22.879404 RX_GATING_TRACK_MODE = 2
3842 13:38:22.882713 SELPH_MODE = 1
3843 13:38:22.886088 PICG_EARLY_EN = 1
3844 13:38:22.889435 VALID_LAT_VALUE = 1
3845 13:38:22.896130 ==============================================================
3846 13:38:22.899421 Enter into Gating configuration >>>>
3847 13:38:22.902521 Exit from Gating configuration <<<<
3848 13:38:22.906043 Enter into DVFS_PRE_config >>>>>
3849 13:38:22.915631 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3850 13:38:22.919075 Exit from DVFS_PRE_config <<<<<
3851 13:38:22.922179 Enter into PICG configuration >>>>
3852 13:38:22.925936 Exit from PICG configuration <<<<
3853 13:38:22.929070 [RX_INPUT] configuration >>>>>
3854 13:38:22.929154 [RX_INPUT] configuration <<<<<
3855 13:38:22.935724 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3856 13:38:22.942216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3857 13:38:22.945536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 13:38:22.952062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 13:38:22.958731 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 13:38:22.965383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 13:38:22.969252 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3862 13:38:22.972315 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3863 13:38:22.978745 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3864 13:38:22.982131 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3865 13:38:22.985291 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3866 13:38:22.991864 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 13:38:22.995088 ===================================
3868 13:38:22.995198 LPDDR4 DRAM CONFIGURATION
3869 13:38:22.998396 ===================================
3870 13:38:23.001806 EX_ROW_EN[0] = 0x0
3871 13:38:23.005210 EX_ROW_EN[1] = 0x0
3872 13:38:23.005292 LP4Y_EN = 0x0
3873 13:38:23.008454 WORK_FSP = 0x0
3874 13:38:23.008536 WL = 0x2
3875 13:38:23.011733 RL = 0x2
3876 13:38:23.011814 BL = 0x2
3877 13:38:23.014954 RPST = 0x0
3878 13:38:23.015035 RD_PRE = 0x0
3879 13:38:23.018138 WR_PRE = 0x1
3880 13:38:23.018253 WR_PST = 0x0
3881 13:38:23.021435 DBI_WR = 0x0
3882 13:38:23.021517 DBI_RD = 0x0
3883 13:38:23.025251 OTF = 0x1
3884 13:38:23.028298 ===================================
3885 13:38:23.031809 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3886 13:38:23.034600 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3887 13:38:23.041272 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 13:38:23.044865 ===================================
3889 13:38:23.044948 LPDDR4 DRAM CONFIGURATION
3890 13:38:23.047998 ===================================
3891 13:38:23.051590 EX_ROW_EN[0] = 0x10
3892 13:38:23.051674 EX_ROW_EN[1] = 0x0
3893 13:38:23.054797 LP4Y_EN = 0x0
3894 13:38:23.058017 WORK_FSP = 0x0
3895 13:38:23.058103 WL = 0x2
3896 13:38:23.061246 RL = 0x2
3897 13:38:23.061322 BL = 0x2
3898 13:38:23.064709 RPST = 0x0
3899 13:38:23.064819 RD_PRE = 0x0
3900 13:38:23.068072 WR_PRE = 0x1
3901 13:38:23.068186 WR_PST = 0x0
3902 13:38:23.071376 DBI_WR = 0x0
3903 13:38:23.071479 DBI_RD = 0x0
3904 13:38:23.074428 OTF = 0x1
3905 13:38:23.077744 ===================================
3906 13:38:23.084436 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3907 13:38:23.087725 nWR fixed to 30
3908 13:38:23.087811 [ModeRegInit_LP4] CH0 RK0
3909 13:38:23.090840 [ModeRegInit_LP4] CH0 RK1
3910 13:38:23.094759 [ModeRegInit_LP4] CH1 RK0
3911 13:38:23.094845 [ModeRegInit_LP4] CH1 RK1
3912 13:38:23.097927 match AC timing 17
3913 13:38:23.101100 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3914 13:38:23.107777 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3915 13:38:23.110945 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3916 13:38:23.114251 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3917 13:38:23.120858 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3918 13:38:23.120942 ==
3919 13:38:23.124127 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 13:38:23.127340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 13:38:23.127413 ==
3922 13:38:23.134143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 13:38:23.140580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3924 13:38:23.143807 [CA 0] Center 37 (7~67) winsize 61
3925 13:38:23.147573 [CA 1] Center 36 (6~67) winsize 62
3926 13:38:23.150512 [CA 2] Center 35 (5~65) winsize 61
3927 13:38:23.154148 [CA 3] Center 35 (5~65) winsize 61
3928 13:38:23.157165 [CA 4] Center 34 (4~65) winsize 62
3929 13:38:23.160749 [CA 5] Center 34 (4~64) winsize 61
3930 13:38:23.160827
3931 13:38:23.164346 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3932 13:38:23.164424
3933 13:38:23.167295 [CATrainingPosCal] consider 1 rank data
3934 13:38:23.170983 u2DelayCellTimex100 = 270/100 ps
3935 13:38:23.174161 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3936 13:38:23.177440 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3937 13:38:23.180646 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3938 13:38:23.183921 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3939 13:38:23.187108 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3940 13:38:23.190288 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3941 13:38:23.190374
3942 13:38:23.197233 CA PerBit enable=1, Macro0, CA PI delay=34
3943 13:38:23.197322
3944 13:38:23.197389 [CBTSetCACLKResult] CA Dly = 34
3945 13:38:23.200369 CS Dly: 5 (0~36)
3946 13:38:23.200453 ==
3947 13:38:23.203735 Dram Type= 6, Freq= 0, CH_0, rank 1
3948 13:38:23.207100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 13:38:23.207186 ==
3950 13:38:23.213688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 13:38:23.220403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3952 13:38:23.223578 [CA 0] Center 37 (7~67) winsize 61
3953 13:38:23.226735 [CA 1] Center 37 (7~67) winsize 61
3954 13:38:23.230084 [CA 2] Center 35 (5~65) winsize 61
3955 13:38:23.233498 [CA 3] Center 35 (5~65) winsize 61
3956 13:38:23.236821 [CA 4] Center 34 (3~65) winsize 63
3957 13:38:23.240195 [CA 5] Center 34 (3~65) winsize 63
3958 13:38:23.240273
3959 13:38:23.243229 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3960 13:38:23.243332
3961 13:38:23.246633 [CATrainingPosCal] consider 2 rank data
3962 13:38:23.249844 u2DelayCellTimex100 = 270/100 ps
3963 13:38:23.252943 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3964 13:38:23.256380 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3965 13:38:23.259731 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3966 13:38:23.262986 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3967 13:38:23.266290 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3968 13:38:23.273281 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3969 13:38:23.273386
3970 13:38:23.276452 CA PerBit enable=1, Macro0, CA PI delay=34
3971 13:38:23.276554
3972 13:38:23.279458 [CBTSetCACLKResult] CA Dly = 34
3973 13:38:23.279563 CS Dly: 5 (0~37)
3974 13:38:23.279653
3975 13:38:23.283056 ----->DramcWriteLeveling(PI) begin...
3976 13:38:23.283161 ==
3977 13:38:23.286123 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 13:38:23.293241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 13:38:23.293320 ==
3980 13:38:23.296301 Write leveling (Byte 0): 32 => 32
3981 13:38:23.296399 Write leveling (Byte 1): 30 => 30
3982 13:38:23.299341 DramcWriteLeveling(PI) end<-----
3983 13:38:23.299417
3984 13:38:23.299483 ==
3985 13:38:23.303029 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 13:38:23.309252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 13:38:23.309366 ==
3988 13:38:23.312569 [Gating] SW mode calibration
3989 13:38:23.319882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3990 13:38:23.322506 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3991 13:38:23.329618 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 13:38:23.333015 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 13:38:23.336338 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 13:38:23.342918 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3995 13:38:23.346298 0 9 16 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
3996 13:38:23.349565 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 13:38:23.356295 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 13:38:23.359555 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 13:38:23.362777 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 13:38:23.366000 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 13:38:23.373151 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 13:38:23.376257 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4003 13:38:23.379599 0 10 16 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4004 13:38:23.386196 0 10 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4005 13:38:23.389254 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 13:38:23.392403 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 13:38:23.399150 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:38:23.402783 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 13:38:23.405875 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 13:38:23.412437 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 13:38:23.415632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4012 13:38:23.418785 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 13:38:23.426157 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:38:23.429346 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:38:23.432043 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:38:23.439083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:38:23.442376 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:38:23.445843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:38:23.452377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:38:23.455588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:38:23.458887 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:38:23.465406 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:38:23.468614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:38:23.472330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:38:23.478922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:38:23.482006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:38:23.485395 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4028 13:38:23.488697 Total UI for P1: 0, mck2ui 16
4029 13:38:23.492000 best dqsien dly found for B0: ( 0, 13, 14)
4030 13:38:23.499021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 13:38:23.499115 Total UI for P1: 0, mck2ui 16
4032 13:38:23.502208 best dqsien dly found for B1: ( 0, 13, 16)
4033 13:38:23.508403 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4034 13:38:23.512057 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4035 13:38:23.512142
4036 13:38:23.515125 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4037 13:38:23.518845 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4038 13:38:23.522026 [Gating] SW calibration Done
4039 13:38:23.522107 ==
4040 13:38:23.525230 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 13:38:23.528925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 13:38:23.529015 ==
4043 13:38:23.532093 RX Vref Scan: 0
4044 13:38:23.532205
4045 13:38:23.532306 RX Vref 0 -> 0, step: 1
4046 13:38:23.532407
4047 13:38:23.535214 RX Delay -230 -> 252, step: 16
4048 13:38:23.538465 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4049 13:38:23.544985 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4050 13:38:23.548339 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4051 13:38:23.551572 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4052 13:38:23.554837 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4053 13:38:23.561995 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4054 13:38:23.564743 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4055 13:38:23.568506 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4056 13:38:23.571766 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4057 13:38:23.577999 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4058 13:38:23.581192 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4059 13:38:23.584375 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4060 13:38:23.588200 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4061 13:38:23.594814 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4062 13:38:23.597922 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4063 13:38:23.601158 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4064 13:38:23.601244 ==
4065 13:38:23.604501 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 13:38:23.607660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 13:38:23.607765 ==
4068 13:38:23.610926 DQS Delay:
4069 13:38:23.611010 DQS0 = 0, DQS1 = 0
4070 13:38:23.614696 DQM Delay:
4071 13:38:23.614779 DQM0 = 37, DQM1 = 29
4072 13:38:23.617976 DQ Delay:
4073 13:38:23.618065 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4074 13:38:23.621067 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4075 13:38:23.623977 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4076 13:38:23.627684 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4077 13:38:23.627786
4078 13:38:23.630686
4079 13:38:23.630770 ==
4080 13:38:23.634373 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 13:38:23.637407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 13:38:23.637485 ==
4083 13:38:23.637550
4084 13:38:23.637609
4085 13:38:23.641064 TX Vref Scan disable
4086 13:38:23.641201 == TX Byte 0 ==
4087 13:38:23.647620 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4088 13:38:23.651173 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4089 13:38:23.651298 == TX Byte 1 ==
4090 13:38:23.657127 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4091 13:38:23.660305 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4092 13:38:23.660422 ==
4093 13:38:23.663537 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 13:38:23.667508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 13:38:23.667608 ==
4096 13:38:23.667674
4097 13:38:23.667735
4098 13:38:23.670680 TX Vref Scan disable
4099 13:38:23.673956 == TX Byte 0 ==
4100 13:38:23.677112 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4101 13:38:23.680387 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4102 13:38:23.683867 == TX Byte 1 ==
4103 13:38:23.687146 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 13:38:23.693555 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 13:38:23.693643
4106 13:38:23.693709 [DATLAT]
4107 13:38:23.693770 Freq=600, CH0 RK0
4108 13:38:23.693830
4109 13:38:23.696876 DATLAT Default: 0x9
4110 13:38:23.696961 0, 0xFFFF, sum = 0
4111 13:38:23.700137 1, 0xFFFF, sum = 0
4112 13:38:23.703304 2, 0xFFFF, sum = 0
4113 13:38:23.703388 3, 0xFFFF, sum = 0
4114 13:38:23.706584 4, 0xFFFF, sum = 0
4115 13:38:23.706668 5, 0xFFFF, sum = 0
4116 13:38:23.709887 6, 0xFFFF, sum = 0
4117 13:38:23.709973 7, 0xFFFF, sum = 0
4118 13:38:23.713120 8, 0x0, sum = 1
4119 13:38:23.713205 9, 0x0, sum = 2
4120 13:38:23.716397 10, 0x0, sum = 3
4121 13:38:23.716482 11, 0x0, sum = 4
4122 13:38:23.716550 best_step = 9
4123 13:38:23.716619
4124 13:38:23.719636 ==
4125 13:38:23.722955 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 13:38:23.726147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 13:38:23.726230 ==
4128 13:38:23.726297 RX Vref Scan: 1
4129 13:38:23.726360
4130 13:38:23.729997 RX Vref 0 -> 0, step: 1
4131 13:38:23.730079
4132 13:38:23.732929 RX Delay -195 -> 252, step: 8
4133 13:38:23.733012
4134 13:38:23.736655 Set Vref, RX VrefLevel [Byte0]: 60
4135 13:38:23.739593 [Byte1]: 55
4136 13:38:23.739677
4137 13:38:23.743194 Final RX Vref Byte 0 = 60 to rank0
4138 13:38:23.746259 Final RX Vref Byte 1 = 55 to rank0
4139 13:38:23.749328 Final RX Vref Byte 0 = 60 to rank1
4140 13:38:23.752928 Final RX Vref Byte 1 = 55 to rank1==
4141 13:38:23.755896 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 13:38:23.759240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 13:38:23.762463 ==
4144 13:38:23.762549 DQS Delay:
4145 13:38:23.762615 DQS0 = 0, DQS1 = 0
4146 13:38:23.766336 DQM Delay:
4147 13:38:23.766419 DQM0 = 34, DQM1 = 29
4148 13:38:23.769568 DQ Delay:
4149 13:38:23.769654 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4150 13:38:23.772717 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4151 13:38:23.776091 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4152 13:38:23.779293 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4153 13:38:23.782641
4154 13:38:23.782736
4155 13:38:23.789217 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4156 13:38:23.792545 CH0 RK0: MR19=808, MR18=3E3D
4157 13:38:23.798972 CH0_RK0: MR19=0x808, MR18=0x3E3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4158 13:38:23.799058
4159 13:38:23.802480 ----->DramcWriteLeveling(PI) begin...
4160 13:38:23.802577 ==
4161 13:38:23.806303 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 13:38:23.809518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 13:38:23.809600 ==
4164 13:38:23.812883 Write leveling (Byte 0): 32 => 32
4165 13:38:23.816117 Write leveling (Byte 1): 32 => 32
4166 13:38:23.818816 DramcWriteLeveling(PI) end<-----
4167 13:38:23.818898
4168 13:38:23.818962 ==
4169 13:38:23.822208 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 13:38:23.825814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 13:38:23.825892 ==
4172 13:38:23.829182 [Gating] SW mode calibration
4173 13:38:23.835671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4174 13:38:23.842579 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4175 13:38:23.845659 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 13:38:23.848880 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 13:38:23.855813 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 13:38:23.858962 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4179 13:38:23.862200 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4180 13:38:23.868832 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 13:38:23.872328 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 13:38:23.875532 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 13:38:23.881917 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 13:38:23.885185 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 13:38:23.889064 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 13:38:23.895874 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4187 13:38:23.899096 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4188 13:38:23.902415 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 13:38:23.908628 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 13:38:23.912357 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 13:38:23.915108 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:38:23.922317 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 13:38:23.925578 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 13:38:23.928746 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4195 13:38:23.935331 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4196 13:38:23.938608 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 13:38:23.941922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:38:23.948315 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:38:23.952175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:38:23.955337 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:38:23.961818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:38:23.965017 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:38:23.968389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:38:23.974773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:38:23.978361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:38:23.981371 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:38:23.987973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:38:23.991652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:38:23.994673 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:38:23.997996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4211 13:38:24.001178 Total UI for P1: 0, mck2ui 16
4212 13:38:24.005127 best dqsien dly found for B0: ( 0, 13, 10)
4213 13:38:24.011697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 13:38:24.014731 Total UI for P1: 0, mck2ui 16
4215 13:38:24.017667 best dqsien dly found for B1: ( 0, 13, 12)
4216 13:38:24.021593 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4217 13:38:24.024784 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4218 13:38:24.024892
4219 13:38:24.028038 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4220 13:38:24.031319 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4221 13:38:24.034792 [Gating] SW calibration Done
4222 13:38:24.034933 ==
4223 13:38:24.037840 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 13:38:24.041220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 13:38:24.041362 ==
4226 13:38:24.044591 RX Vref Scan: 0
4227 13:38:24.044698
4228 13:38:24.047822 RX Vref 0 -> 0, step: 1
4229 13:38:24.047927
4230 13:38:24.051028 RX Delay -230 -> 252, step: 16
4231 13:38:24.054176 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4232 13:38:24.057924 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4233 13:38:24.060799 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4234 13:38:24.064887 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4235 13:38:24.071250 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4236 13:38:24.074564 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4237 13:38:24.077967 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4238 13:38:24.081395 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4239 13:38:24.087698 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4240 13:38:24.091009 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4241 13:38:24.094017 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4242 13:38:24.097660 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4243 13:38:24.104153 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4244 13:38:24.107695 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4245 13:38:24.110468 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4246 13:38:24.113801 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4247 13:38:24.113912 ==
4248 13:38:24.117083 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 13:38:24.124144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 13:38:24.124254 ==
4251 13:38:24.124351 DQS Delay:
4252 13:38:24.127233 DQS0 = 0, DQS1 = 0
4253 13:38:24.127341 DQM Delay:
4254 13:38:24.127434 DQM0 = 33, DQM1 = 28
4255 13:38:24.130361 DQ Delay:
4256 13:38:24.133733 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4257 13:38:24.136994 DQ4 =33, DQ5 =17, DQ6 =41, DQ7 =41
4258 13:38:24.140239 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4259 13:38:24.143553 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4260 13:38:24.143660
4261 13:38:24.143754
4262 13:38:24.143846 ==
4263 13:38:24.146837 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 13:38:24.150198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 13:38:24.150307 ==
4266 13:38:24.150400
4267 13:38:24.150489
4268 13:38:24.153704 TX Vref Scan disable
4269 13:38:24.153811 == TX Byte 0 ==
4270 13:38:24.160088 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4271 13:38:24.163900 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4272 13:38:24.164007 == TX Byte 1 ==
4273 13:38:24.170559 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4274 13:38:24.173720 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4275 13:38:24.173831 ==
4276 13:38:24.176974 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 13:38:24.180210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 13:38:24.180320 ==
4279 13:38:24.183484
4280 13:38:24.183592
4281 13:38:24.183686 TX Vref Scan disable
4282 13:38:24.187308 == TX Byte 0 ==
4283 13:38:24.190756 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4284 13:38:24.196771 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4285 13:38:24.196883 == TX Byte 1 ==
4286 13:38:24.200652 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4287 13:38:24.206882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4288 13:38:24.206993
4289 13:38:24.207087 [DATLAT]
4290 13:38:24.207179 Freq=600, CH0 RK1
4291 13:38:24.207269
4292 13:38:24.210677 DATLAT Default: 0x9
4293 13:38:24.210786 0, 0xFFFF, sum = 0
4294 13:38:24.213429 1, 0xFFFF, sum = 0
4295 13:38:24.213546 2, 0xFFFF, sum = 0
4296 13:38:24.216862 3, 0xFFFF, sum = 0
4297 13:38:24.220666 4, 0xFFFF, sum = 0
4298 13:38:24.220756 5, 0xFFFF, sum = 0
4299 13:38:24.223448 6, 0xFFFF, sum = 0
4300 13:38:24.223558 7, 0xFFFF, sum = 0
4301 13:38:24.226800 8, 0x0, sum = 1
4302 13:38:24.226898 9, 0x0, sum = 2
4303 13:38:24.226968 10, 0x0, sum = 3
4304 13:38:24.230127 11, 0x0, sum = 4
4305 13:38:24.230202 best_step = 9
4306 13:38:24.230265
4307 13:38:24.230332 ==
4308 13:38:24.233742 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 13:38:24.240069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 13:38:24.240149 ==
4311 13:38:24.240217 RX Vref Scan: 0
4312 13:38:24.240282
4313 13:38:24.243392 RX Vref 0 -> 0, step: 1
4314 13:38:24.243477
4315 13:38:24.246825 RX Delay -195 -> 252, step: 8
4316 13:38:24.253042 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4317 13:38:24.256367 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4318 13:38:24.260307 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4319 13:38:24.263005 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4320 13:38:24.266263 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4321 13:38:24.273072 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4322 13:38:24.276429 iDelay=205, Bit 6, Center 40 (-123 ~ 204) 328
4323 13:38:24.279815 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4324 13:38:24.282987 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4325 13:38:24.286863 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4326 13:38:24.293381 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4327 13:38:24.296772 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4328 13:38:24.300134 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4329 13:38:24.303387 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4330 13:38:24.310006 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4331 13:38:24.313155 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4332 13:38:24.313263 ==
4333 13:38:24.316384 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 13:38:24.319708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 13:38:24.319786 ==
4336 13:38:24.322912 DQS Delay:
4337 13:38:24.322980 DQS0 = 0, DQS1 = 0
4338 13:38:24.323041 DQM Delay:
4339 13:38:24.326268 DQM0 = 33, DQM1 = 28
4340 13:38:24.326344 DQ Delay:
4341 13:38:24.329673 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4342 13:38:24.332762 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =40
4343 13:38:24.336580 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4344 13:38:24.339730 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4345 13:38:24.339855
4346 13:38:24.339953
4347 13:38:24.349587 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4348 13:38:24.352863 CH0 RK1: MR19=808, MR18=6A3A
4349 13:38:24.356177 CH0_RK1: MR19=0x808, MR18=0x6A3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4350 13:38:24.360014 [RxdqsGatingPostProcess] freq 600
4351 13:38:24.366116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 13:38:24.369442 Pre-setting of DQS Precalculation
4353 13:38:24.372783 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 13:38:24.372896 ==
4355 13:38:24.375963 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 13:38:24.382972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 13:38:24.383083 ==
4358 13:38:24.386266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 13:38:24.392847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4360 13:38:24.396085 [CA 0] Center 35 (5~66) winsize 62
4361 13:38:24.399333 [CA 1] Center 35 (5~66) winsize 62
4362 13:38:24.402540 [CA 2] Center 34 (4~65) winsize 62
4363 13:38:24.405952 [CA 3] Center 34 (4~65) winsize 62
4364 13:38:24.409223 [CA 4] Center 34 (4~65) winsize 62
4365 13:38:24.412738 [CA 5] Center 33 (3~64) winsize 62
4366 13:38:24.412862
4367 13:38:24.415938 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4368 13:38:24.416053
4369 13:38:24.419040 [CATrainingPosCal] consider 1 rank data
4370 13:38:24.422268 u2DelayCellTimex100 = 270/100 ps
4371 13:38:24.425722 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 13:38:24.432448 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 13:38:24.435472 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 13:38:24.439430 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 13:38:24.442311 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 13:38:24.445652 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 13:38:24.445761
4378 13:38:24.448780 CA PerBit enable=1, Macro0, CA PI delay=33
4379 13:38:24.448887
4380 13:38:24.452656 [CBTSetCACLKResult] CA Dly = 33
4381 13:38:24.455719 CS Dly: 4 (0~35)
4382 13:38:24.455822 ==
4383 13:38:24.459084 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 13:38:24.462297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 13:38:24.462406 ==
4386 13:38:24.468842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 13:38:24.472094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4388 13:38:24.476321 [CA 0] Center 36 (6~66) winsize 61
4389 13:38:24.479594 [CA 1] Center 35 (5~66) winsize 62
4390 13:38:24.482722 [CA 2] Center 34 (4~65) winsize 62
4391 13:38:24.486525 [CA 3] Center 34 (3~65) winsize 63
4392 13:38:24.489657 [CA 4] Center 34 (4~65) winsize 62
4393 13:38:24.492969 [CA 5] Center 34 (3~65) winsize 63
4394 13:38:24.493072
4395 13:38:24.496341 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4396 13:38:24.496447
4397 13:38:24.499571 [CATrainingPosCal] consider 2 rank data
4398 13:38:24.502873 u2DelayCellTimex100 = 270/100 ps
4399 13:38:24.506059 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4400 13:38:24.509272 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 13:38:24.515971 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 13:38:24.519315 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 13:38:24.522668 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 13:38:24.526345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 13:38:24.526452
4406 13:38:24.529717 CA PerBit enable=1, Macro0, CA PI delay=33
4407 13:38:24.529822
4408 13:38:24.532519 [CBTSetCACLKResult] CA Dly = 33
4409 13:38:24.532630 CS Dly: 5 (0~37)
4410 13:38:24.532724
4411 13:38:24.539135 ----->DramcWriteLeveling(PI) begin...
4412 13:38:24.539242 ==
4413 13:38:24.542465 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 13:38:24.545909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 13:38:24.546018 ==
4416 13:38:24.548987 Write leveling (Byte 0): 29 => 29
4417 13:38:24.552685 Write leveling (Byte 1): 30 => 30
4418 13:38:24.555671 DramcWriteLeveling(PI) end<-----
4419 13:38:24.555777
4420 13:38:24.555868 ==
4421 13:38:24.559018 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 13:38:24.562442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 13:38:24.562545 ==
4424 13:38:24.565948 [Gating] SW mode calibration
4425 13:38:24.572159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 13:38:24.579178 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 13:38:24.582373 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 13:38:24.585714 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 13:38:24.592658 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 13:38:24.595454 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 0)
4431 13:38:24.598814 0 9 16 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
4432 13:38:24.605341 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 13:38:24.608772 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 13:38:24.611990 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 13:38:24.615618 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 13:38:24.622070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 13:38:24.625398 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 13:38:24.628482 0 10 12 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (1 1)
4439 13:38:24.635400 0 10 16 | B1->B0 | 4242 4343 | 1 0 | (0 0) (0 0)
4440 13:38:24.638929 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 13:38:24.642083 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 13:38:24.648855 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 13:38:24.652079 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 13:38:24.655356 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 13:38:24.662162 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 13:38:24.665407 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:38:24.668590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 13:38:24.675076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 13:38:24.678186 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 13:38:24.681619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:38:24.688802 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:38:24.691816 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:38:24.694738 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:38:24.701875 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:38:24.705006 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:38:24.708389 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:38:24.715226 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:38:24.718547 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:38:24.721564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:38:24.728117 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:38:24.731418 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:38:24.734751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4463 13:38:24.741650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4464 13:38:24.741734 Total UI for P1: 0, mck2ui 16
4465 13:38:24.748204 best dqsien dly found for B0: ( 0, 13, 12)
4466 13:38:24.751578 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 13:38:24.754846 Total UI for P1: 0, mck2ui 16
4468 13:38:24.757873 best dqsien dly found for B1: ( 0, 13, 14)
4469 13:38:24.761190 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4470 13:38:24.764465 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4471 13:38:24.764585
4472 13:38:24.767821 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4473 13:38:24.771039 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4474 13:38:24.774411 [Gating] SW calibration Done
4475 13:38:24.774512 ==
4476 13:38:24.777846 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 13:38:24.780959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 13:38:24.784460 ==
4479 13:38:24.784566 RX Vref Scan: 0
4480 13:38:24.784676
4481 13:38:24.787745 RX Vref 0 -> 0, step: 1
4482 13:38:24.787850
4483 13:38:24.791411 RX Delay -230 -> 252, step: 16
4484 13:38:24.794434 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4485 13:38:24.798063 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4486 13:38:24.801063 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4487 13:38:24.807688 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4488 13:38:24.810799 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4489 13:38:24.813934 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4490 13:38:24.817318 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4491 13:38:24.820667 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4492 13:38:24.827128 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4493 13:38:24.830862 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4494 13:38:24.834157 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4495 13:38:24.837534 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4496 13:38:24.843965 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4497 13:38:24.847252 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4498 13:38:24.850370 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4499 13:38:24.854263 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4500 13:38:24.854342 ==
4501 13:38:24.857607 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 13:38:24.864150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 13:38:24.864232 ==
4504 13:38:24.864335 DQS Delay:
4505 13:38:24.867523 DQS0 = 0, DQS1 = 0
4506 13:38:24.867602 DQM Delay:
4507 13:38:24.870190 DQM0 = 38, DQM1 = 29
4508 13:38:24.870267 DQ Delay:
4509 13:38:24.873783 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4510 13:38:24.876979 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4511 13:38:24.880360 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4512 13:38:24.883541 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4513 13:38:24.883617
4514 13:38:24.883718
4515 13:38:24.883813 ==
4516 13:38:24.887025 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 13:38:24.890858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 13:38:24.890934 ==
4519 13:38:24.891013
4520 13:38:24.891093
4521 13:38:24.893790 TX Vref Scan disable
4522 13:38:24.896978 == TX Byte 0 ==
4523 13:38:24.900349 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4524 13:38:24.903946 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4525 13:38:24.906997 == TX Byte 1 ==
4526 13:38:24.910372 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 13:38:24.913710 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 13:38:24.913790 ==
4529 13:38:24.917336 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 13:38:24.920422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 13:38:24.923581 ==
4532 13:38:24.923663
4533 13:38:24.923726
4534 13:38:24.923799 TX Vref Scan disable
4535 13:38:24.927703 == TX Byte 0 ==
4536 13:38:24.930572 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4537 13:38:24.937485 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4538 13:38:24.937567 == TX Byte 1 ==
4539 13:38:24.940672 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 13:38:24.947729 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 13:38:24.947812
4542 13:38:24.947930 [DATLAT]
4543 13:38:24.948023 Freq=600, CH1 RK0
4544 13:38:24.948116
4545 13:38:24.951129 DATLAT Default: 0x9
4546 13:38:24.951224 0, 0xFFFF, sum = 0
4547 13:38:24.954348 1, 0xFFFF, sum = 0
4548 13:38:24.957438 2, 0xFFFF, sum = 0
4549 13:38:24.957519 3, 0xFFFF, sum = 0
4550 13:38:24.960593 4, 0xFFFF, sum = 0
4551 13:38:24.960704 5, 0xFFFF, sum = 0
4552 13:38:24.963948 6, 0xFFFF, sum = 0
4553 13:38:24.964029 7, 0xFFFF, sum = 0
4554 13:38:24.967267 8, 0x0, sum = 1
4555 13:38:24.967366 9, 0x0, sum = 2
4556 13:38:24.967461 10, 0x0, sum = 3
4557 13:38:24.970610 11, 0x0, sum = 4
4558 13:38:24.970707 best_step = 9
4559 13:38:24.970830
4560 13:38:24.970904 ==
4561 13:38:24.973845 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 13:38:24.980404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 13:38:24.980527 ==
4564 13:38:24.980641 RX Vref Scan: 1
4565 13:38:24.980719
4566 13:38:24.983627 RX Vref 0 -> 0, step: 1
4567 13:38:24.983708
4568 13:38:24.987094 RX Delay -195 -> 252, step: 8
4569 13:38:24.987177
4570 13:38:24.990352 Set Vref, RX VrefLevel [Byte0]: 57
4571 13:38:24.993663 [Byte1]: 54
4572 13:38:24.993745
4573 13:38:24.997125 Final RX Vref Byte 0 = 57 to rank0
4574 13:38:25.000275 Final RX Vref Byte 1 = 54 to rank0
4575 13:38:25.004003 Final RX Vref Byte 0 = 57 to rank1
4576 13:38:25.006591 Final RX Vref Byte 1 = 54 to rank1==
4577 13:38:25.010470 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 13:38:25.013509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 13:38:25.013593 ==
4580 13:38:25.016593 DQS Delay:
4581 13:38:25.016676 DQS0 = 0, DQS1 = 0
4582 13:38:25.019961 DQM Delay:
4583 13:38:25.020043 DQM0 = 39, DQM1 = 28
4584 13:38:25.023258 DQ Delay:
4585 13:38:25.023340 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4586 13:38:25.026487 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4587 13:38:25.029896 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4588 13:38:25.033048 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4589 13:38:25.033131
4590 13:38:25.036698
4591 13:38:25.043445 [DQSOSCAuto] RK0, (LSB)MR18= 0x2432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4592 13:38:25.046574 CH1 RK0: MR19=808, MR18=2432
4593 13:38:25.053111 CH1_RK0: MR19=0x808, MR18=0x2432, DQSOSC=400, MR23=63, INC=163, DEC=109
4594 13:38:25.053196
4595 13:38:25.056201 ----->DramcWriteLeveling(PI) begin...
4596 13:38:25.056284 ==
4597 13:38:25.059554 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 13:38:25.063453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 13:38:25.063531 ==
4600 13:38:25.066447 Write leveling (Byte 0): 28 => 28
4601 13:38:25.069665 Write leveling (Byte 1): 29 => 29
4602 13:38:25.072803 DramcWriteLeveling(PI) end<-----
4603 13:38:25.072890
4604 13:38:25.072989 ==
4605 13:38:25.076085 Dram Type= 6, Freq= 0, CH_1, rank 1
4606 13:38:25.079358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 13:38:25.079441 ==
4608 13:38:25.082776 [Gating] SW mode calibration
4609 13:38:25.089439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4610 13:38:25.096017 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4611 13:38:25.099908 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 13:38:25.102673 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 13:38:25.109690 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 13:38:25.113079 0 9 12 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (1 0)
4615 13:38:25.116216 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4616 13:38:25.122545 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 13:38:25.126401 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 13:38:25.129695 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 13:38:25.136063 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 13:38:25.139350 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 13:38:25.142577 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4622 13:38:25.149052 0 10 12 | B1->B0 | 2c2c 3a3a | 0 0 | (1 1) (1 1)
4623 13:38:25.152486 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4624 13:38:25.155615 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 13:38:25.162368 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 13:38:25.165627 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 13:38:25.169372 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 13:38:25.175907 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 13:38:25.179074 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 13:38:25.182431 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4631 13:38:25.189055 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 13:38:25.192334 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:38:25.195823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 13:38:25.202553 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 13:38:25.205709 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 13:38:25.209155 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:38:25.215741 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:38:25.218820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:38:25.221999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:38:25.228867 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:38:25.231877 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:38:25.235694 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:38:25.242274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:38:25.245585 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:38:25.248710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:38:25.255363 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4647 13:38:25.258836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 13:38:25.262209 Total UI for P1: 0, mck2ui 16
4649 13:38:25.265464 best dqsien dly found for B0: ( 0, 13, 12)
4650 13:38:25.268814 Total UI for P1: 0, mck2ui 16
4651 13:38:25.272177 best dqsien dly found for B1: ( 0, 13, 12)
4652 13:38:25.275500 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4653 13:38:25.278846 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4654 13:38:25.278940
4655 13:38:25.281702 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4656 13:38:25.285158 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4657 13:38:25.288215 [Gating] SW calibration Done
4658 13:38:25.288330 ==
4659 13:38:25.291730 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 13:38:25.295645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 13:38:25.295747 ==
4662 13:38:25.298098 RX Vref Scan: 0
4663 13:38:25.298181
4664 13:38:25.302025 RX Vref 0 -> 0, step: 1
4665 13:38:25.302108
4666 13:38:25.302172 RX Delay -230 -> 252, step: 16
4667 13:38:25.308881 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4668 13:38:25.311518 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4669 13:38:25.314800 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4670 13:38:25.318698 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4671 13:38:25.325357 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4672 13:38:25.328474 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4673 13:38:25.331449 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4674 13:38:25.335273 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4675 13:38:25.338442 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4676 13:38:25.344757 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4677 13:38:25.348733 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4678 13:38:25.351892 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4679 13:38:25.355003 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4680 13:38:25.361840 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4681 13:38:25.365075 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4682 13:38:25.368285 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4683 13:38:25.368385 ==
4684 13:38:25.371572 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 13:38:25.378083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 13:38:25.378189 ==
4687 13:38:25.378286 DQS Delay:
4688 13:38:25.378347 DQS0 = 0, DQS1 = 0
4689 13:38:25.381309 DQM Delay:
4690 13:38:25.381418 DQM0 = 35, DQM1 = 29
4691 13:38:25.384669 DQ Delay:
4692 13:38:25.387939 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4693 13:38:25.388021 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4694 13:38:25.391127 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4695 13:38:25.398085 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4696 13:38:25.398167
4697 13:38:25.398233
4698 13:38:25.398294 ==
4699 13:38:25.401268 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 13:38:25.404201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 13:38:25.404283 ==
4702 13:38:25.404348
4703 13:38:25.404409
4704 13:38:25.407862 TX Vref Scan disable
4705 13:38:25.407945 == TX Byte 0 ==
4706 13:38:25.414584 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 13:38:25.417769 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 13:38:25.417853 == TX Byte 1 ==
4709 13:38:25.424430 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4710 13:38:25.427597 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4711 13:38:25.427706 ==
4712 13:38:25.431071 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 13:38:25.434253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 13:38:25.434336 ==
4715 13:38:25.434401
4716 13:38:25.437889
4717 13:38:25.437974 TX Vref Scan disable
4718 13:38:25.441043 == TX Byte 0 ==
4719 13:38:25.444278 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4720 13:38:25.451147 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4721 13:38:25.451231 == TX Byte 1 ==
4722 13:38:25.454281 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4723 13:38:25.460854 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4724 13:38:25.460936
4725 13:38:25.461002 [DATLAT]
4726 13:38:25.461062 Freq=600, CH1 RK1
4727 13:38:25.461122
4728 13:38:25.464599 DATLAT Default: 0x9
4729 13:38:25.464682 0, 0xFFFF, sum = 0
4730 13:38:25.467829 1, 0xFFFF, sum = 0
4731 13:38:25.467913 2, 0xFFFF, sum = 0
4732 13:38:25.471174 3, 0xFFFF, sum = 0
4733 13:38:25.474333 4, 0xFFFF, sum = 0
4734 13:38:25.474417 5, 0xFFFF, sum = 0
4735 13:38:25.477818 6, 0xFFFF, sum = 0
4736 13:38:25.477902 7, 0xFFFF, sum = 0
4737 13:38:25.480490 8, 0x0, sum = 1
4738 13:38:25.480607 9, 0x0, sum = 2
4739 13:38:25.480676 10, 0x0, sum = 3
4740 13:38:25.483797 11, 0x0, sum = 4
4741 13:38:25.483880 best_step = 9
4742 13:38:25.483945
4743 13:38:25.484005 ==
4744 13:38:25.487341 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 13:38:25.493959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 13:38:25.494042 ==
4747 13:38:25.494107 RX Vref Scan: 0
4748 13:38:25.494169
4749 13:38:25.497286 RX Vref 0 -> 0, step: 1
4750 13:38:25.497369
4751 13:38:25.500630 RX Delay -195 -> 252, step: 8
4752 13:38:25.503742 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4753 13:38:25.510416 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4754 13:38:25.514270 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4755 13:38:25.517093 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4756 13:38:25.520752 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4757 13:38:25.527384 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4758 13:38:25.530604 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4759 13:38:25.533930 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4760 13:38:25.537277 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4761 13:38:25.543616 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4762 13:38:25.546682 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4763 13:38:25.550690 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4764 13:38:25.553752 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4765 13:38:25.556773 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4766 13:38:25.563652 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4767 13:38:25.566849 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4768 13:38:25.566932 ==
4769 13:38:25.569932 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 13:38:25.573176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 13:38:25.573264 ==
4772 13:38:25.577009 DQS Delay:
4773 13:38:25.577092 DQS0 = 0, DQS1 = 0
4774 13:38:25.580170 DQM Delay:
4775 13:38:25.580253 DQM0 = 35, DQM1 = 31
4776 13:38:25.580318 DQ Delay:
4777 13:38:25.583420 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4778 13:38:25.586921 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =32
4779 13:38:25.589590 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4780 13:38:25.592957 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4781 13:38:25.593044
4782 13:38:25.593109
4783 13:38:25.603336 [DQSOSCAuto] RK1, (LSB)MR18= 0x3655, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4784 13:38:25.606772 CH1 RK1: MR19=808, MR18=3655
4785 13:38:25.613165 CH1_RK1: MR19=0x808, MR18=0x3655, DQSOSC=393, MR23=63, INC=169, DEC=113
4786 13:38:25.616612 [RxdqsGatingPostProcess] freq 600
4787 13:38:25.619951 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4788 13:38:25.623110 Pre-setting of DQS Precalculation
4789 13:38:25.626316 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4790 13:38:25.636174 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4791 13:38:25.642843 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4792 13:38:25.642967
4793 13:38:25.643059
4794 13:38:25.646202 [Calibration Summary] 1200 Mbps
4795 13:38:25.646286 CH 0, Rank 0
4796 13:38:25.649596 SW Impedance : PASS
4797 13:38:25.652879 DUTY Scan : NO K
4798 13:38:25.652964 ZQ Calibration : PASS
4799 13:38:25.655968 Jitter Meter : NO K
4800 13:38:25.659255 CBT Training : PASS
4801 13:38:25.659341 Write leveling : PASS
4802 13:38:25.662302 RX DQS gating : PASS
4803 13:38:25.662386 RX DQ/DQS(RDDQC) : PASS
4804 13:38:25.665627 TX DQ/DQS : PASS
4805 13:38:25.668970 RX DATLAT : PASS
4806 13:38:25.669058 RX DQ/DQS(Engine): PASS
4807 13:38:25.672201 TX OE : NO K
4808 13:38:25.672286 All Pass.
4809 13:38:25.672352
4810 13:38:25.675910 CH 0, Rank 1
4811 13:38:25.676000 SW Impedance : PASS
4812 13:38:25.679116 DUTY Scan : NO K
4813 13:38:25.682612 ZQ Calibration : PASS
4814 13:38:25.682699 Jitter Meter : NO K
4815 13:38:25.685365 CBT Training : PASS
4816 13:38:25.688687 Write leveling : PASS
4817 13:38:25.688797 RX DQS gating : PASS
4818 13:38:25.692658 RX DQ/DQS(RDDQC) : PASS
4819 13:38:25.695358 TX DQ/DQS : PASS
4820 13:38:25.695443 RX DATLAT : PASS
4821 13:38:25.698710 RX DQ/DQS(Engine): PASS
4822 13:38:25.702150 TX OE : NO K
4823 13:38:25.702233 All Pass.
4824 13:38:25.702299
4825 13:38:25.702361 CH 1, Rank 0
4826 13:38:25.705409 SW Impedance : PASS
4827 13:38:25.708847 DUTY Scan : NO K
4828 13:38:25.708929 ZQ Calibration : PASS
4829 13:38:25.712073 Jitter Meter : NO K
4830 13:38:25.715315 CBT Training : PASS
4831 13:38:25.715398 Write leveling : PASS
4832 13:38:25.718645 RX DQS gating : PASS
4833 13:38:25.718758 RX DQ/DQS(RDDQC) : PASS
4834 13:38:25.721791 TX DQ/DQS : PASS
4835 13:38:25.725133 RX DATLAT : PASS
4836 13:38:25.725219 RX DQ/DQS(Engine): PASS
4837 13:38:25.728458 TX OE : NO K
4838 13:38:25.728542 All Pass.
4839 13:38:25.728615
4840 13:38:25.731692 CH 1, Rank 1
4841 13:38:25.734796 SW Impedance : PASS
4842 13:38:25.734909 DUTY Scan : NO K
4843 13:38:25.738115 ZQ Calibration : PASS
4844 13:38:25.738208 Jitter Meter : NO K
4845 13:38:25.741967 CBT Training : PASS
4846 13:38:25.745385 Write leveling : PASS
4847 13:38:25.745507 RX DQS gating : PASS
4848 13:38:25.748042 RX DQ/DQS(RDDQC) : PASS
4849 13:38:25.751316 TX DQ/DQS : PASS
4850 13:38:25.751440 RX DATLAT : PASS
4851 13:38:25.754824 RX DQ/DQS(Engine): PASS
4852 13:38:25.758075 TX OE : NO K
4853 13:38:25.758222 All Pass.
4854 13:38:25.758322
4855 13:38:25.761289 DramC Write-DBI off
4856 13:38:25.761422 PER_BANK_REFRESH: Hybrid Mode
4857 13:38:25.764605 TX_TRACKING: ON
4858 13:38:25.771674 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4859 13:38:25.778220 [FAST_K] Save calibration result to emmc
4860 13:38:25.781432 dramc_set_vcore_voltage set vcore to 662500
4861 13:38:25.781517 Read voltage for 933, 3
4862 13:38:25.784396 Vio18 = 0
4863 13:38:25.784479 Vcore = 662500
4864 13:38:25.784545 Vdram = 0
4865 13:38:25.787996 Vddq = 0
4866 13:38:25.788088 Vmddr = 0
4867 13:38:25.791169 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4868 13:38:25.797759 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4869 13:38:25.801261 MEM_TYPE=3, freq_sel=17
4870 13:38:25.804610 sv_algorithm_assistance_LP4_1600
4871 13:38:25.808009 ============ PULL DRAM RESETB DOWN ============
4872 13:38:25.811252 ========== PULL DRAM RESETB DOWN end =========
4873 13:38:25.817781 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4874 13:38:25.821096 ===================================
4875 13:38:25.821175 LPDDR4 DRAM CONFIGURATION
4876 13:38:25.824283 ===================================
4877 13:38:25.827584 EX_ROW_EN[0] = 0x0
4878 13:38:25.827657 EX_ROW_EN[1] = 0x0
4879 13:38:25.830889 LP4Y_EN = 0x0
4880 13:38:25.830962 WORK_FSP = 0x0
4881 13:38:25.834460 WL = 0x3
4882 13:38:25.837625 RL = 0x3
4883 13:38:25.837698 BL = 0x2
4884 13:38:25.840820 RPST = 0x0
4885 13:38:25.840892 RD_PRE = 0x0
4886 13:38:25.844474 WR_PRE = 0x1
4887 13:38:25.844550 WR_PST = 0x0
4888 13:38:25.847823 DBI_WR = 0x0
4889 13:38:25.847895 DBI_RD = 0x0
4890 13:38:25.851211 OTF = 0x1
4891 13:38:25.854522 ===================================
4892 13:38:25.857739 ===================================
4893 13:38:25.857818 ANA top config
4894 13:38:25.860602 ===================================
4895 13:38:25.864041 DLL_ASYNC_EN = 0
4896 13:38:25.867370 ALL_SLAVE_EN = 1
4897 13:38:25.867452 NEW_RANK_MODE = 1
4898 13:38:25.870427 DLL_IDLE_MODE = 1
4899 13:38:25.874203 LP45_APHY_COMB_EN = 1
4900 13:38:25.877461 TX_ODT_DIS = 1
4901 13:38:25.880580 NEW_8X_MODE = 1
4902 13:38:25.883987 ===================================
4903 13:38:25.887324 ===================================
4904 13:38:25.887405 data_rate = 1866
4905 13:38:25.890577 CKR = 1
4906 13:38:25.893707 DQ_P2S_RATIO = 8
4907 13:38:25.897536 ===================================
4908 13:38:25.900703 CA_P2S_RATIO = 8
4909 13:38:25.903946 DQ_CA_OPEN = 0
4910 13:38:25.907349 DQ_SEMI_OPEN = 0
4911 13:38:25.907430 CA_SEMI_OPEN = 0
4912 13:38:25.910904 CA_FULL_RATE = 0
4913 13:38:25.913513 DQ_CKDIV4_EN = 1
4914 13:38:25.916878 CA_CKDIV4_EN = 1
4915 13:38:25.920175 CA_PREDIV_EN = 0
4916 13:38:25.923483 PH8_DLY = 0
4917 13:38:25.923564 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4918 13:38:25.926917 DQ_AAMCK_DIV = 4
4919 13:38:25.930366 CA_AAMCK_DIV = 4
4920 13:38:25.933561 CA_ADMCK_DIV = 4
4921 13:38:25.936888 DQ_TRACK_CA_EN = 0
4922 13:38:25.940113 CA_PICK = 933
4923 13:38:25.943404 CA_MCKIO = 933
4924 13:38:25.943486 MCKIO_SEMI = 0
4925 13:38:25.946800 PLL_FREQ = 3732
4926 13:38:25.950121 DQ_UI_PI_RATIO = 32
4927 13:38:25.953326 CA_UI_PI_RATIO = 0
4928 13:38:25.956616 ===================================
4929 13:38:25.960028 ===================================
4930 13:38:25.963463 memory_type:LPDDR4
4931 13:38:25.963544 GP_NUM : 10
4932 13:38:25.968611 SRAM_EN : 1
4933 13:38:25.968745 MD32_EN : 0
4934 13:38:25.970168 ===================================
4935 13:38:25.973280 [ANA_INIT] >>>>>>>>>>>>>>
4936 13:38:25.976509 <<<<<< [CONFIGURE PHASE]: ANA_TX
4937 13:38:25.980282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4938 13:38:25.983633 ===================================
4939 13:38:25.986770 data_rate = 1866,PCW = 0X8f00
4940 13:38:25.989946 ===================================
4941 13:38:25.993330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4942 13:38:26.000086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 13:38:26.003309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 13:38:26.009793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4945 13:38:26.013044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4946 13:38:26.016448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4947 13:38:26.016551 [ANA_INIT] flow start
4948 13:38:26.019737 [ANA_INIT] PLL >>>>>>>>
4949 13:38:26.023115 [ANA_INIT] PLL <<<<<<<<
4950 13:38:26.023189 [ANA_INIT] MIDPI >>>>>>>>
4951 13:38:26.026435 [ANA_INIT] MIDPI <<<<<<<<
4952 13:38:26.029792 [ANA_INIT] DLL >>>>>>>>
4953 13:38:26.029876 [ANA_INIT] flow end
4954 13:38:26.036427 ============ LP4 DIFF to SE enter ============
4955 13:38:26.039772 ============ LP4 DIFF to SE exit ============
4956 13:38:26.043176 [ANA_INIT] <<<<<<<<<<<<<
4957 13:38:26.046472 [Flow] Enable top DCM control >>>>>
4958 13:38:26.049737 [Flow] Enable top DCM control <<<<<
4959 13:38:26.049840 Enable DLL master slave shuffle
4960 13:38:26.056304 ==============================================================
4961 13:38:26.059774 Gating Mode config
4962 13:38:26.062491 ==============================================================
4963 13:38:26.065877 Config description:
4964 13:38:26.076059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4965 13:38:26.082433 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4966 13:38:26.086062 SELPH_MODE 0: By rank 1: By Phase
4967 13:38:26.092464 ==============================================================
4968 13:38:26.095723 GAT_TRACK_EN = 1
4969 13:38:26.098984 RX_GATING_MODE = 2
4970 13:38:26.102312 RX_GATING_TRACK_MODE = 2
4971 13:38:26.105728 SELPH_MODE = 1
4972 13:38:26.108914 PICG_EARLY_EN = 1
4973 13:38:26.109039 VALID_LAT_VALUE = 1
4974 13:38:26.116118 ==============================================================
4975 13:38:26.119327 Enter into Gating configuration >>>>
4976 13:38:26.122684 Exit from Gating configuration <<<<
4977 13:38:26.125875 Enter into DVFS_PRE_config >>>>>
4978 13:38:26.135770 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4979 13:38:26.139221 Exit from DVFS_PRE_config <<<<<
4980 13:38:26.142489 Enter into PICG configuration >>>>
4981 13:38:26.145676 Exit from PICG configuration <<<<
4982 13:38:26.148811 [RX_INPUT] configuration >>>>>
4983 13:38:26.152090 [RX_INPUT] configuration <<<<<
4984 13:38:26.159054 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4985 13:38:26.162431 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4986 13:38:26.169021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 13:38:26.175680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 13:38:26.181713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 13:38:26.188361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 13:38:26.192361 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4991 13:38:26.195379 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4992 13:38:26.198620 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4993 13:38:26.205487 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4994 13:38:26.208541 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4995 13:38:26.211826 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 13:38:26.215184 ===================================
4997 13:38:26.218310 LPDDR4 DRAM CONFIGURATION
4998 13:38:26.221508 ===================================
4999 13:38:26.221592 EX_ROW_EN[0] = 0x0
5000 13:38:26.224812 EX_ROW_EN[1] = 0x0
5001 13:38:26.228151 LP4Y_EN = 0x0
5002 13:38:26.228233 WORK_FSP = 0x0
5003 13:38:26.231487 WL = 0x3
5004 13:38:26.231630 RL = 0x3
5005 13:38:26.235372 BL = 0x2
5006 13:38:26.235484 RPST = 0x0
5007 13:38:26.238705 RD_PRE = 0x0
5008 13:38:26.238787 WR_PRE = 0x1
5009 13:38:26.241357 WR_PST = 0x0
5010 13:38:26.241432 DBI_WR = 0x0
5011 13:38:26.244833 DBI_RD = 0x0
5012 13:38:26.244916 OTF = 0x1
5013 13:38:26.248175 ===================================
5014 13:38:26.251542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5015 13:38:26.257958 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5016 13:38:26.261058 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5017 13:38:26.264767 ===================================
5018 13:38:26.268053 LPDDR4 DRAM CONFIGURATION
5019 13:38:26.271430 ===================================
5020 13:38:26.271512 EX_ROW_EN[0] = 0x10
5021 13:38:26.274686 EX_ROW_EN[1] = 0x0
5022 13:38:26.277983 LP4Y_EN = 0x0
5023 13:38:26.278082 WORK_FSP = 0x0
5024 13:38:26.281403 WL = 0x3
5025 13:38:26.281492 RL = 0x3
5026 13:38:26.284723 BL = 0x2
5027 13:38:26.284807 RPST = 0x0
5028 13:38:26.287977 RD_PRE = 0x0
5029 13:38:26.288060 WR_PRE = 0x1
5030 13:38:26.291362 WR_PST = 0x0
5031 13:38:26.291443 DBI_WR = 0x0
5032 13:38:26.294734 DBI_RD = 0x0
5033 13:38:26.294815 OTF = 0x1
5034 13:38:26.298107 ===================================
5035 13:38:26.304307 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5036 13:38:26.308306 nWR fixed to 30
5037 13:38:26.311536 [ModeRegInit_LP4] CH0 RK0
5038 13:38:26.311610 [ModeRegInit_LP4] CH0 RK1
5039 13:38:26.315264 [ModeRegInit_LP4] CH1 RK0
5040 13:38:26.318304 [ModeRegInit_LP4] CH1 RK1
5041 13:38:26.318378 match AC timing 9
5042 13:38:26.324799 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5043 13:38:26.328639 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5044 13:38:26.331754 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5045 13:38:26.338442 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5046 13:38:26.341766 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5047 13:38:26.341840 ==
5048 13:38:26.345195 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 13:38:26.348630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 13:38:26.348697 ==
5051 13:38:26.354798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 13:38:26.361352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 13:38:26.364704 [CA 0] Center 38 (8~69) winsize 62
5054 13:38:26.367926 [CA 1] Center 38 (8~69) winsize 62
5055 13:38:26.371651 [CA 2] Center 35 (5~66) winsize 62
5056 13:38:26.374716 [CA 3] Center 35 (5~66) winsize 62
5057 13:38:26.378414 [CA 4] Center 34 (4~64) winsize 61
5058 13:38:26.381433 [CA 5] Center 33 (3~64) winsize 62
5059 13:38:26.381534
5060 13:38:26.384699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 13:38:26.384772
5062 13:38:26.387983 [CATrainingPosCal] consider 1 rank data
5063 13:38:26.391366 u2DelayCellTimex100 = 270/100 ps
5064 13:38:26.394675 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5065 13:38:26.398052 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5066 13:38:26.401357 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5067 13:38:26.404551 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5068 13:38:26.407947 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5069 13:38:26.414329 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5070 13:38:26.414407
5071 13:38:26.417846 CA PerBit enable=1, Macro0, CA PI delay=33
5072 13:38:26.417915
5073 13:38:26.421522 [CBTSetCACLKResult] CA Dly = 33
5074 13:38:26.421619 CS Dly: 7 (0~38)
5075 13:38:26.421682 ==
5076 13:38:26.424616 Dram Type= 6, Freq= 0, CH_0, rank 1
5077 13:38:26.427653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 13:38:26.430755 ==
5079 13:38:26.433966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 13:38:26.441142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5081 13:38:26.444292 [CA 0] Center 38 (8~69) winsize 62
5082 13:38:26.447461 [CA 1] Center 38 (8~69) winsize 62
5083 13:38:26.450778 [CA 2] Center 35 (5~66) winsize 62
5084 13:38:26.454093 [CA 3] Center 35 (5~66) winsize 62
5085 13:38:26.457451 [CA 4] Center 34 (4~65) winsize 62
5086 13:38:26.460720 [CA 5] Center 34 (4~64) winsize 61
5087 13:38:26.460817
5088 13:38:26.464021 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5089 13:38:26.464091
5090 13:38:26.467277 [CATrainingPosCal] consider 2 rank data
5091 13:38:26.470703 u2DelayCellTimex100 = 270/100 ps
5092 13:38:26.474041 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5093 13:38:26.477305 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5094 13:38:26.483585 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5095 13:38:26.486730 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5096 13:38:26.490445 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5097 13:38:26.493510 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5098 13:38:26.493584
5099 13:38:26.496765 CA PerBit enable=1, Macro0, CA PI delay=34
5100 13:38:26.496871
5101 13:38:26.500075 [CBTSetCACLKResult] CA Dly = 34
5102 13:38:26.500172 CS Dly: 7 (0~39)
5103 13:38:26.500269
5104 13:38:26.503449 ----->DramcWriteLeveling(PI) begin...
5105 13:38:26.506809 ==
5106 13:38:26.510239 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 13:38:26.513110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 13:38:26.513187 ==
5109 13:38:26.517079 Write leveling (Byte 0): 29 => 29
5110 13:38:26.520202 Write leveling (Byte 1): 29 => 29
5111 13:38:26.522976 DramcWriteLeveling(PI) end<-----
5112 13:38:26.523057
5113 13:38:26.523141 ==
5114 13:38:26.526391 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 13:38:26.529656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 13:38:26.529731 ==
5117 13:38:26.533381 [Gating] SW mode calibration
5118 13:38:26.539655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5119 13:38:26.546546 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5120 13:38:26.549753 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5121 13:38:26.553007 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
5122 13:38:26.559659 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 13:38:26.562815 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 13:38:26.566072 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 13:38:26.572823 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 13:38:26.576258 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 13:38:26.579585 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5128 13:38:26.586099 0 15 0 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 1)
5129 13:38:26.589299 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5130 13:38:26.592777 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 13:38:26.599344 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 13:38:26.602658 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 13:38:26.605675 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 13:38:26.612343 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 13:38:26.615724 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 13:38:26.619084 1 0 0 | B1->B0 | 3131 3f3f | 0 0 | (0 0) (0 0)
5137 13:38:26.625536 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5138 13:38:26.629184 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 13:38:26.632536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 13:38:26.639046 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 13:38:26.642081 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 13:38:26.645658 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 13:38:26.648803 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 13:38:26.655900 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5145 13:38:26.659008 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 13:38:26.662218 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 13:38:26.669112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 13:38:26.672452 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 13:38:26.675833 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:38:26.681929 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:38:26.685141 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:38:26.688420 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:38:26.695046 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:38:26.698424 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:38:26.701715 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:38:26.708945 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:38:26.712150 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:38:26.715342 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:38:26.722216 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:38:26.724958 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5161 13:38:26.728982 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 13:38:26.731509 Total UI for P1: 0, mck2ui 16
5163 13:38:26.735252 best dqsien dly found for B0: ( 1, 3, 0)
5164 13:38:26.738445 Total UI for P1: 0, mck2ui 16
5165 13:38:26.741808 best dqsien dly found for B1: ( 1, 3, 2)
5166 13:38:26.745095 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5167 13:38:26.748373 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5168 13:38:26.748539
5169 13:38:26.754758 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5170 13:38:26.758252 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5171 13:38:26.758355 [Gating] SW calibration Done
5172 13:38:26.761630 ==
5173 13:38:26.764824 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 13:38:26.768128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 13:38:26.768218 ==
5176 13:38:26.768323 RX Vref Scan: 0
5177 13:38:26.768421
5178 13:38:26.771835 RX Vref 0 -> 0, step: 1
5179 13:38:26.771919
5180 13:38:26.774964 RX Delay -80 -> 252, step: 8
5181 13:38:26.778175 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5182 13:38:26.781265 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5183 13:38:26.784463 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5184 13:38:26.791080 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5185 13:38:26.795017 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5186 13:38:26.798392 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5187 13:38:26.801162 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5188 13:38:26.805065 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5189 13:38:26.807771 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5190 13:38:26.814421 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5191 13:38:26.817836 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5192 13:38:26.821251 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5193 13:38:26.824356 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5194 13:38:26.827544 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5195 13:38:26.834840 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5196 13:38:26.838279 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5197 13:38:26.838370 ==
5198 13:38:26.840915 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 13:38:26.844770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 13:38:26.844861 ==
5201 13:38:26.847436 DQS Delay:
5202 13:38:26.847541 DQS0 = 0, DQS1 = 0
5203 13:38:26.847636 DQM Delay:
5204 13:38:26.850784 DQM0 = 94, DQM1 = 83
5205 13:38:26.850893 DQ Delay:
5206 13:38:26.854212 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =87
5207 13:38:26.857679 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5208 13:38:26.860971 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5209 13:38:26.864048 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5210 13:38:26.864120
5211 13:38:26.864181
5212 13:38:26.864244 ==
5213 13:38:26.867855 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 13:38:26.874093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 13:38:26.874173 ==
5216 13:38:26.874236
5217 13:38:26.874295
5218 13:38:26.874351 TX Vref Scan disable
5219 13:38:26.877927 == TX Byte 0 ==
5220 13:38:26.881685 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5221 13:38:26.888095 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5222 13:38:26.888202 == TX Byte 1 ==
5223 13:38:26.891224 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 13:38:26.897968 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 13:38:26.898048 ==
5226 13:38:26.901252 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 13:38:26.904742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 13:38:26.904815 ==
5229 13:38:26.904879
5230 13:38:26.904937
5231 13:38:26.907904 TX Vref Scan disable
5232 13:38:26.907973 == TX Byte 0 ==
5233 13:38:26.914485 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5234 13:38:26.917846 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5235 13:38:26.917933 == TX Byte 1 ==
5236 13:38:26.924561 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5237 13:38:26.927930 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5238 13:38:26.928010
5239 13:38:26.928073 [DATLAT]
5240 13:38:26.931060 Freq=933, CH0 RK0
5241 13:38:26.931150
5242 13:38:26.931217 DATLAT Default: 0xd
5243 13:38:26.934311 0, 0xFFFF, sum = 0
5244 13:38:26.934392 1, 0xFFFF, sum = 0
5245 13:38:26.937585 2, 0xFFFF, sum = 0
5246 13:38:26.940869 3, 0xFFFF, sum = 0
5247 13:38:26.940950 4, 0xFFFF, sum = 0
5248 13:38:26.944174 5, 0xFFFF, sum = 0
5249 13:38:26.944282 6, 0xFFFF, sum = 0
5250 13:38:26.947406 7, 0xFFFF, sum = 0
5251 13:38:26.947523 8, 0xFFFF, sum = 0
5252 13:38:26.950819 9, 0xFFFF, sum = 0
5253 13:38:26.950902 10, 0x0, sum = 1
5254 13:38:26.953853 11, 0x0, sum = 2
5255 13:38:26.953942 12, 0x0, sum = 3
5256 13:38:26.957129 13, 0x0, sum = 4
5257 13:38:26.957237 best_step = 11
5258 13:38:26.957327
5259 13:38:26.957414 ==
5260 13:38:26.960489 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 13:38:26.963888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 13:38:26.963993 ==
5263 13:38:26.967171 RX Vref Scan: 1
5264 13:38:26.967272
5265 13:38:26.970441 RX Vref 0 -> 0, step: 1
5266 13:38:26.970537
5267 13:38:26.970632 RX Delay -69 -> 252, step: 4
5268 13:38:26.970717
5269 13:38:26.974252 Set Vref, RX VrefLevel [Byte0]: 60
5270 13:38:26.977318 [Byte1]: 55
5271 13:38:26.982162
5272 13:38:26.982276 Final RX Vref Byte 0 = 60 to rank0
5273 13:38:26.985346 Final RX Vref Byte 1 = 55 to rank0
5274 13:38:26.988530 Final RX Vref Byte 0 = 60 to rank1
5275 13:38:26.991852 Final RX Vref Byte 1 = 55 to rank1==
5276 13:38:26.994790 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 13:38:27.001872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 13:38:27.001953 ==
5279 13:38:27.002019 DQS Delay:
5280 13:38:27.005020 DQS0 = 0, DQS1 = 0
5281 13:38:27.005094 DQM Delay:
5282 13:38:27.005156 DQM0 = 96, DQM1 = 84
5283 13:38:27.008296 DQ Delay:
5284 13:38:27.011597 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5285 13:38:27.014765 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =108
5286 13:38:27.018095 DQ8 =80, DQ9 =72, DQ10 =82, DQ11 =80
5287 13:38:27.021451 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =88
5288 13:38:27.021521
5289 13:38:27.021582
5290 13:38:27.028191 [DQSOSCAuto] RK0, (LSB)MR18= 0x1817, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5291 13:38:27.031584 CH0 RK0: MR19=505, MR18=1817
5292 13:38:27.038353 CH0_RK0: MR19=0x505, MR18=0x1817, DQSOSC=414, MR23=63, INC=63, DEC=42
5293 13:38:27.038428
5294 13:38:27.041650 ----->DramcWriteLeveling(PI) begin...
5295 13:38:27.041723 ==
5296 13:38:27.044915 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 13:38:27.048182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 13:38:27.048266 ==
5299 13:38:27.051420 Write leveling (Byte 0): 30 => 30
5300 13:38:27.054690 Write leveling (Byte 1): 28 => 28
5301 13:38:27.057920 DramcWriteLeveling(PI) end<-----
5302 13:38:27.057992
5303 13:38:27.058057 ==
5304 13:38:27.061709 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 13:38:27.065046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 13:38:27.065139 ==
5307 13:38:27.068342 [Gating] SW mode calibration
5308 13:38:27.074996 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 13:38:27.081449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 13:38:27.084599 0 14 0 | B1->B0 | 2827 3434 | 1 1 | (0 0) (1 1)
5311 13:38:27.090973 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 13:38:27.094135 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 13:38:27.098066 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 13:38:27.104127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 13:38:27.107426 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 13:38:27.110645 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 13:38:27.117610 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
5318 13:38:27.120873 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5319 13:38:27.124199 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 13:38:27.130906 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 13:38:27.134340 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 13:38:27.137612 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 13:38:27.143865 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 13:38:27.147187 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 13:38:27.150523 0 15 28 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
5326 13:38:27.157608 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5327 13:38:27.160860 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 13:38:27.164195 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 13:38:27.170396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 13:38:27.173743 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 13:38:27.177067 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 13:38:27.180317 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 13:38:27.186935 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5334 13:38:27.190364 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5335 13:38:27.193838 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 13:38:27.200104 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 13:38:27.203838 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 13:38:27.206816 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 13:38:27.213637 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 13:38:27.216727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 13:38:27.219969 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:38:27.226655 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:38:27.229853 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:38:27.233182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:38:27.239851 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:38:27.243179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:38:27.246456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:38:27.253146 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:38:27.256500 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5350 13:38:27.259812 Total UI for P1: 0, mck2ui 16
5351 13:38:27.263145 best dqsien dly found for B0: ( 1, 2, 26)
5352 13:38:27.266325 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 13:38:27.269671 Total UI for P1: 0, mck2ui 16
5354 13:38:27.272939 best dqsien dly found for B1: ( 1, 2, 28)
5355 13:38:27.276785 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5356 13:38:27.280040 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5357 13:38:27.282828
5358 13:38:27.286057 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5359 13:38:27.289878 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5360 13:38:27.293129 [Gating] SW calibration Done
5361 13:38:27.293247 ==
5362 13:38:27.296479 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 13:38:27.299801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 13:38:27.299923 ==
5365 13:38:27.300019 RX Vref Scan: 0
5366 13:38:27.300109
5367 13:38:27.303044 RX Vref 0 -> 0, step: 1
5368 13:38:27.303156
5369 13:38:27.306554 RX Delay -80 -> 252, step: 8
5370 13:38:27.309262 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5371 13:38:27.313014 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5372 13:38:27.319563 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5373 13:38:27.323021 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5374 13:38:27.326188 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5375 13:38:27.329241 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5376 13:38:27.332485 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5377 13:38:27.339394 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5378 13:38:27.342608 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5379 13:38:27.345503 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5380 13:38:27.348884 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5381 13:38:27.352184 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5382 13:38:27.358711 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5383 13:38:27.362087 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5384 13:38:27.365352 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5385 13:38:27.368753 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5386 13:38:27.368836 ==
5387 13:38:27.372072 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 13:38:27.375781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 13:38:27.378877 ==
5390 13:38:27.378988 DQS Delay:
5391 13:38:27.379093 DQS0 = 0, DQS1 = 0
5392 13:38:27.381958 DQM Delay:
5393 13:38:27.382059 DQM0 = 91, DQM1 = 83
5394 13:38:27.385729 DQ Delay:
5395 13:38:27.388885 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5396 13:38:27.392394 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5397 13:38:27.392494 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5398 13:38:27.399108 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5399 13:38:27.399211
5400 13:38:27.399302
5401 13:38:27.399388 ==
5402 13:38:27.401809 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 13:38:27.405159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 13:38:27.405262 ==
5405 13:38:27.405372
5406 13:38:27.405462
5407 13:38:27.408459 TX Vref Scan disable
5408 13:38:27.408528 == TX Byte 0 ==
5409 13:38:27.415173 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5410 13:38:27.418382 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5411 13:38:27.418489 == TX Byte 1 ==
5412 13:38:27.425479 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5413 13:38:27.428767 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5414 13:38:27.428843 ==
5415 13:38:27.431929 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 13:38:27.435082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 13:38:27.435221 ==
5418 13:38:27.435311
5419 13:38:27.435397
5420 13:38:27.438200 TX Vref Scan disable
5421 13:38:27.442027 == TX Byte 0 ==
5422 13:38:27.445146 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5423 13:38:27.448291 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5424 13:38:27.451742 == TX Byte 1 ==
5425 13:38:27.455024 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5426 13:38:27.458300 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5427 13:38:27.458400
5428 13:38:27.461811 [DATLAT]
5429 13:38:27.461894 Freq=933, CH0 RK1
5430 13:38:27.461976
5431 13:38:27.465199 DATLAT Default: 0xb
5432 13:38:27.465280 0, 0xFFFF, sum = 0
5433 13:38:27.468547 1, 0xFFFF, sum = 0
5434 13:38:27.468667 2, 0xFFFF, sum = 0
5435 13:38:27.471762 3, 0xFFFF, sum = 0
5436 13:38:27.471871 4, 0xFFFF, sum = 0
5437 13:38:27.475134 5, 0xFFFF, sum = 0
5438 13:38:27.475242 6, 0xFFFF, sum = 0
5439 13:38:27.478433 7, 0xFFFF, sum = 0
5440 13:38:27.481145 8, 0xFFFF, sum = 0
5441 13:38:27.481230 9, 0xFFFF, sum = 0
5442 13:38:27.485081 10, 0x0, sum = 1
5443 13:38:27.485164 11, 0x0, sum = 2
5444 13:38:27.485230 12, 0x0, sum = 3
5445 13:38:27.488384 13, 0x0, sum = 4
5446 13:38:27.488483 best_step = 11
5447 13:38:27.488616
5448 13:38:27.491713 ==
5449 13:38:27.491784 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 13:38:27.498074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 13:38:27.498208 ==
5452 13:38:27.498314 RX Vref Scan: 0
5453 13:38:27.498402
5454 13:38:27.501110 RX Vref 0 -> 0, step: 1
5455 13:38:27.501200
5456 13:38:27.504886 RX Delay -77 -> 252, step: 4
5457 13:38:27.507688 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5458 13:38:27.514316 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5459 13:38:27.517682 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5460 13:38:27.521101 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5461 13:38:27.524290 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5462 13:38:27.527593 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5463 13:38:27.534082 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5464 13:38:27.538017 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5465 13:38:27.541192 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5466 13:38:27.544270 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5467 13:38:27.547635 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5468 13:38:27.553898 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5469 13:38:27.557702 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5470 13:38:27.561004 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5471 13:38:27.564385 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5472 13:38:27.567681 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5473 13:38:27.567756 ==
5474 13:38:27.587461 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 13:38:27.587796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 13:38:27.587893 ==
5477 13:38:27.587992 DQS Delay:
5478 13:38:27.588082 DQS0 = 0, DQS1 = 0
5479 13:38:27.588172 DQM Delay:
5480 13:38:27.588261 DQM0 = 92, DQM1 = 84
5481 13:38:27.588355 DQ Delay:
5482 13:38:27.588449 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5483 13:38:27.590410 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5484 13:38:27.593883 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5485 13:38:27.597123 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =92
5486 13:38:27.597226
5487 13:38:27.597318
5488 13:38:27.603650 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5489 13:38:27.618308 CH0 RK1: MR19=505, MR18=2D0F
5490 13:38:27.618513 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5491 13:38:27.618619 [RxdqsGatingPostProcess] freq 933
5492 13:38:27.620145 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5493 13:38:27.623474 best DQS0 dly(2T, 0.5T) = (0, 11)
5494 13:38:27.626829 best DQS1 dly(2T, 0.5T) = (0, 11)
5495 13:38:27.630199 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5496 13:38:27.634093 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5497 13:38:27.636706 best DQS0 dly(2T, 0.5T) = (0, 10)
5498 13:38:27.640683 best DQS1 dly(2T, 0.5T) = (0, 10)
5499 13:38:27.643919 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5500 13:38:27.647166 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5501 13:38:27.650389 Pre-setting of DQS Precalculation
5502 13:38:27.653780 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5503 13:38:27.657029 ==
5504 13:38:27.660248 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 13:38:27.663413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 13:38:27.663496 ==
5507 13:38:27.666530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 13:38:27.673190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5509 13:38:27.677208 [CA 0] Center 37 (7~67) winsize 61
5510 13:38:27.680422 [CA 1] Center 37 (7~68) winsize 62
5511 13:38:27.683803 [CA 2] Center 34 (5~64) winsize 60
5512 13:38:27.687196 [CA 3] Center 34 (5~64) winsize 60
5513 13:38:27.690572 [CA 4] Center 35 (5~65) winsize 61
5514 13:38:27.693915 [CA 5] Center 34 (4~64) winsize 61
5515 13:38:27.694041
5516 13:38:27.696932 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5517 13:38:27.697093
5518 13:38:27.700121 [CATrainingPosCal] consider 1 rank data
5519 13:38:27.703680 u2DelayCellTimex100 = 270/100 ps
5520 13:38:27.706831 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5521 13:38:27.713449 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5522 13:38:27.716728 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5523 13:38:27.719947 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5524 13:38:27.723823 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5525 13:38:27.726811 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5526 13:38:27.726929
5527 13:38:27.730055 CA PerBit enable=1, Macro0, CA PI delay=34
5528 13:38:27.730167
5529 13:38:27.733372 [CBTSetCACLKResult] CA Dly = 34
5530 13:38:27.733555 CS Dly: 6 (0~37)
5531 13:38:27.736730 ==
5532 13:38:27.740010 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 13:38:27.743280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 13:38:27.743440 ==
5535 13:38:27.747083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 13:38:27.753209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5537 13:38:27.757058 [CA 0] Center 37 (7~68) winsize 62
5538 13:38:27.760219 [CA 1] Center 37 (7~68) winsize 62
5539 13:38:27.763508 [CA 2] Center 35 (5~65) winsize 61
5540 13:38:27.766736 [CA 3] Center 34 (4~64) winsize 61
5541 13:38:27.770007 [CA 4] Center 35 (5~65) winsize 61
5542 13:38:27.773816 [CA 5] Center 33 (3~64) winsize 62
5543 13:38:27.773967
5544 13:38:27.777144 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5545 13:38:27.777253
5546 13:38:27.780512 [CATrainingPosCal] consider 2 rank data
5547 13:38:27.783361 u2DelayCellTimex100 = 270/100 ps
5548 13:38:27.786747 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5549 13:38:27.793511 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5550 13:38:27.796817 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5551 13:38:27.800172 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5552 13:38:27.803440 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5553 13:38:27.806709 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5554 13:38:27.806785
5555 13:38:27.810136 CA PerBit enable=1, Macro0, CA PI delay=34
5556 13:38:27.810225
5557 13:38:27.813498 [CBTSetCACLKResult] CA Dly = 34
5558 13:38:27.813607 CS Dly: 7 (0~39)
5559 13:38:27.816731
5560 13:38:27.820020 ----->DramcWriteLeveling(PI) begin...
5561 13:38:27.820136 ==
5562 13:38:27.823480 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 13:38:27.826648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 13:38:27.826771 ==
5565 13:38:27.829844 Write leveling (Byte 0): 25 => 25
5566 13:38:27.833699 Write leveling (Byte 1): 27 => 27
5567 13:38:27.836674 DramcWriteLeveling(PI) end<-----
5568 13:38:27.836843
5569 13:38:27.836951 ==
5570 13:38:27.839724 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 13:38:27.843392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 13:38:27.843543 ==
5573 13:38:27.846759 [Gating] SW mode calibration
5574 13:38:27.853205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5575 13:38:27.859608 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5576 13:38:27.862750 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5577 13:38:27.866093 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 13:38:27.872937 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 13:38:27.876267 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 13:38:27.879716 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 13:38:27.886453 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 13:38:27.889124 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 13:38:27.892370 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5584 13:38:27.899212 0 15 0 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
5585 13:38:27.902533 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 13:38:27.905748 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 13:38:27.912380 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 13:38:27.915746 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 13:38:27.919131 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 13:38:27.925739 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 13:38:27.929074 0 15 28 | B1->B0 | 2f2f 302f | 0 1 | (0 0) (0 0)
5592 13:38:27.932249 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5593 13:38:27.939013 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 13:38:27.942245 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 13:38:27.945784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 13:38:27.952340 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 13:38:27.955342 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 13:38:27.959212 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 13:38:27.965447 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 13:38:27.969285 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:38:27.972350 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:38:27.978922 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:38:27.982135 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:38:27.985420 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:38:27.992507 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:38:27.995940 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:38:27.998557 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:38:28.005356 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:38:28.008692 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:38:28.012027 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:38:28.018749 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:38:28.022449 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:38:28.025479 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:38:28.031989 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:38:28.035253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5616 13:38:28.038499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 13:38:28.041902 Total UI for P1: 0, mck2ui 16
5618 13:38:28.045235 best dqsien dly found for B0: ( 1, 2, 28)
5619 13:38:28.048640 Total UI for P1: 0, mck2ui 16
5620 13:38:28.051862 best dqsien dly found for B1: ( 1, 2, 28)
5621 13:38:28.055119 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5622 13:38:28.058463 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5623 13:38:28.058943
5624 13:38:28.061675 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5625 13:38:28.068117 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5626 13:38:28.068724 [Gating] SW calibration Done
5627 13:38:28.069212 ==
5628 13:38:28.071664 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 13:38:28.078539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 13:38:28.079015 ==
5631 13:38:28.079352 RX Vref Scan: 0
5632 13:38:28.079668
5633 13:38:28.081470 RX Vref 0 -> 0, step: 1
5634 13:38:28.081885
5635 13:38:28.084975 RX Delay -80 -> 252, step: 8
5636 13:38:28.088124 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5637 13:38:28.091226 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5638 13:38:28.095026 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5639 13:38:28.101717 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5640 13:38:28.105034 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5641 13:38:28.108327 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5642 13:38:28.111449 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5643 13:38:28.114820 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5644 13:38:28.118248 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5645 13:38:28.124596 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5646 13:38:28.127660 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5647 13:38:28.131081 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5648 13:38:28.134497 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5649 13:38:28.137639 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5650 13:38:28.144179 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5651 13:38:28.147578 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5652 13:38:28.148028 ==
5653 13:38:28.151431 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 13:38:28.154723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 13:38:28.155305 ==
5656 13:38:28.158080 DQS Delay:
5657 13:38:28.158645 DQS0 = 0, DQS1 = 0
5658 13:38:28.159163 DQM Delay:
5659 13:38:28.161501 DQM0 = 94, DQM1 = 86
5660 13:38:28.161965 DQ Delay:
5661 13:38:28.164663 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5662 13:38:28.168059 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5663 13:38:28.170832 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5664 13:38:28.174192 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5665 13:38:28.174757
5666 13:38:28.175250
5667 13:38:28.175708 ==
5668 13:38:28.177486 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 13:38:28.184505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 13:38:28.184997 ==
5671 13:38:28.185506
5672 13:38:28.186078
5673 13:38:28.186585 TX Vref Scan disable
5674 13:38:28.187440 == TX Byte 0 ==
5675 13:38:28.191286 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 13:38:28.197580 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 13:38:28.198210 == TX Byte 1 ==
5678 13:38:28.201004 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5679 13:38:28.207945 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5680 13:38:28.208507 ==
5681 13:38:28.210433 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 13:38:28.213774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 13:38:28.214367 ==
5684 13:38:28.214868
5685 13:38:28.215411
5686 13:38:28.217352 TX Vref Scan disable
5687 13:38:28.217745 == TX Byte 0 ==
5688 13:38:28.224273 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 13:38:28.227634 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 13:38:28.228113 == TX Byte 1 ==
5691 13:38:28.233929 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5692 13:38:28.237255 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5693 13:38:28.237659
5694 13:38:28.238060 [DATLAT]
5695 13:38:28.240342 Freq=933, CH1 RK0
5696 13:38:28.240753
5697 13:38:28.241020 DATLAT Default: 0xd
5698 13:38:28.243552 0, 0xFFFF, sum = 0
5699 13:38:28.243871 1, 0xFFFF, sum = 0
5700 13:38:28.246937 2, 0xFFFF, sum = 0
5701 13:38:28.247246 3, 0xFFFF, sum = 0
5702 13:38:28.250502 4, 0xFFFF, sum = 0
5703 13:38:28.253707 5, 0xFFFF, sum = 0
5704 13:38:28.254025 6, 0xFFFF, sum = 0
5705 13:38:28.257112 7, 0xFFFF, sum = 0
5706 13:38:28.257417 8, 0xFFFF, sum = 0
5707 13:38:28.260263 9, 0xFFFF, sum = 0
5708 13:38:28.260600 10, 0x0, sum = 1
5709 13:38:28.263498 11, 0x0, sum = 2
5710 13:38:28.263734 12, 0x0, sum = 3
5711 13:38:28.266807 13, 0x0, sum = 4
5712 13:38:28.267123 best_step = 11
5713 13:38:28.267402
5714 13:38:28.267654 ==
5715 13:38:28.270270 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 13:38:28.273541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 13:38:28.273844 ==
5718 13:38:28.276925 RX Vref Scan: 1
5719 13:38:28.277240
5720 13:38:28.280304 RX Vref 0 -> 0, step: 1
5721 13:38:28.280586
5722 13:38:28.280794 RX Delay -69 -> 252, step: 4
5723 13:38:28.280968
5724 13:38:28.283629 Set Vref, RX VrefLevel [Byte0]: 57
5725 13:38:28.286937 [Byte1]: 54
5726 13:38:28.291500
5727 13:38:28.291749 Final RX Vref Byte 0 = 57 to rank0
5728 13:38:28.294705 Final RX Vref Byte 1 = 54 to rank0
5729 13:38:28.298024 Final RX Vref Byte 0 = 57 to rank1
5730 13:38:28.301434 Final RX Vref Byte 1 = 54 to rank1==
5731 13:38:28.304397 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 13:38:28.311484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 13:38:28.311729 ==
5734 13:38:28.311907 DQS Delay:
5735 13:38:28.312115 DQS0 = 0, DQS1 = 0
5736 13:38:28.314444 DQM Delay:
5737 13:38:28.314685 DQM0 = 97, DQM1 = 88
5738 13:38:28.317970 DQ Delay:
5739 13:38:28.321122 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =92
5740 13:38:28.324412 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5741 13:38:28.327843 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5742 13:38:28.331290 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5743 13:38:28.331560
5744 13:38:28.331773
5745 13:38:28.337987 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5746 13:38:28.341289 CH1 RK0: MR19=405, MR18=FF08
5747 13:38:28.347540 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5748 13:38:28.347972
5749 13:38:28.350998 ----->DramcWriteLeveling(PI) begin...
5750 13:38:28.351397 ==
5751 13:38:28.354262 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 13:38:28.357345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 13:38:28.357467 ==
5754 13:38:28.360767 Write leveling (Byte 0): 27 => 27
5755 13:38:28.363966 Write leveling (Byte 1): 29 => 29
5756 13:38:28.367341 DramcWriteLeveling(PI) end<-----
5757 13:38:28.367427
5758 13:38:28.367515 ==
5759 13:38:28.370702 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 13:38:28.374006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 13:38:28.377485 ==
5762 13:38:28.377571 [Gating] SW mode calibration
5763 13:38:28.383600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5764 13:38:28.390324 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5765 13:38:28.393607 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5766 13:38:28.400305 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 13:38:28.403597 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 13:38:28.407396 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 13:38:28.413342 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 13:38:28.416774 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 13:38:28.420079 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
5772 13:38:28.427112 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5773 13:38:28.430240 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5774 13:38:28.433665 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 13:38:28.440373 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 13:38:28.443725 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 13:38:28.447016 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 13:38:28.453569 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 13:38:28.456597 0 15 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5780 13:38:28.460451 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5781 13:38:28.466509 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 13:38:28.469779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 13:38:28.473118 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 13:38:28.479696 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 13:38:28.483057 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 13:38:28.486395 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 13:38:28.493119 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 13:38:28.496336 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5789 13:38:28.499719 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 13:38:28.506455 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 13:38:28.509530 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 13:38:28.512831 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 13:38:28.519734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 13:38:28.523084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 13:38:28.526325 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:38:28.533133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:38:28.535757 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:38:28.539594 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:38:28.546161 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:38:28.549432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:38:28.552498 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:38:28.555802 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:38:28.562489 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5804 13:38:28.565771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5805 13:38:28.572592 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 13:38:28.572687 Total UI for P1: 0, mck2ui 16
5807 13:38:28.575741 best dqsien dly found for B0: ( 1, 2, 26)
5808 13:38:28.579214 Total UI for P1: 0, mck2ui 16
5809 13:38:28.582415 best dqsien dly found for B1: ( 1, 2, 26)
5810 13:38:28.585821 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5811 13:38:28.592497 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5812 13:38:28.592604
5813 13:38:28.595865 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5814 13:38:28.598650 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5815 13:38:28.602024 [Gating] SW calibration Done
5816 13:38:28.602107 ==
5817 13:38:28.605294 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 13:38:28.608566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 13:38:28.608667 ==
5820 13:38:28.612060 RX Vref Scan: 0
5821 13:38:28.612141
5822 13:38:28.612205 RX Vref 0 -> 0, step: 1
5823 13:38:28.612265
5824 13:38:28.615502 RX Delay -80 -> 252, step: 8
5825 13:38:28.618359 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5826 13:38:28.625327 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5827 13:38:28.628824 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5828 13:38:28.631499 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5829 13:38:28.634785 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5830 13:38:28.638174 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5831 13:38:28.641564 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5832 13:38:28.648114 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5833 13:38:28.652037 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5834 13:38:28.655023 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5835 13:38:28.658039 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5836 13:38:28.661859 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5837 13:38:28.668005 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5838 13:38:28.671246 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5839 13:38:28.674372 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5840 13:38:28.678325 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5841 13:38:28.678405 ==
5842 13:38:28.681443 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 13:38:28.684555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 13:38:28.688009 ==
5845 13:38:28.688090 DQS Delay:
5846 13:38:28.688154 DQS0 = 0, DQS1 = 0
5847 13:38:28.691312 DQM Delay:
5848 13:38:28.691392 DQM0 = 94, DQM1 = 90
5849 13:38:28.694658 DQ Delay:
5850 13:38:28.697966 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5851 13:38:28.701437 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5852 13:38:28.701518 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5853 13:38:28.707547 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5854 13:38:28.707641
5855 13:38:28.707733
5856 13:38:28.707807 ==
5857 13:38:28.711405 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 13:38:28.714746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 13:38:28.714853 ==
5860 13:38:28.714945
5861 13:38:28.715041
5862 13:38:28.717975 TX Vref Scan disable
5863 13:38:28.718055 == TX Byte 0 ==
5864 13:38:28.724062 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 13:38:28.727383 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 13:38:28.727507 == TX Byte 1 ==
5867 13:38:28.734339 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5868 13:38:28.737622 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5869 13:38:28.737717 ==
5870 13:38:28.741015 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 13:38:28.744358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 13:38:28.744438 ==
5873 13:38:28.744501
5874 13:38:28.744584
5875 13:38:28.747743 TX Vref Scan disable
5876 13:38:28.751148 == TX Byte 0 ==
5877 13:38:28.754562 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5878 13:38:28.757868 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5879 13:38:28.761012 == TX Byte 1 ==
5880 13:38:28.764192 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5881 13:38:28.767302 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5882 13:38:28.767383
5883 13:38:28.770566 [DATLAT]
5884 13:38:28.770646 Freq=933, CH1 RK1
5885 13:38:28.770747
5886 13:38:28.773784 DATLAT Default: 0xb
5887 13:38:28.773863 0, 0xFFFF, sum = 0
5888 13:38:28.777665 1, 0xFFFF, sum = 0
5889 13:38:28.777748 2, 0xFFFF, sum = 0
5890 13:38:28.780674 3, 0xFFFF, sum = 0
5891 13:38:28.780756 4, 0xFFFF, sum = 0
5892 13:38:28.784116 5, 0xFFFF, sum = 0
5893 13:38:28.784198 6, 0xFFFF, sum = 0
5894 13:38:28.787294 7, 0xFFFF, sum = 0
5895 13:38:28.787376 8, 0xFFFF, sum = 0
5896 13:38:28.790388 9, 0xFFFF, sum = 0
5897 13:38:28.790487 10, 0x0, sum = 1
5898 13:38:28.794086 11, 0x0, sum = 2
5899 13:38:28.794185 12, 0x0, sum = 3
5900 13:38:28.797416 13, 0x0, sum = 4
5901 13:38:28.797515 best_step = 11
5902 13:38:28.797593
5903 13:38:28.797684 ==
5904 13:38:28.800138 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 13:38:28.807342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 13:38:28.807423 ==
5907 13:38:28.807486 RX Vref Scan: 0
5908 13:38:28.807546
5909 13:38:28.810162 RX Vref 0 -> 0, step: 1
5910 13:38:28.810242
5911 13:38:28.813358 RX Delay -69 -> 252, step: 4
5912 13:38:28.816669 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5913 13:38:28.823838 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5914 13:38:28.827207 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5915 13:38:28.829855 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5916 13:38:28.833241 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5917 13:38:28.836587 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5918 13:38:28.839763 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5919 13:38:28.846807 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5920 13:38:28.849686 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5921 13:38:28.853137 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5922 13:38:28.856409 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5923 13:38:28.859714 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5924 13:38:28.866418 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
5925 13:38:28.869648 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5926 13:38:28.872872 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5927 13:38:28.876141 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5928 13:38:28.876238 ==
5929 13:38:28.879704 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 13:38:28.886260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 13:38:28.886343 ==
5932 13:38:28.886407 DQS Delay:
5933 13:38:28.886465 DQS0 = 0, DQS1 = 0
5934 13:38:28.889460 DQM Delay:
5935 13:38:28.889541 DQM0 = 92, DQM1 = 92
5936 13:38:28.893245 DQ Delay:
5937 13:38:28.896426 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
5938 13:38:28.899651 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5939 13:38:28.902719 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
5940 13:38:28.905968 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5941 13:38:28.906047
5942 13:38:28.906110
5943 13:38:28.912770 [DQSOSCAuto] RK1, (LSB)MR18= 0x1226, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5944 13:38:28.916099 CH1 RK1: MR19=505, MR18=1226
5945 13:38:28.922815 CH1_RK1: MR19=0x505, MR18=0x1226, DQSOSC=409, MR23=63, INC=64, DEC=43
5946 13:38:28.926072 [RxdqsGatingPostProcess] freq 933
5947 13:38:28.929212 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5948 13:38:28.932689 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 13:38:28.935852 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 13:38:28.939174 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 13:38:28.942517 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 13:38:28.945739 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 13:38:28.948896 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 13:38:28.952492 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 13:38:28.955953 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 13:38:28.959336 Pre-setting of DQS Precalculation
5957 13:38:28.965657 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5958 13:38:28.971752 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5959 13:38:28.978816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5960 13:38:28.978898
5961 13:38:28.978961
5962 13:38:28.981965 [Calibration Summary] 1866 Mbps
5963 13:38:28.982068 CH 0, Rank 0
5964 13:38:28.985236 SW Impedance : PASS
5965 13:38:28.988412 DUTY Scan : NO K
5966 13:38:28.988518 ZQ Calibration : PASS
5967 13:38:28.991768 Jitter Meter : NO K
5968 13:38:28.991849 CBT Training : PASS
5969 13:38:28.995028 Write leveling : PASS
5970 13:38:28.998398 RX DQS gating : PASS
5971 13:38:28.998479 RX DQ/DQS(RDDQC) : PASS
5972 13:38:29.002076 TX DQ/DQS : PASS
5973 13:38:29.005239 RX DATLAT : PASS
5974 13:38:29.005324 RX DQ/DQS(Engine): PASS
5975 13:38:29.008712 TX OE : NO K
5976 13:38:29.008795 All Pass.
5977 13:38:29.008881
5978 13:38:29.011787 CH 0, Rank 1
5979 13:38:29.011871 SW Impedance : PASS
5980 13:38:29.015350 DUTY Scan : NO K
5981 13:38:29.018711 ZQ Calibration : PASS
5982 13:38:29.018796 Jitter Meter : NO K
5983 13:38:29.022200 CBT Training : PASS
5984 13:38:29.025419 Write leveling : PASS
5985 13:38:29.025503 RX DQS gating : PASS
5986 13:38:29.028857 RX DQ/DQS(RDDQC) : PASS
5987 13:38:29.032159 TX DQ/DQS : PASS
5988 13:38:29.032243 RX DATLAT : PASS
5989 13:38:29.035410 RX DQ/DQS(Engine): PASS
5990 13:38:29.035494 TX OE : NO K
5991 13:38:29.038581 All Pass.
5992 13:38:29.038665
5993 13:38:29.038750 CH 1, Rank 0
5994 13:38:29.041792 SW Impedance : PASS
5995 13:38:29.041876 DUTY Scan : NO K
5996 13:38:29.045212 ZQ Calibration : PASS
5997 13:38:29.048469 Jitter Meter : NO K
5998 13:38:29.048555 CBT Training : PASS
5999 13:38:29.051915 Write leveling : PASS
6000 13:38:29.055326 RX DQS gating : PASS
6001 13:38:29.055407 RX DQ/DQS(RDDQC) : PASS
6002 13:38:29.058374 TX DQ/DQS : PASS
6003 13:38:29.061712 RX DATLAT : PASS
6004 13:38:29.061849 RX DQ/DQS(Engine): PASS
6005 13:38:29.065098 TX OE : NO K
6006 13:38:29.065180 All Pass.
6007 13:38:29.065244
6008 13:38:29.068494 CH 1, Rank 1
6009 13:38:29.068598 SW Impedance : PASS
6010 13:38:29.071821 DUTY Scan : NO K
6011 13:38:29.075059 ZQ Calibration : PASS
6012 13:38:29.075145 Jitter Meter : NO K
6013 13:38:29.077795 CBT Training : PASS
6014 13:38:29.081272 Write leveling : PASS
6015 13:38:29.081356 RX DQS gating : PASS
6016 13:38:29.084417 RX DQ/DQS(RDDQC) : PASS
6017 13:38:29.087759 TX DQ/DQS : PASS
6018 13:38:29.087841 RX DATLAT : PASS
6019 13:38:29.091580 RX DQ/DQS(Engine): PASS
6020 13:38:29.094704 TX OE : NO K
6021 13:38:29.094846 All Pass.
6022 13:38:29.094938
6023 13:38:29.095025 DramC Write-DBI off
6024 13:38:29.097830 PER_BANK_REFRESH: Hybrid Mode
6025 13:38:29.101186 TX_TRACKING: ON
6026 13:38:29.108687 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6027 13:38:29.111258 [FAST_K] Save calibration result to emmc
6028 13:38:29.118040 dramc_set_vcore_voltage set vcore to 650000
6029 13:38:29.118122 Read voltage for 400, 6
6030 13:38:29.121033 Vio18 = 0
6031 13:38:29.121151 Vcore = 650000
6032 13:38:29.121215 Vdram = 0
6033 13:38:29.121275 Vddq = 0
6034 13:38:29.124748 Vmddr = 0
6035 13:38:29.128008 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6036 13:38:29.134196 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6037 13:38:29.137536 MEM_TYPE=3, freq_sel=20
6038 13:38:29.137620 sv_algorithm_assistance_LP4_800
6039 13:38:29.144133 ============ PULL DRAM RESETB DOWN ============
6040 13:38:29.148069 ========== PULL DRAM RESETB DOWN end =========
6041 13:38:29.150828 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6042 13:38:29.154153 ===================================
6043 13:38:29.157461 LPDDR4 DRAM CONFIGURATION
6044 13:38:29.160863 ===================================
6045 13:38:29.164110 EX_ROW_EN[0] = 0x0
6046 13:38:29.164194 EX_ROW_EN[1] = 0x0
6047 13:38:29.167775 LP4Y_EN = 0x0
6048 13:38:29.167859 WORK_FSP = 0x0
6049 13:38:29.171105 WL = 0x2
6050 13:38:29.171189 RL = 0x2
6051 13:38:29.173883 BL = 0x2
6052 13:38:29.173966 RPST = 0x0
6053 13:38:29.177178 RD_PRE = 0x0
6054 13:38:29.177261 WR_PRE = 0x1
6055 13:38:29.180457 WR_PST = 0x0
6056 13:38:29.180541 DBI_WR = 0x0
6057 13:38:29.183911 DBI_RD = 0x0
6058 13:38:29.187221 OTF = 0x1
6059 13:38:29.190616 ===================================
6060 13:38:29.193998 ===================================
6061 13:38:29.194080 ANA top config
6062 13:38:29.197379 ===================================
6063 13:38:29.200728 DLL_ASYNC_EN = 0
6064 13:38:29.200816 ALL_SLAVE_EN = 1
6065 13:38:29.203994 NEW_RANK_MODE = 1
6066 13:38:29.207429 DLL_IDLE_MODE = 1
6067 13:38:29.210702 LP45_APHY_COMB_EN = 1
6068 13:38:29.213934 TX_ODT_DIS = 1
6069 13:38:29.214019 NEW_8X_MODE = 1
6070 13:38:29.217308 ===================================
6071 13:38:29.220651 ===================================
6072 13:38:29.223913 data_rate = 800
6073 13:38:29.227011 CKR = 1
6074 13:38:29.230685 DQ_P2S_RATIO = 4
6075 13:38:29.233885 ===================================
6076 13:38:29.236849 CA_P2S_RATIO = 4
6077 13:38:29.240761 DQ_CA_OPEN = 0
6078 13:38:29.240842 DQ_SEMI_OPEN = 1
6079 13:38:29.243998 CA_SEMI_OPEN = 1
6080 13:38:29.247361 CA_FULL_RATE = 0
6081 13:38:29.250744 DQ_CKDIV4_EN = 0
6082 13:38:29.254006 CA_CKDIV4_EN = 1
6083 13:38:29.257275 CA_PREDIV_EN = 0
6084 13:38:29.257358 PH8_DLY = 0
6085 13:38:29.260674 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6086 13:38:29.264101 DQ_AAMCK_DIV = 0
6087 13:38:29.266822 CA_AAMCK_DIV = 0
6088 13:38:29.270159 CA_ADMCK_DIV = 4
6089 13:38:29.273945 DQ_TRACK_CA_EN = 0
6090 13:38:29.274026 CA_PICK = 800
6091 13:38:29.277230 CA_MCKIO = 400
6092 13:38:29.280576 MCKIO_SEMI = 400
6093 13:38:29.283881 PLL_FREQ = 3016
6094 13:38:29.286668 DQ_UI_PI_RATIO = 32
6095 13:38:29.290562 CA_UI_PI_RATIO = 32
6096 13:38:29.293764 ===================================
6097 13:38:29.296461 ===================================
6098 13:38:29.300391 memory_type:LPDDR4
6099 13:38:29.300512 GP_NUM : 10
6100 13:38:29.303778 SRAM_EN : 1
6101 13:38:29.303858 MD32_EN : 0
6102 13:38:29.306462 ===================================
6103 13:38:29.309768 [ANA_INIT] >>>>>>>>>>>>>>
6104 13:38:29.313232 <<<<<< [CONFIGURE PHASE]: ANA_TX
6105 13:38:29.316863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6106 13:38:29.319834 ===================================
6107 13:38:29.323229 data_rate = 800,PCW = 0X7400
6108 13:38:29.326478 ===================================
6109 13:38:29.329846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6110 13:38:29.333177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 13:38:29.346583 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6112 13:38:29.349637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6113 13:38:29.352910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6114 13:38:29.356410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6115 13:38:29.359505 [ANA_INIT] flow start
6116 13:38:29.362754 [ANA_INIT] PLL >>>>>>>>
6117 13:38:29.362834 [ANA_INIT] PLL <<<<<<<<
6118 13:38:29.366048 [ANA_INIT] MIDPI >>>>>>>>
6119 13:38:29.369424 [ANA_INIT] MIDPI <<<<<<<<
6120 13:38:29.369505 [ANA_INIT] DLL >>>>>>>>
6121 13:38:29.372785 [ANA_INIT] flow end
6122 13:38:29.376750 ============ LP4 DIFF to SE enter ============
6123 13:38:29.383043 ============ LP4 DIFF to SE exit ============
6124 13:38:29.383128 [ANA_INIT] <<<<<<<<<<<<<
6125 13:38:29.386369 [Flow] Enable top DCM control >>>>>
6126 13:38:29.389680 [Flow] Enable top DCM control <<<<<
6127 13:38:29.393035 Enable DLL master slave shuffle
6128 13:38:29.399643 ==============================================================
6129 13:38:29.399725 Gating Mode config
6130 13:38:29.406278 ==============================================================
6131 13:38:29.409616 Config description:
6132 13:38:29.419035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6133 13:38:29.425679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6134 13:38:29.429473 SELPH_MODE 0: By rank 1: By Phase
6135 13:38:29.435951 ==============================================================
6136 13:38:29.438859 GAT_TRACK_EN = 0
6137 13:38:29.438943 RX_GATING_MODE = 2
6138 13:38:29.442507 RX_GATING_TRACK_MODE = 2
6139 13:38:29.445831 SELPH_MODE = 1
6140 13:38:29.449211 PICG_EARLY_EN = 1
6141 13:38:29.452437 VALID_LAT_VALUE = 1
6142 13:38:29.458925 ==============================================================
6143 13:38:29.462187 Enter into Gating configuration >>>>
6144 13:38:29.465349 Exit from Gating configuration <<<<
6145 13:38:29.468992 Enter into DVFS_PRE_config >>>>>
6146 13:38:29.478460 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6147 13:38:29.482503 Exit from DVFS_PRE_config <<<<<
6148 13:38:29.485773 Enter into PICG configuration >>>>
6149 13:38:29.488983 Exit from PICG configuration <<<<
6150 13:38:29.491996 [RX_INPUT] configuration >>>>>
6151 13:38:29.495425 [RX_INPUT] configuration <<<<<
6152 13:38:29.498843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6153 13:38:29.505493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6154 13:38:29.511715 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 13:38:29.518461 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 13:38:29.521853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 13:38:29.528470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 13:38:29.531840 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6159 13:38:29.538614 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6160 13:38:29.541798 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6161 13:38:29.544768 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6162 13:38:29.548418 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6163 13:38:29.554808 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 13:38:29.558388 ===================================
6165 13:38:29.561420 LPDDR4 DRAM CONFIGURATION
6166 13:38:29.564793 ===================================
6167 13:38:29.564873 EX_ROW_EN[0] = 0x0
6168 13:38:29.568065 EX_ROW_EN[1] = 0x0
6169 13:38:29.568146 LP4Y_EN = 0x0
6170 13:38:29.571310 WORK_FSP = 0x0
6171 13:38:29.571391 WL = 0x2
6172 13:38:29.574619 RL = 0x2
6173 13:38:29.574700 BL = 0x2
6174 13:38:29.577969 RPST = 0x0
6175 13:38:29.578050 RD_PRE = 0x0
6176 13:38:29.581264 WR_PRE = 0x1
6177 13:38:29.581348 WR_PST = 0x0
6178 13:38:29.584970 DBI_WR = 0x0
6179 13:38:29.585073 DBI_RD = 0x0
6180 13:38:29.588194 OTF = 0x1
6181 13:38:29.591736 ===================================
6182 13:38:29.595054 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6183 13:38:29.598186 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6184 13:38:29.604767 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 13:38:29.608124 ===================================
6186 13:38:29.608208 LPDDR4 DRAM CONFIGURATION
6187 13:38:29.611399 ===================================
6188 13:38:29.614715 EX_ROW_EN[0] = 0x10
6189 13:38:29.618109 EX_ROW_EN[1] = 0x0
6190 13:38:29.618193 LP4Y_EN = 0x0
6191 13:38:29.621486 WORK_FSP = 0x0
6192 13:38:29.621570 WL = 0x2
6193 13:38:29.624842 RL = 0x2
6194 13:38:29.624925 BL = 0x2
6195 13:38:29.627983 RPST = 0x0
6196 13:38:29.628066 RD_PRE = 0x0
6197 13:38:29.631310 WR_PRE = 0x1
6198 13:38:29.631394 WR_PST = 0x0
6199 13:38:29.634658 DBI_WR = 0x0
6200 13:38:29.634742 DBI_RD = 0x0
6201 13:38:29.637838 OTF = 0x1
6202 13:38:29.641053 ===================================
6203 13:38:29.647704 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6204 13:38:29.651149 nWR fixed to 30
6205 13:38:29.654448 [ModeRegInit_LP4] CH0 RK0
6206 13:38:29.654532 [ModeRegInit_LP4] CH0 RK1
6207 13:38:29.657625 [ModeRegInit_LP4] CH1 RK0
6208 13:38:29.660776 [ModeRegInit_LP4] CH1 RK1
6209 13:38:29.660860 match AC timing 19
6210 13:38:29.667298 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6211 13:38:29.670887 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6212 13:38:29.674262 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6213 13:38:29.680943 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6214 13:38:29.683968 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6215 13:38:29.684049 ==
6216 13:38:29.687222 Dram Type= 6, Freq= 0, CH_0, rank 0
6217 13:38:29.690573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 13:38:29.690654 ==
6219 13:38:29.697591 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 13:38:29.704022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6221 13:38:29.707210 [CA 0] Center 36 (8~64) winsize 57
6222 13:38:29.710862 [CA 1] Center 36 (8~64) winsize 57
6223 13:38:29.710944 [CA 2] Center 36 (8~64) winsize 57
6224 13:38:29.713959 [CA 3] Center 36 (8~64) winsize 57
6225 13:38:29.717462 [CA 4] Center 36 (8~64) winsize 57
6226 13:38:29.720788 [CA 5] Center 36 (8~64) winsize 57
6227 13:38:29.720868
6228 13:38:29.724213 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6229 13:38:29.724293
6230 13:38:29.730739 [CATrainingPosCal] consider 1 rank data
6231 13:38:29.730818 u2DelayCellTimex100 = 270/100 ps
6232 13:38:29.736914 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 13:38:29.740335 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 13:38:29.743855 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 13:38:29.747082 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 13:38:29.750392 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:38:29.753766 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:38:29.753846
6239 13:38:29.757113 CA PerBit enable=1, Macro0, CA PI delay=36
6240 13:38:29.757207
6241 13:38:29.760453 [CBTSetCACLKResult] CA Dly = 36
6242 13:38:29.763787 CS Dly: 1 (0~32)
6243 13:38:29.763892 ==
6244 13:38:29.767042 Dram Type= 6, Freq= 0, CH_0, rank 1
6245 13:38:29.770254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 13:38:29.770335 ==
6247 13:38:29.777164 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 13:38:29.779738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6249 13:38:29.783098 [CA 0] Center 36 (8~64) winsize 57
6250 13:38:29.786918 [CA 1] Center 36 (8~64) winsize 57
6251 13:38:29.790014 [CA 2] Center 36 (8~64) winsize 57
6252 13:38:29.793474 [CA 3] Center 36 (8~64) winsize 57
6253 13:38:29.796979 [CA 4] Center 36 (8~64) winsize 57
6254 13:38:29.800297 [CA 5] Center 36 (8~64) winsize 57
6255 13:38:29.800409
6256 13:38:29.803416 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6257 13:38:29.803515
6258 13:38:29.806597 [CATrainingPosCal] consider 2 rank data
6259 13:38:29.809793 u2DelayCellTimex100 = 270/100 ps
6260 13:38:29.813480 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:38:29.816681 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:38:29.819955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:38:29.826551 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 13:38:29.830365 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:38:29.833165 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 13:38:29.833248
6267 13:38:29.836460 CA PerBit enable=1, Macro0, CA PI delay=36
6268 13:38:29.836542
6269 13:38:29.839729 [CBTSetCACLKResult] CA Dly = 36
6270 13:38:29.839815 CS Dly: 1 (0~32)
6271 13:38:29.839900
6272 13:38:29.843063 ----->DramcWriteLeveling(PI) begin...
6273 13:38:29.846431 ==
6274 13:38:29.846511 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 13:38:29.853052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 13:38:29.853133 ==
6277 13:38:29.856343 Write leveling (Byte 0): 40 => 8
6278 13:38:29.859728 Write leveling (Byte 1): 40 => 8
6279 13:38:29.863009 DramcWriteLeveling(PI) end<-----
6280 13:38:29.863090
6281 13:38:29.863154 ==
6282 13:38:29.866275 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 13:38:29.869681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 13:38:29.869787 ==
6285 13:38:29.873005 [Gating] SW mode calibration
6286 13:38:29.879484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6287 13:38:29.882773 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6288 13:38:29.889362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 13:38:29.892756 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6290 13:38:29.896272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 13:38:29.902694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 13:38:29.905765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 13:38:29.909149 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 13:38:29.916132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 13:38:29.919321 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 13:38:29.922687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 13:38:29.925964 Total UI for P1: 0, mck2ui 16
6298 13:38:29.929197 best dqsien dly found for B0: ( 0, 14, 24)
6299 13:38:29.932403 Total UI for P1: 0, mck2ui 16
6300 13:38:29.935967 best dqsien dly found for B1: ( 0, 14, 24)
6301 13:38:29.941859 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6302 13:38:29.945448 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6303 13:38:29.945529
6304 13:38:29.948845 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 13:38:29.952107 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6306 13:38:29.955389 [Gating] SW calibration Done
6307 13:38:29.955468 ==
6308 13:38:29.958698 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 13:38:29.962087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 13:38:29.962203 ==
6311 13:38:29.965467 RX Vref Scan: 0
6312 13:38:29.965547
6313 13:38:29.965609 RX Vref 0 -> 0, step: 1
6314 13:38:29.965698
6315 13:38:29.968889 RX Delay -410 -> 252, step: 16
6316 13:38:29.975360 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6317 13:38:29.978755 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6318 13:38:29.981983 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6319 13:38:29.985032 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6320 13:38:29.991776 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6321 13:38:29.995162 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6322 13:38:29.998495 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6323 13:38:30.001765 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6324 13:38:30.005175 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6325 13:38:30.011844 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6326 13:38:30.015124 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6327 13:38:30.018306 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6328 13:38:30.024658 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6329 13:38:30.028108 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6330 13:38:30.031721 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6331 13:38:30.035029 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6332 13:38:30.038454 ==
6333 13:38:30.038535 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:38:30.044965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:38:30.045047 ==
6336 13:38:30.045110 DQS Delay:
6337 13:38:30.048129 DQS0 = 59, DQS1 = 59
6338 13:38:30.048209 DQM Delay:
6339 13:38:30.051077 DQM0 = 18, DQM1 = 10
6340 13:38:30.051158 DQ Delay:
6341 13:38:30.054668 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6342 13:38:30.058220 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6343 13:38:30.061008 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6344 13:38:30.064295 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6345 13:38:30.064375
6346 13:38:30.064439
6347 13:38:30.064500 ==
6348 13:38:30.067793 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 13:38:30.071084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 13:38:30.071167 ==
6351 13:38:30.071231
6352 13:38:30.071290
6353 13:38:30.074387 TX Vref Scan disable
6354 13:38:30.074468 == TX Byte 0 ==
6355 13:38:30.081111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 13:38:30.084420 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 13:38:30.084519 == TX Byte 1 ==
6358 13:38:30.090905 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 13:38:30.094676 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 13:38:30.094761 ==
6361 13:38:30.097944 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 13:38:30.101184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 13:38:30.101255 ==
6364 13:38:30.101315
6365 13:38:30.101371
6366 13:38:30.104455 TX Vref Scan disable
6367 13:38:30.104521 == TX Byte 0 ==
6368 13:38:30.111151 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 13:38:30.114423 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 13:38:30.114503 == TX Byte 1 ==
6371 13:38:30.121062 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 13:38:30.124424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 13:38:30.124504
6374 13:38:30.124590 [DATLAT]
6375 13:38:30.127779 Freq=400, CH0 RK0
6376 13:38:30.127859
6377 13:38:30.127921 DATLAT Default: 0xf
6378 13:38:30.131076 0, 0xFFFF, sum = 0
6379 13:38:30.131189 1, 0xFFFF, sum = 0
6380 13:38:30.134463 2, 0xFFFF, sum = 0
6381 13:38:30.134544 3, 0xFFFF, sum = 0
6382 13:38:30.137688 4, 0xFFFF, sum = 0
6383 13:38:30.137769 5, 0xFFFF, sum = 0
6384 13:38:30.140733 6, 0xFFFF, sum = 0
6385 13:38:30.140815 7, 0xFFFF, sum = 0
6386 13:38:30.144238 8, 0xFFFF, sum = 0
6387 13:38:30.147640 9, 0xFFFF, sum = 0
6388 13:38:30.147721 10, 0xFFFF, sum = 0
6389 13:38:30.150850 11, 0xFFFF, sum = 0
6390 13:38:30.150932 12, 0xFFFF, sum = 0
6391 13:38:30.154183 13, 0x0, sum = 1
6392 13:38:30.154265 14, 0x0, sum = 2
6393 13:38:30.157692 15, 0x0, sum = 3
6394 13:38:30.157773 16, 0x0, sum = 4
6395 13:38:30.157839 best_step = 14
6396 13:38:30.157898
6397 13:38:30.160959 ==
6398 13:38:30.164370 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 13:38:30.167613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 13:38:30.167694 ==
6401 13:38:30.167775 RX Vref Scan: 1
6402 13:38:30.167849
6403 13:38:30.170868 RX Vref 0 -> 0, step: 1
6404 13:38:30.170947
6405 13:38:30.173923 RX Delay -359 -> 252, step: 8
6406 13:38:30.174002
6407 13:38:30.177508 Set Vref, RX VrefLevel [Byte0]: 60
6408 13:38:30.180479 [Byte1]: 55
6409 13:38:30.184429
6410 13:38:30.184514 Final RX Vref Byte 0 = 60 to rank0
6411 13:38:30.187906 Final RX Vref Byte 1 = 55 to rank0
6412 13:38:30.191297 Final RX Vref Byte 0 = 60 to rank1
6413 13:38:30.194790 Final RX Vref Byte 1 = 55 to rank1==
6414 13:38:30.197769 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 13:38:30.204116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 13:38:30.204226 ==
6417 13:38:30.204319 DQS Delay:
6418 13:38:30.207387 DQS0 = 60, DQS1 = 68
6419 13:38:30.207468 DQM Delay:
6420 13:38:30.207532 DQM0 = 14, DQM1 = 14
6421 13:38:30.210742 DQ Delay:
6422 13:38:30.214058 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6423 13:38:30.217346 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6424 13:38:30.217458 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6425 13:38:30.224219 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6426 13:38:30.224316
6427 13:38:30.224382
6428 13:38:30.231009 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6429 13:38:30.234254 CH0 RK0: MR19=C0C, MR18=8281
6430 13:38:30.240406 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6431 13:38:30.240546 ==
6432 13:38:30.243877 Dram Type= 6, Freq= 0, CH_0, rank 1
6433 13:38:30.247217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 13:38:30.247332 ==
6435 13:38:30.250412 [Gating] SW mode calibration
6436 13:38:30.257134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6437 13:38:30.263663 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6438 13:38:30.266782 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 13:38:30.270597 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 13:38:30.277119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 13:38:30.280354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 13:38:30.283711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 13:38:30.290220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 13:38:30.293640 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 13:38:30.296803 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 13:38:30.303426 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 13:38:30.303597 Total UI for P1: 0, mck2ui 16
6448 13:38:30.309815 best dqsien dly found for B0: ( 0, 14, 24)
6449 13:38:30.309901 Total UI for P1: 0, mck2ui 16
6450 13:38:30.316362 best dqsien dly found for B1: ( 0, 14, 24)
6451 13:38:30.319797 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6452 13:38:30.323101 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6453 13:38:30.323210
6454 13:38:30.326435 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 13:38:30.329805 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6456 13:38:30.333121 [Gating] SW calibration Done
6457 13:38:30.333204 ==
6458 13:38:30.336388 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 13:38:30.339626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 13:38:30.339703 ==
6461 13:38:30.343020 RX Vref Scan: 0
6462 13:38:30.343097
6463 13:38:30.343157 RX Vref 0 -> 0, step: 1
6464 13:38:30.343216
6465 13:38:30.346365 RX Delay -410 -> 252, step: 16
6466 13:38:30.352976 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6467 13:38:30.356410 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6468 13:38:30.359748 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6469 13:38:30.362932 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6470 13:38:30.369635 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6471 13:38:30.372877 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6472 13:38:30.376083 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6473 13:38:30.380001 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6474 13:38:30.386102 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6475 13:38:30.389481 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6476 13:38:30.392922 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6477 13:38:30.396282 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6478 13:38:30.403281 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6479 13:38:30.406255 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6480 13:38:30.409892 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6481 13:38:30.412845 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6482 13:38:30.415988 ==
6483 13:38:30.419577 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 13:38:30.423031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 13:38:30.423113 ==
6486 13:38:30.423177 DQS Delay:
6487 13:38:30.426140 DQS0 = 59, DQS1 = 59
6488 13:38:30.426237 DQM Delay:
6489 13:38:30.429594 DQM0 = 16, DQM1 = 10
6490 13:38:30.429706 DQ Delay:
6491 13:38:30.432832 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6492 13:38:30.436157 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6493 13:38:30.439372 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6494 13:38:30.442761 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6495 13:38:30.442841
6496 13:38:30.442940
6497 13:38:30.442999 ==
6498 13:38:30.446178 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 13:38:30.449289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 13:38:30.449387 ==
6501 13:38:30.449483
6502 13:38:30.449557
6503 13:38:30.452772 TX Vref Scan disable
6504 13:38:30.452869 == TX Byte 0 ==
6505 13:38:30.459345 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 13:38:30.462727 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 13:38:30.462826 == TX Byte 1 ==
6508 13:38:30.469340 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6509 13:38:30.472579 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6510 13:38:30.472692 ==
6511 13:38:30.475791 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 13:38:30.479014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 13:38:30.479096 ==
6514 13:38:30.479161
6515 13:38:30.479252
6516 13:38:30.482266 TX Vref Scan disable
6517 13:38:30.482347 == TX Byte 0 ==
6518 13:38:30.489293 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6519 13:38:30.492546 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6520 13:38:30.492703 == TX Byte 1 ==
6521 13:38:30.499368 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 13:38:30.502237 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 13:38:30.502332
6524 13:38:30.502426 [DATLAT]
6525 13:38:30.506069 Freq=400, CH0 RK1
6526 13:38:30.506150
6527 13:38:30.506213 DATLAT Default: 0xe
6528 13:38:30.509344 0, 0xFFFF, sum = 0
6529 13:38:30.509454 1, 0xFFFF, sum = 0
6530 13:38:30.512410 2, 0xFFFF, sum = 0
6531 13:38:30.512491 3, 0xFFFF, sum = 0
6532 13:38:30.515602 4, 0xFFFF, sum = 0
6533 13:38:30.515684 5, 0xFFFF, sum = 0
6534 13:38:30.518823 6, 0xFFFF, sum = 0
6535 13:38:30.518919 7, 0xFFFF, sum = 0
6536 13:38:30.522641 8, 0xFFFF, sum = 0
6537 13:38:30.525942 9, 0xFFFF, sum = 0
6538 13:38:30.526045 10, 0xFFFF, sum = 0
6539 13:38:30.529189 11, 0xFFFF, sum = 0
6540 13:38:30.529272 12, 0xFFFF, sum = 0
6541 13:38:30.532364 13, 0x0, sum = 1
6542 13:38:30.532446 14, 0x0, sum = 2
6543 13:38:30.535348 15, 0x0, sum = 3
6544 13:38:30.535425 16, 0x0, sum = 4
6545 13:38:30.535517 best_step = 14
6546 13:38:30.539185
6547 13:38:30.539257 ==
6548 13:38:30.542496 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 13:38:30.545833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 13:38:30.545928 ==
6551 13:38:30.546005 RX Vref Scan: 0
6552 13:38:30.546065
6553 13:38:30.549229 RX Vref 0 -> 0, step: 1
6554 13:38:30.549324
6555 13:38:30.551903 RX Delay -359 -> 252, step: 8
6556 13:38:30.559420 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6557 13:38:30.562682 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6558 13:38:30.566074 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6559 13:38:30.569446 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6560 13:38:30.575652 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6561 13:38:30.578855 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6562 13:38:30.582644 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6563 13:38:30.589153 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6564 13:38:30.591949 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6565 13:38:30.595305 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6566 13:38:30.598663 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6567 13:38:30.605642 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6568 13:38:30.609067 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6569 13:38:30.611769 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6570 13:38:30.615148 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6571 13:38:30.621905 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6572 13:38:30.621988 ==
6573 13:38:30.625113 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 13:38:30.628947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 13:38:30.629030 ==
6576 13:38:30.629096 DQS Delay:
6577 13:38:30.632069 DQS0 = 60, DQS1 = 72
6578 13:38:30.632151 DQM Delay:
6579 13:38:30.635298 DQM0 = 11, DQM1 = 17
6580 13:38:30.635381 DQ Delay:
6581 13:38:30.638807 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6582 13:38:30.642082 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6583 13:38:30.645247 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6584 13:38:30.648327 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6585 13:38:30.648409
6586 13:38:30.648473
6587 13:38:30.655175 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6588 13:38:30.658459 CH0 RK1: MR19=C0C, MR18=C67D
6589 13:38:30.665080 CH0_RK1: MR19=0xC0C, MR18=0xC67D, DQSOSC=385, MR23=63, INC=398, DEC=265
6590 13:38:30.668338 [RxdqsGatingPostProcess] freq 400
6591 13:38:30.675213 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6592 13:38:30.678007 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 13:38:30.681301 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 13:38:30.684684 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 13:38:30.688469 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 13:38:30.688552 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 13:38:30.691715 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 13:38:30.695035 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 13:38:30.697814 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 13:38:30.701220 Pre-setting of DQS Precalculation
6601 13:38:30.708083 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6602 13:38:30.708166 ==
6603 13:38:30.711239 Dram Type= 6, Freq= 0, CH_1, rank 0
6604 13:38:30.714366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 13:38:30.714450 ==
6606 13:38:30.721243 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 13:38:30.728104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6608 13:38:30.731365 [CA 0] Center 36 (8~64) winsize 57
6609 13:38:30.734574 [CA 1] Center 36 (8~64) winsize 57
6610 13:38:30.734660 [CA 2] Center 36 (8~64) winsize 57
6611 13:38:30.737792 [CA 3] Center 36 (8~64) winsize 57
6612 13:38:30.740875 [CA 4] Center 36 (8~64) winsize 57
6613 13:38:30.744423 [CA 5] Center 36 (8~64) winsize 57
6614 13:38:30.744510
6615 13:38:30.747823 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6616 13:38:30.747904
6617 13:38:30.754295 [CATrainingPosCal] consider 1 rank data
6618 13:38:30.754379 u2DelayCellTimex100 = 270/100 ps
6619 13:38:30.760654 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 13:38:30.763770 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 13:38:30.767121 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 13:38:30.770506 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 13:38:30.773915 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:38:30.777235 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:38:30.777318
6626 13:38:30.780783 CA PerBit enable=1, Macro0, CA PI delay=36
6627 13:38:30.780866
6628 13:38:30.783603 [CBTSetCACLKResult] CA Dly = 36
6629 13:38:30.787070 CS Dly: 1 (0~32)
6630 13:38:30.787199 ==
6631 13:38:30.790325 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 13:38:30.793604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 13:38:30.793704 ==
6634 13:38:30.800704 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 13:38:30.803582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6636 13:38:30.807030 [CA 0] Center 36 (8~64) winsize 57
6637 13:38:30.810488 [CA 1] Center 36 (8~64) winsize 57
6638 13:38:30.813289 [CA 2] Center 36 (8~64) winsize 57
6639 13:38:30.816877 [CA 3] Center 36 (8~64) winsize 57
6640 13:38:30.820373 [CA 4] Center 36 (8~64) winsize 57
6641 13:38:30.823717 [CA 5] Center 36 (8~64) winsize 57
6642 13:38:30.823827
6643 13:38:30.826863 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6644 13:38:30.826944
6645 13:38:30.829967 [CATrainingPosCal] consider 2 rank data
6646 13:38:30.833349 u2DelayCellTimex100 = 270/100 ps
6647 13:38:30.837162 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:38:30.840102 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:38:30.846658 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:38:30.850398 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 13:38:30.853688 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:38:30.856926 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 13:38:30.857008
6654 13:38:30.859684 CA PerBit enable=1, Macro0, CA PI delay=36
6655 13:38:30.859781
6656 13:38:30.863008 [CBTSetCACLKResult] CA Dly = 36
6657 13:38:30.863105 CS Dly: 1 (0~32)
6658 13:38:30.863199
6659 13:38:30.866991 ----->DramcWriteLeveling(PI) begin...
6660 13:38:30.869596 ==
6661 13:38:30.872930 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 13:38:30.876231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 13:38:30.876328 ==
6664 13:38:30.879680 Write leveling (Byte 0): 40 => 8
6665 13:38:30.882983 Write leveling (Byte 1): 40 => 8
6666 13:38:30.886405 DramcWriteLeveling(PI) end<-----
6667 13:38:30.886488
6668 13:38:30.886553 ==
6669 13:38:30.889797 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 13:38:30.893122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 13:38:30.893205 ==
6672 13:38:30.896394 [Gating] SW mode calibration
6673 13:38:30.903021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6674 13:38:30.909770 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6675 13:38:30.913014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 13:38:30.916433 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6677 13:38:30.922588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 13:38:30.926024 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 13:38:30.929349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 13:38:30.932715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 13:38:30.939370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 13:38:30.942766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 13:38:30.945793 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 13:38:30.949364 Total UI for P1: 0, mck2ui 16
6685 13:38:30.952934 best dqsien dly found for B0: ( 0, 14, 24)
6686 13:38:30.955834 Total UI for P1: 0, mck2ui 16
6687 13:38:30.959103 best dqsien dly found for B1: ( 0, 14, 24)
6688 13:38:30.962629 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6689 13:38:30.968812 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6690 13:38:30.968892
6691 13:38:30.972418 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 13:38:30.975633 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 13:38:30.978851 [Gating] SW calibration Done
6694 13:38:30.978934 ==
6695 13:38:30.982607 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 13:38:30.985816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 13:38:30.985900 ==
6698 13:38:30.989165 RX Vref Scan: 0
6699 13:38:30.989246
6700 13:38:30.989344 RX Vref 0 -> 0, step: 1
6701 13:38:30.989437
6702 13:38:30.992575 RX Delay -410 -> 252, step: 16
6703 13:38:30.998667 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6704 13:38:31.001879 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6705 13:38:31.005784 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6706 13:38:31.008460 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6707 13:38:31.011982 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6708 13:38:31.018694 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6709 13:38:31.022129 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6710 13:38:31.025411 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6711 13:38:31.028681 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6712 13:38:31.035352 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6713 13:38:31.038729 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6714 13:38:31.042109 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6715 13:38:31.048895 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6716 13:38:31.052143 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6717 13:38:31.055357 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6718 13:38:31.058727 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6719 13:38:31.058808 ==
6720 13:38:31.061962 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:38:31.068249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:38:31.068361 ==
6723 13:38:31.068425 DQS Delay:
6724 13:38:31.072097 DQS0 = 51, DQS1 = 67
6725 13:38:31.072204 DQM Delay:
6726 13:38:31.075363 DQM0 = 12, DQM1 = 18
6727 13:38:31.075444 DQ Delay:
6728 13:38:31.078466 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6729 13:38:31.082006 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6730 13:38:31.084962 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6731 13:38:31.088420 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6732 13:38:31.088502
6733 13:38:31.088588
6734 13:38:31.088662 ==
6735 13:38:31.091866 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 13:38:31.095080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 13:38:31.095162 ==
6738 13:38:31.095249
6739 13:38:31.095324
6740 13:38:31.098218 TX Vref Scan disable
6741 13:38:31.098299 == TX Byte 0 ==
6742 13:38:31.104930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 13:38:31.108057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 13:38:31.108138 == TX Byte 1 ==
6745 13:38:31.111906 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 13:38:31.118209 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 13:38:31.118293 ==
6748 13:38:31.121504 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 13:38:31.124796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 13:38:31.124878 ==
6751 13:38:31.124942
6752 13:38:31.125002
6753 13:38:31.128183 TX Vref Scan disable
6754 13:38:31.128263 == TX Byte 0 ==
6755 13:38:31.134987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 13:38:31.138319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 13:38:31.138401 == TX Byte 1 ==
6758 13:38:31.145086 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 13:38:31.148378 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 13:38:31.148460
6761 13:38:31.148538 [DATLAT]
6762 13:38:31.151206 Freq=400, CH1 RK0
6763 13:38:31.151305
6764 13:38:31.151400 DATLAT Default: 0xf
6765 13:38:31.154610 0, 0xFFFF, sum = 0
6766 13:38:31.154693 1, 0xFFFF, sum = 0
6767 13:38:31.157922 2, 0xFFFF, sum = 0
6768 13:38:31.158007 3, 0xFFFF, sum = 0
6769 13:38:31.161262 4, 0xFFFF, sum = 0
6770 13:38:31.161349 5, 0xFFFF, sum = 0
6771 13:38:31.164761 6, 0xFFFF, sum = 0
6772 13:38:31.164904 7, 0xFFFF, sum = 0
6773 13:38:31.168213 8, 0xFFFF, sum = 0
6774 13:38:31.168295 9, 0xFFFF, sum = 0
6775 13:38:31.171554 10, 0xFFFF, sum = 0
6776 13:38:31.171651 11, 0xFFFF, sum = 0
6777 13:38:31.174728 12, 0xFFFF, sum = 0
6778 13:38:31.174811 13, 0x0, sum = 1
6779 13:38:31.178209 14, 0x0, sum = 2
6780 13:38:31.178307 15, 0x0, sum = 3
6781 13:38:31.181563 16, 0x0, sum = 4
6782 13:38:31.181701 best_step = 14
6783 13:38:31.181765
6784 13:38:31.181850 ==
6785 13:38:31.184808 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 13:38:31.191320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 13:38:31.191426 ==
6788 13:38:31.191520 RX Vref Scan: 1
6789 13:38:31.191611
6790 13:38:31.194696 RX Vref 0 -> 0, step: 1
6791 13:38:31.194798
6792 13:38:31.198086 RX Delay -375 -> 252, step: 8
6793 13:38:31.198186
6794 13:38:31.200824 Set Vref, RX VrefLevel [Byte0]: 57
6795 13:38:31.204066 [Byte1]: 54
6796 13:38:31.207715
6797 13:38:31.207847 Final RX Vref Byte 0 = 57 to rank0
6798 13:38:31.211491 Final RX Vref Byte 1 = 54 to rank0
6799 13:38:31.214522 Final RX Vref Byte 0 = 57 to rank1
6800 13:38:31.217945 Final RX Vref Byte 1 = 54 to rank1==
6801 13:38:31.220871 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 13:38:31.227462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 13:38:31.227546 ==
6804 13:38:31.227643 DQS Delay:
6805 13:38:31.231228 DQS0 = 56, DQS1 = 68
6806 13:38:31.231328 DQM Delay:
6807 13:38:31.231394 DQM0 = 12, DQM1 = 13
6808 13:38:31.234164 DQ Delay:
6809 13:38:31.237809 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6810 13:38:31.241093 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6811 13:38:31.241178 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6812 13:38:31.244447 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6813 13:38:31.247167
6814 13:38:31.247240
6815 13:38:31.254064 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6816 13:38:31.257275 CH1 RK0: MR19=C0C, MR18=5D71
6817 13:38:31.263983 CH1_RK0: MR19=0xC0C, MR18=0x5D71, DQSOSC=395, MR23=63, INC=378, DEC=252
6818 13:38:31.264066 ==
6819 13:38:31.267361 Dram Type= 6, Freq= 0, CH_1, rank 1
6820 13:38:31.270792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 13:38:31.270874 ==
6822 13:38:31.274162 [Gating] SW mode calibration
6823 13:38:31.280897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6824 13:38:31.287611 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6825 13:38:31.290260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6826 13:38:31.294336 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6827 13:38:31.300819 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 13:38:31.304235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 13:38:31.306873 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 13:38:31.314160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 13:38:31.316860 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 13:38:31.320257 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 13:38:31.326937 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 13:38:31.327023 Total UI for P1: 0, mck2ui 16
6835 13:38:31.330674 best dqsien dly found for B0: ( 0, 14, 24)
6836 13:38:31.333944 Total UI for P1: 0, mck2ui 16
6837 13:38:31.337061 best dqsien dly found for B1: ( 0, 14, 24)
6838 13:38:31.343749 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6839 13:38:31.346632 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6840 13:38:31.346719
6841 13:38:31.350178 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 13:38:31.353756 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6843 13:38:31.356751 [Gating] SW calibration Done
6844 13:38:31.356839 ==
6845 13:38:31.360403 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 13:38:31.363470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 13:38:31.363557 ==
6848 13:38:31.366823 RX Vref Scan: 0
6849 13:38:31.366942
6850 13:38:31.367038 RX Vref 0 -> 0, step: 1
6851 13:38:31.367131
6852 13:38:31.370146 RX Delay -410 -> 252, step: 16
6853 13:38:31.376897 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6854 13:38:31.379862 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6855 13:38:31.383008 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6856 13:38:31.386377 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6857 13:38:31.393155 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6858 13:38:31.396541 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6859 13:38:31.399839 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6860 13:38:31.403118 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6861 13:38:31.410011 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6862 13:38:31.413379 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6863 13:38:31.416680 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6864 13:38:31.420028 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6865 13:38:31.426226 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6866 13:38:31.430030 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6867 13:38:31.432810 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6868 13:38:31.436174 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6869 13:38:31.439365 ==
6870 13:38:31.442762 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 13:38:31.446033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 13:38:31.446117 ==
6873 13:38:31.446183 DQS Delay:
6874 13:38:31.449945 DQS0 = 59, DQS1 = 59
6875 13:38:31.450028 DQM Delay:
6876 13:38:31.453072 DQM0 = 19, DQM1 = 14
6877 13:38:31.453155 DQ Delay:
6878 13:38:31.456174 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6879 13:38:31.459376 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6880 13:38:31.462707 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6881 13:38:31.466261 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6882 13:38:31.466344
6883 13:38:31.466411
6884 13:38:31.466471 ==
6885 13:38:31.469262 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 13:38:31.472758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 13:38:31.472843 ==
6888 13:38:31.472909
6889 13:38:31.472969
6890 13:38:31.475960 TX Vref Scan disable
6891 13:38:31.476042 == TX Byte 0 ==
6892 13:38:31.482566 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 13:38:31.485911 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 13:38:31.485999 == TX Byte 1 ==
6895 13:38:31.492411 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6896 13:38:31.495724 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6897 13:38:31.495813 ==
6898 13:38:31.499044 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 13:38:31.502445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 13:38:31.502529 ==
6901 13:38:31.502595
6902 13:38:31.502656
6903 13:38:31.505697 TX Vref Scan disable
6904 13:38:31.505810 == TX Byte 0 ==
6905 13:38:31.512451 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6906 13:38:31.515947 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6907 13:38:31.516030 == TX Byte 1 ==
6908 13:38:31.522691 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 13:38:31.525960 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 13:38:31.526072
6911 13:38:31.526171 [DATLAT]
6912 13:38:31.529379 Freq=400, CH1 RK1
6913 13:38:31.529488
6914 13:38:31.529585 DATLAT Default: 0xe
6915 13:38:31.532673 0, 0xFFFF, sum = 0
6916 13:38:31.532758 1, 0xFFFF, sum = 0
6917 13:38:31.535833 2, 0xFFFF, sum = 0
6918 13:38:31.535918 3, 0xFFFF, sum = 0
6919 13:38:31.539132 4, 0xFFFF, sum = 0
6920 13:38:31.539218 5, 0xFFFF, sum = 0
6921 13:38:31.541904 6, 0xFFFF, sum = 0
6922 13:38:31.545170 7, 0xFFFF, sum = 0
6923 13:38:31.545260 8, 0xFFFF, sum = 0
6924 13:38:31.548630 9, 0xFFFF, sum = 0
6925 13:38:31.548711 10, 0xFFFF, sum = 0
6926 13:38:31.552170 11, 0xFFFF, sum = 0
6927 13:38:31.552254 12, 0xFFFF, sum = 0
6928 13:38:31.555453 13, 0x0, sum = 1
6929 13:38:31.555532 14, 0x0, sum = 2
6930 13:38:31.558667 15, 0x0, sum = 3
6931 13:38:31.558739 16, 0x0, sum = 4
6932 13:38:31.561807 best_step = 14
6933 13:38:31.561883
6934 13:38:31.561951 ==
6935 13:38:31.565093 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 13:38:31.568492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 13:38:31.568598 ==
6938 13:38:31.568662 RX Vref Scan: 0
6939 13:38:31.571788
6940 13:38:31.571860 RX Vref 0 -> 0, step: 1
6941 13:38:31.571921
6942 13:38:31.574990 RX Delay -359 -> 252, step: 8
6943 13:38:31.582773 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6944 13:38:31.586114 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6945 13:38:31.589359 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6946 13:38:31.592675 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6947 13:38:31.599320 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6948 13:38:31.602236 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6949 13:38:31.605428 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6950 13:38:31.609194 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6951 13:38:31.615719 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6952 13:38:31.619098 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6953 13:38:31.622301 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6954 13:38:31.628917 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
6955 13:38:31.632172 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6956 13:38:31.635550 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6957 13:38:31.638827 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6958 13:38:31.645438 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6959 13:38:31.645520 ==
6960 13:38:31.648888 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 13:38:31.652286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 13:38:31.652365 ==
6963 13:38:31.652443 DQS Delay:
6964 13:38:31.655067 DQS0 = 60, DQS1 = 64
6965 13:38:31.655147 DQM Delay:
6966 13:38:31.658516 DQM0 = 12, DQM1 = 10
6967 13:38:31.658603 DQ Delay:
6968 13:38:31.661726 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6969 13:38:31.665084 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6970 13:38:31.668423 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6971 13:38:31.671698 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6972 13:38:31.671807
6973 13:38:31.671904
6974 13:38:31.678494 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
6975 13:38:31.681750 CH1 RK1: MR19=C0C, MR18=7EAE
6976 13:38:31.688770 CH1_RK1: MR19=0xC0C, MR18=0x7EAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6977 13:38:31.692246 [RxdqsGatingPostProcess] freq 400
6978 13:38:31.698466 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6979 13:38:31.701721 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 13:38:31.701827 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 13:38:31.704943 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 13:38:31.708361 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 13:38:31.711850 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 13:38:31.714973 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 13:38:31.718722 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 13:38:31.721834 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 13:38:31.725391 Pre-setting of DQS Precalculation
6988 13:38:31.731637 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6989 13:38:31.738339 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6990 13:38:31.744842 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6991 13:38:31.744932
6992 13:38:31.744995
6993 13:38:31.748301 [Calibration Summary] 800 Mbps
6994 13:38:31.748407 CH 0, Rank 0
6995 13:38:31.751655 SW Impedance : PASS
6996 13:38:31.755084 DUTY Scan : NO K
6997 13:38:31.755190 ZQ Calibration : PASS
6998 13:38:31.758484 Jitter Meter : NO K
6999 13:38:31.758584 CBT Training : PASS
7000 13:38:31.761991 Write leveling : PASS
7001 13:38:31.765211 RX DQS gating : PASS
7002 13:38:31.765290 RX DQ/DQS(RDDQC) : PASS
7003 13:38:31.768537 TX DQ/DQS : PASS
7004 13:38:31.771791 RX DATLAT : PASS
7005 13:38:31.771882 RX DQ/DQS(Engine): PASS
7006 13:38:31.775174 TX OE : NO K
7007 13:38:31.775285 All Pass.
7008 13:38:31.775376
7009 13:38:31.778496 CH 0, Rank 1
7010 13:38:31.778574 SW Impedance : PASS
7011 13:38:31.781704 DUTY Scan : NO K
7012 13:38:31.785082 ZQ Calibration : PASS
7013 13:38:31.785178 Jitter Meter : NO K
7014 13:38:31.787780 CBT Training : PASS
7015 13:38:31.791685 Write leveling : NO K
7016 13:38:31.791801 RX DQS gating : PASS
7017 13:38:31.794905 RX DQ/DQS(RDDQC) : PASS
7018 13:38:31.798179 TX DQ/DQS : PASS
7019 13:38:31.798305 RX DATLAT : PASS
7020 13:38:31.801590 RX DQ/DQS(Engine): PASS
7021 13:38:31.804928 TX OE : NO K
7022 13:38:31.805010 All Pass.
7023 13:38:31.805075
7024 13:38:31.805134 CH 1, Rank 0
7025 13:38:31.808344 SW Impedance : PASS
7026 13:38:31.811014 DUTY Scan : NO K
7027 13:38:31.811095 ZQ Calibration : PASS
7028 13:38:31.814987 Jitter Meter : NO K
7029 13:38:31.815068 CBT Training : PASS
7030 13:38:31.817765 Write leveling : PASS
7031 13:38:31.821223 RX DQS gating : PASS
7032 13:38:31.821304 RX DQ/DQS(RDDQC) : PASS
7033 13:38:31.824295 TX DQ/DQS : PASS
7034 13:38:31.828052 RX DATLAT : PASS
7035 13:38:31.828135 RX DQ/DQS(Engine): PASS
7036 13:38:31.831297 TX OE : NO K
7037 13:38:31.831378 All Pass.
7038 13:38:31.831442
7039 13:38:31.834499 CH 1, Rank 1
7040 13:38:31.834580 SW Impedance : PASS
7041 13:38:31.837629 DUTY Scan : NO K
7042 13:38:31.841075 ZQ Calibration : PASS
7043 13:38:31.841155 Jitter Meter : NO K
7044 13:38:31.844620 CBT Training : PASS
7045 13:38:31.847672 Write leveling : NO K
7046 13:38:31.847753 RX DQS gating : PASS
7047 13:38:31.851126 RX DQ/DQS(RDDQC) : PASS
7048 13:38:31.854455 TX DQ/DQS : PASS
7049 13:38:31.854537 RX DATLAT : PASS
7050 13:38:31.857837 RX DQ/DQS(Engine): PASS
7051 13:38:31.861215 TX OE : NO K
7052 13:38:31.861299 All Pass.
7053 13:38:31.861381
7054 13:38:31.861457 DramC Write-DBI off
7055 13:38:31.864483 PER_BANK_REFRESH: Hybrid Mode
7056 13:38:31.867693 TX_TRACKING: ON
7057 13:38:31.874371 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7058 13:38:31.877408 [FAST_K] Save calibration result to emmc
7059 13:38:31.884184 dramc_set_vcore_voltage set vcore to 725000
7060 13:38:31.884271 Read voltage for 1600, 0
7061 13:38:31.887594 Vio18 = 0
7062 13:38:31.887701 Vcore = 725000
7063 13:38:31.887789 Vdram = 0
7064 13:38:31.890804 Vddq = 0
7065 13:38:31.890886 Vmddr = 0
7066 13:38:31.894315 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7067 13:38:31.900813 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7068 13:38:31.904088 MEM_TYPE=3, freq_sel=13
7069 13:38:31.907165 sv_algorithm_assistance_LP4_3733
7070 13:38:31.910580 ============ PULL DRAM RESETB DOWN ============
7071 13:38:31.913913 ========== PULL DRAM RESETB DOWN end =========
7072 13:38:31.917368 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7073 13:38:31.920714 ===================================
7074 13:38:31.924065 LPDDR4 DRAM CONFIGURATION
7075 13:38:31.927418 ===================================
7076 13:38:31.930660 EX_ROW_EN[0] = 0x0
7077 13:38:31.930742 EX_ROW_EN[1] = 0x0
7078 13:38:31.934154 LP4Y_EN = 0x0
7079 13:38:31.934235 WORK_FSP = 0x1
7080 13:38:31.936891 WL = 0x5
7081 13:38:31.936972 RL = 0x5
7082 13:38:31.940334 BL = 0x2
7083 13:38:31.940416 RPST = 0x0
7084 13:38:31.944159 RD_PRE = 0x0
7085 13:38:31.946909 WR_PRE = 0x1
7086 13:38:31.946990 WR_PST = 0x1
7087 13:38:31.950174 DBI_WR = 0x0
7088 13:38:31.950258 DBI_RD = 0x0
7089 13:38:31.953894 OTF = 0x1
7090 13:38:31.956998 ===================================
7091 13:38:31.960600 ===================================
7092 13:38:31.960696 ANA top config
7093 13:38:31.964050 ===================================
7094 13:38:31.967063 DLL_ASYNC_EN = 0
7095 13:38:31.967145 ALL_SLAVE_EN = 0
7096 13:38:31.970499 NEW_RANK_MODE = 1
7097 13:38:31.973586 DLL_IDLE_MODE = 1
7098 13:38:31.976865 LP45_APHY_COMB_EN = 1
7099 13:38:31.980112 TX_ODT_DIS = 0
7100 13:38:31.980195 NEW_8X_MODE = 1
7101 13:38:31.984017 ===================================
7102 13:38:31.987330 ===================================
7103 13:38:31.990063 data_rate = 3200
7104 13:38:31.993564 CKR = 1
7105 13:38:31.996865 DQ_P2S_RATIO = 8
7106 13:38:32.000287 ===================================
7107 13:38:32.003593 CA_P2S_RATIO = 8
7108 13:38:32.006767 DQ_CA_OPEN = 0
7109 13:38:32.006849 DQ_SEMI_OPEN = 0
7110 13:38:32.009990 CA_SEMI_OPEN = 0
7111 13:38:32.013178 CA_FULL_RATE = 0
7112 13:38:32.016920 DQ_CKDIV4_EN = 0
7113 13:38:32.020049 CA_CKDIV4_EN = 0
7114 13:38:32.023425 CA_PREDIV_EN = 0
7115 13:38:32.023505 PH8_DLY = 12
7116 13:38:32.026765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7117 13:38:32.030117 DQ_AAMCK_DIV = 4
7118 13:38:32.033441 CA_AAMCK_DIV = 4
7119 13:38:32.036748 CA_ADMCK_DIV = 4
7120 13:38:32.040087 DQ_TRACK_CA_EN = 0
7121 13:38:32.043386 CA_PICK = 1600
7122 13:38:32.043469 CA_MCKIO = 1600
7123 13:38:32.046710 MCKIO_SEMI = 0
7124 13:38:32.050035 PLL_FREQ = 3068
7125 13:38:32.052879 DQ_UI_PI_RATIO = 32
7126 13:38:32.056909 CA_UI_PI_RATIO = 0
7127 13:38:32.060186 ===================================
7128 13:38:32.062838 ===================================
7129 13:38:32.066086 memory_type:LPDDR4
7130 13:38:32.066168 GP_NUM : 10
7131 13:38:32.069822 SRAM_EN : 1
7132 13:38:32.073070 MD32_EN : 0
7133 13:38:32.076244 ===================================
7134 13:38:32.076329 [ANA_INIT] >>>>>>>>>>>>>>
7135 13:38:32.079327 <<<<<< [CONFIGURE PHASE]: ANA_TX
7136 13:38:32.082906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7137 13:38:32.086083 ===================================
7138 13:38:32.089349 data_rate = 3200,PCW = 0X7600
7139 13:38:32.092714 ===================================
7140 13:38:32.096132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7141 13:38:32.102971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 13:38:32.106142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7143 13:38:32.112686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7144 13:38:32.116195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7145 13:38:32.118860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7146 13:38:32.118960 [ANA_INIT] flow start
7147 13:38:32.122707 [ANA_INIT] PLL >>>>>>>>
7148 13:38:32.125961 [ANA_INIT] PLL <<<<<<<<
7149 13:38:32.126044 [ANA_INIT] MIDPI >>>>>>>>
7150 13:38:32.129036 [ANA_INIT] MIDPI <<<<<<<<
7151 13:38:32.132192 [ANA_INIT] DLL >>>>>>>>
7152 13:38:32.135393 [ANA_INIT] DLL <<<<<<<<
7153 13:38:32.135465 [ANA_INIT] flow end
7154 13:38:32.139344 ============ LP4 DIFF to SE enter ============
7155 13:38:32.145367 ============ LP4 DIFF to SE exit ============
7156 13:38:32.145442 [ANA_INIT] <<<<<<<<<<<<<
7157 13:38:32.148741 [Flow] Enable top DCM control >>>>>
7158 13:38:32.152115 [Flow] Enable top DCM control <<<<<
7159 13:38:32.155479 Enable DLL master slave shuffle
7160 13:38:32.162108 ==============================================================
7161 13:38:32.162182 Gating Mode config
7162 13:38:32.168827 ==============================================================
7163 13:38:32.172217 Config description:
7164 13:38:32.182171 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7165 13:38:32.188856 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7166 13:38:32.192083 SELPH_MODE 0: By rank 1: By Phase
7167 13:38:32.198076 ==============================================================
7168 13:38:32.201871 GAT_TRACK_EN = 1
7169 13:38:32.204972 RX_GATING_MODE = 2
7170 13:38:32.208473 RX_GATING_TRACK_MODE = 2
7171 13:38:32.208616 SELPH_MODE = 1
7172 13:38:32.211347 PICG_EARLY_EN = 1
7173 13:38:32.215247 VALID_LAT_VALUE = 1
7174 13:38:32.221719 ==============================================================
7175 13:38:32.224921 Enter into Gating configuration >>>>
7176 13:38:32.228179 Exit from Gating configuration <<<<
7177 13:38:32.231477 Enter into DVFS_PRE_config >>>>>
7178 13:38:32.241805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7179 13:38:32.245077 Exit from DVFS_PRE_config <<<<<
7180 13:38:32.247850 Enter into PICG configuration >>>>
7181 13:38:32.251290 Exit from PICG configuration <<<<
7182 13:38:32.254695 [RX_INPUT] configuration >>>>>
7183 13:38:32.258138 [RX_INPUT] configuration <<<<<
7184 13:38:32.261412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7185 13:38:32.268106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7186 13:38:32.274840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 13:38:32.281377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 13:38:32.287859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 13:38:32.290991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 13:38:32.297705 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7191 13:38:32.300953 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7192 13:38:32.304365 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7193 13:38:32.307790 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7194 13:38:32.311107 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7195 13:38:32.317939 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 13:38:32.321137 ===================================
7197 13:38:32.324340 LPDDR4 DRAM CONFIGURATION
7198 13:38:32.327299 ===================================
7199 13:38:32.327382 EX_ROW_EN[0] = 0x0
7200 13:38:32.330730 EX_ROW_EN[1] = 0x0
7201 13:38:32.330811 LP4Y_EN = 0x0
7202 13:38:32.334249 WORK_FSP = 0x1
7203 13:38:32.334331 WL = 0x5
7204 13:38:32.337100 RL = 0x5
7205 13:38:32.337182 BL = 0x2
7206 13:38:32.340465 RPST = 0x0
7207 13:38:32.340546 RD_PRE = 0x0
7208 13:38:32.343774 WR_PRE = 0x1
7209 13:38:32.343855 WR_PST = 0x1
7210 13:38:32.347148 DBI_WR = 0x0
7211 13:38:32.350395 DBI_RD = 0x0
7212 13:38:32.350491 OTF = 0x1
7213 13:38:32.353842 ===================================
7214 13:38:32.357270 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7215 13:38:32.360762 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7216 13:38:32.366878 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 13:38:32.370118 ===================================
7218 13:38:32.373579 LPDDR4 DRAM CONFIGURATION
7219 13:38:32.376918 ===================================
7220 13:38:32.377000 EX_ROW_EN[0] = 0x10
7221 13:38:32.380392 EX_ROW_EN[1] = 0x0
7222 13:38:32.380473 LP4Y_EN = 0x0
7223 13:38:32.383882 WORK_FSP = 0x1
7224 13:38:32.383963 WL = 0x5
7225 13:38:32.387057 RL = 0x5
7226 13:38:32.387154 BL = 0x2
7227 13:38:32.390429 RPST = 0x0
7228 13:38:32.390510 RD_PRE = 0x0
7229 13:38:32.393698 WR_PRE = 0x1
7230 13:38:32.393779 WR_PST = 0x1
7231 13:38:32.397084 DBI_WR = 0x0
7232 13:38:32.397165 DBI_RD = 0x0
7233 13:38:32.400416 OTF = 0x1
7234 13:38:32.403841 ===================================
7235 13:38:32.410327 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7236 13:38:32.410409 ==
7237 13:38:32.413774 Dram Type= 6, Freq= 0, CH_0, rank 0
7238 13:38:32.417110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7239 13:38:32.417193 ==
7240 13:38:32.420317 [Duty_Offset_Calibration]
7241 13:38:32.420399 B0:2 B1:0 CA:3
7242 13:38:32.423588
7243 13:38:32.423668 [DutyScan_Calibration_Flow] k_type=0
7244 13:38:32.434319
7245 13:38:32.434404 ==CLK 0==
7246 13:38:32.437717 Final CLK duty delay cell = 0
7247 13:38:32.440981 [0] MAX Duty = 5031%(X100), DQS PI = 12
7248 13:38:32.444369 [0] MIN Duty = 4907%(X100), DQS PI = 6
7249 13:38:32.444485 [0] AVG Duty = 4969%(X100)
7250 13:38:32.447629
7251 13:38:32.450909 CH0 CLK Duty spec in!! Max-Min= 124%
7252 13:38:32.454655 [DutyScan_Calibration_Flow] ====Done====
7253 13:38:32.454764
7254 13:38:32.457758 [DutyScan_Calibration_Flow] k_type=1
7255 13:38:32.474313
7256 13:38:32.474455 ==DQS 0 ==
7257 13:38:32.477407 Final DQS duty delay cell = 0
7258 13:38:32.480803 [0] MAX Duty = 5094%(X100), DQS PI = 30
7259 13:38:32.484394 [0] MIN Duty = 4875%(X100), DQS PI = 48
7260 13:38:32.487767 [0] AVG Duty = 4984%(X100)
7261 13:38:32.487848
7262 13:38:32.487936 ==DQS 1 ==
7263 13:38:32.491125 Final DQS duty delay cell = 0
7264 13:38:32.494341 [0] MAX Duty = 5156%(X100), DQS PI = 32
7265 13:38:32.497615 [0] MIN Duty = 5062%(X100), DQS PI = 10
7266 13:38:32.500798 [0] AVG Duty = 5109%(X100)
7267 13:38:32.500877
7268 13:38:32.504121 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7269 13:38:32.504223
7270 13:38:32.507504 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7271 13:38:32.510753 [DutyScan_Calibration_Flow] ====Done====
7272 13:38:32.510854
7273 13:38:32.514177 [DutyScan_Calibration_Flow] k_type=3
7274 13:38:32.532400
7275 13:38:32.532526 ==DQM 0 ==
7276 13:38:32.535666 Final DQM duty delay cell = 0
7277 13:38:32.538795 [0] MAX Duty = 5156%(X100), DQS PI = 30
7278 13:38:32.542028 [0] MIN Duty = 4875%(X100), DQS PI = 0
7279 13:38:32.545213 [0] AVG Duty = 5015%(X100)
7280 13:38:32.545315
7281 13:38:32.545405 ==DQM 1 ==
7282 13:38:32.548461 Final DQM duty delay cell = 4
7283 13:38:32.551817 [4] MAX Duty = 5187%(X100), DQS PI = 62
7284 13:38:32.555210 [4] MIN Duty = 5000%(X100), DQS PI = 38
7285 13:38:32.558639 [4] AVG Duty = 5093%(X100)
7286 13:38:32.558741
7287 13:38:32.562046 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7288 13:38:32.562128
7289 13:38:32.565291 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7290 13:38:32.568512 [DutyScan_Calibration_Flow] ====Done====
7291 13:38:32.568640
7292 13:38:32.571759 [DutyScan_Calibration_Flow] k_type=2
7293 13:38:32.588010
7294 13:38:32.588131 ==DQ 0 ==
7295 13:38:32.591614 Final DQ duty delay cell = -4
7296 13:38:32.594911 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7297 13:38:32.598349 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7298 13:38:32.601450 [-4] AVG Duty = 4938%(X100)
7299 13:38:32.601533
7300 13:38:32.601596 ==DQ 1 ==
7301 13:38:32.604646 Final DQ duty delay cell = 0
7302 13:38:32.608260 [0] MAX Duty = 5156%(X100), DQS PI = 58
7303 13:38:32.611388 [0] MIN Duty = 5000%(X100), DQS PI = 16
7304 13:38:32.614682 [0] AVG Duty = 5078%(X100)
7305 13:38:32.614759
7306 13:38:32.618148 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7307 13:38:32.618222
7308 13:38:32.621574 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7309 13:38:32.624916 [DutyScan_Calibration_Flow] ====Done====
7310 13:38:32.624994 ==
7311 13:38:32.628416 Dram Type= 6, Freq= 0, CH_1, rank 0
7312 13:38:32.631721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7313 13:38:32.631792 ==
7314 13:38:32.635000 [Duty_Offset_Calibration]
7315 13:38:32.635094 B0:1 B1:-2 CA:1
7316 13:38:32.635181
7317 13:38:32.637802 [DutyScan_Calibration_Flow] k_type=0
7318 13:38:32.649116
7319 13:38:32.649190 ==CLK 0==
7320 13:38:32.652384 Final CLK duty delay cell = 0
7321 13:38:32.655607 [0] MAX Duty = 5094%(X100), DQS PI = 22
7322 13:38:32.658873 [0] MIN Duty = 4844%(X100), DQS PI = 4
7323 13:38:32.658974 [0] AVG Duty = 4969%(X100)
7324 13:38:32.662168
7325 13:38:32.662242 CH1 CLK Duty spec in!! Max-Min= 250%
7326 13:38:32.668769 [DutyScan_Calibration_Flow] ====Done====
7327 13:38:32.668850
7328 13:38:32.672086 [DutyScan_Calibration_Flow] k_type=1
7329 13:38:32.688325
7330 13:38:32.688436 ==DQS 0 ==
7331 13:38:32.691737 Final DQS duty delay cell = 0
7332 13:38:32.695198 [0] MAX Duty = 5187%(X100), DQS PI = 24
7333 13:38:32.698417 [0] MIN Duty = 5031%(X100), DQS PI = 54
7334 13:38:32.701574 [0] AVG Duty = 5109%(X100)
7335 13:38:32.701671
7336 13:38:32.701760 ==DQS 1 ==
7337 13:38:32.705178 Final DQS duty delay cell = 0
7338 13:38:32.708320 [0] MAX Duty = 5093%(X100), DQS PI = 60
7339 13:38:32.711817 [0] MIN Duty = 4844%(X100), DQS PI = 24
7340 13:38:32.715086 [0] AVG Duty = 4968%(X100)
7341 13:38:32.715189
7342 13:38:32.718167 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7343 13:38:32.718237
7344 13:38:32.721314 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7345 13:38:32.725104 [DutyScan_Calibration_Flow] ====Done====
7346 13:38:32.725192
7347 13:38:32.728370 [DutyScan_Calibration_Flow] k_type=3
7348 13:38:32.745182
7349 13:38:32.745266 ==DQM 0 ==
7350 13:38:32.748432 Final DQM duty delay cell = 0
7351 13:38:32.751559 [0] MAX Duty = 5031%(X100), DQS PI = 24
7352 13:38:32.754920 [0] MIN Duty = 4813%(X100), DQS PI = 56
7353 13:38:32.758245 [0] AVG Duty = 4922%(X100)
7354 13:38:32.758325
7355 13:38:32.758424 ==DQM 1 ==
7356 13:38:32.761667 Final DQM duty delay cell = 0
7357 13:38:32.764991 [0] MAX Duty = 5062%(X100), DQS PI = 34
7358 13:38:32.768294 [0] MIN Duty = 4875%(X100), DQS PI = 24
7359 13:38:32.771571 [0] AVG Duty = 4968%(X100)
7360 13:38:32.771681
7361 13:38:32.774838 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7362 13:38:32.774944
7363 13:38:32.778091 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7364 13:38:32.781392 [DutyScan_Calibration_Flow] ====Done====
7365 13:38:32.781492
7366 13:38:32.784626 [DutyScan_Calibration_Flow] k_type=2
7367 13:38:32.802040
7368 13:38:32.802172 ==DQ 0 ==
7369 13:38:32.805365 Final DQ duty delay cell = 0
7370 13:38:32.808535 [0] MAX Duty = 5093%(X100), DQS PI = 22
7371 13:38:32.811815 [0] MIN Duty = 4907%(X100), DQS PI = 60
7372 13:38:32.811922 [0] AVG Duty = 5000%(X100)
7373 13:38:32.815433
7374 13:38:32.815529 ==DQ 1 ==
7375 13:38:32.818636 Final DQ duty delay cell = 0
7376 13:38:32.821875 [0] MAX Duty = 5125%(X100), DQS PI = 34
7377 13:38:32.825195 [0] MIN Duty = 4969%(X100), DQS PI = 24
7378 13:38:32.828321 [0] AVG Duty = 5047%(X100)
7379 13:38:32.828429
7380 13:38:32.831549 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7381 13:38:32.831646
7382 13:38:32.835203 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7383 13:38:32.838359 [DutyScan_Calibration_Flow] ====Done====
7384 13:38:32.841707 nWR fixed to 30
7385 13:38:32.845064 [ModeRegInit_LP4] CH0 RK0
7386 13:38:32.845179 [ModeRegInit_LP4] CH0 RK1
7387 13:38:32.848264 [ModeRegInit_LP4] CH1 RK0
7388 13:38:32.851726 [ModeRegInit_LP4] CH1 RK1
7389 13:38:32.851796 match AC timing 5
7390 13:38:32.858319 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7391 13:38:32.861173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7392 13:38:32.865071 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7393 13:38:32.871642 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7394 13:38:32.874993 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7395 13:38:32.875108 [MiockJmeterHQA]
7396 13:38:32.875214
7397 13:38:32.878162 [DramcMiockJmeter] u1RxGatingPI = 0
7398 13:38:32.881429 0 : 4255, 4030
7399 13:38:32.881516 4 : 4254, 4029
7400 13:38:32.884669 8 : 4255, 4029
7401 13:38:32.884769 12 : 4255, 4029
7402 13:38:32.887970 16 : 4254, 4029
7403 13:38:32.888089 20 : 4368, 4140
7404 13:38:32.888192 24 : 4253, 4027
7405 13:38:32.891259 28 : 4257, 4029
7406 13:38:32.891369 32 : 4257, 4029
7407 13:38:32.894618 36 : 4257, 4030
7408 13:38:32.894727 40 : 4257, 4029
7409 13:38:32.897753 44 : 4255, 4029
7410 13:38:32.897842 48 : 4257, 4031
7411 13:38:32.900900 52 : 4368, 4140
7412 13:38:32.900986 56 : 4252, 4030
7413 13:38:32.901053 60 : 4255, 4029
7414 13:38:32.904338 64 : 4253, 4029
7415 13:38:32.904422 68 : 4258, 4032
7416 13:38:32.907809 72 : 4366, 4140
7417 13:38:32.907893 76 : 4252, 4030
7418 13:38:32.911060 80 : 4253, 4029
7419 13:38:32.911145 84 : 4255, 4029
7420 13:38:32.914270 88 : 4252, 4030
7421 13:38:32.914353 92 : 4252, 4029
7422 13:38:32.914421 96 : 4252, 4029
7423 13:38:32.917625 100 : 4257, 4031
7424 13:38:32.917708 104 : 4250, 3457
7425 13:38:32.921068 108 : 4252, 0
7426 13:38:32.921155 112 : 4258, 0
7427 13:38:32.921221 116 : 4363, 0
7428 13:38:32.924235 120 : 4366, 0
7429 13:38:32.924320 124 : 4365, 0
7430 13:38:32.927473 128 : 4253, 0
7431 13:38:32.927557 132 : 4252, 0
7432 13:38:32.927623 136 : 4255, 0
7433 13:38:32.930774 140 : 4252, 0
7434 13:38:32.930858 144 : 4363, 0
7435 13:38:32.934113 148 : 4366, 0
7436 13:38:32.934196 152 : 4368, 0
7437 13:38:32.934263 156 : 4252, 0
7438 13:38:32.937293 160 : 4363, 0
7439 13:38:32.937376 164 : 4250, 0
7440 13:38:32.940641 168 : 4363, 0
7441 13:38:32.940724 172 : 4253, 0
7442 13:38:32.940791 176 : 4363, 0
7443 13:38:32.944046 180 : 4253, 0
7444 13:38:32.944120 184 : 4252, 0
7445 13:38:32.947174 188 : 4255, 0
7446 13:38:32.947258 192 : 4252, 0
7447 13:38:32.947325 196 : 4363, 0
7448 13:38:32.950930 200 : 4366, 0
7449 13:38:32.951014 204 : 4253, 0
7450 13:38:32.951081 208 : 4252, 0
7451 13:38:32.954213 212 : 4252, 0
7452 13:38:32.954297 216 : 4253, 0
7453 13:38:32.957574 220 : 4365, 0
7454 13:38:32.957657 224 : 4365, 0
7455 13:38:32.957724 228 : 4255, 0
7456 13:38:32.960716 232 : 4252, 0
7457 13:38:32.960827 236 : 4250, 1113
7458 13:38:32.964107 240 : 4361, 4137
7459 13:38:32.964191 244 : 4253, 4029
7460 13:38:32.967430 248 : 4252, 4029
7461 13:38:32.967514 252 : 4252, 4029
7462 13:38:32.970111 256 : 4252, 4029
7463 13:38:32.970194 260 : 4252, 4029
7464 13:38:32.973439 264 : 4252, 4029
7465 13:38:32.973523 268 : 4255, 4029
7466 13:38:32.977368 272 : 4363, 4140
7467 13:38:32.977455 276 : 4252, 4030
7468 13:38:32.977556 280 : 4360, 4137
7469 13:38:32.980127 284 : 4255, 4029
7470 13:38:32.980211 288 : 4253, 4029
7471 13:38:32.983457 292 : 4363, 4140
7472 13:38:32.983539 296 : 4255, 4029
7473 13:38:32.986821 300 : 4255, 4029
7474 13:38:32.986931 304 : 4252, 4029
7475 13:38:32.990300 308 : 4252, 4029
7476 13:38:32.990383 312 : 4253, 4029
7477 13:38:32.993712 316 : 4257, 4032
7478 13:38:32.993794 320 : 4255, 4029
7479 13:38:32.997114 324 : 4363, 4140
7480 13:38:32.997212 328 : 4252, 4030
7481 13:38:33.000380 332 : 4360, 4137
7482 13:38:33.000482 336 : 4255, 4029
7483 13:38:33.003457 340 : 4254, 4029
7484 13:38:33.003539 344 : 4363, 4140
7485 13:38:33.003656 348 : 4254, 4029
7486 13:38:33.006519 352 : 4255, 4004
7487 13:38:33.006600 356 : 4253, 2775
7488 13:38:33.010327 360 : 4363, 0
7489 13:38:33.010425
7490 13:38:33.013313 MIOCK jitter meter ch=0
7491 13:38:33.013393
7492 13:38:33.013461 1T = (360-108) = 252 dly cells
7493 13:38:33.020438 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7494 13:38:33.020548 ==
7495 13:38:33.023081 Dram Type= 6, Freq= 0, CH_0, rank 0
7496 13:38:33.027153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 13:38:33.029753 ==
7498 13:38:33.033037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 13:38:33.036724 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 13:38:33.043156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 13:38:33.046512 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 13:38:33.057053 [CA 0] Center 44 (14~75) winsize 62
7503 13:38:33.060084 [CA 1] Center 43 (13~74) winsize 62
7504 13:38:33.063867 [CA 2] Center 40 (11~69) winsize 59
7505 13:38:33.067006 [CA 3] Center 39 (10~69) winsize 60
7506 13:38:33.070187 [CA 4] Center 37 (8~67) winsize 60
7507 13:38:33.073390 [CA 5] Center 37 (8~66) winsize 59
7508 13:38:33.073507
7509 13:38:33.076695 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 13:38:33.076780
7511 13:38:33.083391 [CATrainingPosCal] consider 1 rank data
7512 13:38:33.083474 u2DelayCellTimex100 = 258/100 ps
7513 13:38:33.089998 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7514 13:38:33.093294 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7515 13:38:33.096769 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7516 13:38:33.099990 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7517 13:38:33.103432 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7518 13:38:33.106802 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7519 13:38:33.106906
7520 13:38:33.110063 CA PerBit enable=1, Macro0, CA PI delay=37
7521 13:38:33.110145
7522 13:38:33.113388 [CBTSetCACLKResult] CA Dly = 37
7523 13:38:33.116736 CS Dly: 11 (0~42)
7524 13:38:33.119796 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 13:38:33.123229 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 13:38:33.123310 ==
7527 13:38:33.126296 Dram Type= 6, Freq= 0, CH_0, rank 1
7528 13:38:33.133183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 13:38:33.133265 ==
7530 13:38:33.136615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 13:38:33.142963 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 13:38:33.146098 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 13:38:33.153052 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 13:38:33.160933 [CA 0] Center 43 (13~74) winsize 62
7535 13:38:33.164228 [CA 1] Center 43 (13~74) winsize 62
7536 13:38:33.167435 [CA 2] Center 39 (10~68) winsize 59
7537 13:38:33.170655 [CA 3] Center 39 (10~68) winsize 59
7538 13:38:33.173832 [CA 4] Center 36 (6~66) winsize 61
7539 13:38:33.177068 [CA 5] Center 36 (6~66) winsize 61
7540 13:38:33.177149
7541 13:38:33.180935 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7542 13:38:33.181032
7543 13:38:33.187198 [CATrainingPosCal] consider 2 rank data
7544 13:38:33.187293 u2DelayCellTimex100 = 258/100 ps
7545 13:38:33.193939 CA0 delay=44 (14~74),Diff = 7 PI (26 cell)
7546 13:38:33.197264 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7547 13:38:33.200420 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7548 13:38:33.203755 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7549 13:38:33.207131 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
7550 13:38:33.210536 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7551 13:38:33.210631
7552 13:38:33.213683 CA PerBit enable=1, Macro0, CA PI delay=37
7553 13:38:33.213778
7554 13:38:33.217119 [CBTSetCACLKResult] CA Dly = 37
7555 13:38:33.220663 CS Dly: 11 (0~43)
7556 13:38:33.223861 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 13:38:33.227041 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 13:38:33.227136
7559 13:38:33.230124 ----->DramcWriteLeveling(PI) begin...
7560 13:38:33.230220 ==
7561 13:38:33.233704 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 13:38:33.239925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 13:38:33.240011 ==
7564 13:38:33.243398 Write leveling (Byte 0): 35 => 35
7565 13:38:33.246858 Write leveling (Byte 1): 26 => 26
7566 13:38:33.249985 DramcWriteLeveling(PI) end<-----
7567 13:38:33.250084
7568 13:38:33.250174 ==
7569 13:38:33.253135 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 13:38:33.256792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 13:38:33.256868 ==
7572 13:38:33.259998 [Gating] SW mode calibration
7573 13:38:33.266694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7574 13:38:33.270012 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7575 13:38:33.276647 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 13:38:33.279792 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 13:38:33.283040 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 13:38:33.289776 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 13:38:33.292882 1 4 16 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7580 13:38:33.296095 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7581 13:38:33.303140 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7582 13:38:33.306421 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 13:38:33.309294 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 13:38:33.316178 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 13:38:33.319426 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 13:38:33.322737 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 13:38:33.329511 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7588 13:38:33.332238 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7589 13:38:33.335636 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7590 13:38:33.342419 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 13:38:33.345645 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 13:38:33.349251 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:38:33.355746 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 13:38:33.358894 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7595 13:38:33.362135 1 6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7596 13:38:33.369183 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7597 13:38:33.371940 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7598 13:38:33.375403 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 13:38:33.382065 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 13:38:33.385408 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 13:38:33.388789 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 13:38:33.395501 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7603 13:38:33.398773 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7604 13:38:33.402033 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7605 13:38:33.408711 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7606 13:38:33.411963 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 13:38:33.415242 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 13:38:33.421825 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 13:38:33.425134 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 13:38:33.428607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 13:38:33.435450 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 13:38:33.438718 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 13:38:33.441899 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 13:38:33.448377 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:38:33.451837 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:38:33.455245 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:38:33.461684 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:38:33.464809 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:38:33.468355 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 13:38:33.474929 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7621 13:38:33.475009 Total UI for P1: 0, mck2ui 16
7622 13:38:33.481554 best dqsien dly found for B0: ( 1, 9, 16)
7623 13:38:33.485033 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 13:38:33.487735 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 13:38:33.491587 Total UI for P1: 0, mck2ui 16
7626 13:38:33.494783 best dqsien dly found for B1: ( 1, 9, 24)
7627 13:38:33.498091 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7628 13:38:33.500923 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7629 13:38:33.500998
7630 13:38:33.507951 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7631 13:38:33.511372 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7632 13:38:33.514852 [Gating] SW calibration Done
7633 13:38:33.514964 ==
7634 13:38:33.518084 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 13:38:33.521412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 13:38:33.521496 ==
7637 13:38:33.521560 RX Vref Scan: 0
7638 13:38:33.521619
7639 13:38:33.524246 RX Vref 0 -> 0, step: 1
7640 13:38:33.524327
7641 13:38:33.527740 RX Delay 0 -> 252, step: 8
7642 13:38:33.531206 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7643 13:38:33.534494 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7644 13:38:33.537934 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7645 13:38:33.544681 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7646 13:38:33.547306 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7647 13:38:33.550732 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7648 13:38:33.554075 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7649 13:38:33.561146 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7650 13:38:33.563850 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7651 13:38:33.567308 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7652 13:38:33.570684 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7653 13:38:33.574194 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7654 13:38:33.580219 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7655 13:38:33.583997 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7656 13:38:33.587207 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7657 13:38:33.590265 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7658 13:38:33.590378 ==
7659 13:38:33.593714 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 13:38:33.600665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 13:38:33.600751 ==
7662 13:38:33.600816 DQS Delay:
7663 13:38:33.603636 DQS0 = 0, DQS1 = 0
7664 13:38:33.603716 DQM Delay:
7665 13:38:33.603779 DQM0 = 127, DQM1 = 123
7666 13:38:33.607469 DQ Delay:
7667 13:38:33.610608 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7668 13:38:33.613776 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =143
7669 13:38:33.616802 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7670 13:38:33.620094 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =127
7671 13:38:33.620200
7672 13:38:33.620291
7673 13:38:33.620378 ==
7674 13:38:33.623987 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 13:38:33.627265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 13:38:33.630146 ==
7677 13:38:33.630226
7678 13:38:33.630289
7679 13:38:33.630348 TX Vref Scan disable
7680 13:38:33.633457 == TX Byte 0 ==
7681 13:38:33.636746 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7682 13:38:33.640132 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7683 13:38:33.643448 == TX Byte 1 ==
7684 13:38:33.646894 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7685 13:38:33.650233 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7686 13:38:33.653405 ==
7687 13:38:33.653486 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 13:38:33.660099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 13:38:33.660180 ==
7690 13:38:33.673415
7691 13:38:33.676793 TX Vref early break, caculate TX vref
7692 13:38:33.679364 TX Vref=16, minBit 8, minWin=21, winSum=361
7693 13:38:33.682738 TX Vref=18, minBit 4, minWin=22, winSum=368
7694 13:38:33.686127 TX Vref=20, minBit 8, minWin=22, winSum=377
7695 13:38:33.689468 TX Vref=22, minBit 9, minWin=23, winSum=390
7696 13:38:33.692782 TX Vref=24, minBit 4, minWin=24, winSum=402
7697 13:38:33.699617 TX Vref=26, minBit 11, minWin=24, winSum=407
7698 13:38:33.702917 TX Vref=28, minBit 4, minWin=24, winSum=403
7699 13:38:33.705798 TX Vref=30, minBit 4, minWin=24, winSum=398
7700 13:38:33.709373 TX Vref=32, minBit 9, minWin=22, winSum=386
7701 13:38:33.712731 TX Vref=34, minBit 8, minWin=22, winSum=373
7702 13:38:33.719494 [TxChooseVref] Worse bit 11, Min win 24, Win sum 407, Final Vref 26
7703 13:38:33.719577
7704 13:38:33.722587 Final TX Range 0 Vref 26
7705 13:38:33.722668
7706 13:38:33.722730 ==
7707 13:38:33.726204 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 13:38:33.729363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 13:38:33.729444 ==
7710 13:38:33.729508
7711 13:38:33.729566
7712 13:38:33.732413 TX Vref Scan disable
7713 13:38:33.739670 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7714 13:38:33.739754 == TX Byte 0 ==
7715 13:38:33.742710 u2DelayCellOfst[0]=11 cells (3 PI)
7716 13:38:33.745778 u2DelayCellOfst[1]=15 cells (4 PI)
7717 13:38:33.749200 u2DelayCellOfst[2]=7 cells (2 PI)
7718 13:38:33.752724 u2DelayCellOfst[3]=11 cells (3 PI)
7719 13:38:33.756063 u2DelayCellOfst[4]=3 cells (1 PI)
7720 13:38:33.759376 u2DelayCellOfst[5]=0 cells (0 PI)
7721 13:38:33.762715 u2DelayCellOfst[6]=15 cells (4 PI)
7722 13:38:33.765628 u2DelayCellOfst[7]=15 cells (4 PI)
7723 13:38:33.768971 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7724 13:38:33.772375 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7725 13:38:33.775886 == TX Byte 1 ==
7726 13:38:33.779210 u2DelayCellOfst[8]=0 cells (0 PI)
7727 13:38:33.782464 u2DelayCellOfst[9]=3 cells (1 PI)
7728 13:38:33.782544 u2DelayCellOfst[10]=11 cells (3 PI)
7729 13:38:33.785853 u2DelayCellOfst[11]=7 cells (2 PI)
7730 13:38:33.789119 u2DelayCellOfst[12]=15 cells (4 PI)
7731 13:38:33.792452 u2DelayCellOfst[13]=15 cells (4 PI)
7732 13:38:33.795243 u2DelayCellOfst[14]=18 cells (5 PI)
7733 13:38:33.798796 u2DelayCellOfst[15]=15 cells (4 PI)
7734 13:38:33.805442 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7735 13:38:33.808800 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7736 13:38:33.808880 DramC Write-DBI on
7737 13:38:33.808943 ==
7738 13:38:33.812146 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 13:38:33.818778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 13:38:33.818860 ==
7741 13:38:33.818923
7742 13:38:33.818982
7743 13:38:33.821951 TX Vref Scan disable
7744 13:38:33.822031 == TX Byte 0 ==
7745 13:38:33.828411 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7746 13:38:33.828518 == TX Byte 1 ==
7747 13:38:33.831882 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7748 13:38:33.834903 DramC Write-DBI off
7749 13:38:33.834983
7750 13:38:33.835045 [DATLAT]
7751 13:38:33.838646 Freq=1600, CH0 RK0
7752 13:38:33.838727
7753 13:38:33.838790 DATLAT Default: 0xf
7754 13:38:33.841773 0, 0xFFFF, sum = 0
7755 13:38:33.841854 1, 0xFFFF, sum = 0
7756 13:38:33.844879 2, 0xFFFF, sum = 0
7757 13:38:33.844961 3, 0xFFFF, sum = 0
7758 13:38:33.848199 4, 0xFFFF, sum = 0
7759 13:38:33.848280 5, 0xFFFF, sum = 0
7760 13:38:33.851677 6, 0xFFFF, sum = 0
7761 13:38:33.851758 7, 0xFFFF, sum = 0
7762 13:38:33.854732 8, 0xFFFF, sum = 0
7763 13:38:33.857940 9, 0xFFFF, sum = 0
7764 13:38:33.858022 10, 0xFFFF, sum = 0
7765 13:38:33.861799 11, 0xFFFF, sum = 0
7766 13:38:33.861880 12, 0xFFFF, sum = 0
7767 13:38:33.864881 13, 0xEFFF, sum = 0
7768 13:38:33.864962 14, 0x0, sum = 1
7769 13:38:33.868095 15, 0x0, sum = 2
7770 13:38:33.868176 16, 0x0, sum = 3
7771 13:38:33.871370 17, 0x0, sum = 4
7772 13:38:33.871452 best_step = 15
7773 13:38:33.871516
7774 13:38:33.871574 ==
7775 13:38:33.874674 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 13:38:33.877990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 13:38:33.878071 ==
7778 13:38:33.881306 RX Vref Scan: 1
7779 13:38:33.881386
7780 13:38:33.884802 Set Vref Range= 24 -> 127
7781 13:38:33.884882
7782 13:38:33.884944 RX Vref 24 -> 127, step: 1
7783 13:38:33.885004
7784 13:38:33.888103 RX Delay 11 -> 252, step: 4
7785 13:38:33.888183
7786 13:38:33.891371 Set Vref, RX VrefLevel [Byte0]: 24
7787 13:38:33.894779 [Byte1]: 24
7788 13:38:33.898098
7789 13:38:33.898178 Set Vref, RX VrefLevel [Byte0]: 25
7790 13:38:33.901410 [Byte1]: 25
7791 13:38:33.905490
7792 13:38:33.905570 Set Vref, RX VrefLevel [Byte0]: 26
7793 13:38:33.908988 [Byte1]: 26
7794 13:38:33.913763
7795 13:38:33.913843 Set Vref, RX VrefLevel [Byte0]: 27
7796 13:38:33.916424 [Byte1]: 27
7797 13:38:33.921052
7798 13:38:33.921132 Set Vref, RX VrefLevel [Byte0]: 28
7799 13:38:33.924518 [Byte1]: 28
7800 13:38:33.928688
7801 13:38:33.928767 Set Vref, RX VrefLevel [Byte0]: 29
7802 13:38:33.931729 [Byte1]: 29
7803 13:38:33.936215
7804 13:38:33.936312 Set Vref, RX VrefLevel [Byte0]: 30
7805 13:38:33.939336 [Byte1]: 30
7806 13:38:33.943642
7807 13:38:33.943722 Set Vref, RX VrefLevel [Byte0]: 31
7808 13:38:33.946888 [Byte1]: 31
7809 13:38:33.951236
7810 13:38:33.951316 Set Vref, RX VrefLevel [Byte0]: 32
7811 13:38:33.955034 [Byte1]: 32
7812 13:38:33.959043
7813 13:38:33.959123 Set Vref, RX VrefLevel [Byte0]: 33
7814 13:38:33.962416 [Byte1]: 33
7815 13:38:33.966912
7816 13:38:33.966991 Set Vref, RX VrefLevel [Byte0]: 34
7817 13:38:33.970152 [Byte1]: 34
7818 13:38:33.974299
7819 13:38:33.974379 Set Vref, RX VrefLevel [Byte0]: 35
7820 13:38:33.977237 [Byte1]: 35
7821 13:38:33.981928
7822 13:38:33.982011 Set Vref, RX VrefLevel [Byte0]: 36
7823 13:38:33.985362 [Byte1]: 36
7824 13:38:33.989296
7825 13:38:33.989372 Set Vref, RX VrefLevel [Byte0]: 37
7826 13:38:33.992667 [Byte1]: 37
7827 13:38:33.996833
7828 13:38:33.996913 Set Vref, RX VrefLevel [Byte0]: 38
7829 13:38:34.000308 [Byte1]: 38
7830 13:38:34.004450
7831 13:38:34.004530 Set Vref, RX VrefLevel [Byte0]: 39
7832 13:38:34.007802 [Byte1]: 39
7833 13:38:34.012461
7834 13:38:34.012593 Set Vref, RX VrefLevel [Byte0]: 40
7835 13:38:34.015733 [Byte1]: 40
7836 13:38:34.019703
7837 13:38:34.019782 Set Vref, RX VrefLevel [Byte0]: 41
7838 13:38:34.023090 [Byte1]: 41
7839 13:38:34.027884
7840 13:38:34.027964 Set Vref, RX VrefLevel [Byte0]: 42
7841 13:38:34.031232 [Byte1]: 42
7842 13:38:34.035285
7843 13:38:34.035365 Set Vref, RX VrefLevel [Byte0]: 43
7844 13:38:34.038623 [Byte1]: 43
7845 13:38:34.042672
7846 13:38:34.042772 Set Vref, RX VrefLevel [Byte0]: 44
7847 13:38:34.045931 [Byte1]: 44
7848 13:38:34.050400
7849 13:38:34.050480 Set Vref, RX VrefLevel [Byte0]: 45
7850 13:38:34.053841 [Byte1]: 45
7851 13:38:34.058198
7852 13:38:34.058278 Set Vref, RX VrefLevel [Byte0]: 46
7853 13:38:34.061413 [Byte1]: 46
7854 13:38:34.065774
7855 13:38:34.065877 Set Vref, RX VrefLevel [Byte0]: 47
7856 13:38:34.068884 [Byte1]: 47
7857 13:38:34.072952
7858 13:38:34.073031 Set Vref, RX VrefLevel [Byte0]: 48
7859 13:38:34.076275 [Byte1]: 48
7860 13:38:34.080940
7861 13:38:34.081019 Set Vref, RX VrefLevel [Byte0]: 49
7862 13:38:34.084176 [Byte1]: 49
7863 13:38:34.088726
7864 13:38:34.088855 Set Vref, RX VrefLevel [Byte0]: 50
7865 13:38:34.091889 [Byte1]: 50
7866 13:38:34.096280
7867 13:38:34.096360 Set Vref, RX VrefLevel [Byte0]: 51
7868 13:38:34.099113 [Byte1]: 51
7869 13:38:34.103919
7870 13:38:34.103997 Set Vref, RX VrefLevel [Byte0]: 52
7871 13:38:34.107029 [Byte1]: 52
7872 13:38:34.111524
7873 13:38:34.111631 Set Vref, RX VrefLevel [Byte0]: 53
7874 13:38:34.114855 [Byte1]: 53
7875 13:38:34.118995
7876 13:38:34.119098 Set Vref, RX VrefLevel [Byte0]: 54
7877 13:38:34.122264 [Byte1]: 54
7878 13:38:34.126201
7879 13:38:34.126270 Set Vref, RX VrefLevel [Byte0]: 55
7880 13:38:34.130151 [Byte1]: 55
7881 13:38:34.134192
7882 13:38:34.134298 Set Vref, RX VrefLevel [Byte0]: 56
7883 13:38:34.137500 [Byte1]: 56
7884 13:38:34.141396
7885 13:38:34.141469 Set Vref, RX VrefLevel [Byte0]: 57
7886 13:38:34.144869 [Byte1]: 57
7887 13:38:34.149469
7888 13:38:34.149539 Set Vref, RX VrefLevel [Byte0]: 58
7889 13:38:34.152646 [Byte1]: 58
7890 13:38:34.156992
7891 13:38:34.157065 Set Vref, RX VrefLevel [Byte0]: 59
7892 13:38:34.160387 [Byte1]: 59
7893 13:38:34.165173
7894 13:38:34.165255 Set Vref, RX VrefLevel [Byte0]: 60
7895 13:38:34.167770 [Byte1]: 60
7896 13:38:34.172448
7897 13:38:34.172555 Set Vref, RX VrefLevel [Byte0]: 61
7898 13:38:34.175483 [Byte1]: 61
7899 13:38:34.179664
7900 13:38:34.179743 Set Vref, RX VrefLevel [Byte0]: 62
7901 13:38:34.182954 [Byte1]: 62
7902 13:38:34.187648
7903 13:38:34.187729 Set Vref, RX VrefLevel [Byte0]: 63
7904 13:38:34.190949 [Byte1]: 63
7905 13:38:34.194923
7906 13:38:34.195026 Set Vref, RX VrefLevel [Byte0]: 64
7907 13:38:34.198340 [Byte1]: 64
7908 13:38:34.202394
7909 13:38:34.202504 Set Vref, RX VrefLevel [Byte0]: 65
7910 13:38:34.205586 [Byte1]: 65
7911 13:38:34.209949
7912 13:38:34.210050 Set Vref, RX VrefLevel [Byte0]: 66
7913 13:38:34.213236 [Byte1]: 66
7914 13:38:34.217597
7915 13:38:34.217678 Set Vref, RX VrefLevel [Byte0]: 67
7916 13:38:34.221343 [Byte1]: 67
7917 13:38:34.225676
7918 13:38:34.225754 Set Vref, RX VrefLevel [Byte0]: 68
7919 13:38:34.229143 [Byte1]: 68
7920 13:38:34.233169
7921 13:38:34.233245 Set Vref, RX VrefLevel [Byte0]: 69
7922 13:38:34.236712 [Byte1]: 69
7923 13:38:34.240751
7924 13:38:34.240825 Set Vref, RX VrefLevel [Byte0]: 70
7925 13:38:34.244020 [Byte1]: 70
7926 13:38:34.248625
7927 13:38:34.248700 Set Vref, RX VrefLevel [Byte0]: 71
7928 13:38:34.251938 [Byte1]: 71
7929 13:38:34.255889
7930 13:38:34.256002 Set Vref, RX VrefLevel [Byte0]: 72
7931 13:38:34.259241 [Byte1]: 72
7932 13:38:34.263481
7933 13:38:34.263563 Set Vref, RX VrefLevel [Byte0]: 73
7934 13:38:34.266695 [Byte1]: 73
7935 13:38:34.271371
7936 13:38:34.271452 Set Vref, RX VrefLevel [Byte0]: 74
7937 13:38:34.274675 [Byte1]: 74
7938 13:38:34.278675
7939 13:38:34.278771 Set Vref, RX VrefLevel [Byte0]: 75
7940 13:38:34.281994 [Byte1]: 75
7941 13:38:34.286676
7942 13:38:34.286780 Set Vref, RX VrefLevel [Byte0]: 76
7943 13:38:34.289645 [Byte1]: 76
7944 13:38:34.294182
7945 13:38:34.294265 Set Vref, RX VrefLevel [Byte0]: 77
7946 13:38:34.297356 [Byte1]: 77
7947 13:38:34.301249
7948 13:38:34.301329 Final RX Vref Byte 0 = 61 to rank0
7949 13:38:34.305183 Final RX Vref Byte 1 = 60 to rank0
7950 13:38:34.307893 Final RX Vref Byte 0 = 61 to rank1
7951 13:38:34.311935 Final RX Vref Byte 1 = 60 to rank1==
7952 13:38:34.314575 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 13:38:34.321272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 13:38:34.321355 ==
7955 13:38:34.321419 DQS Delay:
7956 13:38:34.321478 DQS0 = 0, DQS1 = 0
7957 13:38:34.324635 DQM Delay:
7958 13:38:34.324716 DQM0 = 126, DQM1 = 120
7959 13:38:34.327948 DQ Delay:
7960 13:38:34.331184 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
7961 13:38:34.334945 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
7962 13:38:34.338071 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7963 13:38:34.341375 DQ12 =124, DQ13 =124, DQ14 =132, DQ15 =128
7964 13:38:34.341455
7965 13:38:34.341518
7966 13:38:34.341576
7967 13:38:34.344765 [DramC_TX_OE_Calibration] TA2
7968 13:38:34.347912 Original DQ_B0 (3 6) =30, OEN = 27
7969 13:38:34.351180 Original DQ_B1 (3 6) =30, OEN = 27
7970 13:38:34.354469 24, 0x0, End_B0=24 End_B1=24
7971 13:38:34.354551 25, 0x0, End_B0=25 End_B1=25
7972 13:38:34.357889 26, 0x0, End_B0=26 End_B1=26
7973 13:38:34.361212 27, 0x0, End_B0=27 End_B1=27
7974 13:38:34.364708 28, 0x0, End_B0=28 End_B1=28
7975 13:38:34.367963 29, 0x0, End_B0=29 End_B1=29
7976 13:38:34.368044 30, 0x0, End_B0=30 End_B1=30
7977 13:38:34.370960 31, 0x4141, End_B0=30 End_B1=30
7978 13:38:34.374019 Byte0 end_step=30 best_step=27
7979 13:38:34.377382 Byte1 end_step=30 best_step=27
7980 13:38:34.380712 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 13:38:34.384153 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 13:38:34.384233
7983 13:38:34.384296
7984 13:38:34.390811 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7985 13:38:34.394117 CH0 RK0: MR19=303, MR18=1313
7986 13:38:34.400566 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
7987 13:38:34.400664
7988 13:38:34.404229 ----->DramcWriteLeveling(PI) begin...
7989 13:38:34.404337 ==
7990 13:38:34.407312 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 13:38:34.410557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 13:38:34.410639 ==
7993 13:38:34.414046 Write leveling (Byte 0): 35 => 35
7994 13:38:34.417389 Write leveling (Byte 1): 29 => 29
7995 13:38:34.420595 DramcWriteLeveling(PI) end<-----
7996 13:38:34.420689
7997 13:38:34.420752 ==
7998 13:38:34.424054 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 13:38:34.427527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 13:38:34.427608 ==
8001 13:38:34.430819 [Gating] SW mode calibration
8002 13:38:34.437445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 13:38:34.444144 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 13:38:34.447368 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 13:38:34.453784 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 13:38:34.457048 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 13:38:34.460450 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8008 13:38:34.467122 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8009 13:38:34.470361 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8010 13:38:34.473777 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 13:38:34.480141 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 13:38:34.483745 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 13:38:34.487143 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 13:38:34.493249 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8015 13:38:34.496472 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8016 13:38:34.499837 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8017 13:38:34.506664 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8018 13:38:34.510311 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 13:38:34.513341 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 13:38:34.519751 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 13:38:34.523464 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 13:38:34.526853 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 13:38:34.533342 1 6 12 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
8024 13:38:34.536029 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8025 13:38:34.539402 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 13:38:34.546170 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 13:38:34.549487 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 13:38:34.552887 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 13:38:34.559253 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 13:38:34.562845 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 13:38:34.565753 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 13:38:34.572403 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8033 13:38:34.575781 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 13:38:34.579089 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 13:38:34.586035 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:38:34.589280 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:38:34.592294 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:38:34.599208 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:38:34.602583 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:38:34.605737 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:38:34.612253 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:38:34.615465 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 13:38:34.618728 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:38:34.621984 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:38:34.628844 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 13:38:34.632075 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 13:38:34.635225 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 13:38:34.642487 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 13:38:34.645848 Total UI for P1: 0, mck2ui 16
8050 13:38:34.649135 best dqsien dly found for B0: ( 1, 9, 12)
8051 13:38:34.651822 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 13:38:34.655369 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 13:38:34.658776 Total UI for P1: 0, mck2ui 16
8054 13:38:34.662168 best dqsien dly found for B1: ( 1, 9, 18)
8055 13:38:34.665633 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8056 13:38:34.668929 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8057 13:38:34.672119
8058 13:38:34.675126 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8059 13:38:34.678738 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8060 13:38:34.681912 [Gating] SW calibration Done
8061 13:38:34.682000 ==
8062 13:38:34.685277 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 13:38:34.688715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 13:38:34.688796 ==
8065 13:38:34.692040 RX Vref Scan: 0
8066 13:38:34.692121
8067 13:38:34.692184 RX Vref 0 -> 0, step: 1
8068 13:38:34.692244
8069 13:38:34.695408 RX Delay 0 -> 252, step: 8
8070 13:38:34.698513 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8071 13:38:34.701563 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8072 13:38:34.708395 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8073 13:38:34.711879 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8074 13:38:34.714525 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8075 13:38:34.717827 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8076 13:38:34.721317 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8077 13:38:34.728153 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8078 13:38:34.731529 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8079 13:38:34.734522 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8080 13:38:34.737922 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8081 13:38:34.744447 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8082 13:38:34.747800 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8083 13:38:34.751268 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8084 13:38:34.754221 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8085 13:38:34.758107 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8086 13:38:34.758187 ==
8087 13:38:34.761363 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 13:38:34.767728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 13:38:34.767840 ==
8090 13:38:34.767933 DQS Delay:
8091 13:38:34.771076 DQS0 = 0, DQS1 = 0
8092 13:38:34.771157 DQM Delay:
8093 13:38:34.774228 DQM0 = 128, DQM1 = 122
8094 13:38:34.774308 DQ Delay:
8095 13:38:34.777478 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8096 13:38:34.780767 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8097 13:38:34.784095 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8098 13:38:34.787733 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8099 13:38:34.787838
8100 13:38:34.787919
8101 13:38:34.787978 ==
8102 13:38:34.790820 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 13:38:34.797579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 13:38:34.797679 ==
8105 13:38:34.797744
8106 13:38:34.797803
8107 13:38:34.797859 TX Vref Scan disable
8108 13:38:34.801451 == TX Byte 0 ==
8109 13:38:34.804136 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8110 13:38:34.811154 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8111 13:38:34.811239 == TX Byte 1 ==
8112 13:38:34.814263 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8113 13:38:34.820675 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8114 13:38:34.820762 ==
8115 13:38:34.824512 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:38:34.827133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:38:34.827216 ==
8118 13:38:34.841675
8119 13:38:34.845361 TX Vref early break, caculate TX vref
8120 13:38:34.848764 TX Vref=16, minBit 8, minWin=22, winSum=371
8121 13:38:34.852019 TX Vref=18, minBit 8, minWin=22, winSum=378
8122 13:38:34.854734 TX Vref=20, minBit 8, minWin=22, winSum=388
8123 13:38:34.858055 TX Vref=22, minBit 0, minWin=24, winSum=397
8124 13:38:34.861886 TX Vref=24, minBit 0, minWin=24, winSum=398
8125 13:38:34.868423 TX Vref=26, minBit 0, minWin=25, winSum=409
8126 13:38:34.871711 TX Vref=28, minBit 2, minWin=25, winSum=415
8127 13:38:34.875086 TX Vref=30, minBit 8, minWin=24, winSum=407
8128 13:38:34.877798 TX Vref=32, minBit 4, minWin=24, winSum=403
8129 13:38:34.881250 TX Vref=34, minBit 8, minWin=23, winSum=394
8130 13:38:34.884544 TX Vref=36, minBit 8, minWin=22, winSum=386
8131 13:38:34.891446 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 28
8132 13:38:34.891541
8133 13:38:34.894614 Final TX Range 0 Vref 28
8134 13:38:34.894713
8135 13:38:34.894805 ==
8136 13:38:34.897767 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 13:38:34.901062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 13:38:34.901147 ==
8139 13:38:34.904308
8140 13:38:34.904414
8141 13:38:34.904517 TX Vref Scan disable
8142 13:38:34.911134 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8143 13:38:34.911254 == TX Byte 0 ==
8144 13:38:34.914480 u2DelayCellOfst[0]=11 cells (3 PI)
8145 13:38:34.917787 u2DelayCellOfst[1]=18 cells (5 PI)
8146 13:38:34.920925 u2DelayCellOfst[2]=11 cells (3 PI)
8147 13:38:34.924060 u2DelayCellOfst[3]=11 cells (3 PI)
8148 13:38:34.927737 u2DelayCellOfst[4]=7 cells (2 PI)
8149 13:38:34.930909 u2DelayCellOfst[5]=0 cells (0 PI)
8150 13:38:34.934528 u2DelayCellOfst[6]=18 cells (5 PI)
8151 13:38:34.937617 u2DelayCellOfst[7]=18 cells (5 PI)
8152 13:38:34.941074 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8153 13:38:34.944260 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8154 13:38:34.947492 == TX Byte 1 ==
8155 13:38:34.950691 u2DelayCellOfst[8]=0 cells (0 PI)
8156 13:38:34.954637 u2DelayCellOfst[9]=0 cells (0 PI)
8157 13:38:34.957306 u2DelayCellOfst[10]=3 cells (1 PI)
8158 13:38:34.960511 u2DelayCellOfst[11]=3 cells (1 PI)
8159 13:38:34.963829 u2DelayCellOfst[12]=11 cells (3 PI)
8160 13:38:34.963925 u2DelayCellOfst[13]=11 cells (3 PI)
8161 13:38:34.967138 u2DelayCellOfst[14]=11 cells (3 PI)
8162 13:38:34.970444 u2DelayCellOfst[15]=7 cells (2 PI)
8163 13:38:34.977369 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8164 13:38:34.980727 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8165 13:38:34.980819 DramC Write-DBI on
8166 13:38:34.983951 ==
8167 13:38:34.987349 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 13:38:34.990741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 13:38:34.990826 ==
8170 13:38:34.990891
8171 13:38:34.990950
8172 13:38:34.993517 TX Vref Scan disable
8173 13:38:34.993599 == TX Byte 0 ==
8174 13:38:35.000288 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8175 13:38:35.000373 == TX Byte 1 ==
8176 13:38:35.003482 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8177 13:38:35.006666 DramC Write-DBI off
8178 13:38:35.006747
8179 13:38:35.006811 [DATLAT]
8180 13:38:35.010321 Freq=1600, CH0 RK1
8181 13:38:35.010403
8182 13:38:35.010475 DATLAT Default: 0xf
8183 13:38:35.013609 0, 0xFFFF, sum = 0
8184 13:38:35.013692 1, 0xFFFF, sum = 0
8185 13:38:35.016822 2, 0xFFFF, sum = 0
8186 13:38:35.016930 3, 0xFFFF, sum = 0
8187 13:38:35.020264 4, 0xFFFF, sum = 0
8188 13:38:35.023402 5, 0xFFFF, sum = 0
8189 13:38:35.023533 6, 0xFFFF, sum = 0
8190 13:38:35.026672 7, 0xFFFF, sum = 0
8191 13:38:35.026782 8, 0xFFFF, sum = 0
8192 13:38:35.030038 9, 0xFFFF, sum = 0
8193 13:38:35.030138 10, 0xFFFF, sum = 0
8194 13:38:35.032989 11, 0xFFFF, sum = 0
8195 13:38:35.033065 12, 0xFFFF, sum = 0
8196 13:38:35.036813 13, 0xCFFF, sum = 0
8197 13:38:35.036913 14, 0x0, sum = 1
8198 13:38:35.039952 15, 0x0, sum = 2
8199 13:38:35.040066 16, 0x0, sum = 3
8200 13:38:35.042979 17, 0x0, sum = 4
8201 13:38:35.043077 best_step = 15
8202 13:38:35.043163
8203 13:38:35.043249 ==
8204 13:38:35.046715 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 13:38:35.050115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 13:38:35.052903 ==
8207 13:38:35.052975 RX Vref Scan: 0
8208 13:38:35.053035
8209 13:38:35.056204 RX Vref 0 -> 0, step: 1
8210 13:38:35.056310
8211 13:38:35.056410 RX Delay 3 -> 252, step: 4
8212 13:38:35.063874 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8213 13:38:35.067150 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8214 13:38:35.070440 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8215 13:38:35.073933 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8216 13:38:35.080545 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8217 13:38:35.083773 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8218 13:38:35.087007 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8219 13:38:35.090239 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8220 13:38:35.093627 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8221 13:38:35.100455 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8222 13:38:35.103730 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8223 13:38:35.106992 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8224 13:38:35.110317 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8225 13:38:35.113519 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8226 13:38:35.119814 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8227 13:38:35.123686 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8228 13:38:35.123769 ==
8229 13:38:35.126464 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 13:38:35.130402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 13:38:35.130485 ==
8232 13:38:35.130550 DQS Delay:
8233 13:38:35.133760 DQS0 = 0, DQS1 = 0
8234 13:38:35.133841 DQM Delay:
8235 13:38:35.136991 DQM0 = 124, DQM1 = 118
8236 13:38:35.137072 DQ Delay:
8237 13:38:35.140263 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =122
8238 13:38:35.143604 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8239 13:38:35.147025 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8240 13:38:35.153193 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8241 13:38:35.153284
8242 13:38:35.153350
8243 13:38:35.153408
8244 13:38:35.157037 [DramC_TX_OE_Calibration] TA2
8245 13:38:35.157134 Original DQ_B0 (3 6) =30, OEN = 27
8246 13:38:35.159810 Original DQ_B1 (3 6) =30, OEN = 27
8247 13:38:35.163177 24, 0x0, End_B0=24 End_B1=24
8248 13:38:35.166207 25, 0x0, End_B0=25 End_B1=25
8249 13:38:35.170074 26, 0x0, End_B0=26 End_B1=26
8250 13:38:35.173339 27, 0x0, End_B0=27 End_B1=27
8251 13:38:35.173443 28, 0x0, End_B0=28 End_B1=28
8252 13:38:35.176815 29, 0x0, End_B0=29 End_B1=29
8253 13:38:35.180088 30, 0x0, End_B0=30 End_B1=30
8254 13:38:35.183288 31, 0x4141, End_B0=30 End_B1=30
8255 13:38:35.186488 Byte0 end_step=30 best_step=27
8256 13:38:35.186572 Byte1 end_step=30 best_step=27
8257 13:38:35.189895 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 13:38:35.193335 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 13:38:35.193471
8260 13:38:35.193552
8261 13:38:35.202704 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8262 13:38:35.202812 CH0 RK1: MR19=303, MR18=2412
8263 13:38:35.209446 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8264 13:38:35.212702 [RxdqsGatingPostProcess] freq 1600
8265 13:38:35.219378 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 13:38:35.222621 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 13:38:35.225958 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 13:38:35.229045 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 13:38:35.232282 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 13:38:35.236081 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 13:38:35.236163 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 13:38:35.239554 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 13:38:35.242944 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 13:38:35.246098 Pre-setting of DQS Precalculation
8275 13:38:35.252122 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 13:38:35.252205 ==
8277 13:38:35.256023 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 13:38:35.259383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 13:38:35.259465 ==
8280 13:38:35.265577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 13:38:35.269092 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 13:38:35.272437 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 13:38:35.278540 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 13:38:35.288395 [CA 0] Center 41 (12~71) winsize 60
8285 13:38:35.291762 [CA 1] Center 42 (12~72) winsize 61
8286 13:38:35.294520 [CA 2] Center 37 (9~66) winsize 58
8287 13:38:35.297796 [CA 3] Center 36 (7~66) winsize 60
8288 13:38:35.301623 [CA 4] Center 37 (8~66) winsize 59
8289 13:38:35.304984 [CA 5] Center 36 (7~66) winsize 60
8290 13:38:35.305072
8291 13:38:35.307807 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8292 13:38:35.307923
8293 13:38:35.311026 [CATrainingPosCal] consider 1 rank data
8294 13:38:35.314453 u2DelayCellTimex100 = 258/100 ps
8295 13:38:35.317889 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8296 13:38:35.324714 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8297 13:38:35.328010 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8298 13:38:35.331246 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8299 13:38:35.334706 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8300 13:38:35.337887 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 13:38:35.337977
8302 13:38:35.341056 CA PerBit enable=1, Macro0, CA PI delay=36
8303 13:38:35.341152
8304 13:38:35.344187 [CBTSetCACLKResult] CA Dly = 36
8305 13:38:35.348055 CS Dly: 9 (0~40)
8306 13:38:35.351192 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 13:38:35.354591 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 13:38:35.354674 ==
8309 13:38:35.357835 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 13:38:35.361114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 13:38:35.364410 ==
8312 13:38:35.367394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 13:38:35.371223 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 13:38:35.377804 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 13:38:35.381051 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 13:38:35.391555 [CA 0] Center 42 (13~71) winsize 59
8317 13:38:35.394280 [CA 1] Center 42 (12~72) winsize 61
8318 13:38:35.397778 [CA 2] Center 37 (8~67) winsize 60
8319 13:38:35.401069 [CA 3] Center 36 (7~66) winsize 60
8320 13:38:35.404431 [CA 4] Center 38 (8~68) winsize 61
8321 13:38:35.407765 [CA 5] Center 37 (7~67) winsize 61
8322 13:38:35.407847
8323 13:38:35.410963 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 13:38:35.411044
8325 13:38:35.414548 [CATrainingPosCal] consider 2 rank data
8326 13:38:35.417786 u2DelayCellTimex100 = 258/100 ps
8327 13:38:35.424087 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8328 13:38:35.427417 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8329 13:38:35.430623 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8330 13:38:35.433988 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8331 13:38:35.437821 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8332 13:38:35.440678 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 13:38:35.440759
8334 13:38:35.444098 CA PerBit enable=1, Macro0, CA PI delay=36
8335 13:38:35.444179
8336 13:38:35.447261 [CBTSetCACLKResult] CA Dly = 36
8337 13:38:35.450440 CS Dly: 10 (0~43)
8338 13:38:35.453737 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 13:38:35.456993 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 13:38:35.457074
8341 13:38:35.460731 ----->DramcWriteLeveling(PI) begin...
8342 13:38:35.460814 ==
8343 13:38:35.464134 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 13:38:35.470759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 13:38:35.470843 ==
8346 13:38:35.474050 Write leveling (Byte 0): 26 => 26
8347 13:38:35.477292 Write leveling (Byte 1): 29 => 29
8348 13:38:35.477374 DramcWriteLeveling(PI) end<-----
8349 13:38:35.477437
8350 13:38:35.480734 ==
8351 13:38:35.484175 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 13:38:35.486821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 13:38:35.486903 ==
8354 13:38:35.490261 [Gating] SW mode calibration
8355 13:38:35.496996 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 13:38:35.499979 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 13:38:35.506603 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 13:38:35.509941 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 13:38:35.513264 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 13:38:35.519931 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8361 13:38:35.523241 1 4 16 | B1->B0 | 3131 3130 | 1 1 | (1 1) (0 0)
8362 13:38:35.526572 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 13:38:35.533405 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 13:38:35.536703 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 13:38:35.540057 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 13:38:35.546651 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 13:38:35.549920 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 13:38:35.553268 1 5 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 0)
8369 13:38:35.559953 1 5 16 | B1->B0 | 2727 2727 | 0 1 | (1 0) (1 0)
8370 13:38:35.563277 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 13:38:35.566621 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 13:38:35.573063 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 13:38:35.576343 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 13:38:35.579634 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 13:38:35.586144 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 13:38:35.589459 1 6 12 | B1->B0 | 2c2c 2525 | 1 0 | (0 0) (0 0)
8377 13:38:35.592755 1 6 16 | B1->B0 | 4444 4444 | 1 1 | (0 0) (0 0)
8378 13:38:35.599533 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 13:38:35.602835 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 13:38:35.606083 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 13:38:35.612739 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 13:38:35.615913 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 13:38:35.619118 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 13:38:35.625809 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8385 13:38:35.629150 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 13:38:35.632388 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:38:35.639071 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:38:35.642328 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:38:35.645771 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:38:35.652430 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:38:35.655740 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:38:35.659174 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:38:35.665773 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:38:35.669086 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:38:35.672450 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:38:35.678886 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:38:35.682418 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:38:35.685770 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:38:35.692283 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:38:35.695732 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:38:35.699110 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 13:38:35.705247 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 13:38:35.705330 Total UI for P1: 0, mck2ui 16
8404 13:38:35.708444 best dqsien dly found for B0: ( 1, 9, 16)
8405 13:38:35.711995 Total UI for P1: 0, mck2ui 16
8406 13:38:35.715112 best dqsien dly found for B1: ( 1, 9, 16)
8407 13:38:35.718801 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8408 13:38:35.725573 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8409 13:38:35.725655
8410 13:38:35.728479 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 13:38:35.731632 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 13:38:35.734887 [Gating] SW calibration Done
8413 13:38:35.734969 ==
8414 13:38:35.738304 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 13:38:35.741640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 13:38:35.741722 ==
8417 13:38:35.744954 RX Vref Scan: 0
8418 13:38:35.745059
8419 13:38:35.745126 RX Vref 0 -> 0, step: 1
8420 13:38:35.745192
8421 13:38:35.748852 RX Delay 0 -> 252, step: 8
8422 13:38:35.752173 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8423 13:38:35.755403 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8424 13:38:35.761990 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8425 13:38:35.765497 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8426 13:38:35.768732 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8427 13:38:35.771894 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8428 13:38:35.775538 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8429 13:38:35.781955 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8430 13:38:35.785194 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8431 13:38:35.788436 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8432 13:38:35.791737 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8433 13:38:35.795109 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8434 13:38:35.801523 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8435 13:38:35.804871 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8436 13:38:35.808214 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8437 13:38:35.811639 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8438 13:38:35.811721 ==
8439 13:38:35.814908 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 13:38:35.821791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 13:38:35.821874 ==
8442 13:38:35.821940 DQS Delay:
8443 13:38:35.825083 DQS0 = 0, DQS1 = 0
8444 13:38:35.825164 DQM Delay:
8445 13:38:35.828555 DQM0 = 132, DQM1 = 126
8446 13:38:35.828675 DQ Delay:
8447 13:38:35.831257 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8448 13:38:35.835081 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8449 13:38:35.838262 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8450 13:38:35.841440 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8451 13:38:35.841521
8452 13:38:35.841585
8453 13:38:35.841644 ==
8454 13:38:35.845212 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 13:38:35.848425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 13:38:35.851522 ==
8457 13:38:35.851607
8458 13:38:35.851686
8459 13:38:35.851746 TX Vref Scan disable
8460 13:38:35.854816 == TX Byte 0 ==
8461 13:38:35.858335 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8462 13:38:35.861685 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 13:38:35.864988 == TX Byte 1 ==
8464 13:38:35.867683 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8465 13:38:35.871040 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8466 13:38:35.874407 ==
8467 13:38:35.877762 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:38:35.881018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:38:35.881102 ==
8470 13:38:35.893402
8471 13:38:35.896722 TX Vref early break, caculate TX vref
8472 13:38:35.900091 TX Vref=16, minBit 8, minWin=21, winSum=359
8473 13:38:35.903363 TX Vref=18, minBit 11, minWin=21, winSum=371
8474 13:38:35.906577 TX Vref=20, minBit 9, minWin=22, winSum=380
8475 13:38:35.909740 TX Vref=22, minBit 8, minWin=23, winSum=392
8476 13:38:35.913120 TX Vref=24, minBit 11, minWin=23, winSum=401
8477 13:38:35.919822 TX Vref=26, minBit 13, minWin=24, winSum=411
8478 13:38:35.923147 TX Vref=28, minBit 1, minWin=25, winSum=416
8479 13:38:35.926495 TX Vref=30, minBit 0, minWin=25, winSum=413
8480 13:38:35.929714 TX Vref=32, minBit 9, minWin=23, winSum=403
8481 13:38:35.933148 TX Vref=34, minBit 1, minWin=23, winSum=391
8482 13:38:35.939811 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
8483 13:38:35.939894
8484 13:38:35.943153 Final TX Range 0 Vref 28
8485 13:38:35.943234
8486 13:38:35.943371 ==
8487 13:38:35.946341 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 13:38:35.949642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 13:38:35.949725 ==
8490 13:38:35.949789
8491 13:38:35.949847
8492 13:38:35.952899 TX Vref Scan disable
8493 13:38:35.959137 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8494 13:38:35.959223 == TX Byte 0 ==
8495 13:38:35.962958 u2DelayCellOfst[0]=18 cells (5 PI)
8496 13:38:35.966281 u2DelayCellOfst[1]=11 cells (3 PI)
8497 13:38:35.969258 u2DelayCellOfst[2]=0 cells (0 PI)
8498 13:38:35.972570 u2DelayCellOfst[3]=7 cells (2 PI)
8499 13:38:35.975918 u2DelayCellOfst[4]=7 cells (2 PI)
8500 13:38:35.979339 u2DelayCellOfst[5]=22 cells (6 PI)
8501 13:38:35.982616 u2DelayCellOfst[6]=22 cells (6 PI)
8502 13:38:35.985883 u2DelayCellOfst[7]=7 cells (2 PI)
8503 13:38:35.989091 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8504 13:38:35.992474 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8505 13:38:35.995922 == TX Byte 1 ==
8506 13:38:35.999045 u2DelayCellOfst[8]=0 cells (0 PI)
8507 13:38:36.002426 u2DelayCellOfst[9]=7 cells (2 PI)
8508 13:38:36.002529 u2DelayCellOfst[10]=11 cells (3 PI)
8509 13:38:36.006009 u2DelayCellOfst[11]=7 cells (2 PI)
8510 13:38:36.008699 u2DelayCellOfst[12]=15 cells (4 PI)
8511 13:38:36.012128 u2DelayCellOfst[13]=22 cells (6 PI)
8512 13:38:36.015220 u2DelayCellOfst[14]=18 cells (5 PI)
8513 13:38:36.018494 u2DelayCellOfst[15]=18 cells (5 PI)
8514 13:38:36.025155 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8515 13:38:36.028554 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8516 13:38:36.028662 DramC Write-DBI on
8517 13:38:36.032069 ==
8518 13:38:36.032144 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 13:38:36.038659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 13:38:36.038749 ==
8521 13:38:36.038814
8522 13:38:36.038873
8523 13:38:36.041915 TX Vref Scan disable
8524 13:38:36.041985 == TX Byte 0 ==
8525 13:38:36.048448 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8526 13:38:36.048568 == TX Byte 1 ==
8527 13:38:36.051821 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8528 13:38:36.055167 DramC Write-DBI off
8529 13:38:36.055282
8530 13:38:36.055372 [DATLAT]
8531 13:38:36.058519 Freq=1600, CH1 RK0
8532 13:38:36.058627
8533 13:38:36.058717 DATLAT Default: 0xf
8534 13:38:36.061650 0, 0xFFFF, sum = 0
8535 13:38:36.061772 1, 0xFFFF, sum = 0
8536 13:38:36.064786 2, 0xFFFF, sum = 0
8537 13:38:36.064876 3, 0xFFFF, sum = 0
8538 13:38:36.068121 4, 0xFFFF, sum = 0
8539 13:38:36.068238 5, 0xFFFF, sum = 0
8540 13:38:36.071339 6, 0xFFFF, sum = 0
8541 13:38:36.071428 7, 0xFFFF, sum = 0
8542 13:38:36.074932 8, 0xFFFF, sum = 0
8543 13:38:36.078081 9, 0xFFFF, sum = 0
8544 13:38:36.078154 10, 0xFFFF, sum = 0
8545 13:38:36.081737 11, 0xFFFF, sum = 0
8546 13:38:36.081813 12, 0xFFFF, sum = 0
8547 13:38:36.084553 13, 0x8FFF, sum = 0
8548 13:38:36.084672 14, 0x0, sum = 1
8549 13:38:36.088281 15, 0x0, sum = 2
8550 13:38:36.088361 16, 0x0, sum = 3
8551 13:38:36.091382 17, 0x0, sum = 4
8552 13:38:36.091456 best_step = 15
8553 13:38:36.091522
8554 13:38:36.091580 ==
8555 13:38:36.094426 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 13:38:36.097903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 13:38:36.097993 ==
8558 13:38:36.101063 RX Vref Scan: 1
8559 13:38:36.101136
8560 13:38:36.104428 Set Vref Range= 24 -> 127
8561 13:38:36.104540
8562 13:38:36.104630 RX Vref 24 -> 127, step: 1
8563 13:38:36.104688
8564 13:38:36.107718 RX Delay 11 -> 252, step: 4
8565 13:38:36.107792
8566 13:38:36.111080 Set Vref, RX VrefLevel [Byte0]: 24
8567 13:38:36.114481 [Byte1]: 24
8568 13:38:36.117759
8569 13:38:36.117861 Set Vref, RX VrefLevel [Byte0]: 25
8570 13:38:36.121549 [Byte1]: 25
8571 13:38:36.125884
8572 13:38:36.125962 Set Vref, RX VrefLevel [Byte0]: 26
8573 13:38:36.128710 [Byte1]: 26
8574 13:38:36.133472
8575 13:38:36.133558 Set Vref, RX VrefLevel [Byte0]: 27
8576 13:38:36.136723 [Byte1]: 27
8577 13:38:36.140736
8578 13:38:36.140817 Set Vref, RX VrefLevel [Byte0]: 28
8579 13:38:36.144160 [Byte1]: 28
8580 13:38:36.148765
8581 13:38:36.148845 Set Vref, RX VrefLevel [Byte0]: 29
8582 13:38:36.152030 [Byte1]: 29
8583 13:38:36.156065
8584 13:38:36.156152 Set Vref, RX VrefLevel [Byte0]: 30
8585 13:38:36.159414 [Byte1]: 30
8586 13:38:36.164100
8587 13:38:36.164180 Set Vref, RX VrefLevel [Byte0]: 31
8588 13:38:36.166734 [Byte1]: 31
8589 13:38:36.171214
8590 13:38:36.171313 Set Vref, RX VrefLevel [Byte0]: 32
8591 13:38:36.174331 [Byte1]: 32
8592 13:38:36.179145
8593 13:38:36.179279 Set Vref, RX VrefLevel [Byte0]: 33
8594 13:38:36.182368 [Byte1]: 33
8595 13:38:36.186278
8596 13:38:36.186383 Set Vref, RX VrefLevel [Byte0]: 34
8597 13:38:36.190064 [Byte1]: 34
8598 13:38:36.194367
8599 13:38:36.194471 Set Vref, RX VrefLevel [Byte0]: 35
8600 13:38:36.197506 [Byte1]: 35
8601 13:38:36.201831
8602 13:38:36.201920 Set Vref, RX VrefLevel [Byte0]: 36
8603 13:38:36.205100 [Byte1]: 36
8604 13:38:36.209312
8605 13:38:36.209390 Set Vref, RX VrefLevel [Byte0]: 37
8606 13:38:36.212650 [Byte1]: 37
8607 13:38:36.217238
8608 13:38:36.217311 Set Vref, RX VrefLevel [Byte0]: 38
8609 13:38:36.220684 [Byte1]: 38
8610 13:38:36.224698
8611 13:38:36.224779 Set Vref, RX VrefLevel [Byte0]: 39
8612 13:38:36.227985 [Byte1]: 39
8613 13:38:36.232248
8614 13:38:36.232335 Set Vref, RX VrefLevel [Byte0]: 40
8615 13:38:36.235670 [Byte1]: 40
8616 13:38:36.239775
8617 13:38:36.239852 Set Vref, RX VrefLevel [Byte0]: 41
8618 13:38:36.242994 [Byte1]: 41
8619 13:38:36.247762
8620 13:38:36.247839 Set Vref, RX VrefLevel [Byte0]: 42
8621 13:38:36.250493 [Byte1]: 42
8622 13:38:36.255024
8623 13:38:36.255117 Set Vref, RX VrefLevel [Byte0]: 43
8624 13:38:36.258397 [Byte1]: 43
8625 13:38:36.262798
8626 13:38:36.262893 Set Vref, RX VrefLevel [Byte0]: 44
8627 13:38:36.266198 [Byte1]: 44
8628 13:38:36.270146
8629 13:38:36.270243 Set Vref, RX VrefLevel [Byte0]: 45
8630 13:38:36.273442 [Byte1]: 45
8631 13:38:36.277773
8632 13:38:36.277932 Set Vref, RX VrefLevel [Byte0]: 46
8633 13:38:36.281019 [Byte1]: 46
8634 13:38:36.285693
8635 13:38:36.285818 Set Vref, RX VrefLevel [Byte0]: 47
8636 13:38:36.288580 [Byte1]: 47
8637 13:38:36.293206
8638 13:38:36.293328 Set Vref, RX VrefLevel [Byte0]: 48
8639 13:38:36.296449 [Byte1]: 48
8640 13:38:36.301012
8641 13:38:36.301103 Set Vref, RX VrefLevel [Byte0]: 49
8642 13:38:36.303677 [Byte1]: 49
8643 13:38:36.308365
8644 13:38:36.308480 Set Vref, RX VrefLevel [Byte0]: 50
8645 13:38:36.311609 [Byte1]: 50
8646 13:38:36.315995
8647 13:38:36.316085 Set Vref, RX VrefLevel [Byte0]: 51
8648 13:38:36.318973 [Byte1]: 51
8649 13:38:36.323431
8650 13:38:36.323518 Set Vref, RX VrefLevel [Byte0]: 52
8651 13:38:36.326664 [Byte1]: 52
8652 13:38:36.331556
8653 13:38:36.331647 Set Vref, RX VrefLevel [Byte0]: 53
8654 13:38:36.334343 [Byte1]: 53
8655 13:38:36.338933
8656 13:38:36.339017 Set Vref, RX VrefLevel [Byte0]: 54
8657 13:38:36.342150 [Byte1]: 54
8658 13:38:36.346191
8659 13:38:36.346271 Set Vref, RX VrefLevel [Byte0]: 55
8660 13:38:36.349664 [Byte1]: 55
8661 13:38:36.354287
8662 13:38:36.354367 Set Vref, RX VrefLevel [Byte0]: 56
8663 13:38:36.357010 [Byte1]: 56
8664 13:38:36.361781
8665 13:38:36.361859 Set Vref, RX VrefLevel [Byte0]: 57
8666 13:38:36.364582 [Byte1]: 57
8667 13:38:36.369455
8668 13:38:36.369559 Set Vref, RX VrefLevel [Byte0]: 58
8669 13:38:36.372786 [Byte1]: 58
8670 13:38:36.376808
8671 13:38:36.376889 Set Vref, RX VrefLevel [Byte0]: 59
8672 13:38:36.380101 [Byte1]: 59
8673 13:38:36.384154
8674 13:38:36.384234 Set Vref, RX VrefLevel [Byte0]: 60
8675 13:38:36.387471 [Byte1]: 60
8676 13:38:36.391958
8677 13:38:36.392044 Set Vref, RX VrefLevel [Byte0]: 61
8678 13:38:36.395350 [Byte1]: 61
8679 13:38:36.399406
8680 13:38:36.399541 Set Vref, RX VrefLevel [Byte0]: 62
8681 13:38:36.402752 [Byte1]: 62
8682 13:38:36.407416
8683 13:38:36.407527 Set Vref, RX VrefLevel [Byte0]: 63
8684 13:38:36.410825 [Byte1]: 63
8685 13:38:36.414798
8686 13:38:36.414911 Set Vref, RX VrefLevel [Byte0]: 64
8687 13:38:36.418233 [Byte1]: 64
8688 13:38:36.422337
8689 13:38:36.422443 Set Vref, RX VrefLevel [Byte0]: 65
8690 13:38:36.425615 [Byte1]: 65
8691 13:38:36.429919
8692 13:38:36.430036 Set Vref, RX VrefLevel [Byte0]: 66
8693 13:38:36.433642 [Byte1]: 66
8694 13:38:36.437651
8695 13:38:36.437760 Set Vref, RX VrefLevel [Byte0]: 67
8696 13:38:36.440808 [Byte1]: 67
8697 13:38:36.445235
8698 13:38:36.445347 Set Vref, RX VrefLevel [Byte0]: 68
8699 13:38:36.448435 [Byte1]: 68
8700 13:38:36.452952
8701 13:38:36.453061 Set Vref, RX VrefLevel [Byte0]: 69
8702 13:38:36.456260 [Byte1]: 69
8703 13:38:36.460282
8704 13:38:36.460383 Set Vref, RX VrefLevel [Byte0]: 70
8705 13:38:36.463717 [Byte1]: 70
8706 13:38:36.467868
8707 13:38:36.467973 Final RX Vref Byte 0 = 56 to rank0
8708 13:38:36.471236 Final RX Vref Byte 1 = 52 to rank0
8709 13:38:36.474559 Final RX Vref Byte 0 = 56 to rank1
8710 13:38:36.478015 Final RX Vref Byte 1 = 52 to rank1==
8711 13:38:36.481491 Dram Type= 6, Freq= 0, CH_1, rank 0
8712 13:38:36.488246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 13:38:36.488335 ==
8714 13:38:36.488401 DQS Delay:
8715 13:38:36.490949 DQS0 = 0, DQS1 = 0
8716 13:38:36.491032 DQM Delay:
8717 13:38:36.491100 DQM0 = 131, DQM1 = 123
8718 13:38:36.494922 DQ Delay:
8719 13:38:36.498238 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8720 13:38:36.501582 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8721 13:38:36.504301 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8722 13:38:36.507662 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8723 13:38:36.507765
8724 13:38:36.507831
8725 13:38:36.507905
8726 13:38:36.510924 [DramC_TX_OE_Calibration] TA2
8727 13:38:36.514373 Original DQ_B0 (3 6) =30, OEN = 27
8728 13:38:36.517922 Original DQ_B1 (3 6) =30, OEN = 27
8729 13:38:36.521512 24, 0x0, End_B0=24 End_B1=24
8730 13:38:36.521600 25, 0x0, End_B0=25 End_B1=25
8731 13:38:36.524154 26, 0x0, End_B0=26 End_B1=26
8732 13:38:36.527695 27, 0x0, End_B0=27 End_B1=27
8733 13:38:36.531093 28, 0x0, End_B0=28 End_B1=28
8734 13:38:36.534368 29, 0x0, End_B0=29 End_B1=29
8735 13:38:36.534452 30, 0x0, End_B0=30 End_B1=30
8736 13:38:36.537408 31, 0x4141, End_B0=30 End_B1=30
8737 13:38:36.540663 Byte0 end_step=30 best_step=27
8738 13:38:36.544024 Byte1 end_step=30 best_step=27
8739 13:38:36.547304 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 13:38:36.551157 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 13:38:36.551242
8742 13:38:36.551307
8743 13:38:36.557658 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8744 13:38:36.560699 CH1 RK0: MR19=303, MR18=70C
8745 13:38:36.567931 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8746 13:38:36.568015
8747 13:38:36.570744 ----->DramcWriteLeveling(PI) begin...
8748 13:38:36.570829 ==
8749 13:38:36.573970 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 13:38:36.577332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 13:38:36.577437 ==
8752 13:38:36.580651 Write leveling (Byte 0): 24 => 24
8753 13:38:36.583985 Write leveling (Byte 1): 25 => 25
8754 13:38:36.587517 DramcWriteLeveling(PI) end<-----
8755 13:38:36.587600
8756 13:38:36.587664 ==
8757 13:38:36.590876 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 13:38:36.593680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 13:38:36.593779 ==
8760 13:38:36.597138 [Gating] SW mode calibration
8761 13:38:36.603755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8762 13:38:36.610385 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8763 13:38:36.613584 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 13:38:36.620080 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 13:38:36.623606 1 4 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8766 13:38:36.627050 1 4 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
8767 13:38:36.633787 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 13:38:36.636546 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 13:38:36.639941 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 13:38:36.647039 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 13:38:36.650344 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 13:38:36.653183 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 13:38:36.659959 1 5 8 | B1->B0 | 3333 2525 | 1 0 | (1 1) (1 0)
8774 13:38:36.663466 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
8775 13:38:36.666801 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 13:38:36.670147 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 13:38:36.676401 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 13:38:36.680044 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 13:38:36.683198 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 13:38:36.689708 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8781 13:38:36.692959 1 6 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8782 13:38:36.696325 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
8783 13:38:36.703010 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 13:38:36.706528 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 13:38:36.709392 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 13:38:36.716030 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 13:38:36.719214 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 13:38:36.723001 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 13:38:36.728946 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8790 13:38:36.732501 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8791 13:38:36.736048 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 13:38:36.742805 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 13:38:36.745591 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 13:38:36.749372 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 13:38:36.756083 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 13:38:36.758723 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 13:38:36.762172 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:38:36.769042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:38:36.772587 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:38:36.775246 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:38:36.782679 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:38:36.785833 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:38:36.789004 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:38:36.795633 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8805 13:38:36.798698 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8806 13:38:36.802307 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8807 13:38:36.809000 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 13:38:36.809090 Total UI for P1: 0, mck2ui 16
8809 13:38:36.815795 best dqsien dly found for B0: ( 1, 9, 8)
8810 13:38:36.815891 Total UI for P1: 0, mck2ui 16
8811 13:38:36.822421 best dqsien dly found for B1: ( 1, 9, 12)
8812 13:38:36.825680 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8813 13:38:36.828886 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8814 13:38:36.828970
8815 13:38:36.832037 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8816 13:38:36.835285 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8817 13:38:36.838636 [Gating] SW calibration Done
8818 13:38:36.838719 ==
8819 13:38:36.842088 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 13:38:36.845398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 13:38:36.845482 ==
8822 13:38:36.848237 RX Vref Scan: 0
8823 13:38:36.848319
8824 13:38:36.848382 RX Vref 0 -> 0, step: 1
8825 13:38:36.848443
8826 13:38:36.851633 RX Delay 0 -> 252, step: 8
8827 13:38:36.854870 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8828 13:38:36.861430 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8829 13:38:36.865379 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8830 13:38:36.868170 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8831 13:38:36.871958 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8832 13:38:36.874701 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8833 13:38:36.881399 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8834 13:38:36.884784 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8835 13:38:36.888230 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8836 13:38:36.891495 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8837 13:38:36.894825 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8838 13:38:36.901447 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8839 13:38:36.904784 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8840 13:38:36.908151 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8841 13:38:36.911231 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8842 13:38:36.917915 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8843 13:38:36.918050 ==
8844 13:38:36.921054 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 13:38:36.924312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 13:38:36.924399 ==
8847 13:38:36.924521 DQS Delay:
8848 13:38:36.927705 DQS0 = 0, DQS1 = 0
8849 13:38:36.927815 DQM Delay:
8850 13:38:36.931112 DQM0 = 133, DQM1 = 129
8851 13:38:36.931228 DQ Delay:
8852 13:38:36.934217 DQ0 =135, DQ1 =127, DQ2 =123, DQ3 =131
8853 13:38:36.937782 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8854 13:38:36.940917 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8855 13:38:36.944235 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8856 13:38:36.944349
8857 13:38:36.947659
8858 13:38:36.947798 ==
8859 13:38:36.951115 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 13:38:36.953720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 13:38:36.953829 ==
8862 13:38:36.953925
8863 13:38:36.954001
8864 13:38:36.957152 TX Vref Scan disable
8865 13:38:36.957244 == TX Byte 0 ==
8866 13:38:36.963840 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8867 13:38:36.967158 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 13:38:36.967256 == TX Byte 1 ==
8869 13:38:36.974073 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8870 13:38:36.977438 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8871 13:38:36.977524 ==
8872 13:38:36.980740 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 13:38:36.983437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 13:38:36.983530 ==
8875 13:38:36.998166
8876 13:38:37.001537 TX Vref early break, caculate TX vref
8877 13:38:37.004871 TX Vref=16, minBit 0, minWin=23, winSum=385
8878 13:38:37.008346 TX Vref=18, minBit 0, minWin=23, winSum=399
8879 13:38:37.011669 TX Vref=20, minBit 0, minWin=23, winSum=405
8880 13:38:37.015123 TX Vref=22, minBit 0, minWin=24, winSum=409
8881 13:38:37.017992 TX Vref=24, minBit 0, minWin=25, winSum=421
8882 13:38:37.024705 TX Vref=26, minBit 1, minWin=25, winSum=426
8883 13:38:37.027826 TX Vref=28, minBit 0, minWin=25, winSum=424
8884 13:38:37.031442 TX Vref=30, minBit 1, minWin=25, winSum=423
8885 13:38:37.035087 TX Vref=32, minBit 1, minWin=24, winSum=418
8886 13:38:37.038032 TX Vref=34, minBit 1, minWin=23, winSum=406
8887 13:38:37.041218 TX Vref=36, minBit 5, minWin=23, winSum=396
8888 13:38:37.048186 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8889 13:38:37.048310
8890 13:38:37.051526 Final TX Range 0 Vref 26
8891 13:38:37.051638
8892 13:38:37.051737 ==
8893 13:38:37.054794 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 13:38:37.058294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 13:38:37.058403 ==
8896 13:38:37.058509
8897 13:38:37.058608
8898 13:38:37.060987 TX Vref Scan disable
8899 13:38:37.068231 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8900 13:38:37.068344 == TX Byte 0 ==
8901 13:38:37.071294 u2DelayCellOfst[0]=18 cells (5 PI)
8902 13:38:37.074749 u2DelayCellOfst[1]=11 cells (3 PI)
8903 13:38:37.077582 u2DelayCellOfst[2]=0 cells (0 PI)
8904 13:38:37.081102 u2DelayCellOfst[3]=3 cells (1 PI)
8905 13:38:37.084415 u2DelayCellOfst[4]=7 cells (2 PI)
8906 13:38:37.087677 u2DelayCellOfst[5]=22 cells (6 PI)
8907 13:38:37.091110 u2DelayCellOfst[6]=18 cells (5 PI)
8908 13:38:37.094651 u2DelayCellOfst[7]=7 cells (2 PI)
8909 13:38:37.098041 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8910 13:38:37.100696 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8911 13:38:37.104197 == TX Byte 1 ==
8912 13:38:37.107595 u2DelayCellOfst[8]=0 cells (0 PI)
8913 13:38:37.111006 u2DelayCellOfst[9]=7 cells (2 PI)
8914 13:38:37.111133 u2DelayCellOfst[10]=15 cells (4 PI)
8915 13:38:37.114329 u2DelayCellOfst[11]=7 cells (2 PI)
8916 13:38:37.117778 u2DelayCellOfst[12]=15 cells (4 PI)
8917 13:38:37.121129 u2DelayCellOfst[13]=18 cells (5 PI)
8918 13:38:37.124451 u2DelayCellOfst[14]=18 cells (5 PI)
8919 13:38:37.127760 u2DelayCellOfst[15]=18 cells (5 PI)
8920 13:38:37.134456 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8921 13:38:37.137758 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8922 13:38:37.137878 DramC Write-DBI on
8923 13:38:37.137981 ==
8924 13:38:37.141070 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 13:38:37.147440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 13:38:37.147562 ==
8927 13:38:37.147669
8928 13:38:37.147764
8929 13:38:37.147852 TX Vref Scan disable
8930 13:38:37.151248 == TX Byte 0 ==
8931 13:38:37.154530 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8932 13:38:37.158043 == TX Byte 1 ==
8933 13:38:37.161751 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8934 13:38:37.164781 DramC Write-DBI off
8935 13:38:37.164867
8936 13:38:37.164936 [DATLAT]
8937 13:38:37.165032 Freq=1600, CH1 RK1
8938 13:38:37.165118
8939 13:38:37.168117 DATLAT Default: 0xf
8940 13:38:37.171435 0, 0xFFFF, sum = 0
8941 13:38:37.171536 1, 0xFFFF, sum = 0
8942 13:38:37.174519 2, 0xFFFF, sum = 0
8943 13:38:37.174603 3, 0xFFFF, sum = 0
8944 13:38:37.177752 4, 0xFFFF, sum = 0
8945 13:38:37.177834 5, 0xFFFF, sum = 0
8946 13:38:37.181088 6, 0xFFFF, sum = 0
8947 13:38:37.181168 7, 0xFFFF, sum = 0
8948 13:38:37.184535 8, 0xFFFF, sum = 0
8949 13:38:37.184664 9, 0xFFFF, sum = 0
8950 13:38:37.188085 10, 0xFFFF, sum = 0
8951 13:38:37.188199 11, 0xFFFF, sum = 0
8952 13:38:37.191500 12, 0xFFFF, sum = 0
8953 13:38:37.191620 13, 0x8FFF, sum = 0
8954 13:38:37.194871 14, 0x0, sum = 1
8955 13:38:37.195001 15, 0x0, sum = 2
8956 13:38:37.197765 16, 0x0, sum = 3
8957 13:38:37.197851 17, 0x0, sum = 4
8958 13:38:37.201120 best_step = 15
8959 13:38:37.201211
8960 13:38:37.201275 ==
8961 13:38:37.204622 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 13:38:37.208042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 13:38:37.208154 ==
8964 13:38:37.210794 RX Vref Scan: 0
8965 13:38:37.210905
8966 13:38:37.211007 RX Vref 0 -> 0, step: 1
8967 13:38:37.211097
8968 13:38:37.214128 RX Delay 11 -> 252, step: 4
8969 13:38:37.217678 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8970 13:38:37.224273 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8971 13:38:37.227804 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8972 13:38:37.231152 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8973 13:38:37.233888 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8974 13:38:37.240938 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8975 13:38:37.244291 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8976 13:38:37.247746 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8977 13:38:37.250573 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8978 13:38:37.253930 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8979 13:38:37.257606 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8980 13:38:37.263811 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8981 13:38:37.267617 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8982 13:38:37.270837 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8983 13:38:37.273918 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8984 13:38:37.281099 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8985 13:38:37.281242 ==
8986 13:38:37.283860 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 13:38:37.287379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 13:38:37.287497 ==
8989 13:38:37.287590 DQS Delay:
8990 13:38:37.290446 DQS0 = 0, DQS1 = 0
8991 13:38:37.290555 DQM Delay:
8992 13:38:37.293783 DQM0 = 129, DQM1 = 125
8993 13:38:37.293910 DQ Delay:
8994 13:38:37.297358 DQ0 =134, DQ1 =126, DQ2 =116, DQ3 =126
8995 13:38:37.300553 DQ4 =124, DQ5 =140, DQ6 =142, DQ7 =124
8996 13:38:37.304051 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
8997 13:38:37.306796 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =134
8998 13:38:37.306928
8999 13:38:37.310173
9000 13:38:37.310269
9001 13:38:37.310360 [DramC_TX_OE_Calibration] TA2
9002 13:38:37.313802 Original DQ_B0 (3 6) =30, OEN = 27
9003 13:38:37.317172 Original DQ_B1 (3 6) =30, OEN = 27
9004 13:38:37.320427 24, 0x0, End_B0=24 End_B1=24
9005 13:38:37.323668 25, 0x0, End_B0=25 End_B1=25
9006 13:38:37.327066 26, 0x0, End_B0=26 End_B1=26
9007 13:38:37.327205 27, 0x0, End_B0=27 End_B1=27
9008 13:38:37.329738 28, 0x0, End_B0=28 End_B1=28
9009 13:38:37.333127 29, 0x0, End_B0=29 End_B1=29
9010 13:38:37.336545 30, 0x0, End_B0=30 End_B1=30
9011 13:38:37.339890 31, 0x4141, End_B0=30 End_B1=30
9012 13:38:37.339976 Byte0 end_step=30 best_step=27
9013 13:38:37.343147 Byte1 end_step=30 best_step=27
9014 13:38:37.346470 Byte0 TX OE(2T, 0.5T) = (3, 3)
9015 13:38:37.349777 Byte1 TX OE(2T, 0.5T) = (3, 3)
9016 13:38:37.349858
9017 13:38:37.349922
9018 13:38:37.359988 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9019 13:38:37.360092 CH1 RK1: MR19=303, MR18=111D
9020 13:38:37.366611 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9021 13:38:37.370024 [RxdqsGatingPostProcess] freq 1600
9022 13:38:37.376259 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9023 13:38:37.379685 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 13:38:37.383039 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 13:38:37.385889 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 13:38:37.389682 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 13:38:37.389763 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 13:38:37.392828 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 13:38:37.396068 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 13:38:37.399146 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 13:38:37.402617 Pre-setting of DQS Precalculation
9032 13:38:37.409506 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9033 13:38:37.416161 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9034 13:38:37.422730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9035 13:38:37.422823
9036 13:38:37.422887
9037 13:38:37.425595 [Calibration Summary] 3200 Mbps
9038 13:38:37.425701 CH 0, Rank 0
9039 13:38:37.429034 SW Impedance : PASS
9040 13:38:37.432334 DUTY Scan : NO K
9041 13:38:37.432418 ZQ Calibration : PASS
9042 13:38:37.435760 Jitter Meter : NO K
9043 13:38:37.439122 CBT Training : PASS
9044 13:38:37.439206 Write leveling : PASS
9045 13:38:37.442635 RX DQS gating : PASS
9046 13:38:37.445369 RX DQ/DQS(RDDQC) : PASS
9047 13:38:37.445463 TX DQ/DQS : PASS
9048 13:38:37.448837 RX DATLAT : PASS
9049 13:38:37.452245 RX DQ/DQS(Engine): PASS
9050 13:38:37.452329 TX OE : PASS
9051 13:38:37.452394 All Pass.
9052 13:38:37.455626
9053 13:38:37.455714 CH 0, Rank 1
9054 13:38:37.458995 SW Impedance : PASS
9055 13:38:37.459100 DUTY Scan : NO K
9056 13:38:37.462369 ZQ Calibration : PASS
9057 13:38:37.465836 Jitter Meter : NO K
9058 13:38:37.465925 CBT Training : PASS
9059 13:38:37.468580 Write leveling : PASS
9060 13:38:37.468667 RX DQS gating : PASS
9061 13:38:37.472288 RX DQ/DQS(RDDQC) : PASS
9062 13:38:37.475646 TX DQ/DQS : PASS
9063 13:38:37.475730 RX DATLAT : PASS
9064 13:38:37.478367 RX DQ/DQS(Engine): PASS
9065 13:38:37.481794 TX OE : PASS
9066 13:38:37.481875 All Pass.
9067 13:38:37.481958
9068 13:38:37.482037 CH 1, Rank 0
9069 13:38:37.485054 SW Impedance : PASS
9070 13:38:37.488309 DUTY Scan : NO K
9071 13:38:37.488410 ZQ Calibration : PASS
9072 13:38:37.491665 Jitter Meter : NO K
9073 13:38:37.495078 CBT Training : PASS
9074 13:38:37.495181 Write leveling : PASS
9075 13:38:37.498641 RX DQS gating : PASS
9076 13:38:37.501488 RX DQ/DQS(RDDQC) : PASS
9077 13:38:37.501570 TX DQ/DQS : PASS
9078 13:38:37.504970 RX DATLAT : PASS
9079 13:38:37.508380 RX DQ/DQS(Engine): PASS
9080 13:38:37.508490 TX OE : PASS
9081 13:38:37.511814 All Pass.
9082 13:38:37.511901
9083 13:38:37.511987 CH 1, Rank 1
9084 13:38:37.515186 SW Impedance : PASS
9085 13:38:37.515272 DUTY Scan : NO K
9086 13:38:37.518406 ZQ Calibration : PASS
9087 13:38:37.521447 Jitter Meter : NO K
9088 13:38:37.521559 CBT Training : PASS
9089 13:38:37.525224 Write leveling : PASS
9090 13:38:37.528025 RX DQS gating : PASS
9091 13:38:37.528110 RX DQ/DQS(RDDQC) : PASS
9092 13:38:37.531608 TX DQ/DQS : PASS
9093 13:38:37.534559 RX DATLAT : PASS
9094 13:38:37.534645 RX DQ/DQS(Engine): PASS
9095 13:38:37.537858 TX OE : PASS
9096 13:38:37.537943 All Pass.
9097 13:38:37.538028
9098 13:38:37.540936 DramC Write-DBI on
9099 13:38:37.544565 PER_BANK_REFRESH: Hybrid Mode
9100 13:38:37.544654 TX_TRACKING: ON
9101 13:38:37.554661 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9102 13:38:37.561438 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9103 13:38:37.567687 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 13:38:37.571175 [FAST_K] Save calibration result to emmc
9105 13:38:37.574470 sync common calibartion params.
9106 13:38:37.577242 sync cbt_mode0:1, 1:1
9107 13:38:37.581024 dram_init: ddr_geometry: 2
9108 13:38:37.581108 dram_init: ddr_geometry: 2
9109 13:38:37.584109 dram_init: ddr_geometry: 2
9110 13:38:37.587393 0:dram_rank_size:100000000
9111 13:38:37.590778 1:dram_rank_size:100000000
9112 13:38:37.594082 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9113 13:38:37.597478 DFS_SHUFFLE_HW_MODE: ON
9114 13:38:37.600801 dramc_set_vcore_voltage set vcore to 725000
9115 13:38:37.604298 Read voltage for 1600, 0
9116 13:38:37.604405 Vio18 = 0
9117 13:38:37.604499 Vcore = 725000
9118 13:38:37.607140 Vdram = 0
9119 13:38:37.607242 Vddq = 0
9120 13:38:37.607332 Vmddr = 0
9121 13:38:37.610514 switch to 3200 Mbps bootup
9122 13:38:37.613835 [DramcRunTimeConfig]
9123 13:38:37.613922 PHYPLL
9124 13:38:37.614007 DPM_CONTROL_AFTERK: ON
9125 13:38:37.617418 PER_BANK_REFRESH: ON
9126 13:38:37.620932 REFRESH_OVERHEAD_REDUCTION: ON
9127 13:38:37.621018 CMD_PICG_NEW_MODE: OFF
9128 13:38:37.623745 XRTWTW_NEW_MODE: ON
9129 13:38:37.623829 XRTRTR_NEW_MODE: ON
9130 13:38:37.627133 TX_TRACKING: ON
9131 13:38:37.627242 RDSEL_TRACKING: OFF
9132 13:38:37.630391 DQS Precalculation for DVFS: ON
9133 13:38:37.633639 RX_TRACKING: OFF
9134 13:38:37.633745 HW_GATING DBG: ON
9135 13:38:37.637334 ZQCS_ENABLE_LP4: ON
9136 13:38:37.637418 RX_PICG_NEW_MODE: ON
9137 13:38:37.640353 TX_PICG_NEW_MODE: ON
9138 13:38:37.643787 ENABLE_RX_DCM_DPHY: ON
9139 13:38:37.647147 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9140 13:38:37.647275 DUMMY_READ_FOR_TRACKING: OFF
9141 13:38:37.650521 !!! SPM_CONTROL_AFTERK: OFF
9142 13:38:37.653742 !!! SPM could not control APHY
9143 13:38:37.656728 IMPEDANCE_TRACKING: ON
9144 13:38:37.656802 TEMP_SENSOR: ON
9145 13:38:37.660324 HW_SAVE_FOR_SR: OFF
9146 13:38:37.660420 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9147 13:38:37.666842 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9148 13:38:37.666949 Read ODT Tracking: ON
9149 13:38:37.670251 Refresh Rate DeBounce: ON
9150 13:38:37.673745 DFS_NO_QUEUE_FLUSH: ON
9151 13:38:37.673824 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9152 13:38:37.676573 ENABLE_DFS_RUNTIME_MRW: OFF
9153 13:38:37.680132 DDR_RESERVE_NEW_MODE: ON
9154 13:38:37.683547 MR_CBT_SWITCH_FREQ: ON
9155 13:38:37.683649 =========================
9156 13:38:37.702864 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9157 13:38:37.706224 dram_init: ddr_geometry: 2
9158 13:38:37.724663 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9159 13:38:37.728105 dram_init: dram init end (result: 0)
9160 13:38:37.734238 DRAM-K: Full calibration passed in 24565 msecs
9161 13:38:37.737655 MRC: failed to locate region type 0.
9162 13:38:37.737765 DRAM rank0 size:0x100000000,
9163 13:38:37.741073 DRAM rank1 size=0x100000000
9164 13:38:37.750980 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9165 13:38:37.757523 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9166 13:38:37.764139 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9167 13:38:37.770679 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9168 13:38:37.774428 DRAM rank0 size:0x100000000,
9169 13:38:37.777691 DRAM rank1 size=0x100000000
9170 13:38:37.777774 CBMEM:
9171 13:38:37.780878 IMD: root @ 0xfffff000 254 entries.
9172 13:38:37.784392 IMD: root @ 0xffffec00 62 entries.
9173 13:38:37.787074 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9174 13:38:37.793734 WARNING: RO_VPD is uninitialized or empty.
9175 13:38:37.797174 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9176 13:38:37.804775 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9177 13:38:37.817679 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9178 13:38:37.829117 BS: romstage times (exec / console): total (unknown) / 24031 ms
9179 13:38:37.829220
9180 13:38:37.829286
9181 13:38:37.838766 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9182 13:38:37.842076 ARM64: Exception handlers installed.
9183 13:38:37.845541 ARM64: Testing exception
9184 13:38:37.848947 ARM64: Done test exception
9185 13:38:37.849054 Enumerating buses...
9186 13:38:37.852219 Show all devs... Before device enumeration.
9187 13:38:37.855566 Root Device: enabled 1
9188 13:38:37.858613 CPU_CLUSTER: 0: enabled 1
9189 13:38:37.858696 CPU: 00: enabled 1
9190 13:38:37.862198 Compare with tree...
9191 13:38:37.862313 Root Device: enabled 1
9192 13:38:37.865703 CPU_CLUSTER: 0: enabled 1
9193 13:38:37.868324 CPU: 00: enabled 1
9194 13:38:37.868411 Root Device scanning...
9195 13:38:37.871710 scan_static_bus for Root Device
9196 13:38:37.875207 CPU_CLUSTER: 0 enabled
9197 13:38:37.878416 scan_static_bus for Root Device done
9198 13:38:37.881683 scan_bus: bus Root Device finished in 8 msecs
9199 13:38:37.881768 done
9200 13:38:37.888848 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9201 13:38:37.891939 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9202 13:38:37.898108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9203 13:38:37.901543 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9204 13:38:37.905028 Allocating resources...
9205 13:38:37.908367 Reading resources...
9206 13:38:37.911843 Root Device read_resources bus 0 link: 0
9207 13:38:37.911927 DRAM rank0 size:0x100000000,
9208 13:38:37.915334 DRAM rank1 size=0x100000000
9209 13:38:37.918586 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9210 13:38:37.921698 CPU: 00 missing read_resources
9211 13:38:37.924957 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9212 13:38:37.931337 Root Device read_resources bus 0 link: 0 done
9213 13:38:37.931420 Done reading resources.
9214 13:38:37.938057 Show resources in subtree (Root Device)...After reading.
9215 13:38:37.941495 Root Device child on link 0 CPU_CLUSTER: 0
9216 13:38:37.945025 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 13:38:37.954725 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 13:38:37.954829 CPU: 00
9219 13:38:37.958316 Root Device assign_resources, bus 0 link: 0
9220 13:38:37.961686 CPU_CLUSTER: 0 missing set_resources
9221 13:38:37.967847 Root Device assign_resources, bus 0 link: 0 done
9222 13:38:37.967933 Done setting resources.
9223 13:38:37.974700 Show resources in subtree (Root Device)...After assigning values.
9224 13:38:37.977971 Root Device child on link 0 CPU_CLUSTER: 0
9225 13:38:37.981254 CPU_CLUSTER: 0 child on link 0 CPU: 00
9226 13:38:37.991536 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9227 13:38:37.991631 CPU: 00
9228 13:38:37.994944 Done allocating resources.
9229 13:38:37.997669 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9230 13:38:38.000970 Enabling resources...
9231 13:38:38.001089 done.
9232 13:38:38.007673 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9233 13:38:38.007795 Initializing devices...
9234 13:38:38.011022 Root Device init
9235 13:38:38.011138 init hardware done!
9236 13:38:38.014194 0x00000018: ctrlr->caps
9237 13:38:38.017675 52.000 MHz: ctrlr->f_max
9238 13:38:38.017763 0.400 MHz: ctrlr->f_min
9239 13:38:38.020967 0x40ff8080: ctrlr->voltages
9240 13:38:38.024335 sclk: 390625
9241 13:38:38.024418 Bus Width = 1
9242 13:38:38.024485 sclk: 390625
9243 13:38:38.027675 Bus Width = 1
9244 13:38:38.027758 Early init status = 3
9245 13:38:38.033955 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9246 13:38:38.037680 in-header: 03 fc 00 00 01 00 00 00
9247 13:38:38.037766 in-data: 00
9248 13:38:38.043957 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9249 13:38:38.048432 in-header: 03 fd 00 00 00 00 00 00
9250 13:38:38.051332 in-data:
9251 13:38:38.054891 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9252 13:38:38.058925 in-header: 03 fc 00 00 01 00 00 00
9253 13:38:38.062307 in-data: 00
9254 13:38:38.065759 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9255 13:38:38.071045 in-header: 03 fd 00 00 00 00 00 00
9256 13:38:38.074285 in-data:
9257 13:38:38.077629 [SSUSB] Setting up USB HOST controller...
9258 13:38:38.080943 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9259 13:38:38.084522 [SSUSB] phy power-on done.
9260 13:38:38.087832 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9261 13:38:38.094531 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9262 13:38:38.097796 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9263 13:38:38.104473 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9264 13:38:38.110876 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9265 13:38:38.117789 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9266 13:38:38.123947 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9267 13:38:38.130867 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9268 13:38:38.134313 SPM: binary array size = 0x9dc
9269 13:38:38.137134 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9270 13:38:38.143823 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9271 13:38:38.150684 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9272 13:38:38.157343 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9273 13:38:38.160544 configure_display: Starting display init
9274 13:38:38.194284 anx7625_power_on_init: Init interface.
9275 13:38:38.197946 anx7625_disable_pd_protocol: Disabled PD feature.
9276 13:38:38.200825 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9277 13:38:38.229141 anx7625_start_dp_work: Secure OCM version=00
9278 13:38:38.232102 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9279 13:38:38.246785 sp_tx_get_edid_block: EDID Block = 1
9280 13:38:38.349417 Extracted contents:
9281 13:38:38.353137 header: 00 ff ff ff ff ff ff 00
9282 13:38:38.356197 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9283 13:38:38.359660 version: 01 04
9284 13:38:38.362405 basic params: 95 1f 11 78 0a
9285 13:38:38.365742 chroma info: 76 90 94 55 54 90 27 21 50 54
9286 13:38:38.369099 established: 00 00 00
9287 13:38:38.375706 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9288 13:38:38.378950 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9289 13:38:38.385477 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9290 13:38:38.392368 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9291 13:38:38.399056 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9292 13:38:38.402558 extensions: 00
9293 13:38:38.402649 checksum: fb
9294 13:38:38.402714
9295 13:38:38.405731 Manufacturer: IVO Model 57d Serial Number 0
9296 13:38:38.409171 Made week 0 of 2020
9297 13:38:38.412461 EDID version: 1.4
9298 13:38:38.412578 Digital display
9299 13:38:38.415672 6 bits per primary color channel
9300 13:38:38.415757 DisplayPort interface
9301 13:38:38.418965 Maximum image size: 31 cm x 17 cm
9302 13:38:38.422133 Gamma: 220%
9303 13:38:38.422216 Check DPMS levels
9304 13:38:38.425550 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9305 13:38:38.432087 First detailed timing is preferred timing
9306 13:38:38.432171 Established timings supported:
9307 13:38:38.435545 Standard timings supported:
9308 13:38:38.438797 Detailed timings
9309 13:38:38.442167 Hex of detail: 383680a07038204018303c0035ae10000019
9310 13:38:38.448745 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9311 13:38:38.451986 0780 0798 07c8 0820 hborder 0
9312 13:38:38.455398 0438 043b 0447 0458 vborder 0
9313 13:38:38.458658 -hsync -vsync
9314 13:38:38.458741 Did detailed timing
9315 13:38:38.465127 Hex of detail: 000000000000000000000000000000000000
9316 13:38:38.468329 Manufacturer-specified data, tag 0
9317 13:38:38.471745 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9318 13:38:38.474746 ASCII string: InfoVision
9319 13:38:38.478432 Hex of detail: 000000fe00523134304e574635205248200a
9320 13:38:38.481804 ASCII string: R140NWF5 RH
9321 13:38:38.481899 Checksum
9322 13:38:38.485124 Checksum: 0xfb (valid)
9323 13:38:38.488338 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9324 13:38:38.491961 DSI data_rate: 832800000 bps
9325 13:38:38.498320 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9326 13:38:38.501144 anx7625_parse_edid: pixelclock(138800).
9327 13:38:38.504510 hactive(1920), hsync(48), hfp(24), hbp(88)
9328 13:38:38.507883 vactive(1080), vsync(12), vfp(3), vbp(17)
9329 13:38:38.511082 anx7625_dsi_config: config dsi.
9330 13:38:38.517789 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9331 13:38:38.531863 anx7625_dsi_config: success to config DSI
9332 13:38:38.534541 anx7625_dp_start: MIPI phy setup OK.
9333 13:38:38.538406 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9334 13:38:38.541761 mtk_ddp_mode_set invalid vrefresh 60
9335 13:38:38.545163 main_disp_path_setup
9336 13:38:38.545244 ovl_layer_smi_id_en
9337 13:38:38.548362 ovl_layer_smi_id_en
9338 13:38:38.548443 ccorr_config
9339 13:38:38.548506 aal_config
9340 13:38:38.551733 gamma_config
9341 13:38:38.551813 postmask_config
9342 13:38:38.555006 dither_config
9343 13:38:38.557747 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9344 13:38:38.564411 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9345 13:38:38.567759 Root Device init finished in 553 msecs
9346 13:38:38.571201 CPU_CLUSTER: 0 init
9347 13:38:38.577926 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9348 13:38:38.581510 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9349 13:38:38.584781 APU_MBOX 0x190000b0 = 0x10001
9350 13:38:38.587981 APU_MBOX 0x190001b0 = 0x10001
9351 13:38:38.591118 APU_MBOX 0x190005b0 = 0x10001
9352 13:38:38.594835 APU_MBOX 0x190006b0 = 0x10001
9353 13:38:38.597892 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9354 13:38:38.610351 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9355 13:38:38.623207 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9356 13:38:38.629139 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9357 13:38:38.641196 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9358 13:38:38.650558 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9359 13:38:38.653883 CPU_CLUSTER: 0 init finished in 81 msecs
9360 13:38:38.657101 Devices initialized
9361 13:38:38.660600 Show all devs... After init.
9362 13:38:38.660751 Root Device: enabled 1
9363 13:38:38.663819 CPU_CLUSTER: 0: enabled 1
9364 13:38:38.667103 CPU: 00: enabled 1
9365 13:38:38.670495 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9366 13:38:38.673269 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9367 13:38:38.676704 ELOG: NV offset 0x57f000 size 0x1000
9368 13:38:38.683423 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9369 13:38:38.689875 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9370 13:38:38.693379 ELOG: Event(17) added with size 13 at 2024-05-28 13:38:39 UTC
9371 13:38:38.700092 out: cmd=0x121: 03 db 21 01 00 00 00 00
9372 13:38:38.703546 in-header: 03 61 00 00 2c 00 00 00
9373 13:38:38.713366 in-data: fe 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9374 13:38:38.719705 ELOG: Event(A1) added with size 10 at 2024-05-28 13:38:39 UTC
9375 13:38:38.726179 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9376 13:38:38.732989 ELOG: Event(A0) added with size 9 at 2024-05-28 13:38:39 UTC
9377 13:38:38.736200 elog_add_boot_reason: Logged dev mode boot
9378 13:38:38.742731 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9379 13:38:38.742826 Finalize devices...
9380 13:38:38.746402 Devices finalized
9381 13:38:38.749810 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9382 13:38:38.753181 Writing coreboot table at 0xffe64000
9383 13:38:38.755896 0. 000000000010a000-0000000000113fff: RAMSTAGE
9384 13:38:38.759240 1. 0000000040000000-00000000400fffff: RAM
9385 13:38:38.766030 2. 0000000040100000-000000004032afff: RAMSTAGE
9386 13:38:38.769414 3. 000000004032b000-00000000545fffff: RAM
9387 13:38:38.772925 4. 0000000054600000-000000005465ffff: BL31
9388 13:38:38.776292 5. 0000000054660000-00000000ffe63fff: RAM
9389 13:38:38.782413 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9390 13:38:38.785803 7. 0000000100000000-000000023fffffff: RAM
9391 13:38:38.789357 Passing 5 GPIOs to payload:
9392 13:38:38.792666 NAME | PORT | POLARITY | VALUE
9393 13:38:38.799516 EC in RW | 0x000000aa | low | undefined
9394 13:38:38.802890 EC interrupt | 0x00000005 | low | undefined
9395 13:38:38.805721 TPM interrupt | 0x000000ab | high | undefined
9396 13:38:38.812397 SD card detect | 0x00000011 | high | undefined
9397 13:38:38.815970 speaker enable | 0x00000093 | high | undefined
9398 13:38:38.818688 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9399 13:38:38.822127 in-header: 03 f9 00 00 02 00 00 00
9400 13:38:38.825692 in-data: 02 00
9401 13:38:38.828995 ADC[4]: Raw value=893711 ID=7
9402 13:38:38.829075 ADC[3]: Raw value=213070 ID=1
9403 13:38:38.832193 RAM Code: 0x71
9404 13:38:38.835405 ADC[6]: Raw value=74722 ID=0
9405 13:38:38.835491 ADC[5]: Raw value=211590 ID=1
9406 13:38:38.839117 SKU Code: 0x1
9407 13:38:38.842162 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d2a
9408 13:38:38.845355 coreboot table: 964 bytes.
9409 13:38:38.848665 IMD ROOT 0. 0xfffff000 0x00001000
9410 13:38:38.852322 IMD SMALL 1. 0xffffe000 0x00001000
9411 13:38:38.855283 RO MCACHE 2. 0xffffc000 0x00001104
9412 13:38:38.858718 CONSOLE 3. 0xfff7c000 0x00080000
9413 13:38:38.862078 FMAP 4. 0xfff7b000 0x00000452
9414 13:38:38.865424 TIME STAMP 5. 0xfff7a000 0x00000910
9415 13:38:38.868458 VBOOT WORK 6. 0xfff66000 0x00014000
9416 13:38:38.872026 RAMOOPS 7. 0xffe66000 0x00100000
9417 13:38:38.875286 COREBOOT 8. 0xffe64000 0x00002000
9418 13:38:38.878565 IMD small region:
9419 13:38:38.881964 IMD ROOT 0. 0xffffec00 0x00000400
9420 13:38:38.885375 VPD 1. 0xffffeb80 0x0000006c
9421 13:38:38.888093 MMC STATUS 2. 0xffffeb60 0x00000004
9422 13:38:38.891435 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9423 13:38:38.894845 Probing TPM: done!
9424 13:38:38.898863 Connected to device vid:did:rid of 1ae0:0028:00
9425 13:38:38.909073 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9426 13:38:38.912486 Initialized TPM device CR50 revision 0
9427 13:38:38.915790 Checking cr50 for pending updates
9428 13:38:38.919895 Reading cr50 TPM mode
9429 13:38:38.928128 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9430 13:38:38.935034 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9431 13:38:38.975607 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9432 13:38:38.978815 Checking segment from ROM address 0x40100000
9433 13:38:38.982024 Checking segment from ROM address 0x4010001c
9434 13:38:38.988386 Loading segment from ROM address 0x40100000
9435 13:38:38.988533 code (compression=0)
9436 13:38:38.998671 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9437 13:38:39.005411 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9438 13:38:39.005552 it's not compressed!
9439 13:38:39.012002 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9440 13:38:39.015376 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9441 13:38:39.035976 Loading segment from ROM address 0x4010001c
9442 13:38:39.036177 Entry Point 0x80000000
9443 13:38:39.038882 Loaded segments
9444 13:38:39.042295 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9445 13:38:39.048989 Jumping to boot code at 0x80000000(0xffe64000)
9446 13:38:39.055659 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9447 13:38:39.061944 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9448 13:38:39.070016 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9449 13:38:39.073369 Checking segment from ROM address 0x40100000
9450 13:38:39.076788 Checking segment from ROM address 0x4010001c
9451 13:38:39.083319 Loading segment from ROM address 0x40100000
9452 13:38:39.083422 code (compression=1)
9453 13:38:39.090009 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9454 13:38:39.099854 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9455 13:38:39.099989 using LZMA
9456 13:38:39.108295 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9457 13:38:39.115198 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9458 13:38:39.118365 Loading segment from ROM address 0x4010001c
9459 13:38:39.118449 Entry Point 0x54601000
9460 13:38:39.121505 Loaded segments
9461 13:38:39.124696 NOTICE: MT8192 bl31_setup
9462 13:38:39.132253 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9463 13:38:39.134985 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9464 13:38:39.138376 WARNING: region 0:
9465 13:38:39.141991 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 13:38:39.142100 WARNING: region 1:
9467 13:38:39.148886 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9468 13:38:39.152200 WARNING: region 2:
9469 13:38:39.155562 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9470 13:38:39.158824 WARNING: region 3:
9471 13:38:39.162024 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 13:38:39.165385 WARNING: region 4:
9473 13:38:39.172130 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9474 13:38:39.172219 WARNING: region 5:
9475 13:38:39.175450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 13:38:39.178948 WARNING: region 6:
9477 13:38:39.182053 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 13:38:39.185305 WARNING: region 7:
9479 13:38:39.188788 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 13:38:39.195517 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9481 13:38:39.198998 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9482 13:38:39.201663 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9483 13:38:39.208948 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9484 13:38:39.212187 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9485 13:38:39.215488 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9486 13:38:39.222231 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9487 13:38:39.225438 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9488 13:38:39.232150 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9489 13:38:39.235425 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9490 13:38:39.238731 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9491 13:38:39.245566 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9492 13:38:39.248278 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9493 13:38:39.251840 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9494 13:38:39.258716 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9495 13:38:39.262050 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9496 13:38:39.268747 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9497 13:38:39.271967 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9498 13:38:39.275103 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9499 13:38:39.282057 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9500 13:38:39.285437 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9501 13:38:39.288533 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9502 13:38:39.295547 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9503 13:38:39.298771 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9504 13:38:39.305499 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9505 13:38:39.308815 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9506 13:38:39.312092 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9507 13:38:39.318707 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9508 13:38:39.322113 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9509 13:38:39.328353 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9510 13:38:39.331609 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9511 13:38:39.335535 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9512 13:38:39.342091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9513 13:38:39.345386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9514 13:38:39.348766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9515 13:38:39.352113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9516 13:38:39.358850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9517 13:38:39.362333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9518 13:38:39.365120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9519 13:38:39.368651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9520 13:38:39.372048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9521 13:38:39.378737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9522 13:38:39.381912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9523 13:38:39.385081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9524 13:38:39.391858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9525 13:38:39.395135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9526 13:38:39.398394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9527 13:38:39.401741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9528 13:38:39.408438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9529 13:38:39.411343 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9530 13:38:39.418171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9531 13:38:39.421339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9532 13:38:39.428229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9533 13:38:39.431419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9534 13:38:39.434740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9535 13:38:39.441520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9536 13:38:39.444822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9537 13:38:39.451555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9538 13:38:39.454916 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9539 13:38:39.461447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9540 13:38:39.465022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9541 13:38:39.471227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9542 13:38:39.474646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9543 13:38:39.478131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9544 13:38:39.484895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9545 13:38:39.488070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9546 13:38:39.494483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9547 13:38:39.497916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9548 13:38:39.504756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9549 13:38:39.508072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9550 13:38:39.511381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9551 13:38:39.518172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9552 13:38:39.521571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9553 13:38:39.528206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9554 13:38:39.531403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9555 13:38:39.537815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9556 13:38:39.541329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9557 13:38:39.544516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9558 13:38:39.551723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9559 13:38:39.555147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9560 13:38:39.561263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9561 13:38:39.564715 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9562 13:38:39.571480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9563 13:38:39.574933 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9564 13:38:39.578162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9565 13:38:39.584820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9566 13:38:39.588078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9567 13:38:39.594784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9568 13:38:39.598481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9569 13:38:39.604776 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9570 13:38:39.608058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9571 13:38:39.611323 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9572 13:38:39.618028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9573 13:38:39.621265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9574 13:38:39.627904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9575 13:38:39.631204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9576 13:38:39.634533 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9577 13:38:39.641168 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9578 13:38:39.644376 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9579 13:38:39.647649 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9580 13:38:39.650973 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9581 13:38:39.658026 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9582 13:38:39.661410 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9583 13:38:39.668007 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9584 13:38:39.671366 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9585 13:38:39.674633 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9586 13:38:39.681362 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9587 13:38:39.684594 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9588 13:38:39.691237 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9589 13:38:39.694721 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9590 13:38:39.698056 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9591 13:38:39.704094 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9592 13:38:39.707557 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9593 13:38:39.714624 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9594 13:38:39.717808 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9595 13:38:39.720892 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9596 13:38:39.727631 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9597 13:38:39.730718 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9598 13:38:39.734265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9599 13:38:39.740780 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9600 13:38:39.744059 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9601 13:38:39.747461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9602 13:38:39.750823 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9603 13:38:39.757806 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9604 13:38:39.761021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9605 13:38:39.764250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9606 13:38:39.771379 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9607 13:38:39.774705 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9608 13:38:39.781241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9609 13:38:39.784387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9610 13:38:39.787809 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9611 13:38:39.794457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9612 13:38:39.797736 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9613 13:38:39.800986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9614 13:38:39.807809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9615 13:38:39.811109 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9616 13:38:39.817816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9617 13:38:39.821138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9618 13:38:39.824428 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9619 13:38:39.830969 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9620 13:38:39.834727 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9621 13:38:39.841071 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9622 13:38:39.844718 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9623 13:38:39.847687 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9624 13:38:39.854737 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9625 13:38:39.857937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9626 13:38:39.861239 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9627 13:38:39.867692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9628 13:38:39.870837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9629 13:38:39.877934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9630 13:38:39.881394 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9631 13:38:39.884673 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9632 13:38:39.891378 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9633 13:38:39.894705 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9634 13:38:39.901288 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9635 13:38:39.904716 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9636 13:38:39.908108 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9637 13:38:39.914132 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9638 13:38:39.917378 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9639 13:38:39.920751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9640 13:38:39.927310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9641 13:38:39.931283 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9642 13:38:39.937836 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9643 13:38:39.941050 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9644 13:38:39.947571 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9645 13:38:39.950805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9646 13:38:39.953948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9647 13:38:39.960718 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9648 13:38:39.964324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9649 13:38:39.967631 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9650 13:38:39.974002 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9651 13:38:39.977305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9652 13:38:39.983823 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9653 13:38:39.987091 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9654 13:38:39.990341 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9655 13:38:39.997090 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9656 13:38:40.000441 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9657 13:38:40.007116 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9658 13:38:40.010481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9659 13:38:40.014011 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9660 13:38:40.020495 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9661 13:38:40.023767 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9662 13:38:40.030302 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9663 13:38:40.033704 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9664 13:38:40.037075 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9665 13:38:40.043757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9666 13:38:40.047024 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9667 13:38:40.053608 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9668 13:38:40.056840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9669 13:38:40.060253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9670 13:38:40.066827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9671 13:38:40.069824 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9672 13:38:40.076636 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9673 13:38:40.079688 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9674 13:38:40.082996 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9675 13:38:40.089696 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9676 13:38:40.093351 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9677 13:38:40.100105 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9678 13:38:40.103333 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9679 13:38:40.110103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9680 13:38:40.112776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9681 13:38:40.116126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9682 13:38:40.122740 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9683 13:38:40.126071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9684 13:38:40.132680 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9685 13:38:40.136133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9686 13:38:40.142759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9687 13:38:40.146124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9688 13:38:40.149385 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9689 13:38:40.156119 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9690 13:38:40.159251 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9691 13:38:40.165877 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9692 13:38:40.169788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9693 13:38:40.173039 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9694 13:38:40.179624 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9695 13:38:40.182862 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9696 13:38:40.189609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9697 13:38:40.192924 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9698 13:38:40.199261 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9699 13:38:40.202771 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9700 13:38:40.206216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9701 13:38:40.212693 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9702 13:38:40.215861 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9703 13:38:40.222590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9704 13:38:40.225788 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9705 13:38:40.229163 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9706 13:38:40.235775 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9707 13:38:40.239006 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9708 13:38:40.245781 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9709 13:38:40.249084 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9710 13:38:40.252480 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9711 13:38:40.255805 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9712 13:38:40.262457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9713 13:38:40.265638 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9714 13:38:40.269073 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9715 13:38:40.275145 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9716 13:38:40.279070 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9717 13:38:40.281731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9718 13:38:40.288906 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9719 13:38:40.292166 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9720 13:38:40.295463 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9721 13:38:40.302162 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9722 13:38:40.305565 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9723 13:38:40.308724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9724 13:38:40.315052 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9725 13:38:40.318788 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9726 13:38:40.324972 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9727 13:38:40.328796 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9728 13:38:40.332330 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9729 13:38:40.338400 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9730 13:38:40.341737 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9731 13:38:40.344978 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9732 13:38:40.351760 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9733 13:38:40.355157 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9734 13:38:40.361672 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9735 13:38:40.365044 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9736 13:38:40.368144 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9737 13:38:40.374786 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9738 13:38:40.378274 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9739 13:38:40.381364 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9740 13:38:40.388143 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9741 13:38:40.391478 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9742 13:38:40.398171 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9743 13:38:40.401460 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9744 13:38:40.404862 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9745 13:38:40.411564 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9746 13:38:40.414725 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9747 13:38:40.418024 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9748 13:38:40.424570 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9749 13:38:40.427818 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9750 13:38:40.431240 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9751 13:38:40.434399 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9752 13:38:40.441212 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9753 13:38:40.444197 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9754 13:38:40.447910 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9755 13:38:40.450964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9756 13:38:40.457255 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9757 13:38:40.460848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9758 13:38:40.463848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9759 13:38:40.467206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9760 13:38:40.473724 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9761 13:38:40.477430 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9762 13:38:40.480799 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9763 13:38:40.487199 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9764 13:38:40.490618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9765 13:38:40.496997 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9766 13:38:40.500303 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9767 13:38:40.507145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9768 13:38:40.510465 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9769 13:38:40.513146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9770 13:38:40.519988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9771 13:38:40.523353 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9772 13:38:40.530039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9773 13:38:40.533157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9774 13:38:40.539660 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9775 13:38:40.543031 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9776 13:38:40.546406 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9777 13:38:40.553115 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9778 13:38:40.556415 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9779 13:38:40.562994 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9780 13:38:40.566096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9781 13:38:40.569750 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9782 13:38:40.576530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9783 13:38:40.579526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9784 13:38:40.586161 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9785 13:38:40.589725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9786 13:38:40.592912 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9787 13:38:40.599294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9788 13:38:40.602519 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9789 13:38:40.609140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9790 13:38:40.612451 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9791 13:38:40.619078 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9792 13:38:40.622327 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9793 13:38:40.625661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9794 13:38:40.632328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9795 13:38:40.635591 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9796 13:38:40.642071 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9797 13:38:40.645605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9798 13:38:40.652128 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9799 13:38:40.655567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9800 13:38:40.658892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9801 13:38:40.665351 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9802 13:38:40.668803 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9803 13:38:40.672160 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9804 13:38:40.678784 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9805 13:38:40.682227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9806 13:38:40.688964 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9807 13:38:40.692168 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9808 13:38:40.698636 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9809 13:38:40.702455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9810 13:38:40.705145 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9811 13:38:40.711737 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9812 13:38:40.715048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9813 13:38:40.721496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9814 13:38:40.725393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9815 13:38:40.732080 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9816 13:38:40.734836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9817 13:38:40.738239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9818 13:38:40.744795 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9819 13:38:40.748071 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9820 13:38:40.754873 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9821 13:38:40.757936 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9822 13:38:40.761354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9823 13:38:40.768155 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9824 13:38:40.771283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9825 13:38:40.778022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9826 13:38:40.781441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9827 13:38:40.784788 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9828 13:38:40.791364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9829 13:38:40.794761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9830 13:38:40.801415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9831 13:38:40.804740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9832 13:38:40.811018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9833 13:38:40.814409 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9834 13:38:40.817703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9835 13:38:40.824530 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9836 13:38:40.827402 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9837 13:38:40.834114 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9838 13:38:40.837689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9839 13:38:40.843757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9840 13:38:40.847185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9841 13:38:40.850697 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9842 13:38:40.857287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9843 13:38:40.860627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9844 13:38:40.866967 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9845 13:38:40.870775 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9846 13:38:40.877059 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9847 13:38:40.880477 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9848 13:38:40.887092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9849 13:38:40.890438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9850 13:38:40.893729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9851 13:38:40.900377 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9852 13:38:40.903176 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9853 13:38:40.909777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9854 13:38:40.913102 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9855 13:38:40.920127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9856 13:38:40.923265 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9857 13:38:40.926709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9858 13:38:40.933343 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9859 13:38:40.936650 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9860 13:38:40.943117 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9861 13:38:40.946094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9862 13:38:40.952801 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9863 13:38:40.956063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9864 13:38:40.963113 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9865 13:38:40.965905 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9866 13:38:40.969316 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9867 13:38:40.976264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9868 13:38:40.979239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9869 13:38:40.985619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9870 13:38:40.989426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9871 13:38:40.995971 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9872 13:38:40.999411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9873 13:38:41.005572 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9874 13:38:41.008964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9875 13:38:41.012313 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9876 13:38:41.018728 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9877 13:38:41.022083 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9878 13:38:41.028723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9879 13:38:41.031975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9880 13:38:41.038739 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9881 13:38:41.042147 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9882 13:38:41.045458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9883 13:38:41.051934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9884 13:38:41.055209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9885 13:38:41.062069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9886 13:38:41.065421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9887 13:38:41.071626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9888 13:38:41.074954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9889 13:38:41.081820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9890 13:38:41.085193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9891 13:38:41.091696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9892 13:38:41.095436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9893 13:38:41.101557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9894 13:38:41.105252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9895 13:38:41.111760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9896 13:38:41.115068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9897 13:38:41.121735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9898 13:38:41.125153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9899 13:38:41.131792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9900 13:38:41.135054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9901 13:38:41.141667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9902 13:38:41.144774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9903 13:38:41.151444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9904 13:38:41.154740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9905 13:38:41.161437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9906 13:38:41.164812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9907 13:38:41.171127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9908 13:38:41.174895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9909 13:38:41.181127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9910 13:38:41.184901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9911 13:38:41.191377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9912 13:38:41.194783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9913 13:38:41.201328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9914 13:38:41.204535 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9915 13:38:41.207729 INFO: [APUAPC] vio 0
9916 13:38:41.210911 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9917 13:38:41.214494 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9918 13:38:41.217648 INFO: [APUAPC] D0_APC_0: 0x400510
9919 13:38:41.220852 INFO: [APUAPC] D0_APC_1: 0x0
9920 13:38:41.224255 INFO: [APUAPC] D0_APC_2: 0x1540
9921 13:38:41.227754 INFO: [APUAPC] D0_APC_3: 0x0
9922 13:38:41.231074 INFO: [APUAPC] D1_APC_0: 0xffffffff
9923 13:38:41.234342 INFO: [APUAPC] D1_APC_1: 0xffffffff
9924 13:38:41.237722 INFO: [APUAPC] D1_APC_2: 0x3fffff
9925 13:38:41.241014 INFO: [APUAPC] D1_APC_3: 0x0
9926 13:38:41.244219 INFO: [APUAPC] D2_APC_0: 0xffffffff
9927 13:38:41.247479 INFO: [APUAPC] D2_APC_1: 0xffffffff
9928 13:38:41.250728 INFO: [APUAPC] D2_APC_2: 0x3fffff
9929 13:38:41.253945 INFO: [APUAPC] D2_APC_3: 0x0
9930 13:38:41.257733 INFO: [APUAPC] D3_APC_0: 0xffffffff
9931 13:38:41.260417 INFO: [APUAPC] D3_APC_1: 0xffffffff
9932 13:38:41.263811 INFO: [APUAPC] D3_APC_2: 0x3fffff
9933 13:38:41.267155 INFO: [APUAPC] D3_APC_3: 0x0
9934 13:38:41.270456 INFO: [APUAPC] D4_APC_0: 0xffffffff
9935 13:38:41.273815 INFO: [APUAPC] D4_APC_1: 0xffffffff
9936 13:38:41.277108 INFO: [APUAPC] D4_APC_2: 0x3fffff
9937 13:38:41.280948 INFO: [APUAPC] D4_APC_3: 0x0
9938 13:38:41.283725 INFO: [APUAPC] D5_APC_0: 0xffffffff
9939 13:38:41.287130 INFO: [APUAPC] D5_APC_1: 0xffffffff
9940 13:38:41.290254 INFO: [APUAPC] D5_APC_2: 0x3fffff
9941 13:38:41.294008 INFO: [APUAPC] D5_APC_3: 0x0
9942 13:38:41.297138 INFO: [APUAPC] D6_APC_0: 0xffffffff
9943 13:38:41.300420 INFO: [APUAPC] D6_APC_1: 0xffffffff
9944 13:38:41.303841 INFO: [APUAPC] D6_APC_2: 0x3fffff
9945 13:38:41.307205 INFO: [APUAPC] D6_APC_3: 0x0
9946 13:38:41.310730 INFO: [APUAPC] D7_APC_0: 0xffffffff
9947 13:38:41.313984 INFO: [APUAPC] D7_APC_1: 0xffffffff
9948 13:38:41.316699 INFO: [APUAPC] D7_APC_2: 0x3fffff
9949 13:38:41.320062 INFO: [APUAPC] D7_APC_3: 0x0
9950 13:38:41.323439 INFO: [APUAPC] D8_APC_0: 0xffffffff
9951 13:38:41.327222 INFO: [APUAPC] D8_APC_1: 0xffffffff
9952 13:38:41.330181 INFO: [APUAPC] D8_APC_2: 0x3fffff
9953 13:38:41.333279 INFO: [APUAPC] D8_APC_3: 0x0
9954 13:38:41.336707 INFO: [APUAPC] D9_APC_0: 0xffffffff
9955 13:38:41.340054 INFO: [APUAPC] D9_APC_1: 0xffffffff
9956 13:38:41.343314 INFO: [APUAPC] D9_APC_2: 0x3fffff
9957 13:38:41.343384 INFO: [APUAPC] D9_APC_3: 0x0
9958 13:38:41.350422 INFO: [APUAPC] D10_APC_0: 0xffffffff
9959 13:38:41.353754 INFO: [APUAPC] D10_APC_1: 0xffffffff
9960 13:38:41.356937 INFO: [APUAPC] D10_APC_2: 0x3fffff
9961 13:38:41.357012 INFO: [APUAPC] D10_APC_3: 0x0
9962 13:38:41.363635 INFO: [APUAPC] D11_APC_0: 0xffffffff
9963 13:38:41.366871 INFO: [APUAPC] D11_APC_1: 0xffffffff
9964 13:38:41.370262 INFO: [APUAPC] D11_APC_2: 0x3fffff
9965 13:38:41.373000 INFO: [APUAPC] D11_APC_3: 0x0
9966 13:38:41.376612 INFO: [APUAPC] D12_APC_0: 0xffffffff
9967 13:38:41.379804 INFO: [APUAPC] D12_APC_1: 0xffffffff
9968 13:38:41.383105 INFO: [APUAPC] D12_APC_2: 0x3fffff
9969 13:38:41.386292 INFO: [APUAPC] D12_APC_3: 0x0
9970 13:38:41.389644 INFO: [APUAPC] D13_APC_0: 0xffffffff
9971 13:38:41.393172 INFO: [APUAPC] D13_APC_1: 0xffffffff
9972 13:38:41.396219 INFO: [APUAPC] D13_APC_2: 0x3fffff
9973 13:38:41.400020 INFO: [APUAPC] D13_APC_3: 0x0
9974 13:38:41.403197 INFO: [APUAPC] D14_APC_0: 0xffffffff
9975 13:38:41.406633 INFO: [APUAPC] D14_APC_1: 0xffffffff
9976 13:38:41.409798 INFO: [APUAPC] D14_APC_2: 0x3fffff
9977 13:38:41.413073 INFO: [APUAPC] D14_APC_3: 0x0
9978 13:38:41.416403 INFO: [APUAPC] D15_APC_0: 0xffffffff
9979 13:38:41.419714 INFO: [APUAPC] D15_APC_1: 0xffffffff
9980 13:38:41.423155 INFO: [APUAPC] D15_APC_2: 0x3fffff
9981 13:38:41.426438 INFO: [APUAPC] D15_APC_3: 0x0
9982 13:38:41.426539 INFO: [APUAPC] APC_CON: 0x4
9983 13:38:41.429743 INFO: [NOCDAPC] D0_APC_0: 0x0
9984 13:38:41.432952 INFO: [NOCDAPC] D0_APC_1: 0x0
9985 13:38:41.436375 INFO: [NOCDAPC] D1_APC_0: 0x0
9986 13:38:41.439583 INFO: [NOCDAPC] D1_APC_1: 0xfff
9987 13:38:41.442637 INFO: [NOCDAPC] D2_APC_0: 0x0
9988 13:38:41.446530 INFO: [NOCDAPC] D2_APC_1: 0xfff
9989 13:38:41.449699 INFO: [NOCDAPC] D3_APC_0: 0x0
9990 13:38:41.453070 INFO: [NOCDAPC] D3_APC_1: 0xfff
9991 13:38:41.456404 INFO: [NOCDAPC] D4_APC_0: 0x0
9992 13:38:41.459181 INFO: [NOCDAPC] D4_APC_1: 0xfff
9993 13:38:41.459281 INFO: [NOCDAPC] D5_APC_0: 0x0
9994 13:38:41.462467 INFO: [NOCDAPC] D5_APC_1: 0xfff
9995 13:38:41.465735 INFO: [NOCDAPC] D6_APC_0: 0x0
9996 13:38:41.469022 INFO: [NOCDAPC] D6_APC_1: 0xfff
9997 13:38:41.472839 INFO: [NOCDAPC] D7_APC_0: 0x0
9998 13:38:41.476119 INFO: [NOCDAPC] D7_APC_1: 0xfff
9999 13:38:41.479492 INFO: [NOCDAPC] D8_APC_0: 0x0
10000 13:38:41.482780 INFO: [NOCDAPC] D8_APC_1: 0xfff
10001 13:38:41.486054 INFO: [NOCDAPC] D9_APC_0: 0x0
10002 13:38:41.488740 INFO: [NOCDAPC] D9_APC_1: 0xfff
10003 13:38:41.492554 INFO: [NOCDAPC] D10_APC_0: 0x0
10004 13:38:41.495875 INFO: [NOCDAPC] D10_APC_1: 0xfff
10005 13:38:41.495948 INFO: [NOCDAPC] D11_APC_0: 0x0
10006 13:38:41.499399 INFO: [NOCDAPC] D11_APC_1: 0xfff
10007 13:38:41.502624 INFO: [NOCDAPC] D12_APC_0: 0x0
10008 13:38:41.505783 INFO: [NOCDAPC] D12_APC_1: 0xfff
10009 13:38:41.508961 INFO: [NOCDAPC] D13_APC_0: 0x0
10010 13:38:41.512187 INFO: [NOCDAPC] D13_APC_1: 0xfff
10011 13:38:41.515503 INFO: [NOCDAPC] D14_APC_0: 0x0
10012 13:38:41.518793 INFO: [NOCDAPC] D14_APC_1: 0xfff
10013 13:38:41.522002 INFO: [NOCDAPC] D15_APC_0: 0x0
10014 13:38:41.525824 INFO: [NOCDAPC] D15_APC_1: 0xfff
10015 13:38:41.528690 INFO: [NOCDAPC] APC_CON: 0x4
10016 13:38:41.532011 INFO: [APUAPC] set_apusys_apc done
10017 13:38:41.535259 INFO: [DEVAPC] devapc_init done
10018 13:38:41.538768 INFO: GICv3 without legacy support detected.
10019 13:38:41.542152 INFO: ARM GICv3 driver initialized in EL3
10020 13:38:41.545367 INFO: Maximum SPI INTID supported: 639
10021 13:38:41.551657 INFO: BL31: Initializing runtime services
10022 13:38:41.554936 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10023 13:38:41.558770 INFO: SPM: enable CPC mode
10024 13:38:41.565234 INFO: mcdi ready for mcusys-off-idle and system suspend
10025 13:38:41.568618 INFO: BL31: Preparing for EL3 exit to normal world
10026 13:38:41.571890 INFO: Entry point address = 0x80000000
10027 13:38:41.575151 INFO: SPSR = 0x8
10028 13:38:41.580498
10029 13:38:41.580653
10030 13:38:41.580747
10031 13:38:41.583121 Starting depthcharge on Spherion...
10032 13:38:41.583235
10033 13:38:41.583329 Wipe memory regions:
10034 13:38:41.583420
10035 13:38:41.584288 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10036 13:38:41.584419 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10037 13:38:41.584537 Setting prompt string to ['asurada:']
10038 13:38:41.584687 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10039 13:38:41.586585 [0x00000040000000, 0x00000054600000)
10040 13:38:41.709341
10041 13:38:41.709486 [0x00000054660000, 0x00000080000000)
10042 13:38:41.969159
10043 13:38:41.969321 [0x000000821a7280, 0x000000ffe64000)
10044 13:38:42.713984
10045 13:38:42.714158 [0x00000100000000, 0x00000240000000)
10046 13:38:44.602302
10047 13:38:44.605463 Initializing XHCI USB controller at 0x11200000.
10048 13:38:45.643325
10049 13:38:45.647004 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10050 13:38:45.647124
10051 13:38:45.647202
10052 13:38:45.647490 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 13:38:45.747828 asurada: tftpboot 192.168.201.1 14063039/tftp-deploy-e4u_78p6/kernel/image.itb 14063039/tftp-deploy-e4u_78p6/kernel/cmdline
10055 13:38:45.748017 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 13:38:45.748124 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10057 13:38:45.752413 tftpboot 192.168.201.1 14063039/tftp-deploy-e4u_78p6/kernel/image.itp-deploy-e4u_78p6/kernel/cmdline
10058 13:38:45.752532
10059 13:38:45.752651 Waiting for link
10060 13:38:45.913241
10061 13:38:45.913391 R8152: Initializing
10062 13:38:45.913497
10063 13:38:45.916306 Version 6 (ocp_data = 5c30)
10064 13:38:45.916413
10065 13:38:45.919292 R8152: Done initializing
10066 13:38:45.919373
10067 13:38:45.919436 Adding net device
10068 13:38:47.823046
10069 13:38:47.823216 done.
10070 13:38:47.823313
10071 13:38:47.823402 MAC: 00:24:32:30:78:ff
10072 13:38:47.823490
10073 13:38:47.826344 Sending DHCP discover... done.
10074 13:38:47.826450
10075 13:38:47.829679 Waiting for reply... done.
10076 13:38:47.829792
10077 13:38:47.832972 Sending DHCP request... done.
10078 13:38:47.833076
10079 13:38:47.833165 Waiting for reply... done.
10080 13:38:47.833252
10081 13:38:47.836218 My ip is 192.168.201.21
10082 13:38:47.836325
10083 13:38:47.839268 The DHCP server ip is 192.168.201.1
10084 13:38:47.839376
10085 13:38:47.842230 TFTP server IP predefined by user: 192.168.201.1
10086 13:38:47.842313
10087 13:38:47.849134 Bootfile predefined by user: 14063039/tftp-deploy-e4u_78p6/kernel/image.itb
10088 13:38:47.849212
10089 13:38:47.852351 Sending tftp read request... done.
10090 13:38:47.852422
10091 13:38:47.855698 Waiting for the transfer...
10092 13:38:47.855780
10093 13:38:48.400780 00000000 ################################################################
10094 13:38:48.400919
10095 13:38:48.931181 00080000 ################################################################
10096 13:38:48.931318
10097 13:38:49.477655 00100000 ################################################################
10098 13:38:49.477794
10099 13:38:50.010063 00180000 ################################################################
10100 13:38:50.010205
10101 13:38:50.538838 00200000 ################################################################
10102 13:38:50.539011
10103 13:38:51.069263 00280000 ################################################################
10104 13:38:51.069400
10105 13:38:51.606368 00300000 ################################################################
10106 13:38:51.606524
10107 13:38:52.139995 00380000 ################################################################
10108 13:38:52.140152
10109 13:38:52.669192 00400000 ################################################################
10110 13:38:52.669351
10111 13:38:53.202182 00480000 ################################################################
10112 13:38:53.202323
10113 13:38:53.847127 00500000 ################################################################
10114 13:38:53.847303
10115 13:38:54.482998 00580000 ################################################################
10116 13:38:54.483191
10117 13:38:55.064953 00600000 ################################################################
10118 13:38:55.065144
10119 13:38:55.601154 00680000 ################################################################
10120 13:38:55.601309
10121 13:38:56.141500 00700000 ################################################################
10122 13:38:56.141629
10123 13:38:56.700555 00780000 ################################################################
10124 13:38:56.700756
10125 13:38:57.249588 00800000 ################################################################
10126 13:38:57.249721
10127 13:38:57.791393 00880000 ################################################################
10128 13:38:57.791557
10129 13:38:58.343712 00900000 ################################################################
10130 13:38:58.343848
10131 13:38:58.908564 00980000 ################################################################
10132 13:38:58.908708
10133 13:38:59.494404 00a00000 ################################################################
10134 13:38:59.494550
10135 13:39:00.065163 00a80000 ################################################################
10136 13:39:00.065308
10137 13:39:00.620791 00b00000 ################################################################
10138 13:39:00.620927
10139 13:39:01.163691 00b80000 ################################################################
10140 13:39:01.163826
10141 13:39:01.708711 00c00000 ################################################################
10142 13:39:01.708840
10143 13:39:02.244364 00c80000 ################################################################
10144 13:39:02.244526
10145 13:39:02.786381 00d00000 ################################################################
10146 13:39:02.786543
10147 13:39:03.341022 00d80000 ################################################################
10148 13:39:03.341160
10149 13:39:03.894129 00e00000 ################################################################
10150 13:39:03.894264
10151 13:39:04.432575 00e80000 ################################################################
10152 13:39:04.432710
10153 13:39:04.991233 00f00000 ################################################################
10154 13:39:04.991379
10155 13:39:05.537172 00f80000 ################################################################
10156 13:39:05.537377
10157 13:39:06.083005 01000000 ################################################################
10158 13:39:06.083147
10159 13:39:06.639594 01080000 ################################################################
10160 13:39:06.639724
10161 13:39:07.173262 01100000 ################################################################
10162 13:39:07.173417
10163 13:39:07.708720 01180000 ################################################################
10164 13:39:07.708885
10165 13:39:08.242931 01200000 ################################################################
10166 13:39:08.243080
10167 13:39:08.773322 01280000 ################################################################
10168 13:39:08.773471
10169 13:39:09.296942 01300000 ################################################################
10170 13:39:09.297124
10171 13:39:09.823686 01380000 ################################################################
10172 13:39:09.823857
10173 13:39:10.365975 01400000 ################################################################
10174 13:39:10.366151
10175 13:39:10.901931 01480000 ################################################################
10176 13:39:10.902125
10177 13:39:11.432615 01500000 ################################################################
10178 13:39:11.432778
10179 13:39:11.974449 01580000 ################################################################
10180 13:39:11.974594
10181 13:39:12.548881 01600000 ################################################################
10182 13:39:12.549029
10183 13:39:13.149655 01680000 ################################################################
10184 13:39:13.149794
10185 13:39:13.730733 01700000 ################################################################
10186 13:39:13.730871
10187 13:39:14.307965 01780000 ################################################################
10188 13:39:14.308095
10189 13:39:14.888639 01800000 ################################################################
10190 13:39:14.888798
10191 13:39:15.479119 01880000 ################################################################
10192 13:39:15.479252
10193 13:39:16.050612 01900000 ################################################################
10194 13:39:16.050753
10195 13:39:16.636279 01980000 ################################################################
10196 13:39:16.636410
10197 13:39:17.206527 01a00000 ################################################################
10198 13:39:17.206659
10199 13:39:17.787174 01a80000 ################################################################
10200 13:39:17.787309
10201 13:39:18.333368 01b00000 ################################################################
10202 13:39:18.333502
10203 13:39:18.952041 01b80000 ################################################################
10204 13:39:18.952697
10205 13:39:19.550396 01c00000 ################################################################
10206 13:39:19.550533
10207 13:39:20.193440 01c80000 ################################################################
10208 13:39:20.193576
10209 13:39:20.781666 01d00000 ################################################################
10210 13:39:20.781801
10211 13:39:21.439700 01d80000 ################################################################
10212 13:39:21.440273
10213 13:39:22.108909 01e00000 ################################################################
10214 13:39:22.109045
10215 13:39:22.768531 01e80000 ################################################################
10216 13:39:22.769299
10217 13:39:23.441306 01f00000 ################################################################
10218 13:39:23.441944
10219 13:39:24.103243 01f80000 ################################################################
10220 13:39:24.103377
10221 13:39:24.714327 02000000 ################################################################
10222 13:39:24.714963
10223 13:39:25.405047 02080000 ################################################################
10224 13:39:25.405619
10225 13:39:26.114464 02100000 ################################################################
10226 13:39:26.114995
10227 13:39:26.848398 02180000 ################################################################
10228 13:39:26.848975
10229 13:39:27.545093 02200000 ################################################################
10230 13:39:27.545609
10231 13:39:28.235220 02280000 ################################################################
10232 13:39:28.235727
10233 13:39:28.922983 02300000 ################################################################
10234 13:39:28.923346
10235 13:39:29.591032 02380000 ################################################################
10236 13:39:29.591539
10237 13:39:30.283825 02400000 ################################################################
10238 13:39:30.284409
10239 13:39:30.971683 02480000 ################################################################
10240 13:39:30.972173
10241 13:39:31.666818 02500000 ################################################################
10242 13:39:31.667347
10243 13:39:32.366039 02580000 ################################################################
10244 13:39:32.366551
10245 13:39:33.075112 02600000 ################################################################
10246 13:39:33.075678
10247 13:39:33.764689 02680000 ################################################################
10248 13:39:33.764834
10249 13:39:34.362413 02700000 ################################################################
10250 13:39:34.362581
10251 13:39:35.033315 02780000 ################################################################
10252 13:39:35.033872
10253 13:39:35.723373 02800000 ################################################################
10254 13:39:35.723979
10255 13:39:36.348764 02880000 ################################################################
10256 13:39:36.348907
10257 13:39:36.887460 02900000 ################################################################
10258 13:39:36.887606
10259 13:39:37.429612 02980000 ################################################################
10260 13:39:37.429779
10261 13:39:38.013993 02a00000 ################################################################
10262 13:39:38.014532
10263 13:39:38.638149 02a80000 ################################################################
10264 13:39:38.638675
10265 13:39:39.277859 02b00000 ################################################################
10266 13:39:39.277992
10267 13:39:39.990420 02b80000 ################################################################
10268 13:39:39.990561
10269 13:39:40.671706 02c00000 ################################################################
10270 13:39:40.671855
10271 13:39:41.263537 02c80000 ################################################################
10272 13:39:41.263687
10273 13:39:41.817391 02d00000 ################################################################
10274 13:39:41.817528
10275 13:39:42.416405 02d80000 ################################################################
10276 13:39:42.416594
10277 13:39:42.967430 02e00000 ################################################################
10278 13:39:42.967577
10279 13:39:43.533771 02e80000 ################################################################
10280 13:39:43.534343
10281 13:39:44.118469 02f00000 ################################################################
10282 13:39:44.118617
10283 13:39:44.674607 02f80000 ################################################################
10284 13:39:44.674748
10285 13:39:45.280735 03000000 ################################################################
10286 13:39:45.280884
10287 13:39:45.952499 03080000 ################################################################
10288 13:39:45.952681
10289 13:39:46.538668 03100000 ################################################################
10290 13:39:46.538803
10291 13:39:47.105322 03180000 ################################################################
10292 13:39:47.105472
10293 13:39:47.675136 03200000 ################################################################
10294 13:39:47.675274
10295 13:39:48.237689 03280000 ################################################################
10296 13:39:48.237843
10297 13:39:48.797077 03300000 ################################################################
10298 13:39:48.797220
10299 13:39:49.348971 03380000 ################################################################
10300 13:39:49.349122
10301 13:39:49.892492 03400000 ################################################################
10302 13:39:49.892696
10303 13:39:50.424508 03480000 ################################################################
10304 13:39:50.424663
10305 13:39:50.955545 03500000 ################################################################
10306 13:39:50.955698
10307 13:39:51.512376 03580000 ################################################################
10308 13:39:51.512546
10309 13:39:52.055311 03600000 ################################################################
10310 13:39:52.055528
10311 13:39:52.610917 03680000 ################################################################
10312 13:39:52.611093
10313 13:39:53.201487 03700000 ################################################################
10314 13:39:53.201623
10315 13:39:53.789814 03780000 ################################################################
10316 13:39:53.790033
10317 13:39:54.371181 03800000 ################################################################
10318 13:39:54.371362
10319 13:39:54.956489 03880000 ################################################################
10320 13:39:54.956684
10321 13:39:55.554297 03900000 ################################################################
10322 13:39:55.554498
10323 13:39:56.129542 03980000 ################################################################
10324 13:39:56.129691
10325 13:39:56.727178 03a00000 ################################################################
10326 13:39:56.727338
10327 13:39:57.322102 03a80000 ################################################################
10328 13:39:57.322256
10329 13:39:57.925916 03b00000 ################################################################
10330 13:39:57.926063
10331 13:39:58.521640 03b80000 ################################################################
10332 13:39:58.521780
10333 13:39:59.114156 03c00000 ################################################################
10334 13:39:59.114333
10335 13:39:59.675204 03c80000 ################################################################
10336 13:39:59.675371
10337 13:40:00.252701 03d00000 ################################################################
10338 13:40:00.252844
10339 13:40:00.834193 03d80000 ################################################################
10340 13:40:00.834334
10341 13:40:01.425610 03e00000 ################################################################
10342 13:40:01.425790
10343 13:40:01.996379 03e80000 ################################################################
10344 13:40:01.996525
10345 13:40:02.548855 03f00000 ################################################################
10346 13:40:02.549027
10347 13:40:03.076809 03f80000 ################################################################
10348 13:40:03.076961
10349 13:40:03.645513 04000000 ################################################################
10350 13:40:03.645657
10351 13:40:04.237784 04080000 ################################################################
10352 13:40:04.237927
10353 13:40:04.823156 04100000 ################################################################
10354 13:40:04.823306
10355 13:40:05.393430 04180000 ################################################################
10356 13:40:05.393596
10357 13:40:05.970736 04200000 ################################################################
10358 13:40:05.970936
10359 13:40:06.541216 04280000 ################################################################
10360 13:40:06.541401
10361 13:40:07.118375 04300000 ################################################################
10362 13:40:07.118512
10363 13:40:07.690087 04380000 ################################################################
10364 13:40:07.690227
10365 13:40:08.257588 04400000 ################################################################
10366 13:40:08.257746
10367 13:40:08.838313 04480000 ################################################################
10368 13:40:08.838505
10369 13:40:09.418959 04500000 ################################################################
10370 13:40:09.419108
10371 13:40:09.998827 04580000 ################################################################
10372 13:40:09.998999
10373 13:40:10.551189 04600000 ################################################################
10374 13:40:10.551341
10375 13:40:10.739943 04680000 ###################### done.
10376 13:40:10.740101
10377 13:40:10.743586 The bootfile was 74097030 bytes long.
10378 13:40:10.743672
10379 13:40:10.746754 Sending tftp read request... done.
10380 13:40:10.746836
10381 13:40:10.746901 Waiting for the transfer...
10382 13:40:10.746960
10383 13:40:10.749904 00000000 # done.
10384 13:40:10.749989
10385 13:40:10.756533 Command line loaded dynamically from TFTP file: 14063039/tftp-deploy-e4u_78p6/kernel/cmdline
10386 13:40:10.756666
10387 13:40:10.770229 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10388 13:40:10.770323
10389 13:40:10.773360 Loading FIT.
10390 13:40:10.773469
10391 13:40:10.776753 Image ramdisk-1 has 60986433 bytes.
10392 13:40:10.776851
10393 13:40:10.776914 Image fdt-1 has 47258 bytes.
10394 13:40:10.779841
10395 13:40:10.779922 Image kernel-1 has 13061303 bytes.
10396 13:40:10.779986
10397 13:40:10.789960 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10398 13:40:10.790059
10399 13:40:10.806542 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10400 13:40:10.806682
10401 13:40:10.813067 Choosing best match conf-1 for compat google,spherion-rev2.
10402 13:40:10.817598
10403 13:40:10.821615 Connected to device vid:did:rid of 1ae0:0028:00
10404 13:40:10.829091
10405 13:40:10.832562 tpm_get_response: command 0x17b, return code 0x0
10406 13:40:10.832674
10407 13:40:10.835618 ec_init: CrosEC protocol v3 supported (256, 248)
10408 13:40:10.840348
10409 13:40:10.843467 tpm_cleanup: add release locality here.
10410 13:40:10.843575
10411 13:40:10.843669 Shutting down all USB controllers.
10412 13:40:10.847026
10413 13:40:10.847129 Removing current net device
10414 13:40:10.847225
10415 13:40:10.853696 Exiting depthcharge with code 4 at timestamp: 118575775
10416 13:40:10.853805
10417 13:40:10.856799 LZMA decompressing kernel-1 to 0x821a6718
10418 13:40:10.856876
10419 13:40:10.860452 LZMA decompressing kernel-1 to 0x40000000
10420 13:40:12.471624
10421 13:40:12.471772 jumping to kernel
10422 13:40:12.472305 end: 2.2.4 bootloader-commands (duration 00:01:31) [common]
10423 13:40:12.472407 start: 2.2.5 auto-login-action (timeout 00:02:54) [common]
10424 13:40:12.472489 Setting prompt string to ['Linux version [0-9]']
10425 13:40:12.472635 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10426 13:40:12.472720 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10427 13:40:12.553560
10428 13:40:12.557279 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10429 13:40:12.560319 start: 2.2.5.1 login-action (timeout 00:02:54) [common]
10430 13:40:12.560453 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10431 13:40:12.560571 Setting prompt string to []
10432 13:40:12.560707 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10433 13:40:12.560798 Using line separator: #'\n'#
10434 13:40:12.560871 No login prompt set.
10435 13:40:12.560953 Parsing kernel messages
10436 13:40:12.561048 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10437 13:40:12.561234 [login-action] Waiting for messages, (timeout 00:02:54)
10438 13:40:12.561338 Waiting using forced prompt support (timeout 00:01:27)
10439 13:40:12.579735 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10440 13:40:12.583321 [ 0.000000] random: crng init done
10441 13:40:12.590024 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10442 13:40:12.593094 [ 0.000000] efi: UEFI not found.
10443 13:40:12.599827 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10444 13:40:12.609870 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10445 13:40:12.619610 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10446 13:40:12.626281 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10447 13:40:12.633012 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10448 13:40:12.639297 [ 0.000000] printk: bootconsole [mtk8250] enabled
10449 13:40:12.645903 [ 0.000000] NUMA: No NUMA configuration found
10450 13:40:12.652752 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10451 13:40:12.659370 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10452 13:40:12.659506 [ 0.000000] Zone ranges:
10453 13:40:12.666093 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10454 13:40:12.669065 [ 0.000000] DMA32 empty
10455 13:40:12.675479 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10456 13:40:12.678743 [ 0.000000] Movable zone start for each node
10457 13:40:12.682147 [ 0.000000] Early memory node ranges
10458 13:40:12.689266 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10459 13:40:12.695328 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10460 13:40:12.702159 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10461 13:40:12.708908 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10462 13:40:12.715109 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10463 13:40:12.721962 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10464 13:40:12.778315 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10465 13:40:12.784819 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10466 13:40:12.791329 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10467 13:40:12.794855 [ 0.000000] psci: probing for conduit method from DT.
10468 13:40:12.801576 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10469 13:40:12.804997 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10470 13:40:12.811103 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10471 13:40:12.814837 [ 0.000000] psci: SMC Calling Convention v1.2
10472 13:40:12.821144 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10473 13:40:12.824763 [ 0.000000] Detected VIPT I-cache on CPU0
10474 13:40:12.831470 [ 0.000000] CPU features: detected: GIC system register CPU interface
10475 13:40:12.838097 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10476 13:40:12.844753 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10477 13:40:12.850897 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10478 13:40:12.860834 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10479 13:40:12.867219 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10480 13:40:12.871013 [ 0.000000] alternatives: applying boot alternatives
10481 13:40:12.877250 [ 0.000000] Fallback order for Node 0: 0
10482 13:40:12.883720 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10483 13:40:12.887389 [ 0.000000] Policy zone: Normal
10484 13:40:12.900323 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10485 13:40:12.910394 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10486 13:40:12.922937 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10487 13:40:12.932762 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10488 13:40:12.939272 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10489 13:40:12.942449 <6>[ 0.000000] software IO TLB: area num 8.
10490 13:40:12.999897 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10491 13:40:13.149600 <6>[ 0.000000] Memory: 7904632K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 448136K reserved, 32768K cma-reserved)
10492 13:40:13.155980 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10493 13:40:13.162710 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10494 13:40:13.165738 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10495 13:40:13.172761 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10496 13:40:13.179384 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10497 13:40:13.182434 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10498 13:40:13.192723 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10499 13:40:13.198778 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10500 13:40:13.205548 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10501 13:40:13.212318 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10502 13:40:13.215853 <6>[ 0.000000] GICv3: 608 SPIs implemented
10503 13:40:13.218800 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10504 13:40:13.225415 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10505 13:40:13.228670 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10506 13:40:13.235228 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10507 13:40:13.248141 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10508 13:40:13.261319 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10509 13:40:13.267840 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10510 13:40:13.275938 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10511 13:40:13.288987 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10512 13:40:13.295985 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10513 13:40:13.302635 <6>[ 0.009174] Console: colour dummy device 80x25
10514 13:40:13.312391 <6>[ 0.013893] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10515 13:40:13.319130 <6>[ 0.024335] pid_max: default: 32768 minimum: 301
10516 13:40:13.322608 <6>[ 0.029237] LSM: Security Framework initializing
10517 13:40:13.328799 <6>[ 0.034175] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10518 13:40:13.339306 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10519 13:40:13.345491 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10520 13:40:13.352167 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10521 13:40:13.361947 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10522 13:40:13.365611 <6>[ 0.072678] cblist_init_generic: Setting shift to 3 and lim to 1.
10523 13:40:13.371993 <6>[ 0.079078] rcu: Hierarchical SRCU implementation.
10524 13:40:13.379155 <6>[ 0.084093] rcu: Max phase no-delay instances is 1000.
10525 13:40:13.385624 <6>[ 0.091111] EFI services will not be available.
10526 13:40:13.388750 <6>[ 0.096070] smp: Bringing up secondary CPUs ...
10527 13:40:13.396764 <6>[ 0.101121] Detected VIPT I-cache on CPU1
10528 13:40:13.403147 <6>[ 0.101192] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10529 13:40:13.409997 <6>[ 0.101222] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10530 13:40:13.413671 <6>[ 0.101566] Detected VIPT I-cache on CPU2
10531 13:40:13.423536 <6>[ 0.101619] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10532 13:40:13.429918 <6>[ 0.101637] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10533 13:40:13.433031 <6>[ 0.101893] Detected VIPT I-cache on CPU3
10534 13:40:13.439710 <6>[ 0.101940] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10535 13:40:13.446497 <6>[ 0.101954] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10536 13:40:13.449750 <6>[ 0.102257] CPU features: detected: Spectre-v4
10537 13:40:13.456511 <6>[ 0.102263] CPU features: detected: Spectre-BHB
10538 13:40:13.459464 <6>[ 0.102268] Detected PIPT I-cache on CPU4
10539 13:40:13.466169 <6>[ 0.102325] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10540 13:40:13.472990 <6>[ 0.102342] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10541 13:40:13.479164 <6>[ 0.102636] Detected PIPT I-cache on CPU5
10542 13:40:13.486324 <6>[ 0.102698] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10543 13:40:13.492354 <6>[ 0.102714] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10544 13:40:13.495754 <6>[ 0.102994] Detected PIPT I-cache on CPU6
10545 13:40:13.502842 <6>[ 0.103058] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10546 13:40:13.508923 <6>[ 0.103074] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10547 13:40:13.516108 <6>[ 0.103371] Detected PIPT I-cache on CPU7
10548 13:40:13.522642 <6>[ 0.103438] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10549 13:40:13.529051 <6>[ 0.103454] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10550 13:40:13.532456 <6>[ 0.103500] smp: Brought up 1 node, 8 CPUs
10551 13:40:13.538646 <6>[ 0.244908] SMP: Total of 8 processors activated.
10552 13:40:13.542376 <6>[ 0.249859] CPU features: detected: 32-bit EL0 Support
10553 13:40:13.552151 <6>[ 0.255222] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10554 13:40:13.559089 <6>[ 0.264022] CPU features: detected: Common not Private translations
10555 13:40:13.565304 <6>[ 0.270498] CPU features: detected: CRC32 instructions
10556 13:40:13.568475 <6>[ 0.275849] CPU features: detected: RCpc load-acquire (LDAPR)
10557 13:40:13.575285 <6>[ 0.281809] CPU features: detected: LSE atomic instructions
10558 13:40:13.582052 <6>[ 0.287626] CPU features: detected: Privileged Access Never
10559 13:40:13.588293 <6>[ 0.293406] CPU features: detected: RAS Extension Support
10560 13:40:13.595194 <6>[ 0.299014] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10561 13:40:13.598717 <6>[ 0.306278] CPU: All CPU(s) started at EL2
10562 13:40:13.604992 <6>[ 0.310595] alternatives: applying system-wide alternatives
10563 13:40:13.614518 <6>[ 0.321444] devtmpfs: initialized
10564 13:40:13.626634 <6>[ 0.330258] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10565 13:40:13.636498 <6>[ 0.340220] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10566 13:40:13.643616 <6>[ 0.348239] pinctrl core: initialized pinctrl subsystem
10567 13:40:13.646976 <6>[ 0.354904] DMI not present or invalid.
10568 13:40:13.653404 <6>[ 0.359312] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10569 13:40:13.663206 <6>[ 0.366095] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10570 13:40:13.669956 <6>[ 0.373677] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10571 13:40:13.679918 <6>[ 0.381892] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10572 13:40:13.683069 <6>[ 0.390138] audit: initializing netlink subsys (disabled)
10573 13:40:13.693042 <5>[ 0.395832] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10574 13:40:13.699927 <6>[ 0.396532] thermal_sys: Registered thermal governor 'step_wise'
10575 13:40:13.705889 <6>[ 0.403794] thermal_sys: Registered thermal governor 'power_allocator'
10576 13:40:13.709059 <6>[ 0.410048] cpuidle: using governor menu
10577 13:40:13.716184 <6>[ 0.421005] NET: Registered PF_QIPCRTR protocol family
10578 13:40:13.722297 <6>[ 0.426487] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10579 13:40:13.728782 <6>[ 0.433587] ASID allocator initialised with 32768 entries
10580 13:40:13.732217 <6>[ 0.440165] Serial: AMBA PL011 UART driver
10581 13:40:13.742230 <4>[ 0.448998] Trying to register duplicate clock ID: 134
10582 13:40:13.800259 <6>[ 0.510349] KASLR enabled
10583 13:40:13.814594 <6>[ 0.518004] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10584 13:40:13.821105 <6>[ 0.525018] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10585 13:40:13.827433 <6>[ 0.531506] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10586 13:40:13.834361 <6>[ 0.538511] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10587 13:40:13.840966 <6>[ 0.544999] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10588 13:40:13.847543 <6>[ 0.552005] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10589 13:40:13.854258 <6>[ 0.558490] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10590 13:40:13.860889 <6>[ 0.565492] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10591 13:40:13.864387 <6>[ 0.572936] ACPI: Interpreter disabled.
10592 13:40:13.872301 <6>[ 0.579375] iommu: Default domain type: Translated
10593 13:40:13.879171 <6>[ 0.584486] iommu: DMA domain TLB invalidation policy: strict mode
10594 13:40:13.882513 <5>[ 0.591142] SCSI subsystem initialized
10595 13:40:13.888963 <6>[ 0.595386] usbcore: registered new interface driver usbfs
10596 13:40:13.895602 <6>[ 0.601116] usbcore: registered new interface driver hub
10597 13:40:13.898776 <6>[ 0.606667] usbcore: registered new device driver usb
10598 13:40:13.906237 <6>[ 0.612776] pps_core: LinuxPPS API ver. 1 registered
10599 13:40:13.916602 <6>[ 0.617968] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10600 13:40:13.918765 <6>[ 0.627311] PTP clock support registered
10601 13:40:13.922475 <6>[ 0.631553] EDAC MC: Ver: 3.0.0
10602 13:40:13.929659 <6>[ 0.636728] FPGA manager framework
10603 13:40:13.936448 <6>[ 0.640402] Advanced Linux Sound Architecture Driver Initialized.
10604 13:40:13.939549 <6>[ 0.647167] vgaarb: loaded
10605 13:40:13.946179 <6>[ 0.650314] clocksource: Switched to clocksource arch_sys_counter
10606 13:40:13.949797 <5>[ 0.656758] VFS: Disk quotas dquot_6.6.0
10607 13:40:13.956547 <6>[ 0.660946] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10608 13:40:13.959543 <6>[ 0.668135] pnp: PnP ACPI: disabled
10609 13:40:13.968167 <6>[ 0.674854] NET: Registered PF_INET protocol family
10610 13:40:13.978301 <6>[ 0.680450] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10611 13:40:13.989136 <6>[ 0.692767] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10612 13:40:13.999025 <6>[ 0.701583] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10613 13:40:14.005875 <6>[ 0.709552] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10614 13:40:14.015819 <6>[ 0.718251] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10615 13:40:14.022301 <6>[ 0.727991] TCP: Hash tables configured (established 65536 bind 65536)
10616 13:40:14.028819 <6>[ 0.734792] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10617 13:40:14.038968 <6>[ 0.741987] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10618 13:40:14.045212 <6>[ 0.749691] NET: Registered PF_UNIX/PF_LOCAL protocol family
10619 13:40:14.048356 <6>[ 0.755796] RPC: Registered named UNIX socket transport module.
10620 13:40:14.055042 <6>[ 0.761947] RPC: Registered udp transport module.
10621 13:40:14.058623 <6>[ 0.766879] RPC: Registered tcp transport module.
10622 13:40:14.065227 <6>[ 0.771810] RPC: Registered tcp NFSv4.1 backchannel transport module.
10623 13:40:14.071865 <6>[ 0.778474] PCI: CLS 0 bytes, default 64
10624 13:40:14.074801 <6>[ 0.782880] Unpacking initramfs...
10625 13:40:14.091561 <6>[ 0.794964] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10626 13:40:14.101371 <6>[ 0.803624] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10627 13:40:14.104917 <6>[ 0.812463] kvm [1]: IPA Size Limit: 40 bits
10628 13:40:14.111122 <6>[ 0.816992] kvm [1]: GICv3: no GICV resource entry
10629 13:40:14.114395 <6>[ 0.822014] kvm [1]: disabling GICv2 emulation
10630 13:40:14.121209 <6>[ 0.826698] kvm [1]: GIC system register CPU interface enabled
10631 13:40:14.127685 <6>[ 0.834358] kvm [1]: vgic interrupt IRQ18
10632 13:40:14.130961 <6>[ 0.838734] kvm [1]: VHE mode initialized successfully
10633 13:40:14.138673 <5>[ 0.845128] Initialise system trusted keyrings
10634 13:40:14.144825 <6>[ 0.849908] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10635 13:40:14.153542 <6>[ 0.859889] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10636 13:40:14.160102 <5>[ 0.866255] NFS: Registering the id_resolver key type
10637 13:40:14.163234 <5>[ 0.871555] Key type id_resolver registered
10638 13:40:14.169815 <5>[ 0.875972] Key type id_legacy registered
10639 13:40:14.176035 <6>[ 0.880250] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10640 13:40:14.182930 <6>[ 0.887170] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10641 13:40:14.189174 <6>[ 0.894905] 9p: Installing v9fs 9p2000 file system support
10642 13:40:14.225343 <5>[ 0.932414] Key type asymmetric registered
10643 13:40:14.228811 <5>[ 0.936741] Asymmetric key parser 'x509' registered
10644 13:40:14.239192 <6>[ 0.941876] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10645 13:40:14.242066 <6>[ 0.949505] io scheduler mq-deadline registered
10646 13:40:14.245221 <6>[ 0.954272] io scheduler kyber registered
10647 13:40:14.264452 <6>[ 0.971333] EINJ: ACPI disabled.
10648 13:40:14.297049 <4>[ 0.997497] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10649 13:40:14.306945 <4>[ 1.008128] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 13:40:14.321991 <6>[ 1.029078] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10651 13:40:14.330358 <6>[ 1.037096] printk: console [ttyS0] disabled
10652 13:40:14.358088 <6>[ 1.061733] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10653 13:40:14.364906 <6>[ 1.071211] printk: console [ttyS0] enabled
10654 13:40:14.368141 <6>[ 1.071211] printk: console [ttyS0] enabled
10655 13:40:14.374911 <6>[ 1.080106] printk: bootconsole [mtk8250] disabled
10656 13:40:14.378023 <6>[ 1.080106] printk: bootconsole [mtk8250] disabled
10657 13:40:14.384289 <6>[ 1.091405] SuperH (H)SCI(F) driver initialized
10658 13:40:14.388065 <6>[ 1.096673] msm_serial: driver initialized
10659 13:40:14.402338 <6>[ 1.105635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10660 13:40:14.412353 <6>[ 1.114189] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10661 13:40:14.418617 <6>[ 1.122733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10662 13:40:14.428511 <6>[ 1.131361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10663 13:40:14.438613 <6>[ 1.140068] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10664 13:40:14.445431 <6>[ 1.148797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10665 13:40:14.455241 <6>[ 1.157337] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10666 13:40:14.461922 <6>[ 1.166140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10667 13:40:14.471850 <6>[ 1.174684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10668 13:40:14.480331 <6>[ 1.190238] loop: module loaded
10669 13:40:14.489322 <6>[ 1.196343] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10670 13:40:14.512568 <4>[ 1.219814] mtk-pmic-keys: Failed to locate of_node [id: -1]
10671 13:40:14.520069 <6>[ 1.226875] megasas: 07.719.03.00-rc1
10672 13:40:14.529981 <6>[ 1.236667] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10673 13:40:14.539056 <6>[ 1.245690] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10674 13:40:14.555423 <6>[ 1.262278] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10675 13:40:14.611099 <6>[ 1.311666] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10676 13:40:16.762558 <6>[ 3.469601] Freeing initrd memory: 59552K
10677 13:40:16.774047 <6>[ 3.481302] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10678 13:40:16.784951 <6>[ 3.492438] tun: Universal TUN/TAP device driver, 1.6
10679 13:40:16.788318 <6>[ 3.498537] thunder_xcv, ver 1.0
10680 13:40:16.792120 <6>[ 3.502033] thunder_bgx, ver 1.0
10681 13:40:16.795121 <6>[ 3.505529] nicpf, ver 1.0
10682 13:40:16.805731 <6>[ 3.509548] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10683 13:40:16.808866 <6>[ 3.517024] hns3: Copyright (c) 2017 Huawei Corporation.
10684 13:40:16.815821 <6>[ 3.522613] hclge is initializing
10685 13:40:16.819186 <6>[ 3.526190] e1000: Intel(R) PRO/1000 Network Driver
10686 13:40:16.825471 <6>[ 3.531320] e1000: Copyright (c) 1999-2006 Intel Corporation.
10687 13:40:16.829108 <6>[ 3.537333] e1000e: Intel(R) PRO/1000 Network Driver
10688 13:40:16.835653 <6>[ 3.542549] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10689 13:40:16.842502 <6>[ 3.548734] igb: Intel(R) Gigabit Ethernet Network Driver
10690 13:40:16.848745 <6>[ 3.554384] igb: Copyright (c) 2007-2014 Intel Corporation.
10691 13:40:16.855548 <6>[ 3.560221] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10692 13:40:16.862086 <6>[ 3.566738] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10693 13:40:16.865037 <6>[ 3.573202] sky2: driver version 1.30
10694 13:40:16.871914 <6>[ 3.578122] usbcore: registered new device driver r8152-cfgselector
10695 13:40:16.878496 <6>[ 3.584657] usbcore: registered new interface driver r8152
10696 13:40:16.884854 <6>[ 3.590486] VFIO - User Level meta-driver version: 0.3
10697 13:40:16.891723 <6>[ 3.598708] usbcore: registered new interface driver usb-storage
10698 13:40:16.898265 <6>[ 3.605156] usbcore: registered new device driver onboard-usb-hub
10699 13:40:16.907017 <6>[ 3.614298] mt6397-rtc mt6359-rtc: registered as rtc0
10700 13:40:16.917001 <6>[ 3.619764] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:40:17 UTC (1716903617)
10701 13:40:16.920167 <6>[ 3.629330] i2c_dev: i2c /dev entries driver
10702 13:40:16.937514 <6>[ 3.641164] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10703 13:40:16.944238 <4>[ 3.649896] cpu cpu0: supply cpu not found, using dummy regulator
10704 13:40:16.950698 <4>[ 3.656331] cpu cpu1: supply cpu not found, using dummy regulator
10705 13:40:16.956966 <4>[ 3.662733] cpu cpu2: supply cpu not found, using dummy regulator
10706 13:40:16.964111 <4>[ 3.669134] cpu cpu3: supply cpu not found, using dummy regulator
10707 13:40:16.970402 <4>[ 3.675532] cpu cpu4: supply cpu not found, using dummy regulator
10708 13:40:16.977132 <4>[ 3.681927] cpu cpu5: supply cpu not found, using dummy regulator
10709 13:40:16.983904 <4>[ 3.688337] cpu cpu6: supply cpu not found, using dummy regulator
10710 13:40:16.989967 <4>[ 3.694736] cpu cpu7: supply cpu not found, using dummy regulator
10711 13:40:17.009476 <6>[ 3.716370] cpu cpu0: EM: created perf domain
10712 13:40:17.012175 <6>[ 3.721299] cpu cpu4: EM: created perf domain
10713 13:40:17.020176 <6>[ 3.726935] sdhci: Secure Digital Host Controller Interface driver
10714 13:40:17.026396 <6>[ 3.733365] sdhci: Copyright(c) Pierre Ossman
10715 13:40:17.032755 <6>[ 3.738326] Synopsys Designware Multimedia Card Interface Driver
10716 13:40:17.039393 <6>[ 3.744977] sdhci-pltfm: SDHCI platform and OF driver helper
10717 13:40:17.042935 <6>[ 3.745034] mmc0: CQHCI version 5.10
10718 13:40:17.049663 <6>[ 3.755186] ledtrig-cpu: registered to indicate activity on CPUs
10719 13:40:17.056175 <6>[ 3.762300] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10720 13:40:17.062941 <6>[ 3.769355] usbcore: registered new interface driver usbhid
10721 13:40:17.065948 <6>[ 3.775177] usbhid: USB HID core driver
10722 13:40:17.073002 <6>[ 3.779388] spi_master spi0: will run message pump with realtime priority
10723 13:40:17.122248 <6>[ 3.822432] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10724 13:40:17.141609 <6>[ 3.838164] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10725 13:40:17.144935 <6>[ 3.851737] mmc0: Command Queue Engine enabled
10726 13:40:17.151454 <6>[ 3.853815] cros-ec-spi spi0.0: Chrome EC device registered
10727 13:40:17.158166 <6>[ 3.856461] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10728 13:40:17.161260 <6>[ 3.869708] mmcblk0: mmc0:0001 DA4128 116 GiB
10729 13:40:17.173004 <6>[ 3.876720] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10730 13:40:17.179305 <6>[ 3.881175] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10731 13:40:17.185843 <6>[ 3.887194] NET: Registered PF_PACKET protocol family
10732 13:40:17.189121 <6>[ 3.893234] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10733 13:40:17.195844 <6>[ 3.897405] 9pnet: Installing 9P2000 support
10734 13:40:17.199943 <6>[ 3.903182] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10735 13:40:17.205833 <5>[ 3.907071] Key type dns_resolver registered
10736 13:40:17.212579 <6>[ 3.912929] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10737 13:40:17.215730 <6>[ 3.917318] registered taskstats version 1
10738 13:40:17.219501 <5>[ 3.927658] Loading compiled-in X.509 certificates
10739 13:40:17.248875 <4>[ 3.949408] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10740 13:40:17.258938 <4>[ 3.960134] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10741 13:40:17.272263 <6>[ 3.979605] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10742 13:40:17.279069 <6>[ 3.986390] xhci-mtk 11200000.usb: xHCI Host Controller
10743 13:40:17.286100 <6>[ 3.991930] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10744 13:40:17.295829 <6>[ 3.999789] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10745 13:40:17.302476 <6>[ 4.009235] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10746 13:40:17.309331 <6>[ 4.015448] xhci-mtk 11200000.usb: xHCI Host Controller
10747 13:40:17.316046 <6>[ 4.020941] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10748 13:40:17.322758 <6>[ 4.028603] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10749 13:40:17.328902 <6>[ 4.036272] hub 1-0:1.0: USB hub found
10750 13:40:17.332596 <6>[ 4.040297] hub 1-0:1.0: 1 port detected
10751 13:40:17.342204 <6>[ 4.044580] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10752 13:40:17.345494 <6>[ 4.053247] hub 2-0:1.0: USB hub found
10753 13:40:17.349096 <6>[ 4.057269] hub 2-0:1.0: 1 port detected
10754 13:40:17.357124 <6>[ 4.064279] mtk-msdc 11f70000.mmc: Got CD GPIO
10755 13:40:17.374966 <6>[ 4.078802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10756 13:40:17.381648 <6>[ 4.086828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10757 13:40:17.391574 <4>[ 4.094733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10758 13:40:17.401371 <6>[ 4.104269] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10759 13:40:17.408276 <6>[ 4.112350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10760 13:40:17.414995 <6>[ 4.120372] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10761 13:40:17.424947 <6>[ 4.128285] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10762 13:40:17.431491 <6>[ 4.136102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10763 13:40:17.441216 <6>[ 4.143921] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10764 13:40:17.451401 <6>[ 4.153887] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10765 13:40:17.457360 <6>[ 4.162241] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10766 13:40:17.467309 <6>[ 4.170589] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10767 13:40:17.474086 <6>[ 4.178928] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10768 13:40:17.484268 <6>[ 4.187266] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10769 13:40:17.490739 <6>[ 4.195603] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10770 13:40:17.500440 <6>[ 4.203941] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10771 13:40:17.507011 <6>[ 4.212278] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10772 13:40:17.516910 <6>[ 4.220616] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10773 13:40:17.523683 <6>[ 4.228954] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10774 13:40:17.533616 <6>[ 4.237294] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10775 13:40:17.540085 <6>[ 4.245632] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10776 13:40:17.549841 <6>[ 4.253969] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10777 13:40:17.560065 <6>[ 4.262307] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10778 13:40:17.566757 <6>[ 4.270644] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10779 13:40:17.573347 <6>[ 4.279371] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10780 13:40:17.580014 <6>[ 4.286534] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10781 13:40:17.586708 <6>[ 4.293294] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10782 13:40:17.593024 <6>[ 4.300048] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10783 13:40:17.602950 <6>[ 4.306985] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10784 13:40:17.609713 <6>[ 4.313845] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10785 13:40:17.619852 <6>[ 4.322981] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10786 13:40:17.629429 <6>[ 4.332101] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10787 13:40:17.639246 <6>[ 4.341394] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10788 13:40:17.649516 <6>[ 4.350861] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10789 13:40:17.656317 <6>[ 4.360327] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10790 13:40:17.665686 <6>[ 4.369447] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10791 13:40:17.676181 <6>[ 4.378913] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10792 13:40:17.686156 <6>[ 4.388033] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10793 13:40:17.695681 <6>[ 4.397327] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10794 13:40:17.705558 <6>[ 4.407487] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10795 13:40:17.715127 <6>[ 4.419134] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10796 13:40:17.762334 <6>[ 4.466571] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10797 13:40:17.915122 <6>[ 4.622588] hub 1-1:1.0: USB hub found
10798 13:40:17.918884 <6>[ 4.626951] hub 1-1:1.0: 4 ports detected
10799 13:40:17.926823 <6>[ 4.633735] hub 1-1:1.0: USB hub found
10800 13:40:17.929692 <6>[ 4.638074] hub 1-1:1.0: 4 ports detected
10801 13:40:18.042947 <6>[ 4.746953] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10802 13:40:18.069330 <6>[ 4.776511] hub 2-1:1.0: USB hub found
10803 13:40:18.072353 <6>[ 4.781015] hub 2-1:1.0: 3 ports detected
10804 13:40:18.082079 <6>[ 4.789298] hub 2-1:1.0: USB hub found
10805 13:40:18.085337 <6>[ 4.793816] hub 2-1:1.0: 3 ports detected
10806 13:40:18.258748 <6>[ 4.962680] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10807 13:40:18.391226 <6>[ 5.098414] hub 1-1.4:1.0: USB hub found
10808 13:40:18.394442 <6>[ 5.103076] hub 1-1.4:1.0: 2 ports detected
10809 13:40:18.403683 <6>[ 5.110979] hub 1-1.4:1.0: USB hub found
10810 13:40:18.407039 <6>[ 5.115499] hub 1-1.4:1.0: 2 ports detected
10811 13:40:18.474928 <6>[ 5.178715] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10812 13:40:18.583574 <6>[ 5.287259] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10813 13:40:18.619731 <4>[ 5.323376] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10814 13:40:18.628822 <4>[ 5.332444] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10815 13:40:18.664723 <6>[ 5.372125] r8152 2-1.3:1.0 eth0: v1.12.13
10816 13:40:18.702481 <6>[ 5.406637] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10817 13:40:18.894650 <6>[ 5.598599] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10818 13:40:20.355318 <6>[ 7.062765] r8152 2-1.3:1.0 eth0: carrier on
10819 13:40:22.858378 <5>[ 7.086427] Sending DHCP requests .., OK
10820 13:40:22.865591 <6>[ 9.570801] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10821 13:40:22.868480 <6>[ 9.579102] IP-Config: Complete:
10822 13:40:22.882096 <6>[ 9.582600] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10823 13:40:22.888357 <6>[ 9.593323] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10824 13:40:22.895024 <6>[ 9.601943] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10825 13:40:22.901925 <6>[ 9.601952] nameserver0=192.168.201.1
10826 13:40:22.905060 <6>[ 9.614130] clk: Disabling unused clocks
10827 13:40:22.908833 <6>[ 9.619654] ALSA device list:
10828 13:40:22.914818 <6>[ 9.622913] No soundcards found.
10829 13:40:22.923091 <6>[ 9.630623] Freeing unused kernel memory: 8512K
10830 13:40:22.925891 <6>[ 9.635658] Run /init as init process
10831 13:40:22.960110 <6>[ 9.668140] NET: Registered PF_INET6 protocol family
10832 13:40:22.966994 <6>[ 9.675009] Segment Routing with IPv6
10833 13:40:22.970326 <6>[ 9.678967] In-situ OAM (IOAM) with IPv6
10834 13:40:23.013385 <30>[ 9.694966] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10835 13:40:23.020221 <30>[ 9.728100] systemd[1]: Detected architecture arm64.
10836 13:40:23.020361
10837 13:40:23.026981 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10838 13:40:23.027135
10839 13:40:23.038623 <30>[ 9.746615] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10840 13:40:23.157901 <30>[ 9.862370] systemd[1]: Queued start job for default target graphical.target.
10841 13:40:23.199501 <30>[ 9.904400] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10842 13:40:23.206372 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10843 13:40:23.226660 <30>[ 9.931347] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10844 13:40:23.236881 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10845 13:40:23.254878 <30>[ 9.959541] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10846 13:40:23.265052 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10847 13:40:23.282698 <30>[ 9.987094] systemd[1]: Created slice user.slice - User and Session Slice.
10848 13:40:23.288861 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10849 13:40:23.309099 <30>[ 10.010615] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10850 13:40:23.315726 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10851 13:40:23.337734 <30>[ 10.039054] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10852 13:40:23.344977 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10853 13:40:23.372106 <30>[ 10.067010] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10854 13:40:23.382684 <30>[ 10.086919] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10855 13:40:23.389046 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10856 13:40:23.406161 <30>[ 10.110538] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10857 13:40:23.412873 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10858 13:40:23.430314 <30>[ 10.134622] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10859 13:40:23.440102 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10860 13:40:23.454687 <30>[ 10.162701] systemd[1]: Reached target paths.target - Path Units.
10861 13:40:23.464725 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10862 13:40:23.482225 <30>[ 10.186619] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10863 13:40:23.488453 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10864 13:40:23.502645 <30>[ 10.210597] systemd[1]: Reached target slices.target - Slice Units.
10865 13:40:23.512588 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10866 13:40:23.527136 <30>[ 10.235089] systemd[1]: Reached target swap.target - Swaps.
10867 13:40:23.533875 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10868 13:40:23.554127 <30>[ 10.258709] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10869 13:40:23.564324 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10870 13:40:23.582915 <30>[ 10.287570] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10871 13:40:23.593038 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10872 13:40:23.612254 <30>[ 10.316870] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10873 13:40:23.622328 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10874 13:40:23.638799 <30>[ 10.343409] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10875 13:40:23.649085 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10876 13:40:23.666820 <30>[ 10.371204] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10877 13:40:23.673184 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10878 13:40:23.690585 <30>[ 10.395256] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10879 13:40:23.700249 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10880 13:40:23.718299 <30>[ 10.423089] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10881 13:40:23.728605 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10882 13:40:23.769951 <30>[ 10.474763] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10883 13:40:23.776874 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10884 13:40:23.796050 <30>[ 10.500500] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10885 13:40:23.802825 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10886 13:40:23.824736 <30>[ 10.529412] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10887 13:40:23.831229 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10888 13:40:23.856474 <30>[ 10.554814] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10889 13:40:23.890679 <30>[ 10.595129] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10890 13:40:23.900335 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10891 13:40:23.922991 <30>[ 10.627666] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10892 13:40:23.929800 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10893 13:40:23.955419 <30>[ 10.659934] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10894 13:40:23.965166 Startin<6>[ 10.669313] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10895 13:40:23.972042 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10896 13:40:23.999244 <30>[ 10.704160] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10897 13:40:24.006029 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10898 13:40:24.031185 <30>[ 10.736036] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10899 13:40:24.040935 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10900 13:40:24.098461 <30>[ 10.802969] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10901 13:40:24.104728 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10902 13:40:24.134801 <30>[ 10.839381] systemd[1]: Starting systemd-journald.service - Journal Service...
10903 13:40:24.141526 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10904 13:40:24.160592 <30>[ 10.865223] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10905 13:40:24.166883 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10906 13:40:24.194443 <30>[ 10.895912] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10907 13:40:24.201175 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10908 13:40:24.226531 <30>[ 10.931516] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10909 13:40:24.236476 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10910 13:40:24.261992 <30>[ 10.966454] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10911 13:40:24.271518 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10912 13:40:24.294828 <30>[ 10.999806] systemd[1]: Started systemd-journald.service - Journal Service.
10913 13:40:24.301640 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10914 13:40:24.328617 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10915 13:40:24.351419 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10916 13:40:24.370636 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10917 13:40:24.390607 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10918 13:40:24.411564 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10919 13:40:24.430783 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10920 13:40:24.450902 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10921 13:40:24.471568 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10922 13:40:24.491604 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10923 13:40:24.516679 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10924 13:40:24.539755 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10925 13:40:24.564302 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10926 13:40:24.582294 See 'systemctl status systemd-remount-fs.service' for details.
10927 13:40:24.603897 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10928 13:40:24.624395 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10929 13:40:24.682426 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10930 13:40:24.706864 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10931 13:40:24.726401 <46>[ 11.431010] systemd-journald[191]: Received client request to flush runtime journal.
10932 13:40:24.732517 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10933 13:40:24.758054 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10934 13:40:24.779828 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10935 13:40:24.807524 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10936 13:40:24.827023 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10937 13:40:24.847055 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10938 13:40:24.867498 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10939 13:40:24.887393 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10940 13:40:24.946726 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10941 13:40:24.982468 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10942 13:40:25.002722 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10943 13:40:25.022186 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10944 13:40:25.061740 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10945 13:40:25.085767 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10946 13:40:25.111351 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10947 13:40:25.133256 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10948 13:40:25.200901 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10949 13:40:25.351942 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10950 13:40:25.376268 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10951 13:40:25.408296 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10952 13:40:25.449081 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10953 13:40:25.466538 <46>[ 12.174674] systemd-journald[191]: Time jumped backwards, rotating.
10954 13:40:25.481928 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10955 13:40:25.492504 <3>[ 12.197092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10956 13:40:25.502099 <3>[ 12.205669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10957 13:40:25.508855 <3>[ 12.214207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10958 13:40:25.515686 <6>[ 12.222247] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10959 13:40:25.525357 [[0;32m OK [<3>[ 12.222469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 13:40:25.535479 0m] Reached targ<6>[ 12.230177] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10961 13:40:25.545400 et [0;1;39mtime<3>[ 12.239336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 13:40:25.555208 <3>[ 12.239341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 13:40:25.561425 <3>[ 12.239350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 13:40:25.571559 <6>[ 12.249424] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10965 13:40:25.578446 <4>[ 12.251400] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10966 13:40:25.588197 -set.target[0m <4>[ 12.258801] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10967 13:40:25.594525 <3>[ 12.259100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10968 13:40:25.598096 <6>[ 12.260274] mc: Linux media interface: v0.10
10969 13:40:25.607770 <6>[ 12.285140] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10970 13:40:25.614516 <3>[ 12.291102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10971 13:40:25.620998 - System Time Se<6>[ 12.293179] videodev: Linux video capture interface: v2.00
10972 13:40:25.621207 t.
10973 13:40:25.630925 <3>[ 12.335247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 13:40:25.637789 <3>[ 12.343748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 13:40:25.647260 <3>[ 12.351828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 13:40:25.657263 <6>[ 12.359270] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10977 13:40:25.664768 <3>[ 12.359949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 13:40:25.674749 <4>[ 12.361167] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10979 13:40:25.677673 <4>[ 12.361167] Fallback method does not support PEC.
10980 13:40:25.688016 <6>[ 12.370292] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10981 13:40:25.697495 <6>[ 12.374246] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10982 13:40:25.704576 <3>[ 12.376173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 13:40:25.714440 <3>[ 12.378054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 13:40:25.721071 <3>[ 12.378056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 13:40:25.730439 <3>[ 12.378060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10986 13:40:25.737550 <3>[ 12.378063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10987 13:40:25.743710 <6>[ 12.387711] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10988 13:40:25.750481 <6>[ 12.387718] pci_bus 0000:00: root bus resource [bus 00-ff]
10989 13:40:25.757013 <6>[ 12.387721] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10990 13:40:25.767061 <6>[ 12.387723] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10991 13:40:25.774047 <6>[ 12.387752] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10992 13:40:25.780654 <6>[ 12.387765] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10993 13:40:25.787462 <6>[ 12.387835] pci 0000:00:00.0: supports D1 D2
10994 13:40:25.794045 <6>[ 12.387837] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10995 13:40:25.801101 <6>[ 12.388832] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10996 13:40:25.808235 <6>[ 12.388906] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10997 13:40:25.815222 <6>[ 12.388931] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10998 13:40:25.821709 <6>[ 12.388949] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10999 13:40:25.828673 <6>[ 12.388965] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11000 13:40:25.835688 <6>[ 12.389074] pci 0000:01:00.0: supports D1 D2
11001 13:40:25.842204 <6>[ 12.389075] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11002 13:40:25.849331 <6>[ 12.398394] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11003 13:40:25.855591 <3>[ 12.400761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11004 13:40:25.866109 <6>[ 12.410061] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11005 13:40:25.872923 <6>[ 12.412088] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11006 13:40:25.876211 <6>[ 12.414510] remoteproc remoteproc0: scp is available
11007 13:40:25.882981 <6>[ 12.414611] remoteproc remoteproc0: powering up scp
11008 13:40:25.890505 <6>[ 12.414618] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11009 13:40:25.897347 <6>[ 12.414642] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11010 13:40:25.900399 <6>[ 12.443728] Bluetooth: Core ver 2.22
11011 13:40:25.907671 <6>[ 12.451238] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11012 13:40:25.918102 <6>[ 12.451264] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11013 13:40:25.920913 <6>[ 12.458209] NET: Registered PF_BLUETOOTH protocol family
11014 13:40:25.930737 <6>[ 12.463866] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11015 13:40:25.937287 <6>[ 12.464717] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11016 13:40:25.947933 <6>[ 12.465819] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11017 13:40:25.955111 <6>[ 12.465916] usbcore: registered new interface driver uvcvideo
11018 13:40:25.961319 <6>[ 12.470981] Bluetooth: HCI device and connection manager initialized
11019 13:40:25.971544 <6>[ 12.480894] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11020 13:40:25.974710 <6>[ 12.487155] Bluetooth: HCI socket layer initialized
11021 13:40:25.982286 <6>[ 12.487826] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11022 13:40:25.985339 <6>[ 12.494618] pci 0000:00:00.0: PCI bridge to [bus 01]
11023 13:40:25.995110 <3>[ 12.497691] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 13:40:26.002636 <6>[ 12.499127] Bluetooth: L2CAP socket layer initialized
11025 13:40:26.009584 <3>[ 12.499645] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11026 13:40:26.016397 <6>[ 12.505988] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11027 13:40:26.022923 <6>[ 12.514246] Bluetooth: SCO socket layer initialized
11028 13:40:26.026896 <6>[ 12.520616] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11029 13:40:26.036779 <3>[ 12.530060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 13:40:26.046978 <3>[ 12.530915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11031 13:40:26.050694 <6>[ 12.536302] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11032 13:40:26.060595 <6>[ 12.541865] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11033 13:40:26.067120 <6>[ 12.541991] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11034 13:40:26.073747 <6>[ 12.541998] remoteproc remoteproc0: remote processor scp is now up
11035 13:40:26.083361 <3>[ 12.545340] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 13:40:26.086544 <6>[ 12.548743] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11037 13:40:26.096568 <6>[ 12.549492] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11038 13:40:26.103526 <6>[ 12.551562] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11039 13:40:26.110092 <6>[ 12.570447] usbcore: registered new interface driver btusb
11040 13:40:26.120038 <4>[ 12.571415] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11041 13:40:26.126442 <3>[ 12.571428] Bluetooth: hci0: Failed to load firmware file (-2)
11042 13:40:26.132999 <3>[ 12.571432] Bluetooth: hci0: Failed to set up firmware (-2)
11043 13:40:26.142704 <4>[ 12.571436] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11044 13:40:26.152933 <3>[ 12.577459] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 13:40:26.159276 <5>[ 12.598080] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11046 13:40:26.169548 <3>[ 12.598479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 13:40:26.179407 <3>[ 12.619911] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 13:40:26.185973 <5>[ 12.636304] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11049 13:40:26.192499 <3>[ 12.665747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11050 13:40:26.202357 <5>[ 12.669016] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11051 13:40:26.212669 <4>[ 12.915258] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11052 13:40:26.215726 <6>[ 12.924177] cfg80211: failed to load regulatory.db
11053 13:40:26.222174 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11054 13:40:26.245402 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11055 13:40:26.260605 <6>[ 12.965710] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11056 13:40:26.267138 <6>[ 12.973265] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11057 13:40:26.274075 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11058 13:40:26.294051 [[0;32m OK [<6>[ 13.000147] mt7921e 0000:01:00.0: ASIC revision: 79610010
11059 13:40:26.300716 0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11060 13:40:26.318767 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11061 13:40:26.337904 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11062 13:40:26.357813 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11063 13:40:26.374505 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11064 13:40:26.395736 [[0;32m OK [0m] Reached targ<6>[ 13.098722] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11065 13:40:26.395880 <6>[ 13.098722]
11066 13:40:26.402086 et [0;1;39msockets.target[0m - Socket Units.
11067 13:40:26.418353 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11068 13:40:26.434307 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11069 13:40:26.482924 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11070 13:40:26.510588 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11071 13:40:26.532715 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11072 13:40:26.551092 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11073 13:40:26.592827 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11074 13:40:26.651378 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11075 13:40:26.663680 <6>[ 13.368392] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11076 13:40:26.699022 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11077 13:40:26.717971 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11078 13:40:26.766816 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11079 13:40:26.787730 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11080 13:40:26.806487 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11081 13:40:26.828486 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11082 13:40:26.846931 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11083 13:40:26.891143 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11084 13:40:26.922201 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11085 13:40:26.951616
11086 13:40:26.954725 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11087 13:40:26.954809
11088 13:40:26.957952 debian-bookworm-arm64 login: root (automatic login)
11089 13:40:26.958045
11090 13:40:26.972966 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11091 13:40:26.973115
11092 13:40:26.979673 The programs included with the Debian GNU/Linux system are free software;
11093 13:40:26.986448 the exact distribution terms for each program are described in the
11094 13:40:26.989590 individual files in /usr/share/doc/*/copyright.
11095 13:40:26.989676
11096 13:40:26.996092 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11097 13:40:26.999499 permitted by applicable law.
11098 13:40:26.999913 Matched prompt #10: / #
11100 13:40:27.000117 Setting prompt string to ['/ #']
11101 13:40:27.000207 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11103 13:40:27.000502 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11104 13:40:27.000653 start: 2.2.6 expect-shell-connection (timeout 00:02:40) [common]
11105 13:40:27.000725 Setting prompt string to ['/ #']
11106 13:40:27.000817 Forcing a shell prompt, looking for ['/ #']
11108 13:40:27.051038 / #
11109 13:40:27.051250 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11110 13:40:27.051378 Waiting using forced prompt support (timeout 00:02:30)
11111 13:40:27.056299
11112 13:40:27.056636 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11113 13:40:27.056732 start: 2.2.7 export-device-env (timeout 00:02:40) [common]
11114 13:40:27.056822 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11115 13:40:27.056907 end: 2.2 depthcharge-retry (duration 00:02:20) [common]
11116 13:40:27.056988 end: 2 depthcharge-action (duration 00:02:20) [common]
11117 13:40:27.057074 start: 3 lava-test-retry (timeout 00:07:13) [common]
11118 13:40:27.057155 start: 3.1 lava-test-shell (timeout 00:07:13) [common]
11119 13:40:27.057282 Using namespace: common
11121 13:40:27.157661 / # #
11122 13:40:27.157849 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11123 13:40:27.163403 #
11124 13:40:27.163691 Using /lava-14063039
11126 13:40:27.264044 / # export SHELL=/bin/sh
11127 13:40:27.269763 export SHELL=/bin/sh
11129 13:40:27.370342 / # . /lava-14063039/environment
11130 13:40:27.375494 . /lava-14063039/environment
11132 13:40:27.476051 / # /lava-14063039/bin/lava-test-runner /lava-14063039/0
11133 13:40:27.476254 Test shell timeout: 10s (minimum of the action and connection timeout)
11134 13:40:27.481386 /lava-14063039/bin/lava-test-runner /lava-14063039/0
11135 13:40:27.512603 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 14.219709] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14063039_1.5.2.3.1>
11136 13:40:27.512916 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14063039_1.5.2.3.1
11137 13:40:27.512997 Starting test lava.0_igt-gpu-panfrost (14063039_1.5.2.3.1)
11138 13:40:27.513079 Skipping test definition patterns.
11139 13:40:27.516129 nfrost
11140 13:40:27.522273 + cd /lava-14063039/0/tests/0_igt-gpu-pa<6>[ 14.230830] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11141 13:40:27.526135 nfrost
11142 13:40:27.526224 + cat uuid
11143 13:40:27.529164 + UUID=14063039_1.5.2.3.1
11144 13:40:27.529259 + set +x
11145 13:40:27.538767 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11146 13:40:27.548355 <8>[ 14.256535] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11147 13:40:27.548657 Received signal: <TESTSET> START panfrost_gem_new
11148 13:40:27.548737 Starting test_set panfrost_gem_new
11149 13:40:27.568403 <14>[ 14.276984] [IGT] panfrost_gem_new: executing
11150 13:40:27.578334 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.284533] [IGT] panfrost_gem_new: exiting, ret=77
11151 13:40:27.578453 .91-cip21 aarch64)
11152 13:40:27.592006 Using IGT_SRANDOM=1716903627 for randomisati<8>[ 14.296204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11153 13:40:27.592129 on
11154 13:40:27.592370 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11156 13:40:27.598246 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11157 13:40:27.601485 Test requirement: !(fd<0)
11158 13:40:27.608771 No known gpu found for chipset flags 0x32 (panf<14>[ 14.317708] [IGT] panfrost_gem_new: executing
11159 13:40:27.608867 rost)
11160 13:40:27.618032 Last errno: 2, No such fi<14>[ 14.324797] [IGT] panfrost_gem_new: exiting, ret=77
11161 13:40:27.618122 le or directory
11162 13:40:27.621780 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11163 13:40:27.628200 IG<8>[ 14.335194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11164 13:40:27.628459 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11166 13:40:27.634788 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11167 13:40:27.638070 Using IGT_SRANDOM=1716903627 for randomisation
11168 13:40:27.648255 Test requirement not met in function drm_open_<14>[ 14.355612] [IGT] panfrost_gem_new: executing
11169 13:40:27.654682 driver, file ../lib/drmtest.c:69<14>[ 14.363698] [IGT] panfrost_gem_new: exiting, ret=77
11170 13:40:27.658286 4:
11171 13:40:27.658383 Test requirement: !(fd<0)
11172 13:40:27.668379 No known gpu found for chipset fl<8>[ 14.374002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11173 13:40:27.668669 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11175 13:40:27.674664 ags 0x32 (panfro<8>[ 14.383647] <LAVA_SIGNAL_TESTSET STOP>
11176 13:40:27.674766 st)
11177 13:40:27.675028 Received signal: <TESTSET> STOP
11178 13:40:27.675122 Closing test_set panfrost_gem_new
11179 13:40:27.677770 Last errno: 2, No such file or directory
11180 13:40:27.681450 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11181 13:40:27.687659 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11182 13:40:27.698093 Using IGT_SRANDOM=1716903627 for ra<8>[ 14.404077] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11183 13:40:27.698192 ndomisation
11184 13:40:27.698431 Received signal: <TESTSET> START panfrost_get_param
11185 13:40:27.698499 Starting test_set panfrost_get_param
11186 13:40:27.704410 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11187 13:40:27.707429 Test requirement: !(fd<0)
11188 13:40:27.714383 No known gpu found for chipset flags 0<14>[ 14.424186] [IGT] panfrost_get_param: executing
11189 13:40:27.717560 x32 (panfrost)
11190 13:40:27.724495 Last errno: 2, N<14>[ 14.431397] [IGT] panfrost_get_param: exiting, ret=77
11191 13:40:27.727751 o such file or directory
11192 13:40:27.737343 [1mSubtest gem-new-zeroed: SKIP (0.00<8>[ 14.441745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11193 13:40:27.737449 0s)[0m
11194 13:40:27.737694 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11196 13:40:27.744050 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11197 13:40:27.747043 Using IGT_SRANDOM=1716903627 for randomisation
11198 13:40:27.754321 Test requirement not met in functio<14>[ 14.462526] [IGT] panfrost_get_param: executing
11199 13:40:27.764146 n drm_open_driver, file ../lib/d<14>[ 14.471005] [IGT] panfrost_get_param: exiting, ret=77
11200 13:40:27.764266 rmtest.c:694:
11201 13:40:27.766889 Test requirement: !(fd<0)
11202 13:40:27.776921 No known gpu found for<8>[ 14.481558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11203 13:40:27.777187 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11205 13:40:27.780098 chipset flags 0x32 (panfrost)
11206 13:40:27.783898 Last errno: 2, No such file or directory
11207 13:40:27.787063 [1mSubtest base-params: SKIP (0.000s)[0m
11208 13:40:27.793293 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11209 13:40:27.796905 Using IGT_SRANDOM=1716903627 for randomisation
11210 13:40:27.806769 Test requirement not met in function drm_open_driver, <14>[ 14.514207] [IGT] panfrost_get_param: executing
11211 13:40:27.810009 file ../lib/drmtest.c:694:
11212 13:40:27.816488 Test requirement: !(<14>[ 14.523599] [IGT] panfrost_get_param: exiting, ret=77
11213 13:40:27.816632 fd<0)
11214 13:40:27.819673 No known gpu found for chipset flags 0x32 (panfrost)
11215 13:40:27.829755 Las<8>[ 14.534622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11216 13:40:27.830016 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11218 13:40:27.836367 t errno: 2, No such file or dire<8>[ 14.543477] <LAVA_SIGNAL_TESTSET STOP>
11219 13:40:27.836450 ctory
11220 13:40:27.836685 Received signal: <TESTSET> STOP
11221 13:40:27.836752 Closing test_set panfrost_get_param
11222 13:40:27.839478 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11223 13:40:27.846373 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11224 13:40:27.849554 Using IGT_SRANDOM=1716903627 for randomisation
11225 13:40:27.859679 Test requirement not met in function dr<8>[ 14.565852] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11226 13:40:27.859937 Received signal: <TESTSET> START panfrost_prime
11227 13:40:27.860006 Starting test_set panfrost_prime
11228 13:40:27.862746 m_open_driver, file ../lib/drmtest.c:694:
11229 13:40:27.866500 Test requirement: !(fd<0)
11230 13:40:27.869724 No known gpu found for chipset flags 0x32 (panfrost)
11231 13:40:27.872848 Last errno: 2, No such file or directory
11232 13:40:27.879519 [1mSubtest get-bad-paddin<14>[ 14.588362] [IGT] panfrost_prime: executing
11233 13:40:27.882364 g: SKIP (0.000s)[0m
11234 13:40:27.889131 IGT-Versio<14>[ 14.595848] [IGT] panfrost_prime: exiting, ret=77
11235 13:40:27.892313 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11236 13:40:27.899567 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11238 13:40:27.902618 Using <8>[ 14.606639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11239 13:40:27.905656 IGT_SRANDOM=1716<8>[ 14.615595] <LAVA_SIGNAL_TESTSET STOP>
11240 13:40:27.905909 Received signal: <TESTSET> STOP
11241 13:40:27.905983 Closing test_set panfrost_prime
11242 13:40:27.909212 903627 for randomisation
11243 13:40:27.915673 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11244 13:40:27.919057 Test requirement: !(fd<0)
11245 13:40:27.922069 No known gpu found for chipset flags 0x32 (panfrost)
11246 13:40:27.925300 Last errno: 2, No such file or directory
11247 13:40:27.932164 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11248 13:40:27.938561 <8>[ 14.646113] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11249 13:40:27.938829 Received signal: <TESTSET> START panfrost_submit
11250 13:40:27.938902 Starting test_set panfrost_submit
11251 13:40:27.967555 <14>[ 14.675608] [IGT] panfrost_submit: executing
11252 13:40:27.976849 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.683582] [IGT] panfrost_submit: exiting, ret=77
11253 13:40:27.976976 .91-cip21 aarch64)
11254 13:40:27.983878 Using IGT_SRANDOM=1716903628 for randomisation
11255 13:40:27.990173 Test require<8>[ 14.695535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11256 13:40:27.990448 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11258 13:40:27.997028 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11259 13:40:27.997118 Test requirement: !(fd<0)
11260 13:40:28.003787 No known gpu found for chipset flags 0x32 (panfrost)
11261 13:40:28.010632 Last errn<14>[ 14.717226] [IGT] panfrost_submit: executing
11262 13:40:28.010728 o: 2, No such file or directory
11263 13:40:28.017151 <14>[ 14.724541] [IGT] panfrost_submit: exiting, ret=77
11264 13:40:28.017248
11265 13:40:28.020366 [1mSubtest pan-submit: SKIP (0.000s)[0m
11266 13:40:28.029780 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 14.735692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11267 13:40:28.030060 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11269 13:40:28.033090 (Linux: 6.1.91-cip21 aarch64)
11270 13:40:28.040037 Using IGT_SRANDOM=1716903628 for randomisation
11271 13:40:28.046410 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11272 13:40:28.050120 Test requireme<14>[ 14.759671] [IGT] panfrost_submit: executing
11273 13:40:28.053307 nt: !(fd<0)
11274 13:40:28.059523 No known gpu found <14>[ 14.767106] [IGT] panfrost_submit: exiting, ret=77
11275 13:40:28.062954 for chipset flags 0x32 (panfrost)
11276 13:40:28.072746 Last errno: 2, No such file o<8>[ 14.778105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11277 13:40:28.072862 r directory
11278 13:40:28.073126 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11280 13:40:28.079759 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11281 13:40:28.086110 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11282 13:40:28.093040 Using IGT_SRANDOM=171690<14>[ 14.800055] [IGT] panfrost_submit: executing
11283 13:40:28.093131 3628 for randomisation
11284 13:40:28.099601 Test req<14>[ 14.807836] [IGT] panfrost_submit: exiting, ret=77
11285 13:40:28.112757 uirement not met in function drm_open_driver, file ../lib/drmtes<8>[ 14.817660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11286 13:40:28.113058 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11288 13:40:28.116425 t.c:694:
11289 13:40:28.116551 Test requirement: !(fd<0)
11290 13:40:28.122506 No known gpu found for chipset flags 0x32 (panfrost)
11291 13:40:28.125938 Last errno: 2, No such file or directory
11292 13:40:28.132525 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11293 13:40:28.135898 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11294 13:40:28.142906 Using IGT_SRANDOM=1716903<14>[ 14.851742] [IGT] panfrost_submit: executing
11295 13:40:28.146089 628 for randomisation
11296 13:40:28.152392 Test requirement not met <14>[ 14.861083] [IGT] panfrost_submit: exiting, ret=77
11297 13:40:28.159484 in function drm_open_driver, file ../lib/drmtest.c:694:
11298 13:40:28.169044 Test requirement: !(fd<<8>[ 14.872363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11299 13:40:28.169157 0)
11300 13:40:28.169399 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11302 13:40:28.172275 No known gpu found for chipset flags 0x32 (panfrost)
11303 13:40:28.179061 Last errno: 2, No such file or directory
11304 13:40:28.182056 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11305 13:40:28.188749 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11306 13:40:28.192535 Using IGT_SRANDOM=1716903628 for randomisation
11307 13:40:28.198887 Test req<14>[ 14.906280] [IGT] panfrost_submit: executing
11308 13:40:28.208480 uirement not met in function drm_open_driver, fi<14>[ 14.915292] [IGT] panfrost_submit: exiting, ret=77
11309 13:40:28.208627 le ../lib/drmtest.c:694:
11310 13:40:28.211704 Test requirement: !(fd<0)
11311 13:40:28.222326 No known gp<8>[ 14.926723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11312 13:40:28.222620 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11314 13:40:28.225136 u found for chipset flags 0x32 (panfrost)
11315 13:40:28.228925 Last errno: 2, No such file or directory
11316 13:40:28.235284 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11317 13:40:28.241992 IGT-Versi<14>[ 14.949149] [IGT] panfrost_submit: executing
11318 13:40:28.248479 on: 1.28-ga44ebfe (aarch64) (Lin<14>[ 14.956290] [IGT] panfrost_submit: exiting, ret=77
11319 13:40:28.251730 ux: 6.1.91-cip21 aarch64)
11320 13:40:28.255038 Using IGT_SRANDOM=1716903628 for randomisation
11321 13:40:28.262036 Test <8>[ 14.967547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11322 13:40:28.262314 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11324 13:40:28.268162 requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11325 13:40:28.271333 Test requirement: !(fd<0)
11326 13:40:28.275046 No known gpu found for chipset flags 0x32 (panfrost)
11327 13:40:28.284537 Last errno: 2, No such file or dir<14>[ 14.991259] [IGT] panfrost_submit: executing
11328 13:40:28.284678 ectory
11329 13:40:28.291398 [1mSubtest pan-submit-e<14>[ 14.999000] [IGT] panfrost_submit: exiting, ret=77
11330 13:40:28.294593 rror-bad-out-sync: SKIP (0.000s)[0m
11331 13:40:28.304933 IGT-Version: 1.28-ga44ebfe<8>[ 15.010231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11332 13:40:28.305222 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11334 13:40:28.308051 (aarch64) (Linux: 6.1.91-cip21 aarch64)
11335 13:40:28.311110 Using IGT_SRANDOM=1716903628 for randomisation
11336 13:40:28.324782 Test requirement not met in function drm_open_driver, file ../lib/drmt<14>[ 15.031593] [IGT] panfrost_submit: executing
11337 13:40:28.324927 est.c:694:
11338 13:40:28.331527 Test requirement: !(<14>[ 15.038758] [IGT] panfrost_submit: exiting, ret=77
11339 13:40:28.331650 fd<0)
11340 13:40:28.338125 No known gpu found for chipset flags 0x32 (panfrost)
11341 13:40:28.344272 Las<8>[ 15.049764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11342 13:40:28.344613 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11344 13:40:28.351361 t errno: 2, No such file or dire<8>[ 15.059533] <LAVA_SIGNAL_TESTSET STOP>
11345 13:40:28.351455 ctory
11346 13:40:28.351693 Received signal: <TESTSET> STOP
11347 13:40:28.351759 Closing test_set panfrost_submit
11348 13:40:28.361360 [1mSubte<8>[ 15.065663] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14063039_1.5.2.3.1>
11349 13:40:28.361477 st pan-reset: SKIP (0.000s)[0m
11350 13:40:28.361737 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14063039_1.5.2.3.1
11351 13:40:28.361822 Ending use of test pattern.
11352 13:40:28.361883 Ending test lava.0_igt-gpu-panfrost (14063039_1.5.2.3.1), duration 0.85
11354 13:40:28.367593 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11355 13:40:28.374504 Using IGT_SRANDOM=1716903628 for randomisation
11356 13:40:28.380826 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11357 13:40:28.380927 Test requirement: !(fd<0)
11358 13:40:28.387223 No known gpu found for chipset flags 0x32 (panfrost)
11359 13:40:28.391021 Last errno: 2, No such file or directory
11360 13:40:28.394148 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11361 13:40:28.400856 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11362 13:40:28.404313 Using IGT_SRANDOM=1716903628 for randomisation
11363 13:40:28.410436 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11364 13:40:28.414284 Test requirement: !(fd<0)
11365 13:40:28.420849 No known gpu found for chipset flags 0x32 (panfrost)
11366 13:40:28.424106 Last errno: 2, No such file or directory
11367 13:40:28.427319 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11368 13:40:28.427409 + set +x
11369 13:40:28.430347 <LAVA_TEST_RUNNER EXIT>
11370 13:40:28.430609 ok: lava_test_shell seems to have completed
11371 13:40:28.430922 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11372 13:40:28.431025 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11373 13:40:28.431111 end: 3 lava-test-retry (duration 00:00:01) [common]
11374 13:40:28.431217 start: 4 finalize (timeout 00:07:12) [common]
11375 13:40:28.431306 start: 4.1 power-off (timeout 00:00:30) [common]
11376 13:40:28.431460 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11377 13:40:28.501106 >> Command sent successfully.
11378 13:40:28.503367 Returned 0 in 0 seconds
11379 13:40:28.603776 end: 4.1 power-off (duration 00:00:00) [common]
11381 13:40:28.604102 start: 4.2 read-feedback (timeout 00:07:12) [common]
11382 13:40:28.604366 Listened to connection for namespace 'common' for up to 1s
11383 13:40:29.605314 Finalising connection for namespace 'common'
11384 13:40:29.605491 Disconnecting from shell: Finalise
11385 13:40:29.605572 / #
11386 13:40:29.705904 end: 4.2 read-feedback (duration 00:00:01) [common]
11387 13:40:29.706072 end: 4 finalize (duration 00:00:01) [common]
11388 13:40:29.706192 Cleaning after the job
11389 13:40:29.706290 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/ramdisk
11390 13:40:29.712850 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/kernel
11391 13:40:29.727980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/dtb
11392 13:40:29.728213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063039/tftp-deploy-e4u_78p6/modules
11393 13:40:29.733910 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063039
11394 13:40:29.851150 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063039
11395 13:40:29.851327 Job finished correctly