Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:36:27.513818 lava-dispatcher, installed at version: 2024.03
2 13:36:27.514008 start: 0 validate
3 13:36:27.514146 Start time: 2024-05-28 13:36:27.514139+00:00 (UTC)
4 13:36:27.514261 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:36:27.514387 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:36:27.776213 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:36:27.776852 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:37:41.600337 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:37:41.600585 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:37:41.858457 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:37:41.858631 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:37:42.373038 validate duration: 74.86
14 13:37:42.373314 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:37:42.373419 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:37:42.373516 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:37:42.373655 Not decompressing ramdisk as can be used compressed.
18 13:37:42.373739 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 13:37:42.373802 saving as /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/ramdisk/rootfs.cpio.gz
20 13:37:42.373867 total size: 47897469 (45 MB)
21 13:37:42.633177 progress 0 % (0 MB)
22 13:37:42.645767 progress 5 % (2 MB)
23 13:37:42.658222 progress 10 % (4 MB)
24 13:37:42.670685 progress 15 % (6 MB)
25 13:37:42.683315 progress 20 % (9 MB)
26 13:37:42.695910 progress 25 % (11 MB)
27 13:37:42.708791 progress 30 % (13 MB)
28 13:37:42.721776 progress 35 % (16 MB)
29 13:37:42.734327 progress 40 % (18 MB)
30 13:37:42.746723 progress 45 % (20 MB)
31 13:37:42.759312 progress 50 % (22 MB)
32 13:37:42.771817 progress 55 % (25 MB)
33 13:37:42.784580 progress 60 % (27 MB)
34 13:37:42.797110 progress 65 % (29 MB)
35 13:37:42.810034 progress 70 % (32 MB)
36 13:37:42.822553 progress 75 % (34 MB)
37 13:37:42.835309 progress 80 % (36 MB)
38 13:37:42.847956 progress 85 % (38 MB)
39 13:37:42.860223 progress 90 % (41 MB)
40 13:37:42.872171 progress 95 % (43 MB)
41 13:37:42.884293 progress 100 % (45 MB)
42 13:37:42.884584 45 MB downloaded in 0.51 s (89.44 MB/s)
43 13:37:42.884749 end: 1.1.1 http-download (duration 00:00:01) [common]
45 13:37:42.885102 end: 1.1 download-retry (duration 00:00:01) [common]
46 13:37:42.885190 start: 1.2 download-retry (timeout 00:09:59) [common]
47 13:37:42.885298 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 13:37:42.885439 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:37:42.885507 saving as /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/kernel/Image
50 13:37:42.885568 total size: 54682112 (52 MB)
51 13:37:42.885630 No compression specified
52 13:37:42.886808 progress 0 % (0 MB)
53 13:37:42.901102 progress 5 % (2 MB)
54 13:37:42.915659 progress 10 % (5 MB)
55 13:37:42.930678 progress 15 % (7 MB)
56 13:37:42.945716 progress 20 % (10 MB)
57 13:37:42.961107 progress 25 % (13 MB)
58 13:37:42.975968 progress 30 % (15 MB)
59 13:37:42.990155 progress 35 % (18 MB)
60 13:37:43.004228 progress 40 % (20 MB)
61 13:37:43.018358 progress 45 % (23 MB)
62 13:37:43.032539 progress 50 % (26 MB)
63 13:37:43.046729 progress 55 % (28 MB)
64 13:37:43.060948 progress 60 % (31 MB)
65 13:37:43.075057 progress 65 % (33 MB)
66 13:37:43.089308 progress 70 % (36 MB)
67 13:37:43.103474 progress 75 % (39 MB)
68 13:37:43.117811 progress 80 % (41 MB)
69 13:37:43.131894 progress 85 % (44 MB)
70 13:37:43.146008 progress 90 % (46 MB)
71 13:37:43.160117 progress 95 % (49 MB)
72 13:37:43.173861 progress 100 % (52 MB)
73 13:37:43.174152 52 MB downloaded in 0.29 s (180.71 MB/s)
74 13:37:43.174335 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:37:43.174598 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:37:43.174703 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:37:43.174807 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:37:43.174963 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:37:43.175039 saving as /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/dtb/mt8192-asurada-spherion-r0.dtb
81 13:37:43.175141 total size: 47258 (0 MB)
82 13:37:43.175243 No compression specified
83 13:37:43.176943 progress 69 % (0 MB)
84 13:37:43.177271 progress 100 % (0 MB)
85 13:37:43.177475 0 MB downloaded in 0.00 s (19.33 MB/s)
86 13:37:43.177656 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:37:43.177914 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:37:43.178018 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:37:43.178133 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:37:43.178276 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:37:43.178352 saving as /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/modules/modules.tar
93 13:37:43.178453 total size: 8607916 (8 MB)
94 13:37:43.178556 Using unxz to decompress xz
95 13:37:43.183180 progress 0 % (0 MB)
96 13:37:43.204109 progress 5 % (0 MB)
97 13:37:43.230620 progress 10 % (0 MB)
98 13:37:43.257725 progress 15 % (1 MB)
99 13:37:43.284428 progress 20 % (1 MB)
100 13:37:43.311456 progress 25 % (2 MB)
101 13:37:43.337022 progress 30 % (2 MB)
102 13:37:43.361453 progress 35 % (2 MB)
103 13:37:43.388170 progress 40 % (3 MB)
104 13:37:43.414063 progress 45 % (3 MB)
105 13:37:43.440112 progress 50 % (4 MB)
106 13:37:43.466810 progress 55 % (4 MB)
107 13:37:43.493452 progress 60 % (4 MB)
108 13:37:43.519632 progress 65 % (5 MB)
109 13:37:43.548690 progress 70 % (5 MB)
110 13:37:43.578473 progress 75 % (6 MB)
111 13:37:43.604431 progress 80 % (6 MB)
112 13:37:43.630159 progress 85 % (7 MB)
113 13:37:43.654670 progress 90 % (7 MB)
114 13:37:43.684582 progress 95 % (7 MB)
115 13:37:43.713460 progress 100 % (8 MB)
116 13:37:43.719219 8 MB downloaded in 0.54 s (15.18 MB/s)
117 13:37:43.719508 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:37:43.719787 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:37:43.719883 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:37:43.719981 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:37:43.720073 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:37:43.720165 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:37:43.720408 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood
125 13:37:43.720546 makedir: /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin
126 13:37:43.720655 makedir: /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/tests
127 13:37:43.720756 makedir: /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/results
128 13:37:43.720876 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-add-keys
129 13:37:43.721093 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-add-sources
130 13:37:43.721277 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-background-process-start
131 13:37:43.721415 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-background-process-stop
132 13:37:43.721547 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-common-functions
133 13:37:43.721675 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-echo-ipv4
134 13:37:43.721803 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-install-packages
135 13:37:43.721929 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-installed-packages
136 13:37:43.722060 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-os-build
137 13:37:43.722186 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-probe-channel
138 13:37:43.722313 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-probe-ip
139 13:37:43.722441 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-target-ip
140 13:37:43.722567 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-target-mac
141 13:37:43.722692 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-target-storage
142 13:37:43.722825 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-case
143 13:37:43.722973 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-event
144 13:37:43.723101 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-feedback
145 13:37:43.723229 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-raise
146 13:37:43.723358 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-reference
147 13:37:43.723484 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-runner
148 13:37:43.723611 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-set
149 13:37:43.723736 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-test-shell
150 13:37:43.723868 Updating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-install-packages (oe)
151 13:37:43.724027 Updating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/bin/lava-installed-packages (oe)
152 13:37:43.724155 Creating /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/environment
153 13:37:43.724263 LAVA metadata
154 13:37:43.724339 - LAVA_JOB_ID=14063027
155 13:37:43.724406 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:37:43.724513 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:37:43.724584 skipped lava-vland-overlay
158 13:37:43.724662 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:37:43.724748 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:37:43.724815 skipped lava-multinode-overlay
161 13:37:43.724890 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:37:43.724978 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:37:43.725057 Loading test definitions
164 13:37:43.725155 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:37:43.725231 Using /lava-14063027 at stage 0
166 13:37:43.725559 uuid=14063027_1.5.2.3.1 testdef=None
167 13:37:43.725651 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:37:43.725743 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:37:43.726901 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:37:43.727132 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:37:43.727760 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:37:43.728012 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:37:43.728624 runner path: /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/0/tests/0_igt-kms-mediatek test_uuid 14063027_1.5.2.3.1
176 13:37:43.728785 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:37:43.729120 Creating lava-test-runner.conf files
179 13:37:43.729214 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063027/lava-overlay-oz8lwood/lava-14063027/0 for stage 0
180 13:37:43.729340 - 0_igt-kms-mediatek
181 13:37:43.729450 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:37:43.729540 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:37:43.737082 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:37:43.737252 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:37:43.737408 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:37:43.737533 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:37:43.737622 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:37:45.594046 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 13:37:45.594508 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 13:37:45.594662 extracting modules file /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063027/extract-overlay-ramdisk-fhco8e0c/ramdisk
191 13:37:45.893514 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:37:45.893677 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 13:37:45.893772 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063027/compress-overlay-8vaw1q9d/overlay-1.5.2.4.tar.gz to ramdisk
194 13:37:45.893846 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063027/compress-overlay-8vaw1q9d/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063027/extract-overlay-ramdisk-fhco8e0c/ramdisk
195 13:37:45.900610 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:37:45.900735 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 13:37:45.900829 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:37:45.900921 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 13:37:45.901033 Building ramdisk /var/lib/lava/dispatcher/tmp/14063027/extract-overlay-ramdisk-fhco8e0c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063027/extract-overlay-ramdisk-fhco8e0c/ramdisk
200 13:37:47.059356 >> 465919 blocks
201 13:37:53.396400 rename /var/lib/lava/dispatcher/tmp/14063027/extract-overlay-ramdisk-fhco8e0c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/ramdisk/ramdisk.cpio.gz
202 13:37:53.396929 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 13:37:53.397088 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 13:37:53.397185 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 13:37:53.397332 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/kernel/Image']
206 13:38:07.664301 Returned 0 in 14 seconds
207 13:38:07.764906 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/kernel/image.itb
208 13:38:08.627264 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:38:08.627640 output: Created: Tue May 28 14:38:08 2024
210 13:38:08.627717 output: Image 0 (kernel-1)
211 13:38:08.627782 output: Description:
212 13:38:08.627846 output: Created: Tue May 28 14:38:08 2024
213 13:38:08.627908 output: Type: Kernel Image
214 13:38:08.627970 output: Compression: lzma compressed
215 13:38:08.628032 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:38:08.628094 output: Architecture: AArch64
217 13:38:08.628155 output: OS: Linux
218 13:38:08.628219 output: Load Address: 0x00000000
219 13:38:08.628282 output: Entry Point: 0x00000000
220 13:38:08.628339 output: Hash algo: crc32
221 13:38:08.628398 output: Hash value: 0578ee26
222 13:38:08.628456 output: Image 1 (fdt-1)
223 13:38:08.628510 output: Description: mt8192-asurada-spherion-r0
224 13:38:08.628567 output: Created: Tue May 28 14:38:08 2024
225 13:38:08.628622 output: Type: Flat Device Tree
226 13:38:08.628676 output: Compression: uncompressed
227 13:38:08.628730 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:38:08.628784 output: Architecture: AArch64
229 13:38:08.628838 output: Hash algo: crc32
230 13:38:08.628892 output: Hash value: 0f8e4d2e
231 13:38:08.628945 output: Image 2 (ramdisk-1)
232 13:38:08.628998 output: Description: unavailable
233 13:38:08.629051 output: Created: Tue May 28 14:38:08 2024
234 13:38:08.629104 output: Type: RAMDisk Image
235 13:38:08.629157 output: Compression: Unknown Compression
236 13:38:08.629211 output: Data Size: 60993576 Bytes = 59564.04 KiB = 58.17 MiB
237 13:38:08.629272 output: Architecture: AArch64
238 13:38:08.629327 output: OS: Linux
239 13:38:08.629380 output: Load Address: unavailable
240 13:38:08.629433 output: Entry Point: unavailable
241 13:38:08.629486 output: Hash algo: crc32
242 13:38:08.629539 output: Hash value: 83f6a1fe
243 13:38:08.629594 output: Default Configuration: 'conf-1'
244 13:38:08.629647 output: Configuration 0 (conf-1)
245 13:38:08.629701 output: Description: mt8192-asurada-spherion-r0
246 13:38:08.629754 output: Kernel: kernel-1
247 13:38:08.629807 output: Init Ramdisk: ramdisk-1
248 13:38:08.629860 output: FDT: fdt-1
249 13:38:08.629913 output: Loadables: kernel-1
250 13:38:08.629966 output:
251 13:38:08.630174 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:38:08.630269 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:38:08.630380 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 13:38:08.630477 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 13:38:08.630553 No LXC device requested
256 13:38:08.630632 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:38:08.630717 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 13:38:08.630797 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:38:08.630870 Checking files for TFTP limit of 4294967296 bytes.
260 13:38:08.631376 end: 1 tftp-deploy (duration 00:00:26) [common]
261 13:38:08.631486 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:38:08.631584 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:38:08.631710 substitutions:
264 13:38:08.631780 - {DTB}: 14063027/tftp-deploy-jw8mi1o4/dtb/mt8192-asurada-spherion-r0.dtb
265 13:38:08.631844 - {INITRD}: 14063027/tftp-deploy-jw8mi1o4/ramdisk/ramdisk.cpio.gz
266 13:38:08.631904 - {KERNEL}: 14063027/tftp-deploy-jw8mi1o4/kernel/Image
267 13:38:08.631963 - {LAVA_MAC}: None
268 13:38:08.632020 - {PRESEED_CONFIG}: None
269 13:38:08.632077 - {PRESEED_LOCAL}: None
270 13:38:08.632132 - {RAMDISK}: 14063027/tftp-deploy-jw8mi1o4/ramdisk/ramdisk.cpio.gz
271 13:38:08.632188 - {ROOT_PART}: None
272 13:38:08.632266 - {ROOT}: None
273 13:38:08.632325 - {SERVER_IP}: 192.168.201.1
274 13:38:08.632381 - {TEE}: None
275 13:38:08.632436 Parsed boot commands:
276 13:38:08.632491 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:38:08.632667 Parsed boot commands: tftpboot 192.168.201.1 14063027/tftp-deploy-jw8mi1o4/kernel/image.itb 14063027/tftp-deploy-jw8mi1o4/kernel/cmdline
278 13:38:08.632759 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:38:08.632852 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:38:08.632945 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:38:08.633036 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:38:08.633109 Not connected, no need to disconnect.
283 13:38:08.633184 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:38:08.633278 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:38:08.633349 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 13:38:08.637094 Setting prompt string to ['lava-test: # ']
287 13:38:08.637494 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:38:08.637604 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:38:08.637706 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:38:08.637806 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:38:08.637991 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 13:38:22.429725 Returned 0 in 13 seconds
293 13:38:22.530370 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 13:38:22.530905 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 13:38:22.531025 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 13:38:22.531153 Setting prompt string to 'Starting depthcharge on Spherion...'
298 13:38:22.531258 Changing prompt to 'Starting depthcharge on Spherion...'
299 13:38:22.531374 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 13:38:22.531968 [Enter `^Ec?' for help]
301 13:38:22.532082
302 13:38:22.532189
303 13:38:22.532291 F0: 102B 0000
304 13:38:22.532392
305 13:38:22.532491 F3: 1001 0000 [0200]
306 13:38:22.532594
307 13:38:22.532694 F3: 1001 0000
308 13:38:22.532794
309 13:38:22.532892 F7: 102D 0000
310 13:38:22.532989
311 13:38:22.533086 F1: 0000 0000
312 13:38:22.533184
313 13:38:22.533289 V0: 0000 0000 [0001]
314 13:38:22.533386
315 13:38:22.533482 00: 0007 8000
316 13:38:22.533584
317 13:38:22.533680 01: 0000 0000
318 13:38:22.533777
319 13:38:22.533872 BP: 0C00 0209 [0000]
320 13:38:22.533966
321 13:38:22.534063 G0: 1182 0000
322 13:38:22.534169
323 13:38:22.534259 EC: 0000 0021 [4000]
324 13:38:22.534349
325 13:38:22.534434 S7: 0000 0000 [0000]
326 13:38:22.534521
327 13:38:22.534614 CC: 0000 0000 [0001]
328 13:38:22.534700
329 13:38:22.534786 T0: 0000 0040 [010F]
330 13:38:22.534872
331 13:38:22.534963 Jump to BL
332 13:38:22.535052
333 13:38:22.535138
334 13:38:22.535223
335 13:38:22.535310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 13:38:22.535399 ARM64: Exception handlers installed.
337 13:38:22.535484 ARM64: Testing exception
338 13:38:22.535572 ARM64: Done test exception
339 13:38:22.535659 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 13:38:22.535746 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 13:38:22.535833 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 13:38:22.535920 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 13:38:22.536009 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 13:38:22.536098 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 13:38:22.536186 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 13:38:22.536272 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 13:38:22.536359 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 13:38:22.536445 WDT: Last reset was cold boot
349 13:38:22.536530 SPI1(PAD0) initialized at 2873684 Hz
350 13:38:22.536609 SPI5(PAD0) initialized at 992727 Hz
351 13:38:22.536665 VBOOT: Loading verstage.
352 13:38:22.536720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 13:38:22.536775 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 13:38:22.536829 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 13:38:22.536884 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 13:38:22.536938 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 13:38:22.536994 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 13:38:22.537049 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 13:38:22.537104
360 13:38:22.537167
361 13:38:22.537255 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 13:38:22.537322 ARM64: Exception handlers installed.
363 13:38:22.537377 ARM64: Testing exception
364 13:38:22.537431 ARM64: Done test exception
365 13:38:22.537484 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 13:38:22.537539 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 13:38:22.537594 Probing TPM: . done!
368 13:38:22.537648 TPM ready after 0 ms
369 13:38:22.537705 Connected to device vid:did:rid of 1ae0:0028:00
370 13:38:22.537761 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 13:38:22.537816 Initialized TPM device CR50 revision 0
372 13:38:22.537870 tlcl_send_startup: Startup return code is 0
373 13:38:22.537925 TPM: setup succeeded
374 13:38:22.537980 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 13:38:22.538035 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 13:38:22.538113 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 13:38:22.538192 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:38:22.538273 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 13:38:22.538369 in-header: 03 07 00 00 08 00 00 00
380 13:38:22.538464 in-data: aa e4 47 04 13 02 00 00
381 13:38:22.538558 Chrome EC: UHEPI supported
382 13:38:22.538653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 13:38:22.538748 in-header: 03 a9 00 00 08 00 00 00
384 13:38:22.538845 in-data: 84 60 60 08 00 00 00 00
385 13:38:22.538940 Phase 1
386 13:38:22.539035 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 13:38:22.539130 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 13:38:22.539225 VB2:vb2_check_recovery() Recovery was requested manually
389 13:38:22.539320 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 13:38:22.539417 Recovery requested (1009000e)
391 13:38:22.539512 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:38:22.539606 tlcl_extend: response is 0
393 13:38:22.539701 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:38:22.539776 tlcl_extend: response is 0
395 13:38:22.539871 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:38:22.539966 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
397 13:38:22.540062 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 13:38:22.540157
399 13:38:22.540251
400 13:38:22.540346 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:38:22.540443 ARM64: Exception handlers installed.
402 13:38:22.540539 ARM64: Testing exception
403 13:38:22.540640 ARM64: Done test exception
404 13:38:22.540736 pmic_efuse_setting: Set efuses in 11 msecs
405 13:38:22.540832 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:38:22.540927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:38:22.541024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:38:22.541302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:38:22.541399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:38:22.541498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:38:22.541596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:38:22.541693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:38:22.541789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:38:22.541884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:38:22.541980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:38:22.542077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:38:22.542172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:38:22.542267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:38:22.542362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:38:22.542472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:38:22.542567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:38:22.542661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:38:22.542748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:38:22.542837 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:38:22.542930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:38:22.543018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:38:22.543105 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:38:22.543192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:38:22.543280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:38:22.543367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:38:22.543454 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:38:22.543556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:38:22.543643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:38:22.543736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:38:22.543827 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:38:22.543914 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:38:22.544006 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:38:22.544068 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:38:22.544124 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:38:22.544179 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:38:22.544233 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:38:22.544288 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:38:22.544351 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:38:22.544437 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:38:22.544522 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:38:22.544618 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:38:22.544704 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:38:22.544789 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:38:22.544877 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:38:22.544939 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:38:22.544997 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:38:22.545053 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:38:22.545148 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:38:22.545233 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:38:22.545312 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:38:22.545369 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:38:22.545427 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 13:38:22.545483 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:38:22.545539 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:38:22.545605 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:38:22.545664 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:38:22.545719 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:38:22.545774 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:38:22.545828 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:38:22.545882 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0xb
466 13:38:22.545944 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 13:38:22.546023 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 13:38:22.546099 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:38:22.546175 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 13:38:22.546269 [RTC]rtc_get_frequency_meter,154: input=7, output=726
471 13:38:22.546363 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 13:38:22.546459 [RTC]rtc_get_frequency_meter,154: input=13, output=822
473 13:38:22.546554 [RTC]rtc_get_frequency_meter,154: input=12, output=806
474 13:38:22.546648 [RTC]rtc_get_frequency_meter,154: input=11, output=790
475 13:38:22.546742 [RTC]rtc_get_frequency_meter,154: input=12, output=806
476 13:38:22.546837 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 13:38:22.546939 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 13:38:22.547234 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 13:38:22.547330 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 13:38:22.547428 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 13:38:22.547526 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 13:38:22.547623 ADC[4]: Raw value=904802 ID=7
483 13:38:22.547719 ADC[3]: Raw value=213916 ID=1
484 13:38:22.547814 RAM Code: 0x71
485 13:38:22.547909 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 13:38:22.548008 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 13:38:22.548104 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 13:38:22.548200 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 13:38:22.548296 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 13:38:22.548392 in-header: 03 07 00 00 08 00 00 00
491 13:38:22.548488 in-data: aa e4 47 04 13 02 00 00
492 13:38:22.548584 Chrome EC: UHEPI supported
493 13:38:22.548678 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 13:38:22.548773 in-header: 03 a9 00 00 08 00 00 00
495 13:38:22.548870 in-data: 84 60 60 08 00 00 00 00
496 13:38:22.548967 MRC: failed to locate region type 0.
497 13:38:22.549062 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 13:38:22.549157 DRAM-K: Running full calibration
499 13:38:22.549252 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 13:38:22.549356 header.status = 0x0
501 13:38:22.549451 header.version = 0x6 (expected: 0x6)
502 13:38:22.549547 header.size = 0xd00 (expected: 0xd00)
503 13:38:22.549642 header.flags = 0x0
504 13:38:22.549737 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 13:38:22.549832 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 13:38:22.549928 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 13:38:22.550023 dram_init: ddr_geometry: 2
508 13:38:22.550119 [EMI] MDL number = 2
509 13:38:22.550213 [EMI] Get MDL freq = 0
510 13:38:22.550307 dram_init: ddr_type: 0
511 13:38:22.550401 is_discrete_lpddr4: 1
512 13:38:22.550495 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 13:38:22.550589
514 13:38:22.550684
515 13:38:22.550778 [Bian_co] ETT version 0.0.0.1
516 13:38:22.550873 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 13:38:22.550967
518 13:38:22.551061 dramc_set_vcore_voltage set vcore to 650000
519 13:38:22.551155 Read voltage for 800, 4
520 13:38:22.551250 Vio18 = 0
521 13:38:22.551356 Vcore = 650000
522 13:38:22.551449 Vdram = 0
523 13:38:22.551536 Vddq = 0
524 13:38:22.551623 Vmddr = 0
525 13:38:22.551706 dram_init: config_dvfs: 1
526 13:38:22.551798 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 13:38:22.551887 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 13:38:22.551975 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 13:38:22.552061 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 13:38:22.552148 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 13:38:22.552234 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 13:38:22.552322 MEM_TYPE=3, freq_sel=18
533 13:38:22.552417 sv_algorithm_assistance_LP4_1600
534 13:38:22.552505 ============ PULL DRAM RESETB DOWN ============
535 13:38:22.552591 ========== PULL DRAM RESETB DOWN end =========
536 13:38:22.552677 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 13:38:22.552765 ===================================
538 13:38:22.552850 LPDDR4 DRAM CONFIGURATION
539 13:38:22.552944 ===================================
540 13:38:22.553030 EX_ROW_EN[0] = 0x0
541 13:38:22.553115 EX_ROW_EN[1] = 0x0
542 13:38:22.553200 LP4Y_EN = 0x0
543 13:38:22.553298 WORK_FSP = 0x0
544 13:38:22.553385 WL = 0x2
545 13:38:22.553478 RL = 0x2
546 13:38:22.553564 BL = 0x2
547 13:38:22.553649 RPST = 0x0
548 13:38:22.553733 RD_PRE = 0x0
549 13:38:22.553820 WR_PRE = 0x1
550 13:38:22.553904 WR_PST = 0x0
551 13:38:22.553997 DBI_WR = 0x0
552 13:38:22.554083 DBI_RD = 0x0
553 13:38:22.554167 OTF = 0x1
554 13:38:22.554253 ===================================
555 13:38:22.554341 ===================================
556 13:38:22.554426 ANA top config
557 13:38:22.554520 ===================================
558 13:38:22.554606 DLL_ASYNC_EN = 0
559 13:38:22.554690 ALL_SLAVE_EN = 1
560 13:38:22.554777 NEW_RANK_MODE = 1
561 13:38:22.554867 DLL_IDLE_MODE = 1
562 13:38:22.554952 LP45_APHY_COMB_EN = 1
563 13:38:22.555045 TX_ODT_DIS = 1
564 13:38:22.555131 NEW_8X_MODE = 1
565 13:38:22.555217 ===================================
566 13:38:22.555313 ===================================
567 13:38:22.555401 data_rate = 1600
568 13:38:22.555488 CKR = 1
569 13:38:22.555580 DQ_P2S_RATIO = 8
570 13:38:22.555656 ===================================
571 13:38:22.555732 CA_P2S_RATIO = 8
572 13:38:22.555811 DQ_CA_OPEN = 0
573 13:38:22.555905 DQ_SEMI_OPEN = 0
574 13:38:22.556000 CA_SEMI_OPEN = 0
575 13:38:22.556094 CA_FULL_RATE = 0
576 13:38:22.556187 DQ_CKDIV4_EN = 1
577 13:38:22.556281 CA_CKDIV4_EN = 1
578 13:38:22.556376 CA_PREDIV_EN = 0
579 13:38:22.556469 PH8_DLY = 0
580 13:38:22.556562 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 13:38:22.556656 DQ_AAMCK_DIV = 4
582 13:38:22.556749 CA_AAMCK_DIV = 4
583 13:38:22.556844 CA_ADMCK_DIV = 4
584 13:38:22.556938 DQ_TRACK_CA_EN = 0
585 13:38:22.557032 CA_PICK = 800
586 13:38:22.557126 CA_MCKIO = 800
587 13:38:22.557220 MCKIO_SEMI = 0
588 13:38:22.557324 PLL_FREQ = 3068
589 13:38:22.557421 DQ_UI_PI_RATIO = 32
590 13:38:22.557516 CA_UI_PI_RATIO = 0
591 13:38:22.557610 ===================================
592 13:38:22.557705 ===================================
593 13:38:22.557800 memory_type:LPDDR4
594 13:38:22.557894 GP_NUM : 10
595 13:38:22.557989 SRAM_EN : 1
596 13:38:22.558083 MD32_EN : 0
597 13:38:22.558179 ===================================
598 13:38:22.558491 [ANA_INIT] >>>>>>>>>>>>>>
599 13:38:22.558587 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 13:38:22.558687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 13:38:22.558784 ===================================
602 13:38:22.558883 data_rate = 1600,PCW = 0X7600
603 13:38:22.558979 ===================================
604 13:38:22.559075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 13:38:22.559172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 13:38:22.559269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:38:22.559366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 13:38:22.559463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 13:38:22.559558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:38:22.559654 [ANA_INIT] flow start
611 13:38:22.559749 [ANA_INIT] PLL >>>>>>>>
612 13:38:22.559845 [ANA_INIT] PLL <<<<<<<<
613 13:38:22.559940 [ANA_INIT] MIDPI >>>>>>>>
614 13:38:22.560035 [ANA_INIT] MIDPI <<<<<<<<
615 13:38:22.560129 [ANA_INIT] DLL >>>>>>>>
616 13:38:22.560223 [ANA_INIT] flow end
617 13:38:22.560317 ============ LP4 DIFF to SE enter ============
618 13:38:22.560414 ============ LP4 DIFF to SE exit ============
619 13:38:22.560508 [ANA_INIT] <<<<<<<<<<<<<
620 13:38:22.560602 [Flow] Enable top DCM control >>>>>
621 13:38:22.560696 [Flow] Enable top DCM control <<<<<
622 13:38:22.560790 Enable DLL master slave shuffle
623 13:38:22.560886 ==============================================================
624 13:38:22.560981 Gating Mode config
625 13:38:22.561076 ==============================================================
626 13:38:22.561171 Config description:
627 13:38:22.561274 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 13:38:22.561374 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 13:38:22.561471 SELPH_MODE 0: By rank 1: By Phase
630 13:38:22.561567 ==============================================================
631 13:38:22.561662 GAT_TRACK_EN = 1
632 13:38:22.561757 RX_GATING_MODE = 2
633 13:38:22.561852 RX_GATING_TRACK_MODE = 2
634 13:38:22.561947 SELPH_MODE = 1
635 13:38:22.562041 PICG_EARLY_EN = 1
636 13:38:22.562136 VALID_LAT_VALUE = 1
637 13:38:22.562230 ==============================================================
638 13:38:22.562325 Enter into Gating configuration >>>>
639 13:38:22.562421 Exit from Gating configuration <<<<
640 13:38:22.562515 Enter into DVFS_PRE_config >>>>>
641 13:38:22.562609 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 13:38:22.562708 Exit from DVFS_PRE_config <<<<<
643 13:38:22.562802 Enter into PICG configuration >>>>
644 13:38:22.562897 Exit from PICG configuration <<<<
645 13:38:22.562991 [RX_INPUT] configuration >>>>>
646 13:38:22.563085 [RX_INPUT] configuration <<<<<
647 13:38:22.563179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 13:38:22.563273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 13:38:22.563370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:38:22.563465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:38:22.563560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 13:38:22.563654 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 13:38:22.563749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 13:38:22.563845 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 13:38:22.563939 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 13:38:22.564042 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 13:38:22.564138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 13:38:22.564233 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 13:38:22.564329 ===================================
660 13:38:22.564426 LPDDR4 DRAM CONFIGURATION
661 13:38:22.564520 ===================================
662 13:38:22.564615 EX_ROW_EN[0] = 0x0
663 13:38:22.564709 EX_ROW_EN[1] = 0x0
664 13:38:22.564802 LP4Y_EN = 0x0
665 13:38:22.564899 WORK_FSP = 0x0
666 13:38:22.564994 WL = 0x2
667 13:38:22.565087 RL = 0x2
668 13:38:22.565182 BL = 0x2
669 13:38:22.565287 RPST = 0x0
670 13:38:22.565386 RD_PRE = 0x0
671 13:38:22.565481 WR_PRE = 0x1
672 13:38:22.565576 WR_PST = 0x0
673 13:38:22.565671 DBI_WR = 0x0
674 13:38:22.565765 DBI_RD = 0x0
675 13:38:22.565860 OTF = 0x1
676 13:38:22.565955 ===================================
677 13:38:22.566050 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 13:38:22.566145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 13:38:22.566241 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 13:38:22.566336 ===================================
681 13:38:22.566432 LPDDR4 DRAM CONFIGURATION
682 13:38:22.566526 ===================================
683 13:38:22.566621 EX_ROW_EN[0] = 0x10
684 13:38:22.566715 EX_ROW_EN[1] = 0x0
685 13:38:22.566809 LP4Y_EN = 0x0
686 13:38:22.566904 WORK_FSP = 0x0
687 13:38:22.566998 WL = 0x2
688 13:38:22.567091 RL = 0x2
689 13:38:22.567185 BL = 0x2
690 13:38:22.567278 RPST = 0x0
691 13:38:22.567374 RD_PRE = 0x0
692 13:38:22.567468 WR_PRE = 0x1
693 13:38:22.567561 WR_PST = 0x0
694 13:38:22.567654 DBI_WR = 0x0
695 13:38:22.567748 DBI_RD = 0x0
696 13:38:22.567842 OTF = 0x1
697 13:38:22.567937 ===================================
698 13:38:22.568032 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 13:38:22.568127 nWR fixed to 40
700 13:38:22.568222 [ModeRegInit_LP4] CH0 RK0
701 13:38:22.568316 [ModeRegInit_LP4] CH0 RK1
702 13:38:22.568412 [ModeRegInit_LP4] CH1 RK0
703 13:38:22.568506 [ModeRegInit_LP4] CH1 RK1
704 13:38:22.568600 match AC timing 13
705 13:38:22.568694 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 13:38:22.568993 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 13:38:22.569090 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 13:38:22.569188 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 13:38:22.569299 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 13:38:22.569382 [EMI DOE] emi_dcm 0
711 13:38:22.569478 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 13:38:22.569553 ==
713 13:38:22.569649 Dram Type= 6, Freq= 0, CH_0, rank 0
714 13:38:22.569724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 13:38:22.569821 ==
716 13:38:22.569917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 13:38:22.570013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 13:38:22.570109 [CA 0] Center 37 (7~68) winsize 62
719 13:38:22.570204 [CA 1] Center 37 (6~68) winsize 63
720 13:38:22.570299 [CA 2] Center 34 (4~65) winsize 62
721 13:38:22.570397 [CA 3] Center 34 (4~65) winsize 62
722 13:38:22.570492 [CA 4] Center 34 (3~65) winsize 63
723 13:38:22.570587 [CA 5] Center 33 (3~64) winsize 62
724 13:38:22.570681
725 13:38:22.570776 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 13:38:22.570872
727 13:38:22.570967 [CATrainingPosCal] consider 1 rank data
728 13:38:22.571061 u2DelayCellTimex100 = 270/100 ps
729 13:38:22.571155 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 13:38:22.571249 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 13:38:22.571345 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 13:38:22.571440 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:38:22.571533 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 13:38:22.571629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:38:22.571723
736 13:38:22.571816 CA PerBit enable=1, Macro0, CA PI delay=33
737 13:38:22.571912
738 13:38:22.572006 [CBTSetCACLKResult] CA Dly = 33
739 13:38:22.572100 CS Dly: 5 (0~36)
740 13:38:22.572194 ==
741 13:38:22.572288 Dram Type= 6, Freq= 0, CH_0, rank 1
742 13:38:22.572384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 13:38:22.572485 ==
744 13:38:22.572576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 13:38:22.572664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 13:38:22.572751 [CA 0] Center 38 (7~69) winsize 63
747 13:38:22.572839 [CA 1] Center 37 (7~68) winsize 62
748 13:38:22.572929 [CA 2] Center 35 (4~66) winsize 63
749 13:38:22.573015 [CA 3] Center 34 (4~65) winsize 62
750 13:38:22.573101 [CA 4] Center 34 (3~65) winsize 63
751 13:38:22.573186 [CA 5] Center 33 (3~64) winsize 62
752 13:38:22.573277
753 13:38:22.573365 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 13:38:22.573450
755 13:38:22.573536 [CATrainingPosCal] consider 2 rank data
756 13:38:22.573621 u2DelayCellTimex100 = 270/100 ps
757 13:38:22.573706 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 13:38:22.573792 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:38:22.573879 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 13:38:22.573965 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:38:22.574050 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
762 13:38:22.574135 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:38:22.574219
764 13:38:22.574307 CA PerBit enable=1, Macro0, CA PI delay=33
765 13:38:22.574395
766 13:38:22.574480 [CBTSetCACLKResult] CA Dly = 33
767 13:38:22.574564 CS Dly: 6 (0~38)
768 13:38:22.574648
769 13:38:22.574739 ----->DramcWriteLeveling(PI) begin...
770 13:38:22.574825 ==
771 13:38:22.574912 Dram Type= 6, Freq= 0, CH_0, rank 0
772 13:38:22.574999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 13:38:22.575085 ==
774 13:38:22.575173 Write leveling (Byte 0): 27 => 27
775 13:38:22.575264 Write leveling (Byte 1): 26 => 26
776 13:38:22.575366 DramcWriteLeveling(PI) end<-----
777 13:38:22.575463
778 13:38:22.575557 ==
779 13:38:22.575664 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:38:22.575761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:38:22.575849 ==
782 13:38:22.575937 [Gating] SW mode calibration
783 13:38:22.576025 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 13:38:22.576112 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 13:38:22.576198 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 13:38:22.576284 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 13:38:22.576374 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 13:38:22.576442 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:38:22.576505 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:38:22.576592 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:38:22.576678 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:38:22.576764 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:38:22.576850 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:38:22.576940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:38:22.577037 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:38:22.577132 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:38:22.577227 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:38:22.577316 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:38:22.577410 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:38:22.577506 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:38:22.577603 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:38:22.577698 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 13:38:22.577792 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
804 13:38:22.577886 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 13:38:22.577985 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:38:22.578082 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:38:22.578176 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:38:22.578271 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:38:22.578365 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:38:22.578461 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:38:22.578558 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
812 13:38:22.578653 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
813 13:38:22.578747 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:38:22.579054 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:38:22.579153 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:38:22.579250 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:38:22.579347 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:38:22.579444 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
819 13:38:22.579542 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 0)
820 13:38:22.579645 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
821 13:38:22.579740 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:38:22.579836 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:38:22.579932 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:38:22.580028 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:38:22.580125 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:38:22.580220 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
827 13:38:22.580314 0 11 8 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
828 13:38:22.580409 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
829 13:38:22.580510 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:38:22.580608 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:38:22.580703 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:38:22.580798 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:38:22.580892 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:38:22.580989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:38:22.581087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
836 13:38:22.581183 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 13:38:22.581288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:38:22.581384 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:38:22.581479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:38:22.581575 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:38:22.581672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:38:22.581767 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:38:22.581861 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:38:22.581956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:38:22.582053 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:38:22.582149 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:38:22.582245 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:38:22.582340 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:38:22.582434 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:38:22.582530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:38:22.582626 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 13:38:22.582722 Total UI for P1: 0, mck2ui 16
853 13:38:22.582817 best dqsien dly found for B0: ( 0, 14, 6)
854 13:38:22.582912 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 13:38:22.583006 Total UI for P1: 0, mck2ui 16
856 13:38:22.583104 best dqsien dly found for B1: ( 0, 14, 8)
857 13:38:22.583200 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 13:38:22.583295 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 13:38:22.583389
860 13:38:22.583483 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 13:38:22.583577 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 13:38:22.583679 [Gating] SW calibration Done
863 13:38:22.583776 ==
864 13:38:22.583871 Dram Type= 6, Freq= 0, CH_0, rank 0
865 13:38:22.583966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 13:38:22.584060 ==
867 13:38:22.584158 RX Vref Scan: 0
868 13:38:22.584255
869 13:38:22.584350 RX Vref 0 -> 0, step: 1
870 13:38:22.584444
871 13:38:22.584538 RX Delay -130 -> 252, step: 16
872 13:38:22.584632 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 13:38:22.584729 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 13:38:22.584825 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 13:38:22.584920 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 13:38:22.585015 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 13:38:22.585109 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 13:38:22.585205 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 13:38:22.585335 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 13:38:22.585420 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 13:38:22.585488 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 13:38:22.585551 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 13:38:22.585612 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 13:38:22.585672 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 13:38:22.585731 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 13:38:22.585790 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 13:38:22.585848 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 13:38:22.585912 ==
889 13:38:22.585969 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:38:22.586026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 13:38:22.586084 ==
892 13:38:22.586141 DQS Delay:
893 13:38:22.586231 DQS0 = 0, DQS1 = 0
894 13:38:22.586292 DQM Delay:
895 13:38:22.586348 DQM0 = 88, DQM1 = 74
896 13:38:22.586411 DQ Delay:
897 13:38:22.586468 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 13:38:22.586524 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 13:38:22.586580 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
900 13:38:22.586636 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 13:38:22.586691
902 13:38:22.586747
903 13:38:22.586801 ==
904 13:38:22.586858 Dram Type= 6, Freq= 0, CH_0, rank 0
905 13:38:22.586918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 13:38:22.586974 ==
907 13:38:22.587030
908 13:38:22.587086
909 13:38:22.587142 TX Vref Scan disable
910 13:38:22.587197 == TX Byte 0 ==
911 13:38:22.587252 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
912 13:38:22.587309 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
913 13:38:22.587369 == TX Byte 1 ==
914 13:38:22.587426 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
915 13:38:22.587481 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
916 13:38:22.587537 ==
917 13:38:22.587592 Dram Type= 6, Freq= 0, CH_0, rank 0
918 13:38:22.587647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 13:38:22.587703 ==
920 13:38:22.587759 TX Vref=22, minBit 3, minWin=26, winSum=440
921 13:38:22.587814 TX Vref=24, minBit 7, minWin=26, winSum=445
922 13:38:22.588102 TX Vref=26, minBit 1, minWin=27, winSum=448
923 13:38:22.588243 TX Vref=28, minBit 0, minWin=27, winSum=447
924 13:38:22.588381 TX Vref=30, minBit 4, minWin=27, winSum=453
925 13:38:22.588522 TX Vref=32, minBit 8, minWin=27, winSum=451
926 13:38:22.588660 [TxChooseVref] Worse bit 4, Min win 27, Win sum 453, Final Vref 30
927 13:38:22.588751
928 13:38:22.588811 Final TX Range 1 Vref 30
929 13:38:22.588886
930 13:38:22.588991 ==
931 13:38:22.589081 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:38:22.589170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:38:22.589266 ==
934 13:38:22.589329
935 13:38:22.589392
936 13:38:22.589449 TX Vref Scan disable
937 13:38:22.589505 == TX Byte 0 ==
938 13:38:22.589561 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
939 13:38:22.589617 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
940 13:38:22.589673 == TX Byte 1 ==
941 13:38:22.589729 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
942 13:38:22.589784 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
943 13:38:22.589855
944 13:38:22.589913 [DATLAT]
945 13:38:22.589969 Freq=800, CH0 RK0
946 13:38:22.590025
947 13:38:22.590080 DATLAT Default: 0xa
948 13:38:22.590136 0, 0xFFFF, sum = 0
949 13:38:22.590193 1, 0xFFFF, sum = 0
950 13:38:22.590249 2, 0xFFFF, sum = 0
951 13:38:22.590305 3, 0xFFFF, sum = 0
952 13:38:22.590367 4, 0xFFFF, sum = 0
953 13:38:22.590445 5, 0xFFFF, sum = 0
954 13:38:22.590503 6, 0xFFFF, sum = 0
955 13:38:22.590561 7, 0xFFFF, sum = 0
956 13:38:22.590617 8, 0xFFFF, sum = 0
957 13:38:22.590673 9, 0x0, sum = 1
958 13:38:22.590730 10, 0x0, sum = 2
959 13:38:22.590786 11, 0x0, sum = 3
960 13:38:22.590850 12, 0x0, sum = 4
961 13:38:22.590907 best_step = 10
962 13:38:22.590976
963 13:38:22.591034 ==
964 13:38:22.591090 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:38:22.591147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 13:38:22.591203 ==
967 13:38:22.591259 RX Vref Scan: 1
968 13:38:22.591314
969 13:38:22.591378 Set Vref Range= 32 -> 127
970 13:38:22.591435
971 13:38:22.591509 RX Vref 32 -> 127, step: 1
972 13:38:22.591566
973 13:38:22.591621 RX Delay -111 -> 252, step: 8
974 13:38:22.591677
975 13:38:22.591732 Set Vref, RX VrefLevel [Byte0]: 32
976 13:38:22.591788 [Byte1]: 32
977 13:38:22.591844
978 13:38:22.591904 Set Vref, RX VrefLevel [Byte0]: 33
979 13:38:22.591974 [Byte1]: 33
980 13:38:22.592033
981 13:38:22.592088 Set Vref, RX VrefLevel [Byte0]: 34
982 13:38:22.592144 [Byte1]: 34
983 13:38:22.592199
984 13:38:22.592254 Set Vref, RX VrefLevel [Byte0]: 35
985 13:38:22.592310 [Byte1]: 35
986 13:38:22.592365
987 13:38:22.592428 Set Vref, RX VrefLevel [Byte0]: 36
988 13:38:22.592502 [Byte1]: 36
989 13:38:22.592560
990 13:38:22.592615 Set Vref, RX VrefLevel [Byte0]: 37
991 13:38:22.592671 [Byte1]: 37
992 13:38:22.592726
993 13:38:22.592781 Set Vref, RX VrefLevel [Byte0]: 38
994 13:38:22.592837 [Byte1]: 38
995 13:38:22.592892
996 13:38:22.592958 Set Vref, RX VrefLevel [Byte0]: 39
997 13:38:22.593024 [Byte1]: 39
998 13:38:22.593080
999 13:38:22.593135 Set Vref, RX VrefLevel [Byte0]: 40
1000 13:38:22.593190 [Byte1]: 40
1001 13:38:22.593245
1002 13:38:22.593310 Set Vref, RX VrefLevel [Byte0]: 41
1003 13:38:22.593365 [Byte1]: 41
1004 13:38:22.593423
1005 13:38:22.593500 Set Vref, RX VrefLevel [Byte0]: 42
1006 13:38:22.593559 [Byte1]: 42
1007 13:38:22.593614
1008 13:38:22.593669 Set Vref, RX VrefLevel [Byte0]: 43
1009 13:38:22.593725 [Byte1]: 43
1010 13:38:22.593780
1011 13:38:22.593836 Set Vref, RX VrefLevel [Byte0]: 44
1012 13:38:22.593891 [Byte1]: 44
1013 13:38:22.593946
1014 13:38:22.594024 Set Vref, RX VrefLevel [Byte0]: 45
1015 13:38:22.594082 [Byte1]: 45
1016 13:38:22.594137
1017 13:38:22.594193 Set Vref, RX VrefLevel [Byte0]: 46
1018 13:38:22.594250 [Byte1]: 46
1019 13:38:22.594306
1020 13:38:22.594361 Set Vref, RX VrefLevel [Byte0]: 47
1021 13:38:22.594416 [Byte1]: 47
1022 13:38:22.594478
1023 13:38:22.594545 Set Vref, RX VrefLevel [Byte0]: 48
1024 13:38:22.594604 [Byte1]: 48
1025 13:38:22.594665
1026 13:38:22.594722 Set Vref, RX VrefLevel [Byte0]: 49
1027 13:38:22.594778 [Byte1]: 49
1028 13:38:22.594833
1029 13:38:22.594889 Set Vref, RX VrefLevel [Byte0]: 50
1030 13:38:22.594945 [Byte1]: 50
1031 13:38:22.595018
1032 13:38:22.595077 Set Vref, RX VrefLevel [Byte0]: 51
1033 13:38:22.595133 [Byte1]: 51
1034 13:38:22.595188
1035 13:38:22.595243 Set Vref, RX VrefLevel [Byte0]: 52
1036 13:38:22.595299 [Byte1]: 52
1037 13:38:22.595353
1038 13:38:22.595408 Set Vref, RX VrefLevel [Byte0]: 53
1039 13:38:22.595463 [Byte1]: 53
1040 13:38:22.595540
1041 13:38:22.595597 Set Vref, RX VrefLevel [Byte0]: 54
1042 13:38:22.595653 [Byte1]: 54
1043 13:38:22.595708
1044 13:38:22.595763 Set Vref, RX VrefLevel [Byte0]: 55
1045 13:38:22.595818 [Byte1]: 55
1046 13:38:22.595873
1047 13:38:22.595928 Set Vref, RX VrefLevel [Byte0]: 56
1048 13:38:22.595983 [Byte1]: 56
1049 13:38:22.596059
1050 13:38:22.596116 Set Vref, RX VrefLevel [Byte0]: 57
1051 13:38:22.596171 [Byte1]: 57
1052 13:38:22.596226
1053 13:38:22.596280 Set Vref, RX VrefLevel [Byte0]: 58
1054 13:38:22.596335 [Byte1]: 58
1055 13:38:22.596390
1056 13:38:22.596444 Set Vref, RX VrefLevel [Byte0]: 59
1057 13:38:22.596507 [Byte1]: 59
1058 13:38:22.596571
1059 13:38:22.596627 Set Vref, RX VrefLevel [Byte0]: 60
1060 13:38:22.596682 [Byte1]: 60
1061 13:38:22.596737
1062 13:38:22.596792 Set Vref, RX VrefLevel [Byte0]: 61
1063 13:38:22.596847 [Byte1]: 61
1064 13:38:22.596901
1065 13:38:22.596955 Set Vref, RX VrefLevel [Byte0]: 62
1066 13:38:22.597014 [Byte1]: 62
1067 13:38:22.597086
1068 13:38:22.597143 Set Vref, RX VrefLevel [Byte0]: 63
1069 13:38:22.597198 [Byte1]: 63
1070 13:38:22.597253
1071 13:38:22.597318 Set Vref, RX VrefLevel [Byte0]: 64
1072 13:38:22.597374 [Byte1]: 64
1073 13:38:22.597428
1074 13:38:22.597484 Set Vref, RX VrefLevel [Byte0]: 65
1075 13:38:22.597552 [Byte1]: 65
1076 13:38:22.597612
1077 13:38:22.597668 Set Vref, RX VrefLevel [Byte0]: 66
1078 13:38:22.597723 [Byte1]: 66
1079 13:38:22.597777
1080 13:38:22.597837 Set Vref, RX VrefLevel [Byte0]: 67
1081 13:38:22.597895 [Byte1]: 67
1082 13:38:22.597950
1083 13:38:22.598005 Set Vref, RX VrefLevel [Byte0]: 68
1084 13:38:22.598082 [Byte1]: 68
1085 13:38:22.598139
1086 13:38:22.598194 Set Vref, RX VrefLevel [Byte0]: 69
1087 13:38:22.598249 [Byte1]: 69
1088 13:38:22.598303
1089 13:38:22.598359 Set Vref, RX VrefLevel [Byte0]: 70
1090 13:38:22.598620 [Byte1]: 70
1091 13:38:22.598757
1092 13:38:22.598887 Set Vref, RX VrefLevel [Byte0]: 71
1093 13:38:22.599026 [Byte1]: 71
1094 13:38:22.599161
1095 13:38:22.599293 Set Vref, RX VrefLevel [Byte0]: 72
1096 13:38:22.599356 [Byte1]: 72
1097 13:38:22.599413
1098 13:38:22.599470 Set Vref, RX VrefLevel [Byte0]: 73
1099 13:38:22.599526 [Byte1]: 73
1100 13:38:22.599585
1101 13:38:22.599643 Final RX Vref Byte 0 = 55 to rank0
1102 13:38:22.599699 Final RX Vref Byte 1 = 60 to rank0
1103 13:38:22.599754 Final RX Vref Byte 0 = 55 to rank1
1104 13:38:22.599809 Final RX Vref Byte 1 = 60 to rank1==
1105 13:38:22.599866 Dram Type= 6, Freq= 0, CH_0, rank 0
1106 13:38:22.599921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1107 13:38:22.599977 ==
1108 13:38:22.600031 DQS Delay:
1109 13:38:22.600089 DQS0 = 0, DQS1 = 0
1110 13:38:22.600145 DQM Delay:
1111 13:38:22.600199 DQM0 = 87, DQM1 = 76
1112 13:38:22.600254 DQ Delay:
1113 13:38:22.600308 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =80
1114 13:38:22.600363 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1115 13:38:22.600417 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1116 13:38:22.600471 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1117 13:38:22.600526
1118 13:38:22.600583
1119 13:38:22.600668 [DQSOSCAuto] RK0, (LSB)MR18= 0x322c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1120 13:38:22.600752 CH0 RK0: MR19=606, MR18=322C
1121 13:38:22.600835 CH0_RK0: MR19=0x606, MR18=0x322C, DQSOSC=397, MR23=63, INC=93, DEC=62
1122 13:38:22.600894
1123 13:38:22.600951 ----->DramcWriteLeveling(PI) begin...
1124 13:38:22.601008 ==
1125 13:38:22.601063 Dram Type= 6, Freq= 0, CH_0, rank 1
1126 13:38:22.601139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 13:38:22.601225 ==
1128 13:38:22.601312 Write leveling (Byte 0): 33 => 33
1129 13:38:22.601370 Write leveling (Byte 1): 26 => 26
1130 13:38:22.601426 DramcWriteLeveling(PI) end<-----
1131 13:38:22.601481
1132 13:38:22.601536 ==
1133 13:38:22.601596 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 13:38:22.601653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 13:38:22.601709 ==
1136 13:38:22.601764 [Gating] SW mode calibration
1137 13:38:22.601837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1138 13:38:22.601909 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1139 13:38:22.601996 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1140 13:38:22.602056 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1141 13:38:22.602119 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1142 13:38:22.602176 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 13:38:22.602231 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 13:38:22.602286 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 13:38:22.602341 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 13:38:22.602396 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 13:38:22.602451 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 13:38:22.602505 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:38:22.602559 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:38:22.602621 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:38:22.602676 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:38:22.602731 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:38:22.602785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:38:22.602839 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:38:22.602893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:38:22.602948 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1157 13:38:22.603003 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:38:22.603058 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1159 13:38:22.603119 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:38:22.603175 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:38:22.603229 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:38:22.603284 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:38:22.603338 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:38:22.603393 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1165 13:38:22.603447 0 9 8 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
1166 13:38:22.603502 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1167 13:38:22.603557 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 13:38:22.603617 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 13:38:22.603673 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 13:38:22.603728 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 13:38:22.603782 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 13:38:22.603837 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1173 13:38:22.603892 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1174 13:38:22.603947 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:38:22.604001 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:38:22.604056 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:38:22.604116 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:38:22.604172 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:38:22.604227 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:38:22.604282 0 11 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1181 13:38:22.604336 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
1182 13:38:22.604391 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 13:38:22.604445 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 13:38:22.604500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 13:38:22.604554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 13:38:22.604615 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 13:38:22.604670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 13:38:22.604725 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 13:38:22.604780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1190 13:38:22.604835 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 13:38:22.605098 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 13:38:22.605236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 13:38:22.605382 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 13:38:22.605519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:38:22.605655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:38:22.605740 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:38:22.605799 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:38:22.605855 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:38:22.605911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:38:22.605966 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:38:22.606021 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:38:22.606084 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:38:22.606140 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:38:22.606195 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 13:38:22.606249 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1206 13:38:22.606304 Total UI for P1: 0, mck2ui 16
1207 13:38:22.606359 best dqsien dly found for B0: ( 0, 14, 4)
1208 13:38:22.606414 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 13:38:22.606469 Total UI for P1: 0, mck2ui 16
1210 13:38:22.606523 best dqsien dly found for B1: ( 0, 14, 6)
1211 13:38:22.606585 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1212 13:38:22.606640 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1213 13:38:22.606695
1214 13:38:22.606749 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1215 13:38:22.606804 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1216 13:38:22.606859 [Gating] SW calibration Done
1217 13:38:22.606913 ==
1218 13:38:22.606968 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 13:38:22.607023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 13:38:22.607111 ==
1221 13:38:22.607196 RX Vref Scan: 0
1222 13:38:22.607280
1223 13:38:22.607365 RX Vref 0 -> 0, step: 1
1224 13:38:22.607449
1225 13:38:22.607536 RX Delay -130 -> 252, step: 16
1226 13:38:22.607622 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1227 13:38:22.607710 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1228 13:38:22.607796 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1229 13:38:22.607881 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1230 13:38:22.607966 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1231 13:38:22.608053 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1232 13:38:22.608139 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1233 13:38:22.608223 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1234 13:38:22.608308 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1235 13:38:22.608393 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1236 13:38:22.608481 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1237 13:38:22.608575 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1238 13:38:22.608664 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1239 13:38:22.608749 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1240 13:38:22.608831 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1241 13:38:22.608924 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1242 13:38:22.609011 ==
1243 13:38:22.609099 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 13:38:22.609189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 13:38:22.609285 ==
1246 13:38:22.609344 DQS Delay:
1247 13:38:22.609400 DQS0 = 0, DQS1 = 0
1248 13:38:22.609455 DQM Delay:
1249 13:38:22.609510 DQM0 = 86, DQM1 = 77
1250 13:38:22.609579 DQ Delay:
1251 13:38:22.609644 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1252 13:38:22.609700 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1253 13:38:22.609756 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1254 13:38:22.609811 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 13:38:22.609866
1256 13:38:22.609920
1257 13:38:22.609974 ==
1258 13:38:22.610028 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 13:38:22.610090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 13:38:22.610145 ==
1261 13:38:22.610200
1262 13:38:22.610254
1263 13:38:22.610308 TX Vref Scan disable
1264 13:38:22.610363 == TX Byte 0 ==
1265 13:38:22.610417 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1266 13:38:22.610472 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1267 13:38:22.610527 == TX Byte 1 ==
1268 13:38:22.610586 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1269 13:38:22.610642 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1270 13:38:22.610696 ==
1271 13:38:22.610751 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 13:38:22.610806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 13:38:22.610861 ==
1274 13:38:22.610915 TX Vref=22, minBit 1, minWin=27, winSum=442
1275 13:38:22.610970 TX Vref=24, minBit 1, minWin=27, winSum=448
1276 13:38:22.611025 TX Vref=26, minBit 1, minWin=27, winSum=450
1277 13:38:22.611084 TX Vref=28, minBit 9, minWin=27, winSum=453
1278 13:38:22.611140 TX Vref=30, minBit 0, minWin=28, winSum=454
1279 13:38:22.611195 TX Vref=32, minBit 2, minWin=27, winSum=447
1280 13:38:22.611249 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1281 13:38:22.611304
1282 13:38:22.611358 Final TX Range 1 Vref 30
1283 13:38:22.611413
1284 13:38:22.611468 ==
1285 13:38:22.611522 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 13:38:22.611576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 13:38:22.611639 ==
1288 13:38:22.611694
1289 13:38:22.611748
1290 13:38:22.611802 TX Vref Scan disable
1291 13:38:22.611857 == TX Byte 0 ==
1292 13:38:22.611911 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1293 13:38:22.611965 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1294 13:38:22.612020 == TX Byte 1 ==
1295 13:38:22.612100 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1296 13:38:22.612165 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1297 13:38:22.612220
1298 13:38:22.612275 [DATLAT]
1299 13:38:22.612329 Freq=800, CH0 RK1
1300 13:38:22.612383
1301 13:38:22.612437 DATLAT Default: 0xa
1302 13:38:22.612490 0, 0xFFFF, sum = 0
1303 13:38:22.612545 1, 0xFFFF, sum = 0
1304 13:38:22.612600 2, 0xFFFF, sum = 0
1305 13:38:22.612661 3, 0xFFFF, sum = 0
1306 13:38:22.612717 4, 0xFFFF, sum = 0
1307 13:38:22.612772 5, 0xFFFF, sum = 0
1308 13:38:22.612827 6, 0xFFFF, sum = 0
1309 13:38:22.612881 7, 0xFFFF, sum = 0
1310 13:38:22.612935 8, 0xFFFF, sum = 0
1311 13:38:22.612990 9, 0x0, sum = 1
1312 13:38:22.613044 10, 0x0, sum = 2
1313 13:38:22.613098 11, 0x0, sum = 3
1314 13:38:22.613152 12, 0x0, sum = 4
1315 13:38:22.613242 best_step = 10
1316 13:38:22.613312
1317 13:38:22.613368 ==
1318 13:38:22.613423 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 13:38:22.613478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 13:38:22.613533 ==
1321 13:38:22.613586 RX Vref Scan: 0
1322 13:38:22.613640
1323 13:38:22.613695 RX Vref 0 -> 0, step: 1
1324 13:38:22.613756
1325 13:38:22.613811 RX Delay -95 -> 252, step: 8
1326 13:38:22.613865 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1327 13:38:22.614127 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1328 13:38:22.614263 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1329 13:38:22.614399 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1330 13:38:22.614532 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1331 13:38:22.614664 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1332 13:38:22.614768 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1333 13:38:22.614858 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1334 13:38:22.614944 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1335 13:38:22.615030 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1336 13:38:22.615115 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1337 13:38:22.615200 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1338 13:38:22.615284 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1339 13:38:22.615371 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1340 13:38:22.615456 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1341 13:38:22.615546 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1342 13:38:22.615641 ==
1343 13:38:22.615726 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 13:38:22.615811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 13:38:22.615886 ==
1346 13:38:22.615942 DQS Delay:
1347 13:38:22.615997 DQS0 = 0, DQS1 = 0
1348 13:38:22.616058 DQM Delay:
1349 13:38:22.616147 DQM0 = 86, DQM1 = 76
1350 13:38:22.616234 DQ Delay:
1351 13:38:22.616318 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1352 13:38:22.616403 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1353 13:38:22.616493 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1354 13:38:22.616580 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1355 13:38:22.616664
1356 13:38:22.616748
1357 13:38:22.616822 [DQSOSCAuto] RK1, (LSB)MR18= 0x2926, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1358 13:38:22.616880 CH0 RK1: MR19=606, MR18=2926
1359 13:38:22.616964 CH0_RK1: MR19=0x606, MR18=0x2926, DQSOSC=399, MR23=63, INC=92, DEC=61
1360 13:38:22.617049 [RxdqsGatingPostProcess] freq 800
1361 13:38:22.617133 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1362 13:38:22.617218 Pre-setting of DQS Precalculation
1363 13:38:22.617307 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1364 13:38:22.617364 ==
1365 13:38:22.617419 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 13:38:22.617480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 13:38:22.617534 ==
1368 13:38:22.617589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1369 13:38:22.617644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1370 13:38:22.617698 [CA 0] Center 36 (6~67) winsize 62
1371 13:38:22.617752 [CA 1] Center 36 (6~67) winsize 62
1372 13:38:22.617806 [CA 2] Center 35 (5~65) winsize 61
1373 13:38:22.617862 [CA 3] Center 34 (4~65) winsize 62
1374 13:38:22.617917 [CA 4] Center 34 (4~65) winsize 62
1375 13:38:22.617976 [CA 5] Center 34 (3~65) winsize 63
1376 13:38:22.618031
1377 13:38:22.618085 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1378 13:38:22.618139
1379 13:38:22.618193 [CATrainingPosCal] consider 1 rank data
1380 13:38:22.618247 u2DelayCellTimex100 = 270/100 ps
1381 13:38:22.618301 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1382 13:38:22.618355 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1383 13:38:22.618409 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1384 13:38:22.618463 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1385 13:38:22.618519 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1386 13:38:22.618577 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1387 13:38:22.618631
1388 13:38:22.618684 CA PerBit enable=1, Macro0, CA PI delay=34
1389 13:38:22.618738
1390 13:38:22.618792 [CBTSetCACLKResult] CA Dly = 34
1391 13:38:22.618845 CS Dly: 4 (0~35)
1392 13:38:22.618899 ==
1393 13:38:22.618966 Dram Type= 6, Freq= 0, CH_1, rank 1
1394 13:38:22.619034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 13:38:22.619095 ==
1396 13:38:22.619151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 13:38:22.619206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 13:38:22.619261 [CA 0] Center 36 (6~67) winsize 62
1399 13:38:22.619315 [CA 1] Center 36 (6~67) winsize 62
1400 13:38:22.619368 [CA 2] Center 34 (4~65) winsize 62
1401 13:38:22.619421 [CA 3] Center 34 (3~65) winsize 63
1402 13:38:22.619474 [CA 4] Center 34 (3~65) winsize 63
1403 13:38:22.619527 [CA 5] Center 33 (3~64) winsize 62
1404 13:38:22.619585
1405 13:38:22.619640 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 13:38:22.619694
1407 13:38:22.619749 [CATrainingPosCal] consider 2 rank data
1408 13:38:22.619803 u2DelayCellTimex100 = 270/100 ps
1409 13:38:22.619857 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1410 13:38:22.619911 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 13:38:22.619966 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1412 13:38:22.620021 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 13:38:22.620076 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 13:38:22.620134 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 13:38:22.620188
1416 13:38:22.620242 CA PerBit enable=1, Macro0, CA PI delay=33
1417 13:38:22.620296
1418 13:38:22.620349 [CBTSetCACLKResult] CA Dly = 33
1419 13:38:22.620403 CS Dly: 5 (0~37)
1420 13:38:22.620490
1421 13:38:22.620547 ----->DramcWriteLeveling(PI) begin...
1422 13:38:22.620607 ==
1423 13:38:22.620664 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 13:38:22.620718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 13:38:22.620773 ==
1426 13:38:22.620827 Write leveling (Byte 0): 25 => 25
1427 13:38:22.620881 Write leveling (Byte 1): 29 => 29
1428 13:38:22.620934 DramcWriteLeveling(PI) end<-----
1429 13:38:22.620988
1430 13:38:22.621041 ==
1431 13:38:22.621095 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 13:38:22.621183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 13:38:22.621273 ==
1434 13:38:22.621339 [Gating] SW mode calibration
1435 13:38:22.621417 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1436 13:38:22.621475 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1437 13:38:22.621530 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1438 13:38:22.621585 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1439 13:38:22.621644 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 13:38:22.621700 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 13:38:22.621754 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 13:38:22.621808 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 13:38:22.621862 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 13:38:22.622128 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:38:22.622270 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 13:38:22.622407 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:38:22.622539 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:38:22.622672 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:38:22.622745 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:38:22.622804 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:38:22.622860 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:38:22.622914 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:38:22.622969 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1454 13:38:22.623023 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1455 13:38:22.623077 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:38:22.623131 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:38:22.623185 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:38:22.623247 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:38:22.623301 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:38:22.623356 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:38:22.623409 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:38:22.623463 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:38:22.623517 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1464 13:38:22.623571 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 13:38:22.623625 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 13:38:22.623679 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 13:38:22.623738 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 13:38:22.623793 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 13:38:22.623847 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 13:38:22.623901 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
1471 13:38:22.623956 0 10 8 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
1472 13:38:22.624010 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:38:22.624064 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:38:22.624117 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:38:22.624172 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:38:22.624226 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:38:22.624286 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:38:22.624344 0 11 4 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
1479 13:38:22.624431 0 11 8 | B1->B0 | 3d3d 4141 | 1 0 | (0 0) (0 0)
1480 13:38:22.624517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 13:38:22.624602 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 13:38:22.624683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 13:38:22.624772 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 13:38:22.624862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 13:38:22.624948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 13:38:22.625033 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1487 13:38:22.625118 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 13:38:22.625202 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 13:38:22.625299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 13:38:22.625388 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 13:38:22.625473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 13:38:22.625557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 13:38:22.625642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 13:38:22.625727 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:38:22.625811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:38:22.625900 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:38:22.625959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:38:22.626014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:38:22.626069 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:38:22.626123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:38:22.626177 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:38:22.626232 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 13:38:22.626285 Total UI for P1: 0, mck2ui 16
1504 13:38:22.626341 best dqsien dly found for B0: ( 0, 14, 2)
1505 13:38:22.626408 Total UI for P1: 0, mck2ui 16
1506 13:38:22.626471 best dqsien dly found for B1: ( 0, 14, 2)
1507 13:38:22.626526 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1508 13:38:22.626580 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1509 13:38:22.626634
1510 13:38:22.626689 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1511 13:38:22.626743 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1512 13:38:22.626797 [Gating] SW calibration Done
1513 13:38:22.626851 ==
1514 13:38:22.626905 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 13:38:22.626960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 13:38:22.627021 ==
1517 13:38:22.627075 RX Vref Scan: 0
1518 13:38:22.627130
1519 13:38:22.627185 RX Vref 0 -> 0, step: 1
1520 13:38:22.627239
1521 13:38:22.627293 RX Delay -130 -> 252, step: 16
1522 13:38:22.627347 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1523 13:38:22.627402 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1524 13:38:22.627456 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1525 13:38:22.627510 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1526 13:38:22.627569 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1527 13:38:22.627623 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1528 13:38:22.627678 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1529 13:38:22.627732 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1530 13:38:22.627785 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1531 13:38:22.627839 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1532 13:38:22.627893 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1533 13:38:22.627947 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1534 13:38:22.628205 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1535 13:38:22.628342 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1536 13:38:22.628476 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1537 13:38:22.628609 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1538 13:38:22.628742 ==
1539 13:38:22.628864 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 13:38:22.628924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 13:38:22.628981 ==
1542 13:38:22.629062 DQS Delay:
1543 13:38:22.629137 DQS0 = 0, DQS1 = 0
1544 13:38:22.629228 DQM Delay:
1545 13:38:22.629312 DQM0 = 86, DQM1 = 78
1546 13:38:22.629370 DQ Delay:
1547 13:38:22.629425 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1548 13:38:22.629480 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =77
1549 13:38:22.629535 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1550 13:38:22.629594 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1551 13:38:22.629650
1552 13:38:22.629704
1553 13:38:22.629758 ==
1554 13:38:22.629811 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 13:38:22.629865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 13:38:22.629920 ==
1557 13:38:22.629975
1558 13:38:22.630029
1559 13:38:22.630084 TX Vref Scan disable
1560 13:38:22.630143 == TX Byte 0 ==
1561 13:38:22.630197 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1562 13:38:22.630278 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1563 13:38:22.630338 == TX Byte 1 ==
1564 13:38:22.630392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1565 13:38:22.630446 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1566 13:38:22.630500 ==
1567 13:38:22.630554 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 13:38:22.630613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 13:38:22.630687 ==
1570 13:38:22.630747 TX Vref=22, minBit 5, minWin=27, winSum=445
1571 13:38:22.630818 TX Vref=24, minBit 4, minWin=27, winSum=446
1572 13:38:22.630874 TX Vref=26, minBit 6, minWin=27, winSum=453
1573 13:38:22.630952 TX Vref=28, minBit 0, minWin=28, winSum=459
1574 13:38:22.631044 TX Vref=30, minBit 6, minWin=27, winSum=456
1575 13:38:22.631134 TX Vref=32, minBit 0, minWin=27, winSum=453
1576 13:38:22.631229 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1577 13:38:22.631314
1578 13:38:22.631398 Final TX Range 1 Vref 28
1579 13:38:22.631482
1580 13:38:22.631566 ==
1581 13:38:22.631653 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 13:38:22.631738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 13:38:22.631822 ==
1584 13:38:22.631906
1585 13:38:22.631988
1586 13:38:22.632071 TX Vref Scan disable
1587 13:38:22.632158 == TX Byte 0 ==
1588 13:38:22.632248 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1589 13:38:22.632320 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1590 13:38:22.632376 == TX Byte 1 ==
1591 13:38:22.632430 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 13:38:22.632498 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 13:38:22.632553
1594 13:38:22.632609 [DATLAT]
1595 13:38:22.632668 Freq=800, CH1 RK0
1596 13:38:22.632723
1597 13:38:22.632776 DATLAT Default: 0xa
1598 13:38:22.632834 0, 0xFFFF, sum = 0
1599 13:38:22.632926 1, 0xFFFF, sum = 0
1600 13:38:22.633015 2, 0xFFFF, sum = 0
1601 13:38:22.633101 3, 0xFFFF, sum = 0
1602 13:38:22.633185 4, 0xFFFF, sum = 0
1603 13:38:22.633281 5, 0xFFFF, sum = 0
1604 13:38:22.633342 6, 0xFFFF, sum = 0
1605 13:38:22.633399 7, 0xFFFF, sum = 0
1606 13:38:22.633455 8, 0xFFFF, sum = 0
1607 13:38:22.633510 9, 0x0, sum = 1
1608 13:38:22.633566 10, 0x0, sum = 2
1609 13:38:22.633623 11, 0x0, sum = 3
1610 13:38:22.633681 12, 0x0, sum = 4
1611 13:38:22.633736 best_step = 10
1612 13:38:22.633790
1613 13:38:22.633844 ==
1614 13:38:22.633898 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 13:38:22.633952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 13:38:22.634006 ==
1617 13:38:22.634060 RX Vref Scan: 1
1618 13:38:22.634114
1619 13:38:22.634172 Set Vref Range= 32 -> 127
1620 13:38:22.634226
1621 13:38:22.634280 RX Vref 32 -> 127, step: 1
1622 13:38:22.634334
1623 13:38:22.634388 RX Delay -95 -> 252, step: 8
1624 13:38:22.634442
1625 13:38:22.634495 Set Vref, RX VrefLevel [Byte0]: 32
1626 13:38:22.634549 [Byte1]: 32
1627 13:38:22.634603
1628 13:38:22.634656 Set Vref, RX VrefLevel [Byte0]: 33
1629 13:38:22.634718 [Byte1]: 33
1630 13:38:22.634772
1631 13:38:22.634826 Set Vref, RX VrefLevel [Byte0]: 34
1632 13:38:22.634880 [Byte1]: 34
1633 13:38:22.634933
1634 13:38:22.634987 Set Vref, RX VrefLevel [Byte0]: 35
1635 13:38:22.635041 [Byte1]: 35
1636 13:38:22.635095
1637 13:38:22.635148 Set Vref, RX VrefLevel [Byte0]: 36
1638 13:38:22.635210 [Byte1]: 36
1639 13:38:22.635264
1640 13:38:22.635319 Set Vref, RX VrefLevel [Byte0]: 37
1641 13:38:22.635372 [Byte1]: 37
1642 13:38:22.635426
1643 13:38:22.635480 Set Vref, RX VrefLevel [Byte0]: 38
1644 13:38:22.635534 [Byte1]: 38
1645 13:38:22.635616
1646 13:38:22.635674 Set Vref, RX VrefLevel [Byte0]: 39
1647 13:38:22.635739 [Byte1]: 39
1648 13:38:22.635794
1649 13:38:22.635848 Set Vref, RX VrefLevel [Byte0]: 40
1650 13:38:22.635902 [Byte1]: 40
1651 13:38:22.635956
1652 13:38:22.636010 Set Vref, RX VrefLevel [Byte0]: 41
1653 13:38:22.636064 [Byte1]: 41
1654 13:38:22.636117
1655 13:38:22.636171 Set Vref, RX VrefLevel [Byte0]: 42
1656 13:38:22.636231 [Byte1]: 42
1657 13:38:22.636284
1658 13:38:22.636338 Set Vref, RX VrefLevel [Byte0]: 43
1659 13:38:22.636396 [Byte1]: 43
1660 13:38:22.636481
1661 13:38:22.636569 Set Vref, RX VrefLevel [Byte0]: 44
1662 13:38:22.636626 [Byte1]: 44
1663 13:38:22.636681
1664 13:38:22.636741 Set Vref, RX VrefLevel [Byte0]: 45
1665 13:38:22.636795 [Byte1]: 45
1666 13:38:22.636849
1667 13:38:22.636903 Set Vref, RX VrefLevel [Byte0]: 46
1668 13:38:22.636957 [Byte1]: 46
1669 13:38:22.637010
1670 13:38:22.637064 Set Vref, RX VrefLevel [Byte0]: 47
1671 13:38:22.637117 [Byte1]: 47
1672 13:38:22.637171
1673 13:38:22.637244 Set Vref, RX VrefLevel [Byte0]: 48
1674 13:38:22.637311 [Byte1]: 48
1675 13:38:22.637367
1676 13:38:22.637421 Set Vref, RX VrefLevel [Byte0]: 49
1677 13:38:22.637475 [Byte1]: 49
1678 13:38:22.637529
1679 13:38:22.637583 Set Vref, RX VrefLevel [Byte0]: 50
1680 13:38:22.637637 [Byte1]: 50
1681 13:38:22.637690
1682 13:38:22.637751 Set Vref, RX VrefLevel [Byte0]: 51
1683 13:38:22.637806 [Byte1]: 51
1684 13:38:22.637860
1685 13:38:22.637914 Set Vref, RX VrefLevel [Byte0]: 52
1686 13:38:22.637968 [Byte1]: 52
1687 13:38:22.638022
1688 13:38:22.638076 Set Vref, RX VrefLevel [Byte0]: 53
1689 13:38:22.638159 [Byte1]: 53
1690 13:38:22.638218
1691 13:38:22.638277 Set Vref, RX VrefLevel [Byte0]: 54
1692 13:38:22.638333 [Byte1]: 54
1693 13:38:22.638387
1694 13:38:22.638441 Set Vref, RX VrefLevel [Byte0]: 55
1695 13:38:22.638494 [Byte1]: 55
1696 13:38:22.638548
1697 13:38:22.638635 Set Vref, RX VrefLevel [Byte0]: 56
1698 13:38:22.638692 [Byte1]: 56
1699 13:38:22.638954
1700 13:38:22.639088 Set Vref, RX VrefLevel [Byte0]: 57
1701 13:38:22.639221 [Byte1]: 57
1702 13:38:22.639353
1703 13:38:22.639485 Set Vref, RX VrefLevel [Byte0]: 58
1704 13:38:22.639580 [Byte1]: 58
1705 13:38:22.639638
1706 13:38:22.639693 Set Vref, RX VrefLevel [Byte0]: 59
1707 13:38:22.639748 [Byte1]: 59
1708 13:38:22.639803
1709 13:38:22.639864 Set Vref, RX VrefLevel [Byte0]: 60
1710 13:38:22.639918 [Byte1]: 60
1711 13:38:22.639972
1712 13:38:22.640026 Set Vref, RX VrefLevel [Byte0]: 61
1713 13:38:22.640080 [Byte1]: 61
1714 13:38:22.640133
1715 13:38:22.640187 Set Vref, RX VrefLevel [Byte0]: 62
1716 13:38:22.640241 [Byte1]: 62
1717 13:38:22.640295
1718 13:38:22.640352 Set Vref, RX VrefLevel [Byte0]: 63
1719 13:38:22.640408 [Byte1]: 63
1720 13:38:22.640461
1721 13:38:22.640514 Set Vref, RX VrefLevel [Byte0]: 64
1722 13:38:22.640568 [Byte1]: 64
1723 13:38:22.640621
1724 13:38:22.640675 Set Vref, RX VrefLevel [Byte0]: 65
1725 13:38:22.640728 [Byte1]: 65
1726 13:38:22.640782
1727 13:38:22.640835 Set Vref, RX VrefLevel [Byte0]: 66
1728 13:38:22.640900 [Byte1]: 66
1729 13:38:22.640985
1730 13:38:22.641069 Set Vref, RX VrefLevel [Byte0]: 67
1731 13:38:22.641153 [Byte1]: 67
1732 13:38:22.641243
1733 13:38:22.641335 Set Vref, RX VrefLevel [Byte0]: 68
1734 13:38:22.641396 [Byte1]: 68
1735 13:38:22.641458
1736 13:38:22.641557 Set Vref, RX VrefLevel [Byte0]: 69
1737 13:38:22.641649 [Byte1]: 69
1738 13:38:22.641736
1739 13:38:22.641826 Set Vref, RX VrefLevel [Byte0]: 70
1740 13:38:22.641918 [Byte1]: 70
1741 13:38:22.642017
1742 13:38:22.642106 Set Vref, RX VrefLevel [Byte0]: 71
1743 13:38:22.642198 [Byte1]: 71
1744 13:38:22.642290
1745 13:38:22.642376 Set Vref, RX VrefLevel [Byte0]: 72
1746 13:38:22.642463 [Byte1]: 72
1747 13:38:22.642548
1748 13:38:22.642632 Set Vref, RX VrefLevel [Byte0]: 73
1749 13:38:22.642716 [Byte1]: 73
1750 13:38:22.642799
1751 13:38:22.642883 Set Vref, RX VrefLevel [Byte0]: 74
1752 13:38:22.642967 [Byte1]: 74
1753 13:38:22.643051
1754 13:38:22.643134 Set Vref, RX VrefLevel [Byte0]: 75
1755 13:38:22.643218 [Byte1]: 75
1756 13:38:22.643301
1757 13:38:22.643385 Final RX Vref Byte 0 = 53 to rank0
1758 13:38:22.643469 Final RX Vref Byte 1 = 52 to rank0
1759 13:38:22.643554 Final RX Vref Byte 0 = 53 to rank1
1760 13:38:22.643638 Final RX Vref Byte 1 = 52 to rank1==
1761 13:38:22.643722 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 13:38:22.643807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 13:38:22.643891 ==
1764 13:38:22.643948 DQS Delay:
1765 13:38:22.644002 DQS0 = 0, DQS1 = 0
1766 13:38:22.644055 DQM Delay:
1767 13:38:22.644110 DQM0 = 84, DQM1 = 80
1768 13:38:22.644164 DQ Delay:
1769 13:38:22.644218 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1770 13:38:22.644272 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1771 13:38:22.644328 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1772 13:38:22.644382 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1773 13:38:22.644441
1774 13:38:22.644495
1775 13:38:22.644549 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
1776 13:38:22.644605 CH1 RK0: MR19=606, MR18=1B2F
1777 13:38:22.644659 CH1_RK0: MR19=0x606, MR18=0x1B2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1778 13:38:22.644714
1779 13:38:22.644768 ----->DramcWriteLeveling(PI) begin...
1780 13:38:22.644823 ==
1781 13:38:22.644876 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 13:38:22.644937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 13:38:22.644992 ==
1784 13:38:22.645045 Write leveling (Byte 0): 24 => 24
1785 13:38:22.645099 Write leveling (Byte 1): 30 => 30
1786 13:38:22.645153 DramcWriteLeveling(PI) end<-----
1787 13:38:22.645206
1788 13:38:22.645270 ==
1789 13:38:22.645326 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 13:38:22.645381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 13:38:22.645439 ==
1792 13:38:22.645494 [Gating] SW mode calibration
1793 13:38:22.645548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 13:38:22.645603 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 13:38:22.645657 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1796 13:38:22.645712 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1797 13:38:22.645766 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1798 13:38:22.645820 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 13:38:22.645874 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 13:38:22.645932 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 13:38:22.645987 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 13:38:22.646042 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 13:38:22.646095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 13:38:22.646148 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 13:38:22.646202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:38:22.646256 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:38:22.646310 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:38:22.646364 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:38:22.646418 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:38:22.646477 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:38:22.646532 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1812 13:38:22.646586 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1813 13:38:22.646640 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1814 13:38:22.646694 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:38:22.646747 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:38:22.646801 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:38:22.646854 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:38:22.646908 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:38:22.646962 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:38:22.647022 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1821 13:38:22.647076 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1822 13:38:22.647130 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 13:38:22.647184 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 13:38:22.647446 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 13:38:22.647585 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 13:38:22.647719 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 13:38:22.647850 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1828 13:38:22.647983 0 10 4 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
1829 13:38:22.648057 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1830 13:38:22.648115 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:38:22.648169 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:38:22.648224 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:38:22.648278 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:38:22.648332 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:38:22.648386 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1836 13:38:22.648440 0 11 4 | B1->B0 | 2929 3939 | 0 0 | (0 0) (0 0)
1837 13:38:22.648494 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1838 13:38:22.648553 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 13:38:22.648609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 13:38:22.648663 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 13:38:22.648719 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 13:38:22.648773 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 13:38:22.648827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1844 13:38:22.648881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 13:38:22.648935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1846 13:38:22.648988 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 13:38:22.649042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 13:38:22.649120 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 13:38:22.649205 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 13:38:22.649293 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 13:38:22.649349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 13:38:22.649404 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 13:38:22.649458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:38:22.649512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:38:22.649566 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:38:22.649627 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:38:22.649682 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:38:22.649736 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:38:22.649790 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1860 13:38:22.649844 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1861 13:38:22.649898 Total UI for P1: 0, mck2ui 16
1862 13:38:22.649953 best dqsien dly found for B0: ( 0, 14, 0)
1863 13:38:22.650007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1864 13:38:22.650061 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 13:38:22.650120 Total UI for P1: 0, mck2ui 16
1866 13:38:22.650175 best dqsien dly found for B1: ( 0, 14, 6)
1867 13:38:22.650230 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1868 13:38:22.650284 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1869 13:38:22.650338
1870 13:38:22.650395 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1871 13:38:22.650486 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1872 13:38:22.650573 [Gating] SW calibration Done
1873 13:38:22.650659 ==
1874 13:38:22.650741 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 13:38:22.650819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 13:38:22.650879 ==
1877 13:38:22.650935 RX Vref Scan: 0
1878 13:38:22.650990
1879 13:38:22.651045 RX Vref 0 -> 0, step: 1
1880 13:38:22.651100
1881 13:38:22.651154 RX Delay -130 -> 252, step: 16
1882 13:38:22.651214 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1883 13:38:22.651269 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1884 13:38:22.651323 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1885 13:38:22.651378 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1886 13:38:22.651433 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1887 13:38:22.651486 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1888 13:38:22.651540 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1889 13:38:22.651594 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1890 13:38:22.651648 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1891 13:38:22.651708 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1892 13:38:22.651763 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1893 13:38:22.651824 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1894 13:38:22.651889 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1895 13:38:22.651954 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1896 13:38:22.652024 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1897 13:38:22.652092 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1898 13:38:22.652177 ==
1899 13:38:22.652265 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 13:38:22.652354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 13:38:22.652439 ==
1902 13:38:22.652522 DQS Delay:
1903 13:38:22.652580 DQS0 = 0, DQS1 = 0
1904 13:38:22.652635 DQM Delay:
1905 13:38:22.652690 DQM0 = 84, DQM1 = 80
1906 13:38:22.652766 DQ Delay:
1907 13:38:22.652826 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1908 13:38:22.652898 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1909 13:38:22.652954 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1910 13:38:22.653008 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1911 13:38:22.653082
1912 13:38:22.653166
1913 13:38:22.653272 ==
1914 13:38:22.653339 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 13:38:22.653402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 13:38:23.323904 ==
1917 13:38:23.324048
1918 13:38:23.324117
1919 13:38:23.324179 TX Vref Scan disable
1920 13:38:23.324239 == TX Byte 0 ==
1921 13:38:23.324296 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1922 13:38:23.324353 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1923 13:38:23.324410 == TX Byte 1 ==
1924 13:38:23.324474 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1925 13:38:23.324536 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1926 13:38:23.324592 ==
1927 13:38:23.324646 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 13:38:23.324702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 13:38:23.324757 ==
1930 13:38:23.324810 TX Vref=22, minBit 1, minWin=27, winSum=443
1931 13:38:23.325093 TX Vref=24, minBit 0, minWin=27, winSum=448
1932 13:38:23.325157 TX Vref=26, minBit 5, minWin=27, winSum=451
1933 13:38:23.325214 TX Vref=28, minBit 6, minWin=27, winSum=456
1934 13:38:23.325280 TX Vref=30, minBit 6, minWin=27, winSum=454
1935 13:38:23.325337 TX Vref=32, minBit 4, minWin=27, winSum=453
1936 13:38:23.325393 [TxChooseVref] Worse bit 6, Min win 27, Win sum 456, Final Vref 28
1937 13:38:23.325453
1938 13:38:23.325519 Final TX Range 1 Vref 28
1939 13:38:23.325575
1940 13:38:23.325629 ==
1941 13:38:23.325683 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 13:38:23.325737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 13:38:23.325792 ==
1944 13:38:23.325846
1945 13:38:23.325900
1946 13:38:23.325953 TX Vref Scan disable
1947 13:38:23.326026 == TX Byte 0 ==
1948 13:38:23.326094 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1949 13:38:23.326148 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1950 13:38:23.326202 == TX Byte 1 ==
1951 13:38:23.326254 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1952 13:38:23.326308 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1953 13:38:23.326360
1954 13:38:23.326413 [DATLAT]
1955 13:38:23.326465 Freq=800, CH1 RK1
1956 13:38:23.326534
1957 13:38:23.326588 DATLAT Default: 0xa
1958 13:38:23.326641 0, 0xFFFF, sum = 0
1959 13:38:23.326695 1, 0xFFFF, sum = 0
1960 13:38:23.326748 2, 0xFFFF, sum = 0
1961 13:38:23.326801 3, 0xFFFF, sum = 0
1962 13:38:23.326855 4, 0xFFFF, sum = 0
1963 13:38:23.326908 5, 0xFFFF, sum = 0
1964 13:38:23.326961 6, 0xFFFF, sum = 0
1965 13:38:23.327060 7, 0xFFFF, sum = 0
1966 13:38:23.327115 8, 0xFFFF, sum = 0
1967 13:38:23.327168 9, 0x0, sum = 1
1968 13:38:23.327223 10, 0x0, sum = 2
1969 13:38:23.327308 11, 0x0, sum = 3
1970 13:38:23.327394 12, 0x0, sum = 4
1971 13:38:23.327447 best_step = 10
1972 13:38:23.327514
1973 13:38:23.327569 ==
1974 13:38:23.327623 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 13:38:23.327676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 13:38:23.327730 ==
1977 13:38:23.327782 RX Vref Scan: 0
1978 13:38:23.327835
1979 13:38:23.327902 RX Vref 0 -> 0, step: 1
1980 13:38:23.327996
1981 13:38:23.328053 RX Delay -95 -> 252, step: 8
1982 13:38:23.328107 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1983 13:38:23.328162 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1984 13:38:23.328229 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1985 13:38:23.328282 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1986 13:38:23.328334 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1987 13:38:23.328387 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1988 13:38:23.328440 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1989 13:38:23.328505 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1990 13:38:23.328561 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1991 13:38:23.328613 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1992 13:38:23.328665 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1993 13:38:23.328718 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1994 13:38:23.328771 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1995 13:38:23.328823 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1996 13:38:23.328876 iDelay=209, Bit 14, Center 84 (-23 ~ 192) 216
1997 13:38:23.328929 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1998 13:38:23.328993 ==
1999 13:38:23.329049 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 13:38:23.329102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 13:38:23.329155 ==
2002 13:38:23.329208 DQS Delay:
2003 13:38:23.329284 DQS0 = 0, DQS1 = 0
2004 13:38:23.329354 DQM Delay:
2005 13:38:23.329407 DQM0 = 85, DQM1 = 80
2006 13:38:23.329505 DQ Delay:
2007 13:38:23.329594 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2008 13:38:23.329648 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2009 13:38:23.329701 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2010 13:38:23.329754 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
2011 13:38:23.329806
2012 13:38:23.329859
2013 13:38:23.329911 [DQSOSCAuto] RK1, (LSB)MR18= 0x2742, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2014 13:38:23.329966 CH1 RK1: MR19=606, MR18=2742
2015 13:38:23.330037 CH1_RK1: MR19=0x606, MR18=0x2742, DQSOSC=393, MR23=63, INC=95, DEC=63
2016 13:38:23.330125 [RxdqsGatingPostProcess] freq 800
2017 13:38:23.330178 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 13:38:23.330231 Pre-setting of DQS Precalculation
2019 13:38:23.330284 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 13:38:23.330337 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 13:38:23.330391 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 13:38:23.330443
2023 13:38:23.330504
2024 13:38:23.330563 [Calibration Summary] 1600 Mbps
2025 13:38:23.330616 CH 0, Rank 0
2026 13:38:23.330669 SW Impedance : PASS
2027 13:38:23.330722 DUTY Scan : NO K
2028 13:38:23.330775 ZQ Calibration : PASS
2029 13:38:23.330846 Jitter Meter : NO K
2030 13:38:23.330912 CBT Training : PASS
2031 13:38:23.330998 Write leveling : PASS
2032 13:38:23.331067 RX DQS gating : PASS
2033 13:38:23.331121 RX DQ/DQS(RDDQC) : PASS
2034 13:38:23.331174 TX DQ/DQS : PASS
2035 13:38:23.331227 RX DATLAT : PASS
2036 13:38:23.331280 RX DQ/DQS(Engine): PASS
2037 13:38:23.331333 TX OE : NO K
2038 13:38:23.331386 All Pass.
2039 13:38:23.331439
2040 13:38:23.331491 CH 0, Rank 1
2041 13:38:23.331562 SW Impedance : PASS
2042 13:38:23.331617 DUTY Scan : NO K
2043 13:38:23.331670 ZQ Calibration : PASS
2044 13:38:23.331723 Jitter Meter : NO K
2045 13:38:23.331775 CBT Training : PASS
2046 13:38:23.331828 Write leveling : PASS
2047 13:38:23.331929 RX DQS gating : PASS
2048 13:38:23.331996 RX DQ/DQS(RDDQC) : PASS
2049 13:38:23.332066 TX DQ/DQS : PASS
2050 13:38:23.332121 RX DATLAT : PASS
2051 13:38:23.332173 RX DQ/DQS(Engine): PASS
2052 13:38:23.332226 TX OE : NO K
2053 13:38:23.332279 All Pass.
2054 13:38:23.332332
2055 13:38:23.332442 CH 1, Rank 0
2056 13:38:23.332509 SW Impedance : PASS
2057 13:38:23.332575 DUTY Scan : NO K
2058 13:38:23.332632 ZQ Calibration : PASS
2059 13:38:23.332685 Jitter Meter : NO K
2060 13:38:23.332738 CBT Training : PASS
2061 13:38:23.332791 Write leveling : PASS
2062 13:38:23.332845 RX DQS gating : PASS
2063 13:38:23.332923 RX DQ/DQS(RDDQC) : PASS
2064 13:38:23.333009 TX DQ/DQS : PASS
2065 13:38:23.333063 RX DATLAT : PASS
2066 13:38:23.333145 RX DQ/DQS(Engine): PASS
2067 13:38:23.333231 TX OE : NO K
2068 13:38:23.333320 All Pass.
2069 13:38:23.333375
2070 13:38:23.333429 CH 1, Rank 1
2071 13:38:23.333482 SW Impedance : PASS
2072 13:38:23.333536 DUTY Scan : NO K
2073 13:38:23.333589 ZQ Calibration : PASS
2074 13:38:23.333659 Jitter Meter : NO K
2075 13:38:23.333715 CBT Training : PASS
2076 13:38:23.333768 Write leveling : PASS
2077 13:38:23.333821 RX DQS gating : PASS
2078 13:38:23.333874 RX DQ/DQS(RDDQC) : PASS
2079 13:38:23.333928 TX DQ/DQS : PASS
2080 13:38:23.333981 RX DATLAT : PASS
2081 13:38:23.334034 RX DQ/DQS(Engine): PASS
2082 13:38:23.334087 TX OE : NO K
2083 13:38:23.334360 All Pass.
2084 13:38:23.334477
2085 13:38:23.334547 DramC Write-DBI off
2086 13:38:23.334623 PER_BANK_REFRESH: Hybrid Mode
2087 13:38:23.334687 TX_TRACKING: ON
2088 13:38:23.334743 [GetDramInforAfterCalByMRR] Vendor 6.
2089 13:38:23.334797 [GetDramInforAfterCalByMRR] Revision 606.
2090 13:38:23.334852 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 13:38:23.334907 MR0 0x3b3b
2092 13:38:23.335009 MR8 0x5151
2093 13:38:23.335069 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 13:38:23.335131
2095 13:38:23.335195 MR0 0x3b3b
2096 13:38:23.335251 MR8 0x5151
2097 13:38:23.335305 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 13:38:23.335375
2099 13:38:23.335429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 13:38:23.335484 [FAST_K] Save calibration result to emmc
2101 13:38:23.335538 [FAST_K] Save calibration result to emmc
2102 13:38:23.335608 dram_init: config_dvfs: 1
2103 13:38:23.335695 dramc_set_vcore_voltage set vcore to 662500
2104 13:38:23.335750 Read voltage for 1200, 2
2105 13:38:23.335803 Vio18 = 0
2106 13:38:23.335857 Vcore = 662500
2107 13:38:23.335910 Vdram = 0
2108 13:38:23.335964 Vddq = 0
2109 13:38:23.336016 Vmddr = 0
2110 13:38:23.336069 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 13:38:23.336161 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 13:38:23.336223 MEM_TYPE=3, freq_sel=15
2113 13:38:23.336277 sv_algorithm_assistance_LP4_1600
2114 13:38:23.336330 ============ PULL DRAM RESETB DOWN ============
2115 13:38:23.336385 ========== PULL DRAM RESETB DOWN end =========
2116 13:38:23.336471 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 13:38:23.336525 ===================================
2118 13:38:23.336578 LPDDR4 DRAM CONFIGURATION
2119 13:38:23.336631 ===================================
2120 13:38:23.336703 EX_ROW_EN[0] = 0x0
2121 13:38:23.336758 EX_ROW_EN[1] = 0x0
2122 13:38:23.336811 LP4Y_EN = 0x0
2123 13:38:23.336865 WORK_FSP = 0x0
2124 13:38:23.336918 WL = 0x4
2125 13:38:23.336971 RL = 0x4
2126 13:38:23.337023 BL = 0x2
2127 13:38:23.337076 RPST = 0x0
2128 13:38:23.337129 RD_PRE = 0x0
2129 13:38:23.337195 WR_PRE = 0x1
2130 13:38:23.337316 WR_PST = 0x0
2131 13:38:23.337372 DBI_WR = 0x0
2132 13:38:23.337426 DBI_RD = 0x0
2133 13:38:23.337481 OTF = 0x1
2134 13:38:23.337534 ===================================
2135 13:38:23.337588 ===================================
2136 13:38:23.337642 ANA top config
2137 13:38:23.337748 ===================================
2138 13:38:23.337804 DLL_ASYNC_EN = 0
2139 13:38:23.337858 ALL_SLAVE_EN = 0
2140 13:38:23.337912 NEW_RANK_MODE = 1
2141 13:38:23.337966 DLL_IDLE_MODE = 1
2142 13:38:23.338019 LP45_APHY_COMB_EN = 1
2143 13:38:23.338072 TX_ODT_DIS = 1
2144 13:38:23.338125 NEW_8X_MODE = 1
2145 13:38:23.338180 ===================================
2146 13:38:23.338251 ===================================
2147 13:38:23.338306 data_rate = 2400
2148 13:38:23.338384 CKR = 1
2149 13:38:23.338444 DQ_P2S_RATIO = 8
2150 13:38:23.338498 ===================================
2151 13:38:23.338551 CA_P2S_RATIO = 8
2152 13:38:23.338605 DQ_CA_OPEN = 0
2153 13:38:23.338658 DQ_SEMI_OPEN = 0
2154 13:38:23.338720 CA_SEMI_OPEN = 0
2155 13:38:23.338779 CA_FULL_RATE = 0
2156 13:38:23.338833 DQ_CKDIV4_EN = 0
2157 13:38:23.338885 CA_CKDIV4_EN = 0
2158 13:38:23.338964 CA_PREDIV_EN = 0
2159 13:38:23.339049 PH8_DLY = 17
2160 13:38:23.339116 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 13:38:23.339228 DQ_AAMCK_DIV = 4
2162 13:38:23.339287 CA_AAMCK_DIV = 4
2163 13:38:23.339342 CA_ADMCK_DIV = 4
2164 13:38:23.339397 DQ_TRACK_CA_EN = 0
2165 13:38:23.339452 CA_PICK = 1200
2166 13:38:23.339520 CA_MCKIO = 1200
2167 13:38:23.339573 MCKIO_SEMI = 0
2168 13:38:23.339644 PLL_FREQ = 2366
2169 13:38:23.339718 DQ_UI_PI_RATIO = 32
2170 13:38:23.339797 CA_UI_PI_RATIO = 0
2171 13:38:23.339865 ===================================
2172 13:38:23.339919 ===================================
2173 13:38:23.339972 memory_type:LPDDR4
2174 13:38:23.340026 GP_NUM : 10
2175 13:38:23.340079 SRAM_EN : 1
2176 13:38:23.340132 MD32_EN : 0
2177 13:38:23.340185 ===================================
2178 13:38:23.340251 [ANA_INIT] >>>>>>>>>>>>>>
2179 13:38:23.340308 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 13:38:23.340403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 13:38:23.340457 ===================================
2182 13:38:23.340511 data_rate = 2400,PCW = 0X5b00
2183 13:38:23.340564 ===================================
2184 13:38:23.340618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 13:38:23.340672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 13:38:23.340726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 13:38:23.340796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 13:38:23.340851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 13:38:23.340939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 13:38:23.340992 [ANA_INIT] flow start
2191 13:38:23.341049 [ANA_INIT] PLL >>>>>>>>
2192 13:38:23.341102 [ANA_INIT] PLL <<<<<<<<
2193 13:38:23.341155 [ANA_INIT] MIDPI >>>>>>>>
2194 13:38:23.341208 [ANA_INIT] MIDPI <<<<<<<<
2195 13:38:23.341296 [ANA_INIT] DLL >>>>>>>>
2196 13:38:23.341374 [ANA_INIT] DLL <<<<<<<<
2197 13:38:23.341478 [ANA_INIT] flow end
2198 13:38:23.341540 ============ LP4 DIFF to SE enter ============
2199 13:38:23.341605 ============ LP4 DIFF to SE exit ============
2200 13:38:23.341661 [ANA_INIT] <<<<<<<<<<<<<
2201 13:38:23.341715 [Flow] Enable top DCM control >>>>>
2202 13:38:23.341776 [Flow] Enable top DCM control <<<<<
2203 13:38:23.341838 Enable DLL master slave shuffle
2204 13:38:23.341892 ==============================================================
2205 13:38:23.341946 Gating Mode config
2206 13:38:23.341999 ==============================================================
2207 13:38:23.342053 Config description:
2208 13:38:23.342107 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 13:38:23.342368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 13:38:23.342486 SELPH_MODE 0: By rank 1: By Phase
2211 13:38:23.342556 ==============================================================
2212 13:38:23.342611 GAT_TRACK_EN = 1
2213 13:38:23.342666 RX_GATING_MODE = 2
2214 13:38:23.342719 RX_GATING_TRACK_MODE = 2
2215 13:38:23.342772 SELPH_MODE = 1
2216 13:38:23.342845 PICG_EARLY_EN = 1
2217 13:38:23.342900 VALID_LAT_VALUE = 1
2218 13:38:23.342954 ==============================================================
2219 13:38:23.343008 Enter into Gating configuration >>>>
2220 13:38:23.343088 Exit from Gating configuration <<<<
2221 13:38:23.343227 Enter into DVFS_PRE_config >>>>>
2222 13:38:23.343332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 13:38:23.343392 Exit from DVFS_PRE_config <<<<<
2224 13:38:23.343448 Enter into PICG configuration >>>>
2225 13:38:23.343517 Exit from PICG configuration <<<<
2226 13:38:23.343570 [RX_INPUT] configuration >>>>>
2227 13:38:23.343623 [RX_INPUT] configuration <<<<<
2228 13:38:23.343676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 13:38:23.343731 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 13:38:23.343784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 13:38:23.343850 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 13:38:23.343907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 13:38:23.343961 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 13:38:23.344015 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 13:38:23.344068 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 13:38:23.344122 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 13:38:23.344176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 13:38:23.344229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 13:38:23.344283 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 13:38:23.344336 ===================================
2241 13:38:23.344405 LPDDR4 DRAM CONFIGURATION
2242 13:38:23.344459 ===================================
2243 13:38:23.344512 EX_ROW_EN[0] = 0x0
2244 13:38:23.344565 EX_ROW_EN[1] = 0x0
2245 13:38:23.344618 LP4Y_EN = 0x0
2246 13:38:23.344671 WORK_FSP = 0x0
2247 13:38:23.344724 WL = 0x4
2248 13:38:23.344777 RL = 0x4
2249 13:38:23.344831 BL = 0x2
2250 13:38:23.344901 RPST = 0x0
2251 13:38:23.344964 RD_PRE = 0x0
2252 13:38:23.345033 WR_PRE = 0x1
2253 13:38:23.345128 WR_PST = 0x0
2254 13:38:23.345181 DBI_WR = 0x0
2255 13:38:23.345234 DBI_RD = 0x0
2256 13:38:23.345330 OTF = 0x1
2257 13:38:23.345397 ===================================
2258 13:38:23.345455 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 13:38:23.345509 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 13:38:23.345563 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 13:38:23.345617 ===================================
2262 13:38:23.345671 LPDDR4 DRAM CONFIGURATION
2263 13:38:23.345724 ===================================
2264 13:38:23.345778 EX_ROW_EN[0] = 0x10
2265 13:38:23.345831 EX_ROW_EN[1] = 0x0
2266 13:38:23.345891 LP4Y_EN = 0x0
2267 13:38:23.345952 WORK_FSP = 0x0
2268 13:38:23.346006 WL = 0x4
2269 13:38:23.346059 RL = 0x4
2270 13:38:23.346112 BL = 0x2
2271 13:38:23.346164 RPST = 0x0
2272 13:38:23.346217 RD_PRE = 0x0
2273 13:38:23.346294 WR_PRE = 0x1
2274 13:38:23.346428 WR_PST = 0x0
2275 13:38:23.346502 DBI_WR = 0x0
2276 13:38:23.346570 DBI_RD = 0x0
2277 13:38:23.346623 OTF = 0x1
2278 13:38:23.346677 ===================================
2279 13:38:23.346731 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 13:38:23.346784 ==
2281 13:38:23.346837 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 13:38:23.346891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 13:38:23.346963 ==
2284 13:38:23.347018 [Duty_Offset_Calibration]
2285 13:38:23.347071 B0:2 B1:0 CA:4
2286 13:38:23.347124
2287 13:38:23.347177 [DutyScan_Calibration_Flow] k_type=0
2288 13:38:23.347231
2289 13:38:23.347284 ==CLK 0==
2290 13:38:23.347338 Final CLK duty delay cell = -4
2291 13:38:23.347391 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2292 13:38:23.347460 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2293 13:38:23.347540 [-4] AVG Duty = 4937%(X100)
2294 13:38:23.347629
2295 13:38:23.347682 CH0 CLK Duty spec in!! Max-Min= 187%
2296 13:38:23.347735 [DutyScan_Calibration_Flow] ====Done====
2297 13:38:23.347788
2298 13:38:23.347841 [DutyScan_Calibration_Flow] k_type=1
2299 13:38:23.347893
2300 13:38:23.347957 ==DQS 0 ==
2301 13:38:23.348013 Final DQS duty delay cell = 0
2302 13:38:23.348067 [0] MAX Duty = 5156%(X100), DQS PI = 6
2303 13:38:23.348120 [0] MIN Duty = 5093%(X100), DQS PI = 0
2304 13:38:23.348173 [0] AVG Duty = 5124%(X100)
2305 13:38:23.348225
2306 13:38:23.348278 ==DQS 1 ==
2307 13:38:23.348330 Final DQS duty delay cell = 0
2308 13:38:23.348383 [0] MAX Duty = 5125%(X100), DQS PI = 52
2309 13:38:23.348437 [0] MIN Duty = 4969%(X100), DQS PI = 16
2310 13:38:23.348533 [0] AVG Duty = 5047%(X100)
2311 13:38:23.348586
2312 13:38:23.348638 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2313 13:38:23.348691
2314 13:38:23.348744 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 13:38:23.348797 [DutyScan_Calibration_Flow] ====Done====
2316 13:38:23.348850
2317 13:38:23.348902 [DutyScan_Calibration_Flow] k_type=3
2318 13:38:23.348958
2319 13:38:23.349021 ==DQM 0 ==
2320 13:38:23.349128 Final DQM duty delay cell = 0
2321 13:38:23.349182 [0] MAX Duty = 5062%(X100), DQS PI = 18
2322 13:38:23.349236 [0] MIN Duty = 4844%(X100), DQS PI = 44
2323 13:38:23.349314 [0] AVG Duty = 4953%(X100)
2324 13:38:23.349368
2325 13:38:23.349420 ==DQM 1 ==
2326 13:38:23.349482 Final DQM duty delay cell = 0
2327 13:38:23.349540 [0] MAX Duty = 4969%(X100), DQS PI = 4
2328 13:38:23.349594 [0] MIN Duty = 4875%(X100), DQS PI = 20
2329 13:38:23.349647 [0] AVG Duty = 4922%(X100)
2330 13:38:23.349714
2331 13:38:23.349796 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2332 13:38:23.349864
2333 13:38:23.349916 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2334 13:38:23.349969 [DutyScan_Calibration_Flow] ====Done====
2335 13:38:23.350040
2336 13:38:23.350095 [DutyScan_Calibration_Flow] k_type=2
2337 13:38:23.350147
2338 13:38:23.350200 ==DQ 0 ==
2339 13:38:23.350253 Final DQ duty delay cell = 0
2340 13:38:23.350517 [0] MAX Duty = 5125%(X100), DQS PI = 18
2341 13:38:23.350633 [0] MIN Duty = 4938%(X100), DQS PI = 58
2342 13:38:23.350689 [0] AVG Duty = 5031%(X100)
2343 13:38:23.350744
2344 13:38:23.350799 ==DQ 1 ==
2345 13:38:23.350853 Final DQ duty delay cell = 0
2346 13:38:23.350908 [0] MAX Duty = 5156%(X100), DQS PI = 6
2347 13:38:23.350961 [0] MIN Duty = 4938%(X100), DQS PI = 14
2348 13:38:23.351028 [0] AVG Duty = 5047%(X100)
2349 13:38:23.351099
2350 13:38:23.351152 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2351 13:38:23.351205
2352 13:38:23.351258 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2353 13:38:23.351310 [DutyScan_Calibration_Flow] ====Done====
2354 13:38:23.351362 ==
2355 13:38:23.351414 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 13:38:23.351467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 13:38:23.351568 ==
2358 13:38:23.351623 [Duty_Offset_Calibration]
2359 13:38:23.351676 B0:0 B1:-1 CA:3
2360 13:38:23.351729
2361 13:38:23.351781 [DutyScan_Calibration_Flow] k_type=0
2362 13:38:23.351833
2363 13:38:23.351886 ==CLK 0==
2364 13:38:23.351938 Final CLK duty delay cell = -4
2365 13:38:23.351991 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2366 13:38:23.352050 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2367 13:38:23.352143 [-4] AVG Duty = 4938%(X100)
2368 13:38:23.352196
2369 13:38:23.352248 CH1 CLK Duty spec in!! Max-Min= 124%
2370 13:38:23.352317 [DutyScan_Calibration_Flow] ====Done====
2371 13:38:23.352385
2372 13:38:23.352437 [DutyScan_Calibration_Flow] k_type=1
2373 13:38:23.352489
2374 13:38:23.352541 ==DQS 0 ==
2375 13:38:23.352612 Final DQS duty delay cell = 0
2376 13:38:23.352666 [0] MAX Duty = 5187%(X100), DQS PI = 28
2377 13:38:23.352718 [0] MIN Duty = 4907%(X100), DQS PI = 38
2378 13:38:23.352772 [0] AVG Duty = 5047%(X100)
2379 13:38:23.352842
2380 13:38:23.352927 ==DQS 1 ==
2381 13:38:23.352993 Final DQS duty delay cell = 0
2382 13:38:23.353047 [0] MAX Duty = 5156%(X100), DQS PI = 8
2383 13:38:23.353134 [0] MIN Duty = 5031%(X100), DQS PI = 2
2384 13:38:23.353217 [0] AVG Duty = 5093%(X100)
2385 13:38:23.353328
2386 13:38:23.353412 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2387 13:38:23.353465
2388 13:38:23.353518 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2389 13:38:23.353575 [DutyScan_Calibration_Flow] ====Done====
2390 13:38:23.353639
2391 13:38:23.353692 [DutyScan_Calibration_Flow] k_type=3
2392 13:38:23.353744
2393 13:38:23.353796 ==DQM 0 ==
2394 13:38:23.353848 Final DQM duty delay cell = 0
2395 13:38:23.353902 [0] MAX Duty = 5031%(X100), DQS PI = 28
2396 13:38:23.353954 [0] MIN Duty = 4813%(X100), DQS PI = 38
2397 13:38:23.354007 [0] AVG Duty = 4922%(X100)
2398 13:38:23.354060
2399 13:38:23.354125 ==DQM 1 ==
2400 13:38:23.354179 Final DQM duty delay cell = 0
2401 13:38:23.354232 [0] MAX Duty = 5000%(X100), DQS PI = 34
2402 13:38:23.354284 [0] MIN Duty = 4813%(X100), DQS PI = 0
2403 13:38:23.354366 [0] AVG Duty = 4906%(X100)
2404 13:38:23.354419
2405 13:38:23.354471 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2406 13:38:23.354523
2407 13:38:23.354582 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2408 13:38:23.354659 [DutyScan_Calibration_Flow] ====Done====
2409 13:38:23.354727
2410 13:38:23.354780 [DutyScan_Calibration_Flow] k_type=2
2411 13:38:23.354831
2412 13:38:23.354883 ==DQ 0 ==
2413 13:38:23.354936 Final DQ duty delay cell = -4
2414 13:38:23.354989 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2415 13:38:23.355042 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2416 13:38:23.355105 [-4] AVG Duty = 4922%(X100)
2417 13:38:23.355161
2418 13:38:23.355213 ==DQ 1 ==
2419 13:38:23.355267 Final DQ duty delay cell = 4
2420 13:38:23.355319 [4] MAX Duty = 5156%(X100), DQS PI = 26
2421 13:38:23.355373 [4] MIN Duty = 5031%(X100), DQS PI = 62
2422 13:38:23.355426 [4] AVG Duty = 5093%(X100)
2423 13:38:23.355478
2424 13:38:23.355530 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 13:38:23.355582
2426 13:38:23.355652 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2427 13:38:23.355706 [DutyScan_Calibration_Flow] ====Done====
2428 13:38:23.355758 nWR fixed to 30
2429 13:38:23.355812 [ModeRegInit_LP4] CH0 RK0
2430 13:38:23.355864 [ModeRegInit_LP4] CH0 RK1
2431 13:38:23.355916 [ModeRegInit_LP4] CH1 RK0
2432 13:38:23.355969 [ModeRegInit_LP4] CH1 RK1
2433 13:38:23.356021 match AC timing 7
2434 13:38:23.356073 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 13:38:23.356185 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 13:38:23.356255 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 13:38:23.356326 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 13:38:23.356394 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 13:38:23.356447 ==
2440 13:38:23.356500 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 13:38:23.356552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 13:38:23.356605 ==
2443 13:38:23.356670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 13:38:23.356726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 13:38:23.356779 [CA 0] Center 39 (9~70) winsize 62
2446 13:38:23.356832 [CA 1] Center 39 (9~70) winsize 62
2447 13:38:23.356885 [CA 2] Center 35 (5~66) winsize 62
2448 13:38:23.356937 [CA 3] Center 35 (5~66) winsize 62
2449 13:38:23.356989 [CA 4] Center 33 (3~64) winsize 62
2450 13:38:23.357042 [CA 5] Center 33 (3~63) winsize 61
2451 13:38:23.357094
2452 13:38:23.357147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2453 13:38:23.357237
2454 13:38:23.357358 [CATrainingPosCal] consider 1 rank data
2455 13:38:23.357442 u2DelayCellTimex100 = 270/100 ps
2456 13:38:23.357590 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2457 13:38:23.357704 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2458 13:38:23.357760 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2459 13:38:23.357813 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2460 13:38:23.357898 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2461 13:38:23.357966 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2462 13:38:23.358049
2463 13:38:23.358117 CA PerBit enable=1, Macro0, CA PI delay=33
2464 13:38:23.358175
2465 13:38:23.358263 [CBTSetCACLKResult] CA Dly = 33
2466 13:38:23.358346 CS Dly: 7 (0~38)
2467 13:38:23.358428 ==
2468 13:38:23.358484 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 13:38:23.358538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 13:38:23.358591 ==
2471 13:38:23.358644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 13:38:23.358712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 13:38:23.358769 [CA 0] Center 39 (9~70) winsize 62
2474 13:38:23.358822 [CA 1] Center 39 (9~70) winsize 62
2475 13:38:23.358875 [CA 2] Center 35 (5~66) winsize 62
2476 13:38:23.358927 [CA 3] Center 35 (5~66) winsize 62
2477 13:38:23.358980 [CA 4] Center 34 (3~65) winsize 63
2478 13:38:23.359032 [CA 5] Center 33 (3~63) winsize 61
2479 13:38:23.359085
2480 13:38:23.359137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 13:38:23.359190
2482 13:38:23.359257 [CATrainingPosCal] consider 2 rank data
2483 13:38:23.359311 u2DelayCellTimex100 = 270/100 ps
2484 13:38:23.359570 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 13:38:23.359681 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 13:38:23.359754 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 13:38:23.359826 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 13:38:23.359896 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2489 13:38:23.359951 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 13:38:23.360006
2491 13:38:23.360061 CA PerBit enable=1, Macro0, CA PI delay=33
2492 13:38:23.360158
2493 13:38:23.360236 [CBTSetCACLKResult] CA Dly = 33
2494 13:38:23.360320 CS Dly: 8 (0~41)
2495 13:38:23.360401
2496 13:38:23.360487 ----->DramcWriteLeveling(PI) begin...
2497 13:38:23.360546 ==
2498 13:38:23.360600 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 13:38:23.360653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 13:38:23.360757 ==
2501 13:38:23.360812 Write leveling (Byte 0): 32 => 32
2502 13:38:23.360866 Write leveling (Byte 1): 25 => 25
2503 13:38:23.360919 DramcWriteLeveling(PI) end<-----
2504 13:38:23.360971
2505 13:38:23.361024 ==
2506 13:38:23.361077 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 13:38:23.361131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 13:38:23.361242 ==
2509 13:38:23.361330 [Gating] SW mode calibration
2510 13:38:23.361385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 13:38:23.361439 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 13:38:23.361493 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2513 13:38:23.361546 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2514 13:38:23.361599 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 13:38:23.361652 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 13:38:23.361718 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 13:38:23.361791 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 13:38:23.361858 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2519 13:38:23.361911 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2520 13:38:23.361964 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2521 13:38:23.362017 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 13:38:23.362069 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 13:38:23.362122 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 13:38:23.362175 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 13:38:23.362244 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 13:38:23.362299 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2527 13:38:23.362352 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2528 13:38:23.362404 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2529 13:38:23.362457 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 13:38:23.362510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 13:38:23.362562 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 13:38:23.362615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 13:38:23.362668 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 13:38:23.362778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 13:38:23.362850 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 13:38:23.362903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 13:38:23.362955 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 13:38:23.363008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 13:38:23.363061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 13:38:23.363113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 13:38:23.363166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 13:38:23.363219 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 13:38:23.363287 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 13:38:23.363343 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:38:23.363396 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:38:23.363449 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:38:23.363502 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:38:23.363554 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:38:23.363606 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:38:23.363659 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:38:23.363711 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 13:38:23.363776 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 13:38:23.363832 Total UI for P1: 0, mck2ui 16
2554 13:38:23.363886 best dqsien dly found for B0: ( 1, 3, 28)
2555 13:38:23.363940 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 13:38:23.363993 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 13:38:23.364062 Total UI for P1: 0, mck2ui 16
2558 13:38:23.364126 best dqsien dly found for B1: ( 1, 4, 2)
2559 13:38:23.364180 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2560 13:38:23.364233 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2561 13:38:23.364298
2562 13:38:23.364353 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2563 13:38:23.364429 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2564 13:38:23.364519 [Gating] SW calibration Done
2565 13:38:23.364572 ==
2566 13:38:23.364626 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 13:38:23.364679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 13:38:23.364732 ==
2569 13:38:23.364795 RX Vref Scan: 0
2570 13:38:23.364854
2571 13:38:23.364908 RX Vref 0 -> 0, step: 1
2572 13:38:23.364961
2573 13:38:23.365013 RX Delay -40 -> 252, step: 8
2574 13:38:23.365066 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2575 13:38:23.365118 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2576 13:38:23.365171 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 13:38:23.365223 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2578 13:38:23.365323 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 13:38:23.365380 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2580 13:38:23.365434 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2581 13:38:23.365486 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 13:38:23.365539 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2583 13:38:23.365591 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2584 13:38:23.365644 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2585 13:38:23.365898 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2586 13:38:23.365959 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 13:38:23.366013 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2588 13:38:23.366066 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2589 13:38:23.366120 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2590 13:38:23.366190 ==
2591 13:38:23.366276 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 13:38:23.366346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 13:38:23.366417 ==
2594 13:38:23.366471 DQS Delay:
2595 13:38:23.366541 DQS0 = 0, DQS1 = 0
2596 13:38:23.366607 DQM Delay:
2597 13:38:23.366660 DQM0 = 118, DQM1 = 108
2598 13:38:23.366713 DQ Delay:
2599 13:38:23.366765 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2600 13:38:23.366842 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2601 13:38:23.366914 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2602 13:38:23.366967 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2603 13:38:23.367020
2604 13:38:23.367072
2605 13:38:23.367124 ==
2606 13:38:23.367176 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 13:38:23.367228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 13:38:23.367281 ==
2609 13:38:23.367341
2610 13:38:23.367400
2611 13:38:23.367454 TX Vref Scan disable
2612 13:38:23.367507 == TX Byte 0 ==
2613 13:38:23.367559 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2614 13:38:23.367611 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2615 13:38:23.367664 == TX Byte 1 ==
2616 13:38:23.367716 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2617 13:38:23.367769 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2618 13:38:23.367821 ==
2619 13:38:23.367892 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 13:38:23.367946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 13:38:23.367999 ==
2622 13:38:23.368052 TX Vref=22, minBit 13, minWin=24, winSum=412
2623 13:38:23.368105 TX Vref=24, minBit 10, minWin=25, winSum=420
2624 13:38:23.368163 TX Vref=26, minBit 8, minWin=25, winSum=428
2625 13:38:23.368251 TX Vref=28, minBit 4, minWin=26, winSum=431
2626 13:38:23.368323 TX Vref=30, minBit 5, minWin=26, winSum=434
2627 13:38:23.368424 TX Vref=32, minBit 1, minWin=26, winSum=428
2628 13:38:23.368494 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 30
2629 13:38:23.368549
2630 13:38:23.368601 Final TX Range 1 Vref 30
2631 13:38:23.368655
2632 13:38:23.368707 ==
2633 13:38:23.368776 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 13:38:23.368844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 13:38:23.368914 ==
2636 13:38:23.368968
2637 13:38:23.369020
2638 13:38:23.369072 TX Vref Scan disable
2639 13:38:23.369125 == TX Byte 0 ==
2640 13:38:23.369178 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2641 13:38:23.369230 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2642 13:38:23.369325 == TX Byte 1 ==
2643 13:38:23.369392 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2644 13:38:23.369449 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2645 13:38:23.369501
2646 13:38:23.369553 [DATLAT]
2647 13:38:23.369605 Freq=1200, CH0 RK0
2648 13:38:23.369658
2649 13:38:23.369711 DATLAT Default: 0xd
2650 13:38:23.369763 0, 0xFFFF, sum = 0
2651 13:38:23.369817 1, 0xFFFF, sum = 0
2652 13:38:23.369872 2, 0xFFFF, sum = 0
2653 13:38:23.369926 3, 0xFFFF, sum = 0
2654 13:38:23.369979 4, 0xFFFF, sum = 0
2655 13:38:23.370041 5, 0xFFFF, sum = 0
2656 13:38:23.370101 6, 0xFFFF, sum = 0
2657 13:38:23.370155 7, 0xFFFF, sum = 0
2658 13:38:23.370208 8, 0xFFFF, sum = 0
2659 13:38:23.370262 9, 0xFFFF, sum = 0
2660 13:38:23.370315 10, 0xFFFF, sum = 0
2661 13:38:23.370369 11, 0xFFFF, sum = 0
2662 13:38:23.370422 12, 0x0, sum = 1
2663 13:38:23.370476 13, 0x0, sum = 2
2664 13:38:23.370530 14, 0x0, sum = 3
2665 13:38:23.370583 15, 0x0, sum = 4
2666 13:38:23.370637 best_step = 13
2667 13:38:23.370723
2668 13:38:23.370804 ==
2669 13:38:23.370859 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 13:38:23.370912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 13:38:23.370967 ==
2672 13:38:23.371021 RX Vref Scan: 1
2673 13:38:23.371103
2674 13:38:23.371164 Set Vref Range= 32 -> 127
2675 13:38:23.371260
2676 13:38:23.371353 RX Vref 32 -> 127, step: 1
2677 13:38:23.371438
2678 13:38:23.371522 RX Delay -21 -> 252, step: 4
2679 13:38:23.371605
2680 13:38:23.371689 Set Vref, RX VrefLevel [Byte0]: 32
2681 13:38:23.371773 [Byte1]: 32
2682 13:38:23.371855
2683 13:38:23.371911 Set Vref, RX VrefLevel [Byte0]: 33
2684 13:38:23.371965 [Byte1]: 33
2685 13:38:23.372019
2686 13:38:23.372073 Set Vref, RX VrefLevel [Byte0]: 34
2687 13:38:23.372127 [Byte1]: 34
2688 13:38:23.372181
2689 13:38:23.372235 Set Vref, RX VrefLevel [Byte0]: 35
2690 13:38:23.372289 [Byte1]: 35
2691 13:38:23.372377
2692 13:38:23.372462 Set Vref, RX VrefLevel [Byte0]: 36
2693 13:38:23.372551 [Byte1]: 36
2694 13:38:23.372610
2695 13:38:23.372665 Set Vref, RX VrefLevel [Byte0]: 37
2696 13:38:23.372719 [Byte1]: 37
2697 13:38:23.372814
2698 13:38:23.372877 Set Vref, RX VrefLevel [Byte0]: 38
2699 13:38:23.372933 [Byte1]: 38
2700 13:38:23.372987
2701 13:38:23.373041 Set Vref, RX VrefLevel [Byte0]: 39
2702 13:38:23.373095 [Byte1]: 39
2703 13:38:23.373149
2704 13:38:23.373203 Set Vref, RX VrefLevel [Byte0]: 40
2705 13:38:23.373263 [Byte1]: 40
2706 13:38:23.373332
2707 13:38:23.373389 Set Vref, RX VrefLevel [Byte0]: 41
2708 13:38:23.373443 [Byte1]: 41
2709 13:38:23.373498
2710 13:38:23.373551 Set Vref, RX VrefLevel [Byte0]: 42
2711 13:38:23.373605 [Byte1]: 42
2712 13:38:23.373659
2713 13:38:23.373712 Set Vref, RX VrefLevel [Byte0]: 43
2714 13:38:23.373765 [Byte1]: 43
2715 13:38:23.373830
2716 13:38:23.373887 Set Vref, RX VrefLevel [Byte0]: 44
2717 13:38:23.373941 [Byte1]: 44
2718 13:38:23.373995
2719 13:38:23.374048 Set Vref, RX VrefLevel [Byte0]: 45
2720 13:38:23.374102 [Byte1]: 45
2721 13:38:23.374155
2722 13:38:23.374208 Set Vref, RX VrefLevel [Byte0]: 46
2723 13:38:23.374261 [Byte1]: 46
2724 13:38:23.374315
2725 13:38:23.374385 Set Vref, RX VrefLevel [Byte0]: 47
2726 13:38:23.374472 [Byte1]: 47
2727 13:38:23.374529
2728 13:38:23.374584 Set Vref, RX VrefLevel [Byte0]: 48
2729 13:38:23.374638 [Byte1]: 48
2730 13:38:23.374692
2731 13:38:23.374746 Set Vref, RX VrefLevel [Byte0]: 49
2732 13:38:23.374806 [Byte1]: 49
2733 13:38:23.374915
2734 13:38:23.374989 Set Vref, RX VrefLevel [Byte0]: 50
2735 13:38:23.375053 [Byte1]: 50
2736 13:38:23.375109
2737 13:38:23.375163 Set Vref, RX VrefLevel [Byte0]: 51
2738 13:38:23.375217 [Byte1]: 51
2739 13:38:23.375273
2740 13:38:23.375327 Set Vref, RX VrefLevel [Byte0]: 52
2741 13:38:23.375381 [Byte1]: 52
2742 13:38:23.375436
2743 13:38:23.375489 Set Vref, RX VrefLevel [Byte0]: 53
2744 13:38:23.375576 [Byte1]: 53
2745 13:38:23.375662
2746 13:38:23.375747 Set Vref, RX VrefLevel [Byte0]: 54
2747 13:38:23.375832 [Byte1]: 54
2748 13:38:23.375915
2749 13:38:23.376206 Set Vref, RX VrefLevel [Byte0]: 55
2750 13:38:23.376298 [Byte1]: 55
2751 13:38:23.376382
2752 13:38:23.376466 Set Vref, RX VrefLevel [Byte0]: 56
2753 13:38:23.376551 [Byte1]: 56
2754 13:38:23.376635
2755 13:38:23.376719 Set Vref, RX VrefLevel [Byte0]: 57
2756 13:38:23.376805 [Byte1]: 57
2757 13:38:23.376897
2758 13:38:23.376954 Set Vref, RX VrefLevel [Byte0]: 58
2759 13:38:23.377010 [Byte1]: 58
2760 13:38:23.377065
2761 13:38:23.377150 Set Vref, RX VrefLevel [Byte0]: 59
2762 13:38:23.377235 [Byte1]: 59
2763 13:38:23.377310
2764 13:38:23.377365 Set Vref, RX VrefLevel [Byte0]: 60
2765 13:38:23.377420 [Byte1]: 60
2766 13:38:23.377474
2767 13:38:23.377527 Set Vref, RX VrefLevel [Byte0]: 61
2768 13:38:23.377581 [Byte1]: 61
2769 13:38:23.377635
2770 13:38:23.377688 Set Vref, RX VrefLevel [Byte0]: 62
2771 13:38:23.377741 [Byte1]: 62
2772 13:38:23.377795
2773 13:38:23.377848 Set Vref, RX VrefLevel [Byte0]: 63
2774 13:38:23.377902 [Byte1]: 63
2775 13:38:23.377955
2776 13:38:23.378023 Set Vref, RX VrefLevel [Byte0]: 64
2777 13:38:23.378090 [Byte1]: 64
2778 13:38:23.378145
2779 13:38:23.378199 Set Vref, RX VrefLevel [Byte0]: 65
2780 13:38:23.378253 [Byte1]: 65
2781 13:38:23.378308
2782 13:38:23.378362 Set Vref, RX VrefLevel [Byte0]: 66
2783 13:38:23.378415 [Byte1]: 66
2784 13:38:23.378469
2785 13:38:23.378522 Set Vref, RX VrefLevel [Byte0]: 67
2786 13:38:23.378575 [Byte1]: 67
2787 13:38:23.378628
2788 13:38:23.378682 Set Vref, RX VrefLevel [Byte0]: 68
2789 13:38:23.378736 [Byte1]: 68
2790 13:38:23.378789
2791 13:38:23.378843 Set Vref, RX VrefLevel [Byte0]: 69
2792 13:38:23.378897 [Byte1]: 69
2793 13:38:23.378951
2794 13:38:23.379003 Final RX Vref Byte 0 = 50 to rank0
2795 13:38:23.379058 Final RX Vref Byte 1 = 58 to rank0
2796 13:38:23.379111 Final RX Vref Byte 0 = 50 to rank1
2797 13:38:23.379166 Final RX Vref Byte 1 = 58 to rank1==
2798 13:38:23.379220 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 13:38:23.379274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 13:38:23.379330 ==
2801 13:38:23.379383 DQS Delay:
2802 13:38:23.379437 DQS0 = 0, DQS1 = 0
2803 13:38:23.379491 DQM Delay:
2804 13:38:23.379545 DQM0 = 117, DQM1 = 105
2805 13:38:23.379598 DQ Delay:
2806 13:38:23.379652 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2807 13:38:23.379705 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2808 13:38:23.379759 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2809 13:38:23.379812 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2810 13:38:23.379866
2811 13:38:23.379920
2812 13:38:23.379974 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2813 13:38:23.380029 CH0 RK0: MR19=403, MR18=3FE
2814 13:38:23.380083 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2815 13:38:23.380137
2816 13:38:23.380191 ----->DramcWriteLeveling(PI) begin...
2817 13:38:23.380245 ==
2818 13:38:23.380300 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 13:38:23.380354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 13:38:23.380409 ==
2821 13:38:23.380462 Write leveling (Byte 0): 34 => 34
2822 13:38:23.380517 Write leveling (Byte 1): 25 => 25
2823 13:38:23.380603 DramcWriteLeveling(PI) end<-----
2824 13:38:23.380661
2825 13:38:23.380715 ==
2826 13:38:23.380769 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 13:38:23.380824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 13:38:23.380878 ==
2829 13:38:23.380932 [Gating] SW mode calibration
2830 13:38:23.380986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 13:38:23.381040 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 13:38:23.381094 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2833 13:38:23.381168 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 13:38:23.381255 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 13:38:23.381351 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 13:38:23.381441 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 13:38:23.381537 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 13:38:23.381595 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2839 13:38:23.381650 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (0 1) (0 0)
2840 13:38:23.381705 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2841 13:38:23.381759 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 13:38:23.381813 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 13:38:23.381868 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 13:38:23.381921 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 13:38:23.381976 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 13:38:23.382030 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2847 13:38:23.382084 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2848 13:38:23.382138 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2849 13:38:23.382216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 13:38:23.382273 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 13:38:23.382327 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 13:38:23.382382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 13:38:23.382436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 13:38:23.382490 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2855 13:38:23.382544 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2856 13:38:23.382598 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2857 13:38:23.382653 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 13:38:23.382708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 13:38:23.382761 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 13:38:23.382815 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 13:38:23.382869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 13:38:23.382923 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 13:38:23.382977 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 13:38:23.383031 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:38:23.383088 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:38:23.383158 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:38:23.383456 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:38:23.383524 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:38:23.383582 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:38:23.383638 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2871 13:38:23.383693 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2872 13:38:23.383748 Total UI for P1: 0, mck2ui 16
2873 13:38:23.383803 best dqsien dly found for B0: ( 1, 3, 24)
2874 13:38:23.383857 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2875 13:38:23.383911 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 13:38:23.383966 Total UI for P1: 0, mck2ui 16
2877 13:38:23.384020 best dqsien dly found for B1: ( 1, 3, 30)
2878 13:38:23.384074 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2879 13:38:23.384129 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2880 13:38:23.384184
2881 13:38:23.384240 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2882 13:38:23.384295 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 13:38:23.384348 [Gating] SW calibration Done
2884 13:38:23.384402 ==
2885 13:38:23.384456 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 13:38:23.384510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 13:38:23.384565 ==
2888 13:38:23.384619 RX Vref Scan: 0
2889 13:38:23.384673
2890 13:38:23.384727 RX Vref 0 -> 0, step: 1
2891 13:38:23.384791
2892 13:38:23.384861 RX Delay -40 -> 252, step: 8
2893 13:38:23.384917 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2894 13:38:23.384972 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2895 13:38:23.385027 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2896 13:38:23.385081 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2897 13:38:23.385135 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2898 13:38:23.385188 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2899 13:38:23.385242 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2900 13:38:23.385309 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2901 13:38:23.385384 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2902 13:38:23.385447 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2903 13:38:23.385502 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2904 13:38:23.385557 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2905 13:38:23.385611 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2906 13:38:23.385664 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2907 13:38:23.385718 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2908 13:38:23.385772 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2909 13:38:23.385826 ==
2910 13:38:23.385879 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 13:38:23.385933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 13:38:23.385988 ==
2913 13:38:23.386042 DQS Delay:
2914 13:38:23.386095 DQS0 = 0, DQS1 = 0
2915 13:38:23.386149 DQM Delay:
2916 13:38:23.386202 DQM0 = 115, DQM1 = 109
2917 13:38:23.386256 DQ Delay:
2918 13:38:23.386309 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2919 13:38:23.386363 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2920 13:38:23.386417 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2921 13:38:23.386471 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2922 13:38:23.386525
2923 13:38:23.386578
2924 13:38:23.386631 ==
2925 13:38:23.386685 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 13:38:23.386738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 13:38:23.386792 ==
2928 13:38:23.386846
2929 13:38:23.386899
2930 13:38:23.386952 TX Vref Scan disable
2931 13:38:23.387006 == TX Byte 0 ==
2932 13:38:23.387059 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2933 13:38:23.387113 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2934 13:38:23.878501 == TX Byte 1 ==
2935 13:38:23.878661 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2936 13:38:23.878762 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2937 13:38:23.878859 ==
2938 13:38:23.878956 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 13:38:23.879056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 13:38:23.879145 ==
2941 13:38:23.879232 TX Vref=22, minBit 1, minWin=26, winSum=419
2942 13:38:23.879319 TX Vref=24, minBit 10, minWin=25, winSum=422
2943 13:38:23.879415 TX Vref=26, minBit 1, minWin=26, winSum=425
2944 13:38:23.879511 TX Vref=28, minBit 1, minWin=26, winSum=428
2945 13:38:23.879602 TX Vref=30, minBit 10, minWin=26, winSum=431
2946 13:38:23.879687 TX Vref=32, minBit 13, minWin=26, winSum=430
2947 13:38:23.879773 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
2948 13:38:23.879857
2949 13:38:23.879951 Final TX Range 1 Vref 30
2950 13:38:23.880047
2951 13:38:23.880131 ==
2952 13:38:23.880215 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 13:38:23.880299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 13:38:23.880386 ==
2955 13:38:23.880477
2956 13:38:23.880571
2957 13:38:23.880655 TX Vref Scan disable
2958 13:38:23.880738 == TX Byte 0 ==
2959 13:38:23.880822 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 13:38:23.880913 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 13:38:23.881001 == TX Byte 1 ==
2962 13:38:23.881096 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2963 13:38:23.881181 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2964 13:38:23.881274
2965 13:38:23.881358 [DATLAT]
2966 13:38:23.881451 Freq=1200, CH0 RK1
2967 13:38:23.881538
2968 13:38:23.881632 DATLAT Default: 0xd
2969 13:38:23.881715 0, 0xFFFF, sum = 0
2970 13:38:23.881800 1, 0xFFFF, sum = 0
2971 13:38:23.881885 2, 0xFFFF, sum = 0
2972 13:38:23.881980 3, 0xFFFF, sum = 0
2973 13:38:23.882071 4, 0xFFFF, sum = 0
2974 13:38:23.882164 5, 0xFFFF, sum = 0
2975 13:38:23.882249 6, 0xFFFF, sum = 0
2976 13:38:23.882334 7, 0xFFFF, sum = 0
2977 13:38:23.882418 8, 0xFFFF, sum = 0
2978 13:38:23.882516 9, 0xFFFF, sum = 0
2979 13:38:23.882612 10, 0xFFFF, sum = 0
2980 13:38:23.882700 11, 0xFFFF, sum = 0
2981 13:38:23.882785 12, 0x0, sum = 1
2982 13:38:23.882869 13, 0x0, sum = 2
2983 13:38:23.882959 14, 0x0, sum = 3
2984 13:38:23.883051 15, 0x0, sum = 4
2985 13:38:23.883146 best_step = 13
2986 13:38:23.883229
2987 13:38:23.883312 ==
2988 13:38:23.883395 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 13:38:23.883487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 13:38:23.883575 ==
2991 13:38:23.883669 RX Vref Scan: 0
2992 13:38:23.883753
2993 13:38:23.883836 RX Vref 0 -> 0, step: 1
2994 13:38:23.883918
2995 13:38:23.884007 RX Delay -21 -> 252, step: 4
2996 13:38:23.884095 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
2997 13:38:23.884189 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
2998 13:38:23.884274 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
2999 13:38:23.884358 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3000 13:38:23.884441 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
3001 13:38:23.884533 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
3002 13:38:23.884618 iDelay=191, Bit 6, Center 126 (63 ~ 190) 128
3003 13:38:23.884714 iDelay=191, Bit 7, Center 120 (55 ~ 186) 132
3004 13:38:23.884798 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3005 13:38:23.885095 iDelay=191, Bit 9, Center 92 (27 ~ 158) 132
3006 13:38:23.885195 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3007 13:38:23.885293 iDelay=191, Bit 11, Center 100 (31 ~ 170) 140
3008 13:38:23.885378 iDelay=191, Bit 12, Center 112 (47 ~ 178) 132
3009 13:38:23.885462 iDelay=191, Bit 13, Center 110 (43 ~ 178) 136
3010 13:38:23.885553 iDelay=191, Bit 14, Center 120 (55 ~ 186) 132
3011 13:38:23.885641 iDelay=191, Bit 15, Center 112 (47 ~ 178) 132
3012 13:38:23.885735 ==
3013 13:38:23.885820 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 13:38:23.885904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 13:38:23.885987 ==
3016 13:38:23.886078 DQS Delay:
3017 13:38:23.886169 DQS0 = 0, DQS1 = 0
3018 13:38:23.886260 DQM Delay:
3019 13:38:23.886345 DQM0 = 115, DQM1 = 106
3020 13:38:23.886427 DQ Delay:
3021 13:38:23.886510 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3022 13:38:23.886593 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3023 13:38:23.886684 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3024 13:38:23.886778 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =112
3025 13:38:23.886866
3026 13:38:23.886949
3027 13:38:23.887033 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3028 13:38:23.887117 CH0 RK1: MR19=403, MR18=1FE
3029 13:38:23.887209 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3030 13:38:23.887296 [RxdqsGatingPostProcess] freq 1200
3031 13:38:23.887390 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3032 13:38:23.887474 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 13:38:23.887558 best DQS1 dly(2T, 0.5T) = (0, 12)
3034 13:38:23.887641 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 13:38:23.887733 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3036 13:38:23.887821 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 13:38:23.887912 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 13:38:23.887998 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 13:38:23.888084 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 13:38:23.888175 Pre-setting of DQS Precalculation
3041 13:38:23.888276 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3042 13:38:23.888382 ==
3043 13:38:23.888478 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 13:38:23.888572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 13:38:23.888665 ==
3046 13:38:23.888767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3047 13:38:23.888869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3048 13:38:23.888967 [CA 0] Center 38 (8~68) winsize 61
3049 13:38:23.889061 [CA 1] Center 38 (8~68) winsize 61
3050 13:38:23.889157 [CA 2] Center 35 (5~65) winsize 61
3051 13:38:23.889255 [CA 3] Center 34 (4~64) winsize 61
3052 13:38:23.889354 [CA 4] Center 34 (4~65) winsize 62
3053 13:38:23.889449 [CA 5] Center 33 (3~63) winsize 61
3054 13:38:23.889536
3055 13:38:23.889620 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3056 13:38:23.889704
3057 13:38:23.889795 [CATrainingPosCal] consider 1 rank data
3058 13:38:23.889891 u2DelayCellTimex100 = 270/100 ps
3059 13:38:23.889979 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3060 13:38:23.890065 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3061 13:38:23.890150 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 13:38:23.890233 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 13:38:23.890328 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3064 13:38:23.890423 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3065 13:38:23.890509
3066 13:38:23.890594 CA PerBit enable=1, Macro0, CA PI delay=33
3067 13:38:23.890677
3068 13:38:23.890761 [CBTSetCACLKResult] CA Dly = 33
3069 13:38:23.890856 CS Dly: 5 (0~36)
3070 13:38:23.890947 ==
3071 13:38:23.891032 Dram Type= 6, Freq= 0, CH_1, rank 1
3072 13:38:23.891119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 13:38:23.891203 ==
3074 13:38:23.891287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 13:38:23.891382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 13:38:23.891470 [CA 0] Center 38 (8~68) winsize 61
3077 13:38:23.891555 [CA 1] Center 38 (7~69) winsize 63
3078 13:38:23.891640 [CA 2] Center 35 (5~65) winsize 61
3079 13:38:23.891724 [CA 3] Center 33 (3~64) winsize 62
3080 13:38:23.891808 [CA 4] Center 34 (4~64) winsize 61
3081 13:38:23.891901 [CA 5] Center 33 (3~63) winsize 61
3082 13:38:23.891987
3083 13:38:23.892072 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3084 13:38:23.892155
3085 13:38:23.892240 [CATrainingPosCal] consider 2 rank data
3086 13:38:23.892324 u2DelayCellTimex100 = 270/100 ps
3087 13:38:23.892417 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 13:38:23.892505 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 13:38:23.892590 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 13:38:23.892673 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 13:38:23.892759 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 13:38:23.892842 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3093 13:38:23.892936
3094 13:38:23.893024 CA PerBit enable=1, Macro0, CA PI delay=33
3095 13:38:23.893107
3096 13:38:23.893191 [CBTSetCACLKResult] CA Dly = 33
3097 13:38:23.893280 CS Dly: 6 (0~39)
3098 13:38:23.893337
3099 13:38:23.893391 ----->DramcWriteLeveling(PI) begin...
3100 13:38:23.893467 ==
3101 13:38:23.893526 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 13:38:23.893609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 13:38:23.893704 ==
3104 13:38:23.893796 Write leveling (Byte 0): 26 => 26
3105 13:38:23.893889 Write leveling (Byte 1): 27 => 27
3106 13:38:23.893991 DramcWriteLeveling(PI) end<-----
3107 13:38:23.894086
3108 13:38:23.894179 ==
3109 13:38:23.894273 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 13:38:23.894366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 13:38:23.894459 ==
3112 13:38:23.894553 [Gating] SW mode calibration
3113 13:38:23.894647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3114 13:38:23.894741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3115 13:38:23.894835 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 13:38:23.894929 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 13:38:23.895023 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 13:38:23.895118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 13:38:23.895211 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 13:38:23.895304 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 13:38:23.895398 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
3122 13:38:23.895491 0 15 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
3123 13:38:23.895803 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 13:38:23.895900 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 13:38:23.895996 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 13:38:23.896099 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 13:38:23.896192 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 13:38:23.896279 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 13:38:23.896366 1 0 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
3130 13:38:23.896452 1 0 28 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3131 13:38:23.896537 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 13:38:23.896630 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 13:38:23.896719 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 13:38:23.896803 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 13:38:23.896887 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 13:38:23.896973 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 13:38:23.897057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3138 13:38:23.897153 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3139 13:38:23.897240 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 13:38:23.897336 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 13:38:23.897421 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:38:23.897507 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:38:23.897591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:38:23.897687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 13:38:23.897774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 13:38:23.897858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:38:23.897942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:38:23.898027 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:38:23.898114 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:38:23.898209 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:38:23.898293 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:38:23.898377 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:38:23.898461 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3154 13:38:23.898546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3155 13:38:23.898634 Total UI for P1: 0, mck2ui 16
3156 13:38:23.898727 best dqsien dly found for B0: ( 1, 3, 24)
3157 13:38:23.898812 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:38:23.898896 Total UI for P1: 0, mck2ui 16
3159 13:38:23.898980 best dqsien dly found for B1: ( 1, 3, 28)
3160 13:38:23.899066 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3161 13:38:23.899161 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3162 13:38:23.899247
3163 13:38:23.899331 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3164 13:38:23.899415 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3165 13:38:23.899499 [Gating] SW calibration Done
3166 13:38:23.899581 ==
3167 13:38:23.899667 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 13:38:23.899762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 13:38:23.899848 ==
3170 13:38:23.899931 RX Vref Scan: 0
3171 13:38:23.900014
3172 13:38:23.900096 RX Vref 0 -> 0, step: 1
3173 13:38:23.900179
3174 13:38:23.900272 RX Delay -40 -> 252, step: 8
3175 13:38:23.900359 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3176 13:38:23.900444 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3177 13:38:23.900528 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 13:38:23.900612 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3179 13:38:23.900700 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3180 13:38:23.900790 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3181 13:38:23.900878 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3182 13:38:23.900962 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3183 13:38:23.901046 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3184 13:38:23.901130 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3185 13:38:23.901223 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3186 13:38:23.901318 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3187 13:38:23.901404 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 13:38:23.901488 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3189 13:38:23.901572 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3190 13:38:23.901656 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3191 13:38:23.901750 ==
3192 13:38:23.901836 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 13:38:23.901922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 13:38:23.902006 ==
3195 13:38:23.902089 DQS Delay:
3196 13:38:23.902173 DQS0 = 0, DQS1 = 0
3197 13:38:23.902266 DQM Delay:
3198 13:38:23.902352 DQM0 = 116, DQM1 = 112
3199 13:38:23.902436 DQ Delay:
3200 13:38:23.902519 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3201 13:38:23.902603 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3202 13:38:23.902695 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3203 13:38:23.902784 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3204 13:38:23.902869
3205 13:38:23.902956
3206 13:38:23.903040 ==
3207 13:38:23.903124 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 13:38:23.903220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 13:38:23.903307 ==
3210 13:38:23.903392
3211 13:38:23.903474
3212 13:38:23.903558 TX Vref Scan disable
3213 13:38:23.903641 == TX Byte 0 ==
3214 13:38:23.903736 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3215 13:38:23.903830 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3216 13:38:23.903914 == TX Byte 1 ==
3217 13:38:23.903998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3218 13:38:23.904083 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3219 13:38:23.904170 ==
3220 13:38:23.904263 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 13:38:23.904349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 13:38:23.904433 ==
3223 13:38:23.904517 TX Vref=22, minBit 9, minWin=24, winSum=410
3224 13:38:23.904602 TX Vref=24, minBit 8, minWin=25, winSum=418
3225 13:38:23.904694 TX Vref=26, minBit 1, minWin=26, winSum=424
3226 13:38:23.904784 TX Vref=28, minBit 1, minWin=26, winSum=425
3227 13:38:23.904870 TX Vref=30, minBit 2, minWin=26, winSum=427
3228 13:38:23.904956 TX Vref=32, minBit 2, minWin=26, winSum=429
3229 13:38:23.905047 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 32
3230 13:38:23.905140
3231 13:38:23.905244 Final TX Range 1 Vref 32
3232 13:38:23.905347
3233 13:38:23.905440 ==
3234 13:38:23.905745 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 13:38:23.905849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 13:38:23.905942 ==
3237 13:38:23.906043
3238 13:38:23.906135
3239 13:38:23.906234 TX Vref Scan disable
3240 13:38:23.906324 == TX Byte 0 ==
3241 13:38:23.906410 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3242 13:38:23.906496 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3243 13:38:23.906580 == TX Byte 1 ==
3244 13:38:23.906664 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3245 13:38:23.906761 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3246 13:38:23.906848
3247 13:38:23.906932 [DATLAT]
3248 13:38:23.907015 Freq=1200, CH1 RK0
3249 13:38:23.907099
3250 13:38:23.907182 DATLAT Default: 0xd
3251 13:38:23.907276 0, 0xFFFF, sum = 0
3252 13:38:23.907365 1, 0xFFFF, sum = 0
3253 13:38:23.907451 2, 0xFFFF, sum = 0
3254 13:38:23.907536 3, 0xFFFF, sum = 0
3255 13:38:23.907621 4, 0xFFFF, sum = 0
3256 13:38:23.907713 5, 0xFFFF, sum = 0
3257 13:38:23.907810 6, 0xFFFF, sum = 0
3258 13:38:23.907907 7, 0xFFFF, sum = 0
3259 13:38:23.907994 8, 0xFFFF, sum = 0
3260 13:38:23.908079 9, 0xFFFF, sum = 0
3261 13:38:23.908164 10, 0xFFFF, sum = 0
3262 13:38:23.908262 11, 0xFFFF, sum = 0
3263 13:38:23.908351 12, 0x0, sum = 1
3264 13:38:23.908437 13, 0x0, sum = 2
3265 13:38:23.908522 14, 0x0, sum = 3
3266 13:38:23.908607 15, 0x0, sum = 4
3267 13:38:23.908700 best_step = 13
3268 13:38:23.908788
3269 13:38:23.908874 ==
3270 13:38:23.908958 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 13:38:23.909042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 13:38:23.909126 ==
3273 13:38:23.909220 RX Vref Scan: 1
3274 13:38:23.909317
3275 13:38:23.909403 Set Vref Range= 32 -> 127
3276 13:38:23.909487
3277 13:38:23.909570 RX Vref 32 -> 127, step: 1
3278 13:38:23.909653
3279 13:38:23.909748 RX Delay -13 -> 252, step: 4
3280 13:38:23.909834
3281 13:38:23.909918 Set Vref, RX VrefLevel [Byte0]: 32
3282 13:38:23.910002 [Byte1]: 32
3283 13:38:23.910086
3284 13:38:23.910169 Set Vref, RX VrefLevel [Byte0]: 33
3285 13:38:23.910264 [Byte1]: 33
3286 13:38:23.910351
3287 13:38:23.910435 Set Vref, RX VrefLevel [Byte0]: 34
3288 13:38:23.910518 [Byte1]: 34
3289 13:38:23.910601
3290 13:38:23.910685 Set Vref, RX VrefLevel [Byte0]: 35
3291 13:38:23.910780 [Byte1]: 35
3292 13:38:23.910867
3293 13:38:23.910954 Set Vref, RX VrefLevel [Byte0]: 36
3294 13:38:23.911037 [Byte1]: 36
3295 13:38:23.911119
3296 13:38:23.911204 Set Vref, RX VrefLevel [Byte0]: 37
3297 13:38:23.911298 [Byte1]: 37
3298 13:38:23.911384
3299 13:38:23.911468 Set Vref, RX VrefLevel [Byte0]: 38
3300 13:38:23.911551 [Byte1]: 38
3301 13:38:23.911633
3302 13:38:23.911726 Set Vref, RX VrefLevel [Byte0]: 39
3303 13:38:23.911814 [Byte1]: 39
3304 13:38:23.911899
3305 13:38:23.911982 Set Vref, RX VrefLevel [Byte0]: 40
3306 13:38:23.912065 [Byte1]: 40
3307 13:38:23.912148
3308 13:38:23.912242 Set Vref, RX VrefLevel [Byte0]: 41
3309 13:38:23.912330 [Byte1]: 41
3310 13:38:23.912414
3311 13:38:23.912497 Set Vref, RX VrefLevel [Byte0]: 42
3312 13:38:23.912581 [Byte1]: 42
3313 13:38:23.912663
3314 13:38:23.912757 Set Vref, RX VrefLevel [Byte0]: 43
3315 13:38:23.912844 [Byte1]: 43
3316 13:38:23.912928
3317 13:38:23.913010 Set Vref, RX VrefLevel [Byte0]: 44
3318 13:38:23.913093 [Byte1]: 44
3319 13:38:23.913176
3320 13:38:23.913275 Set Vref, RX VrefLevel [Byte0]: 45
3321 13:38:23.913337 [Byte1]: 45
3322 13:38:23.913396
3323 13:38:23.913479 Set Vref, RX VrefLevel [Byte0]: 46
3324 13:38:23.913562 [Byte1]: 46
3325 13:38:23.913644
3326 13:38:23.913727 Set Vref, RX VrefLevel [Byte0]: 47
3327 13:38:23.913802 [Byte1]: 47
3328 13:38:23.913861
3329 13:38:23.913934 Set Vref, RX VrefLevel [Byte0]: 48
3330 13:38:23.914018 [Byte1]: 48
3331 13:38:23.914100
3332 13:38:23.914182 Set Vref, RX VrefLevel [Byte0]: 49
3333 13:38:23.914277 [Byte1]: 49
3334 13:38:23.914363
3335 13:38:23.914448 Set Vref, RX VrefLevel [Byte0]: 50
3336 13:38:23.914533 [Byte1]: 50
3337 13:38:23.914615
3338 13:38:23.914698 Set Vref, RX VrefLevel [Byte0]: 51
3339 13:38:23.914792 [Byte1]: 51
3340 13:38:23.914878
3341 13:38:23.914962 Set Vref, RX VrefLevel [Byte0]: 52
3342 13:38:23.915045 [Byte1]: 52
3343 13:38:23.915127
3344 13:38:23.915209 Set Vref, RX VrefLevel [Byte0]: 53
3345 13:38:23.915303 [Byte1]: 53
3346 13:38:23.915388
3347 13:38:23.915472 Set Vref, RX VrefLevel [Byte0]: 54
3348 13:38:23.915556 [Byte1]: 54
3349 13:38:23.915638
3350 13:38:23.915721 Set Vref, RX VrefLevel [Byte0]: 55
3351 13:38:23.915810 [Byte1]: 55
3352 13:38:23.915898
3353 13:38:23.915981 Set Vref, RX VrefLevel [Byte0]: 56
3354 13:38:23.916065 [Byte1]: 56
3355 13:38:23.916128
3356 13:38:23.916202 Set Vref, RX VrefLevel [Byte0]: 57
3357 13:38:23.916286 [Byte1]: 57
3358 13:38:23.916379
3359 13:38:23.916464 Set Vref, RX VrefLevel [Byte0]: 58
3360 13:38:23.916547 [Byte1]: 58
3361 13:38:23.916631
3362 13:38:23.916715 Set Vref, RX VrefLevel [Byte0]: 59
3363 13:38:23.916799 [Byte1]: 59
3364 13:38:23.916893
3365 13:38:23.916977 Set Vref, RX VrefLevel [Byte0]: 60
3366 13:38:23.917060 [Byte1]: 60
3367 13:38:23.917145
3368 13:38:23.917229 Set Vref, RX VrefLevel [Byte0]: 61
3369 13:38:23.917304 [Byte1]: 61
3370 13:38:23.917377
3371 13:38:23.917435 Set Vref, RX VrefLevel [Byte0]: 62
3372 13:38:23.917488 [Byte1]: 62
3373 13:38:23.917541
3374 13:38:23.917598 Set Vref, RX VrefLevel [Byte0]: 63
3375 13:38:23.917655 [Byte1]: 63
3376 13:38:23.917711
3377 13:38:23.917763 Set Vref, RX VrefLevel [Byte0]: 64
3378 13:38:23.917818 [Byte1]: 64
3379 13:38:23.917894
3380 13:38:23.917951 Set Vref, RX VrefLevel [Byte0]: 65
3381 13:38:23.918004 [Byte1]: 65
3382 13:38:23.918058
3383 13:38:23.918111 Set Vref, RX VrefLevel [Byte0]: 66
3384 13:38:23.918167 [Byte1]: 66
3385 13:38:23.918251
3386 13:38:23.918334 Final RX Vref Byte 0 = 53 to rank0
3387 13:38:23.918431 Final RX Vref Byte 1 = 51 to rank0
3388 13:38:23.918520 Final RX Vref Byte 0 = 53 to rank1
3389 13:38:23.918605 Final RX Vref Byte 1 = 51 to rank1==
3390 13:38:23.918691 Dram Type= 6, Freq= 0, CH_1, rank 0
3391 13:38:23.918775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3392 13:38:23.918865 ==
3393 13:38:23.918955 DQS Delay:
3394 13:38:23.919038 DQS0 = 0, DQS1 = 0
3395 13:38:23.919121 DQM Delay:
3396 13:38:23.919206 DQM0 = 114, DQM1 = 113
3397 13:38:23.919289 DQ Delay:
3398 13:38:23.919380 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3399 13:38:23.919467 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3400 13:38:23.919551 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3401 13:38:23.919636 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =120
3402 13:38:23.919720
3403 13:38:23.919802
3404 13:38:23.920106 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3405 13:38:23.920198 CH1 RK0: MR19=304, MR18=F400
3406 13:38:23.920284 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3407 13:38:23.920374
3408 13:38:23.920455 ----->DramcWriteLeveling(PI) begin...
3409 13:38:23.920540 ==
3410 13:38:23.920626 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 13:38:23.920712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 13:38:23.920795 ==
3413 13:38:23.920884 Write leveling (Byte 0): 24 => 24
3414 13:38:23.920975 Write leveling (Byte 1): 28 => 28
3415 13:38:23.921058 DramcWriteLeveling(PI) end<-----
3416 13:38:23.921142
3417 13:38:23.921229 ==
3418 13:38:23.921310 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 13:38:23.921402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 13:38:23.921496 ==
3421 13:38:23.921580 [Gating] SW mode calibration
3422 13:38:23.921667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3423 13:38:23.921752 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3424 13:38:23.921839 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3425 13:38:23.921923 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 13:38:23.922007 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 13:38:23.922098 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 13:38:23.922161 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 13:38:23.922246 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 13:38:23.922330 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3431 13:38:23.922413 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3432 13:38:23.922496 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 13:38:23.922583 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 13:38:23.922677 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 13:38:23.922762 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 13:38:23.922846 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 13:38:23.922929 1 0 20 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3438 13:38:23.923012 1 0 24 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
3439 13:38:23.923105 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3440 13:38:23.923194 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 13:38:23.923278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 13:38:23.923361 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 13:38:23.923445 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 13:38:23.923528 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 13:38:23.923620 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3446 13:38:23.923709 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3447 13:38:23.923793 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3448 13:38:23.923876 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3449 13:38:23.923960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 13:38:23.924043 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 13:38:23.924138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 13:38:23.924224 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 13:38:23.924309 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 13:38:23.924393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 13:38:23.924476 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 13:38:23.924560 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 13:38:23.924655 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 13:38:23.924741 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 13:38:23.924825 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 13:38:23.924908 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 13:38:23.924991 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:38:23.925075 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3463 13:38:23.925170 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3464 13:38:23.925270 Total UI for P1: 0, mck2ui 16
3465 13:38:23.925358 best dqsien dly found for B0: ( 1, 3, 24)
3466 13:38:23.925442 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 13:38:23.925525 Total UI for P1: 0, mck2ui 16
3468 13:38:23.925609 best dqsien dly found for B1: ( 1, 3, 28)
3469 13:38:23.925704 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3470 13:38:23.925790 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3471 13:38:23.925872
3472 13:38:23.925956 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3473 13:38:23.926039 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3474 13:38:23.926122 [Gating] SW calibration Done
3475 13:38:23.926216 ==
3476 13:38:23.926301 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 13:38:23.926386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 13:38:23.926469 ==
3479 13:38:23.926552 RX Vref Scan: 0
3480 13:38:23.926636
3481 13:38:23.926728 RX Vref 0 -> 0, step: 1
3482 13:38:23.926811
3483 13:38:23.926895 RX Delay -40 -> 252, step: 8
3484 13:38:23.926979 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3485 13:38:23.927062 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3486 13:38:23.927150 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3487 13:38:23.927231 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3488 13:38:23.927314 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3489 13:38:23.927399 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3490 13:38:23.927484 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3491 13:38:23.927567 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3492 13:38:23.927659 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3493 13:38:23.927747 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3494 13:38:23.927830 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3495 13:38:23.927915 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3496 13:38:23.927998 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3497 13:38:23.928086 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3498 13:38:23.928170 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3499 13:38:23.928264 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3500 13:38:23.928349 ==
3501 13:38:23.928433 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 13:38:23.928728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 13:38:23.928828 ==
3504 13:38:23.928917 DQS Delay:
3505 13:38:23.929001 DQS0 = 0, DQS1 = 0
3506 13:38:23.929086 DQM Delay:
3507 13:38:23.929169 DQM0 = 115, DQM1 = 111
3508 13:38:23.929251 DQ Delay:
3509 13:38:23.929322 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3510 13:38:23.929394 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3511 13:38:23.929449 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3512 13:38:23.929503 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3513 13:38:23.929556
3514 13:38:23.929614
3515 13:38:23.929697 ==
3516 13:38:23.929780 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 13:38:23.929875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 13:38:23.929961 ==
3519 13:38:23.930044
3520 13:38:23.930126
3521 13:38:23.930215 TX Vref Scan disable
3522 13:38:23.930273 == TX Byte 0 ==
3523 13:38:23.930327 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3524 13:38:23.930404 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3525 13:38:23.930459 == TX Byte 1 ==
3526 13:38:23.930513 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3527 13:38:23.930566 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3528 13:38:23.930620 ==
3529 13:38:23.930672 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 13:38:23.930734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 13:38:23.930793 ==
3532 13:38:23.930859 TX Vref=22, minBit 3, minWin=25, winSum=422
3533 13:38:23.930949 TX Vref=24, minBit 3, minWin=25, winSum=422
3534 13:38:23.931033 TX Vref=26, minBit 2, minWin=26, winSum=427
3535 13:38:23.931117 TX Vref=28, minBit 3, minWin=26, winSum=434
3536 13:38:23.931200 TX Vref=30, minBit 3, minWin=26, winSum=433
3537 13:38:23.931286 TX Vref=32, minBit 3, minWin=26, winSum=430
3538 13:38:23.931374 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 28
3539 13:38:23.931434
3540 13:38:23.931487 Final TX Range 1 Vref 28
3541 13:38:23.931540
3542 13:38:23.931592 ==
3543 13:38:23.931645 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 13:38:23.931699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 13:38:23.931752 ==
3546 13:38:23.931808
3547 13:38:23.931890
3548 13:38:23.931974 TX Vref Scan disable
3549 13:38:23.932057 == TX Byte 0 ==
3550 13:38:23.932141 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3551 13:38:23.932228 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3552 13:38:23.932313 == TX Byte 1 ==
3553 13:38:23.932406 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3554 13:38:23.932491 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3555 13:38:23.932577
3556 13:38:23.932661 [DATLAT]
3557 13:38:23.932744 Freq=1200, CH1 RK1
3558 13:38:23.932828
3559 13:38:23.932917 DATLAT Default: 0xd
3560 13:38:23.933014 0, 0xFFFF, sum = 0
3561 13:38:23.933102 1, 0xFFFF, sum = 0
3562 13:38:23.933190 2, 0xFFFF, sum = 0
3563 13:38:23.933279 3, 0xFFFF, sum = 0
3564 13:38:23.933339 4, 0xFFFF, sum = 0
3565 13:38:23.933397 5, 0xFFFF, sum = 0
3566 13:38:23.933452 6, 0xFFFF, sum = 0
3567 13:38:23.933506 7, 0xFFFF, sum = 0
3568 13:38:23.933564 8, 0xFFFF, sum = 0
3569 13:38:23.933620 9, 0xFFFF, sum = 0
3570 13:38:23.933675 10, 0xFFFF, sum = 0
3571 13:38:23.933731 11, 0xFFFF, sum = 0
3572 13:38:23.933789 12, 0x0, sum = 1
3573 13:38:23.933843 13, 0x0, sum = 2
3574 13:38:23.933897 14, 0x0, sum = 3
3575 13:38:23.933950 15, 0x0, sum = 4
3576 13:38:23.934015 best_step = 13
3577 13:38:23.934068
3578 13:38:23.934120 ==
3579 13:38:23.934177 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 13:38:23.934262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 13:38:23.934345 ==
3582 13:38:23.934430 RX Vref Scan: 0
3583 13:38:23.934512
3584 13:38:23.934597 RX Vref 0 -> 0, step: 1
3585 13:38:23.934681
3586 13:38:23.934776 RX Delay -13 -> 252, step: 4
3587 13:38:23.934863 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3588 13:38:23.934948 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3589 13:38:23.935033 iDelay=191, Bit 2, Center 106 (39 ~ 174) 136
3590 13:38:23.935116 iDelay=191, Bit 3, Center 114 (47 ~ 182) 136
3591 13:38:23.935199 iDelay=191, Bit 4, Center 112 (43 ~ 182) 140
3592 13:38:23.935294 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3593 13:38:23.935379 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3594 13:38:23.935463 iDelay=191, Bit 7, Center 110 (39 ~ 182) 144
3595 13:38:23.935547 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3596 13:38:23.935631 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3597 13:38:23.935720 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3598 13:38:23.935811 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3599 13:38:23.935895 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3600 13:38:23.935978 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3601 13:38:23.936064 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3602 13:38:23.936147 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3603 13:38:23.936237 ==
3604 13:38:23.936299 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 13:38:23.936356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 13:38:23.936410 ==
3607 13:38:23.936463 DQS Delay:
3608 13:38:23.936516 DQS0 = 0, DQS1 = 0
3609 13:38:23.936589 DQM Delay:
3610 13:38:23.936671 DQM0 = 114, DQM1 = 112
3611 13:38:23.936765 DQ Delay:
3612 13:38:23.936851 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3613 13:38:23.936936 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =110
3614 13:38:23.937020 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3615 13:38:23.937105 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3616 13:38:23.937188
3617 13:38:23.937295
3618 13:38:23.937383 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0f, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3619 13:38:23.937468 CH1 RK1: MR19=304, MR18=FD0F
3620 13:38:23.937552 CH1_RK1: MR19=0x304, MR18=0xFD0F, DQSOSC=404, MR23=63, INC=40, DEC=26
3621 13:38:23.937644 [RxdqsGatingPostProcess] freq 1200
3622 13:38:23.937735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3623 13:38:23.937822 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 13:38:23.937911 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 13:38:23.937992 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 13:38:23.938074 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 13:38:23.938157 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 13:38:23.938254 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 13:38:23.938355 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 13:38:23.938442 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 13:38:23.938527 Pre-setting of DQS Precalculation
3632 13:38:23.938613 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3633 13:38:23.938699 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3634 13:38:23.938792 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3635 13:38:23.938879
3636 13:38:23.938961
3637 13:38:23.939044 [Calibration Summary] 2400 Mbps
3638 13:38:23.939127 CH 0, Rank 0
3639 13:38:23.939191 SW Impedance : PASS
3640 13:38:23.939245 DUTY Scan : NO K
3641 13:38:23.939325 ZQ Calibration : PASS
3642 13:38:23.939410 Jitter Meter : NO K
3643 13:38:23.939701 CBT Training : PASS
3644 13:38:23.939794 Write leveling : PASS
3645 13:38:23.939887 RX DQS gating : PASS
3646 13:38:23.939971 RX DQ/DQS(RDDQC) : PASS
3647 13:38:23.940054 TX DQ/DQS : PASS
3648 13:38:23.940138 RX DATLAT : PASS
3649 13:38:23.940223 RX DQ/DQS(Engine): PASS
3650 13:38:23.940314 TX OE : NO K
3651 13:38:23.940404 All Pass.
3652 13:38:23.940487
3653 13:38:23.940569 CH 0, Rank 1
3654 13:38:23.940652 SW Impedance : PASS
3655 13:38:23.940737 DUTY Scan : NO K
3656 13:38:23.940830 ZQ Calibration : PASS
3657 13:38:23.940917 Jitter Meter : NO K
3658 13:38:23.941001 CBT Training : PASS
3659 13:38:23.941084 Write leveling : PASS
3660 13:38:23.941166 RX DQS gating : PASS
3661 13:38:23.941251 RX DQ/DQS(RDDQC) : PASS
3662 13:38:23.941331 TX DQ/DQS : PASS
3663 13:38:23.941391 RX DATLAT : PASS
3664 13:38:23.941474 RX DQ/DQS(Engine): PASS
3665 13:38:23.941557 TX OE : NO K
3666 13:38:23.941640 All Pass.
3667 13:38:23.941723
3668 13:38:23.941779 CH 1, Rank 0
3669 13:38:23.941849 SW Impedance : PASS
3670 13:38:23.941911 DUTY Scan : NO K
3671 13:38:23.941995 ZQ Calibration : PASS
3672 13:38:23.942078 Jitter Meter : NO K
3673 13:38:23.942160 CBT Training : PASS
3674 13:38:23.942245 Write leveling : PASS
3675 13:38:23.942337 RX DQS gating : PASS
3676 13:38:23.942424 RX DQ/DQS(RDDQC) : PASS
3677 13:38:23.942508 TX DQ/DQS : PASS
3678 13:38:23.942591 RX DATLAT : PASS
3679 13:38:23.942674 RX DQ/DQS(Engine): PASS
3680 13:38:23.942756 TX OE : NO K
3681 13:38:23.942839 All Pass.
3682 13:38:23.942928
3683 13:38:23.943019 CH 1, Rank 1
3684 13:38:23.943102 SW Impedance : PASS
3685 13:38:23.943185 DUTY Scan : NO K
3686 13:38:23.943268 ZQ Calibration : PASS
3687 13:38:23.943352 Jitter Meter : NO K
3688 13:38:23.943436 CBT Training : PASS
3689 13:38:23.943531 Write leveling : PASS
3690 13:38:23.943614 RX DQS gating : PASS
3691 13:38:23.943698 RX DQ/DQS(RDDQC) : PASS
3692 13:38:23.943783 TX DQ/DQS : PASS
3693 13:38:23.943867 RX DATLAT : PASS
3694 13:38:23.943950 RX DQ/DQS(Engine): PASS
3695 13:38:23.944043 TX OE : NO K
3696 13:38:23.944129 All Pass.
3697 13:38:23.944213
3698 13:38:23.944295 DramC Write-DBI off
3699 13:38:23.944378 PER_BANK_REFRESH: Hybrid Mode
3700 13:38:23.944461 TX_TRACKING: ON
3701 13:38:23.944558 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3702 13:38:23.944644 [FAST_K] Save calibration result to emmc
3703 13:38:23.944728 dramc_set_vcore_voltage set vcore to 650000
3704 13:38:23.944811 Read voltage for 600, 5
3705 13:38:23.944893 Vio18 = 0
3706 13:38:23.944984 Vcore = 650000
3707 13:38:23.945072 Vdram = 0
3708 13:38:23.945155 Vddq = 0
3709 13:38:23.945237 Vmddr = 0
3710 13:38:23.945328 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3711 13:38:23.945412 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3712 13:38:23.945507 MEM_TYPE=3, freq_sel=19
3713 13:38:23.945593 sv_algorithm_assistance_LP4_1600
3714 13:38:23.945677 ============ PULL DRAM RESETB DOWN ============
3715 13:38:23.945761 ========== PULL DRAM RESETB DOWN end =========
3716 13:38:23.945846 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3717 13:38:23.945929 ===================================
3718 13:38:23.946012 LPDDR4 DRAM CONFIGURATION
3719 13:38:23.946108 ===================================
3720 13:38:23.946194 EX_ROW_EN[0] = 0x0
3721 13:38:23.946277 EX_ROW_EN[1] = 0x0
3722 13:38:23.946361 LP4Y_EN = 0x0
3723 13:38:23.946447 WORK_FSP = 0x0
3724 13:38:23.946504 WL = 0x2
3725 13:38:23.946584 RL = 0x2
3726 13:38:23.946669 BL = 0x2
3727 13:38:23.946752 RPST = 0x0
3728 13:38:23.946834 RD_PRE = 0x0
3729 13:38:23.946917 WR_PRE = 0x1
3730 13:38:23.946999 WR_PST = 0x0
3731 13:38:23.947093 DBI_WR = 0x0
3732 13:38:23.947179 DBI_RD = 0x0
3733 13:38:23.947262 OTF = 0x1
3734 13:38:23.947345 ===================================
3735 13:38:23.947429 ===================================
3736 13:38:23.947513 ANA top config
3737 13:38:23.947607 ===================================
3738 13:38:23.947693 DLL_ASYNC_EN = 0
3739 13:38:23.947777 ALL_SLAVE_EN = 1
3740 13:38:23.947860 NEW_RANK_MODE = 1
3741 13:38:23.947943 DLL_IDLE_MODE = 1
3742 13:38:23.948026 LP45_APHY_COMB_EN = 1
3743 13:38:23.948121 TX_ODT_DIS = 1
3744 13:38:23.948207 NEW_8X_MODE = 1
3745 13:38:23.948292 ===================================
3746 13:38:23.948375 ===================================
3747 13:38:23.948458 data_rate = 1200
3748 13:38:23.948545 CKR = 1
3749 13:38:23.948639 DQ_P2S_RATIO = 8
3750 13:38:23.948725 ===================================
3751 13:38:23.948808 CA_P2S_RATIO = 8
3752 13:38:23.948891 DQ_CA_OPEN = 0
3753 13:38:23.948974 DQ_SEMI_OPEN = 0
3754 13:38:23.949056 CA_SEMI_OPEN = 0
3755 13:38:23.949150 CA_FULL_RATE = 0
3756 13:38:23.949235 DQ_CKDIV4_EN = 1
3757 13:38:23.949327 CA_CKDIV4_EN = 1
3758 13:38:23.949410 CA_PREDIV_EN = 0
3759 13:38:23.949492 PH8_DLY = 0
3760 13:38:23.949576 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3761 13:38:23.949649 DQ_AAMCK_DIV = 4
3762 13:38:23.949721 CA_AAMCK_DIV = 4
3763 13:38:23.949804 CA_ADMCK_DIV = 4
3764 13:38:23.949887 DQ_TRACK_CA_EN = 0
3765 13:38:23.949969 CA_PICK = 600
3766 13:38:23.950052 CA_MCKIO = 600
3767 13:38:23.950147 MCKIO_SEMI = 0
3768 13:38:23.950231 PLL_FREQ = 2288
3769 13:38:23.950314 DQ_UI_PI_RATIO = 32
3770 13:38:23.950398 CA_UI_PI_RATIO = 0
3771 13:38:23.950481 ===================================
3772 13:38:23.950563 ===================================
3773 13:38:23.950635 memory_type:LPDDR4
3774 13:38:23.950695 GP_NUM : 10
3775 13:38:23.950748 SRAM_EN : 1
3776 13:38:23.950803 MD32_EN : 0
3777 13:38:23.950856 ===================================
3778 13:38:23.950910 [ANA_INIT] >>>>>>>>>>>>>>
3779 13:38:23.950963 <<<<<< [CONFIGURE PHASE]: ANA_TX
3780 13:38:23.951019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3781 13:38:23.951073 ===================================
3782 13:38:23.951140 data_rate = 1200,PCW = 0X5800
3783 13:38:23.951200 ===================================
3784 13:38:23.951254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3785 13:38:23.951308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3786 13:38:23.951361 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 13:38:23.951624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3788 13:38:23.951722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3789 13:38:23.951807 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3790 13:38:23.951891 [ANA_INIT] flow start
3791 13:38:23.951974 [ANA_INIT] PLL >>>>>>>>
3792 13:38:23.952058 [ANA_INIT] PLL <<<<<<<<
3793 13:38:23.952146 [ANA_INIT] MIDPI >>>>>>>>
3794 13:38:23.952236 [ANA_INIT] MIDPI <<<<<<<<
3795 13:38:23.952319 [ANA_INIT] DLL >>>>>>>>
3796 13:38:23.952401 [ANA_INIT] flow end
3797 13:38:23.952484 ============ LP4 DIFF to SE enter ============
3798 13:38:23.952573 ============ LP4 DIFF to SE exit ============
3799 13:38:23.952665 [ANA_INIT] <<<<<<<<<<<<<
3800 13:38:23.952753 [Flow] Enable top DCM control >>>>>
3801 13:38:23.952836 [Flow] Enable top DCM control <<<<<
3802 13:38:23.952920 Enable DLL master slave shuffle
3803 13:38:23.953003 ==============================================================
3804 13:38:23.953089 Gating Mode config
3805 13:38:23.953182 ==============================================================
3806 13:38:23.953278 Config description:
3807 13:38:23.953364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3808 13:38:23.953450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3809 13:38:23.953534 SELPH_MODE 0: By rank 1: By Phase
3810 13:38:23.953620 ==============================================================
3811 13:38:23.953716 GAT_TRACK_EN = 1
3812 13:38:23.953802 RX_GATING_MODE = 2
3813 13:38:23.953885 RX_GATING_TRACK_MODE = 2
3814 13:38:23.953968 SELPH_MODE = 1
3815 13:38:23.954051 PICG_EARLY_EN = 1
3816 13:38:23.954137 VALID_LAT_VALUE = 1
3817 13:38:23.954232 ==============================================================
3818 13:38:23.954316 Enter into Gating configuration >>>>
3819 13:38:23.954404 Exit from Gating configuration <<<<
3820 13:38:23.954487 Enter into DVFS_PRE_config >>>>>
3821 13:38:23.954572 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3822 13:38:23.954663 Exit from DVFS_PRE_config <<<<<
3823 13:38:23.954754 Enter into PICG configuration >>>>
3824 13:38:23.954838 Exit from PICG configuration <<<<
3825 13:38:23.954921 [RX_INPUT] configuration >>>>>
3826 13:38:23.955003 [RX_INPUT] configuration <<<<<
3827 13:38:23.955086 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3828 13:38:23.955149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3829 13:38:23.955237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3830 13:38:23.955322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3831 13:38:23.955406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 13:38:23.955490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 13:38:23.955573 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3834 13:38:23.955658 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3835 13:38:23.955753 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3836 13:38:23.955842 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3837 13:38:23.955900 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3838 13:38:23.955954 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3839 13:38:23.956007 ===================================
3840 13:38:23.956061 LPDDR4 DRAM CONFIGURATION
3841 13:38:23.956113 ===================================
3842 13:38:23.956170 EX_ROW_EN[0] = 0x0
3843 13:38:23.956264 EX_ROW_EN[1] = 0x0
3844 13:38:23.956347 LP4Y_EN = 0x0
3845 13:38:23.956430 WORK_FSP = 0x0
3846 13:38:23.956512 WL = 0x2
3847 13:38:23.956599 RL = 0x2
3848 13:38:23.956684 BL = 0x2
3849 13:38:23.956778 RPST = 0x0
3850 13:38:23.956862 RD_PRE = 0x0
3851 13:38:23.956945 WR_PRE = 0x1
3852 13:38:23.957027 WR_PST = 0x0
3853 13:38:23.957109 DBI_WR = 0x0
3854 13:38:23.957193 DBI_RD = 0x0
3855 13:38:23.957293 OTF = 0x1
3856 13:38:23.957379 ===================================
3857 13:38:23.957463 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3858 13:38:23.957546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3859 13:38:23.957630 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 13:38:23.957715 ===================================
3861 13:38:23.957810 LPDDR4 DRAM CONFIGURATION
3862 13:38:23.957895 ===================================
3863 13:38:23.957978 EX_ROW_EN[0] = 0x10
3864 13:38:23.958061 EX_ROW_EN[1] = 0x0
3865 13:38:23.958143 LP4Y_EN = 0x0
3866 13:38:23.958228 WORK_FSP = 0x0
3867 13:38:23.958321 WL = 0x2
3868 13:38:23.958405 RL = 0x2
3869 13:38:23.958478 BL = 0x2
3870 13:38:23.958532 RPST = 0x0
3871 13:38:23.958601 RD_PRE = 0x0
3872 13:38:23.958655 WR_PRE = 0x1
3873 13:38:23.958708 WR_PST = 0x0
3874 13:38:23.958764 DBI_WR = 0x0
3875 13:38:23.958839 DBI_RD = 0x0
3876 13:38:23.958893 OTF = 0x1
3877 13:38:23.958947 ===================================
3878 13:38:23.959000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3879 13:38:23.959054 nWR fixed to 30
3880 13:38:23.959108 [ModeRegInit_LP4] CH0 RK0
3881 13:38:23.959161 [ModeRegInit_LP4] CH0 RK1
3882 13:38:23.959216 [ModeRegInit_LP4] CH1 RK0
3883 13:38:23.959274 [ModeRegInit_LP4] CH1 RK1
3884 13:38:23.959344 match AC timing 17
3885 13:38:23.959399 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3886 13:38:23.959452 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3887 13:38:23.959505 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3888 13:38:23.959560 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3889 13:38:23.959614 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3890 13:38:23.959667 ==
3891 13:38:23.959720 Dram Type= 6, Freq= 0, CH_0, rank 0
3892 13:38:23.959774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3893 13:38:23.959828 ==
3894 13:38:23.959899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3895 13:38:23.959988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3896 13:38:23.960283 [CA 0] Center 36 (6~67) winsize 62
3897 13:38:23.960375 [CA 1] Center 36 (6~67) winsize 62
3898 13:38:23.960474 [CA 2] Center 34 (4~65) winsize 62
3899 13:38:23.960561 [CA 3] Center 34 (4~65) winsize 62
3900 13:38:23.960645 [CA 4] Center 33 (3~64) winsize 62
3901 13:38:23.960729 [CA 5] Center 33 (3~64) winsize 62
3902 13:38:23.960811
3903 13:38:23.960903 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3904 13:38:23.960991
3905 13:38:23.961075 [CATrainingPosCal] consider 1 rank data
3906 13:38:23.961158 u2DelayCellTimex100 = 270/100 ps
3907 13:38:23.961241 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3908 13:38:23.961336 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3909 13:38:23.961431 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3910 13:38:23.961519 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3911 13:38:23.961603 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3912 13:38:23.961686 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3913 13:38:23.961767
3914 13:38:23.961851 CA PerBit enable=1, Macro0, CA PI delay=33
3915 13:38:23.961943
3916 13:38:23.962030 [CBTSetCACLKResult] CA Dly = 33
3917 13:38:23.962113 CS Dly: 6 (0~37)
3918 13:38:23.962195 ==
3919 13:38:23.962278 Dram Type= 6, Freq= 0, CH_0, rank 1
3920 13:38:23.962362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 13:38:23.962456 ==
3922 13:38:23.962544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 13:38:23.962629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3924 13:38:23.962712 [CA 0] Center 36 (6~67) winsize 62
3925 13:38:23.962795 [CA 1] Center 36 (6~67) winsize 62
3926 13:38:24.628546 [CA 2] Center 34 (4~65) winsize 62
3927 13:38:24.628688 [CA 3] Center 34 (4~65) winsize 62
3928 13:38:24.628763 [CA 4] Center 34 (3~65) winsize 63
3929 13:38:24.628826 [CA 5] Center 33 (3~64) winsize 62
3930 13:38:24.628886
3931 13:38:24.628944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3932 13:38:24.629002
3933 13:38:24.629075 [CATrainingPosCal] consider 2 rank data
3934 13:38:24.629133 u2DelayCellTimex100 = 270/100 ps
3935 13:38:24.629189 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 13:38:24.629245 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 13:38:24.629314 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 13:38:24.629370 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 13:38:24.629426 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 13:38:24.629480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 13:38:24.629550
3942 13:38:24.629609 CA PerBit enable=1, Macro0, CA PI delay=33
3943 13:38:24.629665
3944 13:38:24.629720 [CBTSetCACLKResult] CA Dly = 33
3945 13:38:24.629774 CS Dly: 6 (0~37)
3946 13:38:24.629828
3947 13:38:24.629886 ----->DramcWriteLeveling(PI) begin...
3948 13:38:24.629971 ==
3949 13:38:24.630034 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 13:38:24.630099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 13:38:24.630155 ==
3952 13:38:24.630210 Write leveling (Byte 0): 33 => 33
3953 13:38:24.630264 Write leveling (Byte 1): 29 => 29
3954 13:38:24.630319 DramcWriteLeveling(PI) end<-----
3955 13:38:24.630395
3956 13:38:24.630474 ==
3957 13:38:24.630560 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 13:38:24.630620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 13:38:24.630676 ==
3960 13:38:24.630730 [Gating] SW mode calibration
3961 13:38:24.630785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3962 13:38:24.630840 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3963 13:38:24.630896 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 13:38:24.630951 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 13:38:24.631005 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 13:38:24.631073 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
3967 13:38:24.631130 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
3968 13:38:24.631185 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 13:38:24.631240 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 13:38:24.631298 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 13:38:24.631352 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 13:38:24.631406 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 13:38:24.631461 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 13:38:24.631515 0 10 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
3975 13:38:24.631587 0 10 16 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
3976 13:38:24.631643 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 13:38:24.631698 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 13:38:24.631753 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 13:38:24.631808 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 13:38:24.631862 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 13:38:24.631916 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 13:38:24.631969 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3983 13:38:24.632023 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3984 13:38:24.632095 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 13:38:24.632150 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 13:38:24.632205 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 13:38:24.632259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 13:38:24.632313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 13:38:24.632367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 13:38:24.632421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:38:24.632475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:38:24.632528 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:38:24.632598 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 13:38:24.632686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 13:38:24.632743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 13:38:24.632799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:38:24.632854 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:38:24.632908 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3999 13:38:24.632963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4000 13:38:24.633017 Total UI for P1: 0, mck2ui 16
4001 13:38:24.633114 best dqsien dly found for B0: ( 0, 13, 12)
4002 13:38:24.633423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 13:38:24.633493 Total UI for P1: 0, mck2ui 16
4004 13:38:24.633554 best dqsien dly found for B1: ( 0, 13, 16)
4005 13:38:24.633615 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4006 13:38:24.633674 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4007 13:38:24.633729
4008 13:38:24.633784 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4009 13:38:24.633840 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4010 13:38:24.633895 [Gating] SW calibration Done
4011 13:38:24.633949 ==
4012 13:38:24.634003 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 13:38:24.634058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 13:38:24.634113 ==
4015 13:38:24.634172 RX Vref Scan: 0
4016 13:38:24.634227
4017 13:38:24.634281 RX Vref 0 -> 0, step: 1
4018 13:38:24.634336
4019 13:38:24.634389 RX Delay -230 -> 252, step: 16
4020 13:38:24.634444 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4021 13:38:24.634498 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4022 13:38:24.634552 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4023 13:38:24.634606 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4024 13:38:24.634664 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4025 13:38:24.634720 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4026 13:38:24.634774 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4027 13:38:24.634829 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4028 13:38:24.634883 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4029 13:38:24.634937 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4030 13:38:24.634990 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4031 13:38:24.635044 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4032 13:38:24.635098 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4033 13:38:24.635176 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4034 13:38:24.635262 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4035 13:38:24.635341 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4036 13:38:24.635415 ==
4037 13:38:24.635470 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 13:38:24.635525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 13:38:24.635584 ==
4040 13:38:24.635640 DQS Delay:
4041 13:38:24.635693 DQS0 = 0, DQS1 = 0
4042 13:38:24.635747 DQM Delay:
4043 13:38:24.635801 DQM0 = 42, DQM1 = 33
4044 13:38:24.635854 DQ Delay:
4045 13:38:24.635908 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4046 13:38:24.635962 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4047 13:38:24.636016 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4048 13:38:24.636074 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4049 13:38:24.636129
4050 13:38:24.636182
4051 13:38:24.636235 ==
4052 13:38:24.636338 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 13:38:24.636400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 13:38:24.636456 ==
4055 13:38:24.636517
4056 13:38:24.636601
4057 13:38:24.636659 TX Vref Scan disable
4058 13:38:24.636714 == TX Byte 0 ==
4059 13:38:24.636768 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4060 13:38:24.636824 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4061 13:38:24.636878 == TX Byte 1 ==
4062 13:38:24.636932 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4063 13:38:24.636986 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4064 13:38:24.637063 ==
4065 13:38:24.637147 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 13:38:24.637226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 13:38:24.637308 ==
4068 13:38:24.637364
4069 13:38:24.637418
4070 13:38:24.637472 TX Vref Scan disable
4071 13:38:24.637533 == TX Byte 0 ==
4072 13:38:24.637588 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4073 13:38:24.637643 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4074 13:38:24.637698 == TX Byte 1 ==
4075 13:38:24.637751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4076 13:38:24.637806 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4077 13:38:24.637860
4078 13:38:24.637914 [DATLAT]
4079 13:38:24.637975 Freq=600, CH0 RK0
4080 13:38:24.638030
4081 13:38:24.638084 DATLAT Default: 0x9
4082 13:38:24.638137 0, 0xFFFF, sum = 0
4083 13:38:24.638192 1, 0xFFFF, sum = 0
4084 13:38:24.638247 2, 0xFFFF, sum = 0
4085 13:38:24.638302 3, 0xFFFF, sum = 0
4086 13:38:24.638356 4, 0xFFFF, sum = 0
4087 13:38:24.638417 5, 0xFFFF, sum = 0
4088 13:38:24.638473 6, 0xFFFF, sum = 0
4089 13:38:24.638528 7, 0xFFFF, sum = 0
4090 13:38:24.638582 8, 0x0, sum = 1
4091 13:38:24.638637 9, 0x0, sum = 2
4092 13:38:24.638691 10, 0x0, sum = 3
4093 13:38:24.638745 11, 0x0, sum = 4
4094 13:38:24.638800 best_step = 9
4095 13:38:24.638852
4096 13:38:24.638937 ==
4097 13:38:24.639019 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 13:38:24.639097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 13:38:24.639163 ==
4100 13:38:24.639217 RX Vref Scan: 1
4101 13:38:24.639271
4102 13:38:24.639325 RX Vref 0 -> 0, step: 1
4103 13:38:24.639384
4104 13:38:24.639437 RX Delay -195 -> 252, step: 8
4105 13:38:24.639532
4106 13:38:24.639618 Set Vref, RX VrefLevel [Byte0]: 50
4107 13:38:24.639702 [Byte1]: 58
4108 13:38:24.639786
4109 13:38:24.639874 Final RX Vref Byte 0 = 50 to rank0
4110 13:38:24.639959 Final RX Vref Byte 1 = 58 to rank0
4111 13:38:24.640043 Final RX Vref Byte 0 = 50 to rank1
4112 13:38:24.640128 Final RX Vref Byte 1 = 58 to rank1==
4113 13:38:24.640212 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 13:38:24.640300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 13:38:24.640385 ==
4116 13:38:24.640469 DQS Delay:
4117 13:38:24.640553 DQS0 = 0, DQS1 = 0
4118 13:38:24.640637 DQM Delay:
4119 13:38:24.640720 DQM0 = 40, DQM1 = 32
4120 13:38:24.640815 DQ Delay:
4121 13:38:24.640902 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4122 13:38:24.640982 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4123 13:38:24.641063 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4124 13:38:24.641148 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4125 13:38:24.641232
4126 13:38:24.641328
4127 13:38:24.641414 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4128 13:38:24.641499 CH0 RK0: MR19=808, MR18=4F47
4129 13:38:24.641585 CH0_RK0: MR19=0x808, MR18=0x4F47, DQSOSC=394, MR23=63, INC=168, DEC=112
4130 13:38:24.641669
4131 13:38:24.641756 ----->DramcWriteLeveling(PI) begin...
4132 13:38:24.641843 ==
4133 13:38:24.641927 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 13:38:24.642012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 13:38:24.642095 ==
4136 13:38:24.642180 Write leveling (Byte 0): 34 => 34
4137 13:38:24.642268 Write leveling (Byte 1): 29 => 29
4138 13:38:24.642352 DramcWriteLeveling(PI) end<-----
4139 13:38:24.642436
4140 13:38:24.642519 ==
4141 13:38:24.642603 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 13:38:24.642697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 13:38:24.642785 ==
4144 13:38:24.642864 [Gating] SW mode calibration
4145 13:38:24.642938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4146 13:38:24.642995 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4147 13:38:24.643049 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 13:38:24.643104 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 13:38:24.643398 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 13:38:24.643462 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4151 13:38:24.643518 0 9 16 | B1->B0 | 2727 2727 | 1 0 | (1 0) (0 0)
4152 13:38:24.643573 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 13:38:24.643636 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 13:38:24.643691 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 13:38:24.643746 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 13:38:24.643800 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 13:38:24.643854 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 13:38:24.643908 0 10 12 | B1->B0 | 2424 3231 | 0 1 | (0 0) (0 0)
4159 13:38:24.643962 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4160 13:38:24.644016 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 13:38:24.644075 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 13:38:24.644130 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 13:38:24.644185 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 13:38:24.644238 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 13:38:24.644292 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 13:38:24.644346 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 13:38:24.644399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4168 13:38:24.644453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 13:38:24.644507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 13:38:24.644597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 13:38:24.644678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 13:38:24.644756 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 13:38:24.644815 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 13:38:24.644870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 13:38:24.644923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 13:38:24.644981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 13:38:24.645037 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 13:38:24.645091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 13:38:24.645145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 13:38:24.645199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:38:24.645253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:38:24.645318 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:38:24.645380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4184 13:38:24.645472 Total UI for P1: 0, mck2ui 16
4185 13:38:24.645562 best dqsien dly found for B0: ( 0, 13, 14)
4186 13:38:24.645646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 13:38:24.645704 Total UI for P1: 0, mck2ui 16
4188 13:38:24.645759 best dqsien dly found for B1: ( 0, 13, 16)
4189 13:38:24.645814 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4190 13:38:24.645869 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4191 13:38:24.645923
4192 13:38:24.645982 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4193 13:38:24.646037 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4194 13:38:24.646091 [Gating] SW calibration Done
4195 13:38:24.646145 ==
4196 13:38:24.646200 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 13:38:24.646254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 13:38:24.646308 ==
4199 13:38:24.646361 RX Vref Scan: 0
4200 13:38:24.646436
4201 13:38:24.646520 RX Vref 0 -> 0, step: 1
4202 13:38:24.646598
4203 13:38:24.646670 RX Delay -230 -> 252, step: 16
4204 13:38:24.646726 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4205 13:38:24.646781 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4206 13:38:24.646836 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4207 13:38:24.646897 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4208 13:38:24.646953 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4209 13:38:24.647007 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4210 13:38:24.647061 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4211 13:38:24.647115 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4212 13:38:24.647169 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4213 13:38:24.647223 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4214 13:38:24.647277 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4215 13:38:24.647330 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4216 13:38:24.647390 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4217 13:38:24.647444 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4218 13:38:24.647498 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4219 13:38:24.647552 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4220 13:38:24.647605 ==
4221 13:38:24.647658 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 13:38:24.647712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 13:38:24.647766 ==
4224 13:38:24.647824 DQS Delay:
4225 13:38:24.647879 DQS0 = 0, DQS1 = 0
4226 13:38:24.647932 DQM Delay:
4227 13:38:24.647986 DQM0 = 41, DQM1 = 32
4228 13:38:24.648039 DQ Delay:
4229 13:38:24.648093 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4230 13:38:24.648146 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =41
4231 13:38:24.648200 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4232 13:38:24.648253 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4233 13:38:24.648333
4234 13:38:24.648418
4235 13:38:24.648495 ==
4236 13:38:24.648570 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 13:38:24.648625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 13:38:24.648679 ==
4239 13:38:24.648733
4240 13:38:24.648791
4241 13:38:24.648846 TX Vref Scan disable
4242 13:38:24.648899 == TX Byte 0 ==
4243 13:38:24.648953 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4244 13:38:24.649008 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4245 13:38:24.649062 == TX Byte 1 ==
4246 13:38:24.649115 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4247 13:38:24.649168 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4248 13:38:24.649223 ==
4249 13:38:24.649284 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 13:38:24.649345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 13:38:24.649400 ==
4252 13:38:24.649454
4253 13:38:24.649507
4254 13:38:24.649560 TX Vref Scan disable
4255 13:38:24.649613 == TX Byte 0 ==
4256 13:38:24.649667 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4257 13:38:24.649721 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4258 13:38:24.649775 == TX Byte 1 ==
4259 13:38:24.649835 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4260 13:38:24.650088 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4261 13:38:24.650149
4262 13:38:24.650203 [DATLAT]
4263 13:38:24.650266 Freq=600, CH0 RK1
4264 13:38:24.650358
4265 13:38:24.650437 DATLAT Default: 0x9
4266 13:38:24.650515 0, 0xFFFF, sum = 0
4267 13:38:24.650573 1, 0xFFFF, sum = 0
4268 13:38:24.650628 2, 0xFFFF, sum = 0
4269 13:38:24.650683 3, 0xFFFF, sum = 0
4270 13:38:24.650743 4, 0xFFFF, sum = 0
4271 13:38:24.650800 5, 0xFFFF, sum = 0
4272 13:38:24.650855 6, 0xFFFF, sum = 0
4273 13:38:24.650910 7, 0xFFFF, sum = 0
4274 13:38:24.650965 8, 0x0, sum = 1
4275 13:38:24.651020 9, 0x0, sum = 2
4276 13:38:24.651075 10, 0x0, sum = 3
4277 13:38:24.651130 11, 0x0, sum = 4
4278 13:38:24.651186 best_step = 9
4279 13:38:24.651248
4280 13:38:24.651303 ==
4281 13:38:24.651357 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 13:38:24.651412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 13:38:24.651466 ==
4284 13:38:24.651521 RX Vref Scan: 0
4285 13:38:24.651575
4286 13:38:24.651629 RX Vref 0 -> 0, step: 1
4287 13:38:24.651687
4288 13:38:24.651743 RX Delay -195 -> 252, step: 8
4289 13:38:24.651798 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4290 13:38:24.651852 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4291 13:38:24.651906 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4292 13:38:24.651961 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4293 13:38:24.652014 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4294 13:38:24.652068 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4295 13:38:24.652121 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4296 13:38:24.652208 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4297 13:38:24.652289 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4298 13:38:24.652368 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4299 13:38:24.652430 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4300 13:38:24.652485 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4301 13:38:24.652538 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4302 13:38:24.652592 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4303 13:38:24.652653 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4304 13:38:24.652707 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4305 13:38:24.652761 ==
4306 13:38:24.652815 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 13:38:24.652869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 13:38:24.652923 ==
4309 13:38:24.652977 DQS Delay:
4310 13:38:24.653030 DQS0 = 0, DQS1 = 0
4311 13:38:24.653103 DQM Delay:
4312 13:38:24.653187 DQM0 = 41, DQM1 = 33
4313 13:38:24.653281 DQ Delay:
4314 13:38:24.653368 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4315 13:38:24.653454 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4316 13:38:24.653527 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4317 13:38:24.653594 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4318 13:38:24.653649
4319 13:38:24.653704
4320 13:38:24.653758 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4321 13:38:24.653814 CH0 RK1: MR19=808, MR18=4B47
4322 13:38:24.653868 CH0_RK1: MR19=0x808, MR18=0x4B47, DQSOSC=395, MR23=63, INC=168, DEC=112
4323 13:38:24.653922 [RxdqsGatingPostProcess] freq 600
4324 13:38:24.653976 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 13:38:24.654040 Pre-setting of DQS Precalculation
4326 13:38:24.654128 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 13:38:24.654208 ==
4328 13:38:24.654285 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 13:38:24.654340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 13:38:24.654395 ==
4331 13:38:24.654451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 13:38:24.654513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4333 13:38:24.654568 [CA 0] Center 35 (5~66) winsize 62
4334 13:38:24.654622 [CA 1] Center 35 (5~66) winsize 62
4335 13:38:24.654675 [CA 2] Center 34 (4~65) winsize 62
4336 13:38:24.654729 [CA 3] Center 34 (4~65) winsize 62
4337 13:38:24.654782 [CA 4] Center 34 (4~65) winsize 62
4338 13:38:24.654836 [CA 5] Center 34 (3~65) winsize 63
4339 13:38:24.654889
4340 13:38:24.654947 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4341 13:38:24.655003
4342 13:38:24.655057 [CATrainingPosCal] consider 1 rank data
4343 13:38:24.655110 u2DelayCellTimex100 = 270/100 ps
4344 13:38:24.655164 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4345 13:38:24.655218 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4346 13:38:24.655271 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4347 13:38:24.655325 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4348 13:38:24.655397 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4349 13:38:24.655460 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4350 13:38:24.655515
4351 13:38:24.661977 CA PerBit enable=1, Macro0, CA PI delay=34
4352 13:38:24.662068
4353 13:38:24.665400 [CBTSetCACLKResult] CA Dly = 34
4354 13:38:24.665512 CS Dly: 4 (0~35)
4355 13:38:24.665590 ==
4356 13:38:24.668686 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 13:38:24.671917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 13:38:24.672006 ==
4359 13:38:24.678798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 13:38:24.685528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4361 13:38:24.688889 [CA 0] Center 36 (6~66) winsize 61
4362 13:38:24.691732 [CA 1] Center 35 (5~66) winsize 62
4363 13:38:24.695322 [CA 2] Center 34 (4~65) winsize 62
4364 13:38:24.698447 [CA 3] Center 33 (3~64) winsize 62
4365 13:38:24.701500 [CA 4] Center 34 (4~65) winsize 62
4366 13:38:24.705165 [CA 5] Center 33 (3~64) winsize 62
4367 13:38:24.705329
4368 13:38:24.708435 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4369 13:38:24.708542
4370 13:38:24.711542 [CATrainingPosCal] consider 2 rank data
4371 13:38:24.714537 u2DelayCellTimex100 = 270/100 ps
4372 13:38:24.718016 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4373 13:38:24.721211 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 13:38:24.724536 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 13:38:24.727876 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4376 13:38:24.734765 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 13:38:24.738172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 13:38:24.738290
4379 13:38:24.741170 CA PerBit enable=1, Macro0, CA PI delay=33
4380 13:38:24.741292
4381 13:38:24.744595 [CBTSetCACLKResult] CA Dly = 33
4382 13:38:24.744711 CS Dly: 4 (0~35)
4383 13:38:24.744809
4384 13:38:24.747596 ----->DramcWriteLeveling(PI) begin...
4385 13:38:24.747711 ==
4386 13:38:24.750759 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 13:38:24.757846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 13:38:24.757973 ==
4389 13:38:24.761133 Write leveling (Byte 0): 29 => 29
4390 13:38:24.764319 Write leveling (Byte 1): 31 => 31
4391 13:38:24.764434 DramcWriteLeveling(PI) end<-----
4392 13:38:24.767534
4393 13:38:24.767648 ==
4394 13:38:24.771138 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 13:38:24.774182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 13:38:24.774294 ==
4397 13:38:24.777602 [Gating] SW mode calibration
4398 13:38:24.784106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 13:38:24.787740 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 13:38:24.793945 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 13:38:24.797091 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 13:38:24.800538 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 13:38:24.806965 0 9 12 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
4404 13:38:24.810168 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 13:38:24.813859 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 13:38:24.820124 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 13:38:24.823655 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 13:38:24.826759 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 13:38:24.833728 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 13:38:24.836940 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 13:38:24.839966 0 10 12 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
4412 13:38:24.846339 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 13:38:24.850169 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 13:38:24.856587 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 13:38:24.859711 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 13:38:24.863125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 13:38:24.869503 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 13:38:24.872612 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 13:38:24.875888 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4420 13:38:24.882801 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 13:38:24.885841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:38:24.889348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:38:24.895755 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:38:24.899278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:38:24.902327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:38:24.908815 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:38:24.912019 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:38:24.915623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:38:24.922132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:38:24.925625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 13:38:24.928589 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:38:24.935458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:38:24.938745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:38:24.942180 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:38:24.948393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 13:38:24.948496 Total UI for P1: 0, mck2ui 16
4437 13:38:24.954870 best dqsien dly found for B0: ( 0, 13, 10)
4438 13:38:24.954987 Total UI for P1: 0, mck2ui 16
4439 13:38:24.958760 best dqsien dly found for B1: ( 0, 13, 10)
4440 13:38:24.965008 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4441 13:38:24.968326 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4442 13:38:24.968459
4443 13:38:24.971437 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4444 13:38:24.974935 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4445 13:38:24.978071 [Gating] SW calibration Done
4446 13:38:24.978233 ==
4447 13:38:24.981229 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 13:38:24.984491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 13:38:24.984615 ==
4450 13:38:24.988451 RX Vref Scan: 0
4451 13:38:24.988608
4452 13:38:24.988683 RX Vref 0 -> 0, step: 1
4453 13:38:24.988746
4454 13:38:24.991632 RX Delay -230 -> 252, step: 16
4455 13:38:24.997716 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4456 13:38:25.001238 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4457 13:38:25.004403 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4458 13:38:25.007558 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4459 13:38:25.014379 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4460 13:38:25.017554 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4461 13:38:25.020729 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4462 13:38:25.024642 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4463 13:38:25.027878 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4464 13:38:25.033775 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4465 13:38:25.037431 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4466 13:38:25.040514 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4467 13:38:25.044024 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4468 13:38:25.050453 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4469 13:38:25.053813 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4470 13:38:25.057191 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4471 13:38:25.057351 ==
4472 13:38:25.060599 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 13:38:25.066766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 13:38:25.066924 ==
4475 13:38:25.067036 DQS Delay:
4476 13:38:25.070221 DQS0 = 0, DQS1 = 0
4477 13:38:25.070313 DQM Delay:
4478 13:38:25.070379 DQM0 = 43, DQM1 = 39
4479 13:38:25.073437 DQ Delay:
4480 13:38:25.076718 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4481 13:38:25.080106 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4482 13:38:25.083337 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4483 13:38:25.086607 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4484 13:38:25.086722
4485 13:38:25.086828
4486 13:38:25.086921 ==
4487 13:38:25.089934 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 13:38:25.093038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 13:38:25.093156 ==
4490 13:38:25.093251
4491 13:38:25.093337
4492 13:38:25.096299 TX Vref Scan disable
4493 13:38:25.099669 == TX Byte 0 ==
4494 13:38:25.102886 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4495 13:38:25.106118 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4496 13:38:25.109395 == TX Byte 1 ==
4497 13:38:25.112879 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4498 13:38:25.116392 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4499 13:38:25.116508 ==
4500 13:38:25.119263 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 13:38:25.122917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 13:38:25.126007 ==
4503 13:38:25.126108
4504 13:38:25.126204
4505 13:38:25.126293 TX Vref Scan disable
4506 13:38:25.129742 == TX Byte 0 ==
4507 13:38:25.133469 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 13:38:25.140035 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 13:38:25.140194 == TX Byte 1 ==
4510 13:38:25.143398 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4511 13:38:25.149760 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4512 13:38:25.149927
4513 13:38:25.150028 [DATLAT]
4514 13:38:25.150121 Freq=600, CH1 RK0
4515 13:38:25.150212
4516 13:38:25.153328 DATLAT Default: 0x9
4517 13:38:25.156614 0, 0xFFFF, sum = 0
4518 13:38:25.156721 1, 0xFFFF, sum = 0
4519 13:38:25.159662 2, 0xFFFF, sum = 0
4520 13:38:25.159758 3, 0xFFFF, sum = 0
4521 13:38:25.163256 4, 0xFFFF, sum = 0
4522 13:38:25.163357 5, 0xFFFF, sum = 0
4523 13:38:25.166272 6, 0xFFFF, sum = 0
4524 13:38:25.166371 7, 0xFFFF, sum = 0
4525 13:38:25.169985 8, 0x0, sum = 1
4526 13:38:25.170081 9, 0x0, sum = 2
4527 13:38:25.172841 10, 0x0, sum = 3
4528 13:38:25.172919 11, 0x0, sum = 4
4529 13:38:25.172984 best_step = 9
4530 13:38:25.173045
4531 13:38:25.176109 ==
4532 13:38:25.179649 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 13:38:25.182673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 13:38:25.182769 ==
4535 13:38:25.182837 RX Vref Scan: 1
4536 13:38:25.182899
4537 13:38:25.186266 RX Vref 0 -> 0, step: 1
4538 13:38:25.186353
4539 13:38:25.189283 RX Delay -179 -> 252, step: 8
4540 13:38:25.189368
4541 13:38:25.192525 Set Vref, RX VrefLevel [Byte0]: 53
4542 13:38:25.195779 [Byte1]: 51
4543 13:38:25.195864
4544 13:38:25.199238 Final RX Vref Byte 0 = 53 to rank0
4545 13:38:25.202420 Final RX Vref Byte 1 = 51 to rank0
4546 13:38:25.205635 Final RX Vref Byte 0 = 53 to rank1
4547 13:38:25.208950 Final RX Vref Byte 1 = 51 to rank1==
4548 13:38:25.212133 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 13:38:25.215366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 13:38:25.219106 ==
4551 13:38:25.219191 DQS Delay:
4552 13:38:25.219258 DQS0 = 0, DQS1 = 0
4553 13:38:25.222276 DQM Delay:
4554 13:38:25.222388 DQM0 = 41, DQM1 = 34
4555 13:38:25.225848 DQ Delay:
4556 13:38:25.228778 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4557 13:38:25.228862 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4558 13:38:25.232499 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4559 13:38:25.238679 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4560 13:38:25.238766
4561 13:38:25.238832
4562 13:38:25.245185 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4563 13:38:25.248586 CH1 RK0: MR19=808, MR18=2F49
4564 13:38:25.255164 CH1_RK0: MR19=0x808, MR18=0x2F49, DQSOSC=396, MR23=63, INC=167, DEC=111
4565 13:38:25.255291
4566 13:38:25.258627 ----->DramcWriteLeveling(PI) begin...
4567 13:38:25.258751 ==
4568 13:38:25.261822 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 13:38:25.265231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 13:38:25.265332 ==
4571 13:38:25.268370 Write leveling (Byte 0): 29 => 29
4572 13:38:25.271712 Write leveling (Byte 1): 31 => 31
4573 13:38:25.274774 DramcWriteLeveling(PI) end<-----
4574 13:38:25.274860
4575 13:38:25.274928 ==
4576 13:38:25.278110 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 13:38:25.281664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 13:38:25.281817 ==
4579 13:38:25.284907 [Gating] SW mode calibration
4580 13:38:25.291497 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4581 13:38:25.298145 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4582 13:38:25.301637 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 13:38:25.308308 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 13:38:25.311184 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4585 13:38:25.314519 0 9 12 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (1 1)
4586 13:38:25.321452 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4587 13:38:25.324780 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 13:38:25.327389 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 13:38:25.334644 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 13:38:25.337798 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 13:38:25.340841 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 13:38:25.347532 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4593 13:38:25.350979 0 10 12 | B1->B0 | 3434 4242 | 1 1 | (0 0) (0 0)
4594 13:38:25.354422 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4595 13:38:25.360996 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 13:38:25.364171 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 13:38:25.367502 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 13:38:25.373771 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 13:38:25.377599 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 13:38:25.380865 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4601 13:38:25.387074 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4602 13:38:25.390336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 13:38:25.393962 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 13:38:25.400305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 13:38:25.403686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 13:38:25.406844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 13:38:25.413877 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 13:38:25.416989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 13:38:25.420246 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 13:38:25.426648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 13:38:25.429975 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 13:38:25.433397 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 13:38:25.439934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 13:38:25.443185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 13:38:25.446604 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:38:25.453057 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:38:25.456599 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4618 13:38:25.459721 Total UI for P1: 0, mck2ui 16
4619 13:38:25.463171 best dqsien dly found for B0: ( 0, 13, 10)
4620 13:38:25.466231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 13:38:25.469621 Total UI for P1: 0, mck2ui 16
4622 13:38:25.472689 best dqsien dly found for B1: ( 0, 13, 12)
4623 13:38:25.476071 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4624 13:38:25.479254 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4625 13:38:25.479353
4626 13:38:25.486077 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4627 13:38:25.489696 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4628 13:38:25.489833 [Gating] SW calibration Done
4629 13:38:25.492666 ==
4630 13:38:25.496052 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 13:38:25.499070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 13:38:25.499164 ==
4633 13:38:25.499237 RX Vref Scan: 0
4634 13:38:25.499302
4635 13:38:25.502212 RX Vref 0 -> 0, step: 1
4636 13:38:25.502304
4637 13:38:25.505923 RX Delay -230 -> 252, step: 16
4638 13:38:25.509112 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4639 13:38:25.515951 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4640 13:38:25.519216 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4641 13:38:25.522515 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4642 13:38:25.525600 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4643 13:38:25.528645 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4644 13:38:25.535786 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4645 13:38:25.539080 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4646 13:38:25.542268 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4647 13:38:25.545657 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4648 13:38:25.552041 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4649 13:38:25.555362 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4650 13:38:25.558504 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4651 13:38:25.561600 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4652 13:38:25.568365 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4653 13:38:25.571955 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4654 13:38:25.572067 ==
4655 13:38:25.575395 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 13:38:25.578865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 13:38:25.578955 ==
4658 13:38:25.581831 DQS Delay:
4659 13:38:25.581945 DQS0 = 0, DQS1 = 0
4660 13:38:25.582036 DQM Delay:
4661 13:38:25.584980 DQM0 = 42, DQM1 = 39
4662 13:38:25.585079 DQ Delay:
4663 13:38:25.588625 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4664 13:38:25.591851 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4665 13:38:25.595058 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4666 13:38:25.598254 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4667 13:38:25.598367
4668 13:38:25.598473
4669 13:38:25.598568 ==
4670 13:38:25.601461 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 13:38:25.608199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 13:38:25.608327 ==
4673 13:38:25.608421
4674 13:38:25.608517
4675 13:38:25.608611 TX Vref Scan disable
4676 13:38:25.611984 == TX Byte 0 ==
4677 13:38:25.615154 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4678 13:38:25.621355 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4679 13:38:25.621490 == TX Byte 1 ==
4680 13:38:25.625355 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4681 13:38:25.631643 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4682 13:38:25.631735 ==
4683 13:38:25.634743 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 13:38:25.638177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 13:38:25.638267 ==
4686 13:38:25.638335
4687 13:38:25.638396
4688 13:38:25.641366 TX Vref Scan disable
4689 13:38:25.644707 == TX Byte 0 ==
4690 13:38:25.648253 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 13:38:25.651255 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 13:38:25.654564 == TX Byte 1 ==
4693 13:38:25.657842 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 13:38:25.661079 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 13:38:25.661185
4696 13:38:25.661289 [DATLAT]
4697 13:38:25.664852 Freq=600, CH1 RK1
4698 13:38:25.664936
4699 13:38:25.668049 DATLAT Default: 0x9
4700 13:38:25.668141 0, 0xFFFF, sum = 0
4701 13:38:25.671365 1, 0xFFFF, sum = 0
4702 13:38:25.671449 2, 0xFFFF, sum = 0
4703 13:38:25.674707 3, 0xFFFF, sum = 0
4704 13:38:25.674796 4, 0xFFFF, sum = 0
4705 13:38:25.677865 5, 0xFFFF, sum = 0
4706 13:38:25.677955 6, 0xFFFF, sum = 0
4707 13:38:25.680886 7, 0xFFFF, sum = 0
4708 13:38:25.680978 8, 0x0, sum = 1
4709 13:38:25.684183 9, 0x0, sum = 2
4710 13:38:25.684274 10, 0x0, sum = 3
4711 13:38:25.687580 11, 0x0, sum = 4
4712 13:38:25.687663 best_step = 9
4713 13:38:25.687728
4714 13:38:25.687789 ==
4715 13:38:25.690878 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 13:38:25.694419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 13:38:25.694535 ==
4718 13:38:25.697371 RX Vref Scan: 0
4719 13:38:25.697494
4720 13:38:25.700910 RX Vref 0 -> 0, step: 1
4721 13:38:25.701025
4722 13:38:25.701130 RX Delay -179 -> 252, step: 8
4723 13:38:25.708500 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4724 13:38:25.711791 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4725 13:38:25.715613 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4726 13:38:25.718796 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4727 13:38:25.725395 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4728 13:38:25.728670 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4729 13:38:25.731911 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4730 13:38:25.735186 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4731 13:38:25.741562 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4732 13:38:25.744764 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4733 13:38:25.748026 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4734 13:38:25.751925 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4735 13:38:25.758381 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4736 13:38:25.761715 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4737 13:38:25.764883 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4738 13:38:25.768064 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4739 13:38:25.768146 ==
4740 13:38:25.771295 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 13:38:25.777866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 13:38:25.777956 ==
4743 13:38:25.778032 DQS Delay:
4744 13:38:25.781062 DQS0 = 0, DQS1 = 0
4745 13:38:25.781167 DQM Delay:
4746 13:38:25.781265 DQM0 = 37, DQM1 = 34
4747 13:38:25.784376 DQ Delay:
4748 13:38:25.787542 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4749 13:38:25.790845 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4750 13:38:25.794054 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =24
4751 13:38:25.797722 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4752 13:38:25.797826
4753 13:38:25.797919
4754 13:38:25.803942 [DQSOSCAuto] RK1, (LSB)MR18= 0x365a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4755 13:38:25.807447 CH1 RK1: MR19=808, MR18=365A
4756 13:38:25.814066 CH1_RK1: MR19=0x808, MR18=0x365A, DQSOSC=392, MR23=63, INC=170, DEC=113
4757 13:38:25.817255 [RxdqsGatingPostProcess] freq 600
4758 13:38:25.823646 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4759 13:38:25.823749 Pre-setting of DQS Precalculation
4760 13:38:25.830526 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4761 13:38:25.837075 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4762 13:38:25.844067 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4763 13:38:25.844153
4764 13:38:25.844219
4765 13:38:25.847080 [Calibration Summary] 1200 Mbps
4766 13:38:25.850448 CH 0, Rank 0
4767 13:38:25.850559 SW Impedance : PASS
4768 13:38:25.853829 DUTY Scan : NO K
4769 13:38:25.856885 ZQ Calibration : PASS
4770 13:38:25.856967 Jitter Meter : NO K
4771 13:38:25.859783 CBT Training : PASS
4772 13:38:25.863603 Write leveling : PASS
4773 13:38:25.863688 RX DQS gating : PASS
4774 13:38:25.866854 RX DQ/DQS(RDDQC) : PASS
4775 13:38:25.870151 TX DQ/DQS : PASS
4776 13:38:25.870241 RX DATLAT : PASS
4777 13:38:25.873140 RX DQ/DQS(Engine): PASS
4778 13:38:25.876466 TX OE : NO K
4779 13:38:25.876569 All Pass.
4780 13:38:25.876659
4781 13:38:25.876732 CH 0, Rank 1
4782 13:38:25.879614 SW Impedance : PASS
4783 13:38:25.882853 DUTY Scan : NO K
4784 13:38:25.882942 ZQ Calibration : PASS
4785 13:38:25.886097 Jitter Meter : NO K
4786 13:38:25.886197 CBT Training : PASS
4787 13:38:25.889859 Write leveling : PASS
4788 13:38:25.893187 RX DQS gating : PASS
4789 13:38:25.893290 RX DQ/DQS(RDDQC) : PASS
4790 13:38:25.896487 TX DQ/DQS : PASS
4791 13:38:25.899583 RX DATLAT : PASS
4792 13:38:25.899681 RX DQ/DQS(Engine): PASS
4793 13:38:25.902804 TX OE : NO K
4794 13:38:25.902878 All Pass.
4795 13:38:25.902940
4796 13:38:25.906483 CH 1, Rank 0
4797 13:38:25.906555 SW Impedance : PASS
4798 13:38:25.909793 DUTY Scan : NO K
4799 13:38:25.912508 ZQ Calibration : PASS
4800 13:38:25.912591 Jitter Meter : NO K
4801 13:38:25.916360 CBT Training : PASS
4802 13:38:25.919577 Write leveling : PASS
4803 13:38:25.919659 RX DQS gating : PASS
4804 13:38:25.922631 RX DQ/DQS(RDDQC) : PASS
4805 13:38:25.926232 TX DQ/DQS : PASS
4806 13:38:25.926321 RX DATLAT : PASS
4807 13:38:25.929220 RX DQ/DQS(Engine): PASS
4808 13:38:25.932785 TX OE : NO K
4809 13:38:25.932865 All Pass.
4810 13:38:25.932929
4811 13:38:25.932989 CH 1, Rank 1
4812 13:38:25.935791 SW Impedance : PASS
4813 13:38:25.939111 DUTY Scan : NO K
4814 13:38:25.939201 ZQ Calibration : PASS
4815 13:38:25.942693 Jitter Meter : NO K
4816 13:38:25.945462 CBT Training : PASS
4817 13:38:25.945538 Write leveling : PASS
4818 13:38:25.948846 RX DQS gating : PASS
4819 13:38:25.952741 RX DQ/DQS(RDDQC) : PASS
4820 13:38:25.952828 TX DQ/DQS : PASS
4821 13:38:25.955832 RX DATLAT : PASS
4822 13:38:25.958708 RX DQ/DQS(Engine): PASS
4823 13:38:25.958782 TX OE : NO K
4824 13:38:25.958845 All Pass.
4825 13:38:25.958965
4826 13:38:25.961909 DramC Write-DBI off
4827 13:38:25.965145 PER_BANK_REFRESH: Hybrid Mode
4828 13:38:25.965233 TX_TRACKING: ON
4829 13:38:25.975581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4830 13:38:25.978679 [FAST_K] Save calibration result to emmc
4831 13:38:25.981832 dramc_set_vcore_voltage set vcore to 662500
4832 13:38:25.985091 Read voltage for 933, 3
4833 13:38:25.985196 Vio18 = 0
4834 13:38:25.988489 Vcore = 662500
4835 13:38:25.988568 Vdram = 0
4836 13:38:25.988633 Vddq = 0
4837 13:38:25.988700 Vmddr = 0
4838 13:38:25.994938 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4839 13:38:26.001380 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4840 13:38:26.001484 MEM_TYPE=3, freq_sel=17
4841 13:38:26.005296 sv_algorithm_assistance_LP4_1600
4842 13:38:26.008325 ============ PULL DRAM RESETB DOWN ============
4843 13:38:26.015252 ========== PULL DRAM RESETB DOWN end =========
4844 13:38:26.017811 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 13:38:26.021795 ===================================
4846 13:38:26.025078 LPDDR4 DRAM CONFIGURATION
4847 13:38:26.028185 ===================================
4848 13:38:26.028297 EX_ROW_EN[0] = 0x0
4849 13:38:26.031478 EX_ROW_EN[1] = 0x0
4850 13:38:26.034631 LP4Y_EN = 0x0
4851 13:38:26.034709 WORK_FSP = 0x0
4852 13:38:26.037838 WL = 0x3
4853 13:38:26.037937 RL = 0x3
4854 13:38:26.040869 BL = 0x2
4855 13:38:26.040971 RPST = 0x0
4856 13:38:26.044630 RD_PRE = 0x0
4857 13:38:26.044712 WR_PRE = 0x1
4858 13:38:26.047850 WR_PST = 0x0
4859 13:38:26.047929 DBI_WR = 0x0
4860 13:38:26.051005 DBI_RD = 0x0
4861 13:38:26.051110 OTF = 0x1
4862 13:38:26.054269 ===================================
4863 13:38:26.058172 ===================================
4864 13:38:26.061191 ANA top config
4865 13:38:26.064419 ===================================
4866 13:38:26.064520 DLL_ASYNC_EN = 0
4867 13:38:26.067577 ALL_SLAVE_EN = 1
4868 13:38:26.071078 NEW_RANK_MODE = 1
4869 13:38:26.074120 DLL_IDLE_MODE = 1
4870 13:38:26.077700 LP45_APHY_COMB_EN = 1
4871 13:38:26.077811 TX_ODT_DIS = 1
4872 13:38:26.080506 NEW_8X_MODE = 1
4873 13:38:26.083877 ===================================
4874 13:38:26.087724 ===================================
4875 13:38:26.090324 data_rate = 1866
4876 13:38:26.094295 CKR = 1
4877 13:38:26.097428 DQ_P2S_RATIO = 8
4878 13:38:26.100658 ===================================
4879 13:38:26.103927 CA_P2S_RATIO = 8
4880 13:38:26.104034 DQ_CA_OPEN = 0
4881 13:38:26.107225 DQ_SEMI_OPEN = 0
4882 13:38:26.110467 CA_SEMI_OPEN = 0
4883 13:38:26.113473 CA_FULL_RATE = 0
4884 13:38:26.117021 DQ_CKDIV4_EN = 1
4885 13:38:26.120438 CA_CKDIV4_EN = 1
4886 13:38:26.123724 CA_PREDIV_EN = 0
4887 13:38:26.123798 PH8_DLY = 0
4888 13:38:26.126365 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4889 13:38:26.129591 DQ_AAMCK_DIV = 4
4890 13:38:26.133292 CA_AAMCK_DIV = 4
4891 13:38:26.136454 CA_ADMCK_DIV = 4
4892 13:38:26.139810 DQ_TRACK_CA_EN = 0
4893 13:38:26.139890 CA_PICK = 933
4894 13:38:26.143136 CA_MCKIO = 933
4895 13:38:26.146362 MCKIO_SEMI = 0
4896 13:38:26.149441 PLL_FREQ = 3732
4897 13:38:26.152703 DQ_UI_PI_RATIO = 32
4898 13:38:26.156431 CA_UI_PI_RATIO = 0
4899 13:38:26.159734 ===================================
4900 13:38:26.162915 ===================================
4901 13:38:26.166412 memory_type:LPDDR4
4902 13:38:26.166492 GP_NUM : 10
4903 13:38:26.169347 SRAM_EN : 1
4904 13:38:26.169424 MD32_EN : 0
4905 13:38:26.172478 ===================================
4906 13:38:26.176105 [ANA_INIT] >>>>>>>>>>>>>>
4907 13:38:26.179343 <<<<<< [CONFIGURE PHASE]: ANA_TX
4908 13:38:26.182526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4909 13:38:26.185734 ===================================
4910 13:38:26.189487 data_rate = 1866,PCW = 0X8f00
4911 13:38:26.192340 ===================================
4912 13:38:26.195773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4913 13:38:26.202384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4914 13:38:26.205658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 13:38:26.212234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4916 13:38:26.215501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4917 13:38:26.218453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4918 13:38:26.218540 [ANA_INIT] flow start
4919 13:38:26.222280 [ANA_INIT] PLL >>>>>>>>
4920 13:38:26.225539 [ANA_INIT] PLL <<<<<<<<
4921 13:38:26.225619 [ANA_INIT] MIDPI >>>>>>>>
4922 13:38:26.228787 [ANA_INIT] MIDPI <<<<<<<<
4923 13:38:26.231879 [ANA_INIT] DLL >>>>>>>>
4924 13:38:26.231964 [ANA_INIT] flow end
4925 13:38:26.238759 ============ LP4 DIFF to SE enter ============
4926 13:38:26.241994 ============ LP4 DIFF to SE exit ============
4927 13:38:26.245092 [ANA_INIT] <<<<<<<<<<<<<
4928 13:38:26.248427 [Flow] Enable top DCM control >>>>>
4929 13:38:26.251515 [Flow] Enable top DCM control <<<<<
4930 13:38:26.255363 Enable DLL master slave shuffle
4931 13:38:26.258485 ==============================================================
4932 13:38:26.261605 Gating Mode config
4933 13:38:26.264911 ==============================================================
4934 13:38:26.268784 Config description:
4935 13:38:26.278273 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4936 13:38:26.285132 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4937 13:38:26.288305 SELPH_MODE 0: By rank 1: By Phase
4938 13:38:26.294808 ==============================================================
4939 13:38:26.298136 GAT_TRACK_EN = 1
4940 13:38:26.301344 RX_GATING_MODE = 2
4941 13:38:26.304334 RX_GATING_TRACK_MODE = 2
4942 13:38:26.307924 SELPH_MODE = 1
4943 13:38:26.311151 PICG_EARLY_EN = 1
4944 13:38:26.314154 VALID_LAT_VALUE = 1
4945 13:38:26.318225 ==============================================================
4946 13:38:26.320762 Enter into Gating configuration >>>>
4947 13:38:26.324490 Exit from Gating configuration <<<<
4948 13:38:26.327499 Enter into DVFS_PRE_config >>>>>
4949 13:38:26.340897 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4950 13:38:26.341026 Exit from DVFS_PRE_config <<<<<
4951 13:38:26.344003 Enter into PICG configuration >>>>
4952 13:38:26.347208 Exit from PICG configuration <<<<
4953 13:38:26.350346 [RX_INPUT] configuration >>>>>
4954 13:38:26.354320 [RX_INPUT] configuration <<<<<
4955 13:38:26.360713 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4956 13:38:26.363635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4957 13:38:26.370295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 13:38:26.376896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 13:38:26.383783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 13:38:26.390146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 13:38:26.393624 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4962 13:38:26.396862 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4963 13:38:26.403283 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4964 13:38:26.406570 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4965 13:38:26.409843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4966 13:38:26.412943 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 13:38:26.416756 ===================================
4968 13:38:26.420018 LPDDR4 DRAM CONFIGURATION
4969 13:38:26.423130 ===================================
4970 13:38:26.426593 EX_ROW_EN[0] = 0x0
4971 13:38:26.426729 EX_ROW_EN[1] = 0x0
4972 13:38:26.429684 LP4Y_EN = 0x0
4973 13:38:26.429792 WORK_FSP = 0x0
4974 13:38:26.433004 WL = 0x3
4975 13:38:26.433121 RL = 0x3
4976 13:38:26.436392 BL = 0x2
4977 13:38:26.436496 RPST = 0x0
4978 13:38:26.439772 RD_PRE = 0x0
4979 13:38:26.439889 WR_PRE = 0x1
4980 13:38:26.443017 WR_PST = 0x0
4981 13:38:26.446175 DBI_WR = 0x0
4982 13:38:26.446279 DBI_RD = 0x0
4983 13:38:26.449300 OTF = 0x1
4984 13:38:26.452940 ===================================
4985 13:38:26.456248 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4986 13:38:26.459529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4987 13:38:26.462780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 13:38:26.465973 ===================================
4989 13:38:26.469226 LPDDR4 DRAM CONFIGURATION
4990 13:38:26.472415 ===================================
4991 13:38:26.475453 EX_ROW_EN[0] = 0x10
4992 13:38:26.475576 EX_ROW_EN[1] = 0x0
4993 13:38:26.479237 LP4Y_EN = 0x0
4994 13:38:26.479338 WORK_FSP = 0x0
4995 13:38:26.482440 WL = 0x3
4996 13:38:26.482552 RL = 0x3
4997 13:38:26.485770 BL = 0x2
4998 13:38:26.485864 RPST = 0x0
4999 13:38:26.489098 RD_PRE = 0x0
5000 13:38:26.492356 WR_PRE = 0x1
5001 13:38:26.492445 WR_PST = 0x0
5002 13:38:26.495612 DBI_WR = 0x0
5003 13:38:26.495738 DBI_RD = 0x0
5004 13:38:26.498626 OTF = 0x1
5005 13:38:26.502451 ===================================
5006 13:38:26.505296 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5007 13:38:26.510916 nWR fixed to 30
5008 13:38:26.514267 [ModeRegInit_LP4] CH0 RK0
5009 13:38:26.514384 [ModeRegInit_LP4] CH0 RK1
5010 13:38:26.517461 [ModeRegInit_LP4] CH1 RK0
5011 13:38:26.520622 [ModeRegInit_LP4] CH1 RK1
5012 13:38:26.520742 match AC timing 9
5013 13:38:26.527019 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5014 13:38:26.530205 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5015 13:38:26.533951 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5016 13:38:26.540797 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5017 13:38:26.543598 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5018 13:38:26.543686 ==
5019 13:38:26.547111 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 13:38:26.550483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5021 13:38:26.550569 ==
5022 13:38:26.556697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5023 13:38:26.563461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5024 13:38:26.567057 [CA 0] Center 37 (7~68) winsize 62
5025 13:38:26.570394 [CA 1] Center 37 (7~68) winsize 62
5026 13:38:26.573658 [CA 2] Center 35 (5~65) winsize 61
5027 13:38:26.576858 [CA 3] Center 34 (4~65) winsize 62
5028 13:38:26.580128 [CA 4] Center 32 (2~63) winsize 62
5029 13:38:26.583217 [CA 5] Center 32 (2~63) winsize 62
5030 13:38:26.583304
5031 13:38:26.586921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5032 13:38:26.587009
5033 13:38:26.590168 [CATrainingPosCal] consider 1 rank data
5034 13:38:26.593560 u2DelayCellTimex100 = 270/100 ps
5035 13:38:26.596639 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5036 13:38:26.600013 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5037 13:38:26.603110 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5038 13:38:26.609603 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 13:38:26.612994 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5040 13:38:26.616686 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5041 13:38:26.616775
5042 13:38:26.620010 CA PerBit enable=1, Macro0, CA PI delay=32
5043 13:38:26.620092
5044 13:38:26.623070 [CBTSetCACLKResult] CA Dly = 32
5045 13:38:26.623160 CS Dly: 6 (0~37)
5046 13:38:26.623228 ==
5047 13:38:26.626314 Dram Type= 6, Freq= 0, CH_0, rank 1
5048 13:38:26.632810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 13:38:26.632903 ==
5050 13:38:26.636635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 13:38:26.643233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5052 13:38:26.646534 [CA 0] Center 37 (7~68) winsize 62
5053 13:38:26.649730 [CA 1] Center 37 (7~68) winsize 62
5054 13:38:26.653040 [CA 2] Center 34 (4~65) winsize 62
5055 13:38:26.656092 [CA 3] Center 34 (4~65) winsize 62
5056 13:38:26.659365 [CA 4] Center 33 (3~64) winsize 62
5057 13:38:26.662519 [CA 5] Center 32 (2~63) winsize 62
5058 13:38:26.662605
5059 13:38:26.665869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5060 13:38:26.665955
5061 13:38:26.669201 [CATrainingPosCal] consider 2 rank data
5062 13:38:26.672184 u2DelayCellTimex100 = 270/100 ps
5063 13:38:26.675488 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5064 13:38:26.682595 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 13:38:26.685813 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5066 13:38:26.688813 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 13:38:26.692172 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5068 13:38:26.695629 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5069 13:38:26.695741
5070 13:38:26.698796 CA PerBit enable=1, Macro0, CA PI delay=32
5071 13:38:26.698880
5072 13:38:26.701991 [CBTSetCACLKResult] CA Dly = 32
5073 13:38:26.705755 CS Dly: 7 (0~39)
5074 13:38:26.705833
5075 13:38:26.708879 ----->DramcWriteLeveling(PI) begin...
5076 13:38:26.708965 ==
5077 13:38:26.712044 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 13:38:26.715309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 13:38:26.715393 ==
5080 13:38:26.718707 Write leveling (Byte 0): 31 => 31
5081 13:38:26.721996 Write leveling (Byte 1): 28 => 28
5082 13:38:26.724929 DramcWriteLeveling(PI) end<-----
5083 13:38:26.725037
5084 13:38:26.725131 ==
5085 13:38:26.728440 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 13:38:26.731704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 13:38:26.731782 ==
5088 13:38:26.734843 [Gating] SW mode calibration
5089 13:38:26.741383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 13:38:26.748431 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5091 13:38:26.751183 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5092 13:38:26.758201 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5093 13:38:26.761087 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 13:38:26.764328 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 13:38:26.771453 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 13:38:26.774750 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 13:38:26.778024 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5098 13:38:26.784064 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5099 13:38:26.787701 0 15 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (1 0)
5100 13:38:26.790669 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5101 13:38:26.797227 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 13:38:26.800752 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 13:38:26.804108 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 13:38:26.810367 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 13:38:26.813592 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5106 13:38:26.817610 0 15 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
5107 13:38:26.823965 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5108 13:38:26.827190 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 13:38:26.830241 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 13:38:26.837153 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 13:38:26.840899 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 13:38:26.843501 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 13:38:26.850323 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 13:38:26.853562 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5115 13:38:26.856777 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5116 13:38:26.863103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 13:38:26.866808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 13:38:26.870086 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 13:38:26.876440 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:38:26.879650 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:38:26.882907 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:38:26.889368 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:38:26.893167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:38:26.896263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 13:38:26.902747 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 13:38:26.905988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 13:38:26.909118 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:38:26.916105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:38:26.919491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5130 13:38:26.922525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 13:38:26.929317 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 13:38:26.929435 Total UI for P1: 0, mck2ui 16
5133 13:38:26.935739 best dqsien dly found for B0: ( 1, 2, 26)
5134 13:38:26.938832 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 13:38:26.942059 Total UI for P1: 0, mck2ui 16
5136 13:38:26.945391 best dqsien dly found for B1: ( 1, 3, 0)
5137 13:38:26.948933 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5138 13:38:26.951817 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5139 13:38:26.951898
5140 13:38:26.955266 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5141 13:38:26.958561 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5142 13:38:26.962062 [Gating] SW calibration Done
5143 13:38:26.962147 ==
5144 13:38:26.965340 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 13:38:26.968637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 13:38:26.976938 ==
5147 13:38:26.977082 RX Vref Scan: 0
5148 13:38:26.977191
5149 13:38:26.977294 RX Vref 0 -> 0, step: 1
5150 13:38:26.977384
5151 13:38:26.978432 RX Delay -80 -> 252, step: 8
5152 13:38:26.981706 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5153 13:38:26.984931 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5154 13:38:26.988123 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5155 13:38:26.991386 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5156 13:38:26.995289 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5157 13:38:27.001711 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5158 13:38:27.004868 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5159 13:38:27.008108 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5160 13:38:27.011341 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5161 13:38:27.014661 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5162 13:38:27.021078 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5163 13:38:27.025001 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5164 13:38:27.028195 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5165 13:38:27.031180 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5166 13:38:27.034553 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5167 13:38:27.037988 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5168 13:38:27.041385 ==
5169 13:38:27.044348 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 13:38:27.047722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 13:38:27.047804 ==
5172 13:38:27.047871 DQS Delay:
5173 13:38:27.050904 DQS0 = 0, DQS1 = 0
5174 13:38:27.050986 DQM Delay:
5175 13:38:27.054249 DQM0 = 100, DQM1 = 89
5176 13:38:27.054330 DQ Delay:
5177 13:38:27.057918 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5178 13:38:27.061010 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =103
5179 13:38:27.064047 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5180 13:38:27.067656 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5181 13:38:27.067745
5182 13:38:27.067820
5183 13:38:27.067882 ==
5184 13:38:27.071020 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 13:38:27.074406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 13:38:27.074488 ==
5187 13:38:27.077481
5188 13:38:27.077563
5189 13:38:27.077633 TX Vref Scan disable
5190 13:38:27.080587 == TX Byte 0 ==
5191 13:38:27.083736 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5192 13:38:27.087588 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5193 13:38:27.090684 == TX Byte 1 ==
5194 13:38:27.094105 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5195 13:38:27.097449 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5196 13:38:27.100691 ==
5197 13:38:27.103989 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 13:38:27.107234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 13:38:27.107352 ==
5200 13:38:27.107463
5201 13:38:27.107554
5202 13:38:27.110199 TX Vref Scan disable
5203 13:38:27.110327 == TX Byte 0 ==
5204 13:38:27.116701 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5205 13:38:27.120048 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5206 13:38:27.120161 == TX Byte 1 ==
5207 13:38:27.127041 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 13:38:27.130272 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 13:38:27.130394
5210 13:38:27.130494 [DATLAT]
5211 13:38:27.133561 Freq=933, CH0 RK0
5212 13:38:27.133667
5213 13:38:27.133762 DATLAT Default: 0xd
5214 13:38:27.137176 0, 0xFFFF, sum = 0
5215 13:38:27.137295 1, 0xFFFF, sum = 0
5216 13:38:27.139976 2, 0xFFFF, sum = 0
5217 13:38:27.140090 3, 0xFFFF, sum = 0
5218 13:38:27.143264 4, 0xFFFF, sum = 0
5219 13:38:27.146375 5, 0xFFFF, sum = 0
5220 13:38:27.146497 6, 0xFFFF, sum = 0
5221 13:38:27.149548 7, 0xFFFF, sum = 0
5222 13:38:27.149679 8, 0xFFFF, sum = 0
5223 13:38:27.153366 9, 0xFFFF, sum = 0
5224 13:38:27.153478 10, 0x0, sum = 1
5225 13:38:27.156304 11, 0x0, sum = 2
5226 13:38:27.156433 12, 0x0, sum = 3
5227 13:38:27.156532 13, 0x0, sum = 4
5228 13:38:27.159838 best_step = 11
5229 13:38:27.159950
5230 13:38:27.160059 ==
5231 13:38:27.163101 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 13:38:27.166006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 13:38:27.166128 ==
5234 13:38:27.169610 RX Vref Scan: 1
5235 13:38:27.169732
5236 13:38:27.172796 RX Vref 0 -> 0, step: 1
5237 13:38:27.172906
5238 13:38:27.173011 RX Delay -61 -> 252, step: 4
5239 13:38:27.173099
5240 13:38:27.176139 Set Vref, RX VrefLevel [Byte0]: 50
5241 13:38:27.179087 [Byte1]: 58
5242 13:38:27.184467
5243 13:38:27.184569 Final RX Vref Byte 0 = 50 to rank0
5244 13:38:27.187479 Final RX Vref Byte 1 = 58 to rank0
5245 13:38:27.190890 Final RX Vref Byte 0 = 50 to rank1
5246 13:38:27.193921 Final RX Vref Byte 1 = 58 to rank1==
5247 13:38:27.197129 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 13:38:27.204156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 13:38:27.204278 ==
5250 13:38:27.204372 DQS Delay:
5251 13:38:27.207342 DQS0 = 0, DQS1 = 0
5252 13:38:27.207453 DQM Delay:
5253 13:38:27.207540 DQM0 = 99, DQM1 = 88
5254 13:38:27.210357 DQ Delay:
5255 13:38:27.214142 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =94
5256 13:38:27.216835 DQ4 =100, DQ5 =92, DQ6 =108, DQ7 =106
5257 13:38:27.220533 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5258 13:38:27.223855 DQ12 =96, DQ13 =90, DQ14 =96, DQ15 =94
5259 13:38:27.223980
5260 13:38:27.224073
5261 13:38:27.230436 [DQSOSCAuto] RK0, (LSB)MR18= 0x211b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 411 ps
5262 13:38:27.233562 CH0 RK0: MR19=505, MR18=211B
5263 13:38:27.239905 CH0_RK0: MR19=0x505, MR18=0x211B, DQSOSC=411, MR23=63, INC=64, DEC=42
5264 13:38:27.240006
5265 13:38:27.243990 ----->DramcWriteLeveling(PI) begin...
5266 13:38:27.244084 ==
5267 13:38:27.246871 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 13:38:27.249914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 13:38:27.250027 ==
5270 13:38:27.253617 Write leveling (Byte 0): 30 => 30
5271 13:38:27.256883 Write leveling (Byte 1): 27 => 27
5272 13:38:27.260161 DramcWriteLeveling(PI) end<-----
5273 13:38:27.260249
5274 13:38:27.260316 ==
5275 13:38:27.263334 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 13:38:27.269679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 13:38:27.269779 ==
5278 13:38:27.269848 [Gating] SW mode calibration
5279 13:38:27.279249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5280 13:38:27.282662 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5281 13:38:27.289334 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5282 13:38:27.292943 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 13:38:27.296157 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 13:38:27.302440 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 13:38:27.305909 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 13:38:27.309334 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 13:38:27.316093 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5288 13:38:27.319543 0 14 28 | B1->B0 | 3030 2a2a | 1 0 | (1 1) (0 0)
5289 13:38:27.322552 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5290 13:38:27.329193 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5291 13:38:27.332366 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 13:38:27.335543 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 13:38:27.342189 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 13:38:27.345867 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 13:38:27.348818 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 13:38:27.355369 0 15 28 | B1->B0 | 2828 3e3e | 0 0 | (0 0) (0 0)
5297 13:38:27.358864 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5298 13:38:27.361665 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 13:38:27.368447 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 13:38:27.371589 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 13:38:27.374830 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 13:38:27.381367 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 13:38:27.384690 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 13:38:27.387869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5305 13:38:27.394593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5306 13:38:27.397772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 13:38:27.401351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 13:38:27.407587 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 13:38:27.410841 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 13:38:27.414297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 13:38:27.420612 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 13:38:27.424460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 13:38:27.427444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 13:38:27.434845 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 13:38:27.437463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 13:38:27.440658 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 13:38:27.447712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 13:38:27.450959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:38:27.454142 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:38:27.460613 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5321 13:38:27.460713 Total UI for P1: 0, mck2ui 16
5322 13:38:27.467418 best dqsien dly found for B0: ( 1, 2, 26)
5323 13:38:27.470464 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5324 13:38:27.473762 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 13:38:27.477082 Total UI for P1: 0, mck2ui 16
5326 13:38:27.480337 best dqsien dly found for B1: ( 1, 3, 2)
5327 13:38:27.483684 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5328 13:38:27.486750 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5329 13:38:27.486863
5330 13:38:27.493756 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5331 13:38:27.496919 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5332 13:38:27.497004 [Gating] SW calibration Done
5333 13:38:27.500152 ==
5334 13:38:27.503364 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 13:38:27.506502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 13:38:27.506586 ==
5337 13:38:27.506651 RX Vref Scan: 0
5338 13:38:27.506713
5339 13:38:27.509837 RX Vref 0 -> 0, step: 1
5340 13:38:27.509917
5341 13:38:27.513610 RX Delay -80 -> 252, step: 8
5342 13:38:27.516650 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5343 13:38:27.519531 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5344 13:38:27.523079 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5345 13:38:27.529489 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5346 13:38:27.532962 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5347 13:38:27.536375 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5348 13:38:27.539781 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5349 13:38:27.542909 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5350 13:38:27.546154 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5351 13:38:27.552553 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5352 13:38:27.555849 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5353 13:38:27.559630 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5354 13:38:27.562414 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5355 13:38:27.566357 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5356 13:38:27.572711 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5357 13:38:27.575713 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5358 13:38:27.575813 ==
5359 13:38:27.579106 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 13:38:27.582547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 13:38:27.582660 ==
5362 13:38:27.582756 DQS Delay:
5363 13:38:27.585852 DQS0 = 0, DQS1 = 0
5364 13:38:27.585960 DQM Delay:
5365 13:38:27.589081 DQM0 = 97, DQM1 = 90
5366 13:38:27.589184 DQ Delay:
5367 13:38:27.592173 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5368 13:38:27.595492 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5369 13:38:27.598674 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5370 13:38:27.601859 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5371 13:38:27.601946
5372 13:38:27.602019
5373 13:38:27.602083 ==
5374 13:38:27.605163 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 13:38:27.611972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 13:38:27.612107 ==
5377 13:38:27.612204
5378 13:38:27.612294
5379 13:38:27.612381 TX Vref Scan disable
5380 13:38:27.615547 == TX Byte 0 ==
5381 13:38:27.618716 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5382 13:38:27.625233 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5383 13:38:27.625341 == TX Byte 1 ==
5384 13:38:27.628361 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5385 13:38:27.634800 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5386 13:38:27.634924 ==
5387 13:38:27.638664 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 13:38:27.641676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 13:38:27.641764 ==
5390 13:38:27.641851
5391 13:38:27.641915
5392 13:38:27.645176 TX Vref Scan disable
5393 13:38:27.648275 == TX Byte 0 ==
5394 13:38:27.651593 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5395 13:38:27.654614 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5396 13:38:27.658450 == TX Byte 1 ==
5397 13:38:27.661772 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5398 13:38:27.664478 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5399 13:38:27.664580
5400 13:38:27.664647 [DATLAT]
5401 13:38:27.668195 Freq=933, CH0 RK1
5402 13:38:27.668272
5403 13:38:27.668335 DATLAT Default: 0xb
5404 13:38:27.671479 0, 0xFFFF, sum = 0
5405 13:38:27.674765 1, 0xFFFF, sum = 0
5406 13:38:27.674848 2, 0xFFFF, sum = 0
5407 13:38:27.677942 3, 0xFFFF, sum = 0
5408 13:38:27.678045 4, 0xFFFF, sum = 0
5409 13:38:27.681303 5, 0xFFFF, sum = 0
5410 13:38:27.681386 6, 0xFFFF, sum = 0
5411 13:38:27.684834 7, 0xFFFF, sum = 0
5412 13:38:27.684922 8, 0xFFFF, sum = 0
5413 13:38:27.687879 9, 0xFFFF, sum = 0
5414 13:38:27.687991 10, 0x0, sum = 1
5415 13:38:27.691113 11, 0x0, sum = 2
5416 13:38:27.691226 12, 0x0, sum = 3
5417 13:38:27.694359 13, 0x0, sum = 4
5418 13:38:27.694474 best_step = 11
5419 13:38:27.694568
5420 13:38:27.694660 ==
5421 13:38:27.697576 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 13:38:27.701406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 13:38:27.704545 ==
5424 13:38:27.704650 RX Vref Scan: 0
5425 13:38:27.704725
5426 13:38:27.707849 RX Vref 0 -> 0, step: 1
5427 13:38:27.707947
5428 13:38:27.711130 RX Delay -53 -> 252, step: 4
5429 13:38:27.714367 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5430 13:38:27.717528 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5431 13:38:27.720724 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5432 13:38:27.727272 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5433 13:38:27.730545 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5434 13:38:27.733782 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5435 13:38:27.737618 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5436 13:38:27.740494 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5437 13:38:27.746943 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5438 13:38:27.750518 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5439 13:38:27.753613 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5440 13:38:27.757091 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5441 13:38:27.760191 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5442 13:38:27.763365 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5443 13:38:27.770003 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5444 13:38:27.773221 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5445 13:38:27.773327 ==
5446 13:38:27.777031 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 13:38:27.780313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 13:38:27.780395 ==
5449 13:38:27.783535 DQS Delay:
5450 13:38:27.783646 DQS0 = 0, DQS1 = 0
5451 13:38:27.783743 DQM Delay:
5452 13:38:27.786731 DQM0 = 97, DQM1 = 89
5453 13:38:27.786838 DQ Delay:
5454 13:38:27.789917 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5455 13:38:27.793066 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5456 13:38:27.796667 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5457 13:38:27.800016 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =96
5458 13:38:27.800128
5459 13:38:27.800227
5460 13:38:27.809634 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5461 13:38:27.813492 CH0 RK1: MR19=505, MR18=1B19
5462 13:38:27.816637 CH0_RK1: MR19=0x505, MR18=0x1B19, DQSOSC=413, MR23=63, INC=63, DEC=42
5463 13:38:27.819825 [RxdqsGatingPostProcess] freq 933
5464 13:38:27.826550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 13:38:27.829746 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 13:38:27.833042 best DQS1 dly(2T, 0.5T) = (0, 11)
5467 13:38:27.836195 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 13:38:27.839544 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5469 13:38:27.842587 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 13:38:27.845898 best DQS1 dly(2T, 0.5T) = (0, 11)
5471 13:38:27.849054 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 13:38:27.852699 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5473 13:38:27.855707 Pre-setting of DQS Precalculation
5474 13:38:27.859052 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 13:38:27.859161 ==
5476 13:38:27.862747 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 13:38:27.869001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 13:38:27.869124 ==
5479 13:38:27.872395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 13:38:27.878711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5481 13:38:27.882126 [CA 0] Center 36 (6~67) winsize 62
5482 13:38:27.885202 [CA 1] Center 37 (7~67) winsize 61
5483 13:38:27.888965 [CA 2] Center 35 (5~65) winsize 61
5484 13:38:27.892269 [CA 3] Center 34 (4~64) winsize 61
5485 13:38:27.895551 [CA 4] Center 34 (4~64) winsize 61
5486 13:38:27.898851 [CA 5] Center 33 (3~64) winsize 62
5487 13:38:27.898965
5488 13:38:27.901837 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5489 13:38:27.901945
5490 13:38:27.905436 [CATrainingPosCal] consider 1 rank data
5491 13:38:27.908656 u2DelayCellTimex100 = 270/100 ps
5492 13:38:27.911872 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 13:38:27.915055 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5494 13:38:27.921479 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5495 13:38:27.924794 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5496 13:38:27.928802 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5497 13:38:27.931786 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 13:38:27.931920
5499 13:38:27.935136 CA PerBit enable=1, Macro0, CA PI delay=33
5500 13:38:27.935233
5501 13:38:27.938486 [CBTSetCACLKResult] CA Dly = 33
5502 13:38:27.938575 CS Dly: 5 (0~36)
5503 13:38:27.941723 ==
5504 13:38:27.944508 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 13:38:27.947920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 13:38:27.948037 ==
5507 13:38:27.951086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 13:38:27.957659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5509 13:38:27.961583 [CA 0] Center 36 (6~67) winsize 62
5510 13:38:27.965301 [CA 1] Center 37 (6~68) winsize 63
5511 13:38:27.968243 [CA 2] Center 34 (4~65) winsize 62
5512 13:38:27.971551 [CA 3] Center 33 (3~64) winsize 62
5513 13:38:27.974756 [CA 4] Center 34 (4~64) winsize 61
5514 13:38:27.978075 [CA 5] Center 33 (3~63) winsize 61
5515 13:38:27.978168
5516 13:38:27.981234 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5517 13:38:27.981327
5518 13:38:27.985101 [CATrainingPosCal] consider 2 rank data
5519 13:38:27.987978 u2DelayCellTimex100 = 270/100 ps
5520 13:38:27.994414 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 13:38:27.997743 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5522 13:38:28.001283 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5523 13:38:28.004521 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 13:38:28.007719 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 13:38:28.010817 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5526 13:38:28.010931
5527 13:38:28.014332 CA PerBit enable=1, Macro0, CA PI delay=33
5528 13:38:28.014439
5529 13:38:28.017367 [CBTSetCACLKResult] CA Dly = 33
5530 13:38:28.020537 CS Dly: 6 (0~39)
5531 13:38:28.020642
5532 13:38:28.024211 ----->DramcWriteLeveling(PI) begin...
5533 13:38:28.024322 ==
5534 13:38:28.027102 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 13:38:28.030927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 13:38:28.031037 ==
5537 13:38:28.034248 Write leveling (Byte 0): 25 => 25
5538 13:38:28.036922 Write leveling (Byte 1): 29 => 29
5539 13:38:28.040776 DramcWriteLeveling(PI) end<-----
5540 13:38:28.040873
5541 13:38:28.040940 ==
5542 13:38:28.043939 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 13:38:28.047226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 13:38:28.047305 ==
5545 13:38:28.050334 [Gating] SW mode calibration
5546 13:38:28.057417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 13:38:28.063674 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 13:38:28.066823 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 13:38:28.073328 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 13:38:28.076948 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 13:38:28.080063 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 13:38:28.086451 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 13:38:28.089777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 13:38:28.093357 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
5555 13:38:28.099706 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5556 13:38:28.103070 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 13:38:28.106049 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 13:38:28.112750 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 13:38:28.115919 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 13:38:28.119180 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 13:38:28.126081 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 13:38:28.129628 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5563 13:38:28.132486 0 15 28 | B1->B0 | 3a3a 4444 | 0 0 | (1 1) (0 0)
5564 13:38:28.139475 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 13:38:28.142567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 13:38:28.145812 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 13:38:28.152356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 13:38:28.155539 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 13:38:28.159321 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 13:38:28.165885 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 13:38:28.169046 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5572 13:38:28.172433 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5573 13:38:28.178730 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 13:38:28.181928 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:38:28.185910 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:38:28.192324 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:38:28.195186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:38:28.198843 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:38:28.205435 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:38:28.208405 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 13:38:28.212257 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 13:38:28.218419 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:38:28.221818 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:38:28.225140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:38:28.231495 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:38:28.234829 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5587 13:38:28.238696 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 13:38:28.244747 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 13:38:28.244845 Total UI for P1: 0, mck2ui 16
5590 13:38:28.251284 best dqsien dly found for B0: ( 1, 2, 26)
5591 13:38:28.251402 Total UI for P1: 0, mck2ui 16
5592 13:38:28.254815 best dqsien dly found for B1: ( 1, 2, 28)
5593 13:38:28.261395 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5594 13:38:28.264517 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5595 13:38:28.264604
5596 13:38:28.267918 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5597 13:38:28.271167 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5598 13:38:28.274493 [Gating] SW calibration Done
5599 13:38:28.274574 ==
5600 13:38:28.277800 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 13:38:28.281182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 13:38:28.281291 ==
5603 13:38:28.284341 RX Vref Scan: 0
5604 13:38:28.284426
5605 13:38:28.284490 RX Vref 0 -> 0, step: 1
5606 13:38:28.284551
5607 13:38:28.287580 RX Delay -80 -> 252, step: 8
5608 13:38:28.290890 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5609 13:38:28.297311 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5610 13:38:28.301107 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5611 13:38:28.304340 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5612 13:38:28.307433 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5613 13:38:28.310452 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5614 13:38:28.314038 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5615 13:38:28.320321 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5616 13:38:28.323863 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5617 13:38:28.327707 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5618 13:38:28.330343 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5619 13:38:28.333782 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5620 13:38:28.340349 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5621 13:38:28.343539 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5622 13:38:28.346771 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5623 13:38:28.350613 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5624 13:38:28.350712 ==
5625 13:38:28.353733 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 13:38:28.356891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 13:38:28.360520 ==
5628 13:38:28.360632 DQS Delay:
5629 13:38:28.360739 DQS0 = 0, DQS1 = 0
5630 13:38:28.363093 DQM Delay:
5631 13:38:28.363178 DQM0 = 98, DQM1 = 93
5632 13:38:28.366548 DQ Delay:
5633 13:38:28.369831 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5634 13:38:28.373583 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5635 13:38:28.376785 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5636 13:38:28.380058 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =103
5637 13:38:28.380162
5638 13:38:28.380254
5639 13:38:28.380345 ==
5640 13:38:28.383198 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 13:38:28.386423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 13:38:28.386515 ==
5643 13:38:28.386581
5644 13:38:28.386640
5645 13:38:28.389665 TX Vref Scan disable
5646 13:38:28.392852 == TX Byte 0 ==
5647 13:38:28.396108 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5648 13:38:28.399334 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5649 13:38:28.402594 == TX Byte 1 ==
5650 13:38:28.405843 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5651 13:38:28.409738 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5652 13:38:28.409822 ==
5653 13:38:28.412906 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 13:38:28.416126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 13:38:28.419379 ==
5656 13:38:28.419487
5657 13:38:28.419584
5658 13:38:28.419674 TX Vref Scan disable
5659 13:38:28.423011 == TX Byte 0 ==
5660 13:38:28.425987 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5661 13:38:28.432646 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5662 13:38:28.432777 == TX Byte 1 ==
5663 13:38:28.436081 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5664 13:38:28.442837 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5665 13:38:28.442957
5666 13:38:28.443055 [DATLAT]
5667 13:38:28.443147 Freq=933, CH1 RK0
5668 13:38:28.443237
5669 13:38:28.446268 DATLAT Default: 0xd
5670 13:38:28.446366 0, 0xFFFF, sum = 0
5671 13:38:28.449529 1, 0xFFFF, sum = 0
5672 13:38:28.452929 2, 0xFFFF, sum = 0
5673 13:38:28.453034 3, 0xFFFF, sum = 0
5674 13:38:28.456201 4, 0xFFFF, sum = 0
5675 13:38:28.456308 5, 0xFFFF, sum = 0
5676 13:38:28.459142 6, 0xFFFF, sum = 0
5677 13:38:28.459225 7, 0xFFFF, sum = 0
5678 13:38:28.462848 8, 0xFFFF, sum = 0
5679 13:38:28.462954 9, 0xFFFF, sum = 0
5680 13:38:28.466070 10, 0x0, sum = 1
5681 13:38:28.466177 11, 0x0, sum = 2
5682 13:38:28.469157 12, 0x0, sum = 3
5683 13:38:28.469269 13, 0x0, sum = 4
5684 13:38:28.469366 best_step = 11
5685 13:38:28.472324
5686 13:38:28.472429 ==
5687 13:38:28.475907 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 13:38:28.478893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 13:38:28.479007 ==
5690 13:38:28.479103 RX Vref Scan: 1
5691 13:38:28.479193
5692 13:38:28.482144 RX Vref 0 -> 0, step: 1
5693 13:38:28.482242
5694 13:38:28.485869 RX Delay -61 -> 252, step: 4
5695 13:38:28.485984
5696 13:38:28.489140 Set Vref, RX VrefLevel [Byte0]: 53
5697 13:38:28.492370 [Byte1]: 51
5698 13:38:28.495510
5699 13:38:28.495591 Final RX Vref Byte 0 = 53 to rank0
5700 13:38:28.498888 Final RX Vref Byte 1 = 51 to rank0
5701 13:38:28.502039 Final RX Vref Byte 0 = 53 to rank1
5702 13:38:28.505196 Final RX Vref Byte 1 = 51 to rank1==
5703 13:38:28.508488 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 13:38:28.515639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 13:38:28.515726 ==
5706 13:38:28.515797 DQS Delay:
5707 13:38:28.515876 DQS0 = 0, DQS1 = 0
5708 13:38:28.519221 DQM Delay:
5709 13:38:28.519313 DQM0 = 96, DQM1 = 93
5710 13:38:28.522242 DQ Delay:
5711 13:38:28.525413 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5712 13:38:28.528549 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5713 13:38:28.531810 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5714 13:38:28.534996 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5715 13:38:28.535121
5716 13:38:28.535247
5717 13:38:28.541496 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5718 13:38:28.545000 CH1 RK0: MR19=505, MR18=C1C
5719 13:38:28.551416 CH1_RK0: MR19=0x505, MR18=0xC1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5720 13:38:28.551536
5721 13:38:28.555082 ----->DramcWriteLeveling(PI) begin...
5722 13:38:28.555199 ==
5723 13:38:28.558083 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 13:38:28.561772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 13:38:28.561874 ==
5726 13:38:28.564483 Write leveling (Byte 0): 26 => 26
5727 13:38:28.568046 Write leveling (Byte 1): 26 => 26
5728 13:38:28.571158 DramcWriteLeveling(PI) end<-----
5729 13:38:28.571243
5730 13:38:28.571314 ==
5731 13:38:28.574567 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 13:38:28.580956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 13:38:28.581083 ==
5734 13:38:28.581184 [Gating] SW mode calibration
5735 13:38:28.591163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5736 13:38:28.594391 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5737 13:38:28.597639 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 13:38:28.604167 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 13:38:28.607911 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 13:38:28.611043 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 13:38:28.617546 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 13:38:28.620806 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5743 13:38:28.624099 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5744 13:38:28.630619 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5745 13:38:28.633716 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 13:38:28.637460 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 13:38:28.644205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 13:38:28.647391 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 13:38:28.650427 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 13:38:28.656975 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 13:38:28.660173 0 15 24 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
5752 13:38:28.663417 0 15 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5753 13:38:28.670448 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 13:38:28.673549 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 13:38:28.676689 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 13:38:28.683116 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 13:38:28.686492 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 13:38:28.692964 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 13:38:28.696583 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5760 13:38:28.699558 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5761 13:38:28.706146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 13:38:28.710111 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 13:38:28.712788 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 13:38:28.719225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:38:28.723072 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:38:28.726322 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 13:38:28.732860 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 13:38:28.735978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 13:38:28.739213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 13:38:28.745671 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 13:38:28.748875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 13:38:28.752235 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:38:28.759084 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:38:28.761994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:38:28.765502 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5776 13:38:28.772512 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5777 13:38:28.772635 Total UI for P1: 0, mck2ui 16
5778 13:38:28.778981 best dqsien dly found for B0: ( 1, 2, 24)
5779 13:38:28.782219 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 13:38:28.785332 Total UI for P1: 0, mck2ui 16
5781 13:38:28.788414 best dqsien dly found for B1: ( 1, 2, 26)
5782 13:38:28.792051 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5783 13:38:28.795185 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5784 13:38:28.795306
5785 13:38:28.798163 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5786 13:38:28.801594 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5787 13:38:28.804965 [Gating] SW calibration Done
5788 13:38:28.805074 ==
5789 13:38:28.808262 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 13:38:28.812085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 13:38:28.814732 ==
5792 13:38:28.814822 RX Vref Scan: 0
5793 13:38:28.814891
5794 13:38:28.818357 RX Vref 0 -> 0, step: 1
5795 13:38:28.818438
5796 13:38:28.821446 RX Delay -80 -> 252, step: 8
5797 13:38:28.824569 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5798 13:38:28.827914 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5799 13:38:28.831332 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5800 13:38:28.834466 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5801 13:38:28.837678 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5802 13:38:28.844673 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5803 13:38:28.848013 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5804 13:38:28.851370 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5805 13:38:28.854678 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5806 13:38:28.858073 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5807 13:38:28.864525 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5808 13:38:28.867584 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5809 13:38:28.870947 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5810 13:38:28.874158 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5811 13:38:28.877107 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5812 13:38:28.884215 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5813 13:38:28.884348 ==
5814 13:38:28.886945 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 13:38:28.890870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 13:38:28.890990 ==
5817 13:38:28.891086 DQS Delay:
5818 13:38:28.893974 DQS0 = 0, DQS1 = 0
5819 13:38:28.894055 DQM Delay:
5820 13:38:28.897411 DQM0 = 96, DQM1 = 92
5821 13:38:28.897492 DQ Delay:
5822 13:38:28.900617 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5823 13:38:28.903900 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5824 13:38:28.906930 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5825 13:38:28.910146 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5826 13:38:28.910266
5827 13:38:28.910364
5828 13:38:28.910442 ==
5829 13:38:28.913572 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 13:38:28.919977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 13:38:28.920063 ==
5832 13:38:28.920173
5833 13:38:28.920260
5834 13:38:28.920347 TX Vref Scan disable
5835 13:38:28.923538 == TX Byte 0 ==
5836 13:38:28.926451 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5837 13:38:28.930006 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5838 13:38:28.933463 == TX Byte 1 ==
5839 13:38:28.936435 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5840 13:38:28.943171 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5841 13:38:28.943261 ==
5842 13:38:28.946262 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 13:38:28.949438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 13:38:28.949517 ==
5845 13:38:28.949586
5846 13:38:28.949648
5847 13:38:28.953410 TX Vref Scan disable
5848 13:38:28.953505 == TX Byte 0 ==
5849 13:38:28.959855 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5850 13:38:28.963285 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5851 13:38:28.963397 == TX Byte 1 ==
5852 13:38:28.969749 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5853 13:38:28.972975 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5854 13:38:28.973093
5855 13:38:28.973191 [DATLAT]
5856 13:38:28.976301 Freq=933, CH1 RK1
5857 13:38:28.976437
5858 13:38:28.976535 DATLAT Default: 0xb
5859 13:38:28.979415 0, 0xFFFF, sum = 0
5860 13:38:28.979524 1, 0xFFFF, sum = 0
5861 13:38:28.982675 2, 0xFFFF, sum = 0
5862 13:38:28.985887 3, 0xFFFF, sum = 0
5863 13:38:28.986017 4, 0xFFFF, sum = 0
5864 13:38:28.989390 5, 0xFFFF, sum = 0
5865 13:38:28.989487 6, 0xFFFF, sum = 0
5866 13:38:28.992748 7, 0xFFFF, sum = 0
5867 13:38:28.992875 8, 0xFFFF, sum = 0
5868 13:38:28.995635 9, 0xFFFF, sum = 0
5869 13:38:28.995751 10, 0x0, sum = 1
5870 13:38:28.999144 11, 0x0, sum = 2
5871 13:38:28.999224 12, 0x0, sum = 3
5872 13:38:29.002508 13, 0x0, sum = 4
5873 13:38:29.002614 best_step = 11
5874 13:38:29.002718
5875 13:38:29.002810 ==
5876 13:38:29.005683 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 13:38:29.009028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 13:38:29.009142 ==
5879 13:38:29.012123 RX Vref Scan: 0
5880 13:38:29.012232
5881 13:38:29.015434 RX Vref 0 -> 0, step: 1
5882 13:38:29.015537
5883 13:38:29.015652 RX Delay -61 -> 252, step: 4
5884 13:38:29.023474 iDelay=199, Bit 0, Center 100 (7 ~ 194) 188
5885 13:38:29.027056 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5886 13:38:29.030346 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5887 13:38:29.033834 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5888 13:38:29.036983 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5889 13:38:29.043544 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5890 13:38:29.046977 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5891 13:38:29.049942 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5892 13:38:29.053730 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5893 13:38:29.056954 iDelay=199, Bit 9, Center 80 (-13 ~ 174) 188
5894 13:38:29.060258 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5895 13:38:29.066537 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5896 13:38:29.069874 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5897 13:38:29.073384 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5898 13:38:29.076379 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5899 13:38:29.082970 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5900 13:38:29.083086 ==
5901 13:38:29.086715 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 13:38:29.089982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 13:38:29.090094 ==
5904 13:38:29.090190 DQS Delay:
5905 13:38:29.093364 DQS0 = 0, DQS1 = 0
5906 13:38:29.093446 DQM Delay:
5907 13:38:29.096220 DQM0 = 96, DQM1 = 92
5908 13:38:29.096327 DQ Delay:
5909 13:38:29.100034 DQ0 =100, DQ1 =94, DQ2 =84, DQ3 =92
5910 13:38:29.102780 DQ4 =98, DQ5 =104, DQ6 =104, DQ7 =94
5911 13:38:29.106196 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5912 13:38:29.109602 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5913 13:38:29.109700
5914 13:38:29.109771
5915 13:38:29.119498 [DQSOSCAuto] RK1, (LSB)MR18= 0x1229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 416 ps
5916 13:38:29.119611 CH1 RK1: MR19=505, MR18=1229
5917 13:38:29.126090 CH1_RK1: MR19=0x505, MR18=0x1229, DQSOSC=408, MR23=63, INC=65, DEC=43
5918 13:38:29.129285 [RxdqsGatingPostProcess] freq 933
5919 13:38:29.135747 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5920 13:38:29.139523 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 13:38:29.142275 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 13:38:29.145387 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 13:38:29.149078 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 13:38:29.152265 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 13:38:29.155266 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 13:38:29.158888 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 13:38:29.162251 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 13:38:29.162372 Pre-setting of DQS Precalculation
5929 13:38:29.168461 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5930 13:38:29.175631 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5931 13:38:29.181435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5932 13:38:29.181532
5933 13:38:29.181601
5934 13:38:29.184824 [Calibration Summary] 1866 Mbps
5935 13:38:29.188694 CH 0, Rank 0
5936 13:38:29.188788 SW Impedance : PASS
5937 13:38:29.191388 DUTY Scan : NO K
5938 13:38:29.195298 ZQ Calibration : PASS
5939 13:38:29.195384 Jitter Meter : NO K
5940 13:38:29.197934 CBT Training : PASS
5941 13:38:29.201334 Write leveling : PASS
5942 13:38:29.201422 RX DQS gating : PASS
5943 13:38:29.204941 RX DQ/DQS(RDDQC) : PASS
5944 13:38:29.208195 TX DQ/DQS : PASS
5945 13:38:29.208285 RX DATLAT : PASS
5946 13:38:29.211497 RX DQ/DQS(Engine): PASS
5947 13:38:29.214666 TX OE : NO K
5948 13:38:29.214754 All Pass.
5949 13:38:29.214821
5950 13:38:29.214885 CH 0, Rank 1
5951 13:38:29.217605 SW Impedance : PASS
5952 13:38:29.221344 DUTY Scan : NO K
5953 13:38:29.221447 ZQ Calibration : PASS
5954 13:38:29.224372 Jitter Meter : NO K
5955 13:38:29.227874 CBT Training : PASS
5956 13:38:29.227961 Write leveling : PASS
5957 13:38:29.230913 RX DQS gating : PASS
5958 13:38:29.234415 RX DQ/DQS(RDDQC) : PASS
5959 13:38:29.234540 TX DQ/DQS : PASS
5960 13:38:29.237486 RX DATLAT : PASS
5961 13:38:29.240734 RX DQ/DQS(Engine): PASS
5962 13:38:29.240820 TX OE : NO K
5963 13:38:29.240888 All Pass.
5964 13:38:29.243910
5965 13:38:29.244027 CH 1, Rank 0
5966 13:38:29.247488 SW Impedance : PASS
5967 13:38:29.247601 DUTY Scan : NO K
5968 13:38:29.250376 ZQ Calibration : PASS
5969 13:38:29.253918 Jitter Meter : NO K
5970 13:38:29.254031 CBT Training : PASS
5971 13:38:29.257275 Write leveling : PASS
5972 13:38:29.257355 RX DQS gating : PASS
5973 13:38:29.260578 RX DQ/DQS(RDDQC) : PASS
5974 13:38:29.263815 TX DQ/DQS : PASS
5975 13:38:29.263922 RX DATLAT : PASS
5976 13:38:29.266877 RX DQ/DQS(Engine): PASS
5977 13:38:29.270665 TX OE : NO K
5978 13:38:29.270780 All Pass.
5979 13:38:29.270875
5980 13:38:29.270965 CH 1, Rank 1
5981 13:38:29.273503 SW Impedance : PASS
5982 13:38:29.276896 DUTY Scan : NO K
5983 13:38:29.276999 ZQ Calibration : PASS
5984 13:38:29.280412 Jitter Meter : NO K
5985 13:38:29.283718 CBT Training : PASS
5986 13:38:29.283831 Write leveling : PASS
5987 13:38:29.287125 RX DQS gating : PASS
5988 13:38:29.290232 RX DQ/DQS(RDDQC) : PASS
5989 13:38:29.290345 TX DQ/DQS : PASS
5990 13:38:29.293483 RX DATLAT : PASS
5991 13:38:29.297275 RX DQ/DQS(Engine): PASS
5992 13:38:29.297366 TX OE : NO K
5993 13:38:29.300568 All Pass.
5994 13:38:29.300668
5995 13:38:29.300760 DramC Write-DBI off
5996 13:38:29.303914 PER_BANK_REFRESH: Hybrid Mode
5997 13:38:29.304023 TX_TRACKING: ON
5998 13:38:29.313706 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5999 13:38:29.316701 [FAST_K] Save calibration result to emmc
6000 13:38:29.319940 dramc_set_vcore_voltage set vcore to 650000
6001 13:38:29.323222 Read voltage for 400, 6
6002 13:38:29.323305 Vio18 = 0
6003 13:38:29.326315 Vcore = 650000
6004 13:38:29.326425 Vdram = 0
6005 13:38:29.326518 Vddq = 0
6006 13:38:29.329568 Vmddr = 0
6007 13:38:29.333421 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6008 13:38:29.339560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6009 13:38:29.339657 MEM_TYPE=3, freq_sel=20
6010 13:38:29.343023 sv_algorithm_assistance_LP4_800
6011 13:38:29.349550 ============ PULL DRAM RESETB DOWN ============
6012 13:38:29.352786 ========== PULL DRAM RESETB DOWN end =========
6013 13:38:29.356208 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 13:38:29.359787 ===================================
6015 13:38:29.362552 LPDDR4 DRAM CONFIGURATION
6016 13:38:29.366075 ===================================
6017 13:38:29.369426 EX_ROW_EN[0] = 0x0
6018 13:38:29.369511 EX_ROW_EN[1] = 0x0
6019 13:38:29.372685 LP4Y_EN = 0x0
6020 13:38:29.372765 WORK_FSP = 0x0
6021 13:38:29.375978 WL = 0x2
6022 13:38:29.376067 RL = 0x2
6023 13:38:29.379173 BL = 0x2
6024 13:38:29.379285 RPST = 0x0
6025 13:38:29.382543 RD_PRE = 0x0
6026 13:38:29.382628 WR_PRE = 0x1
6027 13:38:29.385896 WR_PST = 0x0
6028 13:38:29.385981 DBI_WR = 0x0
6029 13:38:29.389327 DBI_RD = 0x0
6030 13:38:29.389428 OTF = 0x1
6031 13:38:29.392320 ===================================
6032 13:38:29.395786 ===================================
6033 13:38:29.399306 ANA top config
6034 13:38:29.402459 ===================================
6035 13:38:29.405596 DLL_ASYNC_EN = 0
6036 13:38:29.405677 ALL_SLAVE_EN = 1
6037 13:38:29.408752 NEW_RANK_MODE = 1
6038 13:38:29.412059 DLL_IDLE_MODE = 1
6039 13:38:29.415438 LP45_APHY_COMB_EN = 1
6040 13:38:29.418600 TX_ODT_DIS = 1
6041 13:38:29.418711 NEW_8X_MODE = 1
6042 13:38:29.421779 ===================================
6043 13:38:29.425566 ===================================
6044 13:38:29.428879 data_rate = 800
6045 13:38:29.432017 CKR = 1
6046 13:38:29.435324 DQ_P2S_RATIO = 4
6047 13:38:29.438401 ===================================
6048 13:38:29.441700 CA_P2S_RATIO = 4
6049 13:38:29.445926 DQ_CA_OPEN = 0
6050 13:38:29.446040 DQ_SEMI_OPEN = 1
6051 13:38:29.448761 CA_SEMI_OPEN = 1
6052 13:38:29.451579 CA_FULL_RATE = 0
6053 13:38:29.455138 DQ_CKDIV4_EN = 0
6054 13:38:29.458600 CA_CKDIV4_EN = 1
6055 13:38:29.461809 CA_PREDIV_EN = 0
6056 13:38:29.461923 PH8_DLY = 0
6057 13:38:29.465040 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6058 13:38:29.468099 DQ_AAMCK_DIV = 0
6059 13:38:29.471705 CA_AAMCK_DIV = 0
6060 13:38:29.474664 CA_ADMCK_DIV = 4
6061 13:38:29.477948 DQ_TRACK_CA_EN = 0
6062 13:38:29.478059 CA_PICK = 800
6063 13:38:29.481116 CA_MCKIO = 400
6064 13:38:29.484972 MCKIO_SEMI = 400
6065 13:38:29.488188 PLL_FREQ = 3016
6066 13:38:29.491397 DQ_UI_PI_RATIO = 32
6067 13:38:29.494578 CA_UI_PI_RATIO = 32
6068 13:38:29.498304 ===================================
6069 13:38:29.501415 ===================================
6070 13:38:29.504402 memory_type:LPDDR4
6071 13:38:29.504488 GP_NUM : 10
6072 13:38:29.507737 SRAM_EN : 1
6073 13:38:29.507819 MD32_EN : 0
6074 13:38:29.511033 ===================================
6075 13:38:29.514187 [ANA_INIT] >>>>>>>>>>>>>>
6076 13:38:29.517322 <<<<<< [CONFIGURE PHASE]: ANA_TX
6077 13:38:29.520576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6078 13:38:29.523824 ===================================
6079 13:38:29.527146 data_rate = 800,PCW = 0X7400
6080 13:38:29.531020 ===================================
6081 13:38:29.534131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6082 13:38:29.540602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 13:38:29.550385 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 13:38:29.556772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6085 13:38:29.560436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6086 13:38:29.563614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6087 13:38:29.563728 [ANA_INIT] flow start
6088 13:38:29.566794 [ANA_INIT] PLL >>>>>>>>
6089 13:38:29.570434 [ANA_INIT] PLL <<<<<<<<
6090 13:38:29.570527 [ANA_INIT] MIDPI >>>>>>>>
6091 13:38:29.573234 [ANA_INIT] MIDPI <<<<<<<<
6092 13:38:29.576829 [ANA_INIT] DLL >>>>>>>>
6093 13:38:29.576915 [ANA_INIT] flow end
6094 13:38:29.583258 ============ LP4 DIFF to SE enter ============
6095 13:38:29.586389 ============ LP4 DIFF to SE exit ============
6096 13:38:29.589748 [ANA_INIT] <<<<<<<<<<<<<
6097 13:38:29.593019 [Flow] Enable top DCM control >>>>>
6098 13:38:29.596170 [Flow] Enable top DCM control <<<<<
6099 13:38:29.596283 Enable DLL master slave shuffle
6100 13:38:29.602718 ==============================================================
6101 13:38:29.606435 Gating Mode config
6102 13:38:29.609589 ==============================================================
6103 13:38:29.612844 Config description:
6104 13:38:29.622453 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6105 13:38:29.629578 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6106 13:38:29.632853 SELPH_MODE 0: By rank 1: By Phase
6107 13:38:29.639100 ==============================================================
6108 13:38:29.642321 GAT_TRACK_EN = 0
6109 13:38:29.645630 RX_GATING_MODE = 2
6110 13:38:29.648844 RX_GATING_TRACK_MODE = 2
6111 13:38:29.652564 SELPH_MODE = 1
6112 13:38:29.655725 PICG_EARLY_EN = 1
6113 13:38:29.658922 VALID_LAT_VALUE = 1
6114 13:38:29.662075 ==============================================================
6115 13:38:29.665432 Enter into Gating configuration >>>>
6116 13:38:29.668643 Exit from Gating configuration <<<<
6117 13:38:29.671828 Enter into DVFS_PRE_config >>>>>
6118 13:38:29.685358 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6119 13:38:29.685472 Exit from DVFS_PRE_config <<<<<
6120 13:38:29.688443 Enter into PICG configuration >>>>
6121 13:38:29.691721 Exit from PICG configuration <<<<
6122 13:38:29.694997 [RX_INPUT] configuration >>>>>
6123 13:38:29.698558 [RX_INPUT] configuration <<<<<
6124 13:38:29.704912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6125 13:38:29.708096 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6126 13:38:29.714890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 13:38:29.721398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 13:38:29.728166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 13:38:29.734285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 13:38:29.737931 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6131 13:38:29.741315 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6132 13:38:29.747707 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6133 13:38:29.750849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6134 13:38:29.754059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6135 13:38:29.757421 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 13:38:29.760779 ===================================
6137 13:38:29.764097 LPDDR4 DRAM CONFIGURATION
6138 13:38:29.767868 ===================================
6139 13:38:29.770519 EX_ROW_EN[0] = 0x0
6140 13:38:29.770600 EX_ROW_EN[1] = 0x0
6141 13:38:29.774315 LP4Y_EN = 0x0
6142 13:38:29.774400 WORK_FSP = 0x0
6143 13:38:29.777482 WL = 0x2
6144 13:38:29.777561 RL = 0x2
6145 13:38:29.780651 BL = 0x2
6146 13:38:29.780754 RPST = 0x0
6147 13:38:29.783829 RD_PRE = 0x0
6148 13:38:29.787051 WR_PRE = 0x1
6149 13:38:29.787139 WR_PST = 0x0
6150 13:38:29.790265 DBI_WR = 0x0
6151 13:38:29.790368 DBI_RD = 0x0
6152 13:38:29.793516 OTF = 0x1
6153 13:38:29.797140 ===================================
6154 13:38:29.800138 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6155 13:38:29.803478 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6156 13:38:29.807010 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 13:38:29.810369 ===================================
6158 13:38:29.813598 LPDDR4 DRAM CONFIGURATION
6159 13:38:29.816947 ===================================
6160 13:38:29.820262 EX_ROW_EN[0] = 0x10
6161 13:38:29.820345 EX_ROW_EN[1] = 0x0
6162 13:38:29.823455 LP4Y_EN = 0x0
6163 13:38:29.823552 WORK_FSP = 0x0
6164 13:38:29.826767 WL = 0x2
6165 13:38:29.826844 RL = 0x2
6166 13:38:29.829860 BL = 0x2
6167 13:38:29.829939 RPST = 0x0
6168 13:38:29.833134 RD_PRE = 0x0
6169 13:38:29.836918 WR_PRE = 0x1
6170 13:38:29.837001 WR_PST = 0x0
6171 13:38:29.840254 DBI_WR = 0x0
6172 13:38:29.840331 DBI_RD = 0x0
6173 13:38:29.843351 OTF = 0x1
6174 13:38:29.846372 ===================================
6175 13:38:29.849588 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6176 13:38:29.855377 nWR fixed to 30
6177 13:38:29.858485 [ModeRegInit_LP4] CH0 RK0
6178 13:38:29.858570 [ModeRegInit_LP4] CH0 RK1
6179 13:38:29.861726 [ModeRegInit_LP4] CH1 RK0
6180 13:38:29.865105 [ModeRegInit_LP4] CH1 RK1
6181 13:38:29.865187 match AC timing 19
6182 13:38:29.871735 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6183 13:38:29.875251 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6184 13:38:29.878096 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6185 13:38:29.885033 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6186 13:38:29.888359 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6187 13:38:29.888475 ==
6188 13:38:29.891621 Dram Type= 6, Freq= 0, CH_0, rank 0
6189 13:38:29.894889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6190 13:38:29.894992 ==
6191 13:38:29.901104 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6192 13:38:29.907741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6193 13:38:29.911541 [CA 0] Center 36 (8~64) winsize 57
6194 13:38:29.914773 [CA 1] Center 36 (8~64) winsize 57
6195 13:38:29.918052 [CA 2] Center 36 (8~64) winsize 57
6196 13:38:29.920949 [CA 3] Center 36 (8~64) winsize 57
6197 13:38:29.924269 [CA 4] Center 36 (8~64) winsize 57
6198 13:38:29.927371 [CA 5] Center 36 (8~64) winsize 57
6199 13:38:29.927454
6200 13:38:29.931087 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6201 13:38:29.931170
6202 13:38:29.934212 [CATrainingPosCal] consider 1 rank data
6203 13:38:29.937764 u2DelayCellTimex100 = 270/100 ps
6204 13:38:29.940877 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 13:38:29.944139 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 13:38:29.947198 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 13:38:29.951107 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 13:38:29.954244 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 13:38:29.957294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 13:38:29.957384
6211 13:38:29.964052 CA PerBit enable=1, Macro0, CA PI delay=36
6212 13:38:29.964160
6213 13:38:29.964234 [CBTSetCACLKResult] CA Dly = 36
6214 13:38:29.967158 CS Dly: 1 (0~32)
6215 13:38:29.967243 ==
6216 13:38:29.970634 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 13:38:29.973706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 13:38:29.973796 ==
6219 13:38:29.980822 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 13:38:29.987444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6221 13:38:29.990786 [CA 0] Center 36 (8~64) winsize 57
6222 13:38:29.993971 [CA 1] Center 36 (8~64) winsize 57
6223 13:38:29.997120 [CA 2] Center 36 (8~64) winsize 57
6224 13:38:30.000355 [CA 3] Center 36 (8~64) winsize 57
6225 13:38:30.000462 [CA 4] Center 36 (8~64) winsize 57
6226 13:38:30.003481 [CA 5] Center 36 (8~64) winsize 57
6227 13:38:30.003567
6228 13:38:30.010597 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6229 13:38:30.010688
6230 13:38:30.013744 [CATrainingPosCal] consider 2 rank data
6231 13:38:30.016971 u2DelayCellTimex100 = 270/100 ps
6232 13:38:30.020312 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 13:38:30.023508 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 13:38:30.026874 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 13:38:30.030236 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 13:38:30.033365 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:38:30.036667 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:38:30.036751
6239 13:38:30.039603 CA PerBit enable=1, Macro0, CA PI delay=36
6240 13:38:30.039688
6241 13:38:30.043127 [CBTSetCACLKResult] CA Dly = 36
6242 13:38:30.046382 CS Dly: 1 (0~32)
6243 13:38:30.046491
6244 13:38:30.049530 ----->DramcWriteLeveling(PI) begin...
6245 13:38:30.049612 ==
6246 13:38:30.052628 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 13:38:30.056439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 13:38:30.056524 ==
6249 13:38:30.059468 Write leveling (Byte 0): 40 => 8
6250 13:38:30.062644 Write leveling (Byte 1): 40 => 8
6251 13:38:30.066113 DramcWriteLeveling(PI) end<-----
6252 13:38:30.066200
6253 13:38:30.066292 ==
6254 13:38:30.069904 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 13:38:30.073055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 13:38:30.073139 ==
6257 13:38:30.076238 [Gating] SW mode calibration
6258 13:38:30.082834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6259 13:38:30.089064 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6260 13:38:30.092252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 13:38:30.098845 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 13:38:30.102066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 13:38:30.105606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 13:38:30.112082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 13:38:30.115684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 13:38:30.118874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 13:38:30.125466 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 13:38:30.128721 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 13:38:30.131979 Total UI for P1: 0, mck2ui 16
6270 13:38:30.135110 best dqsien dly found for B0: ( 0, 14, 24)
6271 13:38:30.138947 Total UI for P1: 0, mck2ui 16
6272 13:38:30.142249 best dqsien dly found for B1: ( 0, 14, 24)
6273 13:38:30.145584 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6274 13:38:30.148974 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6275 13:38:30.149072
6276 13:38:30.152136 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 13:38:30.155319 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 13:38:30.158483 [Gating] SW calibration Done
6279 13:38:30.158584 ==
6280 13:38:30.161939 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 13:38:30.168512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 13:38:30.168640 ==
6283 13:38:30.168742 RX Vref Scan: 0
6284 13:38:30.168841
6285 13:38:30.171936 RX Vref 0 -> 0, step: 1
6286 13:38:30.172061
6287 13:38:30.174705 RX Delay -410 -> 252, step: 16
6288 13:38:30.178047 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6289 13:38:30.181489 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6290 13:38:30.188090 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6291 13:38:30.191382 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6292 13:38:30.194837 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6293 13:38:30.198108 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6294 13:38:30.204615 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6295 13:38:30.207970 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6296 13:38:30.211271 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6297 13:38:30.214396 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6298 13:38:30.221098 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6299 13:38:30.224387 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6300 13:38:30.227500 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6301 13:38:30.230750 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6302 13:38:30.237668 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6303 13:38:30.240860 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6304 13:38:30.240978 ==
6305 13:38:30.244024 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 13:38:30.247297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 13:38:30.247407 ==
6308 13:38:30.251081 DQS Delay:
6309 13:38:30.251162 DQS0 = 35, DQS1 = 59
6310 13:38:30.254338 DQM Delay:
6311 13:38:30.254413 DQM0 = 4, DQM1 = 17
6312 13:38:30.254476 DQ Delay:
6313 13:38:30.257565 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6314 13:38:30.260688 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6315 13:38:30.264169 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6316 13:38:30.267682 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6317 13:38:30.267767
6318 13:38:30.267832
6319 13:38:30.267893 ==
6320 13:38:30.270623 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 13:38:30.277140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 13:38:30.277267 ==
6323 13:38:30.277340
6324 13:38:30.277402
6325 13:38:30.277461 TX Vref Scan disable
6326 13:38:30.280428 == TX Byte 0 ==
6327 13:38:30.283951 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 13:38:30.287170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 13:38:30.290349 == TX Byte 1 ==
6330 13:38:30.293353 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 13:38:30.296642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 13:38:30.299971 ==
6333 13:38:30.303098 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:38:30.306545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:38:30.306633 ==
6336 13:38:30.306700
6337 13:38:30.306765
6338 13:38:30.309806 TX Vref Scan disable
6339 13:38:30.309889 == TX Byte 0 ==
6340 13:38:30.313079 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 13:38:30.319913 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 13:38:30.320008 == TX Byte 1 ==
6343 13:38:30.323001 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 13:38:30.329563 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 13:38:30.329647
6346 13:38:30.329715 [DATLAT]
6347 13:38:30.329775 Freq=400, CH0 RK0
6348 13:38:30.329835
6349 13:38:30.332812 DATLAT Default: 0xf
6350 13:38:30.336771 0, 0xFFFF, sum = 0
6351 13:38:30.336847 1, 0xFFFF, sum = 0
6352 13:38:30.339799 2, 0xFFFF, sum = 0
6353 13:38:30.339885 3, 0xFFFF, sum = 0
6354 13:38:30.342928 4, 0xFFFF, sum = 0
6355 13:38:30.343006 5, 0xFFFF, sum = 0
6356 13:38:30.346004 6, 0xFFFF, sum = 0
6357 13:38:30.346079 7, 0xFFFF, sum = 0
6358 13:38:30.349289 8, 0xFFFF, sum = 0
6359 13:38:30.349365 9, 0xFFFF, sum = 0
6360 13:38:30.353151 10, 0xFFFF, sum = 0
6361 13:38:30.353237 11, 0xFFFF, sum = 0
6362 13:38:30.356464 12, 0xFFFF, sum = 0
6363 13:38:30.356549 13, 0x0, sum = 1
6364 13:38:30.359672 14, 0x0, sum = 2
6365 13:38:30.359756 15, 0x0, sum = 3
6366 13:38:30.362833 16, 0x0, sum = 4
6367 13:38:30.362919 best_step = 14
6368 13:38:30.362985
6369 13:38:30.363052 ==
6370 13:38:30.366193 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 13:38:30.372618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 13:38:30.372707 ==
6373 13:38:30.372776 RX Vref Scan: 1
6374 13:38:30.372854
6375 13:38:30.375655 RX Vref 0 -> 0, step: 1
6376 13:38:30.375729
6377 13:38:30.378969 RX Delay -359 -> 252, step: 8
6378 13:38:30.379055
6379 13:38:30.382636 Set Vref, RX VrefLevel [Byte0]: 50
6380 13:38:30.385906 [Byte1]: 58
6381 13:38:30.386007
6382 13:38:30.388898 Final RX Vref Byte 0 = 50 to rank0
6383 13:38:30.392213 Final RX Vref Byte 1 = 58 to rank0
6384 13:38:30.395714 Final RX Vref Byte 0 = 50 to rank1
6385 13:38:30.398885 Final RX Vref Byte 1 = 58 to rank1==
6386 13:38:30.402079 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 13:38:30.405254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 13:38:30.409076 ==
6389 13:38:30.409156 DQS Delay:
6390 13:38:30.409220 DQS0 = 40, DQS1 = 60
6391 13:38:30.412136 DQM Delay:
6392 13:38:30.412247 DQM0 = 7, DQM1 = 16
6393 13:38:30.415268 DQ Delay:
6394 13:38:30.415345 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =4
6395 13:38:30.418476 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6396 13:38:30.421889 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6397 13:38:30.425273 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6398 13:38:30.425361
6399 13:38:30.425425
6400 13:38:30.435078 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
6401 13:38:30.438359 CH0 RK0: MR19=C0C, MR18=9F93
6402 13:38:30.444960 CH0_RK0: MR19=0xC0C, MR18=0x9F93, DQSOSC=389, MR23=63, INC=390, DEC=260
6403 13:38:30.445065 ==
6404 13:38:30.448309 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 13:38:30.451427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 13:38:30.451536 ==
6407 13:38:30.454712 [Gating] SW mode calibration
6408 13:38:30.461271 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6409 13:38:30.467831 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6410 13:38:30.471632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 13:38:30.474296 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 13:38:30.481273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 13:38:30.484571 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 13:38:30.487457 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 13:38:30.494153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 13:38:30.497237 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 13:38:30.501069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 13:38:30.507649 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 13:38:30.507733 Total UI for P1: 0, mck2ui 16
6420 13:38:30.514108 best dqsien dly found for B0: ( 0, 14, 24)
6421 13:38:30.514200 Total UI for P1: 0, mck2ui 16
6422 13:38:30.520612 best dqsien dly found for B1: ( 0, 14, 24)
6423 13:38:30.523873 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6424 13:38:30.527052 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6425 13:38:30.527138
6426 13:38:30.530884 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 13:38:30.534074 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 13:38:30.537174 [Gating] SW calibration Done
6429 13:38:30.537295 ==
6430 13:38:30.540738 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 13:38:30.543707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 13:38:30.543814 ==
6433 13:38:30.547317 RX Vref Scan: 0
6434 13:38:30.547423
6435 13:38:30.547518 RX Vref 0 -> 0, step: 1
6436 13:38:30.547610
6437 13:38:30.550232 RX Delay -410 -> 252, step: 16
6438 13:38:30.556885 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6439 13:38:30.560409 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6440 13:38:30.563387 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6441 13:38:30.567136 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6442 13:38:30.573608 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6443 13:38:30.576897 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6444 13:38:30.580131 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6445 13:38:30.583348 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6446 13:38:30.589874 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6447 13:38:30.593100 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6448 13:38:30.596037 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6449 13:38:30.603086 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6450 13:38:30.606067 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6451 13:38:30.609771 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6452 13:38:30.613034 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6453 13:38:30.619378 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6454 13:38:30.619494 ==
6455 13:38:30.622983 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 13:38:30.626351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 13:38:30.626437 ==
6458 13:38:30.626504 DQS Delay:
6459 13:38:30.629482 DQS0 = 43, DQS1 = 59
6460 13:38:30.629561 DQM Delay:
6461 13:38:30.632824 DQM0 = 15, DQM1 = 17
6462 13:38:30.632935 DQ Delay:
6463 13:38:30.636110 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6464 13:38:30.639252 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6465 13:38:30.642575 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6466 13:38:30.645506 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6467 13:38:30.645595
6468 13:38:30.645662
6469 13:38:30.645724 ==
6470 13:38:30.648846 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 13:38:30.652062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 13:38:30.655368 ==
6473 13:38:30.655482
6474 13:38:30.655577
6475 13:38:30.655675 TX Vref Scan disable
6476 13:38:30.659200 == TX Byte 0 ==
6477 13:38:30.662203 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6478 13:38:30.665364 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6479 13:38:30.669121 == TX Byte 1 ==
6480 13:38:30.671851 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6481 13:38:30.675189 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6482 13:38:30.675317 ==
6483 13:38:30.678727 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 13:38:30.682039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 13:38:30.685111 ==
6486 13:38:30.685224
6487 13:38:30.685311
6488 13:38:30.685374 TX Vref Scan disable
6489 13:38:30.688402 == TX Byte 0 ==
6490 13:38:30.691671 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6491 13:38:30.695500 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6492 13:38:30.698789 == TX Byte 1 ==
6493 13:38:30.701908 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6494 13:38:30.705071 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6495 13:38:30.705159
6496 13:38:30.708228 [DATLAT]
6497 13:38:30.708342 Freq=400, CH0 RK1
6498 13:38:30.708414
6499 13:38:30.711748 DATLAT Default: 0xe
6500 13:38:30.711853 0, 0xFFFF, sum = 0
6501 13:38:30.715051 1, 0xFFFF, sum = 0
6502 13:38:30.715138 2, 0xFFFF, sum = 0
6503 13:38:30.718383 3, 0xFFFF, sum = 0
6504 13:38:30.718469 4, 0xFFFF, sum = 0
6505 13:38:30.721682 5, 0xFFFF, sum = 0
6506 13:38:30.721768 6, 0xFFFF, sum = 0
6507 13:38:30.724991 7, 0xFFFF, sum = 0
6508 13:38:30.725077 8, 0xFFFF, sum = 0
6509 13:38:30.728115 9, 0xFFFF, sum = 0
6510 13:38:30.728206 10, 0xFFFF, sum = 0
6511 13:38:30.731827 11, 0xFFFF, sum = 0
6512 13:38:30.735085 12, 0xFFFF, sum = 0
6513 13:38:30.735174 13, 0x0, sum = 1
6514 13:38:30.735243 14, 0x0, sum = 2
6515 13:38:30.738365 15, 0x0, sum = 3
6516 13:38:30.738453 16, 0x0, sum = 4
6517 13:38:30.741561 best_step = 14
6518 13:38:30.741647
6519 13:38:30.741715 ==
6520 13:38:30.744762 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 13:38:30.747944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 13:38:30.748061 ==
6523 13:38:30.750943 RX Vref Scan: 0
6524 13:38:30.751032
6525 13:38:30.751100 RX Vref 0 -> 0, step: 1
6526 13:38:30.754153
6527 13:38:30.754266 RX Delay -359 -> 252, step: 8
6528 13:38:30.762841 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6529 13:38:30.766460 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6530 13:38:30.769381 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6531 13:38:30.776468 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6532 13:38:30.779393 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6533 13:38:30.782455 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6534 13:38:30.785668 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6535 13:38:30.792612 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6536 13:38:30.795844 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6537 13:38:30.799438 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6538 13:38:30.802619 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6539 13:38:30.809041 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6540 13:38:30.812672 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6541 13:38:30.815792 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6542 13:38:30.819303 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6543 13:38:30.825819 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6544 13:38:30.825912 ==
6545 13:38:30.829233 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 13:38:30.832284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 13:38:30.832370 ==
6548 13:38:30.832438 DQS Delay:
6549 13:38:30.835284 DQS0 = 44, DQS1 = 60
6550 13:38:30.835391 DQM Delay:
6551 13:38:30.839083 DQM0 = 9, DQM1 = 16
6552 13:38:30.839195 DQ Delay:
6553 13:38:30.842158 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6554 13:38:30.845461 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6555 13:38:30.848625 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6556 13:38:30.851918 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6557 13:38:30.852030
6558 13:38:30.852125
6559 13:38:30.861589 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6560 13:38:30.861720 CH0 RK1: MR19=C0C, MR18=8A83
6561 13:38:30.868674 CH0_RK1: MR19=0xC0C, MR18=0x8A83, DQSOSC=392, MR23=63, INC=384, DEC=256
6562 13:38:30.871961 [RxdqsGatingPostProcess] freq 400
6563 13:38:30.878354 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6564 13:38:30.881615 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 13:38:30.884847 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 13:38:30.888186 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 13:38:30.891100 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 13:38:30.894522 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 13:38:30.894609 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 13:38:30.897815 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 13:38:30.901541 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 13:38:30.904434 Pre-setting of DQS Precalculation
6573 13:38:30.911175 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6574 13:38:30.911271 ==
6575 13:38:30.914381 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 13:38:30.917871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 13:38:30.917969 ==
6578 13:38:30.924561 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6579 13:38:30.930796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6580 13:38:30.934101 [CA 0] Center 36 (8~64) winsize 57
6581 13:38:30.937942 [CA 1] Center 36 (8~64) winsize 57
6582 13:38:30.940988 [CA 2] Center 36 (8~64) winsize 57
6583 13:38:30.941078 [CA 3] Center 36 (8~64) winsize 57
6584 13:38:30.943998 [CA 4] Center 36 (8~64) winsize 57
6585 13:38:30.947263 [CA 5] Center 36 (8~64) winsize 57
6586 13:38:30.947350
6587 13:38:30.954320 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6588 13:38:30.954412
6589 13:38:30.957691 [CATrainingPosCal] consider 1 rank data
6590 13:38:30.960908 u2DelayCellTimex100 = 270/100 ps
6591 13:38:30.963959 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 13:38:30.967015 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 13:38:30.970889 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 13:38:30.974060 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 13:38:30.977363 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 13:38:30.980600 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 13:38:30.980687
6598 13:38:30.983813 CA PerBit enable=1, Macro0, CA PI delay=36
6599 13:38:30.983898
6600 13:38:30.987253 [CBTSetCACLKResult] CA Dly = 36
6601 13:38:30.990390 CS Dly: 1 (0~32)
6602 13:38:30.990493 ==
6603 13:38:30.993757 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 13:38:30.996910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 13:38:30.996997 ==
6606 13:38:31.003427 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 13:38:31.010287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6608 13:38:31.013428 [CA 0] Center 36 (8~64) winsize 57
6609 13:38:31.013516 [CA 1] Center 36 (8~64) winsize 57
6610 13:38:31.016629 [CA 2] Center 36 (8~64) winsize 57
6611 13:38:31.020366 [CA 3] Center 36 (8~64) winsize 57
6612 13:38:31.023386 [CA 4] Center 36 (8~64) winsize 57
6613 13:38:31.026368 [CA 5] Center 36 (8~64) winsize 57
6614 13:38:31.026482
6615 13:38:31.030065 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6616 13:38:31.030169
6617 13:38:31.036409 [CATrainingPosCal] consider 2 rank data
6618 13:38:31.036532 u2DelayCellTimex100 = 270/100 ps
6619 13:38:31.043204 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 13:38:31.046483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 13:38:31.049613 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 13:38:31.052639 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 13:38:31.055849 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:38:31.059767 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:38:31.059884
6626 13:38:31.063027 CA PerBit enable=1, Macro0, CA PI delay=36
6627 13:38:31.063134
6628 13:38:31.066239 [CBTSetCACLKResult] CA Dly = 36
6629 13:38:31.069600 CS Dly: 1 (0~32)
6630 13:38:31.069707
6631 13:38:31.072722 ----->DramcWriteLeveling(PI) begin...
6632 13:38:31.072826 ==
6633 13:38:31.075886 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 13:38:31.078969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 13:38:31.079079 ==
6636 13:38:31.082094 Write leveling (Byte 0): 40 => 8
6637 13:38:31.085377 Write leveling (Byte 1): 40 => 8
6638 13:38:31.089435 DramcWriteLeveling(PI) end<-----
6639 13:38:31.089551
6640 13:38:31.089650 ==
6641 13:38:31.092747 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 13:38:31.095844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 13:38:31.095922 ==
6644 13:38:31.099069 [Gating] SW mode calibration
6645 13:38:31.105458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 13:38:31.112110 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6647 13:38:31.115302 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 13:38:31.122086 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 13:38:31.125218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 13:38:31.128628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 13:38:31.135501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 13:38:31.138688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 13:38:31.141811 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 13:38:31.148359 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 13:38:31.151800 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 13:38:31.154695 Total UI for P1: 0, mck2ui 16
6657 13:38:31.157869 best dqsien dly found for B0: ( 0, 14, 24)
6658 13:38:31.161501 Total UI for P1: 0, mck2ui 16
6659 13:38:31.164645 best dqsien dly found for B1: ( 0, 14, 24)
6660 13:38:31.167825 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6661 13:38:31.171238 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6662 13:38:31.171347
6663 13:38:31.174469 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 13:38:31.177688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 13:38:31.180945 [Gating] SW calibration Done
6666 13:38:31.181054 ==
6667 13:38:31.184490 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 13:38:31.190860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 13:38:31.190996 ==
6670 13:38:31.191103 RX Vref Scan: 0
6671 13:38:31.191198
6672 13:38:31.194168 RX Vref 0 -> 0, step: 1
6673 13:38:31.194272
6674 13:38:31.197424 RX Delay -410 -> 252, step: 16
6675 13:38:31.200690 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6676 13:38:31.203994 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6677 13:38:31.210490 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6678 13:38:31.214172 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6679 13:38:31.217486 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6680 13:38:31.220737 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6681 13:38:31.227150 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6682 13:38:31.230155 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6683 13:38:31.234000 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6684 13:38:31.236999 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6685 13:38:31.243469 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6686 13:38:31.246637 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6687 13:38:31.250081 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6688 13:38:31.253211 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6689 13:38:31.259889 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6690 13:38:31.263439 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6691 13:38:31.263528 ==
6692 13:38:31.266439 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 13:38:31.269655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 13:38:31.269736 ==
6695 13:38:31.273092 DQS Delay:
6696 13:38:31.273173 DQS0 = 43, DQS1 = 51
6697 13:38:31.276731 DQM Delay:
6698 13:38:31.276812 DQM0 = 13, DQM1 = 13
6699 13:38:31.279928 DQ Delay:
6700 13:38:31.280004 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6701 13:38:31.283028 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6702 13:38:31.286384 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 13:38:31.289677 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6704 13:38:31.289773
6705 13:38:31.289839
6706 13:38:31.289900 ==
6707 13:38:31.293177 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 13:38:31.299604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 13:38:31.299717 ==
6710 13:38:31.299820
6711 13:38:31.299915
6712 13:38:31.300003 TX Vref Scan disable
6713 13:38:31.302868 == TX Byte 0 ==
6714 13:38:31.306118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 13:38:31.309152 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 13:38:31.312379 == TX Byte 1 ==
6717 13:38:31.316337 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 13:38:31.319441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 13:38:31.322596 ==
6720 13:38:31.325803 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:38:31.328977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:38:31.329060 ==
6723 13:38:31.329126
6724 13:38:31.329187
6725 13:38:31.332845 TX Vref Scan disable
6726 13:38:31.332932 == TX Byte 0 ==
6727 13:38:31.335463 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 13:38:31.341975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 13:38:31.342075 == TX Byte 1 ==
6730 13:38:31.345785 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 13:38:31.352213 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 13:38:31.352311
6733 13:38:31.352379 [DATLAT]
6734 13:38:31.352443 Freq=400, CH1 RK0
6735 13:38:31.352504
6736 13:38:31.355574 DATLAT Default: 0xf
6737 13:38:31.358639 0, 0xFFFF, sum = 0
6738 13:38:31.358729 1, 0xFFFF, sum = 0
6739 13:38:31.361874 2, 0xFFFF, sum = 0
6740 13:38:31.361962 3, 0xFFFF, sum = 0
6741 13:38:31.365472 4, 0xFFFF, sum = 0
6742 13:38:31.365561 5, 0xFFFF, sum = 0
6743 13:38:31.368666 6, 0xFFFF, sum = 0
6744 13:38:31.368756 7, 0xFFFF, sum = 0
6745 13:38:31.371703 8, 0xFFFF, sum = 0
6746 13:38:31.371796 9, 0xFFFF, sum = 0
6747 13:38:31.375452 10, 0xFFFF, sum = 0
6748 13:38:31.375545 11, 0xFFFF, sum = 0
6749 13:38:31.378754 12, 0xFFFF, sum = 0
6750 13:38:31.378841 13, 0x0, sum = 1
6751 13:38:31.381629 14, 0x0, sum = 2
6752 13:38:31.381716 15, 0x0, sum = 3
6753 13:38:31.384975 16, 0x0, sum = 4
6754 13:38:31.385064 best_step = 14
6755 13:38:31.385131
6756 13:38:31.385194 ==
6757 13:38:31.388176 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 13:38:31.395196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 13:38:31.395292 ==
6760 13:38:31.395362 RX Vref Scan: 1
6761 13:38:31.395425
6762 13:38:31.398400 RX Vref 0 -> 0, step: 1
6763 13:38:31.398487
6764 13:38:31.402274 RX Delay -343 -> 252, step: 8
6765 13:38:31.402363
6766 13:38:31.405147 Set Vref, RX VrefLevel [Byte0]: 53
6767 13:38:31.408398 [Byte1]: 51
6768 13:38:31.408479
6769 13:38:31.411705 Final RX Vref Byte 0 = 53 to rank0
6770 13:38:31.414746 Final RX Vref Byte 1 = 51 to rank0
6771 13:38:31.417975 Final RX Vref Byte 0 = 53 to rank1
6772 13:38:31.421107 Final RX Vref Byte 1 = 51 to rank1==
6773 13:38:31.424793 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 13:38:31.428210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 13:38:31.431524 ==
6776 13:38:31.431634 DQS Delay:
6777 13:38:31.431738 DQS0 = 44, DQS1 = 52
6778 13:38:31.434882 DQM Delay:
6779 13:38:31.434987 DQM0 = 10, DQM1 = 11
6780 13:38:31.438077 DQ Delay:
6781 13:38:31.441224 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6782 13:38:31.441326 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6783 13:38:31.444446 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6784 13:38:31.447639 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6785 13:38:31.447751
6786 13:38:31.451247
6787 13:38:31.457624 [DQSOSCAuto] RK0, (LSB)MR18= 0x6991, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6788 13:38:31.460897 CH1 RK0: MR19=C0C, MR18=6991
6789 13:38:31.467317 CH1_RK0: MR19=0xC0C, MR18=0x6991, DQSOSC=391, MR23=63, INC=386, DEC=257
6790 13:38:31.467408 ==
6791 13:38:31.470559 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 13:38:31.473664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 13:38:31.473758 ==
6794 13:38:31.477415 [Gating] SW mode calibration
6795 13:38:31.483943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6796 13:38:31.490257 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6797 13:38:31.493330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 13:38:31.497331 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 13:38:31.503533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 13:38:31.506748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 13:38:31.510666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 13:38:31.516894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 13:38:31.520544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 13:38:31.523190 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 13:38:31.530187 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 13:38:31.530292 Total UI for P1: 0, mck2ui 16
6807 13:38:31.536650 best dqsien dly found for B0: ( 0, 14, 24)
6808 13:38:31.536751 Total UI for P1: 0, mck2ui 16
6809 13:38:31.543232 best dqsien dly found for B1: ( 0, 14, 24)
6810 13:38:31.546355 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6811 13:38:31.549606 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6812 13:38:31.549735
6813 13:38:31.552774 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 13:38:31.556443 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 13:38:31.559445 [Gating] SW calibration Done
6816 13:38:31.559534 ==
6817 13:38:31.563190 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 13:38:31.566366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 13:38:31.566478 ==
6820 13:38:31.569579 RX Vref Scan: 0
6821 13:38:31.569662
6822 13:38:31.569728 RX Vref 0 -> 0, step: 1
6823 13:38:31.569789
6824 13:38:31.572800 RX Delay -410 -> 252, step: 16
6825 13:38:31.579667 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6826 13:38:31.582811 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6827 13:38:31.586192 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6828 13:38:31.589470 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6829 13:38:31.595902 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6830 13:38:31.598927 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6831 13:38:31.602325 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6832 13:38:31.605682 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6833 13:38:31.612339 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6834 13:38:31.615465 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6835 13:38:31.619332 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6836 13:38:31.625608 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6837 13:38:31.628839 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6838 13:38:31.632824 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6839 13:38:31.635274 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6840 13:38:31.641886 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6841 13:38:31.642000 ==
6842 13:38:31.645025 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 13:38:31.648929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 13:38:31.649017 ==
6845 13:38:31.649083 DQS Delay:
6846 13:38:31.651940 DQS0 = 43, DQS1 = 51
6847 13:38:31.652023 DQM Delay:
6848 13:38:31.655340 DQM0 = 8, DQM1 = 14
6849 13:38:31.655423 DQ Delay:
6850 13:38:31.658477 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6851 13:38:31.661877 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6852 13:38:31.664981 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6853 13:38:31.668515 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6854 13:38:31.668616
6855 13:38:31.668713
6856 13:38:31.668805 ==
6857 13:38:31.671366 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 13:38:31.675281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 13:38:31.675395 ==
6860 13:38:31.675489
6861 13:38:31.678468
6862 13:38:31.678545 TX Vref Scan disable
6863 13:38:31.681589 == TX Byte 0 ==
6864 13:38:31.684650 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6865 13:38:31.687762 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6866 13:38:31.691112 == TX Byte 1 ==
6867 13:38:31.695105 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6868 13:38:31.698269 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6869 13:38:31.698381 ==
6870 13:38:31.701460 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 13:38:31.704659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 13:38:31.708165 ==
6873 13:38:31.708285
6874 13:38:31.708383
6875 13:38:31.708480 TX Vref Scan disable
6876 13:38:31.711065 == TX Byte 0 ==
6877 13:38:31.714770 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6878 13:38:31.717783 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6879 13:38:31.720884 == TX Byte 1 ==
6880 13:38:31.724483 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6881 13:38:31.727740 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6882 13:38:31.727857
6883 13:38:31.727966 [DATLAT]
6884 13:38:31.730869 Freq=400, CH1 RK1
6885 13:38:31.730975
6886 13:38:31.733900 DATLAT Default: 0xe
6887 13:38:31.734019 0, 0xFFFF, sum = 0
6888 13:38:31.737648 1, 0xFFFF, sum = 0
6889 13:38:31.737732 2, 0xFFFF, sum = 0
6890 13:38:31.740858 3, 0xFFFF, sum = 0
6891 13:38:31.740965 4, 0xFFFF, sum = 0
6892 13:38:31.743774 5, 0xFFFF, sum = 0
6893 13:38:31.743855 6, 0xFFFF, sum = 0
6894 13:38:31.747731 7, 0xFFFF, sum = 0
6895 13:38:31.747825 8, 0xFFFF, sum = 0
6896 13:38:31.750940 9, 0xFFFF, sum = 0
6897 13:38:31.751027 10, 0xFFFF, sum = 0
6898 13:38:31.754083 11, 0xFFFF, sum = 0
6899 13:38:31.754171 12, 0xFFFF, sum = 0
6900 13:38:31.757484 13, 0x0, sum = 1
6901 13:38:31.757571 14, 0x0, sum = 2
6902 13:38:31.760823 15, 0x0, sum = 3
6903 13:38:31.760906 16, 0x0, sum = 4
6904 13:38:31.763966 best_step = 14
6905 13:38:31.764046
6906 13:38:31.764148 ==
6907 13:38:31.767215 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 13:38:31.770407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 13:38:31.770525 ==
6910 13:38:31.773588 RX Vref Scan: 0
6911 13:38:31.773670
6912 13:38:31.773754 RX Vref 0 -> 0, step: 1
6913 13:38:31.773834
6914 13:38:31.776583 RX Delay -343 -> 252, step: 8
6915 13:38:31.785191 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6916 13:38:31.788268 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6917 13:38:31.791760 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6918 13:38:31.795021 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6919 13:38:31.801604 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6920 13:38:31.804997 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6921 13:38:31.808116 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6922 13:38:31.814761 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6923 13:38:31.818593 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6924 13:38:31.821824 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6925 13:38:31.824847 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6926 13:38:31.831256 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6927 13:38:31.834753 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6928 13:38:31.837704 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6929 13:38:31.841127 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6930 13:38:31.848145 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6931 13:38:31.848282 ==
6932 13:38:31.851041 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 13:38:31.854571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 13:38:31.854689 ==
6935 13:38:31.854788 DQS Delay:
6936 13:38:31.857341 DQS0 = 48, DQS1 = 56
6937 13:38:31.857434 DQM Delay:
6938 13:38:31.860734 DQM0 = 10, DQM1 = 14
6939 13:38:31.860858 DQ Delay:
6940 13:38:31.864065 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6941 13:38:31.867367 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6942 13:38:31.871193 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6943 13:38:31.874463 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6944 13:38:31.874553
6945 13:38:31.874641
6946 13:38:31.883949 [DQSOSCAuto] RK1, (LSB)MR18= 0x82ba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 393 ps
6947 13:38:31.884050 CH1 RK1: MR19=C0C, MR18=82BA
6948 13:38:31.890322 CH1_RK1: MR19=0xC0C, MR18=0x82BA, DQSOSC=386, MR23=63, INC=396, DEC=264
6949 13:38:31.893587 [RxdqsGatingPostProcess] freq 400
6950 13:38:31.900292 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6951 13:38:31.903445 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 13:38:31.906777 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 13:38:31.910005 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 13:38:31.913289 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 13:38:31.916690 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 13:38:31.919914 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 13:38:31.923215 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 13:38:31.926631 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 13:38:31.926750 Pre-setting of DQS Precalculation
6960 13:38:31.933168 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6961 13:38:31.939475 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6962 13:38:31.946577 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6963 13:38:31.946699
6964 13:38:31.946783
6965 13:38:31.949845 [Calibration Summary] 800 Mbps
6966 13:38:31.953082 CH 0, Rank 0
6967 13:38:31.953199 SW Impedance : PASS
6968 13:38:31.955852 DUTY Scan : NO K
6969 13:38:31.959503 ZQ Calibration : PASS
6970 13:38:31.959606 Jitter Meter : NO K
6971 13:38:31.962453 CBT Training : PASS
6972 13:38:31.965709 Write leveling : PASS
6973 13:38:31.965833 RX DQS gating : PASS
6974 13:38:31.969068 RX DQ/DQS(RDDQC) : PASS
6975 13:38:31.972598 TX DQ/DQS : PASS
6976 13:38:31.972685 RX DATLAT : PASS
6977 13:38:31.975938 RX DQ/DQS(Engine): PASS
6978 13:38:31.979132 TX OE : NO K
6979 13:38:31.979223 All Pass.
6980 13:38:31.979291
6981 13:38:31.979354 CH 0, Rank 1
6982 13:38:31.982401 SW Impedance : PASS
6983 13:38:31.985911 DUTY Scan : NO K
6984 13:38:31.985997 ZQ Calibration : PASS
6985 13:38:31.988694 Jitter Meter : NO K
6986 13:38:31.992168 CBT Training : PASS
6987 13:38:31.992290 Write leveling : NO K
6988 13:38:31.995531 RX DQS gating : PASS
6989 13:38:31.995648 RX DQ/DQS(RDDQC) : PASS
6990 13:38:31.998651 TX DQ/DQS : PASS
6991 13:38:32.001830 RX DATLAT : PASS
6992 13:38:32.001943 RX DQ/DQS(Engine): PASS
6993 13:38:32.005581 TX OE : NO K
6994 13:38:32.005706 All Pass.
6995 13:38:32.005804
6996 13:38:32.008574 CH 1, Rank 0
6997 13:38:32.008686 SW Impedance : PASS
6998 13:38:32.012157 DUTY Scan : NO K
6999 13:38:32.015129 ZQ Calibration : PASS
7000 13:38:32.015248 Jitter Meter : NO K
7001 13:38:32.018347 CBT Training : PASS
7002 13:38:32.021692 Write leveling : PASS
7003 13:38:32.021809 RX DQS gating : PASS
7004 13:38:32.024877 RX DQ/DQS(RDDQC) : PASS
7005 13:38:32.028157 TX DQ/DQS : PASS
7006 13:38:32.028240 RX DATLAT : PASS
7007 13:38:32.031468 RX DQ/DQS(Engine): PASS
7008 13:38:32.035366 TX OE : NO K
7009 13:38:32.035453 All Pass.
7010 13:38:32.035521
7011 13:38:32.035582 CH 1, Rank 1
7012 13:38:32.038520 SW Impedance : PASS
7013 13:38:32.041775 DUTY Scan : NO K
7014 13:38:32.041890 ZQ Calibration : PASS
7015 13:38:32.045192 Jitter Meter : NO K
7016 13:38:32.048035 CBT Training : PASS
7017 13:38:32.048146 Write leveling : NO K
7018 13:38:32.052017 RX DQS gating : PASS
7019 13:38:32.055245 RX DQ/DQS(RDDQC) : PASS
7020 13:38:32.055358 TX DQ/DQS : PASS
7021 13:38:32.058328 RX DATLAT : PASS
7022 13:38:32.061595 RX DQ/DQS(Engine): PASS
7023 13:38:32.061701 TX OE : NO K
7024 13:38:32.061799 All Pass.
7025 13:38:32.064805
7026 13:38:32.064916 DramC Write-DBI off
7027 13:38:32.067950 PER_BANK_REFRESH: Hybrid Mode
7028 13:38:32.068069 TX_TRACKING: ON
7029 13:38:32.078244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7030 13:38:32.080886 [FAST_K] Save calibration result to emmc
7031 13:38:32.084801 dramc_set_vcore_voltage set vcore to 725000
7032 13:38:32.087495 Read voltage for 1600, 0
7033 13:38:32.087605 Vio18 = 0
7034 13:38:32.090855 Vcore = 725000
7035 13:38:32.090937 Vdram = 0
7036 13:38:32.091046 Vddq = 0
7037 13:38:32.094450 Vmddr = 0
7038 13:38:32.097807 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7039 13:38:32.104303 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7040 13:38:32.104420 MEM_TYPE=3, freq_sel=13
7041 13:38:32.107606 sv_algorithm_assistance_LP4_3733
7042 13:38:32.114116 ============ PULL DRAM RESETB DOWN ============
7043 13:38:32.117140 ========== PULL DRAM RESETB DOWN end =========
7044 13:38:32.120734 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7045 13:38:32.123795 ===================================
7046 13:38:32.127180 LPDDR4 DRAM CONFIGURATION
7047 13:38:32.130516 ===================================
7048 13:38:32.133771 EX_ROW_EN[0] = 0x0
7049 13:38:32.133883 EX_ROW_EN[1] = 0x0
7050 13:38:32.137046 LP4Y_EN = 0x0
7051 13:38:32.137153 WORK_FSP = 0x1
7052 13:38:32.140121 WL = 0x5
7053 13:38:32.140227 RL = 0x5
7054 13:38:32.143890 BL = 0x2
7055 13:38:32.143993 RPST = 0x0
7056 13:38:32.147326 RD_PRE = 0x0
7057 13:38:32.147429 WR_PRE = 0x1
7058 13:38:32.150354 WR_PST = 0x1
7059 13:38:32.150443 DBI_WR = 0x0
7060 13:38:32.153212 DBI_RD = 0x0
7061 13:38:32.153312 OTF = 0x1
7062 13:38:32.156558 ===================================
7063 13:38:32.159703 ===================================
7064 13:38:32.163504 ANA top config
7065 13:38:32.166718 ===================================
7066 13:38:32.170010 DLL_ASYNC_EN = 0
7067 13:38:32.170092 ALL_SLAVE_EN = 0
7068 13:38:32.173091 NEW_RANK_MODE = 1
7069 13:38:32.176814 DLL_IDLE_MODE = 1
7070 13:38:32.179609 LP45_APHY_COMB_EN = 1
7071 13:38:32.182804 TX_ODT_DIS = 0
7072 13:38:32.182896 NEW_8X_MODE = 1
7073 13:38:32.186370 ===================================
7074 13:38:32.189867 ===================================
7075 13:38:32.192849 data_rate = 3200
7076 13:38:32.196296 CKR = 1
7077 13:38:32.199632 DQ_P2S_RATIO = 8
7078 13:38:32.202649 ===================================
7079 13:38:32.205826 CA_P2S_RATIO = 8
7080 13:38:32.209027 DQ_CA_OPEN = 0
7081 13:38:32.209140 DQ_SEMI_OPEN = 0
7082 13:38:32.212290 CA_SEMI_OPEN = 0
7083 13:38:32.216061 CA_FULL_RATE = 0
7084 13:38:32.219382 DQ_CKDIV4_EN = 0
7085 13:38:32.222270 CA_CKDIV4_EN = 0
7086 13:38:32.225521 CA_PREDIV_EN = 0
7087 13:38:32.229347 PH8_DLY = 12
7088 13:38:32.229457 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7089 13:38:32.232636 DQ_AAMCK_DIV = 4
7090 13:38:32.235879 CA_AAMCK_DIV = 4
7091 13:38:32.239050 CA_ADMCK_DIV = 4
7092 13:38:32.242175 DQ_TRACK_CA_EN = 0
7093 13:38:32.245416 CA_PICK = 1600
7094 13:38:32.248708 CA_MCKIO = 1600
7095 13:38:32.248789 MCKIO_SEMI = 0
7096 13:38:32.251945 PLL_FREQ = 3068
7097 13:38:32.255209 DQ_UI_PI_RATIO = 32
7098 13:38:32.258788 CA_UI_PI_RATIO = 0
7099 13:38:32.261881 ===================================
7100 13:38:32.265124 ===================================
7101 13:38:32.268432 memory_type:LPDDR4
7102 13:38:32.268550 GP_NUM : 10
7103 13:38:32.271591 SRAM_EN : 1
7104 13:38:32.275350 MD32_EN : 0
7105 13:38:32.278604 ===================================
7106 13:38:32.278718 [ANA_INIT] >>>>>>>>>>>>>>
7107 13:38:32.281755 <<<<<< [CONFIGURE PHASE]: ANA_TX
7108 13:38:32.284876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7109 13:38:32.288514 ===================================
7110 13:38:32.291562 data_rate = 3200,PCW = 0X7600
7111 13:38:32.294648 ===================================
7112 13:38:32.298361 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7113 13:38:32.304859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 13:38:32.308068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 13:38:32.314459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7116 13:38:32.317931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7117 13:38:32.321253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7118 13:38:32.324381 [ANA_INIT] flow start
7119 13:38:32.324495 [ANA_INIT] PLL >>>>>>>>
7120 13:38:32.327655 [ANA_INIT] PLL <<<<<<<<
7121 13:38:32.330938 [ANA_INIT] MIDPI >>>>>>>>
7122 13:38:32.331046 [ANA_INIT] MIDPI <<<<<<<<
7123 13:38:32.334085 [ANA_INIT] DLL >>>>>>>>
7124 13:38:32.337730 [ANA_INIT] DLL <<<<<<<<
7125 13:38:32.337853 [ANA_INIT] flow end
7126 13:38:32.344343 ============ LP4 DIFF to SE enter ============
7127 13:38:32.347576 ============ LP4 DIFF to SE exit ============
7128 13:38:32.350677 [ANA_INIT] <<<<<<<<<<<<<
7129 13:38:32.354049 [Flow] Enable top DCM control >>>>>
7130 13:38:32.357362 [Flow] Enable top DCM control <<<<<
7131 13:38:32.357476 Enable DLL master slave shuffle
7132 13:38:32.363923 ==============================================================
7133 13:38:32.367059 Gating Mode config
7134 13:38:32.370849 ==============================================================
7135 13:38:32.373976 Config description:
7136 13:38:32.383460 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7137 13:38:32.390646 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7138 13:38:32.393844 SELPH_MODE 0: By rank 1: By Phase
7139 13:38:32.400280 ==============================================================
7140 13:38:32.403474 GAT_TRACK_EN = 1
7141 13:38:32.406626 RX_GATING_MODE = 2
7142 13:38:32.409705 RX_GATING_TRACK_MODE = 2
7143 13:38:32.412950 SELPH_MODE = 1
7144 13:38:32.416786 PICG_EARLY_EN = 1
7145 13:38:32.419816 VALID_LAT_VALUE = 1
7146 13:38:32.423252 ==============================================================
7147 13:38:32.426338 Enter into Gating configuration >>>>
7148 13:38:32.429367 Exit from Gating configuration <<<<
7149 13:38:32.433040 Enter into DVFS_PRE_config >>>>>
7150 13:38:32.446059 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7151 13:38:32.446225 Exit from DVFS_PRE_config <<<<<
7152 13:38:32.449067 Enter into PICG configuration >>>>
7153 13:38:32.452590 Exit from PICG configuration <<<<
7154 13:38:32.455735 [RX_INPUT] configuration >>>>>
7155 13:38:32.459480 [RX_INPUT] configuration <<<<<
7156 13:38:32.466086 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7157 13:38:32.469037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7158 13:38:32.475885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 13:38:32.482266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 13:38:32.489305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 13:38:32.496113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 13:38:32.499033 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7163 13:38:32.502377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7164 13:38:32.505543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7165 13:38:32.512281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7166 13:38:32.515548 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7167 13:38:32.518248 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 13:38:32.522282 ===================================
7169 13:38:32.525137 LPDDR4 DRAM CONFIGURATION
7170 13:38:32.528467 ===================================
7171 13:38:32.531476 EX_ROW_EN[0] = 0x0
7172 13:38:32.531590 EX_ROW_EN[1] = 0x0
7173 13:38:32.534810 LP4Y_EN = 0x0
7174 13:38:32.534923 WORK_FSP = 0x1
7175 13:38:32.537997 WL = 0x5
7176 13:38:32.538111 RL = 0x5
7177 13:38:32.541971 BL = 0x2
7178 13:38:32.542083 RPST = 0x0
7179 13:38:32.545039 RD_PRE = 0x0
7180 13:38:32.548227 WR_PRE = 0x1
7181 13:38:32.548342 WR_PST = 0x1
7182 13:38:32.551421 DBI_WR = 0x0
7183 13:38:32.551531 DBI_RD = 0x0
7184 13:38:32.554776 OTF = 0x1
7185 13:38:32.557803 ===================================
7186 13:38:32.561500 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7187 13:38:32.564364 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7188 13:38:32.567984 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 13:38:32.571119 ===================================
7190 13:38:32.574321 LPDDR4 DRAM CONFIGURATION
7191 13:38:32.577952 ===================================
7192 13:38:32.580945 EX_ROW_EN[0] = 0x10
7193 13:38:32.581051 EX_ROW_EN[1] = 0x0
7194 13:38:32.584041 LP4Y_EN = 0x0
7195 13:38:32.584122 WORK_FSP = 0x1
7196 13:38:32.587946 WL = 0x5
7197 13:38:32.588024 RL = 0x5
7198 13:38:32.591139 BL = 0x2
7199 13:38:32.594454 RPST = 0x0
7200 13:38:32.594540 RD_PRE = 0x0
7201 13:38:32.597515 WR_PRE = 0x1
7202 13:38:32.597594 WR_PST = 0x1
7203 13:38:32.600965 DBI_WR = 0x0
7204 13:38:32.601077 DBI_RD = 0x0
7205 13:38:32.604104 OTF = 0x1
7206 13:38:32.607337 ===================================
7207 13:38:32.613564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7208 13:38:32.613684 ==
7209 13:38:32.616975 Dram Type= 6, Freq= 0, CH_0, rank 0
7210 13:38:32.620636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7211 13:38:32.620751 ==
7212 13:38:32.623861 [Duty_Offset_Calibration]
7213 13:38:32.623976 B0:2 B1:0 CA:4
7214 13:38:32.624075
7215 13:38:32.627044 [DutyScan_Calibration_Flow] k_type=0
7216 13:38:32.636560
7217 13:38:32.636686 ==CLK 0==
7218 13:38:32.639707 Final CLK duty delay cell = -4
7219 13:38:32.642883 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7220 13:38:32.646691 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7221 13:38:32.649945 [-4] AVG Duty = 4922%(X100)
7222 13:38:32.650025
7223 13:38:32.653080 CH0 CLK Duty spec in!! Max-Min= 218%
7224 13:38:32.656362 [DutyScan_Calibration_Flow] ====Done====
7225 13:38:32.656438
7226 13:38:32.659692 [DutyScan_Calibration_Flow] k_type=1
7227 13:38:32.676791
7228 13:38:32.676921 ==DQS 0 ==
7229 13:38:32.680108 Final DQS duty delay cell = 0
7230 13:38:32.683249 [0] MAX Duty = 5218%(X100), DQS PI = 38
7231 13:38:32.686415 [0] MIN Duty = 5093%(X100), DQS PI = 12
7232 13:38:32.689883 [0] AVG Duty = 5155%(X100)
7233 13:38:32.689967
7234 13:38:32.690034 ==DQS 1 ==
7235 13:38:32.693526 Final DQS duty delay cell = 0
7236 13:38:32.696530 [0] MAX Duty = 5156%(X100), DQS PI = 2
7237 13:38:32.699785 [0] MIN Duty = 4969%(X100), DQS PI = 10
7238 13:38:32.703164 [0] AVG Duty = 5062%(X100)
7239 13:38:32.703274
7240 13:38:32.706735 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7241 13:38:32.706847
7242 13:38:32.709886 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7243 13:38:32.713295 [DutyScan_Calibration_Flow] ====Done====
7244 13:38:32.713409
7245 13:38:32.716266 [DutyScan_Calibration_Flow] k_type=3
7246 13:38:32.733717
7247 13:38:32.733832 ==DQM 0 ==
7248 13:38:32.737383 Final DQM duty delay cell = 0
7249 13:38:32.740226 [0] MAX Duty = 5124%(X100), DQS PI = 22
7250 13:38:32.743560 [0] MIN Duty = 4875%(X100), DQS PI = 54
7251 13:38:32.746755 [0] AVG Duty = 4999%(X100)
7252 13:38:32.746834
7253 13:38:32.746898 ==DQM 1 ==
7254 13:38:32.750029 Final DQM duty delay cell = 0
7255 13:38:32.753813 [0] MAX Duty = 5000%(X100), DQS PI = 2
7256 13:38:32.757111 [0] MIN Duty = 4844%(X100), DQS PI = 16
7257 13:38:32.760446 [0] AVG Duty = 4922%(X100)
7258 13:38:32.760531
7259 13:38:32.763732 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7260 13:38:32.763833
7261 13:38:32.766897 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7262 13:38:32.770092 [DutyScan_Calibration_Flow] ====Done====
7263 13:38:32.770178
7264 13:38:32.773402 [DutyScan_Calibration_Flow] k_type=2
7265 13:38:32.791277
7266 13:38:32.791383 ==DQ 0 ==
7267 13:38:32.794586 Final DQ duty delay cell = 0
7268 13:38:32.797806 [0] MAX Duty = 5124%(X100), DQS PI = 20
7269 13:38:32.800797 [0] MIN Duty = 4938%(X100), DQS PI = 12
7270 13:38:32.804029 [0] AVG Duty = 5031%(X100)
7271 13:38:32.804115
7272 13:38:32.804183 ==DQ 1 ==
7273 13:38:32.807453 Final DQ duty delay cell = 0
7274 13:38:32.810949 [0] MAX Duty = 5187%(X100), DQS PI = 2
7275 13:38:32.814134 [0] MIN Duty = 4907%(X100), DQS PI = 32
7276 13:38:32.814249 [0] AVG Duty = 5047%(X100)
7277 13:38:32.817495
7278 13:38:32.820779 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7279 13:38:32.820864
7280 13:38:32.823915 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7281 13:38:32.827055 [DutyScan_Calibration_Flow] ====Done====
7282 13:38:32.827140 ==
7283 13:38:32.830354 Dram Type= 6, Freq= 0, CH_1, rank 0
7284 13:38:32.833565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 13:38:32.833654 ==
7286 13:38:32.837197 [Duty_Offset_Calibration]
7287 13:38:32.837291 B0:0 B1:-1 CA:3
7288 13:38:32.837360
7289 13:38:32.840079 [DutyScan_Calibration_Flow] k_type=0
7290 13:38:32.851128
7291 13:38:32.851229 ==CLK 0==
7292 13:38:32.854733 Final CLK duty delay cell = 0
7293 13:38:32.857578 [0] MAX Duty = 5187%(X100), DQS PI = 4
7294 13:38:32.861169 [0] MIN Duty = 5000%(X100), DQS PI = 54
7295 13:38:32.864309 [0] AVG Duty = 5093%(X100)
7296 13:38:32.864423
7297 13:38:32.867494 CH1 CLK Duty spec in!! Max-Min= 187%
7298 13:38:32.871350 [DutyScan_Calibration_Flow] ====Done====
7299 13:38:32.871460
7300 13:38:32.874462 [DutyScan_Calibration_Flow] k_type=1
7301 13:38:32.889841
7302 13:38:32.890002 ==DQS 0 ==
7303 13:38:32.893268 Final DQS duty delay cell = 0
7304 13:38:32.896707 [0] MAX Duty = 5250%(X100), DQS PI = 30
7305 13:38:32.899808 [0] MIN Duty = 4907%(X100), DQS PI = 40
7306 13:38:32.903147 [0] AVG Duty = 5078%(X100)
7307 13:38:32.903237
7308 13:38:32.903302 ==DQS 1 ==
7309 13:38:32.906413 Final DQS duty delay cell = -4
7310 13:38:32.909453 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7311 13:38:32.913095 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7312 13:38:32.916019 [-4] AVG Duty = 4906%(X100)
7313 13:38:32.916123
7314 13:38:32.919442 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7315 13:38:32.919549
7316 13:38:32.923217 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7317 13:38:32.926480 [DutyScan_Calibration_Flow] ====Done====
7318 13:38:32.926565
7319 13:38:32.929652 [DutyScan_Calibration_Flow] k_type=3
7320 13:38:32.947916
7321 13:38:32.948030 ==DQM 0 ==
7322 13:38:32.950522 Final DQM duty delay cell = 0
7323 13:38:32.953674 [0] MAX Duty = 5031%(X100), DQS PI = 32
7324 13:38:32.957302 [0] MIN Duty = 4750%(X100), DQS PI = 40
7325 13:38:32.960295 [0] AVG Duty = 4890%(X100)
7326 13:38:32.960407
7327 13:38:32.960503 ==DQM 1 ==
7328 13:38:32.964080 Final DQM duty delay cell = 0
7329 13:38:32.967194 [0] MAX Duty = 5000%(X100), DQS PI = 32
7330 13:38:32.970252 [0] MIN Duty = 4813%(X100), DQS PI = 0
7331 13:38:32.973802 [0] AVG Duty = 4906%(X100)
7332 13:38:32.973908
7333 13:38:32.976877 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7334 13:38:32.976988
7335 13:38:32.980139 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7336 13:38:32.983399 [DutyScan_Calibration_Flow] ====Done====
7337 13:38:32.983517
7338 13:38:32.986694 [DutyScan_Calibration_Flow] k_type=2
7339 13:38:33.003049
7340 13:38:33.003199 ==DQ 0 ==
7341 13:38:33.006575 Final DQ duty delay cell = -4
7342 13:38:33.010184 [-4] MAX Duty = 4938%(X100), DQS PI = 32
7343 13:38:33.013239 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7344 13:38:33.016448 [-4] AVG Duty = 4875%(X100)
7345 13:38:33.016565
7346 13:38:33.016665 ==DQ 1 ==
7347 13:38:33.019910 Final DQ duty delay cell = 0
7348 13:38:33.022839 [0] MAX Duty = 5031%(X100), DQS PI = 32
7349 13:38:33.026803 [0] MIN Duty = 4844%(X100), DQS PI = 58
7350 13:38:33.029610 [0] AVG Duty = 4937%(X100)
7351 13:38:33.029721
7352 13:38:33.032866 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7353 13:38:33.032980
7354 13:38:33.036056 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7355 13:38:33.039842 [DutyScan_Calibration_Flow] ====Done====
7356 13:38:33.043382 nWR fixed to 30
7357 13:38:33.046353 [ModeRegInit_LP4] CH0 RK0
7358 13:38:33.046463 [ModeRegInit_LP4] CH0 RK1
7359 13:38:33.049553 [ModeRegInit_LP4] CH1 RK0
7360 13:38:33.052763 [ModeRegInit_LP4] CH1 RK1
7361 13:38:33.052887 match AC timing 5
7362 13:38:33.059056 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7363 13:38:33.062591 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7364 13:38:33.066194 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7365 13:38:33.072598 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7366 13:38:33.075797 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7367 13:38:33.075907 [MiockJmeterHQA]
7368 13:38:33.079521
7369 13:38:33.079630 [DramcMiockJmeter] u1RxGatingPI = 0
7370 13:38:33.082565 0 : 4365, 4138
7371 13:38:33.082675 4 : 4252, 4027
7372 13:38:33.085631 8 : 4365, 4140
7373 13:38:33.085742 12 : 4252, 4027
7374 13:38:33.088891 16 : 4252, 4027
7375 13:38:33.089000 20 : 4363, 4137
7376 13:38:33.092299 24 : 4255, 4030
7377 13:38:33.092409 28 : 4363, 4137
7378 13:38:33.092509 32 : 4253, 4026
7379 13:38:33.095399 36 : 4252, 4027
7380 13:38:33.095512 40 : 4363, 4137
7381 13:38:33.098622 44 : 4257, 4029
7382 13:38:33.098735 48 : 4363, 4137
7383 13:38:33.102424 52 : 4253, 4027
7384 13:38:33.102535 56 : 4250, 4027
7385 13:38:33.105627 60 : 4252, 4029
7386 13:38:33.105741 64 : 4363, 4137
7387 13:38:33.105839 68 : 4250, 4027
7388 13:38:33.108602 72 : 4363, 4140
7389 13:38:33.108720 76 : 4252, 4030
7390 13:38:33.112007 80 : 4363, 4140
7391 13:38:33.112117 84 : 4250, 4026
7392 13:38:33.115479 88 : 4252, 4029
7393 13:38:33.115605 92 : 4361, 4137
7394 13:38:33.118397 96 : 4250, 2215
7395 13:38:33.118510 100 : 4360, 0
7396 13:38:33.118618 104 : 4250, 0
7397 13:38:33.121907 108 : 4361, 0
7398 13:38:33.122024 112 : 4250, 0
7399 13:38:33.124945 116 : 4253, 0
7400 13:38:33.125059 120 : 4252, 0
7401 13:38:33.125156 124 : 4361, 0
7402 13:38:33.128696 128 : 4250, 0
7403 13:38:33.128807 132 : 4250, 0
7404 13:38:33.131861 136 : 4250, 0
7405 13:38:33.131970 140 : 4252, 0
7406 13:38:33.132072 144 : 4360, 0
7407 13:38:33.134865 148 : 4250, 0
7408 13:38:33.134991 152 : 4249, 0
7409 13:38:33.135089 156 : 4257, 0
7410 13:38:33.138586 160 : 4361, 0
7411 13:38:33.138701 164 : 4250, 0
7412 13:38:33.141817 168 : 4250, 0
7413 13:38:33.141932 172 : 4252, 0
7414 13:38:33.142034 176 : 4361, 0
7415 13:38:33.144566 180 : 4249, 0
7416 13:38:33.144677 184 : 4253, 0
7417 13:38:33.148512 188 : 4250, 0
7418 13:38:33.148621 192 : 4254, 0
7419 13:38:33.148719 196 : 4360, 0
7420 13:38:33.151298 200 : 4250, 0
7421 13:38:33.151409 204 : 4249, 0
7422 13:38:33.155000 208 : 4250, 0
7423 13:38:33.155115 212 : 4361, 0
7424 13:38:33.155214 216 : 4250, 0
7425 13:38:33.158157 220 : 4250, 907
7426 13:38:33.158271 224 : 4250, 4026
7427 13:38:33.161418 228 : 4363, 4140
7428 13:38:33.161533 232 : 4361, 4137
7429 13:38:33.164553 236 : 4247, 4025
7430 13:38:33.164666 240 : 4250, 4027
7431 13:38:33.168241 244 : 4363, 4140
7432 13:38:33.168352 248 : 4361, 4137
7433 13:38:33.171276 252 : 4250, 4027
7434 13:38:33.171386 256 : 4249, 4027
7435 13:38:33.174464 260 : 4250, 4026
7436 13:38:33.174576 264 : 4250, 4026
7437 13:38:33.174675 268 : 4252, 4030
7438 13:38:33.177734 272 : 4250, 4026
7439 13:38:33.177843 276 : 4252, 4029
7440 13:38:33.180954 280 : 4361, 4137
7441 13:38:33.181064 284 : 4255, 4029
7442 13:38:33.184178 288 : 4250, 4027
7443 13:38:33.184294 292 : 4255, 4029
7444 13:38:33.187880 296 : 4363, 4140
7445 13:38:33.187991 300 : 4363, 4137
7446 13:38:33.190911 304 : 4250, 4027
7447 13:38:33.191024 308 : 4363, 4140
7448 13:38:33.194148 312 : 4252, 4029
7449 13:38:33.194264 316 : 4250, 4026
7450 13:38:33.197370 320 : 4252, 4029
7451 13:38:33.197478 324 : 4252, 4029
7452 13:38:33.200628 328 : 4252, 4029
7453 13:38:33.200741 332 : 4361, 3638
7454 13:38:33.200838 336 : 4255, 1168
7455 13:38:33.203828
7456 13:38:33.203939 MIOCK jitter meter ch=0
7457 13:38:33.204035
7458 13:38:33.207760 1T = (336-100) = 236 dly cells
7459 13:38:33.214113 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7460 13:38:33.214224 ==
7461 13:38:33.217188 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 13:38:33.220527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7463 13:38:33.220637 ==
7464 13:38:33.227387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7465 13:38:33.230447 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7466 13:38:33.234152 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7467 13:38:33.240629 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7468 13:38:33.250141 [CA 0] Center 43 (13~74) winsize 62
7469 13:38:33.253278 [CA 1] Center 42 (12~73) winsize 62
7470 13:38:33.256424 [CA 2] Center 37 (8~67) winsize 60
7471 13:38:33.259816 [CA 3] Center 37 (7~67) winsize 61
7472 13:38:33.262888 [CA 4] Center 36 (6~66) winsize 61
7473 13:38:33.266268 [CA 5] Center 35 (5~66) winsize 62
7474 13:38:33.266381
7475 13:38:33.269395 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7476 13:38:33.269509
7477 13:38:33.276257 [CATrainingPosCal] consider 1 rank data
7478 13:38:33.276373 u2DelayCellTimex100 = 275/100 ps
7479 13:38:33.283166 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7480 13:38:33.286189 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7481 13:38:33.289587 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7482 13:38:33.292765 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7483 13:38:33.296090 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7484 13:38:33.299474 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7485 13:38:33.299586
7486 13:38:33.302670 CA PerBit enable=1, Macro0, CA PI delay=35
7487 13:38:33.302784
7488 13:38:33.305729 [CBTSetCACLKResult] CA Dly = 35
7489 13:38:33.308989 CS Dly: 10 (0~41)
7490 13:38:33.312256 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7491 13:38:33.315533 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7492 13:38:33.315613 ==
7493 13:38:33.319310 Dram Type= 6, Freq= 0, CH_0, rank 1
7494 13:38:33.325932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 13:38:33.326017 ==
7496 13:38:33.328545 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 13:38:33.335677 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 13:38:33.338819 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 13:38:33.345265 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 13:38:33.353331 [CA 0] Center 44 (14~75) winsize 62
7501 13:38:33.356714 [CA 1] Center 44 (14~74) winsize 61
7502 13:38:33.359608 [CA 2] Center 39 (10~69) winsize 60
7503 13:38:33.363190 [CA 3] Center 39 (10~68) winsize 59
7504 13:38:33.366318 [CA 4] Center 37 (7~67) winsize 61
7505 13:38:33.370032 [CA 5] Center 36 (7~66) winsize 60
7506 13:38:33.370109
7507 13:38:33.373187 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 13:38:33.373273
7509 13:38:33.379528 [CATrainingPosCal] consider 2 rank data
7510 13:38:33.379614 u2DelayCellTimex100 = 275/100 ps
7511 13:38:33.386605 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7512 13:38:33.389619 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7513 13:38:33.392797 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7514 13:38:33.396097 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7515 13:38:33.399346 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 13:38:33.402665 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 13:38:33.402770
7518 13:38:33.406195 CA PerBit enable=1, Macro0, CA PI delay=36
7519 13:38:33.406300
7520 13:38:33.409214 [CBTSetCACLKResult] CA Dly = 36
7521 13:38:33.412540 CS Dly: 11 (0~44)
7522 13:38:33.416309 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 13:38:33.419622 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 13:38:33.419707
7525 13:38:33.422829 ----->DramcWriteLeveling(PI) begin...
7526 13:38:33.426100 ==
7527 13:38:33.429221 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 13:38:33.432413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 13:38:33.432524 ==
7530 13:38:33.435586 Write leveling (Byte 0): 34 => 34
7531 13:38:33.438840 Write leveling (Byte 1): 28 => 28
7532 13:38:33.442331 DramcWriteLeveling(PI) end<-----
7533 13:38:33.442413
7534 13:38:33.442478 ==
7535 13:38:33.445215 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 13:38:33.448705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 13:38:33.448812 ==
7538 13:38:33.452144 [Gating] SW mode calibration
7539 13:38:33.458515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7540 13:38:33.465298 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7541 13:38:33.468789 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 13:38:33.472247 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 13:38:33.478561 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 13:38:33.482098 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7545 13:38:33.485195 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7546 13:38:33.492066 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7547 13:38:33.495198 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 13:38:33.498311 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 13:38:33.504694 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 13:38:33.508081 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7551 13:38:33.511130 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7552 13:38:33.518227 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7553 13:38:33.521450 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7554 13:38:33.524411 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
7555 13:38:33.531033 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7556 13:38:33.534755 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 13:38:33.538105 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 13:38:33.544612 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 13:38:33.547731 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7560 13:38:33.550852 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7561 13:38:33.557642 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7562 13:38:33.560827 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7563 13:38:33.564763 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 13:38:33.570810 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 13:38:33.573884 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 13:38:33.577004 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 13:38:33.583856 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 13:38:33.587417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 13:38:33.590300 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 13:38:33.597365 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 13:38:33.600524 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 13:38:33.603693 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:38:33.610027 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 13:38:33.613214 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 13:38:33.616670 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 13:38:33.623632 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 13:38:33.626751 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 13:38:33.630109 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:38:33.636621 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:38:33.639867 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:38:33.643202 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:38:33.650356 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 13:38:33.653492 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 13:38:33.656823 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 13:38:33.663196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 13:38:33.663308 Total UI for P1: 0, mck2ui 16
7587 13:38:33.669405 best dqsien dly found for B0: ( 1, 9, 10)
7588 13:38:33.672800 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 13:38:33.676624 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 13:38:33.679740 Total UI for P1: 0, mck2ui 16
7591 13:38:33.682708 best dqsien dly found for B1: ( 1, 9, 18)
7592 13:38:33.686456 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7593 13:38:33.689711 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7594 13:38:33.689825
7595 13:38:33.696057 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7596 13:38:33.699034 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7597 13:38:33.702476 [Gating] SW calibration Done
7598 13:38:33.702591 ==
7599 13:38:33.705770 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 13:38:33.709135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 13:38:33.709252 ==
7602 13:38:33.709357 RX Vref Scan: 0
7603 13:38:33.712214
7604 13:38:33.712322 RX Vref 0 -> 0, step: 1
7605 13:38:33.712417
7606 13:38:33.715638 RX Delay 0 -> 252, step: 8
7607 13:38:33.719058 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7608 13:38:33.722348 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7609 13:38:33.728819 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7610 13:38:33.732040 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7611 13:38:33.735543 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7612 13:38:33.738766 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7613 13:38:33.741830 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7614 13:38:33.748905 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7615 13:38:33.752133 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7616 13:38:33.755448 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7617 13:38:33.758672 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7618 13:38:33.761849 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7619 13:38:33.768843 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7620 13:38:33.771935 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7621 13:38:33.775158 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7622 13:38:33.778434 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7623 13:38:33.778545 ==
7624 13:38:33.781643 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 13:38:33.787829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 13:38:33.787942 ==
7627 13:38:33.788037 DQS Delay:
7628 13:38:33.791061 DQS0 = 0, DQS1 = 0
7629 13:38:33.791168 DQM Delay:
7630 13:38:33.795020 DQM0 = 131, DQM1 = 125
7631 13:38:33.795112 DQ Delay:
7632 13:38:33.798151 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7633 13:38:33.801458 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7634 13:38:33.804676 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7635 13:38:33.807921 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7636 13:38:33.808027
7637 13:38:33.808120
7638 13:38:33.808222 ==
7639 13:38:33.811067 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 13:38:33.817639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 13:38:33.817741 ==
7642 13:38:33.817809
7643 13:38:33.817871
7644 13:38:33.820886 TX Vref Scan disable
7645 13:38:33.820990 == TX Byte 0 ==
7646 13:38:33.823817 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7647 13:38:33.830837 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7648 13:38:33.830956 == TX Byte 1 ==
7649 13:38:33.833705 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7650 13:38:33.840826 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7651 13:38:33.840949 ==
7652 13:38:33.843846 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 13:38:33.847417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 13:38:33.847528 ==
7655 13:38:33.860842
7656 13:38:33.864138 TX Vref early break, caculate TX vref
7657 13:38:33.867247 TX Vref=16, minBit 1, minWin=22, winSum=369
7658 13:38:33.870420 TX Vref=18, minBit 8, minWin=22, winSum=380
7659 13:38:33.873685 TX Vref=20, minBit 7, minWin=23, winSum=389
7660 13:38:33.876892 TX Vref=22, minBit 1, minWin=23, winSum=398
7661 13:38:33.880730 TX Vref=24, minBit 7, minWin=24, winSum=412
7662 13:38:33.887028 TX Vref=26, minBit 8, minWin=24, winSum=416
7663 13:38:33.890331 TX Vref=28, minBit 1, minWin=25, winSum=424
7664 13:38:33.893469 TX Vref=30, minBit 2, minWin=25, winSum=419
7665 13:38:33.896656 TX Vref=32, minBit 0, minWin=25, winSum=408
7666 13:38:33.900087 TX Vref=34, minBit 0, minWin=24, winSum=400
7667 13:38:33.906318 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 28
7668 13:38:33.906482
7669 13:38:33.910161 Final TX Range 0 Vref 28
7670 13:38:33.910284
7671 13:38:33.910383 ==
7672 13:38:33.912957 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 13:38:33.916731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 13:38:33.916863 ==
7675 13:38:33.916960
7676 13:38:33.917050
7677 13:38:33.919916 TX Vref Scan disable
7678 13:38:33.926345 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7679 13:38:33.926495 == TX Byte 0 ==
7680 13:38:33.930050 u2DelayCellOfst[0]=14 cells (4 PI)
7681 13:38:33.933038 u2DelayCellOfst[1]=17 cells (5 PI)
7682 13:38:33.936475 u2DelayCellOfst[2]=14 cells (4 PI)
7683 13:38:33.939207 u2DelayCellOfst[3]=14 cells (4 PI)
7684 13:38:33.942980 u2DelayCellOfst[4]=10 cells (3 PI)
7685 13:38:33.945989 u2DelayCellOfst[5]=0 cells (0 PI)
7686 13:38:33.949293 u2DelayCellOfst[6]=17 cells (5 PI)
7687 13:38:33.952793 u2DelayCellOfst[7]=17 cells (5 PI)
7688 13:38:33.956045 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7689 13:38:33.958878 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7690 13:38:33.962462 == TX Byte 1 ==
7691 13:38:33.965549 u2DelayCellOfst[8]=0 cells (0 PI)
7692 13:38:33.968811 u2DelayCellOfst[9]=0 cells (0 PI)
7693 13:38:33.972546 u2DelayCellOfst[10]=7 cells (2 PI)
7694 13:38:33.975758 u2DelayCellOfst[11]=3 cells (1 PI)
7695 13:38:33.979005 u2DelayCellOfst[12]=10 cells (3 PI)
7696 13:38:33.981999 u2DelayCellOfst[13]=10 cells (3 PI)
7697 13:38:33.985235 u2DelayCellOfst[14]=14 cells (4 PI)
7698 13:38:33.985364 u2DelayCellOfst[15]=10 cells (3 PI)
7699 13:38:33.991768 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7700 13:38:33.995522 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7701 13:38:33.998507 DramC Write-DBI on
7702 13:38:33.998589 ==
7703 13:38:34.001675 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 13:38:34.005405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 13:38:34.005502 ==
7706 13:38:34.005583
7707 13:38:34.005647
7708 13:38:34.008694 TX Vref Scan disable
7709 13:38:34.008771 == TX Byte 0 ==
7710 13:38:34.015320 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7711 13:38:34.015401 == TX Byte 1 ==
7712 13:38:34.021655 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7713 13:38:34.021738 DramC Write-DBI off
7714 13:38:34.021803
7715 13:38:34.021864 [DATLAT]
7716 13:38:34.024697 Freq=1600, CH0 RK0
7717 13:38:34.024771
7718 13:38:34.028446 DATLAT Default: 0xf
7719 13:38:34.028551 0, 0xFFFF, sum = 0
7720 13:38:34.031608 1, 0xFFFF, sum = 0
7721 13:38:34.031685 2, 0xFFFF, sum = 0
7722 13:38:34.034796 3, 0xFFFF, sum = 0
7723 13:38:34.034908 4, 0xFFFF, sum = 0
7724 13:38:34.037999 5, 0xFFFF, sum = 0
7725 13:38:34.038080 6, 0xFFFF, sum = 0
7726 13:38:34.041154 7, 0xFFFF, sum = 0
7727 13:38:34.041274 8, 0xFFFF, sum = 0
7728 13:38:34.044236 9, 0xFFFF, sum = 0
7729 13:38:34.044337 10, 0xFFFF, sum = 0
7730 13:38:34.048009 11, 0xFFFF, sum = 0
7731 13:38:34.048090 12, 0xFFFF, sum = 0
7732 13:38:34.051177 13, 0xFFFF, sum = 0
7733 13:38:34.051256 14, 0x0, sum = 1
7734 13:38:34.054547 15, 0x0, sum = 2
7735 13:38:34.054633 16, 0x0, sum = 3
7736 13:38:34.057708 17, 0x0, sum = 4
7737 13:38:34.057789 best_step = 15
7738 13:38:34.057855
7739 13:38:34.057916 ==
7740 13:38:34.061103 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 13:38:34.067518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 13:38:34.067632 ==
7743 13:38:34.067730 RX Vref Scan: 1
7744 13:38:34.067821
7745 13:38:34.070995 Set Vref Range= 24 -> 127
7746 13:38:34.071086
7747 13:38:34.074403 RX Vref 24 -> 127, step: 1
7748 13:38:34.074485
7749 13:38:34.077393 RX Delay 11 -> 252, step: 4
7750 13:38:34.077469
7751 13:38:34.080961 Set Vref, RX VrefLevel [Byte0]: 24
7752 13:38:34.084033 [Byte1]: 24
7753 13:38:34.084120
7754 13:38:34.087257 Set Vref, RX VrefLevel [Byte0]: 25
7755 13:38:34.091070 [Byte1]: 25
7756 13:38:34.091187
7757 13:38:34.094181 Set Vref, RX VrefLevel [Byte0]: 26
7758 13:38:34.097484 [Byte1]: 26
7759 13:38:34.100727
7760 13:38:34.100807 Set Vref, RX VrefLevel [Byte0]: 27
7761 13:38:34.103952 [Byte1]: 27
7762 13:38:34.108220
7763 13:38:34.108325 Set Vref, RX VrefLevel [Byte0]: 28
7764 13:38:34.111236 [Byte1]: 28
7765 13:38:34.115937
7766 13:38:34.116044 Set Vref, RX VrefLevel [Byte0]: 29
7767 13:38:34.119170 [Byte1]: 29
7768 13:38:34.123605
7769 13:38:34.123718 Set Vref, RX VrefLevel [Byte0]: 30
7770 13:38:34.126774 [Byte1]: 30
7771 13:38:34.131387
7772 13:38:34.131480 Set Vref, RX VrefLevel [Byte0]: 31
7773 13:38:34.134550 [Byte1]: 31
7774 13:38:34.138421
7775 13:38:34.138505 Set Vref, RX VrefLevel [Byte0]: 32
7776 13:38:34.142158 [Byte1]: 32
7777 13:38:34.146632
7778 13:38:34.146721 Set Vref, RX VrefLevel [Byte0]: 33
7779 13:38:34.149613 [Byte1]: 33
7780 13:38:34.154102
7781 13:38:34.154186 Set Vref, RX VrefLevel [Byte0]: 34
7782 13:38:34.157404 [Byte1]: 34
7783 13:38:34.161685
7784 13:38:34.161768 Set Vref, RX VrefLevel [Byte0]: 35
7785 13:38:34.164858 [Byte1]: 35
7786 13:38:34.169342
7787 13:38:34.169455 Set Vref, RX VrefLevel [Byte0]: 36
7788 13:38:34.172578 [Byte1]: 36
7789 13:38:34.176524
7790 13:38:34.176606 Set Vref, RX VrefLevel [Byte0]: 37
7791 13:38:34.180384 [Byte1]: 37
7792 13:38:34.184489
7793 13:38:34.184567 Set Vref, RX VrefLevel [Byte0]: 38
7794 13:38:34.187608 [Byte1]: 38
7795 13:38:34.191793
7796 13:38:34.191879 Set Vref, RX VrefLevel [Byte0]: 39
7797 13:38:34.195243 [Byte1]: 39
7798 13:38:34.199687
7799 13:38:34.199784 Set Vref, RX VrefLevel [Byte0]: 40
7800 13:38:34.203099 [Byte1]: 40
7801 13:38:34.206976
7802 13:38:34.207057 Set Vref, RX VrefLevel [Byte0]: 41
7803 13:38:34.210795 [Byte1]: 41
7804 13:38:34.214588
7805 13:38:34.214670 Set Vref, RX VrefLevel [Byte0]: 42
7806 13:38:34.218204 [Byte1]: 42
7807 13:38:34.222492
7808 13:38:34.222581 Set Vref, RX VrefLevel [Byte0]: 43
7809 13:38:34.225743 [Byte1]: 43
7810 13:38:34.230230
7811 13:38:34.230341 Set Vref, RX VrefLevel [Byte0]: 44
7812 13:38:34.233558 [Byte1]: 44
7813 13:38:34.237853
7814 13:38:34.237959 Set Vref, RX VrefLevel [Byte0]: 45
7815 13:38:34.241171 [Byte1]: 45
7816 13:38:34.245082
7817 13:38:34.245191 Set Vref, RX VrefLevel [Byte0]: 46
7818 13:38:34.248261 [Byte1]: 46
7819 13:38:34.252598
7820 13:38:34.252679 Set Vref, RX VrefLevel [Byte0]: 47
7821 13:38:34.256279 [Byte1]: 47
7822 13:38:34.260248
7823 13:38:34.260334 Set Vref, RX VrefLevel [Byte0]: 48
7824 13:38:34.263472 [Byte1]: 48
7825 13:38:34.267799
7826 13:38:34.267885 Set Vref, RX VrefLevel [Byte0]: 49
7827 13:38:34.271485 [Byte1]: 49
7828 13:38:34.275663
7829 13:38:34.275743 Set Vref, RX VrefLevel [Byte0]: 50
7830 13:38:34.279127 [Byte1]: 50
7831 13:38:34.283477
7832 13:38:34.283564 Set Vref, RX VrefLevel [Byte0]: 51
7833 13:38:34.286607 [Byte1]: 51
7834 13:38:34.291172
7835 13:38:34.291252 Set Vref, RX VrefLevel [Byte0]: 52
7836 13:38:34.294462 [Byte1]: 52
7837 13:38:34.298855
7838 13:38:34.298942 Set Vref, RX VrefLevel [Byte0]: 53
7839 13:38:34.302034 [Byte1]: 53
7840 13:38:34.306445
7841 13:38:34.306529 Set Vref, RX VrefLevel [Byte0]: 54
7842 13:38:34.309550 [Byte1]: 54
7843 13:38:34.313687
7844 13:38:34.313780 Set Vref, RX VrefLevel [Byte0]: 55
7845 13:38:34.317095 [Byte1]: 55
7846 13:38:34.321449
7847 13:38:34.321530 Set Vref, RX VrefLevel [Byte0]: 56
7848 13:38:34.324843 [Byte1]: 56
7849 13:38:34.328850
7850 13:38:34.328932 Set Vref, RX VrefLevel [Byte0]: 57
7851 13:38:34.332243 [Byte1]: 57
7852 13:38:34.336256
7853 13:38:34.336374 Set Vref, RX VrefLevel [Byte0]: 58
7854 13:38:34.340049 [Byte1]: 58
7855 13:38:34.344050
7856 13:38:34.344138 Set Vref, RX VrefLevel [Byte0]: 59
7857 13:38:34.347290 [Byte1]: 59
7858 13:38:34.351949
7859 13:38:34.352039 Set Vref, RX VrefLevel [Byte0]: 60
7860 13:38:34.355066 [Byte1]: 60
7861 13:38:34.359377
7862 13:38:34.359473 Set Vref, RX VrefLevel [Byte0]: 61
7863 13:38:34.362599 [Byte1]: 61
7864 13:38:34.367148
7865 13:38:34.367243 Set Vref, RX VrefLevel [Byte0]: 62
7866 13:38:34.370148 [Byte1]: 62
7867 13:38:34.374548
7868 13:38:34.374640 Set Vref, RX VrefLevel [Byte0]: 63
7869 13:38:34.377768 [Byte1]: 63
7870 13:38:34.382253
7871 13:38:34.382384 Set Vref, RX VrefLevel [Byte0]: 64
7872 13:38:34.385530 [Byte1]: 64
7873 13:38:34.390186
7874 13:38:34.390278 Set Vref, RX VrefLevel [Byte0]: 65
7875 13:38:34.393402 [Byte1]: 65
7876 13:38:34.397801
7877 13:38:34.397936 Set Vref, RX VrefLevel [Byte0]: 66
7878 13:38:34.400893 [Byte1]: 66
7879 13:38:34.404728
7880 13:38:34.404847 Set Vref, RX VrefLevel [Byte0]: 67
7881 13:38:34.408585 [Byte1]: 67
7882 13:38:34.412514
7883 13:38:34.412650 Set Vref, RX VrefLevel [Byte0]: 68
7884 13:38:34.416292 [Byte1]: 68
7885 13:38:34.420002
7886 13:38:34.420119 Set Vref, RX VrefLevel [Byte0]: 69
7887 13:38:34.423611 [Byte1]: 69
7888 13:38:34.427812
7889 13:38:34.427943 Set Vref, RX VrefLevel [Byte0]: 70
7890 13:38:34.430961 [Byte1]: 70
7891 13:38:34.435711
7892 13:38:34.435834 Set Vref, RX VrefLevel [Byte0]: 71
7893 13:38:34.438716 [Byte1]: 71
7894 13:38:34.443499
7895 13:38:34.443603 Set Vref, RX VrefLevel [Byte0]: 72
7896 13:38:34.446380 [Byte1]: 72
7897 13:38:34.450717
7898 13:38:34.450808 Set Vref, RX VrefLevel [Byte0]: 73
7899 13:38:34.454324 [Byte1]: 73
7900 13:38:34.458796
7901 13:38:34.458883 Set Vref, RX VrefLevel [Byte0]: 74
7902 13:38:34.461417 [Byte1]: 74
7903 13:38:34.465752
7904 13:38:34.465832 Set Vref, RX VrefLevel [Byte0]: 75
7905 13:38:34.469610 [Byte1]: 75
7906 13:38:34.473443
7907 13:38:34.473527 Final RX Vref Byte 0 = 56 to rank0
7908 13:38:34.477179 Final RX Vref Byte 1 = 61 to rank0
7909 13:38:34.480372 Final RX Vref Byte 0 = 56 to rank1
7910 13:38:34.483537 Final RX Vref Byte 1 = 61 to rank1==
7911 13:38:34.486752 Dram Type= 6, Freq= 0, CH_0, rank 0
7912 13:38:34.493248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7913 13:38:34.493347 ==
7914 13:38:34.493415 DQS Delay:
7915 13:38:34.496348 DQS0 = 0, DQS1 = 0
7916 13:38:34.496431 DQM Delay:
7917 13:38:34.496496 DQM0 = 128, DQM1 = 124
7918 13:38:34.500173 DQ Delay:
7919 13:38:34.503294 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7920 13:38:34.506349 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7921 13:38:34.509698 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7922 13:38:34.513516 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7923 13:38:34.513606
7924 13:38:34.513674
7925 13:38:34.513736
7926 13:38:34.516842 [DramC_TX_OE_Calibration] TA2
7927 13:38:34.520273 Original DQ_B0 (3 6) =30, OEN = 27
7928 13:38:34.523588 Original DQ_B1 (3 6) =30, OEN = 27
7929 13:38:34.526787 24, 0x0, End_B0=24 End_B1=24
7930 13:38:34.526908 25, 0x0, End_B0=25 End_B1=25
7931 13:38:34.529932 26, 0x0, End_B0=26 End_B1=26
7932 13:38:34.533018 27, 0x0, End_B0=27 End_B1=27
7933 13:38:34.536263 28, 0x0, End_B0=28 End_B1=28
7934 13:38:34.539771 29, 0x0, End_B0=29 End_B1=29
7935 13:38:34.539926 30, 0x0, End_B0=30 End_B1=30
7936 13:38:34.542886 31, 0x4141, End_B0=30 End_B1=30
7937 13:38:34.546240 Byte0 end_step=30 best_step=27
7938 13:38:34.549893 Byte1 end_step=30 best_step=27
7939 13:38:34.553098 Byte0 TX OE(2T, 0.5T) = (3, 3)
7940 13:38:34.556378 Byte1 TX OE(2T, 0.5T) = (3, 3)
7941 13:38:34.556513
7942 13:38:34.556613
7943 13:38:34.562865 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
7944 13:38:34.566404 CH0 RK0: MR19=303, MR18=1B18
7945 13:38:34.573088 CH0_RK0: MR19=0x303, MR18=0x1B18, DQSOSC=396, MR23=63, INC=23, DEC=15
7946 13:38:34.573239
7947 13:38:34.576221 ----->DramcWriteLeveling(PI) begin...
7948 13:38:34.576316 ==
7949 13:38:34.579453 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 13:38:34.582533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 13:38:34.582635 ==
7952 13:38:34.586106 Write leveling (Byte 0): 33 => 33
7953 13:38:34.589382 Write leveling (Byte 1): 27 => 27
7954 13:38:34.592866 DramcWriteLeveling(PI) end<-----
7955 13:38:34.592972
7956 13:38:34.593043 ==
7957 13:38:34.595881 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 13:38:34.599205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 13:38:34.602907 ==
7960 13:38:34.602995 [Gating] SW mode calibration
7961 13:38:34.612194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7962 13:38:34.615447 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7963 13:38:34.618692 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 13:38:34.625177 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 13:38:34.628314 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7966 13:38:34.631588 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7967 13:38:34.638568 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7968 13:38:34.641717 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7969 13:38:34.644817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7970 13:38:34.651844 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7971 13:38:34.655139 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 13:38:34.658200 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 13:38:34.664525 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7974 13:38:34.668386 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7975 13:38:34.671538 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7976 13:38:34.677951 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7977 13:38:34.681361 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 13:38:34.684389 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 13:38:34.691091 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 13:38:34.694791 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7981 13:38:34.697725 1 6 8 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7982 13:38:34.704859 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7983 13:38:34.707993 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7984 13:38:34.711263 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7985 13:38:34.717509 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 13:38:34.720812 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 13:38:34.723931 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 13:38:34.731015 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 13:38:34.734314 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7990 13:38:34.737339 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7991 13:38:34.744259 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7992 13:38:34.747375 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7993 13:38:34.750445 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 13:38:34.757360 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 13:38:34.760475 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 13:38:34.763765 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 13:38:34.770150 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 13:38:34.773879 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 13:38:34.776897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 13:38:34.783500 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 13:38:34.786570 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 13:38:34.790387 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 13:38:34.796563 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 13:38:34.800249 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8005 13:38:34.803196 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8006 13:38:34.810054 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8007 13:38:34.813461 Total UI for P1: 0, mck2ui 16
8008 13:38:34.816648 best dqsien dly found for B0: ( 1, 9, 6)
8009 13:38:34.820196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8010 13:38:34.823547 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 13:38:34.826878 Total UI for P1: 0, mck2ui 16
8012 13:38:34.830187 best dqsien dly found for B1: ( 1, 9, 16)
8013 13:38:34.833567 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8014 13:38:34.836216 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8015 13:38:34.836377
8016 13:38:34.842716 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8017 13:38:34.846549 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8018 13:38:34.849787 [Gating] SW calibration Done
8019 13:38:34.849958 ==
8020 13:38:34.853025 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 13:38:34.856078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 13:38:34.856234 ==
8023 13:38:34.856348 RX Vref Scan: 0
8024 13:38:34.859600
8025 13:38:34.859745 RX Vref 0 -> 0, step: 1
8026 13:38:34.859861
8027 13:38:34.862962 RX Delay 0 -> 252, step: 8
8028 13:38:34.866063 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8029 13:38:34.869146 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8030 13:38:34.876300 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8031 13:38:34.879485 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8032 13:38:34.882527 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8033 13:38:34.885865 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8034 13:38:34.889064 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8035 13:38:34.895430 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8036 13:38:34.898678 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8037 13:38:34.902505 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8038 13:38:34.905297 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8039 13:38:34.908779 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8040 13:38:34.915421 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8041 13:38:34.918555 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8042 13:38:34.921670 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8043 13:38:34.925489 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8044 13:38:34.928732 ==
8045 13:38:34.931884 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 13:38:34.935187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 13:38:34.935266 ==
8048 13:38:34.935331 DQS Delay:
8049 13:38:34.938308 DQS0 = 0, DQS1 = 0
8050 13:38:34.938382 DQM Delay:
8051 13:38:34.941619 DQM0 = 132, DQM1 = 124
8052 13:38:34.941694 DQ Delay:
8053 13:38:34.944907 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8054 13:38:34.948106 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8055 13:38:34.951300 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8056 13:38:34.954532 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8057 13:38:34.954605
8058 13:38:34.954667
8059 13:38:34.957739 ==
8060 13:38:34.957814 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 13:38:34.964589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 13:38:34.964687 ==
8063 13:38:34.964756
8064 13:38:34.964818
8065 13:38:34.967626 TX Vref Scan disable
8066 13:38:34.967706 == TX Byte 0 ==
8067 13:38:34.971526 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8068 13:38:34.977786 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8069 13:38:34.977888 == TX Byte 1 ==
8070 13:38:34.984132 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8071 13:38:34.987214 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8072 13:38:34.987328 ==
8073 13:38:34.990583 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 13:38:34.993842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 13:38:34.993949 ==
8076 13:38:35.008097
8077 13:38:35.010968 TX Vref early break, caculate TX vref
8078 13:38:35.014690 TX Vref=16, minBit 9, minWin=22, winSum=382
8079 13:38:35.017925 TX Vref=18, minBit 1, minWin=24, winSum=394
8080 13:38:35.021012 TX Vref=20, minBit 7, minWin=24, winSum=399
8081 13:38:35.024783 TX Vref=22, minBit 1, minWin=25, winSum=409
8082 13:38:35.027466 TX Vref=24, minBit 1, minWin=25, winSum=414
8083 13:38:35.034576 TX Vref=26, minBit 1, minWin=25, winSum=419
8084 13:38:35.037567 TX Vref=28, minBit 1, minWin=25, winSum=424
8085 13:38:35.040699 TX Vref=30, minBit 1, minWin=25, winSum=416
8086 13:38:35.043920 TX Vref=32, minBit 0, minWin=24, winSum=409
8087 13:38:35.047072 TX Vref=34, minBit 0, minWin=24, winSum=397
8088 13:38:35.054281 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 28
8089 13:38:35.054371
8090 13:38:35.057412 Final TX Range 0 Vref 28
8091 13:38:35.057498
8092 13:38:35.057566 ==
8093 13:38:35.060546 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 13:38:35.063729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 13:38:35.063815 ==
8096 13:38:35.063882
8097 13:38:35.063943
8098 13:38:35.067591 TX Vref Scan disable
8099 13:38:35.073739 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8100 13:38:35.073846 == TX Byte 0 ==
8101 13:38:35.077405 u2DelayCellOfst[0]=14 cells (4 PI)
8102 13:38:35.080567 u2DelayCellOfst[1]=17 cells (5 PI)
8103 13:38:35.083802 u2DelayCellOfst[2]=10 cells (3 PI)
8104 13:38:35.086988 u2DelayCellOfst[3]=10 cells (3 PI)
8105 13:38:35.090245 u2DelayCellOfst[4]=7 cells (2 PI)
8106 13:38:35.094182 u2DelayCellOfst[5]=0 cells (0 PI)
8107 13:38:35.097139 u2DelayCellOfst[6]=17 cells (5 PI)
8108 13:38:35.100251 u2DelayCellOfst[7]=17 cells (5 PI)
8109 13:38:35.103495 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8110 13:38:35.107303 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8111 13:38:35.110493 == TX Byte 1 ==
8112 13:38:35.113213 u2DelayCellOfst[8]=0 cells (0 PI)
8113 13:38:35.116846 u2DelayCellOfst[9]=0 cells (0 PI)
8114 13:38:35.116957 u2DelayCellOfst[10]=7 cells (2 PI)
8115 13:38:35.120034 u2DelayCellOfst[11]=0 cells (0 PI)
8116 13:38:35.123839 u2DelayCellOfst[12]=7 cells (2 PI)
8117 13:38:35.126484 u2DelayCellOfst[13]=10 cells (3 PI)
8118 13:38:35.129743 u2DelayCellOfst[14]=14 cells (4 PI)
8119 13:38:35.133524 u2DelayCellOfst[15]=10 cells (3 PI)
8120 13:38:35.139690 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8121 13:38:35.143286 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8122 13:38:35.143370 DramC Write-DBI on
8123 13:38:35.143436 ==
8124 13:38:35.146671 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 13:38:35.152915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 13:38:35.153008 ==
8127 13:38:35.153077
8128 13:38:35.153140
8129 13:38:35.156186 TX Vref Scan disable
8130 13:38:35.156272 == TX Byte 0 ==
8131 13:38:35.163194 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8132 13:38:35.163283 == TX Byte 1 ==
8133 13:38:35.166253 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8134 13:38:35.169699 DramC Write-DBI off
8135 13:38:35.169784
8136 13:38:35.169851 [DATLAT]
8137 13:38:35.172574 Freq=1600, CH0 RK1
8138 13:38:35.172656
8139 13:38:35.172755 DATLAT Default: 0xf
8140 13:38:35.175809 0, 0xFFFF, sum = 0
8141 13:38:35.175908 1, 0xFFFF, sum = 0
8142 13:38:35.179438 2, 0xFFFF, sum = 0
8143 13:38:35.179522 3, 0xFFFF, sum = 0
8144 13:38:35.182581 4, 0xFFFF, sum = 0
8145 13:38:35.182719 5, 0xFFFF, sum = 0
8146 13:38:35.185766 6, 0xFFFF, sum = 0
8147 13:38:35.185858 7, 0xFFFF, sum = 0
8148 13:38:35.189423 8, 0xFFFF, sum = 0
8149 13:38:35.192897 9, 0xFFFF, sum = 0
8150 13:38:35.193021 10, 0xFFFF, sum = 0
8151 13:38:35.195904 11, 0xFFFF, sum = 0
8152 13:38:35.196017 12, 0xFFFF, sum = 0
8153 13:38:35.199283 13, 0xFFFF, sum = 0
8154 13:38:35.199410 14, 0x0, sum = 1
8155 13:38:35.202523 15, 0x0, sum = 2
8156 13:38:35.202648 16, 0x0, sum = 3
8157 13:38:35.205539 17, 0x0, sum = 4
8158 13:38:35.205637 best_step = 15
8159 13:38:35.205700
8160 13:38:35.205759 ==
8161 13:38:35.208744 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 13:38:35.211942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 13:38:35.215125 ==
8164 13:38:35.215220 RX Vref Scan: 0
8165 13:38:35.215286
8166 13:38:35.218987 RX Vref 0 -> 0, step: 1
8167 13:38:35.219107
8168 13:38:35.222114 RX Delay 11 -> 252, step: 4
8169 13:38:35.225057 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8170 13:38:35.228329 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8171 13:38:35.231503 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8172 13:38:35.238726 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8173 13:38:35.242042 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8174 13:38:35.245454 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8175 13:38:35.248458 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8176 13:38:35.251846 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8177 13:38:35.258173 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8178 13:38:35.261823 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8179 13:38:35.265002 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8180 13:38:35.267960 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8181 13:38:35.271217 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8182 13:38:35.278156 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8183 13:38:35.281419 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8184 13:38:35.284429 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8185 13:38:35.284523 ==
8186 13:38:35.288325 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 13:38:35.291225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 13:38:35.294562 ==
8189 13:38:35.294704 DQS Delay:
8190 13:38:35.294784 DQS0 = 0, DQS1 = 0
8191 13:38:35.297671 DQM Delay:
8192 13:38:35.297834 DQM0 = 129, DQM1 = 123
8193 13:38:35.300930 DQ Delay:
8194 13:38:35.304451 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8195 13:38:35.307420 DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =134
8196 13:38:35.311040 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8197 13:38:35.314219 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8198 13:38:35.314320
8199 13:38:35.314400
8200 13:38:35.314491
8201 13:38:35.317565 [DramC_TX_OE_Calibration] TA2
8202 13:38:35.320851 Original DQ_B0 (3 6) =30, OEN = 27
8203 13:38:35.324081 Original DQ_B1 (3 6) =30, OEN = 27
8204 13:38:35.327201 24, 0x0, End_B0=24 End_B1=24
8205 13:38:35.327288 25, 0x0, End_B0=25 End_B1=25
8206 13:38:35.330862 26, 0x0, End_B0=26 End_B1=26
8207 13:38:35.334087 27, 0x0, End_B0=27 End_B1=27
8208 13:38:35.337255 28, 0x0, End_B0=28 End_B1=28
8209 13:38:35.340499 29, 0x0, End_B0=29 End_B1=29
8210 13:38:35.340619 30, 0x0, End_B0=30 End_B1=30
8211 13:38:35.343901 31, 0x4141, End_B0=30 End_B1=30
8212 13:38:35.346993 Byte0 end_step=30 best_step=27
8213 13:38:35.350324 Byte1 end_step=30 best_step=27
8214 13:38:35.353499 Byte0 TX OE(2T, 0.5T) = (3, 3)
8215 13:38:35.357100 Byte1 TX OE(2T, 0.5T) = (3, 3)
8216 13:38:35.357229
8217 13:38:35.357344
8218 13:38:35.363412 [DQSOSCAuto] RK1, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8219 13:38:35.367182 CH0 RK1: MR19=303, MR18=1614
8220 13:38:35.373318 CH0_RK1: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8221 13:38:35.376981 [RxdqsGatingPostProcess] freq 1600
8222 13:38:35.379863 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8223 13:38:35.383151 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 13:38:35.386876 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 13:38:35.390003 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 13:38:35.393200 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 13:38:35.396436 best DQS0 dly(2T, 0.5T) = (1, 1)
8228 13:38:35.400267 best DQS1 dly(2T, 0.5T) = (1, 1)
8229 13:38:35.403063 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8230 13:38:35.406258 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8231 13:38:35.409424 Pre-setting of DQS Precalculation
8232 13:38:35.412710 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8233 13:38:35.412818 ==
8234 13:38:35.416316 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 13:38:35.422745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 13:38:35.422885 ==
8237 13:38:35.425958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8238 13:38:35.432435 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8239 13:38:35.436074 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8240 13:38:35.442339 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8241 13:38:35.450760 [CA 0] Center 42 (12~72) winsize 61
8242 13:38:35.454080 [CA 1] Center 42 (12~72) winsize 61
8243 13:38:35.457307 [CA 2] Center 38 (9~68) winsize 60
8244 13:38:35.460559 [CA 3] Center 37 (8~67) winsize 60
8245 13:38:35.463756 [CA 4] Center 38 (8~69) winsize 62
8246 13:38:35.466850 [CA 5] Center 37 (8~67) winsize 60
8247 13:38:35.466967
8248 13:38:35.470536 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8249 13:38:35.470651
8250 13:38:35.473717 [CATrainingPosCal] consider 1 rank data
8251 13:38:35.477075 u2DelayCellTimex100 = 275/100 ps
8252 13:38:35.480439 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8253 13:38:35.487211 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8254 13:38:35.490160 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8255 13:38:35.493203 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8256 13:38:35.496864 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8257 13:38:35.500193 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8258 13:38:35.500309
8259 13:38:35.503325 CA PerBit enable=1, Macro0, CA PI delay=37
8260 13:38:35.503433
8261 13:38:35.506839 [CBTSetCACLKResult] CA Dly = 37
8262 13:38:35.509716 CS Dly: 8 (0~39)
8263 13:38:35.512927 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8264 13:38:35.516848 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8265 13:38:35.516953 ==
8266 13:38:35.519915 Dram Type= 6, Freq= 0, CH_1, rank 1
8267 13:38:35.526363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 13:38:35.526456 ==
8269 13:38:35.529603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8270 13:38:35.536143 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8271 13:38:35.539104 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8272 13:38:35.545844 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8273 13:38:35.553635 [CA 0] Center 42 (12~72) winsize 61
8274 13:38:35.556841 [CA 1] Center 42 (13~72) winsize 60
8275 13:38:35.560112 [CA 2] Center 38 (8~68) winsize 61
8276 13:38:35.563329 [CA 3] Center 37 (7~67) winsize 61
8277 13:38:35.566400 [CA 4] Center 38 (8~68) winsize 61
8278 13:38:35.570328 [CA 5] Center 37 (7~67) winsize 61
8279 13:38:35.570404
8280 13:38:35.573398 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8281 13:38:35.573472
8282 13:38:35.579580 [CATrainingPosCal] consider 2 rank data
8283 13:38:35.579669 u2DelayCellTimex100 = 275/100 ps
8284 13:38:35.586706 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8285 13:38:35.589950 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8286 13:38:35.593063 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8287 13:38:35.596452 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8288 13:38:35.599579 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8289 13:38:35.602733 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8290 13:38:35.602809
8291 13:38:35.606373 CA PerBit enable=1, Macro0, CA PI delay=37
8292 13:38:35.606455
8293 13:38:35.609432 [CBTSetCACLKResult] CA Dly = 37
8294 13:38:35.613104 CS Dly: 9 (0~42)
8295 13:38:35.616175 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8296 13:38:35.619520 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8297 13:38:35.619599
8298 13:38:35.622557 ----->DramcWriteLeveling(PI) begin...
8299 13:38:35.622636 ==
8300 13:38:35.625938 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 13:38:35.632434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 13:38:35.632525 ==
8303 13:38:35.635671 Write leveling (Byte 0): 23 => 23
8304 13:38:35.638850 Write leveling (Byte 1): 25 => 25
8305 13:38:35.638933 DramcWriteLeveling(PI) end<-----
8306 13:38:35.642591
8307 13:38:35.642675 ==
8308 13:38:35.645820 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 13:38:35.649025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 13:38:35.649111 ==
8311 13:38:35.651982 [Gating] SW mode calibration
8312 13:38:35.659084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8313 13:38:35.665824 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8314 13:38:35.668567 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 13:38:35.671715 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 13:38:35.678814 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 13:38:35.681650 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8318 13:38:35.685343 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8319 13:38:35.691659 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 13:38:35.694940 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 13:38:35.698109 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 13:38:35.705050 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 13:38:35.708352 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 13:38:35.711554 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8325 13:38:35.718448 1 5 12 | B1->B0 | 2929 2424 | 0 0 | (1 0) (0 0)
8326 13:38:35.721528 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8327 13:38:35.724666 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 13:38:35.731136 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 13:38:35.734213 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 13:38:35.737693 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 13:38:35.744681 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 13:38:35.747923 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8333 13:38:35.751363 1 6 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8334 13:38:35.757611 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 13:38:35.761008 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 13:38:35.764529 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 13:38:35.770954 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 13:38:35.774037 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 13:38:35.777412 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 13:38:35.783746 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 13:38:35.787451 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8342 13:38:35.790433 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 13:38:35.797007 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:38:35.800884 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:38:35.803533 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 13:38:35.810524 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 13:38:35.813911 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 13:38:35.817068 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 13:38:35.823957 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 13:38:35.826621 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 13:38:35.829857 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 13:38:35.837053 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 13:38:35.840166 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 13:38:35.843745 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 13:38:35.850051 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 13:38:35.853361 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8357 13:38:35.856810 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8358 13:38:35.860019 Total UI for P1: 0, mck2ui 16
8359 13:38:35.862906 best dqsien dly found for B0: ( 1, 9, 8)
8360 13:38:35.869951 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8361 13:38:35.873103 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 13:38:35.876285 Total UI for P1: 0, mck2ui 16
8363 13:38:35.879541 best dqsien dly found for B1: ( 1, 9, 14)
8364 13:38:35.883132 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8365 13:38:35.885873 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8366 13:38:35.885981
8367 13:38:35.889072 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8368 13:38:35.892411 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8369 13:38:35.896214 [Gating] SW calibration Done
8370 13:38:35.896357 ==
8371 13:38:35.898788 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 13:38:35.902493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 13:38:35.905546 ==
8374 13:38:35.905641 RX Vref Scan: 0
8375 13:38:35.905707
8376 13:38:35.909025 RX Vref 0 -> 0, step: 1
8377 13:38:35.909131
8378 13:38:35.912451 RX Delay 0 -> 252, step: 8
8379 13:38:35.915656 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8380 13:38:35.918785 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8381 13:38:35.921879 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8382 13:38:35.925576 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8383 13:38:35.932183 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8384 13:38:35.935365 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8385 13:38:35.938408 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8386 13:38:35.941636 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8387 13:38:35.945395 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8388 13:38:35.951996 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8389 13:38:35.954979 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8390 13:38:35.958857 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8391 13:38:35.961719 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8392 13:38:35.964942 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8393 13:38:35.971531 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8394 13:38:35.974808 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8395 13:38:35.974914 ==
8396 13:38:35.978308 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 13:38:35.981606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 13:38:35.981688 ==
8399 13:38:35.984760 DQS Delay:
8400 13:38:35.984832 DQS0 = 0, DQS1 = 0
8401 13:38:35.988058 DQM Delay:
8402 13:38:35.988126 DQM0 = 135, DQM1 = 131
8403 13:38:35.988188 DQ Delay:
8404 13:38:35.991242 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8405 13:38:35.997844 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8406 13:38:36.001055 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8407 13:38:36.004279 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8408 13:38:36.004358
8409 13:38:36.004430
8410 13:38:36.004497 ==
8411 13:38:36.007572 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 13:38:36.011315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 13:38:36.011391 ==
8414 13:38:36.011453
8415 13:38:36.011511
8416 13:38:36.014245 TX Vref Scan disable
8417 13:38:36.017290 == TX Byte 0 ==
8418 13:38:36.021002 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8419 13:38:36.024104 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8420 13:38:36.027601 == TX Byte 1 ==
8421 13:38:36.030776 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8422 13:38:36.034025 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8423 13:38:36.034103 ==
8424 13:38:36.037209 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 13:38:36.044203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 13:38:36.044284 ==
8427 13:38:36.055261
8428 13:38:36.058326 TX Vref early break, caculate TX vref
8429 13:38:36.062273 TX Vref=16, minBit 8, minWin=21, winSum=369
8430 13:38:36.065552 TX Vref=18, minBit 8, minWin=22, winSum=377
8431 13:38:36.068649 TX Vref=20, minBit 8, minWin=23, winSum=390
8432 13:38:36.071854 TX Vref=22, minBit 8, minWin=23, winSum=401
8433 13:38:36.074983 TX Vref=24, minBit 3, minWin=25, winSum=411
8434 13:38:36.081644 TX Vref=26, minBit 1, minWin=25, winSum=416
8435 13:38:36.084966 TX Vref=28, minBit 9, minWin=25, winSum=420
8436 13:38:36.088223 TX Vref=30, minBit 0, minWin=25, winSum=417
8437 13:38:36.091869 TX Vref=32, minBit 0, minWin=25, winSum=410
8438 13:38:36.094788 TX Vref=34, minBit 9, minWin=23, winSum=397
8439 13:38:36.101395 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8440 13:38:36.101478
8441 13:38:36.104629 Final TX Range 0 Vref 28
8442 13:38:36.104712
8443 13:38:36.104773 ==
8444 13:38:36.108418 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 13:38:36.111509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 13:38:36.111611 ==
8447 13:38:36.111724
8448 13:38:36.111813
8449 13:38:36.115017 TX Vref Scan disable
8450 13:38:36.121244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8451 13:38:36.121360 == TX Byte 0 ==
8452 13:38:36.124311 u2DelayCellOfst[0]=10 cells (3 PI)
8453 13:38:36.127598 u2DelayCellOfst[1]=7 cells (2 PI)
8454 13:38:36.131149 u2DelayCellOfst[2]=0 cells (0 PI)
8455 13:38:36.134359 u2DelayCellOfst[3]=3 cells (1 PI)
8456 13:38:36.137878 u2DelayCellOfst[4]=7 cells (2 PI)
8457 13:38:36.140854 u2DelayCellOfst[5]=14 cells (4 PI)
8458 13:38:36.144037 u2DelayCellOfst[6]=14 cells (4 PI)
8459 13:38:36.147249 u2DelayCellOfst[7]=3 cells (1 PI)
8460 13:38:36.150452 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8461 13:38:36.153779 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 13:38:36.157513 == TX Byte 1 ==
8463 13:38:36.160741 u2DelayCellOfst[8]=0 cells (0 PI)
8464 13:38:36.163993 u2DelayCellOfst[9]=7 cells (2 PI)
8465 13:38:36.167202 u2DelayCellOfst[10]=14 cells (4 PI)
8466 13:38:36.167273 u2DelayCellOfst[11]=7 cells (2 PI)
8467 13:38:36.170314 u2DelayCellOfst[12]=17 cells (5 PI)
8468 13:38:36.173618 u2DelayCellOfst[13]=17 cells (5 PI)
8469 13:38:36.177339 u2DelayCellOfst[14]=17 cells (5 PI)
8470 13:38:36.180632 u2DelayCellOfst[15]=17 cells (5 PI)
8471 13:38:36.187213 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8472 13:38:36.190299 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8473 13:38:36.190375 DramC Write-DBI on
8474 13:38:36.193265 ==
8475 13:38:36.196852 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 13:38:36.200303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 13:38:36.200390 ==
8478 13:38:36.200461
8479 13:38:36.200522
8480 13:38:36.203431 TX Vref Scan disable
8481 13:38:36.203507 == TX Byte 0 ==
8482 13:38:36.209984 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8483 13:38:36.210066 == TX Byte 1 ==
8484 13:38:36.213197 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8485 13:38:36.216550 DramC Write-DBI off
8486 13:38:36.216625
8487 13:38:36.216692 [DATLAT]
8488 13:38:36.219956 Freq=1600, CH1 RK0
8489 13:38:36.220033
8490 13:38:36.220097 DATLAT Default: 0xf
8491 13:38:36.223395 0, 0xFFFF, sum = 0
8492 13:38:36.223477 1, 0xFFFF, sum = 0
8493 13:38:36.226563 2, 0xFFFF, sum = 0
8494 13:38:36.226680 3, 0xFFFF, sum = 0
8495 13:38:36.229644 4, 0xFFFF, sum = 0
8496 13:38:36.229736 5, 0xFFFF, sum = 0
8497 13:38:36.232905 6, 0xFFFF, sum = 0
8498 13:38:36.236544 7, 0xFFFF, sum = 0
8499 13:38:36.236649 8, 0xFFFF, sum = 0
8500 13:38:36.239837 9, 0xFFFF, sum = 0
8501 13:38:36.239943 10, 0xFFFF, sum = 0
8502 13:38:36.242989 11, 0xFFFF, sum = 0
8503 13:38:36.243095 12, 0xFFFF, sum = 0
8504 13:38:36.245921 13, 0xFFFF, sum = 0
8505 13:38:36.246007 14, 0x0, sum = 1
8506 13:38:36.249416 15, 0x0, sum = 2
8507 13:38:36.249492 16, 0x0, sum = 3
8508 13:38:36.252681 17, 0x0, sum = 4
8509 13:38:36.252760 best_step = 15
8510 13:38:36.252824
8511 13:38:36.252884 ==
8512 13:38:36.255919 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 13:38:36.259737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 13:38:36.262708 ==
8515 13:38:36.262788 RX Vref Scan: 1
8516 13:38:36.262853
8517 13:38:36.266145 Set Vref Range= 24 -> 127
8518 13:38:36.266224
8519 13:38:36.266288 RX Vref 24 -> 127, step: 1
8520 13:38:36.269396
8521 13:38:36.269483 RX Delay 19 -> 252, step: 4
8522 13:38:36.269549
8523 13:38:36.272508 Set Vref, RX VrefLevel [Byte0]: 24
8524 13:38:36.276007 [Byte1]: 24
8525 13:38:36.279645
8526 13:38:36.279724 Set Vref, RX VrefLevel [Byte0]: 25
8527 13:38:36.282864 [Byte1]: 25
8528 13:38:36.287356
8529 13:38:36.287438 Set Vref, RX VrefLevel [Byte0]: 26
8530 13:38:36.290484 [Byte1]: 26
8531 13:38:36.295019
8532 13:38:36.295130 Set Vref, RX VrefLevel [Byte0]: 27
8533 13:38:36.298207 [Byte1]: 27
8534 13:38:36.302019
8535 13:38:36.302102 Set Vref, RX VrefLevel [Byte0]: 28
8536 13:38:36.305560 [Byte1]: 28
8537 13:38:36.310008
8538 13:38:36.310088 Set Vref, RX VrefLevel [Byte0]: 29
8539 13:38:36.313221 [Byte1]: 29
8540 13:38:36.317213
8541 13:38:36.317304 Set Vref, RX VrefLevel [Byte0]: 30
8542 13:38:36.320815 [Byte1]: 30
8543 13:38:36.325250
8544 13:38:36.325333 Set Vref, RX VrefLevel [Byte0]: 31
8545 13:38:36.328365 [Byte1]: 31
8546 13:38:36.332662
8547 13:38:36.332738 Set Vref, RX VrefLevel [Byte0]: 32
8548 13:38:36.335969 [Byte1]: 32
8549 13:38:36.340410
8550 13:38:36.340508 Set Vref, RX VrefLevel [Byte0]: 33
8551 13:38:36.343591 [Byte1]: 33
8552 13:38:36.348127
8553 13:38:36.348213 Set Vref, RX VrefLevel [Byte0]: 34
8554 13:38:36.350733 [Byte1]: 34
8555 13:38:36.355020
8556 13:38:36.355098 Set Vref, RX VrefLevel [Byte0]: 35
8557 13:38:36.358659 [Byte1]: 35
8558 13:38:36.362783
8559 13:38:36.362864 Set Vref, RX VrefLevel [Byte0]: 36
8560 13:38:36.366236 [Byte1]: 36
8561 13:38:36.370535
8562 13:38:36.370609 Set Vref, RX VrefLevel [Byte0]: 37
8563 13:38:36.373642 [Byte1]: 37
8564 13:38:36.378084
8565 13:38:36.378164 Set Vref, RX VrefLevel [Byte0]: 38
8566 13:38:36.381230 [Byte1]: 38
8567 13:38:36.385658
8568 13:38:36.385734 Set Vref, RX VrefLevel [Byte0]: 39
8569 13:38:36.388807 [Byte1]: 39
8570 13:38:36.393218
8571 13:38:36.393304 Set Vref, RX VrefLevel [Byte0]: 40
8572 13:38:36.396529 [Byte1]: 40
8573 13:38:36.400527
8574 13:38:36.400634 Set Vref, RX VrefLevel [Byte0]: 41
8575 13:38:36.403912 [Byte1]: 41
8576 13:38:36.408174
8577 13:38:36.408282 Set Vref, RX VrefLevel [Byte0]: 42
8578 13:38:36.411325 [Byte1]: 42
8579 13:38:36.415751
8580 13:38:36.415842 Set Vref, RX VrefLevel [Byte0]: 43
8581 13:38:36.419399 [Byte1]: 43
8582 13:38:36.423455
8583 13:38:36.423531 Set Vref, RX VrefLevel [Byte0]: 44
8584 13:38:36.426954 [Byte1]: 44
8585 13:38:36.431159
8586 13:38:36.431238 Set Vref, RX VrefLevel [Byte0]: 45
8587 13:38:36.434116 [Byte1]: 45
8588 13:38:36.438801
8589 13:38:36.438880 Set Vref, RX VrefLevel [Byte0]: 46
8590 13:38:36.441618 [Byte1]: 46
8591 13:38:36.446087
8592 13:38:36.446168 Set Vref, RX VrefLevel [Byte0]: 47
8593 13:38:36.449326 [Byte1]: 47
8594 13:38:36.453827
8595 13:38:36.453931 Set Vref, RX VrefLevel [Byte0]: 48
8596 13:38:36.457107 [Byte1]: 48
8597 13:38:36.461096
8598 13:38:36.461184 Set Vref, RX VrefLevel [Byte0]: 49
8599 13:38:36.464623 [Byte1]: 49
8600 13:38:36.468616
8601 13:38:36.468701 Set Vref, RX VrefLevel [Byte0]: 50
8602 13:38:36.472100 [Byte1]: 50
8603 13:38:36.476661
8604 13:38:36.476739 Set Vref, RX VrefLevel [Byte0]: 51
8605 13:38:36.479740 [Byte1]: 51
8606 13:38:36.484204
8607 13:38:36.484309 Set Vref, RX VrefLevel [Byte0]: 52
8608 13:38:36.487380 [Byte1]: 52
8609 13:38:36.491697
8610 13:38:36.491774 Set Vref, RX VrefLevel [Byte0]: 53
8611 13:38:36.495071 [Byte1]: 53
8612 13:38:36.499306
8613 13:38:36.499380 Set Vref, RX VrefLevel [Byte0]: 54
8614 13:38:36.502656 [Byte1]: 54
8615 13:38:36.507075
8616 13:38:36.507152 Set Vref, RX VrefLevel [Byte0]: 55
8617 13:38:36.510218 [Byte1]: 55
8618 13:38:36.514105
8619 13:38:36.514181 Set Vref, RX VrefLevel [Byte0]: 56
8620 13:38:36.517368 [Byte1]: 56
8621 13:38:36.521977
8622 13:38:36.522055 Set Vref, RX VrefLevel [Byte0]: 57
8623 13:38:36.525086 [Byte1]: 57
8624 13:38:36.529294
8625 13:38:36.529375 Set Vref, RX VrefLevel [Byte0]: 58
8626 13:38:36.532732 [Byte1]: 58
8627 13:38:36.536919
8628 13:38:36.537013 Set Vref, RX VrefLevel [Byte0]: 59
8629 13:38:36.540568 [Byte1]: 59
8630 13:38:36.544314
8631 13:38:36.544398 Set Vref, RX VrefLevel [Byte0]: 60
8632 13:38:36.547680 [Byte1]: 60
8633 13:38:36.552331
8634 13:38:36.552423 Set Vref, RX VrefLevel [Byte0]: 61
8635 13:38:36.555830 [Byte1]: 61
8636 13:38:36.559838
8637 13:38:36.559928 Set Vref, RX VrefLevel [Byte0]: 62
8638 13:38:36.563088 [Byte1]: 62
8639 13:38:36.567647
8640 13:38:36.567725 Set Vref, RX VrefLevel [Byte0]: 63
8641 13:38:36.570895 [Byte1]: 63
8642 13:38:36.574687
8643 13:38:36.574790 Set Vref, RX VrefLevel [Byte0]: 64
8644 13:38:36.577930 [Byte1]: 64
8645 13:38:36.582395
8646 13:38:36.582472 Set Vref, RX VrefLevel [Byte0]: 65
8647 13:38:36.585812 [Byte1]: 65
8648 13:38:36.590022
8649 13:38:36.590100 Set Vref, RX VrefLevel [Byte0]: 66
8650 13:38:36.593149 [Byte1]: 66
8651 13:38:36.597517
8652 13:38:36.597594 Set Vref, RX VrefLevel [Byte0]: 67
8653 13:38:36.600691 [Byte1]: 67
8654 13:38:36.605332
8655 13:38:36.605411 Set Vref, RX VrefLevel [Byte0]: 68
8656 13:38:36.608559 [Byte1]: 68
8657 13:38:36.613017
8658 13:38:36.613122 Set Vref, RX VrefLevel [Byte0]: 69
8659 13:38:36.616144 [Byte1]: 69
8660 13:38:36.620090
8661 13:38:36.623347 Set Vref, RX VrefLevel [Byte0]: 70
8662 13:38:36.626602 [Byte1]: 70
8663 13:38:36.626677
8664 13:38:36.630285 Set Vref, RX VrefLevel [Byte0]: 71
8665 13:38:36.633465 [Byte1]: 71
8666 13:38:36.633590
8667 13:38:36.636635 Set Vref, RX VrefLevel [Byte0]: 72
8668 13:38:36.639997 [Byte1]: 72
8669 13:38:36.640086
8670 13:38:36.643561 Final RX Vref Byte 0 = 57 to rank0
8671 13:38:36.646806 Final RX Vref Byte 1 = 59 to rank0
8672 13:38:36.650032 Final RX Vref Byte 0 = 57 to rank1
8673 13:38:36.653187 Final RX Vref Byte 1 = 59 to rank1==
8674 13:38:36.656165 Dram Type= 6, Freq= 0, CH_1, rank 0
8675 13:38:36.662733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8676 13:38:36.662818 ==
8677 13:38:36.662886 DQS Delay:
8678 13:38:36.666508 DQS0 = 0, DQS1 = 0
8679 13:38:36.666587 DQM Delay:
8680 13:38:36.666657 DQM0 = 132, DQM1 = 128
8681 13:38:36.669751 DQ Delay:
8682 13:38:36.672939 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8683 13:38:36.676226 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8684 13:38:36.679298 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8685 13:38:36.682488 DQ12 =140, DQ13 =138, DQ14 =134, DQ15 =138
8686 13:38:36.682569
8687 13:38:36.682642
8688 13:38:36.682704
8689 13:38:36.686305 [DramC_TX_OE_Calibration] TA2
8690 13:38:36.689563 Original DQ_B0 (3 6) =30, OEN = 27
8691 13:38:36.692460 Original DQ_B1 (3 6) =30, OEN = 27
8692 13:38:36.695544 24, 0x0, End_B0=24 End_B1=24
8693 13:38:36.695654 25, 0x0, End_B0=25 End_B1=25
8694 13:38:36.698971 26, 0x0, End_B0=26 End_B1=26
8695 13:38:36.702350 27, 0x0, End_B0=27 End_B1=27
8696 13:38:36.705556 28, 0x0, End_B0=28 End_B1=28
8697 13:38:36.709189 29, 0x0, End_B0=29 End_B1=29
8698 13:38:36.709304 30, 0x0, End_B0=30 End_B1=30
8699 13:38:36.712320 31, 0x4141, End_B0=30 End_B1=30
8700 13:38:36.715688 Byte0 end_step=30 best_step=27
8701 13:38:36.718897 Byte1 end_step=30 best_step=27
8702 13:38:36.722047 Byte0 TX OE(2T, 0.5T) = (3, 3)
8703 13:38:36.725367 Byte1 TX OE(2T, 0.5T) = (3, 3)
8704 13:38:36.725444
8705 13:38:36.725516
8706 13:38:36.731829 [DQSOSCAuto] RK0, (LSB)MR18= 0xf18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8707 13:38:36.735232 CH1 RK0: MR19=303, MR18=F18
8708 13:38:36.741865 CH1_RK0: MR19=0x303, MR18=0xF18, DQSOSC=397, MR23=63, INC=23, DEC=15
8709 13:38:36.741952
8710 13:38:36.745035 ----->DramcWriteLeveling(PI) begin...
8711 13:38:36.745151 ==
8712 13:38:36.748200 Dram Type= 6, Freq= 0, CH_1, rank 1
8713 13:38:36.752238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 13:38:36.752324 ==
8715 13:38:36.755228 Write leveling (Byte 0): 24 => 24
8716 13:38:36.758444 Write leveling (Byte 1): 25 => 25
8717 13:38:36.761626 DramcWriteLeveling(PI) end<-----
8718 13:38:36.761734
8719 13:38:36.761835 ==
8720 13:38:36.765298 Dram Type= 6, Freq= 0, CH_1, rank 1
8721 13:38:36.768249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 13:38:36.771772 ==
8723 13:38:36.771881 [Gating] SW mode calibration
8724 13:38:36.781449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8725 13:38:36.784672 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8726 13:38:36.787937 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 13:38:36.794458 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 13:38:36.797596 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8729 13:38:36.801607 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8730 13:38:36.807990 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 13:38:36.810860 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 13:38:36.814464 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 13:38:36.820719 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 13:38:36.824056 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 13:38:36.827613 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8736 13:38:36.834546 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8737 13:38:36.837724 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
8738 13:38:36.840965 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8739 13:38:36.847341 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 13:38:36.850841 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 13:38:36.854067 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 13:38:36.860607 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 13:38:36.863804 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8744 13:38:36.867316 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8745 13:38:36.873711 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8746 13:38:36.877279 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 13:38:36.880337 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 13:38:36.887015 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 13:38:36.890321 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 13:38:36.893982 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 13:38:36.899958 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8752 13:38:36.903232 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8753 13:38:36.906799 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8754 13:38:36.913566 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8755 13:38:36.916254 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 13:38:36.919457 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 13:38:36.926537 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 13:38:36.929609 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 13:38:36.932560 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 13:38:36.939612 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 13:38:36.942993 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 13:38:36.946359 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 13:38:36.952808 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 13:38:36.955925 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 13:38:36.958992 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 13:38:36.965640 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 13:38:36.968960 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8768 13:38:36.972939 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8769 13:38:36.979404 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8770 13:38:36.982385 Total UI for P1: 0, mck2ui 16
8771 13:38:36.985601 best dqsien dly found for B0: ( 1, 9, 6)
8772 13:38:36.988731 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 13:38:36.992377 Total UI for P1: 0, mck2ui 16
8774 13:38:36.995642 best dqsien dly found for B1: ( 1, 9, 10)
8775 13:38:36.998786 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8776 13:38:37.001875 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8777 13:38:37.001968
8778 13:38:37.005236 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8779 13:38:37.011946 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8780 13:38:37.012049 [Gating] SW calibration Done
8781 13:38:37.012122 ==
8782 13:38:37.015195 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 13:38:37.021824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 13:38:37.021940 ==
8785 13:38:37.022037 RX Vref Scan: 0
8786 13:38:37.022129
8787 13:38:37.025104 RX Vref 0 -> 0, step: 1
8788 13:38:37.025214
8789 13:38:37.028293 RX Delay 0 -> 252, step: 8
8790 13:38:37.031548 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8791 13:38:37.034652 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8792 13:38:37.038421 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8793 13:38:37.044880 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8794 13:38:37.048024 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8795 13:38:37.051436 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8796 13:38:37.055121 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8797 13:38:37.057847 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8798 13:38:37.064466 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8799 13:38:37.067674 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8800 13:38:37.071044 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8801 13:38:37.074365 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8802 13:38:37.077495 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8803 13:38:37.084511 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8804 13:38:37.087683 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8805 13:38:37.090795 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8806 13:38:37.090911 ==
8807 13:38:37.093944 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 13:38:37.097674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 13:38:37.101334 ==
8810 13:38:37.101455 DQS Delay:
8811 13:38:37.101553 DQS0 = 0, DQS1 = 0
8812 13:38:37.104453 DQM Delay:
8813 13:38:37.104532 DQM0 = 132, DQM1 = 130
8814 13:38:37.107160 DQ Delay:
8815 13:38:37.111130 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =127
8816 13:38:37.113852 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8817 13:38:37.117041 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8818 13:38:37.120273 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8819 13:38:37.120383
8820 13:38:37.120482
8821 13:38:37.120573 ==
8822 13:38:37.124304 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 13:38:37.127262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 13:38:37.130780 ==
8825 13:38:37.130879
8826 13:38:37.130972
8827 13:38:37.131067 TX Vref Scan disable
8828 13:38:37.133726 == TX Byte 0 ==
8829 13:38:37.136972 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8830 13:38:37.140589 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8831 13:38:37.143821 == TX Byte 1 ==
8832 13:38:37.146568 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8833 13:38:37.150367 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8834 13:38:37.153567 ==
8835 13:38:37.156683 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 13:38:37.159848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 13:38:37.159957 ==
8838 13:38:37.173021
8839 13:38:37.176175 TX Vref early break, caculate TX vref
8840 13:38:37.179529 TX Vref=16, minBit 5, minWin=22, winSum=381
8841 13:38:37.182958 TX Vref=18, minBit 9, minWin=22, winSum=385
8842 13:38:37.186323 TX Vref=20, minBit 9, minWin=22, winSum=394
8843 13:38:37.189810 TX Vref=22, minBit 9, minWin=23, winSum=403
8844 13:38:37.192964 TX Vref=24, minBit 9, minWin=23, winSum=409
8845 13:38:37.199345 TX Vref=26, minBit 5, minWin=25, winSum=416
8846 13:38:37.202411 TX Vref=28, minBit 9, minWin=25, winSum=421
8847 13:38:37.206117 TX Vref=30, minBit 8, minWin=25, winSum=419
8848 13:38:37.209228 TX Vref=32, minBit 0, minWin=25, winSum=411
8849 13:38:37.212592 TX Vref=34, minBit 0, minWin=24, winSum=399
8850 13:38:37.215845 TX Vref=36, minBit 8, minWin=23, winSum=397
8851 13:38:37.222783 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8852 13:38:37.222897
8853 13:38:37.226042 Final TX Range 0 Vref 28
8854 13:38:37.226146
8855 13:38:37.226239 ==
8856 13:38:37.229197 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 13:38:37.232413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 13:38:37.232518 ==
8859 13:38:37.235731
8860 13:38:37.235829
8861 13:38:37.235923 TX Vref Scan disable
8862 13:38:37.242003 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8863 13:38:37.242111 == TX Byte 0 ==
8864 13:38:37.245851 u2DelayCellOfst[0]=14 cells (4 PI)
8865 13:38:37.249104 u2DelayCellOfst[1]=7 cells (2 PI)
8866 13:38:37.252261 u2DelayCellOfst[2]=0 cells (0 PI)
8867 13:38:37.255460 u2DelayCellOfst[3]=3 cells (1 PI)
8868 13:38:37.258797 u2DelayCellOfst[4]=7 cells (2 PI)
8869 13:38:37.261911 u2DelayCellOfst[5]=14 cells (4 PI)
8870 13:38:37.265636 u2DelayCellOfst[6]=14 cells (4 PI)
8871 13:38:37.268863 u2DelayCellOfst[7]=3 cells (1 PI)
8872 13:38:37.271978 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8873 13:38:37.275124 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8874 13:38:37.278870 == TX Byte 1 ==
8875 13:38:37.282201 u2DelayCellOfst[8]=0 cells (0 PI)
8876 13:38:37.285526 u2DelayCellOfst[9]=3 cells (1 PI)
8877 13:38:37.288851 u2DelayCellOfst[10]=14 cells (4 PI)
8878 13:38:37.291813 u2DelayCellOfst[11]=7 cells (2 PI)
8879 13:38:37.291971 u2DelayCellOfst[12]=14 cells (4 PI)
8880 13:38:37.295430 u2DelayCellOfst[13]=17 cells (5 PI)
8881 13:38:37.298342 u2DelayCellOfst[14]=21 cells (6 PI)
8882 13:38:37.301979 u2DelayCellOfst[15]=21 cells (6 PI)
8883 13:38:37.308375 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8884 13:38:37.311930 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8885 13:38:37.312067 DramC Write-DBI on
8886 13:38:37.315394 ==
8887 13:38:37.318242 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 13:38:37.321950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 13:38:37.322077 ==
8890 13:38:37.322200
8891 13:38:37.322320
8892 13:38:37.324640 TX Vref Scan disable
8893 13:38:37.324744 == TX Byte 0 ==
8894 13:38:37.331273 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8895 13:38:37.331396 == TX Byte 1 ==
8896 13:38:37.334408 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8897 13:38:37.337891 DramC Write-DBI off
8898 13:38:37.338001
8899 13:38:37.338096 [DATLAT]
8900 13:38:37.340934 Freq=1600, CH1 RK1
8901 13:38:37.341046
8902 13:38:37.341145 DATLAT Default: 0xf
8903 13:38:37.344248 0, 0xFFFF, sum = 0
8904 13:38:37.344359 1, 0xFFFF, sum = 0
8905 13:38:37.348295 2, 0xFFFF, sum = 0
8906 13:38:37.348409 3, 0xFFFF, sum = 0
8907 13:38:37.351237 4, 0xFFFF, sum = 0
8908 13:38:37.354497 5, 0xFFFF, sum = 0
8909 13:38:37.354606 6, 0xFFFF, sum = 0
8910 13:38:37.357618 7, 0xFFFF, sum = 0
8911 13:38:37.357745 8, 0xFFFF, sum = 0
8912 13:38:37.360960 9, 0xFFFF, sum = 0
8913 13:38:37.361071 10, 0xFFFF, sum = 0
8914 13:38:37.364049 11, 0xFFFF, sum = 0
8915 13:38:37.364157 12, 0xFFFF, sum = 0
8916 13:38:37.367200 13, 0xFFFF, sum = 0
8917 13:38:37.367317 14, 0x0, sum = 1
8918 13:38:37.371039 15, 0x0, sum = 2
8919 13:38:37.371126 16, 0x0, sum = 3
8920 13:38:37.374227 17, 0x0, sum = 4
8921 13:38:37.374341 best_step = 15
8922 13:38:37.374439
8923 13:38:37.374529 ==
8924 13:38:37.377409 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 13:38:37.383919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 13:38:37.384046 ==
8927 13:38:37.384145 RX Vref Scan: 0
8928 13:38:37.384240
8929 13:38:37.387058 RX Vref 0 -> 0, step: 1
8930 13:38:37.387171
8931 13:38:37.390359 RX Delay 11 -> 252, step: 4
8932 13:38:37.394032 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8933 13:38:37.397273 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8934 13:38:37.400371 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8935 13:38:37.406774 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8936 13:38:37.409986 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8937 13:38:37.413867 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8938 13:38:37.417082 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8939 13:38:37.420192 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8940 13:38:37.426376 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8941 13:38:37.430115 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8942 13:38:37.433252 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8943 13:38:37.436760 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8944 13:38:37.443205 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8945 13:38:37.446804 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8946 13:38:37.449836 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8947 13:38:37.452952 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8948 13:38:37.453065 ==
8949 13:38:37.456200 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 13:38:37.462727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 13:38:37.462854 ==
8952 13:38:37.462952 DQS Delay:
8953 13:38:37.465973 DQS0 = 0, DQS1 = 0
8954 13:38:37.466084 DQM Delay:
8955 13:38:37.466178 DQM0 = 131, DQM1 = 127
8956 13:38:37.469239 DQ Delay:
8957 13:38:37.472419 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8958 13:38:37.476260 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
8959 13:38:37.479530 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8960 13:38:37.482891 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
8961 13:38:37.483005
8962 13:38:37.483101
8963 13:38:37.483198
8964 13:38:37.486090 [DramC_TX_OE_Calibration] TA2
8965 13:38:37.489433 Original DQ_B0 (3 6) =30, OEN = 27
8966 13:38:37.492341 Original DQ_B1 (3 6) =30, OEN = 27
8967 13:38:37.495314 24, 0x0, End_B0=24 End_B1=24
8968 13:38:37.499252 25, 0x0, End_B0=25 End_B1=25
8969 13:38:37.499372 26, 0x0, End_B0=26 End_B1=26
8970 13:38:37.502555 27, 0x0, End_B0=27 End_B1=27
8971 13:38:37.505617 28, 0x0, End_B0=28 End_B1=28
8972 13:38:37.508793 29, 0x0, End_B0=29 End_B1=29
8973 13:38:37.511945 30, 0x0, End_B0=30 End_B1=30
8974 13:38:37.512058 31, 0x4141, End_B0=30 End_B1=30
8975 13:38:37.515141 Byte0 end_step=30 best_step=27
8976 13:38:37.518376 Byte1 end_step=30 best_step=27
8977 13:38:37.521694 Byte0 TX OE(2T, 0.5T) = (3, 3)
8978 13:38:37.524965 Byte1 TX OE(2T, 0.5T) = (3, 3)
8979 13:38:37.525073
8980 13:38:37.525169
8981 13:38:37.532047 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8982 13:38:37.535032 CH1 RK1: MR19=303, MR18=E1C
8983 13:38:37.541832 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8984 13:38:37.545459 [RxdqsGatingPostProcess] freq 1600
8985 13:38:37.548430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8986 13:38:37.551492 best DQS0 dly(2T, 0.5T) = (1, 1)
8987 13:38:37.554697 best DQS1 dly(2T, 0.5T) = (1, 1)
8988 13:38:37.558732 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8989 13:38:37.561799 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8990 13:38:37.565118 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 13:38:37.568547 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 13:38:37.571715 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 13:38:37.574819 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 13:38:37.578014 Pre-setting of DQS Precalculation
8995 13:38:37.581397 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8996 13:38:37.591207 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8997 13:38:37.597707 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8998 13:38:37.597864
8999 13:38:37.597966
9000 13:38:37.600983 [Calibration Summary] 3200 Mbps
9001 13:38:37.601099 CH 0, Rank 0
9002 13:38:37.604096 SW Impedance : PASS
9003 13:38:37.604223 DUTY Scan : NO K
9004 13:38:37.607350 ZQ Calibration : PASS
9005 13:38:37.611053 Jitter Meter : NO K
9006 13:38:37.611181 CBT Training : PASS
9007 13:38:37.614230 Write leveling : PASS
9008 13:38:37.617392 RX DQS gating : PASS
9009 13:38:37.617501 RX DQ/DQS(RDDQC) : PASS
9010 13:38:37.620927 TX DQ/DQS : PASS
9011 13:38:37.624282 RX DATLAT : PASS
9012 13:38:37.624392 RX DQ/DQS(Engine): PASS
9013 13:38:37.627285 TX OE : PASS
9014 13:38:37.627393 All Pass.
9015 13:38:37.627491
9016 13:38:37.630587 CH 0, Rank 1
9017 13:38:37.630702 SW Impedance : PASS
9018 13:38:37.633940 DUTY Scan : NO K
9019 13:38:37.637169 ZQ Calibration : PASS
9020 13:38:37.637293 Jitter Meter : NO K
9021 13:38:37.640329 CBT Training : PASS
9022 13:38:37.644168 Write leveling : PASS
9023 13:38:37.644283 RX DQS gating : PASS
9024 13:38:37.647288 RX DQ/DQS(RDDQC) : PASS
9025 13:38:37.650478 TX DQ/DQS : PASS
9026 13:38:37.650592 RX DATLAT : PASS
9027 13:38:37.653497 RX DQ/DQS(Engine): PASS
9028 13:38:37.657271 TX OE : PASS
9029 13:38:37.657359 All Pass.
9030 13:38:37.657454
9031 13:38:37.657547 CH 1, Rank 0
9032 13:38:37.660359 SW Impedance : PASS
9033 13:38:37.663302 DUTY Scan : NO K
9034 13:38:37.663407 ZQ Calibration : PASS
9035 13:38:37.666824 Jitter Meter : NO K
9036 13:38:37.669954 CBT Training : PASS
9037 13:38:37.670063 Write leveling : PASS
9038 13:38:37.673213 RX DQS gating : PASS
9039 13:38:37.676539 RX DQ/DQS(RDDQC) : PASS
9040 13:38:37.676657 TX DQ/DQS : PASS
9041 13:38:37.679676 RX DATLAT : PASS
9042 13:38:37.679790 RX DQ/DQS(Engine): PASS
9043 13:38:37.682918 TX OE : PASS
9044 13:38:37.683033 All Pass.
9045 13:38:37.683129
9046 13:38:37.686193 CH 1, Rank 1
9047 13:38:37.689375 SW Impedance : PASS
9048 13:38:37.689471 DUTY Scan : NO K
9049 13:38:37.692683 ZQ Calibration : PASS
9050 13:38:37.692798 Jitter Meter : NO K
9051 13:38:37.696586 CBT Training : PASS
9052 13:38:37.699333 Write leveling : PASS
9053 13:38:37.699452 RX DQS gating : PASS
9054 13:38:37.702614 RX DQ/DQS(RDDQC) : PASS
9055 13:38:37.706295 TX DQ/DQS : PASS
9056 13:38:37.706414 RX DATLAT : PASS
9057 13:38:37.709604 RX DQ/DQS(Engine): PASS
9058 13:38:37.712783 TX OE : PASS
9059 13:38:37.712903 All Pass.
9060 13:38:37.712998
9061 13:38:37.716263 DramC Write-DBI on
9062 13:38:37.716386 PER_BANK_REFRESH: Hybrid Mode
9063 13:38:37.719186 TX_TRACKING: ON
9064 13:38:37.728909 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9065 13:38:37.736103 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9066 13:38:37.742780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 13:38:37.745789 [FAST_K] Save calibration result to emmc
9068 13:38:37.749135 sync common calibartion params.
9069 13:38:37.752342 sync cbt_mode0:1, 1:1
9070 13:38:37.752467 dram_init: ddr_geometry: 2
9071 13:38:37.755510 dram_init: ddr_geometry: 2
9072 13:38:37.758785 dram_init: ddr_geometry: 2
9073 13:38:37.762499 0:dram_rank_size:100000000
9074 13:38:37.762610 1:dram_rank_size:100000000
9075 13:38:37.768765 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9076 13:38:37.771834 DFS_SHUFFLE_HW_MODE: ON
9077 13:38:37.775462 dramc_set_vcore_voltage set vcore to 725000
9078 13:38:37.778452 Read voltage for 1600, 0
9079 13:38:37.778575 Vio18 = 0
9080 13:38:37.778671 Vcore = 725000
9081 13:38:37.781981 Vdram = 0
9082 13:38:37.782103 Vddq = 0
9083 13:38:37.782201 Vmddr = 0
9084 13:38:37.784995 switch to 3200 Mbps bootup
9085 13:38:37.785102 [DramcRunTimeConfig]
9086 13:38:37.788183 PHYPLL
9087 13:38:37.788298 DPM_CONTROL_AFTERK: ON
9088 13:38:37.791581 PER_BANK_REFRESH: ON
9089 13:38:37.794798 REFRESH_OVERHEAD_REDUCTION: ON
9090 13:38:37.794921 CMD_PICG_NEW_MODE: OFF
9091 13:38:37.798148 XRTWTW_NEW_MODE: ON
9092 13:38:37.798263 XRTRTR_NEW_MODE: ON
9093 13:38:37.801354 TX_TRACKING: ON
9094 13:38:37.801467 RDSEL_TRACKING: OFF
9095 13:38:37.804685 DQS Precalculation for DVFS: ON
9096 13:38:37.808440 RX_TRACKING: OFF
9097 13:38:37.808576 HW_GATING DBG: ON
9098 13:38:37.811719 ZQCS_ENABLE_LP4: ON
9099 13:38:37.811836 RX_PICG_NEW_MODE: ON
9100 13:38:37.814953 TX_PICG_NEW_MODE: ON
9101 13:38:37.818075 ENABLE_RX_DCM_DPHY: ON
9102 13:38:37.821318 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9103 13:38:37.821398 DUMMY_READ_FOR_TRACKING: OFF
9104 13:38:37.824479 !!! SPM_CONTROL_AFTERK: OFF
9105 13:38:37.827723 !!! SPM could not control APHY
9106 13:38:37.831496 IMPEDANCE_TRACKING: ON
9107 13:38:37.831603 TEMP_SENSOR: ON
9108 13:38:37.834274 HW_SAVE_FOR_SR: OFF
9109 13:38:37.834381 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9110 13:38:37.841046 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9111 13:38:37.841154 Read ODT Tracking: ON
9112 13:38:37.844343 Refresh Rate DeBounce: ON
9113 13:38:37.847647 DFS_NO_QUEUE_FLUSH: ON
9114 13:38:37.847756 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9115 13:38:37.850875 ENABLE_DFS_RUNTIME_MRW: OFF
9116 13:38:37.854135 DDR_RESERVE_NEW_MODE: ON
9117 13:38:37.857355 MR_CBT_SWITCH_FREQ: ON
9118 13:38:37.857452 =========================
9119 13:38:37.877871 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9120 13:38:37.880176 dram_init: ddr_geometry: 2
9121 13:38:37.898827 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9122 13:38:37.902262 dram_init: dram init end (result: 0)
9123 13:38:37.908685 DRAM-K: Full calibration passed in 24435 msecs
9124 13:38:37.911997 MRC: failed to locate region type 0.
9125 13:38:37.912134 DRAM rank0 size:0x100000000,
9126 13:38:37.915242 DRAM rank1 size=0x100000000
9127 13:38:37.924784 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9128 13:38:37.931457 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9129 13:38:37.938865 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9130 13:38:37.948360 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9131 13:38:37.948492 DRAM rank0 size:0x100000000,
9132 13:38:37.951880 DRAM rank1 size=0x100000000
9133 13:38:37.951994 CBMEM:
9134 13:38:37.954880 IMD: root @ 0xfffff000 254 entries.
9135 13:38:37.958360 IMD: root @ 0xffffec00 62 entries.
9136 13:38:37.961468 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9137 13:38:37.968038 WARNING: RO_VPD is uninitialized or empty.
9138 13:38:37.970866 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9139 13:38:37.979014 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9140 13:38:37.991618 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9141 13:38:38.003348 BS: romstage times (exec / console): total (unknown) / 23960 ms
9142 13:38:38.003482
9143 13:38:38.003583
9144 13:38:38.013003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9145 13:38:38.016303 ARM64: Exception handlers installed.
9146 13:38:38.019820 ARM64: Testing exception
9147 13:38:38.022847 ARM64: Done test exception
9148 13:38:38.022989 Enumerating buses...
9149 13:38:38.026095 Show all devs... Before device enumeration.
9150 13:38:38.029787 Root Device: enabled 1
9151 13:38:38.032980 CPU_CLUSTER: 0: enabled 1
9152 13:38:38.033110 CPU: 00: enabled 1
9153 13:38:38.036415 Compare with tree...
9154 13:38:38.036505 Root Device: enabled 1
9155 13:38:38.039933 CPU_CLUSTER: 0: enabled 1
9156 13:38:38.042876 CPU: 00: enabled 1
9157 13:38:38.042990 Root Device scanning...
9158 13:38:38.045615 scan_static_bus for Root Device
9159 13:38:38.049859 CPU_CLUSTER: 0 enabled
9160 13:38:38.052418 scan_static_bus for Root Device done
9161 13:38:38.056186 scan_bus: bus Root Device finished in 8 msecs
9162 13:38:38.056308 done
9163 13:38:38.062489 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9164 13:38:38.065811 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9165 13:38:38.072068 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9166 13:38:38.075833 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9167 13:38:38.078852 Allocating resources...
9168 13:38:38.082053 Reading resources...
9169 13:38:38.085360 Root Device read_resources bus 0 link: 0
9170 13:38:38.088476 DRAM rank0 size:0x100000000,
9171 13:38:38.088560 DRAM rank1 size=0x100000000
9172 13:38:38.095265 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9173 13:38:38.095376 CPU: 00 missing read_resources
9174 13:38:38.101513 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9175 13:38:38.104914 Root Device read_resources bus 0 link: 0 done
9176 13:38:38.108712 Done reading resources.
9177 13:38:38.111966 Show resources in subtree (Root Device)...After reading.
9178 13:38:38.115301 Root Device child on link 0 CPU_CLUSTER: 0
9179 13:38:38.118430 CPU_CLUSTER: 0 child on link 0 CPU: 00
9180 13:38:38.128246 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9181 13:38:38.128338 CPU: 00
9182 13:38:38.134733 Root Device assign_resources, bus 0 link: 0
9183 13:38:38.138028 CPU_CLUSTER: 0 missing set_resources
9184 13:38:38.141039 Root Device assign_resources, bus 0 link: 0 done
9185 13:38:38.144379 Done setting resources.
9186 13:38:38.147472 Show resources in subtree (Root Device)...After assigning values.
9187 13:38:38.151081 Root Device child on link 0 CPU_CLUSTER: 0
9188 13:38:38.157646 CPU_CLUSTER: 0 child on link 0 CPU: 00
9189 13:38:38.164439 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9190 13:38:38.167557 CPU: 00
9191 13:38:38.167637 Done allocating resources.
9192 13:38:38.174224 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9193 13:38:38.174320 Enabling resources...
9194 13:38:38.177390 done.
9195 13:38:38.180638 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9196 13:38:38.183832 Initializing devices...
9197 13:38:38.183945 Root Device init
9198 13:38:38.187062 init hardware done!
9199 13:38:38.187166 0x00000018: ctrlr->caps
9200 13:38:38.190335 52.000 MHz: ctrlr->f_max
9201 13:38:38.194210 0.400 MHz: ctrlr->f_min
9202 13:38:38.197477 0x40ff8080: ctrlr->voltages
9203 13:38:38.197589 sclk: 390625
9204 13:38:38.197685 Bus Width = 1
9205 13:38:38.200415 sclk: 390625
9206 13:38:38.200525 Bus Width = 1
9207 13:38:38.203828 Early init status = 3
9208 13:38:38.207117 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9209 13:38:38.211623 in-header: 03 fc 00 00 01 00 00 00
9210 13:38:38.214742 in-data: 00
9211 13:38:38.218260 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9212 13:38:38.223907 in-header: 03 fd 00 00 00 00 00 00
9213 13:38:38.227007 in-data:
9214 13:38:38.230188 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9215 13:38:38.234637 in-header: 03 fc 00 00 01 00 00 00
9216 13:38:38.237889 in-data: 00
9217 13:38:38.241668 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9218 13:38:38.247277 in-header: 03 fd 00 00 00 00 00 00
9219 13:38:38.250528 in-data:
9220 13:38:38.253744 [SSUSB] Setting up USB HOST controller...
9221 13:38:38.257308 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9222 13:38:38.260185 [SSUSB] phy power-on done.
9223 13:38:38.263768 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9224 13:38:38.269991 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9225 13:38:38.273544 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9226 13:38:38.279976 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9227 13:38:38.286520 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9228 13:38:38.293061 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9229 13:38:38.299616 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9230 13:38:38.306385 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9231 13:38:38.309641 SPM: binary array size = 0x9dc
9232 13:38:38.316339 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9233 13:38:38.319493 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9234 13:38:38.326073 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9235 13:38:38.332786 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9236 13:38:38.335405 configure_display: Starting display init
9237 13:38:38.370684 anx7625_power_on_init: Init interface.
9238 13:38:38.373710 anx7625_disable_pd_protocol: Disabled PD feature.
9239 13:38:38.376938 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9240 13:38:38.405002 anx7625_start_dp_work: Secure OCM version=00
9241 13:38:38.408362 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9242 13:38:38.423294 sp_tx_get_edid_block: EDID Block = 1
9243 13:38:38.525550 Extracted contents:
9244 13:38:38.528977 header: 00 ff ff ff ff ff ff 00
9245 13:38:38.531963 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9246 13:38:38.535306 version: 01 04
9247 13:38:38.538494 basic params: 95 1f 11 78 0a
9248 13:38:38.541861 chroma info: 76 90 94 55 54 90 27 21 50 54
9249 13:38:38.545135 established: 00 00 00
9250 13:38:38.551688 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9251 13:38:38.558317 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9252 13:38:38.562072 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9253 13:38:38.568219 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9254 13:38:38.575217 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9255 13:38:38.578459 extensions: 00
9256 13:38:38.578551 checksum: fb
9257 13:38:38.578638
9258 13:38:38.584637 Manufacturer: IVO Model 57d Serial Number 0
9259 13:38:38.584722 Made week 0 of 2020
9260 13:38:38.588363 EDID version: 1.4
9261 13:38:38.588447 Digital display
9262 13:38:38.591632 6 bits per primary color channel
9263 13:38:38.591721 DisplayPort interface
9264 13:38:38.594775 Maximum image size: 31 cm x 17 cm
9265 13:38:38.598169 Gamma: 220%
9266 13:38:38.598243 Check DPMS levels
9267 13:38:38.604564 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9268 13:38:38.607773 First detailed timing is preferred timing
9269 13:38:38.607883 Established timings supported:
9270 13:38:38.610882 Standard timings supported:
9271 13:38:38.614638 Detailed timings
9272 13:38:38.617640 Hex of detail: 383680a07038204018303c0035ae10000019
9273 13:38:38.624212 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9274 13:38:38.627437 0780 0798 07c8 0820 hborder 0
9275 13:38:38.630698 0438 043b 0447 0458 vborder 0
9276 13:38:38.633959 -hsync -vsync
9277 13:38:38.634053 Did detailed timing
9278 13:38:38.640944 Hex of detail: 000000000000000000000000000000000000
9279 13:38:38.643853 Manufacturer-specified data, tag 0
9280 13:38:38.647051 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9281 13:38:38.650332 ASCII string: InfoVision
9282 13:38:38.653845 Hex of detail: 000000fe00523134304e574635205248200a
9283 13:38:38.656919 ASCII string: R140NWF5 RH
9284 13:38:38.656997 Checksum
9285 13:38:38.660216 Checksum: 0xfb (valid)
9286 13:38:38.663959 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9287 13:38:38.667186 DSI data_rate: 832800000 bps
9288 13:38:38.673352 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9289 13:38:38.677125 anx7625_parse_edid: pixelclock(138800).
9290 13:38:38.680262 hactive(1920), hsync(48), hfp(24), hbp(88)
9291 13:38:38.683588 vactive(1080), vsync(12), vfp(3), vbp(17)
9292 13:38:38.686999 anx7625_dsi_config: config dsi.
9293 13:38:38.693323 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9294 13:38:38.707676 anx7625_dsi_config: success to config DSI
9295 13:38:38.710817 anx7625_dp_start: MIPI phy setup OK.
9296 13:38:38.714052 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9297 13:38:38.717355 mtk_ddp_mode_set invalid vrefresh 60
9298 13:38:38.720820 main_disp_path_setup
9299 13:38:38.720896 ovl_layer_smi_id_en
9300 13:38:38.723812 ovl_layer_smi_id_en
9301 13:38:38.723907 ccorr_config
9302 13:38:38.723973 aal_config
9303 13:38:38.727566 gamma_config
9304 13:38:38.727644 postmask_config
9305 13:38:38.730514 dither_config
9306 13:38:38.733972 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9307 13:38:38.740493 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9308 13:38:38.743699 Root Device init finished in 555 msecs
9309 13:38:38.747174 CPU_CLUSTER: 0 init
9310 13:38:38.753650 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9311 13:38:38.760218 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9312 13:38:38.760302 APU_MBOX 0x190000b0 = 0x10001
9313 13:38:38.763524 APU_MBOX 0x190001b0 = 0x10001
9314 13:38:38.766787 APU_MBOX 0x190005b0 = 0x10001
9315 13:38:38.770237 APU_MBOX 0x190006b0 = 0x10001
9316 13:38:38.776652 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9317 13:38:38.786262 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9318 13:38:38.798860 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9319 13:38:38.805170 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9320 13:38:38.816985 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9321 13:38:38.826076 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9322 13:38:38.829386 CPU_CLUSTER: 0 init finished in 81 msecs
9323 13:38:38.833284 Devices initialized
9324 13:38:38.836523 Show all devs... After init.
9325 13:38:38.836618 Root Device: enabled 1
9326 13:38:38.839817 CPU_CLUSTER: 0: enabled 1
9327 13:38:38.843060 CPU: 00: enabled 1
9328 13:38:38.845863 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9329 13:38:38.849488 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9330 13:38:38.853167 ELOG: NV offset 0x57f000 size 0x1000
9331 13:38:38.859339 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9332 13:38:38.865872 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9333 13:38:38.869308 ELOG: Event(17) added with size 13 at 2024-05-28 13:38:38 UTC
9334 13:38:38.875750 out: cmd=0x121: 03 db 21 01 00 00 00 00
9335 13:38:38.879603 in-header: 03 95 00 00 2c 00 00 00
9336 13:38:38.888867 in-data: a9 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 13:38:38.895454 ELOG: Event(A1) added with size 10 at 2024-05-28 13:38:38 UTC
9338 13:38:38.902160 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9339 13:38:38.908943 ELOG: Event(A0) added with size 9 at 2024-05-28 13:38:38 UTC
9340 13:38:38.912330 elog_add_boot_reason: Logged dev mode boot
9341 13:38:38.918984 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9342 13:38:38.919069 Finalize devices...
9343 13:38:38.921857 Devices finalized
9344 13:38:38.925160 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9345 13:38:38.928495 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9346 13:38:38.932438 in-header: 03 07 00 00 08 00 00 00
9347 13:38:38.936078 in-data: aa e4 47 04 13 02 00 00
9348 13:38:38.939048 Chrome EC: UHEPI supported
9349 13:38:38.945940 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9350 13:38:38.949062 in-header: 03 a9 00 00 08 00 00 00
9351 13:38:38.952218 in-data: 84 60 60 08 00 00 00 00
9352 13:38:38.959036 ELOG: Event(91) added with size 10 at 2024-05-28 13:38:38 UTC
9353 13:38:38.962186 Chrome EC: clear events_b mask to 0x0000000020004000
9354 13:38:38.968615 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9355 13:38:38.973106 in-header: 03 fd 00 00 00 00 00 00
9356 13:38:38.976291 in-data:
9357 13:38:38.979902 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9358 13:38:38.983006 Writing coreboot table at 0xffe64000
9359 13:38:38.989445 0. 000000000010a000-0000000000113fff: RAMSTAGE
9360 13:38:38.992703 1. 0000000040000000-00000000400fffff: RAM
9361 13:38:38.996366 2. 0000000040100000-000000004032afff: RAMSTAGE
9362 13:38:38.999313 3. 000000004032b000-00000000545fffff: RAM
9363 13:38:39.002546 4. 0000000054600000-000000005465ffff: BL31
9364 13:38:39.005654 5. 0000000054660000-00000000ffe63fff: RAM
9365 13:38:39.012362 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9366 13:38:39.015562 7. 0000000100000000-000000023fffffff: RAM
9367 13:38:39.018518 Passing 5 GPIOs to payload:
9368 13:38:39.022394 NAME | PORT | POLARITY | VALUE
9369 13:38:39.028368 EC in RW | 0x000000aa | low | undefined
9370 13:38:39.032306 EC interrupt | 0x00000005 | low | undefined
9371 13:38:39.038299 TPM interrupt | 0x000000ab | high | undefined
9372 13:38:39.042054 SD card detect | 0x00000011 | high | undefined
9373 13:38:39.045288 speaker enable | 0x00000093 | high | undefined
9374 13:38:39.051882 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9375 13:38:39.055242 in-header: 03 f9 00 00 02 00 00 00
9376 13:38:39.055317 in-data: 02 00
9377 13:38:39.058487 ADC[4]: Raw value=903325 ID=7
9378 13:38:39.061827 ADC[3]: Raw value=213916 ID=1
9379 13:38:39.061898 RAM Code: 0x71
9380 13:38:39.064856 ADC[6]: Raw value=74630 ID=0
9381 13:38:39.068198 ADC[5]: Raw value=213177 ID=1
9382 13:38:39.068271 SKU Code: 0x1
9383 13:38:39.074919 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 908b
9384 13:38:39.078173 coreboot table: 964 bytes.
9385 13:38:39.081036 IMD ROOT 0. 0xfffff000 0x00001000
9386 13:38:39.084721 IMD SMALL 1. 0xffffe000 0x00001000
9387 13:38:39.088073 RO MCACHE 2. 0xffffc000 0x00001104
9388 13:38:39.091260 CONSOLE 3. 0xfff7c000 0x00080000
9389 13:38:39.094468 FMAP 4. 0xfff7b000 0x00000452
9390 13:38:39.097807 TIME STAMP 5. 0xfff7a000 0x00000910
9391 13:38:39.101083 VBOOT WORK 6. 0xfff66000 0x00014000
9392 13:38:39.104418 RAMOOPS 7. 0xffe66000 0x00100000
9393 13:38:39.107822 COREBOOT 8. 0xffe64000 0x00002000
9394 13:38:39.107907 IMD small region:
9395 13:38:39.110941 IMD ROOT 0. 0xffffec00 0x00000400
9396 13:38:39.114101 VPD 1. 0xffffeb80 0x0000006c
9397 13:38:39.117240 MMC STATUS 2. 0xffffeb60 0x00000004
9398 13:38:39.123744 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9399 13:38:39.130129 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9400 13:38:39.169979 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9401 13:38:39.173075 Checking segment from ROM address 0x40100000
9402 13:38:39.179490 Checking segment from ROM address 0x4010001c
9403 13:38:39.182634 Loading segment from ROM address 0x40100000
9404 13:38:39.182715 code (compression=0)
9405 13:38:39.192614 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9406 13:38:39.199599 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9407 13:38:39.199686 it's not compressed!
9408 13:38:39.205916 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9409 13:38:39.212561 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9410 13:38:39.229940 Loading segment from ROM address 0x4010001c
9411 13:38:39.230059 Entry Point 0x80000000
9412 13:38:39.233562 Loaded segments
9413 13:38:39.237122 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9414 13:38:39.243169 Jumping to boot code at 0x80000000(0xffe64000)
9415 13:38:39.250120 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9416 13:38:39.256614 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9417 13:38:39.264458 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9418 13:38:39.267807 Checking segment from ROM address 0x40100000
9419 13:38:39.271077 Checking segment from ROM address 0x4010001c
9420 13:38:39.277565 Loading segment from ROM address 0x40100000
9421 13:38:39.277656 code (compression=1)
9422 13:38:39.284807 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9423 13:38:39.294586 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9424 13:38:39.294706 using LZMA
9425 13:38:39.302989 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9426 13:38:39.309572 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9427 13:38:39.313067 Loading segment from ROM address 0x4010001c
9428 13:38:39.313156 Entry Point 0x54601000
9429 13:38:39.316536 Loaded segments
9430 13:38:39.319555 NOTICE: MT8192 bl31_setup
9431 13:38:39.326855 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9432 13:38:39.329854 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9433 13:38:39.333076 WARNING: region 0:
9434 13:38:39.336229 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 13:38:39.336315 WARNING: region 1:
9436 13:38:39.342848 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9437 13:38:39.346054 WARNING: region 2:
9438 13:38:39.349691 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9439 13:38:39.352703 WARNING: region 3:
9440 13:38:39.359415 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 13:38:39.359512 WARNING: region 4:
9442 13:38:39.366101 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 13:38:39.366199 WARNING: region 5:
9444 13:38:39.369166 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 13:38:39.372567 WARNING: region 6:
9446 13:38:39.376215 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 13:38:39.379358 WARNING: region 7:
9448 13:38:39.382719 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 13:38:39.389365 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9450 13:38:39.392479 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9451 13:38:39.399074 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9452 13:38:39.402995 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9453 13:38:39.406205 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9454 13:38:39.412215 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9455 13:38:39.416180 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9456 13:38:39.418655 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9457 13:38:39.425770 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9458 13:38:39.428551 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9459 13:38:39.435373 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9460 13:38:39.438704 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9461 13:38:39.441918 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9462 13:38:39.449089 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9463 13:38:39.451520 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9464 13:38:39.458496 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9465 13:38:39.461794 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9466 13:38:39.465487 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9467 13:38:39.471872 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9468 13:38:39.475190 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9469 13:38:39.481699 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9470 13:38:39.484892 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9471 13:38:39.488205 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9472 13:38:39.494615 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9473 13:38:39.497844 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9474 13:38:39.504468 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9475 13:38:39.507696 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9476 13:38:39.511032 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9477 13:38:39.517777 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9478 13:38:39.520938 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9479 13:38:39.528007 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9480 13:38:39.531313 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9481 13:38:39.534554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9482 13:38:39.541201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9483 13:38:39.544178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9484 13:38:39.547320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9485 13:38:39.550908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9486 13:38:39.557044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9487 13:38:39.560824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9488 13:38:39.564092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9489 13:38:39.567587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9490 13:38:39.573666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9491 13:38:39.577430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9492 13:38:39.580570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9493 13:38:39.583816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9494 13:38:39.590209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9495 13:38:39.593578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9496 13:38:39.596926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9497 13:38:39.603379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9498 13:38:39.606864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9499 13:38:39.614010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9500 13:38:39.616581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9501 13:38:39.620007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9502 13:38:39.626628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9503 13:38:39.629949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9504 13:38:39.636561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9505 13:38:39.640221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9506 13:38:39.646747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9507 13:38:39.650025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9508 13:38:39.653354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9509 13:38:39.659860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9510 13:38:39.663098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9511 13:38:39.669386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9512 13:38:39.672873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9513 13:38:39.679524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9514 13:38:39.682938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9515 13:38:39.689518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9516 13:38:39.692463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9517 13:38:39.699031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9518 13:38:39.702605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9519 13:38:39.706221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9520 13:38:39.712818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9521 13:38:39.715446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9522 13:38:39.722217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9523 13:38:39.725487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9524 13:38:39.732105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9525 13:38:39.735361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9526 13:38:39.741999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9527 13:38:39.745185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9528 13:38:39.749295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9529 13:38:39.755250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9530 13:38:39.758589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9531 13:38:39.765061 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9532 13:38:39.768406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9533 13:38:39.775009 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9534 13:38:39.778313 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9535 13:38:39.784824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9536 13:38:39.788033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9537 13:38:39.791751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9538 13:38:39.797802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9539 13:38:39.801292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9540 13:38:39.807995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9541 13:38:39.810996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9542 13:38:39.818026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9543 13:38:39.821215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9544 13:38:39.827794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9545 13:38:39.830812 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9546 13:38:39.834079 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9547 13:38:39.837411 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9548 13:38:39.844100 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9549 13:38:39.847146 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9550 13:38:39.850401 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9551 13:38:39.857597 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9552 13:38:39.860961 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9553 13:38:39.866959 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9554 13:38:39.870820 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9555 13:38:39.877299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9556 13:38:39.880575 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9557 13:38:39.883945 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9558 13:38:39.890458 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9559 13:38:39.893892 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9560 13:38:39.900778 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9561 13:38:39.903320 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9562 13:38:39.906606 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9563 13:38:39.913966 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9564 13:38:39.917085 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9565 13:38:39.919962 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9566 13:38:39.926791 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9567 13:38:39.930119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9568 13:38:39.933462 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9569 13:38:39.940001 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9570 13:38:39.943051 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9571 13:38:39.946597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9572 13:38:39.949423 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9573 13:38:39.956151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9574 13:38:39.959856 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9575 13:38:39.965967 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9576 13:38:39.969758 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9577 13:38:39.972776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9578 13:38:39.979436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9579 13:38:39.983008 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9580 13:38:39.989220 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9581 13:38:39.992533 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9582 13:38:39.995876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9583 13:38:40.002649 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9584 13:38:40.005866 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9585 13:38:40.012519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9586 13:38:40.015869 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9587 13:38:40.019006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9588 13:38:40.025600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9589 13:38:40.028859 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9590 13:38:40.035180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9591 13:38:40.038459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9592 13:38:40.041839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9593 13:38:40.048238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9594 13:38:40.052460 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9595 13:38:40.058186 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9596 13:38:40.061332 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9597 13:38:40.064687 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9598 13:38:40.071435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9599 13:38:40.074746 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9600 13:38:40.081265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9601 13:38:40.084994 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9602 13:38:40.087769 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9603 13:38:40.094460 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9604 13:38:40.098297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9605 13:38:40.105096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9606 13:38:40.107546 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9607 13:38:40.111535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9608 13:38:40.117597 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9609 13:38:40.120736 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9610 13:38:40.127724 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9611 13:38:40.130981 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9612 13:38:40.133926 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9613 13:38:40.140661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9614 13:38:40.144017 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9615 13:38:40.150562 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9616 13:38:40.154078 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9617 13:38:40.156940 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9618 13:38:40.163756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9619 13:38:40.167033 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9620 13:38:40.173470 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9621 13:38:40.176829 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9622 13:38:40.180293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9623 13:38:40.186895 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9624 13:38:40.190228 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9625 13:38:40.196422 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9626 13:38:40.199979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9627 13:38:40.206632 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9628 13:38:40.209799 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9629 13:38:40.213330 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9630 13:38:40.219882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9631 13:38:40.223245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9632 13:38:40.226455 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9633 13:38:40.232757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9634 13:38:40.236455 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9635 13:38:40.242896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9636 13:38:40.246603 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9637 13:38:40.249329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9638 13:38:40.256537 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9639 13:38:40.259756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9640 13:38:40.266269 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9641 13:38:40.269672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9642 13:38:40.276176 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9643 13:38:40.279597 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9644 13:38:40.283224 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9645 13:38:40.289648 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9646 13:38:40.293026 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9647 13:38:40.299351 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9648 13:38:40.302750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9649 13:38:40.309371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9650 13:38:40.312723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9651 13:38:40.315958 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9652 13:38:40.322370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9653 13:38:40.325594 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9654 13:38:40.332368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9655 13:38:40.335576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9656 13:38:40.339067 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9657 13:38:40.345742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9658 13:38:40.348821 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9659 13:38:40.355326 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9660 13:38:40.358565 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9661 13:38:40.364997 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9662 13:38:40.368445 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9663 13:38:40.371656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9664 13:38:40.378364 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9665 13:38:40.381591 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9666 13:38:40.388263 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9667 13:38:40.391764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9668 13:38:40.398306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9669 13:38:40.401445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9670 13:38:40.405039 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9671 13:38:40.411459 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9672 13:38:40.414917 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9673 13:38:40.420953 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9674 13:38:40.424212 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9675 13:38:40.431313 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9676 13:38:40.434640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9677 13:38:40.437963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9678 13:38:40.444548 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9679 13:38:40.447828 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9680 13:38:40.450775 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9681 13:38:40.454137 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9682 13:38:40.460858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9683 13:38:40.464343 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9684 13:38:40.467533 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9685 13:38:40.473796 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9686 13:38:40.476933 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9687 13:38:40.480372 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9688 13:38:40.487087 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9689 13:38:40.490435 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9690 13:38:40.497099 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9691 13:38:40.499960 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9692 13:38:40.504026 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9693 13:38:40.510032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9694 13:38:40.513796 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9695 13:38:40.520169 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9696 13:38:40.523569 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9697 13:38:40.526786 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9698 13:38:40.533682 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9699 13:38:40.536458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9700 13:38:40.540316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9701 13:38:40.546929 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9702 13:38:40.549849 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9703 13:38:40.552879 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9704 13:38:40.559566 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9705 13:38:40.562797 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9706 13:38:40.569527 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9707 13:38:40.573165 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9708 13:38:40.576288 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9709 13:38:40.582941 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9710 13:38:40.586270 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9711 13:38:40.592800 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9712 13:38:40.596306 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9713 13:38:40.599494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9714 13:38:40.606076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9715 13:38:40.609130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9716 13:38:40.612577 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9717 13:38:40.618934 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9718 13:38:40.622399 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9719 13:38:40.625558 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9720 13:38:40.628860 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9721 13:38:40.635584 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9722 13:38:40.639377 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9723 13:38:40.642146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9724 13:38:40.645591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9725 13:38:40.652453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9726 13:38:40.656177 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9727 13:38:40.659173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9728 13:38:40.661918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9729 13:38:40.669192 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9730 13:38:40.672583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9731 13:38:40.675683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9732 13:38:40.681694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9733 13:38:40.685094 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9734 13:38:40.691812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9735 13:38:40.695491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9736 13:38:40.701725 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9737 13:38:40.705004 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9738 13:38:40.708472 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9739 13:38:40.715001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9740 13:38:40.718336 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9741 13:38:40.724817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9742 13:38:40.728455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9743 13:38:40.731877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9744 13:38:40.738484 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9745 13:38:40.741744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9746 13:38:40.747877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9747 13:38:40.751069 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9748 13:38:40.754405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9749 13:38:40.761065 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9750 13:38:40.764157 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9751 13:38:40.771224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9752 13:38:40.774337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9753 13:38:40.780941 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9754 13:38:40.784278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9755 13:38:40.787573 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9756 13:38:40.794297 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9757 13:38:40.797569 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9758 13:38:40.804378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9759 13:38:40.807439 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9760 13:38:40.813904 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9761 13:38:40.817167 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9762 13:38:40.820484 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9763 13:38:40.826975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9764 13:38:40.830279 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9765 13:38:40.837052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9766 13:38:40.840398 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9767 13:38:40.843530 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9768 13:38:40.850865 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9769 13:38:40.853473 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9770 13:38:40.860088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9771 13:38:40.863393 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9772 13:38:40.866579 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9773 13:38:40.873731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9774 13:38:40.876880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9775 13:38:40.883280 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9776 13:38:40.886471 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9777 13:38:40.893239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9778 13:38:40.896305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9779 13:38:40.899786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9780 13:38:40.906305 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9781 13:38:40.909374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9782 13:38:40.915953 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9783 13:38:40.919737 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9784 13:38:40.926273 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9785 13:38:40.929823 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9786 13:38:40.932922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9787 13:38:40.939424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9788 13:38:40.942610 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9789 13:38:40.949732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9790 13:38:40.952435 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9791 13:38:40.955928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9792 13:38:40.962342 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9793 13:38:40.965636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9794 13:38:40.972336 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9795 13:38:40.975742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9796 13:38:40.979094 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9797 13:38:40.985650 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9798 13:38:40.988759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9799 13:38:40.995943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9800 13:38:40.999052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9801 13:38:41.005441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9802 13:38:41.008792 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9803 13:38:41.011974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9804 13:38:41.018494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9805 13:38:41.021865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9806 13:38:41.028895 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9807 13:38:41.032149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9808 13:38:41.038724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9809 13:38:41.041855 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9810 13:38:41.045245 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9811 13:38:41.051439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9812 13:38:41.054770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9813 13:38:41.061384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9814 13:38:41.064630 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9815 13:38:41.071483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9816 13:38:41.074842 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9817 13:38:41.081452 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9818 13:38:41.085085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9819 13:38:41.088159 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9820 13:38:41.094672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9821 13:38:41.097968 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9822 13:38:41.104284 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9823 13:38:41.107475 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9824 13:38:41.114418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9825 13:38:41.117634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9826 13:38:41.124131 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9827 13:38:41.127294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9828 13:38:41.133826 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9829 13:38:41.137046 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9830 13:38:41.140915 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9831 13:38:41.147375 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9832 13:38:41.150648 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9833 13:38:41.156993 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9834 13:38:41.160049 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9835 13:38:41.167057 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9836 13:38:41.170430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9837 13:38:41.176350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9838 13:38:41.179716 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9839 13:38:41.186332 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9840 13:38:41.190195 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9841 13:38:41.192817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9842 13:38:41.199972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9843 13:38:41.203236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9844 13:38:41.209694 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9845 13:38:41.212894 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9846 13:38:41.219522 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9847 13:38:41.222619 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9848 13:38:41.229693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9849 13:38:41.232878 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9850 13:38:41.236025 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9851 13:38:41.242556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9852 13:38:41.245801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9853 13:38:41.252322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9854 13:38:41.255611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9855 13:38:41.262014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9856 13:38:41.265421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9857 13:38:41.271926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9858 13:38:41.275588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9859 13:38:41.281919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9860 13:38:41.285268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9861 13:38:41.292041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9862 13:38:41.295254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9863 13:38:41.301884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9864 13:38:41.305140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9865 13:38:41.311603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9866 13:38:41.314808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9867 13:38:41.321237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9868 13:38:41.324447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9869 13:38:41.331024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9870 13:38:41.334906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9871 13:38:41.341185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9872 13:38:41.344584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9873 13:38:41.350947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9874 13:38:41.354336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9875 13:38:41.360655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9876 13:38:41.363837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9877 13:38:41.370585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9878 13:38:41.373999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9879 13:38:41.380394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9880 13:38:41.383562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9881 13:38:41.390579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9882 13:38:41.393442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9883 13:38:41.396695 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9884 13:38:41.399954 INFO: [APUAPC] vio 0
9885 13:38:41.406583 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9886 13:38:41.409839 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9887 13:38:41.413196 INFO: [APUAPC] D0_APC_0: 0x400510
9888 13:38:41.416597 INFO: [APUAPC] D0_APC_1: 0x0
9889 13:38:41.419794 INFO: [APUAPC] D0_APC_2: 0x1540
9890 13:38:41.423478 INFO: [APUAPC] D0_APC_3: 0x0
9891 13:38:41.426672 INFO: [APUAPC] D1_APC_0: 0xffffffff
9892 13:38:41.429756 INFO: [APUAPC] D1_APC_1: 0xffffffff
9893 13:38:41.433336 INFO: [APUAPC] D1_APC_2: 0x3fffff
9894 13:38:41.436296 INFO: [APUAPC] D1_APC_3: 0x0
9895 13:38:41.439532 INFO: [APUAPC] D2_APC_0: 0xffffffff
9896 13:38:41.442698 INFO: [APUAPC] D2_APC_1: 0xffffffff
9897 13:38:41.446008 INFO: [APUAPC] D2_APC_2: 0x3fffff
9898 13:38:41.449510 INFO: [APUAPC] D2_APC_3: 0x0
9899 13:38:41.452771 INFO: [APUAPC] D3_APC_0: 0xffffffff
9900 13:38:41.455901 INFO: [APUAPC] D3_APC_1: 0xffffffff
9901 13:38:41.459210 INFO: [APUAPC] D3_APC_2: 0x3fffff
9902 13:38:41.462693 INFO: [APUAPC] D3_APC_3: 0x0
9903 13:38:41.466039 INFO: [APUAPC] D4_APC_0: 0xffffffff
9904 13:38:41.469449 INFO: [APUAPC] D4_APC_1: 0xffffffff
9905 13:38:41.472928 INFO: [APUAPC] D4_APC_2: 0x3fffff
9906 13:38:41.476020 INFO: [APUAPC] D4_APC_3: 0x0
9907 13:38:41.479313 INFO: [APUAPC] D5_APC_0: 0xffffffff
9908 13:38:41.482639 INFO: [APUAPC] D5_APC_1: 0xffffffff
9909 13:38:41.485972 INFO: [APUAPC] D5_APC_2: 0x3fffff
9910 13:38:41.489190 INFO: [APUAPC] D5_APC_3: 0x0
9911 13:38:41.492673 INFO: [APUAPC] D6_APC_0: 0xffffffff
9912 13:38:41.495543 INFO: [APUAPC] D6_APC_1: 0xffffffff
9913 13:38:41.499375 INFO: [APUAPC] D6_APC_2: 0x3fffff
9914 13:38:41.499481 INFO: [APUAPC] D6_APC_3: 0x0
9915 13:38:41.505829 INFO: [APUAPC] D7_APC_0: 0xffffffff
9916 13:38:41.508822 INFO: [APUAPC] D7_APC_1: 0xffffffff
9917 13:38:41.512284 INFO: [APUAPC] D7_APC_2: 0x3fffff
9918 13:38:41.512423 INFO: [APUAPC] D7_APC_3: 0x0
9919 13:38:41.515544 INFO: [APUAPC] D8_APC_0: 0xffffffff
9920 13:38:41.522216 INFO: [APUAPC] D8_APC_1: 0xffffffff
9921 13:38:41.525532 INFO: [APUAPC] D8_APC_2: 0x3fffff
9922 13:38:41.525676 INFO: [APUAPC] D8_APC_3: 0x0
9923 13:38:41.528737 INFO: [APUAPC] D9_APC_0: 0xffffffff
9924 13:38:41.531822 INFO: [APUAPC] D9_APC_1: 0xffffffff
9925 13:38:41.535148 INFO: [APUAPC] D9_APC_2: 0x3fffff
9926 13:38:41.538435 INFO: [APUAPC] D9_APC_3: 0x0
9927 13:38:41.541620 INFO: [APUAPC] D10_APC_0: 0xffffffff
9928 13:38:41.544796 INFO: [APUAPC] D10_APC_1: 0xffffffff
9929 13:38:41.551799 INFO: [APUAPC] D10_APC_2: 0x3fffff
9930 13:38:41.551946 INFO: [APUAPC] D10_APC_3: 0x0
9931 13:38:41.555117 INFO: [APUAPC] D11_APC_0: 0xffffffff
9932 13:38:41.561814 INFO: [APUAPC] D11_APC_1: 0xffffffff
9933 13:38:41.565090 INFO: [APUAPC] D11_APC_2: 0x3fffff
9934 13:38:41.565226 INFO: [APUAPC] D11_APC_3: 0x0
9935 13:38:41.571220 INFO: [APUAPC] D12_APC_0: 0xffffffff
9936 13:38:41.574985 INFO: [APUAPC] D12_APC_1: 0xffffffff
9937 13:38:41.577729 INFO: [APUAPC] D12_APC_2: 0x3fffff
9938 13:38:41.580982 INFO: [APUAPC] D12_APC_3: 0x0
9939 13:38:41.584373 INFO: [APUAPC] D13_APC_0: 0xffffffff
9940 13:38:41.587860 INFO: [APUAPC] D13_APC_1: 0xffffffff
9941 13:38:41.590985 INFO: [APUAPC] D13_APC_2: 0x3fffff
9942 13:38:41.594368 INFO: [APUAPC] D13_APC_3: 0x0
9943 13:38:41.597637 INFO: [APUAPC] D14_APC_0: 0xffffffff
9944 13:38:41.601111 INFO: [APUAPC] D14_APC_1: 0xffffffff
9945 13:38:41.604187 INFO: [APUAPC] D14_APC_2: 0x3fffff
9946 13:38:41.607480 INFO: [APUAPC] D14_APC_3: 0x0
9947 13:38:41.610792 INFO: [APUAPC] D15_APC_0: 0xffffffff
9948 13:38:41.614094 INFO: [APUAPC] D15_APC_1: 0xffffffff
9949 13:38:41.617444 INFO: [APUAPC] D15_APC_2: 0x3fffff
9950 13:38:41.620375 INFO: [APUAPC] D15_APC_3: 0x0
9951 13:38:41.623471 INFO: [APUAPC] APC_CON: 0x4
9952 13:38:41.623573 INFO: [NOCDAPC] D0_APC_0: 0x0
9953 13:38:41.627320 INFO: [NOCDAPC] D0_APC_1: 0x0
9954 13:38:41.630409 INFO: [NOCDAPC] D1_APC_0: 0x0
9955 13:38:41.633688 INFO: [NOCDAPC] D1_APC_1: 0xfff
9956 13:38:41.636936 INFO: [NOCDAPC] D2_APC_0: 0x0
9957 13:38:41.639979 INFO: [NOCDAPC] D2_APC_1: 0xfff
9958 13:38:41.643866 INFO: [NOCDAPC] D3_APC_0: 0x0
9959 13:38:41.647143 INFO: [NOCDAPC] D3_APC_1: 0xfff
9960 13:38:41.650253 INFO: [NOCDAPC] D4_APC_0: 0x0
9961 13:38:41.653554 INFO: [NOCDAPC] D4_APC_1: 0xfff
9962 13:38:41.656635 INFO: [NOCDAPC] D5_APC_0: 0x0
9963 13:38:41.660124 INFO: [NOCDAPC] D5_APC_1: 0xfff
9964 13:38:41.660228 INFO: [NOCDAPC] D6_APC_0: 0x0
9965 13:38:41.663363 INFO: [NOCDAPC] D6_APC_1: 0xfff
9966 13:38:41.666530 INFO: [NOCDAPC] D7_APC_0: 0x0
9967 13:38:41.670019 INFO: [NOCDAPC] D7_APC_1: 0xfff
9968 13:38:41.673265 INFO: [NOCDAPC] D8_APC_0: 0x0
9969 13:38:41.676580 INFO: [NOCDAPC] D8_APC_1: 0xfff
9970 13:38:41.679788 INFO: [NOCDAPC] D9_APC_0: 0x0
9971 13:38:41.683025 INFO: [NOCDAPC] D9_APC_1: 0xfff
9972 13:38:41.686289 INFO: [NOCDAPC] D10_APC_0: 0x0
9973 13:38:41.689470 INFO: [NOCDAPC] D10_APC_1: 0xfff
9974 13:38:41.692940 INFO: [NOCDAPC] D11_APC_0: 0x0
9975 13:38:41.696295 INFO: [NOCDAPC] D11_APC_1: 0xfff
9976 13:38:41.699488 INFO: [NOCDAPC] D12_APC_0: 0x0
9977 13:38:41.702901 INFO: [NOCDAPC] D12_APC_1: 0xfff
9978 13:38:41.703001 INFO: [NOCDAPC] D13_APC_0: 0x0
9979 13:38:41.706341 INFO: [NOCDAPC] D13_APC_1: 0xfff
9980 13:38:41.709716 INFO: [NOCDAPC] D14_APC_0: 0x0
9981 13:38:41.713062 INFO: [NOCDAPC] D14_APC_1: 0xfff
9982 13:38:41.716449 INFO: [NOCDAPC] D15_APC_0: 0x0
9983 13:38:41.719727 INFO: [NOCDAPC] D15_APC_1: 0xfff
9984 13:38:41.722537 INFO: [NOCDAPC] APC_CON: 0x4
9985 13:38:41.726286 INFO: [APUAPC] set_apusys_apc done
9986 13:38:41.729464 INFO: [DEVAPC] devapc_init done
9987 13:38:41.732430 INFO: GICv3 without legacy support detected.
9988 13:38:41.735962 INFO: ARM GICv3 driver initialized in EL3
9989 13:38:41.742252 INFO: Maximum SPI INTID supported: 639
9990 13:38:41.745510 INFO: BL31: Initializing runtime services
9991 13:38:41.752731 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9992 13:38:41.752855 INFO: SPM: enable CPC mode
9993 13:38:41.759290 INFO: mcdi ready for mcusys-off-idle and system suspend
9994 13:38:41.762675 INFO: BL31: Preparing for EL3 exit to normal world
9995 13:38:41.765713 INFO: Entry point address = 0x80000000
9996 13:38:41.768700 INFO: SPSR = 0x8
9997 13:38:41.775018
9998 13:38:41.775127
9999 13:38:41.775194
10000 13:38:41.778222 Starting depthcharge on Spherion...
10001 13:38:41.778309
10002 13:38:41.778374 Wipe memory regions:
10003 13:38:41.778434
10004 13:38:41.779013 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10005 13:38:41.779112 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10006 13:38:41.779195 Setting prompt string to ['asurada:']
10007 13:38:41.779272 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10008 13:38:41.781528 [0x00000040000000, 0x00000054600000)
10009 13:38:41.904079
10010 13:38:41.904221 [0x00000054660000, 0x00000080000000)
10011 13:38:42.164246
10012 13:38:42.164389 [0x000000821a7280, 0x000000ffe64000)
10013 13:38:42.909202
10014 13:38:42.909365 [0x00000100000000, 0x00000240000000)
10015 13:38:44.799547
10016 13:38:44.802542 Initializing XHCI USB controller at 0x11200000.
10017 13:38:45.840604
10018 13:38:45.843775 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10019 13:38:45.843872
10020 13:38:45.843939
10021 13:38:45.844227 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 13:38:45.944618 asurada: tftpboot 192.168.201.1 14063027/tftp-deploy-jw8mi1o4/kernel/image.itb 14063027/tftp-deploy-jw8mi1o4/kernel/cmdline
10024 13:38:45.944779 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 13:38:45.944892 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10026 13:38:45.949482 tftpboot 192.168.201.1 14063027/tftp-deploy-jw8mi1o4/kernel/image.ittp-deploy-jw8mi1o4/kernel/cmdline
10027 13:38:45.949576
10028 13:38:45.949644 Waiting for link
10029 13:38:46.107335
10030 13:38:46.107493 R8152: Initializing
10031 13:38:46.107593
10032 13:38:46.110464 Version 6 (ocp_data = 5c30)
10033 13:38:46.110549
10034 13:38:46.113858 R8152: Done initializing
10035 13:38:46.114016
10036 13:38:46.114107 Adding net device
10037 13:38:48.066405
10038 13:38:48.066543 done.
10039 13:38:48.066610
10040 13:38:48.066671 MAC: 00:24:32:30:7c:7b
10041 13:38:48.066730
10042 13:38:48.069863 Sending DHCP discover... done.
10043 13:38:48.069955
10044 13:38:48.072969 Waiting for reply... done.
10045 13:38:48.073064
10046 13:38:48.076422 Sending DHCP request... done.
10047 13:38:48.076514
10048 13:38:48.080314 Waiting for reply... done.
10049 13:38:48.080401
10050 13:38:48.080486 My ip is 192.168.201.14
10051 13:38:48.080568
10052 13:38:48.083587 The DHCP server ip is 192.168.201.1
10053 13:38:48.083673
10054 13:38:48.090082 TFTP server IP predefined by user: 192.168.201.1
10055 13:38:48.090168
10056 13:38:48.096691 Bootfile predefined by user: 14063027/tftp-deploy-jw8mi1o4/kernel/image.itb
10057 13:38:48.096847
10058 13:38:48.100039 Sending tftp read request... done.
10059 13:38:48.100146
10060 13:38:48.103861 Waiting for the transfer...
10061 13:38:48.103943
10062 13:38:48.663220 00000000 ################################################################
10063 13:38:48.663363
10064 13:38:49.298042 00080000 ################################################################
10065 13:38:49.298179
10066 13:38:49.898643 00100000 ################################################################
10067 13:38:49.898778
10068 13:38:50.456623 00180000 ################################################################
10069 13:38:50.456778
10070 13:38:51.008914 00200000 ################################################################
10071 13:38:51.009044
10072 13:38:51.559615 00280000 ################################################################
10073 13:38:51.559752
10074 13:38:52.081098 00300000 ################################################################
10075 13:38:52.081239
10076 13:38:52.610545 00380000 ################################################################
10077 13:38:52.610685
10078 13:38:53.123393 00400000 ################################################################
10079 13:38:53.123532
10080 13:38:53.642382 00480000 ################################################################
10081 13:38:53.642607
10082 13:38:54.241855 00500000 ################################################################
10083 13:38:54.241990
10084 13:38:54.774296 00580000 ################################################################
10085 13:38:54.774437
10086 13:38:55.294015 00600000 ################################################################
10087 13:38:55.294153
10088 13:38:55.816080 00680000 ################################################################
10089 13:38:55.816243
10090 13:38:56.335893 00700000 ################################################################
10091 13:38:56.336038
10092 13:38:56.861896 00780000 ################################################################
10093 13:38:56.862058
10094 13:38:57.388523 00800000 ################################################################
10095 13:38:57.388665
10096 13:38:58.232114 00880000 ################################################################
10097 13:38:58.232402
10098 13:38:58.439889 00900000 ################################################################
10099 13:38:58.440078
10100 13:38:58.970538 00980000 ################################################################
10101 13:38:58.970678
10102 13:38:59.503254 00a00000 ################################################################
10103 13:38:59.503427
10104 13:39:00.037794 00a80000 ################################################################
10105 13:39:00.037959
10106 13:39:00.556818 00b00000 ################################################################
10107 13:39:00.556983
10108 13:39:01.074093 00b80000 ################################################################
10109 13:39:01.074229
10110 13:39:01.595405 00c00000 ################################################################
10111 13:39:01.595582
10112 13:39:02.115645 00c80000 ################################################################
10113 13:39:02.115814
10114 13:39:02.636686 00d00000 ################################################################
10115 13:39:02.636823
10116 13:39:03.155854 00d80000 ################################################################
10117 13:39:03.156025
10118 13:39:03.682831 00e00000 ################################################################
10119 13:39:03.682964
10120 13:39:04.198896 00e80000 ################################################################
10121 13:39:04.199059
10122 13:39:04.715967 00f00000 ################################################################
10123 13:39:04.716103
10124 13:39:05.230837 00f80000 ################################################################
10125 13:39:05.231012
10126 13:39:05.772872 01000000 ################################################################
10127 13:39:05.773048
10128 13:39:06.429387 01080000 ################################################################
10129 13:39:06.429888
10130 13:39:07.097006 01100000 ################################################################
10131 13:39:07.097547
10132 13:39:07.696488 01180000 ################################################################
10133 13:39:07.696649
10134 13:39:08.239203 01200000 ################################################################
10135 13:39:08.239336
10136 13:39:08.781720 01280000 ################################################################
10137 13:39:08.781858
10138 13:39:09.332233 01300000 ################################################################
10139 13:39:09.332367
10140 13:39:09.889620 01380000 ################################################################
10141 13:39:09.889753
10142 13:39:10.491102 01400000 ################################################################
10143 13:39:10.491249
10144 13:39:11.065139 01480000 ################################################################
10145 13:39:11.065353
10146 13:39:11.730575 01500000 ################################################################
10147 13:39:11.731069
10148 13:39:12.282902 01580000 ################################################################
10149 13:39:12.283032
10150 13:39:12.831485 01600000 ################################################################
10151 13:39:12.831622
10152 13:39:13.370093 01680000 ################################################################
10153 13:39:13.370281
10154 13:39:13.910725 01700000 ################################################################
10155 13:39:13.910909
10156 13:39:14.471589 01780000 ################################################################
10157 13:39:14.471729
10158 13:39:15.023726 01800000 ################################################################
10159 13:39:15.023896
10160 13:39:15.587174 01880000 ################################################################
10161 13:39:15.587315
10162 13:39:16.129510 01900000 ################################################################
10163 13:39:16.129669
10164 13:39:16.715742 01980000 ################################################################
10165 13:39:16.715886
10166 13:39:17.301240 01a00000 ################################################################
10167 13:39:17.301803
10168 13:39:17.905883 01a80000 ################################################################
10169 13:39:17.906015
10170 13:39:18.456245 01b00000 ################################################################
10171 13:39:18.456389
10172 13:39:19.002299 01b80000 ################################################################
10173 13:39:19.002446
10174 13:39:19.557315 01c00000 ################################################################
10175 13:39:19.557448
10176 13:39:20.105062 01c80000 ################################################################
10177 13:39:20.105230
10178 13:39:20.639141 01d00000 ################################################################
10179 13:39:20.639284
10180 13:39:21.166224 01d80000 ################################################################
10181 13:39:21.166362
10182 13:39:21.693800 01e00000 ################################################################
10183 13:39:21.693935
10184 13:39:22.219446 01e80000 ################################################################
10185 13:39:22.219586
10186 13:39:22.747464 01f00000 ################################################################
10187 13:39:22.747622
10188 13:39:23.285505 01f80000 ################################################################
10189 13:39:23.285642
10190 13:39:23.816763 02000000 ################################################################
10191 13:39:23.816924
10192 13:39:24.356368 02080000 ################################################################
10193 13:39:24.356505
10194 13:39:24.899082 02100000 ################################################################
10195 13:39:24.899236
10196 13:39:25.434254 02180000 ################################################################
10197 13:39:25.434403
10198 13:39:25.961207 02200000 ################################################################
10199 13:39:25.961367
10200 13:39:26.483303 02280000 ################################################################
10201 13:39:26.483437
10202 13:39:27.012533 02300000 ################################################################
10203 13:39:27.012661
10204 13:39:27.537238 02380000 ################################################################
10205 13:39:27.537391
10206 13:39:28.073043 02400000 ################################################################
10207 13:39:28.073174
10208 13:39:28.614892 02480000 ################################################################
10209 13:39:28.615096
10210 13:39:29.158329 02500000 ################################################################
10211 13:39:29.158499
10212 13:39:29.694840 02580000 ################################################################
10213 13:39:29.694973
10214 13:39:30.245192 02600000 ################################################################
10215 13:39:30.245403
10216 13:39:30.784763 02680000 ################################################################
10217 13:39:30.784895
10218 13:39:31.335510 02700000 ################################################################
10219 13:39:31.335647
10220 13:39:31.864642 02780000 ################################################################
10221 13:39:31.864776
10222 13:39:32.405355 02800000 ################################################################
10223 13:39:32.405495
10224 13:39:32.935560 02880000 ################################################################
10225 13:39:32.935695
10226 13:39:33.480852 02900000 ################################################################
10227 13:39:33.481016
10228 13:39:34.048639 02980000 ################################################################
10229 13:39:34.048784
10230 13:39:34.591052 02a00000 ################################################################
10231 13:39:34.591203
10232 13:39:35.144713 02a80000 ################################################################
10233 13:39:35.144880
10234 13:39:35.691324 02b00000 ################################################################
10235 13:39:35.691473
10236 13:39:36.219560 02b80000 ################################################################
10237 13:39:36.219734
10238 13:39:36.774900 02c00000 ################################################################
10239 13:39:36.775072
10240 13:39:37.331184 02c80000 ################################################################
10241 13:39:37.331333
10242 13:39:37.905310 02d00000 ################################################################
10243 13:39:37.905444
10244 13:39:38.496816 02d80000 ################################################################
10245 13:39:38.496950
10246 13:39:39.090115 02e00000 ################################################################
10247 13:39:39.090248
10248 13:39:39.646520 02e80000 ################################################################
10249 13:39:39.646685
10250 13:39:40.246949 02f00000 ################################################################
10251 13:39:40.247086
10252 13:39:40.809433 02f80000 ################################################################
10253 13:39:40.809569
10254 13:39:41.376139 03000000 ################################################################
10255 13:39:41.376302
10256 13:39:41.937824 03080000 ################################################################
10257 13:39:41.937986
10258 13:39:42.544137 03100000 ################################################################
10259 13:39:42.544272
10260 13:39:43.188669 03180000 ################################################################
10261 13:39:43.188817
10262 13:39:43.856211 03200000 ################################################################
10263 13:39:43.856371
10264 13:39:44.553133 03280000 ################################################################
10265 13:39:44.553316
10266 13:39:45.195335 03300000 ################################################################
10267 13:39:45.195877
10268 13:39:45.839856 03380000 ################################################################
10269 13:39:45.840020
10270 13:39:46.488385 03400000 ################################################################
10271 13:39:46.488891
10272 13:39:47.102015 03480000 ################################################################
10273 13:39:47.102205
10274 13:39:47.711182 03500000 ################################################################
10275 13:39:47.711311
10276 13:39:48.384096 03580000 ################################################################
10277 13:39:48.384587
10278 13:39:48.981169 03600000 ################################################################
10279 13:39:48.981329
10280 13:39:49.546628 03680000 ################################################################
10281 13:39:49.546799
10282 13:39:50.124657 03700000 ################################################################
10283 13:39:50.124796
10284 13:39:50.698926 03780000 ################################################################
10285 13:39:50.699074
10286 13:39:51.273417 03800000 ################################################################
10287 13:39:51.273601
10288 13:39:51.841677 03880000 ################################################################
10289 13:39:51.841843
10290 13:39:52.411032 03900000 ################################################################
10291 13:39:52.411182
10292 13:39:52.973494 03980000 ################################################################
10293 13:39:52.973647
10294 13:39:53.532673 03a00000 ################################################################
10295 13:39:53.532852
10296 13:39:54.080898 03a80000 ################################################################
10297 13:39:54.081070
10298 13:39:54.718186 03b00000 ################################################################
10299 13:39:54.718328
10300 13:39:55.289699 03b80000 ################################################################
10301 13:39:55.289850
10302 13:39:55.858715 03c00000 ################################################################
10303 13:39:55.858851
10304 13:39:56.414787 03c80000 ################################################################
10305 13:39:56.414922
10306 13:39:56.957515 03d00000 ################################################################
10307 13:39:56.957654
10308 13:39:57.491002 03d80000 ################################################################
10309 13:39:57.491147
10310 13:39:58.044604 03e00000 ################################################################
10311 13:39:58.044740
10312 13:39:58.595541 03e80000 ################################################################
10313 13:39:58.595692
10314 13:39:59.153254 03f00000 ################################################################
10315 13:39:59.153498
10316 13:39:59.698314 03f80000 ################################################################
10317 13:39:59.698454
10318 13:40:00.240860 04000000 ################################################################
10319 13:40:00.241027
10320 13:40:00.813037 04080000 ################################################################
10321 13:40:00.813191
10322 13:40:01.374628 04100000 ################################################################
10323 13:40:01.374818
10324 13:40:01.914263 04180000 ################################################################
10325 13:40:01.914458
10326 13:40:02.444741 04200000 ################################################################
10327 13:40:02.444943
10328 13:40:02.971391 04280000 ################################################################
10329 13:40:02.971530
10330 13:40:03.503500 04300000 ################################################################
10331 13:40:03.503676
10332 13:40:04.039773 04380000 ################################################################
10333 13:40:04.039952
10334 13:40:04.572083 04400000 ################################################################
10335 13:40:04.572221
10336 13:40:05.109278 04480000 ################################################################
10337 13:40:05.109426
10338 13:40:05.644615 04500000 ################################################################
10339 13:40:05.644753
10340 13:40:06.178113 04580000 ################################################################
10341 13:40:06.178311
10342 13:40:06.710849 04600000 ################################################################
10343 13:40:06.711006
10344 13:40:06.895073 04680000 ###################### done.
10345 13:40:06.895234
10346 13:40:06.898172 The bootfile was 74104170 bytes long.
10347 13:40:06.898260
10348 13:40:06.901734 Sending tftp read request... done.
10349 13:40:06.901817
10350 13:40:06.901882 Waiting for the transfer...
10351 13:40:06.901943
10352 13:40:06.904584 00000000 # done.
10353 13:40:06.904666
10354 13:40:06.911590 Command line loaded dynamically from TFTP file: 14063027/tftp-deploy-jw8mi1o4/kernel/cmdline
10355 13:40:06.911687
10356 13:40:06.924519 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10357 13:40:06.924625
10358 13:40:06.928309 Loading FIT.
10359 13:40:06.928392
10360 13:40:06.931153 Image ramdisk-1 has 60993576 bytes.
10361 13:40:06.931263
10362 13:40:06.934761 Image fdt-1 has 47258 bytes.
10363 13:40:06.934859
10364 13:40:06.934965 Image kernel-1 has 13061303 bytes.
10365 13:40:06.937767
10366 13:40:06.944487 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10367 13:40:06.944645
10368 13:40:06.963945 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10369 13:40:06.964064
10370 13:40:06.967924 Choosing best match conf-1 for compat google,spherion-rev2.
10371 13:40:06.972181
10372 13:40:06.976792 Connected to device vid:did:rid of 1ae0:0028:00
10373 13:40:06.983756
10374 13:40:06.987049 tpm_get_response: command 0x17b, return code 0x0
10375 13:40:06.987143
10376 13:40:06.990328 ec_init: CrosEC protocol v3 supported (256, 248)
10377 13:40:06.994442
10378 13:40:06.998003 tpm_cleanup: add release locality here.
10379 13:40:06.998087
10380 13:40:06.998151 Shutting down all USB controllers.
10381 13:40:06.998225
10382 13:40:07.001084 Removing current net device
10383 13:40:07.001191
10384 13:40:07.007951 Exiting depthcharge with code 4 at timestamp: 114485748
10385 13:40:07.008038
10386 13:40:07.010825 LZMA decompressing kernel-1 to 0x821a6718
10387 13:40:07.010907
10388 13:40:07.014214 LZMA decompressing kernel-1 to 0x40000000
10389 13:40:08.626348
10390 13:40:08.626489 jumping to kernel
10391 13:40:08.627018 end: 2.2.4 bootloader-commands (duration 00:01:27) [common]
10392 13:40:08.627117 start: 2.2.5 auto-login-action (timeout 00:03:00) [common]
10393 13:40:08.627194 Setting prompt string to ['Linux version [0-9]']
10394 13:40:08.627264 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10395 13:40:08.627330 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10396 13:40:08.708755
10397 13:40:08.711741 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10398 13:40:08.715470 start: 2.2.5.1 login-action (timeout 00:03:00) [common]
10399 13:40:08.715566 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10400 13:40:08.715637 Setting prompt string to []
10401 13:40:08.715712 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10402 13:40:08.715781 Using line separator: #'\n'#
10403 13:40:08.715839 No login prompt set.
10404 13:40:08.715898 Parsing kernel messages
10405 13:40:08.715951 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10406 13:40:08.716084 [login-action] Waiting for messages, (timeout 00:03:00)
10407 13:40:08.716162 Waiting using forced prompt support (timeout 00:01:30)
10408 13:40:08.735262 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10409 13:40:08.738379 [ 0.000000] random: crng init done
10410 13:40:08.744840 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10411 13:40:08.748098 [ 0.000000] efi: UEFI not found.
10412 13:40:08.754616 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10413 13:40:08.764805 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10414 13:40:08.774451 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10415 13:40:08.780979 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10416 13:40:08.787759 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10417 13:40:08.793991 [ 0.000000] printk: bootconsole [mtk8250] enabled
10418 13:40:08.800427 [ 0.000000] NUMA: No NUMA configuration found
10419 13:40:08.807623 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10420 13:40:08.814216 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10421 13:40:08.814300 [ 0.000000] Zone ranges:
10422 13:40:08.820740 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10423 13:40:08.823906 [ 0.000000] DMA32 empty
10424 13:40:08.830596 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10425 13:40:08.833885 [ 0.000000] Movable zone start for each node
10426 13:40:08.837005 [ 0.000000] Early memory node ranges
10427 13:40:08.844019 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10428 13:40:08.850618 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10429 13:40:08.856978 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10430 13:40:08.863337 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10431 13:40:08.869996 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10432 13:40:08.876568 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10433 13:40:08.933508 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10434 13:40:08.940276 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10435 13:40:08.946747 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10436 13:40:08.949659 [ 0.000000] psci: probing for conduit method from DT.
10437 13:40:08.956775 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10438 13:40:08.959829 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10439 13:40:08.966246 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10440 13:40:08.969906 [ 0.000000] psci: SMC Calling Convention v1.2
10441 13:40:08.976616 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10442 13:40:08.979947 [ 0.000000] Detected VIPT I-cache on CPU0
10443 13:40:08.986273 [ 0.000000] CPU features: detected: GIC system register CPU interface
10444 13:40:08.992872 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10445 13:40:09.000118 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10446 13:40:09.006286 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10447 13:40:09.012874 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10448 13:40:09.022772 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10449 13:40:09.026028 [ 0.000000] alternatives: applying boot alternatives
10450 13:40:09.033113 [ 0.000000] Fallback order for Node 0: 0
10451 13:40:09.039529 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10452 13:40:09.039638 [ 0.000000] Policy zone: Normal
10453 13:40:09.056564 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10454 13:40:09.065614 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10455 13:40:09.077603 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10456 13:40:09.087528 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10457 13:40:09.094630 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10458 13:40:09.097843 <6>[ 0.000000] software IO TLB: area num 8.
10459 13:40:09.154412 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10460 13:40:09.303830 <6>[ 0.000000] Memory: 7904624K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 448144K reserved, 32768K cma-reserved)
10461 13:40:09.310510 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10462 13:40:09.317082 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10463 13:40:09.320376 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10464 13:40:09.327138 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10465 13:40:09.333930 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10466 13:40:09.337100 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10467 13:40:09.347056 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10468 13:40:09.353531 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10469 13:40:09.356822 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10470 13:40:09.365304 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10471 13:40:09.367969 <6>[ 0.000000] GICv3: 608 SPIs implemented
10472 13:40:09.374776 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10473 13:40:09.378158 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10474 13:40:09.381204 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10475 13:40:09.391336 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10476 13:40:09.401002 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10477 13:40:09.414534 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10478 13:40:09.420991 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10479 13:40:09.429992 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10480 13:40:09.443248 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10481 13:40:09.450045 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10482 13:40:09.456972 <6>[ 0.009178] Console: colour dummy device 80x25
10483 13:40:09.466411 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10484 13:40:09.470238 <6>[ 0.024343] pid_max: default: 32768 minimum: 301
10485 13:40:09.476525 <6>[ 0.029216] LSM: Security Framework initializing
10486 13:40:09.483098 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10487 13:40:09.493106 <6>[ 0.041968] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10488 13:40:09.499555 <6>[ 0.051397] cblist_init_generic: Setting adjustable number of callback queues.
10489 13:40:09.506142 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10490 13:40:09.516483 <6>[ 0.065227] cblist_init_generic: Setting adjustable number of callback queues.
10491 13:40:09.522987 <6>[ 0.072673] cblist_init_generic: Setting shift to 3 and lim to 1.
10492 13:40:09.526226 <6>[ 0.079073] rcu: Hierarchical SRCU implementation.
10493 13:40:09.532743 <6>[ 0.084088] rcu: Max phase no-delay instances is 1000.
10494 13:40:09.539219 <6>[ 0.091111] EFI services will not be available.
10495 13:40:09.542836 <6>[ 0.096070] smp: Bringing up secondary CPUs ...
10496 13:40:09.551215 <6>[ 0.101117] Detected VIPT I-cache on CPU1
10497 13:40:09.557426 <6>[ 0.101187] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10498 13:40:09.564597 <6>[ 0.101217] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10499 13:40:09.567443 <6>[ 0.101547] Detected VIPT I-cache on CPU2
10500 13:40:09.574336 <6>[ 0.101594] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10501 13:40:09.583730 <6>[ 0.101609] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10502 13:40:09.587581 <6>[ 0.101865] Detected VIPT I-cache on CPU3
10503 13:40:09.594441 <6>[ 0.101912] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10504 13:40:09.600336 <6>[ 0.101925] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10505 13:40:09.604172 <6>[ 0.102230] CPU features: detected: Spectre-v4
10506 13:40:09.610764 <6>[ 0.102236] CPU features: detected: Spectre-BHB
10507 13:40:09.614082 <6>[ 0.102241] Detected PIPT I-cache on CPU4
10508 13:40:09.620620 <6>[ 0.102299] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10509 13:40:09.627166 <6>[ 0.102315] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10510 13:40:09.633602 <6>[ 0.102613] Detected PIPT I-cache on CPU5
10511 13:40:09.640760 <6>[ 0.102676] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10512 13:40:09.647061 <6>[ 0.102691] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10513 13:40:09.650671 <6>[ 0.102975] Detected PIPT I-cache on CPU6
10514 13:40:09.657246 <6>[ 0.103042] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10515 13:40:09.663901 <6>[ 0.103058] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10516 13:40:09.670263 <6>[ 0.103360] Detected PIPT I-cache on CPU7
10517 13:40:09.676795 <6>[ 0.103426] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10518 13:40:09.683876 <6>[ 0.103442] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10519 13:40:09.686651 <6>[ 0.103489] smp: Brought up 1 node, 8 CPUs
10520 13:40:09.693040 <6>[ 0.244857] SMP: Total of 8 processors activated.
10521 13:40:09.696741 <6>[ 0.249808] CPU features: detected: 32-bit EL0 Support
10522 13:40:09.706884 <6>[ 0.255204] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10523 13:40:09.713332 <6>[ 0.264005] CPU features: detected: Common not Private translations
10524 13:40:09.720156 <6>[ 0.270481] CPU features: detected: CRC32 instructions
10525 13:40:09.723331 <6>[ 0.275832] CPU features: detected: RCpc load-acquire (LDAPR)
10526 13:40:09.729686 <6>[ 0.281791] CPU features: detected: LSE atomic instructions
10527 13:40:09.736297 <6>[ 0.287608] CPU features: detected: Privileged Access Never
10528 13:40:09.742834 <6>[ 0.293424] CPU features: detected: RAS Extension Support
10529 13:40:09.749309 <6>[ 0.299067] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10530 13:40:09.753181 <6>[ 0.306284] CPU: All CPU(s) started at EL2
10531 13:40:09.759370 <6>[ 0.310601] alternatives: applying system-wide alternatives
10532 13:40:09.768463 <6>[ 0.321450] devtmpfs: initialized
10533 13:40:09.783324 <6>[ 0.330254] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10534 13:40:09.791231 <6>[ 0.340218] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10535 13:40:09.797712 <6>[ 0.348235] pinctrl core: initialized pinctrl subsystem
10536 13:40:09.800877 <6>[ 0.354899] DMI not present or invalid.
10537 13:40:09.807447 <6>[ 0.359310] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10538 13:40:09.817363 <6>[ 0.366099] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10539 13:40:09.824404 <6>[ 0.373681] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10540 13:40:09.834174 <6>[ 0.381897] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10541 13:40:09.837370 <6>[ 0.390140] audit: initializing netlink subsys (disabled)
10542 13:40:09.847574 <5>[ 0.395836] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10543 13:40:09.850867 <6>[ 0.396540] thermal_sys: Registered thermal governor 'step_wise'
10544 13:40:09.860614 <6>[ 0.403803] thermal_sys: Registered thermal governor 'power_allocator'
10545 13:40:09.864356 <6>[ 0.410058] cpuidle: using governor menu
10546 13:40:09.867469 <6>[ 0.421016] NET: Registered PF_QIPCRTR protocol family
10547 13:40:09.877435 <6>[ 0.426498] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10548 13:40:09.880492 <6>[ 0.433606] ASID allocator initialised with 32768 entries
10549 13:40:09.887494 <6>[ 0.440178] Serial: AMBA PL011 UART driver
10550 13:40:09.896176 <4>[ 0.449008] Trying to register duplicate clock ID: 134
10551 13:40:09.954559 <6>[ 0.510453] KASLR enabled
10552 13:40:09.968719 <6>[ 0.518170] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10553 13:40:09.975516 <6>[ 0.525185] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10554 13:40:09.981947 <6>[ 0.531673] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10555 13:40:09.988958 <6>[ 0.538677] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10556 13:40:09.995569 <6>[ 0.545164] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10557 13:40:10.002007 <6>[ 0.552171] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10558 13:40:10.008547 <6>[ 0.558657] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10559 13:40:10.015284 <6>[ 0.565664] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10560 13:40:10.018611 <6>[ 0.573191] ACPI: Interpreter disabled.
10561 13:40:10.027387 <6>[ 0.579611] iommu: Default domain type: Translated
10562 13:40:10.033473 <6>[ 0.584721] iommu: DMA domain TLB invalidation policy: strict mode
10563 13:40:10.036666 <5>[ 0.591379] SCSI subsystem initialized
10564 13:40:10.043523 <6>[ 0.595544] usbcore: registered new interface driver usbfs
10565 13:40:10.050052 <6>[ 0.601275] usbcore: registered new interface driver hub
10566 13:40:10.053266 <6>[ 0.606828] usbcore: registered new device driver usb
10567 13:40:10.060188 <6>[ 0.612923] pps_core: LinuxPPS API ver. 1 registered
10568 13:40:10.070534 <6>[ 0.618118] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10569 13:40:10.073130 <6>[ 0.627467] PTP clock support registered
10570 13:40:10.076385 <6>[ 0.631708] EDAC MC: Ver: 3.0.0
10571 13:40:10.084396 <6>[ 0.636856] FPGA manager framework
10572 13:40:10.090519 <6>[ 0.640543] Advanced Linux Sound Architecture Driver Initialized.
10573 13:40:10.093842 <6>[ 0.647313] vgaarb: loaded
10574 13:40:10.100424 <6>[ 0.650462] clocksource: Switched to clocksource arch_sys_counter
10575 13:40:10.103663 <5>[ 0.656897] VFS: Disk quotas dquot_6.6.0
10576 13:40:10.110749 <6>[ 0.661087] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10577 13:40:10.114137 <6>[ 0.668275] pnp: PnP ACPI: disabled
10578 13:40:10.122016 <6>[ 0.674939] NET: Registered PF_INET protocol family
10579 13:40:10.132146 <6>[ 0.680529] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10580 13:40:10.143689 <6>[ 0.692857] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10581 13:40:10.153178 <6>[ 0.701675] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10582 13:40:10.159875 <6>[ 0.709643] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10583 13:40:10.169815 <6>[ 0.718344] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10584 13:40:10.176591 <6>[ 0.728096] TCP: Hash tables configured (established 65536 bind 65536)
10585 13:40:10.183116 <6>[ 0.734898] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10586 13:40:10.193106 <6>[ 0.742093] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10587 13:40:10.199599 <6>[ 0.749800] NET: Registered PF_UNIX/PF_LOCAL protocol family
10588 13:40:10.202945 <6>[ 0.755953] RPC: Registered named UNIX socket transport module.
10589 13:40:10.209527 <6>[ 0.762108] RPC: Registered udp transport module.
10590 13:40:10.212824 <6>[ 0.767043] RPC: Registered tcp transport module.
10591 13:40:10.219342 <6>[ 0.771974] RPC: Registered tcp NFSv4.1 backchannel transport module.
10592 13:40:10.225776 <6>[ 0.778642] PCI: CLS 0 bytes, default 64
10593 13:40:10.229006 <6>[ 0.782940] Unpacking initramfs...
10594 13:40:10.253868 <6>[ 0.803118] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10595 13:40:10.263820 <6>[ 0.811788] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10596 13:40:10.267068 <6>[ 0.820652] kvm [1]: IPA Size Limit: 40 bits
10597 13:40:10.273557 <6>[ 0.825179] kvm [1]: GICv3: no GICV resource entry
10598 13:40:10.276759 <6>[ 0.830199] kvm [1]: disabling GICv2 emulation
10599 13:40:10.283178 <6>[ 0.834883] kvm [1]: GIC system register CPU interface enabled
10600 13:40:10.286870 <6>[ 0.841039] kvm [1]: vgic interrupt IRQ18
10601 13:40:10.293111 <6>[ 0.845391] kvm [1]: VHE mode initialized successfully
10602 13:40:10.299968 <5>[ 0.851827] Initialise system trusted keyrings
10603 13:40:10.306558 <6>[ 0.856645] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10604 13:40:10.313842 <6>[ 0.866595] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10605 13:40:10.320298 <5>[ 0.872990] NFS: Registering the id_resolver key type
10606 13:40:10.324142 <5>[ 0.878293] Key type id_resolver registered
10607 13:40:10.330761 <5>[ 0.882707] Key type id_legacy registered
10608 13:40:10.337465 <6>[ 0.886985] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10609 13:40:10.343958 <6>[ 0.893905] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10610 13:40:10.350184 <6>[ 0.901655] 9p: Installing v9fs 9p2000 file system support
10611 13:40:10.387716 <5>[ 0.940037] Key type asymmetric registered
10612 13:40:10.391090 <5>[ 0.944372] Asymmetric key parser 'x509' registered
10613 13:40:10.400803 <6>[ 0.949541] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10614 13:40:10.403621 <6>[ 0.957161] io scheduler mq-deadline registered
10615 13:40:10.406835 <6>[ 0.961920] io scheduler kyber registered
10616 13:40:10.426263 <6>[ 0.978874] EINJ: ACPI disabled.
10617 13:40:10.458858 <4>[ 1.004720] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 13:40:10.468573 <4>[ 1.015382] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 13:40:10.484309 <6>[ 1.036819] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10620 13:40:10.492323 <6>[ 1.044938] printk: console [ttyS0] disabled
10621 13:40:10.520057 <6>[ 1.069567] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10622 13:40:10.526586 <6>[ 1.079046] printk: console [ttyS0] enabled
10623 13:40:10.530073 <6>[ 1.079046] printk: console [ttyS0] enabled
10624 13:40:10.536588 <6>[ 1.087944] printk: bootconsole [mtk8250] disabled
10625 13:40:10.539878 <6>[ 1.087944] printk: bootconsole [mtk8250] disabled
10626 13:40:10.546496 <6>[ 1.099201] SuperH (H)SCI(F) driver initialized
10627 13:40:10.549752 <6>[ 1.104466] msm_serial: driver initialized
10628 13:40:10.563961 <6>[ 1.113465] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10629 13:40:10.574036 <6>[ 1.122036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10630 13:40:10.581090 <6>[ 1.130578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10631 13:40:10.591051 <6>[ 1.139210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10632 13:40:10.600716 <6>[ 1.147919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10633 13:40:10.606854 <6>[ 1.156634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10634 13:40:10.616925 <6>[ 1.165182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10635 13:40:10.623492 <6>[ 1.173987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10636 13:40:10.633546 <6>[ 1.182530] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10637 13:40:10.645695 <6>[ 1.198127] loop: module loaded
10638 13:40:10.651744 <6>[ 1.204138] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10639 13:40:10.675020 <4>[ 1.227594] mtk-pmic-keys: Failed to locate of_node [id: -1]
10640 13:40:10.681923 <6>[ 1.234656] megasas: 07.719.03.00-rc1
10641 13:40:10.691917 <6>[ 1.244506] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10642 13:40:10.700890 <6>[ 1.253847] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10643 13:40:10.717651 <6>[ 1.270286] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10644 13:40:10.774503 <6>[ 1.320283] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10645 13:40:12.963755 <6>[ 3.516798] Freeing initrd memory: 59560K
10646 13:40:12.975589 <6>[ 3.528653] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10647 13:40:12.987040 <6>[ 3.539815] tun: Universal TUN/TAP device driver, 1.6
10648 13:40:12.990402 <6>[ 3.545884] thunder_xcv, ver 1.0
10649 13:40:12.993690 <6>[ 3.549393] thunder_bgx, ver 1.0
10650 13:40:12.996759 <6>[ 3.552885] nicpf, ver 1.0
10651 13:40:13.007422 <6>[ 3.556913] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10652 13:40:13.010763 <6>[ 3.564389] hns3: Copyright (c) 2017 Huawei Corporation.
10653 13:40:13.017467 <6>[ 3.569976] hclge is initializing
10654 13:40:13.020556 <6>[ 3.573557] e1000: Intel(R) PRO/1000 Network Driver
10655 13:40:13.027326 <6>[ 3.578685] e1000: Copyright (c) 1999-2006 Intel Corporation.
10656 13:40:13.030662 <6>[ 3.584697] e1000e: Intel(R) PRO/1000 Network Driver
10657 13:40:13.037189 <6>[ 3.589912] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10658 13:40:13.043621 <6>[ 3.596099] igb: Intel(R) Gigabit Ethernet Network Driver
10659 13:40:13.050080 <6>[ 3.601749] igb: Copyright (c) 2007-2014 Intel Corporation.
10660 13:40:13.056537 <6>[ 3.607586] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10661 13:40:13.063548 <6>[ 3.614103] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10662 13:40:13.066642 <6>[ 3.620571] sky2: driver version 1.30
10663 13:40:13.073034 <6>[ 3.625494] usbcore: registered new device driver r8152-cfgselector
10664 13:40:13.079708 <6>[ 3.632028] usbcore: registered new interface driver r8152
10665 13:40:13.086563 <6>[ 3.637855] VFIO - User Level meta-driver version: 0.3
10666 13:40:13.093035 <6>[ 3.646081] usbcore: registered new interface driver usb-storage
10667 13:40:13.100030 <6>[ 3.652540] usbcore: registered new device driver onboard-usb-hub
10668 13:40:13.108959 <6>[ 3.661704] mt6397-rtc mt6359-rtc: registered as rtc0
10669 13:40:13.118709 <6>[ 3.667166] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:40:12 UTC (1716903612)
10670 13:40:13.121876 <6>[ 3.676737] i2c_dev: i2c /dev entries driver
10671 13:40:13.139082 <6>[ 3.688534] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10672 13:40:13.145479 <4>[ 3.697260] cpu cpu0: supply cpu not found, using dummy regulator
10673 13:40:13.152078 <4>[ 3.703687] cpu cpu1: supply cpu not found, using dummy regulator
10674 13:40:13.158669 <4>[ 3.710089] cpu cpu2: supply cpu not found, using dummy regulator
10675 13:40:13.165034 <4>[ 3.716501] cpu cpu3: supply cpu not found, using dummy regulator
10676 13:40:13.172098 <4>[ 3.722896] cpu cpu4: supply cpu not found, using dummy regulator
10677 13:40:13.178307 <4>[ 3.729290] cpu cpu5: supply cpu not found, using dummy regulator
10678 13:40:13.184881 <4>[ 3.735689] cpu cpu6: supply cpu not found, using dummy regulator
10679 13:40:13.191482 <4>[ 3.742085] cpu cpu7: supply cpu not found, using dummy regulator
10680 13:40:13.209771 <6>[ 3.762731] cpu cpu0: EM: created perf domain
10681 13:40:13.213180 <6>[ 3.767664] cpu cpu4: EM: created perf domain
10682 13:40:13.220540 <6>[ 3.773285] sdhci: Secure Digital Host Controller Interface driver
10683 13:40:13.227072 <6>[ 3.779718] sdhci: Copyright(c) Pierre Ossman
10684 13:40:13.233319 <6>[ 3.784677] Synopsys Designware Multimedia Card Interface Driver
10685 13:40:13.240029 <6>[ 3.791312] sdhci-pltfm: SDHCI platform and OF driver helper
10686 13:40:13.243447 <6>[ 3.791364] mmc0: CQHCI version 5.10
10687 13:40:13.249918 <6>[ 3.801329] ledtrig-cpu: registered to indicate activity on CPUs
10688 13:40:13.256324 <6>[ 3.808384] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10689 13:40:13.263120 <6>[ 3.815433] usbcore: registered new interface driver usbhid
10690 13:40:13.266398 <6>[ 3.821254] usbhid: USB HID core driver
10691 13:40:13.272832 <6>[ 3.825468] spi_master spi0: will run message pump with realtime priority
10692 13:40:13.321780 <6>[ 3.867876] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10693 13:40:13.340480 <6>[ 3.883703] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10694 13:40:13.347463 <6>[ 3.898530] cros-ec-spi spi0.0: Chrome EC device registered
10695 13:40:13.350747 <6>[ 3.898668] mmc0: Command Queue Engine enabled
10696 13:40:13.357375 <6>[ 3.909085] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10697 13:40:13.364398 <6>[ 3.916448] mmcblk0: mmc0:0001 DA4128 116 GiB
10698 13:40:13.373750 <6>[ 3.918512] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10699 13:40:13.380174 <6>[ 3.931667] NET: Registered PF_PACKET protocol family
10700 13:40:13.384156 <6>[ 3.933145] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10701 13:40:13.390491 <6>[ 3.937068] 9pnet: Installing 9P2000 support
10702 13:40:13.393664 <6>[ 3.944441] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10703 13:40:13.400302 <5>[ 3.947456] Key type dns_resolver registered
10704 13:40:13.403528 <6>[ 3.947816] registered taskstats version 1
10705 13:40:13.410621 <6>[ 3.953398] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10706 13:40:13.413681 <5>[ 3.957222] Loading compiled-in X.509 certificates
10707 13:40:13.419947 <6>[ 3.962209] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10708 13:40:13.436341 <4>[ 3.982370] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10709 13:40:13.446027 <4>[ 3.993098] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10710 13:40:13.460656 <6>[ 4.013603] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10711 13:40:13.467215 <6>[ 4.020360] xhci-mtk 11200000.usb: xHCI Host Controller
10712 13:40:13.474132 <6>[ 4.025859] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10713 13:40:13.484120 <6>[ 4.033764] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10714 13:40:13.490612 <6>[ 4.043218] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10715 13:40:13.497657 <6>[ 4.049386] xhci-mtk 11200000.usb: xHCI Host Controller
10716 13:40:13.504164 <6>[ 4.054902] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10717 13:40:13.510615 <6>[ 4.062558] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10718 13:40:13.517106 <6>[ 4.070349] hub 1-0:1.0: USB hub found
10719 13:40:13.520382 <6>[ 4.074371] hub 1-0:1.0: 1 port detected
10720 13:40:13.530226 <6>[ 4.078641] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10721 13:40:13.533809 <6>[ 4.087422] hub 2-0:1.0: USB hub found
10722 13:40:13.537076 <6>[ 4.091441] hub 2-0:1.0: 1 port detected
10723 13:40:13.546043 <6>[ 4.099114] mtk-msdc 11f70000.mmc: Got CD GPIO
10724 13:40:13.558162 <6>[ 4.107921] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10725 13:40:13.564845 <6>[ 4.115951] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10726 13:40:13.574838 <4>[ 4.123865] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10727 13:40:13.584832 <6>[ 4.133398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10728 13:40:13.591486 <6>[ 4.141476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10729 13:40:13.598199 <6>[ 4.149492] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10730 13:40:13.607608 <6>[ 4.157422] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10731 13:40:13.614260 <6>[ 4.165239] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10732 13:40:13.624070 <6>[ 4.173056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10733 13:40:13.634489 <6>[ 4.183539] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10734 13:40:13.640935 <6>[ 4.191903] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10735 13:40:13.650669 <6>[ 4.200250] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10736 13:40:13.657282 <6>[ 4.208587] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10737 13:40:13.666938 <6>[ 4.216924] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10738 13:40:13.677402 <6>[ 4.225262] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10739 13:40:13.683717 <6>[ 4.233599] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10740 13:40:13.693288 <6>[ 4.241944] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10741 13:40:13.700168 <6>[ 4.250282] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10742 13:40:13.710208 <6>[ 4.258620] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10743 13:40:13.716856 <6>[ 4.266957] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10744 13:40:13.726555 <6>[ 4.275295] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10745 13:40:13.733123 <6>[ 4.283633] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10746 13:40:13.743349 <6>[ 4.291970] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10747 13:40:13.749604 <6>[ 4.300308] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10748 13:40:13.756129 <6>[ 4.309060] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10749 13:40:13.763408 <6>[ 4.316221] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10750 13:40:13.769797 <6>[ 4.322983] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10751 13:40:13.779982 <6>[ 4.329750] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10752 13:40:13.786834 <6>[ 4.336685] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10753 13:40:13.792852 <6>[ 4.343544] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10754 13:40:13.803249 <6>[ 4.352674] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10755 13:40:13.812873 <6>[ 4.361795] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10756 13:40:13.822715 <6>[ 4.371090] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10757 13:40:13.832596 <6>[ 4.380557] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10758 13:40:13.842518 <6>[ 4.390026] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10759 13:40:13.848960 <6>[ 4.399145] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10760 13:40:13.859148 <6>[ 4.408611] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10761 13:40:13.869018 <6>[ 4.417730] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10762 13:40:13.878682 <6>[ 4.427024] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10763 13:40:13.888488 <6>[ 4.437186] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10764 13:40:13.899088 <6>[ 4.448774] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10765 13:40:13.948826 <6>[ 4.498726] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10766 13:40:14.103937 <6>[ 4.656780] hub 1-1:1.0: USB hub found
10767 13:40:14.106984 <6>[ 4.661304] hub 1-1:1.0: 4 ports detected
10768 13:40:14.116840 <6>[ 4.670111] hub 1-1:1.0: USB hub found
10769 13:40:14.120161 <6>[ 4.674621] hub 1-1:1.0: 4 ports detected
10770 13:40:14.229252 <6>[ 4.779070] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10771 13:40:14.256192 <6>[ 4.808829] hub 2-1:1.0: USB hub found
10772 13:40:14.259231 <6>[ 4.813350] hub 2-1:1.0: 3 ports detected
10773 13:40:14.268448 <6>[ 4.821386] hub 2-1:1.0: USB hub found
10774 13:40:14.271671 <6>[ 4.825857] hub 2-1:1.0: 3 ports detected
10775 13:40:14.444662 <6>[ 4.994761] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10776 13:40:14.576994 <6>[ 5.130325] hub 1-1.4:1.0: USB hub found
10777 13:40:14.580177 <6>[ 5.135033] hub 1-1.4:1.0: 2 ports detected
10778 13:40:14.589784 <6>[ 5.142763] hub 1-1.4:1.0: USB hub found
10779 13:40:14.593135 <6>[ 5.147364] hub 1-1.4:1.0: 2 ports detected
10780 13:40:14.657001 <6>[ 5.206899] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10781 13:40:14.765164 <6>[ 5.315406] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10782 13:40:14.802093 <4>[ 5.351853] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10783 13:40:14.811772 <4>[ 5.361012] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10784 13:40:14.850603 <6>[ 5.404190] r8152 2-1.3:1.0 eth0: v1.12.13
10785 13:40:14.889037 <6>[ 5.438783] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10786 13:40:15.080396 <6>[ 5.630567] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10787 13:40:16.527083 <6>[ 7.080426] r8152 2-1.3:1.0 eth0: carrier on
10788 13:40:19.248945 <5>[ 7.106535] Sending DHCP requests .., OK
10789 13:40:19.255551 <6>[ 9.806909] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10790 13:40:19.258958 <6>[ 9.815203] IP-Config: Complete:
10791 13:40:19.272016 <6>[ 9.818697] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10792 13:40:19.278939 <6>[ 9.829421] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10793 13:40:19.285350 <6>[ 9.838040] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10794 13:40:19.291822 <6>[ 9.838050] nameserver0=192.168.201.1
10795 13:40:19.295207 <6>[ 9.850222] clk: Disabling unused clocks
10796 13:40:19.298553 <6>[ 9.855729] ALSA device list:
10797 13:40:19.305454 <6>[ 9.858980] No soundcards found.
10798 13:40:19.312689 <6>[ 9.866269] Freeing unused kernel memory: 8512K
10799 13:40:19.315866 <6>[ 9.871239] Run /init as init process
10800 13:40:19.345888 <6>[ 9.899540] NET: Registered PF_INET6 protocol family
10801 13:40:19.352496 <6>[ 9.906250] Segment Routing with IPv6
10802 13:40:19.355819 <6>[ 9.910202] In-situ OAM (IOAM) with IPv6
10803 13:40:19.396707 <30>[ 9.924286] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10804 13:40:19.404052 <30>[ 9.957358] systemd[1]: Detected architecture arm64.
10805 13:40:19.404143
10806 13:40:19.410361 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10807 13:40:19.410438
10808 13:40:19.424906 <30>[ 9.978776] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10809 13:40:19.558259 <30>[ 10.108640] systemd[1]: Queued start job for default target graphical.target.
10810 13:40:19.602342 <30>[ 10.152638] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10811 13:40:19.608597 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10812 13:40:19.628764 <30>[ 10.179166] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10813 13:40:19.638492 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10814 13:40:19.657663 <30>[ 10.207953] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10815 13:40:19.667644 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10816 13:40:19.685908 <30>[ 10.236195] systemd[1]: Created slice user.slice - User and Session Slice.
10817 13:40:19.692260 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10818 13:40:19.715839 <30>[ 10.263132] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10819 13:40:19.722602 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10820 13:40:19.743859 <30>[ 10.290888] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10821 13:40:19.750111 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10822 13:40:19.778934 <30>[ 10.319345] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10823 13:40:19.788793 <30>[ 10.339250] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10824 13:40:19.795690 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10825 13:40:19.812616 <30>[ 10.362790] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10826 13:40:19.819183 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10827 13:40:19.836640 <30>[ 10.386836] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10828 13:40:19.845889 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10829 13:40:19.861255 <30>[ 10.414950] systemd[1]: Reached target paths.target - Path Units.
10830 13:40:19.870876 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10831 13:40:19.888231 <30>[ 10.438794] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10832 13:40:19.894760 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10833 13:40:19.908915 <30>[ 10.462747] systemd[1]: Reached target slices.target - Slice Units.
10834 13:40:19.919192 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10835 13:40:19.933547 <30>[ 10.487254] systemd[1]: Reached target swap.target - Swaps.
10836 13:40:19.939767 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10837 13:40:19.960591 <30>[ 10.511250] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10838 13:40:19.970894 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10839 13:40:19.989001 <30>[ 10.539232] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10840 13:40:19.998375 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10841 13:40:20.018462 <30>[ 10.569021] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10842 13:40:20.028518 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10843 13:40:20.044763 <30>[ 10.595482] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10844 13:40:20.055115 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10845 13:40:20.072529 <30>[ 10.623337] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10846 13:40:20.079403 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10847 13:40:20.097320 <30>[ 10.647403] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10848 13:40:20.107040 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10849 13:40:20.124630 <30>[ 10.675237] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10850 13:40:20.134732 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10851 13:40:20.192566 <30>[ 10.743134] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10852 13:40:20.199074 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10853 13:40:20.220872 <30>[ 10.771332] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10854 13:40:20.227148 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10855 13:40:20.276508 <30>[ 10.827056] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10856 13:40:20.282903 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10857 13:40:20.311264 <30>[ 10.855386] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10858 13:40:20.325376 <30>[ 10.875987] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10859 13:40:20.335245 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10860 13:40:20.358116 <30>[ 10.908205] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10861 13:40:20.364428 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10862 13:40:20.389547 <30>[ 10.940289] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10863 13:40:20.399184 Startin<6>[ 10.949689] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10864 13:40:20.405792 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10865 13:40:20.461133 <30>[ 11.011550] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10866 13:40:20.467275 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10867 13:40:20.493898 <30>[ 11.044431] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10868 13:40:20.503838 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10869 13:40:20.525789 <30>[ 11.076456] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10870 13:40:20.532267 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10871 13:40:20.588990 <30>[ 11.139421] systemd[1]: Starting systemd-journald.service - Journal Service...
10872 13:40:20.595551 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10873 13:40:20.619489 <30>[ 11.170077] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10874 13:40:20.626352 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10875 13:40:20.653015 <30>[ 11.199993] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10876 13:40:20.659542 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10877 13:40:20.729124 <30>[ 11.279716] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10878 13:40:20.739344 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10879 13:40:20.759245 <30>[ 11.309802] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10880 13:40:20.766544 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10881 13:40:20.788307 <30>[ 11.338330] systemd[1]: Started systemd-journald.service - Journal Service.
10882 13:40:20.794462 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10883 13:40:20.814940 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10884 13:40:20.833842 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10885 13:40:20.857164 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10886 13:40:20.878231 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10887 13:40:20.902653 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10888 13:40:20.923941 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10889 13:40:20.943275 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10890 13:40:20.963744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10891 13:40:20.986824 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10892 13:40:21.009042 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10893 13:40:21.029466 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10894 13:40:21.054771 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10895 13:40:21.069565 See 'systemctl status systemd-remount-fs.service' for details.
10896 13:40:21.080452 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10897 13:40:21.103366 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10898 13:40:21.149094 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10899 13:40:21.173822 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10900 13:40:21.194404 <46>[ 11.744734] systemd-journald[184]: Received client request to flush runtime journal.
10901 13:40:21.206583 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10902 13:40:21.229313 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10903 13:40:21.252946 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10904 13:40:21.277714 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10905 13:40:21.301805 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10906 13:40:21.321920 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10907 13:40:21.345656 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10908 13:40:21.366072 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10909 13:40:21.409137 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10910 13:40:21.438170 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10911 13:40:21.456961 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10912 13:40:21.476261 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10913 13:40:21.516664 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10914 13:40:21.538525 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10915 13:40:21.559974 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10916 13:40:21.601695 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10917 13:40:21.630555 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10918 13:40:21.650379 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10919 13:40:21.689281 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10920 13:40:21.706950 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10921 13:40:21.766884 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10922 13:40:21.845480 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10923 13:40:21.866205 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10924 13:40:21.884891 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10925 13:40:21.906929 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10926 13:40:21.924622 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10927 13:40:21.942220 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10928 13:40:21.962349 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10929 13:40:21.981715 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10930 13:40:22.012062 <6>[ 12.562267] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10931 13:40:22.021366 <6>[ 12.570354] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10932 13:40:22.027995 <6>[ 12.579639] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10933 13:40:22.039154 <3>[ 12.589455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 13:40:22.045729 <3>[ 12.597659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 13:40:22.055155 <3>[ 12.605770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 13:40:22.062162 <6>[ 12.606153] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10937 13:40:22.068863 <4>[ 12.618876] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10938 13:40:22.078495 <6>[ 12.619048] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10939 13:40:22.085304 <3>[ 12.631570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10940 13:40:22.094930 <3>[ 12.644493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10941 13:40:22.101460 <4>[ 12.651018] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10942 13:40:22.108273 <3>[ 12.652614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10943 13:40:22.114770 Startin<6>[ 12.660570] mc: Linux media interface: v0.10
10944 13:40:22.121432 g [0;1;39mdbus.<6>[ 12.664002] remoteproc remoteproc0: scp is available
10945 13:40:22.127896 <6>[ 12.664146] remoteproc remoteproc0: powering up scp
10946 13:40:22.137523 service[0m - D-<6>[ 12.664154] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10947 13:40:22.140811 <6>[ 12.664191] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10948 13:40:22.151231 <3>[ 12.668096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10949 13:40:22.157466 <3>[ 12.668104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10950 13:40:22.167121 <3>[ 12.675312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10951 13:40:22.170784 <6>[ 12.724392] videodev: Linux video capture interface: v2.00
10952 13:40:22.180920 Bus System Messa<6>[ 12.725779] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10953 13:40:22.181018 ge Bus...
10954 13:40:22.190157 <3>[ 12.727524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10955 13:40:22.196752 <3>[ 12.727558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10956 13:40:22.207105 <3>[ 12.727562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10957 13:40:22.213203 <3>[ 12.727604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10958 13:40:22.223512 <3>[ 12.727607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10959 13:40:22.230602 <3>[ 12.727609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10960 13:40:22.237079 <3>[ 12.727614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 13:40:22.246679 <3>[ 12.727617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 13:40:22.253419 <3>[ 12.727640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 13:40:22.264552 <6>[ 12.735181] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10964 13:40:22.270742 <6>[ 12.739471] pci_bus 0000:00: root bus resource [bus 00-ff]
10965 13:40:22.276939 <6>[ 12.739478] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10966 13:40:22.287423 <6>[ 12.748994] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10967 13:40:22.296865 <6>[ 12.756676] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10968 13:40:22.303422 <6>[ 12.756728] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10969 13:40:22.310521 <4>[ 12.757369] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10970 13:40:22.316934 <4>[ 12.757369] Fallback method does not support PEC.
10971 13:40:22.326962 <6>[ 12.778856] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10972 13:40:22.333304 <6>[ 12.780960] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10973 13:40:22.340163 <6>[ 12.790041] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10974 13:40:22.349706 <6>[ 12.790822] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10975 13:40:22.356607 <6>[ 12.790840] remoteproc remoteproc0: remote processor scp is now up
10976 13:40:22.359691 <6>[ 12.797294] pci 0000:00:00.0: supports D1 D2
10977 13:40:22.362941 <6>[ 12.830013] Bluetooth: Core ver 2.22
10978 13:40:22.373101 <6>[ 12.830909] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10979 13:40:22.379510 <6>[ 12.833001] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10980 13:40:22.386395 <6>[ 12.836640] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10981 13:40:22.392885 <6>[ 12.847278] NET: Registered PF_BLUETOOTH protocol family
10982 13:40:22.399427 <6>[ 12.849765] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10983 13:40:22.413085 <6>[ 12.851050] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10984 13:40:22.416714 <6>[ 12.851240] usbcore: registered new interface driver uvcvideo
10985 13:40:22.427971 <3>[ 12.856990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 13:40:22.435179 <6>[ 12.858245] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10987 13:40:22.442501 <6>[ 12.858468] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10988 13:40:22.449174 <6>[ 12.858503] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10989 13:40:22.455530 <6>[ 12.858525] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10990 13:40:22.465230 <6>[ 12.858541] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10991 13:40:22.468499 <6>[ 12.858656] pci 0000:01:00.0: supports D1 D2
10992 13:40:22.475563 <6>[ 12.858659] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10993 13:40:22.481992 <6>[ 12.861881] Bluetooth: HCI device and connection manager initialized
10994 13:40:22.489019 <6>[ 12.870621] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10995 13:40:22.495457 <6>[ 12.870646] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10996 13:40:22.505137 <6>[ 12.870650] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10997 13:40:22.511461 <6>[ 12.870658] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10998 13:40:22.521933 <6>[ 12.870670] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10999 13:40:22.528375 <6>[ 12.870683] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11000 13:40:22.535129 <6>[ 12.870696] pci 0000:00:00.0: PCI bridge to [bus 01]
11001 13:40:22.541541 <6>[ 12.870701] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11002 13:40:22.548085 <6>[ 12.870825] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11003 13:40:22.554594 <6>[ 12.871305] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11004 13:40:22.561032 <6>[ 12.871781] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11005 13:40:22.567509 <5>[ 12.895055] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11006 13:40:22.574642 <6>[ 12.899379] Bluetooth: HCI socket layer initialized
11007 13:40:22.580692 <6>[ 12.900223] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11008 13:40:22.587331 <5>[ 12.921246] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11009 13:40:22.591019 <6>[ 12.922690] Bluetooth: L2CAP socket layer initialized
11010 13:40:22.601654 <5>[ 12.931188] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11011 13:40:22.604895 <6>[ 12.939187] Bluetooth: SCO socket layer initialized
11012 13:40:22.614443 <4>[ 12.946276] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11013 13:40:22.621554 <3>[ 12.985820] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 13:40:22.628208 <6>[ 12.985954] cfg80211: failed to load regulatory.db
11015 13:40:22.638060 <3>[ 12.986653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11016 13:40:22.644628 <3>[ 12.998653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 13:40:22.654621 <3>[ 12.999445] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11018 13:40:22.657928 <6>[ 13.009035] usbcore: registered new interface driver btusb
11019 13:40:22.671644 <4>[ 13.009542] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11020 13:40:22.675647 <3>[ 13.009549] Bluetooth: hci0: Failed to load firmware file (-2)
11021 13:40:22.682182 <3>[ 13.009551] Bluetooth: hci0: Failed to set up firmware (-2)
11022 13:40:22.692259 <4>[ 13.009553] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11023 13:40:22.699299 <6>[ 13.042873] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11024 13:40:22.709094 <3>[ 13.153978] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 13:40:22.715596 <6>[ 13.159552] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11026 13:40:22.721827 <3>[ 13.186232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 13:40:22.728832 <6>[ 13.207648] mt7921e 0000:01:00.0: ASIC revision: 79610010
11028 13:40:22.738491 <3>[ 13.235162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 13:40:22.745114 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11030 13:40:22.769822 <3>[ 13.320420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11031 13:40:22.783586 <6>[ 13.334212] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11032 13:40:22.786781 <6>[ 13.334212]
11033 13:40:22.793671 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11034 13:40:22.806675 <3>[ 13.356999] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 13:40:22.816550 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11036 13:40:22.840901 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11037 13:40:22.896871 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11038 13:40:22.925518 <46>[ 13.463010] systemd-journald[184]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.9 (1553 of 2047 items, 524288 file size, 337 bytes per hash table item), suggesting rotation.
11039 13:40:22.938472 <46>[ 13.484357] systemd-journald[184]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11040 13:40:22.948940 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11041 13:40:22.969209 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11042 13:40:22.989515 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11043 13:40:23.053185 <6>[ 13.603770] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11044 13:40:23.059285 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11045 13:40:23.125766 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11046 13:40:23.145455 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11047 13:40:23.161019 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11048 13:40:23.180490 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11049 13:40:23.242129 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11050 13:40:23.266981 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11051 13:40:23.291845 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11052 13:40:23.371250 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11053 13:40:23.391064 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11054 13:40:23.415149 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11055 13:40:23.465986
11056 13:40:23.469369 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11057 13:40:23.469809
11058 13:40:23.472243 debian-bookworm-arm64 login: root (automatic login)
11059 13:40:23.472667
11060 13:40:23.484959 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11061 13:40:23.485431
11062 13:40:23.491374 The programs included with the Debian GNU/Linux system are free software;
11063 13:40:23.497825 the exact distribution terms for each program are described in the
11064 13:40:23.501685 individual files in /usr/share/doc/*/copyright.
11065 13:40:23.502122
11066 13:40:23.507639 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11067 13:40:23.511407 permitted by applicable law.
11068 13:40:23.512948 Matched prompt #10: / #
11070 13:40:23.514202 Setting prompt string to ['/ #']
11071 13:40:23.514833 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11073 13:40:23.516003 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11074 13:40:23.516446 start: 2.2.6 expect-shell-connection (timeout 00:02:45) [common]
11075 13:40:23.516842 Setting prompt string to ['/ #']
11076 13:40:23.517199 Forcing a shell prompt, looking for ['/ #']
11078 13:40:23.568136 / #
11079 13:40:23.568835 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11080 13:40:23.569444 Waiting using forced prompt support (timeout 00:02:30)
11081 13:40:23.574486
11082 13:40:23.575360 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11083 13:40:23.576143 start: 2.2.7 export-device-env (timeout 00:02:45) [common]
11084 13:40:23.576748 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11085 13:40:23.577196 end: 2.2 depthcharge-retry (duration 00:02:15) [common]
11086 13:40:23.577838 end: 2 depthcharge-action (duration 00:02:15) [common]
11087 13:40:23.578313 start: 3 lava-test-retry (timeout 00:07:19) [common]
11088 13:40:23.578837 start: 3.1 lava-test-shell (timeout 00:07:19) [common]
11089 13:40:23.579227 Using namespace: common
11091 13:40:23.680388 / # #
11092 13:40:23.681020 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11093 13:40:23.687042 #
11094 13:40:23.687779 Using /lava-14063027
11096 13:40:23.788669 / # export SHELL=/bin/sh
11097 13:40:23.793828 export SHELL=/bin/sh
11099 13:40:23.894380 / # . /lava-14063027/environment
11100 13:40:23.899634 . /lava-14063027/environment
11102 13:40:24.000131 / # /lava-14063027/bin/lava-test-runner /lava-14063027/0
11103 13:40:24.000352 Test shell timeout: 10s (minimum of the action and connection timeout)
11104 13:40:24.000769 <6>[ 14.474913] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11105 13:40:24.004971 /lava-14063027/bin/lava-test-runner /lava-14063027/0
11106 13:40:24.058440 + export TESTRUN_ID=0_igt-kms-me<8>[ 14.587280] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14063027_1.5.2.3.1>
11107 13:40:24.058604 diatek
11108 13:40:24.058738 + cd /lava-14063027/0/tests/0_igt-kms-mediatek
11109 13:40:24.058919 + cat uuid
11110 13:40:24.059063 + UUID=14063027_1.5.2.3.1
11111 13:40:24.059176 + set +x
11112 13:40:24.059477 Received signal: <STARTRUN> 0_igt-kms-mediatek 14063027_1.5.2.3.1
11113 13:40:24.059568 Starting test lava.0_igt-kms-mediatek (14063027_1.5.2.3.1)
11114 13:40:24.059651 Skipping test definition patterns.
11115 13:40:24.063583 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11116 13:40:24.069641 <8>[ 14.623473] <LAVA_SIGNAL_TESTSET START core_auth>
11117 13:40:24.069945 Received signal: <TESTSET> START core_auth
11118 13:40:24.070043 Starting test_set core_auth
11119 13:40:24.097703 <14>[ 14.652237] [IGT] core_auth: executing
11120 13:40:24.104767 IGT-Version: 1.2<14>[ 14.656689] [IGT] core_auth: starting subtest getclient-simple
11121 13:40:24.114550 8-ga44ebfe (aarc<14>[ 14.664526] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11122 13:40:24.117648 h64) (Linux: 6.1<14>[ 14.672539] [IGT] core_auth: exiting, ret=0
11123 13:40:24.121190 .91-cip21 aarch64)
11124 13:40:24.130863 Using IGT_SRANDOM=1716903624 for randomisati<8>[ 14.683735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11125 13:40:24.131055 on
11126 13:40:24.131354 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11128 13:40:24.134302 Starting subtest: getclient-simple
11129 13:40:24.137533 Opened device: /dev/dri/card0
11130 13:40:24.144003 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11131 13:40:24.150964 <14>[ 14.704888] [IGT] core_auth: executing
11132 13:40:24.157482 IGT-Version: 1.2<14>[ 14.709284] [IGT] core_auth: starting subtest getclient-master-drop
11133 13:40:24.167209 8-ga44ebfe (aarc<14>[ 14.717372] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11134 13:40:24.173655 h64) (Linux: 6.1<14>[ 14.726052] [IGT] core_auth: exiting, ret=0
11135 13:40:24.173917 .91-cip21 aarch64)
11136 13:40:24.186927 Using IGT_SRANDOM=1716903624 for randomisati<8>[ 14.736365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11137 13:40:24.187132 on
11138 13:40:24.187427 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11140 13:40:24.190096 Starting subtest: getclient-master-drop
11141 13:40:24.193380 Opened device: /dev/dri/card0
11142 13:40:24.196648 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11143 13:40:24.214773 <14>[ 14.768942] [IGT] core_auth: executing
11144 13:40:24.221723 IGT-Version: 1.2<14>[ 14.773608] [IGT] core_auth: starting subtest basic-auth
11145 13:40:24.227994 8-ga44ebfe (aarc<14>[ 14.780578] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11146 13:40:24.234471 h64) (Linux: 6.1<14>[ 14.788280] [IGT] core_auth: exiting, ret=0
11147 13:40:24.237606 .91-cip21 aarch64)
11148 13:40:24.241095 Using IGT_SRANDOM=1716903624 for randomisation
11149 13:40:24.250922 Opened device: /dev/dri/card<8>[ 14.801152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11150 13:40:24.251008 0
11151 13:40:24.251254 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11153 13:40:24.254204 Starting subtest: basic-auth
11154 13:40:24.257360 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11155 13:40:24.268690 <14>[ 14.823182] [IGT] core_auth: executing
11156 13:40:24.275576 IGT-Version: 1.2<14>[ 14.827615] [IGT] core_auth: starting subtest many-magics
11157 13:40:24.279102 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11158 13:40:24.288612 Using IGT_SRANDOM=1716903624 for randomisati<14>[ 14.841645] [IGT] core_auth: finished subtest many-magics, SUCCESS
11159 13:40:24.292268 on
11160 13:40:24.295377 Opened devic<14>[ 14.849528] [IGT] core_auth: exiting, ret=0
11161 13:40:24.298641 e: /dev/dri/card0
11162 13:40:24.301807 Starting subtest: many-magics
11163 13:40:24.308827 Reopening device failed after <8>[ 14.861956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11164 13:40:24.309160 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11166 13:40:24.311873 1020 opens
11167 13:40:24.315326 Received signal: <TESTSET> STOP
11168 13:40:24.315410 Closing test_set core_auth
11169 13:40:24.318239 [1mSubtest many-mag<8>[ 14.871325] <LAVA_SIGNAL_TESTSET STOP>
11170 13:40:24.318328 ics: SUCCESS (0.007s)[0m
11171 13:40:24.360795 <14>[ 14.914912] [IGT] core_getclient: executing
11172 13:40:24.367458 IGT-Version: 1.2<14>[ 14.919773] [IGT] core_getclient: exiting, ret=0
11173 13:40:24.370596 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11174 13:40:24.380837 Using IGT_SR<8>[ 14.931364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11175 13:40:24.381598 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11177 13:40:24.384563 ANDOM=1716903624 for randomisation
11178 13:40:24.385052 Opened device: /dev/dri/card0
11179 13:40:24.387230 SUCCESS (0.006s)
11180 13:40:24.423780 <14>[ 14.977983] [IGT] core_getstats: executing
11181 13:40:24.431029 IGT-Version: 1.2<14>[ 14.982877] [IGT] core_getstats: exiting, ret=0
11182 13:40:24.434323 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11183 13:40:24.443902 Using IGT_SRANDOM=1716903624<8>[ 14.995336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11184 13:40:24.444619 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11186 13:40:24.447403 for randomisation
11187 13:40:24.447796 Opened device: /dev/dri/card0
11188 13:40:24.450743 SUCCESS (0.006s)
11189 13:40:24.493019 <14>[ 15.046788] [IGT] core_getversion: executing
11190 13:40:24.499334 IGT-Version: 1.2<14>[ 15.052042] [IGT] core_getversion: exiting, ret=0
11191 13:40:24.502487 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11192 13:40:24.512404 Using IGT_SRANDOM=1716903624<8>[ 15.064333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11193 13:40:24.513145 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11195 13:40:24.516249 for randomisation
11196 13:40:24.519627 Opened device: /dev/dri/card0
11197 13:40:24.520055 SUCCESS (0.006s)
11198 13:40:24.563823 <14>[ 15.118033] [IGT] core_setmaster_vs_auth: executing
11199 13:40:24.570563 IGT-Version: 1.2<14>[ 15.123966] [IGT] core_setmaster_vs_auth: exiting, ret=0
11200 13:40:24.576948 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11201 13:40:24.580819 Using IGT_SRANDOM=1716903624 for randomisation
11202 13:40:24.590546 Opened devic<8>[ 15.139897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11203 13:40:24.590948 e: /dev/dri/card0
11204 13:40:24.591554 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11206 13:40:24.594037 SUCCESS (0.007s)
11207 13:40:24.621619 <8>[ 15.175597] <LAVA_SIGNAL_TESTSET START drm_read>
11208 13:40:24.622379 Received signal: <TESTSET> START drm_read
11209 13:40:24.622802 Starting test_set drm_read
11210 13:40:24.650689 <14>[ 15.204643] [IGT] drm_read: executing
11211 13:40:24.657292 IGT-Version: 1.2<14>[ 15.209671] [IGT] drm_read: exiting, ret=77
11212 13:40:24.660406 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11213 13:40:24.670271 Using IGT_SRANDOM=1716903624 for randomisati<8>[ 15.222353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11214 13:40:24.670700 on
11215 13:40:24.671285 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11217 13:40:24.673608 Opened device: /dev/dri/card0
11218 13:40:24.680553 No KMS driver or no outputs, pipes: 16, outputs: 0
11219 13:40:24.683805 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11220 13:40:24.693460 <14>[ 15.247249] [IGT] drm_read: executing
11221 13:40:24.699929 IGT-Version: 1.2<14>[ 15.251704] [IGT] drm_read: exiting, ret=77
11222 13:40:24.703400 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11223 13:40:24.709629 Using IGT_SR<8>[ 15.262578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11224 13:40:24.710340 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11226 13:40:24.713565 ANDOM=1716903624 for randomisation
11227 13:40:24.716294 Opened device: /dev/dri/card0
11228 13:40:24.719673 No KMS driver or no outputs, pipes: 16, outputs: 0
11229 13:40:24.726404 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11230 13:40:24.738798 <14>[ 15.292915] [IGT] drm_read: executing
11231 13:40:24.745788 IGT-Version: 1.2<14>[ 15.297694] [IGT] drm_read: exiting, ret=77
11232 13:40:24.748892 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11233 13:40:24.755693 Using IGT_SR<8>[ 15.308658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11234 13:40:24.756438 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11236 13:40:24.759047 ANDOM=1716903624 for randomisation
11237 13:40:24.762333 Opened device: /dev/dri/card0
11238 13:40:24.768567 No KMS driver or no outputs, pipes: 16, outputs: 0
11239 13:40:24.771673 [1mSubtest empty-block: SKIP (0.000s)[0m
11240 13:40:24.775040 <14>[ 15.329914] [IGT] drm_read: executing
11241 13:40:24.781577 IGT-Version: 1.2<14>[ 15.334378] [IGT] drm_read: exiting, ret=77
11242 13:40:24.785609 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11243 13:40:24.794661 Using IGT_SRANDOM=1716903624<8>[ 15.346439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11244 13:40:24.795466 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11246 13:40:24.798506 for randomisation
11247 13:40:24.798927 Opened device: /dev/dri/card0
11248 13:40:24.805129 No KMS driver or no outputs, pipes: 16, outputs: 0
11249 13:40:24.808372 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11250 13:40:24.823819 <14>[ 15.377298] [IGT] drm_read: executing
11251 13:40:24.830142 IGT-Version: 1.2<14>[ 15.382087] [IGT] drm_read: exiting, ret=77
11252 13:40:24.833234 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11253 13:40:24.843010 Using IGT_SRANDOM=1716903624<8>[ 15.394258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11254 13:40:24.843709 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11256 13:40:24.846176 for randomisation
11257 13:40:24.846599 Opened device: /dev/dri/card0
11258 13:40:24.852748 No KMS driver or no outputs, pipes: 16, outputs: 0
11259 13:40:24.856552 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11260 13:40:24.871943 <14>[ 15.426047] [IGT] drm_read: executing
11261 13:40:24.878709 IGT-Version: 1.2<14>[ 15.431126] [IGT] drm_read: exiting, ret=77
11262 13:40:24.882051 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11263 13:40:24.885311 Using IGT_SRANDOM=1716903624 for randomisation
11264 13:40:24.895166 Opened devic<8>[ 15.445287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11265 13:40:24.895592 e: /dev/dri/card0
11266 13:40:24.896188 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11268 13:40:24.902283 No KMS driver or no outputs, pipes: 16, outputs: 0
11269 13:40:24.905510 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11270 13:40:24.924113 <14>[ 15.477848] [IGT] drm_read: executing
11271 13:40:24.930472 IGT-Version: 1.2<14>[ 15.482724] [IGT] drm_read: exiting, ret=77
11272 13:40:24.933668 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11273 13:40:24.936943 Using IGT_SRANDOM=1716903624 for randomisation
11274 13:40:24.946887 Opened devic<8>[ 15.497046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11275 13:40:24.947328 e: /dev/dri/card0
11276 13:40:24.947974 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11278 13:40:24.953816 No KMS driver<8>[ 15.507169] <LAVA_SIGNAL_TESTSET STOP>
11279 13:40:24.954514 Received signal: <TESTSET> STOP
11280 13:40:24.955019 Closing test_set drm_read
11281 13:40:24.956665 or no outputs, pipes: 16, outputs: 0
11282 13:40:24.960185 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11283 13:40:24.976282 <8>[ 15.530108] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11284 13:40:24.976960 Received signal: <TESTSET> START kms_addfb_basic
11285 13:40:24.977361 Starting test_set kms_addfb_basic
11286 13:40:25.005128 <14>[ 15.559330] [IGT] kms_addfb_basic: executing
11287 13:40:25.018436 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch6<14>[ 15.569142] [IGT] kms_addfb_basic: starting subtest unused-handle
11288 13:40:25.018885 4)
11289 13:40:25.025339 Using IGT_SR<14>[ 15.576621] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11290 13:40:25.028583 ANDOM=1716903625 for randomisation
11291 13:40:25.031752 Opened device: /dev/dri/card0
11292 13:40:25.035047 Starting subtest: unused-handle
11293 13:40:25.041232 [1mSubtest <14>[ 15.594082] [IGT] kms_addfb_basic: exiting, ret=0
11294 13:40:25.044544 unused-handle: SUCCESS (0.000s)[0m
11295 13:40:25.054522 Test requirement not met in function igt_re<8>[ 15.606744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11296 13:40:25.054852 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11298 13:40:25.057565 quire_intel, file ../lib/drmtest.c:880:
11299 13:40:25.060906 Test requirement: is_intel_device(fd)
11300 13:40:25.074048 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 15.627681] [IGT] kms_addfb_basic: executing
11301 13:40:25.074158 0:
11302 13:40:25.077523 Test requirement: is_intel_device(fd)
11303 13:40:25.084210 No KMS driver or no o<14>[ 15.637033] [IGT] kms_addfb_basic: starting subtest unused-pitches
11304 13:40:25.094170 utputs, pipes: 1<14>[ 15.644940] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11305 13:40:25.094259 6, outputs: 0
11306 13:40:25.100667 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11307 13:40:25.107312 Using IGT_SRA<14>[ 15.661588] [IGT] kms_addfb_basic: exiting, ret=0
11308 13:40:25.110611 NDOM=1716903625 for randomisation
11309 13:40:25.113809 Opened device: /dev/dri/card0
11310 13:40:25.120368 Starting subte<8>[ 15.673566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11311 13:40:25.120629 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11313 13:40:25.123737 st: unused-pitches
11314 13:40:25.126835 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11315 13:40:25.133373 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11316 13:40:25.136625 Test requirement: is_intel_device(fd)
11317 13:40:25.150345 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 15.703993] [IGT] kms_addfb_basic: executing
11318 13:40:25.150432 80:
11319 13:40:25.153665 Test requirement: is_intel_device(fd)
11320 13:40:25.163215 No KMS driver or no <14>[ 15.714205] [IGT] kms_addfb_basic: starting subtest unused-offsets
11321 13:40:25.169689 outputs, pipes: <14>[ 15.721516] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11322 13:40:25.172957 16, outputs: 0
11323 13:40:25.179939 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11324 13:40:25.186275 Using IGT_SRANDOM=1716903625<14>[ 15.738973] [IGT] kms_addfb_basic: exiting, ret=0
11325 13:40:25.186358 for randomisation
11326 13:40:25.189422 Opened device: /dev/dri/card0
11327 13:40:25.199720 Starting subtest: unused-offs<8>[ 15.751620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11328 13:40:25.199805 ets
11329 13:40:25.200048 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11331 13:40:25.206517 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11332 13:40:25.213015 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11333 13:40:25.219428 Test requirement: is_<14>[ 15.772786] [IGT] kms_addfb_basic: executing
11334 13:40:25.219524 intel_device(fd)
11335 13:40:25.229216 Test requirement not met in function igt_requi<14>[ 15.782058] [IGT] kms_addfb_basic: starting subtest unused-modifier
11336 13:40:25.239317 re_intel, file .<14>[ 15.790048] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11337 13:40:25.242636 ./lib/drmtest.c:880:
11338 13:40:25.246037 Test requirement: is_intel_device(fd)
11339 13:40:25.252369 No KMS driver or no outputs, pipes:<14>[ 15.806649] [IGT] kms_addfb_basic: exiting, ret=0
11340 13:40:25.255724 16, outputs: 0
11341 13:40:25.265490 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch<8>[ 15.818622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11342 13:40:25.265818 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11344 13:40:25.268559 64)
11345 13:40:25.272415 Using IGT_SRANDOM=1716903625 for randomisation
11346 13:40:25.275635 Opened device: /dev/dri/card0
11347 13:40:25.279050 Starting subtest: unused-modifier
11348 13:40:25.282385 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11349 13:40:25.288796 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11350 13:40:25.295331 Test requirement: <14>[ 15.849773] [IGT] kms_addfb_basic: executing
11351 13:40:25.298159 is_intel_device(fd)
11352 13:40:25.308449 Test requirement not met in function igt_re<14>[ 15.859559] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11353 13:40:25.318212 quire_intel, fil<14>[ 15.867282] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11354 13:40:25.318299 e ../lib/drmtest.c:880:
11355 13:40:25.321810 Test requirement: is_intel_device(fd)
11356 13:40:25.331588 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 15.884987] [IGT] kms_addfb_basic: exiting, ret=77
11357 13:40:25.331672 0
11358 13:40:25.338056 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11359 13:40:25.344680 Using IG<8>[ 15.897765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11360 13:40:25.344939 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11362 13:40:25.351165 T_SRANDOM=1716903625 for randomisation
11363 13:40:25.351247 Opened device: /dev/dri/card0
11364 13:40:25.354286 Starting subtest: clobberred-modifier
11365 13:40:25.367595 Test requirement not met in function igt_require_i915, file ../lib<14>[ 15.919541] [IGT] kms_addfb_basic: executing
11366 13:40:25.367682 /drmtest.c:885:
11367 13:40:25.370818 Test requirement: is_i915_device(fd)
11368 13:40:25.380995 [1mSubte<14>[ 15.929963] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11369 13:40:25.387430 st clobberred-mo<14>[ 15.939003] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11370 13:40:25.390743 difier: SKIP (0.000s)[0m
11371 13:40:25.404155 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 15.956324] [IGT] kms_addfb_basic: exiting, ret=77
11372 13:40:25.404245 rmtest.c:880:
11373 13:40:25.407321 Test requirement: is_intel_device(fd)
11374 13:40:25.417153 Test requirement not met i<8>[ 15.968607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11375 13:40:25.417494 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11377 13:40:25.424007 n function igt_require_intel, file ../lib/drmtest.c:880:
11378 13:40:25.427151 Test requirement: is_intel_device(fd)
11379 13:40:25.430134 No KMS driver or no outputs, pipes: 16, outputs: 0
11380 13:40:25.436965 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11381 13:40:25.440486 Using IGT_SRANDOM=1716903625 for randomisation
11382 13:40:25.446922 Opened <14>[ 16.000300] [IGT] kms_addfb_basic: executing
11383 13:40:25.447001 device: /dev/dri/card0
11384 13:40:25.456997 Starting subtest: invalid-smem-bo-on-dis<14>[ 16.010507] [IGT] kms_addfb_basic: starting subtest legacy-format
11385 13:40:25.460254 crete
11386 13:40:25.466876 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11387 13:40:25.476702 Test requirement: is_intel_device(fd)<14>[ 16.027928] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11388 13:40:25.476834
11389 13:40:25.483137 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11390 13:40:25.490233 Test requirement not met in function igt_require_i<14>[ 16.044465] [IGT] kms_addfb_basic: exiting, ret=0
11391 13:40:25.493540 ntel, file ../lib/drmtest.c:880:
11392 13:40:25.496776 Test requirement: is_intel_device(fd)
11393 13:40:25.506406 Test re<8>[ 16.057396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11394 13:40:25.506661 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11396 13:40:25.512853 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11397 13:40:25.516121 Test requirement: is_intel_device(fd)
11398 13:40:25.522934 No KMS driver or no outputs, pipes: 16, outp<14>[ 16.078290] [IGT] kms_addfb_basic: executing
11399 13:40:25.526248 uts: 0
11400 13:40:25.529562 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11401 13:40:25.536452 Usin<14>[ 16.089798] [IGT] kms_addfb_basic: starting subtest no-handle
11402 13:40:25.546218 g IGT_SRANDOM=17<14>[ 16.096591] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11403 13:40:25.549408 16903625 for randomisation
11404 13:40:25.549489 Opened device: /dev/dri/card0
11405 13:40:25.555851 Starting subtest: leg<14>[ 16.110573] [IGT] kms_addfb_basic: exiting, ret=0
11406 13:40:25.559058 acy-format
11407 13:40:25.562275 Successfully fuzzed 10000 {bpp, depth} variations
11408 13:40:25.572196 [1mSubtest legac<8>[ 16.123436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11409 13:40:25.572281 y-format: SUCCESS (0.010s)[0m
11410 13:40:25.572542 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11412 13:40:25.581933 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11413 13:40:25.585223 Test requirement: is_intel_device(fd)
11414 13:40:25.592202 Test requirement not <14>[ 16.145158] [IGT] kms_addfb_basic: executing
11415 13:40:25.595580 met in function igt_require_intel, file ../lib/drmtest.c:880:
11416 13:40:25.605357 Test requirement:<14>[ 16.156954] [IGT] kms_addfb_basic: starting subtest basic
11417 13:40:25.611769 is_intel_device<14>[ 16.163282] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11418 13:40:25.611852 (fd)
11419 13:40:25.615091 No KMS driver or no outputs, pipes: 16, outputs: 0
11420 13:40:25.624854 IGT-Version: 1.28-ga44<14>[ 16.176902] [IGT] kms_addfb_basic: exiting, ret=0
11421 13:40:25.628159 ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11422 13:40:25.638065 Using IGT_SRANDOM=1716903625 for r<8>[ 16.189567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11423 13:40:25.638158 andomisation
11424 13:40:25.638407 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11426 13:40:25.641280 Opened device: /dev/dri/card0
11427 13:40:25.645032 Starting subtest: no-handle
11428 13:40:25.648049 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11429 13:40:25.657944 Test requirement not met in function igt_require_intel, f<14>[ 16.210665] [IGT] kms_addfb_basic: executing
11430 13:40:25.658066 ile ../lib/drmtest.c:880:
11431 13:40:25.661207 Test requirement: is_intel_device(fd)
11432 13:40:25.671295 Test requireme<14>[ 16.223040] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11433 13:40:25.678004 nt not met in fu<14>[ 16.229693] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11434 13:40:25.684411 nction igt_require_intel, file ../lib/drmtest.c:880:
11435 13:40:25.690945 Test requirement: is_intel<14>[ 16.244038] [IGT] kms_addfb_basic: exiting, ret=0
11436 13:40:25.691078 _device(fd)
11437 13:40:25.697252 No KMS driver or no outputs, pipes: 16, outputs: 0
11438 13:40:25.704518 IGT-Version: 1.<8>[ 16.256759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11439 13:40:25.704801 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11441 13:40:25.707535 28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11442 13:40:25.714028 Using IGT_SRANDOM=1716903625 for randomisation
11443 13:40:25.717757 Opened device: /dev/dri/card0
11444 13:40:25.717855 Starting subtest: basic
11445 13:40:25.720983 [1mSubtest basic: SUCCESS (0.000s)[0m
11446 13:40:25.734123 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 16.286968] [IGT] kms_addfb_basic: executing
11447 13:40:25.734259 t.c:880:
11448 13:40:25.737400 Test requirement: is_intel_device(fd)
11449 13:40:25.747580 Test requirement not met in function igt_requir<14>[ 16.299801] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11450 13:40:25.757155 e_intel, file ..<14>[ 16.307122] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11451 13:40:25.757292 /lib/drmtest.c:880:
11452 13:40:25.760315 Test requirement: is_intel_device(fd)
11453 13:40:25.766949 No KMS driver or no <14>[ 16.322043] [IGT] kms_addfb_basic: exiting, ret=0
11454 13:40:25.770528 outputs, pipes: 16, outputs: 0
11455 13:40:25.783228 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<8>[ 16.334400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11456 13:40:25.783380 .91-cip21 aarch64)
11457 13:40:25.783665 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11459 13:40:25.787181 Using IGT_SRANDOM=1716903625 for randomisation
11460 13:40:25.789869 Opened device: /dev/dri/card0
11461 13:40:25.793723 Starting subtest: bad-pitch-0
11462 13:40:25.799953 [1mSubtest bad-pitch-0: SUCCE<14>[ 16.355245] [IGT] kms_addfb_basic: executing
11463 13:40:25.803392 SS (0.000s)[0m
11464 13:40:25.813149 Test requirement not met in function igt_require_intel, file ..<14>[ 16.366726] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11465 13:40:25.823404 /lib/drmtest.c:8<14>[ 16.373611] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11466 13:40:25.823578 80:
11467 13:40:25.826722 Test requirement: is_intel_device(fd)
11468 13:40:25.836473 Test requirement not met in function<14>[ 16.388122] [IGT] kms_addfb_basic: exiting, ret=0
11469 13:40:25.839746 igt_require_intel, file ../lib/drmtest.c:880:
11470 13:40:25.849403 Test requirement: is_intel_devic<8>[ 16.400685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11471 13:40:25.849512 e(fd)
11472 13:40:25.849757 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11474 13:40:25.852487 No KMS driver or no outputs, pipes: 16, outputs: 0
11475 13:40:25.859429 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11476 13:40:25.862609 Using IGT_SRANDOM=1716903625 for randomisation
11477 13:40:25.865663 Opened device: /dev/dri/card0
11478 13:40:25.869368 Starting subtest: bad-pitch-32
11479 13:40:25.875973 [1mSubtest bad-pitch-32: SUCCESS <14>[ 16.431114] [IGT] kms_addfb_basic: executing
11480 13:40:25.879498 (0.000s)[0m
11481 13:40:25.892211 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<14>[ 16.443781] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11482 13:40:25.892300
11483 13:40:25.898731 Test requireme<14>[ 16.451287] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11484 13:40:25.902477 nt: is_intel_device(fd)
11485 13:40:25.912222 Test requirement not met in function igt_require_intel,<14>[ 16.466258] [IGT] kms_addfb_basic: exiting, ret=0
11486 13:40:25.915449 file ../lib/drmtest.c:880:
11487 13:40:25.918738 Test requirement: is_intel_device(fd)
11488 13:40:25.925564 No KMS drive<8>[ 16.478707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11489 13:40:25.925821 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11491 13:40:25.928675 r or no outputs, pipes: 16, outputs: 0
11492 13:40:25.935113 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11493 13:40:25.938377 Using IGT_SRANDOM=1716903625 for randomisation
11494 13:40:25.941615 Opened device: /dev/dri/card0
11495 13:40:25.948186 Start<14>[ 16.501425] [IGT] kms_addfb_basic: executing
11496 13:40:25.948265 ing subtest: bad-pitch-63
11497 13:40:25.955280 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11498 13:40:25.961373 Test <14>[ 16.513642] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11499 13:40:25.968284 requirement not <14>[ 16.520663] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11500 13:40:25.974634 met in function igt_require_intel, file ../lib/drmtest.c:880:
11501 13:40:25.981576 Test requirement:<14>[ 16.535230] [IGT] kms_addfb_basic: exiting, ret=0
11502 13:40:25.984696 is_intel_device(fd)
11503 13:40:25.994485 Test requirement not met in function igt_require_intel, fi<8>[ 16.547790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11504 13:40:25.994823 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11506 13:40:25.997643 le ../lib/drmtest.c:880:
11507 13:40:26.001007 Test requirement: is_intel_device(fd)
11508 13:40:26.004623 No KMS driver or no outputs, pipes: 16, outputs: 0
11509 13:40:26.011234 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11510 13:40:26.017667 Using IGT_SRANDOM=1716903625 for randomisation
11511 13:40:26.017745 Opened device: /dev/dri/card0
11512 13:40:26.024354 Starting<14>[ 16.578353] [IGT] kms_addfb_basic: executing
11513 13:40:26.027534 subtest: bad-pitch-128
11514 13:40:26.030773 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11515 13:40:26.037254 Test requirement not m<14>[ 16.591085] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11516 13:40:26.046999 et in function i<14>[ 16.598579] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11517 13:40:26.050402 gt_require_intel, file ../lib/drmtest.c:880:
11518 13:40:26.060683 Test requirement: is_intel_device(<14>[ 16.613793] [IGT] kms_addfb_basic: exiting, ret=0
11519 13:40:26.060763 fd)
11520 13:40:26.073684 Test requirement not met in function igt_require_intel, file ../lib/drmtest<8>[ 16.625892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11521 13:40:26.073769 .c:880:
11522 13:40:26.074011 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11524 13:40:26.076848 Test requirement: is_intel_device(fd)
11525 13:40:26.083285 No KMS driver or no outputs, pipes: 16, outputs: 0
11526 13:40:26.093262 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aa<14>[ 16.647290] [IGT] kms_addfb_basic: executing
11527 13:40:26.093354 rch64)
11528 13:40:26.096430 Using IGT_SRANDOM=1716903625 for randomisation
11529 13:40:26.106599 Opened device: /dev/dri/<14>[ 16.658486] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11530 13:40:26.106687 card0
11531 13:40:26.112905 Starting <14>[ 16.665517] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11532 13:40:26.116215 subtest: bad-pitch-256
11533 13:40:26.119457 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11534 13:40:26.126178 Test re<14>[ 16.680158] [IGT] kms_addfb_basic: exiting, ret=0
11535 13:40:26.132781 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11536 13:40:26.139250 Tes<8>[ 16.692701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11537 13:40:26.139503 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11539 13:40:26.142307 t requirement: is_intel_device(fd)
11540 13:40:26.152833 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11541 13:40:26.156282 Test requirement: is_intel_device(fd)
11542 13:40:26.159493 No KMS driver or no outputs, pipes: 16, outputs: 0
11543 13:40:26.169170 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aar<14>[ 16.723153] [IGT] kms_addfb_basic: executing
11544 13:40:26.169264 ch64)
11545 13:40:26.172522 Using IGT_SRANDOM=1716903626 for randomisation
11546 13:40:26.175654 Opened device: /dev/dri/card0
11547 13:40:26.185239 Starting s<14>[ 16.735923] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11548 13:40:26.192218 ubtest: bad-pitc<14>[ 16.743574] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11549 13:40:26.192301 h-1024
11550 13:40:26.198386 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11551 13:40:26.205388 Test requirement not m<14>[ 16.758746] [IGT] kms_addfb_basic: exiting, ret=0
11552 13:40:26.211542 et in function igt_require_intel, file ../lib/drmtest.c:880:
11553 13:40:26.218318 Test requirement: <8>[ 16.770951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11554 13:40:26.218579 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11556 13:40:26.221633 is_intel_device(fd)
11557 13:40:26.228285 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11558 13:40:26.231519 Test requirement: is_intel_device(fd)
11559 13:40:26.234793 No KMS driver or no outputs, pipes: 16, outputs: 0
11560 13:40:26.241432 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11561 13:40:26.247768 Using IG<14>[ 16.801696] [IGT] kms_addfb_basic: executing
11562 13:40:26.251085 T_SRANDOM=1716903626 for randomisation
11563 13:40:26.254680 Opened device: /dev/dri/card0
11564 13:40:26.257995 Starting subtest: bad-pitch-999
11565 13:40:26.263991 [1mSubt<14>[ 16.816289] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11566 13:40:26.274103 est bad-pitch-99<14>[ 16.823778] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11567 13:40:26.274191 9: SUCCESS (0.000s)[0m
11568 13:40:26.284275 Test requirement not met in function ig<14>[ 16.837393] [IGT] kms_addfb_basic: exiting, ret=0
11569 13:40:26.287380 t_require_intel, file ../lib/drmtest.c:880:
11570 13:40:26.297127 Test requirement: is_intel_device(f<8>[ 16.849979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11571 13:40:26.297456 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11573 13:40:26.300385 d)
11574 13:40:26.307092 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11575 13:40:26.310352 Test requirement: is_intel_device(fd)
11576 13:40:26.313612 No KMS driver or no outputs, pipes: 16, outputs: 0
11577 13:40:26.320410 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11578 13:40:26.327198 Using IGT_SRANDOM=1716903<14>[ 16.881464] [IGT] kms_addfb_basic: executing
11579 13:40:26.330459 626 for randomisation
11580 13:40:26.330535 Opened device: /dev/dri/card0
11581 13:40:26.333754 Starting subtest: bad-pitch-65536
11582 13:40:26.343816 [1mSubtest bad-pitch-6<14>[ 16.896002] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11583 13:40:26.353543 5536: SUCCESS (0<14>[ 16.903069] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11584 13:40:26.353622 .000s)[0m
11585 13:40:26.363621 Test requirement not met in function igt_require_int<14>[ 16.916271] [IGT] kms_addfb_basic: exiting, ret=0
11586 13:40:26.366291 el, file ../lib/drmtest.c:880:
11587 13:40:26.369540 Test requirement: is_intel_device(fd)
11588 13:40:26.376648 Test requ<8>[ 16.929328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11589 13:40:26.376913 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11591 13:40:26.383210 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11592 13:40:26.386448 Test requirement: is_intel_device(fd)
11593 13:40:26.396291 No KMS driver or no outputs, pipes: 16, output<14>[ 16.950397] [IGT] kms_addfb_basic: executing
11594 13:40:26.396371 s: 0
11595 13:40:26.402755 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11596 13:40:26.412518 Using IGT_SRANDOM=1716903626 for rando<14>[ 16.963907] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11597 13:40:26.412604 misation
11598 13:40:26.422894 Opened<14>[ 16.972399] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11599 13:40:26.422980 device: /dev/dri/card0
11600 13:40:26.432624 Starting subtest: inval<14>[ 16.985464] [IGT] kms_addfb_basic: exiting, ret=0
11601 13:40:26.432705 id-get-prop-any
11602 13:40:26.438923 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11603 13:40:26.445417 Test re<8>[ 16.997493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11604 13:40:26.445677 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11606 13:40:26.451989 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11607 13:40:26.455938 Test requirement: is_intel_device(fd)
11608 13:40:26.462296 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11609 13:40:26.465434 Test requirement: is_intel_device(fd)
11610 13:40:26.475369 No KMS driver or no outputs, pipe<14>[ 17.028461] [IGT] kms_addfb_basic: executing
11611 13:40:26.475461 s: 16, outputs: 0
11612 13:40:26.481623 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11613 13:40:26.491918 Using IGT_SRANDOM=1716903<14>[ 17.043156] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11614 13:40:26.498589 626 for randomis<14>[ 17.050215] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11615 13:40:26.501419 ation
11616 13:40:26.501490 Opened device: /dev/dri/card0
11617 13:40:26.511943 Starting subtest: invalid-<14>[ 17.063563] [IGT] kms_addfb_basic: exiting, ret=0
11618 13:40:26.512025 get-prop
11619 13:40:26.514922 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11620 13:40:26.525164 Test requirement n<8>[ 17.076482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11621 13:40:26.525421 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11623 13:40:26.531651 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11624 13:40:26.534767 Test requirement: is_intel_device(fd)
11625 13:40:26.541403 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11626 13:40:26.545144 Test requirement: is_intel_device(fd)
11627 13:40:26.551897 No KMS driver or no outputs, pipes: 16, outp<14>[ 17.106932] [IGT] kms_addfb_basic: executing
11628 13:40:26.554396 uts: 0
11629 13:40:26.558278 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11630 13:40:26.564820 Using IGT_SRANDOM=1716903626 for randomisation
11631 13:40:26.571268 Opened device: /dev/<14>[ 17.123912] [IGT] kms_addfb_basic: starting subtest master-rmfb
11632 13:40:26.571353 dri/card0
11633 13:40:26.580979 Start<14>[ 17.131286] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11634 13:40:26.587760 ing subtest: invalid-set-prop-an<14>[ 17.141905] [IGT] kms_addfb_basic: exiting, ret=0
11635 13:40:26.587843 y
11636 13:40:26.594419 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11637 13:40:26.600942 Test requirement not <8>[ 17.154007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11638 13:40:26.601200 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11640 13:40:26.607167 met in function igt_require_intel, file ../lib/drmtest.c:880:
11641 13:40:26.610973 Test requirement: is_intel_device(fd)
11642 13:40:26.620218 Test requirement not met in function igt_require_intel, fi<14>[ 17.174929] [IGT] kms_addfb_basic: executing
11643 13:40:26.624180 le ../lib/drmtest.c:880:
11644 13:40:26.627276 Test requirement: is_intel_device(fd)
11645 13:40:26.630389 No KMS driver or no outputs, pipes: 16, outputs: 0
11646 13:40:26.640305 IGT-Version: 1.28-ga44ebfe <14>[ 17.192185] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11647 13:40:26.650039 (aarch64) (Linux<14>[ 17.200008] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11648 13:40:26.657124 : 6.1.91-cip21 a<14>[ 17.209670] [IGT] kms_addfb_basic: exiting, ret=0
11649 13:40:26.657214 arch64)
11650 13:40:26.659792 Using IGT_SRANDOM=1716903626 for randomisation
11651 13:40:26.670342 Opened device: /dev/dri<8>[ 17.222754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11652 13:40:26.670602 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11654 13:40:26.673043 /card0
11655 13:40:26.676984 Starting subtest: invalid-set-prop
11656 13:40:26.679586 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11657 13:40:26.686162 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11658 13:40:26.689940 Test requirement: is_intel_device(fd)
11659 13:40:26.699517 Test requirement not met in function igt_require_inte<14>[ 17.254423] [IGT] kms_addfb_basic: executing
11660 13:40:26.703010 l, file ../lib/drmtest.c:880:
11661 13:40:26.706188 Test requirement: is_intel_device(fd)
11662 13:40:26.709653 No KMS driver or no outputs, pipes: 16, outputs: 0
11663 13:40:26.719482 IGT-Version: 1.28-ga44ebfe (aarch64) (<14>[ 17.272929] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11664 13:40:26.722508 Linux: 6.1.91-cip21 aarch64)
11665 13:40:26.726366 Using IGT_SRANDOM=1716903626 for randomisation
11666 13:40:26.729173 Opened device: /dev/dri/card0
11667 13:40:26.739070 Sta<14>[ 17.288500] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11668 13:40:26.746170 rting subtest: m<14>[ 17.297815] [IGT] kms_addfb_basic: exiting, ret=98
11669 13:40:26.746252 aster-rmfb
11670 13:40:26.749389 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11671 13:40:26.758969 Test requirement not <8>[ 17.310747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11672 13:40:26.759227 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11674 13:40:26.765562 met in function igt_require_intel, file ../lib/drmtest.c:880:
11675 13:40:26.768873 Test requirement: is_intel_device(fd)
11676 13:40:26.776014 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11677 13:40:26.779167 Test requirement: is_intel_device(fd)
11678 13:40:26.788892 No KMS driver or no outputs, pipes: 16, outputs<14>[ 17.341751] [IGT] kms_addfb_basic: executing
11679 13:40:26.789027 : 0
11680 13:40:26.791830 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11681 13:40:26.798553 Using IGT_SRANDOM=1716903626 for randomisation
11682 13:40:26.802217 Opened device: /dev/dri/card0
11683 13:40:26.808737 Starting subtest: addfb2<14>[ 17.361127] [IGT] kms_addfb_basic: exiting, ret=77
11684 13:40:26.808822 5-modifier-no-flag
11685 13:40:26.815406 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11686 13:40:26.825249 Test requirement<8>[ 17.374443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11687 13:40:26.825548 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11689 13:40:26.831815 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11690 13:40:26.834932 Test requirement: is_intel_device(fd)
11691 13:40:26.841466 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11692 13:40:26.845194 Test requirement: is_intel_device(fd)
11693 13:40:26.851819 No KMS driver or no outputs, pipes: 16, ou<14>[ 17.407436] [IGT] kms_addfb_basic: executing
11694 13:40:26.855091 tputs: 0
11695 13:40:26.858172 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11696 13:40:26.865096 Using IGT_SRANDOM=1716903626 for randomisation
11697 13:40:26.868309 Opened device: /dev/dri/card0
11698 13:40:26.874999 Starting subtest: a<14>[ 17.426913] [IGT] kms_addfb_basic: exiting, ret=77
11699 13:40:26.875080 ddfb25-bad-modifier
11700 13:40:26.888134 (kms_addfb_basic:432) CRITICAL: Test assertion failure func<8>[ 17.439960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11701 13:40:26.888387 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11703 13:40:26.894811 tion addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11704 13:40:26.911142 (kms_addfb_basic:432) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11705 13:40:26.917799 (kms_add<14>[ 17.471003] [IGT] kms_addfb_basic: executing
11706 13:40:26.921029 fb_basic:432) CRITICAL: error: 0 != -1
11707 13:40:26.921135 Stack trace:
11708 13:40:26.924240 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11709 13:40:26.927933 #1 [<unknown>+0xd5084358]
11710 13:40:26.930993 #2 [<unknown>+0xd5085fbc]
11711 13:40:26.937535 #3 [<unknown><14>[ 17.490723] [IGT] kms_addfb_basic: exiting, ret=77
11712 13:40:26.937619 +0xd508156c]
11713 13:40:26.940814 #4 [__libc_init_first+0x80]
11714 13:40:26.943994 #5 [__libc_start_main+0x98]
11715 13:40:26.954360 #6<8>[ 17.502740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11716 13:40:26.954451 [<unknown>+0xd50815b0]
11717 13:40:26.954698 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11719 13:40:26.957759 Subtest addfb25-bad-modifier failed.
11720 13:40:26.960897 **** DEBUG ****
11721 13:40:26.967097 (kms_addfb_basic:432) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11722 13:40:26.974292 (<14>[ 17.526856] [IGT] kms_addfb_basic: executing
11723 13:40:26.984301 kms_addfb_basic:432) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11724 13:40:26.990191 (kms_addfb_basic:432) CRITICAL: Failed asser<14>[ 17.545319] [IGT] kms_addfb_basic: exiting, ret=77
11725 13:40:27.007114 tion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0x<8>[ 17.557891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11726 13:40:27.007377 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11728 13:40:27.013645 B8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11729 13:40:27.016681 (kms_addfb_basic:432) CRITICAL: error: 0 != -1
11730 13:40:27.023180 (kms_addfb_basic:432) igt_core-INFO: Stack trace:
11731 13:40:27.030120 (kms_addfb_basic:432) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11732 13:40:27.033138 (kms_<14>[ 17.589662] [IGT] kms_addfb_basic: executing
11733 13:40:27.039620 addfb_basic:432) igt_core-INFO: #1 [<unknown>+0xd5084358]
11734 13:40:27.046950 (kms_addfb_basic:432) igt_core-INFO: #2 [<unknown>+0xd5085fbc]
11735 13:40:27.056522 (kms_addfb_basic:432) igt_core-INFO: #3 [<unkno<14>[ 17.608605] [IGT] kms_addfb_basic: exiting, ret=77
11736 13:40:27.056630 wn>+0xd508156c]
11737 13:40:27.069956 (kms_addfb_basic:432) igt_core-INFO: #4 [__libc_init_first+0x<8>[ 17.621783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11738 13:40:27.070048 80]
11739 13:40:27.070290 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11741 13:40:27.076029 (kms_addfb_basic:432) igt_core-INFO: #5 [__libc_start_main+0x98]
11742 13:40:27.083226 (kms_addfb_basic:432) igt_core-INFO: #6 [<unknown>+0xd50815b0]
11743 13:40:27.083328 **** END ****
11744 13:40:27.089389 [1mSubtest addfb25-<14>[ 17.643909] [IGT] kms_addfb_basic: executing
11745 13:40:27.093285 bad-modifier: FAIL (0.008s)[0m
11746 13:40:27.099736 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11747 13:40:27.103126 Test requirement: is_intel_device(fd)
11748 13:40:27.109797 Test<14>[ 17.662760] [IGT] kms_addfb_basic: exiting, ret=77
11749 13:40:27.115853 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11750 13:40:27.122399 <8>[ 17.675309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11751 13:40:27.122656 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11753 13:40:27.125996 Test requirement: is_intel_device(fd)
11754 13:40:27.132348 No KMS driver or no outputs, pipes: 16, outputs: 0
11755 13:40:27.139371 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11756 13:40:27.142434 Using IGT_SRANDOM=1716903626 for randomisation
11757 13:40:27.145687 Opened device: /dev/dri/card0
11758 13:40:27.152362 Test requirement not met in functi<14>[ 17.706632] [IGT] kms_addfb_basic: executing
11759 13:40:27.155640 on igt_require_intel, file ../lib/drmtest.c:880:
11760 13:40:27.158992 Test requirement: is_intel_device(fd)
11761 13:40:27.165355 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11762 13:40:27.172129 Test requirement not me<14>[ 17.726037] [IGT] kms_addfb_basic: exiting, ret=77
11763 13:40:27.178876 t in function igt_require_intel, file ../lib/drmtest.c:880:
11764 13:40:27.188333 Test requirement: i<8>[ 17.738997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11765 13:40:27.188497 s_intel_device(fd)
11766 13:40:27.188785 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11768 13:40:27.195320 No KMS driver or no outputs, pipes: 16, outputs: 0
11769 13:40:27.198589 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11770 13:40:27.208424 Using IGT_SRANDOM=1716903626 for ran<14>[ 17.760991] [IGT] kms_addfb_basic: executing
11771 13:40:27.208541 domisation
11772 13:40:27.211839 Opened device: /dev/dri/card0
11773 13:40:27.218298 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11774 13:40:27.224824 Test requirement: is_intel_device<14>[ 17.779762] [IGT] kms_addfb_basic: exiting, ret=77
11775 13:40:27.227954 (fd)
11776 13:40:27.231645 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11777 13:40:27.241235 Test requirement no<8>[ 17.792414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11778 13:40:27.241533 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11780 13:40:27.244519 t met in function igt_require_intel, file ../lib/drmtest.c:880:
11781 13:40:27.248177 Test requirement: is_intel_device(fd)
11782 13:40:27.254601 No KMS driver or no outputs, pipes: 16, outputs: 0
11783 13:40:27.261406 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11784 13:40:27.264687 Using IGT_SRANDOM=1716903626 for randomisation
11785 13:40:27.267943 <14>[ 17.822791] [IGT] kms_addfb_basic: executing
11786 13:40:27.271407 Opened device: /dev/dri/card0
11787 13:40:27.277944 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11788 13:40:27.281377 Test requirement: is_intel_device(fd)
11789 13:40:27.288076 [1mSubtest addfb25-fr<14>[ 17.842303] [IGT] kms_addfb_basic: exiting, ret=77
11790 13:40:27.294767 amebuffer-vs-set-tiling: SKIP (0.000s)[0m
11791 13:40:27.301558 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11793 13:40:27.304383 Test requirement not met in function<8>[ 17.855273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11794 13:40:27.307305 igt_require_intel, file ../lib/drmtest.c:880:
11795 13:40:27.310634 Test requirement: is_intel_device(fd)
11796 13:40:27.314036 No KMS driver or no outputs, pipes: 16, outputs: 0
11797 13:40:27.324110 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 17.876105] [IGT] kms_addfb_basic: executing
11798 13:40:27.324566 (Linux: 6.1.91-cip21 aarch64)
11799 13:40:27.330527 Using IGT_SRANDOM=1716903627 for randomisation
11800 13:40:27.333825 Opened device: /dev/dri/card0
11801 13:40:27.340148 Test requirement not met in functi<14>[ 17.894361] [IGT] kms_addfb_basic: exiting, ret=77
11802 13:40:27.344017 on igt_require_intel, file ../lib/drmtest.c:880:
11803 13:40:27.353546 Test requirement: is_intel_dev<8>[ 17.906411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11804 13:40:27.353629 ice(fd)
11805 13:40:27.353869 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11807 13:40:27.363266 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11808 13:40:27.366661 Test requirement: is_intel_device(fd)
11809 13:40:27.373220 [1mSubtest basic-x-tiled-le<14>[ 17.926504] [IGT] kms_addfb_basic: executing
11810 13:40:27.373342 gacy: SKIP (0.000s)[0m
11811 13:40:27.379870 No KMS driver or no outputs, pipes: 16, outputs: 0
11812 13:40:27.386066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11813 13:40:27.392546 Using IGT_SRAND<14>[ 17.944467] [IGT] kms_addfb_basic: exiting, ret=77
11814 13:40:27.392625 OM=1716903627 for randomisation
11815 13:40:27.396307 Opened device: /dev/dri/card0
11816 13:40:27.406042 Test requirement<8>[ 17.957495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11817 13:40:27.406295 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11819 13:40:27.412519 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11820 13:40:27.416269 Test requirement: is_intel_device(fd)
11821 13:40:27.422563 Test requirement not met in function igt_require_inte<14>[ 17.978198] [IGT] kms_addfb_basic: executing
11822 13:40:27.426028 l, file ../lib/drmtest.c:880:
11823 13:40:27.429172 Test requirement: is_intel_device(fd)
11824 13:40:27.436138 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11825 13:40:27.442665 No KMS driver or no outputs, pip<14>[ 17.995864] [IGT] kms_addfb_basic: exiting, ret=77
11826 13:40:27.446004 es: 16, outputs: 0
11827 13:40:27.456082 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aa<8>[ 18.009023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11828 13:40:27.456167 rch64)
11829 13:40:27.456409 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11831 13:40:27.462189 Using IGT_SRANDOM=1716903627 for randomisation
11832 13:40:27.465499 Opened device: /dev/dri/card0
11833 13:40:27.472009 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11834 13:40:27.475280 Test <14>[ 18.030374] [IGT] kms_addfb_basic: executing
11835 13:40:27.478579 requirement: is_intel_device(fd)
11836 13:40:27.485139 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11837 13:40:27.488907 Test requirement: is_intel_device(fd)
11838 13:40:27.495424 [1<14>[ 18.048587] [IGT] kms_addfb_basic: exiting, ret=77
11839 13:40:27.498619 mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11840 13:40:27.512057 No KMS driver or no outputs, pi<8>[ 18.061737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11841 13:40:27.512174 pes: 16, outputs: 0
11842 13:40:27.512419 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11844 13:40:27.518533 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11845 13:40:27.521714 Using IGT_SRANDOM=1716903627 for randomisation
11846 13:40:27.524881 Opened device: /dev/dri/card0
11847 13:40:27.531773 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11848 13:40:27.538138 Test requirement: is<14>[ 18.093356] [IGT] kms_addfb_basic: executing
11849 13:40:27.541145 _intel_device(fd)
11850 13:40:27.548186 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11851 13:40:27.551415 Test requirement: is_intel_device(fd)
11852 13:40:27.558025 [1mSubtest basic-y-tiled-legacy: <14>[ 18.112876] [IGT] kms_addfb_basic: exiting, ret=77
11853 13:40:27.561064 SKIP (0.000s)[0m
11854 13:40:27.564173 No KMS driver or no outputs, pipes: 16, outputs: 0
11855 13:40:27.574624 IGT-Versi<8>[ 18.125799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11856 13:40:27.574907 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11858 13:40:27.577968 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11859 13:40:27.584492 Using IGT_SRANDOM=1716903627 for randomisation
11860 13:40:27.587734 Opened device: /dev/dri/card0
11861 13:40:27.594274 Test requirement not met in function i<14>[ 18.147783] [IGT] kms_addfb_basic: executing
11862 13:40:27.597394 gt_require_intel, file ../lib/drmtest.c:880:
11863 13:40:27.600646 Test requirement: is_intel_device(fd)
11864 13:40:27.613997 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 18.166285] [IGT] kms_addfb_basic: exiting, ret=77
11865 13:40:27.614113 .c:880:
11866 13:40:27.617194 Test requirement: is_intel_device(fd)
11867 13:40:27.627136 No KMS driver or no outputs, pip<8>[ 18.179351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11868 13:40:27.627410 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11870 13:40:27.630838 es: 16, outputs: 0
11871 13:40:27.633998 [1mSubtest size-max: SKIP (0.000s)[0m
11872 13:40:27.640469 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11873 13:40:27.647473 Using IGT_SRANDOM=1716903627 fo<14>[ 18.200832] [IGT] kms_addfb_basic: executing
11874 13:40:27.647565 r randomisation
11875 13:40:27.650537 Opened device: /dev/dri/card0
11876 13:40:27.657411 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11877 13:40:27.666673 Test requirement: is_intel_d<14>[ 18.219044] [IGT] kms_addfb_basic: exiting, ret=77
11878 13:40:27.666776 evice(fd)
11879 13:40:27.680372 Test requirement not met in function igt_require_intel, file ../lib/d<8>[ 18.231646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11880 13:40:27.680648 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11882 13:40:27.683308 rmtest.c:880:
11883 13:40:27.686473 Test requirement: is_intel_device(fd)
11884 13:40:27.689782 No KMS driver or no outputs, pipes: 16, outputs: 0
11885 13:40:27.693075 [1mSubtest too-wide: SKIP (0.000s)[0m
11886 13:40:27.700052 IGT-Version: 1.28-ga44ebfe (a<14>[ 18.255040] [IGT] kms_addfb_basic: executing
11887 13:40:27.703344 arch64) (Linux: 6.1.91-cip21 aarch64)
11888 13:40:27.710073 Using IGT_SRANDOM=1716903627 for randomisation
11889 13:40:27.710173 Opened device: /dev/dri/card0
11890 13:40:27.720057 Test requirement not met in function igt_r<14>[ 18.273260] [IGT] kms_addfb_basic: exiting, ret=77
11891 13:40:27.723069 equire_intel, file ../lib/drmtest.c:880:
11892 13:40:27.726380 Test requirement: is_intel_device(fd)
11893 13:40:27.732911 <8>[ 18.286523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11894 13:40:27.733003
11895 13:40:27.733246 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11897 13:40:27.739884 Test requiremen<8>[ 18.295169] <LAVA_SIGNAL_TESTSET STOP>
11898 13:40:27.740141 Received signal: <TESTSET> STOP
11899 13:40:27.740211 Closing test_set kms_addfb_basic
11900 13:40:27.746393 t not met in function igt_require_intel, file ../lib/drmtest.c:880:
11901 13:40:27.749571 Test requirement: is_intel_device(fd)
11902 13:40:27.752789 No KMS driver or no outputs, pipes: 16, outputs: 0
11903 13:40:27.756000 [1mSubtest too-high: SKIP (0.000s)[0m
11904 13:40:27.762619 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11905 13:40:27.765786 Using IGT_SRANDOM=1716903627 for randomisation
11906 13:40:27.772532 Ope<8>[ 18.326198] <LAVA_SIGNAL_TESTSET START kms_atomic>
11907 13:40:27.772860 Received signal: <TESTSET> START kms_atomic
11908 13:40:27.772981 Starting test_set kms_atomic
11909 13:40:27.776207 ned device: /dev/dri/card0
11910 13:40:27.782332 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11911 13:40:27.785777 Test requirement: is_intel_device(fd)
11912 13:40:27.792487 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11913 13:40:27.799215 Test requirement: is_<14>[ 18.354116] [IGT] kms_atomic: executing
11914 13:40:27.805576 intel_device(fd)<14>[ 18.359389] [IGT] kms_atomic: exiting, ret=77
11915 13:40:27.805668
11916 13:40:27.808850 No KMS driver or no outputs, pipes: 16, outputs: 0
11917 13:40:27.818652 [1mSubtes<8>[ 18.370210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11918 13:40:27.818929 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11920 13:40:27.822699 t bo-too-small: SKIP (0.000s)[0m
11921 13:40:27.828941 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11922 13:40:27.832306 Using IGT_SRANDOM=1716903627 for randomisation
11923 13:40:27.838606 Opened device: /dev/dri/c<14>[ 18.392327] [IGT] kms_atomic: executing
11924 13:40:27.838692 ard0
11925 13:40:27.845542 Test requi<14>[ 18.397985] [IGT] kms_atomic: exiting, ret=77
11926 13:40:27.852174 rement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11927 13:40:27.858738 Test r<8>[ 18.409541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11928 13:40:27.858997 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11930 13:40:27.861876 equirement: is_intel_device(fd)
11931 13:40:27.868555 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11932 13:40:27.871771 Test requirement: is_intel_device(fd)
11933 13:40:27.878045 No KMS driver or no outputs, pipes: 16, outputs: 0
11934 13:40:27.881869 [1mSubtest small-bo: SKIP (0.000s)[0m
11935 13:40:27.885079 IGT-Version: 1.28-ga44e<14>[ 18.441696] [IGT] kms_atomic: executing
11936 13:40:27.891588 bfe (aarch64) (L<14>[ 18.447086] [IGT] kms_atomic: exiting, ret=77
11937 13:40:27.894776 inux: 6.1.91-cip21 aarch64)
11938 13:40:27.908094 Using IGT_SRANDOM=1716903627 for ra<8>[ 18.457643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11939 13:40:27.908215 ndomisation
11940 13:40:27.908500 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11942 13:40:27.911149 Opened device: /dev/dri/card0
11943 13:40:27.917743 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11944 13:40:27.921011 Test requirement: is_intel_device(fd)
11945 13:40:27.927625 Test requ<14>[ 18.481674] [IGT] kms_atomic: executing
11946 13:40:27.930865 irement not met <14>[ 18.486838] [IGT] kms_atomic: exiting, ret=77
11947 13:40:27.938073 in function igt_require_intel, file ../lib/drmtest.c:880:
11948 13:40:27.947632 Test requirement: is_<8>[ 18.498552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11949 13:40:27.947754 intel_device(fd)
11950 13:40:27.948038 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11952 13:40:27.954395 No KMS driver or no outputs, pipes: 16, outputs: 0
11953 13:40:27.957736 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11954 13:40:27.964199 IGT-Version: 1.28-ga44ebfe (aar<14>[ 18.520542] [IGT] kms_atomic: executing
11955 13:40:27.970709 ch64) (Linux: 6.<14>[ 18.525622] [IGT] kms_atomic: exiting, ret=77
11956 13:40:27.973870 1.91-cip21 aarch64)
11957 13:40:27.977215 Using IGT_SRANDOM=1716903627 for randomisation
11958 13:40:27.984344 Opened devi<8>[ 18.537436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11959 13:40:27.984633 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11961 13:40:27.987551 ce: /dev/dri/card0
11962 13:40:27.993845 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11963 13:40:27.997189 Test requirement: is_intel_device(fd)
11964 13:40:28.003839 Test requirement not met in funct<14>[ 18.558879] [IGT] kms_atomic: executing
11965 13:40:28.010368 ion igt_require_<14>[ 18.564901] [IGT] kms_atomic: exiting, ret=77
11966 13:40:28.013577 intel, file ../lib/drmtest.c:880:
11967 13:40:28.016823 Test requirement: is_intel_device(fd)
11968 13:40:28.023590 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11970 13:40:28.027262 No KMS<8>[ 18.576855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11971 13:40:28.029920 driver or no outputs, pipes: 16, outputs: 0
11972 13:40:28.033268 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11973 13:40:28.039849 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11974 13:40:28.043197 Using IGT_SRANDOM=1716903627 for randomisation
11975 13:40:28.046943 Opened device: /dev/dri/card0
11976 13:40:28.053108 Test requirement not met<14>[ 18.608055] [IGT] kms_atomic: executing
11977 13:40:28.059796 in function igt<14>[ 18.613676] [IGT] kms_atomic: exiting, ret=77
11978 13:40:28.063102 _require_intel, file ../lib/drmtest.c:880:
11979 13:40:28.072912 Test requirement: is_intel_device(fd<8>[ 18.625950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11980 13:40:28.073006 )
11981 13:40:28.073249 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11983 13:40:28.083407 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11984 13:40:28.086048 Test requirement: is_intel_device(fd)
11985 13:40:28.089883 No KMS driver or no outputs, pipes: 16, outputs: 0
11986 13:40:28.093007 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11987 13:40:28.102567 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-ci<14>[ 18.657952] [IGT] kms_atomic: executing
11988 13:40:28.102709 p21 aarch64)
11989 13:40:28.109229 Us<14>[ 18.663617] [IGT] kms_atomic: exiting, ret=77
11990 13:40:28.112534 ing IGT_SRANDOM=1716903627 for randomisation
11991 13:40:28.115751 Opened device: /dev/dri/card0
11992 13:40:28.126068 Test requirement not met in functio<8>[ 18.677826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11993 13:40:28.126374 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11995 13:40:28.132630 n igt_require_intel, file ../lib/drmtest.c:880:
11996 13:40:28.135741 Test requirement: is_intel_device(fd)
11997 13:40:28.142357 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11998 13:40:28.145712 Test requirement: is_intel_device(fd)
11999 13:40:28.148764 No KMS driver or no outputs, pipes: 16, outputs: 0
12000 13:40:28.155725 [1mSubtest addfb25-y-til<14>[ 18.711231] [IGT] kms_atomic: executing
12001 13:40:28.162073 ed-small-legacy:<14>[ 18.717162] [IGT] kms_atomic: exiting, ret=77
12002 13:40:28.165428 SKIP (0.000s)[0m
12003 13:40:28.168926 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12004 13:40:28.178621 Using IG<8>[ 18.729695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12005 13:40:28.178915 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12007 13:40:28.181873 T_SRANDOM=1716903627 for randomisation
12008 13:40:28.185096 Opened device: /dev/dri/card0
12009 13:40:28.191588 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12010 13:40:28.197991 Test requirement: is_intel_device(fd)<14>[ 18.754769] [IGT] kms_atomic: executing
12011 13:40:28.198074
12012 13:40:28.204825 Test requireme<14>[ 18.759594] [IGT] kms_atomic: exiting, ret=77
12013 13:40:28.211285 nt not met in function igt_require_intel, file ../lib/drmtest.c:880:
12014 13:40:28.221599 Test requi<8>[ 18.771662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12015 13:40:28.221892 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12017 13:40:28.225024 rement: is_intel_device(fd)
12018 13:40:28.228222 No KMS driver or no outputs, pipes: 16, outputs: 0
12019 13:40:28.231250 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12020 13:40:28.237939 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12021 13:40:28.244371 Using IGT_S<14>[ 18.797294] [IGT] kms_atomic: executing
12022 13:40:28.247706 RANDOM=171690362<14>[ 18.803177] [IGT] kms_atomic: exiting, ret=77
12023 13:40:28.250866 7 for randomisation
12024 13:40:28.254433 Opened device: /dev/dri/card0
12025 13:40:28.264151 No KMS driver or no outputs,<8>[ 18.815027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12026 13:40:28.264427 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12028 13:40:28.267559 pipes: 16, outputs: 0
12029 13:40:28.270803 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12030 13:40:28.277152 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12031 13:40:28.280729 Using IGT_SRAND<14>[ 18.836900] [IGT] kms_atomic: executing
12032 13:40:28.287006 OM=1716903627 fo<14>[ 18.842275] [IGT] kms_atomic: exiting, ret=77
12033 13:40:28.290666 r randomisation
12034 13:40:28.293957 Opened device: /dev/dri/card0
12035 13:40:28.303523 No KMS driver or no outputs, pip<8>[ 18.854011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12036 13:40:28.303619 es: 16, outputs: 0
12037 13:40:28.303895 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12039 13:40:28.309961 [1mSubtest <8>[ 18.864112] <LAVA_SIGNAL_TESTSET STOP>
12040 13:40:28.310254 Received signal: <TESTSET> STOP
12041 13:40:28.310340 Closing test_set kms_atomic
12042 13:40:28.313849 plane-primary-legacy: SKIP (0.000s)[0m
12043 13:40:28.320423 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12044 13:40:28.323539 Using IGT_SRANDOM=1716903627 for randomisation
12045 13:40:28.326693 Opened device: /dev/dri/card0
12046 13:40:28.329974 No KMS driver or no outputs, pipes: 16, outputs: 0
12047 13:40:28.336857 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12048 13:40:28.342847 IGT-Version: <8>[ 18.895889] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12049 13:40:28.343211 Received signal: <TESTSET> START kms_flip_event_leak
12050 13:40:28.343372 Starting test_set kms_flip_event_leak
12051 13:40:28.346812 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12052 13:40:28.353210 Using IGT_SRANDOM=1716903627 for randomisation
12053 13:40:28.353365 Opened device: /dev/dri/card0
12054 13:40:28.359745 No KMS driver or no outputs, pipes: 16, outputs: 0
12055 13:40:28.363005 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12056 13:40:28.369689 IGT-Version: 1.28<14>[ 18.924766] [IGT] kms_flip_event_leak: executing
12057 13:40:28.376496 -ga44ebfe (aarch<14>[ 18.930936] [IGT] kms_flip_event_leak: exiting, ret=77
12058 13:40:28.379910 64) (Linux: 6.1.91-cip21 aarch64)
12059 13:40:28.389533 Using IGT_SRANDOM=1716903628 for randomisatio<8>[ 18.943031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12060 13:40:28.389636 n
12061 13:40:28.389879 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12063 13:40:28.395869 Opened device: /dev/dri/card0<8>[ 18.951922] <LAVA_SIGNAL_TESTSET STOP>
12064 13:40:28.395970
12065 13:40:28.396205 Received signal: <TESTSET> STOP
12066 13:40:28.396273 Closing test_set kms_flip_event_leak
12067 13:40:28.402563 No KMS driver or no outputs, pipes: 16, outputs: 0
12068 13:40:28.406033 [1mSubtest test-only: SKIP (0.000s)[0m
12069 13:40:28.412540 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12070 13:40:28.415840 Using IGT_SRANDOM=1716903628 for randomisation
12071 13:40:28.418865 Opened device: /dev/dri/card0
12072 13:40:28.422819 No KMS driver or no outputs, pipes: 16, outputs: 0
12073 13:40:28.429151 [1mSubtest plane-cursor-<8>[ 18.983898] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12074 13:40:28.429421 Received signal: <TESTSET> START kms_prop_blob
12075 13:40:28.429527 Starting test_set kms_prop_blob
12076 13:40:28.432474 legacy: SKIP (0.000s)[0m
12077 13:40:28.438985 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12078 13:40:28.442234 Using IGT_SRANDOM=1716903628 for randomisation
12079 13:40:28.445302 Opened device: /dev/dri/card0
12080 13:40:28.448607 No KMS driver or no outputs, pipes: 16, outputs: 0
12081 13:40:28.458937 [1mSubtest plane-invalid-params: SKIP (0.000s<14>[ 19.012437] [IGT] kms_prop_blob: executing
12082 13:40:28.459025 )[0m
12083 13:40:28.465502 IGT-Versi<14>[ 19.018980] [IGT] kms_prop_blob: starting subtest basic
12084 13:40:28.471966 on: 1.28-ga44ebf<14>[ 19.025386] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12085 13:40:28.478621 e (aarch64) (Lin<14>[ 19.033191] [IGT] kms_prop_blob: exiting, ret=0
12086 13:40:28.482052 ux: 6.1.91-cip21 aarch64)
12087 13:40:28.485091 Using IGT_SRANDOM=1716903628 for randomisation
12088 13:40:28.491783 Opene<8>[ 19.046019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12089 13:40:28.492047 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12091 13:40:28.494565 d device: /dev/dri/card0
12092 13:40:28.498224 No KMS driver or no outputs, pipes: 16, outputs: 0
12093 13:40:28.504739 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12094 13:40:28.511272 IGT-Version: 1.28-ga44e<14>[ 19.066590] [IGT] kms_prop_blob: executing
12095 13:40:28.518004 bfe (aarch64) (L<14>[ 19.071410] [IGT] kms_prop_blob: starting subtest blob-prop-core
12096 13:40:28.527773 inux: 6.1.91-cip<14>[ 19.078954] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12097 13:40:28.527881 21 aarch64)
12098 13:40:28.534642 Usi<14>[ 19.087529] [IGT] kms_prop_blob: exiting, ret=0
12099 13:40:28.537594 ng IGT_SRANDOM=1716903628 for randomisation
12100 13:40:28.540857 Opened device: /dev/dri/card0
12101 13:40:28.547375 No K<8>[ 19.099825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12102 13:40:28.547671 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12104 13:40:28.550660 MS driver or no outputs, pipes: 16, outputs: 0
12105 13:40:28.557300 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12106 13:40:28.564393 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12107 13:40:28.570818 Using IGT_SRANDOM=171690<14>[ 19.123859] [IGT] kms_prop_blob: executing
12108 13:40:28.577487 3628 for randomi<14>[ 19.129394] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12109 13:40:28.577599 sation
12110 13:40:28.587284 Opened d<14>[ 19.137361] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12111 13:40:28.593799 evice: /dev/dri/<14>[ 19.146227] [IGT] kms_prop_blob: exiting, ret=0
12112 13:40:28.593881 card0
12113 13:40:28.596916 No KMS driver or no outputs, pipes: 16, outputs: 0
12114 13:40:28.606985 [1mSubtest crtc-inva<8>[ 19.158649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12115 13:40:28.607260 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12117 13:40:28.610125 lid-params-fence: SKIP (0.000s)[0m
12118 13:40:28.616997 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12119 13:40:28.620165 Using IGT_SRANDOM=1716903628 for randomisation
12120 13:40:28.626720 Opened <14>[ 19.179878] [IGT] kms_prop_blob: executing
12121 13:40:28.632902 device: /dev/dri<14>[ 19.185633] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12122 13:40:28.633017 /card0
12123 13:40:28.642959 No KMS d<14>[ 19.193569] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12124 13:40:28.649465 river or no outp<14>[ 19.202629] [IGT] kms_prop_blob: exiting, ret=0
12125 13:40:28.652892 uts, pipes: 16, outputs: 0
12126 13:40:28.662648 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m<8>[ 19.214704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12127 13:40:28.662744
12128 13:40:28.662985 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12130 13:40:28.669737 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12131 13:40:28.672996 Using IGT_SRANDOM=1716903628 for randomisation
12132 13:40:28.676304 Opened device: /dev/dri/card0
12133 13:40:28.682795 No KMS driv<14>[ 19.236264] [IGT] kms_prop_blob: executing
12134 13:40:28.689181 er or no outputs<14>[ 19.241845] [IGT] kms_prop_blob: starting subtest blob-multiple
12135 13:40:28.699044 , pipes: 16, out<14>[ 19.249397] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12136 13:40:28.699144 puts: 0
12137 13:40:28.705537 [1mSub<14>[ 19.257774] [IGT] kms_prop_blob: exiting, ret=0
12138 13:40:28.708715 test atomic-plane-damage: SKIP (0.000s)[0m
12139 13:40:28.718884 IGT-Version: 1.28-ga44ebfe (aarch64<8>[ 19.270121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12140 13:40:28.719196 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12142 13:40:28.721922 ) (Linux: 6.1.91-cip21 aarch64)
12143 13:40:28.725500 Using IGT_SRANDOM=1716903628 for randomisation
12144 13:40:28.728647 Opened device: /dev/dri/card0
12145 13:40:28.731927 No KMS driver or no outputs, pipes: 16, outputs: 0
12146 13:40:28.735411 [1mSubtest basic: SKIP (0.000s)[0m
12147 13:40:28.742161 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12148 13:40:28.745078 Us<14>[ 19.301073] [IGT] kms_prop_blob: executing
12149 13:40:28.755288 ing IGT_SRANDOM=<14>[ 19.306880] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12150 13:40:28.764767 1716903628 for r<14>[ 19.314521] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12151 13:40:28.764878 andomisation
12152 13:40:28.771830 Op<14>[ 19.323607] [IGT] kms_prop_blob: exiting, ret=0
12153 13:40:28.771916 ened device: /dev/dri/card0
12154 13:40:28.775068 Starting subtest: basic
12155 13:40:28.784885 [1mSubtest basic: SUCCESS<8>[ 19.336621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12156 13:40:28.784981 (0.000s)[0m
12157 13:40:28.785226 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12159 13:40:28.791419 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12160 13:40:28.794712 Using IGT_SRANDOM=1716903628 for randomisation
12161 13:40:28.797991 Opened device: /dev/dri/card0
12162 13:40:28.801334 Starting subtest: blob-prop-core
12163 13:40:28.804470 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12164 13:40:28.810883 IGT-Version: 1.28-ga44ebfe<14>[ 19.367753] [IGT] kms_prop_blob: executing
12165 13:40:28.821382 (aarch64) (Linu<14>[ 19.373153] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12166 13:40:28.830869 x: 6.1.91-cip21 <14>[ 19.380634] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12167 13:40:28.830981 aarch64)
12168 13:40:28.834623 Using <14>[ 19.389476] [IGT] kms_prop_blob: exiting, ret=0
12169 13:40:28.840637 IGT_SRANDOM=1716903628 for randomisation
12170 13:40:28.840724 Opened device: /dev/dri/card0
12171 13:40:28.851066 Starting subtest: blob-<8>[ 19.402845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12172 13:40:28.851371 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12174 13:40:28.853867 prop-validate
12175 13:40:28.857310 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12176 13:40:28.863998 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12177 13:40:28.870495 Using IGT_SRANDOM=17169<14>[ 19.424955] [IGT] kms_prop_blob: executing
12178 13:40:28.876955 03628 for random<14>[ 19.429833] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12179 13:40:28.877075 isation
12180 13:40:28.887419 Opened <14>[ 19.438044] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12181 13:40:28.893735 device: /dev/dri<14>[ 19.447095] [IGT] kms_prop_blob: exiting, ret=0
12182 13:40:28.893823 /card0
12183 13:40:28.897143 Starting subtest: blob-prop-lifetime
12184 13:40:28.906833 [1mSubtest blob-p<8>[ 19.457576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12185 13:40:28.907092 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12187 13:40:28.910609 rop-lifetime: SUCCESS (0.000s)[0m
12188 13:40:28.917142 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12189 13:40:28.920274 Using IGT_SRANDOM=1716903628 for randomisation
12190 13:40:28.923434 Opened d<14>[ 19.480021] [IGT] kms_prop_blob: executing
12191 13:40:28.933253 evice: /dev/dri/<14>[ 19.485230] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12192 13:40:28.933367 card0
12193 13:40:28.943430 Starting <14>[ 19.493065] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12194 13:40:28.946401 subtest: blob-mu<14>[ 19.501706] [IGT] kms_prop_blob: exiting, ret=0
12195 13:40:28.949533 ltiple
12196 13:40:28.952808 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12197 13:40:28.959828 IGT-Ver<8>[ 19.512440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12198 13:40:28.960084 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12200 13:40:28.966395 sion: 1.28-ga44e<8>[ 19.522234] <LAVA_SIGNAL_TESTSET STOP>
12201 13:40:28.966643 Received signal: <TESTSET> STOP
12202 13:40:28.966715 Closing test_set kms_prop_blob
12203 13:40:28.969381 bfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12204 13:40:28.976158 Using IGT_SRANDOM=1716903628 for randomisation
12205 13:40:28.976248 Opened device: /dev/dri/card0
12206 13:40:28.979463 Starting subtest: invalid-get-prop-any
12207 13:40:28.989382 [1mSubtest invalid-get-prop<8>[ 19.542371] <LAVA_SIGNAL_TESTSET START kms_setmode>
12208 13:40:28.989471 -any: SUCCESS (0.000s)[0m
12209 13:40:28.989750 Received signal: <TESTSET> START kms_setmode
12210 13:40:28.989869 Starting test_set kms_setmode
12211 13:40:28.996231 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12212 13:40:28.999788 Using IGT_SRANDOM=1716903628 for randomisation
12213 13:40:29.006078 Opened device: /<14>[ 19.561572] [IGT] kms_setmode: executing
12214 13:40:29.009222 dev/dri/card0
12215 13:40:29.012435 S<14>[ 19.567189] [IGT] kms_setmode: starting subtest basic
12216 13:40:29.018942 tarting subtest:<14>[ 19.573328] [IGT] kms_setmode: finished subtest basic, SKIP
12217 13:40:29.025552 invalid-get-pro<14>[ 19.580701] [IGT] kms_setmode: exiting, ret=77
12218 13:40:29.025650 p
12219 13:40:29.032627 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12220 13:40:29.039222 IGT-Versi<8>[ 19.591250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12221 13:40:29.039485 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12223 13:40:29.045866 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12224 13:40:29.048779 Using IGT_SRANDOM=1716903628 for randomisation
12225 13:40:29.052463 Opened device: /dev/dri/card0
12226 13:40:29.055385 Starting subtest: invalid-set-prop-any
12227 13:40:29.059196 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12228 13:40:29.069024 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-ci<14>[ 19.622779] [IGT] kms_setmode: executing
12229 13:40:29.069139 p21 aarch64)
12230 13:40:29.075367 Us<14>[ 19.628828] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12231 13:40:29.085263 ing IGT_SRANDOM=<14>[ 19.636543] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12232 13:40:29.091858 1716903628 for r<14>[ 19.645492] [IGT] kms_setmode: exiting, ret=77
12233 13:40:29.091955 andomisation
12234 13:40:29.095146 Opened device: /dev/dri/card0
12235 13:40:29.104859 Starting subtest: i<8>[ 19.656663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12236 13:40:29.105207 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12238 13:40:29.108073 nvalid-set-prop
12239 13:40:29.111538 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12240 13:40:29.118076 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12241 13:40:29.121246 Using IGT_SRANDOM=1716903629 for randomisation
12242 13:40:29.124480 Opened device: /dev/dri/card0
12243 13:40:29.124566 Starting subtest: basic
12244 13:40:29.128130 No dynamic tests executed.
12245 13:40:29.134797 [1mSubtest basic: <14>[ 19.689522] [IGT] kms_setmode: executing
12246 13:40:29.144792 SKIP (0.000s)[0<14>[ 19.695023] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12247 13:40:29.144890 m
12248 13:40:29.151146 IGT-Version: <14>[ 19.703234] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12249 13:40:29.157460 1.28-ga44ebfe (a<14>[ 19.712182] [IGT] kms_setmode: exiting, ret=77
12250 13:40:29.161134 arch64) (Linux: 6.1.91-cip21 aarch64)
12251 13:40:29.167387 Using IGT_SRANDOM=1716903629 for randomisation
12252 13:40:29.174360 Opened de<8>[ 19.725619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12253 13:40:29.174628 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12255 13:40:29.177710 vice: /dev/dri/card0
12256 13:40:29.181136 Starting subtest: basic-clone-single-crtc
12257 13:40:29.184363 No dynamic tests executed.
12258 13:40:29.187560 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12259 13:40:29.194069 IGT-Version<14>[ 19.748391] [IGT] kms_setmode: executing
12260 13:40:29.200473 : 1.28-ga44ebfe <14>[ 19.753335] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12261 13:40:29.210705 (aarch64) (Linux<14>[ 19.761853] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12262 13:40:29.217360 : 6.1.91-cip21 a<14>[ 19.771221] [IGT] kms_setmode: exiting, ret=77
12263 13:40:29.217477 arch64)
12264 13:40:29.224007 Using IGT_SRANDOM=1716903629 for randomisation
12265 13:40:29.230535 Opened <8>[ 19.781834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12266 13:40:29.230806 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12268 13:40:29.233486 device: /dev/dri/card0
12269 13:40:29.237228 Starting subtest: invalid-clone-single-crtc
12270 13:40:29.240483 No dynamic tests executed.
12271 13:40:29.243822 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12272 13:40:29.250319 IGT-V<14>[ 19.804199] [IGT] kms_setmode: executing
12273 13:40:29.256960 ersion: 1.28-ga4<14>[ 19.809996] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12274 13:40:29.266514 4ebfe (aarch64) <14>[ 19.817763] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12275 13:40:29.273315 (Linux: 6.1.91-c<14>[ 19.826431] [IGT] kms_setmode: exiting, ret=77
12276 13:40:29.273401 ip21 aarch64)
12277 13:40:29.279539 Using IGT_SRANDOM=1716903629 for randomisation
12278 13:40:29.286707 O<8>[ 19.837184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12279 13:40:29.286970 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12281 13:40:29.290004 pened device: /dev/dri/card0
12282 13:40:29.293396 Starting subtest: invalid-clone-exclusive-crtc
12283 13:40:29.296638 No dynamic tests executed.
12284 13:40:29.303047 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s<14>[ 19.859242] [IGT] kms_setmode: executing
12285 13:40:29.306033 )[0m
12286 13:40:29.312746 IGT-Versi<14>[ 19.864529] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12287 13:40:29.322742 on: 1.28-ga44ebf<14>[ 19.873482] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12288 13:40:29.329156 e (aarch64) (Lin<14>[ 19.883482] [IGT] kms_setmode: exiting, ret=77
12289 13:40:29.332462 ux: 6.1.91-cip21 aarch64)
12290 13:40:29.342794 Using IGT_SRANDOM=1716903629 for rand<8>[ 19.893797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12291 13:40:29.343056 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12293 13:40:29.345986 omisation
12294 13:40:29.349456 Opene<8>[ 19.905307] <LAVA_SIGNAL_TESTSET STOP>
12295 13:40:29.349750 Received signal: <TESTSET> STOP
12296 13:40:29.349866 Closing test_set kms_setmode
12297 13:40:29.352736 d device: /dev/dri/card0
12298 13:40:29.355640 Starting subtest: clone-exclusive-crtc
12299 13:40:29.358771 No dynamic tests executed.
12300 13:40:29.362710 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12301 13:40:29.372491 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: <8>[ 19.925257] <LAVA_SIGNAL_TESTSET START kms_vblank>
12302 13:40:29.372623 6.1.91-cip21 aarch64)
12303 13:40:29.372905 Received signal: <TESTSET> START kms_vblank
12304 13:40:29.373013 Starting test_set kms_vblank
12305 13:40:29.379483 Using IGT_SRANDOM=1716903629 for randomisation
12306 13:40:29.379568 Opened device: /dev/dri/card0
12307 13:40:29.385673 Starting subtest: invalid-clone-single-crtc-stealing
12308 13:40:29.389041 No d<14>[ 19.944337] [IGT] kms_vblank: executing
12309 13:40:29.395583 ynamic tests exe<14>[ 19.949783] [IGT] kms_vblank: exiting, ret=77
12310 13:40:29.395669 cuted.
12311 13:40:29.408717 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.<8>[ 19.959955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12312 13:40:29.408804 000s)[0m
12313 13:40:29.409044 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12315 13:40:29.415227 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12316 13:40:29.418255 Using IGT_SRANDOM=1716903629 for randomisation
12317 13:40:29.422132 Opened device: /dev/dri/card0
12318 13:40:29.424947 No<14>[ 19.981358] [IGT] kms_vblank: executing
12319 13:40:29.431590 KMS driver or n<14>[ 19.986185] [IGT] kms_vblank: exiting, ret=77
12320 13:40:29.434710 o outputs, pipes: 16, outputs: 0
12321 13:40:29.444596 [1mSubtest invalid: SKIP (0.0<8>[ 19.996645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12322 13:40:29.444697 00s)[0m
12323 13:40:29.444938 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12325 13:40:29.451695 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12326 13:40:29.454912 Using IGT_SRANDOM=1716903629 for randomisation
12327 13:40:29.457918 Opened device: /dev/dri/card0
12328 13:40:29.461094 No <14>[ 20.017222] [IGT] kms_vblank: executing
12329 13:40:29.467695 KMS driver or no<14>[ 20.022763] [IGT] kms_vblank: exiting, ret=77
12330 13:40:29.471135 outputs, pipes: 16, outputs: 0
12331 13:40:29.481226 [1mSubtest crtc-id: SKIP (0.00<8>[ 20.033017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12332 13:40:29.481336 0s)[0m
12333 13:40:29.481577 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12335 13:40:29.487754 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12336 13:40:29.491258 Using IGT_SRANDOM=1716903629 for randomisation
12337 13:40:29.494258 Opened device: /dev/dri/card0
12338 13:40:29.500796 No KMS driver or no <14>[ 20.055124] [IGT] kms_vblank: executing
12339 13:40:29.507414 outputs, pipes: <14>[ 20.061019] [IGT] kms_vblank: exiting, ret=77
12340 13:40:29.507524 16, outputs: 0
12341 13:40:29.510681 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12342 13:40:29.517632 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12344 13:40:29.520755 IG<8>[ 20.071331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12345 13:40:29.523932 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12346 13:40:29.530488 Using IGT_SRANDOM=1716903629 for randomisation
12347 13:40:29.530576 Opened device: /dev/dri/card0
12348 13:40:29.537408 No KMS driver o<14>[ 20.092676] [IGT] kms_vblank: executing
12349 13:40:29.543971 r no outputs, pi<14>[ 20.097543] [IGT] kms_vblank: exiting, ret=77
12350 13:40:29.544049 pes: 16, outputs: 0
12351 13:40:29.550330 [1mSubtest query-idle: SKIP (0.000s)[0m
12352 13:40:29.556622 <8>[ 20.107861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12353 13:40:29.556877 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12355 13:40:29.563312 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12356 13:40:29.566464 Using IGT_SRANDOM=1716903629 for randomisation
12357 13:40:29.569815 Opened device: /dev/dri/card0
12358 13:40:29.573098 No KMS driver<14>[ 20.129314] [IGT] kms_vblank: executing
12359 13:40:29.580306 or no outputs, <14>[ 20.134805] [IGT] kms_vblank: exiting, ret=77
12360 13:40:29.583499 pipes: 16, outputs: 0
12361 13:40:29.593022 [1mSubtest query-idle-hang: SKIP (0.000s<8>[ 20.145093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12362 13:40:29.593157 )[0m
12363 13:40:29.593435 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12365 13:40:29.599712 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12366 13:40:29.602844 Using IGT_SRANDOM=1716903629 for randomisation
12367 13:40:29.606567 Opened device: /dev/dri/card0
12368 13:40:29.609936 No KMS<14>[ 20.166851] [IGT] kms_vblank: executing
12369 13:40:29.616475 driver or no ou<14>[ 20.171582] [IGT] kms_vblank: exiting, ret=77
12370 13:40:29.619552 tputs, pipes: 16, outputs: 0
12371 13:40:29.629220 [1mSubtest query-forked: SKIP (0.<8>[ 20.182008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12372 13:40:29.629605 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12374 13:40:29.632542 000s)[0m
12375 13:40:29.635844 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12376 13:40:29.642341 Using IGT_SRANDOM=1716903629 for randomisation
12377 13:40:29.642426 Opened device: /dev/dri/card0
12378 13:40:29.649167 No<14>[ 20.204142] [IGT] kms_vblank: executing
12379 13:40:29.655778 KMS driver or n<14>[ 20.208849] [IGT] kms_vblank: exiting, ret=77
12380 13:40:29.659049 o outputs, pipes: 16, outputs: 0
12381 13:40:29.665949 [1mSubtest query-forked-hang:<8>[ 20.219197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12382 13:40:29.666213 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12384 13:40:29.669269 SKIP (0.000s)[0m
12385 13:40:29.675795 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12386 13:40:29.679178 Using IGT_SRANDOM=1716903629 for randomisation
12387 13:40:29.685586 Opened device: /dev/dri/<14>[ 20.240178] [IGT] kms_vblank: executing
12388 13:40:29.685671 card0
12389 13:40:29.691927 No KMS dr<14>[ 20.245523] [IGT] kms_vblank: exiting, ret=77
12390 13:40:29.695561 iver or no outputs, pipes: 16, outputs: 0
12391 13:40:29.705394 [1mSubtest query-bus<8>[ 20.255681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12392 13:40:29.705506 y: SKIP (0.000s)[0m
12393 13:40:29.705763 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12395 13:40:29.711525 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12396 13:40:29.715113 Using IGT_SRANDOM=1716903629 for randomisation
12397 13:40:29.721509 Opened device: /dev/dr<14>[ 20.277363] [IGT] kms_vblank: executing
12398 13:40:29.721639 i/card0
12399 13:40:29.728396 No KMS <14>[ 20.282666] [IGT] kms_vblank: exiting, ret=77
12400 13:40:29.731721 driver or no outputs, pipes: 16, outputs: 0
12401 13:40:29.741516 [1mSubtest query-b<8>[ 20.292974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12402 13:40:29.741781 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12404 13:40:29.744749 usy-hang: SKIP (0.000s)[0m
12405 13:40:29.751165 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12406 13:40:29.754354 Using IGT_SRANDOM=1716903629 for randomisation
12407 13:40:29.757898 Opened device: /dev/dri/card0
12408 13:40:29.760945 <14>[ 20.315348] [IGT] kms_vblank: executing
12409 13:40:29.767637 No KMS driver or<14>[ 20.321222] [IGT] kms_vblank: exiting, ret=77
12410 13:40:29.771074 no outputs, pipes: 16, outputs: 0
12411 13:40:29.781114 [1mSubtest query-forked-bus<8>[ 20.331496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12412 13:40:29.781212 y: SKIP (0.000s)[0m
12413 13:40:29.781486 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12415 13:40:29.787733 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12416 13:40:29.794177 Using IGT_SRANDOM=1716903629 for randomisation
12417 13:40:29.797479 Opened device: /dev/dr<14>[ 20.353676] [IGT] kms_vblank: executing
12418 13:40:29.800874 i/card0
12419 13:40:29.803581 No KMS <14>[ 20.359040] [IGT] kms_vblank: exiting, ret=77
12420 13:40:29.807548 driver or no outputs, pipes: 16, outputs: 0
12421 13:40:29.817236 [1mSubtest query-f<8>[ 20.369167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12422 13:40:29.817554 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12424 13:40:29.820164 orked-busy-hang: SKIP (0.000s)[0m
12425 13:40:29.827015 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12426 13:40:29.830175 Using IGT_SRANDOM=1716903629 for randomisation
12427 13:40:29.837094 Opened device: /dev/dri/<14>[ 20.390952] [IGT] kms_vblank: executing
12428 13:40:29.837208 card0
12429 13:40:29.843650 No KMS dr<14>[ 20.396938] [IGT] kms_vblank: exiting, ret=77
12430 13:40:29.846967 iver or no outputs, pipes: 16, outputs: 0
12431 13:40:29.856835 [1mSubtest wait-idle<8>[ 20.407258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12432 13:40:29.856924 : SKIP (0.000s)[0m
12433 13:40:29.857192 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12435 13:40:29.863377 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12436 13:40:29.866571 Using IGT_SRANDOM=1716903629 for randomisation
12437 13:40:29.872935 Opened device: /dev/dri<14>[ 20.428753] [IGT] kms_vblank: executing
12438 13:40:29.873020 /card0
12439 13:40:29.879742 No KMS d<14>[ 20.433868] [IGT] kms_vblank: exiting, ret=77
12440 13:40:29.882980 river or no outputs, pipes: 16, outputs: 0
12441 13:40:29.893024 [1mSubtest wait-idl<8>[ 20.444107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12442 13:40:29.893124 e-hang: SKIP (0.000s)[0m
12443 13:40:29.893368 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12445 13:40:29.899381 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12446 13:40:29.906032 Using IGT_SRANDOM=1716903629 for randomisation
12447 13:40:29.906118 Opened device: /dev/dri/card0
12448 13:40:29.912670 No<14>[ 20.465980] [IGT] kms_vblank: executing
12449 13:40:29.919582 KMS driver or n<14>[ 20.472003] [IGT] kms_vblank: exiting, ret=77
12450 13:40:29.919676 o outputs, pipes: 16, outputs: 0
12451 13:40:29.929125 [1mSubtest wait-forked: SKIP <8>[ 20.482433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12452 13:40:29.929422 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12454 13:40:29.932390 (0.000s)[0m
12455 13:40:29.939156 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12456 13:40:29.942620 Using IGT_SRANDOM=1716903629 for randomisation
12457 13:40:29.945586 Opened device: /dev/dri/card0
12458 13:40:29.952483 No KMS driver or no outputs, pi<14>[ 20.507256] [IGT] kms_vblank: executing
12459 13:40:29.958899 pes: 16, outputs<14>[ 20.512194] [IGT] kms_vblank: exiting, ret=77
12460 13:40:29.958988 : 0
12461 13:40:29.962077 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12462 13:40:29.968656 IGT-Versio<8>[ 20.522283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12463 13:40:29.968917 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12465 13:40:29.975277 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12466 13:40:29.978425 Using IGT_SRANDOM=1716903629 for randomisation
12467 13:40:29.982350 Opened device: /dev/dri/card0
12468 13:40:29.988457 No KMS driver or no out<14>[ 20.543386] [IGT] kms_vblank: executing
12469 13:40:29.995199 puts, pipes: 16,<14>[ 20.548641] [IGT] kms_vblank: exiting, ret=77
12470 13:40:29.995290 outputs: 0
12471 13:40:29.998685 [1mSubtest wait-busy: SKIP (0.000s)[0m
12472 13:40:30.008810 IGT-Versi<8>[ 20.559052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12473 13:40:30.009073 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12475 13:40:30.012122 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12476 13:40:30.015484 Using IGT_SRANDOM=1716903630 for randomisation
12477 13:40:30.018232 Opened device: /dev/dri/card0
12478 13:40:30.025133 No KMS driver or no ou<14>[ 20.580090] [IGT] kms_vblank: executing
12479 13:40:30.031463 tputs, pipes: 16<14>[ 20.585751] [IGT] kms_vblank: exiting, ret=77
12480 13:40:30.031590 , outputs: 0
12481 13:40:30.037907 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12482 13:40:30.045094 IGT<8>[ 20.595798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12483 13:40:30.045412 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12485 13:40:30.051613 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12486 13:40:30.054791 Using IGT_SRANDOM=1716903630 for randomisation
12487 13:40:30.057864 Opened device: /dev/dri/card0
12488 13:40:30.061039 No KMS driver or<14>[ 20.617811] [IGT] kms_vblank: executing
12489 13:40:30.067681 no outputs, pip<14>[ 20.623013] [IGT] kms_vblank: exiting, ret=77
12490 13:40:30.070924 es: 16, outputs: 0
12491 13:40:30.080786 [1mSubtest wait-forked-busy: SKIP (0.000s)<8>[ 20.633046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12492 13:40:30.080872 [0m
12493 13:40:30.081112 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12495 13:40:30.087539 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12496 13:40:30.090855 Using IGT_SRANDOM=1716903630 for randomisation
12497 13:40:30.094075 Opened device: /dev/dri/card0
12498 13:40:30.100536 No KMS d<14>[ 20.655674] [IGT] kms_vblank: executing
12499 13:40:30.107101 river or no outp<14>[ 20.660523] [IGT] kms_vblank: exiting, ret=77
12500 13:40:30.107179 uts, pipes: 16, outputs: 0
12501 13:40:30.120610 [1mSubtest wait-forked-busy-hang: S<8>[ 20.670920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12502 13:40:30.120736 KIP (0.000s)[0m
12503 13:40:30.121012 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12505 13:40:30.127425 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12506 13:40:30.130655 Using IGT_SRANDOM=1716903630 for randomisation
12507 13:40:30.137035 Opened device: /dev/dri/ca<14>[ 20.693004] [IGT] kms_vblank: executing
12508 13:40:30.137179 rd0
12509 13:40:30.143581 No KMS driv<14>[ 20.698038] [IGT] kms_vblank: exiting, ret=77
12510 13:40:30.146815 er or no outputs, pipes: 16, outputs: 0
12511 13:40:30.157138 [1mSubtest ts-continua<8>[ 20.708312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12512 13:40:30.157426 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12514 13:40:30.160451 tion-idle: SKIP (0.000s)[0m
12515 13:40:30.166954 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12516 13:40:30.170183 Using IGT_SRANDOM=1716903630 for randomisation
12517 13:40:30.176899 Opened device:<14>[ 20.730902] [IGT] kms_vblank: executing
12518 13:40:30.176985 /dev/dri/card0
12519 13:40:30.183283 <14>[ 20.736056] [IGT] kms_vblank: exiting, ret=77
12520 13:40:30.183393
12521 13:40:30.186610 No KMS driver or no outputs, pipes: 16, outputs: 0
12522 13:40:30.196613 [1mSubtest<8>[ 20.746251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12523 13:40:30.196875 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12525 13:40:30.199956 ts-continuation-idle-hang: SKIP (0.000s)[0m
12526 13:40:30.206680 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12527 13:40:30.213195 Using IGT_SRANDOM=1716903630 for randomisatio<14>[ 20.768617] [IGT] kms_vblank: executing
12528 13:40:30.213318 n
12529 13:40:30.219766 Opened device<14>[ 20.773925] [IGT] kms_vblank: exiting, ret=77
12530 13:40:30.222646 : /dev/dri/card0
12531 13:40:30.232836 No KMS driver or no outputs, pipes: 16, output<8>[ 20.784188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12532 13:40:30.232972 s: 0
12533 13:40:30.233230 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12535 13:40:30.239354 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12536 13:40:30.246068 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12537 13:40:30.252872 Using IGT_SRANDOM=1716903630 <14>[ 20.807064] [IGT] kms_vblank: executing
12538 13:40:30.259181 for randomisatio<14>[ 20.812173] [IGT] kms_vblank: exiting, ret=77
12539 13:40:30.259271 n
12540 13:40:30.262383 Opened device: /dev/dri/card0
12541 13:40:30.272136 No KMS driver or no outputs, p<8>[ 20.822331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12542 13:40:30.272256 ipes: 16, outputs: 0
12543 13:40:30.272516 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12545 13:40:30.279171 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12546 13:40:30.285656 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12547 13:40:30.288711 Using IGT<14>[ 20.844766] [IGT] kms_vblank: executing
12548 13:40:30.295323 _SRANDOM=1716903<14>[ 20.849988] [IGT] kms_vblank: exiting, ret=77
12549 13:40:30.298545 630 for randomisation
12550 13:40:30.301894 Opened device: /dev/dri/card0
12551 13:40:30.308360 No KMS dri<8>[ 20.860239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12552 13:40:30.308629 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12554 13:40:30.311633 ver or no outputs, pipes: 16, outputs: 0
12555 13:40:30.318791 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12556 13:40:30.328555 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarc<14>[ 20.882775] [IGT] kms_vblank: executing
12557 13:40:30.328645 h64)
12558 13:40:30.335199 Using IGT_<14>[ 20.887793] [IGT] kms_vblank: exiting, ret=77
12559 13:40:30.338465 SRANDOM=1716903630 for randomisation
12560 13:40:30.348190 Opened device: /dev/dri/ca<8>[ 20.897972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12561 13:40:30.348278 rd0
12562 13:40:30.348520 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12564 13:40:30.351831 No KMS driver or no outputs, pipes: 16, outputs: 0
12565 13:40:30.358045 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12566 13:40:30.365128 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.<14>[ 20.920717] [IGT] kms_vblank: executing
12567 13:40:30.371542 1.91-cip21 aarch<14>[ 20.926056] [IGT] kms_vblank: exiting, ret=77
12568 13:40:30.371655 64)
12569 13:40:30.378065 Using IGT_SRANDOM=1716903630 for randomisation
12570 13:40:30.384635 Opened devi<8>[ 20.936453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12571 13:40:30.384899 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12573 13:40:30.391002 ce: /dev/dri/car<8>[ 20.946976] <LAVA_SIGNAL_TESTSET STOP>
12574 13:40:30.391087 d0
12575 13:40:30.391323 Received signal: <TESTSET> STOP
12576 13:40:30.391390 Closing test_set kms_vblank
12577 13:40:30.397491 No KMS drive<8>[ 20.952081] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14063027_1.5.2.3.1>
12578 13:40:30.397803 Received signal: <ENDRUN> 0_igt-kms-mediatek 14063027_1.5.2.3.1
12579 13:40:30.397913 Ending use of test pattern.
12580 13:40:30.398003 Ending test lava.0_igt-kms-mediatek (14063027_1.5.2.3.1), duration 6.34
12582 13:40:30.404577 r or no outputs, pipes: 16, outputs: 0
12583 13:40:30.407873 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12584 13:40:30.414473 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12585 13:40:30.417740 Using IGT_SRANDOM=1716903630 for randomisation
12586 13:40:30.421022 Opened device: /dev/dri/card0
12587 13:40:30.424378 No KMS driver or no outputs, pipes: 16, outputs: 0
12588 13:40:30.430899 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12589 13:40:30.431028 + set +x
12590 13:40:30.434129 <LAVA_TEST_RUNNER EXIT>
12591 13:40:30.434388 ok: lava_test_shell seems to have completed
12592 13:40:30.435917 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12593 13:40:30.871804 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12594 13:40:30.871965 end: 3 lava-test-retry (duration 00:00:07) [common]
12595 13:40:30.872061 start: 4 finalize (timeout 00:07:12) [common]
12596 13:40:30.872153 start: 4.1 power-off (timeout 00:00:30) [common]
12597 13:40:30.872310 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12598 13:40:31.072410 >> Command sent successfully.
12599 13:40:31.074831 Returned 0 in 0 seconds
12600 13:40:31.175244 end: 4.1 power-off (duration 00:00:00) [common]
12602 13:40:31.175594 start: 4.2 read-feedback (timeout 00:07:11) [common]
12603 13:40:31.175857 Listened to connection for namespace 'common' for up to 1s
12604 13:40:32.176819 Finalising connection for namespace 'common'
12605 13:40:32.176998 Disconnecting from shell: Finalise
12606 13:40:32.177119 / #
12607 13:40:32.277415 end: 4.2 read-feedback (duration 00:00:01) [common]
12608 13:40:32.277594 end: 4 finalize (duration 00:00:01) [common]
12609 13:40:32.277711 Cleaning after the job
12610 13:40:32.277812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/ramdisk
12611 13:40:32.284419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/kernel
12612 13:40:32.299716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/dtb
12613 13:40:32.299930 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063027/tftp-deploy-jw8mi1o4/modules
12614 13:40:32.305718 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063027
12615 13:40:32.420445 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063027
12616 13:40:32.420624 Job finished correctly