Boot log: mt8192-asurada-spherion-r0
- Errors: 3
- Kernel Errors: 36
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 25
1 13:41:06.827878 lava-dispatcher, installed at version: 2024.03
2 13:41:06.828076 start: 0 validate
3 13:41:06.828208 Start time: 2024-05-28 13:41:06.828201+00:00 (UTC)
4 13:41:06.828325 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:41:06.828460 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:41:07.081459 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:41:07.082182 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:41:07.344531 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:41:07.345366 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:41:07.598499 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:41:07.599181 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:41:07.861257 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:41:07.862089 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:41:08.131717 validate duration: 1.30
16 13:41:08.133089 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:41:08.133697 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:41:08.134185 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:41:08.134797 Not decompressing ramdisk as can be used compressed.
20 13:41:08.135258 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 13:41:08.135614 saving as /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/ramdisk/initrd.cpio.gz
22 13:41:08.135963 total size: 5628151 (5 MB)
23 13:41:08.141706 progress 0 % (0 MB)
24 13:41:08.151389 progress 5 % (0 MB)
25 13:41:08.159929 progress 10 % (0 MB)
26 13:41:08.167028 progress 15 % (0 MB)
27 13:41:08.174278 progress 20 % (1 MB)
28 13:41:08.179145 progress 25 % (1 MB)
29 13:41:08.183239 progress 30 % (1 MB)
30 13:41:08.186615 progress 35 % (1 MB)
31 13:41:08.189124 progress 40 % (2 MB)
32 13:41:08.191890 progress 45 % (2 MB)
33 13:41:08.194088 progress 50 % (2 MB)
34 13:41:08.196482 progress 55 % (2 MB)
35 13:41:08.198614 progress 60 % (3 MB)
36 13:41:08.200537 progress 65 % (3 MB)
37 13:41:08.202606 progress 70 % (3 MB)
38 13:41:08.204286 progress 75 % (4 MB)
39 13:41:08.206173 progress 80 % (4 MB)
40 13:41:08.207747 progress 85 % (4 MB)
41 13:41:08.209467 progress 90 % (4 MB)
42 13:41:08.211260 progress 95 % (5 MB)
43 13:41:08.212734 progress 100 % (5 MB)
44 13:41:08.212977 5 MB downloaded in 0.08 s (69.68 MB/s)
45 13:41:08.213193 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:41:08.213471 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:41:08.213562 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:41:08.213651 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:41:08.213786 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:41:08.213856 saving as /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/kernel/Image
52 13:41:08.213918 total size: 54682112 (52 MB)
53 13:41:08.213981 No compression specified
54 13:41:08.215098 progress 0 % (0 MB)
55 13:41:08.228846 progress 5 % (2 MB)
56 13:41:08.242572 progress 10 % (5 MB)
57 13:41:08.256263 progress 15 % (7 MB)
58 13:41:08.269886 progress 20 % (10 MB)
59 13:41:08.283923 progress 25 % (13 MB)
60 13:41:08.297645 progress 30 % (15 MB)
61 13:41:08.311905 progress 35 % (18 MB)
62 13:41:08.325830 progress 40 % (20 MB)
63 13:41:08.339599 progress 45 % (23 MB)
64 13:41:08.353311 progress 50 % (26 MB)
65 13:41:08.366905 progress 55 % (28 MB)
66 13:41:08.380730 progress 60 % (31 MB)
67 13:41:08.394502 progress 65 % (33 MB)
68 13:41:08.408308 progress 70 % (36 MB)
69 13:41:08.421893 progress 75 % (39 MB)
70 13:41:08.436137 progress 80 % (41 MB)
71 13:41:08.449859 progress 85 % (44 MB)
72 13:41:08.463507 progress 90 % (46 MB)
73 13:41:08.477317 progress 95 % (49 MB)
74 13:41:08.490772 progress 100 % (52 MB)
75 13:41:08.491006 52 MB downloaded in 0.28 s (188.21 MB/s)
76 13:41:08.491158 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:41:08.491393 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:41:08.491480 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:41:08.491565 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:41:08.491702 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:41:08.491770 saving as /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/dtb/mt8192-asurada-spherion-r0.dtb
83 13:41:08.491830 total size: 47258 (0 MB)
84 13:41:08.491889 No compression specified
85 13:41:08.493003 progress 69 % (0 MB)
86 13:41:08.493328 progress 100 % (0 MB)
87 13:41:08.493498 0 MB downloaded in 0.00 s (27.05 MB/s)
88 13:41:08.493621 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:41:08.493842 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:41:08.493927 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:41:08.494009 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:41:08.494120 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 13:41:08.494186 saving as /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/nfsrootfs/full.rootfs.tar
95 13:41:08.494249 total size: 69067788 (65 MB)
96 13:41:08.494310 Using unxz to decompress xz
97 13:41:08.498135 progress 0 % (0 MB)
98 13:41:08.688973 progress 5 % (3 MB)
99 13:41:08.888709 progress 10 % (6 MB)
100 13:41:09.088990 progress 15 % (9 MB)
101 13:41:09.250819 progress 20 % (13 MB)
102 13:41:09.427752 progress 25 % (16 MB)
103 13:41:09.626872 progress 30 % (19 MB)
104 13:41:09.744040 progress 35 % (23 MB)
105 13:41:09.840496 progress 40 % (26 MB)
106 13:41:10.040053 progress 45 % (29 MB)
107 13:41:10.247706 progress 50 % (32 MB)
108 13:41:10.451942 progress 55 % (36 MB)
109 13:41:10.669552 progress 60 % (39 MB)
110 13:41:10.855518 progress 65 % (42 MB)
111 13:41:11.049999 progress 70 % (46 MB)
112 13:41:11.242168 progress 75 % (49 MB)
113 13:41:11.453067 progress 80 % (52 MB)
114 13:41:11.625915 progress 85 % (56 MB)
115 13:41:11.813608 progress 90 % (59 MB)
116 13:41:12.013221 progress 95 % (62 MB)
117 13:41:12.212908 progress 100 % (65 MB)
118 13:41:12.219017 65 MB downloaded in 3.72 s (17.68 MB/s)
119 13:41:12.219283 end: 1.4.1 http-download (duration 00:00:04) [common]
121 13:41:12.219549 end: 1.4 download-retry (duration 00:00:04) [common]
122 13:41:12.219640 start: 1.5 download-retry (timeout 00:09:56) [common]
123 13:41:12.219728 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 13:41:12.219881 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:41:12.219950 saving as /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/modules/modules.tar
126 13:41:12.220010 total size: 8607916 (8 MB)
127 13:41:12.220073 Using unxz to decompress xz
128 13:41:12.223967 progress 0 % (0 MB)
129 13:41:12.243656 progress 5 % (0 MB)
130 13:41:12.267713 progress 10 % (0 MB)
131 13:41:12.292805 progress 15 % (1 MB)
132 13:41:12.317592 progress 20 % (1 MB)
133 13:41:12.342972 progress 25 % (2 MB)
134 13:41:12.367350 progress 30 % (2 MB)
135 13:41:12.390470 progress 35 % (2 MB)
136 13:41:12.416191 progress 40 % (3 MB)
137 13:41:12.440693 progress 45 % (3 MB)
138 13:41:12.464563 progress 50 % (4 MB)
139 13:41:12.489033 progress 55 % (4 MB)
140 13:41:12.513208 progress 60 % (4 MB)
141 13:41:12.536830 progress 65 % (5 MB)
142 13:41:12.562683 progress 70 % (5 MB)
143 13:41:12.589396 progress 75 % (6 MB)
144 13:41:12.612417 progress 80 % (6 MB)
145 13:41:12.635718 progress 85 % (7 MB)
146 13:41:12.658926 progress 90 % (7 MB)
147 13:41:12.687745 progress 95 % (7 MB)
148 13:41:12.715445 progress 100 % (8 MB)
149 13:41:12.721004 8 MB downloaded in 0.50 s (16.39 MB/s)
150 13:41:12.721304 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:41:12.721604 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:41:12.721715 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 13:41:12.721825 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 13:41:14.278920 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i
156 13:41:14.279121 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:41:14.279223 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 13:41:14.279386 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c
159 13:41:14.279512 makedir: /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin
160 13:41:14.279614 makedir: /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/tests
161 13:41:14.279711 makedir: /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/results
162 13:41:14.279808 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-add-keys
163 13:41:14.279946 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-add-sources
164 13:41:14.280072 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-background-process-start
165 13:41:14.280198 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-background-process-stop
166 13:41:14.280323 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-common-functions
167 13:41:14.280445 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-echo-ipv4
168 13:41:14.280568 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-install-packages
169 13:41:14.280688 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-installed-packages
170 13:41:14.280808 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-os-build
171 13:41:14.280927 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-probe-channel
172 13:41:14.281049 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-probe-ip
173 13:41:14.281170 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-target-ip
174 13:41:14.281300 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-target-mac
175 13:41:14.281424 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-target-storage
176 13:41:14.281548 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-case
177 13:41:14.281668 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-event
178 13:41:14.281787 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-feedback
179 13:41:14.281935 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-raise
180 13:41:14.282057 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-reference
181 13:41:14.282177 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-runner
182 13:41:14.282296 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-set
183 13:41:14.282414 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-test-shell
184 13:41:14.282536 Updating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-install-packages (oe)
185 13:41:14.282680 Updating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/bin/lava-installed-packages (oe)
186 13:41:14.282796 Creating /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/environment
187 13:41:14.282887 LAVA metadata
188 13:41:14.282952 - LAVA_JOB_ID=14063102
189 13:41:14.283012 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:41:14.283110 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 13:41:14.283174 skipped lava-vland-overlay
192 13:41:14.283246 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:41:14.283323 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 13:41:14.283382 skipped lava-multinode-overlay
195 13:41:14.283451 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:41:14.283525 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 13:41:14.283603 Loading test definitions
198 13:41:14.283690 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 13:41:14.283760 Using /lava-14063102 at stage 0
200 13:41:14.284047 uuid=14063102_1.6.2.3.1 testdef=None
201 13:41:14.284134 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:41:14.284215 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 13:41:14.284692 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:41:14.284905 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 13:41:14.285537 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:41:14.285760 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 13:41:14.286323 runner path: /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/0/tests/0_lc-compliance test_uuid 14063102_1.6.2.3.1
210 13:41:14.286479 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:41:14.286780 Creating lava-test-runner.conf files
213 13:41:14.286849 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063102/lava-overlay-8oidff0c/lava-14063102/0 for stage 0
214 13:41:14.286937 - 0_lc-compliance
215 13:41:14.287033 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 13:41:14.287118 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 13:41:14.293056 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 13:41:14.293154 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 13:41:14.293236 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 13:41:14.293478 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 13:41:14.293564 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 13:41:14.457139 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 13:41:14.457552 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 13:41:14.457669 extracting modules file /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i
225 13:41:14.679721 extracting modules file /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063102/extract-overlay-ramdisk-25b3fptl/ramdisk
226 13:41:14.908146 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 13:41:14.908345 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 13:41:14.908471 [common] Applying overlay to NFS
229 13:41:14.908573 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063102/compress-overlay-9a2877at/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i
230 13:41:14.916782 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 13:41:14.916902 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 13:41:14.916995 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 13:41:14.917086 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 13:41:14.917166 Building ramdisk /var/lib/lava/dispatcher/tmp/14063102/extract-overlay-ramdisk-25b3fptl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063102/extract-overlay-ramdisk-25b3fptl/ramdisk
235 13:41:15.219330 >> 130335 blocks
236 13:41:17.252582 rename /var/lib/lava/dispatcher/tmp/14063102/extract-overlay-ramdisk-25b3fptl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/ramdisk/ramdisk.cpio.gz
237 13:41:17.253060 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 13:41:17.253220 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 13:41:17.253382 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 13:41:17.253485 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/kernel/Image']
241 13:41:30.212795 Returned 0 in 12 seconds
242 13:41:30.313774 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/kernel/image.itb
243 13:41:30.665686 output: FIT description: Kernel Image image with one or more FDT blobs
244 13:41:30.666049 output: Created: Tue May 28 14:41:30 2024
245 13:41:30.666123 output: Image 0 (kernel-1)
246 13:41:30.666189 output: Description:
247 13:41:30.666253 output: Created: Tue May 28 14:41:30 2024
248 13:41:30.666317 output: Type: Kernel Image
249 13:41:30.666381 output: Compression: lzma compressed
250 13:41:30.666441 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
251 13:41:30.666503 output: Architecture: AArch64
252 13:41:30.666562 output: OS: Linux
253 13:41:30.666619 output: Load Address: 0x00000000
254 13:41:30.666675 output: Entry Point: 0x00000000
255 13:41:30.666730 output: Hash algo: crc32
256 13:41:30.666782 output: Hash value: 0578ee26
257 13:41:30.666836 output: Image 1 (fdt-1)
258 13:41:30.666890 output: Description: mt8192-asurada-spherion-r0
259 13:41:30.666945 output: Created: Tue May 28 14:41:30 2024
260 13:41:30.666997 output: Type: Flat Device Tree
261 13:41:30.667050 output: Compression: uncompressed
262 13:41:30.667102 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 13:41:30.667154 output: Architecture: AArch64
264 13:41:30.667205 output: Hash algo: crc32
265 13:41:30.667257 output: Hash value: 0f8e4d2e
266 13:41:30.667309 output: Image 2 (ramdisk-1)
267 13:41:30.667361 output: Description: unavailable
268 13:41:30.667413 output: Created: Tue May 28 14:41:30 2024
269 13:41:30.667465 output: Type: RAMDisk Image
270 13:41:30.667517 output: Compression: Unknown Compression
271 13:41:30.667569 output: Data Size: 18730698 Bytes = 18291.70 KiB = 17.86 MiB
272 13:41:30.667620 output: Architecture: AArch64
273 13:41:30.667672 output: OS: Linux
274 13:41:30.667723 output: Load Address: unavailable
275 13:41:30.667775 output: Entry Point: unavailable
276 13:41:30.667873 output: Hash algo: crc32
277 13:41:30.667937 output: Hash value: e51b332b
278 13:41:30.667989 output: Default Configuration: 'conf-1'
279 13:41:30.668040 output: Configuration 0 (conf-1)
280 13:41:30.668091 output: Description: mt8192-asurada-spherion-r0
281 13:41:30.668143 output: Kernel: kernel-1
282 13:41:30.668195 output: Init Ramdisk: ramdisk-1
283 13:41:30.668247 output: FDT: fdt-1
284 13:41:30.668298 output: Loadables: kernel-1
285 13:41:30.668350 output:
286 13:41:30.668551 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 13:41:30.668646 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 13:41:30.668751 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 13:41:30.668844 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 13:41:30.668926 No LXC device requested
291 13:41:30.669004 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 13:41:30.669094 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 13:41:30.669172 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 13:41:30.669238 Checking files for TFTP limit of 4294967296 bytes.
295 13:41:30.669792 end: 1 tftp-deploy (duration 00:00:23) [common]
296 13:41:30.669895 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 13:41:30.670045 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 13:41:30.670225 substitutions:
299 13:41:30.670292 - {DTB}: 14063102/tftp-deploy-h62bn31c/dtb/mt8192-asurada-spherion-r0.dtb
300 13:41:30.670354 - {INITRD}: 14063102/tftp-deploy-h62bn31c/ramdisk/ramdisk.cpio.gz
301 13:41:30.670412 - {KERNEL}: 14063102/tftp-deploy-h62bn31c/kernel/Image
302 13:41:30.670469 - {LAVA_MAC}: None
303 13:41:30.670524 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i
304 13:41:30.670580 - {NFS_SERVER_IP}: 192.168.201.1
305 13:41:30.670634 - {PRESEED_CONFIG}: None
306 13:41:30.670688 - {PRESEED_LOCAL}: None
307 13:41:30.670741 - {RAMDISK}: 14063102/tftp-deploy-h62bn31c/ramdisk/ramdisk.cpio.gz
308 13:41:30.670795 - {ROOT_PART}: None
309 13:41:30.670848 - {ROOT}: None
310 13:41:30.670900 - {SERVER_IP}: 192.168.201.1
311 13:41:30.670952 - {TEE}: None
312 13:41:30.671005 Parsed boot commands:
313 13:41:30.671058 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 13:41:30.671237 Parsed boot commands: tftpboot 192.168.201.1 14063102/tftp-deploy-h62bn31c/kernel/image.itb 14063102/tftp-deploy-h62bn31c/kernel/cmdline
315 13:41:30.671330 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 13:41:30.671456 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 13:41:30.671555 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 13:41:30.671644 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 13:41:30.671715 Not connected, no need to disconnect.
320 13:41:30.671788 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 13:41:30.671867 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 13:41:30.671935 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 13:41:30.675398 Setting prompt string to ['lava-test: # ']
324 13:41:30.675760 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 13:41:30.675864 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 13:41:30.675983 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 13:41:30.676132 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 13:41:30.676363 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
329 13:41:35.825551 >> Command sent successfully.
330 13:41:35.836694 Returned 0 in 5 seconds
331 13:41:35.938057 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 13:41:35.939571 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 13:41:35.940116 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 13:41:35.940582 Setting prompt string to 'Starting depthcharge on Spherion...'
336 13:41:35.940956 Changing prompt to 'Starting depthcharge on Spherion...'
337 13:41:35.941420 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 13:41:35.943386 [Enter `^Ec?' for help]
339 13:41:36.108050
340 13:41:36.108620
341 13:41:36.109016 F0: 102B 0000
342 13:41:36.109430
343 13:41:36.109782 F3: 1001 0000 [0200]
344 13:41:36.110124
345 13:41:36.111344 F3: 1001 0000
346 13:41:36.111806
347 13:41:36.112170 F7: 102D 0000
348 13:41:36.112508
349 13:41:36.114298 F1: 0000 0000
350 13:41:36.114765
351 13:41:36.115130 V0: 0000 0000 [0001]
352 13:41:36.115468
353 13:41:36.118141 00: 0007 8000
354 13:41:36.118705
355 13:41:36.119089 01: 0000 0000
356 13:41:36.119443
357 13:41:36.120919 BP: 0C00 0209 [0000]
358 13:41:36.121484
359 13:41:36.121857 G0: 1182 0000
360 13:41:36.122197
361 13:41:36.124222 EC: 0000 0021 [4000]
362 13:41:36.124686
363 13:41:36.125050 S7: 0000 0000 [0000]
364 13:41:36.125421
365 13:41:36.127905 CC: 0000 0000 [0001]
366 13:41:36.128365
367 13:41:36.128731 T0: 0000 0040 [010F]
368 13:41:36.129073
369 13:41:36.129429 Jump to BL
370 13:41:36.131268
371 13:41:36.155192
372 13:41:36.155749
373 13:41:36.162137 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 13:41:36.165521 ARM64: Exception handlers installed.
375 13:41:36.169228 ARM64: Testing exception
376 13:41:36.172771 ARM64: Done test exception
377 13:41:36.179106 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 13:41:36.189763 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 13:41:36.196281 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 13:41:36.206133 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 13:41:36.212985 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 13:41:36.219193 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 13:41:36.231579 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 13:41:36.237857 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 13:41:36.257525 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 13:41:36.261119 WDT: Last reset was cold boot
387 13:41:36.264083 SPI1(PAD0) initialized at 2873684 Hz
388 13:41:36.267593 SPI5(PAD0) initialized at 992727 Hz
389 13:41:36.271282 VBOOT: Loading verstage.
390 13:41:36.277392 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 13:41:36.281078 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 13:41:36.284356 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 13:41:36.287291 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 13:41:36.295068 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 13:41:36.301810 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 13:41:36.312461 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 13:41:36.313030
398 13:41:36.313438
399 13:41:36.322804 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 13:41:36.326262 ARM64: Exception handlers installed.
401 13:41:36.329254 ARM64: Testing exception
402 13:41:36.329753 ARM64: Done test exception
403 13:41:36.335884 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 13:41:36.339427 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 13:41:36.354211 Probing TPM: . done!
406 13:41:36.354776 TPM ready after 0 ms
407 13:41:36.361091 Connected to device vid:did:rid of 1ae0:0028:00
408 13:41:36.367662 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
409 13:41:36.418120 Initialized TPM device CR50 revision 0
410 13:41:36.421118 tlcl_send_startup: Startup return code is 0
411 13:41:36.432033 TPM: setup succeeded
412 13:41:36.440983 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 13:41:36.450369 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 13:41:36.460417 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 13:41:36.468696 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 13:41:36.472155 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 13:41:36.475466 in-header: 03 07 00 00 08 00 00 00
418 13:41:36.478233 in-data: aa e4 47 04 13 02 00 00
419 13:41:36.481726 Chrome EC: UHEPI supported
420 13:41:36.488885 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 13:41:36.492433 in-header: 03 95 00 00 08 00 00 00
422 13:41:36.496061 in-data: 18 20 20 08 00 00 00 00
423 13:41:36.496626 Phase 1
424 13:41:36.499715 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 13:41:36.507390 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 13:41:36.510766 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 13:41:36.514278 Recovery requested (1009000e)
428 13:41:36.523494 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 13:41:36.528913 tlcl_extend: response is 0
430 13:41:36.538360 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 13:41:36.543676 tlcl_extend: response is 0
432 13:41:36.550531 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 13:41:36.571577 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 13:41:36.578446 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 13:41:36.578922
436 13:41:36.579294
437 13:41:36.589214 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 13:41:36.589724 ARM64: Exception handlers installed.
439 13:41:36.593408 ARM64: Testing exception
440 13:41:36.596286 ARM64: Done test exception
441 13:41:36.616564 pmic_efuse_setting: Set efuses in 11 msecs
442 13:41:36.619820 pmwrap_interface_init: Select PMIF_VLD_RDY
443 13:41:36.626623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 13:41:36.629760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 13:41:36.636733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 13:41:36.639817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 13:41:36.646392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 13:41:36.649808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 13:41:36.653267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 13:41:36.659836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 13:41:36.663113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 13:41:36.669838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 13:41:36.672987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 13:41:36.676520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 13:41:36.683048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 13:41:36.689938 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 13:41:36.693081 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 13:41:36.700395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 13:41:36.707469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 13:41:36.711006 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 13:41:36.718076 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 13:41:36.721624 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 13:41:36.728660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 13:41:36.732575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 13:41:36.739621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 13:41:36.743475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 13:41:36.750629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 13:41:36.754811 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 13:41:36.761422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 13:41:36.765093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 13:41:36.768592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 13:41:36.776005 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 13:41:36.780245 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 13:41:36.783876 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 13:41:36.791048 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 13:41:36.795191 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 13:41:36.798710 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 13:41:36.805946 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 13:41:36.809953 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 13:41:36.813954 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 13:41:36.821133 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 13:41:36.824779 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 13:41:36.828287 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 13:41:36.832494 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 13:41:36.838920 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 13:41:36.843108 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 13:41:36.846647 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 13:41:36.850601 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 13:41:36.854278 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 13:41:36.857611 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 13:41:36.865441 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 13:41:36.868553 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 13:41:36.872417 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 13:41:36.879563 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 13:41:36.887162 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 13:41:36.894320 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 13:41:36.901597 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 13:41:36.909092 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 13:41:36.912255 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 13:41:36.919590 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 13:41:36.923392 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 13:41:36.930929 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
503 13:41:36.934282 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 13:41:36.941433 [RTC]rtc_osc_init,62: osc32con val = 0xde70
505 13:41:36.944469 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 13:41:36.953906 [RTC]rtc_get_frequency_meter,154: input=15, output=765
507 13:41:36.963409 [RTC]rtc_get_frequency_meter,154: input=23, output=949
508 13:41:36.973138 [RTC]rtc_get_frequency_meter,154: input=19, output=856
509 13:41:36.983165 [RTC]rtc_get_frequency_meter,154: input=17, output=811
510 13:41:36.992181 [RTC]rtc_get_frequency_meter,154: input=16, output=786
511 13:41:37.001852 [RTC]rtc_get_frequency_meter,154: input=16, output=788
512 13:41:37.011344 [RTC]rtc_get_frequency_meter,154: input=17, output=810
513 13:41:37.014302 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
514 13:41:37.021958 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
515 13:41:37.024849 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 13:41:37.028728 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
517 13:41:37.032503 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 13:41:37.036059 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
519 13:41:37.039671 ADC[4]: Raw value=670432 ID=5
520 13:41:37.043620 ADC[3]: Raw value=212917 ID=1
521 13:41:37.044084 RAM Code: 0x51
522 13:41:37.047000 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 13:41:37.054762 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 13:41:37.061616 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
525 13:41:37.068706 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
526 13:41:37.069015 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 13:41:37.072500 in-header: 03 07 00 00 08 00 00 00
528 13:41:37.076200 in-data: aa e4 47 04 13 02 00 00
529 13:41:37.080307 Chrome EC: UHEPI supported
530 13:41:37.087351 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 13:41:37.091296 in-header: 03 95 00 00 08 00 00 00
532 13:41:37.094993 in-data: 18 20 20 08 00 00 00 00
533 13:41:37.098606 MRC: failed to locate region type 0.
534 13:41:37.102173 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 13:41:37.105881 DRAM-K: Running full calibration
536 13:41:37.112881 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
537 13:41:37.113041 header.status = 0x0
538 13:41:37.116604 header.version = 0x6 (expected: 0x6)
539 13:41:37.120332 header.size = 0xd00 (expected: 0xd00)
540 13:41:37.124364 header.flags = 0x0
541 13:41:37.127482 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 13:41:37.147080 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 13:41:37.153989 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 13:41:37.158207 dram_init: ddr_geometry: 0
545 13:41:37.158761 [EMI] MDL number = 0
546 13:41:37.161728 [EMI] Get MDL freq = 0
547 13:41:37.162195 dram_init: ddr_type: 0
548 13:41:37.165246 is_discrete_lpddr4: 1
549 13:41:37.169397 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 13:41:37.169871
551 13:41:37.170239
552 13:41:37.170576 [Bian_co] ETT version 0.0.0.1
553 13:41:37.177436 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
554 13:41:37.177997
555 13:41:37.180539 dramc_set_vcore_voltage set vcore to 650000
556 13:41:37.181007 Read voltage for 800, 4
557 13:41:37.184367 Vio18 = 0
558 13:41:37.184926 Vcore = 650000
559 13:41:37.185342 Vdram = 0
560 13:41:37.185702 Vddq = 0
561 13:41:37.187537 Vmddr = 0
562 13:41:37.188002 dram_init: config_dvfs: 1
563 13:41:37.195336 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 13:41:37.199052 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 13:41:37.202767 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
566 13:41:37.206582 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
567 13:41:37.209822 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
568 13:41:37.213889 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
569 13:41:37.217061 MEM_TYPE=3, freq_sel=18
570 13:41:37.221061 sv_algorithm_assistance_LP4_1600
571 13:41:37.224363 ============ PULL DRAM RESETB DOWN ============
572 13:41:37.228333 ========== PULL DRAM RESETB DOWN end =========
573 13:41:37.231859 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 13:41:37.235153 ===================================
575 13:41:37.238865 LPDDR4 DRAM CONFIGURATION
576 13:41:37.242767 ===================================
577 13:41:37.243350 EX_ROW_EN[0] = 0x0
578 13:41:37.246721 EX_ROW_EN[1] = 0x0
579 13:41:37.247189 LP4Y_EN = 0x0
580 13:41:37.250289 WORK_FSP = 0x0
581 13:41:37.250819 WL = 0x2
582 13:41:37.253867 RL = 0x2
583 13:41:37.254333 BL = 0x2
584 13:41:37.257437 RPST = 0x0
585 13:41:37.257904 RD_PRE = 0x0
586 13:41:37.261366 WR_PRE = 0x1
587 13:41:37.261928 WR_PST = 0x0
588 13:41:37.264972 DBI_WR = 0x0
589 13:41:37.265644 DBI_RD = 0x0
590 13:41:37.268432 OTF = 0x1
591 13:41:37.268909 ===================================
592 13:41:37.272343 ===================================
593 13:41:37.275819 ANA top config
594 13:41:37.279323 ===================================
595 13:41:37.279797 DLL_ASYNC_EN = 0
596 13:41:37.283472 ALL_SLAVE_EN = 1
597 13:41:37.286561 NEW_RANK_MODE = 1
598 13:41:37.287037 DLL_IDLE_MODE = 1
599 13:41:37.290689 LP45_APHY_COMB_EN = 1
600 13:41:37.294025 TX_ODT_DIS = 1
601 13:41:37.297000 NEW_8X_MODE = 1
602 13:41:37.300539 ===================================
603 13:41:37.303976 ===================================
604 13:41:37.304542 data_rate = 1600
605 13:41:37.307023 CKR = 1
606 13:41:37.310565 DQ_P2S_RATIO = 8
607 13:41:37.314071 ===================================
608 13:41:37.318263 CA_P2S_RATIO = 8
609 13:41:37.318737 DQ_CA_OPEN = 0
610 13:41:37.321357 DQ_SEMI_OPEN = 0
611 13:41:37.325447 CA_SEMI_OPEN = 0
612 13:41:37.329209 CA_FULL_RATE = 0
613 13:41:37.329816 DQ_CKDIV4_EN = 1
614 13:41:37.332778 CA_CKDIV4_EN = 1
615 13:41:37.336754 CA_PREDIV_EN = 0
616 13:41:37.339484 PH8_DLY = 0
617 13:41:37.343331 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 13:41:37.343904 DQ_AAMCK_DIV = 4
619 13:41:37.346154 CA_AAMCK_DIV = 4
620 13:41:37.349681 CA_ADMCK_DIV = 4
621 13:41:37.353279 DQ_TRACK_CA_EN = 0
622 13:41:37.356875 CA_PICK = 800
623 13:41:37.359771 CA_MCKIO = 800
624 13:41:37.360233 MCKIO_SEMI = 0
625 13:41:37.363725 PLL_FREQ = 3068
626 13:41:37.366605 DQ_UI_PI_RATIO = 32
627 13:41:37.369900 CA_UI_PI_RATIO = 0
628 13:41:37.373402 ===================================
629 13:41:37.377080 ===================================
630 13:41:37.380995 memory_type:LPDDR4
631 13:41:37.381647 GP_NUM : 10
632 13:41:37.384636 SRAM_EN : 1
633 13:41:37.385241 MD32_EN : 0
634 13:41:37.388359 ===================================
635 13:41:37.392465 [ANA_INIT] >>>>>>>>>>>>>>
636 13:41:37.393024 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 13:41:37.395962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 13:41:37.399898 ===================================
639 13:41:37.403448 data_rate = 1600,PCW = 0X7600
640 13:41:37.406792 ===================================
641 13:41:37.410921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 13:41:37.413612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 13:41:37.420598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 13:41:37.424182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 13:41:37.427184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 13:41:37.430710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 13:41:37.433570 [ANA_INIT] flow start
648 13:41:37.437040 [ANA_INIT] PLL >>>>>>>>
649 13:41:37.437554 [ANA_INIT] PLL <<<<<<<<
650 13:41:37.440464 [ANA_INIT] MIDPI >>>>>>>>
651 13:41:37.444061 [ANA_INIT] MIDPI <<<<<<<<
652 13:41:37.447501 [ANA_INIT] DLL >>>>>>>>
653 13:41:37.447963 [ANA_INIT] flow end
654 13:41:37.450437 ============ LP4 DIFF to SE enter ============
655 13:41:37.457401 ============ LP4 DIFF to SE exit ============
656 13:41:37.457981 [ANA_INIT] <<<<<<<<<<<<<
657 13:41:37.460797 [Flow] Enable top DCM control >>>>>
658 13:41:37.463734 [Flow] Enable top DCM control <<<<<
659 13:41:37.467155 Enable DLL master slave shuffle
660 13:41:37.473484 ==============================================================
661 13:41:37.473961 Gating Mode config
662 13:41:37.480766 ==============================================================
663 13:41:37.484127 Config description:
664 13:41:37.490439 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 13:41:37.497092 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 13:41:37.504276 SELPH_MODE 0: By rank 1: By Phase
667 13:41:37.510883 ==============================================================
668 13:41:37.511451 GAT_TRACK_EN = 1
669 13:41:37.513817 RX_GATING_MODE = 2
670 13:41:37.517131 RX_GATING_TRACK_MODE = 2
671 13:41:37.520736 SELPH_MODE = 1
672 13:41:37.523996 PICG_EARLY_EN = 1
673 13:41:37.527051 VALID_LAT_VALUE = 1
674 13:41:37.533622 ==============================================================
675 13:41:37.537096 Enter into Gating configuration >>>>
676 13:41:37.540374 Exit from Gating configuration <<<<
677 13:41:37.543612 Enter into DVFS_PRE_config >>>>>
678 13:41:37.553486 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 13:41:37.557441 Exit from DVFS_PRE_config <<<<<
680 13:41:37.560467 Enter into PICG configuration >>>>
681 13:41:37.564105 Exit from PICG configuration <<<<
682 13:41:37.566936 [RX_INPUT] configuration >>>>>
683 13:41:37.567509 [RX_INPUT] configuration <<<<<
684 13:41:37.573712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 13:41:37.580521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 13:41:37.586781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 13:41:37.590223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 13:41:37.596662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 13:41:37.603703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 13:41:37.606751 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 13:41:37.610433 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 13:41:37.617175 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 13:41:37.620306 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 13:41:37.623803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 13:41:37.630583 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 13:41:37.633664 ===================================
697 13:41:37.634129 LPDDR4 DRAM CONFIGURATION
698 13:41:37.636676 ===================================
699 13:41:37.640056 EX_ROW_EN[0] = 0x0
700 13:41:37.640519 EX_ROW_EN[1] = 0x0
701 13:41:37.643578 LP4Y_EN = 0x0
702 13:41:37.644043 WORK_FSP = 0x0
703 13:41:37.646959 WL = 0x2
704 13:41:37.647421 RL = 0x2
705 13:41:37.650494 BL = 0x2
706 13:41:37.653491 RPST = 0x0
707 13:41:37.653977 RD_PRE = 0x0
708 13:41:37.657156 WR_PRE = 0x1
709 13:41:37.657790 WR_PST = 0x0
710 13:41:37.660317 DBI_WR = 0x0
711 13:41:37.660897 DBI_RD = 0x0
712 13:41:37.663975 OTF = 0x1
713 13:41:37.667012 ===================================
714 13:41:37.670289 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 13:41:37.673196 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 13:41:37.677073 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 13:41:37.680505 ===================================
718 13:41:37.683461 LPDDR4 DRAM CONFIGURATION
719 13:41:37.686867 ===================================
720 13:41:37.689746 EX_ROW_EN[0] = 0x10
721 13:41:37.690219 EX_ROW_EN[1] = 0x0
722 13:41:37.693535 LP4Y_EN = 0x0
723 13:41:37.694104 WORK_FSP = 0x0
724 13:41:37.697055 WL = 0x2
725 13:41:37.697684 RL = 0x2
726 13:41:37.700354 BL = 0x2
727 13:41:37.700930 RPST = 0x0
728 13:41:37.703652 RD_PRE = 0x0
729 13:41:37.704222 WR_PRE = 0x1
730 13:41:37.707116 WR_PST = 0x0
731 13:41:37.707699 DBI_WR = 0x0
732 13:41:37.710448 DBI_RD = 0x0
733 13:41:37.711010 OTF = 0x1
734 13:41:37.713361 ===================================
735 13:41:37.720002 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 13:41:37.725374 nWR fixed to 40
737 13:41:37.728490 [ModeRegInit_LP4] CH0 RK0
738 13:41:37.729056 [ModeRegInit_LP4] CH0 RK1
739 13:41:37.731641 [ModeRegInit_LP4] CH1 RK0
740 13:41:37.735089 [ModeRegInit_LP4] CH1 RK1
741 13:41:37.735565 match AC timing 12
742 13:41:37.741868 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
743 13:41:37.744937 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 13:41:37.748330 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 13:41:37.754943 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 13:41:37.758977 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 13:41:37.759547 [EMI DOE] emi_dcm 0
748 13:41:37.765208 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 13:41:37.765842 ==
750 13:41:37.768837 Dram Type= 6, Freq= 0, CH_0, rank 0
751 13:41:37.771795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
752 13:41:37.772502 ==
753 13:41:37.778397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 13:41:37.785150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 13:41:37.792253 [CA 0] Center 37 (7~68) winsize 62
756 13:41:37.795847 [CA 1] Center 37 (7~68) winsize 62
757 13:41:37.799382 [CA 2] Center 35 (5~66) winsize 62
758 13:41:37.802126 [CA 3] Center 35 (5~66) winsize 62
759 13:41:37.805509 [CA 4] Center 34 (4~65) winsize 62
760 13:41:37.810013 [CA 5] Center 33 (3~64) winsize 62
761 13:41:37.810593
762 13:41:37.812775 [CmdBusTrainingLP45] Vref(ca) range 1: 32
763 13:41:37.813410
764 13:41:37.815826 [CATrainingPosCal] consider 1 rank data
765 13:41:37.819140 u2DelayCellTimex100 = 270/100 ps
766 13:41:37.822235 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 13:41:37.825804 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
768 13:41:37.832584 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
769 13:41:37.835899 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
770 13:41:37.839333 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
771 13:41:37.843042 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 13:41:37.843624
773 13:41:37.846190 CA PerBit enable=1, Macro0, CA PI delay=33
774 13:41:37.846988
775 13:41:37.849452 [CBTSetCACLKResult] CA Dly = 33
776 13:41:37.849922 CS Dly: 5 (0~36)
777 13:41:37.850294 ==
778 13:41:37.852661 Dram Type= 6, Freq= 0, CH_0, rank 1
779 13:41:37.859286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
780 13:41:37.859756 ==
781 13:41:37.862605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 13:41:37.869368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 13:41:37.878312 [CA 0] Center 37 (7~68) winsize 62
784 13:41:37.881739 [CA 1] Center 37 (6~68) winsize 63
785 13:41:37.884902 [CA 2] Center 35 (5~66) winsize 62
786 13:41:37.888922 [CA 3] Center 35 (4~66) winsize 63
787 13:41:37.891542 [CA 4] Center 34 (4~65) winsize 62
788 13:41:37.895455 [CA 5] Center 34 (3~65) winsize 63
789 13:41:37.896026
790 13:41:37.898769 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 13:41:37.899270
792 13:41:37.902017 [CATrainingPosCal] consider 2 rank data
793 13:41:37.905157 u2DelayCellTimex100 = 270/100 ps
794 13:41:37.908681 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 13:41:37.912003 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 13:41:37.918235 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 13:41:37.921910 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 13:41:37.925083 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 13:41:37.928403 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 13:41:37.928872
801 13:41:37.931939 CA PerBit enable=1, Macro0, CA PI delay=33
802 13:41:37.932479
803 13:41:37.934827 [CBTSetCACLKResult] CA Dly = 33
804 13:41:37.935294 CS Dly: 6 (0~38)
805 13:41:37.935669
806 13:41:37.938404 ----->DramcWriteLeveling(PI) begin...
807 13:41:37.941286 ==
808 13:41:37.945044 Dram Type= 6, Freq= 0, CH_0, rank 0
809 13:41:37.948100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 13:41:37.948571 ==
811 13:41:37.951567 Write leveling (Byte 0): 29 => 29
812 13:41:37.955215 Write leveling (Byte 1): 29 => 29
813 13:41:37.958476 DramcWriteLeveling(PI) end<-----
814 13:41:37.958901
815 13:41:37.959235 ==
816 13:41:37.961712 Dram Type= 6, Freq= 0, CH_0, rank 0
817 13:41:37.965339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
818 13:41:37.965812 ==
819 13:41:37.969475 [Gating] SW mode calibration
820 13:41:37.976638 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 13:41:37.979625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 13:41:37.983099 0 6 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
823 13:41:37.989980 0 6 4 | B1->B0 | 2727 2525 | 0 0 | (1 1) (1 1)
824 13:41:37.992856 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:41:37.996542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:41:38.003578 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:41:38.006737 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 13:41:38.010220 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 13:41:38.017137 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 13:41:38.020118 0 7 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
831 13:41:38.023832 0 7 4 | B1->B0 | 3737 4040 | 1 0 | (1 1) (0 0)
832 13:41:38.030203 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:41:38.033418 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:41:38.037012 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:41:38.040095 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:41:38.046550 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 13:41:38.050218 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 13:41:38.053357 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 13:41:38.060005 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
840 13:41:38.063706 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:41:38.066563 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:41:38.073657 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:41:38.076672 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:41:38.079827 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:41:38.086939 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:41:38.089965 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:41:38.093370 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:41:38.100110 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:41:38.103251 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:41:38.106820 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:41:38.113431 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:41:38.116783 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:41:38.119965 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:41:38.123535 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
855 13:41:38.130275 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 13:41:38.133903 Total UI for P1: 0, mck2ui 16
857 13:41:38.136748 best dqsien dly found for B0: ( 0, 10, 0)
858 13:41:38.140323 Total UI for P1: 0, mck2ui 16
859 13:41:38.143103 best dqsien dly found for B1: ( 0, 10, 0)
860 13:41:38.146736 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
861 13:41:38.150011 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
862 13:41:38.150620
863 13:41:38.153189 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
864 13:41:38.156672 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
865 13:41:38.160627 [Gating] SW calibration Done
866 13:41:38.161197 ==
867 13:41:38.163613 Dram Type= 6, Freq= 0, CH_0, rank 0
868 13:41:38.166932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
869 13:41:38.167511 ==
870 13:41:38.169848 RX Vref Scan: 0
871 13:41:38.170314
872 13:41:38.170684 RX Vref 0 -> 0, step: 1
873 13:41:38.171026
874 13:41:38.173396 RX Delay -130 -> 252, step: 16
875 13:41:38.180557 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
876 13:41:38.183569 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
877 13:41:38.186640 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
878 13:41:38.190217 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
879 13:41:38.193190 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
880 13:41:38.196940 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
881 13:41:38.203433 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
882 13:41:38.206923 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
883 13:41:38.210058 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
884 13:41:38.213479 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
885 13:41:38.220164 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
886 13:41:38.223614 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
887 13:41:38.226544 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
888 13:41:38.230170 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
889 13:41:38.233004 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
890 13:41:38.240241 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
891 13:41:38.240821 ==
892 13:41:38.243711 Dram Type= 6, Freq= 0, CH_0, rank 0
893 13:41:38.246615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
894 13:41:38.247186 ==
895 13:41:38.247555 DQS Delay:
896 13:41:38.249984 DQS0 = 0, DQS1 = 0
897 13:41:38.250446 DQM Delay:
898 13:41:38.253613 DQM0 = 83, DQM1 = 75
899 13:41:38.254203 DQ Delay:
900 13:41:38.256359 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
901 13:41:38.260060 DQ4 =77, DQ5 =69, DQ6 =101, DQ7 =101
902 13:41:38.263738 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
903 13:41:38.267084 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
904 13:41:38.267550
905 13:41:38.267916
906 13:41:38.268255 ==
907 13:41:38.270069 Dram Type= 6, Freq= 0, CH_0, rank 0
908 13:41:38.273478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
909 13:41:38.273943 ==
910 13:41:38.274313
911 13:41:38.274652
912 13:41:38.276966 TX Vref Scan disable
913 13:41:38.280487 == TX Byte 0 ==
914 13:41:38.283525 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
915 13:41:38.286917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
916 13:41:38.289856 == TX Byte 1 ==
917 13:41:38.293252 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
918 13:41:38.296733 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
919 13:41:38.297200 ==
920 13:41:38.300166 Dram Type= 6, Freq= 0, CH_0, rank 0
921 13:41:38.306782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
922 13:41:38.307351 ==
923 13:41:38.318156 TX Vref=22, minBit 0, minWin=27, winSum=444
924 13:41:38.321675 TX Vref=24, minBit 0, minWin=27, winSum=446
925 13:41:38.324964 TX Vref=26, minBit 3, minWin=27, winSum=450
926 13:41:38.328268 TX Vref=28, minBit 0, minWin=28, winSum=457
927 13:41:38.331390 TX Vref=30, minBit 0, minWin=28, winSum=457
928 13:41:38.335104 TX Vref=32, minBit 0, minWin=28, winSum=454
929 13:41:38.341393 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
930 13:41:38.341975
931 13:41:38.345268 Final TX Range 1 Vref 28
932 13:41:38.345885
933 13:41:38.346262 ==
934 13:41:38.348347 Dram Type= 6, Freq= 0, CH_0, rank 0
935 13:41:38.352580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
936 13:41:38.353385 ==
937 13:41:38.353818
938 13:41:38.354169
939 13:41:38.355701 TX Vref Scan disable
940 13:41:38.358725 == TX Byte 0 ==
941 13:41:38.362532 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 13:41:38.365609 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 13:41:38.369085 == TX Byte 1 ==
944 13:41:38.372331 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
945 13:41:38.375640 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
946 13:41:38.376227
947 13:41:38.378891 [DATLAT]
948 13:41:38.379403 Freq=800, CH0 RK0
949 13:41:38.379785
950 13:41:38.382666 DATLAT Default: 0xa
951 13:41:38.383260 0, 0xFFFF, sum = 0
952 13:41:38.385384 1, 0xFFFF, sum = 0
953 13:41:38.385865 2, 0xFFFF, sum = 0
954 13:41:38.389082 3, 0xFFFF, sum = 0
955 13:41:38.389727 4, 0xFFFF, sum = 0
956 13:41:38.391897 5, 0xFFFF, sum = 0
957 13:41:38.392378 6, 0xFFFF, sum = 0
958 13:41:38.395533 7, 0xFFFF, sum = 0
959 13:41:38.396006 8, 0x0, sum = 1
960 13:41:38.398971 9, 0x0, sum = 2
961 13:41:38.399482 10, 0x0, sum = 3
962 13:41:38.402364 11, 0x0, sum = 4
963 13:41:38.402945 best_step = 9
964 13:41:38.403320
965 13:41:38.403666 ==
966 13:41:38.405724 Dram Type= 6, Freq= 0, CH_0, rank 0
967 13:41:38.409004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
968 13:41:38.409507 ==
969 13:41:38.412109 RX Vref Scan: 1
970 13:41:38.412576
971 13:41:38.416022 Set Vref Range= 32 -> 127
972 13:41:38.416591
973 13:41:38.416965 RX Vref 32 -> 127, step: 1
974 13:41:38.417363
975 13:41:38.418600 RX Delay -111 -> 252, step: 8
976 13:41:38.419068
977 13:41:38.422902 Set Vref, RX VrefLevel [Byte0]: 32
978 13:41:38.425965 [Byte1]: 32
979 13:41:38.428972
980 13:41:38.429575 Set Vref, RX VrefLevel [Byte0]: 33
981 13:41:38.432239 [Byte1]: 33
982 13:41:38.436744
983 13:41:38.437209 Set Vref, RX VrefLevel [Byte0]: 34
984 13:41:38.439651 [Byte1]: 34
985 13:41:38.443898
986 13:41:38.444365 Set Vref, RX VrefLevel [Byte0]: 35
987 13:41:38.447538 [Byte1]: 35
988 13:41:38.451858
989 13:41:38.452329 Set Vref, RX VrefLevel [Byte0]: 36
990 13:41:38.455350 [Byte1]: 36
991 13:41:38.459798
992 13:41:38.460363 Set Vref, RX VrefLevel [Byte0]: 37
993 13:41:38.462907 [Byte1]: 37
994 13:41:38.467372
995 13:41:38.467842 Set Vref, RX VrefLevel [Byte0]: 38
996 13:41:38.470284 [Byte1]: 38
997 13:41:38.474692
998 13:41:38.475262 Set Vref, RX VrefLevel [Byte0]: 39
999 13:41:38.478047 [Byte1]: 39
1000 13:41:38.482913
1001 13:41:38.483486 Set Vref, RX VrefLevel [Byte0]: 40
1002 13:41:38.485734 [Byte1]: 40
1003 13:41:38.489820
1004 13:41:38.490286 Set Vref, RX VrefLevel [Byte0]: 41
1005 13:41:38.493276 [Byte1]: 41
1006 13:41:38.497858
1007 13:41:38.498431 Set Vref, RX VrefLevel [Byte0]: 42
1008 13:41:38.501258 [Byte1]: 42
1009 13:41:38.505576
1010 13:41:38.506179 Set Vref, RX VrefLevel [Byte0]: 43
1011 13:41:38.508432 [Byte1]: 43
1012 13:41:38.512780
1013 13:41:38.513249 Set Vref, RX VrefLevel [Byte0]: 44
1014 13:41:38.516590 [Byte1]: 44
1015 13:41:38.520910
1016 13:41:38.521527 Set Vref, RX VrefLevel [Byte0]: 45
1017 13:41:38.524316 [Byte1]: 45
1018 13:41:38.528565
1019 13:41:38.529139 Set Vref, RX VrefLevel [Byte0]: 46
1020 13:41:38.531418 [Byte1]: 46
1021 13:41:38.536009
1022 13:41:38.536583 Set Vref, RX VrefLevel [Byte0]: 47
1023 13:41:38.539168 [Byte1]: 47
1024 13:41:38.543611
1025 13:41:38.544227 Set Vref, RX VrefLevel [Byte0]: 48
1026 13:41:38.547187 [Byte1]: 48
1027 13:41:38.551340
1028 13:41:38.551904 Set Vref, RX VrefLevel [Byte0]: 49
1029 13:41:38.554608 [Byte1]: 49
1030 13:41:38.558744
1031 13:41:38.559240 Set Vref, RX VrefLevel [Byte0]: 50
1032 13:41:38.562664 [Byte1]: 50
1033 13:41:38.566850
1034 13:41:38.567411 Set Vref, RX VrefLevel [Byte0]: 51
1035 13:41:38.569475 [Byte1]: 51
1036 13:41:38.574744
1037 13:41:38.575307 Set Vref, RX VrefLevel [Byte0]: 52
1038 13:41:38.577619 [Byte1]: 52
1039 13:41:38.581596
1040 13:41:38.582057 Set Vref, RX VrefLevel [Byte0]: 53
1041 13:41:38.584840 [Byte1]: 53
1042 13:41:38.589727
1043 13:41:38.590290 Set Vref, RX VrefLevel [Byte0]: 54
1044 13:41:38.592500 [Byte1]: 54
1045 13:41:38.597350
1046 13:41:38.597904 Set Vref, RX VrefLevel [Byte0]: 55
1047 13:41:38.600100 [Byte1]: 55
1048 13:41:38.605157
1049 13:41:38.605768 Set Vref, RX VrefLevel [Byte0]: 56
1050 13:41:38.607836 [Byte1]: 56
1051 13:41:38.612913
1052 13:41:38.613499 Set Vref, RX VrefLevel [Byte0]: 57
1053 13:41:38.615606 [Byte1]: 57
1054 13:41:38.620675
1055 13:41:38.621229 Set Vref, RX VrefLevel [Byte0]: 58
1056 13:41:38.623700 [Byte1]: 58
1057 13:41:38.627949
1058 13:41:38.628411 Set Vref, RX VrefLevel [Byte0]: 59
1059 13:41:38.631282 [Byte1]: 59
1060 13:41:38.635528
1061 13:41:38.636093 Set Vref, RX VrefLevel [Byte0]: 60
1062 13:41:38.639086 [Byte1]: 60
1063 13:41:38.643342
1064 13:41:38.643804 Set Vref, RX VrefLevel [Byte0]: 61
1065 13:41:38.646376 [Byte1]: 61
1066 13:41:38.651131
1067 13:41:38.651682 Set Vref, RX VrefLevel [Byte0]: 62
1068 13:41:38.654468 [Byte1]: 62
1069 13:41:38.658062
1070 13:41:38.658542 Set Vref, RX VrefLevel [Byte0]: 63
1071 13:41:38.661614 [Byte1]: 63
1072 13:41:38.666140
1073 13:41:38.666704 Set Vref, RX VrefLevel [Byte0]: 64
1074 13:41:38.668969 [Byte1]: 64
1075 13:41:38.673712
1076 13:41:38.674174 Set Vref, RX VrefLevel [Byte0]: 65
1077 13:41:38.677318 [Byte1]: 65
1078 13:41:38.681054
1079 13:41:38.681560 Set Vref, RX VrefLevel [Byte0]: 66
1080 13:41:38.684719 [Byte1]: 66
1081 13:41:38.688861
1082 13:41:38.689476 Set Vref, RX VrefLevel [Byte0]: 67
1083 13:41:38.692226 [Byte1]: 67
1084 13:41:38.696417
1085 13:41:38.696991 Set Vref, RX VrefLevel [Byte0]: 68
1086 13:41:38.699688 [Byte1]: 68
1087 13:41:38.704337
1088 13:41:38.704909 Set Vref, RX VrefLevel [Byte0]: 69
1089 13:41:38.707289 [Byte1]: 69
1090 13:41:38.712220
1091 13:41:38.712799 Set Vref, RX VrefLevel [Byte0]: 70
1092 13:41:38.715198 [Byte1]: 70
1093 13:41:38.719448
1094 13:41:38.720024 Set Vref, RX VrefLevel [Byte0]: 71
1095 13:41:38.723002 [Byte1]: 71
1096 13:41:38.727076
1097 13:41:38.727675 Set Vref, RX VrefLevel [Byte0]: 72
1098 13:41:38.730629 [Byte1]: 72
1099 13:41:38.734611
1100 13:41:38.735158 Set Vref, RX VrefLevel [Byte0]: 73
1101 13:41:38.738062 [Byte1]: 73
1102 13:41:38.742163
1103 13:41:38.742710 Set Vref, RX VrefLevel [Byte0]: 74
1104 13:41:38.746038 [Byte1]: 74
1105 13:41:38.750230
1106 13:41:38.750783 Set Vref, RX VrefLevel [Byte0]: 75
1107 13:41:38.753122 [Byte1]: 75
1108 13:41:38.757701
1109 13:41:38.758201 Final RX Vref Byte 0 = 53 to rank0
1110 13:41:38.760672 Final RX Vref Byte 1 = 55 to rank0
1111 13:41:38.764527 Final RX Vref Byte 0 = 53 to rank1
1112 13:41:38.768110 Final RX Vref Byte 1 = 55 to rank1==
1113 13:41:38.770938 Dram Type= 6, Freq= 0, CH_0, rank 0
1114 13:41:38.777583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1115 13:41:38.778045 ==
1116 13:41:38.778413 DQS Delay:
1117 13:41:38.778749 DQS0 = 0, DQS1 = 0
1118 13:41:38.781073 DQM Delay:
1119 13:41:38.781570 DQM0 = 83, DQM1 = 73
1120 13:41:38.784194 DQ Delay:
1121 13:41:38.787648 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1122 13:41:38.788199 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1123 13:41:38.790834 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1124 13:41:38.794313 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1125 13:41:38.797913
1126 13:41:38.798463
1127 13:41:38.804237 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1128 13:41:38.807663 CH0 RK0: MR19=606, MR18=3636
1129 13:41:38.814008 CH0_RK0: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1130 13:41:38.814476
1131 13:41:38.817874 ----->DramcWriteLeveling(PI) begin...
1132 13:41:38.818431 ==
1133 13:41:38.821371 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 13:41:38.824447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1135 13:41:38.825005 ==
1136 13:41:38.827726 Write leveling (Byte 0): 28 => 28
1137 13:41:38.831030 Write leveling (Byte 1): 27 => 27
1138 13:41:38.834466 DramcWriteLeveling(PI) end<-----
1139 13:41:38.835020
1140 13:41:38.835386 ==
1141 13:41:38.837324 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 13:41:38.840874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1143 13:41:38.841475 ==
1144 13:41:38.844472 [Gating] SW mode calibration
1145 13:41:38.850526 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1146 13:41:38.857581 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1147 13:41:38.860798 0 6 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
1148 13:41:38.864251 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1149 13:41:38.870895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:41:38.874575 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:41:38.877424 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:41:38.884621 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:41:38.887908 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:41:38.890661 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:41:38.897843 0 7 0 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
1156 13:41:38.901164 0 7 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1157 13:41:38.904296 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1158 13:41:38.911019 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1159 13:41:38.914406 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1160 13:41:38.917892 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1161 13:41:38.924066 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1162 13:41:38.927617 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1163 13:41:38.930504 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1164 13:41:38.937222 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1165 13:41:38.940655 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1166 13:41:38.944190 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 13:41:38.947639 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 13:41:38.954298 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 13:41:38.957087 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 13:41:38.960596 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1171 13:41:38.967494 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1172 13:41:38.971022 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1173 13:41:38.973563 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1174 13:41:38.980326 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1175 13:41:38.983779 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1176 13:41:38.986913 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1177 13:41:38.993413 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1178 13:41:38.997120 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1179 13:41:39.000457 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1180 13:41:39.007244 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 13:41:39.007852 Total UI for P1: 0, mck2ui 16
1182 13:41:39.013798 best dqsien dly found for B0: ( 0, 10, 2)
1183 13:41:39.014461 Total UI for P1: 0, mck2ui 16
1184 13:41:39.020215 best dqsien dly found for B1: ( 0, 10, 0)
1185 13:41:39.023660 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1186 13:41:39.027158 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1187 13:41:39.027579
1188 13:41:39.030324 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1189 13:41:39.033325 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1190 13:41:39.078053 [Gating] SW calibration Done
1191 13:41:39.078649 ==
1192 13:41:39.079152 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 13:41:39.080011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1194 13:41:39.080586 ==
1195 13:41:39.080943 RX Vref Scan: 0
1196 13:41:39.081272
1197 13:41:39.081650 RX Vref 0 -> 0, step: 1
1198 13:41:39.081971
1199 13:41:39.082279 RX Delay -130 -> 252, step: 16
1200 13:41:39.082588 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1201 13:41:39.082893 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1202 13:41:39.083221 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1203 13:41:39.083551 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1204 13:41:39.083860 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1205 13:41:39.084161 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1206 13:41:39.084465 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1207 13:41:39.084841 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1208 13:41:39.086582 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1209 13:41:39.090170 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1210 13:41:39.093464 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1211 13:41:39.100618 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1212 13:41:39.103511 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1213 13:41:39.106551 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1214 13:41:39.110202 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1215 13:41:39.116397 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1216 13:41:39.117114 ==
1217 13:41:39.120112 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 13:41:39.123245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 13:41:39.123933 ==
1220 13:41:39.124478 DQS Delay:
1221 13:41:39.126538 DQS0 = 0, DQS1 = 0
1222 13:41:39.127001 DQM Delay:
1223 13:41:39.129944 DQM0 = 82, DQM1 = 75
1224 13:41:39.130597 DQ Delay:
1225 13:41:39.133282 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1226 13:41:39.136875 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1227 13:41:39.140268 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1228 13:41:39.143222 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1229 13:41:39.143810
1230 13:41:39.144166
1231 13:41:39.144480 ==
1232 13:41:39.146816 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 13:41:39.149860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1234 13:41:39.150383 ==
1235 13:41:39.150802
1236 13:41:39.151417
1237 13:41:39.153491 TX Vref Scan disable
1238 13:41:39.156796 == TX Byte 0 ==
1239 13:41:39.159858 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1240 13:41:39.163282 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1241 13:41:39.166255 == TX Byte 1 ==
1242 13:41:39.169824 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1243 13:41:39.173609 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1244 13:41:39.174075 ==
1245 13:41:39.176399 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 13:41:39.180038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1247 13:41:39.183331 ==
1248 13:41:39.194372 TX Vref=22, minBit 0, minWin=27, winSum=442
1249 13:41:39.197736 TX Vref=24, minBit 0, minWin=27, winSum=447
1250 13:41:39.201387 TX Vref=26, minBit 1, minWin=28, winSum=454
1251 13:41:39.204981 TX Vref=28, minBit 2, minWin=28, winSum=456
1252 13:41:39.208964 TX Vref=30, minBit 2, minWin=28, winSum=457
1253 13:41:39.212565 TX Vref=32, minBit 0, minWin=28, winSum=458
1254 13:41:39.219486 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 32
1255 13:41:39.219959
1256 13:41:39.220290 Final TX Range 1 Vref 32
1257 13:41:39.222612
1258 13:41:39.223026 ==
1259 13:41:39.226381 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 13:41:39.230155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1261 13:41:39.230586 ==
1262 13:41:39.230921
1263 13:41:39.231228
1264 13:41:39.231524 TX Vref Scan disable
1265 13:41:39.233957 == TX Byte 0 ==
1266 13:41:39.237204 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1267 13:41:39.240627 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1268 13:41:39.243982 == TX Byte 1 ==
1269 13:41:39.247210 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1270 13:41:39.253932 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1271 13:41:39.254238
1272 13:41:39.254470 [DATLAT]
1273 13:41:39.254686 Freq=800, CH0 RK1
1274 13:41:39.254894
1275 13:41:39.257554 DATLAT Default: 0x9
1276 13:41:39.257854 0, 0xFFFF, sum = 0
1277 13:41:39.260425 1, 0xFFFF, sum = 0
1278 13:41:39.260731 2, 0xFFFF, sum = 0
1279 13:41:39.263853 3, 0xFFFF, sum = 0
1280 13:41:39.264155 4, 0xFFFF, sum = 0
1281 13:41:39.267193 5, 0xFFFF, sum = 0
1282 13:41:39.270711 6, 0xFFFF, sum = 0
1283 13:41:39.271029 7, 0xFFFF, sum = 0
1284 13:41:39.271267 8, 0x0, sum = 1
1285 13:41:39.274221 9, 0x0, sum = 2
1286 13:41:39.274640 10, 0x0, sum = 3
1287 13:41:39.277126 11, 0x0, sum = 4
1288 13:41:39.277641 best_step = 9
1289 13:41:39.278070
1290 13:41:39.278398 ==
1291 13:41:39.280772 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 13:41:39.287216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1293 13:41:39.287521 ==
1294 13:41:39.287756 RX Vref Scan: 0
1295 13:41:39.287971
1296 13:41:39.290538 RX Vref 0 -> 0, step: 1
1297 13:41:39.290832
1298 13:41:39.293531 RX Delay -95 -> 252, step: 8
1299 13:41:39.297029 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1300 13:41:39.300672 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1301 13:41:39.307485 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1302 13:41:39.310240 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1303 13:41:39.313901 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1304 13:41:39.316743 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1305 13:41:39.320379 iDelay=217, Bit 6, Center 88 (-31 ~ 208) 240
1306 13:41:39.327198 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1307 13:41:39.330791 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1308 13:41:39.333771 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1309 13:41:39.337248 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1310 13:41:39.340730 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1311 13:41:39.347216 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1312 13:41:39.350859 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1313 13:41:39.354069 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1314 13:41:39.357657 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1315 13:41:39.358069 ==
1316 13:41:39.360603 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 13:41:39.363935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1318 13:41:39.367283 ==
1319 13:41:39.367836 DQS Delay:
1320 13:41:39.368170 DQS0 = 0, DQS1 = 0
1321 13:41:39.370687 DQM Delay:
1322 13:41:39.371142 DQM0 = 85, DQM1 = 74
1323 13:41:39.373866 DQ Delay:
1324 13:41:39.374274 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1325 13:41:39.377416 DQ4 =88, DQ5 =76, DQ6 =88, DQ7 =96
1326 13:41:39.380890 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1327 13:41:39.384156 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1328 13:41:39.387381
1329 13:41:39.387980
1330 13:41:39.393753 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1331 13:41:39.397397 CH0 RK1: MR19=606, MR18=4242
1332 13:41:39.403867 CH0_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1333 13:41:39.406865 [RxdqsGatingPostProcess] freq 800
1334 13:41:39.410520 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1335 13:41:39.414058 Pre-setting of DQS Precalculation
1336 13:41:39.420845 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1337 13:41:39.421494 ==
1338 13:41:39.423662 Dram Type= 6, Freq= 0, CH_1, rank 0
1339 13:41:39.427259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1340 13:41:39.427802 ==
1341 13:41:39.430747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1342 13:41:39.437039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1343 13:41:39.447197 [CA 0] Center 36 (6~67) winsize 62
1344 13:41:39.450516 [CA 1] Center 36 (5~67) winsize 63
1345 13:41:39.453482 [CA 2] Center 34 (4~65) winsize 62
1346 13:41:39.457031 [CA 3] Center 34 (4~65) winsize 62
1347 13:41:39.460566 [CA 4] Center 33 (3~63) winsize 61
1348 13:41:39.463588 [CA 5] Center 32 (2~63) winsize 62
1349 13:41:39.463996
1350 13:41:39.467061 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1351 13:41:39.467504
1352 13:41:39.470302 [CATrainingPosCal] consider 1 rank data
1353 13:41:39.473559 u2DelayCellTimex100 = 270/100 ps
1354 13:41:39.476862 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
1355 13:41:39.479888 CA1 delay=36 (5~67),Diff = 4 PI (28 cell)
1356 13:41:39.486913 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
1357 13:41:39.489846 CA3 delay=34 (4~65),Diff = 2 PI (14 cell)
1358 13:41:39.493412 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
1359 13:41:39.496849 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
1360 13:41:39.497476
1361 13:41:39.500016 CA PerBit enable=1, Macro0, CA PI delay=32
1362 13:41:39.500423
1363 13:41:39.503277 [CBTSetCACLKResult] CA Dly = 32
1364 13:41:39.503686 CS Dly: 4 (0~35)
1365 13:41:39.507006 ==
1366 13:41:39.507477 Dram Type= 6, Freq= 0, CH_1, rank 1
1367 13:41:39.513595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 13:41:39.514010 ==
1369 13:41:39.516606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 13:41:39.523766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 13:41:39.532711 [CA 0] Center 36 (6~67) winsize 62
1372 13:41:39.536246 [CA 1] Center 36 (5~67) winsize 63
1373 13:41:39.539657 [CA 2] Center 34 (4~65) winsize 62
1374 13:41:39.542686 [CA 3] Center 34 (4~65) winsize 62
1375 13:41:39.546291 [CA 4] Center 33 (3~64) winsize 62
1376 13:41:39.549344 [CA 5] Center 33 (3~63) winsize 61
1377 13:41:39.549754
1378 13:41:39.553114 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1379 13:41:39.553564
1380 13:41:39.556153 [CATrainingPosCal] consider 2 rank data
1381 13:41:39.559667 u2DelayCellTimex100 = 270/100 ps
1382 13:41:39.562600 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1383 13:41:39.566138 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1384 13:41:39.572567 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 13:41:39.576163 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 13:41:39.579443 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1387 13:41:39.582529 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1388 13:41:39.582936
1389 13:41:39.585978 CA PerBit enable=1, Macro0, CA PI delay=33
1390 13:41:39.586386
1391 13:41:39.589598 [CBTSetCACLKResult] CA Dly = 33
1392 13:41:39.590007 CS Dly: 4 (0~36)
1393 13:41:39.590325
1394 13:41:39.592473 ----->DramcWriteLeveling(PI) begin...
1395 13:41:39.595663 ==
1396 13:41:39.599057 Dram Type= 6, Freq= 0, CH_1, rank 0
1397 13:41:39.602652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1398 13:41:39.603061 ==
1399 13:41:39.605805 Write leveling (Byte 0): 26 => 26
1400 13:41:39.609571 Write leveling (Byte 1): 26 => 26
1401 13:41:39.612808 DramcWriteLeveling(PI) end<-----
1402 13:41:39.613212
1403 13:41:39.613563 ==
1404 13:41:39.615907 Dram Type= 6, Freq= 0, CH_1, rank 0
1405 13:41:39.619193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1406 13:41:39.619602 ==
1407 13:41:39.622413 [Gating] SW mode calibration
1408 13:41:39.629318 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1409 13:41:39.632835 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1410 13:41:39.639239 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
1411 13:41:39.642689 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1412 13:41:39.645632 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1413 13:41:39.652212 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1414 13:41:39.655940 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1415 13:41:39.659184 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1416 13:41:39.665666 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1417 13:41:39.668965 0 6 28 | B1->B0 | 2626 3030 | 0 1 | (0 0) (0 0)
1418 13:41:39.672767 0 7 0 | B1->B0 | 3131 3d3d | 1 0 | (0 0) (0 0)
1419 13:41:39.679172 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1420 13:41:39.682174 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1421 13:41:39.685704 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1422 13:41:39.692099 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1423 13:41:39.695837 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1424 13:41:39.698862 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1425 13:41:39.705852 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1426 13:41:39.708924 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1427 13:41:39.712272 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1428 13:41:39.719216 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1429 13:41:39.722587 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1430 13:41:39.725700 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 13:41:39.732233 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 13:41:39.735718 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1433 13:41:39.738771 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1434 13:41:39.745487 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1435 13:41:39.749040 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1436 13:41:39.752007 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1437 13:41:39.755534 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1438 13:41:39.762015 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1439 13:41:39.765390 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1440 13:41:39.768933 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1441 13:41:39.775471 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1442 13:41:39.779006 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1443 13:41:39.781956 Total UI for P1: 0, mck2ui 16
1444 13:41:39.785397 best dqsien dly found for B0: ( 0, 9, 28)
1445 13:41:39.788968 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 13:41:39.791871 Total UI for P1: 0, mck2ui 16
1447 13:41:39.795577 best dqsien dly found for B1: ( 0, 9, 30)
1448 13:41:39.798536 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1449 13:41:39.802261 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1450 13:41:39.805108
1451 13:41:39.808632 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1452 13:41:39.812192 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1453 13:41:39.815611 [Gating] SW calibration Done
1454 13:41:39.816018 ==
1455 13:41:39.818664 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 13:41:39.822159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1457 13:41:39.822574 ==
1458 13:41:39.822897 RX Vref Scan: 0
1459 13:41:39.825529
1460 13:41:39.825946 RX Vref 0 -> 0, step: 1
1461 13:41:39.826269
1462 13:41:39.828518 RX Delay -130 -> 252, step: 16
1463 13:41:39.832071 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1464 13:41:39.835366 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1465 13:41:39.842272 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1466 13:41:39.845387 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1467 13:41:39.849039 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1468 13:41:39.851898 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1469 13:41:39.855133 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1470 13:41:39.862067 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1471 13:41:39.865587 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1472 13:41:39.869182 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1473 13:41:39.872673 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1474 13:41:39.876316 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1475 13:41:39.879901 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1476 13:41:39.883458 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1477 13:41:39.887073 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1478 13:41:39.894757 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1479 13:41:39.895169 ==
1480 13:41:39.898603 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 13:41:39.901462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 13:41:39.901875 ==
1483 13:41:39.902199 DQS Delay:
1484 13:41:39.905205 DQS0 = 0, DQS1 = 0
1485 13:41:39.905649 DQM Delay:
1486 13:41:39.905968 DQM0 = 81, DQM1 = 70
1487 13:41:39.908401 DQ Delay:
1488 13:41:39.911582 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1489 13:41:39.915239 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1490 13:41:39.918130 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1491 13:41:39.921614 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1492 13:41:39.922017
1493 13:41:39.922335
1494 13:41:39.922625 ==
1495 13:41:39.925256 Dram Type= 6, Freq= 0, CH_1, rank 0
1496 13:41:39.928393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1497 13:41:39.928801 ==
1498 13:41:39.929121
1499 13:41:39.929459
1500 13:41:39.931938 TX Vref Scan disable
1501 13:41:39.932343 == TX Byte 0 ==
1502 13:41:39.938483 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1503 13:41:39.941349 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1504 13:41:39.941791 == TX Byte 1 ==
1505 13:41:39.948432 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1506 13:41:39.951329 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1507 13:41:39.951738 ==
1508 13:41:39.954877 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 13:41:39.958024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1510 13:41:39.958433 ==
1511 13:41:39.972183 TX Vref=22, minBit 3, minWin=27, winSum=443
1512 13:41:39.975128 TX Vref=24, minBit 3, minWin=27, winSum=445
1513 13:41:39.978514 TX Vref=26, minBit 3, minWin=27, winSum=447
1514 13:41:39.981889 TX Vref=28, minBit 2, minWin=28, winSum=453
1515 13:41:39.985424 TX Vref=30, minBit 2, minWin=28, winSum=454
1516 13:41:39.992255 TX Vref=32, minBit 0, minWin=28, winSum=450
1517 13:41:39.995062 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
1518 13:41:39.995477
1519 13:41:39.998373 Final TX Range 1 Vref 30
1520 13:41:39.998834
1521 13:41:39.999197 ==
1522 13:41:40.001845 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 13:41:40.005486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1524 13:41:40.005901 ==
1525 13:41:40.008377
1526 13:41:40.008782
1527 13:41:40.009106 TX Vref Scan disable
1528 13:41:40.011882 == TX Byte 0 ==
1529 13:41:40.015421 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1530 13:41:40.018395 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1531 13:41:40.021951 == TX Byte 1 ==
1532 13:41:40.025583 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1533 13:41:40.028341 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1534 13:41:40.031666
1535 13:41:40.031884 [DATLAT]
1536 13:41:40.032055 Freq=800, CH1 RK0
1537 13:41:40.032217
1538 13:41:40.035139 DATLAT Default: 0xa
1539 13:41:40.035356 0, 0xFFFF, sum = 0
1540 13:41:40.038571 1, 0xFFFF, sum = 0
1541 13:41:40.038750 2, 0xFFFF, sum = 0
1542 13:41:40.041506 3, 0xFFFF, sum = 0
1543 13:41:40.041714 4, 0xFFFF, sum = 0
1544 13:41:40.044917 5, 0xFFFF, sum = 0
1545 13:41:40.045095 6, 0xFFFF, sum = 0
1546 13:41:40.048427 7, 0xFFFF, sum = 0
1547 13:41:40.048605 8, 0x0, sum = 1
1548 13:41:40.051370 9, 0x0, sum = 2
1549 13:41:40.051548 10, 0x0, sum = 3
1550 13:41:40.054815 11, 0x0, sum = 4
1551 13:41:40.054994 best_step = 9
1552 13:41:40.055132
1553 13:41:40.055260 ==
1554 13:41:40.058249 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 13:41:40.064615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1556 13:41:40.064793 ==
1557 13:41:40.064932 RX Vref Scan: 1
1558 13:41:40.065062
1559 13:41:40.068600 Set Vref Range= 32 -> 127
1560 13:41:40.069007
1561 13:41:40.072116 RX Vref 32 -> 127, step: 1
1562 13:41:40.072625
1563 13:41:40.075239 RX Delay -111 -> 252, step: 8
1564 13:41:40.075647
1565 13:41:40.078524 Set Vref, RX VrefLevel [Byte0]: 32
1566 13:41:40.078938 [Byte1]: 32
1567 13:41:40.082979
1568 13:41:40.083388 Set Vref, RX VrefLevel [Byte0]: 33
1569 13:41:40.086126 [Byte1]: 33
1570 13:41:40.090458
1571 13:41:40.090867 Set Vref, RX VrefLevel [Byte0]: 34
1572 13:41:40.093990 [Byte1]: 34
1573 13:41:40.098106
1574 13:41:40.098513 Set Vref, RX VrefLevel [Byte0]: 35
1575 13:41:40.101881 [Byte1]: 35
1576 13:41:40.105784
1577 13:41:40.106199 Set Vref, RX VrefLevel [Byte0]: 36
1578 13:41:40.109245 [Byte1]: 36
1579 13:41:40.113342
1580 13:41:40.113754 Set Vref, RX VrefLevel [Byte0]: 37
1581 13:41:40.117029 [Byte1]: 37
1582 13:41:40.120945
1583 13:41:40.121388 Set Vref, RX VrefLevel [Byte0]: 38
1584 13:41:40.124397 [Byte1]: 38
1585 13:41:40.128607
1586 13:41:40.129013 Set Vref, RX VrefLevel [Byte0]: 39
1587 13:41:40.132374 [Byte1]: 39
1588 13:41:40.136393
1589 13:41:40.139930 Set Vref, RX VrefLevel [Byte0]: 40
1590 13:41:40.140312 [Byte1]: 40
1591 13:41:40.143966
1592 13:41:40.144410 Set Vref, RX VrefLevel [Byte0]: 41
1593 13:41:40.147538 [Byte1]: 41
1594 13:41:40.151516
1595 13:41:40.151926 Set Vref, RX VrefLevel [Byte0]: 42
1596 13:41:40.154961 [Byte1]: 42
1597 13:41:40.159144
1598 13:41:40.159560 Set Vref, RX VrefLevel [Byte0]: 43
1599 13:41:40.162731 [Byte1]: 43
1600 13:41:40.166704
1601 13:41:40.167152 Set Vref, RX VrefLevel [Byte0]: 44
1602 13:41:40.170509 [Byte1]: 44
1603 13:41:40.174507
1604 13:41:40.174916 Set Vref, RX VrefLevel [Byte0]: 45
1605 13:41:40.177864 [Byte1]: 45
1606 13:41:40.182165
1607 13:41:40.182589 Set Vref, RX VrefLevel [Byte0]: 46
1608 13:41:40.185373 [Byte1]: 46
1609 13:41:40.190045
1610 13:41:40.190518 Set Vref, RX VrefLevel [Byte0]: 47
1611 13:41:40.193509 [Byte1]: 47
1612 13:41:40.197408
1613 13:41:40.197962 Set Vref, RX VrefLevel [Byte0]: 48
1614 13:41:40.200514 [Byte1]: 48
1615 13:41:40.205206
1616 13:41:40.205809 Set Vref, RX VrefLevel [Byte0]: 49
1617 13:41:40.208231 [Byte1]: 49
1618 13:41:40.212911
1619 13:41:40.213453 Set Vref, RX VrefLevel [Byte0]: 50
1620 13:41:40.215855 [Byte1]: 50
1621 13:41:40.220611
1622 13:41:40.221071 Set Vref, RX VrefLevel [Byte0]: 51
1623 13:41:40.223561 [Byte1]: 51
1624 13:41:40.228328
1625 13:41:40.228810 Set Vref, RX VrefLevel [Byte0]: 52
1626 13:41:40.231231 [Byte1]: 52
1627 13:41:40.236038
1628 13:41:40.238937 Set Vref, RX VrefLevel [Byte0]: 53
1629 13:41:40.239449 [Byte1]: 53
1630 13:41:40.243746
1631 13:41:40.244276 Set Vref, RX VrefLevel [Byte0]: 54
1632 13:41:40.246595 [Byte1]: 54
1633 13:41:40.251234
1634 13:41:40.251773 Set Vref, RX VrefLevel [Byte0]: 55
1635 13:41:40.254082 [Byte1]: 55
1636 13:41:40.258650
1637 13:41:40.259145 Set Vref, RX VrefLevel [Byte0]: 56
1638 13:41:40.262289 [Byte1]: 56
1639 13:41:40.266389
1640 13:41:40.266971 Set Vref, RX VrefLevel [Byte0]: 57
1641 13:41:40.269752 [Byte1]: 57
1642 13:41:40.273955
1643 13:41:40.274526 Set Vref, RX VrefLevel [Byte0]: 58
1644 13:41:40.276994 [Byte1]: 58
1645 13:41:40.281569
1646 13:41:40.282111 Set Vref, RX VrefLevel [Byte0]: 59
1647 13:41:40.284857 [Byte1]: 59
1648 13:41:40.289136
1649 13:41:40.289643 Set Vref, RX VrefLevel [Byte0]: 60
1650 13:41:40.292382 [Byte1]: 60
1651 13:41:40.297024
1652 13:41:40.297514 Set Vref, RX VrefLevel [Byte0]: 61
1653 13:41:40.300493 [Byte1]: 61
1654 13:41:40.304619
1655 13:41:40.305028 Set Vref, RX VrefLevel [Byte0]: 62
1656 13:41:40.307954 [Byte1]: 62
1657 13:41:40.312237
1658 13:41:40.312646 Set Vref, RX VrefLevel [Byte0]: 63
1659 13:41:40.315560 [Byte1]: 63
1660 13:41:40.319986
1661 13:41:40.320401 Set Vref, RX VrefLevel [Byte0]: 64
1662 13:41:40.323072 [Byte1]: 64
1663 13:41:40.327293
1664 13:41:40.327708 Set Vref, RX VrefLevel [Byte0]: 65
1665 13:41:40.330522 [Byte1]: 65
1666 13:41:40.335208
1667 13:41:40.335722 Set Vref, RX VrefLevel [Byte0]: 66
1668 13:41:40.338685 [Byte1]: 66
1669 13:41:40.342823
1670 13:41:40.343238 Set Vref, RX VrefLevel [Byte0]: 67
1671 13:41:40.345851 [Byte1]: 67
1672 13:41:40.350749
1673 13:41:40.351237 Set Vref, RX VrefLevel [Byte0]: 68
1674 13:41:40.353641 [Byte1]: 68
1675 13:41:40.358073
1676 13:41:40.358486 Set Vref, RX VrefLevel [Byte0]: 69
1677 13:41:40.361464 [Byte1]: 69
1678 13:41:40.365829
1679 13:41:40.366245 Set Vref, RX VrefLevel [Byte0]: 70
1680 13:41:40.368897 [Byte1]: 70
1681 13:41:40.373477
1682 13:41:40.374038 Set Vref, RX VrefLevel [Byte0]: 71
1683 13:41:40.376502 [Byte1]: 71
1684 13:41:40.381492
1685 13:41:40.381994 Set Vref, RX VrefLevel [Byte0]: 72
1686 13:41:40.384232 [Byte1]: 72
1687 13:41:40.389273
1688 13:41:40.389876 Set Vref, RX VrefLevel [Byte0]: 73
1689 13:41:40.392054 [Byte1]: 73
1690 13:41:40.396595
1691 13:41:40.397053 Set Vref, RX VrefLevel [Byte0]: 74
1692 13:41:40.399629 [Byte1]: 74
1693 13:41:40.403850
1694 13:41:40.404308 Final RX Vref Byte 0 = 58 to rank0
1695 13:41:40.407449 Final RX Vref Byte 1 = 53 to rank0
1696 13:41:40.410594 Final RX Vref Byte 0 = 58 to rank1
1697 13:41:40.414064 Final RX Vref Byte 1 = 53 to rank1==
1698 13:41:40.417572 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 13:41:40.423975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1700 13:41:40.424517 ==
1701 13:41:40.424876 DQS Delay:
1702 13:41:40.425206 DQS0 = 0, DQS1 = 0
1703 13:41:40.427163 DQM Delay:
1704 13:41:40.427610 DQM0 = 79, DQM1 = 72
1705 13:41:40.430430 DQ Delay:
1706 13:41:40.433803 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1707 13:41:40.434220 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1708 13:41:40.437459 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1709 13:41:40.444405 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1710 13:41:40.444996
1711 13:41:40.445433
1712 13:41:40.451187 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1713 13:41:40.454193 CH1 RK0: MR19=606, MR18=4C4C
1714 13:41:40.460895 CH1_RK0: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1715 13:41:40.461377
1716 13:41:40.464447 ----->DramcWriteLeveling(PI) begin...
1717 13:41:40.464904 ==
1718 13:41:40.467996 Dram Type= 6, Freq= 0, CH_1, rank 1
1719 13:41:40.471424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1720 13:41:40.471854 ==
1721 13:41:40.474426 Write leveling (Byte 0): 26 => 26
1722 13:41:40.477912 Write leveling (Byte 1): 27 => 27
1723 13:41:40.481095 DramcWriteLeveling(PI) end<-----
1724 13:41:40.481579
1725 13:41:40.481935 ==
1726 13:41:40.484194 Dram Type= 6, Freq= 0, CH_1, rank 1
1727 13:41:40.487824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1728 13:41:40.488388 ==
1729 13:41:40.491094 [Gating] SW mode calibration
1730 13:41:40.497595 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1731 13:41:40.504638 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1732 13:41:40.507897 0 6 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1733 13:41:40.511009 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1734 13:41:40.517974 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1735 13:41:40.520938 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1736 13:41:40.524251 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1737 13:41:40.527787 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1738 13:41:40.534502 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1739 13:41:40.537777 0 6 28 | B1->B0 | 2424 3131 | 0 0 | (1 1) (0 0)
1740 13:41:40.541609 0 7 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1741 13:41:40.548278 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1742 13:41:40.551310 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1743 13:41:40.554480 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1744 13:41:40.561123 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1745 13:41:40.564100 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1746 13:41:40.567629 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1747 13:41:40.574282 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1748 13:41:40.577259 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1749 13:41:40.580879 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1750 13:41:40.587759 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1751 13:41:40.591136 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1752 13:41:40.594303 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1753 13:41:40.601241 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1754 13:41:40.604308 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1755 13:41:40.607946 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1756 13:41:40.614393 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1757 13:41:40.617919 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1758 13:41:40.620693 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1759 13:41:40.627657 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1760 13:41:40.631255 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1761 13:41:40.634013 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1762 13:41:40.641069 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1763 13:41:40.644155 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1764 13:41:40.648198 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1765 13:41:40.651075 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1766 13:41:40.654534 Total UI for P1: 0, mck2ui 16
1767 13:41:40.657503 best dqsien dly found for B0: ( 0, 9, 28)
1768 13:41:40.660921 Total UI for P1: 0, mck2ui 16
1769 13:41:40.664778 best dqsien dly found for B1: ( 0, 10, 0)
1770 13:41:40.667403 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1771 13:41:40.671217 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1772 13:41:40.671767
1773 13:41:40.677402 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1774 13:41:40.681366 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1775 13:41:40.684690 [Gating] SW calibration Done
1776 13:41:40.685160 ==
1777 13:41:40.687878 Dram Type= 6, Freq= 0, CH_1, rank 1
1778 13:41:40.691102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1779 13:41:40.691560 ==
1780 13:41:40.691913 RX Vref Scan: 0
1781 13:41:40.692245
1782 13:41:40.694460 RX Vref 0 -> 0, step: 1
1783 13:41:40.694961
1784 13:41:40.697916 RX Delay -130 -> 252, step: 16
1785 13:41:40.701431 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1786 13:41:40.704473 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1787 13:41:40.711315 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1788 13:41:40.714162 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1789 13:41:40.717895 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1790 13:41:40.721679 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1791 13:41:40.724583 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1792 13:41:40.728048 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1793 13:41:40.734460 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1794 13:41:40.737766 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1795 13:41:40.741360 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1796 13:41:40.744425 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1797 13:41:40.751269 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1798 13:41:40.754256 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1799 13:41:40.757497 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1800 13:41:40.760954 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1801 13:41:40.761599 ==
1802 13:41:40.764506 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 13:41:40.767497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 13:41:40.771009 ==
1805 13:41:40.771461 DQS Delay:
1806 13:41:40.771984 DQS0 = 0, DQS1 = 0
1807 13:41:40.774501 DQM Delay:
1808 13:41:40.774951 DQM0 = 81, DQM1 = 70
1809 13:41:40.777398 DQ Delay:
1810 13:41:40.781105 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1811 13:41:40.781602 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1812 13:41:40.784171 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1813 13:41:40.787961 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1814 13:41:40.788510
1815 13:41:40.791278
1816 13:41:40.791725 ==
1817 13:41:40.794199 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 13:41:40.797706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1819 13:41:40.798159 ==
1820 13:41:40.798515
1821 13:41:40.798844
1822 13:41:40.800959 TX Vref Scan disable
1823 13:41:40.801550 == TX Byte 0 ==
1824 13:41:40.807900 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1825 13:41:40.811288 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1826 13:41:40.811847 == TX Byte 1 ==
1827 13:41:40.817392 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1828 13:41:40.820774 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1829 13:41:40.821222 ==
1830 13:41:40.824360 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 13:41:40.827522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1832 13:41:40.827977 ==
1833 13:41:40.840836 TX Vref=22, minBit 8, minWin=27, winSum=447
1834 13:41:40.844454 TX Vref=24, minBit 13, minWin=27, winSum=452
1835 13:41:40.847940 TX Vref=26, minBit 8, minWin=27, winSum=453
1836 13:41:40.850605 TX Vref=28, minBit 8, minWin=27, winSum=454
1837 13:41:40.854258 TX Vref=30, minBit 9, minWin=27, winSum=454
1838 13:41:40.860792 TX Vref=32, minBit 9, minWin=27, winSum=452
1839 13:41:40.864462 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 28
1840 13:41:40.865115
1841 13:41:40.867673 Final TX Range 1 Vref 28
1842 13:41:40.868221
1843 13:41:40.868587 ==
1844 13:41:40.870916 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 13:41:40.873917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1846 13:41:40.874377 ==
1847 13:41:40.877103
1848 13:41:40.877595
1849 13:41:40.877956 TX Vref Scan disable
1850 13:41:40.881034 == TX Byte 0 ==
1851 13:41:40.884169 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1852 13:41:40.887933 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1853 13:41:40.890632 == TX Byte 1 ==
1854 13:41:40.894365 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1855 13:41:40.901031 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1856 13:41:40.901697
1857 13:41:40.902074 [DATLAT]
1858 13:41:40.902416 Freq=800, CH1 RK1
1859 13:41:40.902741
1860 13:41:40.904522 DATLAT Default: 0x9
1861 13:41:40.905069 0, 0xFFFF, sum = 0
1862 13:41:40.907583 1, 0xFFFF, sum = 0
1863 13:41:40.908145 2, 0xFFFF, sum = 0
1864 13:41:40.911236 3, 0xFFFF, sum = 0
1865 13:41:40.911799 4, 0xFFFF, sum = 0
1866 13:41:40.914192 5, 0xFFFF, sum = 0
1867 13:41:40.917883 6, 0xFFFF, sum = 0
1868 13:41:40.918617 7, 0xFFFF, sum = 0
1869 13:41:40.920780 8, 0x0, sum = 1
1870 13:41:40.921360 9, 0x0, sum = 2
1871 13:41:40.921793 10, 0x0, sum = 3
1872 13:41:40.924321 11, 0x0, sum = 4
1873 13:41:40.924879 best_step = 9
1874 13:41:40.925240
1875 13:41:40.925639 ==
1876 13:41:40.927502 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 13:41:40.934251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1878 13:41:40.934804 ==
1879 13:41:40.935173 RX Vref Scan: 0
1880 13:41:40.935510
1881 13:41:40.936959 RX Vref 0 -> 0, step: 1
1882 13:41:40.937445
1883 13:41:40.940681 RX Delay -111 -> 252, step: 8
1884 13:41:40.943694 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1885 13:41:40.947180 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1886 13:41:40.954156 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1887 13:41:40.957063 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1888 13:41:40.960499 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1889 13:41:40.963561 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1890 13:41:40.967264 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1891 13:41:40.973713 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1892 13:41:40.976930 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1893 13:41:40.980185 iDelay=217, Bit 9, Center 60 (-63 ~ 184) 248
1894 13:41:40.983605 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1895 13:41:40.986845 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1896 13:41:40.993474 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1897 13:41:40.996886 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1898 13:41:41.000443 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1899 13:41:41.003508 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1900 13:41:41.003964 ==
1901 13:41:41.007035 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 13:41:41.013602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1903 13:41:41.014314 ==
1904 13:41:41.014911 DQS Delay:
1905 13:41:41.016983 DQS0 = 0, DQS1 = 0
1906 13:41:41.017633 DQM Delay:
1907 13:41:41.018049 DQM0 = 82, DQM1 = 72
1908 13:41:41.020642 DQ Delay:
1909 13:41:41.023605 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1910 13:41:41.026987 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1911 13:41:41.029756 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1912 13:41:41.033286 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1913 13:41:41.033387
1914 13:41:41.033503
1915 13:41:41.039929 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1916 13:41:41.043456 CH1 RK1: MR19=606, MR18=3F3F
1917 13:41:41.049555 CH1_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1918 13:41:41.053107 [RxdqsGatingPostProcess] freq 800
1919 13:41:41.056448 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1920 13:41:41.059691 Pre-setting of DQS Precalculation
1921 13:41:41.066595 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1922 13:41:41.073228 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1923 13:41:41.080183 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1924 13:41:41.080278
1925 13:41:41.080341
1926 13:41:41.083153 [Calibration Summary] 1600 Mbps
1927 13:41:41.083232 CH 0, Rank 0
1928 13:41:41.086544 SW Impedance : PASS
1929 13:41:41.090028 DUTY Scan : NO K
1930 13:41:41.090110 ZQ Calibration : PASS
1931 13:41:41.093067 Jitter Meter : NO K
1932 13:41:41.093146 CBT Training : PASS
1933 13:41:41.096439 Write leveling : PASS
1934 13:41:41.099707 RX DQS gating : PASS
1935 13:41:41.099787 RX DQ/DQS(RDDQC) : PASS
1936 13:41:41.103347 TX DQ/DQS : PASS
1937 13:41:41.106592 RX DATLAT : PASS
1938 13:41:41.106671 RX DQ/DQS(Engine): PASS
1939 13:41:41.109916 TX OE : NO K
1940 13:41:41.109995 All Pass.
1941 13:41:41.110057
1942 13:41:41.113540 CH 0, Rank 1
1943 13:41:41.113620 SW Impedance : PASS
1944 13:41:41.116553 DUTY Scan : NO K
1945 13:41:41.120100 ZQ Calibration : PASS
1946 13:41:41.120180 Jitter Meter : NO K
1947 13:41:41.123047 CBT Training : PASS
1948 13:41:41.126695 Write leveling : PASS
1949 13:41:41.126774 RX DQS gating : PASS
1950 13:41:41.129643 RX DQ/DQS(RDDQC) : PASS
1951 13:41:41.133206 TX DQ/DQS : PASS
1952 13:41:41.133286 RX DATLAT : PASS
1953 13:41:41.137095 RX DQ/DQS(Engine): PASS
1954 13:41:41.137174 TX OE : NO K
1955 13:41:41.140065 All Pass.
1956 13:41:41.140161
1957 13:41:41.140237 CH 1, Rank 0
1958 13:41:41.143024 SW Impedance : PASS
1959 13:41:41.143146 DUTY Scan : NO K
1960 13:41:41.146466 ZQ Calibration : PASS
1961 13:41:41.149495 Jitter Meter : NO K
1962 13:41:41.149575 CBT Training : PASS
1963 13:41:41.153046 Write leveling : PASS
1964 13:41:41.156608 RX DQS gating : PASS
1965 13:41:41.156687 RX DQ/DQS(RDDQC) : PASS
1966 13:41:41.159641 TX DQ/DQS : PASS
1967 13:41:41.163165 RX DATLAT : PASS
1968 13:41:41.163244 RX DQ/DQS(Engine): PASS
1969 13:41:41.166535 TX OE : NO K
1970 13:41:41.166641 All Pass.
1971 13:41:41.166744
1972 13:41:41.169566 CH 1, Rank 1
1973 13:41:41.169655 SW Impedance : PASS
1974 13:41:41.173074 DUTY Scan : NO K
1975 13:41:41.176258 ZQ Calibration : PASS
1976 13:41:41.176346 Jitter Meter : NO K
1977 13:41:41.179607 CBT Training : PASS
1978 13:41:41.182838 Write leveling : PASS
1979 13:41:41.182917 RX DQS gating : PASS
1980 13:41:41.186214 RX DQ/DQS(RDDQC) : PASS
1981 13:41:41.186291 TX DQ/DQS : PASS
1982 13:41:41.189486 RX DATLAT : PASS
1983 13:41:41.192864 RX DQ/DQS(Engine): PASS
1984 13:41:41.192956 TX OE : NO K
1985 13:41:41.196423 All Pass.
1986 13:41:41.196512
1987 13:41:41.196592 DramC Write-DBI off
1988 13:41:41.199384 PER_BANK_REFRESH: Hybrid Mode
1989 13:41:41.203067 TX_TRACKING: ON
1990 13:41:41.206463 [GetDramInforAfterCalByMRR] Vendor 6.
1991 13:41:41.209790 [GetDramInforAfterCalByMRR] Revision 606.
1992 13:41:41.213140 [GetDramInforAfterCalByMRR] Revision 2 0.
1993 13:41:41.213217 MR0 0x3939
1994 13:41:41.213362 MR8 0x1111
1995 13:41:41.219566 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1996 13:41:41.219656
1997 13:41:41.219738 MR0 0x3939
1998 13:41:41.219829 MR8 0x1111
1999 13:41:41.223221 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2000 13:41:41.223298
2001 13:41:41.232856 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2002 13:41:41.236428 [FAST_K] Save calibration result to emmc
2003 13:41:41.239890 [FAST_K] Save calibration result to emmc
2004 13:41:41.242780 dram_init: config_dvfs: 1
2005 13:41:41.246237 dramc_set_vcore_voltage set vcore to 662500
2006 13:41:41.249887 Read voltage for 1200, 2
2007 13:41:41.249965 Vio18 = 0
2008 13:41:41.250059 Vcore = 662500
2009 13:41:41.253018 Vdram = 0
2010 13:41:41.253098 Vddq = 0
2011 13:41:41.253161 Vmddr = 0
2012 13:41:41.259599 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2013 13:41:41.263203 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2014 13:41:41.266145 MEM_TYPE=3, freq_sel=15
2015 13:41:41.269770 sv_algorithm_assistance_LP4_1600
2016 13:41:41.272777 ============ PULL DRAM RESETB DOWN ============
2017 13:41:41.276455 ========== PULL DRAM RESETB DOWN end =========
2018 13:41:41.283269 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2019 13:41:41.286542 ===================================
2020 13:41:41.286621 LPDDR4 DRAM CONFIGURATION
2021 13:41:41.289614 ===================================
2022 13:41:41.293148 EX_ROW_EN[0] = 0x0
2023 13:41:41.296129 EX_ROW_EN[1] = 0x0
2024 13:41:41.296234 LP4Y_EN = 0x0
2025 13:41:41.299816 WORK_FSP = 0x0
2026 13:41:41.299909 WL = 0x4
2027 13:41:41.302790 RL = 0x4
2028 13:41:41.302870 BL = 0x2
2029 13:41:41.306638 RPST = 0x0
2030 13:41:41.306718 RD_PRE = 0x0
2031 13:41:41.309781 WR_PRE = 0x1
2032 13:41:41.309860 WR_PST = 0x0
2033 13:41:41.313243 DBI_WR = 0x0
2034 13:41:41.313375 DBI_RD = 0x0
2035 13:41:41.316194 OTF = 0x1
2036 13:41:41.319642 ===================================
2037 13:41:41.323141 ===================================
2038 13:41:41.323234 ANA top config
2039 13:41:41.326107 ===================================
2040 13:41:41.329801 DLL_ASYNC_EN = 0
2041 13:41:41.332645 ALL_SLAVE_EN = 0
2042 13:41:41.336109 NEW_RANK_MODE = 1
2043 13:41:41.336191 DLL_IDLE_MODE = 1
2044 13:41:41.339661 LP45_APHY_COMB_EN = 1
2045 13:41:41.342671 TX_ODT_DIS = 1
2046 13:41:41.346184 NEW_8X_MODE = 1
2047 13:41:41.349801 ===================================
2048 13:41:41.352553 ===================================
2049 13:41:41.356155 data_rate = 2400
2050 13:41:41.356230 CKR = 1
2051 13:41:41.359727 DQ_P2S_RATIO = 8
2052 13:41:41.362686 ===================================
2053 13:41:41.366197 CA_P2S_RATIO = 8
2054 13:41:41.369186 DQ_CA_OPEN = 0
2055 13:41:41.372829 DQ_SEMI_OPEN = 0
2056 13:41:41.372916 CA_SEMI_OPEN = 0
2057 13:41:41.376377 CA_FULL_RATE = 0
2058 13:41:41.379406 DQ_CKDIV4_EN = 0
2059 13:41:41.382983 CA_CKDIV4_EN = 0
2060 13:41:41.386402 CA_PREDIV_EN = 0
2061 13:41:41.389440 PH8_DLY = 17
2062 13:41:41.389525 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2063 13:41:41.392976 DQ_AAMCK_DIV = 4
2064 13:41:41.396082 CA_AAMCK_DIV = 4
2065 13:41:41.399649 CA_ADMCK_DIV = 4
2066 13:41:41.402497 DQ_TRACK_CA_EN = 0
2067 13:41:41.406300 CA_PICK = 1200
2068 13:41:41.409285 CA_MCKIO = 1200
2069 13:41:41.409373 MCKIO_SEMI = 0
2070 13:41:41.412823 PLL_FREQ = 2366
2071 13:41:41.416042 DQ_UI_PI_RATIO = 32
2072 13:41:41.419616 CA_UI_PI_RATIO = 0
2073 13:41:41.422579 ===================================
2074 13:41:41.426263 ===================================
2075 13:41:41.429207 memory_type:LPDDR4
2076 13:41:41.429351 GP_NUM : 10
2077 13:41:41.432778 SRAM_EN : 1
2078 13:41:41.435841 MD32_EN : 0
2079 13:41:41.439455 ===================================
2080 13:41:41.439550 [ANA_INIT] >>>>>>>>>>>>>>
2081 13:41:41.442779 <<<<<< [CONFIGURE PHASE]: ANA_TX
2082 13:41:41.446093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2083 13:41:41.449533 ===================================
2084 13:41:41.452460 data_rate = 2400,PCW = 0X5b00
2085 13:41:41.455973 ===================================
2086 13:41:41.459452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2087 13:41:41.465971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2088 13:41:41.469123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2089 13:41:41.476188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2090 13:41:41.479105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2091 13:41:41.482846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2092 13:41:41.482943 [ANA_INIT] flow start
2093 13:41:41.485771 [ANA_INIT] PLL >>>>>>>>
2094 13:41:41.489443 [ANA_INIT] PLL <<<<<<<<
2095 13:41:41.489549 [ANA_INIT] MIDPI >>>>>>>>
2096 13:41:41.492686 [ANA_INIT] MIDPI <<<<<<<<
2097 13:41:41.495789 [ANA_INIT] DLL >>>>>>>>
2098 13:41:41.499343 [ANA_INIT] DLL <<<<<<<<
2099 13:41:41.499466 [ANA_INIT] flow end
2100 13:41:41.502812 ============ LP4 DIFF to SE enter ============
2101 13:41:41.509509 ============ LP4 DIFF to SE exit ============
2102 13:41:41.509670 [ANA_INIT] <<<<<<<<<<<<<
2103 13:41:41.512344 [Flow] Enable top DCM control >>>>>
2104 13:41:41.515842 [Flow] Enable top DCM control <<<<<
2105 13:41:41.519304 Enable DLL master slave shuffle
2106 13:41:41.526029 ==============================================================
2107 13:41:41.526195 Gating Mode config
2108 13:41:41.532627 ==============================================================
2109 13:41:41.536075 Config description:
2110 13:41:41.542648 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2111 13:41:41.549441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2112 13:41:41.556270 SELPH_MODE 0: By rank 1: By Phase
2113 13:41:41.562681 ==============================================================
2114 13:41:41.562816 GAT_TRACK_EN = 1
2115 13:41:41.566019 RX_GATING_MODE = 2
2116 13:41:41.569427 RX_GATING_TRACK_MODE = 2
2117 13:41:41.572421 SELPH_MODE = 1
2118 13:41:41.576029 PICG_EARLY_EN = 1
2119 13:41:41.579011 VALID_LAT_VALUE = 1
2120 13:41:41.586162 ==============================================================
2121 13:41:41.588993 Enter into Gating configuration >>>>
2122 13:41:41.592447 Exit from Gating configuration <<<<
2123 13:41:41.595928 Enter into DVFS_PRE_config >>>>>
2124 13:41:41.605643 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2125 13:41:41.609275 Exit from DVFS_PRE_config <<<<<
2126 13:41:41.612347 Enter into PICG configuration >>>>
2127 13:41:41.615804 Exit from PICG configuration <<<<
2128 13:41:41.619394 [RX_INPUT] configuration >>>>>
2129 13:41:41.619492 [RX_INPUT] configuration <<<<<
2130 13:41:41.626108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2131 13:41:41.632474 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2132 13:41:41.635870 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2133 13:41:41.642510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2134 13:41:41.649015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2135 13:41:41.656231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2136 13:41:41.659532 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2137 13:41:41.663007 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2138 13:41:41.669314 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2139 13:41:41.672770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2140 13:41:41.675742 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2141 13:41:41.679329 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 13:41:41.682652 ===================================
2143 13:41:41.686152 LPDDR4 DRAM CONFIGURATION
2144 13:41:41.689855 ===================================
2145 13:41:41.692697 EX_ROW_EN[0] = 0x0
2146 13:41:41.692895 EX_ROW_EN[1] = 0x0
2147 13:41:41.696128 LP4Y_EN = 0x0
2148 13:41:41.696290 WORK_FSP = 0x0
2149 13:41:41.699641 WL = 0x4
2150 13:41:41.699854 RL = 0x4
2151 13:41:41.702611 BL = 0x2
2152 13:41:41.702843 RPST = 0x0
2153 13:41:41.705983 RD_PRE = 0x0
2154 13:41:41.706211 WR_PRE = 0x1
2155 13:41:41.709744 WR_PST = 0x0
2156 13:41:41.712776 DBI_WR = 0x0
2157 13:41:41.713065 DBI_RD = 0x0
2158 13:41:41.716238 OTF = 0x1
2159 13:41:41.719728 ===================================
2160 13:41:41.722569 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2161 13:41:41.726060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2162 13:41:41.729724 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2163 13:41:41.733214 ===================================
2164 13:41:41.736842 LPDDR4 DRAM CONFIGURATION
2165 13:41:41.739792 ===================================
2166 13:41:41.743241 EX_ROW_EN[0] = 0x10
2167 13:41:41.743799 EX_ROW_EN[1] = 0x0
2168 13:41:41.746341 LP4Y_EN = 0x0
2169 13:41:41.746818 WORK_FSP = 0x0
2170 13:41:41.749683 WL = 0x4
2171 13:41:41.750243 RL = 0x4
2172 13:41:41.752552 BL = 0x2
2173 13:41:41.753013 RPST = 0x0
2174 13:41:41.756122 RD_PRE = 0x0
2175 13:41:41.756690 WR_PRE = 0x1
2176 13:41:41.759768 WR_PST = 0x0
2177 13:41:41.760244 DBI_WR = 0x0
2178 13:41:41.762602 DBI_RD = 0x0
2179 13:41:41.763078 OTF = 0x1
2180 13:41:41.766353 ===================================
2181 13:41:41.772669 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2182 13:41:41.773149 ==
2183 13:41:41.776066 Dram Type= 6, Freq= 0, CH_0, rank 0
2184 13:41:41.782786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2185 13:41:41.783266 ==
2186 13:41:41.783743 [Duty_Offset_Calibration]
2187 13:41:41.786109 B0:0 B1:2 CA:1
2188 13:41:41.786582
2189 13:41:41.789497 [DutyScan_Calibration_Flow] k_type=0
2190 13:41:41.798296
2191 13:41:41.798931 ==CLK 0==
2192 13:41:41.801699 Final CLK duty delay cell = 0
2193 13:41:41.805274 [0] MAX Duty = 5093%(X100), DQS PI = 12
2194 13:41:41.808118 [0] MIN Duty = 4938%(X100), DQS PI = 54
2195 13:41:41.808696 [0] AVG Duty = 5015%(X100)
2196 13:41:41.811461
2197 13:41:41.815010 CH0 CLK Duty spec in!! Max-Min= 155%
2198 13:41:41.818130 [DutyScan_Calibration_Flow] ====Done====
2199 13:41:41.818591
2200 13:41:41.821743 [DutyScan_Calibration_Flow] k_type=1
2201 13:41:41.837278
2202 13:41:41.837921 ==DQS 0 ==
2203 13:41:41.841206 Final DQS duty delay cell = 0
2204 13:41:41.844097 [0] MAX Duty = 5125%(X100), DQS PI = 30
2205 13:41:41.847607 [0] MIN Duty = 5031%(X100), DQS PI = 6
2206 13:41:41.848096 [0] AVG Duty = 5078%(X100)
2207 13:41:41.850872
2208 13:41:41.851447 ==DQS 1 ==
2209 13:41:41.854229 Final DQS duty delay cell = 0
2210 13:41:41.857764 [0] MAX Duty = 5062%(X100), DQS PI = 56
2211 13:41:41.860882 [0] MIN Duty = 4906%(X100), DQS PI = 14
2212 13:41:41.864655 [0] AVG Duty = 4984%(X100)
2213 13:41:41.865212
2214 13:41:41.867715 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2215 13:41:41.868168
2216 13:41:41.871110 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2217 13:41:41.874196 [DutyScan_Calibration_Flow] ====Done====
2218 13:41:41.874653
2219 13:41:41.877601 [DutyScan_Calibration_Flow] k_type=3
2220 13:41:41.894020
2221 13:41:41.894570 ==DQM 0 ==
2222 13:41:41.897181 Final DQM duty delay cell = 0
2223 13:41:41.900816 [0] MAX Duty = 5187%(X100), DQS PI = 22
2224 13:41:41.903951 [0] MIN Duty = 4969%(X100), DQS PI = 40
2225 13:41:41.907284 [0] AVG Duty = 5078%(X100)
2226 13:41:41.907739
2227 13:41:41.908096 ==DQM 1 ==
2228 13:41:41.910175 Final DQM duty delay cell = 0
2229 13:41:41.914014 [0] MAX Duty = 5000%(X100), DQS PI = 56
2230 13:41:41.917386 [0] MIN Duty = 4844%(X100), DQS PI = 0
2231 13:41:41.920505 [0] AVG Duty = 4922%(X100)
2232 13:41:41.921049
2233 13:41:41.924137 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2234 13:41:41.924683
2235 13:41:41.927107 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2236 13:41:41.930644 [DutyScan_Calibration_Flow] ====Done====
2237 13:41:41.931192
2238 13:41:41.934251 [DutyScan_Calibration_Flow] k_type=2
2239 13:41:41.948709
2240 13:41:41.949255 ==DQ 0 ==
2241 13:41:41.952419 Final DQ duty delay cell = -4
2242 13:41:41.955935 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2243 13:41:41.958981 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2244 13:41:41.962465 [-4] AVG Duty = 4937%(X100)
2245 13:41:41.963017
2246 13:41:41.963381 ==DQ 1 ==
2247 13:41:41.965239 Final DQ duty delay cell = -4
2248 13:41:41.968873 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2249 13:41:41.972068 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2250 13:41:41.975533 [-4] AVG Duty = 4984%(X100)
2251 13:41:41.976012
2252 13:41:41.978864 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2253 13:41:41.979336
2254 13:41:41.982473 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2255 13:41:41.985267 [DutyScan_Calibration_Flow] ====Done====
2256 13:41:41.985809 ==
2257 13:41:41.988797 Dram Type= 6, Freq= 0, CH_1, rank 0
2258 13:41:41.992232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2259 13:41:41.992872 ==
2260 13:41:41.995122 [Duty_Offset_Calibration]
2261 13:41:41.995632 B0:0 B1:5 CA:-5
2262 13:41:41.996010
2263 13:41:41.998834 [DutyScan_Calibration_Flow] k_type=0
2264 13:41:42.009378
2265 13:41:42.009959 ==CLK 0==
2266 13:41:42.012662 Final CLK duty delay cell = 0
2267 13:41:42.015961 [0] MAX Duty = 5094%(X100), DQS PI = 24
2268 13:41:42.019398 [0] MIN Duty = 4876%(X100), DQS PI = 52
2269 13:41:42.019854 [0] AVG Duty = 4985%(X100)
2270 13:41:42.022443
2271 13:41:42.026262 CH1 CLK Duty spec in!! Max-Min= 218%
2272 13:41:42.029158 [DutyScan_Calibration_Flow] ====Done====
2273 13:41:42.029749
2274 13:41:42.032769 [DutyScan_Calibration_Flow] k_type=1
2275 13:41:42.047737
2276 13:41:42.048296 ==DQS 0 ==
2277 13:41:42.051726 Final DQS duty delay cell = 0
2278 13:41:42.054662 [0] MAX Duty = 5125%(X100), DQS PI = 16
2279 13:41:42.058222 [0] MIN Duty = 4875%(X100), DQS PI = 40
2280 13:41:42.058773 [0] AVG Duty = 5000%(X100)
2281 13:41:42.061059
2282 13:41:42.061538 ==DQS 1 ==
2283 13:41:42.064630 Final DQS duty delay cell = -4
2284 13:41:42.067827 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2285 13:41:42.071050 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2286 13:41:42.074544 [-4] AVG Duty = 4953%(X100)
2287 13:41:42.075001
2288 13:41:42.077520 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2289 13:41:42.077975
2290 13:41:42.081414 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2291 13:41:42.084134 [DutyScan_Calibration_Flow] ====Done====
2292 13:41:42.084680
2293 13:41:42.087859 [DutyScan_Calibration_Flow] k_type=3
2294 13:41:42.103059
2295 13:41:42.103605 ==DQM 0 ==
2296 13:41:42.106766 Final DQM duty delay cell = -4
2297 13:41:42.109831 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2298 13:41:42.113166 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2299 13:41:42.116333 [-4] AVG Duty = 4969%(X100)
2300 13:41:42.116881
2301 13:41:42.117572 ==DQM 1 ==
2302 13:41:42.119734 Final DQM duty delay cell = -4
2303 13:41:42.122933 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2304 13:41:42.126146 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2305 13:41:42.129727 [-4] AVG Duty = 5000%(X100)
2306 13:41:42.130195
2307 13:41:42.132906 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2308 13:41:42.133406
2309 13:41:42.136421 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2310 13:41:42.139350 [DutyScan_Calibration_Flow] ====Done====
2311 13:41:42.139822
2312 13:41:42.142580 [DutyScan_Calibration_Flow] k_type=2
2313 13:41:42.159586
2314 13:41:42.159838 ==DQ 0 ==
2315 13:41:42.163098 Final DQ duty delay cell = 0
2316 13:41:42.166891 [0] MAX Duty = 5062%(X100), DQS PI = 0
2317 13:41:42.169748 [0] MIN Duty = 4969%(X100), DQS PI = 42
2318 13:41:42.170033 [0] AVG Duty = 5015%(X100)
2319 13:41:42.170227
2320 13:41:42.173314 ==DQ 1 ==
2321 13:41:42.176193 Final DQ duty delay cell = 0
2322 13:41:42.179741 [0] MAX Duty = 5031%(X100), DQS PI = 8
2323 13:41:42.182852 [0] MIN Duty = 4907%(X100), DQS PI = 0
2324 13:41:42.183077 [0] AVG Duty = 4969%(X100)
2325 13:41:42.183253
2326 13:41:42.186519 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2327 13:41:42.186898
2328 13:41:42.189875 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2329 13:41:42.196236 [DutyScan_Calibration_Flow] ====Done====
2330 13:41:42.199638 nWR fixed to 30
2331 13:41:42.199993 [ModeRegInit_LP4] CH0 RK0
2332 13:41:42.203015 [ModeRegInit_LP4] CH0 RK1
2333 13:41:42.206233 [ModeRegInit_LP4] CH1 RK0
2334 13:41:42.206583 [ModeRegInit_LP4] CH1 RK1
2335 13:41:42.209701 match AC timing 6
2336 13:41:42.213075 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2337 13:41:42.216575 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2338 13:41:42.222578 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2339 13:41:42.226074 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2340 13:41:42.233142 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2341 13:41:42.233647 ==
2342 13:41:42.236313 Dram Type= 6, Freq= 0, CH_0, rank 0
2343 13:41:42.240013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2344 13:41:42.240579 ==
2345 13:41:42.246490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2346 13:41:42.252712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2347 13:41:42.259532 [CA 0] Center 39 (9~70) winsize 62
2348 13:41:42.262885 [CA 1] Center 39 (8~70) winsize 63
2349 13:41:42.266010 [CA 2] Center 36 (5~67) winsize 63
2350 13:41:42.270550 [CA 3] Center 35 (5~66) winsize 62
2351 13:41:42.272665 [CA 4] Center 34 (3~65) winsize 63
2352 13:41:42.276168 [CA 5] Center 33 (3~64) winsize 62
2353 13:41:42.276799
2354 13:41:42.279225 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2355 13:41:42.279675
2356 13:41:42.282883 [CATrainingPosCal] consider 1 rank data
2357 13:41:42.285813 u2DelayCellTimex100 = 270/100 ps
2358 13:41:42.289119 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2359 13:41:42.292605 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2360 13:41:42.299220 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2361 13:41:42.302229 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2362 13:41:42.305756 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2363 13:41:42.308874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2364 13:41:42.309114
2365 13:41:42.312307 CA PerBit enable=1, Macro0, CA PI delay=33
2366 13:41:42.312566
2367 13:41:42.315574 [CBTSetCACLKResult] CA Dly = 33
2368 13:41:42.315815 CS Dly: 7 (0~38)
2369 13:41:42.319229 ==
2370 13:41:42.319487 Dram Type= 6, Freq= 0, CH_0, rank 1
2371 13:41:42.325350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2372 13:41:42.325604 ==
2373 13:41:42.328759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2374 13:41:42.335571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2375 13:41:42.344617 [CA 0] Center 39 (8~70) winsize 63
2376 13:41:42.348311 [CA 1] Center 39 (8~70) winsize 63
2377 13:41:42.351474 [CA 2] Center 36 (5~67) winsize 63
2378 13:41:42.354644 [CA 3] Center 35 (4~66) winsize 63
2379 13:41:42.357834 [CA 4] Center 33 (3~64) winsize 62
2380 13:41:42.361420 [CA 5] Center 34 (3~65) winsize 63
2381 13:41:42.361501
2382 13:41:42.364570 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2383 13:41:42.364647
2384 13:41:42.367974 [CATrainingPosCal] consider 2 rank data
2385 13:41:42.371529 u2DelayCellTimex100 = 270/100 ps
2386 13:41:42.374586 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2387 13:41:42.378135 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2388 13:41:42.384717 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2389 13:41:42.387714 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2390 13:41:42.391160 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2391 13:41:42.394137 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2392 13:41:42.394219
2393 13:41:42.397718 CA PerBit enable=1, Macro0, CA PI delay=33
2394 13:41:42.397827
2395 13:41:42.401219 [CBTSetCACLKResult] CA Dly = 33
2396 13:41:42.401310 CS Dly: 7 (0~39)
2397 13:41:42.401376
2398 13:41:42.404215 ----->DramcWriteLeveling(PI) begin...
2399 13:41:42.407838 ==
2400 13:41:42.410764 Dram Type= 6, Freq= 0, CH_0, rank 0
2401 13:41:42.414314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2402 13:41:42.414396 ==
2403 13:41:42.417337 Write leveling (Byte 0): 30 => 30
2404 13:41:42.420879 Write leveling (Byte 1): 26 => 26
2405 13:41:42.424415 DramcWriteLeveling(PI) end<-----
2406 13:41:42.424496
2407 13:41:42.424560 ==
2408 13:41:42.427778 Dram Type= 6, Freq= 0, CH_0, rank 0
2409 13:41:42.431070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2410 13:41:42.431156 ==
2411 13:41:42.434171 [Gating] SW mode calibration
2412 13:41:42.440607 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2413 13:41:42.447543 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2414 13:41:42.451127 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2415 13:41:42.454313 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2416 13:41:42.460796 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2417 13:41:42.464228 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2418 13:41:42.467554 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2419 13:41:42.470662 0 11 20 | B1->B0 | 2e2e 2929 | 1 1 | (0 1) (1 0)
2420 13:41:42.477424 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2421 13:41:42.481122 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2422 13:41:42.484194 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2423 13:41:42.490657 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2424 13:41:42.494131 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2425 13:41:42.497097 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2426 13:41:42.503779 0 12 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2427 13:41:42.507450 0 12 20 | B1->B0 | 3737 3d3d | 1 0 | (0 0) (0 0)
2428 13:41:42.510488 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2429 13:41:42.517585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2430 13:41:42.520633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2431 13:41:42.524145 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2432 13:41:42.530841 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2433 13:41:42.534271 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2434 13:41:42.537282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2435 13:41:42.544130 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2436 13:41:42.547175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2437 13:41:42.550436 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2438 13:41:42.557179 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2439 13:41:42.560681 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2440 13:41:42.564018 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2441 13:41:42.570613 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2442 13:41:42.573823 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2443 13:41:42.577205 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2444 13:41:42.583691 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2445 13:41:42.587107 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2446 13:41:42.590749 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2447 13:41:42.593798 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2448 13:41:42.600433 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2449 13:41:42.603886 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2450 13:41:42.607466 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2451 13:41:42.614021 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2452 13:41:42.617080 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2453 13:41:42.620632 Total UI for P1: 0, mck2ui 16
2454 13:41:42.624200 best dqsien dly found for B0: ( 0, 15, 18)
2455 13:41:42.627163 Total UI for P1: 0, mck2ui 16
2456 13:41:42.630754 best dqsien dly found for B1: ( 0, 15, 18)
2457 13:41:42.633750 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2458 13:41:42.637208 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2459 13:41:42.637303
2460 13:41:42.640845 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2461 13:41:42.643768 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2462 13:41:42.647347 [Gating] SW calibration Done
2463 13:41:42.647427 ==
2464 13:41:42.650176 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 13:41:42.656959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2466 13:41:42.657056 ==
2467 13:41:42.657135 RX Vref Scan: 0
2468 13:41:42.657194
2469 13:41:42.660612 RX Vref 0 -> 0, step: 1
2470 13:41:42.660691
2471 13:41:42.663958 RX Delay -40 -> 252, step: 8
2472 13:41:42.667326 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2473 13:41:42.670511 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2474 13:41:42.673926 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2475 13:41:42.676808 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2476 13:41:42.683728 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2477 13:41:42.687060 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2478 13:41:42.690420 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2479 13:41:42.693587 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2480 13:41:42.696858 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2481 13:41:42.703458 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2482 13:41:42.707037 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2483 13:41:42.710022 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2484 13:41:42.713713 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2485 13:41:42.716681 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2486 13:41:42.723312 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2487 13:41:42.726972 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2488 13:41:42.727053 ==
2489 13:41:42.730502 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 13:41:42.733611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2491 13:41:42.733693 ==
2492 13:41:42.737172 DQS Delay:
2493 13:41:42.737252 DQS0 = 0, DQS1 = 0
2494 13:41:42.737353 DQM Delay:
2495 13:41:42.740019 DQM0 = 115, DQM1 = 106
2496 13:41:42.740109 DQ Delay:
2497 13:41:42.743586 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2498 13:41:42.746606 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2499 13:41:42.750168 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2500 13:41:42.756683 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2501 13:41:42.756791
2502 13:41:42.756887
2503 13:41:42.756958 ==
2504 13:41:42.760160 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 13:41:42.763245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2506 13:41:42.763341 ==
2507 13:41:42.763455
2508 13:41:42.763596
2509 13:41:42.766722 TX Vref Scan disable
2510 13:41:42.766809 == TX Byte 0 ==
2511 13:41:42.773649 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2512 13:41:42.777054 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2513 13:41:42.777130 == TX Byte 1 ==
2514 13:41:42.783313 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2515 13:41:42.786863 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2516 13:41:42.786970 ==
2517 13:41:42.790311 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 13:41:42.793762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2519 13:41:42.793861 ==
2520 13:41:42.806489 TX Vref=22, minBit 12, minWin=24, winSum=410
2521 13:41:42.809621 TX Vref=24, minBit 1, minWin=25, winSum=412
2522 13:41:42.812972 TX Vref=26, minBit 4, minWin=26, winSum=424
2523 13:41:42.816301 TX Vref=28, minBit 1, minWin=26, winSum=426
2524 13:41:42.819902 TX Vref=30, minBit 0, minWin=26, winSum=428
2525 13:41:42.822881 TX Vref=32, minBit 0, minWin=26, winSum=425
2526 13:41:42.829452 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2527 13:41:42.829540
2528 13:41:42.833308 Final TX Range 1 Vref 30
2529 13:41:42.833471
2530 13:41:42.833547 ==
2531 13:41:42.836703 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 13:41:42.840093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 13:41:42.840195 ==
2534 13:41:42.840289
2535 13:41:42.840358
2536 13:41:42.843114 TX Vref Scan disable
2537 13:41:42.846616 == TX Byte 0 ==
2538 13:41:42.849550 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2539 13:41:42.853386 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2540 13:41:42.856382 == TX Byte 1 ==
2541 13:41:42.859632 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2542 13:41:42.862776 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2543 13:41:42.862867
2544 13:41:42.866446 [DATLAT]
2545 13:41:42.866547 Freq=1200, CH0 RK0
2546 13:41:42.866621
2547 13:41:42.869823 DATLAT Default: 0xd
2548 13:41:42.869916 0, 0xFFFF, sum = 0
2549 13:41:42.872986 1, 0xFFFF, sum = 0
2550 13:41:42.873089 2, 0xFFFF, sum = 0
2551 13:41:42.876352 3, 0xFFFF, sum = 0
2552 13:41:42.876495 4, 0xFFFF, sum = 0
2553 13:41:42.879181 5, 0xFFFF, sum = 0
2554 13:41:42.882635 6, 0xFFFF, sum = 0
2555 13:41:42.882776 7, 0xFFFF, sum = 0
2556 13:41:42.886011 8, 0xFFFF, sum = 0
2557 13:41:42.886161 9, 0xFFFF, sum = 0
2558 13:41:42.889483 10, 0xFFFF, sum = 0
2559 13:41:42.889634 11, 0x0, sum = 1
2560 13:41:42.892443 12, 0x0, sum = 2
2561 13:41:42.892594 13, 0x0, sum = 3
2562 13:41:42.892741 14, 0x0, sum = 4
2563 13:41:42.896045 best_step = 12
2564 13:41:42.896199
2565 13:41:42.896314 ==
2566 13:41:42.899209 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 13:41:42.902742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2568 13:41:42.903004 ==
2569 13:41:42.906252 RX Vref Scan: 1
2570 13:41:42.906463
2571 13:41:42.909351 Set Vref Range= 32 -> 127
2572 13:41:42.909643
2573 13:41:42.909858 RX Vref 32 -> 127, step: 1
2574 13:41:42.910069
2575 13:41:42.912940 RX Delay -21 -> 252, step: 4
2576 13:41:42.913451
2577 13:41:42.916295 Set Vref, RX VrefLevel [Byte0]: 32
2578 13:41:42.919625 [Byte1]: 32
2579 13:41:42.923088
2580 13:41:42.923624 Set Vref, RX VrefLevel [Byte0]: 33
2581 13:41:42.926670 [Byte1]: 33
2582 13:41:42.930730
2583 13:41:42.931231 Set Vref, RX VrefLevel [Byte0]: 34
2584 13:41:42.934401 [Byte1]: 34
2585 13:41:42.939140
2586 13:41:42.939621 Set Vref, RX VrefLevel [Byte0]: 35
2587 13:41:42.941978 [Byte1]: 35
2588 13:41:42.946795
2589 13:41:42.947170 Set Vref, RX VrefLevel [Byte0]: 36
2590 13:41:42.950255 [Byte1]: 36
2591 13:41:42.955172
2592 13:41:42.955869 Set Vref, RX VrefLevel [Byte0]: 37
2593 13:41:42.958101 [Byte1]: 37
2594 13:41:42.962926
2595 13:41:42.963534 Set Vref, RX VrefLevel [Byte0]: 38
2596 13:41:42.965803 [Byte1]: 38
2597 13:41:42.970439
2598 13:41:42.971196 Set Vref, RX VrefLevel [Byte0]: 39
2599 13:41:42.974072 [Byte1]: 39
2600 13:41:42.978546
2601 13:41:42.979334 Set Vref, RX VrefLevel [Byte0]: 40
2602 13:41:42.981652 [Byte1]: 40
2603 13:41:42.986883
2604 13:41:42.987704 Set Vref, RX VrefLevel [Byte0]: 41
2605 13:41:42.989785 [Byte1]: 41
2606 13:41:42.994329
2607 13:41:42.994441 Set Vref, RX VrefLevel [Byte0]: 42
2608 13:41:42.997118 [Byte1]: 42
2609 13:41:43.002043
2610 13:41:43.002122 Set Vref, RX VrefLevel [Byte0]: 43
2611 13:41:43.005694 [Byte1]: 43
2612 13:41:43.009731
2613 13:41:43.009825 Set Vref, RX VrefLevel [Byte0]: 44
2614 13:41:43.013386 [Byte1]: 44
2615 13:41:43.018126
2616 13:41:43.018212 Set Vref, RX VrefLevel [Byte0]: 45
2617 13:41:43.021004 [Byte1]: 45
2618 13:41:43.025882
2619 13:41:43.025963 Set Vref, RX VrefLevel [Byte0]: 46
2620 13:41:43.028926 [Byte1]: 46
2621 13:41:43.033530
2622 13:41:43.033607 Set Vref, RX VrefLevel [Byte0]: 47
2623 13:41:43.037117 [Byte1]: 47
2624 13:41:43.041776
2625 13:41:43.041848 Set Vref, RX VrefLevel [Byte0]: 48
2626 13:41:43.044744 [Byte1]: 48
2627 13:41:43.049539
2628 13:41:43.049614 Set Vref, RX VrefLevel [Byte0]: 49
2629 13:41:43.052976 [Byte1]: 49
2630 13:41:43.057222
2631 13:41:43.057329 Set Vref, RX VrefLevel [Byte0]: 50
2632 13:41:43.060839 [Byte1]: 50
2633 13:41:43.065682
2634 13:41:43.065757 Set Vref, RX VrefLevel [Byte0]: 51
2635 13:41:43.068754 [Byte1]: 51
2636 13:41:43.073486
2637 13:41:43.073578 Set Vref, RX VrefLevel [Byte0]: 52
2638 13:41:43.076408 [Byte1]: 52
2639 13:41:43.081416
2640 13:41:43.081496 Set Vref, RX VrefLevel [Byte0]: 53
2641 13:41:43.084574 [Byte1]: 53
2642 13:41:43.088903
2643 13:41:43.088983 Set Vref, RX VrefLevel [Byte0]: 54
2644 13:41:43.092646 [Byte1]: 54
2645 13:41:43.097270
2646 13:41:43.097406 Set Vref, RX VrefLevel [Byte0]: 55
2647 13:41:43.100218 [Byte1]: 55
2648 13:41:43.105141
2649 13:41:43.105247 Set Vref, RX VrefLevel [Byte0]: 56
2650 13:41:43.108116 [Byte1]: 56
2651 13:41:43.113005
2652 13:41:43.113110 Set Vref, RX VrefLevel [Byte0]: 57
2653 13:41:43.115959 [Byte1]: 57
2654 13:41:43.120895
2655 13:41:43.121001 Set Vref, RX VrefLevel [Byte0]: 58
2656 13:41:43.124347 [Byte1]: 58
2657 13:41:43.129214
2658 13:41:43.129340 Set Vref, RX VrefLevel [Byte0]: 59
2659 13:41:43.132194 [Byte1]: 59
2660 13:41:43.136930
2661 13:41:43.137010 Set Vref, RX VrefLevel [Byte0]: 60
2662 13:41:43.140227 [Byte1]: 60
2663 13:41:43.144659
2664 13:41:43.144739 Set Vref, RX VrefLevel [Byte0]: 61
2665 13:41:43.148062 [Byte1]: 61
2666 13:41:43.152519
2667 13:41:43.152599 Set Vref, RX VrefLevel [Byte0]: 62
2668 13:41:43.156013 [Byte1]: 62
2669 13:41:43.160262
2670 13:41:43.160340 Set Vref, RX VrefLevel [Byte0]: 63
2671 13:41:43.164221 [Byte1]: 63
2672 13:41:43.168251
2673 13:41:43.168331 Set Vref, RX VrefLevel [Byte0]: 64
2674 13:41:43.171873 [Byte1]: 64
2675 13:41:43.176615
2676 13:41:43.176696 Set Vref, RX VrefLevel [Byte0]: 65
2677 13:41:43.179567 [Byte1]: 65
2678 13:41:43.184343
2679 13:41:43.184422 Set Vref, RX VrefLevel [Byte0]: 66
2680 13:41:43.187424 [Byte1]: 66
2681 13:41:43.192192
2682 13:41:43.192274 Final RX Vref Byte 0 = 46 to rank0
2683 13:41:43.195520 Final RX Vref Byte 1 = 50 to rank0
2684 13:41:43.198820 Final RX Vref Byte 0 = 46 to rank1
2685 13:41:43.202331 Final RX Vref Byte 1 = 50 to rank1==
2686 13:41:43.205909 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 13:41:43.209174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2688 13:41:43.212424 ==
2689 13:41:43.212504 DQS Delay:
2690 13:41:43.212567 DQS0 = 0, DQS1 = 0
2691 13:41:43.216045 DQM Delay:
2692 13:41:43.216125 DQM0 = 113, DQM1 = 105
2693 13:41:43.219009 DQ Delay:
2694 13:41:43.222567 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2695 13:41:43.225561 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2696 13:41:43.229160 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2697 13:41:43.232197 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2698 13:41:43.232277
2699 13:41:43.232340
2700 13:41:43.239198 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2701 13:41:43.242244 CH0 RK0: MR19=404, MR18=B0B
2702 13:41:43.249039 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2703 13:41:43.249120
2704 13:41:43.252066 ----->DramcWriteLeveling(PI) begin...
2705 13:41:43.252171 ==
2706 13:41:43.255508 Dram Type= 6, Freq= 0, CH_0, rank 1
2707 13:41:43.259125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2708 13:41:43.259200 ==
2709 13:41:43.262005 Write leveling (Byte 0): 27 => 27
2710 13:41:43.265702 Write leveling (Byte 1): 24 => 24
2711 13:41:43.268964 DramcWriteLeveling(PI) end<-----
2712 13:41:43.269065
2713 13:41:43.269171 ==
2714 13:41:43.272100 Dram Type= 6, Freq= 0, CH_0, rank 1
2715 13:41:43.275239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2716 13:41:43.278979 ==
2717 13:41:43.279088 [Gating] SW mode calibration
2718 13:41:43.288588 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2719 13:41:43.292018 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2720 13:41:43.295526 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2721 13:41:43.301943 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2722 13:41:43.305263 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2723 13:41:43.308665 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2724 13:41:43.315135 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2725 13:41:43.318479 0 11 20 | B1->B0 | 2c2c 2424 | 0 0 | (1 0) (1 0)
2726 13:41:43.321703 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2727 13:41:43.328811 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2728 13:41:43.331718 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2729 13:41:43.335303 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2730 13:41:43.341851 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2731 13:41:43.345416 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2732 13:41:43.348836 0 12 16 | B1->B0 | 2727 3737 | 0 1 | (0 0) (1 1)
2733 13:41:43.355223 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2734 13:41:43.358689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2735 13:41:43.362165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2736 13:41:43.368522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2737 13:41:43.371958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2738 13:41:43.375383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2739 13:41:43.378579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2740 13:41:43.385569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2741 13:41:43.388693 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2742 13:41:43.391742 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2743 13:41:43.398834 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2744 13:41:43.401762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2745 13:41:43.405461 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2746 13:41:43.412235 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2747 13:41:43.415701 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2748 13:41:43.418693 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2749 13:41:43.425685 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2750 13:41:43.429070 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2751 13:41:43.432267 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2752 13:41:43.438794 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2753 13:41:43.442437 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2754 13:41:43.445333 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2755 13:41:43.448835 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2756 13:41:43.455785 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2757 13:41:43.459271 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2758 13:41:43.462192 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2759 13:41:43.465686 Total UI for P1: 0, mck2ui 16
2760 13:41:43.468681 best dqsien dly found for B0: ( 0, 15, 18)
2761 13:41:43.472256 Total UI for P1: 0, mck2ui 16
2762 13:41:43.475663 best dqsien dly found for B1: ( 0, 15, 18)
2763 13:41:43.479224 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2764 13:41:43.482234 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2765 13:41:43.485219
2766 13:41:43.488652 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2767 13:41:43.492013 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2768 13:41:43.495271 [Gating] SW calibration Done
2769 13:41:43.495455 ==
2770 13:41:43.498848 Dram Type= 6, Freq= 0, CH_0, rank 1
2771 13:41:43.501966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2772 13:41:43.502091 ==
2773 13:41:43.502173 RX Vref Scan: 0
2774 13:41:43.505306
2775 13:41:43.505410 RX Vref 0 -> 0, step: 1
2776 13:41:43.505476
2777 13:41:43.508973 RX Delay -40 -> 252, step: 8
2778 13:41:43.512024 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2779 13:41:43.515496 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2780 13:41:43.522219 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2781 13:41:43.525796 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2782 13:41:43.528755 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2783 13:41:43.532221 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2784 13:41:43.535687 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2785 13:41:43.542180 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2786 13:41:43.545268 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2787 13:41:43.548869 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2788 13:41:43.551883 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2789 13:41:43.555493 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2790 13:41:43.558925 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2791 13:41:43.565247 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2792 13:41:43.568984 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2793 13:41:43.572856 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2794 13:41:43.573284 ==
2795 13:41:43.575737 Dram Type= 6, Freq= 0, CH_0, rank 1
2796 13:41:43.579057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2797 13:41:43.582811 ==
2798 13:41:43.583336 DQS Delay:
2799 13:41:43.583664 DQS0 = 0, DQS1 = 0
2800 13:41:43.586049 DQM Delay:
2801 13:41:43.586524 DQM0 = 114, DQM1 = 107
2802 13:41:43.589480 DQ Delay:
2803 13:41:43.592297 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2804 13:41:43.595867 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2805 13:41:43.599232 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2806 13:41:43.602440 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2807 13:41:43.602869
2808 13:41:43.603198
2809 13:41:43.603498 ==
2810 13:41:43.606138 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 13:41:43.608877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2812 13:41:43.609334 ==
2813 13:41:43.609679
2814 13:41:43.609985
2815 13:41:43.612402 TX Vref Scan disable
2816 13:41:43.616236 == TX Byte 0 ==
2817 13:41:43.619112 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2818 13:41:43.622468 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2819 13:41:43.626338 == TX Byte 1 ==
2820 13:41:43.629176 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2821 13:41:43.632826 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2822 13:41:43.633462 ==
2823 13:41:43.636447 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 13:41:43.639125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2825 13:41:43.642083 ==
2826 13:41:43.652494 TX Vref=22, minBit 8, minWin=25, winSum=418
2827 13:41:43.656165 TX Vref=24, minBit 8, minWin=25, winSum=422
2828 13:41:43.658986 TX Vref=26, minBit 9, minWin=25, winSum=423
2829 13:41:43.662476 TX Vref=28, minBit 10, minWin=25, winSum=424
2830 13:41:43.665933 TX Vref=30, minBit 8, minWin=26, winSum=433
2831 13:41:43.669111 TX Vref=32, minBit 1, minWin=26, winSum=434
2832 13:41:43.676279 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 32
2833 13:41:43.676759
2834 13:41:43.679294 Final TX Range 1 Vref 32
2835 13:41:43.679771
2836 13:41:43.680246 ==
2837 13:41:43.682760 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 13:41:43.686086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 13:41:43.686548 ==
2840 13:41:43.686909
2841 13:41:43.689048
2842 13:41:43.689582 TX Vref Scan disable
2843 13:41:43.692551 == TX Byte 0 ==
2844 13:41:43.696049 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2845 13:41:43.699592 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2846 13:41:43.702967 == TX Byte 1 ==
2847 13:41:43.705731 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2848 13:41:43.709231 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2849 13:41:43.709677
2850 13:41:43.712435 [DATLAT]
2851 13:41:43.712850 Freq=1200, CH0 RK1
2852 13:41:43.713178
2853 13:41:43.715676 DATLAT Default: 0xc
2854 13:41:43.716006 0, 0xFFFF, sum = 0
2855 13:41:43.719179 1, 0xFFFF, sum = 0
2856 13:41:43.719602 2, 0xFFFF, sum = 0
2857 13:41:43.722295 3, 0xFFFF, sum = 0
2858 13:41:43.722720 4, 0xFFFF, sum = 0
2859 13:41:43.726024 5, 0xFFFF, sum = 0
2860 13:41:43.726529 6, 0xFFFF, sum = 0
2861 13:41:43.729463 7, 0xFFFF, sum = 0
2862 13:41:43.732388 8, 0xFFFF, sum = 0
2863 13:41:43.732846 9, 0xFFFF, sum = 0
2864 13:41:43.736078 10, 0xFFFF, sum = 0
2865 13:41:43.736499 11, 0x0, sum = 1
2866 13:41:43.739422 12, 0x0, sum = 2
2867 13:41:43.739848 13, 0x0, sum = 3
2868 13:41:43.740182 14, 0x0, sum = 4
2869 13:41:43.742408 best_step = 12
2870 13:41:43.742822
2871 13:41:43.743151 ==
2872 13:41:43.746017 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 13:41:43.749065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2874 13:41:43.749540 ==
2875 13:41:43.752593 RX Vref Scan: 0
2876 13:41:43.753055
2877 13:41:43.753442 RX Vref 0 -> 0, step: 1
2878 13:41:43.756083
2879 13:41:43.756585 RX Delay -21 -> 252, step: 4
2880 13:41:43.762786 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2881 13:41:43.766344 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2882 13:41:43.769838 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2883 13:41:43.772651 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2884 13:41:43.775999 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2885 13:41:43.783543 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2886 13:41:43.786298 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2887 13:41:43.789673 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2888 13:41:43.793164 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2889 13:41:43.795960 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2890 13:41:43.802812 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2891 13:41:43.806580 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2892 13:41:43.809818 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2893 13:41:43.812952 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2894 13:41:43.816529 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2895 13:41:43.823332 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2896 13:41:43.823890 ==
2897 13:41:43.826213 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 13:41:43.829997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2899 13:41:43.830560 ==
2900 13:41:43.830923 DQS Delay:
2901 13:41:43.832947 DQS0 = 0, DQS1 = 0
2902 13:41:43.833554 DQM Delay:
2903 13:41:43.836288 DQM0 = 114, DQM1 = 105
2904 13:41:43.836751 DQ Delay:
2905 13:41:43.839369 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2906 13:41:43.842478 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2907 13:41:43.845978 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2908 13:41:43.849459 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2909 13:41:43.850045
2910 13:41:43.850417
2911 13:41:43.859815 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2912 13:41:43.862396 CH0 RK1: MR19=404, MR18=E0E
2913 13:41:43.865933 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2914 13:41:43.869765 [RxdqsGatingPostProcess] freq 1200
2915 13:41:43.875996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2916 13:41:43.879387 Pre-setting of DQS Precalculation
2917 13:41:43.882683 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2918 13:41:43.883142 ==
2919 13:41:43.886129 Dram Type= 6, Freq= 0, CH_1, rank 0
2920 13:41:43.892959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2921 13:41:43.893546 ==
2922 13:41:43.895982 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2923 13:41:43.902372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2924 13:41:43.911135 [CA 0] Center 37 (7~68) winsize 62
2925 13:41:43.914530 [CA 1] Center 37 (7~68) winsize 62
2926 13:41:43.918053 [CA 2] Center 34 (4~65) winsize 62
2927 13:41:43.921093 [CA 3] Center 33 (3~64) winsize 62
2928 13:41:43.924682 [CA 4] Center 32 (2~63) winsize 62
2929 13:41:43.927682 [CA 5] Center 32 (1~63) winsize 63
2930 13:41:43.928278
2931 13:41:43.931140 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2932 13:41:43.931730
2933 13:41:43.934469 [CATrainingPosCal] consider 1 rank data
2934 13:41:43.937493 u2DelayCellTimex100 = 270/100 ps
2935 13:41:43.940998 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2936 13:41:43.944528 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2937 13:41:43.951071 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2938 13:41:43.954496 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2939 13:41:43.957857 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2940 13:41:43.961217 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2941 13:41:43.961725
2942 13:41:43.964572 CA PerBit enable=1, Macro0, CA PI delay=32
2943 13:41:43.964889
2944 13:41:43.967521 [CBTSetCACLKResult] CA Dly = 32
2945 13:41:43.967836 CS Dly: 5 (0~36)
2946 13:41:43.971013 ==
2947 13:41:43.971328 Dram Type= 6, Freq= 0, CH_1, rank 1
2948 13:41:43.977882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2949 13:41:43.978296 ==
2950 13:41:43.980693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2951 13:41:43.987286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2952 13:41:43.996800 [CA 0] Center 36 (6~67) winsize 62
2953 13:41:43.999630 [CA 1] Center 37 (6~68) winsize 63
2954 13:41:44.002921 [CA 2] Center 33 (3~64) winsize 62
2955 13:41:44.006575 [CA 3] Center 33 (3~64) winsize 62
2956 13:41:44.010220 [CA 4] Center 32 (2~63) winsize 62
2957 13:41:44.013423 [CA 5] Center 32 (2~62) winsize 61
2958 13:41:44.013971
2959 13:41:44.017006 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2960 13:41:44.017638
2961 13:41:44.019667 [CATrainingPosCal] consider 2 rank data
2962 13:41:44.023066 u2DelayCellTimex100 = 270/100 ps
2963 13:41:44.026749 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2964 13:41:44.029708 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2965 13:41:44.036364 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2966 13:41:44.039735 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2967 13:41:44.042996 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2968 13:41:44.046261 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2969 13:41:44.046750
2970 13:41:44.049911 CA PerBit enable=1, Macro0, CA PI delay=32
2971 13:41:44.050365
2972 13:41:44.053018 [CBTSetCACLKResult] CA Dly = 32
2973 13:41:44.053521 CS Dly: 6 (0~38)
2974 13:41:44.053882
2975 13:41:44.056291 ----->DramcWriteLeveling(PI) begin...
2976 13:41:44.059515 ==
2977 13:41:44.063055 Dram Type= 6, Freq= 0, CH_1, rank 0
2978 13:41:44.066027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2979 13:41:44.066440 ==
2980 13:41:44.069639 Write leveling (Byte 0): 21 => 21
2981 13:41:44.072661 Write leveling (Byte 1): 22 => 22
2982 13:41:44.076229 DramcWriteLeveling(PI) end<-----
2983 13:41:44.076648
2984 13:41:44.077014 ==
2985 13:41:44.079460 Dram Type= 6, Freq= 0, CH_1, rank 0
2986 13:41:44.082946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2987 13:41:44.083367 ==
2988 13:41:44.086019 [Gating] SW mode calibration
2989 13:41:44.092897 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2990 13:41:44.099165 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2991 13:41:44.102919 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2992 13:41:44.106391 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2993 13:41:44.109210 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2994 13:41:44.116208 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2995 13:41:44.119104 0 11 16 | B1->B0 | 3131 2828 | 1 0 | (0 0) (0 1)
2996 13:41:44.122589 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2997 13:41:44.129400 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2998 13:41:44.132948 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2999 13:41:44.135934 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3000 13:41:44.143039 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3001 13:41:44.146228 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3002 13:41:44.149635 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3003 13:41:44.155843 0 12 16 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
3004 13:41:44.159516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3005 13:41:44.162798 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3006 13:41:44.169644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3007 13:41:44.172579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3008 13:41:44.176168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3009 13:41:44.182715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3010 13:41:44.185992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3011 13:41:44.189359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3012 13:41:44.195830 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3013 13:41:44.199382 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3014 13:41:44.202388 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3015 13:41:44.209760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3016 13:41:44.212520 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3017 13:41:44.216143 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3018 13:41:44.219416 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3019 13:41:44.225761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3020 13:41:44.229218 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3021 13:41:44.232669 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3022 13:41:44.239357 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3023 13:41:44.242283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3024 13:41:44.245647 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3025 13:41:44.252028 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3026 13:41:44.255355 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3027 13:41:44.258734 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3028 13:41:44.262477 Total UI for P1: 0, mck2ui 16
3029 13:41:44.265688 best dqsien dly found for B0: ( 0, 15, 14)
3030 13:41:44.272172 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3031 13:41:44.275623 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 13:41:44.279157 Total UI for P1: 0, mck2ui 16
3033 13:41:44.282246 best dqsien dly found for B1: ( 0, 15, 18)
3034 13:41:44.285735 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3035 13:41:44.289080 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3036 13:41:44.289188
3037 13:41:44.292662 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3038 13:41:44.295341 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3039 13:41:44.298700 [Gating] SW calibration Done
3040 13:41:44.298808 ==
3041 13:41:44.302407 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 13:41:44.305436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 13:41:44.308986 ==
3044 13:41:44.309093 RX Vref Scan: 0
3045 13:41:44.309187
3046 13:41:44.311977 RX Vref 0 -> 0, step: 1
3047 13:41:44.312074
3048 13:41:44.315595 RX Delay -40 -> 252, step: 8
3049 13:41:44.319074 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3050 13:41:44.322478 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3051 13:41:44.325571 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3052 13:41:44.328868 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3053 13:41:44.335443 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3054 13:41:44.338925 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3055 13:41:44.341926 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3056 13:41:44.345640 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3057 13:41:44.348589 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3058 13:41:44.352102 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3059 13:41:44.358636 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3060 13:41:44.362053 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3061 13:41:44.365471 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3062 13:41:44.368904 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3063 13:41:44.375269 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3064 13:41:44.378657 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3065 13:41:44.378764 ==
3066 13:41:44.381727 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 13:41:44.385160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3068 13:41:44.385272 ==
3069 13:41:44.385408 DQS Delay:
3070 13:41:44.388762 DQS0 = 0, DQS1 = 0
3071 13:41:44.388860 DQM Delay:
3072 13:41:44.391662 DQM0 = 116, DQM1 = 108
3073 13:41:44.391770 DQ Delay:
3074 13:41:44.395020 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3075 13:41:44.398702 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3076 13:41:44.401986 DQ8 =87, DQ9 =99, DQ10 =107, DQ11 =99
3077 13:41:44.405475 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3078 13:41:44.405583
3079 13:41:44.408320
3080 13:41:44.408417 ==
3081 13:41:44.411973 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 13:41:44.415020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3083 13:41:44.415128 ==
3084 13:41:44.415222
3085 13:41:44.415311
3086 13:41:44.418590 TX Vref Scan disable
3087 13:41:44.418690 == TX Byte 0 ==
3088 13:41:44.422158 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3089 13:41:44.428410 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3090 13:41:44.428515 == TX Byte 1 ==
3091 13:41:44.431857 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3092 13:41:44.438559 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3093 13:41:44.438639 ==
3094 13:41:44.441883 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 13:41:44.445255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3096 13:41:44.445386 ==
3097 13:41:44.456882 TX Vref=22, minBit 7, minWin=24, winSum=412
3098 13:41:44.460411 TX Vref=24, minBit 8, minWin=25, winSum=422
3099 13:41:44.463413 TX Vref=26, minBit 3, minWin=25, winSum=426
3100 13:41:44.467205 TX Vref=28, minBit 0, minWin=26, winSum=424
3101 13:41:44.470470 TX Vref=30, minBit 0, minWin=26, winSum=426
3102 13:41:44.476945 TX Vref=32, minBit 2, minWin=26, winSum=426
3103 13:41:44.480618 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
3104 13:41:44.480726
3105 13:41:44.483529 Final TX Range 1 Vref 30
3106 13:41:44.483631
3107 13:41:44.483722 ==
3108 13:41:44.486947 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 13:41:44.490072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 13:41:44.490176 ==
3111 13:41:44.490271
3112 13:41:44.493636
3113 13:41:44.493743 TX Vref Scan disable
3114 13:41:44.496861 == TX Byte 0 ==
3115 13:41:44.500280 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3116 13:41:44.503949 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3117 13:41:44.506842 == TX Byte 1 ==
3118 13:41:44.510261 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3119 13:41:44.513741 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3120 13:41:44.513849
3121 13:41:44.517037 [DATLAT]
3122 13:41:44.517142 Freq=1200, CH1 RK0
3123 13:41:44.517232
3124 13:41:44.520048 DATLAT Default: 0xd
3125 13:41:44.520127 0, 0xFFFF, sum = 0
3126 13:41:44.523619 1, 0xFFFF, sum = 0
3127 13:41:44.523699 2, 0xFFFF, sum = 0
3128 13:41:44.527133 3, 0xFFFF, sum = 0
3129 13:41:44.527214 4, 0xFFFF, sum = 0
3130 13:41:44.530074 5, 0xFFFF, sum = 0
3131 13:41:44.533460 6, 0xFFFF, sum = 0
3132 13:41:44.533543 7, 0xFFFF, sum = 0
3133 13:41:44.536990 8, 0xFFFF, sum = 0
3134 13:41:44.537070 9, 0xFFFF, sum = 0
3135 13:41:44.540439 10, 0xFFFF, sum = 0
3136 13:41:44.540564 11, 0x0, sum = 1
3137 13:41:44.543747 12, 0x0, sum = 2
3138 13:41:44.543846 13, 0x0, sum = 3
3139 13:41:44.543934 14, 0x0, sum = 4
3140 13:41:44.546626 best_step = 12
3141 13:41:44.546705
3142 13:41:44.546767 ==
3143 13:41:44.550164 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 13:41:44.553734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3145 13:41:44.553912 ==
3146 13:41:44.556774 RX Vref Scan: 1
3147 13:41:44.556858
3148 13:41:44.560298 Set Vref Range= 32 -> 127
3149 13:41:44.560383
3150 13:41:44.560449 RX Vref 32 -> 127, step: 1
3151 13:41:44.560510
3152 13:41:44.563877 RX Delay -29 -> 252, step: 4
3153 13:41:44.563966
3154 13:41:44.566928 Set Vref, RX VrefLevel [Byte0]: 32
3155 13:41:44.570381 [Byte1]: 32
3156 13:41:44.573889
3157 13:41:44.573977 Set Vref, RX VrefLevel [Byte0]: 33
3158 13:41:44.576683 [Byte1]: 33
3159 13:41:44.581206
3160 13:41:44.581359 Set Vref, RX VrefLevel [Byte0]: 34
3161 13:41:44.584963 [Byte1]: 34
3162 13:41:44.589643
3163 13:41:44.589758 Set Vref, RX VrefLevel [Byte0]: 35
3164 13:41:44.592747 [Byte1]: 35
3165 13:41:44.597889
3166 13:41:44.598027 Set Vref, RX VrefLevel [Byte0]: 36
3167 13:41:44.600922 [Byte1]: 36
3168 13:41:44.605606
3169 13:41:44.605775 Set Vref, RX VrefLevel [Byte0]: 37
3170 13:41:44.608854 [Byte1]: 37
3171 13:41:44.613328
3172 13:41:44.613498 Set Vref, RX VrefLevel [Byte0]: 38
3173 13:41:44.616800 [Byte1]: 38
3174 13:41:44.621523
3175 13:41:44.621641 Set Vref, RX VrefLevel [Byte0]: 39
3176 13:41:44.624816 [Byte1]: 39
3177 13:41:44.629662
3178 13:41:44.629894 Set Vref, RX VrefLevel [Byte0]: 40
3179 13:41:44.632649 [Byte1]: 40
3180 13:41:44.637510
3181 13:41:44.637727 Set Vref, RX VrefLevel [Byte0]: 41
3182 13:41:44.641011 [Byte1]: 41
3183 13:41:44.645191
3184 13:41:44.645440 Set Vref, RX VrefLevel [Byte0]: 42
3185 13:41:44.648918 [Byte1]: 42
3186 13:41:44.653591
3187 13:41:44.654067 Set Vref, RX VrefLevel [Byte0]: 43
3188 13:41:44.656623 [Byte1]: 43
3189 13:41:44.661496
3190 13:41:44.661942 Set Vref, RX VrefLevel [Byte0]: 44
3191 13:41:44.665258 [Byte1]: 44
3192 13:41:44.670008
3193 13:41:44.670692 Set Vref, RX VrefLevel [Byte0]: 45
3194 13:41:44.672704 [Byte1]: 45
3195 13:41:44.677729
3196 13:41:44.678320 Set Vref, RX VrefLevel [Byte0]: 46
3197 13:41:44.680614 [Byte1]: 46
3198 13:41:44.685457
3199 13:41:44.685909 Set Vref, RX VrefLevel [Byte0]: 47
3200 13:41:44.688435 [Byte1]: 47
3201 13:41:44.693267
3202 13:41:44.693884 Set Vref, RX VrefLevel [Byte0]: 48
3203 13:41:44.696930 [Byte1]: 48
3204 13:41:44.701382
3205 13:41:44.701851 Set Vref, RX VrefLevel [Byte0]: 49
3206 13:41:44.704282 [Byte1]: 49
3207 13:41:44.709010
3208 13:41:44.709571 Set Vref, RX VrefLevel [Byte0]: 50
3209 13:41:44.712211 [Byte1]: 50
3210 13:41:44.717642
3211 13:41:44.718190 Set Vref, RX VrefLevel [Byte0]: 51
3212 13:41:44.720397 [Byte1]: 51
3213 13:41:44.725158
3214 13:41:44.728723 Set Vref, RX VrefLevel [Byte0]: 52
3215 13:41:44.729175 [Byte1]: 52
3216 13:41:44.732956
3217 13:41:44.733615 Set Vref, RX VrefLevel [Byte0]: 53
3218 13:41:44.736729 [Byte1]: 53
3219 13:41:44.741281
3220 13:41:44.741880 Set Vref, RX VrefLevel [Byte0]: 54
3221 13:41:44.744533 [Byte1]: 54
3222 13:41:44.749145
3223 13:41:44.749677 Set Vref, RX VrefLevel [Byte0]: 55
3224 13:41:44.752025 [Byte1]: 55
3225 13:41:44.757125
3226 13:41:44.757663 Set Vref, RX VrefLevel [Byte0]: 56
3227 13:41:44.760709 [Byte1]: 56
3228 13:41:44.765025
3229 13:41:44.765599 Set Vref, RX VrefLevel [Byte0]: 57
3230 13:41:44.768189 [Byte1]: 57
3231 13:41:44.773249
3232 13:41:44.773850 Set Vref, RX VrefLevel [Byte0]: 58
3233 13:41:44.776078 [Byte1]: 58
3234 13:41:44.780948
3235 13:41:44.781653 Set Vref, RX VrefLevel [Byte0]: 59
3236 13:41:44.783988 [Byte1]: 59
3237 13:41:44.788538
3238 13:41:44.789041 Set Vref, RX VrefLevel [Byte0]: 60
3239 13:41:44.791910 [Byte1]: 60
3240 13:41:44.796562
3241 13:41:44.797012 Set Vref, RX VrefLevel [Byte0]: 61
3242 13:41:44.800011 [Byte1]: 61
3243 13:41:44.804725
3244 13:41:44.805181 Set Vref, RX VrefLevel [Byte0]: 62
3245 13:41:44.808311 [Byte1]: 62
3246 13:41:44.812417
3247 13:41:44.812868 Set Vref, RX VrefLevel [Byte0]: 63
3248 13:41:44.815716 [Byte1]: 63
3249 13:41:44.820560
3250 13:41:44.821006 Set Vref, RX VrefLevel [Byte0]: 64
3251 13:41:44.823736 [Byte1]: 64
3252 13:41:44.829039
3253 13:41:44.829607 Set Vref, RX VrefLevel [Byte0]: 65
3254 13:41:44.831737 [Byte1]: 65
3255 13:41:44.837403
3256 13:41:44.837910 Final RX Vref Byte 0 = 57 to rank0
3257 13:41:44.839934 Final RX Vref Byte 1 = 49 to rank0
3258 13:41:44.843545 Final RX Vref Byte 0 = 57 to rank1
3259 13:41:44.846690 Final RX Vref Byte 1 = 49 to rank1==
3260 13:41:44.849886 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 13:41:44.856957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3262 13:41:44.857501 ==
3263 13:41:44.857829 DQS Delay:
3264 13:41:44.858128 DQS0 = 0, DQS1 = 0
3265 13:41:44.859759 DQM Delay:
3266 13:41:44.860164 DQM0 = 115, DQM1 = 105
3267 13:41:44.863223 DQ Delay:
3268 13:41:44.866660 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3269 13:41:44.870397 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3270 13:41:44.873238 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3271 13:41:44.876796 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =112
3272 13:41:44.877523
3273 13:41:44.878069
3274 13:41:44.883228 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3275 13:41:44.887145 CH1 RK0: MR19=404, MR18=1B1B
3276 13:41:44.893221 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3277 13:41:44.893837
3278 13:41:44.896796 ----->DramcWriteLeveling(PI) begin...
3279 13:41:44.897206 ==
3280 13:41:44.899863 Dram Type= 6, Freq= 0, CH_1, rank 1
3281 13:41:44.903071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3282 13:41:44.906298 ==
3283 13:41:44.906823 Write leveling (Byte 0): 21 => 21
3284 13:41:44.909792 Write leveling (Byte 1): 20 => 20
3285 13:41:44.912822 DramcWriteLeveling(PI) end<-----
3286 13:41:44.913395
3287 13:41:44.913734 ==
3288 13:41:44.916516 Dram Type= 6, Freq= 0, CH_1, rank 1
3289 13:41:44.923322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3290 13:41:44.923897 ==
3291 13:41:44.924224 [Gating] SW mode calibration
3292 13:41:44.932667 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3293 13:41:44.936004 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3294 13:41:44.943071 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3295 13:41:44.945996 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3296 13:41:44.949453 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3297 13:41:44.952486 0 11 12 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (0 0)
3298 13:41:44.959272 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
3299 13:41:44.962721 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3300 13:41:44.966182 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3301 13:41:44.973122 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3302 13:41:44.976143 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3303 13:41:44.979461 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3304 13:41:44.986060 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3305 13:41:44.989662 0 12 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3306 13:41:44.992783 0 12 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
3307 13:41:44.999109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3308 13:41:45.002608 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3309 13:41:45.006073 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3310 13:41:45.012688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3311 13:41:45.015928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3312 13:41:45.019057 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3313 13:41:45.025658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3314 13:41:45.029491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3315 13:41:45.032487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3316 13:41:45.039603 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3317 13:41:45.042870 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3318 13:41:45.045981 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3319 13:41:45.052166 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3320 13:41:45.055803 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3321 13:41:45.058920 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3322 13:41:45.065735 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3323 13:41:45.069160 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3324 13:41:45.072770 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3325 13:41:45.079376 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3326 13:41:45.082626 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3327 13:41:45.085810 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3328 13:41:45.089231 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 13:41:45.095646 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3330 13:41:45.099114 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3331 13:41:45.102654 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3332 13:41:45.105725 Total UI for P1: 0, mck2ui 16
3333 13:41:45.109270 best dqsien dly found for B0: ( 0, 15, 14)
3334 13:41:45.115448 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 13:41:45.115902 Total UI for P1: 0, mck2ui 16
3336 13:41:45.122542 best dqsien dly found for B1: ( 0, 15, 18)
3337 13:41:45.125364 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3338 13:41:45.129071 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3339 13:41:45.129438
3340 13:41:45.132012 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3341 13:41:45.135724 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3342 13:41:45.138600 [Gating] SW calibration Done
3343 13:41:45.138925 ==
3344 13:41:45.142059 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 13:41:45.145520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 13:41:45.145860 ==
3347 13:41:45.148959 RX Vref Scan: 0
3348 13:41:45.149277
3349 13:41:45.149573 RX Vref 0 -> 0, step: 1
3350 13:41:45.152379
3351 13:41:45.152695 RX Delay -40 -> 252, step: 8
3352 13:41:45.159236 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3353 13:41:45.162177 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3354 13:41:45.165485 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3355 13:41:45.168883 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3356 13:41:45.172189 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3357 13:41:45.175982 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3358 13:41:45.182229 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3359 13:41:45.185407 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3360 13:41:45.189463 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3361 13:41:45.192385 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3362 13:41:45.196233 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3363 13:41:45.202404 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3364 13:41:45.205339 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3365 13:41:45.209375 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3366 13:41:45.212480 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3367 13:41:45.218927 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3368 13:41:45.219484 ==
3369 13:41:45.222207 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 13:41:45.226038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 13:41:45.226588 ==
3372 13:41:45.226947 DQS Delay:
3373 13:41:45.228745 DQS0 = 0, DQS1 = 0
3374 13:41:45.229376 DQM Delay:
3375 13:41:45.232314 DQM0 = 117, DQM1 = 106
3376 13:41:45.232886 DQ Delay:
3377 13:41:45.235400 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3378 13:41:45.239021 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3379 13:41:45.242121 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3380 13:41:45.245632 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3381 13:41:45.246210
3382 13:41:45.246772
3383 13:41:45.247241 ==
3384 13:41:45.249206 Dram Type= 6, Freq= 0, CH_1, rank 1
3385 13:41:45.255688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3386 13:41:45.256157 ==
3387 13:41:45.256512
3388 13:41:45.256844
3389 13:41:45.257159 TX Vref Scan disable
3390 13:41:45.259002 == TX Byte 0 ==
3391 13:41:45.262405 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3392 13:41:45.268742 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3393 13:41:45.269071 == TX Byte 1 ==
3394 13:41:45.272171 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3395 13:41:45.278854 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3396 13:41:45.279181 ==
3397 13:41:45.282033 Dram Type= 6, Freq= 0, CH_1, rank 1
3398 13:41:45.285367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3399 13:41:45.285603 ==
3400 13:41:45.296776 TX Vref=22, minBit 9, minWin=25, winSum=422
3401 13:41:45.300266 TX Vref=24, minBit 9, minWin=25, winSum=425
3402 13:41:45.303455 TX Vref=26, minBit 11, minWin=25, winSum=426
3403 13:41:45.306626 TX Vref=28, minBit 8, minWin=26, winSum=431
3404 13:41:45.309851 TX Vref=30, minBit 9, minWin=26, winSum=434
3405 13:41:45.317148 TX Vref=32, minBit 0, minWin=26, winSum=431
3406 13:41:45.319842 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3407 13:41:45.320297
3408 13:41:45.323291 Final TX Range 1 Vref 30
3409 13:41:45.323751
3410 13:41:45.324105 ==
3411 13:41:45.326776 Dram Type= 6, Freq= 0, CH_1, rank 1
3412 13:41:45.330271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3413 13:41:45.333243 ==
3414 13:41:45.333851
3415 13:41:45.334243
3416 13:41:45.334620 TX Vref Scan disable
3417 13:41:45.336747 == TX Byte 0 ==
3418 13:41:45.339784 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3419 13:41:45.343181 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3420 13:41:45.346850 == TX Byte 1 ==
3421 13:41:45.349916 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3422 13:41:45.353524 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3423 13:41:45.357043
3424 13:41:45.357648 [DATLAT]
3425 13:41:45.358008 Freq=1200, CH1 RK1
3426 13:41:45.358337
3427 13:41:45.359913 DATLAT Default: 0xc
3428 13:41:45.360447 0, 0xFFFF, sum = 0
3429 13:41:45.363476 1, 0xFFFF, sum = 0
3430 13:41:45.364057 2, 0xFFFF, sum = 0
3431 13:41:45.366282 3, 0xFFFF, sum = 0
3432 13:41:45.366738 4, 0xFFFF, sum = 0
3433 13:41:45.369811 5, 0xFFFF, sum = 0
3434 13:41:45.373465 6, 0xFFFF, sum = 0
3435 13:41:45.374060 7, 0xFFFF, sum = 0
3436 13:41:45.376792 8, 0xFFFF, sum = 0
3437 13:41:45.377400 9, 0xFFFF, sum = 0
3438 13:41:45.379918 10, 0xFFFF, sum = 0
3439 13:41:45.380479 11, 0x0, sum = 1
3440 13:41:45.383181 12, 0x0, sum = 2
3441 13:41:45.383641 13, 0x0, sum = 3
3442 13:41:45.384006 14, 0x0, sum = 4
3443 13:41:45.386416 best_step = 12
3444 13:41:45.386890
3445 13:41:45.387244 ==
3446 13:41:45.390128 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 13:41:45.392951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 13:41:45.393550 ==
3449 13:41:45.396941 RX Vref Scan: 0
3450 13:41:45.397493
3451 13:41:45.397842 RX Vref 0 -> 0, step: 1
3452 13:41:45.398165
3453 13:41:45.400223 RX Delay -29 -> 252, step: 4
3454 13:41:45.407350 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3455 13:41:45.410796 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3456 13:41:45.413438 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3457 13:41:45.417338 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3458 13:41:45.420088 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3459 13:41:45.427122 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3460 13:41:45.430814 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3461 13:41:45.433945 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3462 13:41:45.436583 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3463 13:41:45.440195 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3464 13:41:45.447070 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3465 13:41:45.450614 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3466 13:41:45.453409 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3467 13:41:45.457334 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3468 13:41:45.460600 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3469 13:41:45.466962 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3470 13:41:45.467422 ==
3471 13:41:45.469893 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 13:41:45.473485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3473 13:41:45.473946 ==
3474 13:41:45.474305 DQS Delay:
3475 13:41:45.477324 DQS0 = 0, DQS1 = 0
3476 13:41:45.477875 DQM Delay:
3477 13:41:45.480270 DQM0 = 114, DQM1 = 103
3478 13:41:45.480725 DQ Delay:
3479 13:41:45.483535 DQ0 =114, DQ1 =112, DQ2 =106, DQ3 =112
3480 13:41:45.486999 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3481 13:41:45.490303 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3482 13:41:45.493127 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =110
3483 13:41:45.493734
3484 13:41:45.494242
3485 13:41:45.503235 [DQSOSCAuto] RK1, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
3486 13:41:45.506762 CH1 RK1: MR19=404, MR18=505
3487 13:41:45.510022 CH1_RK1: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
3488 13:41:45.513492 [RxdqsGatingPostProcess] freq 1200
3489 13:41:45.520165 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3490 13:41:45.523280 Pre-setting of DQS Precalculation
3491 13:41:45.527064 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3492 13:41:45.536370 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3493 13:41:45.543157 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3494 13:41:45.543613
3495 13:41:45.544004
3496 13:41:45.546751 [Calibration Summary] 2400 Mbps
3497 13:41:45.547206 CH 0, Rank 0
3498 13:41:45.549784 SW Impedance : PASS
3499 13:41:45.550271 DUTY Scan : NO K
3500 13:41:45.553482 ZQ Calibration : PASS
3501 13:41:45.557265 Jitter Meter : NO K
3502 13:41:45.557861 CBT Training : PASS
3503 13:41:45.560220 Write leveling : PASS
3504 13:41:45.563469 RX DQS gating : PASS
3505 13:41:45.563928 RX DQ/DQS(RDDQC) : PASS
3506 13:41:45.566999 TX DQ/DQS : PASS
3507 13:41:45.569715 RX DATLAT : PASS
3508 13:41:45.570168 RX DQ/DQS(Engine): PASS
3509 13:41:45.573369 TX OE : NO K
3510 13:41:45.573824 All Pass.
3511 13:41:45.574180
3512 13:41:45.576381 CH 0, Rank 1
3513 13:41:45.576829 SW Impedance : PASS
3514 13:41:45.580246 DUTY Scan : NO K
3515 13:41:45.580795 ZQ Calibration : PASS
3516 13:41:45.583452 Jitter Meter : NO K
3517 13:41:45.587216 CBT Training : PASS
3518 13:41:45.587803 Write leveling : PASS
3519 13:41:45.590108 RX DQS gating : PASS
3520 13:41:45.593173 RX DQ/DQS(RDDQC) : PASS
3521 13:41:45.593669 TX DQ/DQS : PASS
3522 13:41:45.596380 RX DATLAT : PASS
3523 13:41:45.599839 RX DQ/DQS(Engine): PASS
3524 13:41:45.600291 TX OE : NO K
3525 13:41:45.603159 All Pass.
3526 13:41:45.603698
3527 13:41:45.604190 CH 1, Rank 0
3528 13:41:45.606478 SW Impedance : PASS
3529 13:41:45.606930 DUTY Scan : NO K
3530 13:41:45.610206 ZQ Calibration : PASS
3531 13:41:45.613348 Jitter Meter : NO K
3532 13:41:45.613845 CBT Training : PASS
3533 13:41:45.616675 Write leveling : PASS
3534 13:41:45.620015 RX DQS gating : PASS
3535 13:41:45.620572 RX DQ/DQS(RDDQC) : PASS
3536 13:41:45.623550 TX DQ/DQS : PASS
3537 13:41:45.624192 RX DATLAT : PASS
3538 13:41:45.626804 RX DQ/DQS(Engine): PASS
3539 13:41:45.629945 TX OE : NO K
3540 13:41:45.630485 All Pass.
3541 13:41:45.630849
3542 13:41:45.631182 CH 1, Rank 1
3543 13:41:45.633102 SW Impedance : PASS
3544 13:41:45.636656 DUTY Scan : NO K
3545 13:41:45.637108 ZQ Calibration : PASS
3546 13:41:45.640058 Jitter Meter : NO K
3547 13:41:45.642995 CBT Training : PASS
3548 13:41:45.643450 Write leveling : PASS
3549 13:41:45.646392 RX DQS gating : PASS
3550 13:41:45.650023 RX DQ/DQS(RDDQC) : PASS
3551 13:41:45.650341 TX DQ/DQS : PASS
3552 13:41:45.653098 RX DATLAT : PASS
3553 13:41:45.656071 RX DQ/DQS(Engine): PASS
3554 13:41:45.656305 TX OE : NO K
3555 13:41:45.659676 All Pass.
3556 13:41:45.659861
3557 13:41:45.660005 DramC Write-DBI off
3558 13:41:45.663022 PER_BANK_REFRESH: Hybrid Mode
3559 13:41:45.663266 TX_TRACKING: ON
3560 13:41:45.672904 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3561 13:41:45.676563 [FAST_K] Save calibration result to emmc
3562 13:41:45.679622 dramc_set_vcore_voltage set vcore to 650000
3563 13:41:45.683094 Read voltage for 600, 5
3564 13:41:45.683328 Vio18 = 0
3565 13:41:45.686013 Vcore = 650000
3566 13:41:45.686171 Vdram = 0
3567 13:41:45.686294 Vddq = 0
3568 13:41:45.686409 Vmddr = 0
3569 13:41:45.693313 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3570 13:41:45.699667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3571 13:41:45.699963 MEM_TYPE=3, freq_sel=19
3572 13:41:45.703228 sv_algorithm_assistance_LP4_1600
3573 13:41:45.706931 ============ PULL DRAM RESETB DOWN ============
3574 13:41:45.713107 ========== PULL DRAM RESETB DOWN end =========
3575 13:41:45.716828 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3576 13:41:45.720179 ===================================
3577 13:41:45.722976 LPDDR4 DRAM CONFIGURATION
3578 13:41:45.726889 ===================================
3579 13:41:45.727350 EX_ROW_EN[0] = 0x0
3580 13:41:45.729642 EX_ROW_EN[1] = 0x0
3581 13:41:45.730096 LP4Y_EN = 0x0
3582 13:41:45.733350 WORK_FSP = 0x0
3583 13:41:45.733913 WL = 0x2
3584 13:41:45.737143 RL = 0x2
3585 13:41:45.737746 BL = 0x2
3586 13:41:45.739950 RPST = 0x0
3587 13:41:45.740496 RD_PRE = 0x0
3588 13:41:45.743624 WR_PRE = 0x1
3589 13:41:45.744079 WR_PST = 0x0
3590 13:41:45.746296 DBI_WR = 0x0
3591 13:41:45.750116 DBI_RD = 0x0
3592 13:41:45.750670 OTF = 0x1
3593 13:41:45.753328 ===================================
3594 13:41:45.756946 ===================================
3595 13:41:45.757553 ANA top config
3596 13:41:45.760445 ===================================
3597 13:41:45.763095 DLL_ASYNC_EN = 0
3598 13:41:45.766025 ALL_SLAVE_EN = 1
3599 13:41:45.769708 NEW_RANK_MODE = 1
3600 13:41:45.773448 DLL_IDLE_MODE = 1
3601 13:41:45.773996 LP45_APHY_COMB_EN = 1
3602 13:41:45.776034 TX_ODT_DIS = 1
3603 13:41:45.779635 NEW_8X_MODE = 1
3604 13:41:45.782618 ===================================
3605 13:41:45.786297 ===================================
3606 13:41:45.790264 data_rate = 1200
3607 13:41:45.792885 CKR = 1
3608 13:41:45.793394 DQ_P2S_RATIO = 8
3609 13:41:45.796291 ===================================
3610 13:41:45.799939 CA_P2S_RATIO = 8
3611 13:41:45.802645 DQ_CA_OPEN = 0
3612 13:41:45.805932 DQ_SEMI_OPEN = 0
3613 13:41:45.809264 CA_SEMI_OPEN = 0
3614 13:41:45.813184 CA_FULL_RATE = 0
3615 13:41:45.813789 DQ_CKDIV4_EN = 1
3616 13:41:45.815925 CA_CKDIV4_EN = 1
3617 13:41:45.819213 CA_PREDIV_EN = 0
3618 13:41:45.822370 PH8_DLY = 0
3619 13:41:45.825971 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3620 13:41:45.829666 DQ_AAMCK_DIV = 4
3621 13:41:45.830220 CA_AAMCK_DIV = 4
3622 13:41:45.832875 CA_ADMCK_DIV = 4
3623 13:41:45.835897 DQ_TRACK_CA_EN = 0
3624 13:41:45.839048 CA_PICK = 600
3625 13:41:45.842218 CA_MCKIO = 600
3626 13:41:45.846114 MCKIO_SEMI = 0
3627 13:41:45.849724 PLL_FREQ = 2288
3628 13:41:45.852455 DQ_UI_PI_RATIO = 32
3629 13:41:45.853004 CA_UI_PI_RATIO = 0
3630 13:41:45.855764 ===================================
3631 13:41:45.859722 ===================================
3632 13:41:45.862387 memory_type:LPDDR4
3633 13:41:45.866006 GP_NUM : 10
3634 13:41:45.866555 SRAM_EN : 1
3635 13:41:45.868969 MD32_EN : 0
3636 13:41:45.872588 ===================================
3637 13:41:45.875584 [ANA_INIT] >>>>>>>>>>>>>>
3638 13:41:45.879073 <<<<<< [CONFIGURE PHASE]: ANA_TX
3639 13:41:45.882544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3640 13:41:45.885578 ===================================
3641 13:41:45.886035 data_rate = 1200,PCW = 0X5800
3642 13:41:45.888546 ===================================
3643 13:41:45.892491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3644 13:41:45.899008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3645 13:41:45.905421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3646 13:41:45.908957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3647 13:41:45.912157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3648 13:41:45.915529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3649 13:41:45.918331 [ANA_INIT] flow start
3650 13:41:45.918783 [ANA_INIT] PLL >>>>>>>>
3651 13:41:45.921924 [ANA_INIT] PLL <<<<<<<<
3652 13:41:45.924866 [ANA_INIT] MIDPI >>>>>>>>
3653 13:41:45.928406 [ANA_INIT] MIDPI <<<<<<<<
3654 13:41:45.928867 [ANA_INIT] DLL >>>>>>>>
3655 13:41:45.932334 [ANA_INIT] flow end
3656 13:41:45.935219 ============ LP4 DIFF to SE enter ============
3657 13:41:45.938558 ============ LP4 DIFF to SE exit ============
3658 13:41:45.941624 [ANA_INIT] <<<<<<<<<<<<<
3659 13:41:45.944846 [Flow] Enable top DCM control >>>>>
3660 13:41:45.948366 [Flow] Enable top DCM control <<<<<
3661 13:41:45.951218 Enable DLL master slave shuffle
3662 13:41:45.957877 ==============================================================
3663 13:41:45.958686 Gating Mode config
3664 13:41:45.964471 ==============================================================
3665 13:41:45.965130 Config description:
3666 13:41:45.974181 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3667 13:41:45.980840 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3668 13:41:45.987762 SELPH_MODE 0: By rank 1: By Phase
3669 13:41:45.994369 ==============================================================
3670 13:41:45.994872 GAT_TRACK_EN = 1
3671 13:41:45.998092 RX_GATING_MODE = 2
3672 13:41:46.001119 RX_GATING_TRACK_MODE = 2
3673 13:41:46.004602 SELPH_MODE = 1
3674 13:41:46.007441 PICG_EARLY_EN = 1
3675 13:41:46.011025 VALID_LAT_VALUE = 1
3676 13:41:46.017623 ==============================================================
3677 13:41:46.020962 Enter into Gating configuration >>>>
3678 13:41:46.024070 Exit from Gating configuration <<<<
3679 13:41:46.027320 Enter into DVFS_PRE_config >>>>>
3680 13:41:46.037763 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3681 13:41:46.041399 Exit from DVFS_PRE_config <<<<<
3682 13:41:46.044030 Enter into PICG configuration >>>>
3683 13:41:46.047492 Exit from PICG configuration <<<<
3684 13:41:46.050807 [RX_INPUT] configuration >>>>>
3685 13:41:46.051332 [RX_INPUT] configuration <<<<<
3686 13:41:46.057515 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3687 13:41:46.063913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3688 13:41:46.066843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3689 13:41:46.074021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3690 13:41:46.080721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3691 13:41:46.087160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3692 13:41:46.090024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3693 13:41:46.093463 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3694 13:41:46.100169 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3695 13:41:46.103797 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3696 13:41:46.106841 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3697 13:41:46.113786 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3698 13:41:46.117033 ===================================
3699 13:41:46.117518 LPDDR4 DRAM CONFIGURATION
3700 13:41:46.120549 ===================================
3701 13:41:46.123611 EX_ROW_EN[0] = 0x0
3702 13:41:46.124019 EX_ROW_EN[1] = 0x0
3703 13:41:46.126586 LP4Y_EN = 0x0
3704 13:41:46.130021 WORK_FSP = 0x0
3705 13:41:46.130433 WL = 0x2
3706 13:41:46.133398 RL = 0x2
3707 13:41:46.133806 BL = 0x2
3708 13:41:46.136498 RPST = 0x0
3709 13:41:46.136983 RD_PRE = 0x0
3710 13:41:46.140000 WR_PRE = 0x1
3711 13:41:46.140408 WR_PST = 0x0
3712 13:41:46.143622 DBI_WR = 0x0
3713 13:41:46.144033 DBI_RD = 0x0
3714 13:41:46.146493 OTF = 0x1
3715 13:41:46.150177 ===================================
3716 13:41:46.153148 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3717 13:41:46.156818 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3718 13:41:46.163623 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 13:41:46.166746 ===================================
3720 13:41:46.167157 LPDDR4 DRAM CONFIGURATION
3721 13:41:46.169746 ===================================
3722 13:41:46.173616 EX_ROW_EN[0] = 0x10
3723 13:41:46.174026 EX_ROW_EN[1] = 0x0
3724 13:41:46.176879 LP4Y_EN = 0x0
3725 13:41:46.177445 WORK_FSP = 0x0
3726 13:41:46.179713 WL = 0x2
3727 13:41:46.183202 RL = 0x2
3728 13:41:46.183614 BL = 0x2
3729 13:41:46.186196 RPST = 0x0
3730 13:41:46.186603 RD_PRE = 0x0
3731 13:41:46.189802 WR_PRE = 0x1
3732 13:41:46.190214 WR_PST = 0x0
3733 13:41:46.193062 DBI_WR = 0x0
3734 13:41:46.193516 DBI_RD = 0x0
3735 13:41:46.196269 OTF = 0x1
3736 13:41:46.200015 ===================================
3737 13:41:46.206555 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3738 13:41:46.209530 nWR fixed to 30
3739 13:41:46.209988 [ModeRegInit_LP4] CH0 RK0
3740 13:41:46.213105 [ModeRegInit_LP4] CH0 RK1
3741 13:41:46.216373 [ModeRegInit_LP4] CH1 RK0
3742 13:41:46.216924 [ModeRegInit_LP4] CH1 RK1
3743 13:41:46.219882 match AC timing 16
3744 13:41:46.223386 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3745 13:41:46.226066 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3746 13:41:46.232990 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3747 13:41:46.236470 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3748 13:41:46.243234 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3749 13:41:46.243792 ==
3750 13:41:46.246216 Dram Type= 6, Freq= 0, CH_0, rank 0
3751 13:41:46.249975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3752 13:41:46.250517 ==
3753 13:41:46.256465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3754 13:41:46.262869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3755 13:41:46.265683 [CA 0] Center 35 (5~66) winsize 62
3756 13:41:46.269283 [CA 1] Center 35 (5~66) winsize 62
3757 13:41:46.272457 [CA 2] Center 34 (4~65) winsize 62
3758 13:41:46.275987 [CA 3] Center 34 (3~65) winsize 63
3759 13:41:46.279338 [CA 4] Center 33 (3~64) winsize 62
3760 13:41:46.279796 [CA 5] Center 33 (3~64) winsize 62
3761 13:41:46.282852
3762 13:41:46.285845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3763 13:41:46.286304
3764 13:41:46.289098 [CATrainingPosCal] consider 1 rank data
3765 13:41:46.292558 u2DelayCellTimex100 = 270/100 ps
3766 13:41:46.296066 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3767 13:41:46.299290 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3768 13:41:46.302375 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3769 13:41:46.305629 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3770 13:41:46.309374 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3771 13:41:46.312675 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3772 13:41:46.313187
3773 13:41:46.315530 CA PerBit enable=1, Macro0, CA PI delay=33
3774 13:41:46.318615
3775 13:41:46.319069 [CBTSetCACLKResult] CA Dly = 33
3776 13:41:46.322370 CS Dly: 6 (0~37)
3777 13:41:46.322856 ==
3778 13:41:46.325336 Dram Type= 6, Freq= 0, CH_0, rank 1
3779 13:41:46.329322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3780 13:41:46.329843 ==
3781 13:41:46.335125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3782 13:41:46.342383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3783 13:41:46.345486 [CA 0] Center 35 (5~66) winsize 62
3784 13:41:46.348772 [CA 1] Center 35 (5~66) winsize 62
3785 13:41:46.352183 [CA 2] Center 34 (4~65) winsize 62
3786 13:41:46.355260 [CA 3] Center 34 (4~65) winsize 62
3787 13:41:46.358818 [CA 4] Center 33 (3~64) winsize 62
3788 13:41:46.362279 [CA 5] Center 33 (3~64) winsize 62
3789 13:41:46.362827
3790 13:41:46.365264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3791 13:41:46.365847
3792 13:41:46.368924 [CATrainingPosCal] consider 2 rank data
3793 13:41:46.372203 u2DelayCellTimex100 = 270/100 ps
3794 13:41:46.375466 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3795 13:41:46.378216 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3796 13:41:46.382232 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3797 13:41:46.384798 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3798 13:41:46.388184 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3799 13:41:46.391711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3800 13:41:46.395032
3801 13:41:46.398554 CA PerBit enable=1, Macro0, CA PI delay=33
3802 13:41:46.399231
3803 13:41:46.401893 [CBTSetCACLKResult] CA Dly = 33
3804 13:41:46.402348 CS Dly: 5 (0~36)
3805 13:41:46.402706
3806 13:41:46.404886 ----->DramcWriteLeveling(PI) begin...
3807 13:41:46.405403 ==
3808 13:41:46.408402 Dram Type= 6, Freq= 0, CH_0, rank 0
3809 13:41:46.411804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3810 13:41:46.415051 ==
3811 13:41:46.415513 Write leveling (Byte 0): 29 => 29
3812 13:41:46.417955 Write leveling (Byte 1): 29 => 29
3813 13:41:46.421719 DramcWriteLeveling(PI) end<-----
3814 13:41:46.422313
3815 13:41:46.422820 ==
3816 13:41:46.424962 Dram Type= 6, Freq= 0, CH_0, rank 0
3817 13:41:46.431497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3818 13:41:46.432047 ==
3819 13:41:46.434660 [Gating] SW mode calibration
3820 13:41:46.441228 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3821 13:41:46.444324 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3822 13:41:46.450792 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3823 13:41:46.454429 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3824 13:41:46.457917 0 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3825 13:41:46.464508 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3826 13:41:46.467286 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3827 13:41:46.470947 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3828 13:41:46.477526 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3829 13:41:46.480394 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3830 13:41:46.483959 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3831 13:41:46.490575 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3832 13:41:46.493883 0 6 8 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (0 0)
3833 13:41:46.496915 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3834 13:41:46.503596 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3835 13:41:46.506850 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3836 13:41:46.510384 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3837 13:41:46.516952 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3838 13:41:46.520461 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3839 13:41:46.524319 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3840 13:41:46.530796 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3841 13:41:46.533719 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3842 13:41:46.536855 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3843 13:41:46.543706 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3844 13:41:46.547440 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3845 13:41:46.550515 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3846 13:41:46.556809 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3847 13:41:46.560375 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3848 13:41:46.563626 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3849 13:41:46.569996 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3850 13:41:46.573258 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3851 13:41:46.576232 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3852 13:41:46.583109 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3853 13:41:46.586502 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3854 13:41:46.589469 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3855 13:41:46.596987 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3856 13:41:46.599833 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3857 13:41:46.602881 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3858 13:41:46.606241 Total UI for P1: 0, mck2ui 16
3859 13:41:46.610017 best dqsien dly found for B0: ( 0, 9, 8)
3860 13:41:46.613462 Total UI for P1: 0, mck2ui 16
3861 13:41:46.616397 best dqsien dly found for B1: ( 0, 9, 10)
3862 13:41:46.619783 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3863 13:41:46.622865 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3864 13:41:46.623321
3865 13:41:46.626510 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3866 13:41:46.632767 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3867 13:41:46.633353 [Gating] SW calibration Done
3868 13:41:46.633725 ==
3869 13:41:46.636326 Dram Type= 6, Freq= 0, CH_0, rank 0
3870 13:41:46.642526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3871 13:41:46.643064 ==
3872 13:41:46.643425 RX Vref Scan: 0
3873 13:41:46.643761
3874 13:41:46.646052 RX Vref 0 -> 0, step: 1
3875 13:41:46.646508
3876 13:41:46.649466 RX Delay -230 -> 252, step: 16
3877 13:41:46.653261 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3878 13:41:46.656044 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3879 13:41:46.662476 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3880 13:41:46.665931 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3881 13:41:46.669508 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3882 13:41:46.672253 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3883 13:41:46.676077 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3884 13:41:46.682586 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3885 13:41:46.685573 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3886 13:41:46.689086 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3887 13:41:46.692561 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3888 13:41:46.699054 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3889 13:41:46.701972 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3890 13:41:46.705611 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3891 13:41:46.709004 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3892 13:41:46.715088 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3893 13:41:46.715413 ==
3894 13:41:46.718722 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 13:41:46.722010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3896 13:41:46.722251 ==
3897 13:41:46.722442 DQS Delay:
3898 13:41:46.724999 DQS0 = 0, DQS1 = 0
3899 13:41:46.725194 DQM Delay:
3900 13:41:46.728069 DQM0 = 43, DQM1 = 34
3901 13:41:46.728258 DQ Delay:
3902 13:41:46.731757 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3903 13:41:46.735339 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3904 13:41:46.738237 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
3905 13:41:46.741786 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3906 13:41:46.742096
3907 13:41:46.742362
3908 13:41:46.742606 ==
3909 13:41:46.744830 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 13:41:46.748351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3911 13:41:46.748665 ==
3912 13:41:46.751349
3913 13:41:46.751588
3914 13:41:46.751793 TX Vref Scan disable
3915 13:41:46.754964 == TX Byte 0 ==
3916 13:41:46.757997 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3917 13:41:46.761365 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3918 13:41:46.764888 == TX Byte 1 ==
3919 13:41:46.767986 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3920 13:41:46.771380 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3921 13:41:46.771561 ==
3922 13:41:46.774368 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 13:41:46.781048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3924 13:41:46.781213 ==
3925 13:41:46.781344
3926 13:41:46.781457
3927 13:41:46.781567 TX Vref Scan disable
3928 13:41:46.786020 == TX Byte 0 ==
3929 13:41:46.789421 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3930 13:41:46.795938 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3931 13:41:46.796075 == TX Byte 1 ==
3932 13:41:46.798937 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3933 13:41:46.805422 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3934 13:41:46.805505
3935 13:41:46.805569 [DATLAT]
3936 13:41:46.805629 Freq=600, CH0 RK0
3937 13:41:46.805687
3938 13:41:46.809102 DATLAT Default: 0x9
3939 13:41:46.811994 0, 0xFFFF, sum = 0
3940 13:41:46.812100 1, 0xFFFF, sum = 0
3941 13:41:46.815592 2, 0xFFFF, sum = 0
3942 13:41:46.815681 3, 0xFFFF, sum = 0
3943 13:41:46.818751 4, 0xFFFF, sum = 0
3944 13:41:46.818836 5, 0xFFFF, sum = 0
3945 13:41:46.822258 6, 0xFFFF, sum = 0
3946 13:41:46.822345 7, 0x0, sum = 1
3947 13:41:46.825164 8, 0x0, sum = 2
3948 13:41:46.825274 9, 0x0, sum = 3
3949 13:41:46.825384 10, 0x0, sum = 4
3950 13:41:46.828759 best_step = 8
3951 13:41:46.828839
3952 13:41:46.828902 ==
3953 13:41:46.832160 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 13:41:46.835437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3955 13:41:46.835519 ==
3956 13:41:46.838710 RX Vref Scan: 1
3957 13:41:46.838790
3958 13:41:46.838854 RX Vref 0 -> 0, step: 1
3959 13:41:46.842080
3960 13:41:46.842491 RX Delay -195 -> 252, step: 8
3961 13:41:46.842816
3962 13:41:46.845879 Set Vref, RX VrefLevel [Byte0]: 46
3963 13:41:46.848561 [Byte1]: 50
3964 13:41:46.853390
3965 13:41:46.853805 Final RX Vref Byte 0 = 46 to rank0
3966 13:41:46.856356 Final RX Vref Byte 1 = 50 to rank0
3967 13:41:46.860130 Final RX Vref Byte 0 = 46 to rank1
3968 13:41:46.863097 Final RX Vref Byte 1 = 50 to rank1==
3969 13:41:46.866847 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 13:41:46.873032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3971 13:41:46.873608 ==
3972 13:41:46.873972 DQS Delay:
3973 13:41:46.876428 DQS0 = 0, DQS1 = 0
3974 13:41:46.876863 DQM Delay:
3975 13:41:46.877187 DQM0 = 39, DQM1 = 30
3976 13:41:46.879845 DQ Delay:
3977 13:41:46.882775 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3978 13:41:46.886355 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
3979 13:41:46.889605 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
3980 13:41:46.892675 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3981 13:41:46.893090
3982 13:41:46.893472
3983 13:41:46.899554 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3984 13:41:46.902570 CH0 RK0: MR19=808, MR18=4D4D
3985 13:41:46.909398 CH0_RK0: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
3986 13:41:46.909824
3987 13:41:46.913050 ----->DramcWriteLeveling(PI) begin...
3988 13:41:46.913505 ==
3989 13:41:46.916194 Dram Type= 6, Freq= 0, CH_0, rank 1
3990 13:41:46.919179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3991 13:41:46.919768 ==
3992 13:41:46.922687 Write leveling (Byte 0): 30 => 30
3993 13:41:46.925873 Write leveling (Byte 1): 29 => 29
3994 13:41:46.929196 DramcWriteLeveling(PI) end<-----
3995 13:41:46.929541
3996 13:41:46.929716 ==
3997 13:41:46.932104 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 13:41:46.935678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 13:41:46.935858 ==
4000 13:41:46.939086 [Gating] SW mode calibration
4001 13:41:46.945466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4002 13:41:46.952013 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4003 13:41:46.955174 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 13:41:46.961856 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 13:41:46.965443 0 5 8 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
4006 13:41:46.968338 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4007 13:41:46.975264 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 13:41:46.978780 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 13:41:46.982180 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 13:41:46.988494 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 13:41:46.992016 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 13:41:46.995701 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 13:41:47.002007 0 6 8 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
4014 13:41:47.005000 0 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4015 13:41:47.008427 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 13:41:47.015499 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 13:41:47.018781 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 13:41:47.021648 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 13:41:47.028611 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 13:41:47.031614 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 13:41:47.034971 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4022 13:41:47.038369 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:41:47.045418 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:41:47.048416 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:41:47.051971 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:41:47.058455 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:41:47.061761 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:41:47.064987 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:41:47.071554 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:41:47.075036 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:41:47.078018 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:41:47.084976 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:41:47.087961 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:41:47.091616 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:41:47.097948 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:41:47.101530 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 13:41:47.104341 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 13:41:47.108031 Total UI for P1: 0, mck2ui 16
4039 13:41:47.111138 best dqsien dly found for B0: ( 0, 9, 6)
4040 13:41:47.114610 Total UI for P1: 0, mck2ui 16
4041 13:41:47.117525 best dqsien dly found for B1: ( 0, 9, 6)
4042 13:41:47.120818 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4043 13:41:47.124727 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4044 13:41:47.124828
4045 13:41:47.131427 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4046 13:41:47.134366 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4047 13:41:47.137766 [Gating] SW calibration Done
4048 13:41:47.137956 ==
4049 13:41:47.140985 Dram Type= 6, Freq= 0, CH_0, rank 1
4050 13:41:47.144000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4051 13:41:47.144149 ==
4052 13:41:47.144283 RX Vref Scan: 0
4053 13:41:47.144412
4054 13:41:47.147497 RX Vref 0 -> 0, step: 1
4055 13:41:47.147653
4056 13:41:47.151078 RX Delay -230 -> 252, step: 16
4057 13:41:47.154446 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4058 13:41:47.160983 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4059 13:41:47.164167 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4060 13:41:47.167021 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4061 13:41:47.170830 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4062 13:41:47.174412 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4063 13:41:47.180902 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4064 13:41:47.183798 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4065 13:41:47.187565 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4066 13:41:47.191041 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4067 13:41:47.197400 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4068 13:41:47.200923 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4069 13:41:47.203873 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4070 13:41:47.207450 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4071 13:41:47.213960 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4072 13:41:47.217226 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4073 13:41:47.217802 ==
4074 13:41:47.220390 Dram Type= 6, Freq= 0, CH_0, rank 1
4075 13:41:47.223779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4076 13:41:47.224243 ==
4077 13:41:47.226843 DQS Delay:
4078 13:41:47.227375 DQS0 = 0, DQS1 = 0
4079 13:41:47.227729 DQM Delay:
4080 13:41:47.230527 DQM0 = 42, DQM1 = 33
4081 13:41:47.230946 DQ Delay:
4082 13:41:47.233922 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4083 13:41:47.237268 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4084 13:41:47.240262 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4085 13:41:47.243975 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4086 13:41:47.244477
4087 13:41:47.244801
4088 13:41:47.245104 ==
4089 13:41:47.246766 Dram Type= 6, Freq= 0, CH_0, rank 1
4090 13:41:47.254098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4091 13:41:47.254671 ==
4092 13:41:47.255173
4093 13:41:47.255725
4094 13:41:47.256142 TX Vref Scan disable
4095 13:41:47.257215 == TX Byte 0 ==
4096 13:41:47.260159 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 13:41:47.267212 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 13:41:47.267623 == TX Byte 1 ==
4099 13:41:47.270656 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4100 13:41:47.276965 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4101 13:41:47.277404 ==
4102 13:41:47.280285 Dram Type= 6, Freq= 0, CH_0, rank 1
4103 13:41:47.283571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4104 13:41:47.284270 ==
4105 13:41:47.284847
4106 13:41:47.285175
4107 13:41:47.287081 TX Vref Scan disable
4108 13:41:47.290184 == TX Byte 0 ==
4109 13:41:47.293795 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4110 13:41:47.296867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4111 13:41:47.300603 == TX Byte 1 ==
4112 13:41:47.303290 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4113 13:41:47.306652 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4114 13:41:47.307062
4115 13:41:47.307387 [DATLAT]
4116 13:41:47.310247 Freq=600, CH0 RK1
4117 13:41:47.310669
4118 13:41:47.310996 DATLAT Default: 0x8
4119 13:41:47.313253 0, 0xFFFF, sum = 0
4120 13:41:47.316840 1, 0xFFFF, sum = 0
4121 13:41:47.317272 2, 0xFFFF, sum = 0
4122 13:41:47.320370 3, 0xFFFF, sum = 0
4123 13:41:47.320798 4, 0xFFFF, sum = 0
4124 13:41:47.323153 5, 0xFFFF, sum = 0
4125 13:41:47.323580 6, 0xFFFF, sum = 0
4126 13:41:47.326798 7, 0x0, sum = 1
4127 13:41:47.327329 8, 0x0, sum = 2
4128 13:41:47.327773 9, 0x0, sum = 3
4129 13:41:47.329766 10, 0x0, sum = 4
4130 13:41:47.330194 best_step = 8
4131 13:41:47.330623
4132 13:41:47.331026 ==
4133 13:41:47.333199 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 13:41:47.339863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4135 13:41:47.340387 ==
4136 13:41:47.340831 RX Vref Scan: 0
4137 13:41:47.341236
4138 13:41:47.343547 RX Vref 0 -> 0, step: 1
4139 13:41:47.344065
4140 13:41:47.346625 RX Delay -195 -> 252, step: 8
4141 13:41:47.349956 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4142 13:41:47.356825 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4143 13:41:47.360121 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4144 13:41:47.363367 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4145 13:41:47.366494 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4146 13:41:47.373439 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4147 13:41:47.376771 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4148 13:41:47.380354 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4149 13:41:47.383263 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4150 13:41:47.386519 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4151 13:41:47.393067 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4152 13:41:47.396649 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4153 13:41:47.399881 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4154 13:41:47.403133 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4155 13:41:47.409559 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4156 13:41:47.413388 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4157 13:41:47.413939 ==
4158 13:41:47.416283 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 13:41:47.419916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 13:41:47.420474 ==
4161 13:41:47.422770 DQS Delay:
4162 13:41:47.423319 DQS0 = 0, DQS1 = 0
4163 13:41:47.426107 DQM Delay:
4164 13:41:47.426558 DQM0 = 40, DQM1 = 32
4165 13:41:47.426915 DQ Delay:
4166 13:41:47.429098 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4167 13:41:47.432892 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4168 13:41:47.435843 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4169 13:41:47.439146 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4170 13:41:47.439609
4171 13:41:47.440078
4172 13:41:47.449245 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4173 13:41:47.453010 CH0 RK1: MR19=808, MR18=6464
4174 13:41:47.459671 CH0_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4175 13:41:47.460226 [RxdqsGatingPostProcess] freq 600
4176 13:41:47.465994 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4177 13:41:47.469484 Pre-setting of DQS Precalculation
4178 13:41:47.472177 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4179 13:41:47.476135 ==
4180 13:41:47.478952 Dram Type= 6, Freq= 0, CH_1, rank 0
4181 13:41:47.482535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4182 13:41:47.483083 ==
4183 13:41:47.485650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4184 13:41:47.492011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4185 13:41:47.495723 [CA 0] Center 35 (5~66) winsize 62
4186 13:41:47.499548 [CA 1] Center 35 (4~66) winsize 63
4187 13:41:47.502731 [CA 2] Center 33 (3~64) winsize 62
4188 13:41:47.505707 [CA 3] Center 33 (3~64) winsize 62
4189 13:41:47.509443 [CA 4] Center 33 (2~64) winsize 63
4190 13:41:47.512440 [CA 5] Center 33 (2~64) winsize 63
4191 13:41:47.513002
4192 13:41:47.516143 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4193 13:41:47.516709
4194 13:41:47.519178 [CATrainingPosCal] consider 1 rank data
4195 13:41:47.522737 u2DelayCellTimex100 = 270/100 ps
4196 13:41:47.525619 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4197 13:41:47.532794 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4198 13:41:47.535709 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4199 13:41:47.539029 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4200 13:41:47.542631 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4201 13:41:47.545946 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4202 13:41:47.546515
4203 13:41:47.549391 CA PerBit enable=1, Macro0, CA PI delay=33
4204 13:41:47.550125
4205 13:41:47.552189 [CBTSetCACLKResult] CA Dly = 33
4206 13:41:47.555675 CS Dly: 4 (0~35)
4207 13:41:47.556089 ==
4208 13:41:47.559026 Dram Type= 6, Freq= 0, CH_1, rank 1
4209 13:41:47.562414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4210 13:41:47.563038 ==
4211 13:41:47.565333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4212 13:41:47.571830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4213 13:41:47.576613 [CA 0] Center 35 (5~66) winsize 62
4214 13:41:47.579268 [CA 1] Center 34 (4~65) winsize 62
4215 13:41:47.582761 [CA 2] Center 33 (3~64) winsize 62
4216 13:41:47.586109 [CA 3] Center 33 (3~64) winsize 62
4217 13:41:47.589345 [CA 4] Center 32 (2~63) winsize 62
4218 13:41:47.592198 [CA 5] Center 32 (2~63) winsize 62
4219 13:41:47.592650
4220 13:41:47.595723 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4221 13:41:47.596174
4222 13:41:47.599491 [CATrainingPosCal] consider 2 rank data
4223 13:41:47.602804 u2DelayCellTimex100 = 270/100 ps
4224 13:41:47.605508 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4225 13:41:47.612624 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4226 13:41:47.616373 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4227 13:41:47.619272 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4228 13:41:47.622810 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4229 13:41:47.625579 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4230 13:41:47.626033
4231 13:41:47.629272 CA PerBit enable=1, Macro0, CA PI delay=32
4232 13:41:47.629881
4233 13:41:47.632327 [CBTSetCACLKResult] CA Dly = 32
4234 13:41:47.632871 CS Dly: 5 (0~37)
4235 13:41:47.635945
4236 13:41:47.638722 ----->DramcWriteLeveling(PI) begin...
4237 13:41:47.639197 ==
4238 13:41:47.642407 Dram Type= 6, Freq= 0, CH_1, rank 0
4239 13:41:47.645780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4240 13:41:47.646236 ==
4241 13:41:47.648606 Write leveling (Byte 0): 28 => 28
4242 13:41:47.652375 Write leveling (Byte 1): 28 => 28
4243 13:41:47.655611 DramcWriteLeveling(PI) end<-----
4244 13:41:47.656061
4245 13:41:47.656566 ==
4246 13:41:47.659177 Dram Type= 6, Freq= 0, CH_1, rank 0
4247 13:41:47.662401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4248 13:41:47.662954 ==
4249 13:41:47.665768 [Gating] SW mode calibration
4250 13:41:47.671864 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4251 13:41:47.678603 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4252 13:41:47.682154 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4253 13:41:47.685188 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4254 13:41:47.692011 0 5 8 | B1->B0 | 3030 2727 | 1 0 | (1 0) (0 0)
4255 13:41:47.695508 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4256 13:41:47.698207 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 13:41:47.705087 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 13:41:47.708297 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 13:41:47.711974 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 13:41:47.718351 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 13:41:47.721477 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
4262 13:41:47.725401 0 6 8 | B1->B0 | 3434 4040 | 0 0 | (0 0) (0 0)
4263 13:41:47.731879 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 13:41:47.734939 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 13:41:47.738526 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 13:41:47.745053 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 13:41:47.748590 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 13:41:47.751290 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 13:41:47.758013 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4270 13:41:47.761547 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 13:41:47.764890 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 13:41:47.771392 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 13:41:47.774658 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 13:41:47.778173 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 13:41:47.781689 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 13:41:47.787779 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 13:41:47.791751 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 13:41:47.794482 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 13:41:47.801206 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 13:41:47.804694 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 13:41:47.808335 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 13:41:47.814500 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 13:41:47.817982 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 13:41:47.821015 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 13:41:47.827884 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 13:41:47.831396 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 13:41:47.834517 Total UI for P1: 0, mck2ui 16
4288 13:41:47.837820 best dqsien dly found for B0: ( 0, 9, 6)
4289 13:41:47.840680 Total UI for P1: 0, mck2ui 16
4290 13:41:47.844408 best dqsien dly found for B1: ( 0, 9, 6)
4291 13:41:47.847756 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4292 13:41:47.850808 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4293 13:41:47.851277
4294 13:41:47.854552 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4295 13:41:47.857362 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4296 13:41:47.861186 [Gating] SW calibration Done
4297 13:41:47.861801 ==
4298 13:41:47.863904 Dram Type= 6, Freq= 0, CH_1, rank 0
4299 13:41:47.867640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4300 13:41:47.870986 ==
4301 13:41:47.871452 RX Vref Scan: 0
4302 13:41:47.871921
4303 13:41:47.874147 RX Vref 0 -> 0, step: 1
4304 13:41:47.874612
4305 13:41:47.877825 RX Delay -230 -> 252, step: 16
4306 13:41:47.880672 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4307 13:41:47.883976 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4308 13:41:47.887194 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4309 13:41:47.893418 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4310 13:41:47.897079 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4311 13:41:47.900468 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4312 13:41:47.903710 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4313 13:41:47.910315 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4314 13:41:47.913951 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4315 13:41:47.916938 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4316 13:41:47.920688 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4317 13:41:47.923896 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4318 13:41:47.929941 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4319 13:41:47.933667 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4320 13:41:47.936616 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4321 13:41:47.940188 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4322 13:41:47.943433 ==
4323 13:41:47.946969 Dram Type= 6, Freq= 0, CH_1, rank 0
4324 13:41:47.949684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4325 13:41:47.950153 ==
4326 13:41:47.950630 DQS Delay:
4327 13:41:47.953671 DQS0 = 0, DQS1 = 0
4328 13:41:47.954241 DQM Delay:
4329 13:41:47.956423 DQM0 = 39, DQM1 = 32
4330 13:41:47.957011 DQ Delay:
4331 13:41:47.959799 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4332 13:41:47.963359 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4333 13:41:47.966318 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4334 13:41:47.969859 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4335 13:41:47.970236
4336 13:41:47.970569
4337 13:41:47.970893 ==
4338 13:41:47.972929 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 13:41:47.976117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4340 13:41:47.976419 ==
4341 13:41:47.976681
4342 13:41:47.976928
4343 13:41:47.979418 TX Vref Scan disable
4344 13:41:47.982740 == TX Byte 0 ==
4345 13:41:47.985911 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4346 13:41:47.989499 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4347 13:41:47.992836 == TX Byte 1 ==
4348 13:41:47.996157 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4349 13:41:47.999449 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4350 13:41:47.999685 ==
4351 13:41:48.002446 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 13:41:48.009131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4353 13:41:48.009419 ==
4354 13:41:48.009644
4355 13:41:48.009830
4356 13:41:48.009972 TX Vref Scan disable
4357 13:41:48.013318 == TX Byte 0 ==
4358 13:41:48.016902 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4359 13:41:48.023413 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4360 13:41:48.023700 == TX Byte 1 ==
4361 13:41:48.026937 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4362 13:41:48.033536 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4363 13:41:48.033875
4364 13:41:48.034097 [DATLAT]
4365 13:41:48.034288 Freq=600, CH1 RK0
4366 13:41:48.034463
4367 13:41:48.037162 DATLAT Default: 0x9
4368 13:41:48.037700 0, 0xFFFF, sum = 0
4369 13:41:48.040398 1, 0xFFFF, sum = 0
4370 13:41:48.040804 2, 0xFFFF, sum = 0
4371 13:41:48.043747 3, 0xFFFF, sum = 0
4372 13:41:48.046989 4, 0xFFFF, sum = 0
4373 13:41:48.047552 5, 0xFFFF, sum = 0
4374 13:41:48.050399 6, 0xFFFF, sum = 0
4375 13:41:48.050856 7, 0x0, sum = 1
4376 13:41:48.051215 8, 0x0, sum = 2
4377 13:41:48.053353 9, 0x0, sum = 3
4378 13:41:48.053808 10, 0x0, sum = 4
4379 13:41:48.056974 best_step = 8
4380 13:41:48.057554
4381 13:41:48.057909 ==
4382 13:41:48.060001 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 13:41:48.063756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4384 13:41:48.064301 ==
4385 13:41:48.066523 RX Vref Scan: 1
4386 13:41:48.066969
4387 13:41:48.067322 RX Vref 0 -> 0, step: 1
4388 13:41:48.067655
4389 13:41:48.070046 RX Delay -195 -> 252, step: 8
4390 13:41:48.070491
4391 13:41:48.073971 Set Vref, RX VrefLevel [Byte0]: 57
4392 13:41:48.076817 [Byte1]: 49
4393 13:41:48.081010
4394 13:41:48.081593 Final RX Vref Byte 0 = 57 to rank0
4395 13:41:48.084294 Final RX Vref Byte 1 = 49 to rank0
4396 13:41:48.087448 Final RX Vref Byte 0 = 57 to rank1
4397 13:41:48.090991 Final RX Vref Byte 1 = 49 to rank1==
4398 13:41:48.093878 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 13:41:48.101167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4400 13:41:48.101772 ==
4401 13:41:48.102131 DQS Delay:
4402 13:41:48.102457 DQS0 = 0, DQS1 = 0
4403 13:41:48.103910 DQM Delay:
4404 13:41:48.104354 DQM0 = 36, DQM1 = 30
4405 13:41:48.107293 DQ Delay:
4406 13:41:48.110633 DQ0 =40, DQ1 =28, DQ2 =28, DQ3 =36
4407 13:41:48.114461 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4408 13:41:48.115007 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4409 13:41:48.121143 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4410 13:41:48.121728
4411 13:41:48.122085
4412 13:41:48.127299 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4413 13:41:48.131081 CH1 RK0: MR19=808, MR18=6E6E
4414 13:41:48.137775 CH1_RK0: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4415 13:41:48.138325
4416 13:41:48.140654 ----->DramcWriteLeveling(PI) begin...
4417 13:41:48.141240 ==
4418 13:41:48.144377 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 13:41:48.147305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4420 13:41:48.147854 ==
4421 13:41:48.150539 Write leveling (Byte 0): 28 => 28
4422 13:41:48.154092 Write leveling (Byte 1): 28 => 28
4423 13:41:48.157195 DramcWriteLeveling(PI) end<-----
4424 13:41:48.157800
4425 13:41:48.158157 ==
4426 13:41:48.160982 Dram Type= 6, Freq= 0, CH_1, rank 1
4427 13:41:48.163994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4428 13:41:48.164541 ==
4429 13:41:48.167616 [Gating] SW mode calibration
4430 13:41:48.173992 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4431 13:41:48.180459 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4432 13:41:48.183569 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 13:41:48.190367 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4434 13:41:48.193380 0 5 8 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 0)
4435 13:41:48.196686 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 13:41:48.203499 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 13:41:48.206522 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 13:41:48.209983 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 13:41:48.216636 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 13:41:48.220468 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 13:41:48.223145 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4442 13:41:48.226708 0 6 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4443 13:41:48.233444 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 13:41:48.237002 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 13:41:48.239786 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 13:41:48.246284 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:41:48.249963 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:41:48.253072 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:41:48.260027 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:41:48.263562 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4451 13:41:48.266240 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:41:48.273154 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:41:48.276200 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:41:48.279918 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:41:48.286014 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:41:48.289791 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:41:48.293039 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:41:48.299702 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:41:48.302712 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:41:48.306203 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:41:48.312740 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:41:48.316101 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:41:48.319579 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:41:48.326187 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:41:48.329085 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4466 13:41:48.332702 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4467 13:41:48.335856 Total UI for P1: 0, mck2ui 16
4468 13:41:48.339558 best dqsien dly found for B1: ( 0, 9, 6)
4469 13:41:48.345978 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 13:41:48.346430 Total UI for P1: 0, mck2ui 16
4471 13:41:48.352365 best dqsien dly found for B0: ( 0, 9, 6)
4472 13:41:48.355923 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4473 13:41:48.358892 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4474 13:41:48.359343
4475 13:41:48.362496 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4476 13:41:48.365687 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4477 13:41:48.369204 [Gating] SW calibration Done
4478 13:41:48.369805 ==
4479 13:41:48.372147 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 13:41:48.375618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4481 13:41:48.376085 ==
4482 13:41:48.379120 RX Vref Scan: 0
4483 13:41:48.379618
4484 13:41:48.379980 RX Vref 0 -> 0, step: 1
4485 13:41:48.380410
4486 13:41:48.382326 RX Delay -230 -> 252, step: 16
4487 13:41:48.385280 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4488 13:41:48.392424 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4489 13:41:48.395632 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4490 13:41:48.398618 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4491 13:41:48.402170 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4492 13:41:48.408736 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4493 13:41:48.412019 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4494 13:41:48.415262 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4495 13:41:48.419107 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4496 13:41:48.422329 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4497 13:41:48.428819 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4498 13:41:48.432088 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4499 13:41:48.435593 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4500 13:41:48.438900 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4501 13:41:48.445590 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4502 13:41:48.448991 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4503 13:41:48.449544 ==
4504 13:41:48.452217 Dram Type= 6, Freq= 0, CH_1, rank 1
4505 13:41:48.455894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4506 13:41:48.456449 ==
4507 13:41:48.458586 DQS Delay:
4508 13:41:48.459098 DQS0 = 0, DQS1 = 0
4509 13:41:48.461910 DQM Delay:
4510 13:41:48.462465 DQM0 = 40, DQM1 = 34
4511 13:41:48.462823 DQ Delay:
4512 13:41:48.465347 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4513 13:41:48.468178 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4514 13:41:48.471726 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4515 13:41:48.475345 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4516 13:41:48.475796
4517 13:41:48.476146
4518 13:41:48.476491 ==
4519 13:41:48.478579 Dram Type= 6, Freq= 0, CH_1, rank 1
4520 13:41:48.485135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4521 13:41:48.485765 ==
4522 13:41:48.486242
4523 13:41:48.486681
4524 13:41:48.487221 TX Vref Scan disable
4525 13:41:48.488777 == TX Byte 0 ==
4526 13:41:48.492146 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4527 13:41:48.499081 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4528 13:41:48.499546 == TX Byte 1 ==
4529 13:41:48.502069 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 13:41:48.509365 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 13:41:48.509945 ==
4532 13:41:48.512085 Dram Type= 6, Freq= 0, CH_1, rank 1
4533 13:41:48.515586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4534 13:41:48.516151 ==
4535 13:41:48.516635
4536 13:41:48.517079
4537 13:41:48.519230 TX Vref Scan disable
4538 13:41:48.522046 == TX Byte 0 ==
4539 13:41:48.525441 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4540 13:41:48.528627 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4541 13:41:48.532231 == TX Byte 1 ==
4542 13:41:48.535095 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4543 13:41:48.538771 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4544 13:41:48.539336
4545 13:41:48.539817 [DATLAT]
4546 13:41:48.542105 Freq=600, CH1 RK1
4547 13:41:48.542573
4548 13:41:48.545550 DATLAT Default: 0x8
4549 13:41:48.546119 0, 0xFFFF, sum = 0
4550 13:41:48.548729 1, 0xFFFF, sum = 0
4551 13:41:48.549328 2, 0xFFFF, sum = 0
4552 13:41:48.552148 3, 0xFFFF, sum = 0
4553 13:41:48.552722 4, 0xFFFF, sum = 0
4554 13:41:48.555826 5, 0xFFFF, sum = 0
4555 13:41:48.556534 6, 0xFFFF, sum = 0
4556 13:41:48.558494 7, 0x0, sum = 1
4557 13:41:48.558971 8, 0x0, sum = 2
4558 13:41:48.559453 9, 0x0, sum = 3
4559 13:41:48.561617 10, 0x0, sum = 4
4560 13:41:48.562089 best_step = 8
4561 13:41:48.562561
4562 13:41:48.563004 ==
4563 13:41:48.565461 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 13:41:48.571525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4565 13:41:48.572136 ==
4566 13:41:48.572605 RX Vref Scan: 0
4567 13:41:48.573045
4568 13:41:48.575133 RX Vref 0 -> 0, step: 1
4569 13:41:48.575596
4570 13:41:48.578110 RX Delay -195 -> 252, step: 8
4571 13:41:48.581929 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4572 13:41:48.588711 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4573 13:41:48.591727 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4574 13:41:48.595238 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4575 13:41:48.597980 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4576 13:41:48.605121 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4577 13:41:48.608270 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4578 13:41:48.611663 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4579 13:41:48.614479 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4580 13:41:48.621880 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4581 13:41:48.624829 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4582 13:41:48.628207 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4583 13:41:48.630976 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4584 13:41:48.637918 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4585 13:41:48.641204 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4586 13:41:48.644520 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4587 13:41:48.644983 ==
4588 13:41:48.648039 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 13:41:48.651305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4590 13:41:48.651857 ==
4591 13:41:48.654316 DQS Delay:
4592 13:41:48.654775 DQS0 = 0, DQS1 = 0
4593 13:41:48.657581 DQM Delay:
4594 13:41:48.658040 DQM0 = 37, DQM1 = 29
4595 13:41:48.658406 DQ Delay:
4596 13:41:48.660944 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4597 13:41:48.664415 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4598 13:41:48.667785 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4599 13:41:48.671083 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4600 13:41:48.671544
4601 13:41:48.671902
4602 13:41:48.681192 [DQSOSCAuto] RK1, (LSB)MR18= 0x5757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4603 13:41:48.684058 CH1 RK1: MR19=808, MR18=5757
4604 13:41:48.690665 CH1_RK1: MR19=0x808, MR18=0x5757, DQSOSC=393, MR23=63, INC=169, DEC=113
4605 13:41:48.691126 [RxdqsGatingPostProcess] freq 600
4606 13:41:48.697511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4607 13:41:48.700707 Pre-setting of DQS Precalculation
4608 13:41:48.704444 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4609 13:41:48.714222 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4610 13:41:48.721106 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4611 13:41:48.721715
4612 13:41:48.722079
4613 13:41:48.724201 [Calibration Summary] 1200 Mbps
4614 13:41:48.724758 CH 0, Rank 0
4615 13:41:48.726933 SW Impedance : PASS
4616 13:41:48.727393 DUTY Scan : NO K
4617 13:41:48.730591 ZQ Calibration : PASS
4618 13:41:48.733579 Jitter Meter : NO K
4619 13:41:48.734036 CBT Training : PASS
4620 13:41:48.737113 Write leveling : PASS
4621 13:41:48.740618 RX DQS gating : PASS
4622 13:41:48.741166 RX DQ/DQS(RDDQC) : PASS
4623 13:41:48.744097 TX DQ/DQS : PASS
4624 13:41:48.747557 RX DATLAT : PASS
4625 13:41:48.748109 RX DQ/DQS(Engine): PASS
4626 13:41:48.750579 TX OE : NO K
4627 13:41:48.751134 All Pass.
4628 13:41:48.751497
4629 13:41:48.753632 CH 0, Rank 1
4630 13:41:48.754182 SW Impedance : PASS
4631 13:41:48.757167 DUTY Scan : NO K
4632 13:41:48.760647 ZQ Calibration : PASS
4633 13:41:48.761199 Jitter Meter : NO K
4634 13:41:48.763718 CBT Training : PASS
4635 13:41:48.767301 Write leveling : PASS
4636 13:41:48.767852 RX DQS gating : PASS
4637 13:41:48.770530 RX DQ/DQS(RDDQC) : PASS
4638 13:41:48.773552 TX DQ/DQS : PASS
4639 13:41:48.774015 RX DATLAT : PASS
4640 13:41:48.776935 RX DQ/DQS(Engine): PASS
4641 13:41:48.780601 TX OE : NO K
4642 13:41:48.781171 All Pass.
4643 13:41:48.781656
4644 13:41:48.782002 CH 1, Rank 0
4645 13:41:48.783644 SW Impedance : PASS
4646 13:41:48.786751 DUTY Scan : NO K
4647 13:41:48.787207 ZQ Calibration : PASS
4648 13:41:48.790090 Jitter Meter : NO K
4649 13:41:48.790547 CBT Training : PASS
4650 13:41:48.793513 Write leveling : PASS
4651 13:41:48.796569 RX DQS gating : PASS
4652 13:41:48.797076 RX DQ/DQS(RDDQC) : PASS
4653 13:41:48.799731 TX DQ/DQS : PASS
4654 13:41:48.803745 RX DATLAT : PASS
4655 13:41:48.804309 RX DQ/DQS(Engine): PASS
4656 13:41:48.806513 TX OE : NO K
4657 13:41:48.807037 All Pass.
4658 13:41:48.807404
4659 13:41:48.809991 CH 1, Rank 1
4660 13:41:48.810447 SW Impedance : PASS
4661 13:41:48.813018 DUTY Scan : NO K
4662 13:41:48.816995 ZQ Calibration : PASS
4663 13:41:48.817609 Jitter Meter : NO K
4664 13:41:48.819831 CBT Training : PASS
4665 13:41:48.823518 Write leveling : PASS
4666 13:41:48.824078 RX DQS gating : PASS
4667 13:41:48.826275 RX DQ/DQS(RDDQC) : PASS
4668 13:41:48.830135 TX DQ/DQS : PASS
4669 13:41:48.830700 RX DATLAT : PASS
4670 13:41:48.833467 RX DQ/DQS(Engine): PASS
4671 13:41:48.836743 TX OE : NO K
4672 13:41:48.837353 All Pass.
4673 13:41:48.837730
4674 13:41:48.838067 DramC Write-DBI off
4675 13:41:48.839997 PER_BANK_REFRESH: Hybrid Mode
4676 13:41:48.842710 TX_TRACKING: ON
4677 13:41:48.849542 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4678 13:41:48.852780 [FAST_K] Save calibration result to emmc
4679 13:41:48.859314 dramc_set_vcore_voltage set vcore to 662500
4680 13:41:48.859904 Read voltage for 933, 3
4681 13:41:48.862945 Vio18 = 0
4682 13:41:48.863496 Vcore = 662500
4683 13:41:48.863857 Vdram = 0
4684 13:41:48.866291 Vddq = 0
4685 13:41:48.866748 Vmddr = 0
4686 13:41:48.869585 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4687 13:41:48.876200 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4688 13:41:48.879175 MEM_TYPE=3, freq_sel=17
4689 13:41:48.882731 sv_algorithm_assistance_LP4_1600
4690 13:41:48.885554 ============ PULL DRAM RESETB DOWN ============
4691 13:41:48.889138 ========== PULL DRAM RESETB DOWN end =========
4692 13:41:48.895795 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4693 13:41:48.899091 ===================================
4694 13:41:48.899558 LPDDR4 DRAM CONFIGURATION
4695 13:41:48.902337 ===================================
4696 13:41:48.905403 EX_ROW_EN[0] = 0x0
4697 13:41:48.905866 EX_ROW_EN[1] = 0x0
4698 13:41:48.909006 LP4Y_EN = 0x0
4699 13:41:48.909601 WORK_FSP = 0x0
4700 13:41:48.911983 WL = 0x3
4701 13:41:48.915532 RL = 0x3
4702 13:41:48.915992 BL = 0x2
4703 13:41:48.918693 RPST = 0x0
4704 13:41:48.919244 RD_PRE = 0x0
4705 13:41:48.922266 WR_PRE = 0x1
4706 13:41:48.922811 WR_PST = 0x0
4707 13:41:48.925597 DBI_WR = 0x0
4708 13:41:48.926057 DBI_RD = 0x0
4709 13:41:48.928580 OTF = 0x1
4710 13:41:48.932238 ===================================
4711 13:41:48.935388 ===================================
4712 13:41:48.935937 ANA top config
4713 13:41:48.939036 ===================================
4714 13:41:48.941988 DLL_ASYNC_EN = 0
4715 13:41:48.945354 ALL_SLAVE_EN = 1
4716 13:41:48.945902 NEW_RANK_MODE = 1
4717 13:41:48.948912 DLL_IDLE_MODE = 1
4718 13:41:48.951671 LP45_APHY_COMB_EN = 1
4719 13:41:48.954738 TX_ODT_DIS = 1
4720 13:41:48.958088 NEW_8X_MODE = 1
4721 13:41:48.961629 ===================================
4722 13:41:48.965011 ===================================
4723 13:41:48.965653 data_rate = 1866
4724 13:41:48.968596 CKR = 1
4725 13:41:48.971581 DQ_P2S_RATIO = 8
4726 13:41:48.974518 ===================================
4727 13:41:48.978101 CA_P2S_RATIO = 8
4728 13:41:48.980974 DQ_CA_OPEN = 0
4729 13:41:48.984613 DQ_SEMI_OPEN = 0
4730 13:41:48.985072 CA_SEMI_OPEN = 0
4731 13:41:48.988169 CA_FULL_RATE = 0
4732 13:41:48.991382 DQ_CKDIV4_EN = 1
4733 13:41:48.994778 CA_CKDIV4_EN = 1
4734 13:41:48.998345 CA_PREDIV_EN = 0
4735 13:41:49.001153 PH8_DLY = 0
4736 13:41:49.001697 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4737 13:41:49.004802 DQ_AAMCK_DIV = 4
4738 13:41:49.007739 CA_AAMCK_DIV = 4
4739 13:41:49.011152 CA_ADMCK_DIV = 4
4740 13:41:49.014409 DQ_TRACK_CA_EN = 0
4741 13:41:49.017528 CA_PICK = 933
4742 13:41:49.021443 CA_MCKIO = 933
4743 13:41:49.021906 MCKIO_SEMI = 0
4744 13:41:49.024637 PLL_FREQ = 3732
4745 13:41:49.027922 DQ_UI_PI_RATIO = 32
4746 13:41:49.031283 CA_UI_PI_RATIO = 0
4747 13:41:49.034487 ===================================
4748 13:41:49.037451 ===================================
4749 13:41:49.041194 memory_type:LPDDR4
4750 13:41:49.041800 GP_NUM : 10
4751 13:41:49.044442 SRAM_EN : 1
4752 13:41:49.047620 MD32_EN : 0
4753 13:41:49.051341 ===================================
4754 13:41:49.051895 [ANA_INIT] >>>>>>>>>>>>>>
4755 13:41:49.054222 <<<<<< [CONFIGURE PHASE]: ANA_TX
4756 13:41:49.057825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4757 13:41:49.061231 ===================================
4758 13:41:49.064145 data_rate = 1866,PCW = 0X8f00
4759 13:41:49.067550 ===================================
4760 13:41:49.070939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4761 13:41:49.077144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4762 13:41:49.081148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4763 13:41:49.087232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4764 13:41:49.090298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4765 13:41:49.094195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4766 13:41:49.094742 [ANA_INIT] flow start
4767 13:41:49.097105 [ANA_INIT] PLL >>>>>>>>
4768 13:41:49.100414 [ANA_INIT] PLL <<<<<<<<
4769 13:41:49.104167 [ANA_INIT] MIDPI >>>>>>>>
4770 13:41:49.104766 [ANA_INIT] MIDPI <<<<<<<<
4771 13:41:49.106910 [ANA_INIT] DLL >>>>>>>>
4772 13:41:49.110480 [ANA_INIT] flow end
4773 13:41:49.113381 ============ LP4 DIFF to SE enter ============
4774 13:41:49.117126 ============ LP4 DIFF to SE exit ============
4775 13:41:49.120144 [ANA_INIT] <<<<<<<<<<<<<
4776 13:41:49.123639 [Flow] Enable top DCM control >>>>>
4777 13:41:49.126595 [Flow] Enable top DCM control <<<<<
4778 13:41:49.130029 Enable DLL master slave shuffle
4779 13:41:49.133484 ==============================================================
4780 13:41:49.136569 Gating Mode config
4781 13:41:49.143196 ==============================================================
4782 13:41:49.143735 Config description:
4783 13:41:49.153416 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4784 13:41:49.159629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4785 13:41:49.162979 SELPH_MODE 0: By rank 1: By Phase
4786 13:41:49.170157 ==============================================================
4787 13:41:49.172932 GAT_TRACK_EN = 1
4788 13:41:49.176724 RX_GATING_MODE = 2
4789 13:41:49.179699 RX_GATING_TRACK_MODE = 2
4790 13:41:49.183040 SELPH_MODE = 1
4791 13:41:49.186066 PICG_EARLY_EN = 1
4792 13:41:49.189603 VALID_LAT_VALUE = 1
4793 13:41:49.192808 ==============================================================
4794 13:41:49.196018 Enter into Gating configuration >>>>
4795 13:41:49.199138 Exit from Gating configuration <<<<
4796 13:41:49.202838 Enter into DVFS_PRE_config >>>>>
4797 13:41:49.215937 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4798 13:41:49.219136 Exit from DVFS_PRE_config <<<<<
4799 13:41:49.221927 Enter into PICG configuration >>>>
4800 13:41:49.225676 Exit from PICG configuration <<<<
4801 13:41:49.226371 [RX_INPUT] configuration >>>>>
4802 13:41:49.229275 [RX_INPUT] configuration <<<<<
4803 13:41:49.235377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4804 13:41:49.238763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4805 13:41:49.245243 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4806 13:41:49.252118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4807 13:41:49.258600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4808 13:41:49.265252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4809 13:41:49.268724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4810 13:41:49.271502 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4811 13:41:49.278672 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4812 13:41:49.281986 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4813 13:41:49.285089 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4814 13:41:49.288919 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4815 13:41:49.291621 ===================================
4816 13:41:49.295001 LPDDR4 DRAM CONFIGURATION
4817 13:41:49.298092 ===================================
4818 13:41:49.301729 EX_ROW_EN[0] = 0x0
4819 13:41:49.302183 EX_ROW_EN[1] = 0x0
4820 13:41:49.305119 LP4Y_EN = 0x0
4821 13:41:49.305599 WORK_FSP = 0x0
4822 13:41:49.308550 WL = 0x3
4823 13:41:49.309098 RL = 0x3
4824 13:41:49.311536 BL = 0x2
4825 13:41:49.311985 RPST = 0x0
4826 13:41:49.314680 RD_PRE = 0x0
4827 13:41:49.318075 WR_PRE = 0x1
4828 13:41:49.318642 WR_PST = 0x0
4829 13:41:49.321357 DBI_WR = 0x0
4830 13:41:49.321804 DBI_RD = 0x0
4831 13:41:49.324871 OTF = 0x1
4832 13:41:49.328307 ===================================
4833 13:41:49.331279 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4834 13:41:49.334799 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4835 13:41:49.337942 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4836 13:41:49.341566 ===================================
4837 13:41:49.345083 LPDDR4 DRAM CONFIGURATION
4838 13:41:49.348136 ===================================
4839 13:41:49.351565 EX_ROW_EN[0] = 0x10
4840 13:41:49.352135 EX_ROW_EN[1] = 0x0
4841 13:41:49.354761 LP4Y_EN = 0x0
4842 13:41:49.355305 WORK_FSP = 0x0
4843 13:41:49.358030 WL = 0x3
4844 13:41:49.358575 RL = 0x3
4845 13:41:49.360946 BL = 0x2
4846 13:41:49.361434 RPST = 0x0
4847 13:41:49.364983 RD_PRE = 0x0
4848 13:41:49.368120 WR_PRE = 0x1
4849 13:41:49.368662 WR_PST = 0x0
4850 13:41:49.370833 DBI_WR = 0x0
4851 13:41:49.371283 DBI_RD = 0x0
4852 13:41:49.374251 OTF = 0x1
4853 13:41:49.377976 ===================================
4854 13:41:49.380862 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4855 13:41:49.386331 nWR fixed to 30
4856 13:41:49.389891 [ModeRegInit_LP4] CH0 RK0
4857 13:41:49.390342 [ModeRegInit_LP4] CH0 RK1
4858 13:41:49.392932 [ModeRegInit_LP4] CH1 RK0
4859 13:41:49.396637 [ModeRegInit_LP4] CH1 RK1
4860 13:41:49.397186 match AC timing 8
4861 13:41:49.402985 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4862 13:41:49.406006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4863 13:41:49.409760 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4864 13:41:49.415967 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4865 13:41:49.419454 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4866 13:41:49.419908 ==
4867 13:41:49.422321 Dram Type= 6, Freq= 0, CH_0, rank 0
4868 13:41:49.425712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4869 13:41:49.426168 ==
4870 13:41:49.432438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4871 13:41:49.439097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4872 13:41:49.442080 [CA 0] Center 38 (8~69) winsize 62
4873 13:41:49.446091 [CA 1] Center 38 (8~69) winsize 62
4874 13:41:49.448669 [CA 2] Center 36 (5~67) winsize 63
4875 13:41:49.452176 [CA 3] Center 36 (5~67) winsize 63
4876 13:41:49.455960 [CA 4] Center 34 (4~65) winsize 62
4877 13:41:49.458651 [CA 5] Center 34 (4~65) winsize 62
4878 13:41:49.459131
4879 13:41:49.462117 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4880 13:41:49.462744
4881 13:41:49.465623 [CATrainingPosCal] consider 1 rank data
4882 13:41:49.469072 u2DelayCellTimex100 = 270/100 ps
4883 13:41:49.472002 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4884 13:41:49.475468 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4885 13:41:49.478507 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4886 13:41:49.481974 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4887 13:41:49.488600 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4888 13:41:49.491883 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4889 13:41:49.492338
4890 13:41:49.495367 CA PerBit enable=1, Macro0, CA PI delay=34
4891 13:41:49.495822
4892 13:41:49.498406 [CBTSetCACLKResult] CA Dly = 34
4893 13:41:49.498860 CS Dly: 7 (0~38)
4894 13:41:49.499216 ==
4895 13:41:49.502045 Dram Type= 6, Freq= 0, CH_0, rank 1
4896 13:41:49.508546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4897 13:41:49.509011 ==
4898 13:41:49.511627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4899 13:41:49.518481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4900 13:41:49.521582 [CA 0] Center 38 (8~69) winsize 62
4901 13:41:49.525023 [CA 1] Center 38 (7~69) winsize 63
4902 13:41:49.528147 [CA 2] Center 36 (5~67) winsize 63
4903 13:41:49.531791 [CA 3] Center 35 (5~66) winsize 62
4904 13:41:49.534909 [CA 4] Center 34 (4~65) winsize 62
4905 13:41:49.538101 [CA 5] Center 34 (4~65) winsize 62
4906 13:41:49.538565
4907 13:41:49.541225 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4908 13:41:49.541741
4909 13:41:49.544833 [CATrainingPosCal] consider 2 rank data
4910 13:41:49.547908 u2DelayCellTimex100 = 270/100 ps
4911 13:41:49.551528 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4912 13:41:49.555059 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4913 13:41:49.561491 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4914 13:41:49.564435 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4915 13:41:49.567972 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4916 13:41:49.570985 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4917 13:41:49.571441
4918 13:41:49.574391 CA PerBit enable=1, Macro0, CA PI delay=34
4919 13:41:49.574772
4920 13:41:49.577663 [CBTSetCACLKResult] CA Dly = 34
4921 13:41:49.578117 CS Dly: 7 (0~39)
4922 13:41:49.578474
4923 13:41:49.581353 ----->DramcWriteLeveling(PI) begin...
4924 13:41:49.584545 ==
4925 13:41:49.587852 Dram Type= 6, Freq= 0, CH_0, rank 0
4926 13:41:49.591220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4927 13:41:49.591676 ==
4928 13:41:49.594377 Write leveling (Byte 0): 31 => 31
4929 13:41:49.597802 Write leveling (Byte 1): 28 => 28
4930 13:41:49.601241 DramcWriteLeveling(PI) end<-----
4931 13:41:49.602010
4932 13:41:49.602445 ==
4933 13:41:49.604259 Dram Type= 6, Freq= 0, CH_0, rank 0
4934 13:41:49.607958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4935 13:41:49.608368 ==
4936 13:41:49.611179 [Gating] SW mode calibration
4937 13:41:49.617699 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4938 13:41:49.624145 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4939 13:41:49.627630 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4940 13:41:49.630961 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4941 13:41:49.637737 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4942 13:41:49.640725 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4943 13:41:49.643920 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4944 13:41:49.650589 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4945 13:41:49.654138 0 10 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4946 13:41:49.657269 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4947 13:41:49.663900 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4948 13:41:49.666952 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4949 13:41:49.670298 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4950 13:41:49.676814 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4951 13:41:49.680292 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4952 13:41:49.684284 0 11 20 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (0 0)
4953 13:41:49.689809 0 11 24 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
4954 13:41:49.693638 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4955 13:41:49.697139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4956 13:41:49.703456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4957 13:41:49.706460 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4958 13:41:49.709985 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4959 13:41:49.716579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4960 13:41:49.720300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4961 13:41:49.723382 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4962 13:41:49.729653 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4963 13:41:49.733209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4964 13:41:49.736793 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4965 13:41:49.743398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4966 13:41:49.746839 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4967 13:41:49.749946 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4968 13:41:49.753639 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4969 13:41:49.760135 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4970 13:41:49.763062 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4971 13:41:49.766412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4972 13:41:49.772832 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4973 13:41:49.776701 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4974 13:41:49.779501 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4975 13:41:49.785933 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4976 13:41:49.789547 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4977 13:41:49.793064 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4978 13:41:49.796277 Total UI for P1: 0, mck2ui 16
4979 13:41:49.799802 best dqsien dly found for B0: ( 0, 14, 18)
4980 13:41:49.802495 Total UI for P1: 0, mck2ui 16
4981 13:41:49.806018 best dqsien dly found for B1: ( 0, 14, 20)
4982 13:41:49.809489 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4983 13:41:49.816155 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4984 13:41:49.816615
4985 13:41:49.818954 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4986 13:41:49.822925 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4987 13:41:49.825727 [Gating] SW calibration Done
4988 13:41:49.826179 ==
4989 13:41:49.829664 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 13:41:49.832324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 13:41:49.832780 ==
4992 13:41:49.836081 RX Vref Scan: 0
4993 13:41:49.836640
4994 13:41:49.836997 RX Vref 0 -> 0, step: 1
4995 13:41:49.837382
4996 13:41:49.839477 RX Delay -80 -> 252, step: 8
4997 13:41:49.842568 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4998 13:41:49.846202 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4999 13:41:49.852702 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5000 13:41:49.855757 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5001 13:41:49.859339 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5002 13:41:49.862107 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5003 13:41:49.865908 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5004 13:41:49.869348 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5005 13:41:49.875541 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5006 13:41:49.879172 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5007 13:41:49.882660 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5008 13:41:49.885918 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5009 13:41:49.892340 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5010 13:41:49.895715 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5011 13:41:49.898867 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5012 13:41:49.902168 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5013 13:41:49.902631 ==
5014 13:41:49.905597 Dram Type= 6, Freq= 0, CH_0, rank 0
5015 13:41:49.908862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5016 13:41:49.909454 ==
5017 13:41:49.912014 DQS Delay:
5018 13:41:49.912474 DQS0 = 0, DQS1 = 0
5019 13:41:49.915332 DQM Delay:
5020 13:41:49.915788 DQM0 = 95, DQM1 = 84
5021 13:41:49.916152 DQ Delay:
5022 13:41:49.918810 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5023 13:41:49.921977 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5024 13:41:49.925468 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5025 13:41:49.929055 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5026 13:41:49.929694
5027 13:41:49.931945
5028 13:41:49.932479 ==
5029 13:41:49.935670 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 13:41:49.938606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5031 13:41:49.939069 ==
5032 13:41:49.939430
5033 13:41:49.939766
5034 13:41:49.942037 TX Vref Scan disable
5035 13:41:49.942497 == TX Byte 0 ==
5036 13:41:49.948799 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5037 13:41:49.951794 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5038 13:41:49.952342 == TX Byte 1 ==
5039 13:41:49.958140 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5040 13:41:49.961662 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5041 13:41:49.962116 ==
5042 13:41:49.964934 Dram Type= 6, Freq= 0, CH_0, rank 0
5043 13:41:49.968565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5044 13:41:49.969108 ==
5045 13:41:49.969573
5046 13:41:49.969915
5047 13:41:49.971249 TX Vref Scan disable
5048 13:41:49.974766 == TX Byte 0 ==
5049 13:41:49.978534 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5050 13:41:49.981354 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5051 13:41:49.984912 == TX Byte 1 ==
5052 13:41:49.987905 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5053 13:41:49.991574 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5054 13:41:49.992035
5055 13:41:49.994662 [DATLAT]
5056 13:41:49.995250 Freq=933, CH0 RK0
5057 13:41:49.995620
5058 13:41:49.997854 DATLAT Default: 0xd
5059 13:41:49.998311 0, 0xFFFF, sum = 0
5060 13:41:50.001769 1, 0xFFFF, sum = 0
5061 13:41:50.002333 2, 0xFFFF, sum = 0
5062 13:41:50.004495 3, 0xFFFF, sum = 0
5063 13:41:50.004970 4, 0xFFFF, sum = 0
5064 13:41:50.008121 5, 0xFFFF, sum = 0
5065 13:41:50.008693 6, 0xFFFF, sum = 0
5066 13:41:50.010887 7, 0xFFFF, sum = 0
5067 13:41:50.011343 8, 0xFFFF, sum = 0
5068 13:41:50.014232 9, 0xFFFF, sum = 0
5069 13:41:50.014701 10, 0x0, sum = 1
5070 13:41:50.017517 11, 0x0, sum = 2
5071 13:41:50.017982 12, 0x0, sum = 3
5072 13:41:50.021030 13, 0x0, sum = 4
5073 13:41:50.021543 best_step = 11
5074 13:41:50.021972
5075 13:41:50.022320 ==
5076 13:41:50.024377 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 13:41:50.031116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5078 13:41:50.031674 ==
5079 13:41:50.032034 RX Vref Scan: 1
5080 13:41:50.032367
5081 13:41:50.034217 RX Vref 0 -> 0, step: 1
5082 13:41:50.034668
5083 13:41:50.037738 RX Delay -77 -> 252, step: 4
5084 13:41:50.038191
5085 13:41:50.040866 Set Vref, RX VrefLevel [Byte0]: 46
5086 13:41:50.043839 [Byte1]: 50
5087 13:41:50.044328
5088 13:41:50.047539 Final RX Vref Byte 0 = 46 to rank0
5089 13:41:50.050831 Final RX Vref Byte 1 = 50 to rank0
5090 13:41:50.054220 Final RX Vref Byte 0 = 46 to rank1
5091 13:41:50.057568 Final RX Vref Byte 1 = 50 to rank1==
5092 13:41:50.060619 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 13:41:50.064285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5094 13:41:50.067044 ==
5095 13:41:50.067500 DQS Delay:
5096 13:41:50.067854 DQS0 = 0, DQS1 = 0
5097 13:41:50.070488 DQM Delay:
5098 13:41:50.070968 DQM0 = 97, DQM1 = 87
5099 13:41:50.071319 DQ Delay:
5100 13:41:50.073931 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =94
5101 13:41:50.076856 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =104
5102 13:41:50.080372 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5103 13:41:50.086933 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5104 13:41:50.087469
5105 13:41:50.087826
5106 13:41:50.093797 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5107 13:41:50.097476 CH0 RK0: MR19=505, MR18=2525
5108 13:41:50.103278 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5109 13:41:50.103828
5110 13:41:50.106831 ----->DramcWriteLeveling(PI) begin...
5111 13:41:50.107298 ==
5112 13:41:50.109952 Dram Type= 6, Freq= 0, CH_0, rank 1
5113 13:41:50.113689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5114 13:41:50.114257 ==
5115 13:41:50.117348 Write leveling (Byte 0): 30 => 30
5116 13:41:50.120336 Write leveling (Byte 1): 25 => 25
5117 13:41:50.123881 DramcWriteLeveling(PI) end<-----
5118 13:41:50.124438
5119 13:41:50.124798 ==
5120 13:41:50.126574 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 13:41:50.130140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5122 13:41:50.130699 ==
5123 13:41:50.133471 [Gating] SW mode calibration
5124 13:41:50.140028 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 13:41:50.146409 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5126 13:41:50.149679 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 13:41:50.156530 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 13:41:50.160027 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 13:41:50.162960 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 13:41:50.166734 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5131 13:41:50.173182 0 10 20 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5132 13:41:50.176258 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 13:41:50.179955 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 13:41:50.186490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 13:41:50.190146 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 13:41:50.193730 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 13:41:50.200238 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:41:50.203185 0 11 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5139 13:41:50.206345 0 11 20 | B1->B0 | 2e2d 3a3a | 1 0 | (0 0) (0 0)
5140 13:41:50.213571 0 11 24 | B1->B0 | 3c3c 4241 | 0 1 | (0 0) (1 1)
5141 13:41:50.216397 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 13:41:50.220056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 13:41:50.226348 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 13:41:50.229676 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:41:50.232895 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:41:50.239077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:41:50.242431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5148 13:41:50.245998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5149 13:41:50.252625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:41:50.256058 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:41:50.259255 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:41:50.265976 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:41:50.269670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:41:50.272392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:41:50.278986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:41:50.282381 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:41:50.285498 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:41:50.292375 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:41:50.295598 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:41:50.298834 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:41:50.306012 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:41:50.308663 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:41:50.312339 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5164 13:41:50.318614 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5165 13:41:50.319074 Total UI for P1: 0, mck2ui 16
5166 13:41:50.325612 best dqsien dly found for B0: ( 0, 14, 20)
5167 13:41:50.328745 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 13:41:50.331980 Total UI for P1: 0, mck2ui 16
5169 13:41:50.335242 best dqsien dly found for B1: ( 0, 14, 24)
5170 13:41:50.338748 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5171 13:41:50.342171 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5172 13:41:50.342722
5173 13:41:50.345181 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5174 13:41:50.348970 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5175 13:41:50.352155 [Gating] SW calibration Done
5176 13:41:50.352700 ==
5177 13:41:50.355313 Dram Type= 6, Freq= 0, CH_0, rank 1
5178 13:41:50.358383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5179 13:41:50.361851 ==
5180 13:41:50.362403 RX Vref Scan: 0
5181 13:41:50.362791
5182 13:41:50.365047 RX Vref 0 -> 0, step: 1
5183 13:41:50.365540
5184 13:41:50.368247 RX Delay -80 -> 252, step: 8
5185 13:41:50.371808 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5186 13:41:50.375315 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5187 13:41:50.378730 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5188 13:41:50.381541 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5189 13:41:50.384620 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5190 13:41:50.391275 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5191 13:41:50.394951 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5192 13:41:50.398163 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5193 13:41:50.401854 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5194 13:41:50.404945 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5195 13:41:50.411349 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5196 13:41:50.414477 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5197 13:41:50.417920 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5198 13:41:50.421478 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5199 13:41:50.424558 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5200 13:41:50.428330 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5201 13:41:50.431127 ==
5202 13:41:50.434605 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 13:41:50.437576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 13:41:50.438028 ==
5205 13:41:50.438384 DQS Delay:
5206 13:41:50.441064 DQS0 = 0, DQS1 = 0
5207 13:41:50.441617 DQM Delay:
5208 13:41:50.444457 DQM0 = 95, DQM1 = 85
5209 13:41:50.444904 DQ Delay:
5210 13:41:50.448143 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5211 13:41:50.451209 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5212 13:41:50.454590 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =75
5213 13:41:50.458009 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5214 13:41:50.458461
5215 13:41:50.458815
5216 13:41:50.459140 ==
5217 13:41:50.461278 Dram Type= 6, Freq= 0, CH_0, rank 1
5218 13:41:50.464158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5219 13:41:50.464610 ==
5220 13:41:50.464960
5221 13:41:50.465318
5222 13:41:50.467687 TX Vref Scan disable
5223 13:41:50.471122 == TX Byte 0 ==
5224 13:41:50.474330 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5225 13:41:50.477560 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5226 13:41:50.480628 == TX Byte 1 ==
5227 13:41:50.484540 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5228 13:41:50.487675 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5229 13:41:50.488347 ==
5230 13:41:50.491031 Dram Type= 6, Freq= 0, CH_0, rank 1
5231 13:41:50.497846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5232 13:41:50.498402 ==
5233 13:41:50.498759
5234 13:41:50.499088
5235 13:41:50.499401 TX Vref Scan disable
5236 13:41:50.501685 == TX Byte 0 ==
5237 13:41:50.504589 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5238 13:41:50.511212 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5239 13:41:50.511667 == TX Byte 1 ==
5240 13:41:50.514426 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5241 13:41:50.521056 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5242 13:41:50.521548
5243 13:41:50.521902 [DATLAT]
5244 13:41:50.522226 Freq=933, CH0 RK1
5245 13:41:50.522543
5246 13:41:50.524650 DATLAT Default: 0xb
5247 13:41:50.525099 0, 0xFFFF, sum = 0
5248 13:41:50.528007 1, 0xFFFF, sum = 0
5249 13:41:50.531063 2, 0xFFFF, sum = 0
5250 13:41:50.531571 3, 0xFFFF, sum = 0
5251 13:41:50.534651 4, 0xFFFF, sum = 0
5252 13:41:50.535106 5, 0xFFFF, sum = 0
5253 13:41:50.537650 6, 0xFFFF, sum = 0
5254 13:41:50.538105 7, 0xFFFF, sum = 0
5255 13:41:50.541540 8, 0xFFFF, sum = 0
5256 13:41:50.542098 9, 0xFFFF, sum = 0
5257 13:41:50.544786 10, 0x0, sum = 1
5258 13:41:50.545244 11, 0x0, sum = 2
5259 13:41:50.547541 12, 0x0, sum = 3
5260 13:41:50.548009 13, 0x0, sum = 4
5261 13:41:50.548368 best_step = 11
5262 13:41:50.548697
5263 13:41:50.551373 ==
5264 13:41:50.554848 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 13:41:50.557509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5266 13:41:50.557967 ==
5267 13:41:50.558324 RX Vref Scan: 0
5268 13:41:50.558658
5269 13:41:50.561216 RX Vref 0 -> 0, step: 1
5270 13:41:50.561694
5271 13:41:50.564555 RX Delay -69 -> 252, step: 4
5272 13:41:50.567714 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5273 13:41:50.574175 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5274 13:41:50.577717 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5275 13:41:50.581140 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5276 13:41:50.584273 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5277 13:41:50.587560 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5278 13:41:50.590939 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5279 13:41:50.598165 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5280 13:41:50.601024 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5281 13:41:50.604642 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5282 13:41:50.607421 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5283 13:41:50.611020 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5284 13:41:50.617277 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5285 13:41:50.620718 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5286 13:41:50.624179 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5287 13:41:50.627368 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5288 13:41:50.627824 ==
5289 13:41:50.630908 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 13:41:50.633925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 13:41:50.637723 ==
5292 13:41:50.638177 DQS Delay:
5293 13:41:50.638535 DQS0 = 0, DQS1 = 0
5294 13:41:50.640298 DQM Delay:
5295 13:41:50.640748 DQM0 = 97, DQM1 = 86
5296 13:41:50.644002 DQ Delay:
5297 13:41:50.646927 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5298 13:41:50.650374 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5299 13:41:50.653611 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5300 13:41:50.657062 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5301 13:41:50.657544
5302 13:41:50.657874
5303 13:41:50.663802 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5304 13:41:50.666868 CH0 RK1: MR19=505, MR18=2727
5305 13:41:50.673887 CH0_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5306 13:41:50.677071 [RxdqsGatingPostProcess] freq 933
5307 13:41:50.680073 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5308 13:41:50.683540 Pre-setting of DQS Precalculation
5309 13:41:50.689901 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5310 13:41:50.690466 ==
5311 13:41:50.693611 Dram Type= 6, Freq= 0, CH_1, rank 0
5312 13:41:50.696644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5313 13:41:50.697117 ==
5314 13:41:50.703699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5315 13:41:50.709660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5316 13:41:50.713257 [CA 0] Center 37 (7~68) winsize 62
5317 13:41:50.716179 [CA 1] Center 37 (6~68) winsize 63
5318 13:41:50.719681 [CA 2] Center 34 (4~65) winsize 62
5319 13:41:50.723222 [CA 3] Center 34 (3~65) winsize 63
5320 13:41:50.726152 [CA 4] Center 33 (2~64) winsize 63
5321 13:41:50.729510 [CA 5] Center 33 (2~64) winsize 63
5322 13:41:50.729918
5323 13:41:50.733006 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5324 13:41:50.733598
5325 13:41:50.736279 [CATrainingPosCal] consider 1 rank data
5326 13:41:50.739951 u2DelayCellTimex100 = 270/100 ps
5327 13:41:50.743201 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5328 13:41:50.746329 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5329 13:41:50.749615 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5330 13:41:50.753055 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5331 13:41:50.755987 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5332 13:41:50.759328 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5333 13:41:50.759777
5334 13:41:50.765729 CA PerBit enable=1, Macro0, CA PI delay=33
5335 13:41:50.766183
5336 13:41:50.766535 [CBTSetCACLKResult] CA Dly = 33
5337 13:41:50.769008 CS Dly: 5 (0~36)
5338 13:41:50.769119 ==
5339 13:41:50.772365 Dram Type= 6, Freq= 0, CH_1, rank 1
5340 13:41:50.775928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5341 13:41:50.776404 ==
5342 13:41:50.782674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5343 13:41:50.789184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5344 13:41:50.792432 [CA 0] Center 37 (7~67) winsize 61
5345 13:41:50.795928 [CA 1] Center 37 (6~68) winsize 63
5346 13:41:50.799739 [CA 2] Center 34 (4~65) winsize 62
5347 13:41:50.802286 [CA 3] Center 34 (4~64) winsize 61
5348 13:41:50.806007 [CA 4] Center 32 (2~63) winsize 62
5349 13:41:50.809457 [CA 5] Center 32 (2~63) winsize 62
5350 13:41:50.809946
5351 13:41:50.812432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5352 13:41:50.812884
5353 13:41:50.815913 [CATrainingPosCal] consider 2 rank data
5354 13:41:50.819129 u2DelayCellTimex100 = 270/100 ps
5355 13:41:50.822552 CA0 delay=37 (7~67),Diff = 5 PI (31 cell)
5356 13:41:50.825486 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5357 13:41:50.829342 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5358 13:41:50.832749 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5359 13:41:50.835558 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5360 13:41:50.842215 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5361 13:41:50.842750
5362 13:41:50.845885 CA PerBit enable=1, Macro0, CA PI delay=32
5363 13:41:50.846432
5364 13:41:50.848620 [CBTSetCACLKResult] CA Dly = 32
5365 13:41:50.849069 CS Dly: 5 (0~37)
5366 13:41:50.849453
5367 13:41:50.852206 ----->DramcWriteLeveling(PI) begin...
5368 13:41:50.852756 ==
5369 13:41:50.855415 Dram Type= 6, Freq= 0, CH_1, rank 0
5370 13:41:50.862159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5371 13:41:50.862613 ==
5372 13:41:50.865410 Write leveling (Byte 0): 25 => 25
5373 13:41:50.865857 Write leveling (Byte 1): 25 => 25
5374 13:41:50.868716 DramcWriteLeveling(PI) end<-----
5375 13:41:50.869260
5376 13:41:50.869675 ==
5377 13:41:50.872284 Dram Type= 6, Freq= 0, CH_1, rank 0
5378 13:41:50.878919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5379 13:41:50.879467 ==
5380 13:41:50.881924 [Gating] SW mode calibration
5381 13:41:50.888519 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5382 13:41:50.892324 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5383 13:41:50.898704 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 13:41:50.901801 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 13:41:50.905168 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 13:41:50.911703 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 13:41:50.915040 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
5388 13:41:50.918829 0 10 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
5389 13:41:50.925035 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5390 13:41:50.928080 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 13:41:50.931561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 13:41:50.938077 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 13:41:50.941825 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 13:41:50.944633 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 13:41:50.951541 0 11 16 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5396 13:41:50.954876 0 11 20 | B1->B0 | 2a2a 4545 | 1 0 | (0 0) (0 0)
5397 13:41:50.957711 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5398 13:41:50.964639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 13:41:50.968018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 13:41:50.971665 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 13:41:50.978101 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 13:41:50.981002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 13:41:50.984533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5404 13:41:50.988394 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5405 13:41:50.994183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 13:41:50.998173 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 13:41:51.000978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 13:41:51.007799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 13:41:51.011121 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 13:41:51.013998 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 13:41:51.020911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 13:41:51.024351 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 13:41:51.027734 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 13:41:51.033852 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 13:41:51.037597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 13:41:51.041383 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 13:41:51.046944 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 13:41:51.050350 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 13:41:51.054008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5420 13:41:51.060905 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 13:41:51.063806 Total UI for P1: 0, mck2ui 16
5422 13:41:51.067200 best dqsien dly found for B0: ( 0, 14, 16)
5423 13:41:51.070542 Total UI for P1: 0, mck2ui 16
5424 13:41:51.073442 best dqsien dly found for B1: ( 0, 14, 18)
5425 13:41:51.077246 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5426 13:41:51.080326 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5427 13:41:51.080653
5428 13:41:51.083223 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5429 13:41:51.087339 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5430 13:41:51.090222 [Gating] SW calibration Done
5431 13:41:51.090783 ==
5432 13:41:51.093677 Dram Type= 6, Freq= 0, CH_1, rank 0
5433 13:41:51.097335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5434 13:41:51.097913 ==
5435 13:41:51.100211 RX Vref Scan: 0
5436 13:41:51.100775
5437 13:41:51.103222 RX Vref 0 -> 0, step: 1
5438 13:41:51.103699
5439 13:41:51.104174 RX Delay -80 -> 252, step: 8
5440 13:41:51.110262 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5441 13:41:51.113589 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5442 13:41:51.117136 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5443 13:41:51.119907 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5444 13:41:51.123829 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5445 13:41:51.130140 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5446 13:41:51.133347 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5447 13:41:51.136663 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5448 13:41:51.139979 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5449 13:41:51.143148 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5450 13:41:51.146604 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5451 13:41:51.153257 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5452 13:41:51.156685 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5453 13:41:51.159454 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5454 13:41:51.162882 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5455 13:41:51.166396 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5456 13:41:51.169395 ==
5457 13:41:51.173049 Dram Type= 6, Freq= 0, CH_1, rank 0
5458 13:41:51.176432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5459 13:41:51.176899 ==
5460 13:41:51.177258 DQS Delay:
5461 13:41:51.179476 DQS0 = 0, DQS1 = 0
5462 13:41:51.179933 DQM Delay:
5463 13:41:51.182912 DQM0 = 94, DQM1 = 86
5464 13:41:51.183369 DQ Delay:
5465 13:41:51.186380 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5466 13:41:51.189557 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5467 13:41:51.192860 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5468 13:41:51.195893 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =95
5469 13:41:51.196350
5470 13:41:51.196708
5471 13:41:51.197043 ==
5472 13:41:51.199776 Dram Type= 6, Freq= 0, CH_1, rank 0
5473 13:41:51.202499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5474 13:41:51.202978 ==
5475 13:41:51.203342
5476 13:41:51.203673
5477 13:41:51.206025 TX Vref Scan disable
5478 13:41:51.209676 == TX Byte 0 ==
5479 13:41:51.212443 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5480 13:41:51.215961 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5481 13:41:51.218865 == TX Byte 1 ==
5482 13:41:51.222498 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5483 13:41:51.225627 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5484 13:41:51.226106 ==
5485 13:41:51.229352 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 13:41:51.236088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5487 13:41:51.236660 ==
5488 13:41:51.237154
5489 13:41:51.237650
5490 13:41:51.238097 TX Vref Scan disable
5491 13:41:51.239969 == TX Byte 0 ==
5492 13:41:51.243149 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5493 13:41:51.250029 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5494 13:41:51.250585 == TX Byte 1 ==
5495 13:41:51.253089 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5496 13:41:51.259521 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5497 13:41:51.260123
5498 13:41:51.260722 [DATLAT]
5499 13:41:51.261269 Freq=933, CH1 RK0
5500 13:41:51.261819
5501 13:41:51.262826 DATLAT Default: 0xd
5502 13:41:51.263384 0, 0xFFFF, sum = 0
5503 13:41:51.265992 1, 0xFFFF, sum = 0
5504 13:41:51.266456 2, 0xFFFF, sum = 0
5505 13:41:51.269677 3, 0xFFFF, sum = 0
5506 13:41:51.272602 4, 0xFFFF, sum = 0
5507 13:41:51.273174 5, 0xFFFF, sum = 0
5508 13:41:51.276494 6, 0xFFFF, sum = 0
5509 13:41:51.276950 7, 0xFFFF, sum = 0
5510 13:41:51.279232 8, 0xFFFF, sum = 0
5511 13:41:51.279691 9, 0xFFFF, sum = 0
5512 13:41:51.282527 10, 0x0, sum = 1
5513 13:41:51.283018 11, 0x0, sum = 2
5514 13:41:51.286097 12, 0x0, sum = 3
5515 13:41:51.286552 13, 0x0, sum = 4
5516 13:41:51.286910 best_step = 11
5517 13:41:51.287236
5518 13:41:51.289627 ==
5519 13:41:51.292964 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 13:41:51.296380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 13:41:51.296832 ==
5522 13:41:51.297199 RX Vref Scan: 1
5523 13:41:51.297598
5524 13:41:51.299818 RX Vref 0 -> 0, step: 1
5525 13:41:51.300372
5526 13:41:51.302686 RX Delay -69 -> 252, step: 4
5527 13:41:51.303138
5528 13:41:51.306305 Set Vref, RX VrefLevel [Byte0]: 57
5529 13:41:51.309335 [Byte1]: 49
5530 13:41:51.309792
5531 13:41:51.312653 Final RX Vref Byte 0 = 57 to rank0
5532 13:41:51.315924 Final RX Vref Byte 1 = 49 to rank0
5533 13:41:51.319106 Final RX Vref Byte 0 = 57 to rank1
5534 13:41:51.322543 Final RX Vref Byte 1 = 49 to rank1==
5535 13:41:51.326066 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 13:41:51.328976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5537 13:41:51.332418 ==
5538 13:41:51.332960 DQS Delay:
5539 13:41:51.333393 DQS0 = 0, DQS1 = 0
5540 13:41:51.336181 DQM Delay:
5541 13:41:51.336727 DQM0 = 94, DQM1 = 88
5542 13:41:51.338979 DQ Delay:
5543 13:41:51.342768 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5544 13:41:51.345639 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5545 13:41:51.346178 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5546 13:41:51.352862 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5547 13:41:51.353452
5548 13:41:51.353813
5549 13:41:51.359397 [DQSOSCAuto] RK0, (LSB)MR18= 0x3030, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5550 13:41:51.362334 CH1 RK0: MR19=505, MR18=3030
5551 13:41:51.368951 CH1_RK0: MR19=0x505, MR18=0x3030, DQSOSC=406, MR23=63, INC=65, DEC=43
5552 13:41:51.369440
5553 13:41:51.372307 ----->DramcWriteLeveling(PI) begin...
5554 13:41:51.372863 ==
5555 13:41:51.375646 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 13:41:51.378979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5557 13:41:51.379437 ==
5558 13:41:51.382415 Write leveling (Byte 0): 23 => 23
5559 13:41:51.385649 Write leveling (Byte 1): 24 => 24
5560 13:41:51.389371 DramcWriteLeveling(PI) end<-----
5561 13:41:51.389927
5562 13:41:51.390304 ==
5563 13:41:51.392161 Dram Type= 6, Freq= 0, CH_1, rank 1
5564 13:41:51.395704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5565 13:41:51.396162 ==
5566 13:41:51.399415 [Gating] SW mode calibration
5567 13:41:51.405458 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5568 13:41:51.412679 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5569 13:41:51.415187 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 13:41:51.418998 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 13:41:51.425498 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 13:41:51.428769 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5573 13:41:51.432291 0 10 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
5574 13:41:51.438808 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5575 13:41:51.441640 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 13:41:51.445553 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 13:41:51.452088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 13:41:51.455417 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 13:41:51.458343 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 13:41:51.465044 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5581 13:41:51.468707 0 11 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5582 13:41:51.471515 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5583 13:41:51.478580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 13:41:51.481706 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 13:41:51.484861 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 13:41:51.491328 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 13:41:51.495105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 13:41:51.498389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 13:41:51.504840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5590 13:41:51.508486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5591 13:41:51.511216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 13:41:51.518231 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 13:41:51.521101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 13:41:51.524999 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:41:51.530945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:41:51.534625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:41:51.537888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:41:51.544601 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:41:51.548037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:41:51.551054 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 13:41:51.557442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 13:41:51.560948 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 13:41:51.563902 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 13:41:51.570962 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:41:51.574055 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5606 13:41:51.577651 Total UI for P1: 0, mck2ui 16
5607 13:41:51.580732 best dqsien dly found for B0: ( 0, 14, 14)
5608 13:41:51.584216 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 13:41:51.587251 Total UI for P1: 0, mck2ui 16
5610 13:41:51.590569 best dqsien dly found for B1: ( 0, 14, 16)
5611 13:41:51.593922 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5612 13:41:51.597052 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5613 13:41:51.600717
5614 13:41:51.603907 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5615 13:41:51.607363 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5616 13:41:51.610717 [Gating] SW calibration Done
5617 13:41:51.611267 ==
5618 13:41:51.613789 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 13:41:51.616561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5620 13:41:51.617016 ==
5621 13:41:51.617428 RX Vref Scan: 0
5622 13:41:51.620554
5623 13:41:51.621098 RX Vref 0 -> 0, step: 1
5624 13:41:51.621532
5625 13:41:51.623559 RX Delay -80 -> 252, step: 8
5626 13:41:51.626877 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5627 13:41:51.630155 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5628 13:41:51.636895 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5629 13:41:51.639931 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5630 13:41:51.643173 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5631 13:41:51.646427 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5632 13:41:51.649877 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5633 13:41:51.653510 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5634 13:41:51.660233 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5635 13:41:51.662865 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5636 13:41:51.666440 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5637 13:41:51.670292 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5638 13:41:51.676105 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5639 13:41:51.679869 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5640 13:41:51.683445 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5641 13:41:51.685998 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5642 13:41:51.686452 ==
5643 13:41:51.689708 Dram Type= 6, Freq= 0, CH_1, rank 1
5644 13:41:51.692910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5645 13:41:51.696114 ==
5646 13:41:51.696564 DQS Delay:
5647 13:41:51.696917 DQS0 = 0, DQS1 = 0
5648 13:41:51.699787 DQM Delay:
5649 13:41:51.700330 DQM0 = 95, DQM1 = 85
5650 13:41:51.702675 DQ Delay:
5651 13:41:51.706245 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5652 13:41:51.709338 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5653 13:41:51.709894 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5654 13:41:51.716230 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =91
5655 13:41:51.716767
5656 13:41:51.717118
5657 13:41:51.717512 ==
5658 13:41:51.719110 Dram Type= 6, Freq= 0, CH_1, rank 1
5659 13:41:51.722779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5660 13:41:51.723249 ==
5661 13:41:51.723602
5662 13:41:51.723929
5663 13:41:51.726056 TX Vref Scan disable
5664 13:41:51.726507 == TX Byte 0 ==
5665 13:41:51.732687 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5666 13:41:51.735780 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5667 13:41:51.736329 == TX Byte 1 ==
5668 13:41:51.742918 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5669 13:41:51.745604 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5670 13:41:51.746057 ==
5671 13:41:51.749131 Dram Type= 6, Freq= 0, CH_1, rank 1
5672 13:41:51.752340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5673 13:41:51.752892 ==
5674 13:41:51.753249
5675 13:41:51.755734
5676 13:41:51.756177 TX Vref Scan disable
5677 13:41:51.759392 == TX Byte 0 ==
5678 13:41:51.762167 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5679 13:41:51.765462 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5680 13:41:51.769209 == TX Byte 1 ==
5681 13:41:51.772099 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5682 13:41:51.775637 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5683 13:41:51.778586
5684 13:41:51.779032 [DATLAT]
5685 13:41:51.779383 Freq=933, CH1 RK1
5686 13:41:51.779712
5687 13:41:51.782125 DATLAT Default: 0xb
5688 13:41:51.782576 0, 0xFFFF, sum = 0
5689 13:41:51.785137 1, 0xFFFF, sum = 0
5690 13:41:51.785744 2, 0xFFFF, sum = 0
5691 13:41:51.788862 3, 0xFFFF, sum = 0
5692 13:41:51.789517 4, 0xFFFF, sum = 0
5693 13:41:51.792092 5, 0xFFFF, sum = 0
5694 13:41:51.794939 6, 0xFFFF, sum = 0
5695 13:41:51.795398 7, 0xFFFF, sum = 0
5696 13:41:51.798365 8, 0xFFFF, sum = 0
5697 13:41:51.798825 9, 0xFFFF, sum = 0
5698 13:41:51.801910 10, 0x0, sum = 1
5699 13:41:51.802371 11, 0x0, sum = 2
5700 13:41:51.805358 12, 0x0, sum = 3
5701 13:41:51.805865 13, 0x0, sum = 4
5702 13:41:51.806225 best_step = 11
5703 13:41:51.806554
5704 13:41:51.808260 ==
5705 13:41:51.811833 Dram Type= 6, Freq= 0, CH_1, rank 1
5706 13:41:51.815196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5707 13:41:51.816022 ==
5708 13:41:51.816720 RX Vref Scan: 0
5709 13:41:51.817455
5710 13:41:51.818446 RX Vref 0 -> 0, step: 1
5711 13:41:51.818943
5712 13:41:51.821405 RX Delay -77 -> 252, step: 4
5713 13:41:51.824934 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5714 13:41:51.831523 iDelay=203, Bit 1, Center 90 (-5 ~ 186) 192
5715 13:41:51.835315 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5716 13:41:51.837919 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5717 13:41:51.841451 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5718 13:41:51.845086 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5719 13:41:51.851966 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5720 13:41:51.854836 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5721 13:41:51.858092 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5722 13:41:51.861977 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5723 13:41:51.864866 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5724 13:41:51.868303 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5725 13:41:51.874916 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5726 13:41:51.877824 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5727 13:41:51.881513 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5728 13:41:51.884532 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5729 13:41:51.884947 ==
5730 13:41:51.888519 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 13:41:51.891274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5732 13:41:51.894626 ==
5733 13:41:51.895044 DQS Delay:
5734 13:41:51.895370 DQS0 = 0, DQS1 = 0
5735 13:41:51.897625 DQM Delay:
5736 13:41:51.898041 DQM0 = 96, DQM1 = 87
5737 13:41:51.901181 DQ Delay:
5738 13:41:51.904630 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5739 13:41:51.907707 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5740 13:41:51.911382 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5741 13:41:51.914040 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5742 13:41:51.914461
5743 13:41:51.914788
5744 13:41:51.921675 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5745 13:41:51.924686 CH1 RK1: MR19=505, MR18=2222
5746 13:41:51.931293 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5747 13:41:51.934024 [RxdqsGatingPostProcess] freq 933
5748 13:41:51.937877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5749 13:41:51.941251 Pre-setting of DQS Precalculation
5750 13:41:51.947646 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5751 13:41:51.954473 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5752 13:41:51.960920 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5753 13:41:51.961461
5754 13:41:51.961790
5755 13:41:51.964052 [Calibration Summary] 1866 Mbps
5756 13:41:51.964584 CH 0, Rank 0
5757 13:41:51.967171 SW Impedance : PASS
5758 13:41:51.971050 DUTY Scan : NO K
5759 13:41:51.971602 ZQ Calibration : PASS
5760 13:41:51.974241 Jitter Meter : NO K
5761 13:41:51.977508 CBT Training : PASS
5762 13:41:51.977985 Write leveling : PASS
5763 13:41:51.980354 RX DQS gating : PASS
5764 13:41:51.983673 RX DQ/DQS(RDDQC) : PASS
5765 13:41:51.984122 TX DQ/DQS : PASS
5766 13:41:51.986993 RX DATLAT : PASS
5767 13:41:51.990759 RX DQ/DQS(Engine): PASS
5768 13:41:51.991535 TX OE : NO K
5769 13:41:51.994103 All Pass.
5770 13:41:51.994555
5771 13:41:51.994968 CH 0, Rank 1
5772 13:41:51.997109 SW Impedance : PASS
5773 13:41:51.997607 DUTY Scan : NO K
5774 13:41:52.000830 ZQ Calibration : PASS
5775 13:41:52.003542 Jitter Meter : NO K
5776 13:41:52.004003 CBT Training : PASS
5777 13:41:52.007278 Write leveling : PASS
5778 13:41:52.007838 RX DQS gating : PASS
5779 13:41:52.010797 RX DQ/DQS(RDDQC) : PASS
5780 13:41:52.013688 TX DQ/DQS : PASS
5781 13:41:52.014286 RX DATLAT : PASS
5782 13:41:52.017061 RX DQ/DQS(Engine): PASS
5783 13:41:52.020820 TX OE : NO K
5784 13:41:52.021441 All Pass.
5785 13:41:52.021813
5786 13:41:52.022150 CH 1, Rank 0
5787 13:41:52.023579 SW Impedance : PASS
5788 13:41:52.027342 DUTY Scan : NO K
5789 13:41:52.027900 ZQ Calibration : PASS
5790 13:41:52.030133 Jitter Meter : NO K
5791 13:41:52.033695 CBT Training : PASS
5792 13:41:52.034152 Write leveling : PASS
5793 13:41:52.036860 RX DQS gating : PASS
5794 13:41:52.040334 RX DQ/DQS(RDDQC) : PASS
5795 13:41:52.040896 TX DQ/DQS : PASS
5796 13:41:52.043578 RX DATLAT : PASS
5797 13:41:52.046499 RX DQ/DQS(Engine): PASS
5798 13:41:52.046957 TX OE : NO K
5799 13:41:52.049948 All Pass.
5800 13:41:52.050403
5801 13:41:52.050760 CH 1, Rank 1
5802 13:41:52.053629 SW Impedance : PASS
5803 13:41:52.054190 DUTY Scan : NO K
5804 13:41:52.056942 ZQ Calibration : PASS
5805 13:41:52.059817 Jitter Meter : NO K
5806 13:41:52.060277 CBT Training : PASS
5807 13:41:52.063501 Write leveling : PASS
5808 13:41:52.066709 RX DQS gating : PASS
5809 13:41:52.067185 RX DQ/DQS(RDDQC) : PASS
5810 13:41:52.070004 TX DQ/DQS : PASS
5811 13:41:52.070466 RX DATLAT : PASS
5812 13:41:52.073713 RX DQ/DQS(Engine): PASS
5813 13:41:52.076756 TX OE : NO K
5814 13:41:52.077217 All Pass.
5815 13:41:52.077617
5816 13:41:52.079943 DramC Write-DBI off
5817 13:41:52.082936 PER_BANK_REFRESH: Hybrid Mode
5818 13:41:52.083398 TX_TRACKING: ON
5819 13:41:52.093104 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5820 13:41:52.096686 [FAST_K] Save calibration result to emmc
5821 13:41:52.100208 dramc_set_vcore_voltage set vcore to 650000
5822 13:41:52.103252 Read voltage for 400, 6
5823 13:41:52.103876 Vio18 = 0
5824 13:41:52.104419 Vcore = 650000
5825 13:41:52.106115 Vdram = 0
5826 13:41:52.106570 Vddq = 0
5827 13:41:52.106930 Vmddr = 0
5828 13:41:52.113479 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5829 13:41:52.116034 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5830 13:41:52.119603 MEM_TYPE=3, freq_sel=20
5831 13:41:52.122948 sv_algorithm_assistance_LP4_800
5832 13:41:52.125970 ============ PULL DRAM RESETB DOWN ============
5833 13:41:52.129769 ========== PULL DRAM RESETB DOWN end =========
5834 13:41:52.136373 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5835 13:41:52.139898 ===================================
5836 13:41:52.140529 LPDDR4 DRAM CONFIGURATION
5837 13:41:52.142590 ===================================
5838 13:41:52.145948 EX_ROW_EN[0] = 0x0
5839 13:41:52.149560 EX_ROW_EN[1] = 0x0
5840 13:41:52.150112 LP4Y_EN = 0x0
5841 13:41:52.152690 WORK_FSP = 0x0
5842 13:41:52.153247 WL = 0x2
5843 13:41:52.156112 RL = 0x2
5844 13:41:52.156666 BL = 0x2
5845 13:41:52.159502 RPST = 0x0
5846 13:41:52.160065 RD_PRE = 0x0
5847 13:41:52.162829 WR_PRE = 0x1
5848 13:41:52.163288 WR_PST = 0x0
5849 13:41:52.165935 DBI_WR = 0x0
5850 13:41:52.166493 DBI_RD = 0x0
5851 13:41:52.169204 OTF = 0x1
5852 13:41:52.172489 ===================================
5853 13:41:52.176005 ===================================
5854 13:41:52.176574 ANA top config
5855 13:41:52.178875 ===================================
5856 13:41:52.182228 DLL_ASYNC_EN = 0
5857 13:41:52.185537 ALL_SLAVE_EN = 1
5858 13:41:52.189392 NEW_RANK_MODE = 1
5859 13:41:52.189944 DLL_IDLE_MODE = 1
5860 13:41:52.192528 LP45_APHY_COMB_EN = 1
5861 13:41:52.195620 TX_ODT_DIS = 1
5862 13:41:52.199307 NEW_8X_MODE = 1
5863 13:41:52.202191 ===================================
5864 13:41:52.205710 ===================================
5865 13:41:52.209110 data_rate = 800
5866 13:41:52.209603 CKR = 1
5867 13:41:52.212348 DQ_P2S_RATIO = 4
5868 13:41:52.215599 ===================================
5869 13:41:52.218913 CA_P2S_RATIO = 4
5870 13:41:52.222502 DQ_CA_OPEN = 0
5871 13:41:52.225932 DQ_SEMI_OPEN = 1
5872 13:41:52.226405 CA_SEMI_OPEN = 1
5873 13:41:52.229115 CA_FULL_RATE = 0
5874 13:41:52.232323 DQ_CKDIV4_EN = 0
5875 13:41:52.235727 CA_CKDIV4_EN = 1
5876 13:41:52.239029 CA_PREDIV_EN = 0
5877 13:41:52.242421 PH8_DLY = 0
5878 13:41:52.242890 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5879 13:41:52.245664 DQ_AAMCK_DIV = 0
5880 13:41:52.249123 CA_AAMCK_DIV = 0
5881 13:41:52.252310 CA_ADMCK_DIV = 4
5882 13:41:52.255636 DQ_TRACK_CA_EN = 0
5883 13:41:52.258391 CA_PICK = 800
5884 13:41:52.261991 CA_MCKIO = 400
5885 13:41:52.262577 MCKIO_SEMI = 400
5886 13:41:52.265244 PLL_FREQ = 3016
5887 13:41:52.268948 DQ_UI_PI_RATIO = 32
5888 13:41:52.272374 CA_UI_PI_RATIO = 32
5889 13:41:52.275469 ===================================
5890 13:41:52.278717 ===================================
5891 13:41:52.281583 memory_type:LPDDR4
5892 13:41:52.282031 GP_NUM : 10
5893 13:41:52.284987 SRAM_EN : 1
5894 13:41:52.288960 MD32_EN : 0
5895 13:41:52.291948 ===================================
5896 13:41:52.292497 [ANA_INIT] >>>>>>>>>>>>>>
5897 13:41:52.295192 <<<<<< [CONFIGURE PHASE]: ANA_TX
5898 13:41:52.298328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5899 13:41:52.301990 ===================================
5900 13:41:52.305178 data_rate = 800,PCW = 0X7400
5901 13:41:52.308099 ===================================
5902 13:41:52.311817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5903 13:41:52.318385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5904 13:41:52.327798 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5905 13:41:52.334426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5906 13:41:52.337638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5907 13:41:52.340854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5908 13:41:52.341093 [ANA_INIT] flow start
5909 13:41:52.344243 [ANA_INIT] PLL >>>>>>>>
5910 13:41:52.347989 [ANA_INIT] PLL <<<<<<<<
5911 13:41:52.348316 [ANA_INIT] MIDPI >>>>>>>>
5912 13:41:52.350756 [ANA_INIT] MIDPI <<<<<<<<
5913 13:41:52.354443 [ANA_INIT] DLL >>>>>>>>
5914 13:41:52.354806 [ANA_INIT] flow end
5915 13:41:52.360886 ============ LP4 DIFF to SE enter ============
5916 13:41:52.364241 ============ LP4 DIFF to SE exit ============
5917 13:41:52.367421 [ANA_INIT] <<<<<<<<<<<<<
5918 13:41:52.370953 [Flow] Enable top DCM control >>>>>
5919 13:41:52.374935 [Flow] Enable top DCM control <<<<<
5920 13:41:52.375494 Enable DLL master slave shuffle
5921 13:41:52.381329 ==============================================================
5922 13:41:52.384696 Gating Mode config
5923 13:41:52.388325 ==============================================================
5924 13:41:52.390837 Config description:
5925 13:41:52.401210 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5926 13:41:52.407750 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5927 13:41:52.411064 SELPH_MODE 0: By rank 1: By Phase
5928 13:41:52.417479 ==============================================================
5929 13:41:52.420430 GAT_TRACK_EN = 0
5930 13:41:52.424050 RX_GATING_MODE = 2
5931 13:41:52.427564 RX_GATING_TRACK_MODE = 2
5932 13:41:52.430343 SELPH_MODE = 1
5933 13:41:52.433726 PICG_EARLY_EN = 1
5934 13:41:52.434273 VALID_LAT_VALUE = 1
5935 13:41:52.440002 ==============================================================
5936 13:41:52.443525 Enter into Gating configuration >>>>
5937 13:41:52.447124 Exit from Gating configuration <<<<
5938 13:41:52.450315 Enter into DVFS_PRE_config >>>>>
5939 13:41:52.460133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5940 13:41:52.463888 Exit from DVFS_PRE_config <<<<<
5941 13:41:52.466460 Enter into PICG configuration >>>>
5942 13:41:52.470008 Exit from PICG configuration <<<<
5943 13:41:52.473505 [RX_INPUT] configuration >>>>>
5944 13:41:52.476774 [RX_INPUT] configuration <<<<<
5945 13:41:52.483075 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5946 13:41:52.486705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5947 13:41:52.492925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5948 13:41:52.500180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5949 13:41:52.506627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5950 13:41:52.513402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5951 13:41:52.515990 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5952 13:41:52.519803 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5953 13:41:52.522774 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5954 13:41:52.529118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5955 13:41:52.532645 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5956 13:41:52.536479 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5957 13:41:52.539044 ===================================
5958 13:41:52.542567 LPDDR4 DRAM CONFIGURATION
5959 13:41:52.546358 ===================================
5960 13:41:52.549094 EX_ROW_EN[0] = 0x0
5961 13:41:52.549679 EX_ROW_EN[1] = 0x0
5962 13:41:52.552818 LP4Y_EN = 0x0
5963 13:41:52.553425 WORK_FSP = 0x0
5964 13:41:52.555613 WL = 0x2
5965 13:41:52.556079 RL = 0x2
5966 13:41:52.559431 BL = 0x2
5967 13:41:52.559996 RPST = 0x0
5968 13:41:52.562761 RD_PRE = 0x0
5969 13:41:52.563324 WR_PRE = 0x1
5970 13:41:52.565869 WR_PST = 0x0
5971 13:41:52.566458 DBI_WR = 0x0
5972 13:41:52.569040 DBI_RD = 0x0
5973 13:41:52.569764 OTF = 0x1
5974 13:41:52.572161 ===================================
5975 13:41:52.579007 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5976 13:41:52.582322 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5977 13:41:52.585970 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5978 13:41:52.588620 ===================================
5979 13:41:52.592253 LPDDR4 DRAM CONFIGURATION
5980 13:41:52.595295 ===================================
5981 13:41:52.598719 EX_ROW_EN[0] = 0x10
5982 13:41:52.599173 EX_ROW_EN[1] = 0x0
5983 13:41:52.602031 LP4Y_EN = 0x0
5984 13:41:52.602483 WORK_FSP = 0x0
5985 13:41:52.605482 WL = 0x2
5986 13:41:52.606031 RL = 0x2
5987 13:41:52.609360 BL = 0x2
5988 13:41:52.609949 RPST = 0x0
5989 13:41:52.612058 RD_PRE = 0x0
5990 13:41:52.612513 WR_PRE = 0x1
5991 13:41:52.615600 WR_PST = 0x0
5992 13:41:52.616052 DBI_WR = 0x0
5993 13:41:52.618557 DBI_RD = 0x0
5994 13:41:52.619045 OTF = 0x1
5995 13:41:52.622010 ===================================
5996 13:41:52.628729 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5997 13:41:52.633374 nWR fixed to 30
5998 13:41:52.636854 [ModeRegInit_LP4] CH0 RK0
5999 13:41:52.637347 [ModeRegInit_LP4] CH0 RK1
6000 13:41:52.639990 [ModeRegInit_LP4] CH1 RK0
6001 13:41:52.643337 [ModeRegInit_LP4] CH1 RK1
6002 13:41:52.643791 match AC timing 18
6003 13:41:52.649826 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6004 13:41:52.653461 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6005 13:41:52.656272 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6006 13:41:52.663587 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6007 13:41:52.666276 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6008 13:41:52.666738 ==
6009 13:41:52.670024 Dram Type= 6, Freq= 0, CH_0, rank 0
6010 13:41:52.672858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6011 13:41:52.673336 ==
6012 13:41:52.679570 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6013 13:41:52.686441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6014 13:41:52.689743 [CA 0] Center 36 (8~64) winsize 57
6015 13:41:52.693058 [CA 1] Center 36 (8~64) winsize 57
6016 13:41:52.696316 [CA 2] Center 36 (8~64) winsize 57
6017 13:41:52.699804 [CA 3] Center 36 (8~64) winsize 57
6018 13:41:52.700451 [CA 4] Center 36 (8~64) winsize 57
6019 13:41:52.703260 [CA 5] Center 36 (8~64) winsize 57
6020 13:41:52.703824
6021 13:41:52.709546 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6022 13:41:52.710107
6023 13:41:52.713351 [CATrainingPosCal] consider 1 rank data
6024 13:41:52.716494 u2DelayCellTimex100 = 270/100 ps
6025 13:41:52.719398 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 13:41:52.722629 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 13:41:52.725965 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 13:41:52.729690 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 13:41:52.733038 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 13:41:52.736246 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 13:41:52.736809
6032 13:41:52.739327 CA PerBit enable=1, Macro0, CA PI delay=36
6033 13:41:52.739780
6034 13:41:52.742559 [CBTSetCACLKResult] CA Dly = 36
6035 13:41:52.746004 CS Dly: 1 (0~32)
6036 13:41:52.746550 ==
6037 13:41:52.749403 Dram Type= 6, Freq= 0, CH_0, rank 1
6038 13:41:52.752347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 13:41:52.752898 ==
6040 13:41:52.759524 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6041 13:41:52.765989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6042 13:41:52.768690 [CA 0] Center 36 (8~64) winsize 57
6043 13:41:52.769162 [CA 1] Center 36 (8~64) winsize 57
6044 13:41:52.772574 [CA 2] Center 36 (8~64) winsize 57
6045 13:41:52.775259 [CA 3] Center 36 (8~64) winsize 57
6046 13:41:52.778917 [CA 4] Center 36 (8~64) winsize 57
6047 13:41:52.782513 [CA 5] Center 36 (8~64) winsize 57
6048 13:41:52.783063
6049 13:41:52.785575 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6050 13:41:52.786123
6051 13:41:52.792257 [CATrainingPosCal] consider 2 rank data
6052 13:41:52.792871 u2DelayCellTimex100 = 270/100 ps
6053 13:41:52.795800 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 13:41:52.802247 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 13:41:52.805464 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 13:41:52.808803 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 13:41:52.812307 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 13:41:52.815591 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 13:41:52.816345
6060 13:41:52.818468 CA PerBit enable=1, Macro0, CA PI delay=36
6061 13:41:52.818934
6062 13:41:52.821716 [CBTSetCACLKResult] CA Dly = 36
6063 13:41:52.825250 CS Dly: 1 (0~32)
6064 13:41:52.825744
6065 13:41:52.828606 ----->DramcWriteLeveling(PI) begin...
6066 13:41:52.829157 ==
6067 13:41:52.832349 Dram Type= 6, Freq= 0, CH_0, rank 0
6068 13:41:52.835189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6069 13:41:52.835643 ==
6070 13:41:52.838703 Write leveling (Byte 0): 32 => 0
6071 13:41:52.842082 Write leveling (Byte 1): 32 => 0
6072 13:41:52.845409 DramcWriteLeveling(PI) end<-----
6073 13:41:52.845963
6074 13:41:52.846318 ==
6075 13:41:52.848411 Dram Type= 6, Freq= 0, CH_0, rank 0
6076 13:41:52.851462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6077 13:41:52.851919 ==
6078 13:41:52.855234 [Gating] SW mode calibration
6079 13:41:52.861624 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6080 13:41:52.868346 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6081 13:41:52.872039 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6082 13:41:52.874692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6083 13:41:52.881658 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6084 13:41:52.885128 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6085 13:41:52.888132 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6086 13:41:52.894656 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6087 13:41:52.898056 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6088 13:41:52.901447 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6089 13:41:52.908055 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6090 13:41:52.908627 Total UI for P1: 0, mck2ui 16
6091 13:41:52.914959 best dqsien dly found for B0: ( 0, 10, 16)
6092 13:41:52.915512 Total UI for P1: 0, mck2ui 16
6093 13:41:52.921146 best dqsien dly found for B1: ( 0, 10, 24)
6094 13:41:52.924734 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6095 13:41:52.927913 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6096 13:41:52.928370
6097 13:41:52.931059 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6098 13:41:52.934623 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6099 13:41:52.937755 [Gating] SW calibration Done
6100 13:41:52.938210 ==
6101 13:41:52.941223 Dram Type= 6, Freq= 0, CH_0, rank 0
6102 13:41:52.944317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6103 13:41:52.944874 ==
6104 13:41:52.947935 RX Vref Scan: 0
6105 13:41:52.948386
6106 13:41:52.948740 RX Vref 0 -> 0, step: 1
6107 13:41:52.949072
6108 13:41:52.951512 RX Delay -410 -> 252, step: 16
6109 13:41:52.957812 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6110 13:41:52.960843 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6111 13:41:52.964184 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6112 13:41:52.967699 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6113 13:41:52.974251 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6114 13:41:52.977659 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6115 13:41:52.980692 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6116 13:41:52.984293 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6117 13:41:52.990823 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6118 13:41:52.993740 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6119 13:41:52.997382 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6120 13:41:53.000381 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6121 13:41:53.007216 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6122 13:41:53.010780 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6123 13:41:53.014195 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6124 13:41:53.020244 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6125 13:41:53.020702 ==
6126 13:41:53.023862 Dram Type= 6, Freq= 0, CH_0, rank 0
6127 13:41:53.027486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6128 13:41:53.028082 ==
6129 13:41:53.028445 DQS Delay:
6130 13:41:53.030263 DQS0 = 51, DQS1 = 59
6131 13:41:53.030718 DQM Delay:
6132 13:41:53.033884 DQM0 = 12, DQM1 = 15
6133 13:41:53.034345 DQ Delay:
6134 13:41:53.037398 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6135 13:41:53.040578 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6136 13:41:53.043811 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6137 13:41:53.047066 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6138 13:41:53.047532
6139 13:41:53.048024
6140 13:41:53.048388 ==
6141 13:41:53.050079 Dram Type= 6, Freq= 0, CH_0, rank 0
6142 13:41:53.053757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6143 13:41:53.054214 ==
6144 13:41:53.054571
6145 13:41:53.054900
6146 13:41:53.056759 TX Vref Scan disable
6147 13:41:53.057214 == TX Byte 0 ==
6148 13:41:53.063383 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6149 13:41:53.066555 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6150 13:41:53.067013 == TX Byte 1 ==
6151 13:41:53.073272 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6152 13:41:53.076422 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6153 13:41:53.076875 ==
6154 13:41:53.079978 Dram Type= 6, Freq= 0, CH_0, rank 0
6155 13:41:53.083559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6156 13:41:53.083976 ==
6157 13:41:53.084299
6158 13:41:53.086454
6159 13:41:53.086864 TX Vref Scan disable
6160 13:41:53.089952 == TX Byte 0 ==
6161 13:41:53.093512 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6162 13:41:53.096596 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6163 13:41:53.100086 == TX Byte 1 ==
6164 13:41:53.103058 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6165 13:41:53.106645 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6166 13:41:53.107055
6167 13:41:53.107380 [DATLAT]
6168 13:41:53.109640 Freq=400, CH0 RK0
6169 13:41:53.110049
6170 13:41:53.113255 DATLAT Default: 0xf
6171 13:41:53.113689 0, 0xFFFF, sum = 0
6172 13:41:53.116470 1, 0xFFFF, sum = 0
6173 13:41:53.116906 2, 0xFFFF, sum = 0
6174 13:41:53.119882 3, 0xFFFF, sum = 0
6175 13:41:53.120298 4, 0xFFFF, sum = 0
6176 13:41:53.123132 5, 0xFFFF, sum = 0
6177 13:41:53.123548 6, 0xFFFF, sum = 0
6178 13:41:53.126217 7, 0xFFFF, sum = 0
6179 13:41:53.126631 8, 0xFFFF, sum = 0
6180 13:41:53.129727 9, 0xFFFF, sum = 0
6181 13:41:53.130141 10, 0xFFFF, sum = 0
6182 13:41:53.133005 11, 0xFFFF, sum = 0
6183 13:41:53.133454 12, 0x0, sum = 1
6184 13:41:53.136029 13, 0x0, sum = 2
6185 13:41:53.136440 14, 0x0, sum = 3
6186 13:41:53.139604 15, 0x0, sum = 4
6187 13:41:53.140049 best_step = 13
6188 13:41:53.140522
6189 13:41:53.140836 ==
6190 13:41:53.142498 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 13:41:53.149219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6192 13:41:53.149780 ==
6193 13:41:53.150166 RX Vref Scan: 1
6194 13:41:53.150471
6195 13:41:53.152789 RX Vref 0 -> 0, step: 1
6196 13:41:53.153196
6197 13:41:53.156319 RX Delay -359 -> 252, step: 8
6198 13:41:53.156822
6199 13:41:53.159711 Set Vref, RX VrefLevel [Byte0]: 46
6200 13:41:53.162552 [Byte1]: 50
6201 13:41:53.162961
6202 13:41:53.165929 Final RX Vref Byte 0 = 46 to rank0
6203 13:41:53.169338 Final RX Vref Byte 1 = 50 to rank0
6204 13:41:53.172833 Final RX Vref Byte 0 = 46 to rank1
6205 13:41:53.175848 Final RX Vref Byte 1 = 50 to rank1==
6206 13:41:53.179295 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 13:41:53.185601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6208 13:41:53.186017 ==
6209 13:41:53.186340 DQS Delay:
6210 13:41:53.188721 DQS0 = 52, DQS1 = 68
6211 13:41:53.189127 DQM Delay:
6212 13:41:53.189504 DQM0 = 9, DQM1 = 17
6213 13:41:53.192762 DQ Delay:
6214 13:41:53.193169 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6215 13:41:53.195563 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6216 13:41:53.199231 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6217 13:41:53.202295 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6218 13:41:53.202801
6219 13:41:53.203128
6220 13:41:53.212643 [DQSOSCAuto] RK0, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6221 13:41:53.215326 CH0 RK0: MR19=C0C, MR18=A6A6
6222 13:41:53.222396 CH0_RK0: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6223 13:41:53.222981 ==
6224 13:41:53.225420 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 13:41:53.229133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6226 13:41:53.229703 ==
6227 13:41:53.232130 [Gating] SW mode calibration
6228 13:41:53.238804 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6229 13:41:53.242002 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6230 13:41:53.248771 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6231 13:41:53.252342 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6232 13:41:53.255182 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6233 13:41:53.261711 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6234 13:41:53.265445 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6235 13:41:53.268107 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6236 13:41:53.274795 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6237 13:41:53.278398 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6238 13:41:53.281702 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6239 13:41:53.285020 Total UI for P1: 0, mck2ui 16
6240 13:41:53.288173 best dqsien dly found for B0: ( 0, 10, 16)
6241 13:41:53.291612 Total UI for P1: 0, mck2ui 16
6242 13:41:53.294965 best dqsien dly found for B1: ( 0, 10, 16)
6243 13:41:53.298334 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6244 13:41:53.305083 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6245 13:41:53.305721
6246 13:41:53.308256 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6247 13:41:53.311732 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6248 13:41:53.314732 [Gating] SW calibration Done
6249 13:41:53.315189 ==
6250 13:41:53.318340 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 13:41:53.321475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 13:41:53.322014 ==
6253 13:41:53.324511 RX Vref Scan: 0
6254 13:41:53.324967
6255 13:41:53.325396 RX Vref 0 -> 0, step: 1
6256 13:41:53.325748
6257 13:41:53.328382 RX Delay -410 -> 252, step: 16
6258 13:41:53.331161 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6259 13:41:53.338032 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6260 13:41:53.341637 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6261 13:41:53.344786 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6262 13:41:53.351487 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6263 13:41:53.354493 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6264 13:41:53.358220 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6265 13:41:53.361533 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6266 13:41:53.364534 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6267 13:41:53.371074 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6268 13:41:53.374054 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6269 13:41:53.377704 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6270 13:41:53.384293 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6271 13:41:53.387614 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6272 13:41:53.391133 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6273 13:41:53.394215 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6274 13:41:53.397535 ==
6275 13:41:53.398090 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 13:41:53.403994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6277 13:41:53.404550 ==
6278 13:41:53.404957 DQS Delay:
6279 13:41:53.407684 DQS0 = 43, DQS1 = 59
6280 13:41:53.408240 DQM Delay:
6281 13:41:53.411029 DQM0 = 7, DQM1 = 15
6282 13:41:53.411584 DQ Delay:
6283 13:41:53.414199 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6284 13:41:53.417552 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6285 13:41:53.421223 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6286 13:41:53.423957 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6287 13:41:53.424422
6288 13:41:53.424784
6289 13:41:53.425113 ==
6290 13:41:53.427894 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 13:41:53.430856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6292 13:41:53.431414 ==
6293 13:41:53.431777
6294 13:41:53.432103
6295 13:41:53.433632 TX Vref Scan disable
6296 13:41:53.434088 == TX Byte 0 ==
6297 13:41:53.440976 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6298 13:41:53.443967 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6299 13:41:53.444521 == TX Byte 1 ==
6300 13:41:53.447588 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6301 13:41:53.453720 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6302 13:41:53.454276 ==
6303 13:41:53.457614 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 13:41:53.460534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6305 13:41:53.460992 ==
6306 13:41:53.461374
6307 13:41:53.461710
6308 13:41:53.464148 TX Vref Scan disable
6309 13:41:53.464702 == TX Byte 0 ==
6310 13:41:53.470327 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6311 13:41:53.473323 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6312 13:41:53.473779 == TX Byte 1 ==
6313 13:41:53.479902 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6314 13:41:53.483532 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6315 13:41:53.483987
6316 13:41:53.484343 [DATLAT]
6317 13:41:53.486744 Freq=400, CH0 RK1
6318 13:41:53.487298
6319 13:41:53.487695 DATLAT Default: 0xd
6320 13:41:53.489822 0, 0xFFFF, sum = 0
6321 13:41:53.490437 1, 0xFFFF, sum = 0
6322 13:41:53.493243 2, 0xFFFF, sum = 0
6323 13:41:53.493703 3, 0xFFFF, sum = 0
6324 13:41:53.496450 4, 0xFFFF, sum = 0
6325 13:41:53.496911 5, 0xFFFF, sum = 0
6326 13:41:53.499806 6, 0xFFFF, sum = 0
6327 13:41:53.500378 7, 0xFFFF, sum = 0
6328 13:41:53.503144 8, 0xFFFF, sum = 0
6329 13:41:53.503707 9, 0xFFFF, sum = 0
6330 13:41:53.506523 10, 0xFFFF, sum = 0
6331 13:41:53.509915 11, 0xFFFF, sum = 0
6332 13:41:53.510387 12, 0x0, sum = 1
6333 13:41:53.512853 13, 0x0, sum = 2
6334 13:41:53.513352 14, 0x0, sum = 3
6335 13:41:53.513727 15, 0x0, sum = 4
6336 13:41:53.516199 best_step = 13
6337 13:41:53.516648
6338 13:41:53.517000 ==
6339 13:41:53.519613 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 13:41:53.522484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6341 13:41:53.522939 ==
6342 13:41:53.525896 RX Vref Scan: 0
6343 13:41:53.526348
6344 13:41:53.529453 RX Vref 0 -> 0, step: 1
6345 13:41:53.529790
6346 13:41:53.530146 RX Delay -359 -> 252, step: 8
6347 13:41:53.538454 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6348 13:41:53.541453 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6349 13:41:53.544831 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6350 13:41:53.547701 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6351 13:41:53.554979 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6352 13:41:53.557803 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6353 13:41:53.561368 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6354 13:41:53.564958 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6355 13:41:53.571391 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6356 13:41:53.574380 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6357 13:41:53.578271 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6358 13:41:53.581762 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6359 13:41:53.588291 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6360 13:41:53.591094 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6361 13:41:53.594456 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6362 13:41:53.601325 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6363 13:41:53.601870 ==
6364 13:41:53.604558 Dram Type= 6, Freq= 0, CH_0, rank 1
6365 13:41:53.607982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6366 13:41:53.608558 ==
6367 13:41:53.608926 DQS Delay:
6368 13:41:53.611187 DQS0 = 52, DQS1 = 64
6369 13:41:53.611742 DQM Delay:
6370 13:41:53.614718 DQM0 = 11, DQM1 = 14
6371 13:41:53.615275 DQ Delay:
6372 13:41:53.617997 DQ0 =4, DQ1 =16, DQ2 =8, DQ3 =8
6373 13:41:53.621028 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6374 13:41:53.624495 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6375 13:41:53.627640 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6376 13:41:53.628090
6377 13:41:53.628442
6378 13:41:53.634469 [DQSOSCAuto] RK1, (LSB)MR18= 0xbbbb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6379 13:41:53.637652 CH0 RK1: MR19=C0C, MR18=BBBB
6380 13:41:53.643742 CH0_RK1: MR19=0xC0C, MR18=0xBBBB, DQSOSC=386, MR23=63, INC=396, DEC=264
6381 13:41:53.647420 [RxdqsGatingPostProcess] freq 400
6382 13:41:53.654119 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6383 13:41:53.657630 Pre-setting of DQS Precalculation
6384 13:41:53.660655 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6385 13:41:53.661189 ==
6386 13:41:53.664529 Dram Type= 6, Freq= 0, CH_1, rank 0
6387 13:41:53.667231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6388 13:41:53.667687 ==
6389 13:41:53.673710 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6390 13:41:53.680439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6391 13:41:53.683727 [CA 0] Center 36 (8~64) winsize 57
6392 13:41:53.687271 [CA 1] Center 36 (8~64) winsize 57
6393 13:41:53.691006 [CA 2] Center 36 (8~64) winsize 57
6394 13:41:53.693964 [CA 3] Center 36 (8~64) winsize 57
6395 13:41:53.697417 [CA 4] Center 36 (8~64) winsize 57
6396 13:41:53.698035 [CA 5] Center 36 (8~64) winsize 57
6397 13:41:53.700054
6398 13:41:53.703908 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6399 13:41:53.704462
6400 13:41:53.707366 [CATrainingPosCal] consider 1 rank data
6401 13:41:53.710324 u2DelayCellTimex100 = 270/100 ps
6402 13:41:53.713952 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 13:41:53.717165 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 13:41:53.720030 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 13:41:53.723270 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 13:41:53.726773 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 13:41:53.730136 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 13:41:53.730594
6409 13:41:53.733354 CA PerBit enable=1, Macro0, CA PI delay=36
6410 13:41:53.733808
6411 13:41:53.736627 [CBTSetCACLKResult] CA Dly = 36
6412 13:41:53.740440 CS Dly: 1 (0~32)
6413 13:41:53.740995 ==
6414 13:41:53.743081 Dram Type= 6, Freq= 0, CH_1, rank 1
6415 13:41:53.746824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 13:41:53.747387 ==
6417 13:41:53.753233 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6418 13:41:53.759834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6419 13:41:53.763532 [CA 0] Center 36 (8~64) winsize 57
6420 13:41:53.766472 [CA 1] Center 36 (8~64) winsize 57
6421 13:41:53.767052 [CA 2] Center 36 (8~64) winsize 57
6422 13:41:53.769927 [CA 3] Center 36 (8~64) winsize 57
6423 13:41:53.773083 [CA 4] Center 32 (8~56) winsize 49
6424 13:41:53.776498 [CA 5] Center 36 (8~64) winsize 57
6425 13:41:53.776948
6426 13:41:53.779475 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6427 13:41:53.783329
6428 13:41:53.786145 [CATrainingPosCal] consider 2 rank data
6429 13:41:53.786601 u2DelayCellTimex100 = 270/100 ps
6430 13:41:53.793163 CA0 delay=36 (8~64),Diff = 4 PI (57 cell)
6431 13:41:53.796126 CA1 delay=36 (8~64),Diff = 4 PI (57 cell)
6432 13:41:53.799916 CA2 delay=36 (8~64),Diff = 4 PI (57 cell)
6433 13:41:53.803067 CA3 delay=36 (8~64),Diff = 4 PI (57 cell)
6434 13:41:53.806526 CA4 delay=32 (8~56),Diff = 0 PI (0 cell)
6435 13:41:53.809432 CA5 delay=36 (8~64),Diff = 4 PI (57 cell)
6436 13:41:53.809979
6437 13:41:53.813237 CA PerBit enable=1, Macro0, CA PI delay=32
6438 13:41:53.813841
6439 13:41:53.816739 [CBTSetCACLKResult] CA Dly = 32
6440 13:41:53.819503 CS Dly: 1 (0~32)
6441 13:41:53.820008
6442 13:41:53.823249 ----->DramcWriteLeveling(PI) begin...
6443 13:41:53.823813 ==
6444 13:41:53.826311 Dram Type= 6, Freq= 0, CH_1, rank 0
6445 13:41:53.829437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6446 13:41:53.829887 ==
6447 13:41:53.832699 Write leveling (Byte 0): 32 => 0
6448 13:41:53.836481 Write leveling (Byte 1): 32 => 0
6449 13:41:53.839794 DramcWriteLeveling(PI) end<-----
6450 13:41:53.840362
6451 13:41:53.840784 ==
6452 13:41:53.843032 Dram Type= 6, Freq= 0, CH_1, rank 0
6453 13:41:53.845643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6454 13:41:53.846095 ==
6455 13:41:53.849338 [Gating] SW mode calibration
6456 13:41:53.855933 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 13:41:53.862591 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6458 13:41:53.865821 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 13:41:53.869368 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 13:41:53.876197 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 13:41:53.879060 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6462 13:41:53.882061 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 13:41:53.888988 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 13:41:53.892446 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 13:41:53.895685 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6466 13:41:53.902200 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 13:41:53.905724 Total UI for P1: 0, mck2ui 16
6468 13:41:53.909119 best dqsien dly found for B0: ( 0, 10, 16)
6469 13:41:53.912161 Total UI for P1: 0, mck2ui 16
6470 13:41:53.915190 best dqsien dly found for B1: ( 0, 10, 16)
6471 13:41:53.918459 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6472 13:41:53.921996 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6473 13:41:53.922458
6474 13:41:53.925203 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6475 13:41:53.928839 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6476 13:41:53.931708 [Gating] SW calibration Done
6477 13:41:53.932260 ==
6478 13:41:53.934822 Dram Type= 6, Freq= 0, CH_1, rank 0
6479 13:41:53.938699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6480 13:41:53.941778 ==
6481 13:41:53.942240 RX Vref Scan: 0
6482 13:41:53.942598
6483 13:41:53.945169 RX Vref 0 -> 0, step: 1
6484 13:41:53.945679
6485 13:41:53.948019 RX Delay -410 -> 252, step: 16
6486 13:41:53.951954 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6487 13:41:53.954873 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6488 13:41:53.957893 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6489 13:41:53.965148 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6490 13:41:53.968039 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6491 13:41:53.971567 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6492 13:41:53.974448 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6493 13:41:53.981094 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6494 13:41:53.984495 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6495 13:41:53.987883 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6496 13:41:53.991235 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6497 13:41:53.997628 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6498 13:41:54.001619 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6499 13:41:54.004312 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6500 13:41:54.011162 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6501 13:41:54.014010 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6502 13:41:54.014574 ==
6503 13:41:54.017487 Dram Type= 6, Freq= 0, CH_1, rank 0
6504 13:41:54.020664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6505 13:41:54.021124 ==
6506 13:41:54.023865 DQS Delay:
6507 13:41:54.024318 DQS0 = 43, DQS1 = 59
6508 13:41:54.024678 DQM Delay:
6509 13:41:54.027404 DQM0 = 6, DQM1 = 15
6510 13:41:54.027857 DQ Delay:
6511 13:41:54.030905 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6512 13:41:54.033914 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6513 13:41:54.037411 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6514 13:41:54.040882 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6515 13:41:54.041451
6516 13:41:54.041817
6517 13:41:54.042150 ==
6518 13:41:54.043764 Dram Type= 6, Freq= 0, CH_1, rank 0
6519 13:41:54.047826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6520 13:41:54.050690 ==
6521 13:41:54.051146
6522 13:41:54.051499
6523 13:41:54.051834 TX Vref Scan disable
6524 13:41:54.053984 == TX Byte 0 ==
6525 13:41:54.057524 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6526 13:41:54.060678 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6527 13:41:54.063978 == TX Byte 1 ==
6528 13:41:54.067305 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6529 13:41:54.070461 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6530 13:41:54.071013 ==
6531 13:41:54.073908 Dram Type= 6, Freq= 0, CH_1, rank 0
6532 13:41:54.080451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6533 13:41:54.080989 ==
6534 13:41:54.081383
6535 13:41:54.081719
6536 13:41:54.082036 TX Vref Scan disable
6537 13:41:54.083404 == TX Byte 0 ==
6538 13:41:54.087273 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6539 13:41:54.090451 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6540 13:41:54.093905 == TX Byte 1 ==
6541 13:41:54.096987 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6542 13:41:54.100036 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6543 13:41:54.103927
6544 13:41:54.104486 [DATLAT]
6545 13:41:54.104847 Freq=400, CH1 RK0
6546 13:41:54.105180
6547 13:41:54.107275 DATLAT Default: 0xf
6548 13:41:54.107828 0, 0xFFFF, sum = 0
6549 13:41:54.109890 1, 0xFFFF, sum = 0
6550 13:41:54.110353 2, 0xFFFF, sum = 0
6551 13:41:54.113545 3, 0xFFFF, sum = 0
6552 13:41:54.116949 4, 0xFFFF, sum = 0
6553 13:41:54.117519 5, 0xFFFF, sum = 0
6554 13:41:54.119995 6, 0xFFFF, sum = 0
6555 13:41:54.120497 7, 0xFFFF, sum = 0
6556 13:41:54.123633 8, 0xFFFF, sum = 0
6557 13:41:54.124104 9, 0xFFFF, sum = 0
6558 13:41:54.126706 10, 0xFFFF, sum = 0
6559 13:41:54.127514 11, 0xFFFF, sum = 0
6560 13:41:54.130238 12, 0x0, sum = 1
6561 13:41:54.131052 13, 0x0, sum = 2
6562 13:41:54.133592 14, 0x0, sum = 3
6563 13:41:54.134304 15, 0x0, sum = 4
6564 13:41:54.134980 best_step = 13
6565 13:41:54.136602
6566 13:41:54.137326 ==
6567 13:41:54.139771 Dram Type= 6, Freq= 0, CH_1, rank 0
6568 13:41:54.143231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6569 13:41:54.143976 ==
6570 13:41:54.144590 RX Vref Scan: 1
6571 13:41:54.144987
6572 13:41:54.146351 RX Vref 0 -> 0, step: 1
6573 13:41:54.146780
6574 13:41:54.149851 RX Delay -359 -> 252, step: 8
6575 13:41:54.150154
6576 13:41:54.152639 Set Vref, RX VrefLevel [Byte0]: 57
6577 13:41:54.156124 [Byte1]: 49
6578 13:41:54.160222
6579 13:41:54.160479 Final RX Vref Byte 0 = 57 to rank0
6580 13:41:54.163604 Final RX Vref Byte 1 = 49 to rank0
6581 13:41:54.166677 Final RX Vref Byte 0 = 57 to rank1
6582 13:41:54.170268 Final RX Vref Byte 1 = 49 to rank1==
6583 13:41:54.173740 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 13:41:54.180862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6585 13:41:54.181258 ==
6586 13:41:54.181592 DQS Delay:
6587 13:41:54.183525 DQS0 = 48, DQS1 = 64
6588 13:41:54.183816 DQM Delay:
6589 13:41:54.184044 DQM0 = 8, DQM1 = 16
6590 13:41:54.187258 DQ Delay:
6591 13:41:54.190239 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6592 13:41:54.190689 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6593 13:41:54.193896 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6594 13:41:54.197200 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6595 13:41:54.197693
6596 13:41:54.198050
6597 13:41:54.207229 [DQSOSCAuto] RK0, (LSB)MR18= 0xdede, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6598 13:41:54.210296 CH1 RK0: MR19=C0C, MR18=DEDE
6599 13:41:54.216836 CH1_RK0: MR19=0xC0C, MR18=0xDEDE, DQSOSC=382, MR23=63, INC=404, DEC=269
6600 13:41:54.217462 ==
6601 13:41:54.220268 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 13:41:54.223115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6603 13:41:54.223577 ==
6604 13:41:54.226635 [Gating] SW mode calibration
6605 13:41:54.233353 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6606 13:41:54.239839 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6607 13:41:54.243176 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6608 13:41:54.246652 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6609 13:41:54.249991 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6610 13:41:54.256374 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6611 13:41:54.259871 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6612 13:41:54.263435 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6613 13:41:54.269719 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6614 13:41:54.273071 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6615 13:41:54.276230 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6616 13:41:54.279774 Total UI for P1: 0, mck2ui 16
6617 13:41:54.282889 best dqsien dly found for B0: ( 0, 10, 16)
6618 13:41:54.285872 Total UI for P1: 0, mck2ui 16
6619 13:41:54.289410 best dqsien dly found for B1: ( 0, 10, 16)
6620 13:41:54.292983 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6621 13:41:54.299648 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6622 13:41:54.300133
6623 13:41:54.302543 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6624 13:41:54.306118 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6625 13:41:54.309544 [Gating] SW calibration Done
6626 13:41:54.310050 ==
6627 13:41:54.312493 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 13:41:54.316052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 13:41:54.316507 ==
6630 13:41:54.318946 RX Vref Scan: 0
6631 13:41:54.319354
6632 13:41:54.319675 RX Vref 0 -> 0, step: 1
6633 13:41:54.319974
6634 13:41:54.322029 RX Delay -410 -> 252, step: 16
6635 13:41:54.328760 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6636 13:41:54.332236 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6637 13:41:54.335692 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6638 13:41:54.339014 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6639 13:41:54.345402 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6640 13:41:54.349133 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6641 13:41:54.352139 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6642 13:41:54.355515 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6643 13:41:54.362153 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6644 13:41:54.365742 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6645 13:41:54.368679 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6646 13:41:54.372210 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6647 13:41:54.378682 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6648 13:41:54.381850 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6649 13:41:54.385381 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6650 13:41:54.392088 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6651 13:41:54.392644 ==
6652 13:41:54.395503 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 13:41:54.398222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6654 13:41:54.398684 ==
6655 13:41:54.399059 DQS Delay:
6656 13:41:54.401797 DQS0 = 43, DQS1 = 59
6657 13:41:54.402316 DQM Delay:
6658 13:41:54.405038 DQM0 = 9, DQM1 = 17
6659 13:41:54.405635 DQ Delay:
6660 13:41:54.408509 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6661 13:41:54.412066 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6662 13:41:54.414776 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6663 13:41:54.418402 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6664 13:41:54.418852
6665 13:41:54.419204
6666 13:41:54.419530 ==
6667 13:41:54.421515 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 13:41:54.425165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6669 13:41:54.425783 ==
6670 13:41:54.426143
6671 13:41:54.426469
6672 13:41:54.428010 TX Vref Scan disable
6673 13:41:54.428493 == TX Byte 0 ==
6674 13:41:54.434997 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6675 13:41:54.438280 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6676 13:41:54.438731 == TX Byte 1 ==
6677 13:41:54.445183 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6678 13:41:54.448354 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6679 13:41:54.448907 ==
6680 13:41:54.451362 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 13:41:54.454824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6682 13:41:54.455278 ==
6683 13:41:54.455632
6684 13:41:54.455970
6685 13:41:54.457769 TX Vref Scan disable
6686 13:41:54.458219 == TX Byte 0 ==
6687 13:41:54.464790 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6688 13:41:54.467664 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6689 13:41:54.468120 == TX Byte 1 ==
6690 13:41:54.474597 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6691 13:41:54.477932 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6692 13:41:54.478390
6693 13:41:54.478747 [DATLAT]
6694 13:41:54.481364 Freq=400, CH1 RK1
6695 13:41:54.481914
6696 13:41:54.482278 DATLAT Default: 0xd
6697 13:41:54.484439 0, 0xFFFF, sum = 0
6698 13:41:54.484904 1, 0xFFFF, sum = 0
6699 13:41:54.487615 2, 0xFFFF, sum = 0
6700 13:41:54.488076 3, 0xFFFF, sum = 0
6701 13:41:54.491344 4, 0xFFFF, sum = 0
6702 13:41:54.491802 5, 0xFFFF, sum = 0
6703 13:41:54.494649 6, 0xFFFF, sum = 0
6704 13:41:54.495203 7, 0xFFFF, sum = 0
6705 13:41:54.497588 8, 0xFFFF, sum = 0
6706 13:41:54.500728 9, 0xFFFF, sum = 0
6707 13:41:54.501188 10, 0xFFFF, sum = 0
6708 13:41:54.504473 11, 0xFFFF, sum = 0
6709 13:41:54.505020 12, 0x0, sum = 1
6710 13:41:54.507536 13, 0x0, sum = 2
6711 13:41:54.508084 14, 0x0, sum = 3
6712 13:41:54.510683 15, 0x0, sum = 4
6713 13:41:54.511144 best_step = 13
6714 13:41:54.511498
6715 13:41:54.511832 ==
6716 13:41:54.514308 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 13:41:54.517676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6718 13:41:54.518136 ==
6719 13:41:54.520844 RX Vref Scan: 0
6720 13:41:54.521447
6721 13:41:54.524508 RX Vref 0 -> 0, step: 1
6722 13:41:54.525070
6723 13:41:54.525480 RX Delay -359 -> 252, step: 8
6724 13:41:54.532795 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6725 13:41:54.536281 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6726 13:41:54.539818 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6727 13:41:54.542555 iDelay=225, Bit 3, Center -40 (-287 ~ 208) 496
6728 13:41:54.549531 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6729 13:41:54.552985 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6730 13:41:54.556524 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6731 13:41:54.559525 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6732 13:41:54.565982 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6733 13:41:54.569398 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6734 13:41:54.572244 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6735 13:41:54.575804 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6736 13:41:54.582397 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6737 13:41:54.586019 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6738 13:41:54.589648 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6739 13:41:54.596168 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6740 13:41:54.596638 ==
6741 13:41:54.598947 Dram Type= 6, Freq= 0, CH_1, rank 1
6742 13:41:54.602711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6743 13:41:54.603264 ==
6744 13:41:54.603620 DQS Delay:
6745 13:41:54.605620 DQS0 = 48, DQS1 = 64
6746 13:41:54.606078 DQM Delay:
6747 13:41:54.609138 DQM0 = 10, DQM1 = 15
6748 13:41:54.609636 DQ Delay:
6749 13:41:54.612397 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6750 13:41:54.615880 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6751 13:41:54.619165 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6752 13:41:54.622295 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6753 13:41:54.622750
6754 13:41:54.623099
6755 13:41:54.629159 [DQSOSCAuto] RK1, (LSB)MR18= 0xa1a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6756 13:41:54.632716 CH1 RK1: MR19=C0C, MR18=A1A1
6757 13:41:54.639271 CH1_RK1: MR19=0xC0C, MR18=0xA1A1, DQSOSC=389, MR23=63, INC=390, DEC=260
6758 13:41:54.642106 [RxdqsGatingPostProcess] freq 400
6759 13:41:54.648600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6760 13:41:54.652538 Pre-setting of DQS Precalculation
6761 13:41:54.655243 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6762 13:41:54.662193 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6763 13:41:54.668873 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6764 13:41:54.669668
6765 13:41:54.670052
6766 13:41:54.672008 [Calibration Summary] 800 Mbps
6767 13:41:54.675541 CH 0, Rank 0
6768 13:41:54.676136 SW Impedance : PASS
6769 13:41:54.678168 DUTY Scan : NO K
6770 13:41:54.681865 ZQ Calibration : PASS
6771 13:41:54.682317 Jitter Meter : NO K
6772 13:41:54.684853 CBT Training : PASS
6773 13:41:54.688594 Write leveling : PASS
6774 13:41:54.689143 RX DQS gating : PASS
6775 13:41:54.691387 RX DQ/DQS(RDDQC) : PASS
6776 13:41:54.695058 TX DQ/DQS : PASS
6777 13:41:54.695513 RX DATLAT : PASS
6778 13:41:54.698462 RX DQ/DQS(Engine): PASS
6779 13:41:54.701730 TX OE : NO K
6780 13:41:54.702179 All Pass.
6781 13:41:54.702548
6782 13:41:54.702917 CH 0, Rank 1
6783 13:41:54.705062 SW Impedance : PASS
6784 13:41:54.708232 DUTY Scan : NO K
6785 13:41:54.708785 ZQ Calibration : PASS
6786 13:41:54.711617 Jitter Meter : NO K
6787 13:41:54.712065 CBT Training : PASS
6788 13:41:54.714803 Write leveling : NO K
6789 13:41:54.718027 RX DQS gating : PASS
6790 13:41:54.718479 RX DQ/DQS(RDDQC) : PASS
6791 13:41:54.721183 TX DQ/DQS : PASS
6792 13:41:54.725064 RX DATLAT : PASS
6793 13:41:54.725769 RX DQ/DQS(Engine): PASS
6794 13:41:54.728202 TX OE : NO K
6795 13:41:54.728655 All Pass.
6796 13:41:54.729009
6797 13:41:54.731358 CH 1, Rank 0
6798 13:41:54.731981 SW Impedance : PASS
6799 13:41:54.734692 DUTY Scan : NO K
6800 13:41:54.738180 ZQ Calibration : PASS
6801 13:41:54.738672 Jitter Meter : NO K
6802 13:41:54.741572 CBT Training : PASS
6803 13:41:54.745060 Write leveling : PASS
6804 13:41:54.745671 RX DQS gating : PASS
6805 13:41:54.747728 RX DQ/DQS(RDDQC) : PASS
6806 13:41:54.751263 TX DQ/DQS : PASS
6807 13:41:54.751717 RX DATLAT : PASS
6808 13:41:54.754772 RX DQ/DQS(Engine): PASS
6809 13:41:54.758303 TX OE : NO K
6810 13:41:54.758854 All Pass.
6811 13:41:54.759213
6812 13:41:54.759547 CH 1, Rank 1
6813 13:41:54.761471 SW Impedance : PASS
6814 13:41:54.764510 DUTY Scan : NO K
6815 13:41:54.764963 ZQ Calibration : PASS
6816 13:41:54.768395 Jitter Meter : NO K
6817 13:41:54.769001 CBT Training : PASS
6818 13:41:54.771001 Write leveling : NO K
6819 13:41:54.774471 RX DQS gating : PASS
6820 13:41:54.774919 RX DQ/DQS(RDDQC) : PASS
6821 13:41:54.778269 TX DQ/DQS : PASS
6822 13:41:54.781066 RX DATLAT : PASS
6823 13:41:54.781667 RX DQ/DQS(Engine): PASS
6824 13:41:54.784722 TX OE : NO K
6825 13:41:54.785229 All Pass.
6826 13:41:54.785702
6827 13:41:54.788218 DramC Write-DBI off
6828 13:41:54.791142 PER_BANK_REFRESH: Hybrid Mode
6829 13:41:54.791597 TX_TRACKING: ON
6830 13:41:54.800669 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6831 13:41:54.804410 [FAST_K] Save calibration result to emmc
6832 13:41:54.808041 dramc_set_vcore_voltage set vcore to 725000
6833 13:41:54.811314 Read voltage for 1600, 0
6834 13:41:54.811913 Vio18 = 0
6835 13:41:54.812275 Vcore = 725000
6836 13:41:54.814008 Vdram = 0
6837 13:41:54.814462 Vddq = 0
6838 13:41:54.814816 Vmddr = 0
6839 13:41:54.820768 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6840 13:41:54.824276 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6841 13:41:54.827638 MEM_TYPE=3, freq_sel=13
6842 13:41:54.830642 sv_algorithm_assistance_LP4_3733
6843 13:41:54.833888 ============ PULL DRAM RESETB DOWN ============
6844 13:41:54.840564 ========== PULL DRAM RESETB DOWN end =========
6845 13:41:54.844202 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6846 13:41:54.846983 ===================================
6847 13:41:54.850709 LPDDR4 DRAM CONFIGURATION
6848 13:41:54.853976 ===================================
6849 13:41:54.854438 EX_ROW_EN[0] = 0x0
6850 13:41:54.856940 EX_ROW_EN[1] = 0x0
6851 13:41:54.857425 LP4Y_EN = 0x0
6852 13:41:54.860726 WORK_FSP = 0x1
6853 13:41:54.861327 WL = 0x5
6854 13:41:54.864142 RL = 0x5
6855 13:41:54.864699 BL = 0x2
6856 13:41:54.867105 RPST = 0x0
6857 13:41:54.867663 RD_PRE = 0x0
6858 13:41:54.870439 WR_PRE = 0x1
6859 13:41:54.870894 WR_PST = 0x1
6860 13:41:54.873980 DBI_WR = 0x0
6861 13:41:54.876979 DBI_RD = 0x0
6862 13:41:54.877478 OTF = 0x1
6863 13:41:54.880519 ===================================
6864 13:41:54.883476 ===================================
6865 13:41:54.883944 ANA top config
6866 13:41:54.886985 ===================================
6867 13:41:54.890406 DLL_ASYNC_EN = 0
6868 13:41:54.893598 ALL_SLAVE_EN = 0
6869 13:41:54.896935 NEW_RANK_MODE = 1
6870 13:41:54.900400 DLL_IDLE_MODE = 1
6871 13:41:54.900859 LP45_APHY_COMB_EN = 1
6872 13:41:54.903539 TX_ODT_DIS = 0
6873 13:41:54.906865 NEW_8X_MODE = 1
6874 13:41:54.910337 ===================================
6875 13:41:54.913737 ===================================
6876 13:41:54.917128 data_rate = 3200
6877 13:41:54.920060 CKR = 1
6878 13:41:54.920516 DQ_P2S_RATIO = 8
6879 13:41:54.923831 ===================================
6880 13:41:54.926680 CA_P2S_RATIO = 8
6881 13:41:54.930334 DQ_CA_OPEN = 0
6882 13:41:54.933620 DQ_SEMI_OPEN = 0
6883 13:41:54.936860 CA_SEMI_OPEN = 0
6884 13:41:54.940389 CA_FULL_RATE = 0
6885 13:41:54.940940 DQ_CKDIV4_EN = 0
6886 13:41:54.943641 CA_CKDIV4_EN = 0
6887 13:41:54.947120 CA_PREDIV_EN = 0
6888 13:41:54.950388 PH8_DLY = 12
6889 13:41:54.953457 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6890 13:41:54.956985 DQ_AAMCK_DIV = 4
6891 13:41:54.957488 CA_AAMCK_DIV = 4
6892 13:41:54.960148 CA_ADMCK_DIV = 4
6893 13:41:54.963008 DQ_TRACK_CA_EN = 0
6894 13:41:54.966704 CA_PICK = 1600
6895 13:41:54.970083 CA_MCKIO = 1600
6896 13:41:54.972981 MCKIO_SEMI = 0
6897 13:41:54.976983 PLL_FREQ = 3068
6898 13:41:54.979713 DQ_UI_PI_RATIO = 32
6899 13:41:54.980169 CA_UI_PI_RATIO = 0
6900 13:41:54.983286 ===================================
6901 13:41:54.986292 ===================================
6902 13:41:54.989968 memory_type:LPDDR4
6903 13:41:54.993521 GP_NUM : 10
6904 13:41:54.994068 SRAM_EN : 1
6905 13:41:54.996466 MD32_EN : 0
6906 13:41:54.999845 ===================================
6907 13:41:55.003379 [ANA_INIT] >>>>>>>>>>>>>>
6908 13:41:55.006258 <<<<<< [CONFIGURE PHASE]: ANA_TX
6909 13:41:55.009929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6910 13:41:55.013079 ===================================
6911 13:41:55.013581 data_rate = 3200,PCW = 0X7600
6912 13:41:55.016689 ===================================
6913 13:41:55.019699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6914 13:41:55.026567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6915 13:41:55.032911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6916 13:41:55.035920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6917 13:41:55.039748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6918 13:41:55.043092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6919 13:41:55.046019 [ANA_INIT] flow start
6920 13:41:55.046509 [ANA_INIT] PLL >>>>>>>>
6921 13:41:55.049684 [ANA_INIT] PLL <<<<<<<<
6922 13:41:55.052908 [ANA_INIT] MIDPI >>>>>>>>
6923 13:41:55.055951 [ANA_INIT] MIDPI <<<<<<<<
6924 13:41:55.056500 [ANA_INIT] DLL >>>>>>>>
6925 13:41:55.059226 [ANA_INIT] DLL <<<<<<<<
6926 13:41:55.062425 [ANA_INIT] flow end
6927 13:41:55.065844 ============ LP4 DIFF to SE enter ============
6928 13:41:55.068881 ============ LP4 DIFF to SE exit ============
6929 13:41:55.072500 [ANA_INIT] <<<<<<<<<<<<<
6930 13:41:55.075655 [Flow] Enable top DCM control >>>>>
6931 13:41:55.079272 [Flow] Enable top DCM control <<<<<
6932 13:41:55.082333 Enable DLL master slave shuffle
6933 13:41:55.086265 ==============================================================
6934 13:41:55.088917 Gating Mode config
6935 13:41:55.095494 ==============================================================
6936 13:41:55.095947 Config description:
6937 13:41:55.105962 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6938 13:41:55.111967 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6939 13:41:55.115924 SELPH_MODE 0: By rank 1: By Phase
6940 13:41:55.122360 ==============================================================
6941 13:41:55.125253 GAT_TRACK_EN = 1
6942 13:41:55.128725 RX_GATING_MODE = 2
6943 13:41:55.132152 RX_GATING_TRACK_MODE = 2
6944 13:41:55.135879 SELPH_MODE = 1
6945 13:41:55.138657 PICG_EARLY_EN = 1
6946 13:41:55.141728 VALID_LAT_VALUE = 1
6947 13:41:55.145415 ==============================================================
6948 13:41:55.148855 Enter into Gating configuration >>>>
6949 13:41:55.151832 Exit from Gating configuration <<<<
6950 13:41:55.155089 Enter into DVFS_PRE_config >>>>>
6951 13:41:55.168810 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6952 13:41:55.169426 Exit from DVFS_PRE_config <<<<<
6953 13:41:55.171611 Enter into PICG configuration >>>>
6954 13:41:55.174809 Exit from PICG configuration <<<<
6955 13:41:55.178116 [RX_INPUT] configuration >>>>>
6956 13:41:55.181722 [RX_INPUT] configuration <<<<<
6957 13:41:55.188624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6958 13:41:55.191288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6959 13:41:55.197950 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6960 13:41:55.204573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6961 13:41:55.211143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6962 13:41:55.218221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6963 13:41:55.221266 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6964 13:41:55.224859 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6965 13:41:55.227817 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6966 13:41:55.234346 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6967 13:41:55.237897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6968 13:41:55.241026 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6969 13:41:55.244591 ===================================
6970 13:41:55.247392 LPDDR4 DRAM CONFIGURATION
6971 13:41:55.251328 ===================================
6972 13:41:55.253994 EX_ROW_EN[0] = 0x0
6973 13:41:55.254451 EX_ROW_EN[1] = 0x0
6974 13:41:55.258171 LP4Y_EN = 0x0
6975 13:41:55.258847 WORK_FSP = 0x1
6976 13:41:55.260628 WL = 0x5
6977 13:41:55.261080 RL = 0x5
6978 13:41:55.264023 BL = 0x2
6979 13:41:55.264475 RPST = 0x0
6980 13:41:55.267924 RD_PRE = 0x0
6981 13:41:55.268476 WR_PRE = 0x1
6982 13:41:55.270760 WR_PST = 0x1
6983 13:41:55.271227 DBI_WR = 0x0
6984 13:41:55.273951 DBI_RD = 0x0
6985 13:41:55.274406 OTF = 0x1
6986 13:41:55.277691 ===================================
6987 13:41:55.283958 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6988 13:41:55.287495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6989 13:41:55.290979 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6990 13:41:55.294430 ===================================
6991 13:41:55.297354 LPDDR4 DRAM CONFIGURATION
6992 13:41:55.300303 ===================================
6993 13:41:55.303885 EX_ROW_EN[0] = 0x10
6994 13:41:55.304384 EX_ROW_EN[1] = 0x0
6995 13:41:55.307485 LP4Y_EN = 0x0
6996 13:41:55.307935 WORK_FSP = 0x1
6997 13:41:55.310424 WL = 0x5
6998 13:41:55.310875 RL = 0x5
6999 13:41:55.314210 BL = 0x2
7000 13:41:55.314762 RPST = 0x0
7001 13:41:55.316887 RD_PRE = 0x0
7002 13:41:55.317417 WR_PRE = 0x1
7003 13:41:55.320350 WR_PST = 0x1
7004 13:41:55.320798 DBI_WR = 0x0
7005 13:41:55.323990 DBI_RD = 0x0
7006 13:41:55.324437 OTF = 0x1
7007 13:41:55.326893 ===================================
7008 13:41:55.333369 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7009 13:41:55.333841 ==
7010 13:41:55.337375 Dram Type= 6, Freq= 0, CH_0, rank 0
7011 13:41:55.343753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7012 13:41:55.344305 ==
7013 13:41:55.344666 [Duty_Offset_Calibration]
7014 13:41:55.346595 B0:0 B1:2 CA:1
7015 13:41:55.347045
7016 13:41:55.350185 [DutyScan_Calibration_Flow] k_type=0
7017 13:41:55.359658
7018 13:41:55.360110 ==CLK 0==
7019 13:41:55.362692 Final CLK duty delay cell = 0
7020 13:41:55.366142 [0] MAX Duty = 5156%(X100), DQS PI = 22
7021 13:41:55.369257 [0] MIN Duty = 4938%(X100), DQS PI = 52
7022 13:41:55.372768 [0] AVG Duty = 5047%(X100)
7023 13:41:55.373216
7024 13:41:55.376363 CH0 CLK Duty spec in!! Max-Min= 218%
7025 13:41:55.379486 [DutyScan_Calibration_Flow] ====Done====
7026 13:41:55.380037
7027 13:41:55.382504 [DutyScan_Calibration_Flow] k_type=1
7028 13:41:55.400013
7029 13:41:55.400832 ==DQS 0 ==
7030 13:41:55.403076 Final DQS duty delay cell = 0
7031 13:41:55.406525 [0] MAX Duty = 5125%(X100), DQS PI = 22
7032 13:41:55.409569 [0] MIN Duty = 5031%(X100), DQS PI = 8
7033 13:41:55.412869 [0] AVG Duty = 5078%(X100)
7034 13:41:55.413511
7035 13:41:55.414027 ==DQS 1 ==
7036 13:41:55.416370 Final DQS duty delay cell = 0
7037 13:41:55.419741 [0] MAX Duty = 5031%(X100), DQS PI = 6
7038 13:41:55.423127 [0] MIN Duty = 4876%(X100), DQS PI = 18
7039 13:41:55.423579 [0] AVG Duty = 4953%(X100)
7040 13:41:55.426057
7041 13:41:55.429703 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7042 13:41:55.430153
7043 13:41:55.432611 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7044 13:41:55.436290 [DutyScan_Calibration_Flow] ====Done====
7045 13:41:55.437027
7046 13:41:55.439215 [DutyScan_Calibration_Flow] k_type=3
7047 13:41:55.456729
7048 13:41:55.457692 ==DQM 0 ==
7049 13:41:55.460083 Final DQM duty delay cell = 0
7050 13:41:55.463128 [0] MAX Duty = 5187%(X100), DQS PI = 24
7051 13:41:55.466590 [0] MIN Duty = 4907%(X100), DQS PI = 56
7052 13:41:55.470117 [0] AVG Duty = 5047%(X100)
7053 13:41:55.470573
7054 13:41:55.470929 ==DQM 1 ==
7055 13:41:55.473080 Final DQM duty delay cell = 0
7056 13:41:55.476558 [0] MAX Duty = 5031%(X100), DQS PI = 52
7057 13:41:55.479537 [0] MIN Duty = 4782%(X100), DQS PI = 12
7058 13:41:55.483021 [0] AVG Duty = 4906%(X100)
7059 13:41:55.483506
7060 13:41:55.486713 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7061 13:41:55.487243
7062 13:41:55.489697 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7063 13:41:55.493193 [DutyScan_Calibration_Flow] ====Done====
7064 13:41:55.493700
7065 13:41:55.496633 [DutyScan_Calibration_Flow] k_type=2
7066 13:41:55.513162
7067 13:41:55.513787 ==DQ 0 ==
7068 13:41:55.516618 Final DQ duty delay cell = 0
7069 13:41:55.519557 [0] MAX Duty = 5218%(X100), DQS PI = 18
7070 13:41:55.522853 [0] MIN Duty = 4938%(X100), DQS PI = 56
7071 13:41:55.523329 [0] AVG Duty = 5078%(X100)
7072 13:41:55.526401
7073 13:41:55.526955 ==DQ 1 ==
7074 13:41:55.529781 Final DQ duty delay cell = -4
7075 13:41:55.533220 [-4] MAX Duty = 5094%(X100), DQS PI = 6
7076 13:41:55.536302 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7077 13:41:55.539258 [-4] AVG Duty = 4969%(X100)
7078 13:41:55.539707
7079 13:41:55.542746 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7080 13:41:55.543198
7081 13:41:55.546650 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7082 13:41:55.549391 [DutyScan_Calibration_Flow] ====Done====
7083 13:41:55.549848 ==
7084 13:41:55.553239 Dram Type= 6, Freq= 0, CH_1, rank 0
7085 13:41:55.556149 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7086 13:41:55.556704 ==
7087 13:41:55.559616 [Duty_Offset_Calibration]
7088 13:41:55.560097 B0:0 B1:4 CA:-5
7089 13:41:55.560455
7090 13:41:55.562664 [DutyScan_Calibration_Flow] k_type=0
7091 13:41:55.573477
7092 13:41:55.573927 ==CLK 0==
7093 13:41:55.577022 Final CLK duty delay cell = 0
7094 13:41:55.580292 [0] MAX Duty = 5156%(X100), DQS PI = 22
7095 13:41:55.583655 [0] MIN Duty = 4906%(X100), DQS PI = 50
7096 13:41:55.584113 [0] AVG Duty = 5031%(X100)
7097 13:41:55.586867
7098 13:41:55.590277 CH1 CLK Duty spec in!! Max-Min= 250%
7099 13:41:55.593849 [DutyScan_Calibration_Flow] ====Done====
7100 13:41:55.594399
7101 13:41:55.596899 [DutyScan_Calibration_Flow] k_type=1
7102 13:41:55.612916
7103 13:41:55.613510 ==DQS 0 ==
7104 13:41:55.615848 Final DQS duty delay cell = 0
7105 13:41:55.619092 [0] MAX Duty = 5187%(X100), DQS PI = 20
7106 13:41:55.622295 [0] MIN Duty = 4907%(X100), DQS PI = 44
7107 13:41:55.625972 [0] AVG Duty = 5047%(X100)
7108 13:41:55.626523
7109 13:41:55.626880 ==DQS 1 ==
7110 13:41:55.629345 Final DQS duty delay cell = -4
7111 13:41:55.631943 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7112 13:41:55.635325 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7113 13:41:55.638871 [-4] AVG Duty = 4922%(X100)
7114 13:41:55.639432
7115 13:41:55.642365 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7116 13:41:55.642830
7117 13:41:55.645414 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7118 13:41:55.648572 [DutyScan_Calibration_Flow] ====Done====
7119 13:41:55.649025
7120 13:41:55.652172 [DutyScan_Calibration_Flow] k_type=3
7121 13:41:55.668186
7122 13:41:55.668742 ==DQM 0 ==
7123 13:41:55.671384 Final DQM duty delay cell = -4
7124 13:41:55.674775 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7125 13:41:55.677923 [-4] MIN Duty = 4813%(X100), DQS PI = 40
7126 13:41:55.681736 [-4] AVG Duty = 4953%(X100)
7127 13:41:55.682294
7128 13:41:55.682655 ==DQM 1 ==
7129 13:41:55.684896 Final DQM duty delay cell = -4
7130 13:41:55.688259 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7131 13:41:55.691538 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7132 13:41:55.695179 [-4] AVG Duty = 5000%(X100)
7133 13:41:55.695734
7134 13:41:55.697993 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7135 13:41:55.698446
7136 13:41:55.701790 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7137 13:41:55.704782 [DutyScan_Calibration_Flow] ====Done====
7138 13:41:55.705406
7139 13:41:55.708285 [DutyScan_Calibration_Flow] k_type=2
7140 13:41:55.726161
7141 13:41:55.726704 ==DQ 0 ==
7142 13:41:55.729240 Final DQ duty delay cell = 0
7143 13:41:55.732501 [0] MAX Duty = 5093%(X100), DQS PI = 20
7144 13:41:55.735459 [0] MIN Duty = 4938%(X100), DQS PI = 46
7145 13:41:55.738894 [0] AVG Duty = 5015%(X100)
7146 13:41:55.739340
7147 13:41:55.739694 ==DQ 1 ==
7148 13:41:55.742709 Final DQ duty delay cell = 0
7149 13:41:55.745917 [0] MAX Duty = 5031%(X100), DQS PI = 2
7150 13:41:55.748952 [0] MIN Duty = 4876%(X100), DQS PI = 28
7151 13:41:55.749458 [0] AVG Duty = 4953%(X100)
7152 13:41:55.752480
7153 13:41:55.755975 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7154 13:41:55.756539
7155 13:41:55.759148 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7156 13:41:55.762177 [DutyScan_Calibration_Flow] ====Done====
7157 13:41:55.766162 nWR fixed to 30
7158 13:41:55.766710 [ModeRegInit_LP4] CH0 RK0
7159 13:41:55.768848 [ModeRegInit_LP4] CH0 RK1
7160 13:41:55.771813 [ModeRegInit_LP4] CH1 RK0
7161 13:41:55.775694 [ModeRegInit_LP4] CH1 RK1
7162 13:41:55.776202 match AC timing 4
7163 13:41:55.782213 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7164 13:41:55.785357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7165 13:41:55.788238 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7166 13:41:55.795295 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7167 13:41:55.798813 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7168 13:41:55.799405 [MiockJmeterHQA]
7169 13:41:55.799765
7170 13:41:55.801854 [DramcMiockJmeter] u1RxGatingPI = 0
7171 13:41:55.804891 0 : 4255, 4029
7172 13:41:55.805409 4 : 4252, 4027
7173 13:41:55.808872 8 : 4255, 4029
7174 13:41:55.809486 12 : 4365, 4139
7175 13:41:55.809859 16 : 4253, 4027
7176 13:41:55.811705 20 : 4255, 4029
7177 13:41:55.812263 24 : 4253, 4027
7178 13:41:55.815168 28 : 4363, 4137
7179 13:41:55.815722 32 : 4252, 4027
7180 13:41:55.818813 36 : 4363, 4137
7181 13:41:55.819371 40 : 4253, 4026
7182 13:41:55.822172 44 : 4252, 4027
7183 13:41:55.822731 48 : 4252, 4026
7184 13:41:55.823094 52 : 4255, 4029
7185 13:41:55.825484 56 : 4363, 4138
7186 13:41:55.826036 60 : 4250, 4027
7187 13:41:55.828379 64 : 4360, 4138
7188 13:41:55.828833 68 : 4250, 4026
7189 13:41:55.832103 72 : 4250, 4027
7190 13:41:55.832657 76 : 4250, 4027
7191 13:41:55.835364 80 : 4361, 4137
7192 13:41:55.835833 84 : 4250, 4027
7193 13:41:55.836460 88 : 4361, 4137
7194 13:41:55.838380 92 : 4250, 4027
7195 13:41:55.838837 96 : 4250, 4027
7196 13:41:55.841865 100 : 4250, 1948
7197 13:41:55.842341 104 : 4250, 0
7198 13:41:55.845184 108 : 4363, 0
7199 13:41:55.845729 112 : 4250, 0
7200 13:41:55.846091 116 : 4250, 0
7201 13:41:55.848289 120 : 4250, 0
7202 13:41:55.848864 124 : 4250, 0
7203 13:41:55.849237 128 : 4252, 0
7204 13:41:55.851760 132 : 4361, 0
7205 13:41:55.852311 136 : 4250, 0
7206 13:41:55.855108 140 : 4250, 0
7207 13:41:55.855681 144 : 4250, 0
7208 13:41:55.856051 148 : 4361, 0
7209 13:41:55.858387 152 : 4360, 0
7210 13:41:55.858846 156 : 4250, 0
7211 13:41:55.861914 160 : 4250, 0
7212 13:41:55.862372 164 : 4250, 0
7213 13:41:55.862737 168 : 4252, 0
7214 13:41:55.865097 172 : 4250, 0
7215 13:41:55.865692 176 : 4250, 0
7216 13:41:55.868192 180 : 4252, 0
7217 13:41:55.868753 184 : 4361, 0
7218 13:41:55.869115 188 : 4250, 0
7219 13:41:55.871452 192 : 4250, 0
7220 13:41:55.871910 196 : 4250, 0
7221 13:41:55.874911 200 : 4361, 0
7222 13:41:55.875369 204 : 4360, 0
7223 13:41:55.875729 208 : 4250, 0
7224 13:41:55.878485 212 : 4250, 0
7225 13:41:55.879042 216 : 4360, 0
7226 13:41:55.879405 220 : 4250, 729
7227 13:41:55.881459 224 : 4250, 4022
7228 13:41:55.881922 228 : 4250, 4027
7229 13:41:55.884965 232 : 4360, 4138
7230 13:41:55.885457 236 : 4250, 4027
7231 13:41:55.888272 240 : 4250, 4027
7232 13:41:55.888845 244 : 4360, 4138
7233 13:41:55.891310 248 : 4361, 4137
7234 13:41:55.891864 252 : 4250, 4027
7235 13:41:55.894483 256 : 4363, 4140
7236 13:41:55.894943 260 : 4360, 4138
7237 13:41:55.898537 264 : 4250, 4026
7238 13:41:55.899274 268 : 4250, 4027
7239 13:41:55.901228 272 : 4252, 4030
7240 13:41:55.901737 276 : 4250, 4027
7241 13:41:55.904921 280 : 4250, 4026
7242 13:41:55.905572 284 : 4250, 4027
7243 13:41:55.905983 288 : 4252, 4029
7244 13:41:55.907956 292 : 4250, 4027
7245 13:41:55.908540 296 : 4361, 4137
7246 13:41:55.911196 300 : 4361, 4138
7247 13:41:55.911657 304 : 4250, 4027
7248 13:41:55.914898 308 : 4363, 4140
7249 13:41:55.915455 312 : 4360, 4138
7250 13:41:55.917488 316 : 4250, 4027
7251 13:41:55.917951 320 : 4250, 4027
7252 13:41:55.921413 324 : 4252, 4029
7253 13:41:55.921979 328 : 4250, 4027
7254 13:41:55.924243 332 : 4250, 4026
7255 13:41:55.924700 336 : 4250, 3644
7256 13:41:55.927885 340 : 4252, 1633
7257 13:41:55.928347
7258 13:41:55.928704 MIOCK jitter meter ch=0
7259 13:41:55.929036
7260 13:41:55.930872 1T = (340-100) = 240 dly cells
7261 13:41:55.937445 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7262 13:41:55.937898 ==
7263 13:41:55.941021 Dram Type= 6, Freq= 0, CH_0, rank 0
7264 13:41:55.944314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7265 13:41:55.944866 ==
7266 13:41:55.950550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7267 13:41:55.954112 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7268 13:41:55.960528 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7269 13:41:55.964094 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7270 13:41:55.973211 [CA 0] Center 42 (12~73) winsize 62
7271 13:41:55.976771 [CA 1] Center 42 (12~73) winsize 62
7272 13:41:55.979734 [CA 2] Center 39 (9~69) winsize 61
7273 13:41:55.983044 [CA 3] Center 38 (9~68) winsize 60
7274 13:41:55.986824 [CA 4] Center 36 (6~67) winsize 62
7275 13:41:55.989842 [CA 5] Center 36 (6~66) winsize 61
7276 13:41:55.990295
7277 13:41:55.993438 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7278 13:41:55.993986
7279 13:41:55.996083 [CATrainingPosCal] consider 1 rank data
7280 13:41:55.999601 u2DelayCellTimex100 = 271/100 ps
7281 13:41:56.002898 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7282 13:41:56.009603 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7283 13:41:56.012762 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7284 13:41:56.016298 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7285 13:41:56.019950 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7286 13:41:56.022662 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7287 13:41:56.023114
7288 13:41:56.026312 CA PerBit enable=1, Macro0, CA PI delay=36
7289 13:41:56.026859
7290 13:41:56.029227 [CBTSetCACLKResult] CA Dly = 36
7291 13:41:56.033026 CS Dly: 10 (0~41)
7292 13:41:56.035781 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7293 13:41:56.039451 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7294 13:41:56.040001 ==
7295 13:41:56.043095 Dram Type= 6, Freq= 0, CH_0, rank 1
7296 13:41:56.049660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7297 13:41:56.050215 ==
7298 13:41:56.052427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7299 13:41:56.056324 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7300 13:41:56.062875 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7301 13:41:56.069126 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7302 13:41:56.076343 [CA 0] Center 42 (12~73) winsize 62
7303 13:41:56.079161 [CA 1] Center 41 (11~72) winsize 62
7304 13:41:56.082849 [CA 2] Center 38 (9~68) winsize 60
7305 13:41:56.085393 [CA 3] Center 37 (7~67) winsize 61
7306 13:41:56.089036 [CA 4] Center 35 (5~65) winsize 61
7307 13:41:56.091885 [CA 5] Center 35 (5~66) winsize 62
7308 13:41:56.092336
7309 13:41:56.095646 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7310 13:41:56.096194
7311 13:41:56.102055 [CATrainingPosCal] consider 2 rank data
7312 13:41:56.102595 u2DelayCellTimex100 = 271/100 ps
7313 13:41:56.109024 CA0 delay=42 (12~73),Diff = 7 PI (25 cell)
7314 13:41:56.112496 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7315 13:41:56.115442 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7316 13:41:56.118838 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7317 13:41:56.122014 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7318 13:41:56.125201 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7319 13:41:56.125718
7320 13:41:56.128427 CA PerBit enable=1, Macro0, CA PI delay=35
7321 13:41:56.128947
7322 13:41:56.132096 [CBTSetCACLKResult] CA Dly = 35
7323 13:41:56.135430 CS Dly: 11 (0~43)
7324 13:41:56.138973 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7325 13:41:56.142002 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7326 13:41:56.142451
7327 13:41:56.145104 ----->DramcWriteLeveling(PI) begin...
7328 13:41:56.145608 ==
7329 13:41:56.148565 Dram Type= 6, Freq= 0, CH_0, rank 0
7330 13:41:56.155231 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7331 13:41:56.155686 ==
7332 13:41:56.158195 Write leveling (Byte 0): 29 => 29
7333 13:41:56.161724 Write leveling (Byte 1): 25 => 25
7334 13:41:56.162179 DramcWriteLeveling(PI) end<-----
7335 13:41:56.164405
7336 13:41:56.164486 ==
7337 13:41:56.168105 Dram Type= 6, Freq= 0, CH_0, rank 0
7338 13:41:56.171358 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7339 13:41:56.171516 ==
7340 13:41:56.174865 [Gating] SW mode calibration
7341 13:41:56.181202 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7342 13:41:56.184426 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7343 13:41:56.191231 0 12 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7344 13:41:56.194478 0 12 4 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7345 13:41:56.197876 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7346 13:41:56.204208 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7347 13:41:56.207668 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7348 13:41:56.211460 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7349 13:41:56.217842 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7350 13:41:56.221105 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7351 13:41:56.224656 0 13 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7352 13:41:56.231852 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
7353 13:41:56.234465 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7354 13:41:56.237999 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7355 13:41:56.244510 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7356 13:41:56.247671 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7357 13:41:56.250938 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7358 13:41:56.257607 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7359 13:41:56.261189 0 14 0 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7360 13:41:56.264257 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7361 13:41:56.270777 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7362 13:41:56.274138 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7363 13:41:56.277091 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7364 13:41:56.283792 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7365 13:41:56.287296 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7366 13:41:56.290410 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7367 13:41:56.297247 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7368 13:41:56.300501 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7369 13:41:56.304054 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7370 13:41:56.310549 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7371 13:41:56.313931 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7372 13:41:56.317037 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7373 13:41:56.323550 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7374 13:41:56.326807 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7375 13:41:56.330317 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7376 13:41:56.336750 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7377 13:41:56.340483 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7378 13:41:56.343718 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7379 13:41:56.350295 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7380 13:41:56.353691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7381 13:41:56.357172 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7382 13:41:56.363218 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7383 13:41:56.366868 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7384 13:41:56.370270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7385 13:41:56.376656 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7386 13:41:56.377213 Total UI for P1: 0, mck2ui 16
7387 13:41:56.383389 best dqsien dly found for B0: ( 1, 0, 30)
7388 13:41:56.383943 Total UI for P1: 0, mck2ui 16
7389 13:41:56.386704 best dqsien dly found for B1: ( 1, 1, 4)
7390 13:41:56.393386 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7391 13:41:56.396920 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7392 13:41:56.397528
7393 13:41:56.400026 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7394 13:41:56.403395 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7395 13:41:56.406348 [Gating] SW calibration Done
7396 13:41:56.406796 ==
7397 13:41:56.409883 Dram Type= 6, Freq= 0, CH_0, rank 0
7398 13:41:56.412908 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7399 13:41:56.413425 ==
7400 13:41:56.416631 RX Vref Scan: 0
7401 13:41:56.417193
7402 13:41:56.417710 RX Vref 0 -> 0, step: 1
7403 13:41:56.418165
7404 13:41:56.419479 RX Delay 0 -> 252, step: 8
7405 13:41:56.422973 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7406 13:41:56.426253 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7407 13:41:56.433124 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7408 13:41:56.436028 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7409 13:41:56.439957 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7410 13:41:56.442912 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7411 13:41:56.446154 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7412 13:41:56.452529 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7413 13:41:56.456073 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7414 13:41:56.459389 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7415 13:41:56.462759 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7416 13:41:56.469039 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7417 13:41:56.472749 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7418 13:41:56.476319 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7419 13:41:56.479312 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7420 13:41:56.482654 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7421 13:41:56.485552 ==
7422 13:41:56.486084 Dram Type= 6, Freq= 0, CH_0, rank 0
7423 13:41:56.492644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7424 13:41:56.493120 ==
7425 13:41:56.493634 DQS Delay:
7426 13:41:56.495566 DQS0 = 0, DQS1 = 0
7427 13:41:56.496039 DQM Delay:
7428 13:41:56.499036 DQM0 = 130, DQM1 = 125
7429 13:41:56.499619 DQ Delay:
7430 13:41:56.502613 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7431 13:41:56.505648 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7432 13:41:56.509224 DQ8 =115, DQ9 =107, DQ10 =127, DQ11 =115
7433 13:41:56.512385 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7434 13:41:56.512969
7435 13:41:56.513381
7436 13:41:56.513726 ==
7437 13:41:56.515385 Dram Type= 6, Freq= 0, CH_0, rank 0
7438 13:41:56.522249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7439 13:41:56.522710 ==
7440 13:41:56.523069
7441 13:41:56.523401
7442 13:41:56.523723 TX Vref Scan disable
7443 13:41:56.525783 == TX Byte 0 ==
7444 13:41:56.529178 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7445 13:41:56.535592 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7446 13:41:56.536127 == TX Byte 1 ==
7447 13:41:56.538958 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7448 13:41:56.545594 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7449 13:41:56.546047 ==
7450 13:41:56.548900 Dram Type= 6, Freq= 0, CH_0, rank 0
7451 13:41:56.552098 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7452 13:41:56.552585 ==
7453 13:41:56.563697
7454 13:41:56.567164 TX Vref early break, caculate TX vref
7455 13:41:56.570162 TX Vref=16, minBit 8, minWin=22, winSum=370
7456 13:41:56.573666 TX Vref=18, minBit 8, minWin=22, winSum=377
7457 13:41:56.576862 TX Vref=20, minBit 8, minWin=22, winSum=384
7458 13:41:56.580109 TX Vref=22, minBit 10, minWin=23, winSum=395
7459 13:41:56.583623 TX Vref=24, minBit 8, minWin=24, winSum=407
7460 13:41:56.590570 TX Vref=26, minBit 9, minWin=24, winSum=413
7461 13:41:56.593540 TX Vref=28, minBit 8, minWin=25, winSum=418
7462 13:41:56.597281 TX Vref=30, minBit 8, minWin=24, winSum=410
7463 13:41:56.600260 TX Vref=32, minBit 6, minWin=24, winSum=396
7464 13:41:56.607045 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
7465 13:41:56.607554
7466 13:41:56.609946 Final TX Range 0 Vref 28
7467 13:41:56.610619
7468 13:41:56.611058 ==
7469 13:41:56.613506 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 13:41:56.616388 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7471 13:41:56.616795 ==
7472 13:41:56.617112
7473 13:41:56.617463
7474 13:41:56.619895 TX Vref Scan disable
7475 13:41:56.626376 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7476 13:41:56.626784 == TX Byte 0 ==
7477 13:41:56.629915 u2DelayCellOfst[0]=14 cells (4 PI)
7478 13:41:56.633340 u2DelayCellOfst[1]=18 cells (5 PI)
7479 13:41:56.636805 u2DelayCellOfst[2]=14 cells (4 PI)
7480 13:41:56.639747 u2DelayCellOfst[3]=10 cells (3 PI)
7481 13:41:56.643361 u2DelayCellOfst[4]=10 cells (3 PI)
7482 13:41:56.646538 u2DelayCellOfst[5]=0 cells (0 PI)
7483 13:41:56.649575 u2DelayCellOfst[6]=18 cells (5 PI)
7484 13:41:56.650040 u2DelayCellOfst[7]=18 cells (5 PI)
7485 13:41:56.656582 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7486 13:41:56.659803 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7487 13:41:56.660352 == TX Byte 1 ==
7488 13:41:56.663339 u2DelayCellOfst[8]=3 cells (1 PI)
7489 13:41:56.666523 u2DelayCellOfst[9]=0 cells (0 PI)
7490 13:41:56.669695 u2DelayCellOfst[10]=14 cells (4 PI)
7491 13:41:56.672741 u2DelayCellOfst[11]=3 cells (1 PI)
7492 13:41:56.676150 u2DelayCellOfst[12]=14 cells (4 PI)
7493 13:41:56.679858 u2DelayCellOfst[13]=14 cells (4 PI)
7494 13:41:56.682605 u2DelayCellOfst[14]=18 cells (5 PI)
7495 13:41:56.686068 u2DelayCellOfst[15]=14 cells (4 PI)
7496 13:41:56.689285 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7497 13:41:56.695961 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7498 13:41:56.696536 DramC Write-DBI on
7499 13:41:56.696887 ==
7500 13:41:56.699434 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 13:41:56.702242 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7502 13:41:56.705985 ==
7503 13:41:56.706290
7504 13:41:56.706540
7505 13:41:56.706738 TX Vref Scan disable
7506 13:41:56.709788 == TX Byte 0 ==
7507 13:41:56.712794 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7508 13:41:56.716432 == TX Byte 1 ==
7509 13:41:56.719557 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7510 13:41:56.722571 DramC Write-DBI off
7511 13:41:56.722842
7512 13:41:56.722998 [DATLAT]
7513 13:41:56.723144 Freq=1600, CH0 RK0
7514 13:41:56.723281
7515 13:41:56.725912 DATLAT Default: 0xf
7516 13:41:56.726097 0, 0xFFFF, sum = 0
7517 13:41:56.728937 1, 0xFFFF, sum = 0
7518 13:41:56.732820 2, 0xFFFF, sum = 0
7519 13:41:56.733134 3, 0xFFFF, sum = 0
7520 13:41:56.735740 4, 0xFFFF, sum = 0
7521 13:41:56.736053 5, 0xFFFF, sum = 0
7522 13:41:56.739595 6, 0xFFFF, sum = 0
7523 13:41:56.739960 7, 0xFFFF, sum = 0
7524 13:41:56.742264 8, 0xFFFF, sum = 0
7525 13:41:56.742585 9, 0xFFFF, sum = 0
7526 13:41:56.745954 10, 0xFFFF, sum = 0
7527 13:41:56.746304 11, 0xFFFF, sum = 0
7528 13:41:56.749126 12, 0xFFF, sum = 0
7529 13:41:56.749668 13, 0x0, sum = 1
7530 13:41:56.752532 14, 0x0, sum = 2
7531 13:41:56.752987 15, 0x0, sum = 3
7532 13:41:56.756069 16, 0x0, sum = 4
7533 13:41:56.756626 best_step = 14
7534 13:41:56.756983
7535 13:41:56.757463 ==
7536 13:41:56.758926 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 13:41:56.762116 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7538 13:41:56.765768 ==
7539 13:41:56.766220 RX Vref Scan: 1
7540 13:41:56.766574
7541 13:41:56.769012 Set Vref Range= 24 -> 127
7542 13:41:56.769532
7543 13:41:56.772173 RX Vref 24 -> 127, step: 1
7544 13:41:56.772654
7545 13:41:56.773050 RX Delay 11 -> 252, step: 4
7546 13:41:56.773447
7547 13:41:56.775741 Set Vref, RX VrefLevel [Byte0]: 24
7548 13:41:56.778598 [Byte1]: 24
7549 13:41:56.782803
7550 13:41:56.783354 Set Vref, RX VrefLevel [Byte0]: 25
7551 13:41:56.786231 [Byte1]: 25
7552 13:41:56.790301
7553 13:41:56.790759 Set Vref, RX VrefLevel [Byte0]: 26
7554 13:41:56.793938 [Byte1]: 26
7555 13:41:56.798491
7556 13:41:56.799044 Set Vref, RX VrefLevel [Byte0]: 27
7557 13:41:56.801165 [Byte1]: 27
7558 13:41:56.805710
7559 13:41:56.806255 Set Vref, RX VrefLevel [Byte0]: 28
7560 13:41:56.809370 [Byte1]: 28
7561 13:41:56.813478
7562 13:41:56.814026 Set Vref, RX VrefLevel [Byte0]: 29
7563 13:41:56.817061 [Byte1]: 29
7564 13:41:56.821124
7565 13:41:56.821743 Set Vref, RX VrefLevel [Byte0]: 30
7566 13:41:56.824260 [Byte1]: 30
7567 13:41:56.828308
7568 13:41:56.828759 Set Vref, RX VrefLevel [Byte0]: 31
7569 13:41:56.831840 [Byte1]: 31
7570 13:41:56.835963
7571 13:41:56.836509 Set Vref, RX VrefLevel [Byte0]: 32
7572 13:41:56.839641 [Byte1]: 32
7573 13:41:56.843578
7574 13:41:56.844185 Set Vref, RX VrefLevel [Byte0]: 33
7575 13:41:56.847301 [Byte1]: 33
7576 13:41:56.851547
7577 13:41:56.851995 Set Vref, RX VrefLevel [Byte0]: 34
7578 13:41:56.854583 [Byte1]: 34
7579 13:41:56.859051
7580 13:41:56.859596 Set Vref, RX VrefLevel [Byte0]: 35
7581 13:41:56.862382 [Byte1]: 35
7582 13:41:56.866344
7583 13:41:56.866802 Set Vref, RX VrefLevel [Byte0]: 36
7584 13:41:56.869918 [Byte1]: 36
7585 13:41:56.874236
7586 13:41:56.874764 Set Vref, RX VrefLevel [Byte0]: 37
7587 13:41:56.877589 [Byte1]: 37
7588 13:41:56.882001
7589 13:41:56.882534 Set Vref, RX VrefLevel [Byte0]: 38
7590 13:41:56.885098 [Byte1]: 38
7591 13:41:56.889529
7592 13:41:56.890127 Set Vref, RX VrefLevel [Byte0]: 39
7593 13:41:56.893069 [Byte1]: 39
7594 13:41:56.897223
7595 13:41:56.897722 Set Vref, RX VrefLevel [Byte0]: 40
7596 13:41:56.900106 [Byte1]: 40
7597 13:41:56.904417
7598 13:41:56.904916 Set Vref, RX VrefLevel [Byte0]: 41
7599 13:41:56.907684 [Byte1]: 41
7600 13:41:56.912269
7601 13:41:56.912796 Set Vref, RX VrefLevel [Byte0]: 42
7602 13:41:56.915693 [Byte1]: 42
7603 13:41:56.920263
7604 13:41:56.920808 Set Vref, RX VrefLevel [Byte0]: 43
7605 13:41:56.923162 [Byte1]: 43
7606 13:41:56.927240
7607 13:41:56.927739 Set Vref, RX VrefLevel [Byte0]: 44
7608 13:41:56.930937 [Byte1]: 44
7609 13:41:56.935157
7610 13:41:56.935697 Set Vref, RX VrefLevel [Byte0]: 45
7611 13:41:56.938105 [Byte1]: 45
7612 13:41:56.942965
7613 13:41:56.943428 Set Vref, RX VrefLevel [Byte0]: 46
7614 13:41:56.945826 [Byte1]: 46
7615 13:41:56.950076
7616 13:41:56.950618 Set Vref, RX VrefLevel [Byte0]: 47
7617 13:41:56.953499 [Byte1]: 47
7618 13:41:56.957709
7619 13:41:56.958407 Set Vref, RX VrefLevel [Byte0]: 48
7620 13:41:56.961204 [Byte1]: 48
7621 13:41:56.965395
7622 13:41:56.965856 Set Vref, RX VrefLevel [Byte0]: 49
7623 13:41:56.968780 [Byte1]: 49
7624 13:41:56.972872
7625 13:41:56.973384 Set Vref, RX VrefLevel [Byte0]: 50
7626 13:41:56.976691 [Byte1]: 50
7627 13:41:56.980480
7628 13:41:56.980940 Set Vref, RX VrefLevel [Byte0]: 51
7629 13:41:56.983871 [Byte1]: 51
7630 13:41:56.988528
7631 13:41:56.989072 Set Vref, RX VrefLevel [Byte0]: 52
7632 13:41:56.991396 [Byte1]: 52
7633 13:41:56.995994
7634 13:41:56.996564 Set Vref, RX VrefLevel [Byte0]: 53
7635 13:41:56.999383 [Byte1]: 53
7636 13:41:57.003555
7637 13:41:57.004025 Set Vref, RX VrefLevel [Byte0]: 54
7638 13:41:57.007039 [Byte1]: 54
7639 13:41:57.011347
7640 13:41:57.011893 Set Vref, RX VrefLevel [Byte0]: 55
7641 13:41:57.014697 [Byte1]: 55
7642 13:41:57.018827
7643 13:41:57.019391 Set Vref, RX VrefLevel [Byte0]: 56
7644 13:41:57.022259 [Byte1]: 56
7645 13:41:57.026760
7646 13:41:57.027336 Set Vref, RX VrefLevel [Byte0]: 57
7647 13:41:57.029921 [Byte1]: 57
7648 13:41:57.034024
7649 13:41:57.034582 Set Vref, RX VrefLevel [Byte0]: 58
7650 13:41:57.037598 [Byte1]: 58
7651 13:41:57.041551
7652 13:41:57.042093 Set Vref, RX VrefLevel [Byte0]: 59
7653 13:41:57.044840 [Byte1]: 59
7654 13:41:57.049495
7655 13:41:57.050038 Set Vref, RX VrefLevel [Byte0]: 60
7656 13:41:57.052366 [Byte1]: 60
7657 13:41:57.057220
7658 13:41:57.057839 Set Vref, RX VrefLevel [Byte0]: 61
7659 13:41:57.060250 [Byte1]: 61
7660 13:41:57.064440
7661 13:41:57.064982 Set Vref, RX VrefLevel [Byte0]: 62
7662 13:41:57.067972 [Byte1]: 62
7663 13:41:57.072096
7664 13:41:57.072630 Set Vref, RX VrefLevel [Byte0]: 63
7665 13:41:57.075386 [Byte1]: 63
7666 13:41:57.079593
7667 13:41:57.080140 Set Vref, RX VrefLevel [Byte0]: 64
7668 13:41:57.083347 [Byte1]: 64
7669 13:41:57.087460
7670 13:41:57.088003 Set Vref, RX VrefLevel [Byte0]: 65
7671 13:41:57.090706 [Byte1]: 65
7672 13:41:57.094887
7673 13:41:57.095607 Set Vref, RX VrefLevel [Byte0]: 66
7674 13:41:57.098183 [Byte1]: 66
7675 13:41:57.102740
7676 13:41:57.103278 Set Vref, RX VrefLevel [Byte0]: 67
7677 13:41:57.105889 [Byte1]: 67
7678 13:41:57.110246
7679 13:41:57.110785 Set Vref, RX VrefLevel [Byte0]: 68
7680 13:41:57.113350 [Byte1]: 68
7681 13:41:57.118156
7682 13:41:57.118696 Set Vref, RX VrefLevel [Byte0]: 69
7683 13:41:57.120872 [Byte1]: 69
7684 13:41:57.125370
7685 13:41:57.125912 Set Vref, RX VrefLevel [Byte0]: 70
7686 13:41:57.128466 [Byte1]: 70
7687 13:41:57.133376
7688 13:41:57.133935 Set Vref, RX VrefLevel [Byte0]: 71
7689 13:41:57.136680 [Byte1]: 71
7690 13:41:57.140510
7691 13:41:57.140960 Set Vref, RX VrefLevel [Byte0]: 72
7692 13:41:57.143626 [Byte1]: 72
7693 13:41:57.148063
7694 13:41:57.148508 Set Vref, RX VrefLevel [Byte0]: 73
7695 13:41:57.151481 [Byte1]: 73
7696 13:41:57.155877
7697 13:41:57.156325 Set Vref, RX VrefLevel [Byte0]: 74
7698 13:41:57.158831 [Byte1]: 74
7699 13:41:57.163825
7700 13:41:57.164366 Final RX Vref Byte 0 = 53 to rank0
7701 13:41:57.166825 Final RX Vref Byte 1 = 59 to rank0
7702 13:41:57.170128 Final RX Vref Byte 0 = 53 to rank1
7703 13:41:57.173232 Final RX Vref Byte 1 = 59 to rank1==
7704 13:41:57.176747 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 13:41:57.183826 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7706 13:41:57.184378 ==
7707 13:41:57.184739 DQS Delay:
7708 13:41:57.185070 DQS0 = 0, DQS1 = 0
7709 13:41:57.186589 DQM Delay:
7710 13:41:57.187051 DQM0 = 126, DQM1 = 121
7711 13:41:57.190292 DQ Delay:
7712 13:41:57.193477 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7713 13:41:57.196766 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7714 13:41:57.200565 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7715 13:41:57.203530 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7716 13:41:57.204089
7717 13:41:57.204456
7718 13:41:57.204836
7719 13:41:57.206985 [DramC_TX_OE_Calibration] TA2
7720 13:41:57.210272 Original DQ_B0 (3 6) =30, OEN = 27
7721 13:41:57.213438 Original DQ_B1 (3 6) =30, OEN = 27
7722 13:41:57.216763 24, 0x0, End_B0=24 End_B1=24
7723 13:41:57.217357 25, 0x0, End_B0=25 End_B1=25
7724 13:41:57.219968 26, 0x0, End_B0=26 End_B1=26
7725 13:41:57.223605 27, 0x0, End_B0=27 End_B1=27
7726 13:41:57.226415 28, 0x0, End_B0=28 End_B1=28
7727 13:41:57.226879 29, 0x0, End_B0=29 End_B1=29
7728 13:41:57.229892 30, 0x0, End_B0=30 End_B1=30
7729 13:41:57.233418 31, 0x4141, End_B0=30 End_B1=30
7730 13:41:57.236478 Byte0 end_step=30 best_step=27
7731 13:41:57.240111 Byte1 end_step=30 best_step=27
7732 13:41:57.242832 Byte0 TX OE(2T, 0.5T) = (3, 3)
7733 13:41:57.243283 Byte1 TX OE(2T, 0.5T) = (3, 3)
7734 13:41:57.246984
7735 13:41:57.247539
7736 13:41:57.253272 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7737 13:41:57.256354 CH0 RK0: MR19=303, MR18=1A1A
7738 13:41:57.263343 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7739 13:41:57.263911
7740 13:41:57.266587 ----->DramcWriteLeveling(PI) begin...
7741 13:41:57.267052 ==
7742 13:41:57.269536 Dram Type= 6, Freq= 0, CH_0, rank 1
7743 13:41:57.273000 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7744 13:41:57.273539 ==
7745 13:41:57.275884 Write leveling (Byte 0): 28 => 28
7746 13:41:57.279633 Write leveling (Byte 1): 27 => 27
7747 13:41:57.282953 DramcWriteLeveling(PI) end<-----
7748 13:41:57.283647
7749 13:41:57.284165 ==
7750 13:41:57.285885 Dram Type= 6, Freq= 0, CH_0, rank 1
7751 13:41:57.289405 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7752 13:41:57.289870 ==
7753 13:41:57.292483 [Gating] SW mode calibration
7754 13:41:57.300229 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7755 13:41:57.306390 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7756 13:41:57.309248 0 12 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7757 13:41:57.312913 0 12 4 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
7758 13:41:57.319344 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7759 13:41:57.322854 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7760 13:41:57.325889 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7761 13:41:57.332628 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7762 13:41:57.335848 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7763 13:41:57.339128 0 12 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7764 13:41:57.345908 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7765 13:41:57.349701 0 13 4 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7766 13:41:57.352757 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7767 13:41:57.359319 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7768 13:41:57.362727 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7769 13:41:57.366134 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7770 13:41:57.372791 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7771 13:41:57.375546 0 13 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7772 13:41:57.379392 0 14 0 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7773 13:41:57.385665 0 14 4 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7774 13:41:57.389133 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7775 13:41:57.392274 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7776 13:41:57.398894 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7777 13:41:57.402296 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7778 13:41:57.405266 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7779 13:41:57.412211 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7780 13:41:57.415469 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7781 13:41:57.418896 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7782 13:41:57.425497 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7783 13:41:57.428905 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7784 13:41:57.431964 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7785 13:41:57.438228 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7786 13:41:57.441807 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7787 13:41:57.445450 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7788 13:41:57.452027 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7789 13:41:57.455377 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7790 13:41:57.458752 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7791 13:41:57.465205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7792 13:41:57.468434 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7793 13:41:57.472026 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7794 13:41:57.478008 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7795 13:41:57.481828 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7796 13:41:57.484828 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7797 13:41:57.488322 Total UI for P1: 0, mck2ui 16
7798 13:41:57.491782 best dqsien dly found for B0: ( 1, 0, 26)
7799 13:41:57.498267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7800 13:41:57.502008 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 13:41:57.504666 Total UI for P1: 0, mck2ui 16
7802 13:41:57.508474 best dqsien dly found for B1: ( 1, 1, 2)
7803 13:41:57.511388 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
7804 13:41:57.514800 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7805 13:41:57.515374
7806 13:41:57.517869 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
7807 13:41:57.521282 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7808 13:41:57.524980 [Gating] SW calibration Done
7809 13:41:57.525607 ==
7810 13:41:57.528156 Dram Type= 6, Freq= 0, CH_0, rank 1
7811 13:41:57.531045 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7812 13:41:57.531626 ==
7813 13:41:57.534688 RX Vref Scan: 0
7814 13:41:57.535157
7815 13:41:57.537813 RX Vref 0 -> 0, step: 1
7816 13:41:57.538398
7817 13:41:57.538889 RX Delay 0 -> 252, step: 8
7818 13:41:57.544304 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7819 13:41:57.547432 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7820 13:41:57.551164 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7821 13:41:57.554425 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7822 13:41:57.557661 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7823 13:41:57.564453 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7824 13:41:57.567116 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7825 13:41:57.570286 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7826 13:41:57.574192 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7827 13:41:57.577345 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7828 13:41:57.584282 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7829 13:41:57.587306 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7830 13:41:57.590415 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7831 13:41:57.594078 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7832 13:41:57.600940 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7833 13:41:57.604012 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7834 13:41:57.604582 ==
7835 13:41:57.606818 Dram Type= 6, Freq= 0, CH_0, rank 1
7836 13:41:57.610637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7837 13:41:57.611217 ==
7838 13:41:57.614059 DQS Delay:
7839 13:41:57.614634 DQS0 = 0, DQS1 = 0
7840 13:41:57.615126 DQM Delay:
7841 13:41:57.617088 DQM0 = 131, DQM1 = 124
7842 13:41:57.617717 DQ Delay:
7843 13:41:57.620714 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7844 13:41:57.623631 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7845 13:41:57.626893 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7846 13:41:57.633456 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7847 13:41:57.633932
7848 13:41:57.634412
7849 13:41:57.634860 ==
7850 13:41:57.637523 Dram Type= 6, Freq= 0, CH_0, rank 1
7851 13:41:57.640458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7852 13:41:57.641059 ==
7853 13:41:57.641614
7854 13:41:57.642096
7855 13:41:57.643709 TX Vref Scan disable
7856 13:41:57.644183 == TX Byte 0 ==
7857 13:41:57.650022 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7858 13:41:57.653594 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7859 13:41:57.654072 == TX Byte 1 ==
7860 13:41:57.660190 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7861 13:41:57.663259 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7862 13:41:57.663736 ==
7863 13:41:57.666741 Dram Type= 6, Freq= 0, CH_0, rank 1
7864 13:41:57.669732 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7865 13:41:57.670210 ==
7866 13:41:57.684916
7867 13:41:57.688184 TX Vref early break, caculate TX vref
7868 13:41:57.691027 TX Vref=16, minBit 9, minWin=22, winSum=379
7869 13:41:57.694441 TX Vref=18, minBit 11, minWin=22, winSum=384
7870 13:41:57.697740 TX Vref=20, minBit 8, minWin=23, winSum=394
7871 13:41:57.700889 TX Vref=22, minBit 8, minWin=23, winSum=399
7872 13:41:57.704428 TX Vref=24, minBit 9, minWin=24, winSum=407
7873 13:41:57.710841 TX Vref=26, minBit 1, minWin=24, winSum=411
7874 13:41:57.714326 TX Vref=28, minBit 8, minWin=24, winSum=412
7875 13:41:57.717429 TX Vref=30, minBit 4, minWin=25, winSum=418
7876 13:41:57.720962 TX Vref=32, minBit 7, minWin=24, winSum=408
7877 13:41:57.724641 TX Vref=34, minBit 8, minWin=22, winSum=398
7878 13:41:57.727434 TX Vref=36, minBit 8, minWin=23, winSum=391
7879 13:41:57.734551 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 30
7880 13:41:57.734753
7881 13:41:57.737591 Final TX Range 0 Vref 30
7882 13:41:57.737795
7883 13:41:57.737915 ==
7884 13:41:57.741153 Dram Type= 6, Freq= 0, CH_0, rank 1
7885 13:41:57.744200 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7886 13:41:57.744357 ==
7887 13:41:57.744482
7888 13:41:57.747705
7889 13:41:57.747886 TX Vref Scan disable
7890 13:41:57.754260 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7891 13:41:57.754610 == TX Byte 0 ==
7892 13:41:57.757090 u2DelayCellOfst[0]=14 cells (4 PI)
7893 13:41:57.760710 u2DelayCellOfst[1]=21 cells (6 PI)
7894 13:41:57.764059 u2DelayCellOfst[2]=14 cells (4 PI)
7895 13:41:57.767940 u2DelayCellOfst[3]=14 cells (4 PI)
7896 13:41:57.770754 u2DelayCellOfst[4]=7 cells (2 PI)
7897 13:41:57.774292 u2DelayCellOfst[5]=0 cells (0 PI)
7898 13:41:57.777161 u2DelayCellOfst[6]=21 cells (6 PI)
7899 13:41:57.780634 u2DelayCellOfst[7]=18 cells (5 PI)
7900 13:41:57.783878 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7901 13:41:57.787432 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7902 13:41:57.791207 == TX Byte 1 ==
7903 13:41:57.793783 u2DelayCellOfst[8]=0 cells (0 PI)
7904 13:41:57.797031 u2DelayCellOfst[9]=0 cells (0 PI)
7905 13:41:57.800396 u2DelayCellOfst[10]=10 cells (3 PI)
7906 13:41:57.803993 u2DelayCellOfst[11]=3 cells (1 PI)
7907 13:41:57.804411 u2DelayCellOfst[12]=14 cells (4 PI)
7908 13:41:57.807365 u2DelayCellOfst[13]=14 cells (4 PI)
7909 13:41:57.810150 u2DelayCellOfst[14]=18 cells (5 PI)
7910 13:41:57.813795 u2DelayCellOfst[15]=14 cells (4 PI)
7911 13:41:57.820397 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7912 13:41:57.823630 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7913 13:41:57.824090 DramC Write-DBI on
7914 13:41:57.826789 ==
7915 13:41:57.830449 Dram Type= 6, Freq= 0, CH_0, rank 1
7916 13:41:57.833413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7917 13:41:57.833877 ==
7918 13:41:57.834254
7919 13:41:57.834752
7920 13:41:57.837191 TX Vref Scan disable
7921 13:41:57.837813 == TX Byte 0 ==
7922 13:41:57.843653 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7923 13:41:57.844215 == TX Byte 1 ==
7924 13:41:57.846540 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7925 13:41:57.850113 DramC Write-DBI off
7926 13:41:57.850570
7927 13:41:57.850933 [DATLAT]
7928 13:41:57.853689 Freq=1600, CH0 RK1
7929 13:41:57.854144
7930 13:41:57.854502 DATLAT Default: 0xe
7931 13:41:57.856561 0, 0xFFFF, sum = 0
7932 13:41:57.857019 1, 0xFFFF, sum = 0
7933 13:41:57.860003 2, 0xFFFF, sum = 0
7934 13:41:57.860462 3, 0xFFFF, sum = 0
7935 13:41:57.863276 4, 0xFFFF, sum = 0
7936 13:41:57.863835 5, 0xFFFF, sum = 0
7937 13:41:57.866910 6, 0xFFFF, sum = 0
7938 13:41:57.867468 7, 0xFFFF, sum = 0
7939 13:41:57.869727 8, 0xFFFF, sum = 0
7940 13:41:57.873631 9, 0xFFFF, sum = 0
7941 13:41:57.874185 10, 0xFFFF, sum = 0
7942 13:41:57.876359 11, 0xFFFF, sum = 0
7943 13:41:57.876823 12, 0x8FFF, sum = 0
7944 13:41:57.880159 13, 0x0, sum = 1
7945 13:41:57.880723 14, 0x0, sum = 2
7946 13:41:57.883783 15, 0x0, sum = 3
7947 13:41:57.884344 16, 0x0, sum = 4
7948 13:41:57.884713 best_step = 14
7949 13:41:57.886383
7950 13:41:57.886830 ==
7951 13:41:57.889808 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 13:41:57.893139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7953 13:41:57.893748 ==
7954 13:41:57.894202 RX Vref Scan: 0
7955 13:41:57.894722
7956 13:41:57.896488 RX Vref 0 -> 0, step: 1
7957 13:41:57.896940
7958 13:41:57.900156 RX Delay 11 -> 252, step: 4
7959 13:41:57.903151 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7960 13:41:57.909756 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7961 13:41:57.913192 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7962 13:41:57.916479 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7963 13:41:57.919558 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7964 13:41:57.923007 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7965 13:41:57.929979 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7966 13:41:57.932609 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7967 13:41:57.936178 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
7968 13:41:57.939488 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7969 13:41:57.942906 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
7970 13:41:57.949455 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7971 13:41:57.952779 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7972 13:41:57.956285 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7973 13:41:57.959059 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7974 13:41:57.962479 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
7975 13:41:57.965822 ==
7976 13:41:57.969607 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 13:41:57.972591 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7978 13:41:57.973143 ==
7979 13:41:57.973556 DQS Delay:
7980 13:41:57.975634 DQS0 = 0, DQS1 = 0
7981 13:41:57.976183 DQM Delay:
7982 13:41:57.979006 DQM0 = 128, DQM1 = 120
7983 13:41:57.979680 DQ Delay:
7984 13:41:57.982493 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7985 13:41:57.985550 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7986 13:41:57.988602 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
7987 13:41:57.992518 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
7988 13:41:57.993081
7989 13:41:57.993507
7990 13:41:57.993847
7991 13:41:57.995116 [DramC_TX_OE_Calibration] TA2
7992 13:41:57.998503 Original DQ_B0 (3 6) =30, OEN = 27
7993 13:41:58.001965 Original DQ_B1 (3 6) =30, OEN = 27
7994 13:41:58.005202 24, 0x0, End_B0=24 End_B1=24
7995 13:41:58.008452 25, 0x0, End_B0=25 End_B1=25
7996 13:41:58.011936 26, 0x0, End_B0=26 End_B1=26
7997 13:41:58.012484 27, 0x0, End_B0=27 End_B1=27
7998 13:41:58.015392 28, 0x0, End_B0=28 End_B1=28
7999 13:41:58.018906 29, 0x0, End_B0=29 End_B1=29
8000 13:41:58.021972 30, 0x0, End_B0=30 End_B1=30
8001 13:41:58.025376 31, 0x4141, End_B0=30 End_B1=30
8002 13:41:58.025921 Byte0 end_step=30 best_step=27
8003 13:41:58.028836 Byte1 end_step=30 best_step=27
8004 13:41:58.032063 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 13:41:58.035011 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 13:41:58.035471
8007 13:41:58.035833
8008 13:41:58.041881 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8009 13:41:58.045473 CH0 RK1: MR19=303, MR18=2121
8010 13:41:58.051674 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8011 13:41:58.055483 [RxdqsGatingPostProcess] freq 1600
8012 13:41:58.061247 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8013 13:41:58.065145 Pre-setting of DQS Precalculation
8014 13:41:58.068526 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8015 13:41:58.069247 ==
8016 13:41:58.071792 Dram Type= 6, Freq= 0, CH_1, rank 0
8017 13:41:58.074867 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8018 13:41:58.078466 ==
8019 13:41:58.081533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8020 13:41:58.085134 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8021 13:41:58.091664 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8022 13:41:58.094532 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8023 13:41:58.104104 [CA 0] Center 41 (11~71) winsize 61
8024 13:41:58.107452 [CA 1] Center 41 (10~72) winsize 63
8025 13:41:58.110747 [CA 2] Center 37 (8~67) winsize 60
8026 13:41:58.114138 [CA 3] Center 36 (7~66) winsize 60
8027 13:41:58.117872 [CA 4] Center 34 (5~64) winsize 60
8028 13:41:58.120976 [CA 5] Center 34 (5~64) winsize 60
8029 13:41:58.121565
8030 13:41:58.124074 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8031 13:41:58.124621
8032 13:41:58.127367 [CATrainingPosCal] consider 1 rank data
8033 13:41:58.130923 u2DelayCellTimex100 = 271/100 ps
8034 13:41:58.137639 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8035 13:41:58.140309 CA1 delay=41 (10~72),Diff = 7 PI (25 cell)
8036 13:41:58.143575 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8037 13:41:58.147676 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8038 13:41:58.150606 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8039 13:41:58.153949 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8040 13:41:58.154404
8041 13:41:58.156724 CA PerBit enable=1, Macro0, CA PI delay=34
8042 13:41:58.157179
8043 13:41:58.160170 [CBTSetCACLKResult] CA Dly = 34
8044 13:41:58.163560 CS Dly: 8 (0~39)
8045 13:41:58.167297 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8046 13:41:58.170110 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8047 13:41:58.170568 ==
8048 13:41:58.173788 Dram Type= 6, Freq= 0, CH_1, rank 1
8049 13:41:58.180458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 13:41:58.181023 ==
8051 13:41:58.183684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8052 13:41:58.186622 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8053 13:41:58.193272 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8054 13:41:58.199835 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8055 13:41:58.206993 [CA 0] Center 41 (11~71) winsize 61
8056 13:41:58.210012 [CA 1] Center 40 (10~71) winsize 62
8057 13:41:58.213693 [CA 2] Center 36 (7~66) winsize 60
8058 13:41:58.216995 [CA 3] Center 36 (7~65) winsize 59
8059 13:41:58.219889 [CA 4] Center 35 (6~64) winsize 59
8060 13:41:58.223213 [CA 5] Center 34 (4~64) winsize 61
8061 13:41:58.223761
8062 13:41:58.226223 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8063 13:41:58.226748
8064 13:41:58.230054 [CATrainingPosCal] consider 2 rank data
8065 13:41:58.233047 u2DelayCellTimex100 = 271/100 ps
8066 13:41:58.240156 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8067 13:41:58.242912 CA1 delay=40 (10~71),Diff = 6 PI (21 cell)
8068 13:41:58.246548 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8069 13:41:58.249646 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8070 13:41:58.252851 CA4 delay=35 (6~64),Diff = 1 PI (3 cell)
8071 13:41:58.256475 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8072 13:41:58.257023
8073 13:41:58.260129 CA PerBit enable=1, Macro0, CA PI delay=34
8074 13:41:58.260678
8075 13:41:58.263247 [CBTSetCACLKResult] CA Dly = 34
8076 13:41:58.266100 CS Dly: 9 (0~41)
8077 13:41:58.269834 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8078 13:41:58.272929 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8079 13:41:58.273520
8080 13:41:58.276184 ----->DramcWriteLeveling(PI) begin...
8081 13:41:58.276641 ==
8082 13:41:58.279506 Dram Type= 6, Freq= 0, CH_1, rank 0
8083 13:41:58.285776 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8084 13:41:58.286229 ==
8085 13:41:58.289648 Write leveling (Byte 0): 22 => 22
8086 13:41:58.292619 Write leveling (Byte 1): 21 => 21
8087 13:41:58.293167 DramcWriteLeveling(PI) end<-----
8088 13:41:58.293569
8089 13:41:58.296156 ==
8090 13:41:58.299265 Dram Type= 6, Freq= 0, CH_1, rank 0
8091 13:41:58.302800 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8092 13:41:58.303352 ==
8093 13:41:58.305765 [Gating] SW mode calibration
8094 13:41:58.312468 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8095 13:41:58.315706 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8096 13:41:58.322575 0 12 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8097 13:41:58.325230 0 12 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8098 13:41:58.328829 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 13:41:58.335473 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 13:41:58.338985 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 13:41:58.342204 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 13:41:58.348334 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8103 13:41:58.351985 0 12 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8104 13:41:58.355175 0 13 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8105 13:41:58.361745 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8106 13:41:58.365275 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 13:41:58.368894 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 13:41:58.375432 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 13:41:58.378322 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 13:41:58.381699 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 13:41:58.388090 0 13 28 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
8112 13:41:58.391656 0 14 0 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
8113 13:41:58.394879 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8114 13:41:58.401937 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 13:41:58.405454 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 13:41:58.408316 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 13:41:58.414933 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 13:41:58.418317 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 13:41:58.421887 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8120 13:41:58.428600 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8121 13:41:58.431260 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8122 13:41:58.434591 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 13:41:58.441624 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 13:41:58.444881 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 13:41:58.448080 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 13:41:58.454963 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 13:41:58.457661 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 13:41:58.461534 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 13:41:58.468526 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 13:41:58.471468 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 13:41:58.475123 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 13:41:58.480992 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 13:41:58.484832 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 13:41:58.487879 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8135 13:41:58.491218 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8136 13:41:58.497773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8137 13:41:58.500899 Total UI for P1: 0, mck2ui 16
8138 13:41:58.504518 best dqsien dly found for B0: ( 1, 0, 26)
8139 13:41:58.507454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8140 13:41:58.511151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 13:41:58.514392 Total UI for P1: 0, mck2ui 16
8142 13:41:58.517320 best dqsien dly found for B1: ( 1, 1, 2)
8143 13:41:58.521194 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8144 13:41:58.527679 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8145 13:41:58.528215
8146 13:41:58.530840 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8147 13:41:58.534248 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8148 13:41:58.537445 [Gating] SW calibration Done
8149 13:41:58.537993 ==
8150 13:41:58.540860 Dram Type= 6, Freq= 0, CH_1, rank 0
8151 13:41:58.544007 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8152 13:41:58.544467 ==
8153 13:41:58.544834 RX Vref Scan: 0
8154 13:41:58.547246
8155 13:41:58.547702 RX Vref 0 -> 0, step: 1
8156 13:41:58.548068
8157 13:41:58.550750 RX Delay 0 -> 252, step: 8
8158 13:41:58.553677 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8159 13:41:58.556853 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8160 13:41:58.564025 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8161 13:41:58.567188 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8162 13:41:58.570155 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8163 13:41:58.573667 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8164 13:41:58.576700 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8165 13:41:58.583977 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8166 13:41:58.586860 iDelay=200, Bit 8, Center 103 (48 ~ 159) 112
8167 13:41:58.590455 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8168 13:41:58.593567 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8169 13:41:58.597061 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8170 13:41:58.603303 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8171 13:41:58.606959 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8172 13:41:58.609989 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8173 13:41:58.613233 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8174 13:41:58.613745 ==
8175 13:41:58.616396 Dram Type= 6, Freq= 0, CH_1, rank 0
8176 13:41:58.623065 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8177 13:41:58.623558 ==
8178 13:41:58.623927 DQS Delay:
8179 13:41:58.626799 DQS0 = 0, DQS1 = 0
8180 13:41:58.627270 DQM Delay:
8181 13:41:58.629705 DQM0 = 129, DQM1 = 125
8182 13:41:58.630164 DQ Delay:
8183 13:41:58.633376 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8184 13:41:58.636479 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8185 13:41:58.639994 DQ8 =103, DQ9 =119, DQ10 =127, DQ11 =115
8186 13:41:58.643004 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8187 13:41:58.643455
8188 13:41:58.643807
8189 13:41:58.644146 ==
8190 13:41:58.646625 Dram Type= 6, Freq= 0, CH_1, rank 0
8191 13:41:58.652980 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8192 13:41:58.653563 ==
8193 13:41:58.653902
8194 13:41:58.654207
8195 13:41:58.654502 TX Vref Scan disable
8196 13:41:58.656261 == TX Byte 0 ==
8197 13:41:58.659698 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8198 13:41:58.666181 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8199 13:41:58.666689 == TX Byte 1 ==
8200 13:41:58.670000 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8201 13:41:58.676416 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8202 13:41:58.676936 ==
8203 13:41:58.679636 Dram Type= 6, Freq= 0, CH_1, rank 0
8204 13:41:58.682383 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8205 13:41:58.682802 ==
8206 13:41:58.695099
8207 13:41:58.697846 TX Vref early break, caculate TX vref
8208 13:41:58.701756 TX Vref=16, minBit 3, minWin=21, winSum=367
8209 13:41:58.704772 TX Vref=18, minBit 4, minWin=22, winSum=378
8210 13:41:58.707911 TX Vref=20, minBit 3, minWin=22, winSum=387
8211 13:41:58.711092 TX Vref=22, minBit 3, minWin=23, winSum=395
8212 13:41:58.714532 TX Vref=24, minBit 0, minWin=24, winSum=403
8213 13:41:58.721596 TX Vref=26, minBit 3, minWin=24, winSum=411
8214 13:41:58.725340 TX Vref=28, minBit 0, minWin=24, winSum=413
8215 13:41:58.728122 TX Vref=30, minBit 3, minWin=24, winSum=405
8216 13:41:58.731191 TX Vref=32, minBit 1, minWin=23, winSum=397
8217 13:41:58.734960 TX Vref=34, minBit 1, minWin=23, winSum=389
8218 13:41:58.741462 [TxChooseVref] Worse bit 0, Min win 24, Win sum 413, Final Vref 28
8219 13:41:58.742028
8220 13:41:58.744436 Final TX Range 0 Vref 28
8221 13:41:58.744997
8222 13:41:58.745399 ==
8223 13:41:58.748072 Dram Type= 6, Freq= 0, CH_1, rank 0
8224 13:41:58.751017 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8225 13:41:58.751581 ==
8226 13:41:58.751947
8227 13:41:58.752282
8228 13:41:58.754413 TX Vref Scan disable
8229 13:41:58.760972 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8230 13:41:58.761589 == TX Byte 0 ==
8231 13:41:58.764421 u2DelayCellOfst[0]=14 cells (4 PI)
8232 13:41:58.767492 u2DelayCellOfst[1]=10 cells (3 PI)
8233 13:41:58.771117 u2DelayCellOfst[2]=0 cells (0 PI)
8234 13:41:58.774212 u2DelayCellOfst[3]=7 cells (2 PI)
8235 13:41:58.777187 u2DelayCellOfst[4]=7 cells (2 PI)
8236 13:41:58.780567 u2DelayCellOfst[5]=14 cells (4 PI)
8237 13:41:58.784207 u2DelayCellOfst[6]=14 cells (4 PI)
8238 13:41:58.787718 u2DelayCellOfst[7]=3 cells (1 PI)
8239 13:41:58.790466 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8240 13:41:58.793960 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8241 13:41:58.797235 == TX Byte 1 ==
8242 13:41:58.797825 u2DelayCellOfst[8]=0 cells (0 PI)
8243 13:41:58.800609 u2DelayCellOfst[9]=7 cells (2 PI)
8244 13:41:58.803867 u2DelayCellOfst[10]=10 cells (3 PI)
8245 13:41:58.807218 u2DelayCellOfst[11]=3 cells (1 PI)
8246 13:41:58.810866 u2DelayCellOfst[12]=18 cells (5 PI)
8247 13:41:58.813835 u2DelayCellOfst[13]=18 cells (5 PI)
8248 13:41:58.817362 u2DelayCellOfst[14]=21 cells (6 PI)
8249 13:41:58.820540 u2DelayCellOfst[15]=21 cells (6 PI)
8250 13:41:58.824034 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8251 13:41:58.830117 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8252 13:41:58.830579 DramC Write-DBI on
8253 13:41:58.830942 ==
8254 13:41:58.833620 Dram Type= 6, Freq= 0, CH_1, rank 0
8255 13:41:58.839752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8256 13:41:58.840314 ==
8257 13:41:58.840685
8258 13:41:58.841026
8259 13:41:58.841389 TX Vref Scan disable
8260 13:41:58.844033 == TX Byte 0 ==
8261 13:41:58.847100 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8262 13:41:58.850364 == TX Byte 1 ==
8263 13:41:58.854405 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8264 13:41:58.854885 DramC Write-DBI off
8265 13:41:58.857168
8266 13:41:58.857688 [DATLAT]
8267 13:41:58.858049 Freq=1600, CH1 RK0
8268 13:41:58.858389
8269 13:41:58.860750 DATLAT Default: 0xf
8270 13:41:58.861200 0, 0xFFFF, sum = 0
8271 13:41:58.863698 1, 0xFFFF, sum = 0
8272 13:41:58.864158 2, 0xFFFF, sum = 0
8273 13:41:58.867182 3, 0xFFFF, sum = 0
8274 13:41:58.870560 4, 0xFFFF, sum = 0
8275 13:41:58.871022 5, 0xFFFF, sum = 0
8276 13:41:58.873775 6, 0xFFFF, sum = 0
8277 13:41:58.874237 7, 0xFFFF, sum = 0
8278 13:41:58.877162 8, 0xFFFF, sum = 0
8279 13:41:58.877703 9, 0xFFFF, sum = 0
8280 13:41:58.880164 10, 0xFFFF, sum = 0
8281 13:41:58.880626 11, 0xFFFF, sum = 0
8282 13:41:58.883391 12, 0x8FFF, sum = 0
8283 13:41:58.883936 13, 0x0, sum = 1
8284 13:41:58.886700 14, 0x0, sum = 2
8285 13:41:58.887119 15, 0x0, sum = 3
8286 13:41:58.890421 16, 0x0, sum = 4
8287 13:41:58.890976 best_step = 14
8288 13:41:58.891445
8289 13:41:58.891890 ==
8290 13:41:58.893432 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 13:41:58.896878 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8292 13:41:58.899720 ==
8293 13:41:58.900135 RX Vref Scan: 1
8294 13:41:58.900458
8295 13:41:58.903728 Set Vref Range= 24 -> 127
8296 13:41:58.904250
8297 13:41:58.906508 RX Vref 24 -> 127, step: 1
8298 13:41:58.906924
8299 13:41:58.907252 RX Delay 3 -> 252, step: 4
8300 13:41:58.907554
8301 13:41:58.910028 Set Vref, RX VrefLevel [Byte0]: 24
8302 13:41:58.913552 [Byte1]: 24
8303 13:41:58.917467
8304 13:41:58.917974 Set Vref, RX VrefLevel [Byte0]: 25
8305 13:41:58.920706 [Byte1]: 25
8306 13:41:58.924856
8307 13:41:58.925402 Set Vref, RX VrefLevel [Byte0]: 26
8308 13:41:58.928239 [Byte1]: 26
8309 13:41:58.932133
8310 13:41:58.932787 Set Vref, RX VrefLevel [Byte0]: 27
8311 13:41:58.935831 [Byte1]: 27
8312 13:41:58.940221
8313 13:41:58.940725 Set Vref, RX VrefLevel [Byte0]: 28
8314 13:41:58.943610 [Byte1]: 28
8315 13:41:58.947671
8316 13:41:58.948085 Set Vref, RX VrefLevel [Byte0]: 29
8317 13:41:58.950897 [Byte1]: 29
8318 13:41:58.955540
8319 13:41:58.956167 Set Vref, RX VrefLevel [Byte0]: 30
8320 13:41:58.959019 [Byte1]: 30
8321 13:41:58.963029
8322 13:41:58.963443 Set Vref, RX VrefLevel [Byte0]: 31
8323 13:41:58.966074 [Byte1]: 31
8324 13:41:58.970848
8325 13:41:58.971259 Set Vref, RX VrefLevel [Byte0]: 32
8326 13:41:58.974313 [Byte1]: 32
8327 13:41:58.978377
8328 13:41:58.978792 Set Vref, RX VrefLevel [Byte0]: 33
8329 13:41:58.981603 [Byte1]: 33
8330 13:41:58.985801
8331 13:41:58.986208 Set Vref, RX VrefLevel [Byte0]: 34
8332 13:41:58.989358 [Byte1]: 34
8333 13:41:58.993487
8334 13:41:58.993907 Set Vref, RX VrefLevel [Byte0]: 35
8335 13:41:58.996788 [Byte1]: 35
8336 13:41:59.001574
8337 13:41:59.001979 Set Vref, RX VrefLevel [Byte0]: 36
8338 13:41:59.004639 [Byte1]: 36
8339 13:41:59.009011
8340 13:41:59.009464 Set Vref, RX VrefLevel [Byte0]: 37
8341 13:41:59.012199 [Byte1]: 37
8342 13:41:59.016927
8343 13:41:59.017460 Set Vref, RX VrefLevel [Byte0]: 38
8344 13:41:59.019722 [Byte1]: 38
8345 13:41:59.024824
8346 13:41:59.025341 Set Vref, RX VrefLevel [Byte0]: 39
8347 13:41:59.027793 [Byte1]: 39
8348 13:41:59.032343
8349 13:41:59.032901 Set Vref, RX VrefLevel [Byte0]: 40
8350 13:41:59.035023 [Byte1]: 40
8351 13:41:59.040080
8352 13:41:59.040624 Set Vref, RX VrefLevel [Byte0]: 41
8353 13:41:59.043346 [Byte1]: 41
8354 13:41:59.047167
8355 13:41:59.047621 Set Vref, RX VrefLevel [Byte0]: 42
8356 13:41:59.050932 [Byte1]: 42
8357 13:41:59.054917
8358 13:41:59.055751 Set Vref, RX VrefLevel [Byte0]: 43
8359 13:41:59.058191 [Byte1]: 43
8360 13:41:59.062454
8361 13:41:59.062902 Set Vref, RX VrefLevel [Byte0]: 44
8362 13:41:59.066130 [Byte1]: 44
8363 13:41:59.069993
8364 13:41:59.070440 Set Vref, RX VrefLevel [Byte0]: 45
8365 13:41:59.073353 [Byte1]: 45
8366 13:41:59.077779
8367 13:41:59.078227 Set Vref, RX VrefLevel [Byte0]: 46
8368 13:41:59.081627 [Byte1]: 46
8369 13:41:59.085641
8370 13:41:59.086199 Set Vref, RX VrefLevel [Byte0]: 47
8371 13:41:59.088857 [Byte1]: 47
8372 13:41:59.093117
8373 13:41:59.093715 Set Vref, RX VrefLevel [Byte0]: 48
8374 13:41:59.096434 [Byte1]: 48
8375 13:41:59.101154
8376 13:41:59.101733 Set Vref, RX VrefLevel [Byte0]: 49
8377 13:41:59.103977 [Byte1]: 49
8378 13:41:59.108832
8379 13:41:59.109413 Set Vref, RX VrefLevel [Byte0]: 50
8380 13:41:59.111774 [Byte1]: 50
8381 13:41:59.116630
8382 13:41:59.117178 Set Vref, RX VrefLevel [Byte0]: 51
8383 13:41:59.119636 [Byte1]: 51
8384 13:41:59.123999
8385 13:41:59.124540 Set Vref, RX VrefLevel [Byte0]: 52
8386 13:41:59.127548 [Byte1]: 52
8387 13:41:59.131770
8388 13:41:59.132319 Set Vref, RX VrefLevel [Byte0]: 53
8389 13:41:59.134549 [Byte1]: 53
8390 13:41:59.139254
8391 13:41:59.139705 Set Vref, RX VrefLevel [Byte0]: 54
8392 13:41:59.142188 [Byte1]: 54
8393 13:41:59.146840
8394 13:41:59.147335 Set Vref, RX VrefLevel [Byte0]: 55
8395 13:41:59.150375 [Byte1]: 55
8396 13:41:59.154160
8397 13:41:59.154624 Set Vref, RX VrefLevel [Byte0]: 56
8398 13:41:59.157867 [Byte1]: 56
8399 13:41:59.162250
8400 13:41:59.162793 Set Vref, RX VrefLevel [Byte0]: 57
8401 13:41:59.165773 [Byte1]: 57
8402 13:41:59.169943
8403 13:41:59.170488 Set Vref, RX VrefLevel [Byte0]: 58
8404 13:41:59.173118 [Byte1]: 58
8405 13:41:59.177262
8406 13:41:59.177871 Set Vref, RX VrefLevel [Byte0]: 59
8407 13:41:59.180800 [Byte1]: 59
8408 13:41:59.185332
8409 13:41:59.185878 Set Vref, RX VrefLevel [Byte0]: 60
8410 13:41:59.188272 [Byte1]: 60
8411 13:41:59.192770
8412 13:41:59.193360 Set Vref, RX VrefLevel [Byte0]: 61
8413 13:41:59.195905 [Byte1]: 61
8414 13:41:59.199959
8415 13:41:59.200409 Set Vref, RX VrefLevel [Byte0]: 62
8416 13:41:59.203530 [Byte1]: 62
8417 13:41:59.208437
8418 13:41:59.209063 Set Vref, RX VrefLevel [Byte0]: 63
8419 13:41:59.211301 [Byte1]: 63
8420 13:41:59.216039
8421 13:41:59.216617 Set Vref, RX VrefLevel [Byte0]: 64
8422 13:41:59.218737 [Byte1]: 64
8423 13:41:59.223375
8424 13:41:59.223922 Set Vref, RX VrefLevel [Byte0]: 65
8425 13:41:59.226508 [Byte1]: 65
8426 13:41:59.231327
8427 13:41:59.231904 Set Vref, RX VrefLevel [Byte0]: 66
8428 13:41:59.234087 [Byte1]: 66
8429 13:41:59.238735
8430 13:41:59.239185 Set Vref, RX VrefLevel [Byte0]: 67
8431 13:41:59.242133 [Byte1]: 67
8432 13:41:59.246476
8433 13:41:59.247023 Set Vref, RX VrefLevel [Byte0]: 68
8434 13:41:59.249460 [Byte1]: 68
8435 13:41:59.254050
8436 13:41:59.254598 Set Vref, RX VrefLevel [Byte0]: 69
8437 13:41:59.257352 [Byte1]: 69
8438 13:41:59.261742
8439 13:41:59.262282 Set Vref, RX VrefLevel [Byte0]: 70
8440 13:41:59.265010 [Byte1]: 70
8441 13:41:59.269249
8442 13:41:59.269745 Set Vref, RX VrefLevel [Byte0]: 71
8443 13:41:59.272461 [Byte1]: 71
8444 13:41:59.276959
8445 13:41:59.277447 Set Vref, RX VrefLevel [Byte0]: 72
8446 13:41:59.279864 [Byte1]: 72
8447 13:41:59.284412
8448 13:41:59.284865 Set Vref, RX VrefLevel [Byte0]: 73
8449 13:41:59.287927 [Byte1]: 73
8450 13:41:59.292334
8451 13:41:59.292883 Set Vref, RX VrefLevel [Byte0]: 74
8452 13:41:59.295262 [Byte1]: 74
8453 13:41:59.300088
8454 13:41:59.300634 Set Vref, RX VrefLevel [Byte0]: 75
8455 13:41:59.302951 [Byte1]: 75
8456 13:41:59.307475
8457 13:41:59.308017 Set Vref, RX VrefLevel [Byte0]: 76
8458 13:41:59.310716 [Byte1]: 76
8459 13:41:59.314956
8460 13:41:59.315766 Set Vref, RX VrefLevel [Byte0]: 77
8461 13:41:59.318408 [Byte1]: 77
8462 13:41:59.322874
8463 13:41:59.323418 Final RX Vref Byte 0 = 60 to rank0
8464 13:41:59.325788 Final RX Vref Byte 1 = 56 to rank0
8465 13:41:59.329451 Final RX Vref Byte 0 = 60 to rank1
8466 13:41:59.332320 Final RX Vref Byte 1 = 56 to rank1==
8467 13:41:59.335833 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:41:59.342263 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8469 13:41:59.342718 ==
8470 13:41:59.343077 DQS Delay:
8471 13:41:59.346147 DQS0 = 0, DQS1 = 0
8472 13:41:59.346692 DQM Delay:
8473 13:41:59.347051 DQM0 = 128, DQM1 = 124
8474 13:41:59.349280 DQ Delay:
8475 13:41:59.352527 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8476 13:41:59.356116 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =126
8477 13:41:59.358752 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8478 13:41:59.362590 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8479 13:41:59.363138
8480 13:41:59.363502
8481 13:41:59.363835
8482 13:41:59.365801 [DramC_TX_OE_Calibration] TA2
8483 13:41:59.369214 Original DQ_B0 (3 6) =30, OEN = 27
8484 13:41:59.372233 Original DQ_B1 (3 6) =30, OEN = 27
8485 13:41:59.375848 24, 0x0, End_B0=24 End_B1=24
8486 13:41:59.376397 25, 0x0, End_B0=25 End_B1=25
8487 13:41:59.378530 26, 0x0, End_B0=26 End_B1=26
8488 13:41:59.382299 27, 0x0, End_B0=27 End_B1=27
8489 13:41:59.385362 28, 0x0, End_B0=28 End_B1=28
8490 13:41:59.388859 29, 0x0, End_B0=29 End_B1=29
8491 13:41:59.389471 30, 0x0, End_B0=30 End_B1=30
8492 13:41:59.392096 31, 0x4141, End_B0=30 End_B1=30
8493 13:41:59.395259 Byte0 end_step=30 best_step=27
8494 13:41:59.398868 Byte1 end_step=30 best_step=27
8495 13:41:59.402153 Byte0 TX OE(2T, 0.5T) = (3, 3)
8496 13:41:59.405285 Byte1 TX OE(2T, 0.5T) = (3, 3)
8497 13:41:59.405862
8498 13:41:59.406224
8499 13:41:59.412243 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8500 13:41:59.415401 CH1 RK0: MR19=303, MR18=2727
8501 13:41:59.421882 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8502 13:41:59.422415
8503 13:41:59.425658 ----->DramcWriteLeveling(PI) begin...
8504 13:41:59.426204 ==
8505 13:41:59.428635 Dram Type= 6, Freq= 0, CH_1, rank 1
8506 13:41:59.432231 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8507 13:41:59.432784 ==
8508 13:41:59.434965 Write leveling (Byte 0): 23 => 23
8509 13:41:59.438544 Write leveling (Byte 1): 23 => 23
8510 13:41:59.441564 DramcWriteLeveling(PI) end<-----
8511 13:41:59.442068
8512 13:41:59.442428 ==
8513 13:41:59.445332 Dram Type= 6, Freq= 0, CH_1, rank 1
8514 13:41:59.448944 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8515 13:41:59.449546 ==
8516 13:41:59.451861 [Gating] SW mode calibration
8517 13:41:59.458388 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8518 13:41:59.464891 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8519 13:41:59.468305 0 12 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8520 13:41:59.475195 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8521 13:41:59.478270 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8522 13:41:59.481208 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8523 13:41:59.488142 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8524 13:41:59.491540 0 12 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8525 13:41:59.494412 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8526 13:41:59.501475 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8527 13:41:59.504645 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8528 13:41:59.508258 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8529 13:41:59.514833 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8530 13:41:59.517910 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8531 13:41:59.521383 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8532 13:41:59.528054 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8533 13:41:59.530919 0 13 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8534 13:41:59.534667 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8535 13:41:59.541097 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8536 13:41:59.544112 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8537 13:41:59.547963 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8538 13:41:59.554552 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8539 13:41:59.557451 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8540 13:41:59.560946 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8541 13:41:59.567340 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8542 13:41:59.570543 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8543 13:41:59.573781 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8544 13:41:59.580550 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8545 13:41:59.583849 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8546 13:41:59.587763 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8547 13:41:59.590551 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8548 13:41:59.597071 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8549 13:41:59.600827 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8550 13:41:59.604241 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8551 13:41:59.610558 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8552 13:41:59.614136 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8553 13:41:59.617080 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 13:41:59.623731 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 13:41:59.627003 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8556 13:41:59.630710 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 13:41:59.636931 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8558 13:41:59.640404 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8559 13:41:59.643558 Total UI for P1: 0, mck2ui 16
8560 13:41:59.646740 best dqsien dly found for B0: ( 1, 0, 24)
8561 13:41:59.650376 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8562 13:41:59.656600 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8563 13:41:59.660144 Total UI for P1: 0, mck2ui 16
8564 13:41:59.663415 best dqsien dly found for B1: ( 1, 0, 30)
8565 13:41:59.666709 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8566 13:41:59.670211 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8567 13:41:59.670665
8568 13:41:59.673500 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8569 13:41:59.677074 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8570 13:41:59.679657 [Gating] SW calibration Done
8571 13:41:59.680113 ==
8572 13:41:59.683532 Dram Type= 6, Freq= 0, CH_1, rank 1
8573 13:41:59.686747 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8574 13:41:59.687303 ==
8575 13:41:59.690017 RX Vref Scan: 0
8576 13:41:59.690470
8577 13:41:59.693491 RX Vref 0 -> 0, step: 1
8578 13:41:59.693946
8579 13:41:59.694304 RX Delay 0 -> 252, step: 8
8580 13:41:59.699979 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8581 13:41:59.703072 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8582 13:41:59.706532 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8583 13:41:59.709788 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8584 13:41:59.713402 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8585 13:41:59.719376 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8586 13:41:59.722994 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8587 13:41:59.726438 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8588 13:41:59.729384 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8589 13:41:59.733390 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8590 13:41:59.739489 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8591 13:41:59.743183 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8592 13:41:59.745847 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8593 13:41:59.749571 iDelay=200, Bit 13, Center 135 (72 ~ 199) 128
8594 13:41:59.752731 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8595 13:41:59.759544 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8596 13:41:59.760074 ==
8597 13:41:59.762332 Dram Type= 6, Freq= 0, CH_1, rank 1
8598 13:41:59.766024 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8599 13:41:59.766511 ==
8600 13:41:59.766866 DQS Delay:
8601 13:41:59.768902 DQS0 = 0, DQS1 = 0
8602 13:41:59.769373 DQM Delay:
8603 13:41:59.772382 DQM0 = 131, DQM1 = 125
8604 13:41:59.772835 DQ Delay:
8605 13:41:59.775941 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8606 13:41:59.778948 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8607 13:41:59.782741 DQ8 =107, DQ9 =115, DQ10 =131, DQ11 =115
8608 13:41:59.789193 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8609 13:41:59.789773
8610 13:41:59.790130
8611 13:41:59.790458 ==
8612 13:41:59.791941 Dram Type= 6, Freq= 0, CH_1, rank 1
8613 13:41:59.795724 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8614 13:41:59.796274 ==
8615 13:41:59.796635
8616 13:41:59.796962
8617 13:41:59.799073 TX Vref Scan disable
8618 13:41:59.799622 == TX Byte 0 ==
8619 13:41:59.805917 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8620 13:41:59.808995 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8621 13:41:59.809497 == TX Byte 1 ==
8622 13:41:59.815508 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8623 13:41:59.819071 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8624 13:41:59.819772 ==
8625 13:41:59.821770 Dram Type= 6, Freq= 0, CH_1, rank 1
8626 13:41:59.825170 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8627 13:41:59.825772 ==
8628 13:41:59.840236
8629 13:41:59.843030 TX Vref early break, caculate TX vref
8630 13:41:59.846288 TX Vref=16, minBit 3, minWin=21, winSum=368
8631 13:41:59.849454 TX Vref=18, minBit 1, minWin=22, winSum=377
8632 13:41:59.852954 TX Vref=20, minBit 1, minWin=22, winSum=388
8633 13:41:59.856389 TX Vref=22, minBit 0, minWin=24, winSum=400
8634 13:41:59.859992 TX Vref=24, minBit 0, minWin=24, winSum=401
8635 13:41:59.866251 TX Vref=26, minBit 0, minWin=25, winSum=416
8636 13:41:59.869465 TX Vref=28, minBit 0, minWin=24, winSum=418
8637 13:41:59.872683 TX Vref=30, minBit 0, minWin=24, winSum=412
8638 13:41:59.876321 TX Vref=32, minBit 0, minWin=23, winSum=404
8639 13:41:59.879473 TX Vref=34, minBit 5, minWin=23, winSum=398
8640 13:41:59.882887 TX Vref=36, minBit 0, minWin=22, winSum=391
8641 13:41:59.889756 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8642 13:41:59.890307
8643 13:41:59.892553 Final TX Range 0 Vref 26
8644 13:41:59.893112
8645 13:41:59.893513 ==
8646 13:41:59.895985 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 13:41:59.899633 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 13:41:59.900187 ==
8649 13:41:59.900543
8650 13:41:59.900870
8651 13:41:59.902649 TX Vref Scan disable
8652 13:41:59.909244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8653 13:41:59.909832 == TX Byte 0 ==
8654 13:41:59.912675 u2DelayCellOfst[0]=14 cells (4 PI)
8655 13:41:59.916254 u2DelayCellOfst[1]=10 cells (3 PI)
8656 13:41:59.919111 u2DelayCellOfst[2]=0 cells (0 PI)
8657 13:41:59.922401 u2DelayCellOfst[3]=7 cells (2 PI)
8658 13:41:59.926177 u2DelayCellOfst[4]=7 cells (2 PI)
8659 13:41:59.929377 u2DelayCellOfst[5]=14 cells (4 PI)
8660 13:41:59.932731 u2DelayCellOfst[6]=14 cells (4 PI)
8661 13:41:59.936246 u2DelayCellOfst[7]=3 cells (1 PI)
8662 13:41:59.938943 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8663 13:41:59.942482 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8664 13:41:59.945716 == TX Byte 1 ==
8665 13:41:59.949156 u2DelayCellOfst[8]=0 cells (0 PI)
8666 13:41:59.952139 u2DelayCellOfst[9]=7 cells (2 PI)
8667 13:41:59.952687 u2DelayCellOfst[10]=10 cells (3 PI)
8668 13:41:59.955731 u2DelayCellOfst[11]=3 cells (1 PI)
8669 13:41:59.958958 u2DelayCellOfst[12]=18 cells (5 PI)
8670 13:41:59.962033 u2DelayCellOfst[13]=21 cells (6 PI)
8671 13:41:59.965707 u2DelayCellOfst[14]=21 cells (6 PI)
8672 13:41:59.968821 u2DelayCellOfst[15]=18 cells (5 PI)
8673 13:41:59.975334 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8674 13:41:59.978573 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8675 13:41:59.979027 DramC Write-DBI on
8676 13:41:59.979380 ==
8677 13:41:59.981629 Dram Type= 6, Freq= 0, CH_1, rank 1
8678 13:41:59.988725 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8679 13:41:59.989325 ==
8680 13:41:59.989709
8681 13:41:59.990040
8682 13:41:59.990408 TX Vref Scan disable
8683 13:41:59.992906 == TX Byte 0 ==
8684 13:41:59.995781 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8685 13:41:59.999391 == TX Byte 1 ==
8686 13:42:00.002206 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8687 13:42:00.005823 DramC Write-DBI off
8688 13:42:00.006276
8689 13:42:00.006629 [DATLAT]
8690 13:42:00.006957 Freq=1600, CH1 RK1
8691 13:42:00.007275
8692 13:42:00.009336 DATLAT Default: 0xe
8693 13:42:00.009805 0, 0xFFFF, sum = 0
8694 13:42:00.012426 1, 0xFFFF, sum = 0
8695 13:42:00.016061 2, 0xFFFF, sum = 0
8696 13:42:00.016610 3, 0xFFFF, sum = 0
8697 13:42:00.018910 4, 0xFFFF, sum = 0
8698 13:42:00.019461 5, 0xFFFF, sum = 0
8699 13:42:00.022379 6, 0xFFFF, sum = 0
8700 13:42:00.022936 7, 0xFFFF, sum = 0
8701 13:42:00.025627 8, 0xFFFF, sum = 0
8702 13:42:00.026186 9, 0xFFFF, sum = 0
8703 13:42:00.028668 10, 0xFFFF, sum = 0
8704 13:42:00.029126 11, 0xFFFF, sum = 0
8705 13:42:00.032461 12, 0xF7F, sum = 0
8706 13:42:00.032935 13, 0x0, sum = 1
8707 13:42:00.035696 14, 0x0, sum = 2
8708 13:42:00.036152 15, 0x0, sum = 3
8709 13:42:00.038948 16, 0x0, sum = 4
8710 13:42:00.039585 best_step = 14
8711 13:42:00.039962
8712 13:42:00.040300 ==
8713 13:42:00.042415 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 13:42:00.045475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8715 13:42:00.048967 ==
8716 13:42:00.049631 RX Vref Scan: 0
8717 13:42:00.050038
8718 13:42:00.051923 RX Vref 0 -> 0, step: 1
8719 13:42:00.052371
8720 13:42:00.052724 RX Delay 3 -> 252, step: 4
8721 13:42:00.059514 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8722 13:42:00.063025 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8723 13:42:00.065852 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8724 13:42:00.069326 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8725 13:42:00.072829 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8726 13:42:00.079838 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8727 13:42:00.082724 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8728 13:42:00.085950 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8729 13:42:00.089242 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8730 13:42:00.092728 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8731 13:42:00.099393 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8732 13:42:00.102364 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8733 13:42:00.105913 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8734 13:42:00.108910 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8735 13:42:00.116008 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8736 13:42:00.119279 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8737 13:42:00.119686 ==
8738 13:42:00.122485 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 13:42:00.125384 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8740 13:42:00.125828 ==
8741 13:42:00.128899 DQS Delay:
8742 13:42:00.129421 DQS0 = 0, DQS1 = 0
8743 13:42:00.129873 DQM Delay:
8744 13:42:00.132386 DQM0 = 126, DQM1 = 123
8745 13:42:00.132863 DQ Delay:
8746 13:42:00.135748 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8747 13:42:00.139022 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8748 13:42:00.142437 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8749 13:42:00.148792 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8750 13:42:00.149202
8751 13:42:00.149615
8752 13:42:00.149929
8753 13:42:00.152112 [DramC_TX_OE_Calibration] TA2
8754 13:42:00.155702 Original DQ_B0 (3 6) =30, OEN = 27
8755 13:42:00.156406 Original DQ_B1 (3 6) =30, OEN = 27
8756 13:42:00.158578 24, 0x0, End_B0=24 End_B1=24
8757 13:42:00.162151 25, 0x0, End_B0=25 End_B1=25
8758 13:42:00.165102 26, 0x0, End_B0=26 End_B1=26
8759 13:42:00.168655 27, 0x0, End_B0=27 End_B1=27
8760 13:42:00.169113 28, 0x0, End_B0=28 End_B1=28
8761 13:42:00.171715 29, 0x0, End_B0=29 End_B1=29
8762 13:42:00.175364 30, 0x0, End_B0=30 End_B1=30
8763 13:42:00.178316 31, 0x4141, End_B0=30 End_B1=30
8764 13:42:00.181933 Byte0 end_step=30 best_step=27
8765 13:42:00.182574 Byte1 end_step=30 best_step=27
8766 13:42:00.185046 Byte0 TX OE(2T, 0.5T) = (3, 3)
8767 13:42:00.188494 Byte1 TX OE(2T, 0.5T) = (3, 3)
8768 13:42:00.188906
8769 13:42:00.189230
8770 13:42:00.198497 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8771 13:42:00.201864 CH1 RK1: MR19=303, MR18=1F1F
8772 13:42:00.205222 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8773 13:42:00.208055 [RxdqsGatingPostProcess] freq 1600
8774 13:42:00.214769 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8775 13:42:00.218527 Pre-setting of DQS Precalculation
8776 13:42:00.222014 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8777 13:42:00.231601 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8778 13:42:00.238410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8779 13:42:00.238869
8780 13:42:00.239230
8781 13:42:00.241243 [Calibration Summary] 3200 Mbps
8782 13:42:00.241738 CH 0, Rank 0
8783 13:42:00.244708 SW Impedance : PASS
8784 13:42:00.245163 DUTY Scan : NO K
8785 13:42:00.248279 ZQ Calibration : PASS
8786 13:42:00.251415 Jitter Meter : NO K
8787 13:42:00.251878 CBT Training : PASS
8788 13:42:00.254652 Write leveling : PASS
8789 13:42:00.257961 RX DQS gating : PASS
8790 13:42:00.258420 RX DQ/DQS(RDDQC) : PASS
8791 13:42:00.261224 TX DQ/DQS : PASS
8792 13:42:00.264565 RX DATLAT : PASS
8793 13:42:00.265024 RX DQ/DQS(Engine): PASS
8794 13:42:00.268051 TX OE : PASS
8795 13:42:00.268506 All Pass.
8796 13:42:00.268867
8797 13:42:00.271030 CH 0, Rank 1
8798 13:42:00.271487 SW Impedance : PASS
8799 13:42:00.274806 DUTY Scan : NO K
8800 13:42:00.277661 ZQ Calibration : PASS
8801 13:42:00.278117 Jitter Meter : NO K
8802 13:42:00.281184 CBT Training : PASS
8803 13:42:00.284166 Write leveling : PASS
8804 13:42:00.284618 RX DQS gating : PASS
8805 13:42:00.287818 RX DQ/DQS(RDDQC) : PASS
8806 13:42:00.288273 TX DQ/DQS : PASS
8807 13:42:00.290833 RX DATLAT : PASS
8808 13:42:00.294320 RX DQ/DQS(Engine): PASS
8809 13:42:00.294776 TX OE : PASS
8810 13:42:00.297811 All Pass.
8811 13:42:00.298264
8812 13:42:00.298635 CH 1, Rank 0
8813 13:42:00.300741 SW Impedance : PASS
8814 13:42:00.301153 DUTY Scan : NO K
8815 13:42:00.304158 ZQ Calibration : PASS
8816 13:42:00.307876 Jitter Meter : NO K
8817 13:42:00.308573 CBT Training : PASS
8818 13:42:00.311111 Write leveling : PASS
8819 13:42:00.314490 RX DQS gating : PASS
8820 13:42:00.315053 RX DQ/DQS(RDDQC) : PASS
8821 13:42:00.318000 TX DQ/DQS : PASS
8822 13:42:00.321250 RX DATLAT : PASS
8823 13:42:00.321860 RX DQ/DQS(Engine): PASS
8824 13:42:00.324457 TX OE : PASS
8825 13:42:00.324919 All Pass.
8826 13:42:00.325280
8827 13:42:00.327751 CH 1, Rank 1
8828 13:42:00.328312 SW Impedance : PASS
8829 13:42:00.330566 DUTY Scan : NO K
8830 13:42:00.334242 ZQ Calibration : PASS
8831 13:42:00.334817 Jitter Meter : NO K
8832 13:42:00.337615 CBT Training : PASS
8833 13:42:00.340714 Write leveling : PASS
8834 13:42:00.341171 RX DQS gating : PASS
8835 13:42:00.344416 RX DQ/DQS(RDDQC) : PASS
8836 13:42:00.347159 TX DQ/DQS : PASS
8837 13:42:00.347623 RX DATLAT : PASS
8838 13:42:00.350745 RX DQ/DQS(Engine): PASS
8839 13:42:00.351197 TX OE : PASS
8840 13:42:00.354091 All Pass.
8841 13:42:00.354636
8842 13:42:00.354995 DramC Write-DBI on
8843 13:42:00.357487 PER_BANK_REFRESH: Hybrid Mode
8844 13:42:00.360795 TX_TRACKING: ON
8845 13:42:00.367168 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8846 13:42:00.377348 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8847 13:42:00.383984 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8848 13:42:00.386743 [FAST_K] Save calibration result to emmc
8849 13:42:00.390611 sync common calibartion params.
8850 13:42:00.391168 sync cbt_mode0:0, 1:0
8851 13:42:00.393447 dram_init: ddr_geometry: 0
8852 13:42:00.397081 dram_init: ddr_geometry: 0
8853 13:42:00.400685 dram_init: ddr_geometry: 0
8854 13:42:00.401243 0:dram_rank_size:80000000
8855 13:42:00.403611 1:dram_rank_size:80000000
8856 13:42:00.410085 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8857 13:42:00.410637 DFS_SHUFFLE_HW_MODE: ON
8858 13:42:00.416875 dramc_set_vcore_voltage set vcore to 725000
8859 13:42:00.417463 Read voltage for 1600, 0
8860 13:42:00.417835 Vio18 = 0
8861 13:42:00.420278 Vcore = 725000
8862 13:42:00.420878 Vdram = 0
8863 13:42:00.421479 Vddq = 0
8864 13:42:00.423131 Vmddr = 0
8865 13:42:00.423586 switch to 3200 Mbps bootup
8866 13:42:00.426708 [DramcRunTimeConfig]
8867 13:42:00.427272 PHYPLL
8868 13:42:00.430081 DPM_CONTROL_AFTERK: ON
8869 13:42:00.430641 PER_BANK_REFRESH: ON
8870 13:42:00.433404 REFRESH_OVERHEAD_REDUCTION: ON
8871 13:42:00.436596 CMD_PICG_NEW_MODE: OFF
8872 13:42:00.437052 XRTWTW_NEW_MODE: ON
8873 13:42:00.440118 XRTRTR_NEW_MODE: ON
8874 13:42:00.440572 TX_TRACKING: ON
8875 13:42:00.443883 RDSEL_TRACKING: OFF
8876 13:42:00.446982 DQS Precalculation for DVFS: ON
8877 13:42:00.447448 RX_TRACKING: OFF
8878 13:42:00.450176 HW_GATING DBG: ON
8879 13:42:00.450692 ZQCS_ENABLE_LP4: ON
8880 13:42:00.453426 RX_PICG_NEW_MODE: ON
8881 13:42:00.453989 TX_PICG_NEW_MODE: ON
8882 13:42:00.456847 ENABLE_RX_DCM_DPHY: ON
8883 13:42:00.460006 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8884 13:42:00.463657 DUMMY_READ_FOR_TRACKING: OFF
8885 13:42:00.466680 !!! SPM_CONTROL_AFTERK: OFF
8886 13:42:00.467170 !!! SPM could not control APHY
8887 13:42:00.469547 IMPEDANCE_TRACKING: ON
8888 13:42:00.470004 TEMP_SENSOR: ON
8889 13:42:00.473367 HW_SAVE_FOR_SR: OFF
8890 13:42:00.476498 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8891 13:42:00.480113 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8892 13:42:00.482905 Read ODT Tracking: ON
8893 13:42:00.483368 Refresh Rate DeBounce: ON
8894 13:42:00.486326 DFS_NO_QUEUE_FLUSH: ON
8895 13:42:00.489941 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8896 13:42:00.493480 ENABLE_DFS_RUNTIME_MRW: OFF
8897 13:42:00.493942 DDR_RESERVE_NEW_MODE: ON
8898 13:42:00.496703 MR_CBT_SWITCH_FREQ: ON
8899 13:42:00.499445 =========================
8900 13:42:00.517617 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8901 13:42:00.520381 dram_init: ddr_geometry: 0
8902 13:42:00.538707 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8903 13:42:00.541753 dram_init: dram init end (result: 0)
8904 13:42:00.548620 DRAM-K: Full calibration passed in 23430 msecs
8905 13:42:00.551783 MRC: failed to locate region type 0.
8906 13:42:00.552345 DRAM rank0 size:0x80000000,
8907 13:42:00.555219 DRAM rank1 size=0x80000000
8908 13:42:00.564949 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8909 13:42:00.571904 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8910 13:42:00.578621 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8911 13:42:00.584771 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8912 13:42:00.588372 DRAM rank0 size:0x80000000,
8913 13:42:00.591939 DRAM rank1 size=0x80000000
8914 13:42:00.592498 CBMEM:
8915 13:42:00.594887 IMD: root @ 0xfffff000 254 entries.
8916 13:42:00.598056 IMD: root @ 0xffffec00 62 entries.
8917 13:42:00.601934 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8918 13:42:00.604930 WARNING: RO_VPD is uninitialized or empty.
8919 13:42:00.611261 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8920 13:42:00.618230 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8921 13:42:00.631213 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8922 13:42:00.642131 BS: romstage times (exec / console): total (unknown) / 22966 ms
8923 13:42:00.642793
8924 13:42:00.643164
8925 13:42:00.652481 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8926 13:42:00.655372 ARM64: Exception handlers installed.
8927 13:42:00.658576 ARM64: Testing exception
8928 13:42:00.661913 ARM64: Done test exception
8929 13:42:00.662372 Enumerating buses...
8930 13:42:00.665496 Show all devs... Before device enumeration.
8931 13:42:00.668731 Root Device: enabled 1
8932 13:42:00.672107 CPU_CLUSTER: 0: enabled 1
8933 13:42:00.672667 CPU: 00: enabled 1
8934 13:42:00.674986 Compare with tree...
8935 13:42:00.675442 Root Device: enabled 1
8936 13:42:00.679108 CPU_CLUSTER: 0: enabled 1
8937 13:42:00.682071 CPU: 00: enabled 1
8938 13:42:00.682533 Root Device scanning...
8939 13:42:00.684935 scan_static_bus for Root Device
8940 13:42:00.688760 CPU_CLUSTER: 0 enabled
8941 13:42:00.691725 scan_static_bus for Root Device done
8942 13:42:00.695183 scan_bus: bus Root Device finished in 8 msecs
8943 13:42:00.695647 done
8944 13:42:00.701532 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8945 13:42:00.705255 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8946 13:42:00.711650 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8947 13:42:00.715430 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8948 13:42:00.718237 Allocating resources...
8949 13:42:00.721957 Reading resources...
8950 13:42:00.724927 Root Device read_resources bus 0 link: 0
8951 13:42:00.728516 DRAM rank0 size:0x80000000,
8952 13:42:00.729073 DRAM rank1 size=0x80000000
8953 13:42:00.731517 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8954 13:42:00.734479 CPU: 00 missing read_resources
8955 13:42:00.741597 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8956 13:42:00.744479 Root Device read_resources bus 0 link: 0 done
8957 13:42:00.745043 Done reading resources.
8958 13:42:00.751676 Show resources in subtree (Root Device)...After reading.
8959 13:42:00.754527 Root Device child on link 0 CPU_CLUSTER: 0
8960 13:42:00.758000 CPU_CLUSTER: 0 child on link 0 CPU: 00
8961 13:42:00.767894 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8962 13:42:00.768466 CPU: 00
8963 13:42:00.771348 Root Device assign_resources, bus 0 link: 0
8964 13:42:00.774100 CPU_CLUSTER: 0 missing set_resources
8965 13:42:00.781368 Root Device assign_resources, bus 0 link: 0 done
8966 13:42:00.781932 Done setting resources.
8967 13:42:00.787461 Show resources in subtree (Root Device)...After assigning values.
8968 13:42:00.790512 Root Device child on link 0 CPU_CLUSTER: 0
8969 13:42:00.794002 CPU_CLUSTER: 0 child on link 0 CPU: 00
8970 13:42:00.804414 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8971 13:42:00.804974 CPU: 00
8972 13:42:00.807006 Done allocating resources.
8973 13:42:00.813542 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8974 13:42:00.814154 Enabling resources...
8975 13:42:00.814537 done.
8976 13:42:00.820920 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8977 13:42:00.823784 Initializing devices...
8978 13:42:00.824336 Root Device init
8979 13:42:00.827117 init hardware done!
8980 13:42:00.827627 0x00000018: ctrlr->caps
8981 13:42:00.830012 52.000 MHz: ctrlr->f_max
8982 13:42:00.833708 0.400 MHz: ctrlr->f_min
8983 13:42:00.834175 0x40ff8080: ctrlr->voltages
8984 13:42:00.836613 sclk: 390625
8985 13:42:00.837092 Bus Width = 1
8986 13:42:00.837511 sclk: 390625
8987 13:42:00.840113 Bus Width = 1
8988 13:42:00.843245 Early init status = 3
8989 13:42:00.847024 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8990 13:42:00.850385 in-header: 03 fc 00 00 01 00 00 00
8991 13:42:00.853610 in-data: 00
8992 13:42:00.857150 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8993 13:42:00.862308 in-header: 03 fd 00 00 00 00 00 00
8994 13:42:00.865136 in-data:
8995 13:42:00.868686 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8996 13:42:00.873475 in-header: 03 fc 00 00 01 00 00 00
8997 13:42:00.876702 in-data: 00
8998 13:42:00.879895 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8999 13:42:00.885477 in-header: 03 fd 00 00 00 00 00 00
9000 13:42:00.889059 in-data:
9001 13:42:00.892504 [SSUSB] Setting up USB HOST controller...
9002 13:42:00.895725 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9003 13:42:00.898340 [SSUSB] phy power-on done.
9004 13:42:00.901926 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9005 13:42:00.908558 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9006 13:42:00.911716 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9007 13:42:00.918314 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9008 13:42:00.925425 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9009 13:42:00.931307 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9010 13:42:00.937986 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9011 13:42:00.944768 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9012 13:42:00.948655 SPM: binary array size = 0x9dc
9013 13:42:00.951576 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9014 13:42:00.957742 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9015 13:42:00.964742 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9016 13:42:00.971288 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9017 13:42:00.974651 configure_display: Starting display init
9018 13:42:01.008883 anx7625_power_on_init: Init interface.
9019 13:42:01.011857 anx7625_disable_pd_protocol: Disabled PD feature.
9020 13:42:01.015376 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9021 13:42:01.043105 anx7625_start_dp_work: Secure OCM version=00
9022 13:42:01.046066 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9023 13:42:01.061128 sp_tx_get_edid_block: EDID Block = 1
9024 13:42:01.163649 Extracted contents:
9025 13:42:01.166788 header: 00 ff ff ff ff ff ff 00
9026 13:42:01.169858 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9027 13:42:01.173253 version: 01 04
9028 13:42:01.176695 basic params: 95 1f 11 78 0a
9029 13:42:01.180047 chroma info: 76 90 94 55 54 90 27 21 50 54
9030 13:42:01.182984 established: 00 00 00
9031 13:42:01.189976 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9032 13:42:01.196774 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9033 13:42:01.199754 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9034 13:42:01.206208 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9035 13:42:01.213187 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9036 13:42:01.216257 extensions: 00
9037 13:42:01.216801 checksum: fb
9038 13:42:01.217163
9039 13:42:01.219764 Manufacturer: IVO Model 57d Serial Number 0
9040 13:42:01.223010 Made week 0 of 2020
9041 13:42:01.225935 EDID version: 1.4
9042 13:42:01.226383 Digital display
9043 13:42:01.229891 6 bits per primary color channel
9044 13:42:01.232533 DisplayPort interface
9045 13:42:01.232986 Maximum image size: 31 cm x 17 cm
9046 13:42:01.236319 Gamma: 220%
9047 13:42:01.236860 Check DPMS levels
9048 13:42:01.239817 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9049 13:42:01.246384 First detailed timing is preferred timing
9050 13:42:01.246943 Established timings supported:
9051 13:42:01.249250 Standard timings supported:
9052 13:42:01.252829 Detailed timings
9053 13:42:01.256386 Hex of detail: 383680a07038204018303c0035ae10000019
9054 13:42:01.263170 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9055 13:42:01.266096 0780 0798 07c8 0820 hborder 0
9056 13:42:01.269349 0438 043b 0447 0458 vborder 0
9057 13:42:01.272543 -hsync -vsync
9058 13:42:01.273102 Did detailed timing
9059 13:42:01.279277 Hex of detail: 000000000000000000000000000000000000
9060 13:42:01.282137 Manufacturer-specified data, tag 0
9061 13:42:01.285412 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9062 13:42:01.289095 ASCII string: InfoVision
9063 13:42:01.292599 Hex of detail: 000000fe00523134304e574635205248200a
9064 13:42:01.295727 ASCII string: R140NWF5 RH
9065 13:42:01.296283 Checksum
9066 13:42:01.299122 Checksum: 0xfb (valid)
9067 13:42:01.301774 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9068 13:42:01.305439 DSI data_rate: 832800000 bps
9069 13:42:01.312073 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9070 13:42:01.315450 anx7625_parse_edid: pixelclock(138800).
9071 13:42:01.318381 hactive(1920), hsync(48), hfp(24), hbp(88)
9072 13:42:01.322005 vactive(1080), vsync(12), vfp(3), vbp(17)
9073 13:42:01.325024 anx7625_dsi_config: config dsi.
9074 13:42:01.331614 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9075 13:42:01.345459 anx7625_dsi_config: success to config DSI
9076 13:42:01.348924 anx7625_dp_start: MIPI phy setup OK.
9077 13:42:01.352370 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9078 13:42:01.355567 mtk_ddp_mode_set invalid vrefresh 60
9079 13:42:01.359202 main_disp_path_setup
9080 13:42:01.359758 ovl_layer_smi_id_en
9081 13:42:01.361991 ovl_layer_smi_id_en
9082 13:42:01.362450 ccorr_config
9083 13:42:01.362810 aal_config
9084 13:42:01.365266 gamma_config
9085 13:42:01.366118 postmask_config
9086 13:42:01.368560 dither_config
9087 13:42:01.372164 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9088 13:42:01.378644 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9089 13:42:01.381607 Root Device init finished in 554 msecs
9090 13:42:01.384951 CPU_CLUSTER: 0 init
9091 13:42:01.391964 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9092 13:42:01.398221 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9093 13:42:01.398683 APU_MBOX 0x190000b0 = 0x10001
9094 13:42:01.401254 APU_MBOX 0x190001b0 = 0x10001
9095 13:42:01.404587 APU_MBOX 0x190005b0 = 0x10001
9096 13:42:01.407890 APU_MBOX 0x190006b0 = 0x10001
9097 13:42:01.414963 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9098 13:42:01.424556 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9099 13:42:01.436794 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9100 13:42:01.443154 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9101 13:42:01.455021 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9102 13:42:01.464000 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9103 13:42:01.467649 CPU_CLUSTER: 0 init finished in 81 msecs
9104 13:42:01.470836 Devices initialized
9105 13:42:01.474392 Show all devs... After init.
9106 13:42:01.474843 Root Device: enabled 1
9107 13:42:01.477835 CPU_CLUSTER: 0: enabled 1
9108 13:42:01.481152 CPU: 00: enabled 1
9109 13:42:01.484454 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9110 13:42:01.487635 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9111 13:42:01.490829 ELOG: NV offset 0x57f000 size 0x1000
9112 13:42:01.497473 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9113 13:42:01.504437 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9114 13:42:01.507140 ELOG: Event(17) added with size 13 at 2024-05-28 13:42:01 UTC
9115 13:42:01.510762 out: cmd=0x121: 03 db 21 01 00 00 00 00
9116 13:42:01.515652 in-header: 03 ea 00 00 2c 00 00 00
9117 13:42:01.528592 in-data: 79 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9118 13:42:01.535828 ELOG: Event(A1) added with size 10 at 2024-05-28 13:42:01 UTC
9119 13:42:01.541911 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9120 13:42:01.545605 ELOG: Event(A0) added with size 9 at 2024-05-28 13:42:01 UTC
9121 13:42:01.552007 elog_add_boot_reason: Logged dev mode boot
9122 13:42:01.555647 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9123 13:42:01.559202 Finalize devices...
9124 13:42:01.559763 Devices finalized
9125 13:42:01.565857 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9126 13:42:01.568988 Writing coreboot table at 0xffe64000
9127 13:42:01.572036 0. 000000000010a000-0000000000113fff: RAMSTAGE
9128 13:42:01.575420 1. 0000000040000000-00000000400fffff: RAM
9129 13:42:01.579085 2. 0000000040100000-000000004032afff: RAMSTAGE
9130 13:42:01.585504 3. 000000004032b000-00000000545fffff: RAM
9131 13:42:01.588711 4. 0000000054600000-000000005465ffff: BL31
9132 13:42:01.592198 5. 0000000054660000-00000000ffe63fff: RAM
9133 13:42:01.595013 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9134 13:42:01.602112 7. 0000000100000000-000000013fffffff: RAM
9135 13:42:01.602804 Passing 5 GPIOs to payload:
9136 13:42:01.608319 NAME | PORT | POLARITY | VALUE
9137 13:42:01.611798 EC in RW | 0x000000aa | low | undefined
9138 13:42:01.618642 EC interrupt | 0x00000005 | low | undefined
9139 13:42:01.621671 TPM interrupt | 0x000000ab | high | undefined
9140 13:42:01.625340 SD card detect | 0x00000011 | high | undefined
9141 13:42:01.631787 speaker enable | 0x00000093 | high | undefined
9142 13:42:01.634859 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9143 13:42:01.638165 in-header: 03 f8 00 00 02 00 00 00
9144 13:42:01.638640 in-data: 03 00
9145 13:42:01.641701 ADC[4]: Raw value=668222 ID=5
9146 13:42:01.644686 ADC[3]: Raw value=212549 ID=1
9147 13:42:01.645158 RAM Code: 0x51
9148 13:42:01.648225 ADC[6]: Raw value=74410 ID=0
9149 13:42:01.651227 ADC[5]: Raw value=211444 ID=1
9150 13:42:01.651722 SKU Code: 0x1
9151 13:42:01.658115 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4156
9152 13:42:01.661759 coreboot table: 964 bytes.
9153 13:42:01.664709 IMD ROOT 0. 0xfffff000 0x00001000
9154 13:42:01.667850 IMD SMALL 1. 0xffffe000 0x00001000
9155 13:42:01.671241 RO MCACHE 2. 0xffffc000 0x00001104
9156 13:42:01.674560 CONSOLE 3. 0xfff7c000 0x00080000
9157 13:42:01.677884 FMAP 4. 0xfff7b000 0x00000452
9158 13:42:01.681183 TIME STAMP 5. 0xfff7a000 0x00000910
9159 13:42:01.684246 VBOOT WORK 6. 0xfff66000 0x00014000
9160 13:42:01.687782 RAMOOPS 7. 0xffe66000 0x00100000
9161 13:42:01.690933 COREBOOT 8. 0xffe64000 0x00002000
9162 13:42:01.691426 IMD small region:
9163 13:42:01.693955 IMD ROOT 0. 0xffffec00 0x00000400
9164 13:42:01.697814 VPD 1. 0xffffeb80 0x0000006c
9165 13:42:01.700628 MMC STATUS 2. 0xffffeb60 0x00000004
9166 13:42:01.707557 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9167 13:42:01.710507 Probing TPM: done!
9168 13:42:01.714416 Connected to device vid:did:rid of 1ae0:0028:00
9169 13:42:01.724274 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9170 13:42:01.727280 Initialized TPM device CR50 revision 0
9171 13:42:01.731689 Checking cr50 for pending updates
9172 13:42:01.734342 Reading cr50 TPM mode
9173 13:42:01.743064 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9174 13:42:01.750007 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9175 13:42:01.790035 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9176 13:42:01.793475 Checking segment from ROM address 0x40100000
9177 13:42:01.796699 Checking segment from ROM address 0x4010001c
9178 13:42:01.803435 Loading segment from ROM address 0x40100000
9179 13:42:01.804000 code (compression=0)
9180 13:42:01.810057 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9181 13:42:01.819864 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9182 13:42:01.820462 it's not compressed!
9183 13:42:01.826354 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9184 13:42:01.830072 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9185 13:42:01.850738 Loading segment from ROM address 0x4010001c
9186 13:42:01.851291 Entry Point 0x80000000
9187 13:42:01.853886 Loaded segments
9188 13:42:01.857161 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9189 13:42:01.863427 Jumping to boot code at 0x80000000(0xffe64000)
9190 13:42:01.870234 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9191 13:42:01.876781 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9192 13:42:01.884399 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9193 13:42:01.888027 Checking segment from ROM address 0x40100000
9194 13:42:01.891404 Checking segment from ROM address 0x4010001c
9195 13:42:01.898195 Loading segment from ROM address 0x40100000
9196 13:42:01.898748 code (compression=1)
9197 13:42:01.904589 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9198 13:42:01.914358 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9199 13:42:01.914994 using LZMA
9200 13:42:01.923577 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9201 13:42:01.929839 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9202 13:42:01.933360 Loading segment from ROM address 0x4010001c
9203 13:42:01.933938 Entry Point 0x54601000
9204 13:42:01.936339 Loaded segments
9205 13:42:01.939639 NOTICE: MT8192 bl31_setup
9206 13:42:01.946946 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9207 13:42:01.950458 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9208 13:42:01.953442 WARNING: region 0:
9209 13:42:01.956921 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9210 13:42:01.957604 WARNING: region 1:
9211 13:42:01.963346 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9212 13:42:01.967250 WARNING: region 2:
9213 13:42:01.970170 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9214 13:42:01.973465 WARNING: region 3:
9215 13:42:01.976742 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9216 13:42:01.980198 WARNING: region 4:
9217 13:42:01.986708 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9218 13:42:01.987171 WARNING: region 5:
9219 13:42:01.989733 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9220 13:42:01.993442 WARNING: region 6:
9221 13:42:01.996590 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9222 13:42:02.000016 WARNING: region 7:
9223 13:42:02.003140 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9224 13:42:02.009903 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9225 13:42:02.013376 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9226 13:42:02.017032 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9227 13:42:02.023301 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9228 13:42:02.026462 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9229 13:42:02.029719 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9230 13:42:02.036502 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9231 13:42:02.040161 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9232 13:42:02.046427 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9233 13:42:02.050128 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9234 13:42:02.053451 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9235 13:42:02.059989 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9236 13:42:02.063482 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9237 13:42:02.066935 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9238 13:42:02.073359 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9239 13:42:02.076894 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9240 13:42:02.080494 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9241 13:42:02.086744 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9242 13:42:02.089845 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9243 13:42:02.096873 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9244 13:42:02.100387 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9245 13:42:02.103176 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9246 13:42:02.109821 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9247 13:42:02.113484 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9248 13:42:02.120182 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9249 13:42:02.123473 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9250 13:42:02.126553 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9251 13:42:02.132969 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9252 13:42:02.136661 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9253 13:42:02.143287 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9254 13:42:02.146714 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9255 13:42:02.150085 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9256 13:42:02.156787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9257 13:42:02.160275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9258 13:42:02.163302 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9259 13:42:02.166563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9260 13:42:02.173631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9261 13:42:02.176516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9262 13:42:02.179838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9263 13:42:02.183261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9264 13:42:02.190224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9265 13:42:02.192976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9266 13:42:02.196721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9267 13:42:02.200274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9268 13:42:02.206475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9269 13:42:02.209865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9270 13:42:02.213202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9271 13:42:02.216809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9272 13:42:02.223304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9273 13:42:02.226567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9274 13:42:02.233174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9275 13:42:02.236180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9276 13:42:02.243082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9277 13:42:02.246509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9278 13:42:02.249868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9279 13:42:02.256860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9280 13:42:02.259795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9281 13:42:02.266937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9282 13:42:02.269876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9283 13:42:02.273207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9284 13:42:02.279829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9285 13:42:02.283114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9286 13:42:02.289454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9287 13:42:02.292620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9288 13:42:02.300021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9289 13:42:02.303095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9290 13:42:02.309881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9291 13:42:02.312667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9292 13:42:02.316112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9293 13:42:02.323103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9294 13:42:02.326454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9295 13:42:02.333200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9296 13:42:02.336543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9297 13:42:02.343036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9298 13:42:02.346316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9299 13:42:02.349616 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9300 13:42:02.356155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9301 13:42:02.359887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9302 13:42:02.366526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9303 13:42:02.370135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9304 13:42:02.376356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9305 13:42:02.379593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9306 13:42:02.382619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9307 13:42:02.389972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9308 13:42:02.393033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9309 13:42:02.399813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9310 13:42:02.402592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9311 13:42:02.409683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9312 13:42:02.413326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9313 13:42:02.416402 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9314 13:42:02.423059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9315 13:42:02.426136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9316 13:42:02.432527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9317 13:42:02.436035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9318 13:42:02.442585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9319 13:42:02.446305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9320 13:42:02.449825 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9321 13:42:02.455889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9322 13:42:02.459440 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9323 13:42:02.462917 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9324 13:42:02.465992 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9325 13:42:02.472408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9326 13:42:02.476038 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9327 13:42:02.482660 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9328 13:42:02.485703 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9329 13:42:02.489213 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9330 13:42:02.495512 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9331 13:42:02.499222 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9332 13:42:02.505694 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9333 13:42:02.509258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9334 13:42:02.512307 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9335 13:42:02.518979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9336 13:42:02.522841 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9337 13:42:02.529132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9338 13:42:02.532462 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9339 13:42:02.535663 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9340 13:42:02.542416 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9341 13:42:02.545251 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9342 13:42:02.548876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9343 13:42:02.555415 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9344 13:42:02.559076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9345 13:42:02.561924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9346 13:42:02.565440 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9347 13:42:02.572133 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9348 13:42:02.575401 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9349 13:42:02.578716 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9350 13:42:02.585193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9351 13:42:02.589094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9352 13:42:02.595445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9353 13:42:02.598595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9354 13:42:02.602224 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9355 13:42:02.608788 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9356 13:42:02.612056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9357 13:42:02.615616 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9358 13:42:02.622069 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9359 13:42:02.625612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9360 13:42:02.632531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9361 13:42:02.635474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9362 13:42:02.639000 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9363 13:42:02.645845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9364 13:42:02.649084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9365 13:42:02.655735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9366 13:42:02.659310 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9367 13:42:02.662834 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9368 13:42:02.669258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9369 13:42:02.672227 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9370 13:42:02.675759 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9371 13:42:02.682705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9372 13:42:02.685727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9373 13:42:02.692354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9374 13:42:02.695634 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9375 13:42:02.699188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9376 13:42:02.705758 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9377 13:42:02.709452 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9378 13:42:02.715358 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9379 13:42:02.718857 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9380 13:42:02.721899 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9381 13:42:02.728566 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9382 13:42:02.732148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9383 13:42:02.735823 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9384 13:42:02.742296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9385 13:42:02.745278 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9386 13:42:02.751762 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9387 13:42:02.755441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9388 13:42:02.761828 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9389 13:42:02.765444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9390 13:42:02.768699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9391 13:42:02.775073 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9392 13:42:02.778557 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9393 13:42:02.781715 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9394 13:42:02.788889 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9395 13:42:02.792027 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9396 13:42:02.798161 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9397 13:42:02.802180 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9398 13:42:02.804916 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9399 13:42:02.811630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9400 13:42:02.815011 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9401 13:42:02.821683 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9402 13:42:02.824797 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9403 13:42:02.828238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9404 13:42:02.834554 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9405 13:42:02.837963 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9406 13:42:02.844641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9407 13:42:02.847917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9408 13:42:02.851251 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9409 13:42:02.858001 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9410 13:42:02.861394 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9411 13:42:02.867961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9412 13:42:02.871204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9413 13:42:02.874788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9414 13:42:02.881178 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9415 13:42:02.884667 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9416 13:42:02.891035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9417 13:42:02.894621 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9418 13:42:02.897601 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9419 13:42:02.904357 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9420 13:42:02.907626 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9421 13:42:02.914175 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9422 13:42:02.917758 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9423 13:42:02.924408 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9424 13:42:02.927383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9425 13:42:02.931000 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9426 13:42:02.937193 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9427 13:42:02.940946 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9428 13:42:02.947218 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9429 13:42:02.950860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9430 13:42:02.957646 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9431 13:42:02.960394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9432 13:42:02.963886 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9433 13:42:02.970338 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9434 13:42:02.973693 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9435 13:42:02.980479 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9436 13:42:02.983398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9437 13:42:02.990091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9438 13:42:02.993574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9439 13:42:02.997013 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9440 13:42:03.003831 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9441 13:42:03.006820 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9442 13:42:03.013571 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9443 13:42:03.016543 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9444 13:42:03.020194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9445 13:42:03.026889 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9446 13:42:03.030169 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9447 13:42:03.036916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9448 13:42:03.040520 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9449 13:42:03.046775 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9450 13:42:03.050276 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9451 13:42:03.053263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9452 13:42:03.060002 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9453 13:42:03.063636 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9454 13:42:03.066267 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9455 13:42:03.069990 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9456 13:42:03.076463 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9457 13:42:03.080159 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9458 13:42:03.083127 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9459 13:42:03.089878 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9460 13:42:03.092734 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9461 13:42:03.099643 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9462 13:42:03.103112 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9463 13:42:03.106232 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9464 13:42:03.112779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9465 13:42:03.116029 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9466 13:42:03.119644 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9467 13:42:03.126093 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9468 13:42:03.129434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9469 13:42:03.132678 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9470 13:42:03.139104 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9471 13:42:03.142653 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9472 13:42:03.145409 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9473 13:42:03.152557 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9474 13:42:03.155526 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9475 13:42:03.162344 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9476 13:42:03.166138 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9477 13:42:03.169219 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9478 13:42:03.175433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9479 13:42:03.178974 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9480 13:42:03.185921 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9481 13:42:03.188902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9482 13:42:03.192456 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9483 13:42:03.198566 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9484 13:42:03.202141 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9485 13:42:03.205752 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9486 13:42:03.212265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9487 13:42:03.215275 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9488 13:42:03.218638 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9489 13:42:03.225438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9490 13:42:03.228561 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9491 13:42:03.235545 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9492 13:42:03.238910 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9493 13:42:03.242004 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9494 13:42:03.245122 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9495 13:42:03.252170 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9496 13:42:03.254930 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9497 13:42:03.258477 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9498 13:42:03.261549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9499 13:42:03.265216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9500 13:42:03.271735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9501 13:42:03.275288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9502 13:42:03.278372 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9503 13:42:03.281670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9504 13:42:03.288014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9505 13:42:03.291294 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9506 13:42:03.298244 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9507 13:42:03.301466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9508 13:42:03.305108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9509 13:42:03.311580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9510 13:42:03.314362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9511 13:42:03.321182 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9512 13:42:03.324682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9513 13:42:03.327787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9514 13:42:03.334424 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9515 13:42:03.337605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9516 13:42:03.344281 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9517 13:42:03.347842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9518 13:42:03.353985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9519 13:42:03.357406 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9520 13:42:03.360937 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9521 13:42:03.367564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9522 13:42:03.370493 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9523 13:42:03.377360 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9524 13:42:03.380688 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9525 13:42:03.384235 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9526 13:42:03.390641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9527 13:42:03.394068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9528 13:42:03.400831 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9529 13:42:03.404421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9530 13:42:03.407012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9531 13:42:03.413966 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9532 13:42:03.417084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9533 13:42:03.423926 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9534 13:42:03.427209 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9535 13:42:03.434242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9536 13:42:03.436779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9537 13:42:03.440211 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9538 13:42:03.446865 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9539 13:42:03.450367 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9540 13:42:03.456896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9541 13:42:03.460489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9542 13:42:03.463665 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9543 13:42:03.470025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9544 13:42:03.473327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9545 13:42:03.479748 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9546 13:42:03.483656 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9547 13:42:03.486989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9548 13:42:03.493497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9549 13:42:03.496575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9550 13:42:03.503604 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9551 13:42:03.506691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9552 13:42:03.512941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9553 13:42:03.516288 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9554 13:42:03.519922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9555 13:42:03.526673 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9556 13:42:03.529477 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9557 13:42:03.536763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9558 13:42:03.539677 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9559 13:42:03.542974 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9560 13:42:03.549862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9561 13:42:03.553228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9562 13:42:03.560042 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9563 13:42:03.562917 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9564 13:42:03.566212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9565 13:42:03.572529 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9566 13:42:03.575990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9567 13:42:03.582692 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9568 13:42:03.586015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9569 13:42:03.589224 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9570 13:42:03.596457 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9571 13:42:03.599190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9572 13:42:03.605952 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9573 13:42:03.609465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9574 13:42:03.616090 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9575 13:42:03.619018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9576 13:42:03.622915 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9577 13:42:03.629573 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9578 13:42:03.632653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9579 13:42:03.639004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9580 13:42:03.642449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9581 13:42:03.649079 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9582 13:42:03.652318 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9583 13:42:03.658674 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9584 13:42:03.662273 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9585 13:42:03.665424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9586 13:42:03.672613 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9587 13:42:03.675260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9588 13:42:03.682447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9589 13:42:03.685361 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9590 13:42:03.691775 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9591 13:42:03.695204 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9592 13:42:03.698852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9593 13:42:03.705336 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9594 13:42:03.708309 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9595 13:42:03.715421 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9596 13:42:03.718579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9597 13:42:03.725262 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9598 13:42:03.728337 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9599 13:42:03.731645 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9600 13:42:03.738374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9601 13:42:03.742059 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9602 13:42:03.748690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9603 13:42:03.752205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9604 13:42:03.758507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9605 13:42:03.761662 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9606 13:42:03.765240 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9607 13:42:03.771952 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9608 13:42:03.775159 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9609 13:42:03.781564 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9610 13:42:03.785102 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9611 13:42:03.791574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9612 13:42:03.795031 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9613 13:42:03.801465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9614 13:42:03.804565 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9615 13:42:03.808154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9616 13:42:03.814944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9617 13:42:03.817822 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9618 13:42:03.824621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9619 13:42:03.828248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9620 13:42:03.834506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9621 13:42:03.838264 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9622 13:42:03.844245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9623 13:42:03.847519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9624 13:42:03.851093 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9625 13:42:03.857865 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9626 13:42:03.861102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9627 13:42:03.864738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9628 13:42:03.871271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9629 13:42:03.873986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9630 13:42:03.880898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9631 13:42:03.883901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9632 13:42:03.890674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9633 13:42:03.894178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9634 13:42:03.900948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9635 13:42:03.904167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9636 13:42:03.910740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9637 13:42:03.913949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9638 13:42:03.920247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9639 13:42:03.923919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9640 13:42:03.930156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9641 13:42:03.934005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9642 13:42:03.939873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9643 13:42:03.943475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9644 13:42:03.950171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9645 13:42:03.953385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9646 13:42:03.959834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9647 13:42:03.963322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9648 13:42:03.969929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9649 13:42:03.973315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9650 13:42:03.979436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9651 13:42:03.983134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9652 13:42:03.989556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9653 13:42:03.993386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9654 13:42:03.999270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9655 13:42:04.003102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9656 13:42:04.009219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9657 13:42:04.012584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9658 13:42:04.019278 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9659 13:42:04.019832 INFO: [APUAPC] vio 0
9660 13:42:04.026576 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9661 13:42:04.030099 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9662 13:42:04.033219 INFO: [APUAPC] D0_APC_0: 0x400510
9663 13:42:04.036619 INFO: [APUAPC] D0_APC_1: 0x0
9664 13:42:04.040130 INFO: [APUAPC] D0_APC_2: 0x1540
9665 13:42:04.042935 INFO: [APUAPC] D0_APC_3: 0x0
9666 13:42:04.046640 INFO: [APUAPC] D1_APC_0: 0xffffffff
9667 13:42:04.049693 INFO: [APUAPC] D1_APC_1: 0xffffffff
9668 13:42:04.053132 INFO: [APUAPC] D1_APC_2: 0x3fffff
9669 13:42:04.056296 INFO: [APUAPC] D1_APC_3: 0x0
9670 13:42:04.059764 INFO: [APUAPC] D2_APC_0: 0xffffffff
9671 13:42:04.063021 INFO: [APUAPC] D2_APC_1: 0xffffffff
9672 13:42:04.066245 INFO: [APUAPC] D2_APC_2: 0x3fffff
9673 13:42:04.069628 INFO: [APUAPC] D2_APC_3: 0x0
9674 13:42:04.072706 INFO: [APUAPC] D3_APC_0: 0xffffffff
9675 13:42:04.076092 INFO: [APUAPC] D3_APC_1: 0xffffffff
9676 13:42:04.079420 INFO: [APUAPC] D3_APC_2: 0x3fffff
9677 13:42:04.082665 INFO: [APUAPC] D3_APC_3: 0x0
9678 13:42:04.085969 INFO: [APUAPC] D4_APC_0: 0xffffffff
9679 13:42:04.089674 INFO: [APUAPC] D4_APC_1: 0xffffffff
9680 13:42:04.092509 INFO: [APUAPC] D4_APC_2: 0x3fffff
9681 13:42:04.092971 INFO: [APUAPC] D4_APC_3: 0x0
9682 13:42:04.099519 INFO: [APUAPC] D5_APC_0: 0xffffffff
9683 13:42:04.102635 INFO: [APUAPC] D5_APC_1: 0xffffffff
9684 13:42:04.106575 INFO: [APUAPC] D5_APC_2: 0x3fffff
9685 13:42:04.107127 INFO: [APUAPC] D5_APC_3: 0x0
9686 13:42:04.109444 INFO: [APUAPC] D6_APC_0: 0xffffffff
9687 13:42:04.112440 INFO: [APUAPC] D6_APC_1: 0xffffffff
9688 13:42:04.116134 INFO: [APUAPC] D6_APC_2: 0x3fffff
9689 13:42:04.119161 INFO: [APUAPC] D6_APC_3: 0x0
9690 13:42:04.122556 INFO: [APUAPC] D7_APC_0: 0xffffffff
9691 13:42:04.125577 INFO: [APUAPC] D7_APC_1: 0xffffffff
9692 13:42:04.129399 INFO: [APUAPC] D7_APC_2: 0x3fffff
9693 13:42:04.132823 INFO: [APUAPC] D7_APC_3: 0x0
9694 13:42:04.135804 INFO: [APUAPC] D8_APC_0: 0xffffffff
9695 13:42:04.139108 INFO: [APUAPC] D8_APC_1: 0xffffffff
9696 13:42:04.142542 INFO: [APUAPC] D8_APC_2: 0x3fffff
9697 13:42:04.145480 INFO: [APUAPC] D8_APC_3: 0x0
9698 13:42:04.149461 INFO: [APUAPC] D9_APC_0: 0xffffffff
9699 13:42:04.152474 INFO: [APUAPC] D9_APC_1: 0xffffffff
9700 13:42:04.155994 INFO: [APUAPC] D9_APC_2: 0x3fffff
9701 13:42:04.158751 INFO: [APUAPC] D9_APC_3: 0x0
9702 13:42:04.162327 INFO: [APUAPC] D10_APC_0: 0xffffffff
9703 13:42:04.165764 INFO: [APUAPC] D10_APC_1: 0xffffffff
9704 13:42:04.168831 INFO: [APUAPC] D10_APC_2: 0x3fffff
9705 13:42:04.172651 INFO: [APUAPC] D10_APC_3: 0x0
9706 13:42:04.175717 INFO: [APUAPC] D11_APC_0: 0xffffffff
9707 13:42:04.178857 INFO: [APUAPC] D11_APC_1: 0xffffffff
9708 13:42:04.182057 INFO: [APUAPC] D11_APC_2: 0x3fffff
9709 13:42:04.185268 INFO: [APUAPC] D11_APC_3: 0x0
9710 13:42:04.188617 INFO: [APUAPC] D12_APC_0: 0xffffffff
9711 13:42:04.192421 INFO: [APUAPC] D12_APC_1: 0xffffffff
9712 13:42:04.195049 INFO: [APUAPC] D12_APC_2: 0x3fffff
9713 13:42:04.198486 INFO: [APUAPC] D12_APC_3: 0x0
9714 13:42:04.202217 INFO: [APUAPC] D13_APC_0: 0xffffffff
9715 13:42:04.204989 INFO: [APUAPC] D13_APC_1: 0xffffffff
9716 13:42:04.208652 INFO: [APUAPC] D13_APC_2: 0x3fffff
9717 13:42:04.211708 INFO: [APUAPC] D13_APC_3: 0x0
9718 13:42:04.215051 INFO: [APUAPC] D14_APC_0: 0xffffffff
9719 13:42:04.218766 INFO: [APUAPC] D14_APC_1: 0xffffffff
9720 13:42:04.221669 INFO: [APUAPC] D14_APC_2: 0x3fffff
9721 13:42:04.224993 INFO: [APUAPC] D14_APC_3: 0x0
9722 13:42:04.228608 INFO: [APUAPC] D15_APC_0: 0xffffffff
9723 13:42:04.231982 INFO: [APUAPC] D15_APC_1: 0xffffffff
9724 13:42:04.234730 INFO: [APUAPC] D15_APC_2: 0x3fffff
9725 13:42:04.238469 INFO: [APUAPC] D15_APC_3: 0x0
9726 13:42:04.241532 INFO: [APUAPC] APC_CON: 0x4
9727 13:42:04.244935 INFO: [NOCDAPC] D0_APC_0: 0x0
9728 13:42:04.248115 INFO: [NOCDAPC] D0_APC_1: 0x0
9729 13:42:04.251386 INFO: [NOCDAPC] D1_APC_0: 0x0
9730 13:42:04.255250 INFO: [NOCDAPC] D1_APC_1: 0xfff
9731 13:42:04.258212 INFO: [NOCDAPC] D2_APC_0: 0x0
9732 13:42:04.261865 INFO: [NOCDAPC] D2_APC_1: 0xfff
9733 13:42:04.262417 INFO: [NOCDAPC] D3_APC_0: 0x0
9734 13:42:04.264475 INFO: [NOCDAPC] D3_APC_1: 0xfff
9735 13:42:04.268194 INFO: [NOCDAPC] D4_APC_0: 0x0
9736 13:42:04.271853 INFO: [NOCDAPC] D4_APC_1: 0xfff
9737 13:42:04.274584 INFO: [NOCDAPC] D5_APC_0: 0x0
9738 13:42:04.278256 INFO: [NOCDAPC] D5_APC_1: 0xfff
9739 13:42:04.281192 INFO: [NOCDAPC] D6_APC_0: 0x0
9740 13:42:04.284464 INFO: [NOCDAPC] D6_APC_1: 0xfff
9741 13:42:04.287932 INFO: [NOCDAPC] D7_APC_0: 0x0
9742 13:42:04.291260 INFO: [NOCDAPC] D7_APC_1: 0xfff
9743 13:42:04.294823 INFO: [NOCDAPC] D8_APC_0: 0x0
9744 13:42:04.297680 INFO: [NOCDAPC] D8_APC_1: 0xfff
9745 13:42:04.298137 INFO: [NOCDAPC] D9_APC_0: 0x0
9746 13:42:04.301214 INFO: [NOCDAPC] D9_APC_1: 0xfff
9747 13:42:04.304431 INFO: [NOCDAPC] D10_APC_0: 0x0
9748 13:42:04.307705 INFO: [NOCDAPC] D10_APC_1: 0xfff
9749 13:42:04.310974 INFO: [NOCDAPC] D11_APC_0: 0x0
9750 13:42:04.314468 INFO: [NOCDAPC] D11_APC_1: 0xfff
9751 13:42:04.318033 INFO: [NOCDAPC] D12_APC_0: 0x0
9752 13:42:04.321001 INFO: [NOCDAPC] D12_APC_1: 0xfff
9753 13:42:04.323999 INFO: [NOCDAPC] D13_APC_0: 0x0
9754 13:42:04.327905 INFO: [NOCDAPC] D13_APC_1: 0xfff
9755 13:42:04.330640 INFO: [NOCDAPC] D14_APC_0: 0x0
9756 13:42:04.334386 INFO: [NOCDAPC] D14_APC_1: 0xfff
9757 13:42:04.337404 INFO: [NOCDAPC] D15_APC_0: 0x0
9758 13:42:04.340631 INFO: [NOCDAPC] D15_APC_1: 0xfff
9759 13:42:04.341081 INFO: [NOCDAPC] APC_CON: 0x4
9760 13:42:04.344110 INFO: [APUAPC] set_apusys_apc done
9761 13:42:04.348026 INFO: [DEVAPC] devapc_init done
9762 13:42:04.354051 INFO: GICv3 without legacy support detected.
9763 13:42:04.357376 INFO: ARM GICv3 driver initialized in EL3
9764 13:42:04.360812 INFO: Maximum SPI INTID supported: 639
9765 13:42:04.364330 INFO: BL31: Initializing runtime services
9766 13:42:04.370614 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9767 13:42:04.374095 INFO: SPM: enable CPC mode
9768 13:42:04.377495 INFO: mcdi ready for mcusys-off-idle and system suspend
9769 13:42:04.383811 INFO: BL31: Preparing for EL3 exit to normal world
9770 13:42:04.387166 INFO: Entry point address = 0x80000000
9771 13:42:04.387620 INFO: SPSR = 0x8
9772 13:42:04.394455
9773 13:42:04.395006
9774 13:42:04.395365
9775 13:42:04.397834 Starting depthcharge on Spherion...
9776 13:42:04.398284
9777 13:42:04.398640 Wipe memory regions:
9778 13:42:04.398972
9779 13:42:04.401467 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9780 13:42:04.401996 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9781 13:42:04.402450 Setting prompt string to ['asurada:']
9782 13:42:04.402871 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9783 13:42:04.403577 [0x00000040000000, 0x00000054600000)
9784 13:42:04.523221
9785 13:42:04.523776 [0x00000054660000, 0x00000080000000)
9786 13:42:04.783944
9787 13:42:04.784491 [0x000000821a7280, 0x000000ffe64000)
9788 13:42:05.528853
9789 13:42:05.529460 [0x00000100000000, 0x00000140000000)
9790 13:42:05.910431
9791 13:42:05.913101 Initializing XHCI USB controller at 0x11200000.
9792 13:42:06.951258
9793 13:42:06.954339 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9794 13:42:06.954798
9795 13:42:06.955154
9796 13:42:06.956017 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9798 13:42:07.057423 asurada: tftpboot 192.168.201.1 14063102/tftp-deploy-h62bn31c/kernel/image.itb 14063102/tftp-deploy-h62bn31c/kernel/cmdline
9799 13:42:07.059260 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9800 13:42:07.059704 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9801 13:42:07.064288 tftpboot 192.168.201.1 14063102/tftp-deploy-h62bn31c/kernel/image.itp-deploy-h62bn31c/kernel/cmdline
9802 13:42:07.064854
9803 13:42:07.065222 Waiting for link
9804 13:42:07.224517
9805 13:42:07.224840 R8152: Initializing
9806 13:42:07.225038
9807 13:42:07.227960 Version 9 (ocp_data = 6010)
9808 13:42:07.228288
9809 13:42:07.230629 R8152: Done initializing
9810 13:42:07.230878
9811 13:42:07.231067 Adding net device
9812 13:42:09.165602
9813 13:42:09.166162 done.
9814 13:42:09.166523
9815 13:42:09.166859 MAC: 00:e0:4c:68:03:bd
9816 13:42:09.167184
9817 13:42:09.168723 Sending DHCP discover... done.
9818 13:42:09.169340
9819 13:42:09.171765 Waiting for reply... done.
9820 13:42:09.172229
9821 13:42:09.175102 Sending DHCP request... done.
9822 13:42:09.175563
9823 13:42:09.179013 Waiting for reply... done.
9824 13:42:09.179472
9825 13:42:09.179836 My ip is 192.168.201.16
9826 13:42:09.180171
9827 13:42:09.182028 The DHCP server ip is 192.168.201.1
9828 13:42:09.182490
9829 13:42:09.189024 TFTP server IP predefined by user: 192.168.201.1
9830 13:42:09.189651
9831 13:42:09.195195 Bootfile predefined by user: 14063102/tftp-deploy-h62bn31c/kernel/image.itb
9832 13:42:09.195749
9833 13:42:09.198284 Sending tftp read request... done.
9834 13:42:09.198745
9835 13:42:09.205179 Waiting for the transfer...
9836 13:42:09.205776
9837 13:42:09.564740 00000000 ################################################################
9838 13:42:09.564888
9839 13:42:09.850842 00080000 ################################################################
9840 13:42:09.850985
9841 13:42:10.118340 00100000 ################################################################
9842 13:42:10.118485
9843 13:42:10.408497 00180000 ################################################################
9844 13:42:10.408641
9845 13:42:10.705742 00200000 ################################################################
9846 13:42:10.705888
9847 13:42:10.974506 00280000 ################################################################
9848 13:42:10.974647
9849 13:42:11.229740 00300000 ################################################################
9850 13:42:11.229889
9851 13:42:11.505212 00380000 ################################################################
9852 13:42:11.505366
9853 13:42:11.771421 00400000 ################################################################
9854 13:42:11.771569
9855 13:42:12.040340 00480000 ################################################################
9856 13:42:12.040487
9857 13:42:12.328580 00500000 ################################################################
9858 13:42:12.328729
9859 13:42:12.624455 00580000 ################################################################
9860 13:42:12.624604
9861 13:42:12.920330 00600000 ################################################################
9862 13:42:12.920472
9863 13:42:13.194037 00680000 ################################################################
9864 13:42:13.194177
9865 13:42:13.478616 00700000 ################################################################
9866 13:42:13.478762
9867 13:42:13.735806 00780000 ################################################################
9868 13:42:13.735951
9869 13:42:14.015016 00800000 ################################################################
9870 13:42:14.015154
9871 13:42:14.297704 00880000 ################################################################
9872 13:42:14.297876
9873 13:42:14.561894 00900000 ################################################################
9874 13:42:14.562039
9875 13:42:14.855231 00980000 ################################################################
9876 13:42:14.855378
9877 13:42:15.156899 00a00000 ################################################################
9878 13:42:15.157039
9879 13:42:15.450805 00a80000 ################################################################
9880 13:42:15.450950
9881 13:42:15.704444 00b00000 ################################################################
9882 13:42:15.704587
9883 13:42:15.994650 00b80000 ################################################################
9884 13:42:15.994789
9885 13:42:16.294428 00c00000 ################################################################
9886 13:42:16.294586
9887 13:42:16.594559 00c80000 ################################################################
9888 13:42:16.594703
9889 13:42:16.890481 00d00000 ################################################################
9890 13:42:16.890623
9891 13:42:17.184149 00d80000 ################################################################
9892 13:42:17.184292
9893 13:42:17.474951 00e00000 ################################################################
9894 13:42:17.475093
9895 13:42:17.761216 00e80000 ################################################################
9896 13:42:17.761397
9897 13:42:18.062290 00f00000 ################################################################
9898 13:42:18.062433
9899 13:42:18.363778 00f80000 ################################################################
9900 13:42:18.363916
9901 13:42:18.651293 01000000 ################################################################
9902 13:42:18.651435
9903 13:42:18.939818 01080000 ################################################################
9904 13:42:18.939963
9905 13:42:19.222792 01100000 ################################################################
9906 13:42:19.222936
9907 13:42:19.520636 01180000 ################################################################
9908 13:42:19.520784
9909 13:42:19.824004 01200000 ################################################################
9910 13:42:19.824150
9911 13:42:20.126504 01280000 ################################################################
9912 13:42:20.126686
9913 13:42:20.409398 01300000 ################################################################
9914 13:42:20.409539
9915 13:42:20.691375 01380000 ################################################################
9916 13:42:20.691518
9917 13:42:20.974686 01400000 ################################################################
9918 13:42:20.974827
9919 13:42:21.264807 01480000 ################################################################
9920 13:42:21.264960
9921 13:42:21.549930 01500000 ################################################################
9922 13:42:21.550076
9923 13:42:21.849302 01580000 ################################################################
9924 13:42:21.849461
9925 13:42:22.149990 01600000 ################################################################
9926 13:42:22.150133
9927 13:42:22.443176 01680000 ################################################################
9928 13:42:22.443322
9929 13:42:22.731449 01700000 ################################################################
9930 13:42:22.731597
9931 13:42:23.025197 01780000 ################################################################
9932 13:42:23.025370
9933 13:42:23.306656 01800000 ################################################################
9934 13:42:23.306797
9935 13:42:23.605166 01880000 ################################################################
9936 13:42:23.605318
9937 13:42:23.901437 01900000 ################################################################
9938 13:42:23.901576
9939 13:42:24.185161 01980000 ################################################################
9940 13:42:24.185293
9941 13:42:24.487172 01a00000 ################################################################
9942 13:42:24.487315
9943 13:42:24.791157 01a80000 ################################################################
9944 13:42:24.791304
9945 13:42:25.083976 01b00000 ################################################################
9946 13:42:25.084120
9947 13:42:25.364255 01b80000 ################################################################
9948 13:42:25.364403
9949 13:42:25.663654 01c00000 ################################################################
9950 13:42:25.663799
9951 13:42:25.965271 01c80000 ################################################################
9952 13:42:25.965420
9953 13:42:26.257489 01d00000 ################################################################
9954 13:42:26.257635
9955 13:42:26.535484 01d80000 ################################################################
9956 13:42:26.535663
9957 13:42:26.746032 01e00000 ############################################### done.
9958 13:42:26.746177
9959 13:42:26.749170 The bootfile was 31841294 bytes long.
9960 13:42:26.749259
9961 13:42:26.752917 Sending tftp read request... done.
9962 13:42:26.753012
9963 13:42:26.753083 Waiting for the transfer...
9964 13:42:26.753148
9965 13:42:26.756414 00000000 # done.
9966 13:42:26.756593
9967 13:42:26.763559 Command line loaded dynamically from TFTP file: 14063102/tftp-deploy-h62bn31c/kernel/cmdline
9968 13:42:26.763750
9969 13:42:26.786198 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9970 13:42:26.786475
9971 13:42:26.786630 Loading FIT.
9972 13:42:26.786766
9973 13:42:26.789176 Image ramdisk-1 has 18730698 bytes.
9974 13:42:26.789396
9975 13:42:26.792958 Image fdt-1 has 47258 bytes.
9976 13:42:26.793249
9977 13:42:26.795634 Image kernel-1 has 13061303 bytes.
9978 13:42:26.795880
9979 13:42:26.806095 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9980 13:42:26.806591
9981 13:42:26.823096 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9982 13:42:26.823709
9983 13:42:26.829647 Choosing best match conf-1 for compat google,spherion-rev3.
9984 13:42:26.832755
9985 13:42:26.836888 Connected to device vid:did:rid of 1ae0:0028:00
9986 13:42:26.844246
9987 13:42:26.847636 tpm_get_response: command 0x17b, return code 0x0
9988 13:42:26.848204
9989 13:42:26.850447 ec_init: CrosEC protocol v3 supported (256, 248)
9990 13:42:26.854552
9991 13:42:26.857892 tpm_cleanup: add release locality here.
9992 13:42:26.858357
9993 13:42:26.858719 Shutting down all USB controllers.
9994 13:42:26.860985
9995 13:42:26.861475 Removing current net device
9996 13:42:26.861843
9997 13:42:26.867789 Exiting depthcharge with code 4 at timestamp: 50709704
9998 13:42:26.868353
9999 13:42:26.871370 LZMA decompressing kernel-1 to 0x821a6718
10000 13:42:26.871834
10001 13:42:26.874277 LZMA decompressing kernel-1 to 0x40000000
10002 13:42:28.484553
10003 13:42:28.485107 jumping to kernel
10004 13:42:28.486981 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10005 13:42:28.487564 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10006 13:42:28.488080 Setting prompt string to ['Linux version [0-9]']
10007 13:42:28.488468 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10008 13:42:28.488857 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10009 13:42:28.536590
10010 13:42:28.539338 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10011 13:42:28.543425 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10012 13:42:28.543944 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10013 13:42:28.544341 Setting prompt string to []
10014 13:42:28.544756 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10015 13:42:28.545150 Using line separator: #'\n'#
10016 13:42:28.545797 No login prompt set.
10017 13:42:28.546185 Parsing kernel messages
10018 13:42:28.546510 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10019 13:42:28.547086 [login-action] Waiting for messages, (timeout 00:04:02)
10020 13:42:28.547460 Waiting using forced prompt support (timeout 00:02:01)
10021 13:42:28.562404 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10022 13:42:28.565796 [ 0.000000] random: crng init done
10023 13:42:28.572361 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10024 13:42:28.575932 [ 0.000000] efi: UEFI not found.
10025 13:42:28.582407 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10026 13:42:28.592093 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10027 13:42:28.599126 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10028 13:42:28.608659 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10029 13:42:28.615611 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10030 13:42:28.621919 [ 0.000000] printk: bootconsole [mtk8250] enabled
10031 13:42:28.628940 [ 0.000000] NUMA: No NUMA configuration found
10032 13:42:28.635240 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10033 13:42:28.641878 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10034 13:42:28.642437 [ 0.000000] Zone ranges:
10035 13:42:28.648463 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10036 13:42:28.651583 [ 0.000000] DMA32 empty
10037 13:42:28.657950 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10038 13:42:28.661834 [ 0.000000] Movable zone start for each node
10039 13:42:28.664923 [ 0.000000] Early memory node ranges
10040 13:42:28.671260 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10041 13:42:28.678002 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10042 13:42:28.684712 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10043 13:42:28.691186 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10044 13:42:28.697991 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10045 13:42:28.704747 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10046 13:42:28.734901 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10047 13:42:28.741627 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10048 13:42:28.748403 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10049 13:42:28.751582 [ 0.000000] psci: probing for conduit method from DT.
10050 13:42:28.758291 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10051 13:42:28.761471 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10052 13:42:28.768423 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10053 13:42:28.771786 [ 0.000000] psci: SMC Calling Convention v1.2
10054 13:42:28.777669 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10055 13:42:28.781523 [ 0.000000] Detected VIPT I-cache on CPU0
10056 13:42:28.788052 [ 0.000000] CPU features: detected: GIC system register CPU interface
10057 13:42:28.794773 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10058 13:42:28.801428 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10059 13:42:28.807749 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10060 13:42:28.815014 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10061 13:42:28.824046 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10062 13:42:28.827551 [ 0.000000] alternatives: applying boot alternatives
10063 13:42:28.834427 [ 0.000000] Fallback order for Node 0: 0
10064 13:42:28.840598 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10065 13:42:28.844352 [ 0.000000] Policy zone: Normal
10066 13:42:28.866884 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10067 13:42:28.877397 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10068 13:42:28.887005 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10069 13:42:28.893927 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10070 13:42:28.900639 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10071 13:42:28.907135 <6>[ 0.000000] software IO TLB: area num 8.
10072 13:42:28.963129 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10073 13:42:29.043182 <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved)
10074 13:42:29.049848 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10075 13:42:29.056627 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10076 13:42:29.060174 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10077 13:42:29.066767 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10078 13:42:29.073172 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10079 13:42:29.076214 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10080 13:42:29.085958 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10081 13:42:29.092909 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10082 13:42:29.099917 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10083 13:42:29.106252 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10084 13:42:29.110078 <6>[ 0.000000] GICv3: 608 SPIs implemented
10085 13:42:29.112981 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10086 13:42:29.119859 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10087 13:42:29.122601 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10088 13:42:29.129506 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10089 13:42:29.142926 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10090 13:42:29.152577 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10091 13:42:29.162613 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10092 13:42:29.169822 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10093 13:42:29.183519 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10094 13:42:29.189919 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10095 13:42:29.196121 <6>[ 0.009227] Console: colour dummy device 80x25
10096 13:42:29.206759 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10097 13:42:29.213128 <6>[ 0.024393] pid_max: default: 32768 minimum: 301
10098 13:42:29.216230 <6>[ 0.029265] LSM: Security Framework initializing
10099 13:42:29.222629 <6>[ 0.034179] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10100 13:42:29.232856 <6>[ 0.041786] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10101 13:42:29.239386 <6>[ 0.051013] cblist_init_generic: Setting adjustable number of callback queues.
10102 13:42:29.245773 <6>[ 0.058455] cblist_init_generic: Setting shift to 3 and lim to 1.
10103 13:42:29.255807 <6>[ 0.064795] cblist_init_generic: Setting adjustable number of callback queues.
10104 13:42:29.259153 <6>[ 0.072267] cblist_init_generic: Setting shift to 3 and lim to 1.
10105 13:42:29.265547 <6>[ 0.078668] rcu: Hierarchical SRCU implementation.
10106 13:42:29.271967 <6>[ 0.083683] rcu: Max phase no-delay instances is 1000.
10107 13:42:29.279321 <6>[ 0.090710] EFI services will not be available.
10108 13:42:29.281992 <6>[ 0.095663] smp: Bringing up secondary CPUs ...
10109 13:42:29.289917 <6>[ 0.100712] Detected VIPT I-cache on CPU1
10110 13:42:29.296561 <6>[ 0.100781] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10111 13:42:29.303058 <6>[ 0.100809] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10112 13:42:29.306397 <6>[ 0.101144] Detected VIPT I-cache on CPU2
10113 13:42:29.316275 <6>[ 0.101192] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10114 13:42:29.323016 <6>[ 0.101208] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10115 13:42:29.326527 <6>[ 0.101464] Detected VIPT I-cache on CPU3
10116 13:42:29.333395 <6>[ 0.101510] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10117 13:42:29.339709 <6>[ 0.101524] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10118 13:42:29.343218 <6>[ 0.101827] CPU features: detected: Spectre-v4
10119 13:42:29.349218 <6>[ 0.101833] CPU features: detected: Spectre-BHB
10120 13:42:29.352699 <6>[ 0.101838] Detected PIPT I-cache on CPU4
10121 13:42:29.359328 <6>[ 0.101898] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10122 13:42:29.366072 <6>[ 0.101914] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10123 13:42:29.372833 <6>[ 0.102206] Detected PIPT I-cache on CPU5
10124 13:42:29.379782 <6>[ 0.102271] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10125 13:42:29.386259 <6>[ 0.102288] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10126 13:42:29.389023 <6>[ 0.102569] Detected PIPT I-cache on CPU6
10127 13:42:29.396129 <6>[ 0.102632] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10128 13:42:29.402613 <6>[ 0.102648] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10129 13:42:29.409162 <6>[ 0.102947] Detected PIPT I-cache on CPU7
10130 13:42:29.416080 <6>[ 0.103015] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10131 13:42:29.422528 <6>[ 0.103031] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10132 13:42:29.425592 <6>[ 0.103079] smp: Brought up 1 node, 8 CPUs
10133 13:42:29.432709 <6>[ 0.244464] SMP: Total of 8 processors activated.
10134 13:42:29.435166 <6>[ 0.249415] CPU features: detected: 32-bit EL0 Support
10135 13:42:29.445612 <6>[ 0.254777] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10136 13:42:29.451873 <6>[ 0.263632] CPU features: detected: Common not Private translations
10137 13:42:29.458258 <6>[ 0.270108] CPU features: detected: CRC32 instructions
10138 13:42:29.461831 <6>[ 0.275460] CPU features: detected: RCpc load-acquire (LDAPR)
10139 13:42:29.468418 <6>[ 0.281420] CPU features: detected: LSE atomic instructions
10140 13:42:29.475294 <6>[ 0.287201] CPU features: detected: Privileged Access Never
10141 13:42:29.481255 <6>[ 0.292981] CPU features: detected: RAS Extension Support
10142 13:42:29.488085 <6>[ 0.298624] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10143 13:42:29.491838 <6>[ 0.305841] CPU: All CPU(s) started at EL2
10144 13:42:29.498140 <6>[ 0.310157] alternatives: applying system-wide alternatives
10145 13:42:29.507278 <6>[ 0.320147] devtmpfs: initialized
10146 13:42:29.518609 <6>[ 0.328455] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10147 13:42:29.528735 <6>[ 0.338419] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10148 13:42:29.535574 <6>[ 0.346684] pinctrl core: initialized pinctrl subsystem
10149 13:42:29.538835 <6>[ 0.353491] DMI not present or invalid.
10150 13:42:29.545024 <6>[ 0.357896] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10151 13:42:29.555363 <6>[ 0.364762] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10152 13:42:29.562052 <6>[ 0.372213] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10153 13:42:29.571507 <6>[ 0.380305] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10154 13:42:29.574885 <6>[ 0.388461] audit: initializing netlink subsys (disabled)
10155 13:42:29.584617 <5>[ 0.394160] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10156 13:42:29.590966 <6>[ 0.394901] thermal_sys: Registered thermal governor 'step_wise'
10157 13:42:29.598036 <6>[ 0.402128] thermal_sys: Registered thermal governor 'power_allocator'
10158 13:42:29.600937 <6>[ 0.408384] cpuidle: using governor menu
10159 13:42:29.607536 <6>[ 0.419343] NET: Registered PF_QIPCRTR protocol family
10160 13:42:29.614517 <6>[ 0.424827] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10161 13:42:29.621017 <6>[ 0.431926] ASID allocator initialised with 32768 entries
10162 13:42:29.624545 <6>[ 0.438543] Serial: AMBA PL011 UART driver
10163 13:42:29.635001 <4>[ 0.447692] Trying to register duplicate clock ID: 134
10164 13:42:29.695662 <6>[ 0.511569] KASLR enabled
10165 13:42:29.709897 <6>[ 0.519370] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10166 13:42:29.716336 <6>[ 0.526383] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10167 13:42:29.722559 <6>[ 0.532869] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10168 13:42:29.729233 <6>[ 0.539871] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10169 13:42:29.736187 <6>[ 0.546361] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10170 13:42:29.742583 <6>[ 0.553368] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10171 13:42:29.749596 <6>[ 0.559851] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10172 13:42:29.756023 <6>[ 0.566851] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10173 13:42:29.759021 <6>[ 0.574372] ACPI: Interpreter disabled.
10174 13:42:29.768059 <6>[ 0.580870] iommu: Default domain type: Translated
10175 13:42:29.774451 <6>[ 0.585982] iommu: DMA domain TLB invalidation policy: strict mode
10176 13:42:29.777666 <5>[ 0.592634] SCSI subsystem initialized
10177 13:42:29.783860 <6>[ 0.596792] usbcore: registered new interface driver usbfs
10178 13:42:29.790731 <6>[ 0.602523] usbcore: registered new interface driver hub
10179 13:42:29.793611 <6>[ 0.608073] usbcore: registered new device driver usb
10180 13:42:29.800939 <6>[ 0.614223] pps_core: LinuxPPS API ver. 1 registered
10181 13:42:29.810477 <6>[ 0.619417] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10182 13:42:29.814237 <6>[ 0.628768] PTP clock support registered
10183 13:42:29.817098 <6>[ 0.633009] EDAC MC: Ver: 3.0.0
10184 13:42:29.824752 <6>[ 0.638202] FPGA manager framework
10185 13:42:29.831827 <6>[ 0.641887] Advanced Linux Sound Architecture Driver Initialized.
10186 13:42:29.834804 <6>[ 0.648660] vgaarb: loaded
10187 13:42:29.841846 <6>[ 0.651820] clocksource: Switched to clocksource arch_sys_counter
10188 13:42:29.845072 <5>[ 0.658258] VFS: Disk quotas dquot_6.6.0
10189 13:42:29.851678 <6>[ 0.662444] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10190 13:42:29.855040 <6>[ 0.669631] pnp: PnP ACPI: disabled
10191 13:42:29.863440 <6>[ 0.676361] NET: Registered PF_INET protocol family
10192 13:42:29.869821 <6>[ 0.681736] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10193 13:42:29.882297 <6>[ 0.691752] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10194 13:42:29.891858 <6>[ 0.700536] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10195 13:42:29.898585 <6>[ 0.708497] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10196 13:42:29.905212 <6>[ 0.716902] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10197 13:42:29.915818 <6>[ 0.725563] TCP: Hash tables configured (established 32768 bind 32768)
10198 13:42:29.922393 <6>[ 0.732421] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10199 13:42:29.929225 <6>[ 0.739438] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10200 13:42:29.935303 <6>[ 0.746956] NET: Registered PF_UNIX/PF_LOCAL protocol family
10201 13:42:29.942428 <6>[ 0.753101] RPC: Registered named UNIX socket transport module.
10202 13:42:29.945656 <6>[ 0.759257] RPC: Registered udp transport module.
10203 13:42:29.952193 <6>[ 0.764190] RPC: Registered tcp transport module.
10204 13:42:29.958204 <6>[ 0.769123] RPC: Registered tcp NFSv4.1 backchannel transport module.
10205 13:42:29.961850 <6>[ 0.775785] PCI: CLS 0 bytes, default 64
10206 13:42:29.965179 <6>[ 0.780076] Unpacking initramfs...
10207 13:42:29.975568 <6>[ 0.784133] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10208 13:42:29.981259 <6>[ 0.792756] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10209 13:42:29.988775 <6>[ 0.801591] kvm [1]: IPA Size Limit: 40 bits
10210 13:42:29.992041 <6>[ 0.806113] kvm [1]: GICv3: no GICV resource entry
10211 13:42:29.998535 <6>[ 0.811133] kvm [1]: disabling GICv2 emulation
10212 13:42:30.005025 <6>[ 0.815821] kvm [1]: GIC system register CPU interface enabled
10213 13:42:30.008726 <6>[ 0.821973] kvm [1]: vgic interrupt IRQ18
10214 13:42:30.015224 <6>[ 0.826332] kvm [1]: VHE mode initialized successfully
10215 13:42:30.018648 <5>[ 0.832801] Initialise system trusted keyrings
10216 13:42:30.024887 <6>[ 0.837601] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10217 13:42:30.035042 <6>[ 0.847671] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10218 13:42:30.041022 <5>[ 0.854114] NFS: Registering the id_resolver key type
10219 13:42:30.044530 <5>[ 0.859428] Key type id_resolver registered
10220 13:42:30.051509 <5>[ 0.863843] Key type id_legacy registered
10221 13:42:30.057754 <6>[ 0.868120] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10222 13:42:30.064274 <6>[ 0.875039] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10223 13:42:30.070900 <6>[ 0.882775] 9p: Installing v9fs 9p2000 file system support
10224 13:42:30.107727 <5>[ 0.920597] Key type asymmetric registered
10225 13:42:30.111127 <5>[ 0.924926] Asymmetric key parser 'x509' registered
10226 13:42:30.120580 <6>[ 0.930070] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10227 13:42:30.124261 <6>[ 0.937679] io scheduler mq-deadline registered
10228 13:42:30.127598 <6>[ 0.942440] io scheduler kyber registered
10229 13:42:30.146976 <6>[ 0.960017] EINJ: ACPI disabled.
10230 13:42:30.180121 <4>[ 0.986761] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10231 13:42:30.190345 <4>[ 0.997469] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10232 13:42:30.205831 <6>[ 1.018976] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10233 13:42:30.214266 <6>[ 1.027067] printk: console [ttyS0] disabled
10234 13:42:30.242007 <6>[ 1.051697] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10235 13:42:30.249090 <6>[ 1.061177] printk: console [ttyS0] enabled
10236 13:42:30.251967 <6>[ 1.061177] printk: console [ttyS0] enabled
10237 13:42:30.258231 <6>[ 1.070075] printk: bootconsole [mtk8250] disabled
10238 13:42:30.262011 <6>[ 1.070075] printk: bootconsole [mtk8250] disabled
10239 13:42:30.268801 <6>[ 1.081364] SuperH (H)SCI(F) driver initialized
10240 13:42:30.271557 <6>[ 1.086681] msm_serial: driver initialized
10241 13:42:30.285913 <6>[ 1.095857] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10242 13:42:30.296495 <6>[ 1.104404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10243 13:42:30.302661 <6>[ 1.112945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10244 13:42:30.313137 <6>[ 1.121574] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10245 13:42:30.322399 <6>[ 1.130281] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10246 13:42:30.329343 <6>[ 1.138995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10247 13:42:30.338853 <6>[ 1.147536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10248 13:42:30.345986 <6>[ 1.156341] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10249 13:42:30.356043 <6>[ 1.164888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10250 13:42:30.367784 <6>[ 1.180902] loop: module loaded
10251 13:42:30.374700 <6>[ 1.186886] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10252 13:42:30.397132 <4>[ 1.210427] mtk-pmic-keys: Failed to locate of_node [id: -1]
10253 13:42:30.404439 <6>[ 1.217464] megasas: 07.719.03.00-rc1
10254 13:42:30.414524 <6>[ 1.227313] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10255 13:42:30.422105 <6>[ 1.235214] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10256 13:42:30.438987 <6>[ 1.251941] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10257 13:42:30.495359 <6>[ 1.301844] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10258 13:42:30.796479 <6>[ 1.609653] Freeing initrd memory: 18288K
10259 13:42:30.808077 <6>[ 1.621219] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10260 13:42:30.819159 <6>[ 1.632439] tun: Universal TUN/TAP device driver, 1.6
10261 13:42:30.822906 <6>[ 1.638546] thunder_xcv, ver 1.0
10262 13:42:30.825697 <6>[ 1.642051] thunder_bgx, ver 1.0
10263 13:42:30.829074 <6>[ 1.645545] nicpf, ver 1.0
10264 13:42:30.840225 <6>[ 1.649606] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10265 13:42:30.843053 <6>[ 1.657083] hns3: Copyright (c) 2017 Huawei Corporation.
10266 13:42:30.849865 <6>[ 1.662670] hclge is initializing
10267 13:42:30.853433 <6>[ 1.666251] e1000: Intel(R) PRO/1000 Network Driver
10268 13:42:30.859395 <6>[ 1.671380] e1000: Copyright (c) 1999-2006 Intel Corporation.
10269 13:42:30.862769 <6>[ 1.677393] e1000e: Intel(R) PRO/1000 Network Driver
10270 13:42:30.869448 <6>[ 1.682609] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10271 13:42:30.876295 <6>[ 1.688797] igb: Intel(R) Gigabit Ethernet Network Driver
10272 13:42:30.882980 <6>[ 1.694447] igb: Copyright (c) 2007-2014 Intel Corporation.
10273 13:42:30.889423 <6>[ 1.700282] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10274 13:42:30.895986 <6>[ 1.706800] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10275 13:42:30.899445 <6>[ 1.713277] sky2: driver version 1.30
10276 13:42:30.906042 <6>[ 1.718251] usbcore: registered new device driver r8152-cfgselector
10277 13:42:30.912731 <6>[ 1.724786] usbcore: registered new interface driver r8152
10278 13:42:30.918737 <6>[ 1.730603] VFIO - User Level meta-driver version: 0.3
10279 13:42:30.925973 <6>[ 1.738930] usbcore: registered new interface driver usb-storage
10280 13:42:30.932579 <6>[ 1.745391] usbcore: registered new device driver onboard-usb-hub
10281 13:42:30.941440 <6>[ 1.754615] mt6397-rtc mt6359-rtc: registered as rtc0
10282 13:42:30.951605 <6>[ 1.760078] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:42:31 UTC (1716903751)
10283 13:42:30.954685 <6>[ 1.769670] i2c_dev: i2c /dev entries driver
10284 13:42:30.971963 <6>[ 1.781778] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10285 13:42:30.978369 <4>[ 1.790526] cpu cpu0: supply cpu not found, using dummy regulator
10286 13:42:30.985167 <4>[ 1.796955] cpu cpu1: supply cpu not found, using dummy regulator
10287 13:42:30.991771 <4>[ 1.803362] cpu cpu2: supply cpu not found, using dummy regulator
10288 13:42:30.998100 <4>[ 1.809779] cpu cpu3: supply cpu not found, using dummy regulator
10289 13:42:31.004869 <4>[ 1.816172] cpu cpu4: supply cpu not found, using dummy regulator
10290 13:42:31.011702 <4>[ 1.822569] cpu cpu5: supply cpu not found, using dummy regulator
10291 13:42:31.018102 <4>[ 1.828969] cpu cpu6: supply cpu not found, using dummy regulator
10292 13:42:31.025080 <4>[ 1.835365] cpu cpu7: supply cpu not found, using dummy regulator
10293 13:42:31.043658 <6>[ 1.857010] cpu cpu0: EM: created perf domain
10294 13:42:31.047127 <6>[ 1.861913] cpu cpu4: EM: created perf domain
10295 13:42:31.054361 <6>[ 1.867504] sdhci: Secure Digital Host Controller Interface driver
10296 13:42:31.060890 <6>[ 1.873937] sdhci: Copyright(c) Pierre Ossman
10297 13:42:31.067762 <6>[ 1.878862] Synopsys Designware Multimedia Card Interface Driver
10298 13:42:31.074289 <6>[ 1.885478] sdhci-pltfm: SDHCI platform and OF driver helper
10299 13:42:31.077807 <6>[ 1.885606] mmc0: CQHCI version 5.10
10300 13:42:31.083926 <6>[ 1.895481] ledtrig-cpu: registered to indicate activity on CPUs
10301 13:42:31.090387 <6>[ 1.902453] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10302 13:42:31.097251 <6>[ 1.909486] usbcore: registered new interface driver usbhid
10303 13:42:31.100734 <6>[ 1.915307] usbhid: USB HID core driver
10304 13:42:31.107071 <6>[ 1.919493] spi_master spi0: will run message pump with realtime priority
10305 13:42:31.152628 <6>[ 1.958922] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10306 13:42:31.170580 <6>[ 1.973831] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10307 13:42:31.174820 <6>[ 1.987458] mmc0: Command Queue Engine enabled
10308 13:42:31.181054 <6>[ 1.992227] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10309 13:42:31.187754 <6>[ 1.999215] cros-ec-spi spi0.0: Chrome EC device registered
10310 13:42:31.191186 <6>[ 1.999661] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10311 13:42:31.201338 <6>[ 2.014505] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10312 13:42:31.209180 <6>[ 2.022006] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10313 13:42:31.215830 <6>[ 2.027909] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10314 13:42:31.222424 <6>[ 2.033937] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10315 13:42:31.231993 <6>[ 2.038457] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10316 13:42:31.239169 <6>[ 2.050856] NET: Registered PF_PACKET protocol family
10317 13:42:31.242060 <6>[ 2.056295] 9pnet: Installing 9P2000 support
10318 13:42:31.248476 <5>[ 2.060863] Key type dns_resolver registered
10319 13:42:31.251865 <6>[ 2.065857] registered taskstats version 1
10320 13:42:31.258673 <5>[ 2.070236] Loading compiled-in X.509 certificates
10321 13:42:31.286210 <4>[ 2.092899] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10322 13:42:31.296162 <4>[ 2.103690] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10323 13:42:31.312020 <6>[ 2.124980] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10324 13:42:31.318896 <6>[ 2.131900] xhci-mtk 11200000.usb: xHCI Host Controller
10325 13:42:31.325745 <6>[ 2.137416] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10326 13:42:31.335645 <6>[ 2.145266] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10327 13:42:31.341967 <6>[ 2.154698] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10328 13:42:31.349204 <6>[ 2.160855] xhci-mtk 11200000.usb: xHCI Host Controller
10329 13:42:31.355518 <6>[ 2.166347] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10330 13:42:31.361673 <6>[ 2.174008] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10331 13:42:31.368754 <6>[ 2.181817] hub 1-0:1.0: USB hub found
10332 13:42:31.371836 <6>[ 2.185854] hub 1-0:1.0: 1 port detected
10333 13:42:31.382061 <6>[ 2.190132] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10334 13:42:31.385387 <6>[ 2.198884] hub 2-0:1.0: USB hub found
10335 13:42:31.388826 <6>[ 2.202907] hub 2-0:1.0: 1 port detected
10336 13:42:31.395894 <6>[ 2.209469] mtk-msdc 11f70000.mmc: Got CD GPIO
10337 13:42:31.407750 <6>[ 2.217659] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10338 13:42:31.414365 <6>[ 2.225691] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10339 13:42:31.424479 <4>[ 2.233586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10340 13:42:31.434288 <6>[ 2.243107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10341 13:42:31.440801 <6>[ 2.251183] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10342 13:42:31.447424 <6>[ 2.259211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10343 13:42:31.457382 <6>[ 2.267125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10344 13:42:31.464082 <6>[ 2.274944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10345 13:42:31.473925 <6>[ 2.282761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10346 13:42:31.483726 <6>[ 2.293098] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10347 13:42:31.490398 <6>[ 2.301455] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10348 13:42:31.500470 <6>[ 2.309802] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10349 13:42:31.506944 <6>[ 2.318141] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10350 13:42:31.517342 <6>[ 2.326478] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10351 13:42:31.523864 <6>[ 2.334815] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10352 13:42:31.533433 <6>[ 2.343153] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10353 13:42:31.540462 <6>[ 2.351490] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10354 13:42:31.550264 <6>[ 2.359830] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10355 13:42:31.559559 <6>[ 2.368167] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10356 13:42:31.566593 <6>[ 2.376504] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10357 13:42:31.576121 <6>[ 2.384841] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10358 13:42:31.583120 <6>[ 2.393179] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10359 13:42:31.592575 <6>[ 2.401516] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10360 13:42:31.599550 <6>[ 2.409854] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10361 13:42:31.606021 <6>[ 2.418564] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10362 13:42:31.612739 <6>[ 2.425684] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10363 13:42:31.619067 <6>[ 2.432431] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10364 13:42:31.629227 <6>[ 2.439179] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10365 13:42:31.636170 <6>[ 2.446088] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10366 13:42:31.642572 <6>[ 2.452930] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10367 13:42:31.652303 <6>[ 2.462079] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10368 13:42:31.662348 <6>[ 2.471200] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10369 13:42:31.672091 <6>[ 2.480495] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10370 13:42:31.682098 <6>[ 2.489961] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10371 13:42:31.692252 <6>[ 2.499428] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10372 13:42:31.698387 <6>[ 2.508551] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10373 13:42:31.708638 <6>[ 2.518017] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10374 13:42:31.718645 <6>[ 2.527135] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10375 13:42:31.728362 <6>[ 2.536429] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10376 13:42:31.738530 <6>[ 2.546603] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10377 13:42:31.748020 <6>[ 2.557661] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10378 13:42:31.754343 <6>[ 2.566874] Trying to probe devices needed for running init ...
10379 13:42:31.778308 <6>[ 2.588368] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10380 13:42:31.807341 <6>[ 2.620605] hub 2-1:1.0: USB hub found
10381 13:42:31.810544 <6>[ 2.625114] hub 2-1:1.0: 3 ports detected
10382 13:42:31.819767 <6>[ 2.632917] hub 2-1:1.0: USB hub found
10383 13:42:31.823134 <6>[ 2.637318] hub 2-1:1.0: 3 ports detected
10384 13:42:31.929958 <6>[ 2.740002] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10385 13:42:32.083960 <6>[ 2.897134] hub 1-1:1.0: USB hub found
10386 13:42:32.087324 <6>[ 2.901609] hub 1-1:1.0: 4 ports detected
10387 13:42:32.096606 <6>[ 2.909516] hub 1-1:1.0: USB hub found
10388 13:42:32.099464 <6>[ 2.913901] hub 1-1:1.0: 4 ports detected
10389 13:42:32.162111 <6>[ 2.972216] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10390 13:42:32.270295 <6>[ 3.080369] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10391 13:42:32.302424 <4>[ 3.112429] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10392 13:42:32.312006 <4>[ 3.121580] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10393 13:42:32.351389 <6>[ 3.164768] r8152 2-1.3:1.0 eth0: v1.12.13
10394 13:42:32.425943 <6>[ 3.236101] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10395 13:42:32.558819 <6>[ 3.372086] hub 1-1.4:1.0: USB hub found
10396 13:42:32.562323 <6>[ 3.376754] hub 1-1.4:1.0: 2 ports detected
10397 13:42:32.571295 <6>[ 3.384870] hub 1-1.4:1.0: USB hub found
10398 13:42:32.574843 <6>[ 3.389543] hub 1-1.4:1.0: 2 ports detected
10399 13:42:32.869972 <6>[ 3.680132] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10400 13:42:33.061999 <6>[ 3.872132] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10401 13:42:33.980629 <6>[ 4.794124] r8152 2-1.3:1.0 eth0: carrier on
10402 13:42:36.966107 <5>[ 4.819932] Sending DHCP requests .., OK
10403 13:42:36.972697 <6>[ 7.784275] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10404 13:42:36.976208 <6>[ 7.792569] IP-Config: Complete:
10405 13:42:36.989088 <6>[ 7.796066] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10406 13:42:36.996013 <6>[ 7.806785] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10407 13:42:37.002296 <6>[ 7.815404] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10408 13:42:37.009419 <6>[ 7.815413] nameserver0=192.168.201.1
10409 13:42:37.012057 <6>[ 7.827569] clk: Disabling unused clocks
10410 13:42:37.015637 <6>[ 7.833050] ALSA device list:
10411 13:42:37.022811 <6>[ 7.836307] No soundcards found.
10412 13:42:37.029704 <6>[ 7.843751] Freeing unused kernel memory: 8512K
10413 13:42:37.033246 <6>[ 7.848708] Run /init as init process
10414 13:42:37.044083 Loading, please wait...
10415 13:42:37.069155 Starting systemd-udevd version 252.22-1~deb12u1
10416 13:42:37.302645 <6>[ 8.113242] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10417 13:42:37.309055 <6>[ 8.114542] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10418 13:42:37.315632 <3>[ 8.119221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10419 13:42:37.325927 <3>[ 8.119245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 13:42:37.332317 <3>[ 8.119256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 13:42:37.342267 <3>[ 8.119963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 13:42:37.349104 <3>[ 8.119976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 13:42:37.358734 <3>[ 8.119985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10424 13:42:37.366523 <3>[ 8.119997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 13:42:37.372719 <3>[ 8.120004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 13:42:37.382913 <3>[ 8.120059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 13:42:37.389925 <3>[ 8.120121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10428 13:42:37.399716 <3>[ 8.120129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10429 13:42:37.406408 <3>[ 8.120137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10430 13:42:37.416687 <3>[ 8.120217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10431 13:42:37.423077 <3>[ 8.120227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10432 13:42:37.432826 <3>[ 8.120234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10433 13:42:37.439213 <3>[ 8.120243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 13:42:37.446076 <3>[ 8.120250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10435 13:42:37.456007 <3>[ 8.120294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10436 13:42:37.462786 <6>[ 8.132861] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10437 13:42:37.469896 <6>[ 8.135446] remoteproc remoteproc0: scp is available
10438 13:42:37.472526 <6>[ 8.135496] remoteproc remoteproc0: powering up scp
10439 13:42:37.482769 <6>[ 8.135501] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10440 13:42:37.488722 <6>[ 8.135511] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10441 13:42:37.495848 <6>[ 8.136581] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10442 13:42:37.505620 <4>[ 8.158074] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10443 13:42:37.508827 <4>[ 8.158074] Fallback method does not support PEC.
10444 13:42:37.519037 <6>[ 8.160628] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10445 13:42:37.522426 <6>[ 8.162066] mc: Linux media interface: v0.10
10446 13:42:37.531969 <4>[ 8.177473] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10447 13:42:37.538607 <3>[ 8.184686] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10448 13:42:37.545563 <6>[ 8.185855] videodev: Linux video capture interface: v2.00
10449 13:42:37.551929 <4>[ 8.194273] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10450 13:42:37.561784 <3>[ 8.208491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10451 13:42:37.568360 <6>[ 8.261299] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10452 13:42:37.578188 <6>[ 8.261348] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10453 13:42:37.581444 <6>[ 8.261357] remoteproc remoteproc0: remote processor scp is now up
10454 13:42:37.591599 <6>[ 8.305445] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10455 13:42:37.601078 <6>[ 8.308656] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10456 13:42:37.604852 <6>[ 8.315408] pci_bus 0000:00: root bus resource [bus 00-ff]
10457 13:42:37.614227 <6>[ 8.329691] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10458 13:42:37.624253 <6>[ 8.330828] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10459 13:42:37.631143 <6>[ 8.332279] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10460 13:42:37.641033 <6>[ 8.334092] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10461 13:42:37.647681 <6>[ 8.337583] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10462 13:42:37.657415 <6>[ 8.337588] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10463 13:42:37.664094 <6>[ 8.337626] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10464 13:42:37.667415 <6>[ 8.387730] Bluetooth: Core ver 2.22
10465 13:42:37.673881 <6>[ 8.395715] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10466 13:42:37.680410 <6>[ 8.402090] NET: Registered PF_BLUETOOTH protocol family
10467 13:42:37.686985 <6>[ 8.403084] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10468 13:42:37.700557 <6>[ 8.404298] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10469 13:42:37.706841 <6>[ 8.404448] usbcore: registered new interface driver uvcvideo
10470 13:42:37.710431 <6>[ 8.409008] pci 0000:00:00.0: supports D1 D2
10471 13:42:37.716705 <6>[ 8.418985] Bluetooth: HCI device and connection manager initialized
10472 13:42:37.723280 <6>[ 8.419006] Bluetooth: HCI socket layer initialized
10473 13:42:37.729894 <6>[ 8.424723] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10474 13:42:37.733741 <6>[ 8.433754] Bluetooth: L2CAP socket layer initialized
10475 13:42:37.740183 <6>[ 8.434180] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10476 13:42:37.750215 <6>[ 8.442804] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10477 13:42:37.753151 <6>[ 8.451301] Bluetooth: SCO socket layer initialized
10478 13:42:37.759874 <6>[ 8.459625] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10479 13:42:37.766412 <6>[ 8.519722] usbcore: registered new interface driver btusb
10480 13:42:37.776134 <4>[ 8.520592] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10481 13:42:37.782966 <3>[ 8.520598] Bluetooth: hci0: Failed to load firmware file (-2)
10482 13:42:37.789469 <3>[ 8.520600] Bluetooth: hci0: Failed to set up firmware (-2)
10483 13:42:37.799530 <4>[ 8.520603] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10484 13:42:37.806358 <6>[ 8.525231] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10485 13:42:37.815676 <6>[ 8.625782] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10486 13:42:37.822584 <6>[ 8.633268] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10487 13:42:37.825754 <6>[ 8.640849] pci 0000:01:00.0: supports D1 D2
10488 13:42:37.832601 <6>[ 8.645368] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10489 13:42:37.853659 <6>[ 8.664007] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10490 13:42:37.860305 <6>[ 8.670931] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10491 13:42:37.866827 <6>[ 8.679016] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10492 13:42:37.877130 <6>[ 8.687011] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10493 13:42:37.883348 <6>[ 8.695013] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10494 13:42:37.893465 <6>[ 8.703012] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10495 13:42:37.896576 <6>[ 8.711011] pci 0000:00:00.0: PCI bridge to [bus 01]
10496 13:42:37.906372 <6>[ 8.716227] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10497 13:42:37.913081 <6>[ 8.724339] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10498 13:42:37.919849 <6>[ 8.731121] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10499 13:42:37.926477 <6>[ 8.737806] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10500 13:42:37.940703 <5>[ 8.751216] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10501 13:42:37.964853 <5>[ 8.775298] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10502 13:42:37.971364 <5>[ 8.782668] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10503 13:42:37.981090 <4>[ 8.791224] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10504 13:42:37.984429 <6>[ 8.800124] cfg80211: failed to load regulatory.db
10505 13:42:38.028198 <6>[ 8.838484] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10506 13:42:38.034349 <6>[ 8.846033] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10507 13:42:38.059111 <6>[ 8.872835] mt7921e 0000:01:00.0: ASIC revision: 79610010
10508 13:42:38.161239 <6>[ 8.971699] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10509 13:42:38.164385 <6>[ 8.971699]
10510 13:42:38.167754 Begin: Loading essential drivers ... done.
10511 13:42:38.171381 Begin: Running /scripts/init-premount ... done.
10512 13:42:38.178120 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10513 13:42:38.187624 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10514 13:42:38.191185 Device /sys/class/net/eth0 found
10515 13:42:38.191735 done.
10516 13:42:38.197513 Begin: Waiting up to 180 secs for any network device to become available ... done.
10517 13:42:38.222010 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10518 13:42:38.228423 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10519 13:42:38.235376 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10520 13:42:38.241566 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10521 13:42:38.248474 host : mt8192-asurada-spherion-r0-cbg-4
10522 13:42:38.254996 domain : lava-rack
10523 13:42:38.258269 rootserver: 192.168.201.1 rootpath:
10524 13:42:38.258725 filename :
10525 13:42:38.363679 done.
10526 13:42:38.371052 Begin: Running /scripts/nfs-bottom ... done.
10527 13:42:38.388462 Begin: Running /scripts/init-bottom ... done.
10528 13:42:38.431230 <6>[ 9.242108] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10529 13:42:39.729189 <6>[ 10.543198] NET: Registered PF_INET6 protocol family
10530 13:42:39.736939 <6>[ 10.550889] Segment Routing with IPv6
10531 13:42:39.739759 <6>[ 10.554846] In-situ OAM (IOAM) with IPv6
10532 13:42:39.908629 <30>[ 10.695796] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10533 13:42:39.914945 <30>[ 10.728958] systemd[1]: Detected architecture arm64.
10534 13:42:39.923937
10535 13:42:39.926782 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10536 13:42:39.927243
10537 13:42:39.951570 <30>[ 10.765608] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10538 13:42:41.015044 <30>[ 11.826298] systemd[1]: Queued start job for default target graphical.target.
10539 13:42:41.057781 <30>[ 11.869070] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10540 13:42:41.064951 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10541 13:42:41.086631 <30>[ 11.897933] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10542 13:42:41.096939 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10543 13:42:41.114608 <30>[ 11.925882] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10544 13:42:41.125141 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10545 13:42:41.143218 <30>[ 11.954330] systemd[1]: Created slice user.slice - User and Session Slice.
10546 13:42:41.149677 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10547 13:42:41.173340 <30>[ 11.980961] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10548 13:42:41.183352 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10549 13:42:41.200744 <30>[ 12.008356] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10550 13:42:41.207401 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10551 13:42:41.235802 <30>[ 12.036743] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10552 13:42:41.245906 <30>[ 12.056640] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10553 13:42:41.252273 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10554 13:42:41.269443 <30>[ 12.080483] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10555 13:42:41.279238 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10556 13:42:41.297702 <30>[ 12.108192] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10557 13:42:41.307392 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10558 13:42:41.322456 <30>[ 12.136650] systemd[1]: Reached target paths.target - Path Units.
10559 13:42:41.332149 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10560 13:42:41.350144 <30>[ 12.160568] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10561 13:42:41.356610 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10562 13:42:41.370197 <30>[ 12.184110] systemd[1]: Reached target slices.target - Slice Units.
10563 13:42:41.380128 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10564 13:42:41.394261 <30>[ 12.208589] systemd[1]: Reached target swap.target - Swaps.
10565 13:42:41.401062 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10566 13:42:41.421541 <30>[ 12.232595] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10567 13:42:41.431066 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10568 13:42:41.449262 <30>[ 12.260583] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10569 13:42:41.459468 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10570 13:42:41.479896 <30>[ 12.291273] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10571 13:42:41.489962 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10572 13:42:41.507247 <30>[ 12.317716] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10573 13:42:41.516550 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10574 13:42:41.533682 <30>[ 12.344779] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10575 13:42:41.540632 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10576 13:42:41.558766 <30>[ 12.369744] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10577 13:42:41.568731 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10578 13:42:41.587856 <30>[ 12.399009] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10579 13:42:41.597577 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10580 13:42:41.613841 <30>[ 12.424603] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10581 13:42:41.623257 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10582 13:42:41.665378 <30>[ 12.476262] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10583 13:42:41.671660 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10584 13:42:41.693612 <30>[ 12.504936] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10585 13:42:41.700511 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10586 13:42:41.725597 <30>[ 12.536999] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10587 13:42:41.732460 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10588 13:42:41.760477 <30>[ 12.564938] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10589 13:42:41.773954 <30>[ 12.584958] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10590 13:42:41.783542 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10591 13:42:41.805279 <30>[ 12.616386] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10592 13:42:41.811803 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10593 13:42:41.838517 <30>[ 12.649630] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10594 13:42:41.844789 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10595 13:42:41.869899 <30>[ 12.680648] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10596 13:42:41.876567 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10597 13:42:41.885859 <6>[ 12.694558] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10598 13:42:41.886422
10599 13:42:41.925715 <30>[ 12.736849] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10600 13:42:41.935479 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10601 13:42:41.959149 <30>[ 12.769977] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10602 13:42:41.965546 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10603 13:42:42.008498 <6>[ 12.823041] fuse: init (API version 7.37)
10604 13:42:42.025765 <30>[ 12.837020] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10605 13:42:42.032378 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10606 13:42:42.063139 <30>[ 12.874124] systemd[1]: Starting systemd-journald.service - Journal Service...
10607 13:42:42.069495 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10608 13:42:42.126086 <30>[ 12.937120] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10609 13:42:42.132438 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10610 13:42:42.161943 <30>[ 12.969578] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10611 13:42:42.168166 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10612 13:42:42.193037 <30>[ 13.004390] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10613 13:42:42.203221 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10614 13:42:42.228096 <3>[ 13.039130] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10615 13:42:42.258124 <30>[ 13.069037] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10616 13:42:42.268527 <3>[ 13.071894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 13:42:42.274955 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10618 13:42:42.296320 <30>[ 13.107335] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10619 13:42:42.309864 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepag<3>[ 13.118675] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10620 13:42:42.313333 es.mount[0m - Huge Pages File System.
10621 13:42:42.330045 <30>[ 13.140723] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10622 13:42:42.336618 <3>[ 13.147557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 13:42:42.346666 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10624 13:42:42.365700 <30>[ 13.176929] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10625 13:42:42.375486 <3>[ 13.178111] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10626 13:42:42.382484 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10627 13:42:42.402542 <30>[ 13.213551] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10628 13:42:42.412405 <3>[ 13.215547] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10629 13:42:42.419142 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10630 13:42:42.439153 <30>[ 13.249911] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10631 13:42:42.446076 <3>[ 13.253051] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 13:42:42.455964 <30>[ 13.264775] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10633 13:42:42.476507 <3>[ 13.287847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 13:42:42.486926 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10635 13:42:42.506143 <30>[ 13.317043] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10636 13:42:42.512360 <3>[ 13.318090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 13:42:42.522806 <30>[ 13.324721] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10638 13:42:42.529141 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10639 13:42:42.545638 <3>[ 13.356620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 13:42:42.555624 <30>[ 13.366808] systemd[1]: modprobe@drm.service: Deactivated successfully.
10641 13:42:42.563039 <30>[ 13.374648] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10642 13:42:42.572674 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10643 13:42:42.582471 <3>[ 13.393254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10644 13:42:42.592753 <30>[ 13.403705] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10645 13:42:42.602539 <30>[ 13.412498] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10646 13:42:42.609661 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10647 13:42:42.619741 <3>[ 13.429871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10648 13:42:42.633989 <30>[ 13.445544] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10649 13:42:42.641126 <30>[ 13.453139] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10650 13:42:42.654488 [[0;32m OK [0m] Finished [0;1;39mmodprobe@f<3>[ 13.463953] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10651 13:42:42.658032 use.service[0m - Load Kernel Module fuse.
10652 13:42:42.679009 <30>[ 13.489755] systemd[1]: modprobe@loop.service: Deactivated successfully.
10653 13:42:42.685735 <3>[ 13.494717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 13:42:42.695083 <30>[ 13.497557] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10655 13:42:42.701761 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10656 13:42:42.723091 <30>[ 13.533483] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10657 13:42:42.729631 <3>[ 13.540284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 13:42:42.746543 <4>[ 13.550366] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10659 13:42:42.753562 <3>[ 13.550369] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10660 13:42:42.764018 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10661 13:42:42.789987 <30>[ 13.597156] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10662 13:42:42.796730 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10663 13:42:42.817554 <30>[ 13.628693] systemd[1]: Started systemd-journald.service - Journal Service.
10664 13:42:42.824143 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10665 13:42:42.849846 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10666 13:42:42.870294 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10667 13:42:42.895762 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10668 13:42:42.957362 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10669 13:42:42.981465 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10670 13:42:43.004366 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10671 13:42:43.025161 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10672 13:42:43.050669 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10673 13:42:43.077951 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10674 13:42:43.084512 <46>[ 13.896822] systemd-journald[308]: Received client request to flush runtime journal.
10675 13:42:43.146278 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10676 13:42:43.165754 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10677 13:42:43.182088 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10678 13:42:43.201490 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10679 13:42:44.190902 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10680 13:42:44.236697 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10681 13:42:44.505279 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10682 13:42:44.598206 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10683 13:42:44.617650 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10684 13:42:44.636873 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10685 13:42:44.702135 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10686 13:42:44.725837 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10687 13:42:44.924022 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10688 13:42:44.978978 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10689 13:42:45.011274 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10690 13:42:45.275012 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10691 13:42:45.353919 <6>[ 16.168791] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10692 13:42:45.364183 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10693 13:42:45.387032 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10694 13:42:45.493451 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10695 13:42:45.514753 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10696 13:42:45.569266 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10697 13:42:45.584655 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10698 13:42:45.628281 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10699 13:42:45.650940 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10700 13:42:45.671310 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10701 13:42:45.694813 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10702 13:42:45.717675 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10703 13:42:45.741843 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10704 13:42:45.765155 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10705 13:42:45.781038 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10706 13:42:45.805177 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10707 13:42:45.823877 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10708 13:42:45.841027 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10709 13:42:45.884123 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10710 13:42:45.905125 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10711 13:42:45.920630 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10712 13:42:45.939254 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10713 13:42:45.956262 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10714 13:42:45.972900 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10715 13:42:46.030552 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10716 13:42:46.065438 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10717 13:42:46.159121 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10718 13:42:46.186303 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10719 13:42:46.259405 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10720 13:42:46.279592 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10721 13:42:46.302414 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10722 13:42:46.332426 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10723 13:42:46.369419 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10724 13:42:46.417648 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10725 13:42:46.436753 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10726 13:42:46.453735 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10727 13:42:46.552654 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10728 13:42:46.573433 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10729 13:42:46.598801 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10730 13:42:46.651807 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10731 13:42:46.702721 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10732 13:42:46.783667
10733 13:42:46.787235 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10734 13:42:46.787742
10735 13:42:46.789979 debian-bookworm-arm64 login: root (automatic login)
10736 13:42:46.790437
10737 13:42:47.066566 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
10738 13:42:47.067107
10739 13:42:47.073107 The programs included with the Debian GNU/Linux system are free software;
10740 13:42:47.079796 the exact distribution terms for each program are described in the
10741 13:42:47.083608 individual files in /usr/share/doc/*/copyright.
10742 13:42:47.084068
10743 13:42:47.090055 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10744 13:42:47.093030 permitted by applicable law.
10745 13:42:47.179242 Matched prompt #10: / #
10747 13:42:47.179540 Setting prompt string to ['/ #']
10748 13:42:47.179642 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10750 13:42:47.179848 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10751 13:42:47.179944 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10752 13:42:47.180019 Setting prompt string to ['/ #']
10753 13:42:47.180083 Forcing a shell prompt, looking for ['/ #']
10755 13:42:47.230408 / #
10756 13:42:47.230867 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10757 13:42:47.231161 Waiting using forced prompt support (timeout 00:02:30)
10758 13:42:47.236431
10759 13:42:47.237281 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10760 13:42:47.237925 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10762 13:42:47.339356 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i'
10763 13:42:47.345871 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063102/extract-nfsrootfs-e24ear_i'
10765 13:42:47.447592 / # export NFS_SERVER_IP='192.168.201.1'
10766 13:42:47.453702 export NFS_SERVER_IP='192.168.201.1'
10767 13:42:47.454520 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10768 13:42:47.454920 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10769 13:42:47.455305 end: 2 depthcharge-action (duration 00:01:17) [common]
10770 13:42:47.455702 start: 3 lava-test-retry (timeout 00:30:00) [common]
10771 13:42:47.456092 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10772 13:42:47.456416 Using namespace: common
10774 13:42:47.557518 / # #
10775 13:42:47.558171 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10776 13:42:47.563721 #
10777 13:42:47.564625 Using /lava-14063102
10779 13:42:47.665880 / # export SHELL=/bin/sh
10780 13:42:47.672001 export SHELL=/bin/sh
10782 13:42:47.773621 / # . /lava-14063102/environment
10783 13:42:47.779949 . /lava-14063102/environment
10785 13:42:47.887273 / # /lava-14063102/bin/lava-test-runner /lava-14063102/0
10786 13:42:47.887921 Test shell timeout: 10s (minimum of the action and connection timeout)
10787 13:42:47.893544 /lava-14063102/bin/lava-test-runner /lava-14063102/0
10788 13:42:48.123607 + export TESTRUN_ID=0_lc-compliance
10789 13:42:48.130168 + cd /lava-14063102/0/tests/0_lc-compliance
10790 13:42:48.130644 + cat uuid
10791 13:42:48.138286 + UUID=14063102_1.6.2.3.1
10792 13:42:48.138862 + set +x
10793 13:42:48.144927 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14063102_1.6.2.3.1>
10794 13:42:48.145746 Received signal: <STARTRUN> 0_lc-compliance 14063102_1.6.2.3.1
10795 13:42:48.146166 Starting test lava.0_lc-compliance (14063102_1.6.2.3.1)
10796 13:42:48.146611 Skipping test definition patterns.
10797 13:42:48.148230 + /usr/bin/lc-compliance-parser.sh
10798 13:42:49.787143 [0:00:20.479621693] [410] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
10799 13:42:49.789905 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10800 13:42:49.806690 [0:00:20.499225154] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10801 13:42:49.863099 [0:00:20.556343847] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10802 13:42:49.872594 [==========] Running 120 tests from 1 test suite.
10803 13:42:49.918042 [0:00:20.611046462] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10804 13:42:49.944308 [----------] Global test environment set-up.
10805 13:42:49.976425 [0:00:20.667907539] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10806 13:42:50.009403 [----------] 120 tests from CaptureTests/SingleStream
10807 13:42:50.082033 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10808 13:42:50.138944 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10809 13:42:50.139721 Received signal: <TESTSET> START CaptureTests/SingleStream
10810 13:42:50.140129 Starting test_set CaptureTests/SingleStream
10811 13:42:50.142018 Camera needs 4 requests, can't test only 1
10812 13:42:50.210438 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10813 13:42:50.275976
10814 13:42:50.354612 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (56 ms)
10815 13:42:50.404035 [0:00:21.097168001] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10816 13:42:50.451212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10817 13:42:50.451976 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10819 13:42:50.466028 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10820 13:42:50.511245 Camera needs 4 requests, can't test only 2
10821 13:42:50.581949 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10822 13:42:50.649482
10823 13:42:50.725953 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (55 ms)
10824 13:42:50.819021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10825 13:42:50.819844 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10827 13:42:50.834232 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10828 13:42:50.889414 Camera needs 4 requests, can't test only 3
10829 13:42:50.968515 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10830 13:42:51.047063
10831 13:42:51.098431 [0:00:21.791774770] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10832 13:42:51.133375 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (57 ms)
10833 13:42:51.224145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10834 13:42:51.224991 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10836 13:42:51.241145 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10837 13:42:51.302635 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (429 ms)
10838 13:42:51.381515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
10839 13:42:51.381882 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
10841 13:42:51.395445 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
10842 13:42:51.443571 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (693 ms)
10843 13:42:51.533695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
10844 13:42:51.534472 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
10846 13:42:51.551061 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
10847 13:42:52.653510 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1563 ms)
10848 13:42:52.663602 [0:00:23.355271385] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10849 13:42:52.755820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
10850 13:42:52.756639 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
10852 13:42:52.774202 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
10853 13:42:54.469010 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1815 ms)
10854 13:42:54.479134 [0:00:25.171254616] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10855 13:42:54.566985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
10856 13:42:54.567756 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
10858 13:42:54.582462 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
10859 13:42:57.503768 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (3034 ms)
10860 13:42:57.513155 [0:00:28.207593770] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10861 13:42:57.596777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
10862 13:42:57.597510 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
10864 13:42:57.614608 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
10865 13:43:01.700950 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
10866 13:43:01.711183 [0:00:32.404295694] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10867 13:43:01.797385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
10868 13:43:01.798518 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
10870 13:43:01.811247 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
10871 13:43:07.151121 <6>[ 37.972050] vpu: disabling
10872 13:43:07.154770 <6>[ 37.975150] vproc2: disabling
10873 13:43:07.158151 <6>[ 37.978468] vproc1: disabling
10874 13:43:07.160915 <6>[ 37.981792] vaud18: disabling
10875 13:43:07.167616 <6>[ 37.985301] vsram_others: disabling
10876 13:43:07.171245 <6>[ 37.989283] va09: disabling
10877 13:43:07.174928 <6>[ 37.992450] vsram_md: disabling
10878 13:43:07.177403 <6>[ 37.996010] Vgpu: disabling
10879 13:43:08.277365 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6577 ms)
10880 13:43:08.287288 [0:00:38.981545386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10881 13:43:08.341010 [0:00:39.035870694] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10882 13:43:08.372303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
10883 13:43:08.372625 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
10885 13:43:08.385198 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
10886 13:43:08.394834 [0:00:39.087916079] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10887 13:43:08.429915 Camera needs 4 requests, can't test only 1
10888 13:43:08.446905 [0:00:39.142253386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10889 13:43:08.502286 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10890 13:43:08.571497
10891 13:43:08.644487 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
10892 13:43:08.727369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
10893 13:43:08.728161 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
10895 13:43:08.743652 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
10896 13:43:08.793883 Camera needs 4 requests, can't test only 2
10897 13:43:08.864747 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10898 13:43:08.933537
10899 13:43:09.002476 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (52 ms)
10900 13:43:09.086242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
10901 13:43:09.086662 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
10903 13:43:09.100630 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
10904 13:43:09.141482 [0:00:39.836749156] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10905 13:43:09.153075 Camera needs 4 requests, can't test only 3
10906 13:43:09.226559 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10907 13:43:09.301623
10908 13:43:09.383628 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
10909 13:43:09.478726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
10910 13:43:09.479534 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
10912 13:43:09.495392 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
10913 13:43:09.541962 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (694 ms)
10914 13:43:09.622578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
10915 13:43:09.623314 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
10917 13:43:09.637889 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
10918 13:43:10.069675 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (935 ms)
10919 13:43:10.082909 [0:00:40.773347386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10920 13:43:10.165268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
10921 13:43:10.166181 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
10923 13:43:10.179365 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
10924 13:43:11.324160 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
10925 13:43:11.337439 [0:00:42.028500617] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10926 13:43:11.413618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
10927 13:43:11.414376 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
10929 13:43:11.428629 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
10930 13:43:13.140649 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1816 ms)
10931 13:43:13.153572 [0:00:43.845496463] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10932 13:43:13.218146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
10933 13:43:13.218478 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
10935 13:43:13.232434 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
10936 13:43:15.897781 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2757 ms)
10937 13:43:15.910815 [0:00:46.602789156] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10938 13:43:15.984881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
10939 13:43:15.985211 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
10941 13:43:16.000056 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
10942 13:43:20.093759 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4196 ms)
10943 13:43:20.106555 [0:00:50.799139849] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10944 13:43:20.183655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
10945 13:43:20.183941 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
10947 13:43:20.195178 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
10948 13:43:26.669653 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6576 ms)
10949 13:43:26.682630 [0:00:57.375789157] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10950 13:43:26.733756 [0:00:57.431192080] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10951 13:43:26.762127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
10952 13:43:26.762854 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
10954 13:43:26.776616 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
10955 13:43:26.791023 [0:00:57.488104003] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10956 13:43:26.825401 Camera needs 4 requests, can't test only 1
10957 13:43:26.847615 [0:00:57.544667541] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10958 13:43:26.900751 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10959 13:43:26.960552
10960 13:43:27.032316 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (55 ms)
10961 13:43:27.111307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
10962 13:43:27.112040 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
10964 13:43:27.127456 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
10965 13:43:27.176034 Camera needs 4 requests, can't test only 2
10966 13:43:27.248858 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10967 13:43:27.320086
10968 13:43:27.398094 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)
10969 13:43:27.486125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
10970 13:43:27.486903 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
10972 13:43:27.502301 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
10973 13:43:27.541722 [0:00:58.239433926] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10974 13:43:27.555349 Camera needs 4 requests, can't test only 3
10975 13:43:27.625403 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10976 13:43:27.697356
10977 13:43:27.780090 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
10978 13:43:27.864195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
10979 13:43:27.864505 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
10981 13:43:27.877923 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
10982 13:43:27.924998 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (695 ms)
10983 13:43:27.991922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
10984 13:43:27.992253 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
10986 13:43:28.004936 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
10987 13:43:28.470843 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (936 ms)
10988 13:43:28.483913 [0:00:59.177393003] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10989 13:43:28.563524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
10990 13:43:28.564216 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
10992 13:43:28.578181 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
10993 13:43:29.726429 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
10994 13:43:29.739717 [0:01:00.433473926] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
10995 13:43:29.823176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
10996 13:43:29.824012 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
10998 13:43:29.840631 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
10999 13:43:31.542873 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1816 ms)
11000 13:43:31.555813 [0:01:02.249627541] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11001 13:43:31.629046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11002 13:43:31.629880 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11004 13:43:31.643787 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11005 13:43:34.298787 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2756 ms)
11006 13:43:34.311936 [0:01:05.006419849] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11007 13:43:34.377217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11008 13:43:34.377705 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11010 13:43:34.389094 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11011 13:43:38.495454 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11012 13:43:38.508167 [0:01:09.203100696] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11013 13:43:38.589367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11014 13:43:38.589992 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11016 13:43:38.605136 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11017 13:43:45.071719 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6576 ms)
11018 13:43:45.084419 [0:01:15.779983542] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11019 13:43:45.135968 [0:01:15.835537158] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11020 13:43:45.167557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11021 13:43:45.168255 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11023 13:43:45.182809 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11024 13:43:45.192700 [0:01:15.891194850] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11025 13:43:45.230667 Camera needs 4 requests, can't test only 1
11026 13:43:45.246482 [0:01:15.946050619] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11027 13:43:45.301100 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11028 13:43:45.359141
11029 13:43:45.419479 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (55 ms)
11030 13:43:45.496928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11031 13:43:45.497304 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11033 13:43:45.512754 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11034 13:43:45.557736 Camera needs 4 requests, can't test only 2
11035 13:43:45.624222 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11036 13:43:45.689757
11037 13:43:45.765273 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11038 13:43:45.839659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11039 13:43:45.840657 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11041 13:43:45.853820 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11042 13:43:45.901771 Camera needs 4 requests, can't test only 3
11043 13:43:45.940300 [0:01:16.640259081] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11044 13:43:45.967031 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11045 13:43:46.018422
11046 13:43:46.078622 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11047 13:43:46.156149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11048 13:43:46.156883 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11050 13:43:46.171568 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11051 13:43:46.222646 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11052 13:43:46.311055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11053 13:43:46.311877 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11055 13:43:46.325863 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11056 13:43:46.838003 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (905 ms)
11057 13:43:46.847525 [0:01:17.546502312] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11058 13:43:46.926007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11059 13:43:46.926768 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11061 13:43:46.942100 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11062 13:43:48.093335 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1255 ms)
11063 13:43:48.106531 [0:01:18.802539850] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11064 13:43:48.187137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11065 13:43:48.187944 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11067 13:43:48.204091 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11068 13:43:49.909158 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1816 ms)
11069 13:43:49.922397 [0:01:20.618726235] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11070 13:43:49.996178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11071 13:43:49.996474 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11073 13:43:50.009254 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11074 13:43:52.635713 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2726 ms)
11075 13:43:52.649055 [0:01:23.345552312] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 13:43:52.722327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11077 13:43:52.722761 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11079 13:43:52.736154 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11080 13:43:56.832282 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4196 ms)
11081 13:43:56.845482 [0:01:27.542258851] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11082 13:43:56.930959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11083 13:43:56.931741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11085 13:43:56.948145 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11086 13:44:03.408350 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6577 ms)
11087 13:44:03.421913 [0:01:34.119380543] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11088 13:44:03.473411 [0:01:34.174965543] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11089 13:44:03.504739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11090 13:44:03.505602 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11092 13:44:03.519163 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11093 13:44:03.529125 [0:01:34.227571082] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11094 13:44:03.562977 Camera needs 4 requests, can't test only 1
11095 13:44:03.582248 [0:01:34.283344774] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11096 13:44:03.640211 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11097 13:44:03.708793
11098 13:44:03.780575 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (55 ms)
11099 13:44:03.866600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11100 13:44:03.867394 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11102 13:44:03.882787 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11103 13:44:03.938661 Camera needs 4 requests, can't test only 2
11104 13:44:04.012550 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11105 13:44:04.077905
11106 13:44:04.152533 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11107 13:44:04.234430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11108 13:44:04.235278 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11110 13:44:04.248932 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11111 13:44:04.301923 Camera needs 4 requests, can't test only 3
11112 13:44:04.372011 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11113 13:44:04.448349
11114 13:44:04.531492 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11115 13:44:04.627997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11116 13:44:04.628813 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11118 13:44:04.645500 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11119 13:44:05.654311 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2080 ms)
11120 13:44:05.667108 [0:01:36.364719313] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 13:44:05.748559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11122 13:44:05.749426 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11124 13:44:05.764805 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11125 13:44:08.456703 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2802 ms)
11126 13:44:08.469434 [0:01:39.169012313] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 13:44:08.545795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11128 13:44:08.546715 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11130 13:44:08.561690 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11131 13:44:12.219178 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3763 ms)
11132 13:44:12.232419 [0:01:42.932701467] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11133 13:44:12.312440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11134 13:44:12.313194 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11136 13:44:12.327847 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11137 13:44:17.661491 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5442 ms)
11138 13:44:17.674792 [0:01:48.375588467] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11139 13:44:17.753423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11140 13:44:17.754344 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11142 13:44:17.769806 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11143 13:44:25.865235 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8204 ms)
11144 13:44:25.878557 [0:01:56.579830545] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11145 13:44:25.964572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11146 13:44:25.965331 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11148 13:44:25.980071 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11149 13:44:38.448231 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12583 ms)
11150 13:44:38.461078 [0:02:09.163964161] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11151 13:44:38.530733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11152 13:44:38.531092 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11154 13:44:38.544855 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11155 13:44:58.170058 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19724 ms)
11156 13:44:58.183127 [0:02:28.889090701] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11157 13:44:58.236525 [0:02:28.944210854] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11158 13:44:58.254600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11159 13:44:58.255201 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11161 13:44:58.267740 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11162 13:44:58.293036 [0:02:29.001135393] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11163 13:44:58.322867 Camera needs 4 requests, can't test only 1
11164 13:44:58.348541 [0:02:29.056762701] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 13:44:58.393206 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11166 13:44:58.467879
11167 13:44:58.547148 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (55 ms)
11168 13:44:58.635381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11169 13:44:58.636191 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11171 13:44:58.648521 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11172 13:44:58.694375 Camera needs 4 requests, can't test only 2
11173 13:44:58.768226 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11174 13:44:58.845528
11175 13:44:58.927682 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11176 13:44:59.013226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11177 13:44:59.014013 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11179 13:44:59.027541 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11180 13:44:59.076967 Camera needs 4 requests, can't test only 3
11181 13:44:59.136617 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11182 13:44:59.193865
11183 13:44:59.270464 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (58 ms)
11184 13:44:59.353462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11185 13:44:59.354323 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11187 13:44:59.367603 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11188 13:45:00.424547 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2080 ms)
11189 13:45:00.434152 [0:02:31.138384239] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11190 13:45:00.523694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11191 13:45:00.524480 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11193 13:45:00.535231 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11194 13:45:03.137403 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2713 ms)
11195 13:45:03.147802 [0:02:33.853233855] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11196 13:45:03.227365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11197 13:45:03.227689 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11199 13:45:03.237849 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11200 13:45:06.899373 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3761 ms)
11201 13:45:06.908828 [0:02:37.615045316] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11202 13:45:06.988173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11203 13:45:06.989054 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11205 13:45:06.999483 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11206 13:45:12.339751 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5440 ms)
11207 13:45:12.349649 [0:02:43.056321009] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 13:45:12.431326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11209 13:45:12.432134 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11211 13:45:12.443370 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11212 13:45:20.542986 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8204 ms)
11213 13:45:20.552717 [0:02:51.260572702] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 13:45:20.636699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11215 13:45:20.637532 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11217 13:45:20.650834 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11218 13:45:33.124795 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12583 ms)
11219 13:45:33.134601 [0:03:03.843826241] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11220 13:45:33.234153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11221 13:45:33.234895 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11223 13:45:33.247467 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11224 13:45:52.846514 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19723 ms)
11225 13:45:52.855973 [0:03:23.567928011] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 13:45:52.908752 [0:03:23.623140704] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11227 13:45:52.942619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11228 13:45:52.943414 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11230 13:45:52.955009 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11231 13:45:52.968789 [0:03:23.679614011] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 13:45:53.005527 Camera needs 4 requests, can't test only 1
11233 13:45:53.020751 [0:03:23.735254165] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 13:45:53.080852 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11235 13:45:53.149057
11236 13:45:53.230429 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11237 13:45:53.318695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11238 13:45:53.319446 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11240 13:45:53.333336 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11241 13:45:53.381850 Camera needs 4 requests, can't test only 2
11242 13:45:53.453004 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11243 13:45:53.519505
11244 13:45:53.601743 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)
11245 13:45:53.694778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11246 13:45:53.695652 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11248 13:45:53.709139 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11249 13:45:53.763249 Camera needs 4 requests, can't test only 3
11250 13:45:53.838034 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11251 13:45:53.904080
11252 13:45:53.974011 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11253 13:45:54.046890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11254 13:45:54.047211 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11256 13:45:54.057687 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11257 13:45:55.097280 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2081 ms)
11258 13:45:55.107075 [0:03:25.817919858] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11259 13:45:55.173590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11260 13:45:55.174320 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11262 13:45:55.185666 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11263 13:45:57.810807 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11264 13:45:57.820026 [0:03:28.532301550] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 13:45:57.902243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11266 13:45:57.902904 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11268 13:45:57.913625 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11269 13:46:01.572540 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3762 ms)
11270 13:46:01.582324 [0:03:32.294972627] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11271 13:46:01.666161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11272 13:46:01.666934 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11274 13:46:01.679588 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11275 13:46:07.015392 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5443 ms)
11276 13:46:07.025064 [0:03:37.738171243] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 13:46:07.110105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11278 13:46:07.111090 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11280 13:46:07.122921 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11281 13:46:15.218405 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8204 ms)
11282 13:46:15.228409 [0:03:45.942472782] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 13:46:15.314362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11284 13:46:15.315211 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11286 13:46:15.328203 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11287 13:46:27.800497 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12583 ms)
11288 13:46:27.810337 [0:03:58.526081937] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 13:46:27.886911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11290 13:46:27.887555 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11292 13:46:27.899013 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11293 13:46:47.523468 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19724 ms)
11294 13:46:47.533341 [0:04:18.251078245] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 13:46:47.585020 [0:04:18.305412322] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11296 13:46:47.631612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11297 13:46:47.632461 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11299 13:46:47.641409 [0:04:18.363904938] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 13:46:47.648117 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11301 13:46:47.691087 Camera needs 4 requests, can't test only 1
11302 13:46:47.701138 [0:04:18.419870092] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 13:46:47.756737 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11304 13:46:47.815417
11305 13:46:47.884154 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11306 13:46:47.959654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11307 13:46:47.959978 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11309 13:46:47.969620 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11310 13:46:48.014073 Camera needs 4 requests, can't test only 2
11311 13:46:48.070570 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11312 13:46:48.126340
11313 13:46:48.196029 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11314 13:46:48.266431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11315 13:46:48.266721 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11317 13:46:48.276746 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11318 13:46:48.322024 Camera needs 4 requests, can't test only 3
11319 13:46:48.393594 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11320 13:46:48.460403
11321 13:46:48.541843 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (55 ms)
11322 13:46:48.628846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11323 13:46:48.629623 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11325 13:46:48.641725 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11326 13:46:49.773696 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2080 ms)
11327 13:46:49.783299 [0:04:20.501683630] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11328 13:46:49.867328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11329 13:46:49.868108 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11331 13:46:49.879392 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11332 14:12:47.456208 Marking unfinished test run as failed
11335 14:12:47.456533 end: 3.1 lava-test-shell (duration 00:30:00) [common]
11337 14:12:47.456706 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 1800 seconds'
11339 14:12:47.456851 end: 3 lava-test-retry (duration 00:30:00) [common]
11341 14:12:47.457069 Cleaning after the job
11342 14:12:47.457198 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/ramdisk
11343 14:12:47.459369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/kernel
11344 14:12:47.470094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/dtb
11345 14:12:47.470270 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/nfsrootfs
11346 14:12:47.510730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063102/tftp-deploy-h62bn31c/modules
11347 14:12:47.516296 start: 4.1 power-off (timeout 00:00:30) [common]
11348 14:12:47.516470 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11349 14:12:47.593499 >> Command sent successfully.
11350 14:12:47.595807 Returned 0 in 0 seconds
11351 14:12:47.696264 end: 4.1 power-off (duration 00:00:00) [common]
11353 14:12:47.696728 start: 4.2 read-feedback (timeout 00:10:00) [common]
11354 14:12:47.697070 Listened to connection for namespace 'common' for up to 1s
11355 14:12:48.697498 Finalising connection for namespace 'common'
11356 14:12:48.698142 Disconnecting from shell: Finalise
11357 14:12:48.799140 end: 4.2 read-feedback (duration 00:00:01) [common]
11358 14:12:48.799784 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063102
11359 14:12:49.096824 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063102
11360 14:12:49.097001 TestError: A test failed to run, look at the error message.