Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 13:41:26.043199 lava-dispatcher, installed at version: 2024.03
2 13:41:26.043407 start: 0 validate
3 13:41:26.043552 Start time: 2024-05-28 13:41:26.043544+00:00 (UTC)
4 13:41:26.043686 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:41:26.043817 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:41:26.301968 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:41:26.302152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:41:26.559242 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:41:26.559413 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:41:26.815670 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:41:26.815839 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:41:27.074428 validate duration: 1.03
14 13:41:27.074734 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:41:27.074854 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:41:27.074958 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:41:27.075093 Not decompressing ramdisk as can be used compressed.
18 13:41:27.075181 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 13:41:27.075253 saving as /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/ramdisk/rootfs.cpio.gz
20 13:41:27.075318 total size: 28105535 (26 MB)
21 13:41:27.076431 progress 0 % (0 MB)
22 13:41:27.083651 progress 5 % (1 MB)
23 13:41:27.090825 progress 10 % (2 MB)
24 13:41:27.098126 progress 15 % (4 MB)
25 13:41:27.105831 progress 20 % (5 MB)
26 13:41:27.113366 progress 25 % (6 MB)
27 13:41:27.121462 progress 30 % (8 MB)
28 13:41:27.129168 progress 35 % (9 MB)
29 13:41:27.137116 progress 40 % (10 MB)
30 13:41:27.144823 progress 45 % (12 MB)
31 13:41:27.152569 progress 50 % (13 MB)
32 13:41:27.160547 progress 55 % (14 MB)
33 13:41:27.168426 progress 60 % (16 MB)
34 13:41:27.175850 progress 65 % (17 MB)
35 13:41:27.183144 progress 70 % (18 MB)
36 13:41:27.190624 progress 75 % (20 MB)
37 13:41:27.198487 progress 80 % (21 MB)
38 13:41:27.206407 progress 85 % (22 MB)
39 13:41:27.214036 progress 90 % (24 MB)
40 13:41:27.221802 progress 95 % (25 MB)
41 13:41:27.229583 progress 100 % (26 MB)
42 13:41:27.229850 26 MB downloaded in 0.15 s (173.45 MB/s)
43 13:41:27.230025 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:41:27.230304 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:41:27.230394 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:41:27.230481 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:41:27.230629 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:41:27.230701 saving as /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/kernel/Image
50 13:41:27.230765 total size: 54682112 (52 MB)
51 13:41:27.230851 No compression specified
52 13:41:27.232476 progress 0 % (0 MB)
53 13:41:27.247459 progress 5 % (2 MB)
54 13:41:27.262593 progress 10 % (5 MB)
55 13:41:27.277416 progress 15 % (7 MB)
56 13:41:27.292553 progress 20 % (10 MB)
57 13:41:27.307593 progress 25 % (13 MB)
58 13:41:27.322167 progress 30 % (15 MB)
59 13:41:27.336367 progress 35 % (18 MB)
60 13:41:27.350326 progress 40 % (20 MB)
61 13:41:27.364294 progress 45 % (23 MB)
62 13:41:27.378451 progress 50 % (26 MB)
63 13:41:27.392400 progress 55 % (28 MB)
64 13:41:27.406514 progress 60 % (31 MB)
65 13:41:27.420760 progress 65 % (33 MB)
66 13:41:27.435405 progress 70 % (36 MB)
67 13:41:27.449386 progress 75 % (39 MB)
68 13:41:27.464364 progress 80 % (41 MB)
69 13:41:27.478863 progress 85 % (44 MB)
70 13:41:27.493432 progress 90 % (46 MB)
71 13:41:27.507960 progress 95 % (49 MB)
72 13:41:27.521990 progress 100 % (52 MB)
73 13:41:27.522277 52 MB downloaded in 0.29 s (178.89 MB/s)
74 13:41:27.522443 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:41:27.522689 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:41:27.522780 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:41:27.522867 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:41:27.523017 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:41:27.523090 saving as /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/dtb/mt8192-asurada-spherion-r0.dtb
81 13:41:27.523154 total size: 47258 (0 MB)
82 13:41:27.523219 No compression specified
83 13:41:27.524325 progress 69 % (0 MB)
84 13:41:27.524606 progress 100 % (0 MB)
85 13:41:27.524775 0 MB downloaded in 0.00 s (27.86 MB/s)
86 13:41:27.524906 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:41:27.525142 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:41:27.525230 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:41:27.525342 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:41:27.525467 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:41:27.525538 saving as /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/modules/modules.tar
93 13:41:27.525601 total size: 8607916 (8 MB)
94 13:41:27.525666 Using unxz to decompress xz
95 13:41:27.529516 progress 0 % (0 MB)
96 13:41:27.550059 progress 5 % (0 MB)
97 13:41:27.575130 progress 10 % (0 MB)
98 13:41:27.601296 progress 15 % (1 MB)
99 13:41:27.626729 progress 20 % (1 MB)
100 13:41:27.657570 progress 25 % (2 MB)
101 13:41:27.684023 progress 30 % (2 MB)
102 13:41:27.709042 progress 35 % (2 MB)
103 13:41:27.739856 progress 40 % (3 MB)
104 13:41:27.768381 progress 45 % (3 MB)
105 13:41:27.795065 progress 50 % (4 MB)
106 13:41:27.821667 progress 55 % (4 MB)
107 13:41:27.847862 progress 60 % (4 MB)
108 13:41:27.873162 progress 65 % (5 MB)
109 13:41:27.899566 progress 70 % (5 MB)
110 13:41:27.927736 progress 75 % (6 MB)
111 13:41:27.952287 progress 80 % (6 MB)
112 13:41:27.977801 progress 85 % (7 MB)
113 13:41:28.003077 progress 90 % (7 MB)
114 13:41:28.033678 progress 95 % (7 MB)
115 13:41:28.063118 progress 100 % (8 MB)
116 13:41:28.068942 8 MB downloaded in 0.54 s (15.11 MB/s)
117 13:41:28.069288 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:41:28.069576 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:41:28.069670 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:41:28.069767 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:41:28.069849 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:41:28.069937 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:41:28.070176 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg
125 13:41:28.070316 makedir: /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin
126 13:41:28.070422 makedir: /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/tests
127 13:41:28.070522 makedir: /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/results
128 13:41:28.070640 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-add-keys
129 13:41:28.070786 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-add-sources
130 13:41:28.070918 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-background-process-start
131 13:41:28.071050 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-background-process-stop
132 13:41:28.071177 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-common-functions
133 13:41:28.071303 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-echo-ipv4
134 13:41:28.071431 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-install-packages
135 13:41:28.071557 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-installed-packages
136 13:41:28.071681 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-os-build
137 13:41:28.071812 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-probe-channel
138 13:41:28.071938 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-probe-ip
139 13:41:28.072068 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-target-ip
140 13:41:28.072195 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-target-mac
141 13:41:28.072320 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-target-storage
142 13:41:28.072450 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-case
143 13:41:28.072575 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-event
144 13:41:28.072699 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-feedback
145 13:41:28.072824 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-raise
146 13:41:28.072948 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-reference
147 13:41:28.073073 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-runner
148 13:41:28.073197 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-set
149 13:41:28.073365 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-test-shell
150 13:41:28.073494 Updating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-install-packages (oe)
151 13:41:28.073646 Updating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/bin/lava-installed-packages (oe)
152 13:41:28.073771 Creating /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/environment
153 13:41:28.073874 LAVA metadata
154 13:41:28.073949 - LAVA_JOB_ID=14063119
155 13:41:28.074015 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:41:28.074125 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:41:28.074195 skipped lava-vland-overlay
158 13:41:28.074271 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:41:28.074356 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:41:28.074432 skipped lava-multinode-overlay
161 13:41:28.074505 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:41:28.074589 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:41:28.074664 Loading test definitions
164 13:41:28.074757 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:41:28.074831 Using /lava-14063119 at stage 0
166 13:41:28.075158 uuid=14063119_1.5.2.3.1 testdef=None
167 13:41:28.075248 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:41:28.075333 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:41:28.075855 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:41:28.076081 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:41:28.076703 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:41:28.076934 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:41:28.077576 runner path: /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14063119_1.5.2.3.1
176 13:41:28.077734 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:41:28.077974 Creating lava-test-runner.conf files
179 13:41:28.078038 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063119/lava-overlay-kbv51cwg/lava-14063119/0 for stage 0
180 13:41:28.078128 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:41:28.078227 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:41:28.078316 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:41:28.085641 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:41:28.085788 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:41:28.085909 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:41:28.086028 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:41:28.086134 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:41:29.007540 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:41:29.007926 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:41:29.008048 extracting modules file /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063119/extract-overlay-ramdisk-y7idkm1a/ramdisk
191 13:41:29.238773 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:41:29.238945 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:41:29.239059 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063119/compress-overlay-31h6v7mk/overlay-1.5.2.4.tar.gz to ramdisk
194 13:41:29.239141 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063119/compress-overlay-31h6v7mk/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063119/extract-overlay-ramdisk-y7idkm1a/ramdisk
195 13:41:29.245848 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:41:29.246015 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:41:29.246155 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:41:29.246288 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:41:29.246407 Building ramdisk /var/lib/lava/dispatcher/tmp/14063119/extract-overlay-ramdisk-y7idkm1a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063119/extract-overlay-ramdisk-y7idkm1a/ramdisk
200 13:41:29.902435 >> 275882 blocks
201 13:41:34.138617 rename /var/lib/lava/dispatcher/tmp/14063119/extract-overlay-ramdisk-y7idkm1a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/ramdisk/ramdisk.cpio.gz
202 13:41:34.139094 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:41:34.139248 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:41:34.139380 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:41:34.139518 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/kernel/Image']
206 13:41:47.759984 Returned 0 in 13 seconds
207 13:41:47.860954 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/kernel/image.itb
208 13:41:48.488566 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:41:48.488947 output: Created: Tue May 28 14:41:48 2024
210 13:41:48.489019 output: Image 0 (kernel-1)
211 13:41:48.489084 output: Description:
212 13:41:48.489144 output: Created: Tue May 28 14:41:48 2024
213 13:41:48.489204 output: Type: Kernel Image
214 13:41:48.489288 output: Compression: lzma compressed
215 13:41:48.489361 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:41:48.489424 output: Architecture: AArch64
217 13:41:48.489484 output: OS: Linux
218 13:41:48.489542 output: Load Address: 0x00000000
219 13:41:48.489598 output: Entry Point: 0x00000000
220 13:41:48.489653 output: Hash algo: crc32
221 13:41:48.489710 output: Hash value: 0578ee26
222 13:41:48.489765 output: Image 1 (fdt-1)
223 13:41:48.489822 output: Description: mt8192-asurada-spherion-r0
224 13:41:48.489879 output: Created: Tue May 28 14:41:48 2024
225 13:41:48.489933 output: Type: Flat Device Tree
226 13:41:48.489988 output: Compression: uncompressed
227 13:41:48.490040 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:41:48.490092 output: Architecture: AArch64
229 13:41:48.490144 output: Hash algo: crc32
230 13:41:48.490195 output: Hash value: 0f8e4d2e
231 13:41:48.490247 output: Image 2 (ramdisk-1)
232 13:41:48.490298 output: Description: unavailable
233 13:41:48.490350 output: Created: Tue May 28 14:41:48 2024
234 13:41:48.490402 output: Type: RAMDisk Image
235 13:41:48.490454 output: Compression: Unknown Compression
236 13:41:48.490506 output: Data Size: 41203518 Bytes = 40237.81 KiB = 39.29 MiB
237 13:41:48.490563 output: Architecture: AArch64
238 13:41:48.490622 output: OS: Linux
239 13:41:48.490674 output: Load Address: unavailable
240 13:41:48.490726 output: Entry Point: unavailable
241 13:41:48.490777 output: Hash algo: crc32
242 13:41:48.490829 output: Hash value: a4da5907
243 13:41:48.490880 output: Default Configuration: 'conf-1'
244 13:41:48.490932 output: Configuration 0 (conf-1)
245 13:41:48.490984 output: Description: mt8192-asurada-spherion-r0
246 13:41:48.491036 output: Kernel: kernel-1
247 13:41:48.491088 output: Init Ramdisk: ramdisk-1
248 13:41:48.491140 output: FDT: fdt-1
249 13:41:48.491191 output: Loadables: kernel-1
250 13:41:48.491242 output:
251 13:41:48.491436 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:41:48.491527 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:41:48.491631 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 13:41:48.491726 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 13:41:48.491802 No LXC device requested
256 13:41:48.491879 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:41:48.491960 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 13:41:48.492036 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:41:48.492101 Checking files for TFTP limit of 4294967296 bytes.
260 13:41:48.492688 end: 1 tftp-deploy (duration 00:00:21) [common]
261 13:41:48.492829 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:41:48.492922 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:41:48.493046 substitutions:
264 13:41:48.493113 - {DTB}: 14063119/tftp-deploy-3bwkfllz/dtb/mt8192-asurada-spherion-r0.dtb
265 13:41:48.493176 - {INITRD}: 14063119/tftp-deploy-3bwkfllz/ramdisk/ramdisk.cpio.gz
266 13:41:48.493236 - {KERNEL}: 14063119/tftp-deploy-3bwkfllz/kernel/Image
267 13:41:48.493336 - {LAVA_MAC}: None
268 13:41:48.493394 - {PRESEED_CONFIG}: None
269 13:41:48.493449 - {PRESEED_LOCAL}: None
270 13:41:48.493504 - {RAMDISK}: 14063119/tftp-deploy-3bwkfllz/ramdisk/ramdisk.cpio.gz
271 13:41:48.493558 - {ROOT_PART}: None
272 13:41:48.493613 - {ROOT}: None
273 13:41:48.493666 - {SERVER_IP}: 192.168.201.1
274 13:41:48.493720 - {TEE}: None
275 13:41:48.493774 Parsed boot commands:
276 13:41:48.493827 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:41:48.494004 Parsed boot commands: tftpboot 192.168.201.1 14063119/tftp-deploy-3bwkfllz/kernel/image.itb 14063119/tftp-deploy-3bwkfllz/kernel/cmdline
278 13:41:48.494092 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:41:48.494180 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:41:48.494268 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:41:48.494359 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:41:48.494428 Not connected, no need to disconnect.
283 13:41:48.494500 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:41:48.494582 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:41:48.494656 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 13:41:48.498120 Setting prompt string to ['lava-test: # ']
287 13:41:48.498475 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:41:48.498574 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:41:48.498671 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:41:48.498778 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:41:48.498992 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 13:42:02.505823 Returned 0 in 14 seconds
293 13:42:02.606906 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 13:42:02.609608 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 13:42:02.610123 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 13:42:02.610567 Setting prompt string to 'Starting depthcharge on Spherion...'
298 13:42:02.610918 Changing prompt to 'Starting depthcharge on Spherion...'
299 13:42:02.611273 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 13:42:02.613192 [Enter `^Ec?' for help]
301 13:42:02.613687
302 13:42:02.614041
303 13:42:02.614370 F0: 102B 0000
304 13:42:02.614693
305 13:42:02.615009 F3: 1001 0000 [0200]
306 13:42:02.615318
307 13:42:02.615627 F3: 1001 0000
308 13:42:02.615944
309 13:42:02.616245 F7: 102D 0000
310 13:42:02.616549
311 13:42:02.616839 F1: 0000 0000
312 13:42:02.617131
313 13:42:02.617464 V0: 0000 0000 [0001]
314 13:42:02.617756
315 13:42:02.618038 00: 0007 8000
316 13:42:02.618344
317 13:42:02.618629 01: 0000 0000
318 13:42:02.618924
319 13:42:02.619346 BP: 0C00 0209 [0000]
320 13:42:02.619648
321 13:42:02.619971 G0: 1182 0000
322 13:42:02.620266
323 13:42:02.620551 EC: 0000 0021 [4000]
324 13:42:02.620868
325 13:42:02.621337 S7: 0000 0000 [0000]
326 13:42:02.621639
327 13:42:02.621925 CC: 0000 0000 [0001]
328 13:42:02.622210
329 13:42:02.622591 T0: 0000 0040 [010F]
330 13:42:02.623171
331 13:42:02.623613 Jump to BL
332 13:42:02.623925
333 13:42:02.624219
334 13:42:02.624508
335 13:42:02.624972 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 13:42:02.625503 ARM64: Exception handlers installed.
337 13:42:02.625821 ARM64: Testing exception
338 13:42:02.626195 ARM64: Done test exception
339 13:42:02.626497 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 13:42:02.626792 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 13:42:02.627082 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 13:42:02.627373 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 13:42:02.627663 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 13:42:02.627951 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 13:42:02.628238 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 13:42:02.628528 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 13:42:02.628814 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 13:42:02.629098 WDT: Last reset was cold boot
349 13:42:02.629432 SPI1(PAD0) initialized at 2873684 Hz
350 13:42:02.629725 SPI5(PAD0) initialized at 992727 Hz
351 13:42:02.630012 VBOOT: Loading verstage.
352 13:42:02.630295 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 13:42:02.630581 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 13:42:02.630868 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 13:42:02.631158 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 13:42:02.631629 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 13:42:02.632090 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 13:42:02.632590 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 13:42:02.633040
360 13:42:02.633528
361 13:42:02.633877 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 13:42:02.634192 ARM64: Exception handlers installed.
363 13:42:02.634504 ARM64: Testing exception
364 13:42:02.634814 ARM64: Done test exception
365 13:42:02.635124 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 13:42:02.635440 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 13:42:02.635751 Probing TPM: . done!
368 13:42:02.636059 TPM ready after 0 ms
369 13:42:02.636370 Connected to device vid:did:rid of 1ae0:0028:00
370 13:42:02.636685 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 13:42:02.637000 Initialized TPM device CR50 revision 0
372 13:42:02.637331 tlcl_send_startup: Startup return code is 0
373 13:42:02.637554 TPM: setup succeeded
374 13:42:02.637760 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 13:42:02.638020 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 13:42:02.638233 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 13:42:02.638442 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:42:02.638640 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 13:42:02.638794 in-header: 03 07 00 00 08 00 00 00
380 13:42:02.638948 in-data: aa e4 47 04 13 02 00 00
381 13:42:02.639100 Chrome EC: UHEPI supported
382 13:42:02.639261 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 13:42:02.639417 in-header: 03 a9 00 00 08 00 00 00
384 13:42:02.639569 in-data: 84 60 60 08 00 00 00 00
385 13:42:02.639743 Phase 1
386 13:42:02.640016 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 13:42:02.640186 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 13:42:02.640343 VB2:vb2_check_recovery() Recovery was requested manually
389 13:42:02.640499 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 13:42:02.640655 Recovery requested (1009000e)
391 13:42:02.640810 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:42:02.640966 tlcl_extend: response is 0
393 13:42:02.641119 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:42:02.641297 tlcl_extend: response is 0
395 13:42:02.641457 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:42:02.641611 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
397 13:42:02.641765 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 13:42:02.641919
399 13:42:02.642072
400 13:42:02.642226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:42:02.642381 ARM64: Exception handlers installed.
402 13:42:02.642534 ARM64: Testing exception
403 13:42:02.642685 ARM64: Done test exception
404 13:42:02.642834 pmic_efuse_setting: Set efuses in 11 msecs
405 13:42:02.642986 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:42:02.643144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:42:02.643298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:42:02.643701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:42:02.643850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:42:02.643977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:42:02.644102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:42:02.644226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:42:02.644348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:42:02.644470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:42:02.644595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:42:02.644718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:42:02.644840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:42:02.644961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:42:02.645084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:42:02.645207 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:42:02.645357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:42:02.645500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:42:02.645645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:42:02.645770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:42:02.645894 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:42:02.646103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:42:02.646305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:42:02.646504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:42:02.646635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:42:02.646761 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:42:02.646918 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:42:02.647052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:42:02.647176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:42:02.647298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:42:02.647422 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:42:02.647545 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:42:02.647668 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:42:02.647790 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:42:02.647912 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:42:02.648052 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:42:02.648183 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:42:02.648307 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:42:02.648430 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:42:02.648553 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:42:02.648669 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:42:02.648770 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:42:02.648872 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:42:02.648974 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:42:02.649075 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:42:02.649176 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:42:02.649292 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:42:02.649396 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:42:02.649498 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:42:02.649600 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:42:02.649701 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:42:02.649803 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:42:02.649906 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 13:42:02.650010 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:42:02.650112 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:42:02.650214 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:42:02.650316 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:42:02.650419 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:42:02.650520 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:42:02.650622 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:42:02.650724 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0xb
466 13:42:02.650826 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 13:42:02.650928 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 13:42:02.651030 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:42:02.651132 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 13:42:02.651233 [RTC]rtc_get_frequency_meter,154: input=7, output=726
471 13:42:02.651335 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 13:42:02.651437 [RTC]rtc_get_frequency_meter,154: input=13, output=820
473 13:42:02.651538 [RTC]rtc_get_frequency_meter,154: input=12, output=804
474 13:42:02.651644 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 13:42:02.651745 [RTC]rtc_get_frequency_meter,154: input=12, output=805
476 13:42:02.651845 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 13:42:02.651946 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 13:42:02.652260 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 13:42:02.652374 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 13:42:02.652481 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 13:42:02.652585 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 13:42:02.652689 ADC[4]: Raw value=905172 ID=7
483 13:42:02.652791 ADC[3]: Raw value=213546 ID=1
484 13:42:02.652894 RAM Code: 0x71
485 13:42:02.652995 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 13:42:02.653099 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 13:42:02.653201 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 13:42:02.653326 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 13:42:02.653431 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 13:42:02.653536 in-header: 03 07 00 00 08 00 00 00
491 13:42:02.653645 in-data: aa e4 47 04 13 02 00 00
492 13:42:02.653733 Chrome EC: UHEPI supported
493 13:42:02.653821 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 13:42:02.653909 in-header: 03 a9 00 00 08 00 00 00
495 13:42:02.654006 in-data: 84 60 60 08 00 00 00 00
496 13:42:02.654093 MRC: failed to locate region type 0.
497 13:42:02.654181 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 13:42:02.654268 DRAM-K: Running full calibration
499 13:42:02.654355 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 13:42:02.654443 header.status = 0x0
501 13:42:02.654530 header.version = 0x6 (expected: 0x6)
502 13:42:02.654616 header.size = 0xd00 (expected: 0xd00)
503 13:42:02.654702 header.flags = 0x0
504 13:42:02.654788 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 13:42:02.654876 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 13:42:02.654965 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 13:42:02.655053 dram_init: ddr_geometry: 2
508 13:42:02.655140 [EMI] MDL number = 2
509 13:42:02.655226 [EMI] Get MDL freq = 0
510 13:42:02.655313 dram_init: ddr_type: 0
511 13:42:02.655400 is_discrete_lpddr4: 1
512 13:42:02.655487 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 13:42:02.655573
514 13:42:02.655661
515 13:42:02.655747 [Bian_co] ETT version 0.0.0.1
516 13:42:02.655834 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 13:42:02.655921
518 13:42:02.656007 dramc_set_vcore_voltage set vcore to 650000
519 13:42:02.656095 Read voltage for 800, 4
520 13:42:02.656182 Vio18 = 0
521 13:42:02.656269 Vcore = 650000
522 13:42:02.656356 Vdram = 0
523 13:42:02.656443 Vddq = 0
524 13:42:02.656529 Vmddr = 0
525 13:42:02.656615 dram_init: config_dvfs: 1
526 13:42:02.656703 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 13:42:02.656791 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 13:42:02.656879 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 13:42:02.656967 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 13:42:02.657054 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 13:42:02.657141 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 13:42:02.657229 MEM_TYPE=3, freq_sel=18
533 13:42:02.657331 sv_algorithm_assistance_LP4_1600
534 13:42:02.657419 ============ PULL DRAM RESETB DOWN ============
535 13:42:02.657511 ========== PULL DRAM RESETB DOWN end =========
536 13:42:02.657599 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 13:42:02.657687 ===================================
538 13:42:02.657774 LPDDR4 DRAM CONFIGURATION
539 13:42:02.657860 ===================================
540 13:42:02.657947 EX_ROW_EN[0] = 0x0
541 13:42:02.658034 EX_ROW_EN[1] = 0x0
542 13:42:02.658120 LP4Y_EN = 0x0
543 13:42:02.658205 WORK_FSP = 0x0
544 13:42:02.658292 WL = 0x2
545 13:42:02.658379 RL = 0x2
546 13:42:02.658465 BL = 0x2
547 13:42:02.658551 RPST = 0x0
548 13:42:02.658644 RD_PRE = 0x0
549 13:42:02.658719 WR_PRE = 0x1
550 13:42:02.658795 WR_PST = 0x0
551 13:42:02.658871 DBI_WR = 0x0
552 13:42:02.658946 DBI_RD = 0x0
553 13:42:02.659022 OTF = 0x1
554 13:42:02.659099 ===================================
555 13:42:02.659175 ===================================
556 13:42:02.659252 ANA top config
557 13:42:02.659328 ===================================
558 13:42:02.659404 DLL_ASYNC_EN = 0
559 13:42:02.659480 ALL_SLAVE_EN = 1
560 13:42:02.659555 NEW_RANK_MODE = 1
561 13:42:02.659632 DLL_IDLE_MODE = 1
562 13:42:02.659707 LP45_APHY_COMB_EN = 1
563 13:42:02.659783 TX_ODT_DIS = 1
564 13:42:02.659858 NEW_8X_MODE = 1
565 13:42:02.659941 ===================================
566 13:42:02.660019 ===================================
567 13:42:02.660095 data_rate = 1600
568 13:42:02.660171 CKR = 1
569 13:42:02.660246 DQ_P2S_RATIO = 8
570 13:42:02.660322 ===================================
571 13:42:02.660397 CA_P2S_RATIO = 8
572 13:42:02.660473 DQ_CA_OPEN = 0
573 13:42:02.660548 DQ_SEMI_OPEN = 0
574 13:42:02.660624 CA_SEMI_OPEN = 0
575 13:42:02.660699 CA_FULL_RATE = 0
576 13:42:02.660775 DQ_CKDIV4_EN = 1
577 13:42:02.660851 CA_CKDIV4_EN = 1
578 13:42:02.660927 CA_PREDIV_EN = 0
579 13:42:02.661002 PH8_DLY = 0
580 13:42:02.661078 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 13:42:02.661154 DQ_AAMCK_DIV = 4
582 13:42:02.661230 CA_AAMCK_DIV = 4
583 13:42:02.661324 CA_ADMCK_DIV = 4
584 13:42:02.661400 DQ_TRACK_CA_EN = 0
585 13:42:02.661477 CA_PICK = 800
586 13:42:02.661553 CA_MCKIO = 800
587 13:42:02.661630 MCKIO_SEMI = 0
588 13:42:02.661706 PLL_FREQ = 3068
589 13:42:02.661781 DQ_UI_PI_RATIO = 32
590 13:42:02.661857 CA_UI_PI_RATIO = 0
591 13:42:02.661946 ===================================
592 13:42:02.662081 ===================================
593 13:42:02.662165 memory_type:LPDDR4
594 13:42:02.662243 GP_NUM : 10
595 13:42:02.662320 SRAM_EN : 1
596 13:42:02.662396 MD32_EN : 0
597 13:42:02.662473 ===================================
598 13:42:02.662771 [ANA_INIT] >>>>>>>>>>>>>>
599 13:42:02.662859 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 13:42:02.662942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 13:42:02.663021 ===================================
602 13:42:02.663099 data_rate = 1600,PCW = 0X7600
603 13:42:02.663176 ===================================
604 13:42:02.663253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 13:42:02.663335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 13:42:02.663412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:42:02.663491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 13:42:02.663569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 13:42:02.663655 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:42:02.663724 [ANA_INIT] flow start
611 13:42:02.663792 [ANA_INIT] PLL >>>>>>>>
612 13:42:02.663860 [ANA_INIT] PLL <<<<<<<<
613 13:42:02.663929 [ANA_INIT] MIDPI >>>>>>>>
614 13:42:02.663997 [ANA_INIT] MIDPI <<<<<<<<
615 13:42:02.664064 [ANA_INIT] DLL >>>>>>>>
616 13:42:02.664133 [ANA_INIT] flow end
617 13:42:02.664201 ============ LP4 DIFF to SE enter ============
618 13:42:02.664270 ============ LP4 DIFF to SE exit ============
619 13:42:02.664338 [ANA_INIT] <<<<<<<<<<<<<
620 13:42:02.664407 [Flow] Enable top DCM control >>>>>
621 13:42:02.664475 [Flow] Enable top DCM control <<<<<
622 13:42:02.664543 Enable DLL master slave shuffle
623 13:42:02.664611 ==============================================================
624 13:42:02.664680 Gating Mode config
625 13:42:02.664748 ==============================================================
626 13:42:02.664816 Config description:
627 13:42:02.664885 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 13:42:02.664955 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 13:42:02.665024 SELPH_MODE 0: By rank 1: By Phase
630 13:42:02.665093 ==============================================================
631 13:42:02.665162 GAT_TRACK_EN = 1
632 13:42:02.665230 RX_GATING_MODE = 2
633 13:42:02.665309 RX_GATING_TRACK_MODE = 2
634 13:42:02.665378 SELPH_MODE = 1
635 13:42:02.665447 PICG_EARLY_EN = 1
636 13:42:02.665515 VALID_LAT_VALUE = 1
637 13:42:02.665582 ==============================================================
638 13:42:02.665650 Enter into Gating configuration >>>>
639 13:42:02.665718 Exit from Gating configuration <<<<
640 13:42:02.665786 Enter into DVFS_PRE_config >>>>>
641 13:42:02.665854 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 13:42:02.665926 Exit from DVFS_PRE_config <<<<<
643 13:42:02.665995 Enter into PICG configuration >>>>
644 13:42:02.666063 Exit from PICG configuration <<<<
645 13:42:02.666130 [RX_INPUT] configuration >>>>>
646 13:42:02.666198 [RX_INPUT] configuration <<<<<
647 13:42:02.666266 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 13:42:02.666334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 13:42:02.666403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:42:02.666471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:42:02.666540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 13:42:02.666608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 13:42:02.666677 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 13:42:02.666746 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 13:42:02.666813 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 13:42:02.666881 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 13:42:02.666949 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 13:42:02.667017 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 13:42:02.667085 ===================================
660 13:42:02.667153 LPDDR4 DRAM CONFIGURATION
661 13:42:02.667221 ===================================
662 13:42:02.667290 EX_ROW_EN[0] = 0x0
663 13:42:02.667357 EX_ROW_EN[1] = 0x0
664 13:42:02.667425 LP4Y_EN = 0x0
665 13:42:02.667493 WORK_FSP = 0x0
666 13:42:02.667560 WL = 0x2
667 13:42:02.667627 RL = 0x2
668 13:42:02.667695 BL = 0x2
669 13:42:02.667762 RPST = 0x0
670 13:42:02.667829 RD_PRE = 0x0
671 13:42:02.667896 WR_PRE = 0x1
672 13:42:02.667964 WR_PST = 0x0
673 13:42:02.668031 DBI_WR = 0x0
674 13:42:02.668098 DBI_RD = 0x0
675 13:42:02.668166 OTF = 0x1
676 13:42:02.668234 ===================================
677 13:42:02.668301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 13:42:02.668369 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 13:42:02.668437 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 13:42:02.668506 ===================================
681 13:42:02.668574 LPDDR4 DRAM CONFIGURATION
682 13:42:02.668649 ===================================
683 13:42:02.668710 EX_ROW_EN[0] = 0x10
684 13:42:02.668771 EX_ROW_EN[1] = 0x0
685 13:42:02.668832 LP4Y_EN = 0x0
686 13:42:02.668893 WORK_FSP = 0x0
687 13:42:02.668953 WL = 0x2
688 13:42:02.669014 RL = 0x2
689 13:42:02.669074 BL = 0x2
690 13:42:02.669135 RPST = 0x0
691 13:42:02.669198 RD_PRE = 0x0
692 13:42:02.669263 WR_PRE = 0x1
693 13:42:02.669326 WR_PST = 0x0
694 13:42:02.669387 DBI_WR = 0x0
695 13:42:02.669447 DBI_RD = 0x0
696 13:42:02.669508 OTF = 0x1
697 13:42:02.669569 ===================================
698 13:42:02.669630 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 13:42:02.669692 nWR fixed to 40
700 13:42:02.669753 [ModeRegInit_LP4] CH0 RK0
701 13:42:02.669815 [ModeRegInit_LP4] CH0 RK1
702 13:42:02.669876 [ModeRegInit_LP4] CH1 RK0
703 13:42:02.669936 [ModeRegInit_LP4] CH1 RK1
704 13:42:02.669997 match AC timing 13
705 13:42:02.670057 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 13:42:02.670318 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 13:42:02.670391 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 13:42:02.670456 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 13:42:02.670518 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 13:42:02.670581 [EMI DOE] emi_dcm 0
711 13:42:02.670643 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 13:42:02.670705 ==
713 13:42:02.670767 Dram Type= 6, Freq= 0, CH_0, rank 0
714 13:42:02.670829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 13:42:02.670891 ==
716 13:42:02.670953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 13:42:02.671015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 13:42:02.671077 [CA 0] Center 37 (7~68) winsize 62
719 13:42:02.671138 [CA 1] Center 37 (7~68) winsize 62
720 13:42:02.671200 [CA 2] Center 34 (4~65) winsize 62
721 13:42:02.671261 [CA 3] Center 35 (4~66) winsize 63
722 13:42:02.671321 [CA 4] Center 33 (3~64) winsize 62
723 13:42:02.671382 [CA 5] Center 33 (3~64) winsize 62
724 13:42:02.671443
725 13:42:02.671504 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 13:42:02.671565
727 13:42:02.671627 [CATrainingPosCal] consider 1 rank data
728 13:42:02.671689 u2DelayCellTimex100 = 270/100 ps
729 13:42:02.671750 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 13:42:02.671811 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:42:02.671873 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 13:42:02.671934 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 13:42:02.671994 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 13:42:02.672056 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:42:02.672116
736 13:42:02.672177 CA PerBit enable=1, Macro0, CA PI delay=33
737 13:42:02.672238
738 13:42:02.672300 [CBTSetCACLKResult] CA Dly = 33
739 13:42:02.672360 CS Dly: 5 (0~36)
740 13:42:02.672422 ==
741 13:42:02.672483 Dram Type= 6, Freq= 0, CH_0, rank 1
742 13:42:02.672545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 13:42:02.672607 ==
744 13:42:02.672668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 13:42:02.672729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 13:42:02.672790 [CA 0] Center 38 (7~69) winsize 63
747 13:42:02.672851 [CA 1] Center 37 (7~68) winsize 62
748 13:42:02.672912 [CA 2] Center 35 (4~66) winsize 63
749 13:42:02.672973 [CA 3] Center 34 (4~65) winsize 62
750 13:42:02.673034 [CA 4] Center 34 (4~65) winsize 62
751 13:42:02.673095 [CA 5] Center 33 (3~64) winsize 62
752 13:42:02.673156
753 13:42:02.673217 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 13:42:02.673287
755 13:42:02.673350 [CATrainingPosCal] consider 2 rank data
756 13:42:02.673411 u2DelayCellTimex100 = 270/100 ps
757 13:42:02.673472 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 13:42:02.673534 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:42:02.673595 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 13:42:02.673666 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:42:02.673721 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
762 13:42:02.673777 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:42:02.673832
764 13:42:02.673887 CA PerBit enable=1, Macro0, CA PI delay=33
765 13:42:02.673943
766 13:42:02.673998 [CBTSetCACLKResult] CA Dly = 33
767 13:42:02.674054 CS Dly: 5 (0~37)
768 13:42:02.674109
769 13:42:02.674164 ----->DramcWriteLeveling(PI) begin...
770 13:42:02.674222 ==
771 13:42:02.674277 Dram Type= 6, Freq= 0, CH_0, rank 0
772 13:42:02.674333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 13:42:02.674389 ==
774 13:42:02.674445 Write leveling (Byte 0): 30 => 30
775 13:42:02.674500 Write leveling (Byte 1): 25 => 25
776 13:42:02.674555 DramcWriteLeveling(PI) end<-----
777 13:42:02.674611
778 13:42:02.674666 ==
779 13:42:02.674722 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:42:02.674778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:42:02.674834 ==
782 13:42:02.674890 [Gating] SW mode calibration
783 13:42:02.674947 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 13:42:02.675002 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 13:42:02.675059 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 13:42:02.675115 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 13:42:02.675171 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 13:42:02.675227 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:42:02.675282 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:42:02.675339 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:42:02.675394 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:42:02.675451 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:42:02.675506 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:42:02.675561 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:42:02.675617 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:42:02.675672 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:42:02.675727 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:42:02.675783 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:42:02.675838 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:42:02.675894 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:42:02.675950 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:42:02.676031 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
803 13:42:02.676101 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 13:42:02.676193 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:42:02.676254 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:42:02.676311 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:42:02.676367 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:42:02.676423 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:42:02.676478 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:42:02.676534 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:42:02.676589 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
812 13:42:02.676645 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
813 13:42:02.676701 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:42:02.676949 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:42:02.677011 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:42:02.677069 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:42:02.677126 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:42:02.677182 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
819 13:42:02.677239 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
820 13:42:02.677309 0 10 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
821 13:42:02.677366 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:42:02.677422 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:42:02.677477 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:42:02.677533 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:42:02.677588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:42:02.677644 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
827 13:42:02.677699 0 11 8 | B1->B0 | 2928 4040 | 1 0 | (0 0) (0 0)
828 13:42:02.677755 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
829 13:42:02.677811 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:42:02.677867 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:42:02.677922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:42:02.677978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:42:02.678033 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:42:02.678089 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 13:42:02.678144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 13:42:02.678200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:42:02.678255 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:42:02.678311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:42:02.678366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:42:02.678422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:42:02.678477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:42:02.678533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:42:02.678601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:42:02.678656 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:42:02.678709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:42:02.678763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:42:02.678818 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:42:02.678872 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:42:02.678926 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:42:02.678981 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 13:42:02.679035 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:42:02.679089 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:42:02.679144 Total UI for P1: 0, mck2ui 16
854 13:42:02.679199 best dqsien dly found for B0: ( 0, 14, 6)
855 13:42:02.679253 Total UI for P1: 0, mck2ui 16
856 13:42:02.679308 best dqsien dly found for B1: ( 0, 14, 10)
857 13:42:02.679362 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 13:42:02.679417 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 13:42:02.679471
860 13:42:02.679526 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 13:42:02.679580 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 13:42:02.679635 [Gating] SW calibration Done
863 13:42:02.679689 ==
864 13:42:02.679744 Dram Type= 6, Freq= 0, CH_0, rank 0
865 13:42:02.679799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 13:42:02.679854 ==
867 13:42:02.679933 RX Vref Scan: 0
868 13:42:02.680002
869 13:42:02.680081 RX Vref 0 -> 0, step: 1
870 13:42:02.680137
871 13:42:02.680204 RX Delay -130 -> 252, step: 16
872 13:42:02.680281 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
873 13:42:02.680349 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 13:42:02.680403 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
875 13:42:02.680457 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
876 13:42:02.680511 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 13:42:02.680565 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 13:42:02.680619 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 13:42:02.680674 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 13:42:02.680729 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 13:42:02.680783 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 13:42:02.680837 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 13:42:02.680892 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 13:42:02.680946 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 13:42:02.681000 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 13:42:02.681054 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 13:42:02.681109 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 13:42:02.681163 ==
889 13:42:02.681217 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:42:02.681293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 13:42:02.681362 ==
892 13:42:02.681417 DQS Delay:
893 13:42:02.681471 DQS0 = 0, DQS1 = 0
894 13:42:02.681525 DQM Delay:
895 13:42:02.681578 DQM0 = 91, DQM1 = 75
896 13:42:02.681632 DQ Delay:
897 13:42:02.681686 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
898 13:42:02.681740 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
899 13:42:02.681794 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
900 13:42:02.681849 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 13:42:02.681903
902 13:42:02.681957
903 13:42:02.682011 ==
904 13:42:02.682065 Dram Type= 6, Freq= 0, CH_0, rank 0
905 13:42:02.682119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 13:42:02.682174 ==
907 13:42:02.682229
908 13:42:02.682283
909 13:42:02.682337 TX Vref Scan disable
910 13:42:02.682391 == TX Byte 0 ==
911 13:42:02.682445 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 13:42:02.682500 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 13:42:02.682555 == TX Byte 1 ==
914 13:42:02.682609 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
915 13:42:02.682664 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
916 13:42:02.682717 ==
917 13:42:02.682771 Dram Type= 6, Freq= 0, CH_0, rank 0
918 13:42:02.682825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 13:42:02.682880 ==
920 13:42:02.682934 TX Vref=22, minBit 0, minWin=27, winSum=434
921 13:42:02.682988 TX Vref=24, minBit 1, minWin=27, winSum=442
922 13:42:02.683236 TX Vref=26, minBit 1, minWin=27, winSum=445
923 13:42:02.683298 TX Vref=28, minBit 6, minWin=27, winSum=448
924 13:42:02.683355 TX Vref=30, minBit 2, minWin=27, winSum=451
925 13:42:02.683410 TX Vref=32, minBit 1, minWin=27, winSum=447
926 13:42:02.683465 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
927 13:42:02.683521
928 13:42:02.683575 Final TX Range 1 Vref 30
929 13:42:02.683630
930 13:42:02.683684 ==
931 13:42:02.683739 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:42:02.683793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:42:02.683848 ==
934 13:42:02.683902
935 13:42:02.683956
936 13:42:02.684009 TX Vref Scan disable
937 13:42:02.684063 == TX Byte 0 ==
938 13:42:02.684118 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
939 13:42:02.684173 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
940 13:42:02.684227 == TX Byte 1 ==
941 13:42:02.684282 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
942 13:42:02.684336 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
943 13:42:02.684395
944 13:42:02.684449 [DATLAT]
945 13:42:02.684502 Freq=800, CH0 RK0
946 13:42:02.684557
947 13:42:02.684611 DATLAT Default: 0xa
948 13:42:02.684664 0, 0xFFFF, sum = 0
949 13:42:02.684719 1, 0xFFFF, sum = 0
950 13:42:02.684775 2, 0xFFFF, sum = 0
951 13:42:02.684829 3, 0xFFFF, sum = 0
952 13:42:02.684885 4, 0xFFFF, sum = 0
953 13:42:02.684940 5, 0xFFFF, sum = 0
954 13:42:02.684995 6, 0xFFFF, sum = 0
955 13:42:02.685050 7, 0xFFFF, sum = 0
956 13:42:02.685104 8, 0xFFFF, sum = 0
957 13:42:02.685158 9, 0x0, sum = 1
958 13:42:02.685213 10, 0x0, sum = 2
959 13:42:02.685295 11, 0x0, sum = 3
960 13:42:02.685384 12, 0x0, sum = 4
961 13:42:02.685441 best_step = 10
962 13:42:02.685498
963 13:42:02.685552 ==
964 13:42:02.685607 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:42:02.685661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 13:42:02.685717 ==
967 13:42:02.685771 RX Vref Scan: 1
968 13:42:02.685825
969 13:42:02.685879 Set Vref Range= 32 -> 127
970 13:42:02.685934
971 13:42:02.685987 RX Vref 32 -> 127, step: 1
972 13:42:02.686042
973 13:42:02.686096 RX Delay -111 -> 252, step: 8
974 13:42:02.686150
975 13:42:02.686204 Set Vref, RX VrefLevel [Byte0]: 32
976 13:42:02.686259 [Byte1]: 32
977 13:42:02.686313
978 13:42:02.686367 Set Vref, RX VrefLevel [Byte0]: 33
979 13:42:02.686421 [Byte1]: 33
980 13:42:02.686475
981 13:42:02.686529 Set Vref, RX VrefLevel [Byte0]: 34
982 13:42:02.686584 [Byte1]: 34
983 13:42:02.686637
984 13:42:02.686692 Set Vref, RX VrefLevel [Byte0]: 35
985 13:42:02.686745 [Byte1]: 35
986 13:42:02.686799
987 13:42:02.686853 Set Vref, RX VrefLevel [Byte0]: 36
988 13:42:02.686907 [Byte1]: 36
989 13:42:02.686961
990 13:42:02.687015 Set Vref, RX VrefLevel [Byte0]: 37
991 13:42:02.687069 [Byte1]: 37
992 13:42:02.687127
993 13:42:02.687187 Set Vref, RX VrefLevel [Byte0]: 38
994 13:42:02.687242 [Byte1]: 38
995 13:42:02.687296
996 13:42:02.687364 Set Vref, RX VrefLevel [Byte0]: 39
997 13:42:02.687422 [Byte1]: 39
998 13:42:02.687478
999 13:42:02.687534 Set Vref, RX VrefLevel [Byte0]: 40
1000 13:42:02.687589 [Byte1]: 40
1001 13:42:02.687644
1002 13:42:02.687699 Set Vref, RX VrefLevel [Byte0]: 41
1003 13:42:02.687753 [Byte1]: 41
1004 13:42:02.687808
1005 13:42:02.687862 Set Vref, RX VrefLevel [Byte0]: 42
1006 13:42:02.687916 [Byte1]: 42
1007 13:42:02.687971
1008 13:42:02.688025 Set Vref, RX VrefLevel [Byte0]: 43
1009 13:42:02.688080 [Byte1]: 43
1010 13:42:02.688134
1011 13:42:02.688189 Set Vref, RX VrefLevel [Byte0]: 44
1012 13:42:02.688244 [Byte1]: 44
1013 13:42:02.688298
1014 13:42:02.688369 Set Vref, RX VrefLevel [Byte0]: 45
1015 13:42:02.688441 [Byte1]: 45
1016 13:42:02.688495
1017 13:42:02.688550 Set Vref, RX VrefLevel [Byte0]: 46
1018 13:42:02.688606 [Byte1]: 46
1019 13:42:02.688661
1020 13:42:02.688715 Set Vref, RX VrefLevel [Byte0]: 47
1021 13:42:02.688770 [Byte1]: 47
1022 13:42:02.688824
1023 13:42:02.688878 Set Vref, RX VrefLevel [Byte0]: 48
1024 13:42:02.688933 [Byte1]: 48
1025 13:42:02.688993
1026 13:42:02.689050 Set Vref, RX VrefLevel [Byte0]: 49
1027 13:42:02.689106 [Byte1]: 49
1028 13:42:02.689161
1029 13:42:02.689215 Set Vref, RX VrefLevel [Byte0]: 50
1030 13:42:02.689295 [Byte1]: 50
1031 13:42:02.689367
1032 13:42:02.689421 Set Vref, RX VrefLevel [Byte0]: 51
1033 13:42:02.689475 [Byte1]: 51
1034 13:42:02.689531
1035 13:42:02.689586 Set Vref, RX VrefLevel [Byte0]: 52
1036 13:42:02.689640 [Byte1]: 52
1037 13:42:02.689694
1038 13:42:02.689747 Set Vref, RX VrefLevel [Byte0]: 53
1039 13:42:02.689802 [Byte1]: 53
1040 13:42:02.689856
1041 13:42:02.689909 Set Vref, RX VrefLevel [Byte0]: 54
1042 13:42:02.689963 [Byte1]: 54
1043 13:42:02.690016
1044 13:42:02.690070 Set Vref, RX VrefLevel [Byte0]: 55
1045 13:42:02.690124 [Byte1]: 55
1046 13:42:02.690177
1047 13:42:02.690231 Set Vref, RX VrefLevel [Byte0]: 56
1048 13:42:02.690285 [Byte1]: 56
1049 13:42:02.690339
1050 13:42:02.690392 Set Vref, RX VrefLevel [Byte0]: 57
1051 13:42:02.690446 [Byte1]: 57
1052 13:42:02.690499
1053 13:42:02.690552 Set Vref, RX VrefLevel [Byte0]: 58
1054 13:42:02.690606 [Byte1]: 58
1055 13:42:02.690659
1056 13:42:02.690712 Set Vref, RX VrefLevel [Byte0]: 59
1057 13:42:02.690766 [Byte1]: 59
1058 13:42:02.690819
1059 13:42:02.690873 Set Vref, RX VrefLevel [Byte0]: 60
1060 13:42:02.690927 [Byte1]: 60
1061 13:42:02.690980
1062 13:42:02.691033 Set Vref, RX VrefLevel [Byte0]: 61
1063 13:42:02.691087 [Byte1]: 61
1064 13:42:02.691140
1065 13:42:02.691194 Set Vref, RX VrefLevel [Byte0]: 62
1066 13:42:02.691248 [Byte1]: 62
1067 13:42:02.691301
1068 13:42:02.691355 Set Vref, RX VrefLevel [Byte0]: 63
1069 13:42:02.691409 [Byte1]: 63
1070 13:42:02.691463
1071 13:42:02.691516 Set Vref, RX VrefLevel [Byte0]: 64
1072 13:42:02.691570 [Byte1]: 64
1073 13:42:02.691623
1074 13:42:02.691676 Set Vref, RX VrefLevel [Byte0]: 65
1075 13:42:02.691729 [Byte1]: 65
1076 13:42:02.691783
1077 13:42:02.691836 Set Vref, RX VrefLevel [Byte0]: 66
1078 13:42:02.691890 [Byte1]: 66
1079 13:42:02.691943
1080 13:42:02.691996 Set Vref, RX VrefLevel [Byte0]: 67
1081 13:42:02.692050 [Byte1]: 67
1082 13:42:02.692103
1083 13:42:02.692156 Set Vref, RX VrefLevel [Byte0]: 68
1084 13:42:02.692210 [Byte1]: 68
1085 13:42:02.692263
1086 13:42:02.692317 Set Vref, RX VrefLevel [Byte0]: 69
1087 13:42:02.692370 [Byte1]: 69
1088 13:42:02.692423
1089 13:42:02.692476 Set Vref, RX VrefLevel [Byte0]: 70
1090 13:42:02.692721 [Byte1]: 70
1091 13:42:02.692784
1092 13:42:02.692840 Set Vref, RX VrefLevel [Byte0]: 71
1093 13:42:02.692895 [Byte1]: 71
1094 13:42:02.692949
1095 13:42:02.693003 Final RX Vref Byte 0 = 55 to rank0
1096 13:42:02.693057 Final RX Vref Byte 1 = 58 to rank0
1097 13:42:02.693112 Final RX Vref Byte 0 = 55 to rank1
1098 13:42:02.693166 Final RX Vref Byte 1 = 58 to rank1==
1099 13:42:02.693221 Dram Type= 6, Freq= 0, CH_0, rank 0
1100 13:42:02.693315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1101 13:42:02.693371 ==
1102 13:42:02.693424 DQS Delay:
1103 13:42:02.693477 DQS0 = 0, DQS1 = 0
1104 13:42:02.693531 DQM Delay:
1105 13:42:02.693585 DQM0 = 88, DQM1 = 76
1106 13:42:02.693638 DQ Delay:
1107 13:42:02.693707 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1108 13:42:02.693763 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1109 13:42:02.693817 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1110 13:42:02.693875 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1111 13:42:02.693929
1112 13:42:02.693983
1113 13:42:02.694036 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1114 13:42:02.694094 CH0 RK0: MR19=606, MR18=342D
1115 13:42:02.694147 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1116 13:42:02.694202
1117 13:42:02.694255 ----->DramcWriteLeveling(PI) begin...
1118 13:42:02.694323 ==
1119 13:42:02.694382 Dram Type= 6, Freq= 0, CH_0, rank 1
1120 13:42:02.694436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 13:42:02.694491 ==
1122 13:42:02.694545 Write leveling (Byte 0): 33 => 33
1123 13:42:02.694599 Write leveling (Byte 1): 26 => 26
1124 13:42:02.694653 DramcWriteLeveling(PI) end<-----
1125 13:42:02.694708
1126 13:42:02.694769 ==
1127 13:42:02.694825 Dram Type= 6, Freq= 0, CH_0, rank 1
1128 13:42:02.694882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 13:42:02.694939 ==
1130 13:42:02.694994 [Gating] SW mode calibration
1131 13:42:02.695048 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1132 13:42:02.695104 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1133 13:42:02.695159 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1134 13:42:02.695213 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1135 13:42:02.695268 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1136 13:42:02.695322 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1137 13:42:02.695376 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1138 13:42:02.695430 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1139 13:42:02.695484 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1140 13:42:02.695538 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1141 13:42:02.695592 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1142 13:42:02.695646 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 13:42:02.695699 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 13:42:02.695753 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 13:42:02.695807 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 13:42:02.695861 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 13:42:02.695914 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 13:42:02.695968 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:42:02.696021 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:42:02.696075 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1151 13:42:02.696128 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 13:42:02.696221 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:42:02.696327 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:42:02.696389 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:42:02.696444 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:42:02.696500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:42:02.696555 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:42:02.696610 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1159 13:42:02.696665 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1160 13:42:02.696718 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1161 13:42:02.696772 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1162 13:42:02.696826 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1163 13:42:02.696880 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1164 13:42:02.696934 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1165 13:42:02.696987 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1166 13:42:02.697041 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1167 13:42:02.697096 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
1168 13:42:02.697150 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:42:02.697204 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:42:02.697265 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:42:02.697355 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:42:02.697409 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:42:02.697463 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:42:02.697517 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1175 13:42:02.697571 0 11 8 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
1176 13:42:02.697625 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1177 13:42:02.697679 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1178 13:42:02.697733 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1179 13:42:02.697786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 13:42:02.697840 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 13:42:02.697894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 13:42:02.697947 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 13:42:02.698002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1184 13:42:02.698056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1185 13:42:02.698109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1186 13:42:02.698163 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 13:42:02.698216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 13:42:02.698459 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 13:42:02.698520 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 13:42:02.698575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 13:42:02.698629 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 13:42:02.698682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 13:42:02.698736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 13:42:02.698790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:42:02.698843 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:42:02.698897 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:42:02.698950 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:42:02.699004 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1199 13:42:02.699058 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1200 13:42:02.699112 Total UI for P1: 0, mck2ui 16
1201 13:42:02.699166 best dqsien dly found for B0: ( 0, 14, 4)
1202 13:42:02.699229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 13:42:02.699318 Total UI for P1: 0, mck2ui 16
1204 13:42:02.699408 best dqsien dly found for B1: ( 0, 14, 6)
1205 13:42:02.699496 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1206 13:42:02.699585 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1207 13:42:02.699674
1208 13:42:02.699762 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1209 13:42:02.699853 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1210 13:42:02.699942 [Gating] SW calibration Done
1211 13:42:02.700029 ==
1212 13:42:02.700117 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 13:42:02.700206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 13:42:02.700294 ==
1215 13:42:02.700381 RX Vref Scan: 0
1216 13:42:02.700468
1217 13:42:02.700555 RX Vref 0 -> 0, step: 1
1218 13:42:02.700641
1219 13:42:02.700731 RX Delay -130 -> 252, step: 16
1220 13:42:02.700819 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1221 13:42:02.700907 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1222 13:42:02.700994 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1223 13:42:02.701082 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1224 13:42:02.701170 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1225 13:42:02.701266 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1226 13:42:02.701391 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1227 13:42:02.701481 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1228 13:42:02.701568 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1229 13:42:02.701656 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1230 13:42:02.701744 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1231 13:42:02.701832 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1232 13:42:02.701921 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1233 13:42:02.702009 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1234 13:42:02.702097 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1235 13:42:02.702185 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1236 13:42:02.702271 ==
1237 13:42:02.702358 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 13:42:02.702448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 13:42:02.702535 ==
1240 13:42:02.702622 DQS Delay:
1241 13:42:02.702709 DQS0 = 0, DQS1 = 0
1242 13:42:02.702796 DQM Delay:
1243 13:42:02.702882 DQM0 = 87, DQM1 = 78
1244 13:42:02.702970 DQ Delay:
1245 13:42:02.703057 DQ0 =85, DQ1 =93, DQ2 =77, DQ3 =85
1246 13:42:02.703145 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1247 13:42:02.703232 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1248 13:42:02.703319 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1249 13:42:02.703406
1250 13:42:02.703494
1251 13:42:02.703580 ==
1252 13:42:02.703667 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 13:42:02.703752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 13:42:02.703839 ==
1255 13:42:02.703922
1256 13:42:02.704006
1257 13:42:02.704090 TX Vref Scan disable
1258 13:42:02.704174 == TX Byte 0 ==
1259 13:42:02.704257 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1260 13:42:02.704342 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1261 13:42:02.704416 == TX Byte 1 ==
1262 13:42:02.704472 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1263 13:42:02.704528 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1264 13:42:02.704582 ==
1265 13:42:02.704636 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 13:42:02.704690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 13:42:02.704745 ==
1268 13:42:02.704799 TX Vref=22, minBit 1, minWin=27, winSum=443
1269 13:42:02.704855 TX Vref=24, minBit 9, minWin=27, winSum=449
1270 13:42:02.704910 TX Vref=26, minBit 2, minWin=27, winSum=449
1271 13:42:02.704966 TX Vref=28, minBit 4, minWin=27, winSum=451
1272 13:42:02.705021 TX Vref=30, minBit 4, minWin=27, winSum=450
1273 13:42:02.705079 TX Vref=32, minBit 4, minWin=27, winSum=450
1274 13:42:02.705166 [TxChooseVref] Worse bit 4, Min win 27, Win sum 451, Final Vref 28
1275 13:42:02.705250
1276 13:42:02.705352 Final TX Range 1 Vref 28
1277 13:42:02.705408
1278 13:42:02.705462 ==
1279 13:42:02.705516 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 13:42:02.705570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 13:42:02.705624 ==
1282 13:42:02.705678
1283 13:42:02.705732
1284 13:42:02.705785 TX Vref Scan disable
1285 13:42:02.705838 == TX Byte 0 ==
1286 13:42:02.705892 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1287 13:42:02.705947 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1288 13:42:02.706001 == TX Byte 1 ==
1289 13:42:02.706055 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1290 13:42:02.706109 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1291 13:42:02.706163
1292 13:42:02.706216 [DATLAT]
1293 13:42:02.706269 Freq=800, CH0 RK1
1294 13:42:02.706323
1295 13:42:02.706376 DATLAT Default: 0xa
1296 13:42:02.706438 0, 0xFFFF, sum = 0
1297 13:42:02.706495 1, 0xFFFF, sum = 0
1298 13:42:02.706550 2, 0xFFFF, sum = 0
1299 13:42:02.706605 3, 0xFFFF, sum = 0
1300 13:42:02.706659 4, 0xFFFF, sum = 0
1301 13:42:02.706713 5, 0xFFFF, sum = 0
1302 13:42:02.706768 6, 0xFFFF, sum = 0
1303 13:42:02.706821 7, 0xFFFF, sum = 0
1304 13:42:02.706875 8, 0xFFFF, sum = 0
1305 13:42:02.706928 9, 0x0, sum = 1
1306 13:42:02.706982 10, 0x0, sum = 2
1307 13:42:02.707036 11, 0x0, sum = 3
1308 13:42:02.707090 12, 0x0, sum = 4
1309 13:42:02.707145 best_step = 10
1310 13:42:02.707198
1311 13:42:02.707251 ==
1312 13:42:02.707305 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 13:42:02.707359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 13:42:02.707413 ==
1315 13:42:02.707466 RX Vref Scan: 0
1316 13:42:02.707519
1317 13:42:02.707571 RX Vref 0 -> 0, step: 1
1318 13:42:02.707625
1319 13:42:02.707677 RX Delay -95 -> 252, step: 8
1320 13:42:02.707731 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1321 13:42:02.707784 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1322 13:42:02.707837 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1323 13:42:02.707890 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1324 13:42:02.708136 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1325 13:42:02.708196 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1326 13:42:02.708251 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1327 13:42:02.708305 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1328 13:42:02.708358 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1329 13:42:02.708411 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1330 13:42:02.708464 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1331 13:42:02.708518 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1332 13:42:02.708571 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1333 13:42:02.708624 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1334 13:42:02.708677 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1335 13:42:02.708732 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1336 13:42:02.708785 ==
1337 13:42:02.708838 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 13:42:02.708891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 13:42:02.708945 ==
1340 13:42:02.708998 DQS Delay:
1341 13:42:02.709070 DQS0 = 0, DQS1 = 0
1342 13:42:02.709153 DQM Delay:
1343 13:42:02.709235 DQM0 = 86, DQM1 = 76
1344 13:42:02.709348 DQ Delay:
1345 13:42:02.709404 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1346 13:42:02.709458 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1347 13:42:02.709511 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1348 13:42:02.709564 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1349 13:42:02.709617
1350 13:42:02.709670
1351 13:42:02.709722 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1352 13:42:02.709777 CH0 RK1: MR19=606, MR18=2E2B
1353 13:42:02.709830 CH0_RK1: MR19=0x606, MR18=0x2E2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1354 13:42:02.709884 [RxdqsGatingPostProcess] freq 800
1355 13:42:02.709938 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1356 13:42:02.709991 Pre-setting of DQS Precalculation
1357 13:42:02.710044 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1358 13:42:02.710098 ==
1359 13:42:02.710152 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 13:42:02.710205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 13:42:02.710258 ==
1362 13:42:02.710311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1363 13:42:02.710365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1364 13:42:02.710419 [CA 0] Center 37 (6~68) winsize 63
1365 13:42:02.710472 [CA 1] Center 37 (6~68) winsize 63
1366 13:42:02.710525 [CA 2] Center 34 (4~65) winsize 62
1367 13:42:02.710577 [CA 3] Center 34 (4~65) winsize 62
1368 13:42:02.710630 [CA 4] Center 34 (4~65) winsize 62
1369 13:42:02.710683 [CA 5] Center 33 (3~64) winsize 62
1370 13:42:02.710736
1371 13:42:02.710789 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1372 13:42:02.710842
1373 13:42:02.710895 [CATrainingPosCal] consider 1 rank data
1374 13:42:02.710949 u2DelayCellTimex100 = 270/100 ps
1375 13:42:02.711003 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1376 13:42:02.711056 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1377 13:42:02.711109 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1378 13:42:02.711167 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1379 13:42:02.711234 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1380 13:42:02.711293 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1381 13:42:02.711348
1382 13:42:02.711401 CA PerBit enable=1, Macro0, CA PI delay=33
1383 13:42:02.711454
1384 13:42:02.711511 [CBTSetCACLKResult] CA Dly = 33
1385 13:42:02.711564 CS Dly: 5 (0~36)
1386 13:42:02.711617 ==
1387 13:42:02.711681 Dram Type= 6, Freq= 0, CH_1, rank 1
1388 13:42:02.711764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 13:42:02.711849 ==
1390 13:42:02.711933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1391 13:42:02.712018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1392 13:42:02.712080 [CA 0] Center 36 (6~67) winsize 62
1393 13:42:02.712134 [CA 1] Center 36 (6~67) winsize 62
1394 13:42:02.712188 [CA 2] Center 34 (4~65) winsize 62
1395 13:42:02.712241 [CA 3] Center 34 (3~65) winsize 63
1396 13:42:02.712294 [CA 4] Center 34 (3~65) winsize 63
1397 13:42:02.712346 [CA 5] Center 33 (3~64) winsize 62
1398 13:42:02.712399
1399 13:42:02.712452 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1400 13:42:02.712504
1401 13:42:02.712557 [CATrainingPosCal] consider 2 rank data
1402 13:42:02.712610 u2DelayCellTimex100 = 270/100 ps
1403 13:42:02.712663 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1404 13:42:02.712716 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1405 13:42:02.712769 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1406 13:42:02.712822 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1407 13:42:02.712875 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1408 13:42:02.712928 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1409 13:42:02.712980
1410 13:42:02.713033 CA PerBit enable=1, Macro0, CA PI delay=33
1411 13:42:02.713086
1412 13:42:02.713139 [CBTSetCACLKResult] CA Dly = 33
1413 13:42:02.713192 CS Dly: 5 (0~37)
1414 13:42:02.713245
1415 13:42:02.713341 ----->DramcWriteLeveling(PI) begin...
1416 13:42:02.713396 ==
1417 13:42:02.713449 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 13:42:02.713503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 13:42:02.713556 ==
1420 13:42:02.713610 Write leveling (Byte 0): 27 => 27
1421 13:42:02.713663 Write leveling (Byte 1): 27 => 27
1422 13:42:02.713716 DramcWriteLeveling(PI) end<-----
1423 13:42:02.713768
1424 13:42:02.713821 ==
1425 13:42:02.713873 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 13:42:02.713927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 13:42:02.713981 ==
1428 13:42:02.714034 [Gating] SW mode calibration
1429 13:42:02.714087 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1430 13:42:02.714142 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1431 13:42:02.714195 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1432 13:42:02.714284 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1433 13:42:02.714342 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1434 13:42:02.714397 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 13:42:02.714451 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 13:42:02.714505 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 13:42:02.714558 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 13:42:02.714611 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 13:42:02.714665 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 13:42:02.714717 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 13:42:02.714965 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 13:42:02.715029 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 13:42:02.715084 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 13:42:02.715137 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 13:42:02.715190 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 13:42:02.715244 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 13:42:02.715297 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:42:02.715350 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1449 13:42:02.715404 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 13:42:02.715458 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:42:02.715512 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:42:02.715565 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:42:02.715618 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:42:02.715671 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:42:02.715724 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:42:02.715777 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1457 13:42:02.715830 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1458 13:42:02.715883 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1459 13:42:02.715936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1460 13:42:02.715989 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1461 13:42:02.716042 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1462 13:42:02.716095 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1463 13:42:02.716148 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1464 13:42:02.716201 0 10 4 | B1->B0 | 3333 3131 | 0 1 | (0 0) (1 0)
1465 13:42:02.716254 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1466 13:42:02.716320 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:42:02.716376 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:42:02.716429 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:42:02.716491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:42:02.716548 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:42:02.716601 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:42:02.716654 0 11 4 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
1473 13:42:02.716710 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1474 13:42:02.716764 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1475 13:42:02.716818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1476 13:42:02.716871 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1477 13:42:02.716924 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1478 13:42:02.716977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1479 13:42:02.717030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 13:42:02.717083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1481 13:42:02.717136 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1482 13:42:02.717189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1483 13:42:02.717243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1484 13:42:02.717332 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1485 13:42:02.717400 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1486 13:42:02.717453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1487 13:42:02.717506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 13:42:02.717559 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 13:42:02.717613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 13:42:02.717666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 13:42:02.717719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 13:42:02.717772 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 13:42:02.717825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 13:42:02.717878 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:42:02.717931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:42:02.717984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1497 13:42:02.718037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:42:02.718090 Total UI for P1: 0, mck2ui 16
1499 13:42:02.718143 best dqsien dly found for B0: ( 0, 14, 4)
1500 13:42:02.718196 Total UI for P1: 0, mck2ui 16
1501 13:42:02.718250 best dqsien dly found for B1: ( 0, 14, 4)
1502 13:42:02.718303 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1503 13:42:02.718356 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1504 13:42:02.718409
1505 13:42:02.718461 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1506 13:42:02.718514 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1507 13:42:02.718566 [Gating] SW calibration Done
1508 13:42:02.718619 ==
1509 13:42:02.718672 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 13:42:02.718725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 13:42:02.718779 ==
1512 13:42:02.718832 RX Vref Scan: 0
1513 13:42:02.718884
1514 13:42:02.718937 RX Vref 0 -> 0, step: 1
1515 13:42:02.718989
1516 13:42:02.719041 RX Delay -130 -> 252, step: 16
1517 13:42:02.719095 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1518 13:42:02.719148 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1519 13:42:02.719202 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1520 13:42:02.719255 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1521 13:42:02.719308 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1522 13:42:02.719361 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1523 13:42:02.719414 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1524 13:42:02.719468 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1525 13:42:02.719521 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1526 13:42:02.719574 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1527 13:42:02.719626 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1528 13:42:02.719679 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1529 13:42:02.719732 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1530 13:42:02.719785 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1531 13:42:02.720029 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1532 13:42:02.720090 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1533 13:42:02.720145 ==
1534 13:42:02.720199 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 13:42:02.720252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 13:42:02.720309 ==
1537 13:42:02.720363 DQS Delay:
1538 13:42:02.720416 DQS0 = 0, DQS1 = 0
1539 13:42:02.720470 DQM Delay:
1540 13:42:02.720531 DQM0 = 86, DQM1 = 80
1541 13:42:02.720587 DQ Delay:
1542 13:42:02.720640 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1543 13:42:02.720697 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1544 13:42:02.720758 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1545 13:42:02.720812 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1546 13:42:02.720865
1547 13:42:02.720929
1548 13:42:02.720983 ==
1549 13:42:02.721037 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 13:42:02.721100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 13:42:02.721184 ==
1552 13:42:02.721295
1553 13:42:02.721367
1554 13:42:02.721421 TX Vref Scan disable
1555 13:42:02.721483 == TX Byte 0 ==
1556 13:42:02.721537 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1557 13:42:02.721591 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1558 13:42:02.721652 == TX Byte 1 ==
1559 13:42:02.721736 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1560 13:42:02.721821 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1561 13:42:02.721905 ==
1562 13:42:02.721987 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 13:42:02.722047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 13:42:02.722101 ==
1565 13:42:02.722154 TX Vref=22, minBit 0, minWin=27, winSum=446
1566 13:42:02.722208 TX Vref=24, minBit 2, minWin=27, winSum=445
1567 13:42:02.722261 TX Vref=26, minBit 1, minWin=27, winSum=451
1568 13:42:02.722314 TX Vref=28, minBit 1, minWin=27, winSum=454
1569 13:42:02.722368 TX Vref=30, minBit 1, minWin=27, winSum=452
1570 13:42:02.722421 TX Vref=32, minBit 1, minWin=27, winSum=453
1571 13:42:02.722475 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
1572 13:42:02.722528
1573 13:42:02.722581 Final TX Range 1 Vref 28
1574 13:42:02.722634
1575 13:42:02.722686 ==
1576 13:42:02.722739 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 13:42:02.722792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 13:42:02.722846 ==
1579 13:42:02.722899
1580 13:42:02.722951
1581 13:42:02.723003 TX Vref Scan disable
1582 13:42:02.723056 == TX Byte 0 ==
1583 13:42:02.723108 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1584 13:42:02.723161 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1585 13:42:02.723214 == TX Byte 1 ==
1586 13:42:02.723266 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1587 13:42:02.723320 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1588 13:42:02.723382
1589 13:42:02.723438 [DATLAT]
1590 13:42:02.723491 Freq=800, CH1 RK0
1591 13:42:02.723548
1592 13:42:02.723601 DATLAT Default: 0xa
1593 13:42:02.723655 0, 0xFFFF, sum = 0
1594 13:42:02.723709 1, 0xFFFF, sum = 0
1595 13:42:02.723768 2, 0xFFFF, sum = 0
1596 13:42:02.723824 3, 0xFFFF, sum = 0
1597 13:42:02.723878 4, 0xFFFF, sum = 0
1598 13:42:02.723932 5, 0xFFFF, sum = 0
1599 13:42:02.724002 6, 0xFFFF, sum = 0
1600 13:42:02.724088 7, 0xFFFF, sum = 0
1601 13:42:02.724172 8, 0xFFFF, sum = 0
1602 13:42:02.724260 9, 0x0, sum = 1
1603 13:42:02.724319 10, 0x0, sum = 2
1604 13:42:02.724377 11, 0x0, sum = 3
1605 13:42:02.724434 12, 0x0, sum = 4
1606 13:42:02.724490 best_step = 10
1607 13:42:02.724542
1608 13:42:02.724595 ==
1609 13:42:02.724648 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 13:42:02.724702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 13:42:02.724755 ==
1612 13:42:02.724809 RX Vref Scan: 1
1613 13:42:02.724862
1614 13:42:02.724914 Set Vref Range= 32 -> 127
1615 13:42:02.724967
1616 13:42:02.725020 RX Vref 32 -> 127, step: 1
1617 13:42:02.725073
1618 13:42:02.725126 RX Delay -95 -> 252, step: 8
1619 13:42:02.725179
1620 13:42:02.725233 Set Vref, RX VrefLevel [Byte0]: 32
1621 13:42:02.725344 [Byte1]: 32
1622 13:42:02.725399
1623 13:42:02.725451 Set Vref, RX VrefLevel [Byte0]: 33
1624 13:42:02.725505 [Byte1]: 33
1625 13:42:02.725558
1626 13:42:02.725610 Set Vref, RX VrefLevel [Byte0]: 34
1627 13:42:02.725663 [Byte1]: 34
1628 13:42:02.725716
1629 13:42:02.725770 Set Vref, RX VrefLevel [Byte0]: 35
1630 13:42:02.725823 [Byte1]: 35
1631 13:42:02.725876
1632 13:42:02.725928 Set Vref, RX VrefLevel [Byte0]: 36
1633 13:42:02.725982 [Byte1]: 36
1634 13:42:02.726035
1635 13:42:02.726087 Set Vref, RX VrefLevel [Byte0]: 37
1636 13:42:02.726140 [Byte1]: 37
1637 13:42:02.726192
1638 13:42:02.726245 Set Vref, RX VrefLevel [Byte0]: 38
1639 13:42:02.726298 [Byte1]: 38
1640 13:42:02.726351
1641 13:42:02.726403 Set Vref, RX VrefLevel [Byte0]: 39
1642 13:42:02.726456 [Byte1]: 39
1643 13:42:02.726509
1644 13:42:02.726561 Set Vref, RX VrefLevel [Byte0]: 40
1645 13:42:02.726614 [Byte1]: 40
1646 13:42:02.726668
1647 13:42:02.726721 Set Vref, RX VrefLevel [Byte0]: 41
1648 13:42:02.726774 [Byte1]: 41
1649 13:42:02.726827
1650 13:42:02.726880 Set Vref, RX VrefLevel [Byte0]: 42
1651 13:42:02.726932 [Byte1]: 42
1652 13:42:02.726985
1653 13:42:02.727037 Set Vref, RX VrefLevel [Byte0]: 43
1654 13:42:02.727090 [Byte1]: 43
1655 13:42:02.727142
1656 13:42:02.727195 Set Vref, RX VrefLevel [Byte0]: 44
1657 13:42:02.727247 [Byte1]: 44
1658 13:42:02.727301
1659 13:42:02.727353 Set Vref, RX VrefLevel [Byte0]: 45
1660 13:42:02.727406 [Byte1]: 45
1661 13:42:02.727459
1662 13:42:02.727512 Set Vref, RX VrefLevel [Byte0]: 46
1663 13:42:02.727565 [Byte1]: 46
1664 13:42:02.727618
1665 13:42:02.727670 Set Vref, RX VrefLevel [Byte0]: 47
1666 13:42:02.727723 [Byte1]: 47
1667 13:42:02.727776
1668 13:42:02.727828 Set Vref, RX VrefLevel [Byte0]: 48
1669 13:42:02.727882 [Byte1]: 48
1670 13:42:02.727934
1671 13:42:02.727986 Set Vref, RX VrefLevel [Byte0]: 49
1672 13:42:02.728039 [Byte1]: 49
1673 13:42:02.728091
1674 13:42:02.728143 Set Vref, RX VrefLevel [Byte0]: 50
1675 13:42:02.728196 [Byte1]: 50
1676 13:42:02.728248
1677 13:42:02.728301 Set Vref, RX VrefLevel [Byte0]: 51
1678 13:42:02.728354 [Byte1]: 51
1679 13:42:02.728407
1680 13:42:02.728459 Set Vref, RX VrefLevel [Byte0]: 52
1681 13:42:02.728512 [Byte1]: 52
1682 13:42:02.728565
1683 13:42:02.728618 Set Vref, RX VrefLevel [Byte0]: 53
1684 13:42:02.728671 [Byte1]: 53
1685 13:42:02.728724
1686 13:42:02.728777 Set Vref, RX VrefLevel [Byte0]: 54
1687 13:42:02.728829 [Byte1]: 54
1688 13:42:02.728883
1689 13:42:02.728936 Set Vref, RX VrefLevel [Byte0]: 55
1690 13:42:02.728989 [Byte1]: 55
1691 13:42:02.729041
1692 13:42:02.729094 Set Vref, RX VrefLevel [Byte0]: 56
1693 13:42:02.729146 [Byte1]: 56
1694 13:42:02.729199
1695 13:42:02.729251 Set Vref, RX VrefLevel [Byte0]: 57
1696 13:42:02.729347 [Byte1]: 57
1697 13:42:02.729401
1698 13:42:02.729646 Set Vref, RX VrefLevel [Byte0]: 58
1699 13:42:02.729707 [Byte1]: 58
1700 13:42:02.729762
1701 13:42:02.729817 Set Vref, RX VrefLevel [Byte0]: 59
1702 13:42:02.729875 [Byte1]: 59
1703 13:42:02.729932
1704 13:42:02.729988 Set Vref, RX VrefLevel [Byte0]: 60
1705 13:42:02.730042 [Byte1]: 60
1706 13:42:02.730096
1707 13:42:02.730149 Set Vref, RX VrefLevel [Byte0]: 61
1708 13:42:02.730204 [Byte1]: 61
1709 13:42:02.730258
1710 13:42:02.730311 Set Vref, RX VrefLevel [Byte0]: 62
1711 13:42:02.730370 [Byte1]: 62
1712 13:42:02.730424
1713 13:42:02.730476 Set Vref, RX VrefLevel [Byte0]: 63
1714 13:42:02.730532 [Byte1]: 63
1715 13:42:02.730586
1716 13:42:02.730639 Set Vref, RX VrefLevel [Byte0]: 64
1717 13:42:02.730692 [Byte1]: 64
1718 13:42:02.730749
1719 13:42:02.730801 Set Vref, RX VrefLevel [Byte0]: 65
1720 13:42:02.730854 [Byte1]: 65
1721 13:42:02.730909
1722 13:42:02.730962 Set Vref, RX VrefLevel [Byte0]: 66
1723 13:42:02.731015 [Byte1]: 66
1724 13:42:02.731068
1725 13:42:02.731124 Set Vref, RX VrefLevel [Byte0]: 67
1726 13:42:02.731177 [Byte1]: 67
1727 13:42:02.731230
1728 13:42:02.731285 Set Vref, RX VrefLevel [Byte0]: 68
1729 13:42:02.731339 [Byte1]: 68
1730 13:42:02.731393
1731 13:42:02.731446 Set Vref, RX VrefLevel [Byte0]: 69
1732 13:42:02.731498 [Byte1]: 69
1733 13:42:02.731551
1734 13:42:02.731603 Set Vref, RX VrefLevel [Byte0]: 70
1735 13:42:02.731655 [Byte1]: 70
1736 13:42:02.731708
1737 13:42:02.731760 Set Vref, RX VrefLevel [Byte0]: 71
1738 13:42:02.731813 [Byte1]: 71
1739 13:42:02.731866
1740 13:42:02.731918 Set Vref, RX VrefLevel [Byte0]: 72
1741 13:42:02.731971 [Byte1]: 72
1742 13:42:02.732024
1743 13:42:02.732076 Set Vref, RX VrefLevel [Byte0]: 73
1744 13:42:02.732129 [Byte1]: 73
1745 13:42:02.732182
1746 13:42:02.732234 Set Vref, RX VrefLevel [Byte0]: 74
1747 13:42:02.732287 [Byte1]: 74
1748 13:42:02.732340
1749 13:42:02.732392 Set Vref, RX VrefLevel [Byte0]: 75
1750 13:42:02.732445 [Byte1]: 75
1751 13:42:02.732497
1752 13:42:02.732550 Final RX Vref Byte 0 = 56 to rank0
1753 13:42:02.732603 Final RX Vref Byte 1 = 56 to rank0
1754 13:42:02.732656 Final RX Vref Byte 0 = 56 to rank1
1755 13:42:02.732709 Final RX Vref Byte 1 = 56 to rank1==
1756 13:42:02.732763 Dram Type= 6, Freq= 0, CH_1, rank 0
1757 13:42:02.732815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1758 13:42:02.732869 ==
1759 13:42:02.732922 DQS Delay:
1760 13:42:02.732975 DQS0 = 0, DQS1 = 0
1761 13:42:02.733027 DQM Delay:
1762 13:42:02.733079 DQM0 = 85, DQM1 = 80
1763 13:42:02.733132 DQ Delay:
1764 13:42:02.733184 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1765 13:42:02.733237 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1766 13:42:02.733354 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1767 13:42:02.733438 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =84
1768 13:42:02.733520
1769 13:42:02.733602
1770 13:42:02.733686 [DQSOSCAuto] RK0, (LSB)MR18= 0x182c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1771 13:42:02.733769 CH1 RK0: MR19=606, MR18=182C
1772 13:42:02.733854 CH1_RK0: MR19=0x606, MR18=0x182C, DQSOSC=398, MR23=63, INC=93, DEC=62
1773 13:42:02.733937
1774 13:42:02.734020 ----->DramcWriteLeveling(PI) begin...
1775 13:42:02.734103 ==
1776 13:42:02.734186 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 13:42:02.734269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 13:42:02.734352 ==
1779 13:42:02.734435 Write leveling (Byte 0): 25 => 25
1780 13:42:02.734518 Write leveling (Byte 1): 31 => 31
1781 13:42:02.734600 DramcWriteLeveling(PI) end<-----
1782 13:42:02.734682
1783 13:42:02.734764 ==
1784 13:42:02.734847 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 13:42:02.734930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 13:42:02.735012 ==
1787 13:42:02.735094 [Gating] SW mode calibration
1788 13:42:02.735178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1789 13:42:02.735263 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1790 13:42:02.735346 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1791 13:42:02.735430 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1792 13:42:02.735513 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1793 13:42:02.735597 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1794 13:42:02.735680 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1795 13:42:02.735763 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 13:42:02.735846 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 13:42:02.735929 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 13:42:02.736012 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 13:42:02.736095 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 13:42:02.736179 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 13:42:02.736268 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 13:42:02.736353 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 13:42:02.736436 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 13:42:02.736519 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 13:42:02.736602 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:42:02.736685 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1807 13:42:02.736768 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1808 13:42:02.736852 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1809 13:42:02.736936 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:42:02.737018 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:42:02.737102 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:42:02.737185 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:42:02.737290 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:42:02.737360 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:42:02.737414 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1816 13:42:02.737468 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1817 13:42:02.737521 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1818 13:42:02.737575 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1819 13:42:02.737628 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1820 13:42:02.737680 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 13:42:02.737927 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 13:42:02.737989 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1823 13:42:02.738044 0 10 4 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1824 13:42:02.738098 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1825 13:42:02.738150 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:42:02.738203 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:42:02.738257 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:42:02.738310 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:42:02.738363 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:42:02.738416 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1831 13:42:02.738469 0 11 4 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
1832 13:42:02.738522 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
1833 13:42:02.738575 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1834 13:42:02.738628 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1835 13:42:02.738681 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1836 13:42:02.738735 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 13:42:02.738788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 13:42:02.738841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 13:42:02.738894 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1840 13:42:02.738946 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1841 13:42:02.739000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1842 13:42:02.739054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1843 13:42:02.739107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 13:42:02.739160 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 13:42:02.739213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 13:42:02.739267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 13:42:02.739320 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 13:42:02.739373 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 13:42:02.739425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 13:42:02.739478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 13:42:02.739530 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 13:42:02.739613 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 13:42:02.739696 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:42:02.739787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1855 13:42:02.739873 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1856 13:42:02.739956 Total UI for P1: 0, mck2ui 16
1857 13:42:02.740048 best dqsien dly found for B0: ( 0, 14, 0)
1858 13:42:02.740140 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1859 13:42:02.740201 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 13:42:02.740255 Total UI for P1: 0, mck2ui 16
1861 13:42:02.740309 best dqsien dly found for B1: ( 0, 14, 6)
1862 13:42:02.740363 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1863 13:42:02.740421 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1864 13:42:02.740475
1865 13:42:02.740528 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1866 13:42:02.740585 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1867 13:42:02.740640 [Gating] SW calibration Done
1868 13:42:02.740693 ==
1869 13:42:02.740747 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 13:42:02.740830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 13:42:02.740913 ==
1872 13:42:02.740997 RX Vref Scan: 0
1873 13:42:02.741079
1874 13:42:02.741162 RX Vref 0 -> 0, step: 1
1875 13:42:02.741244
1876 13:42:02.741344 RX Delay -130 -> 252, step: 16
1877 13:42:02.741398 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1878 13:42:02.741454 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1879 13:42:02.741507 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1880 13:42:02.741560 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1881 13:42:02.741613 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1882 13:42:02.741665 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1883 13:42:02.741718 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1884 13:42:02.741770 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1885 13:42:02.741823 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1886 13:42:02.741875 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1887 13:42:02.741928 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1888 13:42:02.741982 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1889 13:42:02.742035 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1890 13:42:02.742088 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1891 13:42:02.742141 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1892 13:42:02.742194 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1893 13:42:02.742247 ==
1894 13:42:02.742300 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 13:42:02.742354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 13:42:02.742407 ==
1897 13:42:02.742460 DQS Delay:
1898 13:42:02.742513 DQS0 = 0, DQS1 = 0
1899 13:42:02.742566 DQM Delay:
1900 13:42:02.742618 DQM0 = 84, DQM1 = 82
1901 13:42:02.742671 DQ Delay:
1902 13:42:02.742724 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1903 13:42:02.742776 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1904 13:42:02.742829 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1905 13:42:02.742882 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1906 13:42:02.742935
1907 13:42:02.742987
1908 13:42:02.743039 ==
1909 13:42:02.743092 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 13:42:02.743145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 13:42:02.743198 ==
1912 13:42:02.743251
1913 13:42:02.743303
1914 13:42:02.743355 TX Vref Scan disable
1915 13:42:02.743408 == TX Byte 0 ==
1916 13:42:02.743461 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1917 13:42:02.743515 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1918 13:42:03.027193 == TX Byte 1 ==
1919 13:42:03.027687 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1920 13:42:03.028031 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1921 13:42:03.028347 ==
1922 13:42:03.028649 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 13:42:03.028947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 13:42:03.029240 ==
1925 13:42:03.029568 TX Vref=22, minBit 1, minWin=27, winSum=444
1926 13:42:03.029861 TX Vref=24, minBit 1, minWin=27, winSum=449
1927 13:42:03.030148 TX Vref=26, minBit 4, minWin=27, winSum=453
1928 13:42:03.030813 TX Vref=28, minBit 0, minWin=28, winSum=457
1929 13:42:03.031187 TX Vref=30, minBit 6, minWin=27, winSum=453
1930 13:42:03.031534 TX Vref=32, minBit 0, minWin=27, winSum=450
1931 13:42:03.031832 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1932 13:42:03.032125
1933 13:42:03.032409 Final TX Range 1 Vref 28
1934 13:42:03.032713
1935 13:42:03.033060 ==
1936 13:42:03.033382 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 13:42:03.033671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 13:42:03.033959 ==
1939 13:42:03.034357
1940 13:42:03.034814
1941 13:42:03.035112 TX Vref Scan disable
1942 13:42:03.035395 == TX Byte 0 ==
1943 13:42:03.035674 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1944 13:42:03.036170 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1945 13:42:03.036611 == TX Byte 1 ==
1946 13:42:03.037045 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1947 13:42:03.037517 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1948 13:42:03.037992
1949 13:42:03.038423 [DATLAT]
1950 13:42:03.038848 Freq=800, CH1 RK1
1951 13:42:03.039273
1952 13:42:03.039697 DATLAT Default: 0xa
1953 13:42:03.040120 0, 0xFFFF, sum = 0
1954 13:42:03.040556 1, 0xFFFF, sum = 0
1955 13:42:03.041018 2, 0xFFFF, sum = 0
1956 13:42:03.041586 3, 0xFFFF, sum = 0
1957 13:42:03.041902 4, 0xFFFF, sum = 0
1958 13:42:03.042281 5, 0xFFFF, sum = 0
1959 13:42:03.042583 6, 0xFFFF, sum = 0
1960 13:42:03.042868 7, 0xFFFF, sum = 0
1961 13:42:03.043149 8, 0xFFFF, sum = 0
1962 13:42:03.043427 9, 0x0, sum = 1
1963 13:42:03.043707 10, 0x0, sum = 2
1964 13:42:03.043990 11, 0x0, sum = 3
1965 13:42:03.044265 12, 0x0, sum = 4
1966 13:42:03.044544 best_step = 10
1967 13:42:03.044817
1968 13:42:03.045091 ==
1969 13:42:03.045465 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 13:42:03.045754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 13:42:03.046031 ==
1972 13:42:03.046306 RX Vref Scan: 0
1973 13:42:03.046578
1974 13:42:03.046851 RX Vref 0 -> 0, step: 1
1975 13:42:03.047125
1976 13:42:03.047461 RX Delay -95 -> 252, step: 8
1977 13:42:03.047746 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1978 13:42:03.048024 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1979 13:42:03.048328 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1980 13:42:03.048609 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1981 13:42:03.048885 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1982 13:42:03.049162 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1983 13:42:03.049486 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1984 13:42:03.049768 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1985 13:42:03.050040 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1986 13:42:03.050339 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1987 13:42:03.050617 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1988 13:42:03.050893 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1989 13:42:03.051168 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1990 13:42:03.051441 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1991 13:42:03.051715 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1992 13:42:03.051989 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1993 13:42:03.052285 ==
1994 13:42:03.052564 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 13:42:03.052840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 13:42:03.053117 ==
1997 13:42:03.053445 DQS Delay:
1998 13:42:03.053725 DQS0 = 0, DQS1 = 0
1999 13:42:03.053999 DQM Delay:
2000 13:42:03.054305 DQM0 = 86, DQM1 = 81
2001 13:42:03.054584 DQ Delay:
2002 13:42:03.054858 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2003 13:42:03.055134 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2004 13:42:03.055409 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2005 13:42:03.055681 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2006 13:42:03.055955
2007 13:42:03.056347
2008 13:42:03.056718 [DQSOSCAuto] RK1, (LSB)MR18= 0x213d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2009 13:42:03.056928 CH1 RK1: MR19=606, MR18=213D
2010 13:42:03.057129 CH1_RK1: MR19=0x606, MR18=0x213D, DQSOSC=394, MR23=63, INC=95, DEC=63
2011 13:42:03.057359 [RxdqsGatingPostProcess] freq 800
2012 13:42:03.057563 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2013 13:42:03.057764 Pre-setting of DQS Precalculation
2014 13:42:03.057991 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2015 13:42:03.058214 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2016 13:42:03.058417 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2017 13:42:03.058617
2018 13:42:03.058816
2019 13:42:03.059013 [Calibration Summary] 1600 Mbps
2020 13:42:03.059212 CH 0, Rank 0
2021 13:42:03.059411 SW Impedance : PASS
2022 13:42:03.059609 DUTY Scan : NO K
2023 13:42:03.059809 ZQ Calibration : PASS
2024 13:42:03.060006 Jitter Meter : NO K
2025 13:42:03.060231 CBT Training : PASS
2026 13:42:03.060430 Write leveling : PASS
2027 13:42:03.060630 RX DQS gating : PASS
2028 13:42:03.060826 RX DQ/DQS(RDDQC) : PASS
2029 13:42:03.061024 TX DQ/DQS : PASS
2030 13:42:03.061220 RX DATLAT : PASS
2031 13:42:03.061453 RX DQ/DQS(Engine): PASS
2032 13:42:03.061645 TX OE : NO K
2033 13:42:03.061796 All Pass.
2034 13:42:03.061943
2035 13:42:03.062118 CH 0, Rank 1
2036 13:42:03.062358 SW Impedance : PASS
2037 13:42:03.062519 DUTY Scan : NO K
2038 13:42:03.062672 ZQ Calibration : PASS
2039 13:42:03.062823 Jitter Meter : NO K
2040 13:42:03.062974 CBT Training : PASS
2041 13:42:03.063121 Write leveling : PASS
2042 13:42:03.063270 RX DQS gating : PASS
2043 13:42:03.063418 RX DQ/DQS(RDDQC) : PASS
2044 13:42:03.063566 TX DQ/DQS : PASS
2045 13:42:03.063715 RX DATLAT : PASS
2046 13:42:03.063864 RX DQ/DQS(Engine): PASS
2047 13:42:03.064012 TX OE : NO K
2048 13:42:03.064161 All Pass.
2049 13:42:03.064311
2050 13:42:03.064459 CH 1, Rank 0
2051 13:42:03.064606 SW Impedance : PASS
2052 13:42:03.064754 DUTY Scan : NO K
2053 13:42:03.064901 ZQ Calibration : PASS
2054 13:42:03.065049 Jitter Meter : NO K
2055 13:42:03.065196 CBT Training : PASS
2056 13:42:03.065373 Write leveling : PASS
2057 13:42:03.065524 RX DQS gating : PASS
2058 13:42:03.065673 RX DQ/DQS(RDDQC) : PASS
2059 13:42:03.065822 TX DQ/DQS : PASS
2060 13:42:03.065970 RX DATLAT : PASS
2061 13:42:03.066119 RX DQ/DQS(Engine): PASS
2062 13:42:03.066268 TX OE : NO K
2063 13:42:03.066418 All Pass.
2064 13:42:03.066580
2065 13:42:03.066699 CH 1, Rank 1
2066 13:42:03.066819 SW Impedance : PASS
2067 13:42:03.066940 DUTY Scan : NO K
2068 13:42:03.067057 ZQ Calibration : PASS
2069 13:42:03.067176 Jitter Meter : NO K
2070 13:42:03.067295 CBT Training : PASS
2071 13:42:03.067413 Write leveling : PASS
2072 13:42:03.067532 RX DQS gating : PASS
2073 13:42:03.067651 RX DQ/DQS(RDDQC) : PASS
2074 13:42:03.067769 TX DQ/DQS : PASS
2075 13:42:03.067888 RX DATLAT : PASS
2076 13:42:03.068006 RX DQ/DQS(Engine): PASS
2077 13:42:03.068123 TX OE : NO K
2078 13:42:03.068241 All Pass.
2079 13:42:03.068361
2080 13:42:03.068477 DramC Write-DBI off
2081 13:42:03.068597 PER_BANK_REFRESH: Hybrid Mode
2082 13:42:03.068715 TX_TRACKING: ON
2083 13:42:03.069113 [GetDramInforAfterCalByMRR] Vendor 6.
2084 13:42:03.069249 [GetDramInforAfterCalByMRR] Revision 606.
2085 13:42:03.069403 [GetDramInforAfterCalByMRR] Revision 2 0.
2086 13:42:03.069526 MR0 0x3b3b
2087 13:42:03.069646 MR8 0x5151
2088 13:42:03.069768 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2089 13:42:03.069890
2090 13:42:03.070011 MR0 0x3b3b
2091 13:42:03.070130 MR8 0x5151
2092 13:42:03.070249 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2093 13:42:03.070369
2094 13:42:03.070529 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2095 13:42:03.070667 [FAST_K] Save calibration result to emmc
2096 13:42:03.070791 [FAST_K] Save calibration result to emmc
2097 13:42:03.070911 dram_init: config_dvfs: 1
2098 13:42:03.071033 dramc_set_vcore_voltage set vcore to 662500
2099 13:42:03.071154 Read voltage for 1200, 2
2100 13:42:03.071273 Vio18 = 0
2101 13:42:03.071392 Vcore = 662500
2102 13:42:03.071511 Vdram = 0
2103 13:42:03.071639 Vddq = 0
2104 13:42:03.071738 Vmddr = 0
2105 13:42:03.071837 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2106 13:42:03.071939 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2107 13:42:03.072040 MEM_TYPE=3, freq_sel=15
2108 13:42:03.072171 sv_algorithm_assistance_LP4_1600
2109 13:42:03.072277 ============ PULL DRAM RESETB DOWN ============
2110 13:42:03.072383 ========== PULL DRAM RESETB DOWN end =========
2111 13:42:03.072484 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2112 13:42:03.072585 ===================================
2113 13:42:03.072685 LPDDR4 DRAM CONFIGURATION
2114 13:42:03.072785 ===================================
2115 13:42:03.072886 EX_ROW_EN[0] = 0x0
2116 13:42:03.072985 EX_ROW_EN[1] = 0x0
2117 13:42:03.073085 LP4Y_EN = 0x0
2118 13:42:03.073185 WORK_FSP = 0x0
2119 13:42:03.073298 WL = 0x4
2120 13:42:03.073401 RL = 0x4
2121 13:42:03.073502 BL = 0x2
2122 13:42:03.073632 RPST = 0x0
2123 13:42:03.073736 RD_PRE = 0x0
2124 13:42:03.073840 WR_PRE = 0x1
2125 13:42:03.073939 WR_PST = 0x0
2126 13:42:03.074039 DBI_WR = 0x0
2127 13:42:03.074139 DBI_RD = 0x0
2128 13:42:03.074239 OTF = 0x1
2129 13:42:03.074341 ===================================
2130 13:42:03.074441 ===================================
2131 13:42:03.074542 ANA top config
2132 13:42:03.074641 ===================================
2133 13:42:03.074742 DLL_ASYNC_EN = 0
2134 13:42:03.074842 ALL_SLAVE_EN = 0
2135 13:42:03.074941 NEW_RANK_MODE = 1
2136 13:42:03.075042 DLL_IDLE_MODE = 1
2137 13:42:03.075142 LP45_APHY_COMB_EN = 1
2138 13:42:03.075241 TX_ODT_DIS = 1
2139 13:42:03.075342 NEW_8X_MODE = 1
2140 13:42:03.075442 ===================================
2141 13:42:03.075542 ===================================
2142 13:42:03.075641 data_rate = 2400
2143 13:42:03.075742 CKR = 1
2144 13:42:03.075842 DQ_P2S_RATIO = 8
2145 13:42:03.075941 ===================================
2146 13:42:03.076041 CA_P2S_RATIO = 8
2147 13:42:03.076141 DQ_CA_OPEN = 0
2148 13:42:03.076240 DQ_SEMI_OPEN = 0
2149 13:42:03.076338 CA_SEMI_OPEN = 0
2150 13:42:03.076445 CA_FULL_RATE = 0
2151 13:42:03.076557 DQ_CKDIV4_EN = 0
2152 13:42:03.076665 CA_CKDIV4_EN = 0
2153 13:42:03.076751 CA_PREDIV_EN = 0
2154 13:42:03.076836 PH8_DLY = 17
2155 13:42:03.076922 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2156 13:42:03.077007 DQ_AAMCK_DIV = 4
2157 13:42:03.077093 CA_AAMCK_DIV = 4
2158 13:42:03.077179 CA_ADMCK_DIV = 4
2159 13:42:03.077274 DQ_TRACK_CA_EN = 0
2160 13:42:03.077363 CA_PICK = 1200
2161 13:42:03.077449 CA_MCKIO = 1200
2162 13:42:03.077534 MCKIO_SEMI = 0
2163 13:42:03.077620 PLL_FREQ = 2366
2164 13:42:03.077705 DQ_UI_PI_RATIO = 32
2165 13:42:03.077791 CA_UI_PI_RATIO = 0
2166 13:42:03.077876 ===================================
2167 13:42:03.077963 ===================================
2168 13:42:03.078048 memory_type:LPDDR4
2169 13:42:03.078135 GP_NUM : 10
2170 13:42:03.078220 SRAM_EN : 1
2171 13:42:03.078305 MD32_EN : 0
2172 13:42:03.078389 ===================================
2173 13:42:03.078475 [ANA_INIT] >>>>>>>>>>>>>>
2174 13:42:03.078560 <<<<<< [CONFIGURE PHASE]: ANA_TX
2175 13:42:03.078647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2176 13:42:03.078733 ===================================
2177 13:42:03.078818 data_rate = 2400,PCW = 0X5b00
2178 13:42:03.078904 ===================================
2179 13:42:03.078991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2180 13:42:03.079077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2181 13:42:03.079163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2182 13:42:03.079250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2183 13:42:03.079335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2184 13:42:03.079420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2185 13:42:03.079506 [ANA_INIT] flow start
2186 13:42:03.079591 [ANA_INIT] PLL >>>>>>>>
2187 13:42:03.079676 [ANA_INIT] PLL <<<<<<<<
2188 13:42:03.079761 [ANA_INIT] MIDPI >>>>>>>>
2189 13:42:03.079846 [ANA_INIT] MIDPI <<<<<<<<
2190 13:42:03.079931 [ANA_INIT] DLL >>>>>>>>
2191 13:42:03.080016 [ANA_INIT] DLL <<<<<<<<
2192 13:42:03.080101 [ANA_INIT] flow end
2193 13:42:03.080186 ============ LP4 DIFF to SE enter ============
2194 13:42:03.080273 ============ LP4 DIFF to SE exit ============
2195 13:42:03.080359 [ANA_INIT] <<<<<<<<<<<<<
2196 13:42:03.080444 [Flow] Enable top DCM control >>>>>
2197 13:42:03.080529 [Flow] Enable top DCM control <<<<<
2198 13:42:03.080615 Enable DLL master slave shuffle
2199 13:42:03.080701 ==============================================================
2200 13:42:03.080786 Gating Mode config
2201 13:42:03.080872 ==============================================================
2202 13:42:03.080958 Config description:
2203 13:42:03.081043 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2204 13:42:03.081130 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2205 13:42:03.081217 SELPH_MODE 0: By rank 1: By Phase
2206 13:42:03.081537 ==============================================================
2207 13:42:03.081642 GAT_TRACK_EN = 1
2208 13:42:03.081720 RX_GATING_MODE = 2
2209 13:42:03.081797 RX_GATING_TRACK_MODE = 2
2210 13:42:03.081873 SELPH_MODE = 1
2211 13:42:03.081952 PICG_EARLY_EN = 1
2212 13:42:03.082038 VALID_LAT_VALUE = 1
2213 13:42:03.082114 ==============================================================
2214 13:42:03.082191 Enter into Gating configuration >>>>
2215 13:42:03.082267 Exit from Gating configuration <<<<
2216 13:42:03.082342 Enter into DVFS_PRE_config >>>>>
2217 13:42:03.082418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2218 13:42:03.082496 Exit from DVFS_PRE_config <<<<<
2219 13:42:03.082572 Enter into PICG configuration >>>>
2220 13:42:03.082647 Exit from PICG configuration <<<<
2221 13:42:03.082723 [RX_INPUT] configuration >>>>>
2222 13:42:03.082798 [RX_INPUT] configuration <<<<<
2223 13:42:03.082874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2224 13:42:03.082949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2225 13:42:03.083024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2226 13:42:03.083100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2227 13:42:03.083176 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2228 13:42:03.083252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2229 13:42:03.083327 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2230 13:42:03.083403 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2231 13:42:03.083478 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2232 13:42:03.083554 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2233 13:42:03.083630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2234 13:42:03.083705 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2235 13:42:03.083780 ===================================
2236 13:42:03.083855 LPDDR4 DRAM CONFIGURATION
2237 13:42:03.083930 ===================================
2238 13:42:03.084005 EX_ROW_EN[0] = 0x0
2239 13:42:03.084080 EX_ROW_EN[1] = 0x0
2240 13:42:03.084154 LP4Y_EN = 0x0
2241 13:42:03.084230 WORK_FSP = 0x0
2242 13:42:03.084304 WL = 0x4
2243 13:42:03.084378 RL = 0x4
2244 13:42:03.084453 BL = 0x2
2245 13:42:03.084528 RPST = 0x0
2246 13:42:03.084603 RD_PRE = 0x0
2247 13:42:03.084677 WR_PRE = 0x1
2248 13:42:03.084753 WR_PST = 0x0
2249 13:42:03.084827 DBI_WR = 0x0
2250 13:42:03.084902 DBI_RD = 0x0
2251 13:42:03.084976 OTF = 0x1
2252 13:42:03.085050 ===================================
2253 13:42:03.085125 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2254 13:42:03.085200 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2255 13:42:03.085286 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 13:42:03.085364 ===================================
2257 13:42:03.085440 LPDDR4 DRAM CONFIGURATION
2258 13:42:03.085516 ===================================
2259 13:42:03.085591 EX_ROW_EN[0] = 0x10
2260 13:42:03.085666 EX_ROW_EN[1] = 0x0
2261 13:42:03.085741 LP4Y_EN = 0x0
2262 13:42:03.085816 WORK_FSP = 0x0
2263 13:42:03.085891 WL = 0x4
2264 13:42:03.085966 RL = 0x4
2265 13:42:03.086040 BL = 0x2
2266 13:42:03.086115 RPST = 0x0
2267 13:42:03.086190 RD_PRE = 0x0
2268 13:42:03.086265 WR_PRE = 0x1
2269 13:42:03.086340 WR_PST = 0x0
2270 13:42:03.086415 DBI_WR = 0x0
2271 13:42:03.086489 DBI_RD = 0x0
2272 13:42:03.086564 OTF = 0x1
2273 13:42:03.086648 ===================================
2274 13:42:03.086716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2275 13:42:03.086783 ==
2276 13:42:03.086850 Dram Type= 6, Freq= 0, CH_0, rank 0
2277 13:42:03.086918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2278 13:42:03.086986 ==
2279 13:42:03.087053 [Duty_Offset_Calibration]
2280 13:42:03.087119 B0:2 B1:0 CA:4
2281 13:42:03.087186
2282 13:42:03.087252 [DutyScan_Calibration_Flow] k_type=0
2283 13:42:03.087319
2284 13:42:03.087386 ==CLK 0==
2285 13:42:03.087453 Final CLK duty delay cell = -4
2286 13:42:03.087520 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2287 13:42:03.087587 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2288 13:42:03.087655 [-4] AVG Duty = 4953%(X100)
2289 13:42:03.087721
2290 13:42:03.087788 CH0 CLK Duty spec in!! Max-Min= 218%
2291 13:42:03.087855 [DutyScan_Calibration_Flow] ====Done====
2292 13:42:03.087921
2293 13:42:03.087988 [DutyScan_Calibration_Flow] k_type=1
2294 13:42:03.088054
2295 13:42:03.088120 ==DQS 0 ==
2296 13:42:03.088186 Final DQS duty delay cell = 0
2297 13:42:03.088254 [0] MAX Duty = 5156%(X100), DQS PI = 6
2298 13:42:03.088320 [0] MIN Duty = 5093%(X100), DQS PI = 0
2299 13:42:03.088386 [0] AVG Duty = 5124%(X100)
2300 13:42:03.088452
2301 13:42:03.088517 ==DQS 1 ==
2302 13:42:03.088583 Final DQS duty delay cell = 0
2303 13:42:03.088649 [0] MAX Duty = 5125%(X100), DQS PI = 52
2304 13:42:03.088715 [0] MIN Duty = 4969%(X100), DQS PI = 14
2305 13:42:03.088781 [0] AVG Duty = 5047%(X100)
2306 13:42:03.088847
2307 13:42:03.088912 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2308 13:42:03.088978
2309 13:42:03.089044 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2310 13:42:03.089110 [DutyScan_Calibration_Flow] ====Done====
2311 13:42:03.089175
2312 13:42:03.089241 [DutyScan_Calibration_Flow] k_type=3
2313 13:42:03.089313
2314 13:42:03.089379 ==DQM 0 ==
2315 13:42:03.089446 Final DQM duty delay cell = 0
2316 13:42:03.089513 [0] MAX Duty = 5093%(X100), DQS PI = 20
2317 13:42:03.089579 [0] MIN Duty = 4844%(X100), DQS PI = 50
2318 13:42:03.089645 [0] AVG Duty = 4968%(X100)
2319 13:42:03.089711
2320 13:42:03.089777 ==DQM 1 ==
2321 13:42:03.089843 Final DQM duty delay cell = 0
2322 13:42:03.089910 [0] MAX Duty = 4969%(X100), DQS PI = 2
2323 13:42:03.089976 [0] MIN Duty = 4875%(X100), DQS PI = 12
2324 13:42:03.090043 [0] AVG Duty = 4922%(X100)
2325 13:42:03.090109
2326 13:42:03.090174 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2327 13:42:03.090240
2328 13:42:03.090306 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2329 13:42:03.090372 [DutyScan_Calibration_Flow] ====Done====
2330 13:42:03.090438
2331 13:42:03.090504 [DutyScan_Calibration_Flow] k_type=2
2332 13:42:03.090570
2333 13:42:03.090635 ==DQ 0 ==
2334 13:42:03.090701 Final DQ duty delay cell = 0
2335 13:42:03.090767 [0] MAX Duty = 5156%(X100), DQS PI = 18
2336 13:42:03.090833 [0] MIN Duty = 4969%(X100), DQS PI = 58
2337 13:42:03.090901 [0] AVG Duty = 5062%(X100)
2338 13:42:03.090967
2339 13:42:03.091234 ==DQ 1 ==
2340 13:42:03.091309 Final DQ duty delay cell = 0
2341 13:42:03.091378 [0] MAX Duty = 5125%(X100), DQS PI = 4
2342 13:42:03.091446 [0] MIN Duty = 4938%(X100), DQS PI = 14
2343 13:42:03.091513 [0] AVG Duty = 5031%(X100)
2344 13:42:03.091580
2345 13:42:03.091653 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2346 13:42:03.091713
2347 13:42:03.091773 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2348 13:42:03.091834 [DutyScan_Calibration_Flow] ====Done====
2349 13:42:03.091893 ==
2350 13:42:03.091956 Dram Type= 6, Freq= 0, CH_1, rank 0
2351 13:42:03.092018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2352 13:42:03.092079 ==
2353 13:42:03.092139 [Duty_Offset_Calibration]
2354 13:42:03.092199 B0:0 B1:-1 CA:3
2355 13:42:03.092259
2356 13:42:03.092319 [DutyScan_Calibration_Flow] k_type=0
2357 13:42:03.092378
2358 13:42:03.092437 ==CLK 0==
2359 13:42:03.092497 Final CLK duty delay cell = 0
2360 13:42:03.092558 [0] MAX Duty = 5156%(X100), DQS PI = 0
2361 13:42:03.092618 [0] MIN Duty = 5000%(X100), DQS PI = 36
2362 13:42:03.092678 [0] AVG Duty = 5078%(X100)
2363 13:42:03.092737
2364 13:42:03.092796 CH1 CLK Duty spec in!! Max-Min= 156%
2365 13:42:03.092856 [DutyScan_Calibration_Flow] ====Done====
2366 13:42:03.092916
2367 13:42:03.092975 [DutyScan_Calibration_Flow] k_type=1
2368 13:42:03.093035
2369 13:42:03.093095 ==DQS 0 ==
2370 13:42:03.093155 Final DQS duty delay cell = 0
2371 13:42:03.093215 [0] MAX Duty = 5156%(X100), DQS PI = 28
2372 13:42:03.093282 [0] MIN Duty = 4907%(X100), DQS PI = 38
2373 13:42:03.093344 [0] AVG Duty = 5031%(X100)
2374 13:42:03.093403
2375 13:42:03.093462 ==DQS 1 ==
2376 13:42:03.093522 Final DQS duty delay cell = 0
2377 13:42:03.093583 [0] MAX Duty = 5156%(X100), DQS PI = 8
2378 13:42:03.093643 [0] MIN Duty = 5031%(X100), DQS PI = 20
2379 13:42:03.093702 [0] AVG Duty = 5093%(X100)
2380 13:42:03.093763
2381 13:42:03.093823 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2382 13:42:03.093882
2383 13:42:03.093942 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2384 13:42:03.094001 [DutyScan_Calibration_Flow] ====Done====
2385 13:42:03.094061
2386 13:42:03.094120 [DutyScan_Calibration_Flow] k_type=3
2387 13:42:03.094180
2388 13:42:03.094240 ==DQM 0 ==
2389 13:42:03.094300 Final DQM duty delay cell = 0
2390 13:42:03.094360 [0] MAX Duty = 5031%(X100), DQS PI = 28
2391 13:42:03.094419 [0] MIN Duty = 4813%(X100), DQS PI = 38
2392 13:42:03.094479 [0] AVG Duty = 4922%(X100)
2393 13:42:03.094539
2394 13:42:03.094598 ==DQM 1 ==
2395 13:42:03.094657 Final DQM duty delay cell = 0
2396 13:42:03.094722 [0] MAX Duty = 5000%(X100), DQS PI = 34
2397 13:42:03.094783 [0] MIN Duty = 4813%(X100), DQS PI = 0
2398 13:42:03.094843 [0] AVG Duty = 4906%(X100)
2399 13:42:03.094902
2400 13:42:03.094972 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2401 13:42:03.095032
2402 13:42:03.095091 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2403 13:42:03.095170 [DutyScan_Calibration_Flow] ====Done====
2404 13:42:03.095231
2405 13:42:03.095291 [DutyScan_Calibration_Flow] k_type=2
2406 13:42:03.095362
2407 13:42:03.095424 ==DQ 0 ==
2408 13:42:03.095484 Final DQ duty delay cell = -4
2409 13:42:03.095555 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2410 13:42:03.095617 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2411 13:42:03.095676 [-4] AVG Duty = 4922%(X100)
2412 13:42:03.095742
2413 13:42:03.095805 ==DQ 1 ==
2414 13:42:03.095876 Final DQ duty delay cell = 4
2415 13:42:03.095944 [4] MAX Duty = 5156%(X100), DQS PI = 30
2416 13:42:03.096005 [4] MIN Duty = 5031%(X100), DQS PI = 62
2417 13:42:03.096067 [4] AVG Duty = 5093%(X100)
2418 13:42:03.096129
2419 13:42:03.096189 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2420 13:42:03.096251
2421 13:42:03.096313 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2422 13:42:03.096373 [DutyScan_Calibration_Flow] ====Done====
2423 13:42:03.096437 nWR fixed to 30
2424 13:42:03.096498 [ModeRegInit_LP4] CH0 RK0
2425 13:42:03.096558 [ModeRegInit_LP4] CH0 RK1
2426 13:42:03.096627 [ModeRegInit_LP4] CH1 RK0
2427 13:42:03.096681 [ModeRegInit_LP4] CH1 RK1
2428 13:42:03.096735 match AC timing 7
2429 13:42:03.096790 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2430 13:42:03.096845 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2431 13:42:03.096900 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2432 13:42:03.096955 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2433 13:42:03.097010 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2434 13:42:03.097065 ==
2435 13:42:03.097119 Dram Type= 6, Freq= 0, CH_0, rank 0
2436 13:42:03.097174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 13:42:03.097229 ==
2438 13:42:03.097294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2439 13:42:03.097350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2440 13:42:03.097405 [CA 0] Center 39 (9~70) winsize 62
2441 13:42:03.097460 [CA 1] Center 38 (8~69) winsize 62
2442 13:42:03.097515 [CA 2] Center 35 (5~66) winsize 62
2443 13:42:03.097569 [CA 3] Center 35 (5~66) winsize 62
2444 13:42:03.097623 [CA 4] Center 33 (3~64) winsize 62
2445 13:42:03.097678 [CA 5] Center 33 (3~63) winsize 61
2446 13:42:03.097732
2447 13:42:03.097786 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2448 13:42:03.097840
2449 13:42:03.097894 [CATrainingPosCal] consider 1 rank data
2450 13:42:03.097949 u2DelayCellTimex100 = 270/100 ps
2451 13:42:03.098003 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2452 13:42:03.098058 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2453 13:42:03.098112 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2454 13:42:03.098167 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2455 13:42:03.098221 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2456 13:42:03.098276 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2457 13:42:03.098330
2458 13:42:03.098384 CA PerBit enable=1, Macro0, CA PI delay=33
2459 13:42:03.098439
2460 13:42:03.098493 [CBTSetCACLKResult] CA Dly = 33
2461 13:42:03.098548 CS Dly: 7 (0~38)
2462 13:42:03.098603 ==
2463 13:42:03.098681 Dram Type= 6, Freq= 0, CH_0, rank 1
2464 13:42:03.098784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 13:42:03.098857 ==
2466 13:42:03.098914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 13:42:03.098970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2468 13:42:03.099026 [CA 0] Center 39 (9~70) winsize 62
2469 13:42:03.099081 [CA 1] Center 39 (9~70) winsize 62
2470 13:42:03.099135 [CA 2] Center 35 (5~66) winsize 62
2471 13:42:03.099189 [CA 3] Center 35 (5~66) winsize 62
2472 13:42:03.099244 [CA 4] Center 34 (4~65) winsize 62
2473 13:42:03.099298 [CA 5] Center 33 (3~64) winsize 62
2474 13:42:03.099352
2475 13:42:03.099406 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2476 13:42:03.099461
2477 13:42:03.099515 [CATrainingPosCal] consider 2 rank data
2478 13:42:03.099570 u2DelayCellTimex100 = 270/100 ps
2479 13:42:03.099625 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2480 13:42:03.099679 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2481 13:42:03.099926 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2482 13:42:03.099988 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 13:42:03.100044 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2484 13:42:03.100099 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2485 13:42:03.100154
2486 13:42:03.100208 CA PerBit enable=1, Macro0, CA PI delay=33
2487 13:42:03.100263
2488 13:42:03.100318 [CBTSetCACLKResult] CA Dly = 33
2489 13:42:03.100373 CS Dly: 8 (0~41)
2490 13:42:03.100427
2491 13:42:03.100482 ----->DramcWriteLeveling(PI) begin...
2492 13:42:03.100538 ==
2493 13:42:03.100593 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 13:42:03.100647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 13:42:03.100703 ==
2496 13:42:03.100757 Write leveling (Byte 0): 32 => 32
2497 13:42:03.100812 Write leveling (Byte 1): 27 => 27
2498 13:42:03.100866 DramcWriteLeveling(PI) end<-----
2499 13:42:03.100920
2500 13:42:03.100974 ==
2501 13:42:03.101029 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 13:42:03.101083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 13:42:03.101138 ==
2504 13:42:03.101193 [Gating] SW mode calibration
2505 13:42:03.101248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2506 13:42:03.101327 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2507 13:42:03.101384 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2508 13:42:03.101439 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
2509 13:42:03.101514 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2510 13:42:03.101571 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2511 13:42:03.101639 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 13:42:03.101695 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 13:42:03.101747 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2514 13:42:03.101800 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2515 13:42:03.101853 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2516 13:42:03.101937 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2517 13:42:03.101991 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2518 13:42:03.102044 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 13:42:03.102097 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 13:42:03.102150 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 13:42:03.102233 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2522 13:42:03.102286 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2523 13:42:03.102339 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2524 13:42:03.102393 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2525 13:42:03.102446 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2526 13:42:03.102499 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2527 13:42:03.102552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 13:42:03.102605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 13:42:03.102659 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2530 13:42:03.102711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2531 13:42:03.102764 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2532 13:42:03.102817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2533 13:42:03.102870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2534 13:42:03.102923 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 13:42:03.102976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 13:42:03.103029 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 13:42:03.103083 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 13:42:03.103136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 13:42:03.103190 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 13:42:03.103242 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 13:42:03.103296 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 13:42:03.103348 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 13:42:03.103401 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 13:42:03.103454 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:42:03.103507 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2546 13:42:03.103560 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2547 13:42:03.103613 Total UI for P1: 0, mck2ui 16
2548 13:42:03.103669 best dqsien dly found for B0: ( 1, 3, 24)
2549 13:42:03.103724 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2550 13:42:03.103776 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2551 13:42:03.103829 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 13:42:03.103885 Total UI for P1: 0, mck2ui 16
2553 13:42:03.103939 best dqsien dly found for B1: ( 1, 4, 2)
2554 13:42:03.103992 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2555 13:42:03.104046 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2556 13:42:03.104099
2557 13:42:03.104153 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2558 13:42:03.104208 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2559 13:42:03.104260 [Gating] SW calibration Done
2560 13:42:03.104313 ==
2561 13:42:03.104380 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 13:42:03.104436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 13:42:03.104490 ==
2564 13:42:03.104547 RX Vref Scan: 0
2565 13:42:03.104600
2566 13:42:03.104653 RX Vref 0 -> 0, step: 1
2567 13:42:03.104707
2568 13:42:03.104784 RX Delay -40 -> 252, step: 8
2569 13:42:03.104868 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2570 13:42:03.104954 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2571 13:42:03.105037 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2572 13:42:03.105123 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2573 13:42:03.105207 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2574 13:42:03.105299 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2575 13:42:03.105384 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2576 13:42:03.105468 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2577 13:42:03.105552 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2578 13:42:03.105636 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2579 13:42:03.105720 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2580 13:42:03.105804 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2581 13:42:03.105887 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2582 13:42:03.106164 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2583 13:42:03.106253 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2584 13:42:03.106338 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2585 13:42:03.106421 ==
2586 13:42:03.106505 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 13:42:03.106589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 13:42:03.106673 ==
2589 13:42:03.106756 DQS Delay:
2590 13:42:03.106839 DQS0 = 0, DQS1 = 0
2591 13:42:03.106922 DQM Delay:
2592 13:42:03.107006 DQM0 = 117, DQM1 = 107
2593 13:42:03.107089 DQ Delay:
2594 13:42:03.107174 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2595 13:42:03.107258 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2596 13:42:03.107341 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2597 13:42:03.107429 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2598 13:42:03.107494
2599 13:42:03.107548
2600 13:42:03.107601 ==
2601 13:42:03.107655 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 13:42:03.107708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 13:42:03.107763 ==
2604 13:42:03.107815
2605 13:42:03.107868
2606 13:42:03.107920 TX Vref Scan disable
2607 13:42:03.107973 == TX Byte 0 ==
2608 13:42:03.108026 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2609 13:42:03.108079 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2610 13:42:03.108132 == TX Byte 1 ==
2611 13:42:03.108185 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2612 13:42:03.108238 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2613 13:42:03.108291 ==
2614 13:42:03.108345 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 13:42:03.108399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 13:42:03.108453 ==
2617 13:42:03.108506 TX Vref=22, minBit 4, minWin=25, winSum=410
2618 13:42:03.108560 TX Vref=24, minBit 10, minWin=25, winSum=419
2619 13:42:03.108614 TX Vref=26, minBit 10, minWin=25, winSum=420
2620 13:42:03.108668 TX Vref=28, minBit 5, minWin=26, winSum=432
2621 13:42:03.108722 TX Vref=30, minBit 5, minWin=26, winSum=430
2622 13:42:03.108775 TX Vref=32, minBit 5, minWin=26, winSum=429
2623 13:42:03.108829 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
2624 13:42:03.108882
2625 13:42:03.108936 Final TX Range 1 Vref 28
2626 13:42:03.108989
2627 13:42:03.109042 ==
2628 13:42:03.109094 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 13:42:03.109148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 13:42:03.109201 ==
2631 13:42:03.109255
2632 13:42:03.109321
2633 13:42:03.109374 TX Vref Scan disable
2634 13:42:03.109427 == TX Byte 0 ==
2635 13:42:03.109479 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2636 13:42:03.109533 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2637 13:42:03.109586 == TX Byte 1 ==
2638 13:42:03.109639 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2639 13:42:03.109693 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2640 13:42:03.109746
2641 13:42:03.109798 [DATLAT]
2642 13:42:03.109851 Freq=1200, CH0 RK0
2643 13:42:03.109907
2644 13:42:03.109960 DATLAT Default: 0xd
2645 13:42:03.110013 0, 0xFFFF, sum = 0
2646 13:42:03.110067 1, 0xFFFF, sum = 0
2647 13:42:03.110121 2, 0xFFFF, sum = 0
2648 13:42:03.110175 3, 0xFFFF, sum = 0
2649 13:42:03.110229 4, 0xFFFF, sum = 0
2650 13:42:03.110283 5, 0xFFFF, sum = 0
2651 13:42:03.110337 6, 0xFFFF, sum = 0
2652 13:42:03.110391 7, 0xFFFF, sum = 0
2653 13:42:03.110444 8, 0xFFFF, sum = 0
2654 13:42:03.110498 9, 0xFFFF, sum = 0
2655 13:42:03.110552 10, 0xFFFF, sum = 0
2656 13:42:03.110607 11, 0xFFFF, sum = 0
2657 13:42:03.110661 12, 0x0, sum = 1
2658 13:42:03.110715 13, 0x0, sum = 2
2659 13:42:03.110768 14, 0x0, sum = 3
2660 13:42:03.110821 15, 0x0, sum = 4
2661 13:42:03.110875 best_step = 13
2662 13:42:03.110928
2663 13:42:03.110980 ==
2664 13:42:03.111033 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 13:42:03.111086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 13:42:03.111140 ==
2667 13:42:03.111193 RX Vref Scan: 1
2668 13:42:03.111246
2669 13:42:03.111299 Set Vref Range= 32 -> 127
2670 13:42:03.111352
2671 13:42:03.111405 RX Vref 32 -> 127, step: 1
2672 13:42:03.111459
2673 13:42:03.111511 RX Delay -21 -> 252, step: 4
2674 13:42:03.111564
2675 13:42:03.111617 Set Vref, RX VrefLevel [Byte0]: 32
2676 13:42:03.111669 [Byte1]: 32
2677 13:42:03.111722
2678 13:42:03.111775 Set Vref, RX VrefLevel [Byte0]: 33
2679 13:42:03.111828 [Byte1]: 33
2680 13:42:03.111881
2681 13:42:03.111933 Set Vref, RX VrefLevel [Byte0]: 34
2682 13:42:03.111986 [Byte1]: 34
2683 13:42:03.112038
2684 13:42:03.112090 Set Vref, RX VrefLevel [Byte0]: 35
2685 13:42:03.112143 [Byte1]: 35
2686 13:42:03.112195
2687 13:42:03.112247 Set Vref, RX VrefLevel [Byte0]: 36
2688 13:42:03.112300 [Byte1]: 36
2689 13:42:03.112353
2690 13:42:03.112406 Set Vref, RX VrefLevel [Byte0]: 37
2691 13:42:03.112459 [Byte1]: 37
2692 13:42:03.112512
2693 13:42:03.112565 Set Vref, RX VrefLevel [Byte0]: 38
2694 13:42:03.112618 [Byte1]: 38
2695 13:42:03.112671
2696 13:42:03.112731 Set Vref, RX VrefLevel [Byte0]: 39
2697 13:42:03.112787 [Byte1]: 39
2698 13:42:03.112841
2699 13:42:03.112894 Set Vref, RX VrefLevel [Byte0]: 40
2700 13:42:03.112948 [Byte1]: 40
2701 13:42:03.113002
2702 13:42:03.113054 Set Vref, RX VrefLevel [Byte0]: 41
2703 13:42:03.113107 [Byte1]: 41
2704 13:42:03.113160
2705 13:42:03.113212 Set Vref, RX VrefLevel [Byte0]: 42
2706 13:42:03.113272 [Byte1]: 42
2707 13:42:03.113364
2708 13:42:03.113417 Set Vref, RX VrefLevel [Byte0]: 43
2709 13:42:03.113471 [Byte1]: 43
2710 13:42:03.113523
2711 13:42:03.113576 Set Vref, RX VrefLevel [Byte0]: 44
2712 13:42:03.113629 [Byte1]: 44
2713 13:42:03.113683
2714 13:42:03.113735 Set Vref, RX VrefLevel [Byte0]: 45
2715 13:42:03.113788 [Byte1]: 45
2716 13:42:03.113842
2717 13:42:03.113895 Set Vref, RX VrefLevel [Byte0]: 46
2718 13:42:03.113948 [Byte1]: 46
2719 13:42:03.114001
2720 13:42:03.114054 Set Vref, RX VrefLevel [Byte0]: 47
2721 13:42:03.114107 [Byte1]: 47
2722 13:42:03.114160
2723 13:42:03.114212 Set Vref, RX VrefLevel [Byte0]: 48
2724 13:42:03.114266 [Byte1]: 48
2725 13:42:03.114319
2726 13:42:03.114371 Set Vref, RX VrefLevel [Byte0]: 49
2727 13:42:03.114424 [Byte1]: 49
2728 13:42:03.114477
2729 13:42:03.114530 Set Vref, RX VrefLevel [Byte0]: 50
2730 13:42:03.114583 [Byte1]: 50
2731 13:42:03.114635
2732 13:42:03.114688 Set Vref, RX VrefLevel [Byte0]: 51
2733 13:42:03.114741 [Byte1]: 51
2734 13:42:03.114794
2735 13:42:03.114846 Set Vref, RX VrefLevel [Byte0]: 52
2736 13:42:03.114899 [Byte1]: 52
2737 13:42:03.114952
2738 13:42:03.115005 Set Vref, RX VrefLevel [Byte0]: 53
2739 13:42:03.115058 [Byte1]: 53
2740 13:42:03.115111
2741 13:42:03.115164 Set Vref, RX VrefLevel [Byte0]: 54
2742 13:42:03.115217 [Byte1]: 54
2743 13:42:03.115271
2744 13:42:03.115323 Set Vref, RX VrefLevel [Byte0]: 55
2745 13:42:03.115376 [Byte1]: 55
2746 13:42:03.115429
2747 13:42:03.115482 Set Vref, RX VrefLevel [Byte0]: 56
2748 13:42:03.115725 [Byte1]: 56
2749 13:42:03.115785
2750 13:42:03.115839 Set Vref, RX VrefLevel [Byte0]: 57
2751 13:42:03.115893 [Byte1]: 57
2752 13:42:03.115946
2753 13:42:03.115999 Set Vref, RX VrefLevel [Byte0]: 58
2754 13:42:03.116052 [Byte1]: 58
2755 13:42:03.116105
2756 13:42:03.116161 Set Vref, RX VrefLevel [Byte0]: 59
2757 13:42:03.116215 [Byte1]: 59
2758 13:42:03.116269
2759 13:42:03.116322 Set Vref, RX VrefLevel [Byte0]: 60
2760 13:42:03.116375 [Byte1]: 60
2761 13:42:03.116429
2762 13:42:03.116481 Set Vref, RX VrefLevel [Byte0]: 61
2763 13:42:03.116534 [Byte1]: 61
2764 13:42:03.116587
2765 13:42:03.116640 Set Vref, RX VrefLevel [Byte0]: 62
2766 13:42:03.116692 [Byte1]: 62
2767 13:42:03.116745
2768 13:42:03.116797 Set Vref, RX VrefLevel [Byte0]: 63
2769 13:42:03.116851 [Byte1]: 63
2770 13:42:03.116904
2771 13:42:03.116956 Set Vref, RX VrefLevel [Byte0]: 64
2772 13:42:03.117009 [Byte1]: 64
2773 13:42:03.117062
2774 13:42:03.117114 Set Vref, RX VrefLevel [Byte0]: 65
2775 13:42:03.117167 [Byte1]: 65
2776 13:42:03.117220
2777 13:42:03.117313 Set Vref, RX VrefLevel [Byte0]: 66
2778 13:42:03.117369 [Byte1]: 66
2779 13:42:03.117422
2780 13:42:03.117478 Set Vref, RX VrefLevel [Byte0]: 67
2781 13:42:03.117531 [Byte1]: 67
2782 13:42:03.117584
2783 13:42:03.117637 Final RX Vref Byte 0 = 57 to rank0
2784 13:42:03.117691 Final RX Vref Byte 1 = 59 to rank0
2785 13:42:03.117745 Final RX Vref Byte 0 = 57 to rank1
2786 13:42:03.117798 Final RX Vref Byte 1 = 59 to rank1==
2787 13:42:03.117851 Dram Type= 6, Freq= 0, CH_0, rank 0
2788 13:42:03.117905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2789 13:42:03.117959 ==
2790 13:42:03.118012 DQS Delay:
2791 13:42:03.118065 DQS0 = 0, DQS1 = 0
2792 13:42:03.118118 DQM Delay:
2793 13:42:03.118170 DQM0 = 117, DQM1 = 105
2794 13:42:03.118233 DQ Delay:
2795 13:42:03.118287 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2796 13:42:03.118342 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2797 13:42:03.118395 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2798 13:42:03.118449 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2799 13:42:03.118502
2800 13:42:03.118555
2801 13:42:03.118608 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2802 13:42:03.118662 CH0 RK0: MR19=404, MR18=500
2803 13:42:03.118715 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2804 13:42:03.118769
2805 13:42:03.118822 ----->DramcWriteLeveling(PI) begin...
2806 13:42:03.118876 ==
2807 13:42:03.118930 Dram Type= 6, Freq= 0, CH_0, rank 1
2808 13:42:03.118983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 13:42:03.119036 ==
2810 13:42:03.119089 Write leveling (Byte 0): 32 => 32
2811 13:42:03.119143 Write leveling (Byte 1): 26 => 26
2812 13:42:03.119196 DramcWriteLeveling(PI) end<-----
2813 13:42:03.119249
2814 13:42:03.119302 ==
2815 13:42:03.119355 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 13:42:03.119409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 13:42:03.119462 ==
2818 13:42:03.119516 [Gating] SW mode calibration
2819 13:42:03.119569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2820 13:42:03.119623 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2821 13:42:03.119676 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2822 13:42:03.119730 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2823 13:42:03.119783 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2824 13:42:03.119837 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2825 13:42:03.119890 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2826 13:42:03.119943 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2827 13:42:03.119997 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
2828 13:42:03.120050 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2829 13:42:03.120103 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2830 13:42:03.120156 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2831 13:42:03.120209 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2832 13:42:03.120262 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2833 13:42:03.120315 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2834 13:42:03.120368 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2835 13:42:03.120421 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2836 13:42:03.120474 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2837 13:42:03.120526 1 1 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2838 13:42:03.120579 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2839 13:42:03.120632 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2840 13:42:03.120685 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2841 13:42:03.120738 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2842 13:42:03.120791 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2843 13:42:03.120844 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2844 13:42:03.120897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2845 13:42:03.120950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2846 13:42:03.121003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2847 13:42:03.121056 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2848 13:42:03.121109 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2849 13:42:03.121161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2850 13:42:03.121214 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 13:42:03.121275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 13:42:03.121367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 13:42:03.121421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 13:42:03.121474 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 13:42:03.121527 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 13:42:03.121581 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 13:42:03.121635 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 13:42:03.121688 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 13:42:03.121742 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2860 13:42:03.121795 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2861 13:42:03.122036 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2862 13:42:03.122096 Total UI for P1: 0, mck2ui 16
2863 13:42:03.122152 best dqsien dly found for B0: ( 1, 3, 26)
2864 13:42:03.122206 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2865 13:42:03.122260 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 13:42:03.122314 Total UI for P1: 0, mck2ui 16
2867 13:42:03.122368 best dqsien dly found for B1: ( 1, 4, 2)
2868 13:42:03.122422 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2869 13:42:03.122475 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2870 13:42:03.122528
2871 13:42:03.122581 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2872 13:42:03.122635 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2873 13:42:03.122688 [Gating] SW calibration Done
2874 13:42:03.122741 ==
2875 13:42:03.122794 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 13:42:03.122848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 13:42:03.122902 ==
2878 13:42:03.122955 RX Vref Scan: 0
2879 13:42:03.123008
2880 13:42:03.123060 RX Vref 0 -> 0, step: 1
2881 13:42:03.123113
2882 13:42:03.123166 RX Delay -40 -> 252, step: 8
2883 13:42:03.123219 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2884 13:42:03.123272 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2885 13:42:03.123325 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2886 13:42:03.123378 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2887 13:42:03.123431 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2888 13:42:03.123485 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2889 13:42:03.123538 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2890 13:42:03.123591 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2891 13:42:03.123644 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2892 13:42:03.123697 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2893 13:42:03.123750 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2894 13:42:03.123803 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2895 13:42:03.123857 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2896 13:42:03.123910 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2897 13:42:03.123963 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2898 13:42:03.124016 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2899 13:42:03.124069 ==
2900 13:42:03.124123 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 13:42:03.124176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 13:42:03.124230 ==
2903 13:42:03.124283 DQS Delay:
2904 13:42:03.124336 DQS0 = 0, DQS1 = 0
2905 13:42:03.124388 DQM Delay:
2906 13:42:03.124441 DQM0 = 116, DQM1 = 108
2907 13:42:03.124494 DQ Delay:
2908 13:42:03.124547 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2909 13:42:03.124601 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2910 13:42:03.124654 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2911 13:42:03.124707 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2912 13:42:03.124760
2913 13:42:03.124812
2914 13:42:03.124865 ==
2915 13:42:03.124918 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 13:42:03.124971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 13:42:03.125025 ==
2918 13:42:03.125078
2919 13:42:03.125130
2920 13:42:03.125183 TX Vref Scan disable
2921 13:42:03.125236 == TX Byte 0 ==
2922 13:42:03.125299 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2923 13:42:03.125354 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2924 13:42:03.125407 == TX Byte 1 ==
2925 13:42:03.125460 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2926 13:42:03.125513 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2927 13:42:03.125566 ==
2928 13:42:03.125619 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 13:42:03.125673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 13:42:03.125727 ==
2931 13:42:03.125780 TX Vref=22, minBit 0, minWin=25, winSum=420
2932 13:42:03.125835 TX Vref=24, minBit 2, minWin=26, winSum=427
2933 13:42:03.125888 TX Vref=26, minBit 2, minWin=26, winSum=427
2934 13:42:03.125941 TX Vref=28, minBit 13, minWin=25, winSum=426
2935 13:42:03.125994 TX Vref=30, minBit 4, minWin=26, winSum=429
2936 13:42:03.396703 TX Vref=32, minBit 1, minWin=26, winSum=427
2937 13:42:03.397201 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
2938 13:42:03.397563
2939 13:42:03.397879 Final TX Range 1 Vref 30
2940 13:42:03.398185
2941 13:42:03.398481 ==
2942 13:42:03.398772 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 13:42:03.399058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 13:42:03.399344 ==
2945 13:42:03.399625
2946 13:42:03.399904
2947 13:42:03.400181 TX Vref Scan disable
2948 13:42:03.400510 == TX Byte 0 ==
2949 13:42:03.401083 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2950 13:42:03.401544 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2951 13:42:03.401848 == TX Byte 1 ==
2952 13:42:03.402136 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2953 13:42:03.402421 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2954 13:42:03.402698
2955 13:42:03.402974 [DATLAT]
2956 13:42:03.403302 Freq=1200, CH0 RK1
2957 13:42:03.403585
2958 13:42:03.403865 DATLAT Default: 0xd
2959 13:42:03.404146 0, 0xFFFF, sum = 0
2960 13:42:03.404431 1, 0xFFFF, sum = 0
2961 13:42:03.404714 2, 0xFFFF, sum = 0
2962 13:42:03.404993 3, 0xFFFF, sum = 0
2963 13:42:03.405334 4, 0xFFFF, sum = 0
2964 13:42:03.405651 5, 0xFFFF, sum = 0
2965 13:42:03.405934 6, 0xFFFF, sum = 0
2966 13:42:03.406215 7, 0xFFFF, sum = 0
2967 13:42:03.406497 8, 0xFFFF, sum = 0
2968 13:42:03.406780 9, 0xFFFF, sum = 0
2969 13:42:03.407062 10, 0xFFFF, sum = 0
2970 13:42:03.407364 11, 0xFFFF, sum = 0
2971 13:42:03.407656 12, 0x0, sum = 1
2972 13:42:03.407935 13, 0x0, sum = 2
2973 13:42:03.408296 14, 0x0, sum = 3
2974 13:42:03.408593 15, 0x0, sum = 4
2975 13:42:03.408873 best_step = 13
2976 13:42:03.409149
2977 13:42:03.409515 ==
2978 13:42:03.409805 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 13:42:03.410089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 13:42:03.410369 ==
2981 13:42:03.410648 RX Vref Scan: 0
2982 13:42:03.410927
2983 13:42:03.411201 RX Vref 0 -> 0, step: 1
2984 13:42:03.411475
2985 13:42:03.411750 RX Delay -21 -> 252, step: 4
2986 13:42:03.412027 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
2987 13:42:03.412306 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2988 13:42:03.412583 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
2989 13:42:03.412862 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
2990 13:42:03.413136 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2991 13:42:03.413535 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
2992 13:42:03.413834 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2993 13:42:03.414112 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
2994 13:42:03.414389 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
2995 13:42:03.414666 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
2996 13:42:03.414939 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2997 13:42:03.415215 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
2998 13:42:03.415654 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2999 13:42:03.416420 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3000 13:42:03.416744 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3001 13:42:03.417034 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3002 13:42:03.417378 ==
3003 13:42:03.417711 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 13:42:03.417998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 13:42:03.418283 ==
3006 13:42:03.418685 DQS Delay:
3007 13:42:03.418993 DQS0 = 0, DQS1 = 0
3008 13:42:03.419276 DQM Delay:
3009 13:42:03.419775 DQM0 = 116, DQM1 = 106
3010 13:42:03.420208 DQ Delay:
3011 13:42:03.420638 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =114
3012 13:42:03.421070 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3013 13:42:03.421560 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
3014 13:42:03.421995 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3015 13:42:03.422422
3016 13:42:03.422846
3017 13:42:03.423280 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3018 13:42:03.423721 CH0 RK1: MR19=303, MR18=FEFC
3019 13:42:03.424157 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3020 13:42:03.424588 [RxdqsGatingPostProcess] freq 1200
3021 13:42:03.425021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3022 13:42:03.425481 best DQS0 dly(2T, 0.5T) = (0, 11)
3023 13:42:03.425742 best DQS1 dly(2T, 0.5T) = (0, 12)
3024 13:42:03.425942 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3025 13:42:03.426141 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3026 13:42:03.426339 best DQS0 dly(2T, 0.5T) = (0, 11)
3027 13:42:03.426668 best DQS1 dly(2T, 0.5T) = (0, 12)
3028 13:42:03.426903 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3029 13:42:03.427118 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3030 13:42:03.427322 Pre-setting of DQS Precalculation
3031 13:42:03.427523 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3032 13:42:03.427725 ==
3033 13:42:03.427927 Dram Type= 6, Freq= 0, CH_1, rank 0
3034 13:42:03.428129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 13:42:03.428350 ==
3036 13:42:03.428552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3037 13:42:03.428754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3038 13:42:03.428955 [CA 0] Center 38 (8~68) winsize 61
3039 13:42:03.429155 [CA 1] Center 37 (7~68) winsize 62
3040 13:42:03.429391 [CA 2] Center 35 (6~65) winsize 60
3041 13:42:03.429595 [CA 3] Center 34 (4~64) winsize 61
3042 13:42:03.429795 [CA 4] Center 34 (4~65) winsize 62
3043 13:42:03.429994 [CA 5] Center 33 (3~64) winsize 62
3044 13:42:03.430192
3045 13:42:03.430391 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3046 13:42:03.430606
3047 13:42:03.430754 [CATrainingPosCal] consider 1 rank data
3048 13:42:03.430904 u2DelayCellTimex100 = 270/100 ps
3049 13:42:03.431053 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3050 13:42:03.431202 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3051 13:42:03.431363 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3052 13:42:03.431602 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3053 13:42:03.431823 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3054 13:42:03.431981 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3055 13:42:03.432133
3056 13:42:03.432284 CA PerBit enable=1, Macro0, CA PI delay=33
3057 13:42:03.432436
3058 13:42:03.432585 [CBTSetCACLKResult] CA Dly = 33
3059 13:42:03.432737 CS Dly: 4 (0~35)
3060 13:42:03.432888 ==
3061 13:42:03.433041 Dram Type= 6, Freq= 0, CH_1, rank 1
3062 13:42:03.433191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 13:42:03.433378 ==
3064 13:42:03.433534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 13:42:03.433687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 13:42:03.433839 [CA 0] Center 37 (7~68) winsize 62
3067 13:42:03.433990 [CA 1] Center 38 (8~68) winsize 61
3068 13:42:03.434140 [CA 2] Center 35 (5~65) winsize 61
3069 13:42:03.434290 [CA 3] Center 34 (4~64) winsize 61
3070 13:42:03.434441 [CA 4] Center 34 (4~64) winsize 61
3071 13:42:03.434590 [CA 5] Center 33 (3~64) winsize 62
3072 13:42:03.434739
3073 13:42:03.434888 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3074 13:42:03.435037
3075 13:42:03.435187 [CATrainingPosCal] consider 2 rank data
3076 13:42:03.435339 u2DelayCellTimex100 = 270/100 ps
3077 13:42:03.435489 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3078 13:42:03.435641 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3079 13:42:03.435761 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3080 13:42:03.435882 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3081 13:42:03.436002 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3082 13:42:03.436121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3083 13:42:03.436241
3084 13:42:03.436360 CA PerBit enable=1, Macro0, CA PI delay=33
3085 13:42:03.436480
3086 13:42:03.436599 [CBTSetCACLKResult] CA Dly = 33
3087 13:42:03.436720 CS Dly: 6 (0~39)
3088 13:42:03.436840
3089 13:42:03.436959 ----->DramcWriteLeveling(PI) begin...
3090 13:42:03.437081 ==
3091 13:42:03.437202 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 13:42:03.437337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 13:42:03.437460 ==
3094 13:42:03.437579 Write leveling (Byte 0): 25 => 25
3095 13:42:03.437700 Write leveling (Byte 1): 27 => 27
3096 13:42:03.437820 DramcWriteLeveling(PI) end<-----
3097 13:42:03.437941
3098 13:42:03.438060 ==
3099 13:42:03.438181 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 13:42:03.438302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 13:42:03.438423 ==
3102 13:42:03.438542 [Gating] SW mode calibration
3103 13:42:03.438662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3104 13:42:03.438784 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3105 13:42:03.438905 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3106 13:42:03.439026 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3107 13:42:03.439147 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3108 13:42:03.439268 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3109 13:42:03.439388 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 13:42:03.439508 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 13:42:03.439628 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (0 0) (0 1)
3112 13:42:03.439748 0 15 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 1) (0 0)
3113 13:42:03.439867 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3114 13:42:03.439985 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3115 13:42:03.440104 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3116 13:42:03.440225 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3117 13:42:03.440593 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 13:42:03.440741 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 13:42:03.440956 1 0 24 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
3120 13:42:03.441168 1 0 28 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
3121 13:42:03.441396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3122 13:42:03.441569 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3123 13:42:03.441729 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3124 13:42:03.441887 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3125 13:42:03.442043 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 13:42:03.442200 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 13:42:03.442357 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3128 13:42:03.442512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3129 13:42:03.442668 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3130 13:42:03.442824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3131 13:42:03.442999 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3132 13:42:03.443186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3133 13:42:03.443300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 13:42:03.443405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 13:42:03.443508 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 13:42:03.443610 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 13:42:03.443713 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 13:42:03.443815 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 13:42:03.443916 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 13:42:03.444016 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 13:42:03.444117 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 13:42:03.444217 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 13:42:03.444316 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 13:42:03.444417 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3145 13:42:03.444517 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 13:42:03.444617 Total UI for P1: 0, mck2ui 16
3147 13:42:03.444719 best dqsien dly found for B0: ( 1, 3, 28)
3148 13:42:03.444821 Total UI for P1: 0, mck2ui 16
3149 13:42:03.444923 best dqsien dly found for B1: ( 1, 3, 28)
3150 13:42:03.445022 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3151 13:42:03.445122 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3152 13:42:03.445222
3153 13:42:03.445345 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3154 13:42:03.445450 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3155 13:42:03.445551 [Gating] SW calibration Done
3156 13:42:03.445653 ==
3157 13:42:03.445739 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 13:42:03.445825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 13:42:03.445913 ==
3160 13:42:03.445999 RX Vref Scan: 0
3161 13:42:03.446085
3162 13:42:03.446170 RX Vref 0 -> 0, step: 1
3163 13:42:03.446255
3164 13:42:03.446341 RX Delay -40 -> 252, step: 8
3165 13:42:03.446427 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3166 13:42:03.446513 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3167 13:42:03.446599 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3168 13:42:03.446685 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3169 13:42:03.446771 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3170 13:42:03.446857 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3171 13:42:03.446942 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3172 13:42:03.447027 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3173 13:42:03.447111 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3174 13:42:03.447197 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3175 13:42:03.447282 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3176 13:42:03.447367 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3177 13:42:03.447453 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3178 13:42:03.447538 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3179 13:42:03.447623 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3180 13:42:03.447708 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3181 13:42:03.447792 ==
3182 13:42:03.447877 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 13:42:03.447963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 13:42:03.448049 ==
3185 13:42:03.448135 DQS Delay:
3186 13:42:03.448221 DQS0 = 0, DQS1 = 0
3187 13:42:03.448354 DQM Delay:
3188 13:42:03.448488 DQM0 = 118, DQM1 = 115
3189 13:42:03.448621 DQ Delay:
3190 13:42:03.448754 DQ0 =127, DQ1 =111, DQ2 =107, DQ3 =119
3191 13:42:03.448887 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3192 13:42:03.449020 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3193 13:42:03.449154 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3194 13:42:03.449291
3195 13:42:03.449383
3196 13:42:03.449469 ==
3197 13:42:03.449555 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 13:42:03.449643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 13:42:03.449729 ==
3200 13:42:03.449815
3201 13:42:03.449901
3202 13:42:03.449986 TX Vref Scan disable
3203 13:42:03.450072 == TX Byte 0 ==
3204 13:42:03.450158 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3205 13:42:03.450245 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3206 13:42:03.450331 == TX Byte 1 ==
3207 13:42:03.450418 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3208 13:42:03.450504 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3209 13:42:03.450591 ==
3210 13:42:03.450680 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 13:42:03.450756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 13:42:03.450831 ==
3213 13:42:03.450907 TX Vref=22, minBit 1, minWin=25, winSum=412
3214 13:42:03.450983 TX Vref=24, minBit 8, minWin=25, winSum=418
3215 13:42:03.451060 TX Vref=26, minBit 1, minWin=26, winSum=424
3216 13:42:03.451135 TX Vref=28, minBit 11, minWin=25, winSum=425
3217 13:42:03.451211 TX Vref=30, minBit 1, minWin=26, winSum=428
3218 13:42:03.451286 TX Vref=32, minBit 0, minWin=26, winSum=425
3219 13:42:03.451363 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3220 13:42:03.451439
3221 13:42:03.451513 Final TX Range 1 Vref 30
3222 13:42:03.451589
3223 13:42:03.451664 ==
3224 13:42:03.451738 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 13:42:03.451814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 13:42:03.451889 ==
3227 13:42:03.451964
3228 13:42:03.452038
3229 13:42:03.452113 TX Vref Scan disable
3230 13:42:03.452188 == TX Byte 0 ==
3231 13:42:03.452263 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3232 13:42:03.452547 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3233 13:42:03.452633 == TX Byte 1 ==
3234 13:42:03.452712 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3235 13:42:03.452789 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3236 13:42:03.452866
3237 13:42:03.452941 [DATLAT]
3238 13:42:03.453017 Freq=1200, CH1 RK0
3239 13:42:03.453094
3240 13:42:03.453169 DATLAT Default: 0xd
3241 13:42:03.453245 0, 0xFFFF, sum = 0
3242 13:42:03.453340 1, 0xFFFF, sum = 0
3243 13:42:03.453419 2, 0xFFFF, sum = 0
3244 13:42:03.453496 3, 0xFFFF, sum = 0
3245 13:42:03.453573 4, 0xFFFF, sum = 0
3246 13:42:03.453650 5, 0xFFFF, sum = 0
3247 13:42:03.453727 6, 0xFFFF, sum = 0
3248 13:42:03.453804 7, 0xFFFF, sum = 0
3249 13:42:03.453880 8, 0xFFFF, sum = 0
3250 13:42:03.453956 9, 0xFFFF, sum = 0
3251 13:42:03.454033 10, 0xFFFF, sum = 0
3252 13:42:03.454109 11, 0xFFFF, sum = 0
3253 13:42:03.454185 12, 0x0, sum = 1
3254 13:42:03.454261 13, 0x0, sum = 2
3255 13:42:03.454337 14, 0x0, sum = 3
3256 13:42:03.454414 15, 0x0, sum = 4
3257 13:42:03.454491 best_step = 13
3258 13:42:03.454566
3259 13:42:03.454640 ==
3260 13:42:03.454715 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 13:42:03.454790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 13:42:03.454867 ==
3263 13:42:03.454941 RX Vref Scan: 1
3264 13:42:03.455016
3265 13:42:03.455091 Set Vref Range= 32 -> 127
3266 13:42:03.455167
3267 13:42:03.455241 RX Vref 32 -> 127, step: 1
3268 13:42:03.455317
3269 13:42:03.455391 RX Delay -13 -> 252, step: 4
3270 13:42:03.455466
3271 13:42:03.455540 Set Vref, RX VrefLevel [Byte0]: 32
3272 13:42:03.455624 [Byte1]: 32
3273 13:42:03.455691
3274 13:42:03.455757 Set Vref, RX VrefLevel [Byte0]: 33
3275 13:42:03.455823 [Byte1]: 33
3276 13:42:03.455890
3277 13:42:03.455976 Set Vref, RX VrefLevel [Byte0]: 34
3278 13:42:03.456049 [Byte1]: 34
3279 13:42:03.456117
3280 13:42:03.456184 Set Vref, RX VrefLevel [Byte0]: 35
3281 13:42:03.456251 [Byte1]: 35
3282 13:42:03.456318
3283 13:42:03.456384 Set Vref, RX VrefLevel [Byte0]: 36
3284 13:42:03.456450 [Byte1]: 36
3285 13:42:03.456516
3286 13:42:03.456583 Set Vref, RX VrefLevel [Byte0]: 37
3287 13:42:03.456649 [Byte1]: 37
3288 13:42:03.456716
3289 13:42:03.456781 Set Vref, RX VrefLevel [Byte0]: 38
3290 13:42:03.456848 [Byte1]: 38
3291 13:42:03.456914
3292 13:42:03.456980 Set Vref, RX VrefLevel [Byte0]: 39
3293 13:42:03.457047 [Byte1]: 39
3294 13:42:03.457113
3295 13:42:03.457178 Set Vref, RX VrefLevel [Byte0]: 40
3296 13:42:03.457244 [Byte1]: 40
3297 13:42:03.457323
3298 13:42:03.457389 Set Vref, RX VrefLevel [Byte0]: 41
3299 13:42:03.457455 [Byte1]: 41
3300 13:42:03.457521
3301 13:42:03.457601 Set Vref, RX VrefLevel [Byte0]: 42
3302 13:42:03.457669 [Byte1]: 42
3303 13:42:03.457736
3304 13:42:03.457823 Set Vref, RX VrefLevel [Byte0]: 43
3305 13:42:03.457891 [Byte1]: 43
3306 13:42:03.457957
3307 13:42:03.458023 Set Vref, RX VrefLevel [Byte0]: 44
3308 13:42:03.458089 [Byte1]: 44
3309 13:42:03.458155
3310 13:42:03.458220 Set Vref, RX VrefLevel [Byte0]: 45
3311 13:42:03.458286 [Byte1]: 45
3312 13:42:03.458353
3313 13:42:03.458418 Set Vref, RX VrefLevel [Byte0]: 46
3314 13:42:03.458484 [Byte1]: 46
3315 13:42:03.458549
3316 13:42:03.458614 Set Vref, RX VrefLevel [Byte0]: 47
3317 13:42:03.458680 [Byte1]: 47
3318 13:42:03.458747
3319 13:42:03.458812 Set Vref, RX VrefLevel [Byte0]: 48
3320 13:42:03.458879 [Byte1]: 48
3321 13:42:03.458944
3322 13:42:03.459010 Set Vref, RX VrefLevel [Byte0]: 49
3323 13:42:03.459075 [Byte1]: 49
3324 13:42:03.459141
3325 13:42:03.459206 Set Vref, RX VrefLevel [Byte0]: 50
3326 13:42:03.459272 [Byte1]: 50
3327 13:42:03.459338
3328 13:42:03.459404 Set Vref, RX VrefLevel [Byte0]: 51
3329 13:42:03.459470 [Byte1]: 51
3330 13:42:03.459537
3331 13:42:03.459602 Set Vref, RX VrefLevel [Byte0]: 52
3332 13:42:03.459675 [Byte1]: 52
3333 13:42:03.459745
3334 13:42:03.459811 Set Vref, RX VrefLevel [Byte0]: 53
3335 13:42:03.459889 [Byte1]: 53
3336 13:42:03.459962
3337 13:42:03.460028 Set Vref, RX VrefLevel [Byte0]: 54
3338 13:42:03.460095 [Byte1]: 54
3339 13:42:03.460161
3340 13:42:03.460226 Set Vref, RX VrefLevel [Byte0]: 55
3341 13:42:03.460293 [Byte1]: 55
3342 13:42:03.460359
3343 13:42:03.460424 Set Vref, RX VrefLevel [Byte0]: 56
3344 13:42:03.460490 [Byte1]: 56
3345 13:42:03.460556
3346 13:42:03.460630 Set Vref, RX VrefLevel [Byte0]: 57
3347 13:42:03.460689 [Byte1]: 57
3348 13:42:03.460748
3349 13:42:03.460807 Set Vref, RX VrefLevel [Byte0]: 58
3350 13:42:03.460867 [Byte1]: 58
3351 13:42:03.460926
3352 13:42:03.460985 Set Vref, RX VrefLevel [Byte0]: 59
3353 13:42:03.461044 [Byte1]: 59
3354 13:42:03.461103
3355 13:42:03.461161 Set Vref, RX VrefLevel [Byte0]: 60
3356 13:42:03.461221 [Byte1]: 60
3357 13:42:03.461291
3358 13:42:03.461353 Set Vref, RX VrefLevel [Byte0]: 61
3359 13:42:03.461412 [Byte1]: 61
3360 13:42:03.461471
3361 13:42:03.461531 Set Vref, RX VrefLevel [Byte0]: 62
3362 13:42:03.461590 [Byte1]: 62
3363 13:42:03.461650
3364 13:42:03.461709 Set Vref, RX VrefLevel [Byte0]: 63
3365 13:42:03.461769 [Byte1]: 63
3366 13:42:03.461828
3367 13:42:03.461887 Set Vref, RX VrefLevel [Byte0]: 64
3368 13:42:03.461947 [Byte1]: 64
3369 13:42:03.462006
3370 13:42:03.462065 Set Vref, RX VrefLevel [Byte0]: 65
3371 13:42:03.462128 [Byte1]: 65
3372 13:42:03.462189
3373 13:42:03.462248 Set Vref, RX VrefLevel [Byte0]: 66
3374 13:42:03.462308 [Byte1]: 66
3375 13:42:03.462371
3376 13:42:03.462430 Final RX Vref Byte 0 = 50 to rank0
3377 13:42:03.462490 Final RX Vref Byte 1 = 53 to rank0
3378 13:42:03.462565 Final RX Vref Byte 0 = 50 to rank1
3379 13:42:03.462634 Final RX Vref Byte 1 = 53 to rank1==
3380 13:42:03.462695 Dram Type= 6, Freq= 0, CH_1, rank 0
3381 13:42:03.462755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3382 13:42:03.462828 ==
3383 13:42:03.462889 DQS Delay:
3384 13:42:03.462949 DQS0 = 0, DQS1 = 0
3385 13:42:03.463013 DQM Delay:
3386 13:42:03.463074 DQM0 = 117, DQM1 = 115
3387 13:42:03.463134 DQ Delay:
3388 13:42:03.463197 DQ0 =124, DQ1 =112, DQ2 =108, DQ3 =118
3389 13:42:03.463257 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3390 13:42:03.463317 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =110
3391 13:42:03.463377 DQ12 =124, DQ13 =122, DQ14 =124, DQ15 =122
3392 13:42:03.463437
3393 13:42:03.463496
3394 13:42:03.463555 [DQSOSCAuto] RK0, (LSB)MR18= 0xf704, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3395 13:42:03.463616 CH1 RK0: MR19=304, MR18=F704
3396 13:42:03.463677 CH1_RK0: MR19=0x304, MR18=0xF704, DQSOSC=408, MR23=63, INC=39, DEC=26
3397 13:42:03.463737
3398 13:42:03.463995 ----->DramcWriteLeveling(PI) begin...
3399 13:42:03.464067 ==
3400 13:42:03.464130 Dram Type= 6, Freq= 0, CH_1, rank 1
3401 13:42:03.464190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 13:42:03.464252 ==
3403 13:42:03.464311 Write leveling (Byte 0): 22 => 22
3404 13:42:03.464371 Write leveling (Byte 1): 27 => 27
3405 13:42:03.464431 DramcWriteLeveling(PI) end<-----
3406 13:42:03.464491
3407 13:42:03.464550 ==
3408 13:42:03.464610 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 13:42:03.464670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 13:42:03.464731 ==
3411 13:42:03.464791 [Gating] SW mode calibration
3412 13:42:03.464851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3413 13:42:03.464911 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3414 13:42:03.464971 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3415 13:42:03.465032 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3416 13:42:03.465092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 13:42:03.465154 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3418 13:42:03.465215 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3419 13:42:03.465285 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3420 13:42:03.465347 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
3421 13:42:03.465407 0 15 28 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
3422 13:42:03.465467 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3423 13:42:03.465528 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3424 13:42:03.465599 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 13:42:03.465653 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3426 13:42:03.465707 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3427 13:42:03.465774 1 0 20 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
3428 13:42:03.465832 1 0 24 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
3429 13:42:03.465886 1 0 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3430 13:42:03.465941 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3431 13:42:03.465995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3432 13:42:03.466050 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 13:42:03.466103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 13:42:03.466157 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3435 13:42:03.466211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3436 13:42:03.466265 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3437 13:42:03.466319 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3438 13:42:03.466374 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3439 13:42:03.466428 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 13:42:03.466483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 13:42:03.466537 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 13:42:03.466591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 13:42:03.466645 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 13:42:03.466699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 13:42:03.466753 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 13:42:03.466807 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 13:42:03.466862 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 13:42:03.466916 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 13:42:03.466971 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 13:42:03.467026 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 13:42:03.467081 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3452 13:42:03.467136 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3453 13:42:03.467189 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3454 13:42:03.467243 Total UI for P1: 0, mck2ui 16
3455 13:42:03.467297 best dqsien dly found for B0: ( 1, 3, 22)
3456 13:42:03.467352 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 13:42:03.467407 Total UI for P1: 0, mck2ui 16
3458 13:42:03.467462 best dqsien dly found for B1: ( 1, 3, 26)
3459 13:42:03.467517 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3460 13:42:03.467571 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3461 13:42:03.467625
3462 13:42:03.467679 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3463 13:42:03.467734 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3464 13:42:03.467788 [Gating] SW calibration Done
3465 13:42:03.467876 ==
3466 13:42:03.467954 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 13:42:03.468010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 13:42:03.468065 ==
3469 13:42:03.468120 RX Vref Scan: 0
3470 13:42:03.468175
3471 13:42:03.468229 RX Vref 0 -> 0, step: 1
3472 13:42:03.468283
3473 13:42:03.468337 RX Delay -40 -> 252, step: 8
3474 13:42:03.468392 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3475 13:42:03.468446 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3476 13:42:03.468500 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3477 13:42:03.468554 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3478 13:42:03.468609 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3479 13:42:03.468664 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3480 13:42:03.468718 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3481 13:42:03.468771 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3482 13:42:03.468825 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3483 13:42:03.468878 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3484 13:42:03.468932 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3485 13:42:03.468986 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3486 13:42:03.469040 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3487 13:42:03.469094 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3488 13:42:03.469149 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3489 13:42:03.469204 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3490 13:42:03.469263 ==
3491 13:42:03.469326 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 13:42:03.469381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 13:42:03.469436 ==
3494 13:42:03.469490 DQS Delay:
3495 13:42:03.469544 DQS0 = 0, DQS1 = 0
3496 13:42:03.469598 DQM Delay:
3497 13:42:03.469652 DQM0 = 116, DQM1 = 114
3498 13:42:03.469707 DQ Delay:
3499 13:42:03.469761 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3500 13:42:03.469816 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =111
3501 13:42:03.470062 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3502 13:42:03.470124 DQ12 =127, DQ13 =123, DQ14 =115, DQ15 =123
3503 13:42:03.470180
3504 13:42:03.470234
3505 13:42:03.470289 ==
3506 13:42:03.470343 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 13:42:03.470398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 13:42:03.470454 ==
3509 13:42:03.470508
3510 13:42:03.470562
3511 13:42:03.470628 TX Vref Scan disable
3512 13:42:03.470681 == TX Byte 0 ==
3513 13:42:03.470734 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3514 13:42:03.470788 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3515 13:42:03.470841 == TX Byte 1 ==
3516 13:42:03.470894 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3517 13:42:03.470947 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3518 13:42:03.471001 ==
3519 13:42:03.471054 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 13:42:03.471107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 13:42:03.471161 ==
3522 13:42:03.471214 TX Vref=22, minBit 3, minWin=24, winSum=417
3523 13:42:03.471270 TX Vref=24, minBit 2, minWin=25, winSum=424
3524 13:42:03.471325 TX Vref=26, minBit 0, minWin=26, winSum=425
3525 13:42:03.471378 TX Vref=28, minBit 1, minWin=26, winSum=425
3526 13:42:03.471432 TX Vref=30, minBit 3, minWin=26, winSum=433
3527 13:42:03.471489 TX Vref=32, minBit 2, minWin=26, winSum=430
3528 13:42:03.471543 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 30
3529 13:42:03.471598
3530 13:42:03.471654 Final TX Range 1 Vref 30
3531 13:42:03.471707
3532 13:42:03.471759 ==
3533 13:42:03.471811 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 13:42:03.471869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 13:42:03.471924 ==
3536 13:42:03.471985
3537 13:42:03.472042
3538 13:42:03.472096 TX Vref Scan disable
3539 13:42:03.472149 == TX Byte 0 ==
3540 13:42:03.472204 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3541 13:42:03.472259 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3542 13:42:03.472312 == TX Byte 1 ==
3543 13:42:03.472365 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3544 13:42:03.472423 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3545 13:42:03.472476
3546 13:42:03.472529 [DATLAT]
3547 13:42:03.472584 Freq=1200, CH1 RK1
3548 13:42:03.472639
3549 13:42:03.472691 DATLAT Default: 0xd
3550 13:42:03.472744 0, 0xFFFF, sum = 0
3551 13:42:03.472801 1, 0xFFFF, sum = 0
3552 13:42:03.472855 2, 0xFFFF, sum = 0
3553 13:42:03.472908 3, 0xFFFF, sum = 0
3554 13:42:03.472963 4, 0xFFFF, sum = 0
3555 13:42:03.473016 5, 0xFFFF, sum = 0
3556 13:42:03.473071 6, 0xFFFF, sum = 0
3557 13:42:03.473124 7, 0xFFFF, sum = 0
3558 13:42:03.473178 8, 0xFFFF, sum = 0
3559 13:42:03.473231 9, 0xFFFF, sum = 0
3560 13:42:03.473336 10, 0xFFFF, sum = 0
3561 13:42:03.473391 11, 0xFFFF, sum = 0
3562 13:42:03.473445 12, 0x0, sum = 1
3563 13:42:03.473499 13, 0x0, sum = 2
3564 13:42:03.473553 14, 0x0, sum = 3
3565 13:42:03.473607 15, 0x0, sum = 4
3566 13:42:03.473661 best_step = 13
3567 13:42:03.473713
3568 13:42:03.473766 ==
3569 13:42:03.473819 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 13:42:03.473872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 13:42:03.473926 ==
3572 13:42:03.473979 RX Vref Scan: 0
3573 13:42:03.474032
3574 13:42:03.474085 RX Vref 0 -> 0, step: 1
3575 13:42:03.474138
3576 13:42:03.474191 RX Delay -13 -> 252, step: 4
3577 13:42:03.474244 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3578 13:42:03.474298 iDelay=191, Bit 1, Center 112 (47 ~ 178) 132
3579 13:42:03.474351 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3580 13:42:03.474404 iDelay=191, Bit 3, Center 114 (51 ~ 178) 128
3581 13:42:03.474456 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3582 13:42:03.474510 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3583 13:42:03.474562 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3584 13:42:03.474616 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3585 13:42:03.474669 iDelay=191, Bit 8, Center 102 (43 ~ 162) 120
3586 13:42:03.474722 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3587 13:42:03.474775 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
3588 13:42:03.474828 iDelay=191, Bit 11, Center 108 (47 ~ 170) 124
3589 13:42:03.474882 iDelay=191, Bit 12, Center 122 (63 ~ 182) 120
3590 13:42:03.474935 iDelay=191, Bit 13, Center 120 (59 ~ 182) 124
3591 13:42:03.474988 iDelay=191, Bit 14, Center 118 (59 ~ 178) 120
3592 13:42:03.475041 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3593 13:42:03.475094 ==
3594 13:42:03.475147 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 13:42:03.475200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 13:42:03.475253 ==
3597 13:42:03.475306 DQS Delay:
3598 13:42:03.475359 DQS0 = 0, DQS1 = 0
3599 13:42:03.475412 DQM Delay:
3600 13:42:03.475465 DQM0 = 116, DQM1 = 114
3601 13:42:03.475517 DQ Delay:
3602 13:42:03.475570 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3603 13:42:03.475623 DQ4 =116, DQ5 =124, DQ6 =124, DQ7 =112
3604 13:42:03.475676 DQ8 =102, DQ9 =104, DQ10 =118, DQ11 =108
3605 13:42:03.475729 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3606 13:42:03.475782
3607 13:42:03.475835
3608 13:42:03.475888 [DQSOSCAuto] RK1, (LSB)MR18= 0xf809, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3609 13:42:03.475942 CH1 RK1: MR19=304, MR18=F809
3610 13:42:03.475995 CH1_RK1: MR19=0x304, MR18=0xF809, DQSOSC=406, MR23=63, INC=39, DEC=26
3611 13:42:03.476051 [RxdqsGatingPostProcess] freq 1200
3612 13:42:03.476105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3613 13:42:03.476158 best DQS0 dly(2T, 0.5T) = (0, 11)
3614 13:42:03.476211 best DQS1 dly(2T, 0.5T) = (0, 11)
3615 13:42:03.476264 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3616 13:42:03.476317 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3617 13:42:03.476370 best DQS0 dly(2T, 0.5T) = (0, 11)
3618 13:42:03.476423 best DQS1 dly(2T, 0.5T) = (0, 11)
3619 13:42:03.476476 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3620 13:42:03.476529 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3621 13:42:03.476582 Pre-setting of DQS Precalculation
3622 13:42:03.476634 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3623 13:42:03.476688 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3624 13:42:03.476742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3625 13:42:03.476795
3626 13:42:03.476847
3627 13:42:03.476900 [Calibration Summary] 2400 Mbps
3628 13:42:03.476953 CH 0, Rank 0
3629 13:42:03.477006 SW Impedance : PASS
3630 13:42:03.477059 DUTY Scan : NO K
3631 13:42:03.477112 ZQ Calibration : PASS
3632 13:42:03.477164 Jitter Meter : NO K
3633 13:42:03.477217 CBT Training : PASS
3634 13:42:03.477285 Write leveling : PASS
3635 13:42:03.477342 RX DQS gating : PASS
3636 13:42:03.477395 RX DQ/DQS(RDDQC) : PASS
3637 13:42:03.477449 TX DQ/DQS : PASS
3638 13:42:03.477502 RX DATLAT : PASS
3639 13:42:03.477555 RX DQ/DQS(Engine): PASS
3640 13:42:03.477608 TX OE : NO K
3641 13:42:03.477858 All Pass.
3642 13:42:03.477918
3643 13:42:03.477972 CH 0, Rank 1
3644 13:42:03.478025 SW Impedance : PASS
3645 13:42:03.478079 DUTY Scan : NO K
3646 13:42:03.478132 ZQ Calibration : PASS
3647 13:42:03.478186 Jitter Meter : NO K
3648 13:42:03.478239 CBT Training : PASS
3649 13:42:03.478293 Write leveling : PASS
3650 13:42:03.478345 RX DQS gating : PASS
3651 13:42:03.478399 RX DQ/DQS(RDDQC) : PASS
3652 13:42:03.478453 TX DQ/DQS : PASS
3653 13:42:03.478506 RX DATLAT : PASS
3654 13:42:03.478559 RX DQ/DQS(Engine): PASS
3655 13:42:03.478612 TX OE : NO K
3656 13:42:03.478666 All Pass.
3657 13:42:03.478719
3658 13:42:03.478771 CH 1, Rank 0
3659 13:42:03.478825 SW Impedance : PASS
3660 13:42:03.478878 DUTY Scan : NO K
3661 13:42:03.478930 ZQ Calibration : PASS
3662 13:42:03.478984 Jitter Meter : NO K
3663 13:42:03.479037 CBT Training : PASS
3664 13:42:03.479090 Write leveling : PASS
3665 13:42:03.479143 RX DQS gating : PASS
3666 13:42:03.479195 RX DQ/DQS(RDDQC) : PASS
3667 13:42:03.479247 TX DQ/DQS : PASS
3668 13:42:03.479300 RX DATLAT : PASS
3669 13:42:03.479353 RX DQ/DQS(Engine): PASS
3670 13:42:03.479406 TX OE : NO K
3671 13:42:03.479458 All Pass.
3672 13:42:03.479511
3673 13:42:03.479563 CH 1, Rank 1
3674 13:42:03.479616 SW Impedance : PASS
3675 13:42:03.479669 DUTY Scan : NO K
3676 13:42:03.479721 ZQ Calibration : PASS
3677 13:42:03.479774 Jitter Meter : NO K
3678 13:42:03.479827 CBT Training : PASS
3679 13:42:03.479880 Write leveling : PASS
3680 13:42:03.479985 RX DQS gating : PASS
3681 13:42:03.480071 RX DQ/DQS(RDDQC) : PASS
3682 13:42:03.480128 TX DQ/DQS : PASS
3683 13:42:03.480183 RX DATLAT : PASS
3684 13:42:03.480236 RX DQ/DQS(Engine): PASS
3685 13:42:03.480289 TX OE : NO K
3686 13:42:03.480342 All Pass.
3687 13:42:03.480395
3688 13:42:03.480448 DramC Write-DBI off
3689 13:42:03.480502 PER_BANK_REFRESH: Hybrid Mode
3690 13:42:03.480554 TX_TRACKING: ON
3691 13:42:03.480607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3692 13:42:03.480661 [FAST_K] Save calibration result to emmc
3693 13:42:03.480714 dramc_set_vcore_voltage set vcore to 650000
3694 13:42:03.480767 Read voltage for 600, 5
3695 13:42:03.480821 Vio18 = 0
3696 13:42:03.480874 Vcore = 650000
3697 13:42:03.480926 Vdram = 0
3698 13:42:03.480979 Vddq = 0
3699 13:42:03.481031 Vmddr = 0
3700 13:42:03.481083 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3701 13:42:03.481137 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3702 13:42:03.481190 MEM_TYPE=3, freq_sel=19
3703 13:42:03.481242 sv_algorithm_assistance_LP4_1600
3704 13:42:03.481394 ============ PULL DRAM RESETB DOWN ============
3705 13:42:03.481478 ========== PULL DRAM RESETB DOWN end =========
3706 13:42:03.481563 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3707 13:42:03.481646 ===================================
3708 13:42:03.481729 LPDDR4 DRAM CONFIGURATION
3709 13:42:03.481814 ===================================
3710 13:42:03.481882 EX_ROW_EN[0] = 0x0
3711 13:42:03.481937 EX_ROW_EN[1] = 0x0
3712 13:42:03.481990 LP4Y_EN = 0x0
3713 13:42:03.482043 WORK_FSP = 0x0
3714 13:42:03.482097 WL = 0x2
3715 13:42:03.482150 RL = 0x2
3716 13:42:03.482203 BL = 0x2
3717 13:42:03.482256 RPST = 0x0
3718 13:42:03.482309 RD_PRE = 0x0
3719 13:42:03.482361 WR_PRE = 0x1
3720 13:42:03.482414 WR_PST = 0x0
3721 13:42:03.482467 DBI_WR = 0x0
3722 13:42:03.482520 DBI_RD = 0x0
3723 13:42:03.482572 OTF = 0x1
3724 13:42:03.482626 ===================================
3725 13:42:03.482681 ===================================
3726 13:42:03.482743 ANA top config
3727 13:42:03.482797 ===================================
3728 13:42:03.482850 DLL_ASYNC_EN = 0
3729 13:42:03.482903 ALL_SLAVE_EN = 1
3730 13:42:03.482955 NEW_RANK_MODE = 1
3731 13:42:03.483009 DLL_IDLE_MODE = 1
3732 13:42:03.483062 LP45_APHY_COMB_EN = 1
3733 13:42:03.483114 TX_ODT_DIS = 1
3734 13:42:03.483167 NEW_8X_MODE = 1
3735 13:42:03.483221 ===================================
3736 13:42:03.483275 ===================================
3737 13:42:03.483329 data_rate = 1200
3738 13:42:03.483382 CKR = 1
3739 13:42:03.483435 DQ_P2S_RATIO = 8
3740 13:42:03.483488 ===================================
3741 13:42:03.483541 CA_P2S_RATIO = 8
3742 13:42:03.483594 DQ_CA_OPEN = 0
3743 13:42:03.483647 DQ_SEMI_OPEN = 0
3744 13:42:03.483700 CA_SEMI_OPEN = 0
3745 13:42:03.483752 CA_FULL_RATE = 0
3746 13:42:03.483805 DQ_CKDIV4_EN = 1
3747 13:42:03.483857 CA_CKDIV4_EN = 1
3748 13:42:03.483910 CA_PREDIV_EN = 0
3749 13:42:03.483962 PH8_DLY = 0
3750 13:42:03.484015 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3751 13:42:03.484067 DQ_AAMCK_DIV = 4
3752 13:42:03.484120 CA_AAMCK_DIV = 4
3753 13:42:03.484172 CA_ADMCK_DIV = 4
3754 13:42:03.484225 DQ_TRACK_CA_EN = 0
3755 13:42:03.484277 CA_PICK = 600
3756 13:42:03.484330 CA_MCKIO = 600
3757 13:42:03.484383 MCKIO_SEMI = 0
3758 13:42:03.484436 PLL_FREQ = 2288
3759 13:42:03.484488 DQ_UI_PI_RATIO = 32
3760 13:42:03.484541 CA_UI_PI_RATIO = 0
3761 13:42:03.484593 ===================================
3762 13:42:03.484645 ===================================
3763 13:42:03.484699 memory_type:LPDDR4
3764 13:42:03.484752 GP_NUM : 10
3765 13:42:03.484804 SRAM_EN : 1
3766 13:42:03.484857 MD32_EN : 0
3767 13:42:03.484910 ===================================
3768 13:42:03.484963 [ANA_INIT] >>>>>>>>>>>>>>
3769 13:42:03.485016 <<<<<< [CONFIGURE PHASE]: ANA_TX
3770 13:42:03.485070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3771 13:42:03.485123 ===================================
3772 13:42:03.485176 data_rate = 1200,PCW = 0X5800
3773 13:42:03.485228 ===================================
3774 13:42:03.485286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3775 13:42:03.485340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3776 13:42:03.485394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3777 13:42:03.485447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3778 13:42:03.485501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3779 13:42:03.485554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3780 13:42:03.485608 [ANA_INIT] flow start
3781 13:42:03.485661 [ANA_INIT] PLL >>>>>>>>
3782 13:42:03.485713 [ANA_INIT] PLL <<<<<<<<
3783 13:42:03.485765 [ANA_INIT] MIDPI >>>>>>>>
3784 13:42:03.486011 [ANA_INIT] MIDPI <<<<<<<<
3785 13:42:03.486074 [ANA_INIT] DLL >>>>>>>>
3786 13:42:03.486156 [ANA_INIT] flow end
3787 13:42:03.486215 ============ LP4 DIFF to SE enter ============
3788 13:42:03.486276 ============ LP4 DIFF to SE exit ============
3789 13:42:03.486345 [ANA_INIT] <<<<<<<<<<<<<
3790 13:42:03.486400 [Flow] Enable top DCM control >>>>>
3791 13:42:03.486454 [Flow] Enable top DCM control <<<<<
3792 13:42:03.486534 Enable DLL master slave shuffle
3793 13:42:03.486592 ==============================================================
3794 13:42:03.486646 Gating Mode config
3795 13:42:03.486700 ==============================================================
3796 13:42:03.486754 Config description:
3797 13:42:03.486808 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3798 13:42:03.486862 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3799 13:42:03.486917 SELPH_MODE 0: By rank 1: By Phase
3800 13:42:03.486971 ==============================================================
3801 13:42:03.487025 GAT_TRACK_EN = 1
3802 13:42:03.487078 RX_GATING_MODE = 2
3803 13:42:03.487132 RX_GATING_TRACK_MODE = 2
3804 13:42:03.487185 SELPH_MODE = 1
3805 13:42:03.487238 PICG_EARLY_EN = 1
3806 13:42:03.487292 VALID_LAT_VALUE = 1
3807 13:42:03.487345 ==============================================================
3808 13:42:03.487399 Enter into Gating configuration >>>>
3809 13:42:03.487452 Exit from Gating configuration <<<<
3810 13:42:03.487506 Enter into DVFS_PRE_config >>>>>
3811 13:42:03.487560 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3812 13:42:03.487615 Exit from DVFS_PRE_config <<<<<
3813 13:42:03.487668 Enter into PICG configuration >>>>
3814 13:42:03.487721 Exit from PICG configuration <<<<
3815 13:42:03.487774 [RX_INPUT] configuration >>>>>
3816 13:42:03.487827 [RX_INPUT] configuration <<<<<
3817 13:42:03.487881 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3818 13:42:03.487941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3819 13:42:03.488017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3820 13:42:03.488104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3821 13:42:03.488161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3822 13:42:03.488216 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3823 13:42:03.488269 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3824 13:42:03.488323 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3825 13:42:03.488377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3826 13:42:03.488431 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3827 13:42:03.488484 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3828 13:42:03.488537 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3829 13:42:03.488591 ===================================
3830 13:42:03.488645 LPDDR4 DRAM CONFIGURATION
3831 13:42:03.488697 ===================================
3832 13:42:03.488750 EX_ROW_EN[0] = 0x0
3833 13:42:03.488803 EX_ROW_EN[1] = 0x0
3834 13:42:03.488856 LP4Y_EN = 0x0
3835 13:42:03.488909 WORK_FSP = 0x0
3836 13:42:03.488962 WL = 0x2
3837 13:42:03.489014 RL = 0x2
3838 13:42:03.489067 BL = 0x2
3839 13:42:03.489120 RPST = 0x0
3840 13:42:03.489172 RD_PRE = 0x0
3841 13:42:03.489225 WR_PRE = 0x1
3842 13:42:03.489289 WR_PST = 0x0
3843 13:42:03.489343 DBI_WR = 0x0
3844 13:42:03.489395 DBI_RD = 0x0
3845 13:42:03.489447 OTF = 0x1
3846 13:42:03.489501 ===================================
3847 13:42:03.489554 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3848 13:42:03.489609 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3849 13:42:03.489663 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 13:42:03.489716 ===================================
3851 13:42:03.489769 LPDDR4 DRAM CONFIGURATION
3852 13:42:03.489822 ===================================
3853 13:42:03.489875 EX_ROW_EN[0] = 0x10
3854 13:42:03.489928 EX_ROW_EN[1] = 0x0
3855 13:42:03.489981 LP4Y_EN = 0x0
3856 13:42:03.490033 WORK_FSP = 0x0
3857 13:42:03.490086 WL = 0x2
3858 13:42:03.490139 RL = 0x2
3859 13:42:03.490192 BL = 0x2
3860 13:42:03.490244 RPST = 0x0
3861 13:42:03.490296 RD_PRE = 0x0
3862 13:42:03.490349 WR_PRE = 0x1
3863 13:42:03.490401 WR_PST = 0x0
3864 13:42:03.490454 DBI_WR = 0x0
3865 13:42:03.490506 DBI_RD = 0x0
3866 13:42:03.490559 OTF = 0x1
3867 13:42:03.490612 ===================================
3868 13:42:03.490665 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3869 13:42:03.490719 nWR fixed to 30
3870 13:42:03.490772 [ModeRegInit_LP4] CH0 RK0
3871 13:42:03.490825 [ModeRegInit_LP4] CH0 RK1
3872 13:42:03.490877 [ModeRegInit_LP4] CH1 RK0
3873 13:42:03.490930 [ModeRegInit_LP4] CH1 RK1
3874 13:42:03.490982 match AC timing 17
3875 13:42:03.491035 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3876 13:42:03.491088 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3877 13:42:03.491141 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3878 13:42:03.491194 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3879 13:42:03.491247 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3880 13:42:03.491300 ==
3881 13:42:03.491354 Dram Type= 6, Freq= 0, CH_0, rank 0
3882 13:42:03.491407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3883 13:42:03.491460 ==
3884 13:42:03.491513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3885 13:42:03.491567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3886 13:42:03.491621 [CA 0] Center 36 (6~67) winsize 62
3887 13:42:03.491675 [CA 1] Center 36 (6~67) winsize 62
3888 13:42:03.491729 [CA 2] Center 34 (4~65) winsize 62
3889 13:42:03.491781 [CA 3] Center 34 (4~65) winsize 62
3890 13:42:03.491834 [CA 4] Center 33 (3~64) winsize 62
3891 13:42:03.491886 [CA 5] Center 33 (2~64) winsize 63
3892 13:42:03.491939
3893 13:42:03.492182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3894 13:42:03.492246
3895 13:42:03.492300 [CATrainingPosCal] consider 1 rank data
3896 13:42:03.492354 u2DelayCellTimex100 = 270/100 ps
3897 13:42:03.492407 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3898 13:42:03.492462 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3899 13:42:03.492515 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3900 13:42:03.492569 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3901 13:42:03.492622 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3902 13:42:03.492676 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3903 13:42:03.492728
3904 13:42:03.492780 CA PerBit enable=1, Macro0, CA PI delay=33
3905 13:42:03.492834
3906 13:42:03.492887 [CBTSetCACLKResult] CA Dly = 33
3907 13:42:03.492941 CS Dly: 6 (0~37)
3908 13:42:03.492994 ==
3909 13:42:03.493047 Dram Type= 6, Freq= 0, CH_0, rank 1
3910 13:42:03.493100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 13:42:03.493153 ==
3912 13:42:03.493206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 13:42:03.493266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3914 13:42:03.493321 [CA 0] Center 36 (6~67) winsize 62
3915 13:42:03.493375 [CA 1] Center 36 (6~67) winsize 62
3916 13:42:03.493428 [CA 2] Center 34 (4~65) winsize 62
3917 13:42:03.493481 [CA 3] Center 34 (4~65) winsize 62
3918 13:42:03.493533 [CA 4] Center 33 (3~64) winsize 62
3919 13:42:03.493598 [CA 5] Center 33 (3~64) winsize 62
3920 13:42:03.493653
3921 13:42:03.496043 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3922 13:42:03.496292
3923 13:42:03.499901 [CATrainingPosCal] consider 2 rank data
3924 13:42:03.503037 u2DelayCellTimex100 = 270/100 ps
3925 13:42:03.506061 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 13:42:03.512717 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 13:42:03.858128 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 13:42:03.858609 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 13:42:03.858940 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 13:42:03.859252 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 13:42:03.859552
3932 13:42:03.859841 CA PerBit enable=1, Macro0, CA PI delay=33
3933 13:42:03.860129
3934 13:42:03.860409 [CBTSetCACLKResult] CA Dly = 33
3935 13:42:03.860689 CS Dly: 6 (0~38)
3936 13:42:03.860964
3937 13:42:03.861457 ----->DramcWriteLeveling(PI) begin...
3938 13:42:03.861824 ==
3939 13:42:03.862113 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 13:42:03.862391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 13:42:03.862670 ==
3942 13:42:03.862942 Write leveling (Byte 0): 33 => 33
3943 13:42:03.863216 Write leveling (Byte 1): 30 => 30
3944 13:42:03.863488 DramcWriteLeveling(PI) end<-----
3945 13:42:03.863758
3946 13:42:03.864026 ==
3947 13:42:03.864297 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 13:42:03.864618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 13:42:03.864974 ==
3950 13:42:03.865423 [Gating] SW mode calibration
3951 13:42:03.865760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3952 13:42:03.866045 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3953 13:42:03.866322 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3954 13:42:03.866598 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3955 13:42:03.866873 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3956 13:42:03.867142 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
3957 13:42:03.867414 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
3958 13:42:03.867720 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 13:42:03.868046 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3960 13:42:03.868350 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 13:42:03.868621 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 13:42:03.868890 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3963 13:42:03.869162 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3964 13:42:03.869479 0 10 12 | B1->B0 | 2929 2d2d | 1 0 | (0 0) (0 0)
3965 13:42:03.869755 0 10 16 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
3966 13:42:03.870025 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 13:42:03.870296 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3968 13:42:03.870565 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 13:42:03.870892 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 13:42:03.871287 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3971 13:42:03.871572 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3972 13:42:03.871847 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3973 13:42:03.872118 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3974 13:42:03.872389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 13:42:03.872658 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 13:42:03.872927 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 13:42:03.873194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 13:42:03.873510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 13:42:03.873785 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 13:42:03.874054 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 13:42:03.874370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 13:42:03.874718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 13:42:03.874996 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 13:42:03.875266 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 13:42:03.875533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 13:42:03.875802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 13:42:03.876072 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 13:42:03.876343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3989 13:42:03.876609 Total UI for P1: 0, mck2ui 16
3990 13:42:03.876880 best dqsien dly found for B0: ( 0, 13, 10)
3991 13:42:03.877154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3992 13:42:03.877509 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 13:42:03.877879 Total UI for P1: 0, mck2ui 16
3994 13:42:03.878162 best dqsien dly found for B1: ( 0, 13, 16)
3995 13:42:03.878439 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
3996 13:42:03.878712 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
3997 13:42:03.878983
3998 13:42:03.879253 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
3999 13:42:03.879526 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4000 13:42:03.879795 [Gating] SW calibration Done
4001 13:42:03.880063 ==
4002 13:42:03.880332 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 13:42:03.880637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 13:42:03.880987 ==
4005 13:42:03.881425 RX Vref Scan: 0
4006 13:42:03.881710
4007 13:42:03.881982 RX Vref 0 -> 0, step: 1
4008 13:42:03.882256
4009 13:42:03.882528 RX Delay -230 -> 252, step: 16
4010 13:42:03.882797 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4011 13:42:03.883066 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4012 13:42:03.883335 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4013 13:42:03.883604 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4014 13:42:03.883915 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4015 13:42:03.884282 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4016 13:42:03.884574 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4017 13:42:03.884791 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4018 13:42:03.884983 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4019 13:42:03.885177 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4020 13:42:03.885404 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4021 13:42:03.885600 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4022 13:42:03.885792 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4023 13:42:03.885984 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4024 13:42:03.886195 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4025 13:42:03.886387 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4026 13:42:03.886579 ==
4027 13:42:03.886772 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 13:42:03.887012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 13:42:03.887220 ==
4030 13:42:03.887417 DQS Delay:
4031 13:42:03.887641 DQS0 = 0, DQS1 = 0
4032 13:42:03.888176 DQM Delay:
4033 13:42:03.888396 DQM0 = 42, DQM1 = 34
4034 13:42:03.888595 DQ Delay:
4035 13:42:03.888790 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4036 13:42:03.888986 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4037 13:42:03.889183 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4038 13:42:03.889418 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4039 13:42:03.889621
4040 13:42:03.889767
4041 13:42:03.889913 ==
4042 13:42:03.890124 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 13:42:03.891370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 13:42:03.891596 ==
4045 13:42:03.891774
4046 13:42:03.891938
4047 13:42:03.894180 TX Vref Scan disable
4048 13:42:03.894410 == TX Byte 0 ==
4049 13:42:03.900765 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4050 13:42:03.904324 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4051 13:42:03.904567 == TX Byte 1 ==
4052 13:42:03.910802 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4053 13:42:03.914134 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4054 13:42:03.914371 ==
4055 13:42:03.917251 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 13:42:03.921110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 13:42:03.921321 ==
4058 13:42:03.921533
4059 13:42:03.924182
4060 13:42:03.924436 TX Vref Scan disable
4061 13:42:03.927529 == TX Byte 0 ==
4062 13:42:03.930739 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4063 13:42:03.937729 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4064 13:42:03.938064 == TX Byte 1 ==
4065 13:42:03.941112 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4066 13:42:03.947533 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4067 13:42:03.947978
4068 13:42:03.948318 [DATLAT]
4069 13:42:03.948680 Freq=600, CH0 RK0
4070 13:42:03.949209
4071 13:42:03.950855 DATLAT Default: 0x9
4072 13:42:03.954065 0, 0xFFFF, sum = 0
4073 13:42:03.954465 1, 0xFFFF, sum = 0
4074 13:42:03.957683 2, 0xFFFF, sum = 0
4075 13:42:03.958084 3, 0xFFFF, sum = 0
4076 13:42:03.960591 4, 0xFFFF, sum = 0
4077 13:42:03.961050 5, 0xFFFF, sum = 0
4078 13:42:03.964212 6, 0xFFFF, sum = 0
4079 13:42:03.964706 7, 0xFFFF, sum = 0
4080 13:42:03.967638 8, 0x0, sum = 1
4081 13:42:03.968133 9, 0x0, sum = 2
4082 13:42:03.970516 10, 0x0, sum = 3
4083 13:42:03.970918 11, 0x0, sum = 4
4084 13:42:03.971239 best_step = 9
4085 13:42:03.971616
4086 13:42:03.974337 ==
4087 13:42:03.977500 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 13:42:03.981188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 13:42:03.981732 ==
4090 13:42:03.982049 RX Vref Scan: 1
4091 13:42:03.982342
4092 13:42:03.984043 RX Vref 0 -> 0, step: 1
4093 13:42:03.984435
4094 13:42:03.987486 RX Delay -195 -> 252, step: 8
4095 13:42:03.987971
4096 13:42:03.991039 Set Vref, RX VrefLevel [Byte0]: 57
4097 13:42:03.994326 [Byte1]: 59
4098 13:42:03.994792
4099 13:42:03.997683 Final RX Vref Byte 0 = 57 to rank0
4100 13:42:04.000550 Final RX Vref Byte 1 = 59 to rank0
4101 13:42:04.003881 Final RX Vref Byte 0 = 57 to rank1
4102 13:42:04.007007 Final RX Vref Byte 1 = 59 to rank1==
4103 13:42:04.011001 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 13:42:04.014165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 13:42:04.017352 ==
4106 13:42:04.017836 DQS Delay:
4107 13:42:04.018151 DQS0 = 0, DQS1 = 0
4108 13:42:04.020726 DQM Delay:
4109 13:42:04.021208 DQM0 = 40, DQM1 = 32
4110 13:42:04.024243 DQ Delay:
4111 13:42:04.024771 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4112 13:42:04.026965 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4113 13:42:04.030190 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4114 13:42:04.034146 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4115 13:42:04.036860
4116 13:42:04.037387
4117 13:42:04.043427 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4118 13:42:04.046516 CH0 RK0: MR19=808, MR18=5047
4119 13:42:04.053188 CH0_RK0: MR19=0x808, MR18=0x5047, DQSOSC=394, MR23=63, INC=168, DEC=112
4120 13:42:04.053656
4121 13:42:04.056819 ----->DramcWriteLeveling(PI) begin...
4122 13:42:04.057569 ==
4123 13:42:04.059940 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 13:42:04.063273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 13:42:04.063699 ==
4126 13:42:04.066248 Write leveling (Byte 0): 33 => 33
4127 13:42:04.069434 Write leveling (Byte 1): 31 => 31
4128 13:42:04.072978 DramcWriteLeveling(PI) end<-----
4129 13:42:04.073543
4130 13:42:04.073881 ==
4131 13:42:04.076659 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 13:42:04.080091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 13:42:04.080612 ==
4134 13:42:04.083070 [Gating] SW mode calibration
4135 13:42:04.089463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4136 13:42:04.096128 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4137 13:42:04.099491 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4138 13:42:04.105626 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4139 13:42:04.109675 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4140 13:42:04.112887 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
4141 13:42:04.119247 0 9 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (1 1)
4142 13:42:04.122681 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4143 13:42:04.125544 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 13:42:04.131916 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 13:42:04.136001 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 13:42:04.139067 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4147 13:42:04.145223 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4148 13:42:04.148419 0 10 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
4149 13:42:04.152408 0 10 16 | B1->B0 | 3b3b 4343 | 0 1 | (0 0) (0 0)
4150 13:42:04.158149 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4151 13:42:04.161784 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 13:42:04.165566 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 13:42:04.172279 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 13:42:04.175186 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 13:42:04.178277 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4156 13:42:04.185245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4157 13:42:04.188600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4158 13:42:04.192065 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 13:42:04.198184 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 13:42:04.201359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 13:42:04.205493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 13:42:04.211445 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 13:42:04.215091 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 13:42:04.218215 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 13:42:04.225005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 13:42:04.227856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 13:42:04.231462 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 13:42:04.237952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 13:42:04.241167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 13:42:04.244020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 13:42:04.250943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 13:42:04.253878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4173 13:42:04.257632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4174 13:42:04.260924 Total UI for P1: 0, mck2ui 16
4175 13:42:04.263750 best dqsien dly found for B0: ( 0, 13, 12)
4176 13:42:04.270253 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 13:42:04.270858 Total UI for P1: 0, mck2ui 16
4178 13:42:04.277168 best dqsien dly found for B1: ( 0, 13, 14)
4179 13:42:04.280342 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4180 13:42:04.283625 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4181 13:42:04.284061
4182 13:42:04.286972 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4183 13:42:04.290163 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4184 13:42:04.293050 [Gating] SW calibration Done
4185 13:42:04.293323 ==
4186 13:42:04.296581 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 13:42:04.299516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 13:42:04.299721 ==
4189 13:42:04.303194 RX Vref Scan: 0
4190 13:42:04.303364
4191 13:42:04.306446 RX Vref 0 -> 0, step: 1
4192 13:42:04.306601
4193 13:42:04.306710 RX Delay -230 -> 252, step: 16
4194 13:42:04.312842 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4195 13:42:04.316065 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4196 13:42:04.319163 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4197 13:42:04.322293 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4198 13:42:04.329317 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4199 13:42:04.332720 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4200 13:42:04.336149 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4201 13:42:04.339609 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4202 13:42:04.346018 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4203 13:42:04.349170 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4204 13:42:04.352406 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4205 13:42:04.356231 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4206 13:42:04.362579 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4207 13:42:04.366162 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4208 13:42:04.369093 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4209 13:42:04.372706 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4210 13:42:04.373128 ==
4211 13:42:04.375910 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 13:42:04.382191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 13:42:04.382615 ==
4214 13:42:04.382948 DQS Delay:
4215 13:42:04.385371 DQS0 = 0, DQS1 = 0
4216 13:42:04.385793 DQM Delay:
4217 13:42:04.386128 DQM0 = 43, DQM1 = 33
4218 13:42:04.389100 DQ Delay:
4219 13:42:04.392248 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4220 13:42:04.395747 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4221 13:42:04.398908 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4222 13:42:04.402017 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4223 13:42:04.402440
4224 13:42:04.402794
4225 13:42:04.403106 ==
4226 13:42:04.405415 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 13:42:04.409002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 13:42:04.409601 ==
4229 13:42:04.409947
4230 13:42:04.410262
4231 13:42:04.412021 TX Vref Scan disable
4232 13:42:04.415104 == TX Byte 0 ==
4233 13:42:04.418176 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4234 13:42:04.421573 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4235 13:42:04.424757 == TX Byte 1 ==
4236 13:42:04.427973 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4237 13:42:04.431666 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4238 13:42:04.432094 ==
4239 13:42:04.434777 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 13:42:04.441147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 13:42:04.441739 ==
4242 13:42:04.442270
4243 13:42:04.442599
4244 13:42:04.442910 TX Vref Scan disable
4245 13:42:04.445739 == TX Byte 0 ==
4246 13:42:04.448962 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4247 13:42:04.455288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4248 13:42:04.455589 == TX Byte 1 ==
4249 13:42:04.458514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4250 13:42:04.465710 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4251 13:42:04.465897
4252 13:42:04.466038 [DATLAT]
4253 13:42:04.466170 Freq=600, CH0 RK1
4254 13:42:04.466299
4255 13:42:04.468801 DATLAT Default: 0x9
4256 13:42:04.468976 0, 0xFFFF, sum = 0
4257 13:42:04.471795 1, 0xFFFF, sum = 0
4258 13:42:04.474925 2, 0xFFFF, sum = 0
4259 13:42:04.475080 3, 0xFFFF, sum = 0
4260 13:42:04.478758 4, 0xFFFF, sum = 0
4261 13:42:04.478874 5, 0xFFFF, sum = 0
4262 13:42:04.482037 6, 0xFFFF, sum = 0
4263 13:42:04.482140 7, 0xFFFF, sum = 0
4264 13:42:04.485147 8, 0x0, sum = 1
4265 13:42:04.485341 9, 0x0, sum = 2
4266 13:42:04.488023 10, 0x0, sum = 3
4267 13:42:04.488167 11, 0x0, sum = 4
4268 13:42:04.488243 best_step = 9
4269 13:42:04.488311
4270 13:42:04.491413 ==
4271 13:42:04.494970 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 13:42:04.498483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 13:42:04.498913 ==
4274 13:42:04.499322 RX Vref Scan: 0
4275 13:42:04.499703
4276 13:42:04.501601 RX Vref 0 -> 0, step: 1
4277 13:42:04.502004
4278 13:42:04.505414 RX Delay -195 -> 252, step: 8
4279 13:42:04.511630 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4280 13:42:04.514777 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4281 13:42:04.518276 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4282 13:42:04.522200 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4283 13:42:04.524771 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4284 13:42:04.531884 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4285 13:42:04.534865 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4286 13:42:04.538108 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4287 13:42:04.541409 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4288 13:42:04.547898 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4289 13:42:04.551542 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4290 13:42:04.555027 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4291 13:42:04.557890 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4292 13:42:04.564802 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4293 13:42:04.567731 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4294 13:42:04.571098 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4295 13:42:04.571643 ==
4296 13:42:04.574626 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 13:42:04.577832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 13:42:04.580926 ==
4299 13:42:04.581387 DQS Delay:
4300 13:42:04.581735 DQS0 = 0, DQS1 = 0
4301 13:42:04.584184 DQM Delay:
4302 13:42:04.584609 DQM0 = 41, DQM1 = 33
4303 13:42:04.587173 DQ Delay:
4304 13:42:04.587599 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4305 13:42:04.590642 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4306 13:42:04.593877 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4307 13:42:04.597035 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4308 13:42:04.600389
4309 13:42:04.600811
4310 13:42:04.607683 [DQSOSCAuto] RK1, (LSB)MR18= 0x4642, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4311 13:42:04.610300 CH0 RK1: MR19=808, MR18=4642
4312 13:42:04.616881 CH0_RK1: MR19=0x808, MR18=0x4642, DQSOSC=396, MR23=63, INC=167, DEC=111
4313 13:42:04.620110 [RxdqsGatingPostProcess] freq 600
4314 13:42:04.624033 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4315 13:42:04.627002 Pre-setting of DQS Precalculation
4316 13:42:04.634034 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4317 13:42:04.634555 ==
4318 13:42:04.637138 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 13:42:04.640065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 13:42:04.640587 ==
4321 13:42:04.646962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4322 13:42:04.653039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4323 13:42:04.656901 [CA 0] Center 36 (6~66) winsize 61
4324 13:42:04.660283 [CA 1] Center 36 (6~66) winsize 61
4325 13:42:04.662812 [CA 2] Center 34 (4~65) winsize 62
4326 13:42:04.666352 [CA 3] Center 34 (4~65) winsize 62
4327 13:42:04.669644 [CA 4] Center 34 (4~65) winsize 62
4328 13:42:04.673148 [CA 5] Center 34 (3~65) winsize 63
4329 13:42:04.673826
4330 13:42:04.676428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4331 13:42:04.676948
4332 13:42:04.679806 [CATrainingPosCal] consider 1 rank data
4333 13:42:04.683073 u2DelayCellTimex100 = 270/100 ps
4334 13:42:04.686023 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4335 13:42:04.689551 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4336 13:42:04.692818 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4337 13:42:04.695999 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4338 13:42:04.699273 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4339 13:42:04.702920 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4340 13:42:04.703382
4341 13:42:04.709136 CA PerBit enable=1, Macro0, CA PI delay=34
4342 13:42:04.709585
4343 13:42:04.712368 [CBTSetCACLKResult] CA Dly = 34
4344 13:42:04.712791 CS Dly: 5 (0~36)
4345 13:42:04.713189 ==
4346 13:42:04.715433 Dram Type= 6, Freq= 0, CH_1, rank 1
4347 13:42:04.719290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 13:42:04.719721 ==
4349 13:42:04.725726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 13:42:04.732027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4351 13:42:04.735443 [CA 0] Center 36 (6~66) winsize 61
4352 13:42:04.738784 [CA 1] Center 36 (6~66) winsize 61
4353 13:42:04.741832 [CA 2] Center 34 (4~65) winsize 62
4354 13:42:04.745034 [CA 3] Center 34 (3~65) winsize 63
4355 13:42:04.748774 [CA 4] Center 34 (3~65) winsize 63
4356 13:42:04.752131 [CA 5] Center 34 (3~65) winsize 63
4357 13:42:04.752563
4358 13:42:04.755002 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4359 13:42:04.755424
4360 13:42:04.758647 [CATrainingPosCal] consider 2 rank data
4361 13:42:04.761858 u2DelayCellTimex100 = 270/100 ps
4362 13:42:04.765212 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4363 13:42:04.768702 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4364 13:42:04.771912 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 13:42:04.778512 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4366 13:42:04.781656 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4367 13:42:04.785221 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4368 13:42:04.785702
4369 13:42:04.788574 CA PerBit enable=1, Macro0, CA PI delay=34
4370 13:42:04.788999
4371 13:42:04.791484 [CBTSetCACLKResult] CA Dly = 34
4372 13:42:04.791907 CS Dly: 4 (0~35)
4373 13:42:04.792246
4374 13:42:04.795059 ----->DramcWriteLeveling(PI) begin...
4375 13:42:04.798148 ==
4376 13:42:04.798571 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 13:42:04.804781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 13:42:04.805206 ==
4379 13:42:04.807954 Write leveling (Byte 0): 28 => 28
4380 13:42:04.811018 Write leveling (Byte 1): 28 => 28
4381 13:42:04.814303 DramcWriteLeveling(PI) end<-----
4382 13:42:04.814724
4383 13:42:04.815055 ==
4384 13:42:04.817691 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 13:42:04.820780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 13:42:04.821206 ==
4387 13:42:04.823911 [Gating] SW mode calibration
4388 13:42:04.830963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4389 13:42:04.837544 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4390 13:42:04.840797 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4391 13:42:04.844107 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4392 13:42:04.850498 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4393 13:42:04.853695 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
4394 13:42:04.857429 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 13:42:04.863898 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 13:42:04.867065 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 13:42:04.870696 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 13:42:04.877361 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 13:42:04.880967 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 13:42:04.883568 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 13:42:04.890040 0 10 12 | B1->B0 | 3131 3535 | 1 1 | (0 0) (0 0)
4402 13:42:04.893596 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 13:42:04.897223 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 13:42:04.903565 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 13:42:04.907025 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 13:42:04.910267 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 13:42:04.916995 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 13:42:04.920152 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 13:42:04.923353 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4410 13:42:04.929924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4411 13:42:04.933201 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 13:42:04.936920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 13:42:04.943028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 13:42:04.946044 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 13:42:04.949728 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 13:42:04.956242 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 13:42:04.959250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 13:42:04.963047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 13:42:04.969483 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 13:42:04.973040 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 13:42:04.975992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:42:04.982684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:42:04.985757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:42:04.988806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:42:04.995353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4426 13:42:04.995830 Total UI for P1: 0, mck2ui 16
4427 13:42:05.001935 best dqsien dly found for B0: ( 0, 13, 10)
4428 13:42:05.005411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:42:05.008820 Total UI for P1: 0, mck2ui 16
4430 13:42:05.012865 best dqsien dly found for B1: ( 0, 13, 12)
4431 13:42:05.015807 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4432 13:42:05.018452 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4433 13:42:05.018840
4434 13:42:05.022122 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4435 13:42:05.025614 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4436 13:42:05.028657 [Gating] SW calibration Done
4437 13:42:05.029042 ==
4438 13:42:05.031976 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 13:42:05.038642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 13:42:05.039163 ==
4441 13:42:05.039519 RX Vref Scan: 0
4442 13:42:05.039813
4443 13:42:05.041679 RX Vref 0 -> 0, step: 1
4444 13:42:05.042064
4445 13:42:05.045353 RX Delay -230 -> 252, step: 16
4446 13:42:05.048649 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4447 13:42:05.051745 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4448 13:42:05.055363 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4449 13:42:05.061633 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4450 13:42:05.064895 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4451 13:42:05.068467 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4452 13:42:05.071328 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4453 13:42:05.077741 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4454 13:42:05.081060 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4455 13:42:05.084464 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4456 13:42:05.087643 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4457 13:42:05.093949 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4458 13:42:05.097507 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4459 13:42:05.101201 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4460 13:42:05.104571 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4461 13:42:05.111049 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4462 13:42:05.111563 ==
4463 13:42:05.114012 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 13:42:05.117475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 13:42:05.117988 ==
4466 13:42:05.118327 DQS Delay:
4467 13:42:05.120655 DQS0 = 0, DQS1 = 0
4468 13:42:05.121172 DQM Delay:
4469 13:42:05.123762 DQM0 = 46, DQM1 = 38
4470 13:42:05.124277 DQ Delay:
4471 13:42:05.127224 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4472 13:42:05.129974 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4473 13:42:05.133587 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4474 13:42:05.136871 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4475 13:42:05.137335
4476 13:42:05.137678
4477 13:42:05.137986 ==
4478 13:42:05.140741 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 13:42:05.143413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 13:42:05.146711 ==
4481 13:42:05.147132
4482 13:42:05.147462
4483 13:42:05.147782 TX Vref Scan disable
4484 13:42:05.150326 == TX Byte 0 ==
4485 13:42:05.153548 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4486 13:42:05.160357 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4487 13:42:05.160871 == TX Byte 1 ==
4488 13:42:05.163278 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4489 13:42:05.170504 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4490 13:42:05.171022 ==
4491 13:42:05.173427 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 13:42:05.176397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 13:42:05.176816 ==
4494 13:42:05.177143
4495 13:42:05.177530
4496 13:42:05.179968 TX Vref Scan disable
4497 13:42:05.183725 == TX Byte 0 ==
4498 13:42:05.186678 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 13:42:05.189703 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 13:42:05.192814 == TX Byte 1 ==
4501 13:42:05.196510 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4502 13:42:05.199497 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4503 13:42:05.199957
4504 13:42:05.200437 [DATLAT]
4505 13:42:05.203394 Freq=600, CH1 RK0
4506 13:42:05.203913
4507 13:42:05.206132 DATLAT Default: 0x9
4508 13:42:05.206551 0, 0xFFFF, sum = 0
4509 13:42:05.209399 1, 0xFFFF, sum = 0
4510 13:42:05.209917 2, 0xFFFF, sum = 0
4511 13:42:05.212999 3, 0xFFFF, sum = 0
4512 13:42:05.213478 4, 0xFFFF, sum = 0
4513 13:42:05.216692 5, 0xFFFF, sum = 0
4514 13:42:05.217333 6, 0xFFFF, sum = 0
4515 13:42:05.219538 7, 0xFFFF, sum = 0
4516 13:42:05.219957 8, 0x0, sum = 1
4517 13:42:05.222902 9, 0x0, sum = 2
4518 13:42:05.223424 10, 0x0, sum = 3
4519 13:42:05.225854 11, 0x0, sum = 4
4520 13:42:05.226276 best_step = 9
4521 13:42:05.226605
4522 13:42:05.226912 ==
4523 13:42:05.229169 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 13:42:05.232357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 13:42:05.232782 ==
4526 13:42:05.235824 RX Vref Scan: 1
4527 13:42:05.236340
4528 13:42:05.239801 RX Vref 0 -> 0, step: 1
4529 13:42:05.240314
4530 13:42:05.240658 RX Delay -179 -> 252, step: 8
4531 13:42:05.240972
4532 13:42:05.242848 Set Vref, RX VrefLevel [Byte0]: 50
4533 13:42:05.245990 [Byte1]: 53
4534 13:42:05.250174
4535 13:42:05.250805 Final RX Vref Byte 0 = 50 to rank0
4536 13:42:05.253588 Final RX Vref Byte 1 = 53 to rank0
4537 13:42:05.256818 Final RX Vref Byte 0 = 50 to rank1
4538 13:42:05.260149 Final RX Vref Byte 1 = 53 to rank1==
4539 13:42:05.263684 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 13:42:05.269947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 13:42:05.270371 ==
4542 13:42:05.270704 DQS Delay:
4543 13:42:05.273652 DQS0 = 0, DQS1 = 0
4544 13:42:05.274166 DQM Delay:
4545 13:42:05.274508 DQM0 = 44, DQM1 = 36
4546 13:42:05.276589 DQ Delay:
4547 13:42:05.279880 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =44
4548 13:42:05.283743 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4549 13:42:05.286857 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4550 13:42:05.290227 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4551 13:42:05.290746
4552 13:42:05.291142
4553 13:42:05.296631 [DQSOSCAuto] RK0, (LSB)MR18= 0x354f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4554 13:42:05.300048 CH1 RK0: MR19=808, MR18=354F
4555 13:42:05.306784 CH1_RK0: MR19=0x808, MR18=0x354F, DQSOSC=394, MR23=63, INC=168, DEC=112
4556 13:42:05.307323
4557 13:42:05.310727 ----->DramcWriteLeveling(PI) begin...
4558 13:42:05.311267 ==
4559 13:42:05.313365 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 13:42:05.316509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 13:42:05.317026 ==
4562 13:42:05.319657 Write leveling (Byte 0): 29 => 29
4563 13:42:05.323274 Write leveling (Byte 1): 29 => 29
4564 13:42:05.326985 DramcWriteLeveling(PI) end<-----
4565 13:42:05.327501
4566 13:42:05.327836 ==
4567 13:42:05.329993 Dram Type= 6, Freq= 0, CH_1, rank 1
4568 13:42:05.333335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 13:42:05.336558 ==
4570 13:42:05.337072 [Gating] SW mode calibration
4571 13:42:05.342963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4572 13:42:05.349869 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4573 13:42:05.353118 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4574 13:42:05.359793 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4575 13:42:05.362942 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4576 13:42:05.366206 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 1)
4577 13:42:05.372603 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4578 13:42:05.375812 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 13:42:05.379102 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 13:42:05.385817 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 13:42:05.389534 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4582 13:42:05.392666 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4583 13:42:05.399063 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4584 13:42:05.402733 0 10 12 | B1->B0 | 3535 3f3f | 0 0 | (0 0) (0 0)
4585 13:42:05.405488 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4586 13:42:05.412151 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 13:42:05.414848 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 13:42:05.418402 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 13:42:05.425224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4590 13:42:05.428199 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4591 13:42:05.431065 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 13:42:05.438663 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4593 13:42:05.441390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 13:42:05.444952 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 13:42:05.451196 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 13:42:05.454727 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 13:42:05.457888 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 13:42:05.464512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 13:42:05.467703 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 13:42:05.471103 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 13:42:05.477583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 13:42:05.480608 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 13:42:05.484100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 13:42:05.490775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 13:42:05.494000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 13:42:05.497912 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 13:42:05.504450 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4608 13:42:05.507595 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4609 13:42:05.510605 Total UI for P1: 0, mck2ui 16
4610 13:42:05.513679 best dqsien dly found for B0: ( 0, 13, 8)
4611 13:42:05.517358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:42:05.520392 Total UI for P1: 0, mck2ui 16
4613 13:42:05.523969 best dqsien dly found for B1: ( 0, 13, 10)
4614 13:42:05.527568 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4615 13:42:05.533529 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4616 13:42:05.533950
4617 13:42:05.537389 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4618 13:42:05.540843 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4619 13:42:05.544066 [Gating] SW calibration Done
4620 13:42:05.544572 ==
4621 13:42:05.546623 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 13:42:05.549734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 13:42:05.550155 ==
4624 13:42:05.553552 RX Vref Scan: 0
4625 13:42:05.553986
4626 13:42:05.554317 RX Vref 0 -> 0, step: 1
4627 13:42:05.554625
4628 13:42:05.557022 RX Delay -230 -> 252, step: 16
4629 13:42:05.560028 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4630 13:42:05.566440 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4631 13:42:05.569608 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4632 13:42:05.572867 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4633 13:42:05.576134 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4634 13:42:05.583479 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4635 13:42:05.586615 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4636 13:42:05.589733 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4637 13:42:05.592981 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4638 13:42:05.599617 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4639 13:42:05.602745 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4640 13:42:05.606102 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4641 13:42:05.609469 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4642 13:42:05.615561 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4643 13:42:05.619096 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4644 13:42:05.622186 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4645 13:42:05.622731 ==
4646 13:42:05.625706 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 13:42:05.629057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 13:42:05.632052 ==
4649 13:42:05.632514 DQS Delay:
4650 13:42:05.632889 DQS0 = 0, DQS1 = 0
4651 13:42:05.635973 DQM Delay:
4652 13:42:05.636504 DQM0 = 46, DQM1 = 43
4653 13:42:05.638667 DQ Delay:
4654 13:42:05.639094 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4655 13:42:05.641892 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4656 13:42:05.645786 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4657 13:42:05.649196 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4658 13:42:05.652079
4659 13:42:05.652591
4660 13:42:05.653139 ==
4661 13:42:05.655324 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 13:42:05.658762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 13:42:05.659195 ==
4664 13:42:05.659533
4665 13:42:05.659845
4666 13:42:05.661734 TX Vref Scan disable
4667 13:42:05.662196 == TX Byte 0 ==
4668 13:42:05.668414 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4669 13:42:05.671376 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4670 13:42:05.671884 == TX Byte 1 ==
4671 13:42:05.677873 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4672 13:42:05.681654 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4673 13:42:05.682084 ==
4674 13:42:05.684677 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 13:42:05.687847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 13:42:05.688273 ==
4677 13:42:05.688702
4678 13:42:05.689023
4679 13:42:05.690994 TX Vref Scan disable
4680 13:42:05.694978 == TX Byte 0 ==
4681 13:42:05.698229 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4682 13:42:05.704129 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4683 13:42:05.704732 == TX Byte 1 ==
4684 13:42:05.707799 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4685 13:42:05.714406 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4686 13:42:05.714874
4687 13:42:05.715441 [DATLAT]
4688 13:42:05.715916 Freq=600, CH1 RK1
4689 13:42:05.716356
4690 13:42:05.717540 DATLAT Default: 0x9
4691 13:42:05.717963 0, 0xFFFF, sum = 0
4692 13:42:05.721164 1, 0xFFFF, sum = 0
4693 13:42:05.724437 2, 0xFFFF, sum = 0
4694 13:42:05.724864 3, 0xFFFF, sum = 0
4695 13:42:05.727551 4, 0xFFFF, sum = 0
4696 13:42:05.727980 5, 0xFFFF, sum = 0
4697 13:42:05.730648 6, 0xFFFF, sum = 0
4698 13:42:05.731077 7, 0xFFFF, sum = 0
4699 13:42:05.733853 8, 0x0, sum = 1
4700 13:42:05.734283 9, 0x0, sum = 2
4701 13:42:05.737884 10, 0x0, sum = 3
4702 13:42:05.738314 11, 0x0, sum = 4
4703 13:42:05.738658 best_step = 9
4704 13:42:05.738970
4705 13:42:05.740736 ==
4706 13:42:05.743689 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 13:42:05.747325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 13:42:05.747753 ==
4709 13:42:05.748086 RX Vref Scan: 0
4710 13:42:05.748397
4711 13:42:05.750532 RX Vref 0 -> 0, step: 1
4712 13:42:05.750953
4713 13:42:05.753713 RX Delay -179 -> 252, step: 8
4714 13:42:05.760246 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4715 13:42:05.763889 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4716 13:42:05.767195 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4717 13:42:05.770292 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4718 13:42:05.773728 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4719 13:42:05.780114 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4720 13:42:05.783454 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4721 13:42:05.786442 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4722 13:42:05.790199 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4723 13:42:05.796798 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4724 13:42:05.800334 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4725 13:42:05.803429 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4726 13:42:05.806545 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4727 13:42:05.813166 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4728 13:42:05.816285 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4729 13:42:05.819443 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4730 13:42:05.819834 ==
4731 13:42:05.823202 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 13:42:05.826145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 13:42:05.829201 ==
4734 13:42:05.829646 DQS Delay:
4735 13:42:05.829961 DQS0 = 0, DQS1 = 0
4736 13:42:05.832661 DQM Delay:
4737 13:42:05.833048 DQM0 = 40, DQM1 = 38
4738 13:42:05.836274 DQ Delay:
4739 13:42:05.839482 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4740 13:42:05.839871 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4741 13:42:05.842617 DQ8 =24, DQ9 =28, DQ10 =44, DQ11 =28
4742 13:42:05.849291 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4743 13:42:05.849387
4744 13:42:05.849452
4745 13:42:05.855166 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4746 13:42:05.859032 CH1 RK1: MR19=808, MR18=3B60
4747 13:42:05.865293 CH1_RK1: MR19=0x808, MR18=0x3B60, DQSOSC=391, MR23=63, INC=171, DEC=114
4748 13:42:05.868686 [RxdqsGatingPostProcess] freq 600
4749 13:42:05.871762 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4750 13:42:05.875444 Pre-setting of DQS Precalculation
4751 13:42:05.882028 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4752 13:42:05.888320 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4753 13:42:05.895321 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4754 13:42:05.895403
4755 13:42:05.895468
4756 13:42:05.898467 [Calibration Summary] 1200 Mbps
4757 13:42:05.898549 CH 0, Rank 0
4758 13:42:05.901567 SW Impedance : PASS
4759 13:42:05.904892 DUTY Scan : NO K
4760 13:42:05.904974 ZQ Calibration : PASS
4761 13:42:05.908409 Jitter Meter : NO K
4762 13:42:05.911193 CBT Training : PASS
4763 13:42:05.911275 Write leveling : PASS
4764 13:42:05.914602 RX DQS gating : PASS
4765 13:42:05.917788 RX DQ/DQS(RDDQC) : PASS
4766 13:42:05.917871 TX DQ/DQS : PASS
4767 13:42:05.921034 RX DATLAT : PASS
4768 13:42:05.924744 RX DQ/DQS(Engine): PASS
4769 13:42:05.924825 TX OE : NO K
4770 13:42:05.927997 All Pass.
4771 13:42:05.928078
4772 13:42:05.928143 CH 0, Rank 1
4773 13:42:05.931038 SW Impedance : PASS
4774 13:42:05.931120 DUTY Scan : NO K
4775 13:42:05.934555 ZQ Calibration : PASS
4776 13:42:05.937531 Jitter Meter : NO K
4777 13:42:05.937613 CBT Training : PASS
4778 13:42:05.940984 Write leveling : PASS
4779 13:42:05.944274 RX DQS gating : PASS
4780 13:42:05.944356 RX DQ/DQS(RDDQC) : PASS
4781 13:42:05.947634 TX DQ/DQS : PASS
4782 13:42:05.951125 RX DATLAT : PASS
4783 13:42:05.951207 RX DQ/DQS(Engine): PASS
4784 13:42:05.954348 TX OE : NO K
4785 13:42:05.954444 All Pass.
4786 13:42:05.954537
4787 13:42:05.957559 CH 1, Rank 0
4788 13:42:05.957668 SW Impedance : PASS
4789 13:42:05.960729 DUTY Scan : NO K
4790 13:42:05.960838 ZQ Calibration : PASS
4791 13:42:05.964521 Jitter Meter : NO K
4792 13:42:05.967799 CBT Training : PASS
4793 13:42:05.967882 Write leveling : PASS
4794 13:42:05.971006 RX DQS gating : PASS
4795 13:42:05.974242 RX DQ/DQS(RDDQC) : PASS
4796 13:42:05.974323 TX DQ/DQS : PASS
4797 13:42:05.977612 RX DATLAT : PASS
4798 13:42:05.980623 RX DQ/DQS(Engine): PASS
4799 13:42:05.980732 TX OE : NO K
4800 13:42:05.983883 All Pass.
4801 13:42:05.983965
4802 13:42:05.984030 CH 1, Rank 1
4803 13:42:05.987725 SW Impedance : PASS
4804 13:42:05.987807 DUTY Scan : NO K
4805 13:42:05.990815 ZQ Calibration : PASS
4806 13:42:05.994089 Jitter Meter : NO K
4807 13:42:05.994171 CBT Training : PASS
4808 13:42:05.997204 Write leveling : PASS
4809 13:42:06.000437 RX DQS gating : PASS
4810 13:42:06.000519 RX DQ/DQS(RDDQC) : PASS
4811 13:42:06.003527 TX DQ/DQS : PASS
4812 13:42:06.007277 RX DATLAT : PASS
4813 13:42:06.007359 RX DQ/DQS(Engine): PASS
4814 13:42:06.010324 TX OE : NO K
4815 13:42:06.010407 All Pass.
4816 13:42:06.010471
4817 13:42:06.013521 DramC Write-DBI off
4818 13:42:06.016689 PER_BANK_REFRESH: Hybrid Mode
4819 13:42:06.016767 TX_TRACKING: ON
4820 13:42:06.027238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4821 13:42:06.030404 [FAST_K] Save calibration result to emmc
4822 13:42:06.033143 dramc_set_vcore_voltage set vcore to 662500
4823 13:42:06.037133 Read voltage for 933, 3
4824 13:42:06.037219 Vio18 = 0
4825 13:42:06.037366 Vcore = 662500
4826 13:42:06.039700 Vdram = 0
4827 13:42:06.039811 Vddq = 0
4828 13:42:06.039904 Vmddr = 0
4829 13:42:06.046219 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4830 13:42:06.049771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4831 13:42:06.053006 MEM_TYPE=3, freq_sel=17
4832 13:42:06.056424 sv_algorithm_assistance_LP4_1600
4833 13:42:06.059379 ============ PULL DRAM RESETB DOWN ============
4834 13:42:06.066033 ========== PULL DRAM RESETB DOWN end =========
4835 13:42:06.069776 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4836 13:42:06.072742 ===================================
4837 13:42:06.076113 LPDDR4 DRAM CONFIGURATION
4838 13:42:06.079479 ===================================
4839 13:42:06.079616 EX_ROW_EN[0] = 0x0
4840 13:42:06.082645 EX_ROW_EN[1] = 0x0
4841 13:42:06.082781 LP4Y_EN = 0x0
4842 13:42:06.085793 WORK_FSP = 0x0
4843 13:42:06.085950 WL = 0x3
4844 13:42:06.089059 RL = 0x3
4845 13:42:06.089235 BL = 0x2
4846 13:42:06.092323 RPST = 0x0
4847 13:42:06.095604 RD_PRE = 0x0
4848 13:42:06.095806 WR_PRE = 0x1
4849 13:42:06.099522 WR_PST = 0x0
4850 13:42:06.099802 DBI_WR = 0x0
4851 13:42:06.102602 DBI_RD = 0x0
4852 13:42:06.102844 OTF = 0x1
4853 13:42:06.105913 ===================================
4854 13:42:06.109105 ===================================
4855 13:42:06.112303 ANA top config
4856 13:42:06.116009 ===================================
4857 13:42:06.116397 DLL_ASYNC_EN = 0
4858 13:42:06.119292 ALL_SLAVE_EN = 1
4859 13:42:06.122443 NEW_RANK_MODE = 1
4860 13:42:06.125725 DLL_IDLE_MODE = 1
4861 13:42:06.128926 LP45_APHY_COMB_EN = 1
4862 13:42:06.129350 TX_ODT_DIS = 1
4863 13:42:06.132053 NEW_8X_MODE = 1
4864 13:42:06.135843 ===================================
4865 13:42:06.138814 ===================================
4866 13:42:06.142111 data_rate = 1866
4867 13:42:06.145532 CKR = 1
4868 13:42:06.148965 DQ_P2S_RATIO = 8
4869 13:42:06.152054 ===================================
4870 13:42:06.152485 CA_P2S_RATIO = 8
4871 13:42:06.155417 DQ_CA_OPEN = 0
4872 13:42:06.158898 DQ_SEMI_OPEN = 0
4873 13:42:06.161688 CA_SEMI_OPEN = 0
4874 13:42:06.165343 CA_FULL_RATE = 0
4875 13:42:06.168320 DQ_CKDIV4_EN = 1
4876 13:42:06.171901 CA_CKDIV4_EN = 1
4877 13:42:06.172327 CA_PREDIV_EN = 0
4878 13:42:06.174741 PH8_DLY = 0
4879 13:42:06.178356 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4880 13:42:06.181717 DQ_AAMCK_DIV = 4
4881 13:42:06.184947 CA_AAMCK_DIV = 4
4882 13:42:06.188497 CA_ADMCK_DIV = 4
4883 13:42:06.188925 DQ_TRACK_CA_EN = 0
4884 13:42:06.191594 CA_PICK = 933
4885 13:42:06.194884 CA_MCKIO = 933
4886 13:42:06.198248 MCKIO_SEMI = 0
4887 13:42:06.201408 PLL_FREQ = 3732
4888 13:42:06.204502 DQ_UI_PI_RATIO = 32
4889 13:42:06.207739 CA_UI_PI_RATIO = 0
4890 13:42:06.210940 ===================================
4891 13:42:06.214702 ===================================
4892 13:42:06.215168 memory_type:LPDDR4
4893 13:42:06.217922 GP_NUM : 10
4894 13:42:06.221129 SRAM_EN : 1
4895 13:42:06.221652 MD32_EN : 0
4896 13:42:06.224469 ===================================
4897 13:42:06.227627 [ANA_INIT] >>>>>>>>>>>>>>
4898 13:42:06.231298 <<<<<< [CONFIGURE PHASE]: ANA_TX
4899 13:42:06.234323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4900 13:42:06.237522 ===================================
4901 13:42:06.240578 data_rate = 1866,PCW = 0X8f00
4902 13:42:06.244450 ===================================
4903 13:42:06.247583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4904 13:42:06.250573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4905 13:42:06.257112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4906 13:42:06.260787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4907 13:42:06.263756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4908 13:42:06.270284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4909 13:42:06.270440 [ANA_INIT] flow start
4910 13:42:06.273986 [ANA_INIT] PLL >>>>>>>>
4911 13:42:06.274139 [ANA_INIT] PLL <<<<<<<<
4912 13:42:06.277097 [ANA_INIT] MIDPI >>>>>>>>
4913 13:42:06.280345 [ANA_INIT] MIDPI <<<<<<<<
4914 13:42:06.283334 [ANA_INIT] DLL >>>>>>>>
4915 13:42:06.283489 [ANA_INIT] flow end
4916 13:42:06.286986 ============ LP4 DIFF to SE enter ============
4917 13:42:06.293558 ============ LP4 DIFF to SE exit ============
4918 13:42:06.293714 [ANA_INIT] <<<<<<<<<<<<<
4919 13:42:06.296957 [Flow] Enable top DCM control >>>>>
4920 13:42:06.299915 [Flow] Enable top DCM control <<<<<
4921 13:42:06.303082 Enable DLL master slave shuffle
4922 13:42:06.310057 ==============================================================
4923 13:42:06.313217 Gating Mode config
4924 13:42:06.316630 ==============================================================
4925 13:42:06.319512 Config description:
4926 13:42:06.329579 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4927 13:42:06.335842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4928 13:42:06.339496 SELPH_MODE 0: By rank 1: By Phase
4929 13:42:06.345869 ==============================================================
4930 13:42:06.349125 GAT_TRACK_EN = 1
4931 13:42:06.352666 RX_GATING_MODE = 2
4932 13:42:06.355470 RX_GATING_TRACK_MODE = 2
4933 13:42:06.358707 SELPH_MODE = 1
4934 13:42:06.358789 PICG_EARLY_EN = 1
4935 13:42:06.362736 VALID_LAT_VALUE = 1
4936 13:42:06.369146 ==============================================================
4937 13:42:06.372307 Enter into Gating configuration >>>>
4938 13:42:06.375624 Exit from Gating configuration <<<<
4939 13:42:06.378819 Enter into DVFS_PRE_config >>>>>
4940 13:42:06.388677 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4941 13:42:06.391713 Exit from DVFS_PRE_config <<<<<
4942 13:42:06.395018 Enter into PICG configuration >>>>
4943 13:42:06.398510 Exit from PICG configuration <<<<
4944 13:42:06.401478 [RX_INPUT] configuration >>>>>
4945 13:42:06.404796 [RX_INPUT] configuration <<<<<
4946 13:42:06.411736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4947 13:42:06.414761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4948 13:42:06.421635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4949 13:42:06.428050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4950 13:42:06.434647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4951 13:42:06.440956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4952 13:42:06.444639 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4953 13:42:06.447703 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4954 13:42:06.450969 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4955 13:42:06.457388 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4956 13:42:06.460506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4957 13:42:06.464328 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4958 13:42:06.467509 ===================================
4959 13:42:06.470793 LPDDR4 DRAM CONFIGURATION
4960 13:42:06.473918 ===================================
4961 13:42:06.477241 EX_ROW_EN[0] = 0x0
4962 13:42:06.477360 EX_ROW_EN[1] = 0x0
4963 13:42:06.480831 LP4Y_EN = 0x0
4964 13:42:06.480913 WORK_FSP = 0x0
4965 13:42:06.484075 WL = 0x3
4966 13:42:06.484158 RL = 0x3
4967 13:42:06.487152 BL = 0x2
4968 13:42:06.487234 RPST = 0x0
4969 13:42:06.490401 RD_PRE = 0x0
4970 13:42:06.490482 WR_PRE = 0x1
4971 13:42:06.493560 WR_PST = 0x0
4972 13:42:06.493641 DBI_WR = 0x0
4973 13:42:06.497388 DBI_RD = 0x0
4974 13:42:06.500342 OTF = 0x1
4975 13:42:06.503704 ===================================
4976 13:42:06.506968 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4977 13:42:06.510118 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4978 13:42:06.513863 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 13:42:06.516867 ===================================
4980 13:42:06.520345 LPDDR4 DRAM CONFIGURATION
4981 13:42:06.523956 ===================================
4982 13:42:06.526595 EX_ROW_EN[0] = 0x10
4983 13:42:06.526677 EX_ROW_EN[1] = 0x0
4984 13:42:06.529983 LP4Y_EN = 0x0
4985 13:42:06.530065 WORK_FSP = 0x0
4986 13:42:06.533642 WL = 0x3
4987 13:42:06.533724 RL = 0x3
4988 13:42:06.536649 BL = 0x2
4989 13:42:06.536731 RPST = 0x0
4990 13:42:06.540122 RD_PRE = 0x0
4991 13:42:06.540232 WR_PRE = 0x1
4992 13:42:06.543309 WR_PST = 0x0
4993 13:42:06.543417 DBI_WR = 0x0
4994 13:42:06.546371 DBI_RD = 0x0
4995 13:42:06.550106 OTF = 0x1
4996 13:42:06.553305 ===================================
4997 13:42:06.556594 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4998 13:42:06.561727 nWR fixed to 30
4999 13:42:06.564911 [ModeRegInit_LP4] CH0 RK0
5000 13:42:06.564993 [ModeRegInit_LP4] CH0 RK1
5001 13:42:06.567899 [ModeRegInit_LP4] CH1 RK0
5002 13:42:06.571332 [ModeRegInit_LP4] CH1 RK1
5003 13:42:06.571413 match AC timing 9
5004 13:42:06.577844 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5005 13:42:06.581099 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5006 13:42:06.584690 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5007 13:42:06.591288 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5008 13:42:06.594589 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5009 13:42:06.594671 ==
5010 13:42:06.597604 Dram Type= 6, Freq= 0, CH_0, rank 0
5011 13:42:06.600857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5012 13:42:06.600939 ==
5013 13:42:06.607859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5014 13:42:06.614249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5015 13:42:06.617637 [CA 0] Center 37 (7~68) winsize 62
5016 13:42:06.620700 [CA 1] Center 37 (7~68) winsize 62
5017 13:42:06.624033 [CA 2] Center 34 (4~65) winsize 62
5018 13:42:06.627191 [CA 3] Center 34 (4~65) winsize 62
5019 13:42:06.630303 [CA 4] Center 33 (3~63) winsize 61
5020 13:42:06.634195 [CA 5] Center 32 (2~63) winsize 62
5021 13:42:06.634277
5022 13:42:06.637293 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5023 13:42:06.637387
5024 13:42:06.640319 [CATrainingPosCal] consider 1 rank data
5025 13:42:06.644098 u2DelayCellTimex100 = 270/100 ps
5026 13:42:06.647497 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5027 13:42:06.650330 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5028 13:42:06.653552 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5029 13:42:06.660405 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5030 13:42:06.663750 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5031 13:42:06.666820 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5032 13:42:06.666904
5033 13:42:06.670323 CA PerBit enable=1, Macro0, CA PI delay=32
5034 13:42:06.670405
5035 13:42:06.673526 [CBTSetCACLKResult] CA Dly = 32
5036 13:42:06.673608 CS Dly: 6 (0~37)
5037 13:42:06.673674 ==
5038 13:42:06.676673 Dram Type= 6, Freq= 0, CH_0, rank 1
5039 13:42:06.683196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5040 13:42:06.683279 ==
5041 13:42:06.686420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5042 13:42:06.693360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5043 13:42:06.696949 [CA 0] Center 38 (8~68) winsize 61
5044 13:42:06.699761 [CA 1] Center 37 (7~68) winsize 62
5045 13:42:06.702999 [CA 2] Center 34 (4~65) winsize 62
5046 13:42:06.706363 [CA 3] Center 34 (4~65) winsize 62
5047 13:42:06.710186 [CA 4] Center 33 (3~64) winsize 62
5048 13:42:06.713383 [CA 5] Center 32 (2~63) winsize 62
5049 13:42:06.713466
5050 13:42:06.716475 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5051 13:42:06.716557
5052 13:42:06.719891 [CATrainingPosCal] consider 2 rank data
5053 13:42:06.723077 u2DelayCellTimex100 = 270/100 ps
5054 13:42:06.726173 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5055 13:42:06.733047 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5056 13:42:06.736300 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5057 13:42:06.739706 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5058 13:42:06.742693 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5059 13:42:06.745931 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5060 13:42:06.746014
5061 13:42:06.749706 CA PerBit enable=1, Macro0, CA PI delay=32
5062 13:42:06.749789
5063 13:42:06.752842 [CBTSetCACLKResult] CA Dly = 32
5064 13:42:06.755949 CS Dly: 7 (0~39)
5065 13:42:06.756031
5066 13:42:06.759249 ----->DramcWriteLeveling(PI) begin...
5067 13:42:06.759332 ==
5068 13:42:06.762515 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 13:42:06.765998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 13:42:06.766081 ==
5071 13:42:06.769498 Write leveling (Byte 0): 30 => 30
5072 13:42:06.772485 Write leveling (Byte 1): 29 => 29
5073 13:42:06.775753 DramcWriteLeveling(PI) end<-----
5074 13:42:06.775835
5075 13:42:06.775899 ==
5076 13:42:06.778992 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 13:42:06.782331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 13:42:06.782414 ==
5079 13:42:06.785663 [Gating] SW mode calibration
5080 13:42:06.792713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5081 13:42:06.798955 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5082 13:42:06.802620 0 14 0 | B1->B0 | 2827 3434 | 1 1 | (0 0) (1 1)
5083 13:42:06.805488 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5084 13:42:06.812473 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 13:42:06.815748 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 13:42:06.822201 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 13:42:06.825241 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5088 13:42:06.828653 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5089 13:42:06.834920 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
5090 13:42:06.838703 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5091 13:42:06.841820 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5092 13:42:06.848217 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 13:42:06.851876 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 13:42:06.855062 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 13:42:06.861587 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 13:42:06.864782 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5097 13:42:06.867995 0 15 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
5098 13:42:06.874406 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5099 13:42:06.877552 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 13:42:06.881298 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 13:42:06.887845 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 13:42:06.891228 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 13:42:06.894560 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5104 13:42:06.900757 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 13:42:06.904316 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5106 13:42:06.907352 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5107 13:42:06.914042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 13:42:06.917744 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 13:42:06.920961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 13:42:06.927326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 13:42:06.930620 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 13:42:06.933702 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 13:42:06.940258 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 13:42:06.944095 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 13:42:06.947155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 13:42:06.953439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 13:42:06.956766 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 13:42:06.960637 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 13:42:06.966757 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:42:06.970047 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:42:06.973157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5122 13:42:06.976446 Total UI for P1: 0, mck2ui 16
5123 13:42:06.979769 best dqsien dly found for B0: ( 1, 2, 26)
5124 13:42:06.986827 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5125 13:42:06.990090 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 13:42:06.993000 Total UI for P1: 0, mck2ui 16
5127 13:42:06.996211 best dqsien dly found for B1: ( 1, 2, 30)
5128 13:42:06.999498 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5129 13:42:07.002737 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5130 13:42:07.002819
5131 13:42:07.006496 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5132 13:42:07.009417 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5133 13:42:07.012932 [Gating] SW calibration Done
5134 13:42:07.013028 ==
5135 13:42:07.016528 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 13:42:07.019313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 13:42:07.022679 ==
5138 13:42:07.022761 RX Vref Scan: 0
5139 13:42:07.022844
5140 13:42:07.025996 RX Vref 0 -> 0, step: 1
5141 13:42:07.026079
5142 13:42:07.029207 RX Delay -80 -> 252, step: 8
5143 13:42:07.032277 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5144 13:42:07.035615 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5145 13:42:07.039310 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5146 13:42:07.042328 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5147 13:42:07.045371 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5148 13:42:07.052143 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5149 13:42:07.055947 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5150 13:42:07.058692 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5151 13:42:07.062545 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5152 13:42:07.065736 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5153 13:42:07.072192 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5154 13:42:07.075530 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5155 13:42:07.078673 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5156 13:42:07.081799 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5157 13:42:07.085484 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5158 13:42:07.088637 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5159 13:42:07.091821 ==
5160 13:42:07.095020 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 13:42:07.098701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 13:42:07.098783 ==
5163 13:42:07.098849 DQS Delay:
5164 13:42:07.101978 DQS0 = 0, DQS1 = 0
5165 13:42:07.102059 DQM Delay:
5166 13:42:07.104983 DQM0 = 100, DQM1 = 89
5167 13:42:07.105065 DQ Delay:
5168 13:42:07.108302 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5169 13:42:07.111595 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5170 13:42:07.114848 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5171 13:42:07.118732 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5172 13:42:07.118815
5173 13:42:07.118880
5174 13:42:07.118959 ==
5175 13:42:07.121850 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 13:42:07.124944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 13:42:07.128222 ==
5178 13:42:07.128304
5179 13:42:07.128368
5180 13:42:07.128428 TX Vref Scan disable
5181 13:42:07.131374 == TX Byte 0 ==
5182 13:42:07.134716 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5183 13:42:07.138342 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5184 13:42:07.141073 == TX Byte 1 ==
5185 13:42:07.144707 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5186 13:42:07.147802 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5187 13:42:07.151345 ==
5188 13:42:07.154159 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 13:42:07.157909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 13:42:07.157993 ==
5191 13:42:07.158058
5192 13:42:07.158119
5193 13:42:07.161148 TX Vref Scan disable
5194 13:42:07.161230 == TX Byte 0 ==
5195 13:42:07.167543 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5196 13:42:07.170719 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5197 13:42:07.170802 == TX Byte 1 ==
5198 13:42:07.177132 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5199 13:42:07.180770 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5200 13:42:07.180857
5201 13:42:07.180923 [DATLAT]
5202 13:42:07.183937 Freq=933, CH0 RK0
5203 13:42:07.184019
5204 13:42:07.184083 DATLAT Default: 0xd
5205 13:42:07.187204 0, 0xFFFF, sum = 0
5206 13:42:07.187288 1, 0xFFFF, sum = 0
5207 13:42:07.190881 2, 0xFFFF, sum = 0
5208 13:42:07.194130 3, 0xFFFF, sum = 0
5209 13:42:07.194214 4, 0xFFFF, sum = 0
5210 13:42:07.197269 5, 0xFFFF, sum = 0
5211 13:42:07.197352 6, 0xFFFF, sum = 0
5212 13:42:07.200398 7, 0xFFFF, sum = 0
5213 13:42:07.200482 8, 0xFFFF, sum = 0
5214 13:42:07.203626 9, 0xFFFF, sum = 0
5215 13:42:07.203710 10, 0x0, sum = 1
5216 13:42:07.207338 11, 0x0, sum = 2
5217 13:42:07.207422 12, 0x0, sum = 3
5218 13:42:07.210685 13, 0x0, sum = 4
5219 13:42:07.210768 best_step = 11
5220 13:42:07.210833
5221 13:42:07.210893 ==
5222 13:42:07.213683 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 13:42:07.216995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 13:42:07.217077 ==
5225 13:42:07.220117 RX Vref Scan: 1
5226 13:42:07.220200
5227 13:42:07.223810 RX Vref 0 -> 0, step: 1
5228 13:42:07.223893
5229 13:42:07.223958 RX Delay -61 -> 252, step: 4
5230 13:42:07.224019
5231 13:42:07.227121 Set Vref, RX VrefLevel [Byte0]: 57
5232 13:42:07.230347 [Byte1]: 59
5233 13:42:07.234655
5234 13:42:07.234737 Final RX Vref Byte 0 = 57 to rank0
5235 13:42:07.238517 Final RX Vref Byte 1 = 59 to rank0
5236 13:42:07.241702 Final RX Vref Byte 0 = 57 to rank1
5237 13:42:07.244714 Final RX Vref Byte 1 = 59 to rank1==
5238 13:42:07.248410 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 13:42:07.254960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 13:42:07.255061 ==
5241 13:42:07.255177 DQS Delay:
5242 13:42:07.257988 DQS0 = 0, DQS1 = 0
5243 13:42:07.258071 DQM Delay:
5244 13:42:07.258137 DQM0 = 98, DQM1 = 88
5245 13:42:07.261660 DQ Delay:
5246 13:42:07.264597 DQ0 =100, DQ1 =100, DQ2 =92, DQ3 =94
5247 13:42:07.267551 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5248 13:42:07.270693 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5249 13:42:07.274572 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =92
5250 13:42:07.274654
5251 13:42:07.274722
5252 13:42:07.281040 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5253 13:42:07.283915 CH0 RK0: MR19=505, MR18=1E18
5254 13:42:07.290711 CH0_RK0: MR19=0x505, MR18=0x1E18, DQSOSC=412, MR23=63, INC=63, DEC=42
5255 13:42:07.290795
5256 13:42:07.293930 ----->DramcWriteLeveling(PI) begin...
5257 13:42:07.294016 ==
5258 13:42:07.297057 Dram Type= 6, Freq= 0, CH_0, rank 1
5259 13:42:07.300425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 13:42:07.304194 ==
5261 13:42:07.304276 Write leveling (Byte 0): 31 => 31
5262 13:42:07.307171 Write leveling (Byte 1): 29 => 29
5263 13:42:07.310869 DramcWriteLeveling(PI) end<-----
5264 13:42:07.310951
5265 13:42:07.311015 ==
5266 13:42:07.314072 Dram Type= 6, Freq= 0, CH_0, rank 1
5267 13:42:07.320692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 13:42:07.320775 ==
5269 13:42:07.323785 [Gating] SW mode calibration
5270 13:42:07.330154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5271 13:42:07.333295 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5272 13:42:07.340062 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5273 13:42:07.343364 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5274 13:42:07.346959 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 13:42:07.353269 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 13:42:07.356632 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 13:42:07.360361 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5278 13:42:07.366874 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5279 13:42:07.369831 0 14 28 | B1->B0 | 3030 2c2c | 1 0 | (0 1) (0 1)
5280 13:42:07.373196 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5281 13:42:07.379587 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5282 13:42:07.383032 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 13:42:07.386214 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 13:42:07.393149 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 13:42:07.396331 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5286 13:42:07.399975 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5287 13:42:07.406272 0 15 28 | B1->B0 | 2f2f 3d3d | 0 0 | (0 0) (0 0)
5288 13:42:07.409453 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5289 13:42:07.412925 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5290 13:42:07.419416 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 13:42:07.422567 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 13:42:07.426483 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 13:42:07.432647 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5294 13:42:07.435887 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 13:42:07.439082 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5296 13:42:07.445526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5297 13:42:07.449299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 13:42:07.452534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 13:42:07.458679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 13:42:07.462602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 13:42:07.465926 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 13:42:07.472237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 13:42:07.475637 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 13:42:07.478844 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 13:42:07.484988 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 13:42:07.488339 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 13:42:07.491965 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 13:42:07.498370 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 13:42:07.501647 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 13:42:07.505192 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5311 13:42:07.511625 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5312 13:42:07.515198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5313 13:42:07.518355 Total UI for P1: 0, mck2ui 16
5314 13:42:07.521769 best dqsien dly found for B0: ( 1, 2, 26)
5315 13:42:07.524852 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 13:42:07.528077 Total UI for P1: 0, mck2ui 16
5317 13:42:07.531918 best dqsien dly found for B1: ( 1, 2, 30)
5318 13:42:07.534510 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5319 13:42:07.538291 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5320 13:42:07.538372
5321 13:42:07.541578 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5322 13:42:07.547988 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5323 13:42:07.548070 [Gating] SW calibration Done
5324 13:42:07.551108 ==
5325 13:42:07.551190 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 13:42:07.557709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 13:42:07.557791 ==
5328 13:42:07.557855 RX Vref Scan: 0
5329 13:42:07.557915
5330 13:42:07.561306 RX Vref 0 -> 0, step: 1
5331 13:42:07.561387
5332 13:42:07.564543 RX Delay -80 -> 252, step: 8
5333 13:42:07.567743 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5334 13:42:07.570988 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5335 13:42:07.574076 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5336 13:42:07.580905 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5337 13:42:07.584026 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5338 13:42:07.587707 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5339 13:42:07.590986 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5340 13:42:07.594725 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5341 13:42:07.597685 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5342 13:42:07.604352 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5343 13:42:07.607057 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5344 13:42:07.610402 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5345 13:42:07.613732 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5346 13:42:07.617310 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5347 13:42:07.620442 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5348 13:42:07.627125 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5349 13:42:07.627219 ==
5350 13:42:07.630341 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 13:42:07.633569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 13:42:07.633651 ==
5353 13:42:07.633716 DQS Delay:
5354 13:42:07.637321 DQS0 = 0, DQS1 = 0
5355 13:42:07.637402 DQM Delay:
5356 13:42:07.640352 DQM0 = 97, DQM1 = 91
5357 13:42:07.640433 DQ Delay:
5358 13:42:07.643621 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5359 13:42:07.646750 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5360 13:42:07.649992 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5361 13:42:07.653317 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5362 13:42:07.653398
5363 13:42:07.653462
5364 13:42:07.653521 ==
5365 13:42:07.656564 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 13:42:07.660471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 13:42:07.663669 ==
5368 13:42:07.663750
5369 13:42:07.663813
5370 13:42:07.663872 TX Vref Scan disable
5371 13:42:07.666713 == TX Byte 0 ==
5372 13:42:07.669790 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5373 13:42:07.676969 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5374 13:42:07.677051 == TX Byte 1 ==
5375 13:42:07.680066 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5376 13:42:07.686497 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5377 13:42:07.686578 ==
5378 13:42:07.689820 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 13:42:07.692830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 13:42:07.692912 ==
5381 13:42:07.692977
5382 13:42:07.693036
5383 13:42:07.696228 TX Vref Scan disable
5384 13:42:07.696310 == TX Byte 0 ==
5385 13:42:07.703170 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5386 13:42:07.706313 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5387 13:42:07.709498 == TX Byte 1 ==
5388 13:42:07.713104 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5389 13:42:07.716112 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5390 13:42:07.716193
5391 13:42:07.716257 [DATLAT]
5392 13:42:07.719274 Freq=933, CH0 RK1
5393 13:42:07.719356
5394 13:42:07.719420 DATLAT Default: 0xb
5395 13:42:07.722785 0, 0xFFFF, sum = 0
5396 13:42:07.726047 1, 0xFFFF, sum = 0
5397 13:42:07.726130 2, 0xFFFF, sum = 0
5398 13:42:07.729230 3, 0xFFFF, sum = 0
5399 13:42:07.729350 4, 0xFFFF, sum = 0
5400 13:42:07.732264 5, 0xFFFF, sum = 0
5401 13:42:07.732346 6, 0xFFFF, sum = 0
5402 13:42:07.735850 7, 0xFFFF, sum = 0
5403 13:42:07.735933 8, 0xFFFF, sum = 0
5404 13:42:07.739302 9, 0xFFFF, sum = 0
5405 13:42:07.739384 10, 0x0, sum = 1
5406 13:42:07.742436 11, 0x0, sum = 2
5407 13:42:07.742518 12, 0x0, sum = 3
5408 13:42:07.745487 13, 0x0, sum = 4
5409 13:42:07.745569 best_step = 11
5410 13:42:07.745634
5411 13:42:07.745694 ==
5412 13:42:07.748779 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 13:42:07.752175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 13:42:07.752266 ==
5415 13:42:07.755963 RX Vref Scan: 0
5416 13:42:07.756051
5417 13:42:07.759288 RX Vref 0 -> 0, step: 1
5418 13:42:07.759382
5419 13:42:07.759457 RX Delay -53 -> 252, step: 4
5420 13:42:07.766909 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5421 13:42:07.770278 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5422 13:42:07.773880 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5423 13:42:07.777036 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5424 13:42:07.780297 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5425 13:42:07.786780 iDelay=199, Bit 5, Center 88 (-1 ~ 178) 180
5426 13:42:07.790143 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5427 13:42:07.793507 iDelay=199, Bit 7, Center 106 (19 ~ 194) 176
5428 13:42:07.797122 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5429 13:42:07.800258 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5430 13:42:07.803947 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5431 13:42:07.810173 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5432 13:42:07.813414 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5433 13:42:07.817103 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5434 13:42:07.820378 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5435 13:42:07.823442 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5436 13:42:07.826612 ==
5437 13:42:07.827029 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 13:42:07.833117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 13:42:07.833621 ==
5440 13:42:07.833963 DQS Delay:
5441 13:42:07.836758 DQS0 = 0, DQS1 = 0
5442 13:42:07.837177 DQM Delay:
5443 13:42:07.839763 DQM0 = 98, DQM1 = 89
5444 13:42:07.840209 DQ Delay:
5445 13:42:07.843288 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =94
5446 13:42:07.846410 DQ4 =100, DQ5 =88, DQ6 =108, DQ7 =106
5447 13:42:07.850116 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5448 13:42:07.852945 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5449 13:42:07.853407
5450 13:42:07.853750
5451 13:42:07.859746 [DQSOSCAuto] RK1, (LSB)MR18= 0x130f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5452 13:42:07.862906 CH0 RK1: MR19=505, MR18=130F
5453 13:42:07.869573 CH0_RK1: MR19=0x505, MR18=0x130F, DQSOSC=415, MR23=63, INC=62, DEC=41
5454 13:42:07.872905 [RxdqsGatingPostProcess] freq 933
5455 13:42:07.879141 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5456 13:42:07.882998 best DQS0 dly(2T, 0.5T) = (0, 10)
5457 13:42:07.886213 best DQS1 dly(2T, 0.5T) = (0, 10)
5458 13:42:07.889222 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5459 13:42:07.892474 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5460 13:42:07.892899 best DQS0 dly(2T, 0.5T) = (0, 10)
5461 13:42:07.895906 best DQS1 dly(2T, 0.5T) = (0, 10)
5462 13:42:07.898874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5463 13:42:07.902914 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5464 13:42:07.905946 Pre-setting of DQS Precalculation
5465 13:42:07.912421 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5466 13:42:07.912842 ==
5467 13:42:07.916017 Dram Type= 6, Freq= 0, CH_1, rank 0
5468 13:42:07.919681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 13:42:07.920181 ==
5470 13:42:07.925822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5471 13:42:07.931917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5472 13:42:07.935284 [CA 0] Center 37 (7~67) winsize 61
5473 13:42:07.939100 [CA 1] Center 37 (6~68) winsize 63
5474 13:42:07.941449 [CA 2] Center 35 (5~65) winsize 61
5475 13:42:07.945040 [CA 3] Center 34 (4~64) winsize 61
5476 13:42:07.948183 [CA 4] Center 34 (4~65) winsize 62
5477 13:42:07.951561 [CA 5] Center 33 (3~64) winsize 62
5478 13:42:07.951642
5479 13:42:07.955136 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5480 13:42:07.955218
5481 13:42:07.958276 [CATrainingPosCal] consider 1 rank data
5482 13:42:07.961639 u2DelayCellTimex100 = 270/100 ps
5483 13:42:07.964864 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5484 13:42:07.968416 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5485 13:42:07.971149 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5486 13:42:07.974474 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5487 13:42:07.978222 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5488 13:42:07.981149 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5489 13:42:07.984154
5490 13:42:07.987867 CA PerBit enable=1, Macro0, CA PI delay=33
5491 13:42:07.987950
5492 13:42:07.990989 [CBTSetCACLKResult] CA Dly = 33
5493 13:42:07.991090 CS Dly: 6 (0~37)
5494 13:42:07.991157 ==
5495 13:42:07.994219 Dram Type= 6, Freq= 0, CH_1, rank 1
5496 13:42:07.997506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 13:42:08.000643 ==
5498 13:42:08.003971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5499 13:42:08.010858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5500 13:42:08.014112 [CA 0] Center 37 (6~68) winsize 63
5501 13:42:08.017279 [CA 1] Center 37 (7~67) winsize 61
5502 13:42:08.020639 [CA 2] Center 34 (4~65) winsize 62
5503 13:42:08.024095 [CA 3] Center 33 (3~64) winsize 62
5504 13:42:08.027505 [CA 4] Center 33 (3~64) winsize 62
5505 13:42:08.030512 [CA 5] Center 33 (3~64) winsize 62
5506 13:42:08.030620
5507 13:42:08.034091 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5508 13:42:08.034173
5509 13:42:08.037116 [CATrainingPosCal] consider 2 rank data
5510 13:42:08.040350 u2DelayCellTimex100 = 270/100 ps
5511 13:42:08.043490 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5512 13:42:08.047237 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5513 13:42:08.050527 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5514 13:42:08.056752 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5515 13:42:08.060492 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5516 13:42:08.063722 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5517 13:42:08.063824
5518 13:42:08.067006 CA PerBit enable=1, Macro0, CA PI delay=33
5519 13:42:08.067115
5520 13:42:08.070301 [CBTSetCACLKResult] CA Dly = 33
5521 13:42:08.070401 CS Dly: 6 (0~38)
5522 13:42:08.070503
5523 13:42:08.073535 ----->DramcWriteLeveling(PI) begin...
5524 13:42:08.076848 ==
5525 13:42:08.076947 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 13:42:08.083273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 13:42:08.083384 ==
5528 13:42:08.086853 Write leveling (Byte 0): 22 => 22
5529 13:42:08.089845 Write leveling (Byte 1): 27 => 27
5530 13:42:08.093474 DramcWriteLeveling(PI) end<-----
5531 13:42:08.093561
5532 13:42:08.093653 ==
5533 13:42:08.096746 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 13:42:08.099757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 13:42:08.099856 ==
5536 13:42:08.103054 [Gating] SW mode calibration
5537 13:42:08.109777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5538 13:42:08.116599 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5539 13:42:08.119859 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 13:42:08.123020 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 13:42:08.129474 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 13:42:08.132827 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 13:42:08.135950 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 13:42:08.142601 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 13:42:08.145841 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
5546 13:42:08.149026 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5547 13:42:08.155930 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 13:42:08.159295 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 13:42:08.162512 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 13:42:08.169350 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 13:42:08.172521 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 13:42:08.175860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 13:42:08.182294 0 15 24 | B1->B0 | 2424 2929 | 1 0 | (0 0) (0 0)
5554 13:42:08.185488 0 15 28 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
5555 13:42:08.188696 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 13:42:08.195107 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 13:42:08.198947 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 13:42:08.202080 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 13:42:08.208358 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 13:42:08.211813 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 13:42:08.215196 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5562 13:42:08.221421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5563 13:42:08.224925 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 13:42:08.228341 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 13:42:08.234661 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 13:42:08.238124 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 13:42:08.241667 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 13:42:08.248314 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 13:42:08.251676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 13:42:08.254748 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 13:42:08.261547 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 13:42:08.264555 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 13:42:08.267623 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 13:42:08.274567 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:42:08.277824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:42:08.281025 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:42:08.287589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5578 13:42:08.290688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5579 13:42:08.294086 Total UI for P1: 0, mck2ui 16
5580 13:42:08.297108 best dqsien dly found for B0: ( 1, 2, 24)
5581 13:42:08.300341 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 13:42:08.303606 Total UI for P1: 0, mck2ui 16
5583 13:42:08.306986 best dqsien dly found for B1: ( 1, 2, 26)
5584 13:42:08.310908 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5585 13:42:08.314146 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5586 13:42:08.314244
5587 13:42:08.320620 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5588 13:42:08.323826 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5589 13:42:08.326940 [Gating] SW calibration Done
5590 13:42:08.327040 ==
5591 13:42:08.329872 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 13:42:08.333479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 13:42:08.333580 ==
5594 13:42:08.333672 RX Vref Scan: 0
5595 13:42:08.333733
5596 13:42:08.336829 RX Vref 0 -> 0, step: 1
5597 13:42:08.336928
5598 13:42:08.339712 RX Delay -80 -> 252, step: 8
5599 13:42:08.343117 iDelay=208, Bit 0, Center 107 (8 ~ 207) 200
5600 13:42:08.346520 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5601 13:42:08.353182 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5602 13:42:08.356257 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5603 13:42:08.359873 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5604 13:42:08.362903 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5605 13:42:08.366544 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5606 13:42:08.369278 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5607 13:42:08.376108 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5608 13:42:08.379351 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5609 13:42:08.382287 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5610 13:42:08.386067 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5611 13:42:08.389371 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5612 13:42:08.395763 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5613 13:42:08.398938 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5614 13:42:08.402259 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5615 13:42:08.402357 ==
5616 13:42:08.405477 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 13:42:08.408698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 13:42:08.408795 ==
5619 13:42:08.412481 DQS Delay:
5620 13:42:08.412576 DQS0 = 0, DQS1 = 0
5621 13:42:08.415644 DQM Delay:
5622 13:42:08.415748 DQM0 = 99, DQM1 = 95
5623 13:42:08.415844 DQ Delay:
5624 13:42:08.418873 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5625 13:42:08.421990 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5626 13:42:08.425361 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5627 13:42:08.431879 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5628 13:42:08.432006
5629 13:42:08.432130
5630 13:42:08.432256 ==
5631 13:42:08.434861 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 13:42:08.438683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 13:42:08.438788 ==
5634 13:42:08.438883
5635 13:42:08.438973
5636 13:42:08.441656 TX Vref Scan disable
5637 13:42:08.441759 == TX Byte 0 ==
5638 13:42:08.448600 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5639 13:42:08.451877 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5640 13:42:08.451981 == TX Byte 1 ==
5641 13:42:08.458690 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5642 13:42:08.461731 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5643 13:42:08.461815 ==
5644 13:42:08.465156 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 13:42:08.467979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 13:42:08.468087 ==
5647 13:42:08.471347
5648 13:42:08.471429
5649 13:42:08.471494 TX Vref Scan disable
5650 13:42:08.474965 == TX Byte 0 ==
5651 13:42:08.478119 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5652 13:42:08.484949 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5653 13:42:08.485054 == TX Byte 1 ==
5654 13:42:08.487686 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5655 13:42:08.494329 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5656 13:42:08.494418
5657 13:42:08.494484 [DATLAT]
5658 13:42:08.494545 Freq=933, CH1 RK0
5659 13:42:08.494604
5660 13:42:08.498007 DATLAT Default: 0xd
5661 13:42:08.498090 0, 0xFFFF, sum = 0
5662 13:42:08.500871 1, 0xFFFF, sum = 0
5663 13:42:08.504160 2, 0xFFFF, sum = 0
5664 13:42:08.504254 3, 0xFFFF, sum = 0
5665 13:42:08.507940 4, 0xFFFF, sum = 0
5666 13:42:08.508039 5, 0xFFFF, sum = 0
5667 13:42:08.511118 6, 0xFFFF, sum = 0
5668 13:42:08.511206 7, 0xFFFF, sum = 0
5669 13:42:08.514416 8, 0xFFFF, sum = 0
5670 13:42:08.514501 9, 0xFFFF, sum = 0
5671 13:42:08.517451 10, 0x0, sum = 1
5672 13:42:08.517535 11, 0x0, sum = 2
5673 13:42:08.521466 12, 0x0, sum = 3
5674 13:42:08.521549 13, 0x0, sum = 4
5675 13:42:08.521615 best_step = 11
5676 13:42:08.524637
5677 13:42:08.524746 ==
5678 13:42:08.527799 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 13:42:08.530786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 13:42:08.530890 ==
5681 13:42:08.530982 RX Vref Scan: 1
5682 13:42:08.531106
5683 13:42:08.533979 RX Vref 0 -> 0, step: 1
5684 13:42:08.534076
5685 13:42:08.537213 RX Delay -53 -> 252, step: 4
5686 13:42:08.537355
5687 13:42:08.540466 Set Vref, RX VrefLevel [Byte0]: 50
5688 13:42:08.544109 [Byte1]: 53
5689 13:42:08.547354
5690 13:42:08.547442 Final RX Vref Byte 0 = 50 to rank0
5691 13:42:08.550451 Final RX Vref Byte 1 = 53 to rank0
5692 13:42:08.554113 Final RX Vref Byte 0 = 50 to rank1
5693 13:42:08.557305 Final RX Vref Byte 1 = 53 to rank1==
5694 13:42:08.560716 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 13:42:08.566820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 13:42:08.566904 ==
5697 13:42:08.566970 DQS Delay:
5698 13:42:08.570360 DQS0 = 0, DQS1 = 0
5699 13:42:08.570442 DQM Delay:
5700 13:42:08.570508 DQM0 = 99, DQM1 = 96
5701 13:42:08.574047 DQ Delay:
5702 13:42:08.577187 DQ0 =106, DQ1 =94, DQ2 =88, DQ3 =98
5703 13:42:08.580034 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5704 13:42:08.583935 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =92
5705 13:42:08.587114 DQ12 =106, DQ13 =106, DQ14 =104, DQ15 =106
5706 13:42:08.587197
5707 13:42:08.587262
5708 13:42:08.593270 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5709 13:42:08.596960 CH1 RK0: MR19=505, MR18=C1B
5710 13:42:08.603733 CH1_RK0: MR19=0x505, MR18=0xC1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5711 13:42:08.603816
5712 13:42:08.606518 ----->DramcWriteLeveling(PI) begin...
5713 13:42:08.606606 ==
5714 13:42:08.610084 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 13:42:08.613477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 13:42:08.613560 ==
5717 13:42:08.616438 Write leveling (Byte 0): 26 => 26
5718 13:42:08.619976 Write leveling (Byte 1): 26 => 26
5719 13:42:08.622922 DramcWriteLeveling(PI) end<-----
5720 13:42:08.623004
5721 13:42:08.623069 ==
5722 13:42:08.626184 Dram Type= 6, Freq= 0, CH_1, rank 1
5723 13:42:08.633161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 13:42:08.633244 ==
5725 13:42:08.633357 [Gating] SW mode calibration
5726 13:42:08.642879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5727 13:42:08.646093 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5728 13:42:08.649299 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5729 13:42:08.656595 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 13:42:08.659659 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 13:42:08.662944 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 13:42:08.668978 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 13:42:08.672977 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 13:42:08.675576 0 14 24 | B1->B0 | 3434 2929 | 0 0 | (0 1) (1 1)
5735 13:42:08.682319 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5736 13:42:08.685959 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 13:42:08.689049 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 13:42:08.695791 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 13:42:08.699011 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 13:42:08.702054 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 13:42:08.708832 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 13:42:08.712141 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5743 13:42:08.715766 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5744 13:42:08.721770 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 13:42:08.725633 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 13:42:08.728614 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 13:42:08.735545 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 13:42:08.738718 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 13:42:08.742030 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 13:42:08.748425 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5751 13:42:08.751705 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 13:42:08.758190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 13:42:08.761706 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 13:42:08.764749 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 13:42:08.767885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 13:42:08.774806 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 13:42:08.777966 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 13:42:08.781290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 13:42:08.787771 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 13:42:08.790889 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 13:42:08.797380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 13:42:08.801006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 13:42:08.804345 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 13:42:08.810816 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 13:42:08.813953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 13:42:08.817684 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5767 13:42:08.820959 Total UI for P1: 0, mck2ui 16
5768 13:42:08.823998 best dqsien dly found for B0: ( 1, 2, 22)
5769 13:42:08.827483 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 13:42:08.830489 Total UI for P1: 0, mck2ui 16
5771 13:42:08.833654 best dqsien dly found for B1: ( 1, 2, 24)
5772 13:42:08.840577 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5773 13:42:08.843714 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5774 13:42:08.843796
5775 13:42:08.846689 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5776 13:42:08.850061 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5777 13:42:08.853226 [Gating] SW calibration Done
5778 13:42:08.853363 ==
5779 13:42:08.857017 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 13:42:08.860317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 13:42:08.860401 ==
5782 13:42:08.863313 RX Vref Scan: 0
5783 13:42:08.863397
5784 13:42:08.863463 RX Vref 0 -> 0, step: 1
5785 13:42:08.863524
5786 13:42:08.866688 RX Delay -80 -> 252, step: 8
5787 13:42:08.869733 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5788 13:42:08.876684 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5789 13:42:08.879923 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5790 13:42:08.883203 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5791 13:42:08.886257 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5792 13:42:08.889755 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5793 13:42:08.892924 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5794 13:42:08.899860 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5795 13:42:08.902918 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5796 13:42:08.906040 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5797 13:42:08.909637 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5798 13:42:08.912983 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5799 13:42:08.919479 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5800 13:42:08.922330 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5801 13:42:08.925586 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5802 13:42:08.929340 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5803 13:42:08.929424 ==
5804 13:42:08.932439 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 13:42:08.939009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 13:42:08.939093 ==
5807 13:42:08.939159 DQS Delay:
5808 13:42:08.939220 DQS0 = 0, DQS1 = 0
5809 13:42:08.942052 DQM Delay:
5810 13:42:08.942135 DQM0 = 97, DQM1 = 95
5811 13:42:08.945275 DQ Delay:
5812 13:42:08.948583 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5813 13:42:08.952510 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5814 13:42:08.955462 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5815 13:42:08.958310 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =103
5816 13:42:08.958392
5817 13:42:08.958457
5818 13:42:08.958517 ==
5819 13:42:08.961771 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 13:42:08.964896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 13:42:08.964979 ==
5822 13:42:08.965045
5823 13:42:08.965106
5824 13:42:08.968209 TX Vref Scan disable
5825 13:42:08.972065 == TX Byte 0 ==
5826 13:42:08.975340 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5827 13:42:08.978713 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5828 13:42:08.981759 == TX Byte 1 ==
5829 13:42:08.985134 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5830 13:42:08.988213 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5831 13:42:08.988297 ==
5832 13:42:08.991483 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 13:42:08.997864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 13:42:08.997948 ==
5835 13:42:08.998013
5836 13:42:08.998073
5837 13:42:08.998131 TX Vref Scan disable
5838 13:42:09.001645 == TX Byte 0 ==
5839 13:42:09.005442 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5840 13:42:09.011905 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5841 13:42:09.011988 == TX Byte 1 ==
5842 13:42:09.014959 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5843 13:42:09.021746 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5844 13:42:09.021833
5845 13:42:09.021898 [DATLAT]
5846 13:42:09.021959 Freq=933, CH1 RK1
5847 13:42:09.022018
5848 13:42:09.025075 DATLAT Default: 0xb
5849 13:42:09.028151 0, 0xFFFF, sum = 0
5850 13:42:09.028235 1, 0xFFFF, sum = 0
5851 13:42:09.031543 2, 0xFFFF, sum = 0
5852 13:42:09.031627 3, 0xFFFF, sum = 0
5853 13:42:09.034534 4, 0xFFFF, sum = 0
5854 13:42:09.034618 5, 0xFFFF, sum = 0
5855 13:42:09.037827 6, 0xFFFF, sum = 0
5856 13:42:09.037923 7, 0xFFFF, sum = 0
5857 13:42:09.041152 8, 0xFFFF, sum = 0
5858 13:42:09.041272 9, 0xFFFF, sum = 0
5859 13:42:09.044321 10, 0x0, sum = 1
5860 13:42:09.044405 11, 0x0, sum = 2
5861 13:42:09.047966 12, 0x0, sum = 3
5862 13:42:09.048050 13, 0x0, sum = 4
5863 13:42:09.051433 best_step = 11
5864 13:42:09.051516
5865 13:42:09.051581 ==
5866 13:42:09.054654 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 13:42:09.057854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 13:42:09.057938 ==
5869 13:42:09.058004 RX Vref Scan: 0
5870 13:42:09.061144
5871 13:42:09.061253 RX Vref 0 -> 0, step: 1
5872 13:42:09.061333
5873 13:42:09.064190 RX Delay -53 -> 252, step: 4
5874 13:42:09.071006 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5875 13:42:09.074282 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5876 13:42:09.077561 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5877 13:42:09.080820 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5878 13:42:09.083977 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5879 13:42:09.087281 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5880 13:42:09.094213 iDelay=199, Bit 6, Center 106 (19 ~ 194) 176
5881 13:42:09.097666 iDelay=199, Bit 7, Center 96 (7 ~ 186) 180
5882 13:42:09.100704 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5883 13:42:09.103957 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5884 13:42:09.107146 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5885 13:42:09.114209 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5886 13:42:09.117653 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5887 13:42:09.120521 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5888 13:42:09.123672 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5889 13:42:09.126886 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5890 13:42:09.130139 ==
5891 13:42:09.133368 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 13:42:09.136886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 13:42:09.136969 ==
5894 13:42:09.137033 DQS Delay:
5895 13:42:09.140417 DQS0 = 0, DQS1 = 0
5896 13:42:09.140498 DQM Delay:
5897 13:42:09.143198 DQM0 = 98, DQM1 = 96
5898 13:42:09.143279 DQ Delay:
5899 13:42:09.146978 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =96
5900 13:42:09.149942 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =96
5901 13:42:09.153461 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
5902 13:42:09.156265 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =104
5903 13:42:09.156348
5904 13:42:09.156412
5905 13:42:09.166240 [DQSOSCAuto] RK1, (LSB)MR18= 0x1027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5906 13:42:09.166327 CH1 RK1: MR19=505, MR18=1027
5907 13:42:09.173346 CH1_RK1: MR19=0x505, MR18=0x1027, DQSOSC=409, MR23=63, INC=64, DEC=43
5908 13:42:09.176527 [RxdqsGatingPostProcess] freq 933
5909 13:42:09.182758 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5910 13:42:09.186080 best DQS0 dly(2T, 0.5T) = (0, 10)
5911 13:42:09.189601 best DQS1 dly(2T, 0.5T) = (0, 10)
5912 13:42:09.192565 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5913 13:42:09.196212 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5914 13:42:09.199246 best DQS0 dly(2T, 0.5T) = (0, 10)
5915 13:42:09.202409 best DQS1 dly(2T, 0.5T) = (0, 10)
5916 13:42:09.206031 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5917 13:42:09.209355 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5918 13:42:09.209438 Pre-setting of DQS Precalculation
5919 13:42:09.215561 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5920 13:42:09.222385 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5921 13:42:09.228670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5922 13:42:09.228753
5923 13:42:09.228819
5924 13:42:09.232064 [Calibration Summary] 1866 Mbps
5925 13:42:09.235237 CH 0, Rank 0
5926 13:42:09.235319 SW Impedance : PASS
5927 13:42:09.238557 DUTY Scan : NO K
5928 13:42:09.242230 ZQ Calibration : PASS
5929 13:42:09.242313 Jitter Meter : NO K
5930 13:42:09.245489 CBT Training : PASS
5931 13:42:09.248424 Write leveling : PASS
5932 13:42:09.248506 RX DQS gating : PASS
5933 13:42:09.251635 RX DQ/DQS(RDDQC) : PASS
5934 13:42:09.255394 TX DQ/DQS : PASS
5935 13:42:09.255478 RX DATLAT : PASS
5936 13:42:09.258451 RX DQ/DQS(Engine): PASS
5937 13:42:09.261573 TX OE : NO K
5938 13:42:09.261657 All Pass.
5939 13:42:09.261721
5940 13:42:09.261782 CH 0, Rank 1
5941 13:42:09.265271 SW Impedance : PASS
5942 13:42:09.268866 DUTY Scan : NO K
5943 13:42:09.268949 ZQ Calibration : PASS
5944 13:42:09.272190 Jitter Meter : NO K
5945 13:42:09.272303 CBT Training : PASS
5946 13:42:09.275291 Write leveling : PASS
5947 13:42:09.278579 RX DQS gating : PASS
5948 13:42:09.278662 RX DQ/DQS(RDDQC) : PASS
5949 13:42:09.281885 TX DQ/DQS : PASS
5950 13:42:09.285049 RX DATLAT : PASS
5951 13:42:09.285158 RX DQ/DQS(Engine): PASS
5952 13:42:09.288190 TX OE : NO K
5953 13:42:09.288274 All Pass.
5954 13:42:09.288339
5955 13:42:09.291305 CH 1, Rank 0
5956 13:42:09.291388 SW Impedance : PASS
5957 13:42:09.294865 DUTY Scan : NO K
5958 13:42:09.298339 ZQ Calibration : PASS
5959 13:42:09.298422 Jitter Meter : NO K
5960 13:42:09.301512 CBT Training : PASS
5961 13:42:09.304619 Write leveling : PASS
5962 13:42:09.304702 RX DQS gating : PASS
5963 13:42:09.307705 RX DQ/DQS(RDDQC) : PASS
5964 13:42:09.311918 TX DQ/DQS : PASS
5965 13:42:09.312041 RX DATLAT : PASS
5966 13:42:09.314768 RX DQ/DQS(Engine): PASS
5967 13:42:09.317758 TX OE : NO K
5968 13:42:09.317843 All Pass.
5969 13:42:09.317948
5970 13:42:09.318064 CH 1, Rank 1
5971 13:42:09.321002 SW Impedance : PASS
5972 13:42:09.324239 DUTY Scan : NO K
5973 13:42:09.324323 ZQ Calibration : PASS
5974 13:42:09.327438 Jitter Meter : NO K
5975 13:42:09.331209 CBT Training : PASS
5976 13:42:09.331293 Write leveling : PASS
5977 13:42:09.334359 RX DQS gating : PASS
5978 13:42:09.337615 RX DQ/DQS(RDDQC) : PASS
5979 13:42:09.337698 TX DQ/DQS : PASS
5980 13:42:09.340924 RX DATLAT : PASS
5981 13:42:09.344046 RX DQ/DQS(Engine): PASS
5982 13:42:09.344129 TX OE : NO K
5983 13:42:09.344196 All Pass.
5984 13:42:09.347207
5985 13:42:09.347289 DramC Write-DBI off
5986 13:42:09.351009 PER_BANK_REFRESH: Hybrid Mode
5987 13:42:09.351096 TX_TRACKING: ON
5988 13:42:09.360622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5989 13:42:09.363569 [FAST_K] Save calibration result to emmc
5990 13:42:09.367403 dramc_set_vcore_voltage set vcore to 650000
5991 13:42:09.370491 Read voltage for 400, 6
5992 13:42:09.370573 Vio18 = 0
5993 13:42:09.373485 Vcore = 650000
5994 13:42:09.373568 Vdram = 0
5995 13:42:09.373633 Vddq = 0
5996 13:42:09.373694 Vmddr = 0
5997 13:42:09.380298 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5998 13:42:09.386758 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5999 13:42:09.386841 MEM_TYPE=3, freq_sel=20
6000 13:42:09.390006 sv_algorithm_assistance_LP4_800
6001 13:42:09.396481 ============ PULL DRAM RESETB DOWN ============
6002 13:42:09.400275 ========== PULL DRAM RESETB DOWN end =========
6003 13:42:09.403382 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6004 13:42:09.406709 ===================================
6005 13:42:09.409644 LPDDR4 DRAM CONFIGURATION
6006 13:42:09.413040 ===================================
6007 13:42:09.413123 EX_ROW_EN[0] = 0x0
6008 13:42:09.416609 EX_ROW_EN[1] = 0x0
6009 13:42:09.419676 LP4Y_EN = 0x0
6010 13:42:09.419757 WORK_FSP = 0x0
6011 13:42:09.422918 WL = 0x2
6012 13:42:09.422999 RL = 0x2
6013 13:42:09.426314 BL = 0x2
6014 13:42:09.426396 RPST = 0x0
6015 13:42:09.429756 RD_PRE = 0x0
6016 13:42:09.429838 WR_PRE = 0x1
6017 13:42:09.432809 WR_PST = 0x0
6018 13:42:09.432961 DBI_WR = 0x0
6019 13:42:09.435972 DBI_RD = 0x0
6020 13:42:09.436073 OTF = 0x1
6021 13:42:09.439893 ===================================
6022 13:42:09.442632 ===================================
6023 13:42:09.446387 ANA top config
6024 13:42:09.449673 ===================================
6025 13:42:09.452930 DLL_ASYNC_EN = 0
6026 13:42:09.453011 ALL_SLAVE_EN = 1
6027 13:42:09.456065 NEW_RANK_MODE = 1
6028 13:42:09.459520 DLL_IDLE_MODE = 1
6029 13:42:09.462458 LP45_APHY_COMB_EN = 1
6030 13:42:09.462542 TX_ODT_DIS = 1
6031 13:42:09.466123 NEW_8X_MODE = 1
6032 13:42:09.469215 ===================================
6033 13:42:09.472429 ===================================
6034 13:42:09.476341 data_rate = 800
6035 13:42:09.479409 CKR = 1
6036 13:42:09.482495 DQ_P2S_RATIO = 4
6037 13:42:09.486111 ===================================
6038 13:42:09.489376 CA_P2S_RATIO = 4
6039 13:42:09.489458 DQ_CA_OPEN = 0
6040 13:42:09.492617 DQ_SEMI_OPEN = 1
6041 13:42:09.495672 CA_SEMI_OPEN = 1
6042 13:42:09.498964 CA_FULL_RATE = 0
6043 13:42:09.502164 DQ_CKDIV4_EN = 0
6044 13:42:09.505567 CA_CKDIV4_EN = 1
6045 13:42:09.505649 CA_PREDIV_EN = 0
6046 13:42:09.508596 PH8_DLY = 0
6047 13:42:09.512489 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6048 13:42:09.515604 DQ_AAMCK_DIV = 0
6049 13:42:09.518968 CA_AAMCK_DIV = 0
6050 13:42:09.522300 CA_ADMCK_DIV = 4
6051 13:42:09.522382 DQ_TRACK_CA_EN = 0
6052 13:42:09.525160 CA_PICK = 800
6053 13:42:09.528720 CA_MCKIO = 400
6054 13:42:09.532069 MCKIO_SEMI = 400
6055 13:42:09.535405 PLL_FREQ = 3016
6056 13:42:09.538628 DQ_UI_PI_RATIO = 32
6057 13:42:09.541438 CA_UI_PI_RATIO = 32
6058 13:42:09.545181 ===================================
6059 13:42:09.548189 ===================================
6060 13:42:09.551651 memory_type:LPDDR4
6061 13:42:09.551734 GP_NUM : 10
6062 13:42:09.554905 SRAM_EN : 1
6063 13:42:09.554987 MD32_EN : 0
6064 13:42:09.558136 ===================================
6065 13:42:09.561781 [ANA_INIT] >>>>>>>>>>>>>>
6066 13:42:09.564872 <<<<<< [CONFIGURE PHASE]: ANA_TX
6067 13:42:09.568016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6068 13:42:09.571285 ===================================
6069 13:42:09.574733 data_rate = 800,PCW = 0X7400
6070 13:42:09.577720 ===================================
6071 13:42:09.581554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6072 13:42:09.587801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6073 13:42:09.597725 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6074 13:42:09.600846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6075 13:42:09.604599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6076 13:42:09.611082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6077 13:42:09.611165 [ANA_INIT] flow start
6078 13:42:09.614315 [ANA_INIT] PLL >>>>>>>>
6079 13:42:09.617273 [ANA_INIT] PLL <<<<<<<<
6080 13:42:09.617369 [ANA_INIT] MIDPI >>>>>>>>
6081 13:42:09.620661 [ANA_INIT] MIDPI <<<<<<<<
6082 13:42:09.624527 [ANA_INIT] DLL >>>>>>>>
6083 13:42:09.624627 [ANA_INIT] flow end
6084 13:42:09.627423 ============ LP4 DIFF to SE enter ============
6085 13:42:09.633658 ============ LP4 DIFF to SE exit ============
6086 13:42:09.633740 [ANA_INIT] <<<<<<<<<<<<<
6087 13:42:09.637512 [Flow] Enable top DCM control >>>>>
6088 13:42:09.640602 [Flow] Enable top DCM control <<<<<
6089 13:42:09.643832 Enable DLL master slave shuffle
6090 13:42:09.650605 ==============================================================
6091 13:42:09.653587 Gating Mode config
6092 13:42:09.656682 ==============================================================
6093 13:42:09.660199 Config description:
6094 13:42:09.670109 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6095 13:42:09.676890 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6096 13:42:09.679870 SELPH_MODE 0: By rank 1: By Phase
6097 13:42:09.686567 ==============================================================
6098 13:42:09.689679 GAT_TRACK_EN = 0
6099 13:42:09.692956 RX_GATING_MODE = 2
6100 13:42:09.696744 RX_GATING_TRACK_MODE = 2
6101 13:42:09.699572 SELPH_MODE = 1
6102 13:42:09.702645 PICG_EARLY_EN = 1
6103 13:42:09.702775 VALID_LAT_VALUE = 1
6104 13:42:09.709836 ==============================================================
6105 13:42:09.712959 Enter into Gating configuration >>>>
6106 13:42:09.716124 Exit from Gating configuration <<<<
6107 13:42:09.719450 Enter into DVFS_PRE_config >>>>>
6108 13:42:09.729051 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6109 13:42:09.732624 Exit from DVFS_PRE_config <<<<<
6110 13:42:09.735885 Enter into PICG configuration >>>>
6111 13:42:09.738979 Exit from PICG configuration <<<<
6112 13:42:09.742669 [RX_INPUT] configuration >>>>>
6113 13:42:09.745788 [RX_INPUT] configuration <<<<<
6114 13:42:09.752153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6115 13:42:09.755908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6116 13:42:09.762120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6117 13:42:09.768614 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6118 13:42:09.775519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6119 13:42:09.781934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6120 13:42:09.785196 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6121 13:42:09.788906 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6122 13:42:09.791709 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6123 13:42:09.798410 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6124 13:42:09.801631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6125 13:42:09.805261 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6126 13:42:09.808191 ===================================
6127 13:42:09.811401 LPDDR4 DRAM CONFIGURATION
6128 13:42:09.814543 ===================================
6129 13:42:09.818403 EX_ROW_EN[0] = 0x0
6130 13:42:09.818485 EX_ROW_EN[1] = 0x0
6131 13:42:09.821545 LP4Y_EN = 0x0
6132 13:42:09.821627 WORK_FSP = 0x0
6133 13:42:09.824731 WL = 0x2
6134 13:42:09.824812 RL = 0x2
6135 13:42:09.827878 BL = 0x2
6136 13:42:09.827959 RPST = 0x0
6137 13:42:09.831168 RD_PRE = 0x0
6138 13:42:09.831249 WR_PRE = 0x1
6139 13:42:09.834234 WR_PST = 0x0
6140 13:42:09.834315 DBI_WR = 0x0
6141 13:42:09.838055 DBI_RD = 0x0
6142 13:42:09.841293 OTF = 0x1
6143 13:42:09.844486 ===================================
6144 13:42:09.847730 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6145 13:42:09.850671 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6146 13:42:09.854510 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 13:42:09.857734 ===================================
6148 13:42:09.860969 LPDDR4 DRAM CONFIGURATION
6149 13:42:09.863955 ===================================
6150 13:42:09.867696 EX_ROW_EN[0] = 0x10
6151 13:42:09.867777 EX_ROW_EN[1] = 0x0
6152 13:42:09.870967 LP4Y_EN = 0x0
6153 13:42:09.871049 WORK_FSP = 0x0
6154 13:42:09.874213 WL = 0x2
6155 13:42:09.874294 RL = 0x2
6156 13:42:09.877319 BL = 0x2
6157 13:42:09.877405 RPST = 0x0
6158 13:42:09.880711 RD_PRE = 0x0
6159 13:42:09.883900 WR_PRE = 0x1
6160 13:42:09.884001 WR_PST = 0x0
6161 13:42:09.887374 DBI_WR = 0x0
6162 13:42:09.887459 DBI_RD = 0x0
6163 13:42:09.890480 OTF = 0x1
6164 13:42:09.893629 ===================================
6165 13:42:09.896848 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6166 13:42:09.902151 nWR fixed to 30
6167 13:42:09.905419 [ModeRegInit_LP4] CH0 RK0
6168 13:42:09.905501 [ModeRegInit_LP4] CH0 RK1
6169 13:42:09.908711 [ModeRegInit_LP4] CH1 RK0
6170 13:42:09.911980 [ModeRegInit_LP4] CH1 RK1
6171 13:42:09.912061 match AC timing 19
6172 13:42:09.918957 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6173 13:42:09.922084 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6174 13:42:09.925616 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6175 13:42:09.931921 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6176 13:42:09.935150 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6177 13:42:09.935232 ==
6178 13:42:09.938391 Dram Type= 6, Freq= 0, CH_0, rank 0
6179 13:42:09.941603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6180 13:42:09.941685 ==
6181 13:42:09.948695 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6182 13:42:09.955031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6183 13:42:09.958050 [CA 0] Center 36 (8~64) winsize 57
6184 13:42:09.961190 [CA 1] Center 36 (8~64) winsize 57
6185 13:42:09.965061 [CA 2] Center 36 (8~64) winsize 57
6186 13:42:09.968256 [CA 3] Center 36 (8~64) winsize 57
6187 13:42:09.971176 [CA 4] Center 36 (8~64) winsize 57
6188 13:42:09.974408 [CA 5] Center 36 (8~64) winsize 57
6189 13:42:09.974489
6190 13:42:09.977728 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6191 13:42:09.977811
6192 13:42:09.981683 [CATrainingPosCal] consider 1 rank data
6193 13:42:09.984755 u2DelayCellTimex100 = 270/100 ps
6194 13:42:09.988185 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6195 13:42:09.991208 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 13:42:09.994683 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 13:42:09.997731 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 13:42:10.001752 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 13:42:10.004781 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 13:42:10.004863
6201 13:42:10.007907 CA PerBit enable=1, Macro0, CA PI delay=36
6202 13:42:10.011439
6203 13:42:10.011521 [CBTSetCACLKResult] CA Dly = 36
6204 13:42:10.014229 CS Dly: 1 (0~32)
6205 13:42:10.014310 ==
6206 13:42:10.017939 Dram Type= 6, Freq= 0, CH_0, rank 1
6207 13:42:10.020902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 13:42:10.020985 ==
6209 13:42:10.028002 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 13:42:10.034592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6211 13:42:10.037782 [CA 0] Center 36 (8~64) winsize 57
6212 13:42:10.040761 [CA 1] Center 36 (8~64) winsize 57
6213 13:42:10.044088 [CA 2] Center 36 (8~64) winsize 57
6214 13:42:10.047073 [CA 3] Center 36 (8~64) winsize 57
6215 13:42:10.047156 [CA 4] Center 36 (8~64) winsize 57
6216 13:42:10.050766 [CA 5] Center 36 (8~64) winsize 57
6217 13:42:10.050861
6218 13:42:10.057160 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6219 13:42:10.057287
6220 13:42:10.060262 [CATrainingPosCal] consider 2 rank data
6221 13:42:10.063963 u2DelayCellTimex100 = 270/100 ps
6222 13:42:10.067285 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 13:42:10.070611 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 13:42:10.073919 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 13:42:10.076965 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 13:42:10.080058 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 13:42:10.083248 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 13:42:10.083330
6229 13:42:10.086756 CA PerBit enable=1, Macro0, CA PI delay=36
6230 13:42:10.086838
6231 13:42:10.089747 [CBTSetCACLKResult] CA Dly = 36
6232 13:42:10.093748 CS Dly: 1 (0~32)
6233 13:42:10.093856
6234 13:42:10.096381 ----->DramcWriteLeveling(PI) begin...
6235 13:42:10.096463 ==
6236 13:42:10.099591 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 13:42:10.103507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 13:42:10.103590 ==
6239 13:42:10.106723 Write leveling (Byte 0): 40 => 8
6240 13:42:10.110001 Write leveling (Byte 1): 40 => 8
6241 13:42:10.113068 DramcWriteLeveling(PI) end<-----
6242 13:42:10.113149
6243 13:42:10.113214 ==
6244 13:42:10.116304 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 13:42:10.119446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 13:42:10.122932 ==
6247 13:42:10.123014 [Gating] SW mode calibration
6248 13:42:10.132676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6249 13:42:10.135860 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6250 13:42:10.139097 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6251 13:42:10.146065 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6252 13:42:10.149213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6253 13:42:10.152323 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 13:42:10.158856 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6255 13:42:10.162041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 13:42:10.165626 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 13:42:10.172133 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 13:42:10.175610 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6259 13:42:10.178744 Total UI for P1: 0, mck2ui 16
6260 13:42:10.182012 best dqsien dly found for B0: ( 0, 14, 24)
6261 13:42:10.185110 Total UI for P1: 0, mck2ui 16
6262 13:42:10.188312 best dqsien dly found for B1: ( 0, 14, 24)
6263 13:42:10.192151 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6264 13:42:10.195351 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6265 13:42:10.195458
6266 13:42:10.198611 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6267 13:42:10.205035 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6268 13:42:10.205116 [Gating] SW calibration Done
6269 13:42:10.205181 ==
6270 13:42:10.208105 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 13:42:10.215106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 13:42:10.215189 ==
6273 13:42:10.215254 RX Vref Scan: 0
6274 13:42:10.215316
6275 13:42:10.218209 RX Vref 0 -> 0, step: 1
6276 13:42:10.218290
6277 13:42:10.221399 RX Delay -410 -> 252, step: 16
6278 13:42:10.224681 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6279 13:42:10.228377 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6280 13:42:10.234897 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6281 13:42:10.237895 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6282 13:42:10.241109 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6283 13:42:10.244413 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6284 13:42:10.251226 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6285 13:42:10.254555 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6286 13:42:10.257954 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6287 13:42:10.261442 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6288 13:42:10.267680 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6289 13:42:10.270913 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6290 13:42:10.274319 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6291 13:42:10.280845 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6292 13:42:10.283836 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6293 13:42:10.287320 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6294 13:42:10.287402 ==
6295 13:42:10.291033 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 13:42:10.294142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 13:42:10.297117 ==
6298 13:42:10.297198 DQS Delay:
6299 13:42:10.297287 DQS0 = 35, DQS1 = 51
6300 13:42:10.300711 DQM Delay:
6301 13:42:10.300792 DQM0 = 4, DQM1 = 10
6302 13:42:10.303879 DQ Delay:
6303 13:42:10.303961 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6304 13:42:10.307063 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6305 13:42:10.310367 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6306 13:42:10.313542 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6307 13:42:10.313624
6308 13:42:10.313688
6309 13:42:10.316882 ==
6310 13:42:10.316963 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 13:42:10.323787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 13:42:10.323870 ==
6313 13:42:10.323934
6314 13:42:10.323993
6315 13:42:10.327013 TX Vref Scan disable
6316 13:42:10.327094 == TX Byte 0 ==
6317 13:42:10.330228 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6318 13:42:10.336631 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6319 13:42:10.336713 == TX Byte 1 ==
6320 13:42:10.339774 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6321 13:42:10.346213 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6322 13:42:10.346295 ==
6323 13:42:10.349506 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 13:42:10.353210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 13:42:10.353329 ==
6326 13:42:10.353393
6327 13:42:10.353453
6328 13:42:10.356611 TX Vref Scan disable
6329 13:42:10.356693 == TX Byte 0 ==
6330 13:42:10.359819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 13:42:10.366546 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 13:42:10.366628 == TX Byte 1 ==
6333 13:42:10.369643 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 13:42:10.376004 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 13:42:10.376086
6336 13:42:10.376149 [DATLAT]
6337 13:42:10.379294 Freq=400, CH0 RK0
6338 13:42:10.379375
6339 13:42:10.379439 DATLAT Default: 0xf
6340 13:42:10.382556 0, 0xFFFF, sum = 0
6341 13:42:10.382638 1, 0xFFFF, sum = 0
6342 13:42:10.385653 2, 0xFFFF, sum = 0
6343 13:42:10.385735 3, 0xFFFF, sum = 0
6344 13:42:10.389254 4, 0xFFFF, sum = 0
6345 13:42:10.389388 5, 0xFFFF, sum = 0
6346 13:42:10.392387 6, 0xFFFF, sum = 0
6347 13:42:10.392469 7, 0xFFFF, sum = 0
6348 13:42:10.395786 8, 0xFFFF, sum = 0
6349 13:42:10.395868 9, 0xFFFF, sum = 0
6350 13:42:10.399060 10, 0xFFFF, sum = 0
6351 13:42:10.399142 11, 0xFFFF, sum = 0
6352 13:42:10.402607 12, 0xFFFF, sum = 0
6353 13:42:10.402690 13, 0x0, sum = 1
6354 13:42:10.405471 14, 0x0, sum = 2
6355 13:42:10.405552 15, 0x0, sum = 3
6356 13:42:10.408734 16, 0x0, sum = 4
6357 13:42:10.408815 best_step = 14
6358 13:42:10.408879
6359 13:42:10.408937 ==
6360 13:42:10.412276 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 13:42:10.419345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 13:42:10.419434 ==
6363 13:42:10.419499 RX Vref Scan: 1
6364 13:42:10.419559
6365 13:42:10.421921 RX Vref 0 -> 0, step: 1
6366 13:42:10.422001
6367 13:42:10.425870 RX Delay -343 -> 252, step: 8
6368 13:42:10.425952
6369 13:42:10.428904 Set Vref, RX VrefLevel [Byte0]: 57
6370 13:42:10.432043 [Byte1]: 59
6371 13:42:10.435279
6372 13:42:10.435364 Final RX Vref Byte 0 = 57 to rank0
6373 13:42:10.438592 Final RX Vref Byte 1 = 59 to rank0
6374 13:42:10.442201 Final RX Vref Byte 0 = 57 to rank1
6375 13:42:10.445535 Final RX Vref Byte 1 = 59 to rank1==
6376 13:42:10.448533 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 13:42:10.455617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 13:42:10.455699 ==
6379 13:42:10.455764 DQS Delay:
6380 13:42:10.458750 DQS0 = 44, DQS1 = 60
6381 13:42:10.458831 DQM Delay:
6382 13:42:10.458897 DQM0 = 11, DQM1 = 16
6383 13:42:10.462128 DQ Delay:
6384 13:42:10.465581 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6385 13:42:10.468793 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6386 13:42:10.468874 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6387 13:42:10.472110 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6388 13:42:10.475214
6389 13:42:10.475294
6390 13:42:10.481642 [DQSOSCAuto] RK0, (LSB)MR18= 0x978b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6391 13:42:10.484877 CH0 RK0: MR19=C0C, MR18=978B
6392 13:42:10.491300 CH0_RK0: MR19=0xC0C, MR18=0x978B, DQSOSC=390, MR23=63, INC=388, DEC=258
6393 13:42:10.491381 ==
6394 13:42:10.494908 Dram Type= 6, Freq= 0, CH_0, rank 1
6395 13:42:10.498049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 13:42:10.498131 ==
6397 13:42:10.501714 [Gating] SW mode calibration
6398 13:42:10.508341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6399 13:42:10.515029 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6400 13:42:10.518003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 13:42:10.521068 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 13:42:10.528373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 13:42:10.531028 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 13:42:10.534522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 13:42:10.541381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 13:42:10.544435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 13:42:10.548104 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 13:42:10.554650 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6409 13:42:10.554761 Total UI for P1: 0, mck2ui 16
6410 13:42:10.560716 best dqsien dly found for B0: ( 0, 14, 24)
6411 13:42:10.560797 Total UI for P1: 0, mck2ui 16
6412 13:42:10.567721 best dqsien dly found for B1: ( 0, 14, 24)
6413 13:42:10.570822 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6414 13:42:10.574111 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6415 13:42:10.574192
6416 13:42:10.577390 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 13:42:10.580690 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 13:42:10.583826 [Gating] SW calibration Done
6419 13:42:10.583909 ==
6420 13:42:10.586944 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 13:42:10.590252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 13:42:10.590334 ==
6423 13:42:10.593975 RX Vref Scan: 0
6424 13:42:10.594055
6425 13:42:10.597155 RX Vref 0 -> 0, step: 1
6426 13:42:10.597237
6427 13:42:10.597312 RX Delay -410 -> 252, step: 16
6428 13:42:10.603799 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6429 13:42:10.606919 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6430 13:42:10.610002 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6431 13:42:10.617016 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6432 13:42:10.620140 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6433 13:42:10.623185 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6434 13:42:10.626512 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6435 13:42:10.633552 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6436 13:42:10.636805 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6437 13:42:10.639774 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6438 13:42:10.643421 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6439 13:42:10.649524 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6440 13:42:10.652913 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6441 13:42:10.656130 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6442 13:42:10.659811 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6443 13:42:10.666190 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6444 13:42:10.666273 ==
6445 13:42:10.669854 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 13:42:10.672672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 13:42:10.672754 ==
6448 13:42:10.676255 DQS Delay:
6449 13:42:10.676336 DQS0 = 35, DQS1 = 59
6450 13:42:10.676401 DQM Delay:
6451 13:42:10.679226 DQM0 = 5, DQM1 = 16
6452 13:42:10.679307 DQ Delay:
6453 13:42:10.682940 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6454 13:42:10.686228 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6455 13:42:10.689419 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6456 13:42:10.692623 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6457 13:42:10.692704
6458 13:42:10.692768
6459 13:42:10.692826 ==
6460 13:42:10.695931 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 13:42:10.699056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 13:42:10.699137 ==
6463 13:42:10.702159
6464 13:42:10.702240
6465 13:42:10.702303 TX Vref Scan disable
6466 13:42:10.706031 == TX Byte 0 ==
6467 13:42:10.709055 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6468 13:42:10.712339 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6469 13:42:10.715637 == TX Byte 1 ==
6470 13:42:10.718644 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6471 13:42:10.721864 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6472 13:42:10.721946 ==
6473 13:42:10.725108 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 13:42:10.731820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 13:42:10.731905 ==
6476 13:42:10.731969
6477 13:42:10.732029
6478 13:42:10.732087 TX Vref Scan disable
6479 13:42:10.735405 == TX Byte 0 ==
6480 13:42:10.738596 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6481 13:42:10.741858 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6482 13:42:10.744922 == TX Byte 1 ==
6483 13:42:10.748458 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6484 13:42:10.751879 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6485 13:42:10.751975
6486 13:42:10.754865 [DATLAT]
6487 13:42:10.754954 Freq=400, CH0 RK1
6488 13:42:10.755037
6489 13:42:10.758371 DATLAT Default: 0xe
6490 13:42:10.758453 0, 0xFFFF, sum = 0
6491 13:42:10.761237 1, 0xFFFF, sum = 0
6492 13:42:10.761410 2, 0xFFFF, sum = 0
6493 13:42:10.764718 3, 0xFFFF, sum = 0
6494 13:42:10.764802 4, 0xFFFF, sum = 0
6495 13:42:10.767850 5, 0xFFFF, sum = 0
6496 13:42:10.767923 6, 0xFFFF, sum = 0
6497 13:42:10.771128 7, 0xFFFF, sum = 0
6498 13:42:10.771201 8, 0xFFFF, sum = 0
6499 13:42:10.774408 9, 0xFFFF, sum = 0
6500 13:42:10.778239 10, 0xFFFF, sum = 0
6501 13:42:10.778322 11, 0xFFFF, sum = 0
6502 13:42:10.781198 12, 0xFFFF, sum = 0
6503 13:42:10.781372 13, 0x0, sum = 1
6504 13:42:10.784760 14, 0x0, sum = 2
6505 13:42:10.784843 15, 0x0, sum = 3
6506 13:42:10.784908 16, 0x0, sum = 4
6507 13:42:10.788106 best_step = 14
6508 13:42:10.788187
6509 13:42:10.788251 ==
6510 13:42:10.791143 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 13:42:10.794767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 13:42:10.794849 ==
6513 13:42:10.797949 RX Vref Scan: 0
6514 13:42:10.798029
6515 13:42:10.801225 RX Vref 0 -> 0, step: 1
6516 13:42:10.801353
6517 13:42:10.801418 RX Delay -359 -> 252, step: 8
6518 13:42:10.809664 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6519 13:42:10.812875 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6520 13:42:10.816583 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6521 13:42:10.822835 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6522 13:42:10.825964 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6523 13:42:10.829227 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6524 13:42:10.832612 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6525 13:42:10.839490 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6526 13:42:10.842397 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6527 13:42:10.845527 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6528 13:42:10.848730 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6529 13:42:10.855849 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6530 13:42:10.859156 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6531 13:42:10.862148 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6532 13:42:10.869021 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6533 13:42:10.871854 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6534 13:42:10.871936 ==
6535 13:42:10.875272 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 13:42:10.878322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 13:42:10.878404 ==
6538 13:42:10.881641 DQS Delay:
6539 13:42:10.881722 DQS0 = 44, DQS1 = 60
6540 13:42:10.881786 DQM Delay:
6541 13:42:10.885339 DQM0 = 10, DQM1 = 16
6542 13:42:10.885419 DQ Delay:
6543 13:42:10.888579 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6544 13:42:10.891853 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6545 13:42:10.894788 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6546 13:42:10.898394 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6547 13:42:10.898475
6548 13:42:10.898539
6549 13:42:10.908723 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6550 13:42:10.908805 CH0 RK1: MR19=C0C, MR18=8A83
6551 13:42:10.915119 CH0_RK1: MR19=0xC0C, MR18=0x8A83, DQSOSC=392, MR23=63, INC=384, DEC=256
6552 13:42:10.918262 [RxdqsGatingPostProcess] freq 400
6553 13:42:10.924803 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6554 13:42:10.928405 best DQS0 dly(2T, 0.5T) = (0, 10)
6555 13:42:10.931249 best DQS1 dly(2T, 0.5T) = (0, 10)
6556 13:42:10.935004 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6557 13:42:10.938196 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6558 13:42:10.941547 best DQS0 dly(2T, 0.5T) = (0, 10)
6559 13:42:10.944648 best DQS1 dly(2T, 0.5T) = (0, 10)
6560 13:42:10.947685 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6561 13:42:10.951246 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6562 13:42:10.951328 Pre-setting of DQS Precalculation
6563 13:42:10.957761 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6564 13:42:10.957844 ==
6565 13:42:10.960823 Dram Type= 6, Freq= 0, CH_1, rank 0
6566 13:42:10.964242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 13:42:10.964326 ==
6568 13:42:10.970608 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6569 13:42:10.977742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6570 13:42:10.980678 [CA 0] Center 36 (8~64) winsize 57
6571 13:42:10.983863 [CA 1] Center 36 (8~64) winsize 57
6572 13:42:10.987201 [CA 2] Center 36 (8~64) winsize 57
6573 13:42:10.990629 [CA 3] Center 36 (8~64) winsize 57
6574 13:42:10.993621 [CA 4] Center 36 (8~64) winsize 57
6575 13:42:10.997097 [CA 5] Center 36 (8~64) winsize 57
6576 13:42:10.997178
6577 13:42:11.000259 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6578 13:42:11.000341
6579 13:42:11.003395 [CATrainingPosCal] consider 1 rank data
6580 13:42:11.007308 u2DelayCellTimex100 = 270/100 ps
6581 13:42:11.010082 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6582 13:42:11.013632 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 13:42:11.017420 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 13:42:11.020558 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 13:42:11.023829 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 13:42:11.027126 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 13:42:11.027207
6588 13:42:11.030305 CA PerBit enable=1, Macro0, CA PI delay=36
6589 13:42:11.033515
6590 13:42:11.033597 [CBTSetCACLKResult] CA Dly = 36
6591 13:42:11.036777 CS Dly: 1 (0~32)
6592 13:42:11.036858 ==
6593 13:42:11.040372 Dram Type= 6, Freq= 0, CH_1, rank 1
6594 13:42:11.043192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 13:42:11.043274 ==
6596 13:42:11.050101 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 13:42:11.056800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6598 13:42:11.059617 [CA 0] Center 36 (8~64) winsize 57
6599 13:42:11.063526 [CA 1] Center 36 (8~64) winsize 57
6600 13:42:11.066219 [CA 2] Center 36 (8~64) winsize 57
6601 13:42:11.066305 [CA 3] Center 36 (8~64) winsize 57
6602 13:42:11.070094 [CA 4] Center 36 (8~64) winsize 57
6603 13:42:11.072933 [CA 5] Center 36 (8~64) winsize 57
6604 13:42:11.073015
6605 13:42:11.079487 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6606 13:42:11.079569
6607 13:42:11.083198 [CATrainingPosCal] consider 2 rank data
6608 13:42:11.086527 u2DelayCellTimex100 = 270/100 ps
6609 13:42:11.089581 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 13:42:11.092821 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 13:42:11.096389 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 13:42:11.099549 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 13:42:11.102532 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 13:42:11.105949 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 13:42:11.106059
6616 13:42:11.109042 CA PerBit enable=1, Macro0, CA PI delay=36
6617 13:42:11.109124
6618 13:42:11.112809 [CBTSetCACLKResult] CA Dly = 36
6619 13:42:11.115886 CS Dly: 1 (0~32)
6620 13:42:11.115967
6621 13:42:11.119467 ----->DramcWriteLeveling(PI) begin...
6622 13:42:11.119551 ==
6623 13:42:11.122344 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 13:42:11.126130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 13:42:11.126213 ==
6626 13:42:11.129456 Write leveling (Byte 0): 40 => 8
6627 13:42:11.132652 Write leveling (Byte 1): 40 => 8
6628 13:42:11.135886 DramcWriteLeveling(PI) end<-----
6629 13:42:11.135968
6630 13:42:11.136032 ==
6631 13:42:11.139061 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 13:42:11.142349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 13:42:11.142432 ==
6634 13:42:11.145528 [Gating] SW mode calibration
6635 13:42:11.152458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6636 13:42:11.158765 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6637 13:42:11.161975 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6638 13:42:11.168539 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 13:42:11.172388 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6640 13:42:11.175721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 13:42:11.181967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6642 13:42:11.185189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 13:42:11.188443 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 13:42:11.194971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 13:42:11.198297 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6646 13:42:11.201911 Total UI for P1: 0, mck2ui 16
6647 13:42:11.204912 best dqsien dly found for B0: ( 0, 14, 24)
6648 13:42:11.208597 Total UI for P1: 0, mck2ui 16
6649 13:42:11.211504 best dqsien dly found for B1: ( 0, 14, 24)
6650 13:42:11.214574 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6651 13:42:11.218143 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6652 13:42:11.218226
6653 13:42:11.221095 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6654 13:42:11.224555 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6655 13:42:11.227791 [Gating] SW calibration Done
6656 13:42:11.227873 ==
6657 13:42:11.231388 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 13:42:11.234543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 13:42:11.237842 ==
6660 13:42:11.237951 RX Vref Scan: 0
6661 13:42:11.238020
6662 13:42:11.241221 RX Vref 0 -> 0, step: 1
6663 13:42:11.241315
6664 13:42:11.244501 RX Delay -410 -> 252, step: 16
6665 13:42:11.247781 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6666 13:42:11.251055 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6667 13:42:11.254249 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6668 13:42:11.260711 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6669 13:42:11.264274 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6670 13:42:11.267647 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6671 13:42:11.273935 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6672 13:42:11.277500 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6673 13:42:11.280841 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6674 13:42:11.283741 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6675 13:42:11.290300 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6676 13:42:11.293393 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6677 13:42:11.297242 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6678 13:42:11.299844 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6679 13:42:11.306998 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6680 13:42:11.310034 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6681 13:42:11.310116 ==
6682 13:42:11.313041 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 13:42:11.316908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 13:42:11.316990 ==
6685 13:42:11.319978 DQS Delay:
6686 13:42:11.320060 DQS0 = 43, DQS1 = 51
6687 13:42:11.323153 DQM Delay:
6688 13:42:11.323234 DQM0 = 13, DQM1 = 13
6689 13:42:11.326199 DQ Delay:
6690 13:42:11.326285 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6691 13:42:11.329931 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6692 13:42:11.333156 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6693 13:42:11.336605 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6694 13:42:11.336686
6695 13:42:11.336750
6696 13:42:11.336811 ==
6697 13:42:11.339702 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 13:42:11.345997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 13:42:11.346080 ==
6700 13:42:11.346145
6701 13:42:11.346204
6702 13:42:11.349221 TX Vref Scan disable
6703 13:42:11.349345 == TX Byte 0 ==
6704 13:42:11.352446 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6705 13:42:11.359609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6706 13:42:11.359690 == TX Byte 1 ==
6707 13:42:11.362798 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6708 13:42:11.369421 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6709 13:42:11.369503 ==
6710 13:42:11.372293 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 13:42:11.375885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 13:42:11.375978 ==
6713 13:42:11.376046
6714 13:42:11.376106
6715 13:42:11.379022 TX Vref Scan disable
6716 13:42:11.379104 == TX Byte 0 ==
6717 13:42:11.382635 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 13:42:11.389081 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 13:42:11.389163 == TX Byte 1 ==
6720 13:42:11.392376 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 13:42:11.399100 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 13:42:11.399182
6723 13:42:11.399247 [DATLAT]
6724 13:42:11.399307 Freq=400, CH1 RK0
6725 13:42:11.402329
6726 13:42:11.402410 DATLAT Default: 0xf
6727 13:42:11.405664 0, 0xFFFF, sum = 0
6728 13:42:11.405747 1, 0xFFFF, sum = 0
6729 13:42:11.408913 2, 0xFFFF, sum = 0
6730 13:42:11.408996 3, 0xFFFF, sum = 0
6731 13:42:11.412058 4, 0xFFFF, sum = 0
6732 13:42:11.412141 5, 0xFFFF, sum = 0
6733 13:42:11.415137 6, 0xFFFF, sum = 0
6734 13:42:11.415226 7, 0xFFFF, sum = 0
6735 13:42:11.418755 8, 0xFFFF, sum = 0
6736 13:42:11.418865 9, 0xFFFF, sum = 0
6737 13:42:11.421930 10, 0xFFFF, sum = 0
6738 13:42:11.422012 11, 0xFFFF, sum = 0
6739 13:42:11.425493 12, 0xFFFF, sum = 0
6740 13:42:11.425576 13, 0x0, sum = 1
6741 13:42:11.428625 14, 0x0, sum = 2
6742 13:42:11.428708 15, 0x0, sum = 3
6743 13:42:11.431770 16, 0x0, sum = 4
6744 13:42:11.431853 best_step = 14
6745 13:42:11.431917
6746 13:42:11.431977 ==
6747 13:42:11.434968 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 13:42:11.441750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 13:42:11.441861 ==
6750 13:42:11.441956 RX Vref Scan: 1
6751 13:42:11.442028
6752 13:42:11.445035 RX Vref 0 -> 0, step: 1
6753 13:42:11.445117
6754 13:42:11.448250 RX Delay -343 -> 252, step: 8
6755 13:42:11.448332
6756 13:42:11.451832 Set Vref, RX VrefLevel [Byte0]: 50
6757 13:42:11.455217 [Byte1]: 53
6758 13:42:11.455299
6759 13:42:11.458453 Final RX Vref Byte 0 = 50 to rank0
6760 13:42:11.461627 Final RX Vref Byte 1 = 53 to rank0
6761 13:42:11.464904 Final RX Vref Byte 0 = 50 to rank1
6762 13:42:11.468172 Final RX Vref Byte 1 = 53 to rank1==
6763 13:42:11.471524 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 13:42:11.477865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 13:42:11.477948 ==
6766 13:42:11.478013 DQS Delay:
6767 13:42:11.481455 DQS0 = 44, DQS1 = 52
6768 13:42:11.481536 DQM Delay:
6769 13:42:11.481600 DQM0 = 11, DQM1 = 11
6770 13:42:11.484578 DQ Delay:
6771 13:42:11.487858 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6772 13:42:11.487940 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6773 13:42:11.490956 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6774 13:42:11.494807 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6775 13:42:11.494889
6776 13:42:11.497796
6777 13:42:11.504554 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6778 13:42:11.508168 CH1 RK0: MR19=C0C, MR18=6F96
6779 13:42:11.514678 CH1_RK0: MR19=0xC0C, MR18=0x6F96, DQSOSC=391, MR23=63, INC=386, DEC=257
6780 13:42:11.514761 ==
6781 13:42:11.517866 Dram Type= 6, Freq= 0, CH_1, rank 1
6782 13:42:11.521029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 13:42:11.521112 ==
6784 13:42:11.524064 [Gating] SW mode calibration
6785 13:42:11.530928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6786 13:42:11.537148 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6787 13:42:11.540826 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 13:42:11.544000 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 13:42:11.550949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 13:42:11.554101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 13:42:11.557774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 13:42:11.563960 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 13:42:11.566859 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 13:42:11.570503 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 13:42:11.576893 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6796 13:42:11.577001 Total UI for P1: 0, mck2ui 16
6797 13:42:11.583289 best dqsien dly found for B0: ( 0, 14, 24)
6798 13:42:11.583371 Total UI for P1: 0, mck2ui 16
6799 13:42:11.589936 best dqsien dly found for B1: ( 0, 14, 24)
6800 13:42:11.593712 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6801 13:42:11.596935 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6802 13:42:11.597042
6803 13:42:11.600054 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 13:42:11.603269 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 13:42:11.606443 [Gating] SW calibration Done
6806 13:42:11.606549 ==
6807 13:42:11.610106 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 13:42:11.613206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 13:42:11.613343 ==
6810 13:42:11.616529 RX Vref Scan: 0
6811 13:42:11.616609
6812 13:42:11.616673 RX Vref 0 -> 0, step: 1
6813 13:42:11.619632
6814 13:42:11.619712 RX Delay -410 -> 252, step: 16
6815 13:42:11.626445 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6816 13:42:11.630144 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6817 13:42:11.632679 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6818 13:42:11.636439 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6819 13:42:11.642881 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6820 13:42:11.645909 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6821 13:42:11.649624 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6822 13:42:11.652717 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6823 13:42:11.659298 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6824 13:42:11.662292 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6825 13:42:11.666016 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6826 13:42:11.672242 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6827 13:42:11.675806 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6828 13:42:11.679298 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6829 13:42:11.682618 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6830 13:42:11.689112 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6831 13:42:11.689219 ==
6832 13:42:11.692227 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 13:42:11.695277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 13:42:11.695359 ==
6835 13:42:11.695423 DQS Delay:
6836 13:42:11.699010 DQS0 = 43, DQS1 = 51
6837 13:42:11.699091 DQM Delay:
6838 13:42:11.702143 DQM0 = 9, DQM1 = 14
6839 13:42:11.702224 DQ Delay:
6840 13:42:11.705295 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6841 13:42:11.708496 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6842 13:42:11.711841 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6843 13:42:11.715106 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6844 13:42:11.715187
6845 13:42:11.715251
6846 13:42:11.715310 ==
6847 13:42:11.718865 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 13:42:11.721923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 13:42:11.722004 ==
6850 13:42:11.722068
6851 13:42:11.725132
6852 13:42:11.725238 TX Vref Scan disable
6853 13:42:11.728228 == TX Byte 0 ==
6854 13:42:11.731603 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6855 13:42:11.735319 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6856 13:42:11.738467 == TX Byte 1 ==
6857 13:42:11.741510 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6858 13:42:11.744805 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6859 13:42:11.744887 ==
6860 13:42:11.748028 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 13:42:11.751039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 13:42:11.754677 ==
6863 13:42:11.754759
6864 13:42:11.754822
6865 13:42:11.754890 TX Vref Scan disable
6866 13:42:11.757920 == TX Byte 0 ==
6867 13:42:11.761160 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6868 13:42:11.764393 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6869 13:42:11.767502 == TX Byte 1 ==
6870 13:42:11.771364 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6871 13:42:11.774203 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6872 13:42:11.774285
6873 13:42:11.777353 [DATLAT]
6874 13:42:11.777434 Freq=400, CH1 RK1
6875 13:42:11.777499
6876 13:42:11.781043 DATLAT Default: 0xe
6877 13:42:11.781168 0, 0xFFFF, sum = 0
6878 13:42:11.784242 1, 0xFFFF, sum = 0
6879 13:42:11.784350 2, 0xFFFF, sum = 0
6880 13:42:11.787585 3, 0xFFFF, sum = 0
6881 13:42:11.787673 4, 0xFFFF, sum = 0
6882 13:42:11.790848 5, 0xFFFF, sum = 0
6883 13:42:11.790930 6, 0xFFFF, sum = 0
6884 13:42:11.794071 7, 0xFFFF, sum = 0
6885 13:42:11.794152 8, 0xFFFF, sum = 0
6886 13:42:11.797228 9, 0xFFFF, sum = 0
6887 13:42:11.797359 10, 0xFFFF, sum = 0
6888 13:42:11.801096 11, 0xFFFF, sum = 0
6889 13:42:11.801205 12, 0xFFFF, sum = 0
6890 13:42:11.803977 13, 0x0, sum = 1
6891 13:42:11.804058 14, 0x0, sum = 2
6892 13:42:11.807631 15, 0x0, sum = 3
6893 13:42:11.807714 16, 0x0, sum = 4
6894 13:42:11.810599 best_step = 14
6895 13:42:11.810679
6896 13:42:11.810804 ==
6897 13:42:11.813809 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 13:42:11.817007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 13:42:11.817088 ==
6900 13:42:11.820314 RX Vref Scan: 0
6901 13:42:11.820394
6902 13:42:11.820457 RX Vref 0 -> 0, step: 1
6903 13:42:11.820517
6904 13:42:11.823581 RX Delay -343 -> 252, step: 8
6905 13:42:11.831861 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6906 13:42:11.835173 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6907 13:42:11.838464 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6908 13:42:11.845620 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6909 13:42:11.848359 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6910 13:42:11.851807 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6911 13:42:11.855120 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6912 13:42:11.861364 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6913 13:42:11.865044 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6914 13:42:11.868111 iDelay=217, Bit 9, Center -48 (-287 ~ 192) 480
6915 13:42:11.871217 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6916 13:42:11.877654 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6917 13:42:11.881122 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6918 13:42:11.884301 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6919 13:42:11.890956 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6920 13:42:11.894296 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6921 13:42:11.894378 ==
6922 13:42:11.897490 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 13:42:11.901255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 13:42:11.901376 ==
6925 13:42:11.904499 DQS Delay:
6926 13:42:11.904580 DQS0 = 48, DQS1 = 52
6927 13:42:11.904645 DQM Delay:
6928 13:42:11.907550 DQM0 = 12, DQM1 = 11
6929 13:42:11.907661 DQ Delay:
6930 13:42:11.910811 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6931 13:42:11.914274 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6932 13:42:11.917235 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6933 13:42:11.920556 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6934 13:42:11.920638
6935 13:42:11.920701
6936 13:42:11.930158 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bb2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6937 13:42:11.934026 CH1 RK1: MR19=C0C, MR18=7BB2
6938 13:42:11.937273 CH1_RK1: MR19=0xC0C, MR18=0x7BB2, DQSOSC=387, MR23=63, INC=394, DEC=262
6939 13:42:11.940552 [RxdqsGatingPostProcess] freq 400
6940 13:42:11.946796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6941 13:42:11.950182 best DQS0 dly(2T, 0.5T) = (0, 10)
6942 13:42:11.953878 best DQS1 dly(2T, 0.5T) = (0, 10)
6943 13:42:11.956658 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6944 13:42:11.960204 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6945 13:42:11.963191 best DQS0 dly(2T, 0.5T) = (0, 10)
6946 13:42:11.966722 best DQS1 dly(2T, 0.5T) = (0, 10)
6947 13:42:11.970003 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6948 13:42:11.973521 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6949 13:42:11.976412 Pre-setting of DQS Precalculation
6950 13:42:11.980060 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6951 13:42:11.986361 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6952 13:42:11.993120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6953 13:42:11.996191
6954 13:42:11.996354
6955 13:42:11.996465 [Calibration Summary] 800 Mbps
6956 13:42:11.999964 CH 0, Rank 0
6957 13:42:12.000149 SW Impedance : PASS
6958 13:42:12.003170 DUTY Scan : NO K
6959 13:42:12.006041 ZQ Calibration : PASS
6960 13:42:12.006172 Jitter Meter : NO K
6961 13:42:12.009934 CBT Training : PASS
6962 13:42:12.012575 Write leveling : PASS
6963 13:42:12.012681 RX DQS gating : PASS
6964 13:42:12.016294 RX DQ/DQS(RDDQC) : PASS
6965 13:42:12.019450 TX DQ/DQS : PASS
6966 13:42:12.019555 RX DATLAT : PASS
6967 13:42:12.022685 RX DQ/DQS(Engine): PASS
6968 13:42:12.025669 TX OE : NO K
6969 13:42:12.025775 All Pass.
6970 13:42:12.025866
6971 13:42:12.025955 CH 0, Rank 1
6972 13:42:12.029552 SW Impedance : PASS
6973 13:42:12.032402 DUTY Scan : NO K
6974 13:42:12.032513 ZQ Calibration : PASS
6975 13:42:12.035752 Jitter Meter : NO K
6976 13:42:12.039030 CBT Training : PASS
6977 13:42:12.039114 Write leveling : NO K
6978 13:42:12.042783 RX DQS gating : PASS
6979 13:42:12.046035 RX DQ/DQS(RDDQC) : PASS
6980 13:42:12.046117 TX DQ/DQS : PASS
6981 13:42:12.049328 RX DATLAT : PASS
6982 13:42:12.052449 RX DQ/DQS(Engine): PASS
6983 13:42:12.052532 TX OE : NO K
6984 13:42:12.052597 All Pass.
6985 13:42:12.055732
6986 13:42:12.055814 CH 1, Rank 0
6987 13:42:12.059019 SW Impedance : PASS
6988 13:42:12.059102 DUTY Scan : NO K
6989 13:42:12.062530 ZQ Calibration : PASS
6990 13:42:12.065806 Jitter Meter : NO K
6991 13:42:12.065892 CBT Training : PASS
6992 13:42:12.068896 Write leveling : PASS
6993 13:42:12.068979 RX DQS gating : PASS
6994 13:42:12.072145 RX DQ/DQS(RDDQC) : PASS
6995 13:42:12.075678 TX DQ/DQS : PASS
6996 13:42:12.075763 RX DATLAT : PASS
6997 13:42:12.078796 RX DQ/DQS(Engine): PASS
6998 13:42:12.081764 TX OE : NO K
6999 13:42:12.081849 All Pass.
7000 13:42:12.081916
7001 13:42:12.081978 CH 1, Rank 1
7002 13:42:12.085469 SW Impedance : PASS
7003 13:42:12.088736 DUTY Scan : NO K
7004 13:42:12.088820 ZQ Calibration : PASS
7005 13:42:12.091766 Jitter Meter : NO K
7006 13:42:12.095385 CBT Training : PASS
7007 13:42:12.095472 Write leveling : NO K
7008 13:42:12.098830 RX DQS gating : PASS
7009 13:42:12.101786 RX DQ/DQS(RDDQC) : PASS
7010 13:42:12.101872 TX DQ/DQS : PASS
7011 13:42:12.104771 RX DATLAT : PASS
7012 13:42:12.107976 RX DQ/DQS(Engine): PASS
7013 13:42:12.108067 TX OE : NO K
7014 13:42:12.111129 All Pass.
7015 13:42:12.111213
7016 13:42:12.111279 DramC Write-DBI off
7017 13:42:12.114443 PER_BANK_REFRESH: Hybrid Mode
7018 13:42:12.117686 TX_TRACKING: ON
7019 13:42:12.124737 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7020 13:42:12.128026 [FAST_K] Save calibration result to emmc
7021 13:42:12.131270 dramc_set_vcore_voltage set vcore to 725000
7022 13:42:12.134235 Read voltage for 1600, 0
7023 13:42:12.134365 Vio18 = 0
7024 13:42:12.137455 Vcore = 725000
7025 13:42:12.137531 Vdram = 0
7026 13:42:12.137598 Vddq = 0
7027 13:42:12.140936 Vmddr = 0
7028 13:42:12.144364 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7029 13:42:12.151123 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7030 13:42:12.154378 MEM_TYPE=3, freq_sel=13
7031 13:42:12.154463 sv_algorithm_assistance_LP4_3733
7032 13:42:12.160856 ============ PULL DRAM RESETB DOWN ============
7033 13:42:12.164189 ========== PULL DRAM RESETB DOWN end =========
7034 13:42:12.167094 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7035 13:42:12.178326 ===================================
7036 13:42:12.178489 LPDDR4 DRAM CONFIGURATION
7037 13:42:12.178635 ===================================
7038 13:42:12.180192 EX_ROW_EN[0] = 0x0
7039 13:42:12.180319 EX_ROW_EN[1] = 0x0
7040 13:42:12.183595 LP4Y_EN = 0x0
7041 13:42:12.183750 WORK_FSP = 0x1
7042 13:42:12.187734 WL = 0x5
7043 13:42:12.187896 RL = 0x5
7044 13:42:12.190212 BL = 0x2
7045 13:42:12.190382 RPST = 0x0
7046 13:42:12.193634 RD_PRE = 0x0
7047 13:42:12.196878 WR_PRE = 0x1
7048 13:42:12.197024 WR_PST = 0x1
7049 13:42:12.200123 DBI_WR = 0x0
7050 13:42:12.200265 DBI_RD = 0x0
7051 13:42:12.203952 OTF = 0x1
7052 13:42:12.206672 ===================================
7053 13:42:12.210035 ===================================
7054 13:42:12.210202 ANA top config
7055 13:42:12.213699 ===================================
7056 13:42:12.216570 DLL_ASYNC_EN = 0
7057 13:42:12.219969 ALL_SLAVE_EN = 0
7058 13:42:12.220125 NEW_RANK_MODE = 1
7059 13:42:12.223153 DLL_IDLE_MODE = 1
7060 13:42:12.227033 LP45_APHY_COMB_EN = 1
7061 13:42:12.229769 TX_ODT_DIS = 0
7062 13:42:12.229902 NEW_8X_MODE = 1
7063 13:42:12.233369 ===================================
7064 13:42:12.236727 ===================================
7065 13:42:12.240037 data_rate = 3200
7066 13:42:12.243155 CKR = 1
7067 13:42:12.246281 DQ_P2S_RATIO = 8
7068 13:42:12.249954 ===================================
7069 13:42:12.253008 CA_P2S_RATIO = 8
7070 13:42:12.256405 DQ_CA_OPEN = 0
7071 13:42:12.259674 DQ_SEMI_OPEN = 0
7072 13:42:12.259779 CA_SEMI_OPEN = 0
7073 13:42:12.262921 CA_FULL_RATE = 0
7074 13:42:12.266243 DQ_CKDIV4_EN = 0
7075 13:42:12.269293 CA_CKDIV4_EN = 0
7076 13:42:12.272686 CA_PREDIV_EN = 0
7077 13:42:12.275676 PH8_DLY = 12
7078 13:42:12.275822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7079 13:42:12.279381 DQ_AAMCK_DIV = 4
7080 13:42:12.282484 CA_AAMCK_DIV = 4
7081 13:42:12.285799 CA_ADMCK_DIV = 4
7082 13:42:12.288826 DQ_TRACK_CA_EN = 0
7083 13:42:12.292358 CA_PICK = 1600
7084 13:42:12.295177 CA_MCKIO = 1600
7085 13:42:12.298758 MCKIO_SEMI = 0
7086 13:42:12.298906 PLL_FREQ = 3068
7087 13:42:12.301973 DQ_UI_PI_RATIO = 32
7088 13:42:12.305190 CA_UI_PI_RATIO = 0
7089 13:42:12.308565 ===================================
7090 13:42:12.312079 ===================================
7091 13:42:12.315054 memory_type:LPDDR4
7092 13:42:12.318214 GP_NUM : 10
7093 13:42:12.318340 SRAM_EN : 1
7094 13:42:12.321808 MD32_EN : 0
7095 13:42:12.324856 ===================================
7096 13:42:12.324988 [ANA_INIT] >>>>>>>>>>>>>>
7097 13:42:12.328393 <<<<<< [CONFIGURE PHASE]: ANA_TX
7098 13:42:12.331550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7099 13:42:12.334661 ===================================
7100 13:42:12.337899 data_rate = 3200,PCW = 0X7600
7101 13:42:12.341118 ===================================
7102 13:42:12.345061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7103 13:42:12.351528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7104 13:42:12.357890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7105 13:42:12.361493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7106 13:42:12.364480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7107 13:42:12.367976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7108 13:42:12.371432 [ANA_INIT] flow start
7109 13:42:12.371535 [ANA_INIT] PLL >>>>>>>>
7110 13:42:12.374305 [ANA_INIT] PLL <<<<<<<<
7111 13:42:12.378038 [ANA_INIT] MIDPI >>>>>>>>
7112 13:42:12.381226 [ANA_INIT] MIDPI <<<<<<<<
7113 13:42:12.381361 [ANA_INIT] DLL >>>>>>>>
7114 13:42:12.384240 [ANA_INIT] DLL <<<<<<<<
7115 13:42:12.384326 [ANA_INIT] flow end
7116 13:42:12.391136 ============ LP4 DIFF to SE enter ============
7117 13:42:12.394370 ============ LP4 DIFF to SE exit ============
7118 13:42:12.397438 [ANA_INIT] <<<<<<<<<<<<<
7119 13:42:12.400979 [Flow] Enable top DCM control >>>>>
7120 13:42:12.404001 [Flow] Enable top DCM control <<<<<
7121 13:42:12.407045 Enable DLL master slave shuffle
7122 13:42:12.410783 ==============================================================
7123 13:42:12.414157 Gating Mode config
7124 13:42:12.420542 ==============================================================
7125 13:42:12.420629 Config description:
7126 13:42:12.430603 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7127 13:42:12.436839 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7128 13:42:12.440573 SELPH_MODE 0: By rank 1: By Phase
7129 13:42:12.447116 ==============================================================
7130 13:42:12.450260 GAT_TRACK_EN = 1
7131 13:42:12.453381 RX_GATING_MODE = 2
7132 13:42:12.456627 RX_GATING_TRACK_MODE = 2
7133 13:42:12.459781 SELPH_MODE = 1
7134 13:42:12.463752 PICG_EARLY_EN = 1
7135 13:42:12.466773 VALID_LAT_VALUE = 1
7136 13:42:12.469774 ==============================================================
7137 13:42:12.472924 Enter into Gating configuration >>>>
7138 13:42:12.476585 Exit from Gating configuration <<<<
7139 13:42:12.480152 Enter into DVFS_PRE_config >>>>>
7140 13:42:12.492773 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7141 13:42:12.496733 Exit from DVFS_PRE_config <<<<<
7142 13:42:12.500007 Enter into PICG configuration >>>>
7143 13:42:12.500094 Exit from PICG configuration <<<<
7144 13:42:12.503081 [RX_INPUT] configuration >>>>>
7145 13:42:12.506369 [RX_INPUT] configuration <<<<<
7146 13:42:12.513040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7147 13:42:12.516261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7148 13:42:12.522597 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7149 13:42:12.529370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7150 13:42:12.535854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7151 13:42:12.542821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7152 13:42:12.545948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7153 13:42:12.548945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7154 13:42:12.555543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7155 13:42:12.559232 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7156 13:42:12.562419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7157 13:42:12.565646 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7158 13:42:12.568764 ===================================
7159 13:42:12.572072 LPDDR4 DRAM CONFIGURATION
7160 13:42:12.575905 ===================================
7161 13:42:12.578992 EX_ROW_EN[0] = 0x0
7162 13:42:12.579075 EX_ROW_EN[1] = 0x0
7163 13:42:12.581927 LP4Y_EN = 0x0
7164 13:42:12.582011 WORK_FSP = 0x1
7165 13:42:12.585787 WL = 0x5
7166 13:42:12.585871 RL = 0x5
7167 13:42:12.588850 BL = 0x2
7168 13:42:12.588931 RPST = 0x0
7169 13:42:12.592278 RD_PRE = 0x0
7170 13:42:12.592361 WR_PRE = 0x1
7171 13:42:12.595612 WR_PST = 0x1
7172 13:42:12.598470 DBI_WR = 0x0
7173 13:42:12.598574 DBI_RD = 0x0
7174 13:42:12.601722 OTF = 0x1
7175 13:42:12.604928 ===================================
7176 13:42:12.608678 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7177 13:42:12.611976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7178 13:42:12.615134 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 13:42:12.618270 ===================================
7180 13:42:12.621702 LPDDR4 DRAM CONFIGURATION
7181 13:42:12.624732 ===================================
7182 13:42:12.628347 EX_ROW_EN[0] = 0x10
7183 13:42:12.628429 EX_ROW_EN[1] = 0x0
7184 13:42:12.631278 LP4Y_EN = 0x0
7185 13:42:12.631361 WORK_FSP = 0x1
7186 13:42:12.635067 WL = 0x5
7187 13:42:12.635148 RL = 0x5
7188 13:42:12.638496 BL = 0x2
7189 13:42:12.638579 RPST = 0x0
7190 13:42:12.641103 RD_PRE = 0x0
7191 13:42:12.645001 WR_PRE = 0x1
7192 13:42:12.645083 WR_PST = 0x1
7193 13:42:12.648016 DBI_WR = 0x0
7194 13:42:12.648175 DBI_RD = 0x0
7195 13:42:12.651051 OTF = 0x1
7196 13:42:12.654332 ===================================
7197 13:42:12.661043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7198 13:42:12.661148 ==
7199 13:42:12.664312 Dram Type= 6, Freq= 0, CH_0, rank 0
7200 13:42:12.667484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7201 13:42:12.667606 ==
7202 13:42:12.670738 [Duty_Offset_Calibration]
7203 13:42:12.670820 B0:2 B1:0 CA:4
7204 13:42:12.670885
7205 13:42:12.673942 [DutyScan_Calibration_Flow] k_type=0
7206 13:42:12.683559
7207 13:42:12.683641 ==CLK 0==
7208 13:42:12.686752 Final CLK duty delay cell = -4
7209 13:42:12.690412 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7210 13:42:12.693639 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7211 13:42:12.696688 [-4] AVG Duty = 4906%(X100)
7212 13:42:12.696771
7213 13:42:12.700237 CH0 CLK Duty spec in!! Max-Min= 187%
7214 13:42:12.703451 [DutyScan_Calibration_Flow] ====Done====
7215 13:42:12.703550
7216 13:42:12.706555 [DutyScan_Calibration_Flow] k_type=1
7217 13:42:12.723737
7218 13:42:12.723838 ==DQS 0 ==
7219 13:42:12.727338 Final DQS duty delay cell = 0
7220 13:42:12.730353 [0] MAX Duty = 5218%(X100), DQS PI = 38
7221 13:42:12.733503 [0] MIN Duty = 5062%(X100), DQS PI = 14
7222 13:42:12.736999 [0] AVG Duty = 5140%(X100)
7223 13:42:12.737082
7224 13:42:12.737147 ==DQS 1 ==
7225 13:42:12.740139 Final DQS duty delay cell = 0
7226 13:42:12.743530 [0] MAX Duty = 5156%(X100), DQS PI = 2
7227 13:42:12.746756 [0] MIN Duty = 4969%(X100), DQS PI = 10
7228 13:42:12.749948 [0] AVG Duty = 5062%(X100)
7229 13:42:12.750030
7230 13:42:12.753093 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7231 13:42:12.753200
7232 13:42:12.756875 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7233 13:42:12.760040 [DutyScan_Calibration_Flow] ====Done====
7234 13:42:12.760123
7235 13:42:12.763324 [DutyScan_Calibration_Flow] k_type=3
7236 13:42:12.780967
7237 13:42:12.781054 ==DQM 0 ==
7238 13:42:12.784283 Final DQM duty delay cell = 0
7239 13:42:12.787957 [0] MAX Duty = 5124%(X100), DQS PI = 22
7240 13:42:12.791199 [0] MIN Duty = 4844%(X100), DQS PI = 56
7241 13:42:12.794298 [0] AVG Duty = 4984%(X100)
7242 13:42:12.794381
7243 13:42:12.794466 ==DQM 1 ==
7244 13:42:12.797618 Final DQM duty delay cell = 0
7245 13:42:12.800811 [0] MAX Duty = 4969%(X100), DQS PI = 0
7246 13:42:12.803880 [0] MIN Duty = 4844%(X100), DQS PI = 14
7247 13:42:12.807312 [0] AVG Duty = 4906%(X100)
7248 13:42:12.807427
7249 13:42:12.810557 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7250 13:42:12.810664
7251 13:42:12.813702 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7252 13:42:12.817236 [DutyScan_Calibration_Flow] ====Done====
7253 13:42:12.817356
7254 13:42:12.820791 [DutyScan_Calibration_Flow] k_type=2
7255 13:42:12.838290
7256 13:42:12.838381 ==DQ 0 ==
7257 13:42:12.841188 Final DQ duty delay cell = 0
7258 13:42:12.844696 [0] MAX Duty = 5156%(X100), DQS PI = 22
7259 13:42:12.847698 [0] MIN Duty = 4938%(X100), DQS PI = 12
7260 13:42:12.851022 [0] AVG Duty = 5047%(X100)
7261 13:42:12.851127
7262 13:42:12.851218 ==DQ 1 ==
7263 13:42:12.854871 Final DQ duty delay cell = 0
7264 13:42:12.858078 [0] MAX Duty = 5187%(X100), DQS PI = 2
7265 13:42:12.861066 [0] MIN Duty = 4938%(X100), DQS PI = 12
7266 13:42:12.864277 [0] AVG Duty = 5062%(X100)
7267 13:42:12.864383
7268 13:42:12.867527 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7269 13:42:12.867600
7270 13:42:12.870616 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7271 13:42:12.873887 [DutyScan_Calibration_Flow] ====Done====
7272 13:42:12.873961 ==
7273 13:42:12.877153 Dram Type= 6, Freq= 0, CH_1, rank 0
7274 13:42:12.880375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 13:42:12.880447 ==
7276 13:42:12.883609 [Duty_Offset_Calibration]
7277 13:42:12.883679 B0:0 B1:-1 CA:3
7278 13:42:12.883762
7279 13:42:12.887508 [DutyScan_Calibration_Flow] k_type=0
7280 13:42:12.897616
7281 13:42:12.897707 ==CLK 0==
7282 13:42:12.900871 Final CLK duty delay cell = -4
7283 13:42:12.903985 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7284 13:42:12.907256 [-4] MIN Duty = 4813%(X100), DQS PI = 40
7285 13:42:12.910839 [-4] AVG Duty = 4906%(X100)
7286 13:42:12.910930
7287 13:42:12.913873 CH1 CLK Duty spec in!! Max-Min= 187%
7288 13:42:12.917528 [DutyScan_Calibration_Flow] ====Done====
7289 13:42:12.917639
7290 13:42:12.920733 [DutyScan_Calibration_Flow] k_type=1
7291 13:42:12.936899
7292 13:42:12.937003 ==DQS 0 ==
7293 13:42:12.939949 Final DQS duty delay cell = 0
7294 13:42:12.943094 [0] MAX Duty = 5218%(X100), DQS PI = 28
7295 13:42:12.946713 [0] MIN Duty = 4907%(X100), DQS PI = 58
7296 13:42:12.949835 [0] AVG Duty = 5062%(X100)
7297 13:42:12.949907
7298 13:42:12.949967 ==DQS 1 ==
7299 13:42:12.952976 Final DQS duty delay cell = -4
7300 13:42:12.956211 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7301 13:42:12.959494 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7302 13:42:12.962755 [-4] AVG Duty = 4906%(X100)
7303 13:42:12.962831
7304 13:42:12.965796 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7305 13:42:12.965896
7306 13:42:12.969676 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7307 13:42:12.972904 [DutyScan_Calibration_Flow] ====Done====
7308 13:42:12.973003
7309 13:42:12.975936 [DutyScan_Calibration_Flow] k_type=3
7310 13:42:12.993845
7311 13:42:12.993928 ==DQM 0 ==
7312 13:42:12.997575 Final DQM duty delay cell = 0
7313 13:42:13.000672 [0] MAX Duty = 5031%(X100), DQS PI = 30
7314 13:42:13.003951 [0] MIN Duty = 4782%(X100), DQS PI = 38
7315 13:42:13.007119 [0] AVG Duty = 4906%(X100)
7316 13:42:13.007200
7317 13:42:13.007261 ==DQM 1 ==
7318 13:42:13.010961 Final DQM duty delay cell = 0
7319 13:42:13.013511 [0] MAX Duty = 4969%(X100), DQS PI = 30
7320 13:42:13.017138 [0] MIN Duty = 4782%(X100), DQS PI = 60
7321 13:42:13.020122 [0] AVG Duty = 4875%(X100)
7322 13:42:13.020219
7323 13:42:13.023951 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7324 13:42:13.024061
7325 13:42:13.027129 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7326 13:42:13.030346 [DutyScan_Calibration_Flow] ====Done====
7327 13:42:13.030421
7328 13:42:13.033373 [DutyScan_Calibration_Flow] k_type=2
7329 13:42:13.050520
7330 13:42:13.050606 ==DQ 0 ==
7331 13:42:13.053580 Final DQ duty delay cell = -4
7332 13:42:13.056573 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7333 13:42:13.059675 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7334 13:42:13.063296 [-4] AVG Duty = 4891%(X100)
7335 13:42:13.063378
7336 13:42:13.063444 ==DQ 1 ==
7337 13:42:13.066728 Final DQ duty delay cell = 0
7338 13:42:13.069816 [0] MAX Duty = 5031%(X100), DQS PI = 30
7339 13:42:13.073110 [0] MIN Duty = 4875%(X100), DQS PI = 54
7340 13:42:13.076178 [0] AVG Duty = 4953%(X100)
7341 13:42:13.076261
7342 13:42:13.079938 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7343 13:42:13.080053
7344 13:42:13.083188 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7345 13:42:13.086321 [DutyScan_Calibration_Flow] ====Done====
7346 13:42:13.089416 nWR fixed to 30
7347 13:42:13.092733 [ModeRegInit_LP4] CH0 RK0
7348 13:42:13.092833 [ModeRegInit_LP4] CH0 RK1
7349 13:42:13.096364 [ModeRegInit_LP4] CH1 RK0
7350 13:42:13.099457 [ModeRegInit_LP4] CH1 RK1
7351 13:42:13.099558 match AC timing 5
7352 13:42:13.106267 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7353 13:42:13.109611 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7354 13:42:13.112607 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7355 13:42:13.119206 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7356 13:42:13.122296 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7357 13:42:13.125951 [MiockJmeterHQA]
7358 13:42:13.126032
7359 13:42:13.128989 [DramcMiockJmeter] u1RxGatingPI = 0
7360 13:42:13.129070 0 : 4254, 4029
7361 13:42:13.129135 4 : 4363, 4137
7362 13:42:13.132329 8 : 4252, 4027
7363 13:42:13.132412 12 : 4252, 4026
7364 13:42:13.135568 16 : 4252, 4029
7365 13:42:13.135650 20 : 4253, 4027
7366 13:42:13.138667 24 : 4363, 4137
7367 13:42:13.138749 28 : 4360, 4138
7368 13:42:13.142639 32 : 4361, 4137
7369 13:42:13.142722 36 : 4255, 4029
7370 13:42:13.142787 40 : 4252, 4029
7371 13:42:13.145680 44 : 4361, 4137
7372 13:42:13.145762 48 : 4250, 4027
7373 13:42:13.148591 52 : 4363, 4140
7374 13:42:13.148674 56 : 4255, 4029
7375 13:42:13.152188 60 : 4250, 4026
7376 13:42:13.152271 64 : 4253, 4026
7377 13:42:13.155536 68 : 4252, 4030
7378 13:42:13.155620 72 : 4361, 4137
7379 13:42:13.155689 76 : 4250, 4027
7380 13:42:13.158851 80 : 4360, 4137
7381 13:42:13.158933 84 : 4363, 4140
7382 13:42:13.161897 88 : 4252, 4029
7383 13:42:13.161981 92 : 4252, 4029
7384 13:42:13.165520 96 : 4361, 2364
7385 13:42:13.165603 100 : 4250, 0
7386 13:42:13.165668 104 : 4250, 0
7387 13:42:13.168910 108 : 4361, 0
7388 13:42:13.168993 112 : 4250, 0
7389 13:42:13.172072 116 : 4250, 0
7390 13:42:13.172155 120 : 4250, 0
7391 13:42:13.172221 124 : 4363, 0
7392 13:42:13.175236 128 : 4250, 0
7393 13:42:13.175320 132 : 4250, 0
7394 13:42:13.178667 136 : 4366, 0
7395 13:42:13.178768 140 : 4249, 0
7396 13:42:13.178847 144 : 4250, 0
7397 13:42:13.182317 148 : 4250, 0
7398 13:42:13.182400 152 : 4250, 0
7399 13:42:13.185455 156 : 4363, 0
7400 13:42:13.185538 160 : 4366, 0
7401 13:42:13.185603 164 : 4250, 0
7402 13:42:13.188686 168 : 4249, 0
7403 13:42:13.188769 172 : 4361, 0
7404 13:42:13.188835 176 : 4360, 0
7405 13:42:13.191678 180 : 4250, 0
7406 13:42:13.191760 184 : 4250, 0
7407 13:42:13.194856 188 : 4366, 0
7408 13:42:13.194940 192 : 4249, 0
7409 13:42:13.195004 196 : 4250, 0
7410 13:42:13.198646 200 : 4250, 0
7411 13:42:13.198729 204 : 4249, 0
7412 13:42:13.201756 208 : 4360, 0
7413 13:42:13.201840 212 : 4365, 0
7414 13:42:13.201905 216 : 4248, 0
7415 13:42:13.205068 220 : 4250, 1019
7416 13:42:13.205151 224 : 4250, 4025
7417 13:42:13.208160 228 : 4250, 4026
7418 13:42:13.208247 232 : 4361, 4137
7419 13:42:13.211216 236 : 4363, 4137
7420 13:42:13.211301 240 : 4250, 4027
7421 13:42:13.214968 244 : 4250, 4027
7422 13:42:13.215057 248 : 4361, 4137
7423 13:42:13.218135 252 : 4361, 4137
7424 13:42:13.218219 256 : 4250, 4027
7425 13:42:13.221305 260 : 4363, 4140
7426 13:42:13.221449 264 : 4250, 4026
7427 13:42:13.224577 268 : 4250, 4026
7428 13:42:13.224651 272 : 4250, 4027
7429 13:42:13.224791 276 : 4252, 4030
7430 13:42:13.227688 280 : 4250, 4026
7431 13:42:13.227810 284 : 4361, 4137
7432 13:42:13.231588 288 : 4250, 4027
7433 13:42:13.231725 292 : 4250, 4027
7434 13:42:13.234398 296 : 4250, 4027
7435 13:42:13.234485 300 : 4361, 4137
7436 13:42:13.237450 304 : 4361, 4137
7437 13:42:13.237553 308 : 4250, 4027
7438 13:42:13.241652 312 : 4363, 4140
7439 13:42:13.241756 316 : 4250, 4026
7440 13:42:13.244648 320 : 4250, 4026
7441 13:42:13.244753 324 : 4250, 4027
7442 13:42:13.247756 328 : 4252, 4030
7443 13:42:13.247859 332 : 4250, 3748
7444 13:42:13.251023 336 : 4361, 913
7445 13:42:13.251112
7446 13:42:13.251198 MIOCK jitter meter ch=0
7447 13:42:13.251280
7448 13:42:13.254454 1T = (336-100) = 236 dly cells
7449 13:42:13.260366 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7450 13:42:13.260456 ==
7451 13:42:13.263964 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 13:42:13.267251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7453 13:42:13.267341 ==
7454 13:42:13.273866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7455 13:42:13.276977 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7456 13:42:13.280156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7457 13:42:13.287162 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7458 13:42:13.297220 [CA 0] Center 44 (14~74) winsize 61
7459 13:42:13.299872 [CA 1] Center 43 (13~74) winsize 62
7460 13:42:13.303590 [CA 2] Center 38 (9~68) winsize 60
7461 13:42:13.306747 [CA 3] Center 38 (9~68) winsize 60
7462 13:42:13.310438 [CA 4] Center 36 (7~66) winsize 60
7463 13:42:13.313213 [CA 5] Center 36 (6~66) winsize 61
7464 13:42:13.313342
7465 13:42:13.316679 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7466 13:42:13.316795
7467 13:42:13.320236 [CATrainingPosCal] consider 1 rank data
7468 13:42:13.323601 u2DelayCellTimex100 = 275/100 ps
7469 13:42:13.329930 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7470 13:42:13.333070 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7471 13:42:13.336232 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7472 13:42:13.339766 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7473 13:42:13.343434 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7474 13:42:13.346617 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7475 13:42:13.346699
7476 13:42:13.349762 CA PerBit enable=1, Macro0, CA PI delay=36
7477 13:42:13.349844
7478 13:42:13.352929 [CBTSetCACLKResult] CA Dly = 36
7479 13:42:13.356188 CS Dly: 10 (0~41)
7480 13:42:13.359415 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7481 13:42:13.362571 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7482 13:42:13.362652 ==
7483 13:42:13.366187 Dram Type= 6, Freq= 0, CH_0, rank 1
7484 13:42:13.372444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 13:42:13.372527 ==
7486 13:42:13.375892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 13:42:13.382523 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 13:42:13.386004 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 13:42:13.392433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 13:42:13.400188 [CA 0] Center 44 (14~75) winsize 62
7491 13:42:13.403274 [CA 1] Center 44 (14~74) winsize 61
7492 13:42:13.406984 [CA 2] Center 39 (10~69) winsize 60
7493 13:42:13.409995 [CA 3] Center 39 (10~68) winsize 59
7494 13:42:13.413454 [CA 4] Center 37 (7~67) winsize 61
7495 13:42:13.416866 [CA 5] Center 36 (7~66) winsize 60
7496 13:42:13.416949
7497 13:42:13.419711 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 13:42:13.419794
7499 13:42:13.426685 [CATrainingPosCal] consider 2 rank data
7500 13:42:13.426773 u2DelayCellTimex100 = 275/100 ps
7501 13:42:13.432894 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7502 13:42:13.436088 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7503 13:42:13.439957 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7504 13:42:13.443130 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7505 13:42:13.446311 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7506 13:42:13.449312 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7507 13:42:13.449395
7508 13:42:13.452901 CA PerBit enable=1, Macro0, CA PI delay=36
7509 13:42:13.456110
7510 13:42:13.456192 [CBTSetCACLKResult] CA Dly = 36
7511 13:42:13.459470 CS Dly: 11 (0~43)
7512 13:42:13.462645 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 13:42:13.465841 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 13:42:13.469002
7515 13:42:13.472807 ----->DramcWriteLeveling(PI) begin...
7516 13:42:13.472895 ==
7517 13:42:13.476016 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 13:42:13.479062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 13:42:13.479145 ==
7520 13:42:13.482589 Write leveling (Byte 0): 36 => 36
7521 13:42:13.485770 Write leveling (Byte 1): 24 => 24
7522 13:42:13.488650 DramcWriteLeveling(PI) end<-----
7523 13:42:13.488733
7524 13:42:13.488797 ==
7525 13:42:13.492302 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 13:42:13.495483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 13:42:13.495565 ==
7528 13:42:13.498750 [Gating] SW mode calibration
7529 13:42:13.505043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7530 13:42:13.511656 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7531 13:42:13.514946 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7532 13:42:13.518640 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 13:42:13.525020 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7534 13:42:13.528109 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7535 13:42:13.531993 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7536 13:42:13.538041 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7537 13:42:13.541244 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7538 13:42:13.545094 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 13:42:13.551291 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 13:42:13.554466 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7541 13:42:13.561323 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
7542 13:42:13.564705 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7543 13:42:13.568155 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7544 13:42:13.571060 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7545 13:42:13.577514 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7546 13:42:13.581304 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 13:42:13.584562 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 13:42:13.590810 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 13:42:13.594546 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7550 13:42:13.597486 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7551 13:42:13.603929 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7552 13:42:13.607336 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
7553 13:42:13.610533 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7554 13:42:13.617033 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 13:42:13.620893 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 13:42:13.623895 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 13:42:13.630405 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 13:42:13.633496 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7559 13:42:13.636627 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7560 13:42:13.643846 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7561 13:42:13.646669 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7562 13:42:13.650128 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 13:42:13.656691 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 13:42:13.660274 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 13:42:13.663286 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 13:42:13.669990 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 13:42:13.673401 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 13:42:13.676792 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 13:42:13.682983 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 13:42:13.686237 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 13:42:13.689908 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 13:42:13.696696 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 13:42:13.699267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7574 13:42:13.703052 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7575 13:42:13.709651 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7576 13:42:13.712701 Total UI for P1: 0, mck2ui 16
7577 13:42:13.716013 best dqsien dly found for B0: ( 1, 9, 10)
7578 13:42:13.719038 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7579 13:42:13.722389 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 13:42:13.726097 Total UI for P1: 0, mck2ui 16
7581 13:42:13.729107 best dqsien dly found for B1: ( 1, 9, 20)
7582 13:42:13.735784 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7583 13:42:13.738931 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7584 13:42:13.739014
7585 13:42:13.742093 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7586 13:42:13.745793 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7587 13:42:13.749086 [Gating] SW calibration Done
7588 13:42:13.749168 ==
7589 13:42:13.752260 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 13:42:13.755528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 13:42:13.755611 ==
7592 13:42:13.758600 RX Vref Scan: 0
7593 13:42:13.758683
7594 13:42:13.758747 RX Vref 0 -> 0, step: 1
7595 13:42:13.758807
7596 13:42:13.762369 RX Delay 0 -> 252, step: 8
7597 13:42:13.765015 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7598 13:42:13.771855 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7599 13:42:13.775463 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7600 13:42:13.778626 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7601 13:42:13.781682 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7602 13:42:13.785165 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7603 13:42:13.791847 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7604 13:42:13.795202 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7605 13:42:13.798265 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7606 13:42:13.801840 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7607 13:42:13.804917 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7608 13:42:13.811458 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7609 13:42:13.815118 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7610 13:42:13.818019 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7611 13:42:13.821756 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7612 13:42:13.828106 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7613 13:42:13.828189 ==
7614 13:42:13.831175 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 13:42:13.834345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 13:42:13.834429 ==
7617 13:42:13.834494 DQS Delay:
7618 13:42:13.838202 DQS0 = 0, DQS1 = 0
7619 13:42:13.838284 DQM Delay:
7620 13:42:13.841304 DQM0 = 131, DQM1 = 127
7621 13:42:13.841402 DQ Delay:
7622 13:42:13.844709 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7623 13:42:13.848004 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7624 13:42:13.851169 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7625 13:42:13.854270 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7626 13:42:13.854353
7627 13:42:13.854417
7628 13:42:13.857527 ==
7629 13:42:13.861238 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 13:42:13.864423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 13:42:13.864506 ==
7632 13:42:13.864572
7633 13:42:13.864633
7634 13:42:13.867627 TX Vref Scan disable
7635 13:42:13.867713 == TX Byte 0 ==
7636 13:42:13.874582 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7637 13:42:13.877384 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7638 13:42:13.877469 == TX Byte 1 ==
7639 13:42:13.883678 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7640 13:42:13.886996 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7641 13:42:13.887083 ==
7642 13:42:13.890831 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 13:42:13.893990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 13:42:13.894073 ==
7645 13:42:13.908483
7646 13:42:13.911990 TX Vref early break, caculate TX vref
7647 13:42:13.915242 TX Vref=16, minBit 1, minWin=22, winSum=367
7648 13:42:13.918546 TX Vref=18, minBit 1, minWin=22, winSum=378
7649 13:42:13.922195 TX Vref=20, minBit 1, minWin=23, winSum=385
7650 13:42:13.925167 TX Vref=22, minBit 1, minWin=24, winSum=400
7651 13:42:13.928872 TX Vref=24, minBit 8, minWin=24, winSum=406
7652 13:42:13.935086 TX Vref=26, minBit 1, minWin=25, winSum=416
7653 13:42:13.938273 TX Vref=28, minBit 0, minWin=25, winSum=416
7654 13:42:13.941444 TX Vref=30, minBit 2, minWin=25, winSum=412
7655 13:42:13.944684 TX Vref=32, minBit 4, minWin=24, winSum=408
7656 13:42:13.947983 TX Vref=34, minBit 7, minWin=23, winSum=393
7657 13:42:13.954547 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
7658 13:42:13.954631
7659 13:42:13.957679 Final TX Range 0 Vref 26
7660 13:42:13.957762
7661 13:42:13.957826 ==
7662 13:42:13.961731 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 13:42:13.965012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 13:42:13.965095 ==
7665 13:42:13.965159
7666 13:42:13.965219
7667 13:42:13.967663 TX Vref Scan disable
7668 13:42:13.974726 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7669 13:42:13.974809 == TX Byte 0 ==
7670 13:42:13.977807 u2DelayCellOfst[0]=10 cells (3 PI)
7671 13:42:13.981522 u2DelayCellOfst[1]=17 cells (5 PI)
7672 13:42:13.984483 u2DelayCellOfst[2]=14 cells (4 PI)
7673 13:42:13.987770 u2DelayCellOfst[3]=14 cells (4 PI)
7674 13:42:13.990983 u2DelayCellOfst[4]=7 cells (2 PI)
7675 13:42:13.994142 u2DelayCellOfst[5]=0 cells (0 PI)
7676 13:42:13.997305 u2DelayCellOfst[6]=17 cells (5 PI)
7677 13:42:14.001057 u2DelayCellOfst[7]=17 cells (5 PI)
7678 13:42:14.004277 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7679 13:42:14.007479 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7680 13:42:14.011059 == TX Byte 1 ==
7681 13:42:14.014232 u2DelayCellOfst[8]=0 cells (0 PI)
7682 13:42:14.017404 u2DelayCellOfst[9]=0 cells (0 PI)
7683 13:42:14.020786 u2DelayCellOfst[10]=3 cells (1 PI)
7684 13:42:14.020869 u2DelayCellOfst[11]=0 cells (0 PI)
7685 13:42:14.023987 u2DelayCellOfst[12]=7 cells (2 PI)
7686 13:42:14.027390 u2DelayCellOfst[13]=7 cells (2 PI)
7687 13:42:14.030671 u2DelayCellOfst[14]=14 cells (4 PI)
7688 13:42:14.033992 u2DelayCellOfst[15]=7 cells (2 PI)
7689 13:42:14.040287 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7690 13:42:14.043588 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7691 13:42:14.043700 DramC Write-DBI on
7692 13:42:14.043815 ==
7693 13:42:14.047173 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 13:42:14.053543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 13:42:14.053626 ==
7696 13:42:14.053691
7697 13:42:14.053751
7698 13:42:14.056984 TX Vref Scan disable
7699 13:42:14.057066 == TX Byte 0 ==
7700 13:42:14.063516 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7701 13:42:14.063599 == TX Byte 1 ==
7702 13:42:14.066712 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7703 13:42:14.069963 DramC Write-DBI off
7704 13:42:14.070044
7705 13:42:14.070117 [DATLAT]
7706 13:42:14.073072 Freq=1600, CH0 RK0
7707 13:42:14.073154
7708 13:42:14.073219 DATLAT Default: 0xf
7709 13:42:14.076260 0, 0xFFFF, sum = 0
7710 13:42:14.076344 1, 0xFFFF, sum = 0
7711 13:42:14.080046 2, 0xFFFF, sum = 0
7712 13:42:14.080130 3, 0xFFFF, sum = 0
7713 13:42:14.083264 4, 0xFFFF, sum = 0
7714 13:42:14.086667 5, 0xFFFF, sum = 0
7715 13:42:14.086752 6, 0xFFFF, sum = 0
7716 13:42:14.089498 7, 0xFFFF, sum = 0
7717 13:42:14.089582 8, 0xFFFF, sum = 0
7718 13:42:14.092660 9, 0xFFFF, sum = 0
7719 13:42:14.092744 10, 0xFFFF, sum = 0
7720 13:42:14.096449 11, 0xFFFF, sum = 0
7721 13:42:14.096533 12, 0xFFFF, sum = 0
7722 13:42:14.099674 13, 0xFFFF, sum = 0
7723 13:42:14.099758 14, 0x0, sum = 1
7724 13:42:14.102501 15, 0x0, sum = 2
7725 13:42:14.102584 16, 0x0, sum = 3
7726 13:42:14.105771 17, 0x0, sum = 4
7727 13:42:14.105854 best_step = 15
7728 13:42:14.105918
7729 13:42:14.105978 ==
7730 13:42:14.109002 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 13:42:14.115704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 13:42:14.115787 ==
7733 13:42:14.115853 RX Vref Scan: 1
7734 13:42:14.115918
7735 13:42:14.119359 Set Vref Range= 24 -> 127
7736 13:42:14.119440
7737 13:42:14.122699 RX Vref 24 -> 127, step: 1
7738 13:42:14.122781
7739 13:42:14.122845 RX Delay 11 -> 252, step: 4
7740 13:42:14.125707
7741 13:42:14.125790 Set Vref, RX VrefLevel [Byte0]: 24
7742 13:42:14.128956 [Byte1]: 24
7743 13:42:14.133374
7744 13:42:14.133456 Set Vref, RX VrefLevel [Byte0]: 25
7745 13:42:14.136532 [Byte1]: 25
7746 13:42:14.140743
7747 13:42:14.140825 Set Vref, RX VrefLevel [Byte0]: 26
7748 13:42:14.143985 [Byte1]: 26
7749 13:42:14.148265
7750 13:42:14.148346 Set Vref, RX VrefLevel [Byte0]: 27
7751 13:42:14.152026 [Byte1]: 27
7752 13:42:14.155873
7753 13:42:14.155955 Set Vref, RX VrefLevel [Byte0]: 28
7754 13:42:14.159250 [Byte1]: 28
7755 13:42:14.163889
7756 13:42:14.163970 Set Vref, RX VrefLevel [Byte0]: 29
7757 13:42:14.167204 [Byte1]: 29
7758 13:42:14.170935
7759 13:42:14.171017 Set Vref, RX VrefLevel [Byte0]: 30
7760 13:42:14.174360 [Byte1]: 30
7761 13:42:14.178755
7762 13:42:14.178837 Set Vref, RX VrefLevel [Byte0]: 31
7763 13:42:14.181903 [Byte1]: 31
7764 13:42:14.186449
7765 13:42:14.186526 Set Vref, RX VrefLevel [Byte0]: 32
7766 13:42:14.189776 [Byte1]: 32
7767 13:42:14.193897
7768 13:42:14.193979 Set Vref, RX VrefLevel [Byte0]: 33
7769 13:42:14.197149 [Byte1]: 33
7770 13:42:14.201556
7771 13:42:14.201637 Set Vref, RX VrefLevel [Byte0]: 34
7772 13:42:14.204610 [Byte1]: 34
7773 13:42:14.209382
7774 13:42:14.209464 Set Vref, RX VrefLevel [Byte0]: 35
7775 13:42:14.212577 [Byte1]: 35
7776 13:42:14.217122
7777 13:42:14.217204 Set Vref, RX VrefLevel [Byte0]: 36
7778 13:42:14.220283 [Byte1]: 36
7779 13:42:14.224699
7780 13:42:14.224781 Set Vref, RX VrefLevel [Byte0]: 37
7781 13:42:14.227816 [Byte1]: 37
7782 13:42:14.232034
7783 13:42:14.232116 Set Vref, RX VrefLevel [Byte0]: 38
7784 13:42:14.235176 [Byte1]: 38
7785 13:42:14.239594
7786 13:42:14.239676 Set Vref, RX VrefLevel [Byte0]: 39
7787 13:42:14.243164 [Byte1]: 39
7788 13:42:14.247650
7789 13:42:14.247732 Set Vref, RX VrefLevel [Byte0]: 40
7790 13:42:14.250305 [Byte1]: 40
7791 13:42:14.254889
7792 13:42:14.254971 Set Vref, RX VrefLevel [Byte0]: 41
7793 13:42:14.258126 [Byte1]: 41
7794 13:42:14.262350
7795 13:42:14.262432 Set Vref, RX VrefLevel [Byte0]: 42
7796 13:42:14.266016 [Byte1]: 42
7797 13:42:14.269874
7798 13:42:14.269956 Set Vref, RX VrefLevel [Byte0]: 43
7799 13:42:14.273212 [Byte1]: 43
7800 13:42:14.278157
7801 13:42:14.278243 Set Vref, RX VrefLevel [Byte0]: 44
7802 13:42:14.281419 [Byte1]: 44
7803 13:42:14.285184
7804 13:42:14.285292 Set Vref, RX VrefLevel [Byte0]: 45
7805 13:42:14.288823 [Byte1]: 45
7806 13:42:14.293280
7807 13:42:14.293379 Set Vref, RX VrefLevel [Byte0]: 46
7808 13:42:14.296563 [Byte1]: 46
7809 13:42:14.300835
7810 13:42:14.300918 Set Vref, RX VrefLevel [Byte0]: 47
7811 13:42:14.304145 [Byte1]: 47
7812 13:42:14.307965
7813 13:42:14.308047 Set Vref, RX VrefLevel [Byte0]: 48
7814 13:42:14.311717 [Byte1]: 48
7815 13:42:14.315893
7816 13:42:14.315974 Set Vref, RX VrefLevel [Byte0]: 49
7817 13:42:14.319370 [Byte1]: 49
7818 13:42:14.323197
7819 13:42:14.323292 Set Vref, RX VrefLevel [Byte0]: 50
7820 13:42:14.326534 [Byte1]: 50
7821 13:42:14.330919
7822 13:42:14.331001 Set Vref, RX VrefLevel [Byte0]: 51
7823 13:42:14.334250 [Byte1]: 51
7824 13:42:14.338645
7825 13:42:14.338727 Set Vref, RX VrefLevel [Byte0]: 52
7826 13:42:14.341876 [Byte1]: 52
7827 13:42:14.346129
7828 13:42:14.346211 Set Vref, RX VrefLevel [Byte0]: 53
7829 13:42:14.349698 [Byte1]: 53
7830 13:42:14.354179
7831 13:42:14.354273 Set Vref, RX VrefLevel [Byte0]: 54
7832 13:42:14.356830 [Byte1]: 54
7833 13:42:14.361323
7834 13:42:14.361408 Set Vref, RX VrefLevel [Byte0]: 55
7835 13:42:14.364481 [Byte1]: 55
7836 13:42:14.368888
7837 13:42:14.368973 Set Vref, RX VrefLevel [Byte0]: 56
7838 13:42:14.372570 [Byte1]: 56
7839 13:42:14.376579
7840 13:42:14.376665 Set Vref, RX VrefLevel [Byte0]: 57
7841 13:42:14.380081 [Byte1]: 57
7842 13:42:14.384523
7843 13:42:14.384633 Set Vref, RX VrefLevel [Byte0]: 58
7844 13:42:14.387557 [Byte1]: 58
7845 13:42:14.392039
7846 13:42:14.392122 Set Vref, RX VrefLevel [Byte0]: 59
7847 13:42:14.395107 [Byte1]: 59
7848 13:42:14.399824
7849 13:42:14.399908 Set Vref, RX VrefLevel [Byte0]: 60
7850 13:42:14.402819 [Byte1]: 60
7851 13:42:14.407445
7852 13:42:14.407530 Set Vref, RX VrefLevel [Byte0]: 61
7853 13:42:14.410635 [Byte1]: 61
7854 13:42:14.414539
7855 13:42:14.414623 Set Vref, RX VrefLevel [Byte0]: 62
7856 13:42:14.418345 [Byte1]: 62
7857 13:42:14.422649
7858 13:42:14.422734 Set Vref, RX VrefLevel [Byte0]: 63
7859 13:42:14.425581 [Byte1]: 63
7860 13:42:14.429828
7861 13:42:14.429915 Set Vref, RX VrefLevel [Byte0]: 64
7862 13:42:14.433000 [Byte1]: 64
7863 13:42:14.437698
7864 13:42:14.437811 Set Vref, RX VrefLevel [Byte0]: 65
7865 13:42:14.440744 [Byte1]: 65
7866 13:42:14.445218
7867 13:42:14.445341 Set Vref, RX VrefLevel [Byte0]: 66
7868 13:42:14.448389 [Byte1]: 66
7869 13:42:14.452709
7870 13:42:14.452793 Set Vref, RX VrefLevel [Byte0]: 67
7871 13:42:14.459361 [Byte1]: 67
7872 13:42:14.459447
7873 13:42:14.462741 Set Vref, RX VrefLevel [Byte0]: 68
7874 13:42:14.465882 [Byte1]: 68
7875 13:42:14.465966
7876 13:42:14.469024 Set Vref, RX VrefLevel [Byte0]: 69
7877 13:42:14.472169 [Byte1]: 69
7878 13:42:14.476013
7879 13:42:14.476097 Set Vref, RX VrefLevel [Byte0]: 70
7880 13:42:14.479220 [Byte1]: 70
7881 13:42:14.483098
7882 13:42:14.483182 Set Vref, RX VrefLevel [Byte0]: 71
7883 13:42:14.486367 [Byte1]: 71
7884 13:42:14.491107
7885 13:42:14.491204 Set Vref, RX VrefLevel [Byte0]: 72
7886 13:42:14.494096 [Byte1]: 72
7887 13:42:14.498321
7888 13:42:14.498403 Set Vref, RX VrefLevel [Byte0]: 73
7889 13:42:14.501486 [Byte1]: 73
7890 13:42:14.506296
7891 13:42:14.506377 Set Vref, RX VrefLevel [Byte0]: 74
7892 13:42:14.509816 [Byte1]: 74
7893 13:42:14.513658
7894 13:42:14.513739 Final RX Vref Byte 0 = 55 to rank0
7895 13:42:14.516919 Final RX Vref Byte 1 = 57 to rank0
7896 13:42:14.520159 Final RX Vref Byte 0 = 55 to rank1
7897 13:42:14.523425 Final RX Vref Byte 1 = 57 to rank1==
7898 13:42:14.527144 Dram Type= 6, Freq= 0, CH_0, rank 0
7899 13:42:14.533500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7900 13:42:14.533582 ==
7901 13:42:14.533648 DQS Delay:
7902 13:42:14.536461 DQS0 = 0, DQS1 = 0
7903 13:42:14.536543 DQM Delay:
7904 13:42:14.540162 DQM0 = 128, DQM1 = 124
7905 13:42:14.540246 DQ Delay:
7906 13:42:14.543477 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7907 13:42:14.546567 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =132
7908 13:42:14.549729 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7909 13:42:14.553184 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =132
7910 13:42:14.553290
7911 13:42:14.553368
7912 13:42:14.553428
7913 13:42:14.556633 [DramC_TX_OE_Calibration] TA2
7914 13:42:14.559686 Original DQ_B0 (3 6) =30, OEN = 27
7915 13:42:14.563435 Original DQ_B1 (3 6) =30, OEN = 27
7916 13:42:14.566518 24, 0x0, End_B0=24 End_B1=24
7917 13:42:14.569825 25, 0x0, End_B0=25 End_B1=25
7918 13:42:14.569908 26, 0x0, End_B0=26 End_B1=26
7919 13:42:14.573064 27, 0x0, End_B0=27 End_B1=27
7920 13:42:14.576230 28, 0x0, End_B0=28 End_B1=28
7921 13:42:14.579520 29, 0x0, End_B0=29 End_B1=29
7922 13:42:14.579603 30, 0x0, End_B0=30 End_B1=30
7923 13:42:14.582806 31, 0x5151, End_B0=30 End_B1=30
7924 13:42:14.586132 Byte0 end_step=30 best_step=27
7925 13:42:14.589236 Byte1 end_step=30 best_step=27
7926 13:42:14.592400 Byte0 TX OE(2T, 0.5T) = (3, 3)
7927 13:42:14.596017 Byte1 TX OE(2T, 0.5T) = (3, 3)
7928 13:42:14.596126
7929 13:42:14.596193
7930 13:42:14.602588 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7931 13:42:14.605692 CH0 RK0: MR19=303, MR18=1916
7932 13:42:14.612563 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7933 13:42:14.612646
7934 13:42:14.615466 ----->DramcWriteLeveling(PI) begin...
7935 13:42:14.615552 ==
7936 13:42:14.618981 Dram Type= 6, Freq= 0, CH_0, rank 1
7937 13:42:14.622265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7938 13:42:14.622348 ==
7939 13:42:14.625532 Write leveling (Byte 0): 35 => 35
7940 13:42:14.628660 Write leveling (Byte 1): 28 => 28
7941 13:42:14.631931 DramcWriteLeveling(PI) end<-----
7942 13:42:14.632012
7943 13:42:14.632077 ==
7944 13:42:14.635238 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 13:42:14.642287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 13:42:14.642370 ==
7947 13:42:14.642435 [Gating] SW mode calibration
7948 13:42:14.651760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7949 13:42:14.655032 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7950 13:42:14.661924 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7951 13:42:14.664785 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7952 13:42:14.668298 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7953 13:42:14.674738 1 4 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7954 13:42:14.678133 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7955 13:42:14.681881 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7956 13:42:14.688524 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7957 13:42:14.691518 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 13:42:14.694678 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7959 13:42:14.701037 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7960 13:42:14.704752 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7961 13:42:14.707857 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
7962 13:42:14.714178 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7963 13:42:14.717819 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7964 13:42:14.720945 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7965 13:42:14.727372 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 13:42:14.730606 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 13:42:14.739054 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7968 13:42:14.740837 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7969 13:42:14.743906 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7970 13:42:14.747876 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7971 13:42:14.753857 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7972 13:42:14.757653 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 13:42:14.760719 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 13:42:14.767165 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 13:42:14.770875 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7976 13:42:14.774003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7977 13:42:14.780503 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7978 13:42:14.783920 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7979 13:42:14.786845 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7980 13:42:14.793441 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 13:42:14.796987 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 13:42:14.800166 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 13:42:14.806789 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 13:42:14.809932 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 13:42:14.813042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 13:42:14.819792 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 13:42:14.822979 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 13:42:14.826086 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 13:42:14.832781 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 13:42:14.836576 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 13:42:14.839660 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 13:42:14.846035 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7993 13:42:14.849801 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7994 13:42:14.852758 Total UI for P1: 0, mck2ui 16
7995 13:42:14.856038 best dqsien dly found for B0: ( 1, 9, 8)
7996 13:42:14.859124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7997 13:42:14.865568 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7998 13:42:14.869319 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 13:42:14.872312 Total UI for P1: 0, mck2ui 16
8000 13:42:14.876134 best dqsien dly found for B1: ( 1, 9, 18)
8001 13:42:14.879246 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8002 13:42:14.882597 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8003 13:42:14.882708
8004 13:42:14.885595 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8005 13:42:14.888828 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8006 13:42:14.892562 [Gating] SW calibration Done
8007 13:42:14.892670 ==
8008 13:42:14.895481 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 13:42:14.899096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 13:42:14.902421 ==
8011 13:42:14.902494 RX Vref Scan: 0
8012 13:42:14.902572
8013 13:42:14.905296 RX Vref 0 -> 0, step: 1
8014 13:42:14.905384
8015 13:42:14.908370 RX Delay 0 -> 252, step: 8
8016 13:42:14.911877 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8017 13:42:14.915449 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8018 13:42:14.918561 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8019 13:42:14.922134 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8020 13:42:14.928293 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8021 13:42:14.931630 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8022 13:42:14.935050 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8023 13:42:14.938084 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8024 13:42:14.941616 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8025 13:42:14.947970 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8026 13:42:14.951700 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8027 13:42:14.954979 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8028 13:42:14.958104 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8029 13:42:14.964448 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8030 13:42:14.968301 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8031 13:42:14.971547 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8032 13:42:14.971633 ==
8033 13:42:14.974740 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 13:42:14.977697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 13:42:14.977781 ==
8036 13:42:14.980874 DQS Delay:
8037 13:42:14.980959 DQS0 = 0, DQS1 = 0
8038 13:42:14.984643 DQM Delay:
8039 13:42:14.984725 DQM0 = 132, DQM1 = 124
8040 13:42:14.984791 DQ Delay:
8041 13:42:14.990928 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8042 13:42:14.994198 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8043 13:42:14.997309 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8044 13:42:15.000885 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8045 13:42:15.001013
8046 13:42:15.001079
8047 13:42:15.001140 ==
8048 13:42:15.004034 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 13:42:15.007157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 13:42:15.007242 ==
8051 13:42:15.007308
8052 13:42:15.007369
8053 13:42:15.011099 TX Vref Scan disable
8054 13:42:15.014042 == TX Byte 0 ==
8055 13:42:15.017101 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8056 13:42:15.020518 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8057 13:42:15.024080 == TX Byte 1 ==
8058 13:42:15.027179 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8059 13:42:15.030585 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8060 13:42:15.030670 ==
8061 13:42:15.033766 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 13:42:15.040100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 13:42:15.040187 ==
8064 13:42:15.052602
8065 13:42:15.056306 TX Vref early break, caculate TX vref
8066 13:42:15.059532 TX Vref=16, minBit 1, minWin=23, winSum=381
8067 13:42:15.062542 TX Vref=18, minBit 0, minWin=24, winSum=389
8068 13:42:15.065855 TX Vref=20, minBit 2, minWin=24, winSum=398
8069 13:42:15.068995 TX Vref=22, minBit 9, minWin=24, winSum=405
8070 13:42:15.072106 TX Vref=24, minBit 2, minWin=25, winSum=415
8071 13:42:15.078621 TX Vref=26, minBit 10, minWin=25, winSum=420
8072 13:42:15.082364 TX Vref=28, minBit 4, minWin=25, winSum=423
8073 13:42:15.085436 TX Vref=30, minBit 1, minWin=25, winSum=416
8074 13:42:15.088501 TX Vref=32, minBit 0, minWin=24, winSum=405
8075 13:42:15.092276 TX Vref=34, minBit 0, minWin=24, winSum=400
8076 13:42:15.098740 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 28
8077 13:42:15.098837
8078 13:42:15.101850 Final TX Range 0 Vref 28
8079 13:42:15.101949
8080 13:42:15.102018 ==
8081 13:42:15.105516 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 13:42:15.108779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 13:42:15.108864 ==
8084 13:42:15.108932
8085 13:42:15.109014
8086 13:42:15.112031 TX Vref Scan disable
8087 13:42:15.118387 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8088 13:42:15.118472 == TX Byte 0 ==
8089 13:42:15.121526 u2DelayCellOfst[0]=10 cells (3 PI)
8090 13:42:15.125183 u2DelayCellOfst[1]=14 cells (4 PI)
8091 13:42:15.128576 u2DelayCellOfst[2]=7 cells (2 PI)
8092 13:42:15.131706 u2DelayCellOfst[3]=10 cells (3 PI)
8093 13:42:15.134801 u2DelayCellOfst[4]=7 cells (2 PI)
8094 13:42:15.138332 u2DelayCellOfst[5]=0 cells (0 PI)
8095 13:42:15.141497 u2DelayCellOfst[6]=14 cells (4 PI)
8096 13:42:15.144770 u2DelayCellOfst[7]=14 cells (4 PI)
8097 13:42:15.148475 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8098 13:42:15.151431 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8099 13:42:15.154927 == TX Byte 1 ==
8100 13:42:15.158402 u2DelayCellOfst[8]=0 cells (0 PI)
8101 13:42:15.161017 u2DelayCellOfst[9]=0 cells (0 PI)
8102 13:42:15.164397 u2DelayCellOfst[10]=3 cells (1 PI)
8103 13:42:15.164481 u2DelayCellOfst[11]=3 cells (1 PI)
8104 13:42:15.168226 u2DelayCellOfst[12]=10 cells (3 PI)
8105 13:42:15.171136 u2DelayCellOfst[13]=10 cells (3 PI)
8106 13:42:15.174828 u2DelayCellOfst[14]=17 cells (5 PI)
8107 13:42:15.178030 u2DelayCellOfst[15]=10 cells (3 PI)
8108 13:42:15.184332 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8109 13:42:15.187452 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8110 13:42:15.187535 DramC Write-DBI on
8111 13:42:15.191278 ==
8112 13:42:15.194409 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 13:42:15.197406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 13:42:15.197490 ==
8115 13:42:15.197555
8116 13:42:15.197614
8117 13:42:15.200740 TX Vref Scan disable
8118 13:42:15.200848 == TX Byte 0 ==
8119 13:42:15.207479 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8120 13:42:15.207573 == TX Byte 1 ==
8121 13:42:15.210672 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8122 13:42:15.213820 DramC Write-DBI off
8123 13:42:15.213893
8124 13:42:15.213969 [DATLAT]
8125 13:42:15.217021 Freq=1600, CH0 RK1
8126 13:42:15.217125
8127 13:42:15.217214 DATLAT Default: 0xf
8128 13:42:15.220649 0, 0xFFFF, sum = 0
8129 13:42:15.220746 1, 0xFFFF, sum = 0
8130 13:42:15.223934 2, 0xFFFF, sum = 0
8131 13:42:15.224006 3, 0xFFFF, sum = 0
8132 13:42:15.227012 4, 0xFFFF, sum = 0
8133 13:42:15.230464 5, 0xFFFF, sum = 0
8134 13:42:15.230544 6, 0xFFFF, sum = 0
8135 13:42:15.233775 7, 0xFFFF, sum = 0
8136 13:42:15.233847 8, 0xFFFF, sum = 0
8137 13:42:15.236791 9, 0xFFFF, sum = 0
8138 13:42:15.236901 10, 0xFFFF, sum = 0
8139 13:42:15.240049 11, 0xFFFF, sum = 0
8140 13:42:15.240149 12, 0xFFFF, sum = 0
8141 13:42:15.243720 13, 0xFFFF, sum = 0
8142 13:42:15.243824 14, 0x0, sum = 1
8143 13:42:15.246932 15, 0x0, sum = 2
8144 13:42:15.247004 16, 0x0, sum = 3
8145 13:42:15.250069 17, 0x0, sum = 4
8146 13:42:15.250138 best_step = 15
8147 13:42:15.250197
8148 13:42:15.250254 ==
8149 13:42:15.253318 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 13:42:15.259936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 13:42:15.260051 ==
8152 13:42:15.260146 RX Vref Scan: 0
8153 13:42:15.260235
8154 13:42:15.263259 RX Vref 0 -> 0, step: 1
8155 13:42:15.263331
8156 13:42:15.266744 RX Delay 11 -> 252, step: 4
8157 13:42:15.269801 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8158 13:42:15.273400 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8159 13:42:15.276256 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8160 13:42:15.283316 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8161 13:42:15.286153 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8162 13:42:15.289562 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8163 13:42:15.293161 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8164 13:42:15.296220 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8165 13:42:15.302719 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8166 13:42:15.305838 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8167 13:42:15.309612 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8168 13:42:15.312553 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8169 13:42:15.319427 iDelay=191, Bit 12, Center 126 (71 ~ 182) 112
8170 13:42:15.322563 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8171 13:42:15.325680 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8172 13:42:15.328848 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8173 13:42:15.328933 ==
8174 13:42:15.332549 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 13:42:15.338759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 13:42:15.338844 ==
8177 13:42:15.338931 DQS Delay:
8178 13:42:15.342097 DQS0 = 0, DQS1 = 0
8179 13:42:15.342183 DQM Delay:
8180 13:42:15.342268 DQM0 = 128, DQM1 = 123
8181 13:42:15.345402 DQ Delay:
8182 13:42:15.349033 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8183 13:42:15.352222 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8184 13:42:15.355451 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8185 13:42:15.358774 DQ12 =126, DQ13 =130, DQ14 =136, DQ15 =130
8186 13:42:15.358859
8187 13:42:15.358943
8188 13:42:15.359022
8189 13:42:15.362203 [DramC_TX_OE_Calibration] TA2
8190 13:42:15.365471 Original DQ_B0 (3 6) =30, OEN = 27
8191 13:42:15.368594 Original DQ_B1 (3 6) =30, OEN = 27
8192 13:42:15.372121 24, 0x0, End_B0=24 End_B1=24
8193 13:42:15.375293 25, 0x0, End_B0=25 End_B1=25
8194 13:42:15.375399 26, 0x0, End_B0=26 End_B1=26
8195 13:42:15.378592 27, 0x0, End_B0=27 End_B1=27
8196 13:42:15.381703 28, 0x0, End_B0=28 End_B1=28
8197 13:42:15.384969 29, 0x0, End_B0=29 End_B1=29
8198 13:42:15.385072 30, 0x0, End_B0=30 End_B1=30
8199 13:42:15.388487 31, 0x4545, End_B0=30 End_B1=30
8200 13:42:15.392103 Byte0 end_step=30 best_step=27
8201 13:42:15.395467 Byte1 end_step=30 best_step=27
8202 13:42:15.398314 Byte0 TX OE(2T, 0.5T) = (3, 3)
8203 13:42:15.401508 Byte1 TX OE(2T, 0.5T) = (3, 3)
8204 13:42:15.401615
8205 13:42:15.401705
8206 13:42:15.408038 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8207 13:42:15.411604 CH0 RK1: MR19=303, MR18=1715
8208 13:42:15.417928 CH0_RK1: MR19=0x303, MR18=0x1715, DQSOSC=398, MR23=63, INC=23, DEC=15
8209 13:42:15.421712 [RxdqsGatingPostProcess] freq 1600
8210 13:42:15.428103 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8211 13:42:15.428207 best DQS0 dly(2T, 0.5T) = (1, 1)
8212 13:42:15.431281 best DQS1 dly(2T, 0.5T) = (1, 1)
8213 13:42:15.435131 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8214 13:42:15.438283 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8215 13:42:15.441559 best DQS0 dly(2T, 0.5T) = (1, 1)
8216 13:42:15.444560 best DQS1 dly(2T, 0.5T) = (1, 1)
8217 13:42:15.447911 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8218 13:42:15.451452 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8219 13:42:15.454813 Pre-setting of DQS Precalculation
8220 13:42:15.457932 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8221 13:42:15.458003 ==
8222 13:42:15.461086 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 13:42:15.467752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 13:42:15.467861 ==
8225 13:42:15.470987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8226 13:42:15.477836 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8227 13:42:15.480929 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8228 13:42:15.487269 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8229 13:42:15.495550 [CA 0] Center 42 (13~72) winsize 60
8230 13:42:15.498531 [CA 1] Center 42 (12~72) winsize 61
8231 13:42:15.501735 [CA 2] Center 38 (9~68) winsize 60
8232 13:42:15.505650 [CA 3] Center 37 (8~67) winsize 60
8233 13:42:15.508752 [CA 4] Center 38 (8~68) winsize 61
8234 13:42:15.511657 [CA 5] Center 37 (8~67) winsize 60
8235 13:42:15.511742
8236 13:42:15.514872 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8237 13:42:15.514975
8238 13:42:15.518167 [CATrainingPosCal] consider 1 rank data
8239 13:42:15.521614 u2DelayCellTimex100 = 275/100 ps
8240 13:42:15.528654 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8241 13:42:15.531619 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8242 13:42:15.534876 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8243 13:42:15.537988 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8244 13:42:15.541219 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8245 13:42:15.545066 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8246 13:42:15.545139
8247 13:42:15.548208 CA PerBit enable=1, Macro0, CA PI delay=37
8248 13:42:15.548291
8249 13:42:15.551536 [CBTSetCACLKResult] CA Dly = 37
8250 13:42:15.554714 CS Dly: 7 (0~38)
8251 13:42:15.558006 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8252 13:42:15.561448 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8253 13:42:15.561520 ==
8254 13:42:15.564762 Dram Type= 6, Freq= 0, CH_1, rank 1
8255 13:42:15.571119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 13:42:15.571240 ==
8257 13:42:15.574307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8258 13:42:15.581133 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8259 13:42:15.584273 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8260 13:42:15.590710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8261 13:42:15.598719 [CA 0] Center 42 (12~72) winsize 61
8262 13:42:15.602022 [CA 1] Center 42 (13~72) winsize 60
8263 13:42:15.604958 [CA 2] Center 38 (8~68) winsize 61
8264 13:42:15.608113 [CA 3] Center 37 (7~67) winsize 61
8265 13:42:15.611344 [CA 4] Center 37 (8~67) winsize 60
8266 13:42:15.615138 [CA 5] Center 37 (7~67) winsize 61
8267 13:42:15.615239
8268 13:42:15.618337 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8269 13:42:15.618415
8270 13:42:15.624709 [CATrainingPosCal] consider 2 rank data
8271 13:42:15.624862 u2DelayCellTimex100 = 275/100 ps
8272 13:42:15.631523 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8273 13:42:15.634597 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8274 13:42:15.638050 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8275 13:42:15.641086 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8276 13:42:15.644458 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8277 13:42:15.648026 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8278 13:42:15.648104
8279 13:42:15.651226 CA PerBit enable=1, Macro0, CA PI delay=37
8280 13:42:15.651318
8281 13:42:15.654563 [CBTSetCACLKResult] CA Dly = 37
8282 13:42:15.657784 CS Dly: 9 (0~42)
8283 13:42:15.661541 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8284 13:42:15.664727 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8285 13:42:15.664891
8286 13:42:15.668106 ----->DramcWriteLeveling(PI) begin...
8287 13:42:15.668221 ==
8288 13:42:15.670850 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 13:42:15.677572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 13:42:15.677657 ==
8291 13:42:15.680782 Write leveling (Byte 0): 25 => 25
8292 13:42:15.684259 Write leveling (Byte 1): 25 => 25
8293 13:42:15.684338 DramcWriteLeveling(PI) end<-----
8294 13:42:15.687390
8295 13:42:15.687466 ==
8296 13:42:15.690506 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 13:42:15.693810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 13:42:15.693883 ==
8299 13:42:15.697491 [Gating] SW mode calibration
8300 13:42:15.703794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8301 13:42:15.707065 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8302 13:42:15.713986 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8303 13:42:15.717171 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8304 13:42:15.720417 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8305 13:42:15.726526 1 4 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8306 13:42:15.730254 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8307 13:42:15.733610 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 13:42:15.739873 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 13:42:15.743639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 13:42:15.746553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 13:42:15.752912 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 13:42:15.756731 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8313 13:42:15.759574 1 5 12 | B1->B0 | 3131 2424 | 1 0 | (1 0) (1 0)
8314 13:42:15.766584 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 13:42:15.769697 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 13:42:15.776382 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 13:42:15.779532 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 13:42:15.782689 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 13:42:15.786228 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 13:42:15.792911 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8321 13:42:15.795662 1 6 12 | B1->B0 | 2f2f 3f3f | 1 0 | (0 0) (0 0)
8322 13:42:15.802287 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 13:42:15.805971 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 13:42:15.809170 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 13:42:15.815564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 13:42:15.818898 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 13:42:15.822049 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 13:42:15.828826 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8329 13:42:15.832063 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8330 13:42:15.835151 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8331 13:42:15.842122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 13:42:15.845431 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 13:42:15.848614 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 13:42:15.855463 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 13:42:15.858537 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 13:42:15.861531 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 13:42:15.868273 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 13:42:15.871790 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 13:42:15.875014 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 13:42:15.881270 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 13:42:15.884975 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 13:42:15.888139 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 13:42:15.894463 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 13:42:15.897965 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 13:42:15.901500 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8346 13:42:15.907772 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8347 13:42:15.907847 Total UI for P1: 0, mck2ui 16
8348 13:42:15.911329 best dqsien dly found for B0: ( 1, 9, 12)
8349 13:42:15.917597 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 13:42:15.921236 Total UI for P1: 0, mck2ui 16
8351 13:42:15.924191 best dqsien dly found for B1: ( 1, 9, 14)
8352 13:42:15.927628 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8353 13:42:15.931319 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8354 13:42:15.931394
8355 13:42:15.934183 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8356 13:42:15.937450 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8357 13:42:15.941221 [Gating] SW calibration Done
8358 13:42:15.941352 ==
8359 13:42:15.944515 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 13:42:15.947686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 13:42:15.950845 ==
8362 13:42:15.950921 RX Vref Scan: 0
8363 13:42:15.950983
8364 13:42:15.954154 RX Vref 0 -> 0, step: 1
8365 13:42:15.954247
8366 13:42:15.954312 RX Delay 0 -> 252, step: 8
8367 13:42:15.960906 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8368 13:42:15.964158 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8369 13:42:15.967261 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8370 13:42:15.970342 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8371 13:42:15.977089 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8372 13:42:15.980437 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8373 13:42:15.983922 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8374 13:42:15.986925 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8375 13:42:15.990227 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8376 13:42:15.997160 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8377 13:42:16.000310 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8378 13:42:16.003861 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8379 13:42:16.006983 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8380 13:42:16.009954 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8381 13:42:16.016979 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8382 13:42:16.019876 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8383 13:42:16.019959 ==
8384 13:42:16.022967 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 13:42:16.026742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 13:42:16.026834 ==
8387 13:42:16.029752 DQS Delay:
8388 13:42:16.029834 DQS0 = 0, DQS1 = 0
8389 13:42:16.033427 DQM Delay:
8390 13:42:16.033510 DQM0 = 133, DQM1 = 129
8391 13:42:16.033575 DQ Delay:
8392 13:42:16.036481 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8393 13:42:16.043222 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =127
8394 13:42:16.046445 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8395 13:42:16.049659 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8396 13:42:16.049743
8397 13:42:16.049808
8398 13:42:16.049869 ==
8399 13:42:16.052842 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 13:42:16.055925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 13:42:16.056008 ==
8402 13:42:16.056073
8403 13:42:16.056134
8404 13:42:16.059764 TX Vref Scan disable
8405 13:42:16.062873 == TX Byte 0 ==
8406 13:42:16.066011 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8407 13:42:16.069223 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8408 13:42:16.072520 == TX Byte 1 ==
8409 13:42:16.076189 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8410 13:42:16.079220 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8411 13:42:16.079304 ==
8412 13:42:16.082233 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 13:42:16.088854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 13:42:16.088930 ==
8415 13:42:16.101031
8416 13:42:16.104774 TX Vref early break, caculate TX vref
8417 13:42:16.107904 TX Vref=16, minBit 8, minWin=21, winSum=367
8418 13:42:16.111009 TX Vref=18, minBit 8, minWin=22, winSum=381
8419 13:42:16.114397 TX Vref=20, minBit 9, minWin=23, winSum=390
8420 13:42:16.117526 TX Vref=22, minBit 8, minWin=23, winSum=398
8421 13:42:16.121008 TX Vref=24, minBit 8, minWin=24, winSum=408
8422 13:42:16.127434 TX Vref=26, minBit 1, minWin=25, winSum=416
8423 13:42:16.131252 TX Vref=28, minBit 9, minWin=24, winSum=415
8424 13:42:16.134419 TX Vref=30, minBit 9, minWin=25, winSum=417
8425 13:42:16.137402 TX Vref=32, minBit 9, minWin=24, winSum=407
8426 13:42:16.140604 TX Vref=34, minBit 0, minWin=24, winSum=398
8427 13:42:16.147731 TX Vref=36, minBit 0, minWin=23, winSum=385
8428 13:42:16.150672 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 30
8429 13:42:16.150755
8430 13:42:16.154041 Final TX Range 0 Vref 30
8431 13:42:16.154123
8432 13:42:16.154187 ==
8433 13:42:16.157163 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 13:42:16.160982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 13:42:16.161065 ==
8436 13:42:16.164109
8437 13:42:16.164191
8438 13:42:16.164256 TX Vref Scan disable
8439 13:42:16.170543 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8440 13:42:16.170627 == TX Byte 0 ==
8441 13:42:16.173749 u2DelayCellOfst[0]=17 cells (5 PI)
8442 13:42:16.176905 u2DelayCellOfst[1]=10 cells (3 PI)
8443 13:42:16.180102 u2DelayCellOfst[2]=0 cells (0 PI)
8444 13:42:16.183833 u2DelayCellOfst[3]=7 cells (2 PI)
8445 13:42:16.186847 u2DelayCellOfst[4]=10 cells (3 PI)
8446 13:42:16.190530 u2DelayCellOfst[5]=17 cells (5 PI)
8447 13:42:16.193622 u2DelayCellOfst[6]=17 cells (5 PI)
8448 13:42:16.196697 u2DelayCellOfst[7]=7 cells (2 PI)
8449 13:42:16.200249 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8450 13:42:16.203101 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8451 13:42:16.206518 == TX Byte 1 ==
8452 13:42:16.210070 u2DelayCellOfst[8]=0 cells (0 PI)
8453 13:42:16.213538 u2DelayCellOfst[9]=3 cells (1 PI)
8454 13:42:16.216638 u2DelayCellOfst[10]=10 cells (3 PI)
8455 13:42:16.219759 u2DelayCellOfst[11]=3 cells (1 PI)
8456 13:42:16.223452 u2DelayCellOfst[12]=14 cells (4 PI)
8457 13:42:16.226630 u2DelayCellOfst[13]=17 cells (5 PI)
8458 13:42:16.229677 u2DelayCellOfst[14]=14 cells (4 PI)
8459 13:42:16.232944 u2DelayCellOfst[15]=17 cells (5 PI)
8460 13:42:16.236275 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8461 13:42:16.239905 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 13:42:16.242881 DramC Write-DBI on
8463 13:42:16.242954 ==
8464 13:42:16.245994 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 13:42:16.249230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 13:42:16.249311 ==
8467 13:42:16.249373
8468 13:42:16.249430
8469 13:42:16.252580 TX Vref Scan disable
8470 13:42:16.255921 == TX Byte 0 ==
8471 13:42:16.259309 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8472 13:42:16.259384 == TX Byte 1 ==
8473 13:42:16.266096 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8474 13:42:16.266175 DramC Write-DBI off
8475 13:42:16.266237
8476 13:42:16.266298 [DATLAT]
8477 13:42:16.268937 Freq=1600, CH1 RK0
8478 13:42:16.269002
8479 13:42:16.272099 DATLAT Default: 0xf
8480 13:42:16.272179 0, 0xFFFF, sum = 0
8481 13:42:16.275935 1, 0xFFFF, sum = 0
8482 13:42:16.276007 2, 0xFFFF, sum = 0
8483 13:42:16.279074 3, 0xFFFF, sum = 0
8484 13:42:16.279149 4, 0xFFFF, sum = 0
8485 13:42:16.282194 5, 0xFFFF, sum = 0
8486 13:42:16.282262 6, 0xFFFF, sum = 0
8487 13:42:16.285311 7, 0xFFFF, sum = 0
8488 13:42:16.285381 8, 0xFFFF, sum = 0
8489 13:42:16.288908 9, 0xFFFF, sum = 0
8490 13:42:16.288982 10, 0xFFFF, sum = 0
8491 13:42:16.292001 11, 0xFFFF, sum = 0
8492 13:42:16.292074 12, 0xFFFF, sum = 0
8493 13:42:16.295750 13, 0xFFFF, sum = 0
8494 13:42:16.295825 14, 0x0, sum = 1
8495 13:42:16.298824 15, 0x0, sum = 2
8496 13:42:16.298898 16, 0x0, sum = 3
8497 13:42:16.302034 17, 0x0, sum = 4
8498 13:42:16.302106 best_step = 15
8499 13:42:16.302172
8500 13:42:16.302233 ==
8501 13:42:16.305168 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 13:42:16.311939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 13:42:16.312019 ==
8504 13:42:16.312084 RX Vref Scan: 1
8505 13:42:16.312143
8506 13:42:16.315170 Set Vref Range= 24 -> 127
8507 13:42:16.315238
8508 13:42:16.318364 RX Vref 24 -> 127, step: 1
8509 13:42:16.318432
8510 13:42:16.321631 RX Delay 19 -> 252, step: 4
8511 13:42:16.321709
8512 13:42:16.324919 Set Vref, RX VrefLevel [Byte0]: 24
8513 13:42:16.328217 [Byte1]: 24
8514 13:42:16.328290
8515 13:42:16.331878 Set Vref, RX VrefLevel [Byte0]: 25
8516 13:42:16.335078 [Byte1]: 25
8517 13:42:16.335149
8518 13:42:16.338119 Set Vref, RX VrefLevel [Byte0]: 26
8519 13:42:16.341881 [Byte1]: 26
8520 13:42:16.341952
8521 13:42:16.344861 Set Vref, RX VrefLevel [Byte0]: 27
8522 13:42:16.348223 [Byte1]: 27
8523 13:42:16.352001
8524 13:42:16.352073 Set Vref, RX VrefLevel [Byte0]: 28
8525 13:42:16.355941 [Byte1]: 28
8526 13:42:16.359776
8527 13:42:16.359849 Set Vref, RX VrefLevel [Byte0]: 29
8528 13:42:16.363561 [Byte1]: 29
8529 13:42:16.367870
8530 13:42:16.367940 Set Vref, RX VrefLevel [Byte0]: 30
8531 13:42:16.370533 [Byte1]: 30
8532 13:42:16.374702
8533 13:42:16.374790 Set Vref, RX VrefLevel [Byte0]: 31
8534 13:42:16.378599 [Byte1]: 31
8535 13:42:16.382372
8536 13:42:16.382453 Set Vref, RX VrefLevel [Byte0]: 32
8537 13:42:16.386177 [Byte1]: 32
8538 13:42:16.390006
8539 13:42:16.390088 Set Vref, RX VrefLevel [Byte0]: 33
8540 13:42:16.393188 [Byte1]: 33
8541 13:42:16.397566
8542 13:42:16.397648 Set Vref, RX VrefLevel [Byte0]: 34
8543 13:42:16.401242 [Byte1]: 34
8544 13:42:16.405189
8545 13:42:16.405299 Set Vref, RX VrefLevel [Byte0]: 35
8546 13:42:16.408457 [Byte1]: 35
8547 13:42:16.412893
8548 13:42:16.412975 Set Vref, RX VrefLevel [Byte0]: 36
8549 13:42:16.416201 [Byte1]: 36
8550 13:42:16.420408
8551 13:42:16.420490 Set Vref, RX VrefLevel [Byte0]: 37
8552 13:42:16.423791 [Byte1]: 37
8553 13:42:16.427814
8554 13:42:16.427896 Set Vref, RX VrefLevel [Byte0]: 38
8555 13:42:16.431119 [Byte1]: 38
8556 13:42:16.435786
8557 13:42:16.435859 Set Vref, RX VrefLevel [Byte0]: 39
8558 13:42:16.439080 [Byte1]: 39
8559 13:42:16.442973
8560 13:42:16.443050 Set Vref, RX VrefLevel [Byte0]: 40
8561 13:42:16.446298 [Byte1]: 40
8562 13:42:16.450670
8563 13:42:16.450747 Set Vref, RX VrefLevel [Byte0]: 41
8564 13:42:16.454103 [Byte1]: 41
8565 13:42:16.458530
8566 13:42:16.458609 Set Vref, RX VrefLevel [Byte0]: 42
8567 13:42:16.461603 [Byte1]: 42
8568 13:42:16.465735
8569 13:42:16.465813 Set Vref, RX VrefLevel [Byte0]: 43
8570 13:42:16.469631 [Byte1]: 43
8571 13:42:16.473521
8572 13:42:16.473604 Set Vref, RX VrefLevel [Byte0]: 44
8573 13:42:16.476797 [Byte1]: 44
8574 13:42:16.480867
8575 13:42:16.480946 Set Vref, RX VrefLevel [Byte0]: 45
8576 13:42:16.484671 [Byte1]: 45
8577 13:42:16.488499
8578 13:42:16.488574 Set Vref, RX VrefLevel [Byte0]: 46
8579 13:42:16.491611 [Byte1]: 46
8580 13:42:16.496010
8581 13:42:16.496081 Set Vref, RX VrefLevel [Byte0]: 47
8582 13:42:16.499711 [Byte1]: 47
8583 13:42:16.504058
8584 13:42:16.504132 Set Vref, RX VrefLevel [Byte0]: 48
8585 13:42:16.507226 [Byte1]: 48
8586 13:42:16.511061
8587 13:42:16.511136 Set Vref, RX VrefLevel [Byte0]: 49
8588 13:42:16.514937 [Byte1]: 49
8589 13:42:16.518794
8590 13:42:16.518869 Set Vref, RX VrefLevel [Byte0]: 50
8591 13:42:16.522544 [Byte1]: 50
8592 13:42:16.526216
8593 13:42:16.526287 Set Vref, RX VrefLevel [Byte0]: 51
8594 13:42:16.529893 [Byte1]: 51
8595 13:42:16.533780
8596 13:42:16.533851 Set Vref, RX VrefLevel [Byte0]: 52
8597 13:42:16.537535 [Byte1]: 52
8598 13:42:16.541716
8599 13:42:16.541798 Set Vref, RX VrefLevel [Byte0]: 53
8600 13:42:16.544746 [Byte1]: 53
8601 13:42:16.549029
8602 13:42:16.549138 Set Vref, RX VrefLevel [Byte0]: 54
8603 13:42:16.552292 [Byte1]: 54
8604 13:42:16.556873
8605 13:42:16.556955 Set Vref, RX VrefLevel [Byte0]: 55
8606 13:42:16.559777 [Byte1]: 55
8607 13:42:16.564455
8608 13:42:16.564538 Set Vref, RX VrefLevel [Byte0]: 56
8609 13:42:16.567763 [Byte1]: 56
8610 13:42:16.571699
8611 13:42:16.571801 Set Vref, RX VrefLevel [Byte0]: 57
8612 13:42:16.575282 [Byte1]: 57
8613 13:42:16.579800
8614 13:42:16.579882 Set Vref, RX VrefLevel [Byte0]: 58
8615 13:42:16.583019 [Byte1]: 58
8616 13:42:16.586764
8617 13:42:16.586848 Set Vref, RX VrefLevel [Byte0]: 59
8618 13:42:16.590574 [Byte1]: 59
8619 13:42:16.594629
8620 13:42:16.594708 Set Vref, RX VrefLevel [Byte0]: 60
8621 13:42:16.597844 [Byte1]: 60
8622 13:42:16.602161
8623 13:42:16.602236 Set Vref, RX VrefLevel [Byte0]: 61
8624 13:42:16.605235 [Byte1]: 61
8625 13:42:16.609768
8626 13:42:16.609850 Set Vref, RX VrefLevel [Byte0]: 62
8627 13:42:16.612976 [Byte1]: 62
8628 13:42:16.617488
8629 13:42:16.617570 Set Vref, RX VrefLevel [Byte0]: 63
8630 13:42:16.620880 [Byte1]: 63
8631 13:42:16.625063
8632 13:42:16.625145 Set Vref, RX VrefLevel [Byte0]: 64
8633 13:42:16.628157 [Byte1]: 64
8634 13:42:16.632545
8635 13:42:16.632627 Set Vref, RX VrefLevel [Byte0]: 65
8636 13:42:16.635813 [Byte1]: 65
8637 13:42:16.640388
8638 13:42:16.640470 Set Vref, RX VrefLevel [Byte0]: 66
8639 13:42:16.643304 [Byte1]: 66
8640 13:42:16.647770
8641 13:42:16.647881 Set Vref, RX VrefLevel [Byte0]: 67
8642 13:42:16.650912 [Byte1]: 67
8643 13:42:16.655184
8644 13:42:16.655266 Set Vref, RX VrefLevel [Byte0]: 68
8645 13:42:16.658604 [Byte1]: 68
8646 13:42:16.662549
8647 13:42:16.662632 Set Vref, RX VrefLevel [Byte0]: 69
8648 13:42:16.666017 [Byte1]: 69
8649 13:42:16.670580
8650 13:42:16.670662 Set Vref, RX VrefLevel [Byte0]: 70
8651 13:42:16.673576 [Byte1]: 70
8652 13:42:16.677986
8653 13:42:16.678068 Final RX Vref Byte 0 = 56 to rank0
8654 13:42:16.680964 Final RX Vref Byte 1 = 62 to rank0
8655 13:42:16.684868 Final RX Vref Byte 0 = 56 to rank1
8656 13:42:16.687828 Final RX Vref Byte 1 = 62 to rank1==
8657 13:42:16.691360 Dram Type= 6, Freq= 0, CH_1, rank 0
8658 13:42:16.697988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8659 13:42:16.698072 ==
8660 13:42:16.698138 DQS Delay:
8661 13:42:16.698199 DQS0 = 0, DQS1 = 0
8662 13:42:16.700769 DQM Delay:
8663 13:42:16.700881 DQM0 = 131, DQM1 = 128
8664 13:42:16.704654 DQ Delay:
8665 13:42:16.707802 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =130
8666 13:42:16.710884 DQ4 =126, DQ5 =142, DQ6 =144, DQ7 =126
8667 13:42:16.714602 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8668 13:42:16.717765 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8669 13:42:16.717848
8670 13:42:16.717913
8671 13:42:16.717974
8672 13:42:16.721027 [DramC_TX_OE_Calibration] TA2
8673 13:42:16.724232 Original DQ_B0 (3 6) =30, OEN = 27
8674 13:42:16.727828 Original DQ_B1 (3 6) =30, OEN = 27
8675 13:42:16.731057 24, 0x0, End_B0=24 End_B1=24
8676 13:42:16.731143 25, 0x0, End_B0=25 End_B1=25
8677 13:42:16.734211 26, 0x0, End_B0=26 End_B1=26
8678 13:42:16.737224 27, 0x0, End_B0=27 End_B1=27
8679 13:42:16.740613 28, 0x0, End_B0=28 End_B1=28
8680 13:42:16.743839 29, 0x0, End_B0=29 End_B1=29
8681 13:42:16.743926 30, 0x0, End_B0=30 End_B1=30
8682 13:42:16.747700 31, 0x4141, End_B0=30 End_B1=30
8683 13:42:16.750868 Byte0 end_step=30 best_step=27
8684 13:42:16.753982 Byte1 end_step=30 best_step=27
8685 13:42:16.757323 Byte0 TX OE(2T, 0.5T) = (3, 3)
8686 13:42:16.760470 Byte1 TX OE(2T, 0.5T) = (3, 3)
8687 13:42:16.760555
8688 13:42:16.760661
8689 13:42:16.767058 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8690 13:42:16.770593 CH1 RK0: MR19=303, MR18=D17
8691 13:42:16.777052 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8692 13:42:16.777139
8693 13:42:16.779954 ----->DramcWriteLeveling(PI) begin...
8694 13:42:16.780038 ==
8695 13:42:16.783433 Dram Type= 6, Freq= 0, CH_1, rank 1
8696 13:42:16.786818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8697 13:42:16.786902 ==
8698 13:42:16.790083 Write leveling (Byte 0): 24 => 24
8699 13:42:16.793730 Write leveling (Byte 1): 25 => 25
8700 13:42:16.796933 DramcWriteLeveling(PI) end<-----
8701 13:42:16.797075
8702 13:42:16.797175 ==
8703 13:42:16.799886 Dram Type= 6, Freq= 0, CH_1, rank 1
8704 13:42:16.803293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 13:42:16.803376 ==
8706 13:42:16.807083 [Gating] SW mode calibration
8707 13:42:16.813286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8708 13:42:16.819996 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8709 13:42:16.823067 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8710 13:42:16.830188 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8711 13:42:16.833196 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8712 13:42:16.836340 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8713 13:42:16.843263 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8714 13:42:16.846432 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8715 13:42:16.849713 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8716 13:42:16.856097 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8717 13:42:16.859732 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8718 13:42:16.862563 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8719 13:42:16.869616 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8720 13:42:16.873154 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8721 13:42:16.875931 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8722 13:42:16.882585 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8723 13:42:16.885716 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8724 13:42:16.889080 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 13:42:16.895961 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 13:42:16.899251 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8727 13:42:16.902275 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8728 13:42:16.909033 1 6 12 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8729 13:42:16.912246 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8730 13:42:16.915779 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8731 13:42:16.922778 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 13:42:16.925778 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8733 13:42:16.928841 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 13:42:16.935255 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8735 13:42:16.938952 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8736 13:42:16.942062 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8737 13:42:16.948952 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8738 13:42:16.952063 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8739 13:42:16.955279 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8740 13:42:16.962254 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 13:42:16.965489 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 13:42:16.968633 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 13:42:16.975027 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 13:42:16.978251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 13:42:16.981749 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 13:42:16.988071 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 13:42:16.991864 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 13:42:16.994835 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 13:42:17.001215 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 13:42:17.004372 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8751 13:42:17.007669 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8752 13:42:17.014394 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8753 13:42:17.014478 Total UI for P1: 0, mck2ui 16
8754 13:42:17.020923 best dqsien dly found for B0: ( 1, 9, 6)
8755 13:42:17.024110 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 13:42:17.027677 Total UI for P1: 0, mck2ui 16
8757 13:42:17.030673 best dqsien dly found for B1: ( 1, 9, 12)
8758 13:42:17.034381 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8759 13:42:17.037211 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8760 13:42:17.037359
8761 13:42:17.040597 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8762 13:42:17.044233 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8763 13:42:17.047149 [Gating] SW calibration Done
8764 13:42:17.047233 ==
8765 13:42:17.050906 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 13:42:17.054057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 13:42:17.057131 ==
8768 13:42:17.057213 RX Vref Scan: 0
8769 13:42:17.057317
8770 13:42:17.060524 RX Vref 0 -> 0, step: 1
8771 13:42:17.060606
8772 13:42:17.060670 RX Delay 0 -> 252, step: 8
8773 13:42:17.067257 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8774 13:42:17.070596 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8775 13:42:17.073750 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8776 13:42:17.076882 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8777 13:42:17.083926 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8778 13:42:17.086930 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8779 13:42:17.090518 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8780 13:42:17.093648 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8781 13:42:17.096728 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8782 13:42:17.103215 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8783 13:42:17.106822 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8784 13:42:17.109904 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8785 13:42:17.113016 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8786 13:42:17.116816 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8787 13:42:17.122887 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8788 13:42:17.126460 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8789 13:42:17.126547 ==
8790 13:42:17.130155 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 13:42:17.133108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 13:42:17.133191 ==
8793 13:42:17.136266 DQS Delay:
8794 13:42:17.136348 DQS0 = 0, DQS1 = 0
8795 13:42:17.136413 DQM Delay:
8796 13:42:17.140012 DQM0 = 133, DQM1 = 131
8797 13:42:17.140094 DQ Delay:
8798 13:42:17.143038 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8799 13:42:17.146090 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8800 13:42:17.152751 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8801 13:42:17.156017 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8802 13:42:17.156101
8803 13:42:17.156166
8804 13:42:17.156227 ==
8805 13:42:17.159318 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 13:42:17.163103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 13:42:17.163186 ==
8808 13:42:17.163251
8809 13:42:17.163311
8810 13:42:17.166238 TX Vref Scan disable
8811 13:42:17.169559 == TX Byte 0 ==
8812 13:42:17.172847 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8813 13:42:17.175932 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8814 13:42:17.179143 == TX Byte 1 ==
8815 13:42:17.182396 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8816 13:42:17.186260 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8817 13:42:17.186343 ==
8818 13:42:17.189595 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 13:42:17.199971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 13:42:17.200131 ==
8821 13:42:17.208803
8822 13:42:17.212363 TX Vref early break, caculate TX vref
8823 13:42:17.215298 TX Vref=16, minBit 9, minWin=22, winSum=379
8824 13:42:17.218591 TX Vref=18, minBit 9, minWin=22, winSum=382
8825 13:42:17.222325 TX Vref=20, minBit 9, minWin=23, winSum=391
8826 13:42:17.225700 TX Vref=22, minBit 13, minWin=23, winSum=403
8827 13:42:17.228584 TX Vref=24, minBit 9, minWin=23, winSum=408
8828 13:42:17.235047 TX Vref=26, minBit 9, minWin=24, winSum=417
8829 13:42:17.238700 TX Vref=28, minBit 9, minWin=24, winSum=417
8830 13:42:17.241833 TX Vref=30, minBit 9, minWin=25, winSum=417
8831 13:42:17.245648 TX Vref=32, minBit 5, minWin=25, winSum=415
8832 13:42:17.248657 TX Vref=34, minBit 0, minWin=24, winSum=404
8833 13:42:17.255099 TX Vref=36, minBit 0, minWin=23, winSum=396
8834 13:42:17.258476 TX Vref=38, minBit 0, minWin=23, winSum=385
8835 13:42:17.261652 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 30
8836 13:42:17.264726
8837 13:42:17.264808 Final TX Range 0 Vref 30
8838 13:42:17.264873
8839 13:42:17.264934 ==
8840 13:42:17.268153 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 13:42:17.274482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 13:42:17.274566 ==
8843 13:42:17.274633
8844 13:42:17.274693
8845 13:42:17.274750 TX Vref Scan disable
8846 13:42:17.281998 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8847 13:42:17.282085 == TX Byte 0 ==
8848 13:42:17.285214 u2DelayCellOfst[0]=14 cells (4 PI)
8849 13:42:17.288431 u2DelayCellOfst[1]=10 cells (3 PI)
8850 13:42:17.292192 u2DelayCellOfst[2]=0 cells (0 PI)
8851 13:42:17.295349 u2DelayCellOfst[3]=7 cells (2 PI)
8852 13:42:17.298476 u2DelayCellOfst[4]=7 cells (2 PI)
8853 13:42:17.301589 u2DelayCellOfst[5]=17 cells (5 PI)
8854 13:42:17.305072 u2DelayCellOfst[6]=14 cells (4 PI)
8855 13:42:17.308127 u2DelayCellOfst[7]=7 cells (2 PI)
8856 13:42:17.311537 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8857 13:42:17.314919 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8858 13:42:17.318492 == TX Byte 1 ==
8859 13:42:17.321570 u2DelayCellOfst[8]=0 cells (0 PI)
8860 13:42:17.324995 u2DelayCellOfst[9]=7 cells (2 PI)
8861 13:42:17.327819 u2DelayCellOfst[10]=14 cells (4 PI)
8862 13:42:17.331078 u2DelayCellOfst[11]=7 cells (2 PI)
8863 13:42:17.334591 u2DelayCellOfst[12]=14 cells (4 PI)
8864 13:42:17.338179 u2DelayCellOfst[13]=17 cells (5 PI)
8865 13:42:17.341119 u2DelayCellOfst[14]=21 cells (6 PI)
8866 13:42:17.344665 u2DelayCellOfst[15]=21 cells (6 PI)
8867 13:42:17.347741 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8868 13:42:17.350825 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8869 13:42:17.354187 DramC Write-DBI on
8870 13:42:17.354269 ==
8871 13:42:17.357366 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 13:42:17.361177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 13:42:17.361271 ==
8874 13:42:17.361351
8875 13:42:17.361411
8876 13:42:17.364277 TX Vref Scan disable
8877 13:42:17.364359 == TX Byte 0 ==
8878 13:42:17.370783 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8879 13:42:17.370866 == TX Byte 1 ==
8880 13:42:17.377327 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8881 13:42:17.377436 DramC Write-DBI off
8882 13:42:17.377529
8883 13:42:17.377618 [DATLAT]
8884 13:42:17.380935 Freq=1600, CH1 RK1
8885 13:42:17.381043
8886 13:42:17.381136 DATLAT Default: 0xf
8887 13:42:17.384113 0, 0xFFFF, sum = 0
8888 13:42:17.387343 1, 0xFFFF, sum = 0
8889 13:42:17.387454 2, 0xFFFF, sum = 0
8890 13:42:17.390624 3, 0xFFFF, sum = 0
8891 13:42:17.390721 4, 0xFFFF, sum = 0
8892 13:42:17.394356 5, 0xFFFF, sum = 0
8893 13:42:17.394440 6, 0xFFFF, sum = 0
8894 13:42:17.397561 7, 0xFFFF, sum = 0
8895 13:42:17.397644 8, 0xFFFF, sum = 0
8896 13:42:17.400766 9, 0xFFFF, sum = 0
8897 13:42:17.400849 10, 0xFFFF, sum = 0
8898 13:42:17.403818 11, 0xFFFF, sum = 0
8899 13:42:17.403901 12, 0xFFFF, sum = 0
8900 13:42:17.406999 13, 0xFFFF, sum = 0
8901 13:42:17.407082 14, 0x0, sum = 1
8902 13:42:17.410539 15, 0x0, sum = 2
8903 13:42:17.410623 16, 0x0, sum = 3
8904 13:42:17.414286 17, 0x0, sum = 4
8905 13:42:17.414369 best_step = 15
8906 13:42:17.414434
8907 13:42:17.414493 ==
8908 13:42:17.417535 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 13:42:17.423818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 13:42:17.423901 ==
8911 13:42:17.423966 RX Vref Scan: 0
8912 13:42:17.424026
8913 13:42:17.426862 RX Vref 0 -> 0, step: 1
8914 13:42:17.426944
8915 13:42:17.430526 RX Delay 19 -> 252, step: 4
8916 13:42:17.433629 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8917 13:42:17.437006 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8918 13:42:17.440270 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8919 13:42:17.447000 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8920 13:42:17.450017 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8921 13:42:17.453471 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8922 13:42:17.456472 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8923 13:42:17.459705 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8924 13:42:17.466474 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8925 13:42:17.469592 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8926 13:42:17.473195 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8927 13:42:17.476041 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8928 13:42:17.483147 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8929 13:42:17.485986 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8930 13:42:17.489808 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8931 13:42:17.493030 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8932 13:42:17.493104 ==
8933 13:42:17.496233 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 13:42:17.502619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 13:42:17.502706 ==
8936 13:42:17.502776 DQS Delay:
8937 13:42:17.505808 DQS0 = 0, DQS1 = 0
8938 13:42:17.505886 DQM Delay:
8939 13:42:17.509354 DQM0 = 131, DQM1 = 128
8940 13:42:17.509431 DQ Delay:
8941 13:42:17.512492 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8942 13:42:17.515886 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8943 13:42:17.519157 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8944 13:42:17.522300 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8945 13:42:17.522378
8946 13:42:17.522443
8947 13:42:17.522503
8948 13:42:17.526082 [DramC_TX_OE_Calibration] TA2
8949 13:42:17.529107 Original DQ_B0 (3 6) =30, OEN = 27
8950 13:42:17.532214 Original DQ_B1 (3 6) =30, OEN = 27
8951 13:42:17.535553 24, 0x0, End_B0=24 End_B1=24
8952 13:42:17.539017 25, 0x0, End_B0=25 End_B1=25
8953 13:42:17.539093 26, 0x0, End_B0=26 End_B1=26
8954 13:42:17.542123 27, 0x0, End_B0=27 End_B1=27
8955 13:42:17.545210 28, 0x0, End_B0=28 End_B1=28
8956 13:42:17.549147 29, 0x0, End_B0=29 End_B1=29
8957 13:42:17.549229 30, 0x0, End_B0=30 End_B1=30
8958 13:42:17.552181 31, 0x4141, End_B0=30 End_B1=30
8959 13:42:17.555600 Byte0 end_step=30 best_step=27
8960 13:42:17.558675 Byte1 end_step=30 best_step=27
8961 13:42:17.562034 Byte0 TX OE(2T, 0.5T) = (3, 3)
8962 13:42:17.565141 Byte1 TX OE(2T, 0.5T) = (3, 3)
8963 13:42:17.565223
8964 13:42:17.565296
8965 13:42:17.571730 [DQSOSCAuto] RK1, (LSB)MR18= 0x1221, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
8966 13:42:17.575399 CH1 RK1: MR19=303, MR18=1221
8967 13:42:17.581710 CH1_RK1: MR19=0x303, MR18=0x1221, DQSOSC=393, MR23=63, INC=23, DEC=15
8968 13:42:17.584784 [RxdqsGatingPostProcess] freq 1600
8969 13:42:17.591482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8970 13:42:17.591564 best DQS0 dly(2T, 0.5T) = (1, 1)
8971 13:42:17.594916 best DQS1 dly(2T, 0.5T) = (1, 1)
8972 13:42:17.597988 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8973 13:42:17.601684 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8974 13:42:17.604818 best DQS0 dly(2T, 0.5T) = (1, 1)
8975 13:42:17.607937 best DQS1 dly(2T, 0.5T) = (1, 1)
8976 13:42:17.611173 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8977 13:42:17.614924 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8978 13:42:17.618042 Pre-setting of DQS Precalculation
8979 13:42:17.621101 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8980 13:42:17.631571 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8981 13:42:17.637809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8982 13:42:17.637891
8983 13:42:17.637955
8984 13:42:17.640995 [Calibration Summary] 3200 Mbps
8985 13:42:17.641075 CH 0, Rank 0
8986 13:42:17.644010 SW Impedance : PASS
8987 13:42:17.647635 DUTY Scan : NO K
8988 13:42:17.647741 ZQ Calibration : PASS
8989 13:42:17.650747 Jitter Meter : NO K
8990 13:42:17.650827 CBT Training : PASS
8991 13:42:17.653891 Write leveling : PASS
8992 13:42:17.657262 RX DQS gating : PASS
8993 13:42:17.657376 RX DQ/DQS(RDDQC) : PASS
8994 13:42:17.660855 TX DQ/DQS : PASS
8995 13:42:17.663914 RX DATLAT : PASS
8996 13:42:17.663994 RX DQ/DQS(Engine): PASS
8997 13:42:17.667074 TX OE : PASS
8998 13:42:17.667155 All Pass.
8999 13:42:17.667218
9000 13:42:17.670309 CH 0, Rank 1
9001 13:42:17.670389 SW Impedance : PASS
9002 13:42:17.673966 DUTY Scan : NO K
9003 13:42:17.676894 ZQ Calibration : PASS
9004 13:42:17.677001 Jitter Meter : NO K
9005 13:42:17.680216 CBT Training : PASS
9006 13:42:17.683455 Write leveling : PASS
9007 13:42:17.683542 RX DQS gating : PASS
9008 13:42:17.686836 RX DQ/DQS(RDDQC) : PASS
9009 13:42:17.690086 TX DQ/DQS : PASS
9010 13:42:17.690187 RX DATLAT : PASS
9011 13:42:17.693776 RX DQ/DQS(Engine): PASS
9012 13:42:17.696602 TX OE : PASS
9013 13:42:17.696677 All Pass.
9014 13:42:17.696739
9015 13:42:17.696833 CH 1, Rank 0
9016 13:42:17.700037 SW Impedance : PASS
9017 13:42:17.703478 DUTY Scan : NO K
9018 13:42:17.703577 ZQ Calibration : PASS
9019 13:42:17.706766 Jitter Meter : NO K
9020 13:42:17.709912 CBT Training : PASS
9021 13:42:17.710011 Write leveling : PASS
9022 13:42:17.713125 RX DQS gating : PASS
9023 13:42:17.716500 RX DQ/DQS(RDDQC) : PASS
9024 13:42:17.716599 TX DQ/DQS : PASS
9025 13:42:17.719622 RX DATLAT : PASS
9026 13:42:17.723585 RX DQ/DQS(Engine): PASS
9027 13:42:17.723658 TX OE : PASS
9028 13:42:17.723729 All Pass.
9029 13:42:17.726530
9030 13:42:17.726627 CH 1, Rank 1
9031 13:42:17.729757 SW Impedance : PASS
9032 13:42:17.729829 DUTY Scan : NO K
9033 13:42:17.733233 ZQ Calibration : PASS
9034 13:42:17.736209 Jitter Meter : NO K
9035 13:42:17.736316 CBT Training : PASS
9036 13:42:17.739484 Write leveling : PASS
9037 13:42:17.743104 RX DQS gating : PASS
9038 13:42:17.743204 RX DQ/DQS(RDDQC) : PASS
9039 13:42:17.746280 TX DQ/DQS : PASS
9040 13:42:17.746362 RX DATLAT : PASS
9041 13:42:17.749406 RX DQ/DQS(Engine): PASS
9042 13:42:17.752845 TX OE : PASS
9043 13:42:17.752926 All Pass.
9044 13:42:17.752989
9045 13:42:17.755824 DramC Write-DBI on
9046 13:42:17.755905 PER_BANK_REFRESH: Hybrid Mode
9047 13:42:17.759601 TX_TRACKING: ON
9048 13:42:17.768944 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9049 13:42:17.776012 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9050 13:42:17.782401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 13:42:17.785434 [FAST_K] Save calibration result to emmc
9052 13:42:17.788704 sync common calibartion params.
9053 13:42:17.792308 sync cbt_mode0:1, 1:1
9054 13:42:17.795325 dram_init: ddr_geometry: 2
9055 13:42:17.795406 dram_init: ddr_geometry: 2
9056 13:42:17.798856 dram_init: ddr_geometry: 2
9057 13:42:17.802074 0:dram_rank_size:100000000
9058 13:42:17.805401 1:dram_rank_size:100000000
9059 13:42:17.808651 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9060 13:42:17.811718 DFS_SHUFFLE_HW_MODE: ON
9061 13:42:17.815140 dramc_set_vcore_voltage set vcore to 725000
9062 13:42:17.818373 Read voltage for 1600, 0
9063 13:42:17.818454 Vio18 = 0
9064 13:42:17.818519 Vcore = 725000
9065 13:42:17.821509 Vdram = 0
9066 13:42:17.821590 Vddq = 0
9067 13:42:17.821654 Vmddr = 0
9068 13:42:17.825414 switch to 3200 Mbps bootup
9069 13:42:17.828568 [DramcRunTimeConfig]
9070 13:42:17.828653 PHYPLL
9071 13:42:17.828717 DPM_CONTROL_AFTERK: ON
9072 13:42:17.831651 PER_BANK_REFRESH: ON
9073 13:42:17.834711 REFRESH_OVERHEAD_REDUCTION: ON
9074 13:42:17.834796 CMD_PICG_NEW_MODE: OFF
9075 13:42:17.838507 XRTWTW_NEW_MODE: ON
9076 13:42:17.841836 XRTRTR_NEW_MODE: ON
9077 13:42:17.841921 TX_TRACKING: ON
9078 13:42:17.844683 RDSEL_TRACKING: OFF
9079 13:42:17.844789 DQS Precalculation for DVFS: ON
9080 13:42:17.848549 RX_TRACKING: OFF
9081 13:42:17.848630 HW_GATING DBG: ON
9082 13:42:17.851703 ZQCS_ENABLE_LP4: ON
9083 13:42:17.851800 RX_PICG_NEW_MODE: ON
9084 13:42:17.854933 TX_PICG_NEW_MODE: ON
9085 13:42:17.857995 ENABLE_RX_DCM_DPHY: ON
9086 13:42:17.861687 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9087 13:42:17.861769 DUMMY_READ_FOR_TRACKING: OFF
9088 13:42:17.864854 !!! SPM_CONTROL_AFTERK: OFF
9089 13:42:17.868038 !!! SPM could not control APHY
9090 13:42:17.871582 IMPEDANCE_TRACKING: ON
9091 13:42:17.871666 TEMP_SENSOR: ON
9092 13:42:17.874755 HW_SAVE_FOR_SR: OFF
9093 13:42:17.874847 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9094 13:42:17.881164 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9095 13:42:17.881310 Read ODT Tracking: ON
9096 13:42:17.884465 Refresh Rate DeBounce: ON
9097 13:42:17.887744 DFS_NO_QUEUE_FLUSH: ON
9098 13:42:17.890845 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9099 13:42:17.890928 ENABLE_DFS_RUNTIME_MRW: OFF
9100 13:42:17.893938 DDR_RESERVE_NEW_MODE: ON
9101 13:42:17.897672 MR_CBT_SWITCH_FREQ: ON
9102 13:42:17.897755 =========================
9103 13:42:17.917700 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9104 13:42:17.920664 dram_init: ddr_geometry: 2
9105 13:42:17.938573 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9106 13:42:17.942375 dram_init: dram init end (result: 0)
9107 13:42:17.949176 DRAM-K: Full calibration passed in 24407 msecs
9108 13:42:17.951864 MRC: failed to locate region type 0.
9109 13:42:17.951945 DRAM rank0 size:0x100000000,
9110 13:42:17.955566 DRAM rank1 size=0x100000000
9111 13:42:17.964957 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9112 13:42:17.971644 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9113 13:42:17.978489 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9114 13:42:17.988016 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9115 13:42:17.988101 DRAM rank0 size:0x100000000,
9116 13:42:17.991902 DRAM rank1 size=0x100000000
9117 13:42:17.991983 CBMEM:
9118 13:42:17.995050 IMD: root @ 0xfffff000 254 entries.
9119 13:42:17.998229 IMD: root @ 0xffffec00 62 entries.
9120 13:42:18.004826 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9121 13:42:18.007892 WARNING: RO_VPD is uninitialized or empty.
9122 13:42:18.011504 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9123 13:42:18.018960 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9124 13:42:18.031915 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9125 13:42:18.042950 BS: romstage times (exec / console): total (unknown) / 23938 ms
9126 13:42:18.043033
9127 13:42:18.043097
9128 13:42:18.053115 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9129 13:42:18.056280 ARM64: Exception handlers installed.
9130 13:42:18.059744 ARM64: Testing exception
9131 13:42:18.062923 ARM64: Done test exception
9132 13:42:18.063003 Enumerating buses...
9133 13:42:18.066083 Show all devs... Before device enumeration.
9134 13:42:18.069875 Root Device: enabled 1
9135 13:42:18.073076 CPU_CLUSTER: 0: enabled 1
9136 13:42:18.073183 CPU: 00: enabled 1
9137 13:42:18.076164 Compare with tree...
9138 13:42:18.076245 Root Device: enabled 1
9139 13:42:18.079687 CPU_CLUSTER: 0: enabled 1
9140 13:42:18.082747 CPU: 00: enabled 1
9141 13:42:18.082829 Root Device scanning...
9142 13:42:18.085923 scan_static_bus for Root Device
9143 13:42:18.089570 CPU_CLUSTER: 0 enabled
9144 13:42:18.092821 scan_static_bus for Root Device done
9145 13:42:18.096027 scan_bus: bus Root Device finished in 8 msecs
9146 13:42:18.096109 done
9147 13:42:18.102415 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9148 13:42:18.106086 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9149 13:42:18.112585 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9150 13:42:18.115868 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9151 13:42:18.118998 Allocating resources...
9152 13:42:18.122113 Reading resources...
9153 13:42:18.125953 Root Device read_resources bus 0 link: 0
9154 13:42:18.129156 DRAM rank0 size:0x100000000,
9155 13:42:18.129269 DRAM rank1 size=0x100000000
9156 13:42:18.135441 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9157 13:42:18.135523 CPU: 00 missing read_resources
9158 13:42:18.141839 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9159 13:42:18.144936 Root Device read_resources bus 0 link: 0 done
9160 13:42:18.148519 Done reading resources.
9161 13:42:18.151885 Show resources in subtree (Root Device)...After reading.
9162 13:42:18.155014 Root Device child on link 0 CPU_CLUSTER: 0
9163 13:42:18.158383 CPU_CLUSTER: 0 child on link 0 CPU: 00
9164 13:42:18.168122 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9165 13:42:18.168204 CPU: 00
9166 13:42:18.174711 Root Device assign_resources, bus 0 link: 0
9167 13:42:18.178597 CPU_CLUSTER: 0 missing set_resources
9168 13:42:18.181792 Root Device assign_resources, bus 0 link: 0 done
9169 13:42:18.181874 Done setting resources.
9170 13:42:18.187941 Show resources in subtree (Root Device)...After assigning values.
9171 13:42:18.191596 Root Device child on link 0 CPU_CLUSTER: 0
9172 13:42:18.197818 CPU_CLUSTER: 0 child on link 0 CPU: 00
9173 13:42:18.204829 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9174 13:42:18.204937 CPU: 00
9175 13:42:18.207896 Done allocating resources.
9176 13:42:18.214501 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9177 13:42:18.214583 Enabling resources...
9178 13:42:18.217632 done.
9179 13:42:18.221329 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9180 13:42:18.224290 Initializing devices...
9181 13:42:18.224367 Root Device init
9182 13:42:18.227880 init hardware done!
9183 13:42:18.227960 0x00000018: ctrlr->caps
9184 13:42:18.230737 52.000 MHz: ctrlr->f_max
9185 13:42:18.233926 0.400 MHz: ctrlr->f_min
9186 13:42:18.237872 0x40ff8080: ctrlr->voltages
9187 13:42:18.237946 sclk: 390625
9188 13:42:18.238008 Bus Width = 1
9189 13:42:18.241069 sclk: 390625
9190 13:42:18.241144 Bus Width = 1
9191 13:42:18.244154 Early init status = 3
9192 13:42:18.247693 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9193 13:42:18.250873 in-header: 03 fc 00 00 01 00 00 00
9194 13:42:18.254488 in-data: 00
9195 13:42:18.257225 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9196 13:42:18.262678 in-header: 03 fd 00 00 00 00 00 00
9197 13:42:18.266501 in-data:
9198 13:42:18.269710 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9199 13:42:18.274092 in-header: 03 fc 00 00 01 00 00 00
9200 13:42:18.277172 in-data: 00
9201 13:42:18.280262 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9202 13:42:18.286550 in-header: 03 fd 00 00 00 00 00 00
9203 13:42:18.289648 in-data:
9204 13:42:18.292636 [SSUSB] Setting up USB HOST controller...
9205 13:42:18.296354 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9206 13:42:18.299397 [SSUSB] phy power-on done.
9207 13:42:18.302623 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9208 13:42:18.308934 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9209 13:42:18.312225 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9210 13:42:18.318988 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9211 13:42:18.326404 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9212 13:42:18.332437 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9213 13:42:18.339043 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9214 13:42:18.345308 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9215 13:42:18.348475 SPM: binary array size = 0x9dc
9216 13:42:18.352188 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9217 13:42:18.358396 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9218 13:42:18.364981 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9219 13:42:18.371712 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9220 13:42:18.375281 configure_display: Starting display init
9221 13:42:18.409663 anx7625_power_on_init: Init interface.
9222 13:42:18.412765 anx7625_disable_pd_protocol: Disabled PD feature.
9223 13:42:18.416055 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9224 13:42:18.443724 anx7625_start_dp_work: Secure OCM version=00
9225 13:42:18.447302 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9226 13:42:18.461853 sp_tx_get_edid_block: EDID Block = 1
9227 13:42:18.564383 Extracted contents:
9228 13:42:18.568115 header: 00 ff ff ff ff ff ff 00
9229 13:42:18.571153 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9230 13:42:18.574620 version: 01 04
9231 13:42:18.577712 basic params: 95 1f 11 78 0a
9232 13:42:18.581199 chroma info: 76 90 94 55 54 90 27 21 50 54
9233 13:42:18.584380 established: 00 00 00
9234 13:42:18.590578 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9235 13:42:18.594233 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9236 13:42:18.601051 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9237 13:42:18.607197 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9238 13:42:18.614134 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9239 13:42:18.617183 extensions: 00
9240 13:42:18.617324 checksum: fb
9241 13:42:18.617393
9242 13:42:18.620844 Manufacturer: IVO Model 57d Serial Number 0
9243 13:42:18.624015 Made week 0 of 2020
9244 13:42:18.627081 EDID version: 1.4
9245 13:42:18.627159 Digital display
9246 13:42:18.630807 6 bits per primary color channel
9247 13:42:18.630892 DisplayPort interface
9248 13:42:18.633911 Maximum image size: 31 cm x 17 cm
9249 13:42:18.637000 Gamma: 220%
9250 13:42:18.637077 Check DPMS levels
9251 13:42:18.640601 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9252 13:42:18.646870 First detailed timing is preferred timing
9253 13:42:18.646957 Established timings supported:
9254 13:42:18.650615 Standard timings supported:
9255 13:42:18.653764 Detailed timings
9256 13:42:18.657051 Hex of detail: 383680a07038204018303c0035ae10000019
9257 13:42:18.663433 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9258 13:42:18.666790 0780 0798 07c8 0820 hborder 0
9259 13:42:18.669963 0438 043b 0447 0458 vborder 0
9260 13:42:18.673070 -hsync -vsync
9261 13:42:18.673178 Did detailed timing
9262 13:42:18.679631 Hex of detail: 000000000000000000000000000000000000
9263 13:42:18.683415 Manufacturer-specified data, tag 0
9264 13:42:18.686814 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9265 13:42:18.689808 ASCII string: InfoVision
9266 13:42:18.693001 Hex of detail: 000000fe00523134304e574635205248200a
9267 13:42:18.696676 ASCII string: R140NWF5 RH
9268 13:42:18.696756 Checksum
9269 13:42:18.699831 Checksum: 0xfb (valid)
9270 13:42:18.702833 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9271 13:42:18.706608 DSI data_rate: 832800000 bps
9272 13:42:18.712712 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9273 13:42:18.715789 anx7625_parse_edid: pixelclock(138800).
9274 13:42:18.719098 hactive(1920), hsync(48), hfp(24), hbp(88)
9275 13:42:18.722792 vactive(1080), vsync(12), vfp(3), vbp(17)
9276 13:42:18.725849 anx7625_dsi_config: config dsi.
9277 13:42:18.732767 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9278 13:42:18.746461 anx7625_dsi_config: success to config DSI
9279 13:42:18.750036 anx7625_dp_start: MIPI phy setup OK.
9280 13:42:18.753277 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9281 13:42:18.756452 mtk_ddp_mode_set invalid vrefresh 60
9282 13:42:18.759542 main_disp_path_setup
9283 13:42:18.759611 ovl_layer_smi_id_en
9284 13:42:18.762702 ovl_layer_smi_id_en
9285 13:42:18.762773 ccorr_config
9286 13:42:18.762838 aal_config
9287 13:42:18.766579 gamma_config
9288 13:42:18.766651 postmask_config
9289 13:42:18.769566 dither_config
9290 13:42:18.772587 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9291 13:42:18.779278 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9292 13:42:18.782706 Root Device init finished in 554 msecs
9293 13:42:18.786088 CPU_CLUSTER: 0 init
9294 13:42:18.792904 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9295 13:42:18.799140 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9296 13:42:18.799216 APU_MBOX 0x190000b0 = 0x10001
9297 13:42:18.802359 APU_MBOX 0x190001b0 = 0x10001
9298 13:42:18.806019 APU_MBOX 0x190005b0 = 0x10001
9299 13:42:18.809046 APU_MBOX 0x190006b0 = 0x10001
9300 13:42:18.815690 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9301 13:42:18.825839 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9302 13:42:18.838182 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9303 13:42:18.844525 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9304 13:42:18.856561 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9305 13:42:18.865348 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9306 13:42:18.868545 CPU_CLUSTER: 0 init finished in 81 msecs
9307 13:42:18.871710 Devices initialized
9308 13:42:18.875413 Show all devs... After init.
9309 13:42:18.875494 Root Device: enabled 1
9310 13:42:18.878436 CPU_CLUSTER: 0: enabled 1
9311 13:42:18.882026 CPU: 00: enabled 1
9312 13:42:18.884985 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9313 13:42:18.888294 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9314 13:42:18.892017 ELOG: NV offset 0x57f000 size 0x1000
9315 13:42:18.898628 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9316 13:42:18.904932 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9317 13:42:18.908242 ELOG: Event(17) added with size 13 at 2024-05-28 13:42:18 UTC
9318 13:42:18.915030 out: cmd=0x121: 03 db 21 01 00 00 00 00
9319 13:42:18.918012 in-header: 03 fc 00 00 2c 00 00 00
9320 13:42:18.928781 in-data: 41 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9321 13:42:18.934530 ELOG: Event(A1) added with size 10 at 2024-05-28 13:42:18 UTC
9322 13:42:18.941228 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9323 13:42:18.948233 ELOG: Event(A0) added with size 9 at 2024-05-28 13:42:18 UTC
9324 13:42:18.951303 elog_add_boot_reason: Logged dev mode boot
9325 13:42:18.958005 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9326 13:42:18.958082 Finalize devices...
9327 13:42:18.961248 Devices finalized
9328 13:42:18.964439 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9329 13:42:18.967556 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9330 13:42:18.971259 in-header: 03 07 00 00 08 00 00 00
9331 13:42:18.974470 in-data: aa e4 47 04 13 02 00 00
9332 13:42:18.977583 Chrome EC: UHEPI supported
9333 13:42:18.984654 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9334 13:42:18.987417 in-header: 03 a9 00 00 08 00 00 00
9335 13:42:18.991003 in-data: 84 60 60 08 00 00 00 00
9336 13:42:18.997733 ELOG: Event(91) added with size 10 at 2024-05-28 13:42:19 UTC
9337 13:42:19.001088 Chrome EC: clear events_b mask to 0x0000000020004000
9338 13:42:19.007452 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9339 13:42:19.011980 in-header: 03 fd 00 00 00 00 00 00
9340 13:42:19.015871 in-data:
9341 13:42:19.019035 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9342 13:42:19.022066 Writing coreboot table at 0xffe64000
9343 13:42:19.025420 0. 000000000010a000-0000000000113fff: RAMSTAGE
9344 13:42:19.031931 1. 0000000040000000-00000000400fffff: RAM
9345 13:42:19.035124 2. 0000000040100000-000000004032afff: RAMSTAGE
9346 13:42:19.038812 3. 000000004032b000-00000000545fffff: RAM
9347 13:42:19.041944 4. 0000000054600000-000000005465ffff: BL31
9348 13:42:19.045753 5. 0000000054660000-00000000ffe63fff: RAM
9349 13:42:19.051584 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9350 13:42:19.055294 7. 0000000100000000-000000023fffffff: RAM
9351 13:42:19.058543 Passing 5 GPIOs to payload:
9352 13:42:19.061636 NAME | PORT | POLARITY | VALUE
9353 13:42:19.068528 EC in RW | 0x000000aa | low | undefined
9354 13:42:19.071720 EC interrupt | 0x00000005 | low | undefined
9355 13:42:19.078028 TPM interrupt | 0x000000ab | high | undefined
9356 13:42:19.081007 SD card detect | 0x00000011 | high | undefined
9357 13:42:19.084894 speaker enable | 0x00000093 | high | undefined
9358 13:42:19.088138 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9359 13:42:19.091226 in-header: 03 f9 00 00 02 00 00 00
9360 13:42:19.094758 in-data: 02 00
9361 13:42:19.097869 ADC[4]: Raw value=902586 ID=7
9362 13:42:19.101681 ADC[3]: Raw value=213916 ID=1
9363 13:42:19.101763 RAM Code: 0x71
9364 13:42:19.104801 ADC[6]: Raw value=74630 ID=0
9365 13:42:19.107925 ADC[5]: Raw value=213916 ID=1
9366 13:42:19.108006 SKU Code: 0x1
9367 13:42:19.114147 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 219b
9368 13:42:19.114238 coreboot table: 964 bytes.
9369 13:42:19.117828 IMD ROOT 0. 0xfffff000 0x00001000
9370 13:42:19.120833 IMD SMALL 1. 0xffffe000 0x00001000
9371 13:42:19.124248 RO MCACHE 2. 0xffffc000 0x00001104
9372 13:42:19.127569 CONSOLE 3. 0xfff7c000 0x00080000
9373 13:42:19.130599 FMAP 4. 0xfff7b000 0x00000452
9374 13:42:19.134263 TIME STAMP 5. 0xfff7a000 0x00000910
9375 13:42:19.137832 VBOOT WORK 6. 0xfff66000 0x00014000
9376 13:42:19.140559 RAMOOPS 7. 0xffe66000 0x00100000
9377 13:42:19.144323 COREBOOT 8. 0xffe64000 0x00002000
9378 13:42:19.147361 IMD small region:
9379 13:42:19.150440 IMD ROOT 0. 0xffffec00 0x00000400
9380 13:42:19.153904 VPD 1. 0xffffeb80 0x0000006c
9381 13:42:19.157219 MMC STATUS 2. 0xffffeb60 0x00000004
9382 13:42:19.164127 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9383 13:42:19.170470 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9384 13:42:19.209376 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9385 13:42:19.212403 Checking segment from ROM address 0x40100000
9386 13:42:19.215804 Checking segment from ROM address 0x4010001c
9387 13:42:19.221823 Loading segment from ROM address 0x40100000
9388 13:42:19.221906 code (compression=0)
9389 13:42:19.231959 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9390 13:42:19.238637 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9391 13:42:19.238720 it's not compressed!
9392 13:42:19.244961 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9393 13:42:19.251505 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9394 13:42:19.269628 Loading segment from ROM address 0x4010001c
9395 13:42:19.269711 Entry Point 0x80000000
9396 13:42:19.272417 Loaded segments
9397 13:42:19.275993 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9398 13:42:19.282134 Jumping to boot code at 0x80000000(0xffe64000)
9399 13:42:19.289092 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9400 13:42:19.295553 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9401 13:42:19.303654 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9402 13:42:19.306728 Checking segment from ROM address 0x40100000
9403 13:42:19.310146 Checking segment from ROM address 0x4010001c
9404 13:42:19.316875 Loading segment from ROM address 0x40100000
9405 13:42:19.316954 code (compression=1)
9406 13:42:19.323689 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9407 13:42:19.333141 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9408 13:42:19.333221 using LZMA
9409 13:42:19.341939 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9410 13:42:19.348849 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9411 13:42:19.351727 Loading segment from ROM address 0x4010001c
9412 13:42:19.351805 Entry Point 0x54601000
9413 13:42:19.355550 Loaded segments
9414 13:42:19.358648 NOTICE: MT8192 bl31_setup
9415 13:42:19.365655 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9416 13:42:19.368891 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9417 13:42:19.372459 WARNING: region 0:
9418 13:42:19.375503 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9419 13:42:19.375581 WARNING: region 1:
9420 13:42:19.381850 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9421 13:42:19.385196 WARNING: region 2:
9422 13:42:19.388969 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9423 13:42:19.392183 WARNING: region 3:
9424 13:42:19.398534 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9425 13:42:19.398616 WARNING: region 4:
9426 13:42:19.405411 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9427 13:42:19.405494 WARNING: region 5:
9428 13:42:19.408644 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9429 13:42:19.411706 WARNING: region 6:
9430 13:42:19.415570 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 13:42:19.418479 WARNING: region 7:
9432 13:42:19.421397 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 13:42:19.428284 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9434 13:42:19.431904 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9435 13:42:19.438123 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9436 13:42:19.441637 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9437 13:42:19.444804 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9438 13:42:19.451342 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9439 13:42:19.454371 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9440 13:42:19.458142 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9441 13:42:19.464416 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9442 13:42:19.467614 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9443 13:42:19.474551 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9444 13:42:19.477779 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9445 13:42:19.480821 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9446 13:42:19.487426 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9447 13:42:19.491044 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9448 13:42:19.497410 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9449 13:42:19.501065 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9450 13:42:19.504368 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9451 13:42:19.510691 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9452 13:42:19.513674 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9453 13:42:19.520720 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9454 13:42:19.523933 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9455 13:42:19.527380 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9456 13:42:19.534027 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9457 13:42:19.537319 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9458 13:42:19.544118 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9459 13:42:19.547355 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9460 13:42:19.550415 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9461 13:42:19.556999 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9462 13:42:19.560158 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9463 13:42:19.566656 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9464 13:42:19.570388 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9465 13:42:19.573398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9466 13:42:19.576692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9467 13:42:19.583209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9468 13:42:19.586812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9469 13:42:19.590569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9470 13:42:19.593543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9471 13:42:19.599755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9472 13:42:19.603565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9473 13:42:19.606632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9474 13:42:19.613074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9475 13:42:19.616199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9476 13:42:19.620021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9477 13:42:19.623115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9478 13:42:19.629458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9479 13:42:19.632576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9480 13:42:19.636384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9481 13:42:19.642419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9482 13:42:19.646134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9483 13:42:19.652530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9484 13:42:19.655875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9485 13:42:19.659029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9486 13:42:19.665602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9487 13:42:19.668774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9488 13:42:19.675612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9489 13:42:19.678755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9490 13:42:19.685454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9491 13:42:19.688728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9492 13:42:19.695775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9493 13:42:19.698593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9494 13:42:19.702110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9495 13:42:19.708460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9496 13:42:19.711735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9497 13:42:19.718676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9498 13:42:19.721911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9499 13:42:19.728244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9500 13:42:19.731415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9501 13:42:19.738399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9502 13:42:19.741532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9503 13:42:19.747670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9504 13:42:19.751512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9505 13:42:19.754368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9506 13:42:19.760781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9507 13:42:19.764615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9508 13:42:19.771064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9509 13:42:19.774263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9510 13:42:19.780584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9511 13:42:19.783885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9512 13:42:19.790480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9513 13:42:19.793920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9514 13:42:19.797444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9515 13:42:19.803892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9516 13:42:19.807362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9517 13:42:19.814173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9518 13:42:19.817110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9519 13:42:19.823705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9520 13:42:19.827503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9521 13:42:19.833632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9522 13:42:19.836901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9523 13:42:19.840109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9524 13:42:19.846957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9525 13:42:19.850193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9526 13:42:19.856341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9527 13:42:19.860317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9528 13:42:19.866392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9529 13:42:19.869977 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9530 13:42:19.873193 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9531 13:42:19.879813 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9532 13:42:19.882964 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9533 13:42:19.886127 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9534 13:42:19.893043 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9535 13:42:19.896112 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9536 13:42:19.899277 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9537 13:42:19.905784 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9538 13:42:19.909215 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9539 13:42:19.916085 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9540 13:42:19.918979 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9541 13:42:19.922475 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9542 13:42:19.928861 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9543 13:42:19.932671 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9544 13:42:19.938979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9545 13:42:19.942207 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9546 13:42:19.949194 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9547 13:42:19.952346 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9548 13:42:19.955505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9549 13:42:19.958713 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9550 13:42:19.965610 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9551 13:42:19.968823 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9552 13:42:19.971875 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9553 13:42:19.978675 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9554 13:42:19.981989 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9555 13:42:19.985132 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9556 13:42:19.991811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9557 13:42:19.995045 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9558 13:42:19.998144 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9559 13:42:20.004520 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9560 13:42:20.007673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9561 13:42:20.014606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9562 13:42:20.017761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9563 13:42:20.021365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9564 13:42:20.027834 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9565 13:42:20.031242 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9566 13:42:20.037482 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9567 13:42:20.041046 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9568 13:42:20.044160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9569 13:42:20.051108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9570 13:42:20.054235 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9571 13:42:20.060597 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9572 13:42:20.063787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9573 13:42:20.067599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9574 13:42:20.073910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9575 13:42:20.077051 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9576 13:42:20.083920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9577 13:42:20.087639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9578 13:42:20.090602 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9579 13:42:20.097032 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9580 13:42:20.100644 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9581 13:42:20.106863 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9582 13:42:20.110121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9583 13:42:20.113208 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9584 13:42:20.119951 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9585 13:42:20.123365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9586 13:42:20.129858 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9587 13:42:20.133462 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9588 13:42:20.136527 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9589 13:42:20.142977 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9590 13:42:20.146522 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9591 13:42:20.152837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9592 13:42:20.156161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9593 13:42:20.159513 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9594 13:42:20.165802 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9595 13:42:20.169114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9596 13:42:20.176239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9597 13:42:20.179249 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9598 13:42:20.182582 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9599 13:42:20.188850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9600 13:42:20.192650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9601 13:42:20.198810 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9602 13:42:20.201955 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9603 13:42:20.208800 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9604 13:42:20.212040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9605 13:42:20.215361 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9606 13:42:20.221509 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9607 13:42:20.225225 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9608 13:42:20.231809 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9609 13:42:20.234974 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9610 13:42:20.238530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9611 13:42:20.245175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9612 13:42:20.248243 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9613 13:42:20.252013 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9614 13:42:20.257940 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9615 13:42:20.261653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9616 13:42:20.268076 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9617 13:42:20.271297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9618 13:42:20.277581 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9619 13:42:20.280925 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9620 13:42:20.284718 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9621 13:42:20.291017 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9622 13:42:20.294288 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9623 13:42:20.301185 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9624 13:42:20.304807 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9625 13:42:20.307628 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9626 13:42:20.314287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9627 13:42:20.317443 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9628 13:42:20.324278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9629 13:42:20.327462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9630 13:42:20.333924 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9631 13:42:20.337163 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9632 13:42:20.341152 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9633 13:42:20.347488 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9634 13:42:20.350448 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9635 13:42:20.357468 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9636 13:42:20.360569 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9637 13:42:20.367061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9638 13:42:20.370235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9639 13:42:20.373469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9640 13:42:20.380459 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9641 13:42:20.383607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9642 13:42:20.389926 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9643 13:42:20.393736 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9644 13:42:20.399844 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9645 13:42:20.402982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9646 13:42:20.406203 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9647 13:42:20.413115 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9648 13:42:20.416276 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9649 13:42:20.422663 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9650 13:42:20.426248 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9651 13:42:20.432799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9652 13:42:20.436233 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9653 13:42:20.439445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9654 13:42:20.446244 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9655 13:42:20.449786 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9656 13:42:20.455818 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9657 13:42:20.459211 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9658 13:42:20.465813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9659 13:42:20.469151 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9660 13:42:20.472516 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9661 13:42:20.479035 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9662 13:42:20.482312 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9663 13:42:20.485469 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9664 13:42:20.489209 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9665 13:42:20.495433 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9666 13:42:20.498793 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9667 13:42:20.502329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9668 13:42:20.508702 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9669 13:42:20.511903 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9670 13:42:20.518895 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9671 13:42:20.521766 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9672 13:42:20.525592 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9673 13:42:20.531979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9674 13:42:20.535011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9675 13:42:20.538272 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9676 13:42:20.545177 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9677 13:42:20.548278 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9678 13:42:20.551942 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9679 13:42:20.557938 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9680 13:42:20.561597 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9681 13:42:20.568153 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9682 13:42:20.571193 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9683 13:42:20.574550 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9684 13:42:20.580879 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9685 13:42:20.584130 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9686 13:42:20.587459 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9687 13:42:20.594773 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9688 13:42:20.597627 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9689 13:42:20.604090 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9690 13:42:20.607776 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9691 13:42:20.611085 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9692 13:42:20.617412 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9693 13:42:20.620575 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9694 13:42:20.627361 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9695 13:42:20.630637 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9696 13:42:20.633752 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9697 13:42:20.640181 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9698 13:42:20.643465 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9699 13:42:20.647195 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9700 13:42:20.653968 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9701 13:42:20.657009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9702 13:42:20.660256 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9703 13:42:20.666647 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9704 13:42:20.670160 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9705 13:42:20.673379 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9706 13:42:20.676831 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9707 13:42:20.683082 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9708 13:42:20.686454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9709 13:42:20.689744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9710 13:42:20.693054 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9711 13:42:20.699610 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9712 13:42:20.703008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9713 13:42:20.706479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9714 13:42:20.709980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9715 13:42:20.716076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9716 13:42:20.719202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9717 13:42:20.726302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9718 13:42:20.729352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9719 13:42:20.735644 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9720 13:42:20.739451 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9721 13:42:20.742612 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9722 13:42:20.748965 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9723 13:42:20.752728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9724 13:42:20.758811 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9725 13:42:20.762049 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9726 13:42:20.769144 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9727 13:42:20.771964 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9728 13:42:20.775152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9729 13:42:20.782282 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9730 13:42:20.785506 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9731 13:42:20.792161 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9732 13:42:20.794813 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9733 13:42:20.798515 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9734 13:42:20.805032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9735 13:42:20.808550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9736 13:42:20.814910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9737 13:42:20.818396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9738 13:42:20.821698 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9739 13:42:20.828485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9740 13:42:20.831570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9741 13:42:20.837871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9742 13:42:20.841159 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9743 13:42:20.848172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9744 13:42:20.851321 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9745 13:42:20.858138 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9746 13:42:20.861364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9747 13:42:20.864650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9748 13:42:20.870960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9749 13:42:20.874433 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9750 13:42:20.880956 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9751 13:42:20.884105 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9752 13:42:20.887206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9753 13:42:20.894026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9754 13:42:20.897609 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9755 13:42:20.904084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9756 13:42:20.907253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9757 13:42:20.913807 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9758 13:42:20.917294 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9759 13:42:20.920624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9760 13:42:20.927228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9761 13:42:20.930162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9762 13:42:20.936682 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9763 13:42:20.939991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9764 13:42:20.943829 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9765 13:42:20.950040 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9766 13:42:20.953233 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9767 13:42:20.960107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9768 13:42:20.963543 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9769 13:42:20.969941 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9770 13:42:20.973069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9771 13:42:20.977030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9772 13:42:20.983233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9773 13:42:20.986204 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9774 13:42:20.993061 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9775 13:42:20.996271 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9776 13:42:21.003030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9777 13:42:21.006069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9778 13:42:21.009709 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9779 13:42:21.016142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9780 13:42:21.019787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9781 13:42:21.026156 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9782 13:42:21.029435 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9783 13:42:21.032548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9784 13:42:21.038951 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9785 13:42:21.042793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9786 13:42:21.049131 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9787 13:42:21.052124 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9788 13:42:21.058692 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9789 13:42:21.062007 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9790 13:42:21.065188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9791 13:42:21.072001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9792 13:42:21.075135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9793 13:42:21.082142 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9794 13:42:21.085093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9795 13:42:21.091372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9796 13:42:21.095193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9797 13:42:21.101678 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9798 13:42:21.104848 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9799 13:42:21.111160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9800 13:42:21.114753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9801 13:42:21.117779 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9802 13:42:21.124237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9803 13:42:21.127882 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9804 13:42:21.134106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9805 13:42:21.137957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9806 13:42:21.144152 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9807 13:42:21.147173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9808 13:42:21.154119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9809 13:42:21.157283 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9810 13:42:21.160979 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9811 13:42:21.166996 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9812 13:42:21.170415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9813 13:42:21.177063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9814 13:42:21.180233 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9815 13:42:21.186936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9816 13:42:21.190003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9817 13:42:21.196899 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9818 13:42:21.200187 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9819 13:42:21.203164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9820 13:42:21.210163 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9821 13:42:21.213305 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9822 13:42:21.220114 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9823 13:42:21.223292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9824 13:42:21.230067 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9825 13:42:21.233504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9826 13:42:21.236659 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9827 13:42:21.242952 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9828 13:42:21.246464 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9829 13:42:21.252794 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9830 13:42:21.255946 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9831 13:42:21.262602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9832 13:42:21.266174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9833 13:42:21.272554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9834 13:42:21.276243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9835 13:42:21.279275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9836 13:42:21.285539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9837 13:42:21.289135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9838 13:42:21.295912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9839 13:42:21.299029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9840 13:42:21.305298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9841 13:42:21.308624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9842 13:42:21.315680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9843 13:42:21.318954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9844 13:42:21.325184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9845 13:42:21.328609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9846 13:42:21.335492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9847 13:42:21.338437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9848 13:42:21.345210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9849 13:42:21.348376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9850 13:42:21.355310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9851 13:42:21.358501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9852 13:42:21.364691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9853 13:42:21.368590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9854 13:42:21.374706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9855 13:42:21.377812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9856 13:42:21.384812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9857 13:42:21.387872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9858 13:42:21.394323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9859 13:42:21.398142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9860 13:42:21.404787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9861 13:42:21.407791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9862 13:42:21.414293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9863 13:42:21.417395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9864 13:42:21.424257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9865 13:42:21.427447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9866 13:42:21.433902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9867 13:42:21.437191 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9868 13:42:21.440542 INFO: [APUAPC] vio 0
9869 13:42:21.443768 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9870 13:42:21.450156 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9871 13:42:21.453859 INFO: [APUAPC] D0_APC_0: 0x400510
9872 13:42:21.456926 INFO: [APUAPC] D0_APC_1: 0x0
9873 13:42:21.460577 INFO: [APUAPC] D0_APC_2: 0x1540
9874 13:42:21.460660 INFO: [APUAPC] D0_APC_3: 0x0
9875 13:42:21.463801 INFO: [APUAPC] D1_APC_0: 0xffffffff
9876 13:42:21.466744 INFO: [APUAPC] D1_APC_1: 0xffffffff
9877 13:42:21.470594 INFO: [APUAPC] D1_APC_2: 0x3fffff
9878 13:42:21.473631 INFO: [APUAPC] D1_APC_3: 0x0
9879 13:42:21.476571 INFO: [APUAPC] D2_APC_0: 0xffffffff
9880 13:42:21.480486 INFO: [APUAPC] D2_APC_1: 0xffffffff
9881 13:42:21.483647 INFO: [APUAPC] D2_APC_2: 0x3fffff
9882 13:42:21.486721 INFO: [APUAPC] D2_APC_3: 0x0
9883 13:42:21.489859 INFO: [APUAPC] D3_APC_0: 0xffffffff
9884 13:42:21.493165 INFO: [APUAPC] D3_APC_1: 0xffffffff
9885 13:42:21.496470 INFO: [APUAPC] D3_APC_2: 0x3fffff
9886 13:42:21.499589 INFO: [APUAPC] D3_APC_3: 0x0
9887 13:42:21.503556 INFO: [APUAPC] D4_APC_0: 0xffffffff
9888 13:42:21.506460 INFO: [APUAPC] D4_APC_1: 0xffffffff
9889 13:42:21.509644 INFO: [APUAPC] D4_APC_2: 0x3fffff
9890 13:42:21.513562 INFO: [APUAPC] D4_APC_3: 0x0
9891 13:42:21.516744 INFO: [APUAPC] D5_APC_0: 0xffffffff
9892 13:42:21.519744 INFO: [APUAPC] D5_APC_1: 0xffffffff
9893 13:42:21.522858 INFO: [APUAPC] D5_APC_2: 0x3fffff
9894 13:42:21.526363 INFO: [APUAPC] D5_APC_3: 0x0
9895 13:42:21.529371 INFO: [APUAPC] D6_APC_0: 0xffffffff
9896 13:42:21.532643 INFO: [APUAPC] D6_APC_1: 0xffffffff
9897 13:42:21.536282 INFO: [APUAPC] D6_APC_2: 0x3fffff
9898 13:42:21.539306 INFO: [APUAPC] D6_APC_3: 0x0
9899 13:42:21.542598 INFO: [APUAPC] D7_APC_0: 0xffffffff
9900 13:42:21.546041 INFO: [APUAPC] D7_APC_1: 0xffffffff
9901 13:42:21.549230 INFO: [APUAPC] D7_APC_2: 0x3fffff
9902 13:42:21.552333 INFO: [APUAPC] D7_APC_3: 0x0
9903 13:42:21.555838 INFO: [APUAPC] D8_APC_0: 0xffffffff
9904 13:42:21.558879 INFO: [APUAPC] D8_APC_1: 0xffffffff
9905 13:42:21.562619 INFO: [APUAPC] D8_APC_2: 0x3fffff
9906 13:42:21.565695 INFO: [APUAPC] D8_APC_3: 0x0
9907 13:42:21.569131 INFO: [APUAPC] D9_APC_0: 0xffffffff
9908 13:42:21.572109 INFO: [APUAPC] D9_APC_1: 0xffffffff
9909 13:42:21.575307 INFO: [APUAPC] D9_APC_2: 0x3fffff
9910 13:42:21.578946 INFO: [APUAPC] D9_APC_3: 0x0
9911 13:42:21.581895 INFO: [APUAPC] D10_APC_0: 0xffffffff
9912 13:42:21.585155 INFO: [APUAPC] D10_APC_1: 0xffffffff
9913 13:42:21.588423 INFO: [APUAPC] D10_APC_2: 0x3fffff
9914 13:42:21.592249 INFO: [APUAPC] D10_APC_3: 0x0
9915 13:42:21.595581 INFO: [APUAPC] D11_APC_0: 0xffffffff
9916 13:42:21.598643 INFO: [APUAPC] D11_APC_1: 0xffffffff
9917 13:42:21.601753 INFO: [APUAPC] D11_APC_2: 0x3fffff
9918 13:42:21.605427 INFO: [APUAPC] D11_APC_3: 0x0
9919 13:42:21.608628 INFO: [APUAPC] D12_APC_0: 0xffffffff
9920 13:42:21.611589 INFO: [APUAPC] D12_APC_1: 0xffffffff
9921 13:42:21.615417 INFO: [APUAPC] D12_APC_2: 0x3fffff
9922 13:42:21.618620 INFO: [APUAPC] D12_APC_3: 0x0
9923 13:42:21.621742 INFO: [APUAPC] D13_APC_0: 0xffffffff
9924 13:42:21.624855 INFO: [APUAPC] D13_APC_1: 0xffffffff
9925 13:42:21.628046 INFO: [APUAPC] D13_APC_2: 0x3fffff
9926 13:42:21.631317 INFO: [APUAPC] D13_APC_3: 0x0
9927 13:42:21.634522 INFO: [APUAPC] D14_APC_0: 0xffffffff
9928 13:42:21.638135 INFO: [APUAPC] D14_APC_1: 0xffffffff
9929 13:42:21.641151 INFO: [APUAPC] D14_APC_2: 0x3fffff
9930 13:42:21.644515 INFO: [APUAPC] D14_APC_3: 0x0
9931 13:42:21.648030 INFO: [APUAPC] D15_APC_0: 0xffffffff
9932 13:42:21.651083 INFO: [APUAPC] D15_APC_1: 0xffffffff
9933 13:42:21.654611 INFO: [APUAPC] D15_APC_2: 0x3fffff
9934 13:42:21.657785 INFO: [APUAPC] D15_APC_3: 0x0
9935 13:42:21.660982 INFO: [APUAPC] APC_CON: 0x4
9936 13:42:21.664560 INFO: [NOCDAPC] D0_APC_0: 0x0
9937 13:42:21.667512 INFO: [NOCDAPC] D0_APC_1: 0x0
9938 13:42:21.671306 INFO: [NOCDAPC] D1_APC_0: 0x0
9939 13:42:21.674361 INFO: [NOCDAPC] D1_APC_1: 0xfff
9940 13:42:21.677846 INFO: [NOCDAPC] D2_APC_0: 0x0
9941 13:42:21.680910 INFO: [NOCDAPC] D2_APC_1: 0xfff
9942 13:42:21.681014 INFO: [NOCDAPC] D3_APC_0: 0x0
9943 13:42:21.684351 INFO: [NOCDAPC] D3_APC_1: 0xfff
9944 13:42:21.687781 INFO: [NOCDAPC] D4_APC_0: 0x0
9945 13:42:21.690981 INFO: [NOCDAPC] D4_APC_1: 0xfff
9946 13:42:21.693993 INFO: [NOCDAPC] D5_APC_0: 0x0
9947 13:42:21.697963 INFO: [NOCDAPC] D5_APC_1: 0xfff
9948 13:42:21.700972 INFO: [NOCDAPC] D6_APC_0: 0x0
9949 13:42:21.704069 INFO: [NOCDAPC] D6_APC_1: 0xfff
9950 13:42:21.707305 INFO: [NOCDAPC] D7_APC_0: 0x0
9951 13:42:21.710498 INFO: [NOCDAPC] D7_APC_1: 0xfff
9952 13:42:21.714120 INFO: [NOCDAPC] D8_APC_0: 0x0
9953 13:42:21.717117 INFO: [NOCDAPC] D8_APC_1: 0xfff
9954 13:42:21.717200 INFO: [NOCDAPC] D9_APC_0: 0x0
9955 13:42:21.720466 INFO: [NOCDAPC] D9_APC_1: 0xfff
9956 13:42:21.723549 INFO: [NOCDAPC] D10_APC_0: 0x0
9957 13:42:21.727247 INFO: [NOCDAPC] D10_APC_1: 0xfff
9958 13:42:21.730192 INFO: [NOCDAPC] D11_APC_0: 0x0
9959 13:42:21.733535 INFO: [NOCDAPC] D11_APC_1: 0xfff
9960 13:42:21.736680 INFO: [NOCDAPC] D12_APC_0: 0x0
9961 13:42:21.740540 INFO: [NOCDAPC] D12_APC_1: 0xfff
9962 13:42:21.743776 INFO: [NOCDAPC] D13_APC_0: 0x0
9963 13:42:21.746800 INFO: [NOCDAPC] D13_APC_1: 0xfff
9964 13:42:21.749845 INFO: [NOCDAPC] D14_APC_0: 0x0
9965 13:42:21.753397 INFO: [NOCDAPC] D14_APC_1: 0xfff
9966 13:42:21.756866 INFO: [NOCDAPC] D15_APC_0: 0x0
9967 13:42:21.760032 INFO: [NOCDAPC] D15_APC_1: 0xfff
9968 13:42:21.763150 INFO: [NOCDAPC] APC_CON: 0x4
9969 13:42:21.766872 INFO: [APUAPC] set_apusys_apc done
9970 13:42:21.766956 INFO: [DEVAPC] devapc_init done
9971 13:42:21.772961 INFO: GICv3 without legacy support detected.
9972 13:42:21.776516 INFO: ARM GICv3 driver initialized in EL3
9973 13:42:21.779638 INFO: Maximum SPI INTID supported: 639
9974 13:42:21.783407 INFO: BL31: Initializing runtime services
9975 13:42:21.789616 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9976 13:42:21.792628 INFO: SPM: enable CPC mode
9977 13:42:21.796104 INFO: mcdi ready for mcusys-off-idle and system suspend
9978 13:42:21.803068 INFO: BL31: Preparing for EL3 exit to normal world
9979 13:42:21.806160 INFO: Entry point address = 0x80000000
9980 13:42:21.809399 INFO: SPSR = 0x8
9981 13:42:21.814089
9982 13:42:21.814185
9983 13:42:21.814251
9984 13:42:21.817204 Starting depthcharge on Spherion...
9985 13:42:21.817339
9986 13:42:21.817448 Wipe memory regions:
9987 13:42:21.817510
9988 13:42:21.818087 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9989 13:42:21.818187 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9990 13:42:21.818271 Setting prompt string to ['asurada:']
9991 13:42:21.818349 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
9992 13:42:21.820329 [0x00000040000000, 0x00000054600000)
9993 13:42:21.942614
9994 13:42:21.942744 [0x00000054660000, 0x00000080000000)
9995 13:42:22.203605
9996 13:42:22.203788 [0x000000821a7280, 0x000000ffe64000)
9997 13:42:22.948042
9998 13:42:22.948182 [0x00000100000000, 0x00000240000000)
9999 13:42:24.838895
10000 13:42:24.841801 Initializing XHCI USB controller at 0x11200000.
10001 13:42:25.880505
10002 13:42:25.883672 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10003 13:42:25.883761
10004 13:42:25.883827
10005 13:42:25.884111 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10007 13:42:25.984472 asurada: tftpboot 192.168.201.1 14063119/tftp-deploy-3bwkfllz/kernel/image.itb 14063119/tftp-deploy-3bwkfllz/kernel/cmdline
10008 13:42:25.984598 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10009 13:42:25.984738 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10010 13:42:25.989054 tftpboot 192.168.201.1 14063119/tftp-deploy-3bwkfllz/kernel/image.itp-deploy-3bwkfllz/kernel/cmdline
10011 13:42:25.989140
10012 13:42:25.989206 Waiting for link
10013 13:42:26.146905
10014 13:42:26.147028 R8152: Initializing
10015 13:42:26.147118
10016 13:42:26.150040 Version 6 (ocp_data = 5c30)
10017 13:42:26.150124
10018 13:42:26.153200 R8152: Done initializing
10019 13:42:26.153321
10020 13:42:26.153388 Adding net device
10021 13:42:28.090126
10022 13:42:28.090276 done.
10023 13:42:28.090347
10024 13:42:28.090410 MAC: 00:24:32:30:7c:7b
10025 13:42:28.090470
10026 13:42:28.093920 Sending DHCP discover... done.
10027 13:42:28.094006
10028 13:42:28.097069 Waiting for reply... done.
10029 13:42:28.097178
10030 13:42:28.100123 Sending DHCP request... done.
10031 13:42:28.100207
10032 13:42:28.105747 Waiting for reply... done.
10033 13:42:28.105833
10034 13:42:28.105899 My ip is 192.168.201.14
10035 13:42:28.105961
10036 13:42:28.108796 The DHCP server ip is 192.168.201.1
10037 13:42:28.108881
10038 13:42:28.115020 TFTP server IP predefined by user: 192.168.201.1
10039 13:42:28.115104
10040 13:42:28.121720 Bootfile predefined by user: 14063119/tftp-deploy-3bwkfllz/kernel/image.itb
10041 13:42:28.121804
10042 13:42:28.125419 Sending tftp read request... done.
10043 13:42:28.125505
10044 13:42:28.129040 Waiting for the transfer...
10045 13:42:28.129124
10046 13:42:28.671024 00000000 ################################################################
10047 13:42:28.671180
10048 13:42:29.221488 00080000 ################################################################
10049 13:42:29.221626
10050 13:42:29.760847 00100000 ################################################################
10051 13:42:29.760984
10052 13:42:30.319324 00180000 ################################################################
10053 13:42:30.319464
10054 13:42:30.862368 00200000 ################################################################
10055 13:42:30.862511
10056 13:42:31.405325 00280000 ################################################################
10057 13:42:31.405460
10058 13:42:31.950616 00300000 ################################################################
10059 13:42:31.950752
10060 13:42:32.489901 00380000 ################################################################
10061 13:42:32.490073
10062 13:42:33.058623 00400000 ################################################################
10063 13:42:33.058785
10064 13:42:33.609314 00480000 ################################################################
10065 13:42:33.609451
10066 13:42:34.150748 00500000 ################################################################
10067 13:42:34.150896
10068 13:42:34.689129 00580000 ################################################################
10069 13:42:34.689359
10070 13:42:35.238750 00600000 ################################################################
10071 13:42:35.238896
10072 13:42:35.791938 00680000 ################################################################
10073 13:42:35.792091
10074 13:42:36.334102 00700000 ################################################################
10075 13:42:36.334261
10076 13:42:36.878238 00780000 ################################################################
10077 13:42:36.878388
10078 13:42:37.419882 00800000 ################################################################
10079 13:42:37.420045
10080 13:42:37.958047 00880000 ################################################################
10081 13:42:37.958196
10082 13:42:38.503327 00900000 ################################################################
10083 13:42:38.503506
10084 13:42:39.043139 00980000 ################################################################
10085 13:42:39.043290
10086 13:42:39.583458 00a00000 ################################################################
10087 13:42:39.583607
10088 13:42:40.126170 00a80000 ################################################################
10089 13:42:40.126321
10090 13:42:40.671502 00b00000 ################################################################
10091 13:42:40.671651
10092 13:42:41.207916 00b80000 ################################################################
10093 13:42:41.208058
10094 13:42:41.747240 00c00000 ################################################################
10095 13:42:41.747390
10096 13:42:42.299479 00c80000 ################################################################
10097 13:42:42.299629
10098 13:42:42.859117 00d00000 ################################################################
10099 13:42:42.859258
10100 13:42:43.397841 00d80000 ################################################################
10101 13:42:43.397994
10102 13:42:43.938651 00e00000 ################################################################
10103 13:42:43.938801
10104 13:42:44.481285 00e80000 ################################################################
10105 13:42:44.481440
10106 13:42:45.030924 00f00000 ################################################################
10107 13:42:45.031069
10108 13:42:45.591119 00f80000 ################################################################
10109 13:42:45.591264
10110 13:42:46.137462 01000000 ################################################################
10111 13:42:46.137676
10112 13:42:46.686876 01080000 ################################################################
10113 13:42:46.687017
10114 13:42:47.234058 01100000 ################################################################
10115 13:42:47.234239
10116 13:42:47.782041 01180000 ################################################################
10117 13:42:47.782193
10118 13:42:48.339748 01200000 ################################################################
10119 13:42:48.339895
10120 13:42:48.888196 01280000 ################################################################
10121 13:42:48.888335
10122 13:42:49.433963 01300000 ################################################################
10123 13:42:49.434106
10124 13:42:49.981032 01380000 ################################################################
10125 13:42:49.981182
10126 13:42:50.495223 01400000 ################################################################
10127 13:42:50.495370
10128 13:42:51.006921 01480000 ################################################################
10129 13:42:51.007079
10130 13:42:51.539114 01500000 ################################################################
10131 13:42:51.539266
10132 13:42:52.080349 01580000 ################################################################
10133 13:42:52.080499
10134 13:42:52.602883 01600000 ################################################################
10135 13:42:52.603036
10136 13:42:53.128737 01680000 ################################################################
10137 13:42:53.128919
10138 13:42:53.648597 01700000 ################################################################
10139 13:42:53.648751
10140 13:42:54.169188 01780000 ################################################################
10141 13:42:54.169375
10142 13:42:54.685468 01800000 ################################################################
10143 13:42:54.685612
10144 13:42:55.204220 01880000 ################################################################
10145 13:42:55.204370
10146 13:42:55.721942 01900000 ################################################################
10147 13:42:55.722090
10148 13:42:56.247835 01980000 ################################################################
10149 13:42:56.248020
10150 13:42:56.785846 01a00000 ################################################################
10151 13:42:56.786073
10152 13:42:57.328694 01a80000 ################################################################
10153 13:42:57.328844
10154 13:42:57.876399 01b00000 ################################################################
10155 13:42:57.876544
10156 13:42:58.432063 01b80000 ################################################################
10157 13:42:58.432305
10158 13:42:58.984714 01c00000 ################################################################
10159 13:42:58.984868
10160 13:42:59.531808 01c80000 ################################################################
10161 13:42:59.532016
10162 13:43:00.079831 01d00000 ################################################################
10163 13:43:00.079981
10164 13:43:00.625530 01d80000 ################################################################
10165 13:43:00.625675
10166 13:43:01.173365 01e00000 ################################################################
10167 13:43:01.173533
10168 13:43:01.727136 01e80000 ################################################################
10169 13:43:01.727363
10170 13:43:02.267299 01f00000 ################################################################
10171 13:43:02.267455
10172 13:43:02.814751 01f80000 ################################################################
10173 13:43:02.814907
10174 13:43:03.362363 02000000 ################################################################
10175 13:43:03.362543
10176 13:43:03.929689 02080000 ################################################################
10177 13:43:03.929870
10178 13:43:04.476832 02100000 ################################################################
10179 13:43:04.476984
10180 13:43:05.018516 02180000 ################################################################
10181 13:43:05.018668
10182 13:43:05.563673 02200000 ################################################################
10183 13:43:05.563833
10184 13:43:06.114825 02280000 ################################################################
10185 13:43:06.115021
10186 13:43:06.698213 02300000 ################################################################
10187 13:43:06.698374
10188 13:43:07.322646 02380000 ################################################################
10189 13:43:07.322795
10190 13:43:07.886637 02400000 ################################################################
10191 13:43:07.886791
10192 13:43:08.481829 02480000 ################################################################
10193 13:43:08.481973
10194 13:43:09.117136 02500000 ################################################################
10195 13:43:09.117693
10196 13:43:09.827035 02580000 ################################################################
10197 13:43:09.827564
10198 13:43:10.532084 02600000 ################################################################
10199 13:43:10.532597
10200 13:43:11.241836 02680000 ################################################################
10201 13:43:11.242386
10202 13:43:11.911650 02700000 ################################################################
10203 13:43:11.911783
10204 13:43:12.474689 02780000 ################################################################
10205 13:43:12.474854
10206 13:43:13.103633 02800000 ################################################################
10207 13:43:13.104191
10208 13:43:13.811647 02880000 ################################################################
10209 13:43:13.812308
10210 13:43:14.499733 02900000 ################################################################
10211 13:43:14.500248
10212 13:43:15.194688 02980000 ################################################################
10213 13:43:15.195269
10214 13:43:15.892761 02a00000 ################################################################
10215 13:43:15.893505
10216 13:43:16.471594 02a80000 ################################################################
10217 13:43:16.471826
10218 13:43:17.113159 02b00000 ################################################################
10219 13:43:17.113720
10220 13:43:17.782990 02b80000 ################################################################
10221 13:43:17.783504
10222 13:43:18.506038 02c00000 ################################################################
10223 13:43:18.506583
10224 13:43:19.199796 02c80000 ################################################################
10225 13:43:19.200326
10226 13:43:19.912611 02d00000 ################################################################
10227 13:43:19.913125
10228 13:43:20.636785 02d80000 ################################################################
10229 13:43:20.637331
10230 13:43:21.352433 02e00000 ################################################################
10231 13:43:21.352975
10232 13:43:22.045319 02e80000 ################################################################
10233 13:43:22.046003
10234 13:43:22.751972 02f00000 ################################################################
10235 13:43:22.752482
10236 13:43:23.459917 02f80000 ################################################################
10237 13:43:23.460411
10238 13:43:24.013620 03000000 ################################################################
10239 13:43:24.013781
10240 13:43:24.529102 03080000 ################################################################
10241 13:43:24.529290
10242 13:43:25.046872 03100000 ################################################################
10243 13:43:25.047047
10244 13:43:25.571521 03180000 ################################################################
10245 13:43:25.571653
10246 13:43:26.120371 03200000 ################################################################
10247 13:43:26.120537
10248 13:43:26.676249 03280000 ################################################################
10249 13:43:26.676462
10250 13:43:27.232707 03300000 ################################################################
10251 13:43:27.232842
10252 13:43:27.554756 03380000 ####################################### done.
10253 13:43:27.554921
10254 13:43:27.558176 The bootfile was 54314114 bytes long.
10255 13:43:27.558287
10256 13:43:27.561449 Sending tftp read request... done.
10257 13:43:27.561591
10258 13:43:27.564951 Waiting for the transfer...
10259 13:43:27.565039
10260 13:43:27.565107 00000000 # done.
10261 13:43:27.565173
10262 13:43:27.574826 Command line loaded dynamically from TFTP file: 14063119/tftp-deploy-3bwkfllz/kernel/cmdline
10263 13:43:27.574913
10264 13:43:27.588094 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10265 13:43:27.588183
10266 13:43:27.588250 Loading FIT.
10267 13:43:27.588313
10268 13:43:27.590996 Image ramdisk-1 has 41203518 bytes.
10269 13:43:27.591080
10270 13:43:27.594248 Image fdt-1 has 47258 bytes.
10271 13:43:27.594331
10272 13:43:27.597466 Image kernel-1 has 13061303 bytes.
10273 13:43:27.597550
10274 13:43:27.604327 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10275 13:43:27.604411
10276 13:43:27.624050 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10277 13:43:27.624147
10278 13:43:27.627640 Choosing best match conf-1 for compat google,spherion-rev2.
10279 13:43:27.632828
10280 13:43:27.637842 Connected to device vid:did:rid of 1ae0:0028:00
10281 13:43:27.645644
10282 13:43:27.649299 tpm_get_response: command 0x17b, return code 0x0
10283 13:43:27.649383
10284 13:43:27.652629 ec_init: CrosEC protocol v3 supported (256, 248)
10285 13:43:27.656398
10286 13:43:27.660202 tpm_cleanup: add release locality here.
10287 13:43:27.660319
10288 13:43:27.660385 Shutting down all USB controllers.
10289 13:43:27.663492
10290 13:43:27.663616 Removing current net device
10291 13:43:27.663713
10292 13:43:27.669515 Exiting depthcharge with code 4 at timestamp: 95079580
10293 13:43:27.669599
10294 13:43:27.673297 LZMA decompressing kernel-1 to 0x821a6718
10295 13:43:27.673380
10296 13:43:27.676455 LZMA decompressing kernel-1 to 0x40000000
10297 13:43:29.287098
10298 13:43:29.287236 jumping to kernel
10299 13:43:29.288211 end: 2.2.4 bootloader-commands (duration 00:01:07) [common]
10300 13:43:29.288344 start: 2.2.5 auto-login-action (timeout 00:03:19) [common]
10301 13:43:29.288434 Setting prompt string to ['Linux version [0-9]']
10302 13:43:29.288512 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10303 13:43:29.288621 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10304 13:43:29.370406
10305 13:43:29.373448 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10306 13:43:29.376820 start: 2.2.5.1 login-action (timeout 00:03:19) [common]
10307 13:43:29.376929 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10308 13:43:29.377004 Setting prompt string to []
10309 13:43:29.377082 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10310 13:43:29.377160 Using line separator: #'\n'#
10311 13:43:29.377221 No login prompt set.
10312 13:43:29.377328 Parsing kernel messages
10313 13:43:29.377387 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10314 13:43:29.377491 [login-action] Waiting for messages, (timeout 00:03:19)
10315 13:43:29.377559 Waiting using forced prompt support (timeout 00:01:40)
10316 13:43:29.396737 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10317 13:43:29.400040 [ 0.000000] random: crng init done
10318 13:43:29.406613 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10319 13:43:29.409935 [ 0.000000] efi: UEFI not found.
10320 13:43:29.416211 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10321 13:43:29.422847 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10322 13:43:29.433225 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10323 13:43:29.442925 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10324 13:43:29.449400 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10325 13:43:29.455859 [ 0.000000] printk: bootconsole [mtk8250] enabled
10326 13:43:29.462637 [ 0.000000] NUMA: No NUMA configuration found
10327 13:43:29.469227 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 13:43:29.472611 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10329 13:43:29.475846 [ 0.000000] Zone ranges:
10330 13:43:29.482618 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 13:43:29.486405 [ 0.000000] DMA32 empty
10332 13:43:29.492864 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 13:43:29.495688 [ 0.000000] Movable zone start for each node
10334 13:43:29.499043 [ 0.000000] Early memory node ranges
10335 13:43:29.505610 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 13:43:29.512653 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 13:43:29.519093 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 13:43:29.526006 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 13:43:29.529032 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 13:43:29.538769 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 13:43:29.594133 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 13:43:29.600404 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 13:43:29.607533 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 13:43:29.610639 [ 0.000000] psci: probing for conduit method from DT.
10345 13:43:29.617030 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 13:43:29.620823 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 13:43:29.627450 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 13:43:29.630968 [ 0.000000] psci: SMC Calling Convention v1.2
10349 13:43:29.636937 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10350 13:43:29.640757 [ 0.000000] Detected VIPT I-cache on CPU0
10351 13:43:29.646976 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 13:43:29.653489 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 13:43:29.660116 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 13:43:29.667111 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 13:43:29.674127 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 13:43:29.680485 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 13:43:29.687301 [ 0.000000] alternatives: applying boot alternatives
10358 13:43:29.690254 [ 0.000000] Fallback order for Node 0: 0
10359 13:43:29.697206 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 13:43:29.700226 [ 0.000000] Policy zone: Normal
10361 13:43:29.716860 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10362 13:43:29.726727 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 13:43:29.738388 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 13:43:29.748301 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 13:43:29.755181 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 13:43:29.758715 <6>[ 0.000000] software IO TLB: area num 8.
10367 13:43:29.814794 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 13:43:29.963917 <6>[ 0.000000] Memory: 7923952K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 428816K reserved, 32768K cma-reserved)
10369 13:43:29.970605 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 13:43:29.977010 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 13:43:29.980150 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10372 13:43:29.987152 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 13:43:29.994017 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 13:43:29.997180 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10375 13:43:30.006940 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 13:43:30.013608 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 13:43:30.020409 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 13:43:30.026732 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 13:43:30.029787 <6>[ 0.000000] GICv3: 608 SPIs implemented
10380 13:43:30.033535 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10381 13:43:30.040284 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10382 13:43:30.042987 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 13:43:30.050291 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 13:43:30.063347 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 13:43:30.072800 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 13:43:30.082653 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 13:43:30.090209 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 13:43:30.103570 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 13:43:30.110224 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 13:43:30.116508 <6>[ 0.009177] Console: colour dummy device 80x25
10391 13:43:30.126751 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 13:43:30.133048 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10393 13:43:30.137078 <6>[ 0.029285] LSM: Security Framework initializing
10394 13:43:30.143302 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 13:43:30.153571 <6>[ 0.042037] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 13:43:30.159593 <6>[ 0.051470] cblist_init_generic: Setting adjustable number of callback queues.
10397 13:43:30.166535 <6>[ 0.058915] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 13:43:30.176664 <6>[ 0.065291] cblist_init_generic: Setting adjustable number of callback queues.
10399 13:43:30.183207 <6>[ 0.072719] cblist_init_generic: Setting shift to 3 and lim to 1.
10400 13:43:30.186497 <6>[ 0.079120] rcu: Hierarchical SRCU implementation.
10401 13:43:30.192856 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10402 13:43:30.199855 <6>[ 0.091154] EFI services will not be available.
10403 13:43:30.203213 <6>[ 0.096116] smp: Bringing up secondary CPUs ...
10404 13:43:30.210928 <6>[ 0.101197] Detected VIPT I-cache on CPU1
10405 13:43:30.217924 <6>[ 0.101269] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10406 13:43:30.223941 <6>[ 0.101298] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10407 13:43:30.227790 <6>[ 0.101639] Detected VIPT I-cache on CPU2
10408 13:43:30.234294 <6>[ 0.101688] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10409 13:43:30.240541 <6>[ 0.101704] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10410 13:43:30.247580 <6>[ 0.101961] Detected VIPT I-cache on CPU3
10411 13:43:30.253894 <6>[ 0.102007] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10412 13:43:30.260278 <6>[ 0.102020] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10413 13:43:30.264147 <6>[ 0.102322] CPU features: detected: Spectre-v4
10414 13:43:30.270507 <6>[ 0.102328] CPU features: detected: Spectre-BHB
10415 13:43:30.273695 <6>[ 0.102333] Detected PIPT I-cache on CPU4
10416 13:43:30.280455 <6>[ 0.102391] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10417 13:43:30.286862 <6>[ 0.102407] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10418 13:43:30.293423 <6>[ 0.102700] Detected PIPT I-cache on CPU5
10419 13:43:30.300165 <6>[ 0.102762] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10420 13:43:30.307026 <6>[ 0.102778] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10421 13:43:30.310178 <6>[ 0.103057] Detected PIPT I-cache on CPU6
10422 13:43:30.316777 <6>[ 0.103123] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10423 13:43:30.323700 <6>[ 0.103139] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10424 13:43:30.330116 <6>[ 0.103437] Detected PIPT I-cache on CPU7
10425 13:43:30.337169 <6>[ 0.103501] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10426 13:43:30.343270 <6>[ 0.103517] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10427 13:43:30.346780 <6>[ 0.103564] smp: Brought up 1 node, 8 CPUs
10428 13:43:30.353560 <6>[ 0.244848] SMP: Total of 8 processors activated.
10429 13:43:30.356689 <6>[ 0.249769] CPU features: detected: 32-bit EL0 Support
10430 13:43:30.366911 <6>[ 0.255132] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10431 13:43:30.373565 <6>[ 0.263932] CPU features: detected: Common not Private translations
10432 13:43:30.379805 <6>[ 0.270408] CPU features: detected: CRC32 instructions
10433 13:43:30.382988 <6>[ 0.275759] CPU features: detected: RCpc load-acquire (LDAPR)
10434 13:43:30.390086 <6>[ 0.281756] CPU features: detected: LSE atomic instructions
10435 13:43:30.396512 <6>[ 0.287573] CPU features: detected: Privileged Access Never
10436 13:43:30.402791 <6>[ 0.293353] CPU features: detected: RAS Extension Support
10437 13:43:30.409413 <6>[ 0.298962] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10438 13:43:30.412910 <6>[ 0.306179] CPU: All CPU(s) started at EL2
10439 13:43:30.419438 <6>[ 0.310496] alternatives: applying system-wide alternatives
10440 13:43:30.428855 <6>[ 0.321336] devtmpfs: initialized
10441 13:43:30.444048 <6>[ 0.330308] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10442 13:43:30.450731 <6>[ 0.340270] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10443 13:43:30.457745 <6>[ 0.348279] pinctrl core: initialized pinctrl subsystem
10444 13:43:30.460984 <6>[ 0.354960] DMI not present or invalid.
10445 13:43:30.467399 <6>[ 0.359367] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10446 13:43:30.477553 <6>[ 0.366222] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10447 13:43:30.483796 <6>[ 0.373807] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10448 13:43:30.494031 <6>[ 0.382026] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10449 13:43:30.497174 <6>[ 0.390270] audit: initializing netlink subsys (disabled)
10450 13:43:30.507148 <5>[ 0.395964] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10451 13:43:30.513935 <6>[ 0.396675] thermal_sys: Registered thermal governor 'step_wise'
10452 13:43:30.520618 <6>[ 0.403929] thermal_sys: Registered thermal governor 'power_allocator'
10453 13:43:30.523599 <6>[ 0.410186] cpuidle: using governor menu
10454 13:43:30.530870 <6>[ 0.421144] NET: Registered PF_QIPCRTR protocol family
10455 13:43:30.536850 <6>[ 0.426625] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10456 13:43:30.540136 <6>[ 0.433727] ASID allocator initialised with 32768 entries
10457 13:43:30.547768 <6>[ 0.440314] Serial: AMBA PL011 UART driver
10458 13:43:30.556878 <4>[ 0.449143] Trying to register duplicate clock ID: 134
10459 13:43:30.615213 <6>[ 0.510988] KASLR enabled
10460 13:43:30.629600 <6>[ 0.518771] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10461 13:43:30.636337 <6>[ 0.525787] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10462 13:43:30.642752 <6>[ 0.532274] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10463 13:43:30.649113 <6>[ 0.539276] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10464 13:43:30.656163 <6>[ 0.545764] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10465 13:43:30.662685 <6>[ 0.552770] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10466 13:43:30.668906 <6>[ 0.559256] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10467 13:43:30.675947 <6>[ 0.566261] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10468 13:43:30.678874 <6>[ 0.573791] ACPI: Interpreter disabled.
10469 13:43:30.687374 <6>[ 0.580220] iommu: Default domain type: Translated
10470 13:43:30.694256 <6>[ 0.585332] iommu: DMA domain TLB invalidation policy: strict mode
10471 13:43:30.697564 <5>[ 0.591961] SCSI subsystem initialized
10472 13:43:30.704256 <6>[ 0.596124] usbcore: registered new interface driver usbfs
10473 13:43:30.710919 <6>[ 0.601853] usbcore: registered new interface driver hub
10474 13:43:30.714000 <6>[ 0.607401] usbcore: registered new device driver usb
10475 13:43:30.721114 <6>[ 0.613504] pps_core: LinuxPPS API ver. 1 registered
10476 13:43:30.730827 <6>[ 0.618697] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10477 13:43:30.734424 <6>[ 0.628042] PTP clock support registered
10478 13:43:30.737210 <6>[ 0.632286] EDAC MC: Ver: 3.0.0
10479 13:43:30.745049 <6>[ 0.637434] FPGA manager framework
10480 13:43:30.751239 <6>[ 0.641121] Advanced Linux Sound Architecture Driver Initialized.
10481 13:43:30.754415 <6>[ 0.647899] vgaarb: loaded
10482 13:43:30.761436 <6>[ 0.651048] clocksource: Switched to clocksource arch_sys_counter
10483 13:43:30.764414 <5>[ 0.657486] VFS: Disk quotas dquot_6.6.0
10484 13:43:30.770794 <6>[ 0.661669] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10485 13:43:30.774468 <6>[ 0.668858] pnp: PnP ACPI: disabled
10486 13:43:30.782976 <6>[ 0.675564] NET: Registered PF_INET protocol family
10487 13:43:30.792632 <6>[ 0.681162] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10488 13:43:30.804413 <6>[ 0.693477] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10489 13:43:30.814166 <6>[ 0.702294] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10490 13:43:30.820455 <6>[ 0.710265] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10491 13:43:30.830111 <6>[ 0.718965] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10492 13:43:30.837232 <6>[ 0.728720] TCP: Hash tables configured (established 65536 bind 65536)
10493 13:43:30.843595 <6>[ 0.735588] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 13:43:30.853385 <6>[ 0.742784] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 13:43:30.859818 <6>[ 0.750490] NET: Registered PF_UNIX/PF_LOCAL protocol family
10496 13:43:30.866921 <6>[ 0.756649] RPC: Registered named UNIX socket transport module.
10497 13:43:30.870084 <6>[ 0.762802] RPC: Registered udp transport module.
10498 13:43:30.876759 <6>[ 0.767735] RPC: Registered tcp transport module.
10499 13:43:30.883170 <6>[ 0.772664] RPC: Registered tcp NFSv4.1 backchannel transport module.
10500 13:43:30.886890 <6>[ 0.779329] PCI: CLS 0 bytes, default 64
10501 13:43:30.890182 <6>[ 0.783664] Unpacking initramfs...
10502 13:43:30.913885 <6>[ 0.803242] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10503 13:43:30.923480 <6>[ 0.811893] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10504 13:43:30.927465 <6>[ 0.820733] kvm [1]: IPA Size Limit: 40 bits
10505 13:43:30.933895 <6>[ 0.825262] kvm [1]: GICv3: no GICV resource entry
10506 13:43:30.937170 <6>[ 0.830281] kvm [1]: disabling GICv2 emulation
10507 13:43:30.943652 <6>[ 0.834967] kvm [1]: GIC system register CPU interface enabled
10508 13:43:30.946902 <6>[ 0.841121] kvm [1]: vgic interrupt IRQ18
10509 13:43:30.953222 <6>[ 0.845476] kvm [1]: VHE mode initialized successfully
10510 13:43:30.960103 <5>[ 0.851941] Initialise system trusted keyrings
10511 13:43:30.966302 <6>[ 0.856767] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10512 13:43:30.974318 <6>[ 0.866927] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10513 13:43:30.981018 <5>[ 0.873329] NFS: Registering the id_resolver key type
10514 13:43:30.983958 <5>[ 0.878629] Key type id_resolver registered
10515 13:43:30.990905 <5>[ 0.883043] Key type id_legacy registered
10516 13:43:30.997528 <6>[ 0.887337] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10517 13:43:31.003745 <6>[ 0.894258] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10518 13:43:31.010538 <6>[ 0.901987] 9p: Installing v9fs 9p2000 file system support
10519 13:43:31.047410 <5>[ 0.939730] Key type asymmetric registered
10520 13:43:31.050133 <5>[ 0.944061] Asymmetric key parser 'x509' registered
10521 13:43:31.060365 <6>[ 0.949242] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10522 13:43:31.063717 <6>[ 0.956868] io scheduler mq-deadline registered
10523 13:43:31.066753 <6>[ 0.961635] io scheduler kyber registered
10524 13:43:31.085922 <6>[ 0.978712] EINJ: ACPI disabled.
10525 13:43:31.119234 <4>[ 1.004802] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 13:43:31.128602 <4>[ 1.015472] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 13:43:31.143762 <6>[ 1.036400] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10528 13:43:31.152053 <6>[ 1.044443] printk: console [ttyS0] disabled
10529 13:43:31.179928 <6>[ 1.069072] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10530 13:43:31.186434 <6>[ 1.078559] printk: console [ttyS0] enabled
10531 13:43:31.189895 <6>[ 1.078559] printk: console [ttyS0] enabled
10532 13:43:31.195822 <6>[ 1.087454] printk: bootconsole [mtk8250] disabled
10533 13:43:31.199698 <6>[ 1.087454] printk: bootconsole [mtk8250] disabled
10534 13:43:31.206207 <6>[ 1.098733] SuperH (H)SCI(F) driver initialized
10535 13:43:31.209419 <6>[ 1.104051] msm_serial: driver initialized
10536 13:43:31.223586 <6>[ 1.113049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10537 13:43:31.233683 <6>[ 1.121598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10538 13:43:31.240615 <6>[ 1.130141] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10539 13:43:31.250173 <6>[ 1.138769] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10540 13:43:31.260548 <6>[ 1.147476] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10541 13:43:31.266909 <6>[ 1.156191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10542 13:43:31.276419 <6>[ 1.164739] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10543 13:43:31.283082 <6>[ 1.173546] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10544 13:43:31.293421 <6>[ 1.182091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10545 13:43:31.305075 <6>[ 1.197828] loop: module loaded
10546 13:43:31.312018 <6>[ 1.203914] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10547 13:43:31.334576 <4>[ 1.227344] mtk-pmic-keys: Failed to locate of_node [id: -1]
10548 13:43:31.341475 <6>[ 1.234128] megasas: 07.719.03.00-rc1
10549 13:43:31.351309 <6>[ 1.243772] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10550 13:43:31.357785 <6>[ 1.250419] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10551 13:43:31.374179 <6>[ 1.266947] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10552 13:43:31.430425 <6>[ 1.316777] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10553 13:43:32.621206 <6>[ 2.513361] Freeing initrd memory: 40232K
10554 13:43:32.632405 <6>[ 2.524870] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10555 13:43:32.643546 <6>[ 2.535877] tun: Universal TUN/TAP device driver, 1.6
10556 13:43:32.647110 <6>[ 2.541937] thunder_xcv, ver 1.0
10557 13:43:32.649930 <6>[ 2.545441] thunder_bgx, ver 1.0
10558 13:43:32.653239 <6>[ 2.548935] nicpf, ver 1.0
10559 13:43:32.664353 <6>[ 2.552951] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10560 13:43:32.667523 <6>[ 2.560427] hns3: Copyright (c) 2017 Huawei Corporation.
10561 13:43:32.674144 <6>[ 2.566015] hclge is initializing
10562 13:43:32.677010 <6>[ 2.569589] e1000: Intel(R) PRO/1000 Network Driver
10563 13:43:32.683633 <6>[ 2.574718] e1000: Copyright (c) 1999-2006 Intel Corporation.
10564 13:43:32.687029 <6>[ 2.580734] e1000e: Intel(R) PRO/1000 Network Driver
10565 13:43:32.693363 <6>[ 2.585950] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10566 13:43:32.700490 <6>[ 2.592137] igb: Intel(R) Gigabit Ethernet Network Driver
10567 13:43:32.706411 <6>[ 2.597787] igb: Copyright (c) 2007-2014 Intel Corporation.
10568 13:43:32.713536 <6>[ 2.603624] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10569 13:43:32.720009 <6>[ 2.610142] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10570 13:43:32.723216 <6>[ 2.616605] sky2: driver version 1.30
10571 13:43:32.729389 <6>[ 2.621527] usbcore: registered new device driver r8152-cfgselector
10572 13:43:32.736253 <6>[ 2.628061] usbcore: registered new interface driver r8152
10573 13:43:32.742737 <6>[ 2.633883] VFIO - User Level meta-driver version: 0.3
10574 13:43:32.750110 <6>[ 2.642098] usbcore: registered new interface driver usb-storage
10575 13:43:32.756227 <6>[ 2.648552] usbcore: registered new device driver onboard-usb-hub
10576 13:43:32.765403 <6>[ 2.657696] mt6397-rtc mt6359-rtc: registered as rtc0
10577 13:43:32.774988 <6>[ 2.663174] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:43:32 UTC (1716903812)
10578 13:43:32.778276 <6>[ 2.672777] i2c_dev: i2c /dev entries driver
10579 13:43:32.795380 <6>[ 2.684436] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10580 13:43:32.801828 <4>[ 2.693156] cpu cpu0: supply cpu not found, using dummy regulator
10581 13:43:32.808409 <4>[ 2.699583] cpu cpu1: supply cpu not found, using dummy regulator
10582 13:43:32.814874 <4>[ 2.705988] cpu cpu2: supply cpu not found, using dummy regulator
10583 13:43:32.821471 <4>[ 2.712386] cpu cpu3: supply cpu not found, using dummy regulator
10584 13:43:32.828463 <4>[ 2.718785] cpu cpu4: supply cpu not found, using dummy regulator
10585 13:43:32.834923 <4>[ 2.725185] cpu cpu5: supply cpu not found, using dummy regulator
10586 13:43:32.841471 <4>[ 2.731600] cpu cpu6: supply cpu not found, using dummy regulator
10587 13:43:32.847891 <4>[ 2.737996] cpu cpu7: supply cpu not found, using dummy regulator
10588 13:43:32.866311 <6>[ 2.758629] cpu cpu0: EM: created perf domain
10589 13:43:32.869548 <6>[ 2.763540] cpu cpu4: EM: created perf domain
10590 13:43:32.876937 <6>[ 2.769101] sdhci: Secure Digital Host Controller Interface driver
10591 13:43:32.883563 <6>[ 2.775533] sdhci: Copyright(c) Pierre Ossman
10592 13:43:32.889591 <6>[ 2.780492] Synopsys Designware Multimedia Card Interface Driver
10593 13:43:32.896822 <6>[ 2.787127] sdhci-pltfm: SDHCI platform and OF driver helper
10594 13:43:32.899506 <6>[ 2.787248] mmc0: CQHCI version 5.10
10595 13:43:32.906282 <6>[ 2.797026] ledtrig-cpu: registered to indicate activity on CPUs
10596 13:43:32.913030 <6>[ 2.803966] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10597 13:43:32.919887 <6>[ 2.811027] usbcore: registered new interface driver usbhid
10598 13:43:32.922848 <6>[ 2.816848] usbhid: USB HID core driver
10599 13:43:32.930172 <6>[ 2.821015] spi_master spi0: will run message pump with realtime priority
10600 13:43:32.973599 <6>[ 2.859116] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10601 13:43:32.991858 <6>[ 2.874179] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10602 13:43:32.998805 <6>[ 2.889528] cros-ec-spi spi0.0: Chrome EC device registered
10603 13:43:33.002317 <6>[ 2.895591] mmc0: Command Queue Engine enabled
10604 13:43:33.008336 <6>[ 2.900335] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10605 13:43:33.015294 <6>[ 2.907901] mmcblk0: mmc0:0001 DA4128 116 GiB
10606 13:43:33.034445 <6>[ 2.923242] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10607 13:43:33.040995 <6>[ 2.924234] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10608 13:43:33.047421 <6>[ 2.933820] NET: Registered PF_PACKET protocol family
10609 13:43:33.051402 <6>[ 2.939667] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10610 13:43:33.057236 <6>[ 2.943853] 9pnet: Installing 9P2000 support
10611 13:43:33.060568 <6>[ 2.949678] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10612 13:43:33.067655 <5>[ 2.953550] Key type dns_resolver registered
10613 13:43:33.074300 <6>[ 2.959387] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10614 13:43:33.077369 <6>[ 2.963688] registered taskstats version 1
10615 13:43:33.080743 <5>[ 2.974162] Loading compiled-in X.509 certificates
10616 13:43:33.109939 <4>[ 2.996087] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 13:43:33.119421 <4>[ 3.006830] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 13:43:33.133992 <6>[ 3.026568] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10619 13:43:33.141131 <6>[ 3.033466] xhci-mtk 11200000.usb: xHCI Host Controller
10620 13:43:33.147549 <6>[ 3.038980] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10621 13:43:33.157353 <6>[ 3.046838] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10622 13:43:33.164379 <6>[ 3.056275] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10623 13:43:33.170470 <6>[ 3.062364] xhci-mtk 11200000.usb: xHCI Host Controller
10624 13:43:33.177323 <6>[ 3.067937] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10625 13:43:33.183921 <6>[ 3.075633] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10626 13:43:33.190936 <6>[ 3.083537] hub 1-0:1.0: USB hub found
10627 13:43:33.194107 <6>[ 3.087568] hub 1-0:1.0: 1 port detected
10628 13:43:33.204476 <6>[ 3.091869] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10629 13:43:33.207735 <6>[ 3.100602] hub 2-0:1.0: USB hub found
10630 13:43:33.210862 <6>[ 3.104622] hub 2-0:1.0: 1 port detected
10631 13:43:33.219162 <6>[ 3.111491] mtk-msdc 11f70000.mmc: Got CD GPIO
10632 13:43:33.232943 <6>[ 3.121839] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10633 13:43:33.239775 <6>[ 3.129872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10634 13:43:33.249624 <4>[ 3.137786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10635 13:43:33.259008 <6>[ 3.147364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10636 13:43:33.265769 <6>[ 3.155442] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10637 13:43:33.272689 <6>[ 3.163462] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10638 13:43:33.282368 <6>[ 3.171384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10639 13:43:33.288900 <6>[ 3.179200] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10640 13:43:33.299058 <6>[ 3.187017] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10641 13:43:33.308681 <6>[ 3.197432] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10642 13:43:33.315485 <6>[ 3.205791] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10643 13:43:33.325837 <6>[ 3.214136] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10644 13:43:33.331671 <6>[ 3.222475] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10645 13:43:33.341820 <6>[ 3.230812] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10646 13:43:33.351785 <6>[ 3.239150] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10647 13:43:33.357987 <6>[ 3.247489] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10648 13:43:33.368117 <6>[ 3.255827] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10649 13:43:33.374903 <6>[ 3.264164] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10650 13:43:33.385123 <6>[ 3.272502] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10651 13:43:33.391429 <6>[ 3.280839] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10652 13:43:33.401087 <6>[ 3.289176] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10653 13:43:33.407705 <6>[ 3.297513] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10654 13:43:33.417473 <6>[ 3.305852] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10655 13:43:33.424078 <6>[ 3.314190] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10656 13:43:33.430899 <6>[ 3.322923] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10657 13:43:33.437624 <6>[ 3.330075] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10658 13:43:33.444482 <6>[ 3.336836] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10659 13:43:33.454471 <6>[ 3.343591] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10660 13:43:33.461003 <6>[ 3.350524] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10661 13:43:33.467487 <6>[ 3.357295] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10662 13:43:33.477127 <6>[ 3.366422] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10663 13:43:33.487481 <6>[ 3.375542] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10664 13:43:33.497466 <6>[ 3.384834] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10665 13:43:33.507025 <6>[ 3.394302] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10666 13:43:33.514057 <6>[ 3.403769] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10667 13:43:33.524112 <6>[ 3.412892] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10668 13:43:33.533864 <6>[ 3.422358] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10669 13:43:33.543304 <6>[ 3.431477] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10670 13:43:33.553770 <6>[ 3.440771] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10671 13:43:33.563556 <6>[ 3.450935] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10672 13:43:33.572974 <6>[ 3.462405] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10673 13:43:33.614162 <6>[ 3.503330] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10674 13:43:33.766879 <6>[ 3.659661] hub 1-1:1.0: USB hub found
10675 13:43:33.770496 <6>[ 3.664050] hub 1-1:1.0: 4 ports detected
10676 13:43:33.779488 <6>[ 3.671816] hub 1-1:1.0: USB hub found
10677 13:43:33.782291 <6>[ 3.676274] hub 1-1:1.0: 4 ports detected
10678 13:43:33.894000 <6>[ 3.783518] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 13:43:33.919657 <6>[ 3.811882] hub 2-1:1.0: USB hub found
10680 13:43:33.922359 <6>[ 3.816338] hub 2-1:1.0: 3 ports detected
10681 13:43:33.931873 <6>[ 3.824141] hub 2-1:1.0: USB hub found
10682 13:43:33.934879 <6>[ 3.828633] hub 2-1:1.0: 3 ports detected
10683 13:43:34.109792 <6>[ 3.999365] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 13:43:34.241782 <6>[ 4.134564] hub 1-1.4:1.0: USB hub found
10685 13:43:34.245853 <6>[ 4.139291] hub 1-1.4:1.0: 2 ports detected
10686 13:43:34.254052 <6>[ 4.146833] hub 1-1.4:1.0: USB hub found
10687 13:43:34.257668 <6>[ 4.151480] hub 1-1.4:1.0: 2 ports detected
10688 13:43:34.321970 <6>[ 4.211552] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10689 13:43:34.430228 <6>[ 4.320010] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 13:43:34.467063 <4>[ 4.356871] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10691 13:43:34.477477 <4>[ 4.366057] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10692 13:43:34.516213 <6>[ 4.408705] r8152 2-1.3:1.0 eth0: v1.12.13
10693 13:43:34.557882 <6>[ 4.447370] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 13:43:34.749945 <6>[ 4.639364] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 13:43:36.105029 <6>[ 5.997713] r8152 2-1.3:1.0 eth0: carrier on
10696 13:43:38.453763 <5>[ 6.019165] Sending DHCP requests .., OK
10697 13:43:38.460935 <6>[ 8.351511] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10698 13:43:38.463893 <6>[ 8.359829] IP-Config: Complete:
10699 13:43:38.477498 <6>[ 8.363327] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10700 13:43:38.483948 <6>[ 8.374035] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10701 13:43:38.490499 <6>[ 8.382653] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10702 13:43:38.497766 <6>[ 8.382662] nameserver0=192.168.201.1
10703 13:43:38.501216 <6>[ 8.394819] clk: Disabling unused clocks
10704 13:43:38.503943 <6>[ 8.400529] ALSA device list:
10705 13:43:38.511140 <6>[ 8.403774] No soundcards found.
10706 13:43:38.518354 <6>[ 8.411277] Freeing unused kernel memory: 8512K
10707 13:43:38.521761 <6>[ 8.416213] Run /init as init process
10708 13:43:38.551543 <6>[ 8.444716] NET: Registered PF_INET6 protocol family
10709 13:43:38.558493 <6>[ 8.451392] Segment Routing with IPv6
10710 13:43:38.561786 <6>[ 8.455324] In-situ OAM (IOAM) with IPv6
10711 13:43:38.602922 <30>[ 8.469356] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10712 13:43:38.609564 <30>[ 8.502421] systemd[1]: Detected architecture arm64.
10713 13:43:38.610131
10714 13:43:38.615986 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10715 13:43:38.616414
10716 13:43:38.630372 <30>[ 8.523393] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10717 13:43:38.768702 <30>[ 8.658493] systemd[1]: Queued start job for default target graphical.target.
10718 13:43:38.795672 <30>[ 8.685406] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10719 13:43:38.802052 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10720 13:43:38.822795 <30>[ 8.712158] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10721 13:43:38.832105 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10722 13:43:38.850589 <30>[ 8.740512] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10723 13:43:38.860271 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10724 13:43:38.877801 <30>[ 8.767780] systemd[1]: Created slice user.slice - User and Session Slice.
10725 13:43:38.884901 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10726 13:43:38.904784 <30>[ 8.791365] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10727 13:43:38.911841 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10728 13:43:38.933935 <30>[ 8.819900] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10729 13:43:38.940349 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10730 13:43:38.968048 <30>[ 8.847656] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10731 13:43:38.977523 <30>[ 8.867569] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10732 13:43:38.984437 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10733 13:43:39.001291 <30>[ 8.891289] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10734 13:43:39.007878 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10735 13:43:39.025749 <30>[ 8.915345] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10736 13:43:39.035350 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10737 13:43:39.050044 <30>[ 8.943445] systemd[1]: Reached target paths.target - Path Units.
10738 13:43:39.060154 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10739 13:43:39.077809 <30>[ 8.967781] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10740 13:43:39.084847 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10741 13:43:39.098515 <30>[ 8.991438] systemd[1]: Reached target slices.target - Slice Units.
10742 13:43:39.108527 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10743 13:43:39.122439 <30>[ 9.015522] systemd[1]: Reached target swap.target - Swaps.
10744 13:43:39.129249 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10745 13:43:39.149831 <30>[ 9.039759] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10746 13:43:39.160126 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10747 13:43:39.178754 <30>[ 9.068292] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10748 13:43:39.188243 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10749 13:43:39.207844 <30>[ 9.097399] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10750 13:43:39.217479 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10751 13:43:39.233901 <30>[ 9.123966] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10752 13:43:39.243592 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10753 13:43:39.262272 <30>[ 9.151937] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10754 13:43:39.268770 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10755 13:43:39.286624 <30>[ 9.176192] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10756 13:43:39.296599 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10757 13:43:39.315254 <30>[ 9.204785] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10758 13:43:39.325333 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10759 13:43:39.341845 <30>[ 9.231828] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10760 13:43:39.351452 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10761 13:43:39.393680 <30>[ 9.283464] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10762 13:43:39.400695 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10763 13:43:39.413400 <30>[ 9.303022] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10764 13:43:39.419924 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10765 13:43:39.465680 <30>[ 9.355454] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10766 13:43:39.472278 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10767 13:43:39.500559 <30>[ 9.383779] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10768 13:43:39.514246 <30>[ 9.404196] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10769 13:43:39.524895 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10770 13:43:39.582042 <30>[ 9.471807] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10771 13:43:39.588575 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10772 13:43:39.618940 <30>[ 9.508549] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10773 13:43:39.632139 Starting [0;1;39mmodpr<6>[ 9.519650] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10774 13:43:39.634989 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10775 13:43:39.693952 <30>[ 9.583889] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10776 13:43:39.700488 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10777 13:43:39.723379 <30>[ 9.612655] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10778 13:43:39.729209 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10779 13:43:39.773534 <30>[ 9.663690] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10780 13:43:39.780705 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10781 13:43:39.806091 <30>[ 9.696059] systemd[1]: Starting systemd-journald.service - Journal Service...
10782 13:43:39.812653 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10783 13:43:39.832885 <30>[ 9.722443] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10784 13:43:39.838976 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10785 13:43:39.864279 <30>[ 9.750554] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10786 13:43:39.870777 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10787 13:43:39.917995 <30>[ 9.808194] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10788 13:43:39.928048 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10789 13:43:39.951223 <30>[ 9.840902] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10790 13:43:39.957669 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10791 13:43:39.981872 <30>[ 9.871816] systemd[1]: Started systemd-journald.service - Journal Service.
10792 13:43:39.988807 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10793 13:43:40.012566 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10794 13:43:40.034455 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10795 13:43:40.054589 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10796 13:43:40.075401 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10797 13:43:40.096691 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10798 13:43:40.117317 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10799 13:43:40.137052 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10800 13:43:40.157019 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10801 13:43:40.177135 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10802 13:43:40.197204 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10803 13:43:40.215042 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10804 13:43:40.239994 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10805 13:43:40.246712 See 'systemctl status systemd-remount-fs.service' for details.
10806 13:43:40.257100 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10807 13:43:40.277107 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10808 13:43:40.326388 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10809 13:43:40.350905 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10810 13:43:40.369221 <46>[ 10.259014] systemd-journald[192]: Received client request to flush runtime journal.
10811 13:43:40.382364 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10812 13:43:40.403022 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10813 13:43:40.425729 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10814 13:43:40.452349 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10815 13:43:40.471157 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10816 13:43:40.490425 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10817 13:43:40.510568 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10818 13:43:40.530351 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10819 13:43:40.590118 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10820 13:43:40.617497 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10821 13:43:40.633353 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10822 13:43:40.653782 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10823 13:43:40.705990 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10824 13:43:40.731671 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10825 13:43:40.756094 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10826 13:43:40.776403 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10827 13:43:40.810177 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10828 13:43:40.848333 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10829 13:43:40.875458 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10830 13:43:40.902561 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10831 13:43:40.939480 <5>[ 10.829914] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10832 13:43:40.949270 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10833 13:43:40.971420 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord S<5>[ 10.863024] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10834 13:43:40.981088 ystem Boot/Shutd<5>[ 10.871309] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10835 13:43:40.985114 own in UTMP.
10836 13:43:40.991512 <4>[ 10.881349] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10837 13:43:40.997625 <6>[ 10.891015] cfg80211: failed to load regulatory.db
10838 13:43:41.009592 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10839 13:43:41.100154 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10840 13:43:41.122198 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10841 13:43:41.141496 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10842 13:43:41.161218 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10843 13:43:41.177904 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10844 13:43:41.184279 <3>[ 11.075501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 13:43:41.193906 <3>[ 11.084457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 13:43:41.204434 <3>[ 11.092925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 13:43:41.217255 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - <3>[ 11.105573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 13:43:41.217347 Timer Units.
10849 13:43:41.224096 <6>[ 11.106588] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10850 13:43:41.233807 <3>[ 11.114940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 13:43:41.240198 <6>[ 11.123818] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10852 13:43:41.250045 <3>[ 11.131872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 13:43:41.256945 <6>[ 11.138396] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10854 13:43:41.266788 <6>[ 11.140559] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10855 13:43:41.273132 <3>[ 11.148637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 13:43:41.280027 <6>[ 11.166622] remoteproc remoteproc0: scp is available
10857 13:43:41.283118 <6>[ 11.168430] mc: Linux media interface: v0.10
10858 13:43:41.293261 <3>[ 11.172857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 13:43:41.296320 <6>[ 11.178085] remoteproc remoteproc0: powering up scp
10860 13:43:41.303283 <6>[ 11.187151] videodev: Linux video capture interface: v2.00
10861 13:43:41.309598 <3>[ 11.188846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 13:43:41.319915 <6>[ 11.190725] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10863 13:43:41.325765 <3>[ 11.195240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 13:43:41.336170 <3>[ 11.195257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10865 13:43:41.342544 <3>[ 11.195260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 13:43:41.352770 <3>[ 11.202458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 13:43:41.358895 <4>[ 11.206936] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10868 13:43:41.365953 <6>[ 11.209622] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10869 13:43:41.372127 <4>[ 11.214417] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10870 13:43:41.378631 <3>[ 11.218051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 13:43:41.388815 <6>[ 11.277360] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10872 13:43:41.395153 <6>[ 11.277413] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10873 13:43:41.398402 <6>[ 11.277420] pci_bus 0000:00: root bus resource [bus 00-ff]
10874 13:43:41.408353 <6>[ 11.277425] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10875 13:43:41.418433 <6>[ 11.277427] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10876 13:43:41.424725 <6>[ 11.277460] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10877 13:43:41.432153 <6>[ 11.277475] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10878 13:43:41.435847 <6>[ 11.277549] pci 0000:00:00.0: supports D1 D2
10879 13:43:41.442410 <6>[ 11.277551] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10880 13:43:41.451837 <6>[ 11.278609] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10881 13:43:41.459001 <6>[ 11.278701] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10882 13:43:41.465102 <6>[ 11.278726] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10883 13:43:41.472098 <6>[ 11.278742] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10884 13:43:41.478544 <6>[ 11.278757] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10885 13:43:41.488337 <3>[ 11.279013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 13:43:41.494829 <3>[ 11.279019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 13:43:41.504579 <3>[ 11.279022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 13:43:41.511596 <3>[ 11.279052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 13:43:41.521232 <4>[ 11.300348] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10890 13:43:41.524451 <4>[ 11.300348] Fallback method does not support PEC.
10891 13:43:41.534889 <6>[ 11.303393] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10892 13:43:41.544453 <6>[ 11.303747] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10893 13:43:41.551279 <6>[ 11.306238] pci 0000:01:00.0: supports D1 D2
10894 13:43:41.558263 <6>[ 11.322630] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10895 13:43:41.565208 <6>[ 11.329773] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10896 13:43:41.576360 <3>[ 11.332879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 13:43:41.582674 <6>[ 11.341526] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10898 13:43:41.589492 <6>[ 11.352098] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10899 13:43:41.596339 <6>[ 11.355950] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10900 13:43:41.603362 <6>[ 11.355960] remoteproc remoteproc0: remote processor scp is now up
10901 13:43:41.610402 <6>[ 11.356243] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10902 13:43:41.613457 <6>[ 11.356876] Bluetooth: Core ver 2.22
10903 13:43:41.620282 <6>[ 11.356972] NET: Registered PF_BLUETOOTH protocol family
10904 13:43:41.626747 <6>[ 11.356974] Bluetooth: HCI device and connection manager initialized
10905 13:43:41.633811 <6>[ 11.356988] Bluetooth: HCI socket layer initialized
10906 13:43:41.637376 <6>[ 11.356992] Bluetooth: L2CAP socket layer initialized
10907 13:43:41.644151 <6>[ 11.356999] Bluetooth: SCO socket layer initialized
10908 13:43:41.650519 <6>[ 11.378722] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10909 13:43:41.660914 <6>[ 11.386805] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10910 13:43:41.667780 <6>[ 11.388752] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10911 13:43:41.677444 <6>[ 11.390048] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10912 13:43:41.684092 <6>[ 11.390143] usbcore: registered new interface driver uvcvideo
10913 13:43:41.690882 <6>[ 11.404048] usbcore: registered new interface driver btusb
10914 13:43:41.701629 <4>[ 11.405097] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10915 13:43:41.708097 <3>[ 11.405112] Bluetooth: hci0: Failed to load firmware file (-2)
10916 13:43:41.711542 <3>[ 11.405114] Bluetooth: hci0: Failed to set up firmware (-2)
10917 13:43:41.721903 <4>[ 11.405117] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10918 13:43:41.731828 <6>[ 11.411046] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10919 13:43:41.738719 <6>[ 11.426848] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10920 13:43:41.748380 <6>[ 11.434761] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10921 13:43:41.755516 <6>[ 11.435394] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10922 13:43:41.761734 <3>[ 11.465065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 13:43:41.771541 <3>[ 11.465901] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10924 13:43:41.778293 <6>[ 11.473237] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10925 13:43:41.785388 <6>[ 11.473250] pci 0000:00:00.0: PCI bridge to [bus 01]
10926 13:43:41.791571 <3>[ 11.475002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 13:43:41.801651 <3>[ 11.475846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10928 13:43:41.811096 <3>[ 11.508665] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 13:43:41.817889 <6>[ 11.510148] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10930 13:43:41.828108 <3>[ 11.534537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 13:43:41.834432 <6>[ 11.536787] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10932 13:43:41.841332 <3>[ 11.563979] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 13:43:41.847554 <6>[ 11.565516] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10934 13:43:41.857560 <3>[ 11.597733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:43:41.864567 <6>[ 11.600018] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10936 13:43:41.871581 <3>[ 11.626644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 13:43:41.878241 <6>[ 11.744305] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10938 13:43:41.884855 <6>[ 11.778496] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10939 13:43:41.895544 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10940 13:43:41.908751 <6>[ 11.802397] mt7921e 0000:01:00.0: ASIC revision: 79610010
10941 13:43:41.915377 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10942 13:43:41.940019 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10943 13:43:41.979734 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10944 13:43:42.009068 <6>[ 11.899683] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10945 13:43:42.012682 <6>[ 11.899683]
10946 13:43:42.022987 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10947 13:43:42.046551 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10948 13:43:42.064141 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10949 13:43:42.100207 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10950 13:43:42.154514 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10951 13:43:42.176277 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10952 13:43:42.195710 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10953 13:43:42.215422 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10954 13:43:42.254801 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10955 13:43:42.282492 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Get<6>[ 12.171482] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10956 13:43:42.285370 ty on ttyS0.
10957 13:43:42.300858 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10958 13:43:42.316061 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10959 13:43:42.335334 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10960 13:43:42.406357 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10961 13:43:42.430942 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10962 13:43:42.455030 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10963 13:43:42.520492 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10964 13:43:42.539325 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10965 13:43:42.562620 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10966 13:43:42.603703
10967 13:43:42.607300 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10968 13:43:42.607388
10969 13:43:42.610442 debian-bookworm-arm64 login: root (automatic login)
10970 13:43:42.610525
10971 13:43:42.623710 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
10972 13:43:42.623794
10973 13:43:42.630734 The programs included with the Debian GNU/Linux system are free software;
10974 13:43:42.637013 the exact distribution terms for each program are described in the
10975 13:43:42.640675 individual files in /usr/share/doc/*/copyright.
10976 13:43:42.640757
10977 13:43:42.646898 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10978 13:43:42.650261 permitted by applicable law.
10979 13:43:42.650650 Matched prompt #10: / #
10981 13:43:42.650859 Setting prompt string to ['/ #']
10982 13:43:42.650951 end: 2.2.5.1 login-action (duration 00:00:13) [common]
10984 13:43:42.651144 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
10985 13:43:42.651232 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
10986 13:43:42.651306 Setting prompt string to ['/ #']
10987 13:43:42.651367 Forcing a shell prompt, looking for ['/ #']
10989 13:43:42.701620 / #
10990 13:43:42.701736 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10991 13:43:42.701828 Waiting using forced prompt support (timeout 00:02:30)
10992 13:43:42.707184
10993 13:43:42.707457 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10994 13:43:42.707555 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
10995 13:43:42.707645 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10996 13:43:42.707733 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
10997 13:43:42.707817 end: 2 depthcharge-action (duration 00:01:54) [common]
10998 13:43:42.707902 start: 3 lava-test-retry (timeout 00:07:44) [common]
10999 13:43:42.707984 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
11000 13:43:42.708061 Using namespace: common
11002 13:43:42.808386 / # #
11003 13:43:42.808645 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11004 13:43:42.813970 #
11005 13:43:42.814393 Using /lava-14063119
11007 13:43:42.915055 / # export SHELL=/bin/sh
11008 13:43:42.921811 export SHELL=/bin/sh
11010 13:43:43.023355 / # . /lava-14063119/environment
11011 13:43:43.029205 . /lava-14063119/environment
11013 13:43:43.131056 / # /lava-14063119/bin/lava-test-runner /lava-14063119/0
11014 13:43:43.131610 Test shell timeout: 10s (minimum of the action and connection timeout)
11015 13:43:43.137052 /lava-14063119/bin/lava-test-runner /lava-14063119/0
11016 13:43:43.143850 <6>[ 13.037533] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11017 13:43:43.162978 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11018 13:43:43.169130 + cd /lava-14063119/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11019 13:43:43.169720 + cat uuid
11020 13:43:43.172051 + UUID=14063119_1.5.2.3.1
11021 13:43:43.172487 + set +x
11022 13:43:43.178920 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14063119_1.5.2.3.1>
11023 13:43:43.179636 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14063119_1.5.2.3.1
11024 13:43:43.180021 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14063119_1.5.2.3.1)
11025 13:43:43.180429 Skipping test definition patterns.
11026 13:43:43.182024 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11027 13:43:43.188641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11028 13:43:43.189076 device: /dev/video2
11029 13:43:43.189725 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11031 13:43:43.202255 <4>[ 13.092289] use of bytesused == 0 is deprecated and will be removed in the future,
11032 13:43:43.205426 <4>[ 13.100140] use the actual size instead.
11033 13:43:43.220664 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11034 13:43:43.230974 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11035 13:43:43.238511
11036 13:43:43.251540 Compliance test for mtk-vcodec-enc device /dev/video2:
11037 13:43:43.258173
11038 13:43:43.270241 Driver Info:
11039 13:43:43.279329 Driver name : mtk-vcodec-enc
11040 13:43:43.297246 Card type : MT8192 video encoder
11041 13:43:43.307702 Bus info : platform:17020000.vcodec
11042 13:43:43.315871 Driver version : 6.1.91
11043 13:43:43.326399 Capabilities : 0x84204000
11044 13:43:43.337757 Video Memory-to-Memory Multiplanar
11045 13:43:43.347331 Streaming
11046 13:43:43.359716 Extended Pix Format
11047 13:43:43.371128 Device Capabilities
11048 13:43:43.383249 Device Caps : 0x04204000
11049 13:43:43.396966 Video Memory-to-Memory Multiplanar
11050 13:43:43.407133 Streaming
11051 13:43:43.421569 Extended Pix Format
11052 13:43:43.431119 Detected Stateful Encoder
11053 13:43:43.446511
11054 13:43:43.457818 Required ioctls:
11055 13:43:43.472104 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11056 13:43:43.472840 test VIDIOC_QUERYCAP: OK
11057 13:43:43.473728 Received signal: <TESTSET> START Required-ioctls
11058 13:43:43.474113 Starting test_set Required-ioctls
11059 13:43:43.495782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11060 13:43:43.496540 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11062 13:43:43.498942 test invalid ioctls: OK
11063 13:43:43.523885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11064 13:43:43.524329
11065 13:43:43.525112 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11067 13:43:43.533086 Allow for multiple opens:
11068 13:43:43.540541 <LAVA_SIGNAL_TESTSET STOP>
11069 13:43:43.541332 Received signal: <TESTSET> STOP
11070 13:43:43.541738 Closing test_set Required-ioctls
11071 13:43:43.550486 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11072 13:43:43.551178 Received signal: <TESTSET> START Allow-for-multiple-opens
11073 13:43:43.551546 Starting test_set Allow-for-multiple-opens
11074 13:43:43.554199 test second /dev/video2 open: OK
11075 13:43:43.575607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11076 13:43:43.576419 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11078 13:43:43.578567 test VIDIOC_QUERYCAP: OK
11079 13:43:43.596748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11080 13:43:43.597443 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11082 13:43:43.600424 test VIDIOC_G/S_PRIORITY: OK
11083 13:43:43.620171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11084 13:43:43.620899 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11086 13:43:43.623486 test for unlimited opens: OK
11087 13:43:43.649144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11088 13:43:43.649230
11089 13:43:43.649504 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11091 13:43:43.658947 Debug ioctls:
11092 13:43:43.665394 <LAVA_SIGNAL_TESTSET STOP>
11093 13:43:43.665648 Received signal: <TESTSET> STOP
11094 13:43:43.665717 Closing test_set Allow-for-multiple-opens
11095 13:43:43.674535 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11096 13:43:43.674789 Received signal: <TESTSET> START Debug-ioctls
11097 13:43:43.674859 Starting test_set Debug-ioctls
11098 13:43:43.678225 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11099 13:43:43.705417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11100 13:43:43.705693 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11102 13:43:43.711872 test VIDIOC_LOG_STATUS: OK (Not Supported)
11103 13:43:43.730812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11104 13:43:43.730900
11105 13:43:43.731136 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11107 13:43:43.741818 Input ioctls:
11108 13:43:43.748925 <LAVA_SIGNAL_TESTSET STOP>
11109 13:43:43.749188 Received signal: <TESTSET> STOP
11110 13:43:43.749272 Closing test_set Debug-ioctls
11111 13:43:43.759096 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11112 13:43:43.759375 Received signal: <TESTSET> START Input-ioctls
11113 13:43:43.759463 Starting test_set Input-ioctls
11114 13:43:43.762153 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11115 13:43:43.786972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11116 13:43:43.787442 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11118 13:43:43.790447 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11119 13:43:43.808877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11120 13:43:43.809678 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11122 13:43:43.815236 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11123 13:43:43.836379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11124 13:43:43.837157 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11126 13:43:43.843360 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11127 13:43:43.864615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11128 13:43:43.865390 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11130 13:43:43.867956 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11131 13:43:43.893826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11132 13:43:43.894626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11134 13:43:43.897475 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11135 13:43:43.922525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11136 13:43:43.923388 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11138 13:43:43.925516 Inputs: 0 Audio Inputs: 0 Tuners: 0
11139 13:43:43.931629
11140 13:43:43.948748 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11141 13:43:43.976033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11142 13:43:43.976790 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11144 13:43:43.982870 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11145 13:43:44.002063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11146 13:43:44.002808 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11148 13:43:44.008331 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11149 13:43:44.025688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11150 13:43:44.026451 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11152 13:43:44.032278 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11153 13:43:44.050392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11154 13:43:44.051087 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11156 13:43:44.056752 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11157 13:43:44.074088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11158 13:43:44.074612
11159 13:43:44.075405 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11161 13:43:44.094663 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11162 13:43:44.120376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11163 13:43:44.121188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11165 13:43:44.126980 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11166 13:43:44.148477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11167 13:43:44.149449 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11169 13:43:44.151573 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11170 13:43:44.172955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11171 13:43:44.173689 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11173 13:43:44.176187 test VIDIOC_G/S_EDID: OK (Not Supported)
11174 13:43:44.198286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11175 13:43:44.198847
11176 13:43:44.199455 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11178 13:43:44.208580 Control ioctls:
11179 13:43:44.217837 <LAVA_SIGNAL_TESTSET STOP>
11180 13:43:44.218517 Received signal: <TESTSET> STOP
11181 13:43:44.218873 Closing test_set Input-ioctls
11182 13:43:44.227911 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11183 13:43:44.228777 Received signal: <TESTSET> START Control-ioctls
11184 13:43:44.229306 Starting test_set Control-ioctls
11185 13:43:44.230925 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11186 13:43:44.259743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11187 13:43:44.260361 test VIDIOC_QUERYCTRL: OK
11188 13:43:44.261199 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11190 13:43:44.279270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11191 13:43:44.280089 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11193 13:43:44.282574 test VIDIOC_G/S_CTRL: OK
11194 13:43:44.305697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11195 13:43:44.306447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11197 13:43:44.308704 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11198 13:43:44.332177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11199 13:43:44.332866 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11201 13:43:44.339019 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11202 13:43:44.346796 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11203 13:43:44.371006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11204 13:43:44.371809 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11206 13:43:44.374492 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11207 13:43:44.391462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11208 13:43:44.392159 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11210 13:43:44.395311 Standard Controls: 16 Private Controls: 0
11211 13:43:44.402238
11212 13:43:44.413453 Format ioctls:
11213 13:43:44.420528 <LAVA_SIGNAL_TESTSET STOP>
11214 13:43:44.421249 Received signal: <TESTSET> STOP
11215 13:43:44.421655 Closing test_set Control-ioctls
11216 13:43:44.430598 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11217 13:43:44.431282 Received signal: <TESTSET> START Format-ioctls
11218 13:43:44.431653 Starting test_set Format-ioctls
11219 13:43:44.433760 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11220 13:43:44.460186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11221 13:43:44.460444 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11223 13:43:44.463995 test VIDIOC_G/S_PARM: OK
11224 13:43:44.481303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11225 13:43:44.481561 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11227 13:43:44.484270 test VIDIOC_G_FBUF: OK (Not Supported)
11228 13:43:44.506147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11229 13:43:44.506426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11231 13:43:44.509197 test VIDIOC_G_FMT: OK
11232 13:43:44.531040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11233 13:43:44.531314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11235 13:43:44.533790 test VIDIOC_TRY_FMT: OK
11236 13:43:44.554953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11237 13:43:44.555245 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11239 13:43:44.561735 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11240 13:43:44.564676 test VIDIOC_S_FMT: FAIL
11241 13:43:44.588149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11242 13:43:44.588423 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11244 13:43:44.591282 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11245 13:43:44.612940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11246 13:43:44.613207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11248 13:43:44.616623 test Cropping: OK
11249 13:43:44.639197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11250 13:43:44.639455 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11252 13:43:44.642007 test Composing: OK (Not Supported)
11253 13:43:44.663544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11254 13:43:44.663808 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11256 13:43:44.666543 test Scaling: OK (Not Supported)
11257 13:43:44.688027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11258 13:43:44.688136
11259 13:43:44.688381 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11261 13:43:44.704791 Codec ioctls:
11262 13:43:44.711951 <LAVA_SIGNAL_TESTSET STOP>
11263 13:43:44.712272 Received signal: <TESTSET> STOP
11264 13:43:44.712368 Closing test_set Format-ioctls
11265 13:43:44.721254 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11266 13:43:44.721528 Received signal: <TESTSET> START Codec-ioctls
11267 13:43:44.721600 Starting test_set Codec-ioctls
11268 13:43:44.724328 test VIDIOC_(TRY_)ENCODER_CMD: OK
11269 13:43:44.745665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11270 13:43:44.745921 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11272 13:43:44.752641 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11273 13:43:44.769396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11274 13:43:44.769653 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11276 13:43:44.776411 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11277 13:43:44.795865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11278 13:43:44.795966
11279 13:43:44.796205 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11281 13:43:44.805880 Buffer ioctls:
11282 13:43:44.815107 <LAVA_SIGNAL_TESTSET STOP>
11283 13:43:44.815361 Received signal: <TESTSET> STOP
11284 13:43:44.815430 Closing test_set Codec-ioctls
11285 13:43:44.826446 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11286 13:43:44.826699 Received signal: <TESTSET> START Buffer-ioctls
11287 13:43:44.826770 Starting test_set Buffer-ioctls
11288 13:43:44.830098 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11289 13:43:44.854232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11290 13:43:44.854492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11292 13:43:44.857219 test CREATE_BUFS maximum buffers: OK
11293 13:43:44.877962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11294 13:43:44.878240 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11296 13:43:44.880925 test VIDIOC_EXPBUF: OK
11297 13:43:44.902312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11298 13:43:44.902570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11300 13:43:44.905985 test Requests: OK (Not Supported)
11301 13:43:44.926740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11302 13:43:44.926826
11303 13:43:44.927062 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11305 13:43:44.936722 Test input 0:
11306 13:43:44.946174
11307 13:43:44.957402 Streaming ioctls:
11308 13:43:44.964897 <LAVA_SIGNAL_TESTSET STOP>
11309 13:43:44.965154 Received signal: <TESTSET> STOP
11310 13:43:44.965224 Closing test_set Buffer-ioctls
11311 13:43:44.976591 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11312 13:43:44.976846 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11313 13:43:44.976915 Starting test_set Streaming-ioctls_Test-input-0
11314 13:43:44.979558 test read/write: OK (Not Supported)
11315 13:43:44.998629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11316 13:43:44.998895 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11318 13:43:45.005078 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11319 13:43:45.011922 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11320 13:43:45.022889 test blocking wait: FAIL
11321 13:43:45.047942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11322 13:43:45.048219 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11324 13:43:45.054238 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11325 13:43:45.059211 test MMAP (select): FAIL
11326 13:43:45.087327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11327 13:43:45.087598 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11329 13:43:45.093654 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11330 13:43:45.097189 test MMAP (epoll): FAIL
11331 13:43:45.122369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11332 13:43:45.122633 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11334 13:43:45.128914 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11335 13:43:45.137536 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11336 13:43:45.146851 test USERPTR (select): FAIL
11337 13:43:45.176690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11338 13:43:45.176957 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11340 13:43:45.183544 test DMABUF: Cannot test, specify --expbuf-device
11341 13:43:45.189949
11342 13:43:45.208023 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11343 13:43:45.211453 <LAVA_TEST_RUNNER EXIT>
11344 13:43:45.211714 ok: lava_test_shell seems to have completed
11345 13:43:45.211795 Marking unfinished test run as failed
11347 13:43:45.212784 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11348 13:43:45.212919 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11349 13:43:45.213057 end: 3 lava-test-retry (duration 00:00:03) [common]
11350 13:43:45.213187 start: 4 finalize (timeout 00:07:42) [common]
11351 13:43:45.213357 start: 4.1 power-off (timeout 00:00:30) [common]
11352 13:43:45.213642 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11353 13:43:45.413601 >> Command sent successfully.
11354 13:43:45.416432 Returned 0 in 0 seconds
11355 13:43:45.517030 end: 4.1 power-off (duration 00:00:00) [common]
11357 13:43:45.518000 start: 4.2 read-feedback (timeout 00:07:42) [common]
11358 13:43:45.518733 Listened to connection for namespace 'common' for up to 1s
11359 13:43:46.519503 Finalising connection for namespace 'common'
11360 13:43:46.519689 Disconnecting from shell: Finalise
11361 13:43:46.519799 / #
11362 13:43:46.620144 end: 4.2 read-feedback (duration 00:00:01) [common]
11363 13:43:46.620323 end: 4 finalize (duration 00:00:01) [common]
11364 13:43:46.620465 Cleaning after the job
11365 13:43:46.620573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/ramdisk
11366 13:43:46.624737 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/kernel
11367 13:43:46.637338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/dtb
11368 13:43:46.637536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063119/tftp-deploy-3bwkfllz/modules
11369 13:43:46.642840 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063119
11370 13:43:46.704440 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063119
11371 13:43:46.704617 Job finished correctly