Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:36:25.051414 lava-dispatcher, installed at version: 2024.03
2 13:36:25.051641 start: 0 validate
3 13:36:25.051788 Start time: 2024-05-28 13:36:25.051780+00:00 (UTC)
4 13:36:25.051922 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:36:25.052062 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 13:36:25.304796 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:36:25.305046 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:36:25.561916 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:36:25.562132 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:37:07.958817 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:37:07.959439 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:37:08.475499 validate duration: 43.42
14 13:37:08.476525 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:37:08.477017 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:37:08.477435 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:37:08.477941 Not decompressing ramdisk as can be used compressed.
18 13:37:08.478311 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 13:37:08.478593 saving as /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/ramdisk/rootfs.cpio.gz
20 13:37:08.478866 total size: 8181887 (7 MB)
21 13:37:14.858916 progress 0 % (0 MB)
22 13:37:14.870535 progress 5 % (0 MB)
23 13:37:14.881159 progress 10 % (0 MB)
24 13:37:14.890716 progress 15 % (1 MB)
25 13:37:14.896530 progress 20 % (1 MB)
26 13:37:14.901499 progress 25 % (1 MB)
27 13:37:14.905346 progress 30 % (2 MB)
28 13:37:14.909012 progress 35 % (2 MB)
29 13:37:14.912157 progress 40 % (3 MB)
30 13:37:14.915233 progress 45 % (3 MB)
31 13:37:14.918017 progress 50 % (3 MB)
32 13:37:14.920719 progress 55 % (4 MB)
33 13:37:14.923024 progress 60 % (4 MB)
34 13:37:14.925459 progress 65 % (5 MB)
35 13:37:14.927574 progress 70 % (5 MB)
36 13:37:14.929773 progress 75 % (5 MB)
37 13:37:14.931829 progress 80 % (6 MB)
38 13:37:14.933977 progress 85 % (6 MB)
39 13:37:14.935981 progress 90 % (7 MB)
40 13:37:14.938146 progress 95 % (7 MB)
41 13:37:14.940149 progress 100 % (7 MB)
42 13:37:14.940345 7 MB downloaded in 6.46 s (1.21 MB/s)
43 13:37:14.940497 end: 1.1.1 http-download (duration 00:00:06) [common]
45 13:37:14.940732 end: 1.1 download-retry (duration 00:00:06) [common]
46 13:37:14.940817 start: 1.2 download-retry (timeout 00:09:54) [common]
47 13:37:14.940919 start: 1.2.1 http-download (timeout 00:09:54) [common]
48 13:37:14.941097 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:37:14.941165 saving as /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/kernel/Image
50 13:37:14.941225 total size: 54682112 (52 MB)
51 13:37:14.941284 No compression specified
52 13:37:14.942360 progress 0 % (0 MB)
53 13:37:14.956027 progress 5 % (2 MB)
54 13:37:14.969862 progress 10 % (5 MB)
55 13:37:14.983999 progress 15 % (7 MB)
56 13:37:14.998056 progress 20 % (10 MB)
57 13:37:15.012068 progress 25 % (13 MB)
58 13:37:15.026086 progress 30 % (15 MB)
59 13:37:15.040055 progress 35 % (18 MB)
60 13:37:15.053898 progress 40 % (20 MB)
61 13:37:15.067533 progress 45 % (23 MB)
62 13:37:15.081517 progress 50 % (26 MB)
63 13:37:15.095339 progress 55 % (28 MB)
64 13:37:15.109587 progress 60 % (31 MB)
65 13:37:15.127122 progress 65 % (33 MB)
66 13:37:15.141256 progress 70 % (36 MB)
67 13:37:15.155070 progress 75 % (39 MB)
68 13:37:15.168813 progress 80 % (41 MB)
69 13:37:15.182631 progress 85 % (44 MB)
70 13:37:15.196466 progress 90 % (46 MB)
71 13:37:15.210617 progress 95 % (49 MB)
72 13:37:15.224129 progress 100 % (52 MB)
73 13:37:15.224385 52 MB downloaded in 0.28 s (184.17 MB/s)
74 13:37:15.224539 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:37:15.224771 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:37:15.224872 start: 1.3 download-retry (timeout 00:09:53) [common]
78 13:37:15.224981 start: 1.3.1 http-download (timeout 00:09:53) [common]
79 13:37:15.225162 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:37:15.225230 saving as /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/dtb/mt8192-asurada-spherion-r0.dtb
81 13:37:15.225304 total size: 47258 (0 MB)
82 13:37:15.225365 No compression specified
83 13:37:15.226478 progress 69 % (0 MB)
84 13:37:15.226753 progress 100 % (0 MB)
85 13:37:15.226933 0 MB downloaded in 0.00 s (27.72 MB/s)
86 13:37:15.227075 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:37:15.227293 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:37:15.227397 start: 1.4 download-retry (timeout 00:09:53) [common]
90 13:37:15.227515 start: 1.4.1 http-download (timeout 00:09:53) [common]
91 13:37:15.227630 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:37:15.227698 saving as /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/modules/modules.tar
93 13:37:15.227758 total size: 8607916 (8 MB)
94 13:37:15.227818 Using unxz to decompress xz
95 13:37:15.231875 progress 0 % (0 MB)
96 13:37:15.252297 progress 5 % (0 MB)
97 13:37:15.277690 progress 10 % (0 MB)
98 13:37:15.303901 progress 15 % (1 MB)
99 13:37:15.328681 progress 20 % (1 MB)
100 13:37:15.354231 progress 25 % (2 MB)
101 13:37:15.379047 progress 30 % (2 MB)
102 13:37:15.402794 progress 35 % (2 MB)
103 13:37:15.428694 progress 40 % (3 MB)
104 13:37:15.453447 progress 45 % (3 MB)
105 13:37:15.477380 progress 50 % (4 MB)
106 13:37:15.502572 progress 55 % (4 MB)
107 13:37:15.527053 progress 60 % (4 MB)
108 13:37:15.550744 progress 65 % (5 MB)
109 13:37:15.576842 progress 70 % (5 MB)
110 13:37:15.603705 progress 75 % (6 MB)
111 13:37:15.627387 progress 80 % (6 MB)
112 13:37:15.651361 progress 85 % (7 MB)
113 13:37:15.675117 progress 90 % (7 MB)
114 13:37:15.704166 progress 95 % (7 MB)
115 13:37:15.732106 progress 100 % (8 MB)
116 13:37:15.737818 8 MB downloaded in 0.51 s (16.09 MB/s)
117 13:37:15.738071 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:37:15.738340 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:37:15.738491 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 13:37:15.738631 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 13:37:15.738721 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:37:15.738813 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 13:37:15.739049 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j
125 13:37:15.739182 makedir: /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin
126 13:37:15.739319 makedir: /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/tests
127 13:37:15.739419 makedir: /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/results
128 13:37:15.739533 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-add-keys
129 13:37:15.739681 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-add-sources
130 13:37:15.739813 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-background-process-start
131 13:37:15.739942 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-background-process-stop
132 13:37:15.740069 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-common-functions
133 13:37:15.740194 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-echo-ipv4
134 13:37:15.740319 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-install-packages
135 13:37:15.740449 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-installed-packages
136 13:37:15.740574 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-os-build
137 13:37:15.740699 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-probe-channel
138 13:37:15.740831 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-probe-ip
139 13:37:15.741031 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-target-ip
140 13:37:15.741160 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-target-mac
141 13:37:15.741284 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-target-storage
142 13:37:15.741445 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-case
143 13:37:15.741607 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-event
144 13:37:15.741734 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-feedback
145 13:37:15.741905 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-raise
146 13:37:15.742057 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-reference
147 13:37:15.742182 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-runner
148 13:37:15.742311 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-set
149 13:37:15.742439 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-test-shell
150 13:37:15.742603 Updating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-install-packages (oe)
151 13:37:15.742761 Updating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/bin/lava-installed-packages (oe)
152 13:37:15.742885 Creating /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/environment
153 13:37:15.742985 LAVA metadata
154 13:37:15.743059 - LAVA_JOB_ID=14063021
155 13:37:15.743124 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:37:15.743226 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:53) [common]
157 13:37:15.743293 skipped lava-vland-overlay
158 13:37:15.743377 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:37:15.743460 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
160 13:37:15.743525 skipped lava-multinode-overlay
161 13:37:15.743598 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:37:15.743683 start: 1.5.2.3 test-definition (timeout 00:09:53) [common]
163 13:37:15.743762 Loading test definitions
164 13:37:15.743855 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:53) [common]
165 13:37:15.743927 Using /lava-14063021 at stage 0
166 13:37:15.744351 uuid=14063021_1.5.2.3.1 testdef=None
167 13:37:15.744458 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:37:15.744546 start: 1.5.2.3.2 test-overlay (timeout 00:09:53) [common]
169 13:37:15.745125 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:37:15.745352 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:53) [common]
172 13:37:15.746093 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:37:15.746465 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
175 13:37:15.747345 runner path: /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/0/tests/0_dmesg test_uuid 14063021_1.5.2.3.1
176 13:37:15.747539 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:37:15.747877 Creating lava-test-runner.conf files
179 13:37:15.747969 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063021/lava-overlay-2om8gd1j/lava-14063021/0 for stage 0
180 13:37:15.748088 - 0_dmesg
181 13:37:15.748219 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:37:15.748335 start: 1.5.2.4 compress-overlay (timeout 00:09:53) [common]
183 13:37:15.755705 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:37:15.755821 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
185 13:37:15.755910 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:37:15.756026 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:37:15.756111 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
188 13:37:15.994505 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 13:37:15.994874 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
190 13:37:15.994984 extracting modules file /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063021/extract-overlay-ramdisk-ahts_qvr/ramdisk
191 13:37:16.210805 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:37:16.210992 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
193 13:37:16.211090 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063021/compress-overlay-79qy_zr4/overlay-1.5.2.4.tar.gz to ramdisk
194 13:37:16.211161 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063021/compress-overlay-79qy_zr4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063021/extract-overlay-ramdisk-ahts_qvr/ramdisk
195 13:37:16.217813 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:37:16.217935 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
197 13:37:16.218030 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:37:16.218126 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
199 13:37:16.218210 Building ramdisk /var/lib/lava/dispatcher/tmp/14063021/extract-overlay-ramdisk-ahts_qvr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063021/extract-overlay-ramdisk-ahts_qvr/ramdisk
200 13:37:16.598781 >> 145117 blocks
201 13:37:18.866505 rename /var/lib/lava/dispatcher/tmp/14063021/extract-overlay-ramdisk-ahts_qvr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/ramdisk/ramdisk.cpio.gz
202 13:37:18.866963 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 13:37:18.867097 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 13:37:18.867203 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 13:37:18.867316 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/kernel/Image']
206 13:37:32.782278 Returned 0 in 13 seconds
207 13:37:32.883022 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/kernel/image.itb
208 13:37:33.275860 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:37:33.276253 output: Created: Tue May 28 14:37:33 2024
210 13:37:33.276333 output: Image 0 (kernel-1)
211 13:37:33.276401 output: Description:
212 13:37:33.276464 output: Created: Tue May 28 14:37:33 2024
213 13:37:33.276526 output: Type: Kernel Image
214 13:37:33.276589 output: Compression: lzma compressed
215 13:37:33.276668 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:37:33.276732 output: Architecture: AArch64
217 13:37:33.276794 output: OS: Linux
218 13:37:33.276852 output: Load Address: 0x00000000
219 13:37:33.276912 output: Entry Point: 0x00000000
220 13:37:33.276970 output: Hash algo: crc32
221 13:37:33.277044 output: Hash value: 0578ee26
222 13:37:33.277112 output: Image 1 (fdt-1)
223 13:37:33.277207 output: Description: mt8192-asurada-spherion-r0
224 13:37:33.277271 output: Created: Tue May 28 14:37:33 2024
225 13:37:33.277343 output: Type: Flat Device Tree
226 13:37:33.277413 output: Compression: uncompressed
227 13:37:33.277468 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:37:33.277523 output: Architecture: AArch64
229 13:37:33.277577 output: Hash algo: crc32
230 13:37:33.277649 output: Hash value: 0f8e4d2e
231 13:37:33.277705 output: Image 2 (ramdisk-1)
232 13:37:33.277758 output: Description: unavailable
233 13:37:33.277812 output: Created: Tue May 28 14:37:33 2024
234 13:37:33.277867 output: Type: RAMDisk Image
235 13:37:33.277920 output: Compression: Unknown Compression
236 13:37:33.277975 output: Data Size: 21345508 Bytes = 20845.22 KiB = 20.36 MiB
237 13:37:33.278029 output: Architecture: AArch64
238 13:37:33.278083 output: OS: Linux
239 13:37:33.278149 output: Load Address: unavailable
240 13:37:33.278206 output: Entry Point: unavailable
241 13:37:33.278260 output: Hash algo: crc32
242 13:37:33.278313 output: Hash value: 049cd8a8
243 13:37:33.278366 output: Default Configuration: 'conf-1'
244 13:37:33.278421 output: Configuration 0 (conf-1)
245 13:37:33.278474 output: Description: mt8192-asurada-spherion-r0
246 13:37:33.278528 output: Kernel: kernel-1
247 13:37:33.278581 output: Init Ramdisk: ramdisk-1
248 13:37:33.278638 output: FDT: fdt-1
249 13:37:33.278703 output: Loadables: kernel-1
250 13:37:33.278786 output:
251 13:37:33.279021 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:37:33.279131 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:37:33.279283 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 13:37:33.279409 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 13:37:33.279519 No LXC device requested
256 13:37:33.279633 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:37:33.279761 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 13:37:33.279872 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:37:33.279975 Checking files for TFTP limit of 4294967296 bytes.
260 13:37:33.280638 end: 1 tftp-deploy (duration 00:00:25) [common]
261 13:37:33.280795 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:37:33.280928 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:37:33.281083 substitutions:
264 13:37:33.281159 - {DTB}: 14063021/tftp-deploy-00ockxyd/dtb/mt8192-asurada-spherion-r0.dtb
265 13:37:33.281245 - {INITRD}: 14063021/tftp-deploy-00ockxyd/ramdisk/ramdisk.cpio.gz
266 13:37:33.281310 - {KERNEL}: 14063021/tftp-deploy-00ockxyd/kernel/Image
267 13:37:33.281370 - {LAVA_MAC}: None
268 13:37:33.281428 - {PRESEED_CONFIG}: None
269 13:37:33.281485 - {PRESEED_LOCAL}: None
270 13:37:33.281541 - {RAMDISK}: 14063021/tftp-deploy-00ockxyd/ramdisk/ramdisk.cpio.gz
271 13:37:33.281597 - {ROOT_PART}: None
272 13:37:33.281653 - {ROOT}: None
273 13:37:33.281708 - {SERVER_IP}: 192.168.201.1
274 13:37:33.281779 - {TEE}: None
275 13:37:33.281836 Parsed boot commands:
276 13:37:33.281891 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:37:33.282075 Parsed boot commands: tftpboot 192.168.201.1 14063021/tftp-deploy-00ockxyd/kernel/image.itb 14063021/tftp-deploy-00ockxyd/kernel/cmdline
278 13:37:33.282166 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:37:33.282266 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:37:33.282365 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:37:33.282454 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:37:33.282527 Not connected, no need to disconnect.
283 13:37:33.282603 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:37:33.282685 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:37:33.282766 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:37:33.286733 Setting prompt string to ['lava-test: # ']
287 13:37:33.287135 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:37:33.287253 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:37:33.287362 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:37:33.287464 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:37:33.287815 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 13:37:38.415851 >> Command sent successfully.
293 13:37:38.418519 Returned 0 in 5 seconds
294 13:37:38.518961 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:37:38.519277 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:37:38.519380 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:37:38.519466 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:37:38.519532 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:37:38.519600 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:37:38.520027 [Enter `^Ec?' for help]
302 13:37:38.694302
303 13:37:38.694465
304 13:37:38.694536 F0: 102B 0000
305 13:37:38.694603
306 13:37:38.694666 F3: 1001 0000 [0200]
307 13:37:38.694724
308 13:37:38.697453 F3: 1001 0000
309 13:37:38.697564
310 13:37:38.697631 F7: 102D 0000
311 13:37:38.697694
312 13:37:38.697796 F1: 0000 0000
313 13:37:38.697872
314 13:37:38.701391 V0: 0000 0000 [0001]
315 13:37:38.701480
316 13:37:38.701547 00: 0007 8000
317 13:37:38.701614
318 13:37:38.704824 01: 0000 0000
319 13:37:38.704914
320 13:37:38.705005 BP: 0C00 0209 [0000]
321 13:37:38.705084
322 13:37:38.705143 G0: 1182 0000
323 13:37:38.708543
324 13:37:38.708631 EC: 0000 0021 [4000]
325 13:37:38.708697
326 13:37:38.712795 S7: 0000 0000 [0000]
327 13:37:38.712880
328 13:37:38.712946 CC: 0000 0000 [0001]
329 13:37:38.713050
330 13:37:38.715627 T0: 0000 0040 [010F]
331 13:37:38.715710
332 13:37:38.715776 Jump to BL
333 13:37:38.715837
334 13:37:38.740862
335 13:37:38.741085
336 13:37:38.747901 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:37:38.751696 ARM64: Exception handlers installed.
338 13:37:38.755291 ARM64: Testing exception
339 13:37:38.759098 ARM64: Done test exception
340 13:37:38.766248 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:37:38.773211 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:37:38.780491 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:37:38.791494 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:37:38.798168 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:37:38.807902 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:37:38.818605 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:37:38.825506 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:37:38.843127 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:37:38.846689 WDT: Last reset was cold boot
350 13:37:38.850418 SPI1(PAD0) initialized at 2873684 Hz
351 13:37:38.853380 SPI5(PAD0) initialized at 992727 Hz
352 13:37:38.857092 VBOOT: Loading verstage.
353 13:37:38.863768 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:37:38.866682 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:37:38.870006 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:37:38.873395 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:37:38.880821 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:37:38.887590 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:37:38.898653 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:37:38.898813
361 13:37:38.898883
362 13:37:38.908607 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:37:38.912117 ARM64: Exception handlers installed.
364 13:37:38.915116 ARM64: Testing exception
365 13:37:38.915232 ARM64: Done test exception
366 13:37:38.922191 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:37:38.925195 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:37:38.940752 Probing TPM: . done!
369 13:37:38.940908 TPM ready after 0 ms
370 13:37:38.948123 Connected to device vid:did:rid of 1ae0:0028:00
371 13:37:38.954392 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:37:39.012350 Initialized TPM device CR50 revision 0
373 13:37:39.022309 tlcl_send_startup: Startup return code is 0
374 13:37:39.022449 TPM: setup succeeded
375 13:37:39.033687 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:37:39.042430 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:37:39.055487 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:37:39.063494 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:37:39.066921 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:37:39.074455 in-header: 03 07 00 00 08 00 00 00
381 13:37:39.078232 in-data: aa e4 47 04 13 02 00 00
382 13:37:39.082020 Chrome EC: UHEPI supported
383 13:37:39.089543 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:37:39.092635 in-header: 03 ad 00 00 08 00 00 00
385 13:37:39.092736 in-data: 00 20 20 08 00 00 00 00
386 13:37:39.096565 Phase 1
387 13:37:39.100260 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:37:39.107427 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:37:39.111047 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 13:37:39.115190 Recovery requested (1009000e)
391 13:37:39.122871 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:37:39.128139 tlcl_extend: response is 0
393 13:37:39.137791 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:37:39.143397 tlcl_extend: response is 0
395 13:37:39.150341 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:37:39.170045 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 13:37:39.177005 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 13:37:39.177173
399 13:37:39.177245
400 13:37:39.187351 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:37:39.191317 ARM64: Exception handlers installed.
402 13:37:39.191440 ARM64: Testing exception
403 13:37:39.194258 ARM64: Done test exception
404 13:37:39.215335 pmic_efuse_setting: Set efuses in 11 msecs
405 13:37:39.219375 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:37:39.226025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:37:39.228918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:37:39.236101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:37:39.239599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:37:39.243220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:37:39.250550 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:37:39.254240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:37:39.257861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:37:39.261272 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:37:39.268992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:37:39.272688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:37:39.276803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:37:39.280108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:37:39.288012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:37:39.294964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:37:39.298755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:37:39.306449 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:37:39.309733 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:37:39.317388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:37:39.320772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:37:39.328869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:37:39.332373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:37:39.339693 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:37:39.343709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:37:39.350964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:37:39.354044 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:37:39.362093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:37:39.365573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:37:39.368889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:37:39.372861 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:37:39.380285 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:37:39.383979 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:37:39.391129 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:37:39.394421 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:37:39.398523 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:37:39.405783 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:37:39.409242 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:37:39.413417 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:37:39.420169 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:37:39.423569 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:37:39.427279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:37:39.430884 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:37:39.438729 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:37:39.442264 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:37:39.446088 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:37:39.449256 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:37:39.453125 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:37:39.456570 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:37:39.463915 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:37:39.467638 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:37:39.471593 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:37:39.478827 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 13:37:39.486402 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:37:39.489811 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:37:39.501128 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:37:39.508485 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:37:39.512114 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:37:39.515662 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:37:39.523046 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:37:39.530714 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 13:37:39.534507 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 13:37:39.538009 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 13:37:39.541705 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:37:39.553275 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 13:37:39.562667 [RTC]rtc_get_frequency_meter,154: input=23, output=979
471 13:37:39.572408 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 13:37:39.581576 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 13:37:39.591155 [RTC]rtc_get_frequency_meter,154: input=16, output=814
474 13:37:39.600622 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 13:37:39.611010 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 13:37:39.614259 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 13:37:39.618151 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 13:37:39.622133 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 13:37:39.629075 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 13:37:39.632702 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 13:37:39.636471 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 13:37:39.640217 ADC[4]: Raw value=900959 ID=7
483 13:37:39.640340 ADC[3]: Raw value=213336 ID=1
484 13:37:39.643516 RAM Code: 0x71
485 13:37:39.647578 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 13:37:39.651009 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 13:37:39.662926 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 13:37:39.666285 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 13:37:39.670029 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 13:37:39.673577 in-header: 03 07 00 00 08 00 00 00
491 13:37:39.677293 in-data: aa e4 47 04 13 02 00 00
492 13:37:39.681112 Chrome EC: UHEPI supported
493 13:37:39.688605 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 13:37:39.691896 in-header: 03 ed 00 00 08 00 00 00
495 13:37:39.691984 in-data: 80 20 60 08 00 00 00 00
496 13:37:39.695785 MRC: failed to locate region type 0.
497 13:37:39.703401 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 13:37:39.707120 DRAM-K: Running full calibration
499 13:37:39.710827 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 13:37:39.714519 header.status = 0x0
501 13:37:39.718515 header.version = 0x6 (expected: 0x6)
502 13:37:39.721865 header.size = 0xd00 (expected: 0xd00)
503 13:37:39.721977 header.flags = 0x0
504 13:37:39.728853 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 13:37:39.747563 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 13:37:39.755175 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 13:37:39.755314 dram_init: ddr_geometry: 2
508 13:37:39.758834 [EMI] MDL number = 2
509 13:37:39.762151 [EMI] Get MDL freq = 0
510 13:37:39.762265 dram_init: ddr_type: 0
511 13:37:39.766226 is_discrete_lpddr4: 1
512 13:37:39.769576 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 13:37:39.769662
514 13:37:39.769727
515 13:37:39.769792 [Bian_co] ETT version 0.0.0.1
516 13:37:39.776781 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 13:37:39.776872
518 13:37:39.780412 dramc_set_vcore_voltage set vcore to 650000
519 13:37:39.780496 Read voltage for 800, 4
520 13:37:39.784117 Vio18 = 0
521 13:37:39.784200 Vcore = 650000
522 13:37:39.784265 Vdram = 0
523 13:37:39.787855 Vddq = 0
524 13:37:39.787937 Vmddr = 0
525 13:37:39.788001 dram_init: config_dvfs: 1
526 13:37:39.795313 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 13:37:39.798863 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 13:37:39.802335 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 13:37:39.808957 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 13:37:39.812066 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 13:37:39.815279 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 13:37:39.815388 MEM_TYPE=3, freq_sel=18
533 13:37:39.818375 sv_algorithm_assistance_LP4_1600
534 13:37:39.825567 ============ PULL DRAM RESETB DOWN ============
535 13:37:39.828701 ========== PULL DRAM RESETB DOWN end =========
536 13:37:39.832097 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 13:37:39.835565 ===================================
538 13:37:39.838603 LPDDR4 DRAM CONFIGURATION
539 13:37:39.842250 ===================================
540 13:37:39.845308 EX_ROW_EN[0] = 0x0
541 13:37:39.845408 EX_ROW_EN[1] = 0x0
542 13:37:39.848956 LP4Y_EN = 0x0
543 13:37:39.849079 WORK_FSP = 0x0
544 13:37:39.852090 WL = 0x2
545 13:37:39.852187 RL = 0x2
546 13:37:39.855382 BL = 0x2
547 13:37:39.855491 RPST = 0x0
548 13:37:39.858895 RD_PRE = 0x0
549 13:37:39.859009 WR_PRE = 0x1
550 13:37:39.862426 WR_PST = 0x0
551 13:37:39.862563 DBI_WR = 0x0
552 13:37:39.865765 DBI_RD = 0x0
553 13:37:39.865848 OTF = 0x1
554 13:37:39.868984 ===================================
555 13:37:39.871986 ===================================
556 13:37:39.875624 ANA top config
557 13:37:39.879102 ===================================
558 13:37:39.879188 DLL_ASYNC_EN = 0
559 13:37:39.882624 ALL_SLAVE_EN = 1
560 13:37:39.885745 NEW_RANK_MODE = 1
561 13:37:39.888761 DLL_IDLE_MODE = 1
562 13:37:39.888851 LP45_APHY_COMB_EN = 1
563 13:37:39.892392 TX_ODT_DIS = 1
564 13:37:39.896024 NEW_8X_MODE = 1
565 13:37:39.899183 ===================================
566 13:37:39.902669 ===================================
567 13:37:39.905874 data_rate = 1600
568 13:37:39.909307 CKR = 1
569 13:37:39.912222 DQ_P2S_RATIO = 8
570 13:37:39.915505 ===================================
571 13:37:39.915594 CA_P2S_RATIO = 8
572 13:37:39.919195 DQ_CA_OPEN = 0
573 13:37:39.922228 DQ_SEMI_OPEN = 0
574 13:37:39.926006 CA_SEMI_OPEN = 0
575 13:37:39.929443 CA_FULL_RATE = 0
576 13:37:39.929564 DQ_CKDIV4_EN = 1
577 13:37:39.932850 CA_CKDIV4_EN = 1
578 13:37:39.935710 CA_PREDIV_EN = 0
579 13:37:39.939263 PH8_DLY = 0
580 13:37:39.942827 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 13:37:39.945763 DQ_AAMCK_DIV = 4
582 13:37:39.945902 CA_AAMCK_DIV = 4
583 13:37:39.949272 CA_ADMCK_DIV = 4
584 13:37:39.952841 DQ_TRACK_CA_EN = 0
585 13:37:39.955931 CA_PICK = 800
586 13:37:39.959517 CA_MCKIO = 800
587 13:37:39.962692 MCKIO_SEMI = 0
588 13:37:39.962779 PLL_FREQ = 3068
589 13:37:39.967048 DQ_UI_PI_RATIO = 32
590 13:37:39.970546 CA_UI_PI_RATIO = 0
591 13:37:39.974052 ===================================
592 13:37:39.977531 ===================================
593 13:37:39.977623 memory_type:LPDDR4
594 13:37:39.981497 GP_NUM : 10
595 13:37:39.981585 SRAM_EN : 1
596 13:37:39.985144 MD32_EN : 0
597 13:37:39.988841 ===================================
598 13:37:39.988935 [ANA_INIT] >>>>>>>>>>>>>>
599 13:37:39.992774 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 13:37:39.996306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 13:37:40.000586 ===================================
602 13:37:40.003858 data_rate = 1600,PCW = 0X7600
603 13:37:40.007536 ===================================
604 13:37:40.010754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 13:37:40.014270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 13:37:40.021130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:37:40.024166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 13:37:40.027745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 13:37:40.030835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:37:40.034443 [ANA_INIT] flow start
611 13:37:40.038020 [ANA_INIT] PLL >>>>>>>>
612 13:37:40.038143 [ANA_INIT] PLL <<<<<<<<
613 13:37:40.041189 [ANA_INIT] MIDPI >>>>>>>>
614 13:37:40.044143 [ANA_INIT] MIDPI <<<<<<<<
615 13:37:40.044279 [ANA_INIT] DLL >>>>>>>>
616 13:37:40.047867 [ANA_INIT] flow end
617 13:37:40.050797 ============ LP4 DIFF to SE enter ============
618 13:37:40.057795 ============ LP4 DIFF to SE exit ============
619 13:37:40.057952 [ANA_INIT] <<<<<<<<<<<<<
620 13:37:40.060675 [Flow] Enable top DCM control >>>>>
621 13:37:40.064335 [Flow] Enable top DCM control <<<<<
622 13:37:40.067554 Enable DLL master slave shuffle
623 13:37:40.074191 ==============================================================
624 13:37:40.074321 Gating Mode config
625 13:37:40.080806 ==============================================================
626 13:37:40.080909 Config description:
627 13:37:40.091472 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 13:37:40.097635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 13:37:40.104325 SELPH_MODE 0: By rank 1: By Phase
630 13:37:40.107794 ==============================================================
631 13:37:40.111143 GAT_TRACK_EN = 1
632 13:37:40.114305 RX_GATING_MODE = 2
633 13:37:40.117841 RX_GATING_TRACK_MODE = 2
634 13:37:40.121135 SELPH_MODE = 1
635 13:37:40.124464 PICG_EARLY_EN = 1
636 13:37:40.127930 VALID_LAT_VALUE = 1
637 13:37:40.131246 ==============================================================
638 13:37:40.134269 Enter into Gating configuration >>>>
639 13:37:40.138011 Exit from Gating configuration <<<<
640 13:37:40.141040 Enter into DVFS_PRE_config >>>>>
641 13:37:40.154874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 13:37:40.158132 Exit from DVFS_PRE_config <<<<<
643 13:37:40.161483 Enter into PICG configuration >>>>
644 13:37:40.161634 Exit from PICG configuration <<<<
645 13:37:40.164853 [RX_INPUT] configuration >>>>>
646 13:37:40.168664 [RX_INPUT] configuration <<<<<
647 13:37:40.174712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 13:37:40.178310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 13:37:40.185497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:37:40.192719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:37:40.199447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 13:37:40.202327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 13:37:40.208953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 13:37:40.212372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 13:37:40.215605 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 13:37:40.219119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 13:37:40.222691 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 13:37:40.229533 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 13:37:40.232477 ===================================
660 13:37:40.232571 LPDDR4 DRAM CONFIGURATION
661 13:37:40.235870 ===================================
662 13:37:40.239821 EX_ROW_EN[0] = 0x0
663 13:37:40.242669 EX_ROW_EN[1] = 0x0
664 13:37:40.242758 LP4Y_EN = 0x0
665 13:37:40.245883 WORK_FSP = 0x0
666 13:37:40.245967 WL = 0x2
667 13:37:40.249343 RL = 0x2
668 13:37:40.249444 BL = 0x2
669 13:37:40.253099 RPST = 0x0
670 13:37:40.253183 RD_PRE = 0x0
671 13:37:40.256259 WR_PRE = 0x1
672 13:37:40.256341 WR_PST = 0x0
673 13:37:40.259457 DBI_WR = 0x0
674 13:37:40.259570 DBI_RD = 0x0
675 13:37:40.262794 OTF = 0x1
676 13:37:40.266232 ===================================
677 13:37:40.269540 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 13:37:40.273016 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 13:37:40.279590 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 13:37:40.283190 ===================================
681 13:37:40.283283 LPDDR4 DRAM CONFIGURATION
682 13:37:40.286703 ===================================
683 13:37:40.289853 EX_ROW_EN[0] = 0x10
684 13:37:40.289940 EX_ROW_EN[1] = 0x0
685 13:37:40.292884 LP4Y_EN = 0x0
686 13:37:40.292991 WORK_FSP = 0x0
687 13:37:40.296356 WL = 0x2
688 13:37:40.296440 RL = 0x2
689 13:37:40.299826 BL = 0x2
690 13:37:40.303358 RPST = 0x0
691 13:37:40.303460 RD_PRE = 0x0
692 13:37:40.306437 WR_PRE = 0x1
693 13:37:40.306522 WR_PST = 0x0
694 13:37:40.310030 DBI_WR = 0x0
695 13:37:40.310114 DBI_RD = 0x0
696 13:37:40.313559 OTF = 0x1
697 13:37:40.316368 ===================================
698 13:37:40.319989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 13:37:40.325146 nWR fixed to 40
700 13:37:40.328738 [ModeRegInit_LP4] CH0 RK0
701 13:37:40.328826 [ModeRegInit_LP4] CH0 RK1
702 13:37:40.332189 [ModeRegInit_LP4] CH1 RK0
703 13:37:40.335341 [ModeRegInit_LP4] CH1 RK1
704 13:37:40.335426 match AC timing 13
705 13:37:40.342124 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 13:37:40.345414 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 13:37:40.348618 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 13:37:40.355344 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 13:37:40.358928 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 13:37:40.359017 [EMI DOE] emi_dcm 0
711 13:37:40.365456 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 13:37:40.365544 ==
713 13:37:40.368865 Dram Type= 6, Freq= 0, CH_0, rank 0
714 13:37:40.372248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 13:37:40.372333 ==
716 13:37:40.378844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 13:37:40.382409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 13:37:40.392818 [CA 0] Center 37 (7~68) winsize 62
719 13:37:40.395779 [CA 1] Center 37 (6~68) winsize 63
720 13:37:40.399431 [CA 2] Center 35 (5~66) winsize 62
721 13:37:40.402496 [CA 3] Center 34 (4~65) winsize 62
722 13:37:40.405953 [CA 4] Center 34 (4~65) winsize 62
723 13:37:40.409713 [CA 5] Center 33 (3~64) winsize 62
724 13:37:40.409802
725 13:37:40.412740 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 13:37:40.412895
727 13:37:40.415794 [CATrainingPosCal] consider 1 rank data
728 13:37:40.419539 u2DelayCellTimex100 = 270/100 ps
729 13:37:40.423145 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 13:37:40.426161 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 13:37:40.432864 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 13:37:40.436171 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:37:40.439412 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 13:37:40.442663 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:37:40.442801
736 13:37:40.446196 CA PerBit enable=1, Macro0, CA PI delay=33
737 13:37:40.446283
738 13:37:40.449331 [CBTSetCACLKResult] CA Dly = 33
739 13:37:40.449433 CS Dly: 4 (0~35)
740 13:37:40.449528 ==
741 13:37:40.453270 Dram Type= 6, Freq= 0, CH_0, rank 1
742 13:37:40.459442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 13:37:40.459553 ==
744 13:37:40.463111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 13:37:40.470135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 13:37:40.478747 [CA 0] Center 37 (6~68) winsize 63
747 13:37:40.482088 [CA 1] Center 37 (7~68) winsize 62
748 13:37:40.485482 [CA 2] Center 35 (5~66) winsize 62
749 13:37:40.489336 [CA 3] Center 34 (4~65) winsize 62
750 13:37:40.492628 [CA 4] Center 34 (3~65) winsize 63
751 13:37:40.496088 [CA 5] Center 33 (3~64) winsize 62
752 13:37:40.496176
753 13:37:40.498973 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 13:37:40.499058
755 13:37:40.502618 [CATrainingPosCal] consider 2 rank data
756 13:37:40.505819 u2DelayCellTimex100 = 270/100 ps
757 13:37:40.509136 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 13:37:40.512998 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:37:40.515847 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 13:37:40.522715 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:37:40.526248 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 13:37:40.529554 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:37:40.529638
764 13:37:40.532629 CA PerBit enable=1, Macro0, CA PI delay=33
765 13:37:40.532714
766 13:37:40.536175 [CBTSetCACLKResult] CA Dly = 33
767 13:37:40.536261 CS Dly: 5 (0~37)
768 13:37:40.536327
769 13:37:40.539576 ----->DramcWriteLeveling(PI) begin...
770 13:37:40.539664 ==
771 13:37:40.543026 Dram Type= 6, Freq= 0, CH_0, rank 0
772 13:37:40.549819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 13:37:40.549963 ==
774 13:37:40.550047 Write leveling (Byte 0): 31 => 31
775 13:37:40.553476 Write leveling (Byte 1): 31 => 31
776 13:37:40.557322 DramcWriteLeveling(PI) end<-----
777 13:37:40.557445
778 13:37:40.557550 ==
779 13:37:40.561314 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:37:40.565211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:37:40.565303 ==
782 13:37:40.568274 [Gating] SW mode calibration
783 13:37:40.574759 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 13:37:40.578852 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 13:37:40.585458 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 13:37:40.589169 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:37:40.592085 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 13:37:40.599146 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:37:40.602430 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:37:40.605826 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:37:40.612706 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:37:40.616153 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:37:40.619190 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:37:40.626034 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:37:40.629173 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:37:40.632758 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:37:40.635745 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:37:40.642451 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:37:40.646387 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:37:40.649752 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:37:40.656401 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:37:40.659656 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:37:40.662815 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 13:37:40.669960 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 13:37:40.673200 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:37:40.676353 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:37:40.683114 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:37:40.686500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:37:40.689662 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:37:40.693225 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:37:40.700101 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
812 13:37:40.703110 0 9 12 | B1->B0 | 2828 3232 | 0 1 | (0 0) (1 1)
813 13:37:40.706570 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 13:37:40.713337 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:37:40.716459 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:37:40.720032 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:37:40.726580 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:37:40.730413 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
819 13:37:40.733296 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
820 13:37:40.740041 0 10 12 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
821 13:37:40.743587 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:37:40.746623 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:37:40.750296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:37:40.756856 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:37:40.760451 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:37:40.763501 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:37:40.770117 0 11 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
828 13:37:40.773707 0 11 12 | B1->B0 | 3737 3f3f | 0 0 | (1 1) (0 0)
829 13:37:40.777004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:37:40.783868 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:37:40.787030 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:37:40.790423 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:37:40.797237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:37:40.800346 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:37:40.803873 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 13:37:40.810498 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 13:37:40.814030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:37:40.816895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:37:40.820358 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:37:40.827272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:37:40.830578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:37:40.834346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:37:40.840878 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:37:40.844081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:37:40.847533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:37:40.854234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:37:40.857401 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:37:40.861024 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:37:40.867665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:37:40.871225 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:37:40.874579 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:37:40.877782 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:37:40.881297 Total UI for P1: 0, mck2ui 16
854 13:37:40.884754 best dqsien dly found for B0: ( 0, 14, 8)
855 13:37:40.888242 Total UI for P1: 0, mck2ui 16
856 13:37:40.891414 best dqsien dly found for B1: ( 0, 14, 10)
857 13:37:40.894700 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 13:37:40.898217 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 13:37:40.898301
860 13:37:40.904352 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 13:37:40.908020 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 13:37:40.908104 [Gating] SW calibration Done
863 13:37:40.911281 ==
864 13:37:40.914898 Dram Type= 6, Freq= 0, CH_0, rank 0
865 13:37:40.917750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 13:37:40.917834 ==
867 13:37:40.917900 RX Vref Scan: 0
868 13:37:40.917961
869 13:37:40.921451 RX Vref 0 -> 0, step: 1
870 13:37:40.921534
871 13:37:40.924614 RX Delay -130 -> 252, step: 16
872 13:37:40.928073 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 13:37:40.931602 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
874 13:37:40.934796 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 13:37:40.941642 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
876 13:37:40.944990 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
877 13:37:40.948160 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
878 13:37:40.951823 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
879 13:37:40.955069 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
880 13:37:40.958641 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
881 13:37:40.964778 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
882 13:37:40.968592 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 13:37:40.971722 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
884 13:37:40.975203 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 13:37:40.982142 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
886 13:37:40.985351 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
887 13:37:40.988343 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 13:37:40.988441 ==
889 13:37:40.991958 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:37:40.995422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 13:37:40.995509 ==
892 13:37:40.998411 DQS Delay:
893 13:37:40.998494 DQS0 = 0, DQS1 = 0
894 13:37:40.998560 DQM Delay:
895 13:37:41.002090 DQM0 = 83, DQM1 = 78
896 13:37:41.002174 DQ Delay:
897 13:37:41.005421 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 13:37:41.008960 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
899 13:37:41.012129 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
900 13:37:41.015669 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 13:37:41.015753
902 13:37:41.015818
903 13:37:41.015879 ==
904 13:37:41.018634 Dram Type= 6, Freq= 0, CH_0, rank 0
905 13:37:41.025370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 13:37:41.025454 ==
907 13:37:41.025519
908 13:37:41.025580
909 13:37:41.025639 TX Vref Scan disable
910 13:37:41.028865 == TX Byte 0 ==
911 13:37:41.032195 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
912 13:37:41.035762 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
913 13:37:41.038918 == TX Byte 1 ==
914 13:37:41.042327 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
915 13:37:41.046188 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
916 13:37:41.048803 ==
917 13:37:41.048913 Dram Type= 6, Freq= 0, CH_0, rank 0
918 13:37:41.055645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 13:37:41.055787 ==
920 13:37:41.067686 TX Vref=22, minBit 5, minWin=27, winSum=443
921 13:37:41.070868 TX Vref=24, minBit 5, minWin=27, winSum=444
922 13:37:41.074614 TX Vref=26, minBit 5, minWin=27, winSum=448
923 13:37:41.077628 TX Vref=28, minBit 13, minWin=27, winSum=453
924 13:37:41.081174 TX Vref=30, minBit 3, minWin=28, winSum=457
925 13:37:41.087746 TX Vref=32, minBit 2, minWin=28, winSum=460
926 13:37:41.090873 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 32
927 13:37:41.090985
928 13:37:41.094727 Final TX Range 1 Vref 32
929 13:37:41.094839
930 13:37:41.094935 ==
931 13:37:41.097587 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:37:41.101257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:37:41.101369 ==
934 13:37:41.101466
935 13:37:41.104305
936 13:37:41.104414 TX Vref Scan disable
937 13:37:41.108048 == TX Byte 0 ==
938 13:37:41.111442 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
939 13:37:41.115063 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
940 13:37:41.117929 == TX Byte 1 ==
941 13:37:41.121411 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
942 13:37:41.124775 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
943 13:37:41.127899
944 13:37:41.128006 [DATLAT]
945 13:37:41.128100 Freq=800, CH0 RK0
946 13:37:41.128195
947 13:37:41.131438 DATLAT Default: 0xa
948 13:37:41.131546 0, 0xFFFF, sum = 0
949 13:37:41.134595 1, 0xFFFF, sum = 0
950 13:37:41.134679 2, 0xFFFF, sum = 0
951 13:37:41.137717 3, 0xFFFF, sum = 0
952 13:37:41.137802 4, 0xFFFF, sum = 0
953 13:37:41.141373 5, 0xFFFF, sum = 0
954 13:37:41.141521 6, 0xFFFF, sum = 0
955 13:37:41.144829 7, 0xFFFF, sum = 0
956 13:37:41.144946 8, 0xFFFF, sum = 0
957 13:37:41.148009 9, 0x0, sum = 1
958 13:37:41.148103 10, 0x0, sum = 2
959 13:37:41.151240 11, 0x0, sum = 3
960 13:37:41.151342 12, 0x0, sum = 4
961 13:37:41.154631 best_step = 10
962 13:37:41.154760
963 13:37:41.154832 ==
964 13:37:41.158824 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:37:41.161315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 13:37:41.161408 ==
967 13:37:41.164654 RX Vref Scan: 1
968 13:37:41.164742
969 13:37:41.164809 Set Vref Range= 32 -> 127
970 13:37:41.164871
971 13:37:41.167905 RX Vref 32 -> 127, step: 1
972 13:37:41.167997
973 13:37:41.171460 RX Delay -95 -> 252, step: 8
974 13:37:41.171608
975 13:37:41.174684 Set Vref, RX VrefLevel [Byte0]: 32
976 13:37:41.178443 [Byte1]: 32
977 13:37:41.178532
978 13:37:41.181492 Set Vref, RX VrefLevel [Byte0]: 33
979 13:37:41.184989 [Byte1]: 33
980 13:37:41.185119
981 13:37:41.188767 Set Vref, RX VrefLevel [Byte0]: 34
982 13:37:41.191787 [Byte1]: 34
983 13:37:41.195928
984 13:37:41.196011 Set Vref, RX VrefLevel [Byte0]: 35
985 13:37:41.198915 [Byte1]: 35
986 13:37:41.203636
987 13:37:41.203746 Set Vref, RX VrefLevel [Byte0]: 36
988 13:37:41.206765 [Byte1]: 36
989 13:37:41.211042
990 13:37:41.211118 Set Vref, RX VrefLevel [Byte0]: 37
991 13:37:41.214385 [Byte1]: 37
992 13:37:41.218960
993 13:37:41.219037 Set Vref, RX VrefLevel [Byte0]: 38
994 13:37:41.222072 [Byte1]: 38
995 13:37:41.226253
996 13:37:41.226331 Set Vref, RX VrefLevel [Byte0]: 39
997 13:37:41.229978 [Byte1]: 39
998 13:37:41.234088
999 13:37:41.234167 Set Vref, RX VrefLevel [Byte0]: 40
1000 13:37:41.237274 [Byte1]: 40
1001 13:37:41.241389
1002 13:37:41.241473 Set Vref, RX VrefLevel [Byte0]: 41
1003 13:37:41.245154 [Byte1]: 41
1004 13:37:41.249421
1005 13:37:41.249499 Set Vref, RX VrefLevel [Byte0]: 42
1006 13:37:41.252481 [Byte1]: 42
1007 13:37:41.256128
1008 13:37:41.256204 Set Vref, RX VrefLevel [Byte0]: 43
1009 13:37:41.259841 [Byte1]: 43
1010 13:37:41.264081
1011 13:37:41.264156 Set Vref, RX VrefLevel [Byte0]: 44
1012 13:37:41.267086 [Byte1]: 44
1013 13:37:41.271972
1014 13:37:41.272087 Set Vref, RX VrefLevel [Byte0]: 45
1015 13:37:41.275127 [Byte1]: 45
1016 13:37:41.279254
1017 13:37:41.279362 Set Vref, RX VrefLevel [Byte0]: 46
1018 13:37:41.282961 [Byte1]: 46
1019 13:37:41.286618
1020 13:37:41.286709 Set Vref, RX VrefLevel [Byte0]: 47
1021 13:37:41.290269 [Byte1]: 47
1022 13:37:41.294471
1023 13:37:41.294564 Set Vref, RX VrefLevel [Byte0]: 48
1024 13:37:41.297479 [Byte1]: 48
1025 13:37:41.301778
1026 13:37:41.301855 Set Vref, RX VrefLevel [Byte0]: 49
1027 13:37:41.305579 [Byte1]: 49
1028 13:37:41.309581
1029 13:37:41.309653 Set Vref, RX VrefLevel [Byte0]: 50
1030 13:37:41.313213 [Byte1]: 50
1031 13:37:41.317362
1032 13:37:41.317436 Set Vref, RX VrefLevel [Byte0]: 51
1033 13:37:41.320516 [Byte1]: 51
1034 13:37:41.324919
1035 13:37:41.325046 Set Vref, RX VrefLevel [Byte0]: 52
1036 13:37:41.328212 [Byte1]: 52
1037 13:37:41.332171
1038 13:37:41.332244 Set Vref, RX VrefLevel [Byte0]: 53
1039 13:37:41.336027 [Byte1]: 53
1040 13:37:41.340089
1041 13:37:41.340165 Set Vref, RX VrefLevel [Byte0]: 54
1042 13:37:41.343595 [Byte1]: 54
1043 13:37:41.347222
1044 13:37:41.347301 Set Vref, RX VrefLevel [Byte0]: 55
1045 13:37:41.350916 [Byte1]: 55
1046 13:37:41.355156
1047 13:37:41.355236 Set Vref, RX VrefLevel [Byte0]: 56
1048 13:37:41.358855 [Byte1]: 56
1049 13:37:41.362623
1050 13:37:41.362702 Set Vref, RX VrefLevel [Byte0]: 57
1051 13:37:41.366332 [Byte1]: 57
1052 13:37:41.370392
1053 13:37:41.370505 Set Vref, RX VrefLevel [Byte0]: 58
1054 13:37:41.373464 [Byte1]: 58
1055 13:37:41.378153
1056 13:37:41.378234 Set Vref, RX VrefLevel [Byte0]: 59
1057 13:37:41.381394 [Byte1]: 59
1058 13:37:41.385323
1059 13:37:41.385404 Set Vref, RX VrefLevel [Byte0]: 60
1060 13:37:41.388899 [Byte1]: 60
1061 13:37:41.393181
1062 13:37:41.393294 Set Vref, RX VrefLevel [Byte0]: 61
1063 13:37:41.396247 [Byte1]: 61
1064 13:37:41.401149
1065 13:37:41.401230 Set Vref, RX VrefLevel [Byte0]: 62
1066 13:37:41.404194 [Byte1]: 62
1067 13:37:41.408478
1068 13:37:41.408586 Set Vref, RX VrefLevel [Byte0]: 63
1069 13:37:41.411551 [Byte1]: 63
1070 13:37:41.415633
1071 13:37:41.415714 Set Vref, RX VrefLevel [Byte0]: 64
1072 13:37:41.419185 [Byte1]: 64
1073 13:37:41.423635
1074 13:37:41.423719 Set Vref, RX VrefLevel [Byte0]: 65
1075 13:37:41.426940 [Byte1]: 65
1076 13:37:41.431046
1077 13:37:41.431130 Set Vref, RX VrefLevel [Byte0]: 66
1078 13:37:41.434175 [Byte1]: 66
1079 13:37:41.438808
1080 13:37:41.438891 Set Vref, RX VrefLevel [Byte0]: 67
1081 13:37:41.442238 [Byte1]: 67
1082 13:37:41.446243
1083 13:37:41.446328 Set Vref, RX VrefLevel [Byte0]: 68
1084 13:37:41.449738 [Byte1]: 68
1085 13:37:41.454072
1086 13:37:41.454156 Set Vref, RX VrefLevel [Byte0]: 69
1087 13:37:41.457231 [Byte1]: 69
1088 13:37:41.461431
1089 13:37:41.461514 Set Vref, RX VrefLevel [Byte0]: 70
1090 13:37:41.464610 [Byte1]: 70
1091 13:37:41.468861
1092 13:37:41.468972 Set Vref, RX VrefLevel [Byte0]: 71
1093 13:37:41.472581 [Byte1]: 71
1094 13:37:41.476866
1095 13:37:41.476983 Set Vref, RX VrefLevel [Byte0]: 72
1096 13:37:41.479998 [Byte1]: 72
1097 13:37:41.484502
1098 13:37:41.484615 Set Vref, RX VrefLevel [Byte0]: 73
1099 13:37:41.487413 [Byte1]: 73
1100 13:37:41.491647
1101 13:37:41.491730 Set Vref, RX VrefLevel [Byte0]: 74
1102 13:37:41.495074 [Byte1]: 74
1103 13:37:41.499562
1104 13:37:41.499646 Set Vref, RX VrefLevel [Byte0]: 75
1105 13:37:41.502974 [Byte1]: 75
1106 13:37:41.507114
1107 13:37:41.507198 Set Vref, RX VrefLevel [Byte0]: 76
1108 13:37:41.510238 [Byte1]: 76
1109 13:37:41.514463
1110 13:37:41.514547 Final RX Vref Byte 0 = 61 to rank0
1111 13:37:41.518263 Final RX Vref Byte 1 = 58 to rank0
1112 13:37:41.521326 Final RX Vref Byte 0 = 61 to rank1
1113 13:37:41.524832 Final RX Vref Byte 1 = 58 to rank1==
1114 13:37:41.527753 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 13:37:41.531337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 13:37:41.535208 ==
1117 13:37:41.535292 DQS Delay:
1118 13:37:41.535376 DQS0 = 0, DQS1 = 0
1119 13:37:41.538243 DQM Delay:
1120 13:37:41.538349 DQM0 = 87, DQM1 = 80
1121 13:37:41.541239 DQ Delay:
1122 13:37:41.541318 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1123 13:37:41.544695 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1124 13:37:41.548308 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1125 13:37:41.551846 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1126 13:37:41.551930
1127 13:37:41.552015
1128 13:37:41.562145 [DQSOSCAuto] RK0, (LSB)MR18= 0x2911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1129 13:37:41.565304 CH0 RK0: MR19=606, MR18=2911
1130 13:37:41.568281 CH0_RK0: MR19=0x606, MR18=0x2911, DQSOSC=399, MR23=63, INC=92, DEC=61
1131 13:37:41.572107
1132 13:37:41.575197 ----->DramcWriteLeveling(PI) begin...
1133 13:37:41.575308 ==
1134 13:37:41.578323 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 13:37:41.581906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 13:37:41.582016 ==
1137 13:37:41.584967 Write leveling (Byte 0): 28 => 28
1138 13:37:41.588675 Write leveling (Byte 1): 28 => 28
1139 13:37:41.591910 DramcWriteLeveling(PI) end<-----
1140 13:37:41.591992
1141 13:37:41.592056 ==
1142 13:37:41.595402 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 13:37:41.598529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 13:37:41.598629 ==
1145 13:37:41.601735 [Gating] SW mode calibration
1146 13:37:41.608734 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 13:37:41.612322 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 13:37:41.618488 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 13:37:41.622288 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 13:37:41.625319 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1151 13:37:41.672707 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 13:37:41.672819 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:37:41.673395 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:37:41.674220 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:37:41.674503 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:37:41.674609 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:37:41.674673 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:37:41.674744 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:37:41.675393 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:37:41.675689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:37:41.713318 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:37:41.713406 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:37:41.713658 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:37:41.713741 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1165 13:37:41.713911 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 13:37:41.714018 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1167 13:37:41.714080 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:37:41.714169 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:37:41.714240 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:37:41.717502 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:37:41.721055 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:37:41.724389 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:37:41.727661 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:37:41.730993 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
1175 13:37:41.737515 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1176 13:37:41.741248 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 13:37:41.744248 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:37:41.750883 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:37:41.754619 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:37:41.757498 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:37:41.764538 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
1182 13:37:41.768026 0 10 8 | B1->B0 | 3333 2626 | 1 0 | (0 1) (0 0)
1183 13:37:41.771262 0 10 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
1184 13:37:41.774983 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:37:41.781658 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:37:41.784782 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:37:41.787951 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:37:41.794675 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:37:41.798485 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1190 13:37:41.802084 0 11 8 | B1->B0 | 2828 3b3b | 0 0 | (0 0) (0 0)
1191 13:37:41.805758 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1192 13:37:41.810302 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:37:41.817209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:37:41.820729 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:37:41.823664 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:37:41.827453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:37:41.834818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:37:41.838343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1199 13:37:41.841212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:37:41.848141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:37:41.851183 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:37:41.854715 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:37:41.857892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:37:41.864543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:37:41.867854 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:37:41.871373 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:37:41.878371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:37:41.881391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:37:41.885171 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:37:41.891820 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:37:41.895061 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:37:41.898309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:37:41.904802 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 13:37:41.908758 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1215 13:37:41.911776 Total UI for P1: 0, mck2ui 16
1216 13:37:41.915402 best dqsien dly found for B0: ( 0, 14, 4)
1217 13:37:41.918228 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 13:37:41.921731 Total UI for P1: 0, mck2ui 16
1219 13:37:41.924960 best dqsien dly found for B1: ( 0, 14, 8)
1220 13:37:41.928387 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 13:37:41.931716 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 13:37:41.931804
1223 13:37:41.935326 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 13:37:41.938748 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 13:37:41.941759 [Gating] SW calibration Done
1226 13:37:41.941839 ==
1227 13:37:41.945381 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 13:37:41.948497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 13:37:41.952137 ==
1230 13:37:41.952219 RX Vref Scan: 0
1231 13:37:41.952284
1232 13:37:41.955435 RX Vref 0 -> 0, step: 1
1233 13:37:41.955547
1234 13:37:41.958765 RX Delay -130 -> 252, step: 16
1235 13:37:41.962231 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1236 13:37:41.965286 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 13:37:41.968560 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 13:37:41.972200 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1239 13:37:41.978561 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 13:37:41.982054 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1241 13:37:41.985117 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 13:37:41.988840 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1243 13:37:41.992052 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1244 13:37:41.998809 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1245 13:37:42.002003 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1246 13:37:42.005679 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1247 13:37:42.008873 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1248 13:37:42.012104 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1249 13:37:42.019124 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 13:37:42.022397 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1251 13:37:42.022488 ==
1252 13:37:42.025477 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 13:37:42.028995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 13:37:42.029094 ==
1255 13:37:42.029160 DQS Delay:
1256 13:37:42.032393 DQS0 = 0, DQS1 = 0
1257 13:37:42.032475 DQM Delay:
1258 13:37:42.035989 DQM0 = 90, DQM1 = 77
1259 13:37:42.036071 DQ Delay:
1260 13:37:42.039147 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1261 13:37:42.042385 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1262 13:37:42.045839 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1263 13:37:42.049551 DQ12 =69, DQ13 =93, DQ14 =93, DQ15 =93
1264 13:37:42.049640
1265 13:37:42.049706
1266 13:37:42.049766 ==
1267 13:37:42.052742 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 13:37:42.056163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 13:37:42.059183 ==
1270 13:37:42.059301
1271 13:37:42.059394
1272 13:37:42.059454 TX Vref Scan disable
1273 13:37:42.062170 == TX Byte 0 ==
1274 13:37:42.065798 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1275 13:37:42.069270 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1276 13:37:42.072691 == TX Byte 1 ==
1277 13:37:42.075919 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1278 13:37:42.079520 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1279 13:37:42.079603 ==
1280 13:37:42.082538 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 13:37:42.089373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 13:37:42.089479 ==
1283 13:37:42.100957 TX Vref=22, minBit 2, minWin=27, winSum=440
1284 13:37:42.104868 TX Vref=24, minBit 3, minWin=26, winSum=444
1285 13:37:42.108158 TX Vref=26, minBit 3, minWin=27, winSum=446
1286 13:37:42.111204 TX Vref=28, minBit 3, minWin=27, winSum=452
1287 13:37:42.114406 TX Vref=30, minBit 0, minWin=28, winSum=454
1288 13:37:42.118243 TX Vref=32, minBit 13, minWin=27, winSum=448
1289 13:37:42.124615 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1290 13:37:42.124715
1291 13:37:42.127908 Final TX Range 1 Vref 30
1292 13:37:42.127991
1293 13:37:42.128055 ==
1294 13:37:42.131504 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 13:37:42.134655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 13:37:42.134740 ==
1297 13:37:42.134804
1298 13:37:42.134864
1299 13:37:42.137792 TX Vref Scan disable
1300 13:37:42.141485 == TX Byte 0 ==
1301 13:37:42.144941 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1302 13:37:42.147990 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1303 13:37:42.151336 == TX Byte 1 ==
1304 13:37:42.154923 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1305 13:37:42.158675 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1306 13:37:42.158756
1307 13:37:42.161784 [DATLAT]
1308 13:37:42.161854 Freq=800, CH0 RK1
1309 13:37:42.161913
1310 13:37:42.164927 DATLAT Default: 0xa
1311 13:37:42.165044 0, 0xFFFF, sum = 0
1312 13:37:42.168247 1, 0xFFFF, sum = 0
1313 13:37:42.168319 2, 0xFFFF, sum = 0
1314 13:37:42.171994 3, 0xFFFF, sum = 0
1315 13:37:42.172098 4, 0xFFFF, sum = 0
1316 13:37:42.174952 5, 0xFFFF, sum = 0
1317 13:37:42.175026 6, 0xFFFF, sum = 0
1318 13:37:42.178538 7, 0xFFFF, sum = 0
1319 13:37:42.178635 8, 0xFFFF, sum = 0
1320 13:37:42.181813 9, 0x0, sum = 1
1321 13:37:42.181917 10, 0x0, sum = 2
1322 13:37:42.185409 11, 0x0, sum = 3
1323 13:37:42.185550 12, 0x0, sum = 4
1324 13:37:42.188198 best_step = 10
1325 13:37:42.188270
1326 13:37:42.188329 ==
1327 13:37:42.191976 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 13:37:42.195024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 13:37:42.195100 ==
1330 13:37:42.195161 RX Vref Scan: 0
1331 13:37:42.198749
1332 13:37:42.198844 RX Vref 0 -> 0, step: 1
1333 13:37:42.198930
1334 13:37:42.201793 RX Delay -95 -> 252, step: 8
1335 13:37:42.204943 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 13:37:42.211842 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1337 13:37:42.215084 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1338 13:37:42.218334 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1339 13:37:42.222168 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1340 13:37:42.225270 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1341 13:37:42.231811 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1342 13:37:42.235681 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1343 13:37:42.238684 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1344 13:37:42.241880 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 13:37:42.245460 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1346 13:37:42.251758 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1347 13:37:42.255377 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1348 13:37:42.258497 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1349 13:37:42.262106 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1350 13:37:42.265465 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 13:37:42.265563 ==
1352 13:37:42.268881 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 13:37:42.275851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 13:37:42.275935 ==
1355 13:37:42.276006 DQS Delay:
1356 13:37:42.278944 DQS0 = 0, DQS1 = 0
1357 13:37:42.279024 DQM Delay:
1358 13:37:42.279086 DQM0 = 87, DQM1 = 78
1359 13:37:42.282100 DQ Delay:
1360 13:37:42.285645 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1361 13:37:42.288806 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1362 13:37:42.292040 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1363 13:37:42.295682 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1364 13:37:42.295762
1365 13:37:42.295825
1366 13:37:42.301987 [DQSOSCAuto] RK1, (LSB)MR18= 0x321c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1367 13:37:42.305657 CH0 RK1: MR19=606, MR18=321C
1368 13:37:42.312458 CH0_RK1: MR19=0x606, MR18=0x321C, DQSOSC=397, MR23=63, INC=93, DEC=62
1369 13:37:42.315786 [RxdqsGatingPostProcess] freq 800
1370 13:37:42.318903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 13:37:42.322611 Pre-setting of DQS Precalculation
1372 13:37:42.329011 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 13:37:42.329109 ==
1374 13:37:42.332210 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 13:37:42.335984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 13:37:42.336067 ==
1377 13:37:42.342441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 13:37:42.345648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 13:37:42.356275 [CA 0] Center 36 (6~66) winsize 61
1380 13:37:42.359382 [CA 1] Center 36 (6~66) winsize 61
1381 13:37:42.362503 [CA 2] Center 35 (5~65) winsize 61
1382 13:37:42.365752 [CA 3] Center 34 (4~65) winsize 62
1383 13:37:42.369506 [CA 4] Center 34 (4~65) winsize 62
1384 13:37:42.372471 [CA 5] Center 33 (3~64) winsize 62
1385 13:37:42.372553
1386 13:37:42.375816 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 13:37:42.375899
1388 13:37:42.379246 [CATrainingPosCal] consider 1 rank data
1389 13:37:42.382446 u2DelayCellTimex100 = 270/100 ps
1390 13:37:42.386346 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1391 13:37:42.389579 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 13:37:42.392640 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1393 13:37:42.400156 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 13:37:42.403043 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 13:37:42.406197 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 13:37:42.406278
1397 13:37:42.409863 CA PerBit enable=1, Macro0, CA PI delay=33
1398 13:37:42.409945
1399 13:37:42.412793 [CBTSetCACLKResult] CA Dly = 33
1400 13:37:42.412874 CS Dly: 5 (0~36)
1401 13:37:42.412938 ==
1402 13:37:42.416494 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 13:37:42.423296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 13:37:42.423379 ==
1405 13:37:42.426676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 13:37:42.432912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 13:37:42.441870 [CA 0] Center 36 (6~66) winsize 61
1408 13:37:42.445517 [CA 1] Center 36 (6~66) winsize 61
1409 13:37:42.448682 [CA 2] Center 34 (4~65) winsize 62
1410 13:37:42.451963 [CA 3] Center 33 (3~64) winsize 62
1411 13:37:42.455809 [CA 4] Center 34 (4~65) winsize 62
1412 13:37:42.458850 [CA 5] Center 33 (3~64) winsize 62
1413 13:37:42.458933
1414 13:37:42.462400 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 13:37:42.462482
1416 13:37:42.466236 [CATrainingPosCal] consider 2 rank data
1417 13:37:42.469523 u2DelayCellTimex100 = 270/100 ps
1418 13:37:42.474073 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1419 13:37:42.477766 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 13:37:42.481472 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1421 13:37:42.484920 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 13:37:42.489300 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 13:37:42.493013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 13:37:42.493110
1425 13:37:42.496239 CA PerBit enable=1, Macro0, CA PI delay=33
1426 13:37:42.496360
1427 13:37:42.500025 [CBTSetCACLKResult] CA Dly = 33
1428 13:37:42.500119 CS Dly: 5 (0~37)
1429 13:37:42.500229
1430 13:37:42.503219 ----->DramcWriteLeveling(PI) begin...
1431 13:37:42.503316 ==
1432 13:37:42.506928 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 13:37:42.509919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 13:37:42.510002 ==
1435 13:37:42.513666 Write leveling (Byte 0): 27 => 27
1436 13:37:42.516782 Write leveling (Byte 1): 32 => 32
1437 13:37:42.520313 DramcWriteLeveling(PI) end<-----
1438 13:37:42.520394
1439 13:37:42.520458 ==
1440 13:37:42.523499 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 13:37:42.527213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 13:37:42.530303 ==
1443 13:37:42.530384 [Gating] SW mode calibration
1444 13:37:42.536653 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 13:37:42.543864 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 13:37:42.547063 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 13:37:42.554172 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 13:37:42.557230 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:37:42.560305 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:37:42.564109 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:37:42.571098 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:37:42.574324 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:37:42.577322 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:37:42.584300 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:37:42.587294 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:37:42.590842 0 7 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1457 13:37:42.597828 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:37:42.601164 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1459 13:37:42.604325 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 13:37:42.610776 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:37:42.614613 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:37:42.617873 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 13:37:42.621408 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1464 13:37:42.627656 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1465 13:37:42.631324 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:37:42.634447 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:37:42.641079 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:37:42.644546 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:37:42.648079 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:37:42.654483 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:37:42.657632 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:37:42.661360 0 9 8 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1473 13:37:42.668255 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:37:42.671452 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 13:37:42.674629 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:37:42.681323 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 13:37:42.684533 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:37:42.688385 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:37:42.691495 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1480 13:37:42.698258 0 10 8 | B1->B0 | 2d2d 2d2d | 0 1 | (1 0) (1 0)
1481 13:37:42.701600 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:37:42.704807 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:37:42.711542 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:37:42.714724 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:37:42.718038 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:37:42.724853 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:37:42.728425 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 13:37:42.731506 0 11 8 | B1->B0 | 3636 3434 | 0 0 | (0 0) (0 0)
1489 13:37:42.738337 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:37:42.742079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:37:42.745206 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:37:42.748396 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:37:42.755348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:37:42.758845 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:37:42.762343 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:37:42.768802 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:37:42.772058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:37:42.775120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:37:42.782075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:37:42.785335 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:37:42.788433 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:37:42.795536 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:37:42.798582 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:37:42.802218 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:37:42.808845 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:37:42.812561 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:37:42.815678 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:37:42.818824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:37:42.825713 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:37:42.829255 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:37:42.832181 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1512 13:37:42.838832 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 13:37:42.838963 Total UI for P1: 0, mck2ui 16
1514 13:37:42.845864 best dqsien dly found for B0: ( 0, 14, 4)
1515 13:37:42.845989 Total UI for P1: 0, mck2ui 16
1516 13:37:42.852648 best dqsien dly found for B1: ( 0, 14, 6)
1517 13:37:42.855958 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 13:37:42.859185 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 13:37:42.859264
1520 13:37:42.862297 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 13:37:42.865994 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 13:37:42.869098 [Gating] SW calibration Done
1523 13:37:42.869209 ==
1524 13:37:42.872665 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 13:37:42.875726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 13:37:42.875837 ==
1527 13:37:42.875933 RX Vref Scan: 0
1528 13:37:42.879558
1529 13:37:42.879676 RX Vref 0 -> 0, step: 1
1530 13:37:42.879778
1531 13:37:42.882500 RX Delay -130 -> 252, step: 16
1532 13:37:42.885739 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1533 13:37:42.888935 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1534 13:37:42.896032 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1535 13:37:42.899259 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1536 13:37:42.903043 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1537 13:37:42.906035 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1538 13:37:42.909139 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1539 13:37:42.915984 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1540 13:37:42.919337 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1541 13:37:42.923307 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1542 13:37:42.925883 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1543 13:37:42.929655 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1544 13:37:42.936478 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1545 13:37:42.939819 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1546 13:37:42.942598 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1547 13:37:42.946014 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1548 13:37:42.946105 ==
1549 13:37:42.949568 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 13:37:42.953218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 13:37:42.956410 ==
1552 13:37:42.956550 DQS Delay:
1553 13:37:42.956617 DQS0 = 0, DQS1 = 0
1554 13:37:42.959637 DQM Delay:
1555 13:37:42.959720 DQM0 = 82, DQM1 = 75
1556 13:37:42.962865 DQ Delay:
1557 13:37:42.962948 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1558 13:37:42.966029 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1559 13:37:42.969732 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1560 13:37:42.972931 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 13:37:42.973049
1562 13:37:42.973115
1563 13:37:42.976790 ==
1564 13:37:42.980054 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 13:37:42.983118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 13:37:42.983203 ==
1567 13:37:42.983268
1568 13:37:42.983327
1569 13:37:42.986330 TX Vref Scan disable
1570 13:37:42.986442 == TX Byte 0 ==
1571 13:37:42.990242 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 13:37:42.996699 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 13:37:42.996786 == TX Byte 1 ==
1574 13:37:42.999739 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1575 13:37:43.006522 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1576 13:37:43.006620 ==
1577 13:37:43.009861 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 13:37:43.013523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 13:37:43.013611 ==
1580 13:37:43.027024 TX Vref=22, minBit 10, minWin=26, winSum=438
1581 13:37:43.030445 TX Vref=24, minBit 8, minWin=27, winSum=445
1582 13:37:43.033496 TX Vref=26, minBit 4, minWin=27, winSum=448
1583 13:37:43.036586 TX Vref=28, minBit 11, minWin=27, winSum=452
1584 13:37:43.039993 TX Vref=30, minBit 0, minWin=28, winSum=453
1585 13:37:43.043684 TX Vref=32, minBit 1, minWin=28, winSum=455
1586 13:37:43.050889 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 32
1587 13:37:43.050997
1588 13:37:43.054291 Final TX Range 1 Vref 32
1589 13:37:43.054377
1590 13:37:43.054442 ==
1591 13:37:43.057715 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 13:37:43.061189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 13:37:43.061275 ==
1594 13:37:43.061340
1595 13:37:43.061399
1596 13:37:43.064447 TX Vref Scan disable
1597 13:37:43.067737 == TX Byte 0 ==
1598 13:37:43.070798 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 13:37:43.074757 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 13:37:43.077833 == TX Byte 1 ==
1601 13:37:43.081146 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1602 13:37:43.084908 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1603 13:37:43.085039
1604 13:37:43.087976 [DATLAT]
1605 13:37:43.088070 Freq=800, CH1 RK0
1606 13:37:43.088140
1607 13:37:43.091352 DATLAT Default: 0xa
1608 13:37:43.091435 0, 0xFFFF, sum = 0
1609 13:37:43.094549 1, 0xFFFF, sum = 0
1610 13:37:43.094634 2, 0xFFFF, sum = 0
1611 13:37:43.097726 3, 0xFFFF, sum = 0
1612 13:37:43.097838 4, 0xFFFF, sum = 0
1613 13:37:43.101526 5, 0xFFFF, sum = 0
1614 13:37:43.101610 6, 0xFFFF, sum = 0
1615 13:37:43.104652 7, 0xFFFF, sum = 0
1616 13:37:43.104763 8, 0xFFFF, sum = 0
1617 13:37:43.107937 9, 0x0, sum = 1
1618 13:37:43.108021 10, 0x0, sum = 2
1619 13:37:43.111519 11, 0x0, sum = 3
1620 13:37:43.111603 12, 0x0, sum = 4
1621 13:37:43.111668 best_step = 10
1622 13:37:43.114558
1623 13:37:43.114644 ==
1624 13:37:43.117967 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 13:37:43.121352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 13:37:43.121470 ==
1627 13:37:43.121572 RX Vref Scan: 1
1628 13:37:43.121665
1629 13:37:43.124983 Set Vref Range= 32 -> 127
1630 13:37:43.125088
1631 13:37:43.128087 RX Vref 32 -> 127, step: 1
1632 13:37:43.128199
1633 13:37:43.131746 RX Delay -111 -> 252, step: 8
1634 13:37:43.131857
1635 13:37:43.134655 Set Vref, RX VrefLevel [Byte0]: 32
1636 13:37:43.137933 [Byte1]: 32
1637 13:37:43.138030
1638 13:37:43.141757 Set Vref, RX VrefLevel [Byte0]: 33
1639 13:37:43.144778 [Byte1]: 33
1640 13:37:43.144890
1641 13:37:43.148039 Set Vref, RX VrefLevel [Byte0]: 34
1642 13:37:43.151143 [Byte1]: 34
1643 13:37:43.166202
1644 13:37:43.166375 Set Vref, RX VrefLevel [Byte0]: 35
1645 13:37:43.166446 [Byte1]: 35
1646 13:37:43.166507
1647 13:37:43.166565 Set Vref, RX VrefLevel [Byte0]: 36
1648 13:37:43.166622 [Byte1]: 36
1649 13:37:43.170455
1650 13:37:43.170563 Set Vref, RX VrefLevel [Byte0]: 37
1651 13:37:43.173651 [Byte1]: 37
1652 13:37:43.178063
1653 13:37:43.178153 Set Vref, RX VrefLevel [Byte0]: 38
1654 13:37:43.181241 [Byte1]: 38
1655 13:37:43.185733
1656 13:37:43.185822 Set Vref, RX VrefLevel [Byte0]: 39
1657 13:37:43.188948 [Byte1]: 39
1658 13:37:43.193266
1659 13:37:43.193370 Set Vref, RX VrefLevel [Byte0]: 40
1660 13:37:43.196511 [Byte1]: 40
1661 13:37:43.200782
1662 13:37:43.200892 Set Vref, RX VrefLevel [Byte0]: 41
1663 13:37:43.203979 [Byte1]: 41
1664 13:37:43.209184
1665 13:37:43.209328 Set Vref, RX VrefLevel [Byte0]: 42
1666 13:37:43.212061 [Byte1]: 42
1667 13:37:43.216145
1668 13:37:43.216232 Set Vref, RX VrefLevel [Byte0]: 43
1669 13:37:43.219907 [Byte1]: 43
1670 13:37:43.223832
1671 13:37:43.223918 Set Vref, RX VrefLevel [Byte0]: 44
1672 13:37:43.227449 [Byte1]: 44
1673 13:37:43.231593
1674 13:37:43.231693 Set Vref, RX VrefLevel [Byte0]: 45
1675 13:37:43.234549 [Byte1]: 45
1676 13:37:43.239272
1677 13:37:43.239362 Set Vref, RX VrefLevel [Byte0]: 46
1678 13:37:43.242782 [Byte1]: 46
1679 13:37:43.246797
1680 13:37:43.246921 Set Vref, RX VrefLevel [Byte0]: 47
1681 13:37:43.250009 [Byte1]: 47
1682 13:37:43.254713
1683 13:37:43.254807 Set Vref, RX VrefLevel [Byte0]: 48
1684 13:37:43.258127 [Byte1]: 48
1685 13:37:43.261907
1686 13:37:43.261998 Set Vref, RX VrefLevel [Byte0]: 49
1687 13:37:43.265841 [Byte1]: 49
1688 13:37:43.270132
1689 13:37:43.270221 Set Vref, RX VrefLevel [Byte0]: 50
1690 13:37:43.273021 [Byte1]: 50
1691 13:37:43.277493
1692 13:37:43.277581 Set Vref, RX VrefLevel [Byte0]: 51
1693 13:37:43.280831 [Byte1]: 51
1694 13:37:43.285128
1695 13:37:43.285217 Set Vref, RX VrefLevel [Byte0]: 52
1696 13:37:43.288312 [Byte1]: 52
1697 13:37:43.292592
1698 13:37:43.292683 Set Vref, RX VrefLevel [Byte0]: 53
1699 13:37:43.296373 [Byte1]: 53
1700 13:37:43.300286
1701 13:37:43.300380 Set Vref, RX VrefLevel [Byte0]: 54
1702 13:37:43.303462 [Byte1]: 54
1703 13:37:43.307822
1704 13:37:43.307909 Set Vref, RX VrefLevel [Byte0]: 55
1705 13:37:43.311092 [Byte1]: 55
1706 13:37:43.315481
1707 13:37:43.315585 Set Vref, RX VrefLevel [Byte0]: 56
1708 13:37:43.319380 [Byte1]: 56
1709 13:37:43.323621
1710 13:37:43.323722 Set Vref, RX VrefLevel [Byte0]: 57
1711 13:37:43.326815 [Byte1]: 57
1712 13:37:43.330752
1713 13:37:43.330845 Set Vref, RX VrefLevel [Byte0]: 58
1714 13:37:43.334030 [Byte1]: 58
1715 13:37:43.338909
1716 13:37:43.339043 Set Vref, RX VrefLevel [Byte0]: 59
1717 13:37:43.341967 [Byte1]: 59
1718 13:37:43.346425
1719 13:37:43.346571 Set Vref, RX VrefLevel [Byte0]: 60
1720 13:37:43.349686 [Byte1]: 60
1721 13:37:43.353884
1722 13:37:43.353980 Set Vref, RX VrefLevel [Byte0]: 61
1723 13:37:43.357491 [Byte1]: 61
1724 13:37:43.361825
1725 13:37:43.361926 Set Vref, RX VrefLevel [Byte0]: 62
1726 13:37:43.365150 [Byte1]: 62
1727 13:37:43.368955
1728 13:37:43.369086 Set Vref, RX VrefLevel [Byte0]: 63
1729 13:37:43.372861 [Byte1]: 63
1730 13:37:43.376615
1731 13:37:43.376717 Set Vref, RX VrefLevel [Byte0]: 64
1732 13:37:43.380403 [Byte1]: 64
1733 13:37:43.384931
1734 13:37:43.385087 Set Vref, RX VrefLevel [Byte0]: 65
1735 13:37:43.387743 [Byte1]: 65
1736 13:37:43.392028
1737 13:37:43.392124 Set Vref, RX VrefLevel [Byte0]: 66
1738 13:37:43.395385 [Byte1]: 66
1739 13:37:43.399781
1740 13:37:43.399890 Set Vref, RX VrefLevel [Byte0]: 67
1741 13:37:43.403235 [Byte1]: 67
1742 13:37:43.407560
1743 13:37:43.407651 Set Vref, RX VrefLevel [Byte0]: 68
1744 13:37:43.410808 [Byte1]: 68
1745 13:37:43.415226
1746 13:37:43.415322 Set Vref, RX VrefLevel [Byte0]: 69
1747 13:37:43.418356 [Byte1]: 69
1748 13:37:43.422587
1749 13:37:43.422708 Set Vref, RX VrefLevel [Byte0]: 70
1750 13:37:43.426349 [Byte1]: 70
1751 13:37:43.430459
1752 13:37:43.430556 Set Vref, RX VrefLevel [Byte0]: 71
1753 13:37:43.433391 [Byte1]: 71
1754 13:37:43.438024
1755 13:37:43.438114 Set Vref, RX VrefLevel [Byte0]: 72
1756 13:37:43.441568 [Byte1]: 72
1757 13:37:43.445333
1758 13:37:43.445422 Set Vref, RX VrefLevel [Byte0]: 73
1759 13:37:43.449128 [Byte1]: 73
1760 13:37:43.453748
1761 13:37:43.453848 Set Vref, RX VrefLevel [Byte0]: 74
1762 13:37:43.456779 [Byte1]: 74
1763 13:37:43.461400
1764 13:37:43.461489 Final RX Vref Byte 0 = 59 to rank0
1765 13:37:43.464473 Final RX Vref Byte 1 = 57 to rank0
1766 13:37:43.467435 Final RX Vref Byte 0 = 59 to rank1
1767 13:37:43.471275 Final RX Vref Byte 1 = 57 to rank1==
1768 13:37:43.474228 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 13:37:43.481281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 13:37:43.481399 ==
1771 13:37:43.481493 DQS Delay:
1772 13:37:43.481573 DQS0 = 0, DQS1 = 0
1773 13:37:43.484456 DQM Delay:
1774 13:37:43.484542 DQM0 = 82, DQM1 = 74
1775 13:37:43.487625 DQ Delay:
1776 13:37:43.491413 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1777 13:37:43.491505 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1778 13:37:43.494478 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =72
1779 13:37:43.497779 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1780 13:37:43.497888
1781 13:37:43.501584
1782 13:37:43.508057 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1783 13:37:43.511353 CH1 RK0: MR19=606, MR18=2D01
1784 13:37:43.517993 CH1_RK0: MR19=0x606, MR18=0x2D01, DQSOSC=398, MR23=63, INC=93, DEC=62
1785 13:37:43.518101
1786 13:37:43.521272 ----->DramcWriteLeveling(PI) begin...
1787 13:37:43.521360 ==
1788 13:37:43.524296 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 13:37:43.528162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 13:37:43.528266 ==
1791 13:37:43.531096 Write leveling (Byte 0): 27 => 27
1792 13:37:43.534862 Write leveling (Byte 1): 27 => 27
1793 13:37:43.537971 DramcWriteLeveling(PI) end<-----
1794 13:37:43.538125
1795 13:37:43.538229 ==
1796 13:37:43.541296 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 13:37:43.544884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 13:37:43.545045 ==
1799 13:37:43.548056 [Gating] SW mode calibration
1800 13:37:43.554927 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 13:37:43.561312 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 13:37:43.564624 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1803 13:37:43.568321 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1804 13:37:43.571297 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 13:37:43.578324 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 13:37:43.581552 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 13:37:43.584719 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 13:37:43.591712 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 13:37:43.594981 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 13:37:43.598162 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:37:43.604702 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:37:43.608561 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:37:43.611878 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:37:43.618309 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1815 13:37:43.622079 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:37:43.625386 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:37:43.632056 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1818 13:37:43.635010 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1819 13:37:43.638657 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1820 13:37:43.641918 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:37:43.648280 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:37:43.652111 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:37:43.655021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:37:43.662029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:37:43.665258 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:37:43.668882 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:37:43.675825 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1828 13:37:43.678844 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
1829 13:37:43.682103 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 13:37:43.688808 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 13:37:43.692128 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 13:37:43.695883 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 13:37:43.698956 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 13:37:43.705678 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:37:43.709256 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 0)
1836 13:37:43.712168 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1837 13:37:43.719349 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:37:43.722494 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 13:37:43.725624 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:37:43.731992 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:37:43.735634 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:37:43.739006 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1843 13:37:43.745886 0 11 4 | B1->B0 | 2929 3434 | 0 0 | (1 1) (0 0)
1844 13:37:43.749004 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1845 13:37:43.752209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 13:37:43.759034 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 13:37:43.762301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 13:37:43.765499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 13:37:43.772507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 13:37:43.775713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:37:43.778905 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 13:37:43.782781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 13:37:43.788933 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 13:37:43.792362 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 13:37:43.796140 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 13:37:43.802352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 13:37:43.806270 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 13:37:43.809411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:37:43.815684 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:37:43.819540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:37:43.822606 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:37:43.829466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:37:43.832877 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:37:43.836031 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:37:43.839696 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:37:43.846512 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1867 13:37:43.849765 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 13:37:43.853049 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 13:37:43.856552 Total UI for P1: 0, mck2ui 16
1870 13:37:43.859621 best dqsien dly found for B0: ( 0, 14, 2)
1871 13:37:43.863141 Total UI for P1: 0, mck2ui 16
1872 13:37:43.866336 best dqsien dly found for B1: ( 0, 14, 4)
1873 13:37:43.869511 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1874 13:37:43.873384 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 13:37:43.873477
1876 13:37:43.879557 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1877 13:37:43.883340 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 13:37:43.883440 [Gating] SW calibration Done
1879 13:37:43.886468 ==
1880 13:37:43.886554 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 13:37:43.892961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 13:37:43.893100 ==
1883 13:37:43.893169 RX Vref Scan: 0
1884 13:37:43.893231
1885 13:37:43.896765 RX Vref 0 -> 0, step: 1
1886 13:37:43.896851
1887 13:37:43.899923 RX Delay -130 -> 252, step: 16
1888 13:37:43.903077 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1889 13:37:43.906810 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1890 13:37:43.910271 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1891 13:37:43.916476 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1892 13:37:43.920308 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1893 13:37:43.923595 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1894 13:37:43.926707 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1895 13:37:43.930619 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1896 13:37:43.933558 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1897 13:37:43.940493 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1898 13:37:43.943736 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1899 13:37:43.946759 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1900 13:37:43.950135 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1901 13:37:43.953704 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1902 13:37:43.960387 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1903 13:37:43.963566 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1904 13:37:43.963669 ==
1905 13:37:43.967204 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 13:37:43.970613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 13:37:43.970711 ==
1908 13:37:43.973764 DQS Delay:
1909 13:37:43.973853 DQS0 = 0, DQS1 = 0
1910 13:37:43.973919 DQM Delay:
1911 13:37:43.976962 DQM0 = 82, DQM1 = 77
1912 13:37:43.977105 DQ Delay:
1913 13:37:43.980226 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1914 13:37:43.984010 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1915 13:37:43.987096 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1916 13:37:43.990760 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1917 13:37:43.990862
1918 13:37:43.990928
1919 13:37:43.990989 ==
1920 13:37:43.994094 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 13:37:44.000383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 13:37:44.000527 ==
1923 13:37:44.000632
1924 13:37:44.000732
1925 13:37:44.000829 TX Vref Scan disable
1926 13:37:44.003497 == TX Byte 0 ==
1927 13:37:44.007422 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1928 13:37:44.010471 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1929 13:37:44.014180 == TX Byte 1 ==
1930 13:37:44.017282 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1931 13:37:44.020453 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1932 13:37:44.023766 ==
1933 13:37:44.023867 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 13:37:44.030677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 13:37:44.030797 ==
1936 13:37:44.042723 TX Vref=22, minBit 0, minWin=27, winSum=440
1937 13:37:44.045919 TX Vref=24, minBit 9, minWin=27, winSum=443
1938 13:37:44.049479 TX Vref=26, minBit 0, minWin=27, winSum=445
1939 13:37:44.052874 TX Vref=28, minBit 0, minWin=28, winSum=448
1940 13:37:44.056277 TX Vref=30, minBit 0, minWin=28, winSum=451
1941 13:37:44.059614 TX Vref=32, minBit 11, minWin=27, winSum=450
1942 13:37:44.066112 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1943 13:37:44.066224
1944 13:37:44.069872 Final TX Range 1 Vref 30
1945 13:37:44.069976
1946 13:37:44.070043 ==
1947 13:37:44.072998 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 13:37:44.076092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 13:37:44.076181 ==
1950 13:37:44.076247
1951 13:37:44.076306
1952 13:37:44.079860 TX Vref Scan disable
1953 13:37:44.082960 == TX Byte 0 ==
1954 13:37:44.086362 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 13:37:44.089930 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 13:37:44.093235 == TX Byte 1 ==
1957 13:37:44.095919 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1958 13:37:44.099981 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1959 13:37:44.100082
1960 13:37:44.102956 [DATLAT]
1961 13:37:44.103042 Freq=800, CH1 RK1
1962 13:37:44.103109
1963 13:37:44.106244 DATLAT Default: 0xa
1964 13:37:44.106329 0, 0xFFFF, sum = 0
1965 13:37:44.109475 1, 0xFFFF, sum = 0
1966 13:37:44.109565 2, 0xFFFF, sum = 0
1967 13:37:44.112682 3, 0xFFFF, sum = 0
1968 13:37:44.112770 4, 0xFFFF, sum = 0
1969 13:37:44.116261 5, 0xFFFF, sum = 0
1970 13:37:44.116361 6, 0xFFFF, sum = 0
1971 13:37:44.119410 7, 0xFFFF, sum = 0
1972 13:37:44.119498 8, 0xFFFF, sum = 0
1973 13:37:44.122808 9, 0x0, sum = 1
1974 13:37:44.122896 10, 0x0, sum = 2
1975 13:37:44.126422 11, 0x0, sum = 3
1976 13:37:44.126509 12, 0x0, sum = 4
1977 13:37:44.129565 best_step = 10
1978 13:37:44.129651
1979 13:37:44.129715 ==
1980 13:37:44.133299 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 13:37:44.136432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 13:37:44.136538 ==
1983 13:37:44.139682 RX Vref Scan: 0
1984 13:37:44.139767
1985 13:37:44.139831 RX Vref 0 -> 0, step: 1
1986 13:37:44.139891
1987 13:37:44.143396 RX Delay -95 -> 252, step: 8
1988 13:37:44.149734 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1989 13:37:44.153494 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1990 13:37:44.156676 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
1991 13:37:44.160133 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1992 13:37:44.163025 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1993 13:37:44.166603 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1994 13:37:44.173235 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1995 13:37:44.176600 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
1996 13:37:44.180166 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1997 13:37:44.183251 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1998 13:37:44.187120 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1999 13:37:44.193431 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2000 13:37:44.197398 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2001 13:37:44.200372 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2002 13:37:44.203810 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2003 13:37:44.207105 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2004 13:37:44.207210 ==
2005 13:37:44.210319 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 13:37:44.217374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 13:37:44.217508 ==
2008 13:37:44.217579 DQS Delay:
2009 13:37:44.220457 DQS0 = 0, DQS1 = 0
2010 13:37:44.220541 DQM Delay:
2011 13:37:44.220605 DQM0 = 80, DQM1 = 75
2012 13:37:44.224128 DQ Delay:
2013 13:37:44.227124 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2014 13:37:44.230294 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2015 13:37:44.234089 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
2016 13:37:44.237271 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2017 13:37:44.237365
2018 13:37:44.237432
2019 13:37:44.244175 [DQSOSCAuto] RK1, (LSB)MR18= 0x252f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2020 13:37:44.247349 CH1 RK1: MR19=606, MR18=252F
2021 13:37:44.253745 CH1_RK1: MR19=0x606, MR18=0x252F, DQSOSC=397, MR23=63, INC=93, DEC=62
2022 13:37:44.256965 [RxdqsGatingPostProcess] freq 800
2023 13:37:44.260826 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 13:37:44.263987 Pre-setting of DQS Precalculation
2025 13:37:44.271061 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 13:37:44.277525 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 13:37:44.284620 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 13:37:44.284744
2029 13:37:44.284812
2030 13:37:44.287453 [Calibration Summary] 1600 Mbps
2031 13:37:44.287544 CH 0, Rank 0
2032 13:37:44.290987 SW Impedance : PASS
2033 13:37:44.291076 DUTY Scan : NO K
2034 13:37:44.294512 ZQ Calibration : PASS
2035 13:37:44.297611 Jitter Meter : NO K
2036 13:37:44.297700 CBT Training : PASS
2037 13:37:44.301320 Write leveling : PASS
2038 13:37:44.304623 RX DQS gating : PASS
2039 13:37:44.304712 RX DQ/DQS(RDDQC) : PASS
2040 13:37:44.307649 TX DQ/DQS : PASS
2041 13:37:44.311352 RX DATLAT : PASS
2042 13:37:44.311443 RX DQ/DQS(Engine): PASS
2043 13:37:44.314257 TX OE : NO K
2044 13:37:44.314352 All Pass.
2045 13:37:44.314417
2046 13:37:44.317795 CH 0, Rank 1
2047 13:37:44.317897 SW Impedance : PASS
2048 13:37:44.321317 DUTY Scan : NO K
2049 13:37:44.324553 ZQ Calibration : PASS
2050 13:37:44.324641 Jitter Meter : NO K
2051 13:37:44.327685 CBT Training : PASS
2052 13:37:44.327796 Write leveling : PASS
2053 13:37:44.331390 RX DQS gating : PASS
2054 13:37:44.334649 RX DQ/DQS(RDDQC) : PASS
2055 13:37:44.334736 TX DQ/DQS : PASS
2056 13:37:44.338084 RX DATLAT : PASS
2057 13:37:44.341203 RX DQ/DQS(Engine): PASS
2058 13:37:44.341288 TX OE : NO K
2059 13:37:44.344322 All Pass.
2060 13:37:44.344400
2061 13:37:44.344461 CH 1, Rank 0
2062 13:37:44.348213 SW Impedance : PASS
2063 13:37:44.348354 DUTY Scan : NO K
2064 13:37:44.351463 ZQ Calibration : PASS
2065 13:37:44.354499 Jitter Meter : NO K
2066 13:37:44.354586 CBT Training : PASS
2067 13:37:44.358500 Write leveling : PASS
2068 13:37:44.358586 RX DQS gating : PASS
2069 13:37:44.361635 RX DQ/DQS(RDDQC) : PASS
2070 13:37:44.364743 TX DQ/DQS : PASS
2071 13:37:44.364852 RX DATLAT : PASS
2072 13:37:44.367915 RX DQ/DQS(Engine): PASS
2073 13:37:44.371087 TX OE : NO K
2074 13:37:44.371177 All Pass.
2075 13:37:44.371244
2076 13:37:44.371305 CH 1, Rank 1
2077 13:37:44.374461 SW Impedance : PASS
2078 13:37:44.378217 DUTY Scan : NO K
2079 13:37:44.378312 ZQ Calibration : PASS
2080 13:37:44.381354 Jitter Meter : NO K
2081 13:37:44.385102 CBT Training : PASS
2082 13:37:44.385195 Write leveling : PASS
2083 13:37:44.388038 RX DQS gating : PASS
2084 13:37:44.391369 RX DQ/DQS(RDDQC) : PASS
2085 13:37:44.391484 TX DQ/DQS : PASS
2086 13:37:44.394953 RX DATLAT : PASS
2087 13:37:44.395043 RX DQ/DQS(Engine): PASS
2088 13:37:44.398091 TX OE : NO K
2089 13:37:44.398185 All Pass.
2090 13:37:44.398251
2091 13:37:44.401526 DramC Write-DBI off
2092 13:37:44.404905 PER_BANK_REFRESH: Hybrid Mode
2093 13:37:44.405051 TX_TRACKING: ON
2094 13:37:44.408484 [GetDramInforAfterCalByMRR] Vendor 6.
2095 13:37:44.411588 [GetDramInforAfterCalByMRR] Revision 606.
2096 13:37:44.414712 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 13:37:44.418563 MR0 0x3b3b
2098 13:37:44.418654 MR8 0x5151
2099 13:37:44.421647 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 13:37:44.421735
2101 13:37:44.425239 MR0 0x3b3b
2102 13:37:44.425315 MR8 0x5151
2103 13:37:44.428551 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 13:37:44.428626
2105 13:37:44.438416 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 13:37:44.442007 [FAST_K] Save calibration result to emmc
2107 13:37:44.445028 [FAST_K] Save calibration result to emmc
2108 13:37:44.445148 dram_init: config_dvfs: 1
2109 13:37:44.452147 dramc_set_vcore_voltage set vcore to 662500
2110 13:37:44.452258 Read voltage for 1200, 2
2111 13:37:44.455228 Vio18 = 0
2112 13:37:44.455332 Vcore = 662500
2113 13:37:44.455398 Vdram = 0
2114 13:37:44.458318 Vddq = 0
2115 13:37:44.458404 Vmddr = 0
2116 13:37:44.462187 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 13:37:44.468661 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 13:37:44.471722 MEM_TYPE=3, freq_sel=15
2119 13:37:44.471818 sv_algorithm_assistance_LP4_1600
2120 13:37:44.478802 ============ PULL DRAM RESETB DOWN ============
2121 13:37:44.482155 ========== PULL DRAM RESETB DOWN end =========
2122 13:37:44.485387 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 13:37:44.488578 ===================================
2124 13:37:44.492186 LPDDR4 DRAM CONFIGURATION
2125 13:37:44.495446 ===================================
2126 13:37:44.499083 EX_ROW_EN[0] = 0x0
2127 13:37:44.499178 EX_ROW_EN[1] = 0x0
2128 13:37:44.502365 LP4Y_EN = 0x0
2129 13:37:44.502454 WORK_FSP = 0x0
2130 13:37:44.505441 WL = 0x4
2131 13:37:44.505525 RL = 0x4
2132 13:37:44.508935 BL = 0x2
2133 13:37:44.509045 RPST = 0x0
2134 13:37:44.512536 RD_PRE = 0x0
2135 13:37:44.512627 WR_PRE = 0x1
2136 13:37:44.516016 WR_PST = 0x0
2137 13:37:44.516103 DBI_WR = 0x0
2138 13:37:44.519320 DBI_RD = 0x0
2139 13:37:44.519406 OTF = 0x1
2140 13:37:44.522308 ===================================
2141 13:37:44.525611 ===================================
2142 13:37:44.529460 ANA top config
2143 13:37:44.532629 ===================================
2144 13:37:44.532721 DLL_ASYNC_EN = 0
2145 13:37:44.535773 ALL_SLAVE_EN = 0
2146 13:37:44.539025 NEW_RANK_MODE = 1
2147 13:37:44.542674 DLL_IDLE_MODE = 1
2148 13:37:44.545722 LP45_APHY_COMB_EN = 1
2149 13:37:44.545811 TX_ODT_DIS = 1
2150 13:37:44.549134 NEW_8X_MODE = 1
2151 13:37:44.552505 ===================================
2152 13:37:44.555784 ===================================
2153 13:37:44.559615 data_rate = 2400
2154 13:37:44.562890 CKR = 1
2155 13:37:44.562994 DQ_P2S_RATIO = 8
2156 13:37:44.565956 ===================================
2157 13:37:44.569724 CA_P2S_RATIO = 8
2158 13:37:44.572958 DQ_CA_OPEN = 0
2159 13:37:44.576118 DQ_SEMI_OPEN = 0
2160 13:37:44.579453 CA_SEMI_OPEN = 0
2161 13:37:44.583172 CA_FULL_RATE = 0
2162 13:37:44.583265 DQ_CKDIV4_EN = 0
2163 13:37:44.586164 CA_CKDIV4_EN = 0
2164 13:37:44.589634 CA_PREDIV_EN = 0
2165 13:37:44.592754 PH8_DLY = 17
2166 13:37:44.596342 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 13:37:44.599481 DQ_AAMCK_DIV = 4
2168 13:37:44.599575 CA_AAMCK_DIV = 4
2169 13:37:44.602739 CA_ADMCK_DIV = 4
2170 13:37:44.606589 DQ_TRACK_CA_EN = 0
2171 13:37:44.609684 CA_PICK = 1200
2172 13:37:44.612798 CA_MCKIO = 1200
2173 13:37:44.616546 MCKIO_SEMI = 0
2174 13:37:44.619569 PLL_FREQ = 2366
2175 13:37:44.619658 DQ_UI_PI_RATIO = 32
2176 13:37:44.623238 CA_UI_PI_RATIO = 0
2177 13:37:44.626348 ===================================
2178 13:37:44.630156 ===================================
2179 13:37:44.633355 memory_type:LPDDR4
2180 13:37:44.636527 GP_NUM : 10
2181 13:37:44.636615 SRAM_EN : 1
2182 13:37:44.639466 MD32_EN : 0
2183 13:37:44.643270 ===================================
2184 13:37:44.643372 [ANA_INIT] >>>>>>>>>>>>>>
2185 13:37:44.646682 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 13:37:44.649775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 13:37:44.653397 ===================================
2188 13:37:44.656603 data_rate = 2400,PCW = 0X5b00
2189 13:37:44.660192 ===================================
2190 13:37:44.663385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 13:37:44.670085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 13:37:44.672958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 13:37:44.680043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 13:37:44.683265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 13:37:44.686865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 13:37:44.686956 [ANA_INIT] flow start
2197 13:37:44.690047 [ANA_INIT] PLL >>>>>>>>
2198 13:37:44.693178 [ANA_INIT] PLL <<<<<<<<
2199 13:37:44.693264 [ANA_INIT] MIDPI >>>>>>>>
2200 13:37:44.696680 [ANA_INIT] MIDPI <<<<<<<<
2201 13:37:44.700095 [ANA_INIT] DLL >>>>>>>>
2202 13:37:44.703474 [ANA_INIT] DLL <<<<<<<<
2203 13:37:44.703567 [ANA_INIT] flow end
2204 13:37:44.706411 ============ LP4 DIFF to SE enter ============
2205 13:37:44.713440 ============ LP4 DIFF to SE exit ============
2206 13:37:44.713574 [ANA_INIT] <<<<<<<<<<<<<
2207 13:37:44.716433 [Flow] Enable top DCM control >>>>>
2208 13:37:44.720147 [Flow] Enable top DCM control <<<<<
2209 13:37:44.723228 Enable DLL master slave shuffle
2210 13:37:44.729947 ==============================================================
2211 13:37:44.730055 Gating Mode config
2212 13:37:44.736999 ==============================================================
2213 13:37:44.740346 Config description:
2214 13:37:44.746688 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 13:37:44.753606 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 13:37:44.760009 SELPH_MODE 0: By rank 1: By Phase
2217 13:37:44.763763 ==============================================================
2218 13:37:44.767010 GAT_TRACK_EN = 1
2219 13:37:44.770179 RX_GATING_MODE = 2
2220 13:37:44.774037 RX_GATING_TRACK_MODE = 2
2221 13:37:44.776972 SELPH_MODE = 1
2222 13:37:44.780410 PICG_EARLY_EN = 1
2223 13:37:44.783660 VALID_LAT_VALUE = 1
2224 13:37:44.790693 ==============================================================
2225 13:37:44.793864 Enter into Gating configuration >>>>
2226 13:37:44.793994 Exit from Gating configuration <<<<
2227 13:37:44.797219 Enter into DVFS_PRE_config >>>>>
2228 13:37:44.810628 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 13:37:44.813842 Exit from DVFS_PRE_config <<<<<
2230 13:37:44.817484 Enter into PICG configuration >>>>
2231 13:37:44.817580 Exit from PICG configuration <<<<
2232 13:37:44.820783 [RX_INPUT] configuration >>>>>
2233 13:37:44.824238 [RX_INPUT] configuration <<<<<
2234 13:37:44.830932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 13:37:44.833816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 13:37:44.840734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 13:37:44.847627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 13:37:44.854038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 13:37:44.860855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 13:37:44.864730 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 13:37:44.867924 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 13:37:44.871035 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 13:37:44.877633 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 13:37:44.881182 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 13:37:44.884314 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 13:37:44.888134 ===================================
2247 13:37:44.891164 LPDDR4 DRAM CONFIGURATION
2248 13:37:44.894509 ===================================
2249 13:37:44.894605 EX_ROW_EN[0] = 0x0
2250 13:37:44.897938 EX_ROW_EN[1] = 0x0
2251 13:37:44.898031 LP4Y_EN = 0x0
2252 13:37:44.901254 WORK_FSP = 0x0
2253 13:37:44.901358 WL = 0x4
2254 13:37:44.904698 RL = 0x4
2255 13:37:44.908116 BL = 0x2
2256 13:37:44.908208 RPST = 0x0
2257 13:37:44.911299 RD_PRE = 0x0
2258 13:37:44.911384 WR_PRE = 0x1
2259 13:37:44.915029 WR_PST = 0x0
2260 13:37:44.915116 DBI_WR = 0x0
2261 13:37:44.918144 DBI_RD = 0x0
2262 13:37:44.918230 OTF = 0x1
2263 13:37:44.921168 ===================================
2264 13:37:44.924659 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 13:37:44.928249 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 13:37:44.934871 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 13:37:44.938036 ===================================
2268 13:37:44.941268 LPDDR4 DRAM CONFIGURATION
2269 13:37:44.945116 ===================================
2270 13:37:44.945240 EX_ROW_EN[0] = 0x10
2271 13:37:44.947966 EX_ROW_EN[1] = 0x0
2272 13:37:44.948081 LP4Y_EN = 0x0
2273 13:37:44.951929 WORK_FSP = 0x0
2274 13:37:44.952031 WL = 0x4
2275 13:37:44.955077 RL = 0x4
2276 13:37:44.955195 BL = 0x2
2277 13:37:44.958292 RPST = 0x0
2278 13:37:44.958410 RD_PRE = 0x0
2279 13:37:44.961941 WR_PRE = 0x1
2280 13:37:44.962056 WR_PST = 0x0
2281 13:37:44.965165 DBI_WR = 0x0
2282 13:37:44.965293 DBI_RD = 0x0
2283 13:37:44.968218 OTF = 0x1
2284 13:37:44.971433 ===================================
2285 13:37:44.978587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 13:37:44.978704 ==
2287 13:37:44.981655 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 13:37:44.984929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 13:37:44.985078 ==
2290 13:37:44.988770 [Duty_Offset_Calibration]
2291 13:37:44.988859 B0:2 B1:-1 CA:1
2292 13:37:44.988924
2293 13:37:44.991864 [DutyScan_Calibration_Flow] k_type=0
2294 13:37:45.001482
2295 13:37:45.001631 ==CLK 0==
2296 13:37:45.004490 Final CLK duty delay cell = -4
2297 13:37:45.008669 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2298 13:37:45.011427 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2299 13:37:45.011546 [-4] AVG Duty = 4953%(X100)
2300 13:37:45.015236
2301 13:37:45.018428 CH0 CLK Duty spec in!! Max-Min= 156%
2302 13:37:45.021616 [DutyScan_Calibration_Flow] ====Done====
2303 13:37:45.021706
2304 13:37:45.024703 [DutyScan_Calibration_Flow] k_type=1
2305 13:37:45.040345
2306 13:37:45.040477 ==DQS 0 ==
2307 13:37:45.043318 Final DQS duty delay cell = 0
2308 13:37:45.046776 [0] MAX Duty = 5125%(X100), DQS PI = 48
2309 13:37:45.050247 [0] MIN Duty = 5000%(X100), DQS PI = 12
2310 13:37:45.050355 [0] AVG Duty = 5062%(X100)
2311 13:37:45.053806
2312 13:37:45.053894 ==DQS 1 ==
2313 13:37:45.056531 Final DQS duty delay cell = -4
2314 13:37:45.060063 [-4] MAX Duty = 5093%(X100), DQS PI = 4
2315 13:37:45.063191 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2316 13:37:45.067073 [-4] AVG Duty = 5046%(X100)
2317 13:37:45.067166
2318 13:37:45.069977 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2319 13:37:45.070076
2320 13:37:45.073776 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2321 13:37:45.076667 [DutyScan_Calibration_Flow] ====Done====
2322 13:37:45.076754
2323 13:37:45.079924 [DutyScan_Calibration_Flow] k_type=3
2324 13:37:45.097222
2325 13:37:45.097359 ==DQM 0 ==
2326 13:37:45.100258 Final DQM duty delay cell = 0
2327 13:37:45.103499 [0] MAX Duty = 5000%(X100), DQS PI = 54
2328 13:37:45.107225 [0] MIN Duty = 4907%(X100), DQS PI = 2
2329 13:37:45.107318 [0] AVG Duty = 4953%(X100)
2330 13:37:45.110291
2331 13:37:45.110377 ==DQM 1 ==
2332 13:37:45.113475 Final DQM duty delay cell = 0
2333 13:37:45.117383 [0] MAX Duty = 5156%(X100), DQS PI = 62
2334 13:37:45.120400 [0] MIN Duty = 4969%(X100), DQS PI = 10
2335 13:37:45.120495 [0] AVG Duty = 5062%(X100)
2336 13:37:45.123594
2337 13:37:45.126957 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2338 13:37:45.127046
2339 13:37:45.130830 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2340 13:37:45.133909 [DutyScan_Calibration_Flow] ====Done====
2341 13:37:45.133999
2342 13:37:45.136919 [DutyScan_Calibration_Flow] k_type=2
2343 13:37:45.152298
2344 13:37:45.152443 ==DQ 0 ==
2345 13:37:45.155863 Final DQ duty delay cell = -4
2346 13:37:45.158978 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2347 13:37:45.162568 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2348 13:37:45.165403 [-4] AVG Duty = 4969%(X100)
2349 13:37:45.165490
2350 13:37:45.165554 ==DQ 1 ==
2351 13:37:45.168755 Final DQ duty delay cell = 0
2352 13:37:45.172186 [0] MAX Duty = 5031%(X100), DQS PI = 18
2353 13:37:45.175868 [0] MIN Duty = 4907%(X100), DQS PI = 46
2354 13:37:45.179127 [0] AVG Duty = 4969%(X100)
2355 13:37:45.179217
2356 13:37:45.182119 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2357 13:37:45.182217
2358 13:37:45.186106 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2359 13:37:45.189252 [DutyScan_Calibration_Flow] ====Done====
2360 13:37:45.189341 ==
2361 13:37:45.192379 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 13:37:45.195572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 13:37:45.195659 ==
2364 13:37:45.199479 [Duty_Offset_Calibration]
2365 13:37:45.199572 B0:1 B1:1 CA:2
2366 13:37:45.199638
2367 13:37:45.202726 [DutyScan_Calibration_Flow] k_type=0
2368 13:37:45.212856
2369 13:37:45.213003 ==CLK 0==
2370 13:37:45.216129 Final CLK duty delay cell = 0
2371 13:37:45.219807 [0] MAX Duty = 5156%(X100), DQS PI = 24
2372 13:37:45.222901 [0] MIN Duty = 4938%(X100), DQS PI = 40
2373 13:37:45.223027 [0] AVG Duty = 5047%(X100)
2374 13:37:45.223101
2375 13:37:45.226394 CH1 CLK Duty spec in!! Max-Min= 218%
2376 13:37:45.233107 [DutyScan_Calibration_Flow] ====Done====
2377 13:37:45.233225
2378 13:37:45.236051 [DutyScan_Calibration_Flow] k_type=1
2379 13:37:45.252067
2380 13:37:45.252203 ==DQS 0 ==
2381 13:37:45.255245 Final DQS duty delay cell = 0
2382 13:37:45.259018 [0] MAX Duty = 5031%(X100), DQS PI = 20
2383 13:37:45.262637 [0] MIN Duty = 4813%(X100), DQS PI = 50
2384 13:37:45.262730 [0] AVG Duty = 4922%(X100)
2385 13:37:45.265754
2386 13:37:45.265841 ==DQS 1 ==
2387 13:37:45.269052 Final DQS duty delay cell = 0
2388 13:37:45.272084 [0] MAX Duty = 5062%(X100), DQS PI = 36
2389 13:37:45.275390 [0] MIN Duty = 4875%(X100), DQS PI = 16
2390 13:37:45.275478 [0] AVG Duty = 4968%(X100)
2391 13:37:45.278731
2392 13:37:45.282398 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2393 13:37:45.282487
2394 13:37:45.285639 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2395 13:37:45.289276 [DutyScan_Calibration_Flow] ====Done====
2396 13:37:45.289367
2397 13:37:45.292572 [DutyScan_Calibration_Flow] k_type=3
2398 13:37:45.308934
2399 13:37:45.309101 ==DQM 0 ==
2400 13:37:45.312205 Final DQM duty delay cell = 0
2401 13:37:45.315410 [0] MAX Duty = 5093%(X100), DQS PI = 18
2402 13:37:45.318754 [0] MIN Duty = 4875%(X100), DQS PI = 50
2403 13:37:45.318841 [0] AVG Duty = 4984%(X100)
2404 13:37:45.322464
2405 13:37:45.322571 ==DQM 1 ==
2406 13:37:45.325715 Final DQM duty delay cell = 0
2407 13:37:45.329154 [0] MAX Duty = 5156%(X100), DQS PI = 62
2408 13:37:45.332348 [0] MIN Duty = 4938%(X100), DQS PI = 24
2409 13:37:45.332438 [0] AVG Duty = 5047%(X100)
2410 13:37:45.335645
2411 13:37:45.338902 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2412 13:37:45.338996
2413 13:37:45.342060 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2414 13:37:45.345929 [DutyScan_Calibration_Flow] ====Done====
2415 13:37:45.346022
2416 13:37:45.349131 [DutyScan_Calibration_Flow] k_type=2
2417 13:37:45.365749
2418 13:37:45.365884 ==DQ 0 ==
2419 13:37:45.368671 Final DQ duty delay cell = 0
2420 13:37:45.371819 [0] MAX Duty = 5124%(X100), DQS PI = 18
2421 13:37:45.375212 [0] MIN Duty = 4907%(X100), DQS PI = 50
2422 13:37:45.375324 [0] AVG Duty = 5015%(X100)
2423 13:37:45.375391
2424 13:37:45.378593 ==DQ 1 ==
2425 13:37:45.382103 Final DQ duty delay cell = 0
2426 13:37:45.385494 [0] MAX Duty = 5093%(X100), DQS PI = 8
2427 13:37:45.389119 [0] MIN Duty = 5031%(X100), DQS PI = 2
2428 13:37:45.389220 [0] AVG Duty = 5062%(X100)
2429 13:37:45.389286
2430 13:37:45.391986 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2431 13:37:45.392097
2432 13:37:45.395959 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2433 13:37:45.398646 [DutyScan_Calibration_Flow] ====Done====
2434 13:37:45.404161 nWR fixed to 30
2435 13:37:45.407406 [ModeRegInit_LP4] CH0 RK0
2436 13:37:45.407499 [ModeRegInit_LP4] CH0 RK1
2437 13:37:45.410739 [ModeRegInit_LP4] CH1 RK0
2438 13:37:45.414437 [ModeRegInit_LP4] CH1 RK1
2439 13:37:45.414527 match AC timing 7
2440 13:37:45.420943 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 13:37:45.424231 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 13:37:45.427345 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 13:37:45.434353 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 13:37:45.437612 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 13:37:45.437709 ==
2446 13:37:45.441483 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 13:37:45.444686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 13:37:45.444803 ==
2449 13:37:45.450873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 13:37:45.457980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 13:37:45.464943 [CA 0] Center 40 (10~71) winsize 62
2452 13:37:45.468733 [CA 1] Center 39 (9~70) winsize 62
2453 13:37:45.471927 [CA 2] Center 36 (6~67) winsize 62
2454 13:37:45.475201 [CA 3] Center 36 (5~67) winsize 63
2455 13:37:45.479106 [CA 4] Center 35 (5~65) winsize 61
2456 13:37:45.481808 [CA 5] Center 34 (4~65) winsize 62
2457 13:37:45.481897
2458 13:37:45.485401 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2459 13:37:45.485490
2460 13:37:45.489027 [CATrainingPosCal] consider 1 rank data
2461 13:37:45.492193 u2DelayCellTimex100 = 270/100 ps
2462 13:37:45.495517 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2463 13:37:45.498887 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2464 13:37:45.505631 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2465 13:37:45.509012 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2466 13:37:45.512059 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2467 13:37:45.515410 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2468 13:37:45.515507
2469 13:37:45.518981 CA PerBit enable=1, Macro0, CA PI delay=34
2470 13:37:45.519071
2471 13:37:45.522454 [CBTSetCACLKResult] CA Dly = 34
2472 13:37:45.522541 CS Dly: 7 (0~38)
2473 13:37:45.522606 ==
2474 13:37:45.525517 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 13:37:45.532470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 13:37:45.532579 ==
2477 13:37:45.535703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 13:37:45.542498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2479 13:37:45.551468 [CA 0] Center 39 (9~70) winsize 62
2480 13:37:45.554458 [CA 1] Center 39 (9~70) winsize 62
2481 13:37:45.557757 [CA 2] Center 36 (6~67) winsize 62
2482 13:37:45.561466 [CA 3] Center 36 (5~67) winsize 63
2483 13:37:45.564564 [CA 4] Center 34 (4~65) winsize 62
2484 13:37:45.567925 [CA 5] Center 34 (4~64) winsize 61
2485 13:37:45.568014
2486 13:37:45.571034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 13:37:45.571118
2488 13:37:45.575038 [CATrainingPosCal] consider 2 rank data
2489 13:37:45.578138 u2DelayCellTimex100 = 270/100 ps
2490 13:37:45.581359 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2491 13:37:45.584575 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2492 13:37:45.588314 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2493 13:37:45.594831 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2494 13:37:45.597895 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2495 13:37:45.601714 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2496 13:37:45.601823
2497 13:37:45.604791 CA PerBit enable=1, Macro0, CA PI delay=34
2498 13:37:45.604875
2499 13:37:45.608421 [CBTSetCACLKResult] CA Dly = 34
2500 13:37:45.608510 CS Dly: 8 (0~41)
2501 13:37:45.608577
2502 13:37:45.611564 ----->DramcWriteLeveling(PI) begin...
2503 13:37:45.611653 ==
2504 13:37:45.614642 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 13:37:45.621815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 13:37:45.621924 ==
2507 13:37:45.625016 Write leveling (Byte 0): 30 => 30
2508 13:37:45.628565 Write leveling (Byte 1): 29 => 29
2509 13:37:45.628654 DramcWriteLeveling(PI) end<-----
2510 13:37:45.628719
2511 13:37:45.631957 ==
2512 13:37:45.632041 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 13:37:45.638477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 13:37:45.638584 ==
2515 13:37:45.641718 [Gating] SW mode calibration
2516 13:37:45.648278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 13:37:45.652082 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 13:37:45.658355 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 13:37:45.662036 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2520 13:37:45.665315 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2521 13:37:45.671680 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 13:37:45.675594 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 13:37:45.678707 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 13:37:45.681828 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 13:37:45.688680 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 13:37:45.692445 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2527 13:37:45.695665 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2528 13:37:45.701960 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 13:37:45.705693 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 13:37:45.708944 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 13:37:45.715537 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 13:37:45.719289 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:37:45.722566 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 13:37:45.729406 1 1 0 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
2535 13:37:45.732370 1 1 4 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
2536 13:37:45.735749 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 13:37:45.739320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 13:37:45.745963 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 13:37:45.749134 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 13:37:45.752349 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:37:45.759086 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 13:37:45.762390 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 13:37:45.765756 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 13:37:45.772899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 13:37:45.775895 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 13:37:45.779275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 13:37:45.786113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:37:45.789402 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:37:45.792543 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:37:45.799357 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:37:45.802813 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:37:45.806053 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:37:45.809169 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:37:45.816379 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:37:45.819249 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:37:45.822925 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:37:45.829326 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:37:45.832705 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2559 13:37:45.836334 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 13:37:45.839496 Total UI for P1: 0, mck2ui 16
2561 13:37:45.843273 best dqsien dly found for B0: ( 1, 4, 0)
2562 13:37:45.849466 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 13:37:45.849583 Total UI for P1: 0, mck2ui 16
2564 13:37:45.853239 best dqsien dly found for B1: ( 1, 4, 2)
2565 13:37:45.856531 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2566 13:37:45.859582 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2567 13:37:45.863261
2568 13:37:45.866289 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 13:37:45.869843 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2570 13:37:45.873330 [Gating] SW calibration Done
2571 13:37:45.873455 ==
2572 13:37:45.876864 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 13:37:45.880009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 13:37:45.880126 ==
2575 13:37:45.880219 RX Vref Scan: 0
2576 13:37:45.880301
2577 13:37:45.883450 RX Vref 0 -> 0, step: 1
2578 13:37:45.883544
2579 13:37:45.886934 RX Delay -40 -> 252, step: 8
2580 13:37:45.890153 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2581 13:37:45.893328 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2582 13:37:45.896796 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2583 13:37:45.903654 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2584 13:37:45.906805 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2585 13:37:45.910041 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2586 13:37:45.913721 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2587 13:37:45.917014 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2588 13:37:45.923794 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2589 13:37:45.926745 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2590 13:37:45.930454 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2591 13:37:45.933650 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2592 13:37:45.936872 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2593 13:37:45.940353 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2594 13:37:45.946814 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2595 13:37:45.950688 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2596 13:37:45.950856 ==
2597 13:37:45.953677 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:37:45.957234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 13:37:45.957366 ==
2600 13:37:45.960477 DQS Delay:
2601 13:37:45.960580 DQS0 = 0, DQS1 = 0
2602 13:37:45.960648 DQM Delay:
2603 13:37:45.963646 DQM0 = 116, DQM1 = 107
2604 13:37:45.963755 DQ Delay:
2605 13:37:45.967380 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2606 13:37:45.970465 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2607 13:37:45.974070 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2608 13:37:45.980285 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2609 13:37:45.980424
2610 13:37:45.980524
2611 13:37:45.980623 ==
2612 13:37:45.984131 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 13:37:45.986948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 13:37:45.987060 ==
2615 13:37:45.987149
2616 13:37:45.987231
2617 13:37:45.990849 TX Vref Scan disable
2618 13:37:45.990982 == TX Byte 0 ==
2619 13:37:45.996924 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2620 13:37:46.000650 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2621 13:37:46.000801 == TX Byte 1 ==
2622 13:37:46.007477 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2623 13:37:46.010576 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2624 13:37:46.010710 ==
2625 13:37:46.014370 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 13:37:46.017409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 13:37:46.017526 ==
2628 13:37:46.029396 TX Vref=22, minBit 1, minWin=25, winSum=418
2629 13:37:46.033090 TX Vref=24, minBit 1, minWin=25, winSum=424
2630 13:37:46.036505 TX Vref=26, minBit 1, minWin=25, winSum=430
2631 13:37:46.039605 TX Vref=28, minBit 0, minWin=26, winSum=435
2632 13:37:46.043203 TX Vref=30, minBit 4, minWin=26, winSum=434
2633 13:37:46.046314 TX Vref=32, minBit 0, minWin=26, winSum=430
2634 13:37:46.053406 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 28
2635 13:37:46.053548
2636 13:37:46.056680 Final TX Range 1 Vref 28
2637 13:37:46.056777
2638 13:37:46.056880 ==
2639 13:37:46.059573 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 13:37:46.063349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 13:37:46.063472 ==
2642 13:37:46.063576
2643 13:37:46.063676
2644 13:37:46.066453 TX Vref Scan disable
2645 13:37:46.069576 == TX Byte 0 ==
2646 13:37:46.072912 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2647 13:37:46.076656 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2648 13:37:46.079555 == TX Byte 1 ==
2649 13:37:46.083006 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2650 13:37:46.086893 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2651 13:37:46.087021
2652 13:37:46.090002 [DATLAT]
2653 13:37:46.090095 Freq=1200, CH0 RK0
2654 13:37:46.090162
2655 13:37:46.092890 DATLAT Default: 0xd
2656 13:37:46.093031 0, 0xFFFF, sum = 0
2657 13:37:46.096600 1, 0xFFFF, sum = 0
2658 13:37:46.096697 2, 0xFFFF, sum = 0
2659 13:37:46.099656 3, 0xFFFF, sum = 0
2660 13:37:46.099748 4, 0xFFFF, sum = 0
2661 13:37:46.103205 5, 0xFFFF, sum = 0
2662 13:37:46.103297 6, 0xFFFF, sum = 0
2663 13:37:46.106373 7, 0xFFFF, sum = 0
2664 13:37:46.106463 8, 0xFFFF, sum = 0
2665 13:37:46.109536 9, 0xFFFF, sum = 0
2666 13:37:46.109629 10, 0xFFFF, sum = 0
2667 13:37:46.113007 11, 0xFFFF, sum = 0
2668 13:37:46.113111 12, 0x0, sum = 1
2669 13:37:46.116410 13, 0x0, sum = 2
2670 13:37:46.116500 14, 0x0, sum = 3
2671 13:37:46.120046 15, 0x0, sum = 4
2672 13:37:46.120135 best_step = 13
2673 13:37:46.120203
2674 13:37:46.120264 ==
2675 13:37:46.122982 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 13:37:46.130230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 13:37:46.130354 ==
2678 13:37:46.130428 RX Vref Scan: 1
2679 13:37:46.130490
2680 13:37:46.133277 Set Vref Range= 32 -> 127
2681 13:37:46.133381
2682 13:37:46.136355 RX Vref 32 -> 127, step: 1
2683 13:37:46.136441
2684 13:37:46.136506 RX Delay -21 -> 252, step: 4
2685 13:37:46.140016
2686 13:37:46.140104 Set Vref, RX VrefLevel [Byte0]: 32
2687 13:37:46.143145 [Byte1]: 32
2688 13:37:46.147825
2689 13:37:46.147931 Set Vref, RX VrefLevel [Byte0]: 33
2690 13:37:46.150926 [Byte1]: 33
2691 13:37:46.156006
2692 13:37:46.156148 Set Vref, RX VrefLevel [Byte0]: 34
2693 13:37:46.159309 [Byte1]: 34
2694 13:37:46.163645
2695 13:37:46.163847 Set Vref, RX VrefLevel [Byte0]: 35
2696 13:37:46.167316 [Byte1]: 35
2697 13:37:46.171832
2698 13:37:46.171937 Set Vref, RX VrefLevel [Byte0]: 36
2699 13:37:46.174932 [Byte1]: 36
2700 13:37:46.179395
2701 13:37:46.179570 Set Vref, RX VrefLevel [Byte0]: 37
2702 13:37:46.182589 [Byte1]: 37
2703 13:37:46.187520
2704 13:37:46.187619 Set Vref, RX VrefLevel [Byte0]: 38
2705 13:37:46.191034 [Byte1]: 38
2706 13:37:46.195418
2707 13:37:46.195537 Set Vref, RX VrefLevel [Byte0]: 39
2708 13:37:46.198758 [Byte1]: 39
2709 13:37:46.203428
2710 13:37:46.203527 Set Vref, RX VrefLevel [Byte0]: 40
2711 13:37:46.206461 [Byte1]: 40
2712 13:37:46.211456
2713 13:37:46.211555 Set Vref, RX VrefLevel [Byte0]: 41
2714 13:37:46.214779 [Byte1]: 41
2715 13:37:46.219473
2716 13:37:46.219566 Set Vref, RX VrefLevel [Byte0]: 42
2717 13:37:46.222600 [Byte1]: 42
2718 13:37:46.226966
2719 13:37:46.227063 Set Vref, RX VrefLevel [Byte0]: 43
2720 13:37:46.230117 [Byte1]: 43
2721 13:37:46.234850
2722 13:37:46.234966 Set Vref, RX VrefLevel [Byte0]: 44
2723 13:37:46.238206 [Byte1]: 44
2724 13:37:46.243071
2725 13:37:46.243173 Set Vref, RX VrefLevel [Byte0]: 45
2726 13:37:46.246008 [Byte1]: 45
2727 13:37:46.250765
2728 13:37:46.250864 Set Vref, RX VrefLevel [Byte0]: 46
2729 13:37:46.254281 [Byte1]: 46
2730 13:37:46.258698
2731 13:37:46.258806 Set Vref, RX VrefLevel [Byte0]: 47
2732 13:37:46.262549 [Byte1]: 47
2733 13:37:46.266927
2734 13:37:46.267027 Set Vref, RX VrefLevel [Byte0]: 48
2735 13:37:46.270059 [Byte1]: 48
2736 13:37:46.274586
2737 13:37:46.274686 Set Vref, RX VrefLevel [Byte0]: 49
2738 13:37:46.278276 [Byte1]: 49
2739 13:37:46.282617
2740 13:37:46.282715 Set Vref, RX VrefLevel [Byte0]: 50
2741 13:37:46.285850 [Byte1]: 50
2742 13:37:46.290269
2743 13:37:46.290376 Set Vref, RX VrefLevel [Byte0]: 51
2744 13:37:46.294091 [Byte1]: 51
2745 13:37:46.298116
2746 13:37:46.298211 Set Vref, RX VrefLevel [Byte0]: 52
2747 13:37:46.301487 [Byte1]: 52
2748 13:37:46.306598
2749 13:37:46.306694 Set Vref, RX VrefLevel [Byte0]: 53
2750 13:37:46.309444 [Byte1]: 53
2751 13:37:46.314286
2752 13:37:46.314384 Set Vref, RX VrefLevel [Byte0]: 54
2753 13:37:46.317455 [Byte1]: 54
2754 13:37:46.322006
2755 13:37:46.322102 Set Vref, RX VrefLevel [Byte0]: 55
2756 13:37:46.325717 [Byte1]: 55
2757 13:37:46.329953
2758 13:37:46.330047 Set Vref, RX VrefLevel [Byte0]: 56
2759 13:37:46.333914 [Byte1]: 56
2760 13:37:46.338254
2761 13:37:46.338354 Set Vref, RX VrefLevel [Byte0]: 57
2762 13:37:46.341381 [Byte1]: 57
2763 13:37:46.346283
2764 13:37:46.346388 Set Vref, RX VrefLevel [Byte0]: 58
2765 13:37:46.349297 [Byte1]: 58
2766 13:37:46.353773
2767 13:37:46.353885 Set Vref, RX VrefLevel [Byte0]: 59
2768 13:37:46.357283 [Byte1]: 59
2769 13:37:46.361645
2770 13:37:46.361740 Set Vref, RX VrefLevel [Byte0]: 60
2771 13:37:46.365183 [Byte1]: 60
2772 13:37:46.369959
2773 13:37:46.370060 Set Vref, RX VrefLevel [Byte0]: 61
2774 13:37:46.373011 [Byte1]: 61
2775 13:37:46.377902
2776 13:37:46.378006 Set Vref, RX VrefLevel [Byte0]: 62
2777 13:37:46.381187 [Byte1]: 62
2778 13:37:46.385637
2779 13:37:46.385742 Set Vref, RX VrefLevel [Byte0]: 63
2780 13:37:46.388778 [Byte1]: 63
2781 13:37:46.393825
2782 13:37:46.393933 Set Vref, RX VrefLevel [Byte0]: 64
2783 13:37:46.397167 [Byte1]: 64
2784 13:37:46.401542
2785 13:37:46.401646 Set Vref, RX VrefLevel [Byte0]: 65
2786 13:37:46.404631 [Byte1]: 65
2787 13:37:46.409260
2788 13:37:46.409363 Set Vref, RX VrefLevel [Byte0]: 66
2789 13:37:46.412750 [Byte1]: 66
2790 13:37:46.417465
2791 13:37:46.417568 Set Vref, RX VrefLevel [Byte0]: 67
2792 13:37:46.420846 [Byte1]: 67
2793 13:37:46.425261
2794 13:37:46.425361 Set Vref, RX VrefLevel [Byte0]: 68
2795 13:37:46.428406 [Byte1]: 68
2796 13:37:46.433468
2797 13:37:46.433570 Set Vref, RX VrefLevel [Byte0]: 69
2798 13:37:46.436171 [Byte1]: 69
2799 13:37:46.441267
2800 13:37:46.441369 Final RX Vref Byte 0 = 54 to rank0
2801 13:37:46.444554 Final RX Vref Byte 1 = 53 to rank0
2802 13:37:46.447773 Final RX Vref Byte 0 = 54 to rank1
2803 13:37:46.451001 Final RX Vref Byte 1 = 53 to rank1==
2804 13:37:46.454760 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 13:37:46.457739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 13:37:46.461557 ==
2807 13:37:46.461656 DQS Delay:
2808 13:37:46.461722 DQS0 = 0, DQS1 = 0
2809 13:37:46.464623 DQM Delay:
2810 13:37:46.464706 DQM0 = 115, DQM1 = 105
2811 13:37:46.467890 DQ Delay:
2812 13:37:46.471646 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2813 13:37:46.474451 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2814 13:37:46.477763 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2815 13:37:46.481549 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2816 13:37:46.481659
2817 13:37:46.481757
2818 13:37:46.488390 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2819 13:37:46.491528 CH0 RK0: MR19=303, MR18=FFEE
2820 13:37:46.498431 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2821 13:37:46.498570
2822 13:37:46.501842 ----->DramcWriteLeveling(PI) begin...
2823 13:37:46.501933 ==
2824 13:37:46.505003 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 13:37:46.508112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 13:37:46.508202 ==
2827 13:37:46.512128 Write leveling (Byte 0): 34 => 34
2828 13:37:46.514897 Write leveling (Byte 1): 31 => 31
2829 13:37:46.518067 DramcWriteLeveling(PI) end<-----
2830 13:37:46.518160
2831 13:37:46.518224 ==
2832 13:37:46.521422 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 13:37:46.524997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 13:37:46.525133 ==
2835 13:37:46.528570 [Gating] SW mode calibration
2836 13:37:46.534825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 13:37:46.541754 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 13:37:46.545005 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2839 13:37:46.551602 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2840 13:37:46.555396 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 13:37:46.558675 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 13:37:46.561840 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 13:37:46.568487 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 13:37:46.572148 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2845 13:37:46.575506 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2846 13:37:46.581837 1 0 0 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
2847 13:37:46.585657 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2848 13:37:46.589254 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 13:37:46.595484 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 13:37:46.598886 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 13:37:46.602345 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 13:37:46.608882 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2853 13:37:46.612114 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2854 13:37:46.615310 1 1 0 | B1->B0 | 2f2f 3c3c | 0 1 | (0 0) (0 0)
2855 13:37:46.619025 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2856 13:37:46.625435 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 13:37:46.628948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 13:37:46.632526 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 13:37:46.638835 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 13:37:46.642544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 13:37:46.645834 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2862 13:37:46.652300 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2863 13:37:46.655601 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2864 13:37:46.658778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 13:37:46.665827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 13:37:46.668758 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 13:37:46.672310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 13:37:46.678633 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 13:37:46.682384 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 13:37:46.685440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 13:37:46.692080 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:37:46.695751 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:37:46.698824 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:37:46.702576 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:37:46.709434 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:37:46.712264 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:37:46.715543 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2878 13:37:46.722527 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2879 13:37:46.725805 Total UI for P1: 0, mck2ui 16
2880 13:37:46.728827 best dqsien dly found for B0: ( 1, 3, 28)
2881 13:37:46.732418 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 13:37:46.735535 Total UI for P1: 0, mck2ui 16
2883 13:37:46.739294 best dqsien dly found for B1: ( 1, 4, 0)
2884 13:37:46.742441 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2885 13:37:46.746069 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2886 13:37:46.746170
2887 13:37:46.749493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2888 13:37:46.752552 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2889 13:37:46.755895 [Gating] SW calibration Done
2890 13:37:46.755996 ==
2891 13:37:46.759029 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 13:37:46.762444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 13:37:46.762540 ==
2894 13:37:46.766287 RX Vref Scan: 0
2895 13:37:46.766375
2896 13:37:46.769493 RX Vref 0 -> 0, step: 1
2897 13:37:46.769583
2898 13:37:46.769650 RX Delay -40 -> 252, step: 8
2899 13:37:46.775711 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2900 13:37:46.779240 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2901 13:37:46.782454 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2902 13:37:46.786382 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2903 13:37:46.789558 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2904 13:37:46.796123 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2905 13:37:46.799449 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2906 13:37:46.802917 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2907 13:37:46.806071 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2908 13:37:46.809291 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2909 13:37:46.813136 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2910 13:37:46.819516 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2911 13:37:46.822868 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2912 13:37:46.826193 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2913 13:37:46.829329 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2914 13:37:46.832971 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2915 13:37:46.836340 ==
2916 13:37:46.839698 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 13:37:46.843258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 13:37:46.843357 ==
2919 13:37:46.843423 DQS Delay:
2920 13:37:46.846492 DQS0 = 0, DQS1 = 0
2921 13:37:46.846584 DQM Delay:
2922 13:37:46.849707 DQM0 = 115, DQM1 = 106
2923 13:37:46.849796 DQ Delay:
2924 13:37:46.853214 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2925 13:37:46.856703 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2926 13:37:46.859678 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2927 13:37:46.862920 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2928 13:37:46.863017
2929 13:37:46.863083
2930 13:37:46.863142 ==
2931 13:37:46.866697 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 13:37:46.869980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 13:37:46.873018 ==
2934 13:37:46.873110
2935 13:37:46.873175
2936 13:37:46.873235 TX Vref Scan disable
2937 13:37:46.876899 == TX Byte 0 ==
2938 13:37:46.879866 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2939 13:37:46.883305 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2940 13:37:46.886529 == TX Byte 1 ==
2941 13:37:46.890256 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2942 13:37:46.893238 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2943 13:37:46.896368 ==
2944 13:37:46.896469 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 13:37:46.903120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 13:37:46.903230 ==
2947 13:37:46.914220 TX Vref=22, minBit 1, minWin=25, winSum=416
2948 13:37:46.917401 TX Vref=24, minBit 0, minWin=25, winSum=419
2949 13:37:46.921235 TX Vref=26, minBit 1, minWin=25, winSum=424
2950 13:37:46.924505 TX Vref=28, minBit 2, minWin=26, winSum=429
2951 13:37:46.927698 TX Vref=30, minBit 3, minWin=26, winSum=432
2952 13:37:46.931325 TX Vref=32, minBit 1, minWin=26, winSum=425
2953 13:37:46.937650 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
2954 13:37:46.937773
2955 13:37:46.941320 Final TX Range 1 Vref 30
2956 13:37:46.941412
2957 13:37:46.941479 ==
2958 13:37:46.944308 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 13:37:46.947593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 13:37:46.947687 ==
2961 13:37:46.947791
2962 13:37:46.947851
2963 13:37:46.950828 TX Vref Scan disable
2964 13:37:46.954180 == TX Byte 0 ==
2965 13:37:46.957979 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2966 13:37:46.961260 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2967 13:37:46.964712 == TX Byte 1 ==
2968 13:37:46.967981 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2969 13:37:46.971475 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2970 13:37:46.971578
2971 13:37:46.974477 [DATLAT]
2972 13:37:46.974569 Freq=1200, CH0 RK1
2973 13:37:46.974636
2974 13:37:46.978284 DATLAT Default: 0xd
2975 13:37:46.978372 0, 0xFFFF, sum = 0
2976 13:37:46.981424 1, 0xFFFF, sum = 0
2977 13:37:46.981510 2, 0xFFFF, sum = 0
2978 13:37:46.984713 3, 0xFFFF, sum = 0
2979 13:37:46.984798 4, 0xFFFF, sum = 0
2980 13:37:46.988265 5, 0xFFFF, sum = 0
2981 13:37:46.988355 6, 0xFFFF, sum = 0
2982 13:37:46.991247 7, 0xFFFF, sum = 0
2983 13:37:46.991335 8, 0xFFFF, sum = 0
2984 13:37:46.994830 9, 0xFFFF, sum = 0
2985 13:37:46.994916 10, 0xFFFF, sum = 0
2986 13:37:46.998092 11, 0xFFFF, sum = 0
2987 13:37:46.998215 12, 0x0, sum = 1
2988 13:37:47.001787 13, 0x0, sum = 2
2989 13:37:47.001876 14, 0x0, sum = 3
2990 13:37:47.004660 15, 0x0, sum = 4
2991 13:37:47.004747 best_step = 13
2992 13:37:47.004813
2993 13:37:47.004874 ==
2994 13:37:47.008384 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 13:37:47.014754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 13:37:47.014874 ==
2997 13:37:47.014945 RX Vref Scan: 0
2998 13:37:47.015006
2999 13:37:47.017906 RX Vref 0 -> 0, step: 1
3000 13:37:47.017991
3001 13:37:47.021652 RX Delay -21 -> 252, step: 4
3002 13:37:47.024654 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3003 13:37:47.028415 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3004 13:37:47.031529 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3005 13:37:47.038412 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3006 13:37:47.041342 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3007 13:37:47.044970 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3008 13:37:47.048600 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3009 13:37:47.051732 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3010 13:37:47.058325 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3011 13:37:47.061363 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3012 13:37:47.064989 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3013 13:37:47.068522 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3014 13:37:47.071483 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3015 13:37:47.078308 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3016 13:37:47.081585 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3017 13:37:47.085098 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3018 13:37:47.085224 ==
3019 13:37:47.088643 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 13:37:47.091715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 13:37:47.091814 ==
3022 13:37:47.095268 DQS Delay:
3023 13:37:47.095359 DQS0 = 0, DQS1 = 0
3024 13:37:47.095425 DQM Delay:
3025 13:37:47.098198 DQM0 = 114, DQM1 = 105
3026 13:37:47.098284 DQ Delay:
3027 13:37:47.102033 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3028 13:37:47.105211 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3029 13:37:47.108793 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =94
3030 13:37:47.115460 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3031 13:37:47.115600
3032 13:37:47.115668
3033 13:37:47.122454 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3034 13:37:47.125549 CH0 RK1: MR19=403, MR18=3F5
3035 13:37:47.132436 CH0_RK1: MR19=0x403, MR18=0x3F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3036 13:37:47.132586 [RxdqsGatingPostProcess] freq 1200
3037 13:37:47.138734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3038 13:37:47.142637 best DQS0 dly(2T, 0.5T) = (0, 12)
3039 13:37:47.145676 best DQS1 dly(2T, 0.5T) = (0, 12)
3040 13:37:47.149356 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3041 13:37:47.152358 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3042 13:37:47.156006 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 13:37:47.159166 best DQS1 dly(2T, 0.5T) = (0, 12)
3044 13:37:47.162880 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 13:37:47.165762 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3046 13:37:47.165860 Pre-setting of DQS Precalculation
3047 13:37:47.172333 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3048 13:37:47.172451 ==
3049 13:37:47.176031 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 13:37:47.179188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 13:37:47.179290 ==
3052 13:37:47.186091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3053 13:37:47.192831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3054 13:37:47.199642 [CA 0] Center 38 (8~68) winsize 61
3055 13:37:47.203239 [CA 1] Center 38 (8~68) winsize 61
3056 13:37:47.206182 [CA 2] Center 34 (4~65) winsize 62
3057 13:37:47.209722 [CA 3] Center 34 (4~64) winsize 61
3058 13:37:47.213493 [CA 4] Center 34 (4~65) winsize 62
3059 13:37:47.216555 [CA 5] Center 33 (3~64) winsize 62
3060 13:37:47.216667
3061 13:37:47.219674 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3062 13:37:47.219762
3063 13:37:47.223206 [CATrainingPosCal] consider 1 rank data
3064 13:37:47.226413 u2DelayCellTimex100 = 270/100 ps
3065 13:37:47.229643 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3066 13:37:47.233478 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3067 13:37:47.236682 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3068 13:37:47.242966 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 13:37:47.246808 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3070 13:37:47.249989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3071 13:37:47.250114
3072 13:37:47.253014 CA PerBit enable=1, Macro0, CA PI delay=33
3073 13:37:47.253153
3074 13:37:47.256801 [CBTSetCACLKResult] CA Dly = 33
3075 13:37:47.256948 CS Dly: 6 (0~37)
3076 13:37:47.257053 ==
3077 13:37:47.259989 Dram Type= 6, Freq= 0, CH_1, rank 1
3078 13:37:47.266872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 13:37:47.266991 ==
3080 13:37:47.269834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 13:37:47.276736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 13:37:47.285753 [CA 0] Center 38 (8~68) winsize 61
3083 13:37:47.288848 [CA 1] Center 37 (8~67) winsize 60
3084 13:37:47.291964 [CA 2] Center 34 (4~65) winsize 62
3085 13:37:47.295230 [CA 3] Center 34 (4~65) winsize 62
3086 13:37:47.298867 [CA 4] Center 35 (5~65) winsize 61
3087 13:37:47.301964 [CA 5] Center 33 (3~64) winsize 62
3088 13:37:47.302058
3089 13:37:47.305351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3090 13:37:47.305468
3091 13:37:47.308813 [CATrainingPosCal] consider 2 rank data
3092 13:37:47.312226 u2DelayCellTimex100 = 270/100 ps
3093 13:37:47.315210 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 13:37:47.318457 CA1 delay=37 (8~67),Diff = 4 PI (19 cell)
3095 13:37:47.325613 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3096 13:37:47.328653 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 13:37:47.332510 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3098 13:37:47.335616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3099 13:37:47.335741
3100 13:37:47.338704 CA PerBit enable=1, Macro0, CA PI delay=33
3101 13:37:47.338793
3102 13:37:47.342042 [CBTSetCACLKResult] CA Dly = 33
3103 13:37:47.342133 CS Dly: 7 (0~39)
3104 13:37:47.342200
3105 13:37:47.345779 ----->DramcWriteLeveling(PI) begin...
3106 13:37:47.345879 ==
3107 13:37:47.348862 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 13:37:47.355770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 13:37:47.355901 ==
3110 13:37:47.358877 Write leveling (Byte 0): 25 => 25
3111 13:37:47.362769 Write leveling (Byte 1): 28 => 28
3112 13:37:47.362870 DramcWriteLeveling(PI) end<-----
3113 13:37:47.362941
3114 13:37:47.365644 ==
3115 13:37:47.365734 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 13:37:47.372539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 13:37:47.372644 ==
3118 13:37:47.375678 [Gating] SW mode calibration
3119 13:37:47.382761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3120 13:37:47.386006 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3121 13:37:47.392496 0 15 0 | B1->B0 | 2929 2323 | 1 1 | (0 0) (0 0)
3122 13:37:47.396414 0 15 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3123 13:37:47.399336 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3124 13:37:47.406005 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 13:37:47.409163 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 13:37:47.412805 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 13:37:47.415781 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3128 13:37:47.423057 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3129 13:37:47.426381 1 0 0 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
3130 13:37:47.429525 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 13:37:47.436049 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 13:37:47.439861 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 13:37:47.442978 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 13:37:47.449781 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 13:37:47.453511 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 13:37:47.456581 1 0 28 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
3137 13:37:47.463312 1 1 0 | B1->B0 | 4141 2f2f | 0 0 | (0 0) (0 0)
3138 13:37:47.466366 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 13:37:47.470076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 13:37:47.473172 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 13:37:47.479995 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 13:37:47.483146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 13:37:47.486630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 13:37:47.493446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 13:37:47.496775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3146 13:37:47.499889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 13:37:47.506641 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 13:37:47.510429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 13:37:47.513532 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 13:37:47.517342 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 13:37:47.523607 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 13:37:47.526764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 13:37:47.530545 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:37:47.537171 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:37:47.540544 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:37:47.543528 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:37:47.550179 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:37:47.553605 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:37:47.556961 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:37:47.563776 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3161 13:37:47.567528 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3162 13:37:47.570566 Total UI for P1: 0, mck2ui 16
3163 13:37:47.574301 best dqsien dly found for B1: ( 1, 3, 30)
3164 13:37:47.577263 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 13:37:47.580429 Total UI for P1: 0, mck2ui 16
3166 13:37:47.584293 best dqsien dly found for B0: ( 1, 3, 30)
3167 13:37:47.587396 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3168 13:37:47.591046 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3169 13:37:47.591146
3170 13:37:47.594505 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3171 13:37:47.597529 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3172 13:37:47.600695 [Gating] SW calibration Done
3173 13:37:47.600788 ==
3174 13:37:47.603956 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 13:37:47.610759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 13:37:47.610871 ==
3177 13:37:47.610941 RX Vref Scan: 0
3178 13:37:47.611001
3179 13:37:47.614536 RX Vref 0 -> 0, step: 1
3180 13:37:47.614624
3181 13:37:47.617648 RX Delay -40 -> 252, step: 8
3182 13:37:47.621427 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3183 13:37:47.624614 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3184 13:37:47.627845 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3185 13:37:47.631450 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3186 13:37:47.637785 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3187 13:37:47.641208 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3188 13:37:47.644669 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3189 13:37:47.647593 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3190 13:37:47.650878 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3191 13:37:47.654905 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3192 13:37:47.661522 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3193 13:37:47.664386 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3194 13:37:47.667923 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3195 13:37:47.671703 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3196 13:37:47.674912 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3197 13:37:47.681657 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3198 13:37:47.681795 ==
3199 13:37:47.684799 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 13:37:47.689615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 13:37:47.689757 ==
3202 13:37:47.689848 DQS Delay:
3203 13:37:47.691401 DQS0 = 0, DQS1 = 0
3204 13:37:47.691485 DQM Delay:
3205 13:37:47.694620 DQM0 = 115, DQM1 = 108
3206 13:37:47.694711 DQ Delay:
3207 13:37:47.698466 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3208 13:37:47.701536 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3209 13:37:47.705100 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3210 13:37:47.708157 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3211 13:37:47.708257
3212 13:37:47.708394
3213 13:37:47.708515 ==
3214 13:37:47.711919 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 13:37:47.718681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 13:37:47.718796 ==
3217 13:37:47.718939
3218 13:37:47.719015
3219 13:37:47.719077 TX Vref Scan disable
3220 13:37:47.721779 == TX Byte 0 ==
3221 13:37:47.725574 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3222 13:37:47.728787 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3223 13:37:47.732007 == TX Byte 1 ==
3224 13:37:47.735748 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3225 13:37:47.739057 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3226 13:37:47.742217 ==
3227 13:37:47.745385 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 13:37:47.748630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 13:37:47.748719 ==
3230 13:37:47.760158 TX Vref=22, minBit 1, minWin=25, winSum=413
3231 13:37:47.763386 TX Vref=24, minBit 1, minWin=25, winSum=418
3232 13:37:47.766450 TX Vref=26, minBit 8, minWin=25, winSum=419
3233 13:37:47.769991 TX Vref=28, minBit 0, minWin=26, winSum=426
3234 13:37:47.773008 TX Vref=30, minBit 1, minWin=26, winSum=429
3235 13:37:47.776603 TX Vref=32, minBit 1, minWin=26, winSum=429
3236 13:37:47.783597 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3237 13:37:47.783702
3238 13:37:47.786700 Final TX Range 1 Vref 30
3239 13:37:47.786790
3240 13:37:47.786854 ==
3241 13:37:47.789761 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 13:37:47.793528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 13:37:47.793624 ==
3244 13:37:47.793691
3245 13:37:47.793753
3246 13:37:47.796744 TX Vref Scan disable
3247 13:37:47.800496 == TX Byte 0 ==
3248 13:37:47.803590 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3249 13:37:47.806780 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3250 13:37:47.810309 == TX Byte 1 ==
3251 13:37:47.813298 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3252 13:37:47.817005 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3253 13:37:47.817144
3254 13:37:47.820071 [DATLAT]
3255 13:37:47.820182 Freq=1200, CH1 RK0
3256 13:37:47.820279
3257 13:37:47.823698 DATLAT Default: 0xd
3258 13:37:47.823805 0, 0xFFFF, sum = 0
3259 13:37:47.826812 1, 0xFFFF, sum = 0
3260 13:37:47.826914 2, 0xFFFF, sum = 0
3261 13:37:47.830389 3, 0xFFFF, sum = 0
3262 13:37:47.830507 4, 0xFFFF, sum = 0
3263 13:37:47.833594 5, 0xFFFF, sum = 0
3264 13:37:47.833706 6, 0xFFFF, sum = 0
3265 13:37:47.836788 7, 0xFFFF, sum = 0
3266 13:37:47.836898 8, 0xFFFF, sum = 0
3267 13:37:47.840378 9, 0xFFFF, sum = 0
3268 13:37:47.840490 10, 0xFFFF, sum = 0
3269 13:37:47.843527 11, 0xFFFF, sum = 0
3270 13:37:47.843637 12, 0x0, sum = 1
3271 13:37:47.846703 13, 0x0, sum = 2
3272 13:37:47.846813 14, 0x0, sum = 3
3273 13:37:47.850545 15, 0x0, sum = 4
3274 13:37:47.850637 best_step = 13
3275 13:37:47.850702
3276 13:37:47.850762 ==
3277 13:37:47.854055 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 13:37:47.860806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 13:37:47.860922 ==
3280 13:37:47.861033 RX Vref Scan: 1
3281 13:37:47.861123
3282 13:37:47.864144 Set Vref Range= 32 -> 127
3283 13:37:47.864253
3284 13:37:47.867106 RX Vref 32 -> 127, step: 1
3285 13:37:47.867198
3286 13:37:47.867264 RX Delay -21 -> 252, step: 4
3287 13:37:47.867325
3288 13:37:47.870488 Set Vref, RX VrefLevel [Byte0]: 32
3289 13:37:47.873521 [Byte1]: 32
3290 13:37:47.877917
3291 13:37:47.878023 Set Vref, RX VrefLevel [Byte0]: 33
3292 13:37:47.881333 [Byte1]: 33
3293 13:37:47.885981
3294 13:37:47.886127 Set Vref, RX VrefLevel [Byte0]: 34
3295 13:37:47.889603 [Byte1]: 34
3296 13:37:47.894004
3297 13:37:47.894101 Set Vref, RX VrefLevel [Byte0]: 35
3298 13:37:47.897205 [Byte1]: 35
3299 13:37:47.902145
3300 13:37:47.902247 Set Vref, RX VrefLevel [Byte0]: 36
3301 13:37:47.905410 [Byte1]: 36
3302 13:37:47.909766
3303 13:37:47.909895 Set Vref, RX VrefLevel [Byte0]: 37
3304 13:37:47.912907 [Byte1]: 37
3305 13:37:47.917798
3306 13:37:47.917892 Set Vref, RX VrefLevel [Byte0]: 38
3307 13:37:47.920761 [Byte1]: 38
3308 13:37:47.925624
3309 13:37:47.925723 Set Vref, RX VrefLevel [Byte0]: 39
3310 13:37:47.928848 [Byte1]: 39
3311 13:37:47.933277
3312 13:37:47.933379 Set Vref, RX VrefLevel [Byte0]: 40
3313 13:37:47.936947 [Byte1]: 40
3314 13:37:47.941921
3315 13:37:47.942029 Set Vref, RX VrefLevel [Byte0]: 41
3316 13:37:47.945019 [Byte1]: 41
3317 13:37:47.949477
3318 13:37:47.949571 Set Vref, RX VrefLevel [Byte0]: 42
3319 13:37:47.952556 [Byte1]: 42
3320 13:37:47.957682
3321 13:37:47.957782 Set Vref, RX VrefLevel [Byte0]: 43
3322 13:37:47.960812 [Byte1]: 43
3323 13:37:47.965248
3324 13:37:47.965343 Set Vref, RX VrefLevel [Byte0]: 44
3325 13:37:47.968387 [Byte1]: 44
3326 13:37:47.973500
3327 13:37:47.973599 Set Vref, RX VrefLevel [Byte0]: 45
3328 13:37:47.976641 [Byte1]: 45
3329 13:37:47.980874
3330 13:37:47.980968 Set Vref, RX VrefLevel [Byte0]: 46
3331 13:37:47.984483 [Byte1]: 46
3332 13:37:47.989478
3333 13:37:47.989586 Set Vref, RX VrefLevel [Byte0]: 47
3334 13:37:47.992461 [Byte1]: 47
3335 13:37:47.997190
3336 13:37:47.997285 Set Vref, RX VrefLevel [Byte0]: 48
3337 13:37:48.000258 [Byte1]: 48
3338 13:37:48.004832
3339 13:37:48.004931 Set Vref, RX VrefLevel [Byte0]: 49
3340 13:37:48.008468 [Byte1]: 49
3341 13:37:48.012731
3342 13:37:48.012869 Set Vref, RX VrefLevel [Byte0]: 50
3343 13:37:48.015903 [Byte1]: 50
3344 13:37:48.020987
3345 13:37:48.021131 Set Vref, RX VrefLevel [Byte0]: 51
3346 13:37:48.024197 [Byte1]: 51
3347 13:37:48.028529
3348 13:37:48.028611 Set Vref, RX VrefLevel [Byte0]: 52
3349 13:37:48.031660 [Byte1]: 52
3350 13:37:48.036615
3351 13:37:48.036709 Set Vref, RX VrefLevel [Byte0]: 53
3352 13:37:48.039725 [Byte1]: 53
3353 13:37:48.044573
3354 13:37:48.044672 Set Vref, RX VrefLevel [Byte0]: 54
3355 13:37:48.047622 [Byte1]: 54
3356 13:37:48.052159
3357 13:37:48.052286 Set Vref, RX VrefLevel [Byte0]: 55
3358 13:37:48.055366 [Byte1]: 55
3359 13:37:48.060510
3360 13:37:48.060629 Set Vref, RX VrefLevel [Byte0]: 56
3361 13:37:48.063589 [Byte1]: 56
3362 13:37:48.068156
3363 13:37:48.068267 Set Vref, RX VrefLevel [Byte0]: 57
3364 13:37:48.071390 [Byte1]: 57
3365 13:37:48.076437
3366 13:37:48.076548 Set Vref, RX VrefLevel [Byte0]: 58
3367 13:37:48.079683 [Byte1]: 58
3368 13:37:48.084080
3369 13:37:48.084176 Set Vref, RX VrefLevel [Byte0]: 59
3370 13:37:48.087369 [Byte1]: 59
3371 13:37:48.092174
3372 13:37:48.092274 Set Vref, RX VrefLevel [Byte0]: 60
3373 13:37:48.095380 [Byte1]: 60
3374 13:37:48.100058
3375 13:37:48.100163 Set Vref, RX VrefLevel [Byte0]: 61
3376 13:37:48.103038 [Byte1]: 61
3377 13:37:48.108030
3378 13:37:48.108133 Set Vref, RX VrefLevel [Byte0]: 62
3379 13:37:48.110952 [Byte1]: 62
3380 13:37:48.115660
3381 13:37:48.115756 Set Vref, RX VrefLevel [Byte0]: 63
3382 13:37:48.119002 [Byte1]: 63
3383 13:37:48.123493
3384 13:37:48.123592 Set Vref, RX VrefLevel [Byte0]: 64
3385 13:37:48.126708 [Byte1]: 64
3386 13:37:48.131327
3387 13:37:48.131450 Set Vref, RX VrefLevel [Byte0]: 65
3388 13:37:48.134877 [Byte1]: 65
3389 13:37:48.139778
3390 13:37:48.139880 Set Vref, RX VrefLevel [Byte0]: 66
3391 13:37:48.142520 [Byte1]: 66
3392 13:37:48.147166
3393 13:37:48.147288 Set Vref, RX VrefLevel [Byte0]: 67
3394 13:37:48.150992 [Byte1]: 67
3395 13:37:48.155414
3396 13:37:48.155561 Set Vref, RX VrefLevel [Byte0]: 68
3397 13:37:48.158471 [Byte1]: 68
3398 13:37:48.163065
3399 13:37:48.163179 Final RX Vref Byte 0 = 56 to rank0
3400 13:37:48.166819 Final RX Vref Byte 1 = 51 to rank0
3401 13:37:48.170050 Final RX Vref Byte 0 = 56 to rank1
3402 13:37:48.173205 Final RX Vref Byte 1 = 51 to rank1==
3403 13:37:48.177038 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 13:37:48.180114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 13:37:48.183298 ==
3406 13:37:48.183397 DQS Delay:
3407 13:37:48.183488 DQS0 = 0, DQS1 = 0
3408 13:37:48.187027 DQM Delay:
3409 13:37:48.187116 DQM0 = 115, DQM1 = 109
3410 13:37:48.190113 DQ Delay:
3411 13:37:48.193256 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3412 13:37:48.196869 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3413 13:37:48.199998 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =104
3414 13:37:48.203166 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3415 13:37:48.203283
3416 13:37:48.203348
3417 13:37:48.209810 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3418 13:37:48.213400 CH1 RK0: MR19=403, MR18=E5
3419 13:37:48.220279 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3420 13:37:48.220400
3421 13:37:48.223804 ----->DramcWriteLeveling(PI) begin...
3422 13:37:48.223899 ==
3423 13:37:48.226798 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 13:37:48.230416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 13:37:48.230521 ==
3426 13:37:48.233567 Write leveling (Byte 0): 25 => 25
3427 13:37:48.236954 Write leveling (Byte 1): 26 => 26
3428 13:37:48.240611 DramcWriteLeveling(PI) end<-----
3429 13:37:48.240708
3430 13:37:48.240772 ==
3431 13:37:48.243402 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 13:37:48.246956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 13:37:48.247057 ==
3434 13:37:48.250141 [Gating] SW mode calibration
3435 13:37:48.257475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 13:37:48.264108 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 13:37:48.267103 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3438 13:37:48.270303 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 13:37:48.277259 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 13:37:48.280259 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 13:37:48.284248 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 13:37:48.290323 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 13:37:48.294132 0 15 24 | B1->B0 | 3333 2a2a | 1 1 | (1 1) (1 0)
3444 13:37:48.297265 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 13:37:48.303835 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 13:37:48.307649 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 13:37:48.310902 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 13:37:48.317085 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 13:37:48.320732 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 13:37:48.324355 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 13:37:48.327426 1 0 24 | B1->B0 | 2929 4343 | 0 0 | (0 0) (0 0)
3452 13:37:48.334560 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3453 13:37:48.337465 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 13:37:48.341256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 13:37:48.347745 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 13:37:48.350891 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 13:37:48.354209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 13:37:48.360954 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3459 13:37:48.364462 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3460 13:37:48.367844 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3461 13:37:48.374807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 13:37:48.377804 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:37:48.381002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 13:37:48.385195 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 13:37:48.390923 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:37:48.394727 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 13:37:48.397884 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 13:37:48.404165 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 13:37:48.407294 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 13:37:48.410908 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 13:37:48.417888 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 13:37:48.420916 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 13:37:48.424464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 13:37:48.430855 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 13:37:48.433897 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 13:37:48.437556 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3477 13:37:48.440706 Total UI for P1: 0, mck2ui 16
3478 13:37:48.444237 best dqsien dly found for B0: ( 1, 3, 24)
3479 13:37:48.450615 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 13:37:48.450734 Total UI for P1: 0, mck2ui 16
3481 13:37:48.457680 best dqsien dly found for B1: ( 1, 3, 26)
3482 13:37:48.460750 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3483 13:37:48.464621 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3484 13:37:48.464727
3485 13:37:48.467734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3486 13:37:48.470774 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 13:37:48.474359 [Gating] SW calibration Done
3488 13:37:48.474473 ==
3489 13:37:48.477747 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 13:37:48.481123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 13:37:48.481218 ==
3492 13:37:48.484513 RX Vref Scan: 0
3493 13:37:48.484603
3494 13:37:48.484668 RX Vref 0 -> 0, step: 1
3495 13:37:48.484727
3496 13:37:48.487390 RX Delay -40 -> 252, step: 8
3497 13:37:48.491205 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3498 13:37:48.497704 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3499 13:37:48.500893 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3500 13:37:48.504118 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3501 13:37:48.507638 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3502 13:37:48.510981 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3503 13:37:48.517883 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3504 13:37:48.520871 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3505 13:37:48.524261 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3506 13:37:48.527518 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3507 13:37:48.531160 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3508 13:37:48.534345 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3509 13:37:48.540969 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3510 13:37:48.544243 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3511 13:37:48.547674 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3512 13:37:48.551205 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3513 13:37:48.551320 ==
3514 13:37:48.554522 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 13:37:48.561275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 13:37:48.561399 ==
3517 13:37:48.561465 DQS Delay:
3518 13:37:48.564406 DQS0 = 0, DQS1 = 0
3519 13:37:48.564491 DQM Delay:
3520 13:37:48.564555 DQM0 = 113, DQM1 = 108
3521 13:37:48.567572 DQ Delay:
3522 13:37:48.570864 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3523 13:37:48.574583 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3524 13:37:48.577660 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99
3525 13:37:48.581396 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3526 13:37:48.581496
3527 13:37:48.581560
3528 13:37:48.581619 ==
3529 13:37:48.584505 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 13:37:48.588174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 13:37:48.588272 ==
3532 13:37:48.588338
3533 13:37:48.591653
3534 13:37:48.591739 TX Vref Scan disable
3535 13:37:48.594501 == TX Byte 0 ==
3536 13:37:48.597568 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3537 13:37:48.601400 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3538 13:37:48.604640 == TX Byte 1 ==
3539 13:37:48.607825 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3540 13:37:48.611441 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3541 13:37:48.611541 ==
3542 13:37:48.614578 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 13:37:48.621436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 13:37:48.621571 ==
3545 13:37:48.631463 TX Vref=22, minBit 0, minWin=25, winSum=412
3546 13:37:48.634671 TX Vref=24, minBit 0, minWin=25, winSum=417
3547 13:37:48.637924 TX Vref=26, minBit 1, minWin=25, winSum=422
3548 13:37:48.641597 TX Vref=28, minBit 0, minWin=26, winSum=430
3549 13:37:48.644590 TX Vref=30, minBit 9, minWin=26, winSum=433
3550 13:37:48.648204 TX Vref=32, minBit 1, minWin=26, winSum=427
3551 13:37:48.654701 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3552 13:37:48.654829
3553 13:37:48.657804 Final TX Range 1 Vref 30
3554 13:37:48.657958
3555 13:37:48.658056 ==
3556 13:37:48.660988 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 13:37:48.664774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 13:37:48.664871 ==
3559 13:37:48.665002
3560 13:37:48.668217
3561 13:37:48.668315 TX Vref Scan disable
3562 13:37:48.671232 == TX Byte 0 ==
3563 13:37:48.674328 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3564 13:37:48.678278 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3565 13:37:48.681226 == TX Byte 1 ==
3566 13:37:48.684427 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 13:37:48.688356 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 13:37:48.688473
3569 13:37:48.691254 [DATLAT]
3570 13:37:48.691360 Freq=1200, CH1 RK1
3571 13:37:48.691449
3572 13:37:48.694360 DATLAT Default: 0xd
3573 13:37:48.694450 0, 0xFFFF, sum = 0
3574 13:37:48.698159 1, 0xFFFF, sum = 0
3575 13:37:48.698259 2, 0xFFFF, sum = 0
3576 13:37:48.701149 3, 0xFFFF, sum = 0
3577 13:37:48.701258 4, 0xFFFF, sum = 0
3578 13:37:48.704835 5, 0xFFFF, sum = 0
3579 13:37:48.704967 6, 0xFFFF, sum = 0
3580 13:37:48.707950 7, 0xFFFF, sum = 0
3581 13:37:48.711191 8, 0xFFFF, sum = 0
3582 13:37:48.711310 9, 0xFFFF, sum = 0
3583 13:37:48.714700 10, 0xFFFF, sum = 0
3584 13:37:48.714793 11, 0xFFFF, sum = 0
3585 13:37:48.718315 12, 0x0, sum = 1
3586 13:37:48.718409 13, 0x0, sum = 2
3587 13:37:48.718475 14, 0x0, sum = 3
3588 13:37:48.721584 15, 0x0, sum = 4
3589 13:37:48.721689 best_step = 13
3590 13:37:48.721786
3591 13:37:48.724698 ==
3592 13:37:48.724786 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 13:37:48.731094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 13:37:48.731209 ==
3595 13:37:48.731310 RX Vref Scan: 0
3596 13:37:48.731403
3597 13:37:48.734885 RX Vref 0 -> 0, step: 1
3598 13:37:48.734970
3599 13:37:48.738033 RX Delay -21 -> 252, step: 4
3600 13:37:48.741272 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3601 13:37:48.747627 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3602 13:37:48.751545 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3603 13:37:48.754412 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3604 13:37:48.757659 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3605 13:37:48.760869 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3606 13:37:48.764836 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3607 13:37:48.771037 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3608 13:37:48.774641 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3609 13:37:48.777998 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3610 13:37:48.780734 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3611 13:37:48.784223 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3612 13:37:48.791184 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3613 13:37:48.794247 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3614 13:37:48.797871 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3615 13:37:48.800932 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3616 13:37:48.801051 ==
3617 13:37:48.804762 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 13:37:48.811184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 13:37:48.811308 ==
3620 13:37:48.811404 DQS Delay:
3621 13:37:48.811487 DQS0 = 0, DQS1 = 0
3622 13:37:48.814398 DQM Delay:
3623 13:37:48.814489 DQM0 = 113, DQM1 = 109
3624 13:37:48.818141 DQ Delay:
3625 13:37:48.821350 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3626 13:37:48.825171 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3627 13:37:48.828174 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3628 13:37:48.831420 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3629 13:37:48.831526
3630 13:37:48.831617
3631 13:37:48.837893 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3632 13:37:48.841691 CH1 RK1: MR19=303, MR18=F8FF
3633 13:37:48.847947 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3634 13:37:48.851139 [RxdqsGatingPostProcess] freq 1200
3635 13:37:48.857769 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 13:37:48.861549 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 13:37:48.861661 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 13:37:48.864576 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 13:37:48.867804 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 13:37:48.871637 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 13:37:48.874787 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 13:37:48.878002 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 13:37:48.881751 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 13:37:48.884863 Pre-setting of DQS Precalculation
3645 13:37:48.891666 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 13:37:48.898266 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 13:37:48.905150 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 13:37:48.905282
3649 13:37:48.905381
3650 13:37:48.908374 [Calibration Summary] 2400 Mbps
3651 13:37:48.908463 CH 0, Rank 0
3652 13:37:48.911368 SW Impedance : PASS
3653 13:37:48.915102 DUTY Scan : NO K
3654 13:37:48.915237 ZQ Calibration : PASS
3655 13:37:48.918045 Jitter Meter : NO K
3656 13:37:48.918138 CBT Training : PASS
3657 13:37:48.921948 Write leveling : PASS
3658 13:37:48.924968 RX DQS gating : PASS
3659 13:37:48.925091 RX DQ/DQS(RDDQC) : PASS
3660 13:37:48.928104 TX DQ/DQS : PASS
3661 13:37:48.931829 RX DATLAT : PASS
3662 13:37:48.931951 RX DQ/DQS(Engine): PASS
3663 13:37:48.934811 TX OE : NO K
3664 13:37:48.934903 All Pass.
3665 13:37:48.934989
3666 13:37:48.938224 CH 0, Rank 1
3667 13:37:48.938320 SW Impedance : PASS
3668 13:37:48.941859 DUTY Scan : NO K
3669 13:37:48.944970 ZQ Calibration : PASS
3670 13:37:48.945095 Jitter Meter : NO K
3671 13:37:48.948164 CBT Training : PASS
3672 13:37:48.948278 Write leveling : PASS
3673 13:37:48.951368 RX DQS gating : PASS
3674 13:37:48.955128 RX DQ/DQS(RDDQC) : PASS
3675 13:37:48.955219 TX DQ/DQS : PASS
3676 13:37:48.958300 RX DATLAT : PASS
3677 13:37:48.962095 RX DQ/DQS(Engine): PASS
3678 13:37:48.962195 TX OE : NO K
3679 13:37:48.965189 All Pass.
3680 13:37:48.965271
3681 13:37:48.965335 CH 1, Rank 0
3682 13:37:48.968385 SW Impedance : PASS
3683 13:37:48.968460 DUTY Scan : NO K
3684 13:37:48.971591 ZQ Calibration : PASS
3685 13:37:48.974797 Jitter Meter : NO K
3686 13:37:48.974877 CBT Training : PASS
3687 13:37:48.978443 Write leveling : PASS
3688 13:37:48.981690 RX DQS gating : PASS
3689 13:37:48.981772 RX DQ/DQS(RDDQC) : PASS
3690 13:37:48.984911 TX DQ/DQS : PASS
3691 13:37:48.988623 RX DATLAT : PASS
3692 13:37:48.988708 RX DQ/DQS(Engine): PASS
3693 13:37:48.991493 TX OE : NO K
3694 13:37:48.991578 All Pass.
3695 13:37:48.991640
3696 13:37:48.995052 CH 1, Rank 1
3697 13:37:48.995136 SW Impedance : PASS
3698 13:37:48.998228 DUTY Scan : NO K
3699 13:37:48.998304 ZQ Calibration : PASS
3700 13:37:49.001989 Jitter Meter : NO K
3701 13:37:49.005155 CBT Training : PASS
3702 13:37:49.005256 Write leveling : PASS
3703 13:37:49.008205 RX DQS gating : PASS
3704 13:37:49.011571 RX DQ/DQS(RDDQC) : PASS
3705 13:37:49.011656 TX DQ/DQS : PASS
3706 13:37:49.015144 RX DATLAT : PASS
3707 13:37:49.018576 RX DQ/DQS(Engine): PASS
3708 13:37:49.018675 TX OE : NO K
3709 13:37:49.021452 All Pass.
3710 13:37:49.021547
3711 13:37:49.021624 DramC Write-DBI off
3712 13:37:49.025139 PER_BANK_REFRESH: Hybrid Mode
3713 13:37:49.025217 TX_TRACKING: ON
3714 13:37:49.034961 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 13:37:49.038681 [FAST_K] Save calibration result to emmc
3716 13:37:49.041936 dramc_set_vcore_voltage set vcore to 650000
3717 13:37:49.045006 Read voltage for 600, 5
3718 13:37:49.045105 Vio18 = 0
3719 13:37:49.048169 Vcore = 650000
3720 13:37:49.048246 Vdram = 0
3721 13:37:49.048306 Vddq = 0
3722 13:37:49.048364 Vmddr = 0
3723 13:37:49.055149 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 13:37:49.061713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 13:37:49.061833 MEM_TYPE=3, freq_sel=19
3726 13:37:49.065187 sv_algorithm_assistance_LP4_1600
3727 13:37:49.068619 ============ PULL DRAM RESETB DOWN ============
3728 13:37:49.075022 ========== PULL DRAM RESETB DOWN end =========
3729 13:37:49.078192 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 13:37:49.081941 ===================================
3731 13:37:49.084789 LPDDR4 DRAM CONFIGURATION
3732 13:37:49.088599 ===================================
3733 13:37:49.088693 EX_ROW_EN[0] = 0x0
3734 13:37:49.092147 EX_ROW_EN[1] = 0x0
3735 13:37:49.092246 LP4Y_EN = 0x0
3736 13:37:49.095285 WORK_FSP = 0x0
3737 13:37:49.095370 WL = 0x2
3738 13:37:49.098378 RL = 0x2
3739 13:37:49.098458 BL = 0x2
3740 13:37:49.101953 RPST = 0x0
3741 13:37:49.102040 RD_PRE = 0x0
3742 13:37:49.105195 WR_PRE = 0x1
3743 13:37:49.105277 WR_PST = 0x0
3744 13:37:49.108865 DBI_WR = 0x0
3745 13:37:49.108958 DBI_RD = 0x0
3746 13:37:49.112112 OTF = 0x1
3747 13:37:49.115364 ===================================
3748 13:37:49.118366 ===================================
3749 13:37:49.118461 ANA top config
3750 13:37:49.121970 ===================================
3751 13:37:49.125275 DLL_ASYNC_EN = 0
3752 13:37:49.128667 ALL_SLAVE_EN = 1
3753 13:37:49.132313 NEW_RANK_MODE = 1
3754 13:37:49.132492 DLL_IDLE_MODE = 1
3755 13:37:49.135305 LP45_APHY_COMB_EN = 1
3756 13:37:49.138832 TX_ODT_DIS = 1
3757 13:37:49.141829 NEW_8X_MODE = 1
3758 13:37:49.145205 ===================================
3759 13:37:49.149138 ===================================
3760 13:37:49.152242 data_rate = 1200
3761 13:37:49.152340 CKR = 1
3762 13:37:49.155749 DQ_P2S_RATIO = 8
3763 13:37:49.159022 ===================================
3764 13:37:49.162217 CA_P2S_RATIO = 8
3765 13:37:49.166175 DQ_CA_OPEN = 0
3766 13:37:49.169236 DQ_SEMI_OPEN = 0
3767 13:37:49.169356 CA_SEMI_OPEN = 0
3768 13:37:49.172277 CA_FULL_RATE = 0
3769 13:37:49.176077 DQ_CKDIV4_EN = 1
3770 13:37:49.179190 CA_CKDIV4_EN = 1
3771 13:37:49.182424 CA_PREDIV_EN = 0
3772 13:37:49.185763 PH8_DLY = 0
3773 13:37:49.185860 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 13:37:49.189464 DQ_AAMCK_DIV = 4
3775 13:37:49.192672 CA_AAMCK_DIV = 4
3776 13:37:49.195798 CA_ADMCK_DIV = 4
3777 13:37:49.199002 DQ_TRACK_CA_EN = 0
3778 13:37:49.202090 CA_PICK = 600
3779 13:37:49.205673 CA_MCKIO = 600
3780 13:37:49.205763 MCKIO_SEMI = 0
3781 13:37:49.209236 PLL_FREQ = 2288
3782 13:37:49.212287 DQ_UI_PI_RATIO = 32
3783 13:37:49.215821 CA_UI_PI_RATIO = 0
3784 13:37:49.219054 ===================================
3785 13:37:49.222704 ===================================
3786 13:37:49.225954 memory_type:LPDDR4
3787 13:37:49.226061 GP_NUM : 10
3788 13:37:49.228986 SRAM_EN : 1
3789 13:37:49.229104 MD32_EN : 0
3790 13:37:49.232272 ===================================
3791 13:37:49.235855 [ANA_INIT] >>>>>>>>>>>>>>
3792 13:37:49.239374 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 13:37:49.242224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 13:37:49.245542 ===================================
3795 13:37:49.249489 data_rate = 1200,PCW = 0X5800
3796 13:37:49.252634 ===================================
3797 13:37:49.255535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 13:37:49.262728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 13:37:49.265919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 13:37:49.272202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 13:37:49.275565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 13:37:49.279195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 13:37:49.279326 [ANA_INIT] flow start
3804 13:37:49.282379 [ANA_INIT] PLL >>>>>>>>
3805 13:37:49.286368 [ANA_INIT] PLL <<<<<<<<
3806 13:37:49.286469 [ANA_INIT] MIDPI >>>>>>>>
3807 13:37:49.289552 [ANA_INIT] MIDPI <<<<<<<<
3808 13:37:49.292726 [ANA_INIT] DLL >>>>>>>>
3809 13:37:49.292849 [ANA_INIT] flow end
3810 13:37:49.299042 ============ LP4 DIFF to SE enter ============
3811 13:37:49.302794 ============ LP4 DIFF to SE exit ============
3812 13:37:49.302900 [ANA_INIT] <<<<<<<<<<<<<
3813 13:37:49.305907 [Flow] Enable top DCM control >>>>>
3814 13:37:49.309165 [Flow] Enable top DCM control <<<<<
3815 13:37:49.312306 Enable DLL master slave shuffle
3816 13:37:49.318947 ==============================================================
3817 13:37:49.319066 Gating Mode config
3818 13:37:49.325662 ==============================================================
3819 13:37:49.329454 Config description:
3820 13:37:49.338921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 13:37:49.345772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 13:37:49.349515 SELPH_MODE 0: By rank 1: By Phase
3823 13:37:49.356136 ==============================================================
3824 13:37:49.359222 GAT_TRACK_EN = 1
3825 13:37:49.359334 RX_GATING_MODE = 2
3826 13:37:49.362397 RX_GATING_TRACK_MODE = 2
3827 13:37:49.366349 SELPH_MODE = 1
3828 13:37:49.369481 PICG_EARLY_EN = 1
3829 13:37:49.373098 VALID_LAT_VALUE = 1
3830 13:37:49.379580 ==============================================================
3831 13:37:49.383003 Enter into Gating configuration >>>>
3832 13:37:49.386251 Exit from Gating configuration <<<<
3833 13:37:49.389322 Enter into DVFS_PRE_config >>>>>
3834 13:37:49.399388 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 13:37:49.403305 Exit from DVFS_PRE_config <<<<<
3836 13:37:49.405880 Enter into PICG configuration >>>>
3837 13:37:49.409504 Exit from PICG configuration <<<<
3838 13:37:49.412772 [RX_INPUT] configuration >>>>>
3839 13:37:49.412868 [RX_INPUT] configuration <<<<<
3840 13:37:49.419683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 13:37:49.426335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 13:37:49.429709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 13:37:49.436449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 13:37:49.442916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 13:37:49.449501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 13:37:49.453239 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 13:37:49.456272 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 13:37:49.462708 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 13:37:49.466098 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 13:37:49.469595 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 13:37:49.473395 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 13:37:49.476611 ===================================
3853 13:37:49.479528 LPDDR4 DRAM CONFIGURATION
3854 13:37:49.482843 ===================================
3855 13:37:49.486045 EX_ROW_EN[0] = 0x0
3856 13:37:49.486165 EX_ROW_EN[1] = 0x0
3857 13:37:49.489446 LP4Y_EN = 0x0
3858 13:37:49.489549 WORK_FSP = 0x0
3859 13:37:49.492767 WL = 0x2
3860 13:37:49.492857 RL = 0x2
3861 13:37:49.496542 BL = 0x2
3862 13:37:49.496636 RPST = 0x0
3863 13:37:49.499993 RD_PRE = 0x0
3864 13:37:49.500092 WR_PRE = 0x1
3865 13:37:49.503125 WR_PST = 0x0
3866 13:37:49.503246 DBI_WR = 0x0
3867 13:37:49.506084 DBI_RD = 0x0
3868 13:37:49.506194 OTF = 0x1
3869 13:37:49.509784 ===================================
3870 13:37:49.516073 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 13:37:49.519749 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 13:37:49.523063 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 13:37:49.526108 ===================================
3874 13:37:49.529795 LPDDR4 DRAM CONFIGURATION
3875 13:37:49.532981 ===================================
3876 13:37:49.536186 EX_ROW_EN[0] = 0x10
3877 13:37:49.536287 EX_ROW_EN[1] = 0x0
3878 13:37:49.539489 LP4Y_EN = 0x0
3879 13:37:49.539584 WORK_FSP = 0x0
3880 13:37:49.542830 WL = 0x2
3881 13:37:49.542957 RL = 0x2
3882 13:37:49.546681 BL = 0x2
3883 13:37:49.546775 RPST = 0x0
3884 13:37:49.549572 RD_PRE = 0x0
3885 13:37:49.549666 WR_PRE = 0x1
3886 13:37:49.553323 WR_PST = 0x0
3887 13:37:49.553421 DBI_WR = 0x0
3888 13:37:49.556421 DBI_RD = 0x0
3889 13:37:49.556526 OTF = 0x1
3890 13:37:49.559533 ===================================
3891 13:37:49.566695 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 13:37:49.571058 nWR fixed to 30
3893 13:37:49.574335 [ModeRegInit_LP4] CH0 RK0
3894 13:37:49.574435 [ModeRegInit_LP4] CH0 RK1
3895 13:37:49.577447 [ModeRegInit_LP4] CH1 RK0
3896 13:37:49.581137 [ModeRegInit_LP4] CH1 RK1
3897 13:37:49.581237 match AC timing 17
3898 13:37:49.587560 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 13:37:49.591014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 13:37:49.594149 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 13:37:49.600648 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 13:37:49.604049 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 13:37:49.604175 ==
3904 13:37:49.607272 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 13:37:49.611005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 13:37:49.611098 ==
3907 13:37:49.617741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 13:37:49.624179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3909 13:37:49.627888 [CA 0] Center 36 (6~66) winsize 61
3910 13:37:49.630988 [CA 1] Center 36 (6~66) winsize 61
3911 13:37:49.634214 [CA 2] Center 34 (4~65) winsize 62
3912 13:37:49.638111 [CA 3] Center 34 (4~65) winsize 62
3913 13:37:49.641422 [CA 4] Center 34 (4~64) winsize 61
3914 13:37:49.644293 [CA 5] Center 33 (3~64) winsize 62
3915 13:37:49.644384
3916 13:37:49.647833 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3917 13:37:49.647920
3918 13:37:49.650797 [CATrainingPosCal] consider 1 rank data
3919 13:37:49.654213 u2DelayCellTimex100 = 270/100 ps
3920 13:37:49.657836 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3921 13:37:49.661267 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3922 13:37:49.664367 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 13:37:49.668082 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3924 13:37:49.671287 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3925 13:37:49.674419 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3926 13:37:49.674513
3927 13:37:49.677618 CA PerBit enable=1, Macro0, CA PI delay=33
3928 13:37:49.677704
3929 13:37:49.681492 [CBTSetCACLKResult] CA Dly = 33
3930 13:37:49.684649 CS Dly: 4 (0~35)
3931 13:37:49.684754 ==
3932 13:37:49.687725 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 13:37:49.691385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 13:37:49.691479 ==
3935 13:37:49.698130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 13:37:49.704446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 13:37:49.707661 [CA 0] Center 36 (6~66) winsize 61
3938 13:37:49.711217 [CA 1] Center 36 (6~66) winsize 61
3939 13:37:49.714734 [CA 2] Center 34 (4~65) winsize 62
3940 13:37:49.717950 [CA 3] Center 34 (4~65) winsize 62
3941 13:37:49.721565 [CA 4] Center 33 (3~64) winsize 62
3942 13:37:49.724587 [CA 5] Center 33 (3~64) winsize 62
3943 13:37:49.724698
3944 13:37:49.728341 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 13:37:49.728448
3946 13:37:49.731529 [CATrainingPosCal] consider 2 rank data
3947 13:37:49.734769 u2DelayCellTimex100 = 270/100 ps
3948 13:37:49.738437 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 13:37:49.741605 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3950 13:37:49.744990 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 13:37:49.748010 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 13:37:49.751343 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3953 13:37:49.755032 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 13:37:49.755151
3955 13:37:49.758011 CA PerBit enable=1, Macro0, CA PI delay=33
3956 13:37:49.758145
3957 13:37:49.761709 [CBTSetCACLKResult] CA Dly = 33
3958 13:37:49.764629 CS Dly: 4 (0~36)
3959 13:37:49.764748
3960 13:37:49.768499 ----->DramcWriteLeveling(PI) begin...
3961 13:37:49.768592 ==
3962 13:37:49.771680 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 13:37:49.775114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 13:37:49.775307 ==
3965 13:37:49.778134 Write leveling (Byte 0): 31 => 31
3966 13:37:49.781658 Write leveling (Byte 1): 31 => 31
3967 13:37:49.784903 DramcWriteLeveling(PI) end<-----
3968 13:37:49.785078
3969 13:37:49.785151 ==
3970 13:37:49.788180 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 13:37:49.791363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 13:37:49.791461 ==
3973 13:37:49.795035 [Gating] SW mode calibration
3974 13:37:49.801392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 13:37:49.807955 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 13:37:49.811603 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 13:37:49.814704 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 13:37:49.821328 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 13:37:49.824716 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 13:37:49.828048 0 9 16 | B1->B0 | 2f2f 2c2c | 0 0 | (0 1) (1 0)
3981 13:37:49.834846 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 13:37:49.837951 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 13:37:49.841742 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 13:37:49.848068 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 13:37:49.851264 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 13:37:49.854505 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 13:37:49.861537 0 10 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
3988 13:37:49.864750 0 10 16 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
3989 13:37:49.868068 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 13:37:49.874920 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 13:37:49.878219 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 13:37:49.881020 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 13:37:49.888000 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 13:37:49.891601 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 13:37:49.894653 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3996 13:37:49.900991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 13:37:49.904822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:37:49.908024 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:37:49.911120 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:37:49.917809 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:37:49.921418 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:37:49.924492 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:37:49.931328 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:37:49.934765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:37:49.937861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:37:49.944785 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:37:49.948014 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:37:49.951327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:37:49.958263 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 13:37:49.961330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 13:37:49.964370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4012 13:37:49.970944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:37:49.971066 Total UI for P1: 0, mck2ui 16
4014 13:37:49.977958 best dqsien dly found for B0: ( 0, 13, 12)
4015 13:37:49.978075 Total UI for P1: 0, mck2ui 16
4016 13:37:49.984812 best dqsien dly found for B1: ( 0, 13, 14)
4017 13:37:49.987770 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4018 13:37:49.991557 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4019 13:37:49.991661
4020 13:37:49.994494 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4021 13:37:49.998122 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4022 13:37:50.001693 [Gating] SW calibration Done
4023 13:37:50.001799 ==
4024 13:37:50.004630 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 13:37:50.007822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 13:37:50.007948 ==
4027 13:37:50.011640 RX Vref Scan: 0
4028 13:37:50.011734
4029 13:37:50.011801 RX Vref 0 -> 0, step: 1
4030 13:37:50.011862
4031 13:37:50.014818 RX Delay -230 -> 252, step: 16
4032 13:37:50.017949 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4033 13:37:50.024584 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4034 13:37:50.028276 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 13:37:50.031333 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 13:37:50.034601 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4037 13:37:50.041517 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4038 13:37:50.044625 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4039 13:37:50.048240 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4040 13:37:50.051804 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4041 13:37:50.054878 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4042 13:37:50.061303 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4043 13:37:50.064887 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4044 13:37:50.067922 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4045 13:37:50.071060 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4046 13:37:50.078095 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4047 13:37:50.081330 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4048 13:37:50.081428 ==
4049 13:37:50.084873 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 13:37:50.087984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 13:37:50.088077 ==
4052 13:37:50.091022 DQS Delay:
4053 13:37:50.091107 DQS0 = 0, DQS1 = 0
4054 13:37:50.091180 DQM Delay:
4055 13:37:50.094771 DQM0 = 42, DQM1 = 33
4056 13:37:50.094853 DQ Delay:
4057 13:37:50.097786 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4058 13:37:50.101588 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4059 13:37:50.104449 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4060 13:37:50.108107 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4061 13:37:50.108203
4062 13:37:50.108292
4063 13:37:50.108397 ==
4064 13:37:50.111693 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 13:37:50.118013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 13:37:50.118133 ==
4067 13:37:50.118220
4068 13:37:50.118281
4069 13:37:50.118338 TX Vref Scan disable
4070 13:37:50.121138 == TX Byte 0 ==
4071 13:37:50.124814 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4072 13:37:50.128409 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4073 13:37:50.131474 == TX Byte 1 ==
4074 13:37:50.134972 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 13:37:50.138382 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 13:37:50.141439 ==
4077 13:37:50.144577 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 13:37:50.148394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 13:37:50.148532 ==
4080 13:37:50.148638
4081 13:37:50.148728
4082 13:37:50.151624 TX Vref Scan disable
4083 13:37:50.151701 == TX Byte 0 ==
4084 13:37:50.158193 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4085 13:37:50.161974 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4086 13:37:50.162100 == TX Byte 1 ==
4087 13:37:50.168253 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 13:37:50.171326 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 13:37:50.171423
4090 13:37:50.171489 [DATLAT]
4091 13:37:50.175087 Freq=600, CH0 RK0
4092 13:37:50.175183
4093 13:37:50.175295 DATLAT Default: 0x9
4094 13:37:50.178173 0, 0xFFFF, sum = 0
4095 13:37:50.178266 1, 0xFFFF, sum = 0
4096 13:37:50.181357 2, 0xFFFF, sum = 0
4097 13:37:50.181438 3, 0xFFFF, sum = 0
4098 13:37:50.184478 4, 0xFFFF, sum = 0
4099 13:37:50.184553 5, 0xFFFF, sum = 0
4100 13:37:50.188213 6, 0xFFFF, sum = 0
4101 13:37:50.188315 7, 0xFFFF, sum = 0
4102 13:37:50.191251 8, 0x0, sum = 1
4103 13:37:50.191328 9, 0x0, sum = 2
4104 13:37:50.194992 10, 0x0, sum = 3
4105 13:37:50.195072 11, 0x0, sum = 4
4106 13:37:50.198090 best_step = 9
4107 13:37:50.198163
4108 13:37:50.198222 ==
4109 13:37:50.201925 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 13:37:50.204829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 13:37:50.204958 ==
4112 13:37:50.208021 RX Vref Scan: 1
4113 13:37:50.208104
4114 13:37:50.208168 RX Vref 0 -> 0, step: 1
4115 13:37:50.208227
4116 13:37:50.211885 RX Delay -195 -> 252, step: 8
4117 13:37:50.211981
4118 13:37:50.214980 Set Vref, RX VrefLevel [Byte0]: 54
4119 13:37:50.218048 [Byte1]: 53
4120 13:37:50.221752
4121 13:37:50.221844 Final RX Vref Byte 0 = 54 to rank0
4122 13:37:50.225228 Final RX Vref Byte 1 = 53 to rank0
4123 13:37:50.229289 Final RX Vref Byte 0 = 54 to rank1
4124 13:37:50.231673 Final RX Vref Byte 1 = 53 to rank1==
4125 13:37:50.235079 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 13:37:50.238747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 13:37:50.242071 ==
4128 13:37:50.242155 DQS Delay:
4129 13:37:50.242217 DQS0 = 0, DQS1 = 0
4130 13:37:50.245261 DQM Delay:
4131 13:37:50.245335 DQM0 = 42, DQM1 = 34
4132 13:37:50.248380 DQ Delay:
4133 13:37:50.251584 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4134 13:37:50.251660 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4135 13:37:50.255481 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4136 13:37:50.258748 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4137 13:37:50.261736
4138 13:37:50.261816
4139 13:37:50.268363 [DQSOSCAuto] RK0, (LSB)MR18= 0x4624, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4140 13:37:50.272118 CH0 RK0: MR19=808, MR18=4624
4141 13:37:50.278824 CH0_RK0: MR19=0x808, MR18=0x4624, DQSOSC=396, MR23=63, INC=167, DEC=111
4142 13:37:50.278934
4143 13:37:50.281937 ----->DramcWriteLeveling(PI) begin...
4144 13:37:50.282039 ==
4145 13:37:50.285340 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 13:37:50.288535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 13:37:50.288646 ==
4148 13:37:50.291638 Write leveling (Byte 0): 31 => 31
4149 13:37:50.295512 Write leveling (Byte 1): 28 => 28
4150 13:37:50.298458 DramcWriteLeveling(PI) end<-----
4151 13:37:50.298539
4152 13:37:50.298602 ==
4153 13:37:50.302199 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 13:37:50.305436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 13:37:50.305538 ==
4156 13:37:50.308323 [Gating] SW mode calibration
4157 13:37:50.315387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 13:37:50.321723 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 13:37:50.324806 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 13:37:50.328479 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 13:37:50.335099 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4162 13:37:50.338165 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4163 13:37:50.341638 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
4164 13:37:50.348480 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 13:37:50.351688 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 13:37:50.354702 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 13:37:50.361301 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 13:37:50.364940 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 13:37:50.367966 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 13:37:50.374637 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
4171 13:37:50.378409 0 10 16 | B1->B0 | 3838 4545 | 0 0 | (1 1) (0 0)
4172 13:37:50.381483 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 13:37:50.387918 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 13:37:50.391594 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 13:37:50.394750 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 13:37:50.401443 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 13:37:50.404402 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 13:37:50.408286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4179 13:37:50.414394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4180 13:37:50.418330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 13:37:50.421349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:37:50.427799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:37:50.431651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 13:37:50.434844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:37:50.438522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:37:50.444744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:37:50.448141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 13:37:50.451466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:37:50.458234 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 13:37:50.461449 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 13:37:50.464466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 13:37:50.471452 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 13:37:50.474463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 13:37:50.478072 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4195 13:37:50.484837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4196 13:37:50.484955 Total UI for P1: 0, mck2ui 16
4197 13:37:50.491701 best dqsien dly found for B0: ( 0, 13, 12)
4198 13:37:50.494897 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 13:37:50.498010 Total UI for P1: 0, mck2ui 16
4200 13:37:50.501590 best dqsien dly found for B1: ( 0, 13, 16)
4201 13:37:50.504795 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4202 13:37:50.507818 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4203 13:37:50.507902
4204 13:37:50.511441 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 13:37:50.514958 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4206 13:37:50.517997 [Gating] SW calibration Done
4207 13:37:50.518081 ==
4208 13:37:50.521121 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 13:37:50.524893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 13:37:50.528267 ==
4211 13:37:50.528343 RX Vref Scan: 0
4212 13:37:50.528404
4213 13:37:50.531299 RX Vref 0 -> 0, step: 1
4214 13:37:50.531371
4215 13:37:50.534532 RX Delay -230 -> 252, step: 16
4216 13:37:50.538350 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4217 13:37:50.541466 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4218 13:37:50.544631 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4219 13:37:50.547907 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4220 13:37:50.554737 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4221 13:37:50.557860 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4222 13:37:50.561716 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4223 13:37:50.564387 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4224 13:37:50.571156 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4225 13:37:50.574613 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4226 13:37:50.578283 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4227 13:37:50.581396 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4228 13:37:50.584638 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4229 13:37:50.591128 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4230 13:37:50.594742 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4231 13:37:50.597812 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4232 13:37:50.597912 ==
4233 13:37:50.601183 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 13:37:50.607890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 13:37:50.608002 ==
4236 13:37:50.608115 DQS Delay:
4237 13:37:50.608227 DQS0 = 0, DQS1 = 0
4238 13:37:50.611555 DQM Delay:
4239 13:37:50.611639 DQM0 = 42, DQM1 = 31
4240 13:37:50.614523 DQ Delay:
4241 13:37:50.617676 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4242 13:37:50.617784 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =57
4243 13:37:50.621447 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4244 13:37:50.624368 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4245 13:37:50.628127
4246 13:37:50.628209
4247 13:37:50.628272 ==
4248 13:37:50.631363 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 13:37:50.634597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 13:37:50.634704 ==
4251 13:37:50.634795
4252 13:37:50.634923
4253 13:37:50.637652 TX Vref Scan disable
4254 13:37:50.637735 == TX Byte 0 ==
4255 13:37:50.644666 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4256 13:37:50.647954 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4257 13:37:50.648089 == TX Byte 1 ==
4258 13:37:50.654676 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4259 13:37:50.657769 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4260 13:37:50.657874 ==
4261 13:37:50.661568 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 13:37:50.664667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 13:37:50.664774 ==
4264 13:37:50.664864
4265 13:37:50.664950
4266 13:37:50.667782 TX Vref Scan disable
4267 13:37:50.671536 == TX Byte 0 ==
4268 13:37:50.674666 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4269 13:37:50.678166 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4270 13:37:50.681037 == TX Byte 1 ==
4271 13:37:50.684397 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4272 13:37:50.688037 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4273 13:37:50.688136
4274 13:37:50.691098 [DATLAT]
4275 13:37:50.691173 Freq=600, CH0 RK1
4276 13:37:50.691234
4277 13:37:50.694252 DATLAT Default: 0x9
4278 13:37:50.694346 0, 0xFFFF, sum = 0
4279 13:37:50.698019 1, 0xFFFF, sum = 0
4280 13:37:50.698120 2, 0xFFFF, sum = 0
4281 13:37:50.701519 3, 0xFFFF, sum = 0
4282 13:37:50.701591 4, 0xFFFF, sum = 0
4283 13:37:50.704479 5, 0xFFFF, sum = 0
4284 13:37:50.704554 6, 0xFFFF, sum = 0
4285 13:37:50.708099 7, 0xFFFF, sum = 0
4286 13:37:50.708174 8, 0x0, sum = 1
4287 13:37:50.711287 9, 0x0, sum = 2
4288 13:37:50.711362 10, 0x0, sum = 3
4289 13:37:50.714336 11, 0x0, sum = 4
4290 13:37:50.714410 best_step = 9
4291 13:37:50.714469
4292 13:37:50.714525 ==
4293 13:37:50.717943 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 13:37:50.721040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 13:37:50.724767 ==
4296 13:37:50.724873 RX Vref Scan: 0
4297 13:37:50.724960
4298 13:37:50.727792 RX Vref 0 -> 0, step: 1
4299 13:37:50.727863
4300 13:37:50.731505 RX Delay -195 -> 252, step: 8
4301 13:37:50.734798 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4302 13:37:50.737856 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4303 13:37:50.744827 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4304 13:37:50.748057 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4305 13:37:50.751142 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4306 13:37:50.754870 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4307 13:37:50.761459 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4308 13:37:50.764944 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4309 13:37:50.767901 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4310 13:37:50.771565 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4311 13:37:50.774705 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4312 13:37:50.781458 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4313 13:37:50.784915 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4314 13:37:50.788001 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4315 13:37:50.791317 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4316 13:37:50.798121 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4317 13:37:50.798286 ==
4318 13:37:50.801421 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 13:37:50.804501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 13:37:50.804629 ==
4321 13:37:50.804722 DQS Delay:
4322 13:37:50.808152 DQS0 = 0, DQS1 = 0
4323 13:37:50.808232 DQM Delay:
4324 13:37:50.811207 DQM0 = 41, DQM1 = 33
4325 13:37:50.811284 DQ Delay:
4326 13:37:50.814666 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4327 13:37:50.817975 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4328 13:37:50.821297 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4329 13:37:50.824593 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4330 13:37:50.824669
4331 13:37:50.824729
4332 13:37:50.831368 [DQSOSCAuto] RK1, (LSB)MR18= 0x5234, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4333 13:37:50.835155 CH0 RK1: MR19=808, MR18=5234
4334 13:37:50.841594 CH0_RK1: MR19=0x808, MR18=0x5234, DQSOSC=394, MR23=63, INC=168, DEC=112
4335 13:37:50.844691 [RxdqsGatingPostProcess] freq 600
4336 13:37:50.851688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 13:37:50.851785 Pre-setting of DQS Precalculation
4338 13:37:50.858450 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 13:37:50.858549 ==
4340 13:37:50.861550 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 13:37:50.864700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 13:37:50.864793 ==
4343 13:37:50.871558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 13:37:50.878310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4345 13:37:50.881303 [CA 0] Center 35 (5~66) winsize 62
4346 13:37:50.885091 [CA 1] Center 35 (5~66) winsize 62
4347 13:37:50.888131 [CA 2] Center 34 (4~65) winsize 62
4348 13:37:50.891702 [CA 3] Center 33 (3~64) winsize 62
4349 13:37:50.894886 [CA 4] Center 34 (3~65) winsize 63
4350 13:37:50.898119 [CA 5] Center 33 (3~64) winsize 62
4351 13:37:50.898200
4352 13:37:50.901758 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4353 13:37:50.901842
4354 13:37:50.904565 [CATrainingPosCal] consider 1 rank data
4355 13:37:50.908195 u2DelayCellTimex100 = 270/100 ps
4356 13:37:50.911596 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 13:37:50.914710 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4358 13:37:50.918313 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 13:37:50.921800 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 13:37:50.924876 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4361 13:37:50.928239 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4362 13:37:50.928324
4363 13:37:50.931987 CA PerBit enable=1, Macro0, CA PI delay=33
4364 13:37:50.934829
4365 13:37:50.934910 [CBTSetCACLKResult] CA Dly = 33
4366 13:37:50.938427 CS Dly: 4 (0~35)
4367 13:37:50.938512 ==
4368 13:37:50.941459 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 13:37:50.945131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 13:37:50.945224 ==
4371 13:37:50.951596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 13:37:50.958614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4373 13:37:50.961618 [CA 0] Center 35 (5~66) winsize 62
4374 13:37:50.964914 [CA 1] Center 35 (5~66) winsize 62
4375 13:37:50.968256 [CA 2] Center 34 (4~65) winsize 62
4376 13:37:50.972065 [CA 3] Center 34 (3~65) winsize 63
4377 13:37:50.975163 [CA 4] Center 34 (4~65) winsize 62
4378 13:37:50.978393 [CA 5] Center 33 (3~64) winsize 62
4379 13:37:50.978510
4380 13:37:50.982059 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4381 13:37:50.982162
4382 13:37:50.984939 [CATrainingPosCal] consider 2 rank data
4383 13:37:50.988800 u2DelayCellTimex100 = 270/100 ps
4384 13:37:50.992086 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 13:37:50.995136 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 13:37:50.998860 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 13:37:51.002122 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 13:37:51.005165 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 13:37:51.008238 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 13:37:51.008328
4391 13:37:51.012191 CA PerBit enable=1, Macro0, CA PI delay=33
4392 13:37:51.015200
4393 13:37:51.015296 [CBTSetCACLKResult] CA Dly = 33
4394 13:37:51.018519 CS Dly: 4 (0~36)
4395 13:37:51.018605
4396 13:37:51.021955 ----->DramcWriteLeveling(PI) begin...
4397 13:37:51.022044 ==
4398 13:37:51.025158 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 13:37:51.028295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 13:37:51.028389 ==
4401 13:37:51.031979 Write leveling (Byte 0): 28 => 28
4402 13:37:51.035004 Write leveling (Byte 1): 31 => 31
4403 13:37:51.038570 DramcWriteLeveling(PI) end<-----
4404 13:37:51.038689
4405 13:37:51.038780 ==
4406 13:37:51.041993 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 13:37:51.045350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 13:37:51.045445 ==
4409 13:37:51.048610 [Gating] SW mode calibration
4410 13:37:51.055225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 13:37:51.061640 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 13:37:51.065572 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4413 13:37:51.071736 0 9 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4414 13:37:51.075471 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 13:37:51.078513 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
4416 13:37:51.081731 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4417 13:37:51.088233 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4418 13:37:51.092138 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 13:37:51.095291 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 13:37:51.102067 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 13:37:51.104991 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 13:37:51.108317 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 13:37:51.115047 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4424 13:37:51.118839 0 10 16 | B1->B0 | 3b3b 4141 | 0 1 | (0 0) (0 0)
4425 13:37:51.122054 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 13:37:51.128410 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 13:37:51.132187 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 13:37:51.135477 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:37:51.142306 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 13:37:51.145396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 13:37:51.148916 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 13:37:51.152387 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:37:51.158722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:37:51.162294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:37:51.165629 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:37:51.172501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:37:51.175614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:37:51.178751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:37:51.185622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:37:51.188583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:37:51.192518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:37:51.198921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:37:51.202433 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:37:51.205534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:37:51.212514 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 13:37:51.215735 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 13:37:51.218794 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 13:37:51.225643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:37:51.225731 Total UI for P1: 0, mck2ui 16
4450 13:37:51.228824 best dqsien dly found for B0: ( 0, 13, 12)
4451 13:37:51.232004 Total UI for P1: 0, mck2ui 16
4452 13:37:51.235678 best dqsien dly found for B1: ( 0, 13, 12)
4453 13:37:51.242292 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4454 13:37:51.245521 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4455 13:37:51.245608
4456 13:37:51.248559 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 13:37:51.252419 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 13:37:51.255523 [Gating] SW calibration Done
4459 13:37:51.255605 ==
4460 13:37:51.258655 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 13:37:51.262272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 13:37:51.262366 ==
4463 13:37:51.265201 RX Vref Scan: 0
4464 13:37:51.265331
4465 13:37:51.265425 RX Vref 0 -> 0, step: 1
4466 13:37:51.265514
4467 13:37:51.268788 RX Delay -230 -> 252, step: 16
4468 13:37:51.272396 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4469 13:37:51.279002 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 13:37:51.282336 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4471 13:37:51.285543 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4472 13:37:51.288677 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4473 13:37:51.292424 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4474 13:37:51.298827 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4475 13:37:51.302345 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4476 13:37:51.305519 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4477 13:37:51.308921 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4478 13:37:51.315283 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4479 13:37:51.319024 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4480 13:37:51.322013 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4481 13:37:51.325226 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4482 13:37:51.332128 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4483 13:37:51.335305 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4484 13:37:51.335415 ==
4485 13:37:51.339100 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 13:37:51.342113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 13:37:51.342203 ==
4488 13:37:51.342273 DQS Delay:
4489 13:37:51.345620 DQS0 = 0, DQS1 = 0
4490 13:37:51.345727 DQM Delay:
4491 13:37:51.348522 DQM0 = 44, DQM1 = 35
4492 13:37:51.348595 DQ Delay:
4493 13:37:51.351925 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4494 13:37:51.355520 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4495 13:37:51.359112 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4496 13:37:51.362232 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4497 13:37:51.362324
4498 13:37:51.362387
4499 13:37:51.362445 ==
4500 13:37:51.365803 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 13:37:51.368808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 13:37:51.372355 ==
4503 13:37:51.372460
4504 13:37:51.372555
4505 13:37:51.372645 TX Vref Scan disable
4506 13:37:51.375783 == TX Byte 0 ==
4507 13:37:51.378846 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 13:37:51.382166 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 13:37:51.385867 == TX Byte 1 ==
4510 13:37:51.388835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4511 13:37:51.392019 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4512 13:37:51.395774 ==
4513 13:37:51.395888 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 13:37:51.402159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 13:37:51.402253 ==
4516 13:37:51.402321
4517 13:37:51.402380
4518 13:37:51.405959 TX Vref Scan disable
4519 13:37:51.406042 == TX Byte 0 ==
4520 13:37:51.412561 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 13:37:51.415560 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 13:37:51.415650 == TX Byte 1 ==
4523 13:37:51.422468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4524 13:37:51.425511 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4525 13:37:51.425620
4526 13:37:51.425711 [DATLAT]
4527 13:37:51.429281 Freq=600, CH1 RK0
4528 13:37:51.429371
4529 13:37:51.429437 DATLAT Default: 0x9
4530 13:37:51.432513 0, 0xFFFF, sum = 0
4531 13:37:51.432596 1, 0xFFFF, sum = 0
4532 13:37:51.435661 2, 0xFFFF, sum = 0
4533 13:37:51.435752 3, 0xFFFF, sum = 0
4534 13:37:51.438904 4, 0xFFFF, sum = 0
4535 13:37:51.439024 5, 0xFFFF, sum = 0
4536 13:37:51.442073 6, 0xFFFF, sum = 0
4537 13:37:51.442163 7, 0xFFFF, sum = 0
4538 13:37:51.445647 8, 0x0, sum = 1
4539 13:37:51.445741 9, 0x0, sum = 2
4540 13:37:51.449221 10, 0x0, sum = 3
4541 13:37:51.449324 11, 0x0, sum = 4
4542 13:37:51.452345 best_step = 9
4543 13:37:51.452425
4544 13:37:51.452503 ==
4545 13:37:51.455839 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 13:37:51.458851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 13:37:51.458932 ==
4548 13:37:51.462079 RX Vref Scan: 1
4549 13:37:51.462163
4550 13:37:51.462225 RX Vref 0 -> 0, step: 1
4551 13:37:51.462283
4552 13:37:51.465833 RX Delay -195 -> 252, step: 8
4553 13:37:51.465908
4554 13:37:51.468799 Set Vref, RX VrefLevel [Byte0]: 56
4555 13:37:51.472047 [Byte1]: 51
4556 13:37:51.475543
4557 13:37:51.475660 Final RX Vref Byte 0 = 56 to rank0
4558 13:37:51.479467 Final RX Vref Byte 1 = 51 to rank0
4559 13:37:51.482187 Final RX Vref Byte 0 = 56 to rank1
4560 13:37:51.485811 Final RX Vref Byte 1 = 51 to rank1==
4561 13:37:51.488983 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 13:37:51.495865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 13:37:51.495987 ==
4564 13:37:51.496081 DQS Delay:
4565 13:37:51.496168 DQS0 = 0, DQS1 = 0
4566 13:37:51.498987 DQM Delay:
4567 13:37:51.499060 DQM0 = 41, DQM1 = 33
4568 13:37:51.502777 DQ Delay:
4569 13:37:51.505855 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4570 13:37:51.505930 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4571 13:37:51.509267 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4572 13:37:51.512756 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4573 13:37:51.515729
4574 13:37:51.515828
4575 13:37:51.522518 [DQSOSCAuto] RK0, (LSB)MR18= 0x4005, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
4576 13:37:51.525779 CH1 RK0: MR19=808, MR18=4005
4577 13:37:51.532582 CH1_RK0: MR19=0x808, MR18=0x4005, DQSOSC=397, MR23=63, INC=166, DEC=110
4578 13:37:51.532687
4579 13:37:51.535756 ----->DramcWriteLeveling(PI) begin...
4580 13:37:51.535853 ==
4581 13:37:51.539542 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 13:37:51.542840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 13:37:51.542924 ==
4584 13:37:51.546516 Write leveling (Byte 0): 29 => 29
4585 13:37:51.549624 Write leveling (Byte 1): 30 => 30
4586 13:37:51.552659 DramcWriteLeveling(PI) end<-----
4587 13:37:51.552742
4588 13:37:51.552806 ==
4589 13:37:51.556333 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 13:37:51.559995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 13:37:51.560090 ==
4592 13:37:51.562810 [Gating] SW mode calibration
4593 13:37:51.569648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 13:37:51.576667 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 13:37:51.579641 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4596 13:37:51.582871 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4597 13:37:51.589279 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4598 13:37:51.592746 0 9 12 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 0)
4599 13:37:51.595905 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 13:37:51.603047 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 13:37:51.606175 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 13:37:51.609225 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4603 13:37:51.616285 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4604 13:37:51.619300 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4605 13:37:51.622464 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4606 13:37:51.629472 0 10 12 | B1->B0 | 2d2d 4141 | 0 0 | (0 0) (0 0)
4607 13:37:51.632724 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 13:37:51.635789 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 13:37:51.639460 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 13:37:51.646038 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 13:37:51.649936 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:37:51.652847 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 13:37:51.660030 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4614 13:37:51.662987 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4615 13:37:51.665948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:37:51.672842 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:37:51.676242 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:37:51.679270 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:37:51.686108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:37:51.689358 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:37:51.692929 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:37:51.699674 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 13:37:51.702700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:37:51.705996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 13:37:51.713171 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 13:37:51.716344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 13:37:51.719573 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 13:37:51.722711 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 13:37:51.729812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 13:37:51.732890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4631 13:37:51.736025 Total UI for P1: 0, mck2ui 16
4632 13:37:51.739447 best dqsien dly found for B0: ( 0, 13, 10)
4633 13:37:51.743089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 13:37:51.745876 Total UI for P1: 0, mck2ui 16
4635 13:37:51.749760 best dqsien dly found for B1: ( 0, 13, 12)
4636 13:37:51.752886 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4637 13:37:51.755940 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4638 13:37:51.756036
4639 13:37:51.763202 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 13:37:51.766383 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4641 13:37:51.769692 [Gating] SW calibration Done
4642 13:37:51.769819 ==
4643 13:37:51.772812 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 13:37:51.776389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 13:37:51.776481 ==
4646 13:37:51.776547 RX Vref Scan: 0
4647 13:37:51.776609
4648 13:37:51.779852 RX Vref 0 -> 0, step: 1
4649 13:37:51.779939
4650 13:37:51.783128 RX Delay -230 -> 252, step: 16
4651 13:37:51.786279 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4652 13:37:51.789386 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4653 13:37:51.796005 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4654 13:37:51.799425 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4655 13:37:51.803210 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4656 13:37:51.806203 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4657 13:37:51.812734 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4658 13:37:51.815988 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4659 13:37:51.819718 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4660 13:37:51.822717 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4661 13:37:51.825975 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4662 13:37:51.832822 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4663 13:37:51.836802 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4664 13:37:51.839755 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4665 13:37:51.842923 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4666 13:37:51.849628 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4667 13:37:51.849736 ==
4668 13:37:51.853192 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 13:37:51.856334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 13:37:51.856428 ==
4671 13:37:51.856496 DQS Delay:
4672 13:37:51.859546 DQS0 = 0, DQS1 = 0
4673 13:37:51.859628 DQM Delay:
4674 13:37:51.862691 DQM0 = 39, DQM1 = 36
4675 13:37:51.862777 DQ Delay:
4676 13:37:51.866302 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4677 13:37:51.869529 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4678 13:37:51.872754 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4679 13:37:51.876566 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4680 13:37:51.876656
4681 13:37:51.876753
4682 13:37:51.876859 ==
4683 13:37:51.879754 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 13:37:51.882977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 13:37:51.883059 ==
4686 13:37:51.883122
4687 13:37:51.883188
4688 13:37:51.886069 TX Vref Scan disable
4689 13:37:51.889389 == TX Byte 0 ==
4690 13:37:51.893015 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 13:37:51.896091 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 13:37:51.899734 == TX Byte 1 ==
4693 13:37:51.902627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 13:37:51.906462 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 13:37:51.906556 ==
4696 13:37:51.909661 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 13:37:51.916436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 13:37:51.916546 ==
4699 13:37:51.916615
4700 13:37:51.916675
4701 13:37:51.916732 TX Vref Scan disable
4702 13:37:51.920715 == TX Byte 0 ==
4703 13:37:51.923666 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 13:37:51.927551 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 13:37:51.930899 == TX Byte 1 ==
4706 13:37:51.934020 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 13:37:51.937111 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 13:37:51.940279
4709 13:37:51.940406 [DATLAT]
4710 13:37:51.940532 Freq=600, CH1 RK1
4711 13:37:51.940623
4712 13:37:51.944193 DATLAT Default: 0x9
4713 13:37:51.944320 0, 0xFFFF, sum = 0
4714 13:37:51.947449 1, 0xFFFF, sum = 0
4715 13:37:51.947581 2, 0xFFFF, sum = 0
4716 13:37:51.950503 3, 0xFFFF, sum = 0
4717 13:37:51.950593 4, 0xFFFF, sum = 0
4718 13:37:51.953670 5, 0xFFFF, sum = 0
4719 13:37:51.953766 6, 0xFFFF, sum = 0
4720 13:37:51.957593 7, 0xFFFF, sum = 0
4721 13:37:51.957714 8, 0x0, sum = 1
4722 13:37:51.960570 9, 0x0, sum = 2
4723 13:37:51.960684 10, 0x0, sum = 3
4724 13:37:51.963947 11, 0x0, sum = 4
4725 13:37:51.964071 best_step = 9
4726 13:37:51.964151
4727 13:37:51.964249 ==
4728 13:37:51.967525 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 13:37:51.973746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 13:37:51.973860 ==
4731 13:37:51.973936 RX Vref Scan: 0
4732 13:37:51.974000
4733 13:37:51.976952 RX Vref 0 -> 0, step: 1
4734 13:37:51.977066
4735 13:37:51.980695 RX Delay -179 -> 252, step: 8
4736 13:37:51.984074 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4737 13:37:51.990355 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4738 13:37:51.993574 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4739 13:37:51.997339 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4740 13:37:52.000532 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4741 13:37:52.003795 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4742 13:37:52.010357 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4743 13:37:52.014020 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4744 13:37:52.016827 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4745 13:37:52.020143 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4746 13:37:52.027096 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4747 13:37:52.030593 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4748 13:37:52.034107 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4749 13:37:52.037182 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4750 13:37:52.040646 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4751 13:37:52.047520 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4752 13:37:52.047628 ==
4753 13:37:52.050676 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 13:37:52.053722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 13:37:52.053829 ==
4756 13:37:52.053897 DQS Delay:
4757 13:37:52.057630 DQS0 = 0, DQS1 = 0
4758 13:37:52.057719 DQM Delay:
4759 13:37:52.060548 DQM0 = 37, DQM1 = 32
4760 13:37:52.060634 DQ Delay:
4761 13:37:52.063708 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4762 13:37:52.067384 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4763 13:37:52.070632 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4764 13:37:52.074182 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4765 13:37:52.074302
4766 13:37:52.074403
4767 13:37:52.080798 [DQSOSCAuto] RK1, (LSB)MR18= 0x3545, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4768 13:37:52.083894 CH1 RK1: MR19=808, MR18=3545
4769 13:37:52.090882 CH1_RK1: MR19=0x808, MR18=0x3545, DQSOSC=396, MR23=63, INC=167, DEC=111
4770 13:37:52.094207 [RxdqsGatingPostProcess] freq 600
4771 13:37:52.100594 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 13:37:52.103849 Pre-setting of DQS Precalculation
4773 13:37:52.107415 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 13:37:52.113776 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 13:37:52.120691 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 13:37:52.120786
4777 13:37:52.120854
4778 13:37:52.123743 [Calibration Summary] 1200 Mbps
4779 13:37:52.127088 CH 0, Rank 0
4780 13:37:52.127178 SW Impedance : PASS
4781 13:37:52.130360 DUTY Scan : NO K
4782 13:37:52.133938 ZQ Calibration : PASS
4783 13:37:52.134026 Jitter Meter : NO K
4784 13:37:52.137293 CBT Training : PASS
4785 13:37:52.140719 Write leveling : PASS
4786 13:37:52.140810 RX DQS gating : PASS
4787 13:37:52.144093 RX DQ/DQS(RDDQC) : PASS
4788 13:37:52.144178 TX DQ/DQS : PASS
4789 13:37:52.147001 RX DATLAT : PASS
4790 13:37:52.150690 RX DQ/DQS(Engine): PASS
4791 13:37:52.150807 TX OE : NO K
4792 13:37:52.153780 All Pass.
4793 13:37:52.153864
4794 13:37:52.153929 CH 0, Rank 1
4795 13:37:52.157462 SW Impedance : PASS
4796 13:37:52.157572 DUTY Scan : NO K
4797 13:37:52.160591 ZQ Calibration : PASS
4798 13:37:52.163714 Jitter Meter : NO K
4799 13:37:52.163807 CBT Training : PASS
4800 13:37:52.167321 Write leveling : PASS
4801 13:37:52.170639 RX DQS gating : PASS
4802 13:37:52.170755 RX DQ/DQS(RDDQC) : PASS
4803 13:37:52.173737 TX DQ/DQS : PASS
4804 13:37:52.176961 RX DATLAT : PASS
4805 13:37:52.177076 RX DQ/DQS(Engine): PASS
4806 13:37:52.180756 TX OE : NO K
4807 13:37:52.180868 All Pass.
4808 13:37:52.180962
4809 13:37:52.183753 CH 1, Rank 0
4810 13:37:52.183863 SW Impedance : PASS
4811 13:37:52.187276 DUTY Scan : NO K
4812 13:37:52.187417 ZQ Calibration : PASS
4813 13:37:52.190362 Jitter Meter : NO K
4814 13:37:52.194135 CBT Training : PASS
4815 13:37:52.194241 Write leveling : PASS
4816 13:37:52.197659 RX DQS gating : PASS
4817 13:37:52.200759 RX DQ/DQS(RDDQC) : PASS
4818 13:37:52.200848 TX DQ/DQS : PASS
4819 13:37:52.203917 RX DATLAT : PASS
4820 13:37:52.207294 RX DQ/DQS(Engine): PASS
4821 13:37:52.207418 TX OE : NO K
4822 13:37:52.211081 All Pass.
4823 13:37:52.211190
4824 13:37:52.211289 CH 1, Rank 1
4825 13:37:52.213973 SW Impedance : PASS
4826 13:37:52.214092 DUTY Scan : NO K
4827 13:37:52.217756 ZQ Calibration : PASS
4828 13:37:52.220927 Jitter Meter : NO K
4829 13:37:52.221052 CBT Training : PASS
4830 13:37:52.224035 Write leveling : PASS
4831 13:37:52.224128 RX DQS gating : PASS
4832 13:37:52.227209 RX DQ/DQS(RDDQC) : PASS
4833 13:37:52.230861 TX DQ/DQS : PASS
4834 13:37:52.230945 RX DATLAT : PASS
4835 13:37:52.234388 RX DQ/DQS(Engine): PASS
4836 13:37:52.237341 TX OE : NO K
4837 13:37:52.237450 All Pass.
4838 13:37:52.237542
4839 13:37:52.240467 DramC Write-DBI off
4840 13:37:52.240580 PER_BANK_REFRESH: Hybrid Mode
4841 13:37:52.244470 TX_TRACKING: ON
4842 13:37:52.251044 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 13:37:52.257317 [FAST_K] Save calibration result to emmc
4844 13:37:52.260529 dramc_set_vcore_voltage set vcore to 662500
4845 13:37:52.260649 Read voltage for 933, 3
4846 13:37:52.264073 Vio18 = 0
4847 13:37:52.264166 Vcore = 662500
4848 13:37:52.264233 Vdram = 0
4849 13:37:52.267219 Vddq = 0
4850 13:37:52.267303 Vmddr = 0
4851 13:37:52.270952 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 13:37:52.277087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 13:37:52.280916 MEM_TYPE=3, freq_sel=17
4854 13:37:52.284122 sv_algorithm_assistance_LP4_1600
4855 13:37:52.287477 ============ PULL DRAM RESETB DOWN ============
4856 13:37:52.290399 ========== PULL DRAM RESETB DOWN end =========
4857 13:37:52.294044 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 13:37:52.297559 ===================================
4859 13:37:52.300763 LPDDR4 DRAM CONFIGURATION
4860 13:37:52.304071 ===================================
4861 13:37:52.307197 EX_ROW_EN[0] = 0x0
4862 13:37:52.307281 EX_ROW_EN[1] = 0x0
4863 13:37:52.310941 LP4Y_EN = 0x0
4864 13:37:52.311024 WORK_FSP = 0x0
4865 13:37:52.314143 WL = 0x3
4866 13:37:52.314227 RL = 0x3
4867 13:37:52.317405 BL = 0x2
4868 13:37:52.317491 RPST = 0x0
4869 13:37:52.321072 RD_PRE = 0x0
4870 13:37:52.321163 WR_PRE = 0x1
4871 13:37:52.324034 WR_PST = 0x0
4872 13:37:52.324142 DBI_WR = 0x0
4873 13:37:52.327227 DBI_RD = 0x0
4874 13:37:52.331055 OTF = 0x1
4875 13:37:52.331147 ===================================
4876 13:37:52.334418 ===================================
4877 13:37:52.337498 ANA top config
4878 13:37:52.341083 ===================================
4879 13:37:52.344329 DLL_ASYNC_EN = 0
4880 13:37:52.344414 ALL_SLAVE_EN = 1
4881 13:37:52.347397 NEW_RANK_MODE = 1
4882 13:37:52.350608 DLL_IDLE_MODE = 1
4883 13:37:52.354489 LP45_APHY_COMB_EN = 1
4884 13:37:52.354579 TX_ODT_DIS = 1
4885 13:37:52.357621 NEW_8X_MODE = 1
4886 13:37:52.361164 ===================================
4887 13:37:52.364328 ===================================
4888 13:37:52.367613 data_rate = 1866
4889 13:37:52.371071 CKR = 1
4890 13:37:52.374704 DQ_P2S_RATIO = 8
4891 13:37:52.378133 ===================================
4892 13:37:52.381248 CA_P2S_RATIO = 8
4893 13:37:52.381330 DQ_CA_OPEN = 0
4894 13:37:52.384297 DQ_SEMI_OPEN = 0
4895 13:37:52.388128 CA_SEMI_OPEN = 0
4896 13:37:52.391389 CA_FULL_RATE = 0
4897 13:37:52.394448 DQ_CKDIV4_EN = 1
4898 13:37:52.394556 CA_CKDIV4_EN = 1
4899 13:37:52.397587 CA_PREDIV_EN = 0
4900 13:37:52.401195 PH8_DLY = 0
4901 13:37:52.404796 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 13:37:52.408060 DQ_AAMCK_DIV = 4
4903 13:37:52.411122 CA_AAMCK_DIV = 4
4904 13:37:52.411206 CA_ADMCK_DIV = 4
4905 13:37:52.414318 DQ_TRACK_CA_EN = 0
4906 13:37:52.417446 CA_PICK = 933
4907 13:37:52.421197 CA_MCKIO = 933
4908 13:37:52.424304 MCKIO_SEMI = 0
4909 13:37:52.427313 PLL_FREQ = 3732
4910 13:37:52.431387 DQ_UI_PI_RATIO = 32
4911 13:37:52.431483 CA_UI_PI_RATIO = 0
4912 13:37:52.434577 ===================================
4913 13:37:52.437845 ===================================
4914 13:37:52.440925 memory_type:LPDDR4
4915 13:37:52.444073 GP_NUM : 10
4916 13:37:52.444160 SRAM_EN : 1
4917 13:37:52.447846 MD32_EN : 0
4918 13:37:52.450933 ===================================
4919 13:37:52.454430 [ANA_INIT] >>>>>>>>>>>>>>
4920 13:37:52.457571 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 13:37:52.461277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 13:37:52.464416 ===================================
4923 13:37:52.464537 data_rate = 1866,PCW = 0X8f00
4924 13:37:52.467625 ===================================
4925 13:37:52.471394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 13:37:52.477939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 13:37:52.484156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 13:37:52.487807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 13:37:52.491300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 13:37:52.494148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 13:37:52.497652 [ANA_INIT] flow start
4932 13:37:52.497743 [ANA_INIT] PLL >>>>>>>>
4933 13:37:52.501273 [ANA_INIT] PLL <<<<<<<<
4934 13:37:52.504331 [ANA_INIT] MIDPI >>>>>>>>
4935 13:37:52.507418 [ANA_INIT] MIDPI <<<<<<<<
4936 13:37:52.507505 [ANA_INIT] DLL >>>>>>>>
4937 13:37:52.511120 [ANA_INIT] flow end
4938 13:37:52.514105 ============ LP4 DIFF to SE enter ============
4939 13:37:52.517785 ============ LP4 DIFF to SE exit ============
4940 13:37:52.520931 [ANA_INIT] <<<<<<<<<<<<<
4941 13:37:52.524142 [Flow] Enable top DCM control >>>>>
4942 13:37:52.528000 [Flow] Enable top DCM control <<<<<
4943 13:37:52.531003 Enable DLL master slave shuffle
4944 13:37:52.538048 ==============================================================
4945 13:37:52.538154 Gating Mode config
4946 13:37:52.544303 ==============================================================
4947 13:37:52.544412 Config description:
4948 13:37:52.554572 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 13:37:52.560641 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 13:37:52.567236 SELPH_MODE 0: By rank 1: By Phase
4951 13:37:52.570584 ==============================================================
4952 13:37:52.574303 GAT_TRACK_EN = 1
4953 13:37:52.577437 RX_GATING_MODE = 2
4954 13:37:52.581223 RX_GATING_TRACK_MODE = 2
4955 13:37:52.584149 SELPH_MODE = 1
4956 13:37:52.588006 PICG_EARLY_EN = 1
4957 13:37:52.591206 VALID_LAT_VALUE = 1
4958 13:37:52.594457 ==============================================================
4959 13:37:52.597580 Enter into Gating configuration >>>>
4960 13:37:52.601162 Exit from Gating configuration <<<<
4961 13:37:52.604492 Enter into DVFS_PRE_config >>>>>
4962 13:37:52.617701 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 13:37:52.617869 Exit from DVFS_PRE_config <<<<<
4964 13:37:52.621083 Enter into PICG configuration >>>>
4965 13:37:52.624287 Exit from PICG configuration <<<<
4966 13:37:52.628135 [RX_INPUT] configuration >>>>>
4967 13:37:52.631413 [RX_INPUT] configuration <<<<<
4968 13:37:52.638122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 13:37:52.641378 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 13:37:52.647773 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 13:37:52.654818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 13:37:52.661209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 13:37:52.667850 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 13:37:52.671207 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 13:37:52.674767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 13:37:52.678038 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 13:37:52.684161 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 13:37:52.687693 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 13:37:52.691339 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 13:37:52.694330 ===================================
4981 13:37:52.697566 LPDDR4 DRAM CONFIGURATION
4982 13:37:52.700936 ===================================
4983 13:37:52.701096 EX_ROW_EN[0] = 0x0
4984 13:37:52.704528 EX_ROW_EN[1] = 0x0
4985 13:37:52.704610 LP4Y_EN = 0x0
4986 13:37:52.707782 WORK_FSP = 0x0
4987 13:37:52.711253 WL = 0x3
4988 13:37:52.711378 RL = 0x3
4989 13:37:52.714695 BL = 0x2
4990 13:37:52.714803 RPST = 0x0
4991 13:37:52.717761 RD_PRE = 0x0
4992 13:37:52.717863 WR_PRE = 0x1
4993 13:37:52.721327 WR_PST = 0x0
4994 13:37:52.721412 DBI_WR = 0x0
4995 13:37:52.724217 DBI_RD = 0x0
4996 13:37:52.724323 OTF = 0x1
4997 13:37:52.727755 ===================================
4998 13:37:52.731379 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 13:37:52.737701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 13:37:52.741403 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 13:37:52.744663 ===================================
5002 13:37:52.747807 LPDDR4 DRAM CONFIGURATION
5003 13:37:52.750993 ===================================
5004 13:37:52.751084 EX_ROW_EN[0] = 0x10
5005 13:37:52.754932 EX_ROW_EN[1] = 0x0
5006 13:37:52.755017 LP4Y_EN = 0x0
5007 13:37:52.758045 WORK_FSP = 0x0
5008 13:37:52.758130 WL = 0x3
5009 13:37:52.761216 RL = 0x3
5010 13:37:52.761320 BL = 0x2
5011 13:37:52.764423 RPST = 0x0
5012 13:37:52.764515 RD_PRE = 0x0
5013 13:37:52.768262 WR_PRE = 0x1
5014 13:37:52.768349 WR_PST = 0x0
5015 13:37:52.771349 DBI_WR = 0x0
5016 13:37:52.771434 DBI_RD = 0x0
5017 13:37:52.774513 OTF = 0x1
5018 13:37:52.778251 ===================================
5019 13:37:52.784348 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 13:37:52.788209 nWR fixed to 30
5021 13:37:52.791138 [ModeRegInit_LP4] CH0 RK0
5022 13:37:52.791232 [ModeRegInit_LP4] CH0 RK1
5023 13:37:52.794220 [ModeRegInit_LP4] CH1 RK0
5024 13:37:52.797713 [ModeRegInit_LP4] CH1 RK1
5025 13:37:52.797807 match AC timing 9
5026 13:37:52.804610 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 13:37:52.807850 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 13:37:52.811524 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 13:37:52.817959 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 13:37:52.821179 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 13:37:52.821288 ==
5032 13:37:52.824706 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 13:37:52.828281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 13:37:52.828386 ==
5035 13:37:52.834638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 13:37:52.841178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 13:37:52.844761 [CA 0] Center 38 (8~69) winsize 62
5038 13:37:52.847784 [CA 1] Center 38 (8~69) winsize 62
5039 13:37:52.851021 [CA 2] Center 35 (5~66) winsize 62
5040 13:37:52.854807 [CA 3] Center 35 (5~66) winsize 62
5041 13:37:52.858043 [CA 4] Center 34 (4~64) winsize 61
5042 13:37:52.861097 [CA 5] Center 34 (4~64) winsize 61
5043 13:37:52.861232
5044 13:37:52.864912 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 13:37:52.865127
5046 13:37:52.868041 [CATrainingPosCal] consider 1 rank data
5047 13:37:52.871267 u2DelayCellTimex100 = 270/100 ps
5048 13:37:52.874506 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5049 13:37:52.878281 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5050 13:37:52.881386 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5051 13:37:52.884635 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5052 13:37:52.887826 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5053 13:37:52.891314 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5054 13:37:52.891513
5055 13:37:52.894646 CA PerBit enable=1, Macro0, CA PI delay=34
5056 13:37:52.897971
5057 13:37:52.898133 [CBTSetCACLKResult] CA Dly = 34
5058 13:37:52.901464 CS Dly: 6 (0~37)
5059 13:37:52.901620 ==
5060 13:37:52.904372 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 13:37:52.907880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 13:37:52.908035 ==
5063 13:37:52.914911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 13:37:52.921031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 13:37:52.924379 [CA 0] Center 38 (8~69) winsize 62
5066 13:37:52.928274 [CA 1] Center 38 (8~69) winsize 62
5067 13:37:52.931413 [CA 2] Center 35 (5~66) winsize 62
5068 13:37:52.934997 [CA 3] Center 35 (5~66) winsize 62
5069 13:37:52.938481 [CA 4] Center 33 (3~64) winsize 62
5070 13:37:52.938641 [CA 5] Center 33 (3~64) winsize 62
5071 13:37:52.941297
5072 13:37:52.944848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 13:37:52.945016
5074 13:37:52.948562 [CATrainingPosCal] consider 2 rank data
5075 13:37:52.951514 u2DelayCellTimex100 = 270/100 ps
5076 13:37:52.955059 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 13:37:52.958240 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5078 13:37:52.961424 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5079 13:37:52.966605 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5080 13:37:52.968442 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 13:37:52.971503 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5082 13:37:52.971596
5083 13:37:52.974742 CA PerBit enable=1, Macro0, CA PI delay=34
5084 13:37:52.974832
5085 13:37:52.977926 [CBTSetCACLKResult] CA Dly = 34
5086 13:37:52.981782 CS Dly: 7 (0~39)
5087 13:37:52.981885
5088 13:37:52.984797 ----->DramcWriteLeveling(PI) begin...
5089 13:37:52.984911 ==
5090 13:37:52.988619 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 13:37:52.991764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 13:37:52.991856 ==
5093 13:37:52.995067 Write leveling (Byte 0): 34 => 34
5094 13:37:52.998183 Write leveling (Byte 1): 26 => 26
5095 13:37:53.001813 DramcWriteLeveling(PI) end<-----
5096 13:37:53.001926
5097 13:37:53.001994 ==
5098 13:37:53.005145 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 13:37:53.008730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 13:37:53.008844 ==
5101 13:37:53.011567 [Gating] SW mode calibration
5102 13:37:53.018382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 13:37:53.025403 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 13:37:53.028532 0 14 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5105 13:37:53.032021 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5106 13:37:53.038247 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 13:37:53.041572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 13:37:53.045236 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 13:37:53.051676 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 13:37:53.054933 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 13:37:53.058690 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5112 13:37:53.064938 0 15 0 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
5113 13:37:53.068689 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5114 13:37:53.071880 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 13:37:53.078273 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 13:37:53.082109 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 13:37:53.085303 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 13:37:53.092127 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 13:37:53.095254 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 13:37:53.098407 1 0 0 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (1 1)
5121 13:37:53.102272 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5122 13:37:53.108860 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 13:37:53.111809 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 13:37:53.115610 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 13:37:53.121980 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 13:37:53.125264 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 13:37:53.128742 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 13:37:53.135698 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 13:37:53.138521 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5130 13:37:53.141772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:37:53.148735 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:37:53.151743 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:37:53.155537 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:37:53.162058 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:37:53.165638 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:37:53.169006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 13:37:53.172056 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 13:37:53.179158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:37:53.182114 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:37:53.185351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 13:37:53.192246 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 13:37:53.195471 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 13:37:53.199223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5144 13:37:53.205430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 13:37:53.208651 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:37:53.212353 Total UI for P1: 0, mck2ui 16
5147 13:37:53.215248 best dqsien dly found for B0: ( 1, 3, 2)
5148 13:37:53.218853 Total UI for P1: 0, mck2ui 16
5149 13:37:53.222090 best dqsien dly found for B1: ( 1, 3, 2)
5150 13:37:53.225143 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5151 13:37:53.228489 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5152 13:37:53.228654
5153 13:37:53.231886 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5154 13:37:53.235281 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5155 13:37:53.238719 [Gating] SW calibration Done
5156 13:37:53.238840 ==
5157 13:37:53.242023 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 13:37:53.244880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 13:37:53.248388 ==
5160 13:37:53.248529 RX Vref Scan: 0
5161 13:37:53.248623
5162 13:37:53.251972 RX Vref 0 -> 0, step: 1
5163 13:37:53.252061
5164 13:37:53.252127 RX Delay -80 -> 252, step: 8
5165 13:37:53.258866 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5166 13:37:53.262300 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5167 13:37:53.265141 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5168 13:37:53.268234 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5169 13:37:53.271797 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5170 13:37:53.275451 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5171 13:37:53.281852 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5172 13:37:53.285242 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5173 13:37:53.288859 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5174 13:37:53.292030 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5175 13:37:53.295168 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5176 13:37:53.301570 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5177 13:37:53.304875 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5178 13:37:53.308525 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5179 13:37:53.311659 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5180 13:37:53.314928 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5181 13:37:53.315057 ==
5182 13:37:53.318403 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 13:37:53.324899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 13:37:53.325098 ==
5185 13:37:53.325187 DQS Delay:
5186 13:37:53.325251 DQS0 = 0, DQS1 = 0
5187 13:37:53.328680 DQM Delay:
5188 13:37:53.328831 DQM0 = 99, DQM1 = 86
5189 13:37:53.331794 DQ Delay:
5190 13:37:53.335043 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5191 13:37:53.338670 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5192 13:37:53.341380 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5193 13:37:53.344758 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5194 13:37:53.344881
5195 13:37:53.344993
5196 13:37:53.345091 ==
5197 13:37:53.348251 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 13:37:53.351782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 13:37:53.351893 ==
5200 13:37:53.351993
5201 13:37:53.352083
5202 13:37:53.355194 TX Vref Scan disable
5203 13:37:53.355305 == TX Byte 0 ==
5204 13:37:53.361602 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5205 13:37:53.365520 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5206 13:37:53.365651 == TX Byte 1 ==
5207 13:37:53.371535 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5208 13:37:53.374853 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5209 13:37:53.374979 ==
5210 13:37:53.378601 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 13:37:53.381566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 13:37:53.381676 ==
5213 13:37:53.381774
5214 13:37:53.385181
5215 13:37:53.385308 TX Vref Scan disable
5216 13:37:53.388097 == TX Byte 0 ==
5217 13:37:53.391676 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5218 13:37:53.395200 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5219 13:37:53.398061 == TX Byte 1 ==
5220 13:37:53.401830 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5221 13:37:53.404891 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5222 13:37:53.408086
5223 13:37:53.408250 [DATLAT]
5224 13:37:53.408388 Freq=933, CH0 RK0
5225 13:37:53.408512
5226 13:37:53.411342 DATLAT Default: 0xd
5227 13:37:53.411505 0, 0xFFFF, sum = 0
5228 13:37:53.415239 1, 0xFFFF, sum = 0
5229 13:37:53.415386 2, 0xFFFF, sum = 0
5230 13:37:53.418300 3, 0xFFFF, sum = 0
5231 13:37:53.418459 4, 0xFFFF, sum = 0
5232 13:37:53.421398 5, 0xFFFF, sum = 0
5233 13:37:53.425143 6, 0xFFFF, sum = 0
5234 13:37:53.425307 7, 0xFFFF, sum = 0
5235 13:37:53.428028 8, 0xFFFF, sum = 0
5236 13:37:53.428165 9, 0xFFFF, sum = 0
5237 13:37:53.431780 10, 0x0, sum = 1
5238 13:37:53.431928 11, 0x0, sum = 2
5239 13:37:53.432053 12, 0x0, sum = 3
5240 13:37:53.435031 13, 0x0, sum = 4
5241 13:37:53.435141 best_step = 11
5242 13:37:53.435236
5243 13:37:53.438202 ==
5244 13:37:53.438316 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 13:37:53.445345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 13:37:53.445450 ==
5247 13:37:53.445520 RX Vref Scan: 1
5248 13:37:53.445582
5249 13:37:53.448210 RX Vref 0 -> 0, step: 1
5250 13:37:53.448324
5251 13:37:53.451721 RX Delay -69 -> 252, step: 4
5252 13:37:53.451837
5253 13:37:53.454747 Set Vref, RX VrefLevel [Byte0]: 54
5254 13:37:53.458241 [Byte1]: 53
5255 13:37:53.458368
5256 13:37:53.461833 Final RX Vref Byte 0 = 54 to rank0
5257 13:37:53.465408 Final RX Vref Byte 1 = 53 to rank0
5258 13:37:53.468486 Final RX Vref Byte 0 = 54 to rank1
5259 13:37:53.471725 Final RX Vref Byte 1 = 53 to rank1==
5260 13:37:53.475112 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 13:37:53.478359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 13:37:53.478475 ==
5263 13:37:53.481427 DQS Delay:
5264 13:37:53.481532 DQS0 = 0, DQS1 = 0
5265 13:37:53.485434 DQM Delay:
5266 13:37:53.485546 DQM0 = 96, DQM1 = 89
5267 13:37:53.485643 DQ Delay:
5268 13:37:53.488490 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5269 13:37:53.491614 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5270 13:37:53.495165 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5271 13:37:53.498706 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5272 13:37:53.498829
5273 13:37:53.498924
5274 13:37:53.508148 [DQSOSCAuto] RK0, (LSB)MR18= 0x1904, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5275 13:37:53.511871 CH0 RK0: MR19=505, MR18=1904
5276 13:37:53.515180 CH0_RK0: MR19=0x505, MR18=0x1904, DQSOSC=413, MR23=63, INC=63, DEC=42
5277 13:37:53.515326
5278 13:37:53.518262 ----->DramcWriteLeveling(PI) begin...
5279 13:37:53.522032 ==
5280 13:37:53.525094 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 13:37:53.528161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 13:37:53.528336 ==
5283 13:37:53.532000 Write leveling (Byte 0): 32 => 32
5284 13:37:53.534844 Write leveling (Byte 1): 31 => 31
5285 13:37:53.538670 DramcWriteLeveling(PI) end<-----
5286 13:37:53.538806
5287 13:37:53.538905 ==
5288 13:37:53.541796 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 13:37:53.544906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 13:37:53.545030 ==
5291 13:37:53.548179 [Gating] SW mode calibration
5292 13:37:53.555101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 13:37:53.561587 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 13:37:53.564983 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5295 13:37:53.568039 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5296 13:37:53.571364 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 13:37:53.578034 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 13:37:53.581432 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 13:37:53.584942 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 13:37:53.591470 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 13:37:53.594822 0 14 28 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (1 0)
5302 13:37:53.598480 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
5303 13:37:53.604818 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5304 13:37:53.608567 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 13:37:53.611809 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 13:37:53.618107 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 13:37:53.621829 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 13:37:53.624850 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 13:37:53.631595 0 15 28 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
5310 13:37:53.634795 1 0 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5311 13:37:53.638432 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 13:37:53.644861 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 13:37:53.648608 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 13:37:53.651703 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 13:37:53.658168 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 13:37:53.661708 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5317 13:37:53.664940 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 13:37:53.668550 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5319 13:37:53.674965 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:37:53.678204 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:37:53.681358 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:37:53.688304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:37:53.691568 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:37:53.695128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:37:53.701575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:37:53.705086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 13:37:53.708654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 13:37:53.714907 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 13:37:53.718401 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 13:37:53.722074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 13:37:53.728403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 13:37:53.731753 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5333 13:37:53.735458 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 13:37:53.738595 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5335 13:37:53.742167 Total UI for P1: 0, mck2ui 16
5336 13:37:53.745410 best dqsien dly found for B0: ( 1, 2, 26)
5337 13:37:53.752181 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 13:37:53.755470 Total UI for P1: 0, mck2ui 16
5339 13:37:53.758543 best dqsien dly found for B1: ( 1, 3, 0)
5340 13:37:53.762343 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5341 13:37:53.765659 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5342 13:37:53.765788
5343 13:37:53.768796 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5344 13:37:53.772136 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5345 13:37:53.775565 [Gating] SW calibration Done
5346 13:37:53.775687 ==
5347 13:37:53.778576 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 13:37:53.782050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 13:37:53.782170 ==
5350 13:37:53.785770 RX Vref Scan: 0
5351 13:37:53.785890
5352 13:37:53.785986 RX Vref 0 -> 0, step: 1
5353 13:37:53.786084
5354 13:37:53.788819 RX Delay -80 -> 252, step: 8
5355 13:37:53.792060 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5356 13:37:53.798920 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5357 13:37:53.802054 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5358 13:37:53.805673 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5359 13:37:53.808473 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5360 13:37:53.811822 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5361 13:37:53.815039 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5362 13:37:53.818839 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5363 13:37:53.825184 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5364 13:37:53.828953 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5365 13:37:53.832089 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5366 13:37:53.834983 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5367 13:37:53.838626 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5368 13:37:53.845469 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5369 13:37:53.848169 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5370 13:37:53.851731 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5371 13:37:53.851821 ==
5372 13:37:53.854956 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 13:37:53.858302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 13:37:53.858389 ==
5375 13:37:53.861957 DQS Delay:
5376 13:37:53.862043 DQS0 = 0, DQS1 = 0
5377 13:37:53.862108 DQM Delay:
5378 13:37:53.865202 DQM0 = 97, DQM1 = 88
5379 13:37:53.865317 DQ Delay:
5380 13:37:53.868545 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5381 13:37:53.871672 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5382 13:37:53.874899 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5383 13:37:53.878598 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5384 13:37:53.878687
5385 13:37:53.878752
5386 13:37:53.878813 ==
5387 13:37:53.881732 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 13:37:53.888485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 13:37:53.888580 ==
5390 13:37:53.888646
5391 13:37:53.888706
5392 13:37:53.888763 TX Vref Scan disable
5393 13:37:53.891972 == TX Byte 0 ==
5394 13:37:53.895679 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5395 13:37:53.898892 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5396 13:37:53.902128 == TX Byte 1 ==
5397 13:37:53.905972 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5398 13:37:53.909150 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5399 13:37:53.912190 ==
5400 13:37:53.915431 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 13:37:53.918931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 13:37:53.919043 ==
5403 13:37:53.919151
5404 13:37:53.919245
5405 13:37:53.922473 TX Vref Scan disable
5406 13:37:53.922577 == TX Byte 0 ==
5407 13:37:53.929158 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 13:37:53.934472 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 13:37:53.934596 == TX Byte 1 ==
5410 13:37:53.938716 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5411 13:37:53.942441 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5412 13:37:53.942573
5413 13:37:53.942685 [DATLAT]
5414 13:37:53.945921 Freq=933, CH0 RK1
5415 13:37:53.946040
5416 13:37:53.946139 DATLAT Default: 0xb
5417 13:37:53.948967 0, 0xFFFF, sum = 0
5418 13:37:53.949073 1, 0xFFFF, sum = 0
5419 13:37:53.952491 2, 0xFFFF, sum = 0
5420 13:37:53.952591 3, 0xFFFF, sum = 0
5421 13:37:53.955955 4, 0xFFFF, sum = 0
5422 13:37:53.956055 5, 0xFFFF, sum = 0
5423 13:37:53.959287 6, 0xFFFF, sum = 0
5424 13:37:53.959387 7, 0xFFFF, sum = 0
5425 13:37:53.962633 8, 0xFFFF, sum = 0
5426 13:37:53.962734 9, 0xFFFF, sum = 0
5427 13:37:53.965870 10, 0x0, sum = 1
5428 13:37:53.965976 11, 0x0, sum = 2
5429 13:37:53.968996 12, 0x0, sum = 3
5430 13:37:53.969124 13, 0x0, sum = 4
5431 13:37:53.972308 best_step = 11
5432 13:37:53.972431
5433 13:37:53.972540 ==
5434 13:37:53.976056 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 13:37:53.979187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 13:37:53.979326 ==
5437 13:37:53.982217 RX Vref Scan: 0
5438 13:37:53.982323
5439 13:37:53.982415 RX Vref 0 -> 0, step: 1
5440 13:37:53.982504
5441 13:37:53.985950 RX Delay -61 -> 252, step: 4
5442 13:37:53.992207 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5443 13:37:53.995832 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5444 13:37:53.999118 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5445 13:37:54.002915 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5446 13:37:54.006131 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5447 13:37:54.009367 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5448 13:37:54.016090 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5449 13:37:54.019420 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5450 13:37:54.022368 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5451 13:37:54.026290 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5452 13:37:54.029311 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5453 13:37:54.032524 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5454 13:37:54.039118 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5455 13:37:54.042602 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5456 13:37:54.046045 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5457 13:37:54.049267 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5458 13:37:54.049386 ==
5459 13:37:54.052925 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 13:37:54.055860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 13:37:54.059518 ==
5462 13:37:54.059607 DQS Delay:
5463 13:37:54.059674 DQS0 = 0, DQS1 = 0
5464 13:37:54.062298 DQM Delay:
5465 13:37:54.062385 DQM0 = 95, DQM1 = 88
5466 13:37:54.066060 DQ Delay:
5467 13:37:54.066151 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5468 13:37:54.069505 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =104
5469 13:37:54.072952 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5470 13:37:54.075947 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =98
5471 13:37:54.079900
5472 13:37:54.079988
5473 13:37:54.085939 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5474 13:37:54.089213 CH0 RK1: MR19=505, MR18=1D0B
5475 13:37:54.095682 CH0_RK1: MR19=0x505, MR18=0x1D0B, DQSOSC=412, MR23=63, INC=63, DEC=42
5476 13:37:54.099453 [RxdqsGatingPostProcess] freq 933
5477 13:37:54.102499 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5478 13:37:54.106122 best DQS0 dly(2T, 0.5T) = (0, 11)
5479 13:37:54.109185 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 13:37:54.112949 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5481 13:37:54.116134 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 13:37:54.119247 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 13:37:54.123171 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 13:37:54.126214 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 13:37:54.129244 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 13:37:54.132901 Pre-setting of DQS Precalculation
5487 13:37:54.136008 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5488 13:37:54.136144 ==
5489 13:37:54.139345 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 13:37:54.143041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 13:37:54.146053 ==
5492 13:37:54.149772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5493 13:37:54.155959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5494 13:37:54.159307 [CA 0] Center 36 (6~67) winsize 62
5495 13:37:54.162558 [CA 1] Center 37 (7~67) winsize 61
5496 13:37:54.165967 [CA 2] Center 34 (4~64) winsize 61
5497 13:37:54.169453 [CA 3] Center 33 (3~64) winsize 62
5498 13:37:54.172885 [CA 4] Center 34 (4~64) winsize 61
5499 13:37:54.176395 [CA 5] Center 33 (3~63) winsize 61
5500 13:37:54.176503
5501 13:37:54.179269 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5502 13:37:54.179369
5503 13:37:54.182804 [CATrainingPosCal] consider 1 rank data
5504 13:37:54.186206 u2DelayCellTimex100 = 270/100 ps
5505 13:37:54.189251 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 13:37:54.193088 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5507 13:37:54.196392 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5508 13:37:54.199309 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5509 13:37:54.202677 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5510 13:37:54.209380 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5511 13:37:54.209465
5512 13:37:54.213030 CA PerBit enable=1, Macro0, CA PI delay=33
5513 13:37:54.213107
5514 13:37:54.215947 [CBTSetCACLKResult] CA Dly = 33
5515 13:37:54.216025 CS Dly: 4 (0~35)
5516 13:37:54.216088 ==
5517 13:37:54.219628 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 13:37:54.222811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 13:37:54.222889 ==
5520 13:37:54.229667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 13:37:54.235953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5522 13:37:54.239181 [CA 0] Center 36 (6~67) winsize 62
5523 13:37:54.242763 [CA 1] Center 36 (6~67) winsize 62
5524 13:37:54.246404 [CA 2] Center 33 (3~64) winsize 62
5525 13:37:54.249670 [CA 3] Center 33 (3~64) winsize 62
5526 13:37:54.252828 [CA 4] Center 34 (3~65) winsize 63
5527 13:37:54.256085 [CA 5] Center 33 (3~63) winsize 61
5528 13:37:54.256168
5529 13:37:54.259470 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5530 13:37:54.259557
5531 13:37:54.262611 [CATrainingPosCal] consider 2 rank data
5532 13:37:54.265873 u2DelayCellTimex100 = 270/100 ps
5533 13:37:54.269220 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 13:37:54.272472 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5535 13:37:54.275998 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 13:37:54.279437 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 13:37:54.282641 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 13:37:54.289403 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5539 13:37:54.289561
5540 13:37:54.292994 CA PerBit enable=1, Macro0, CA PI delay=33
5541 13:37:54.293133
5542 13:37:54.296189 [CBTSetCACLKResult] CA Dly = 33
5543 13:37:54.296326 CS Dly: 5 (0~37)
5544 13:37:54.296446
5545 13:37:54.299171 ----->DramcWriteLeveling(PI) begin...
5546 13:37:54.299304 ==
5547 13:37:54.302851 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 13:37:54.306182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 13:37:54.309232 ==
5550 13:37:54.309370 Write leveling (Byte 0): 29 => 29
5551 13:37:54.313068 Write leveling (Byte 1): 30 => 30
5552 13:37:54.316234 DramcWriteLeveling(PI) end<-----
5553 13:37:54.316366
5554 13:37:54.316487 ==
5555 13:37:54.319075 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 13:37:54.326297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 13:37:54.326426 ==
5558 13:37:54.326526 [Gating] SW mode calibration
5559 13:37:54.336367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5560 13:37:54.339643 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5561 13:37:54.342657 0 14 0 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
5562 13:37:54.349359 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 13:37:54.352457 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 13:37:54.356243 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5565 13:37:54.363130 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 13:37:54.366259 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 13:37:54.369270 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 13:37:54.376202 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 1)
5569 13:37:54.379793 0 15 0 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
5570 13:37:54.382543 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 13:37:54.389619 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 13:37:54.392990 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 13:37:54.395975 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 13:37:54.402683 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 13:37:54.406140 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 13:37:54.409567 0 15 28 | B1->B0 | 2e2e 2e2e | 0 0 | (1 1) (0 0)
5577 13:37:54.416286 1 0 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
5578 13:37:54.419585 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 13:37:54.422586 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 13:37:54.426360 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 13:37:54.432957 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 13:37:54.436036 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 13:37:54.439559 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 13:37:54.446353 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5585 13:37:54.449454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5586 13:37:54.452920 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:37:54.459370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:37:54.462922 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:37:54.466008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:37:54.472749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:37:54.476069 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 13:37:54.479646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 13:37:54.486373 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 13:37:54.489210 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:37:54.492855 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:37:54.499413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:37:54.502805 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:37:54.506467 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 13:37:54.512562 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 13:37:54.516127 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5601 13:37:54.519498 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 13:37:54.523165 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:37:54.526141 Total UI for P1: 0, mck2ui 16
5604 13:37:54.529257 best dqsien dly found for B0: ( 1, 2, 30)
5605 13:37:54.532995 Total UI for P1: 0, mck2ui 16
5606 13:37:54.536102 best dqsien dly found for B1: ( 1, 2, 30)
5607 13:37:54.539142 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5608 13:37:54.543056 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5609 13:37:54.546253
5610 13:37:54.549458 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5611 13:37:54.552615 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5612 13:37:54.556220 [Gating] SW calibration Done
5613 13:37:54.556335 ==
5614 13:37:54.559471 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 13:37:54.562523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 13:37:54.562638 ==
5617 13:37:54.562734 RX Vref Scan: 0
5618 13:37:54.566242
5619 13:37:54.566354 RX Vref 0 -> 0, step: 1
5620 13:37:54.566451
5621 13:37:54.569326 RX Delay -80 -> 252, step: 8
5622 13:37:54.572425 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5623 13:37:54.576454 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5624 13:37:54.582614 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5625 13:37:54.585801 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5626 13:37:54.589279 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5627 13:37:54.592957 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5628 13:37:54.595970 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5629 13:37:54.599688 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5630 13:37:54.606517 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5631 13:37:54.609410 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5632 13:37:54.612865 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5633 13:37:54.615854 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5634 13:37:54.619618 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5635 13:37:54.622764 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5636 13:37:54.629689 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5637 13:37:54.632633 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5638 13:37:54.632745 ==
5639 13:37:54.636444 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 13:37:54.639497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 13:37:54.639602 ==
5642 13:37:54.639694 DQS Delay:
5643 13:37:54.642778 DQS0 = 0, DQS1 = 0
5644 13:37:54.642880 DQM Delay:
5645 13:37:54.646350 DQM0 = 95, DQM1 = 89
5646 13:37:54.646450 DQ Delay:
5647 13:37:54.649278 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5648 13:37:54.652725 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5649 13:37:54.656035 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5650 13:37:54.659751 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5651 13:37:54.659855
5652 13:37:54.659947
5653 13:37:54.660035 ==
5654 13:37:54.662923 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 13:37:54.666052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 13:37:54.669261 ==
5657 13:37:54.669418
5658 13:37:54.669540
5659 13:37:54.669653 TX Vref Scan disable
5660 13:37:54.672940 == TX Byte 0 ==
5661 13:37:54.676033 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5662 13:37:54.679983 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5663 13:37:54.683178 == TX Byte 1 ==
5664 13:37:54.686207 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5665 13:37:54.689357 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5666 13:37:54.689511 ==
5667 13:37:54.693014 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 13:37:54.699138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 13:37:54.699279 ==
5670 13:37:54.699382
5671 13:37:54.699472
5672 13:37:54.702640 TX Vref Scan disable
5673 13:37:54.702745 == TX Byte 0 ==
5674 13:37:54.709478 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5675 13:37:54.712645 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5676 13:37:54.712752 == TX Byte 1 ==
5677 13:37:54.719498 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5678 13:37:54.722396 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5679 13:37:54.722510
5680 13:37:54.722609 [DATLAT]
5681 13:37:54.726212 Freq=933, CH1 RK0
5682 13:37:54.726333
5683 13:37:54.726437 DATLAT Default: 0xd
5684 13:37:54.729424 0, 0xFFFF, sum = 0
5685 13:37:54.729536 1, 0xFFFF, sum = 0
5686 13:37:54.732643 2, 0xFFFF, sum = 0
5687 13:37:54.732752 3, 0xFFFF, sum = 0
5688 13:37:54.736315 4, 0xFFFF, sum = 0
5689 13:37:54.736428 5, 0xFFFF, sum = 0
5690 13:37:54.739141 6, 0xFFFF, sum = 0
5691 13:37:54.739226 7, 0xFFFF, sum = 0
5692 13:37:54.742487 8, 0xFFFF, sum = 0
5693 13:37:54.742619 9, 0xFFFF, sum = 0
5694 13:37:54.746277 10, 0x0, sum = 1
5695 13:37:54.746367 11, 0x0, sum = 2
5696 13:37:54.749249 12, 0x0, sum = 3
5697 13:37:54.749344 13, 0x0, sum = 4
5698 13:37:54.752384 best_step = 11
5699 13:37:54.752494
5700 13:37:54.752589 ==
5701 13:37:54.756010 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 13:37:54.759472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 13:37:54.759599 ==
5704 13:37:54.762417 RX Vref Scan: 1
5705 13:37:54.762528
5706 13:37:54.762626 RX Vref 0 -> 0, step: 1
5707 13:37:54.762717
5708 13:37:54.766118 RX Delay -61 -> 252, step: 4
5709 13:37:54.766230
5710 13:37:54.769364 Set Vref, RX VrefLevel [Byte0]: 56
5711 13:37:54.773098 [Byte1]: 51
5712 13:37:54.776137
5713 13:37:54.776241 Final RX Vref Byte 0 = 56 to rank0
5714 13:37:54.779982 Final RX Vref Byte 1 = 51 to rank0
5715 13:37:54.782950 Final RX Vref Byte 0 = 56 to rank1
5716 13:37:54.786667 Final RX Vref Byte 1 = 51 to rank1==
5717 13:37:54.789779 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 13:37:54.796586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 13:37:54.796797 ==
5720 13:37:54.796936 DQS Delay:
5721 13:37:54.797076 DQS0 = 0, DQS1 = 0
5722 13:37:54.799774 DQM Delay:
5723 13:37:54.799938 DQM0 = 97, DQM1 = 90
5724 13:37:54.802862 DQ Delay:
5725 13:37:54.806393 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5726 13:37:54.809963 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5727 13:37:54.812748 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5728 13:37:54.816463 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5729 13:37:54.816634
5730 13:37:54.816765
5731 13:37:54.823072 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5732 13:37:54.826313 CH1 RK0: MR19=504, MR18=13F0
5733 13:37:54.832870 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5734 13:37:54.833067
5735 13:37:54.836224 ----->DramcWriteLeveling(PI) begin...
5736 13:37:54.836367 ==
5737 13:37:54.839977 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 13:37:54.843154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 13:37:54.843321 ==
5740 13:37:54.846188 Write leveling (Byte 0): 27 => 27
5741 13:37:54.849636 Write leveling (Byte 1): 28 => 28
5742 13:37:54.852997 DramcWriteLeveling(PI) end<-----
5743 13:37:54.853122
5744 13:37:54.853216 ==
5745 13:37:54.856504 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 13:37:54.860102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 13:37:54.860209 ==
5748 13:37:54.863137 [Gating] SW mode calibration
5749 13:37:54.870081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5750 13:37:54.876716 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5751 13:37:54.879941 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 13:37:54.882900 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5753 13:37:54.889888 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 13:37:54.893092 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 13:37:54.896630 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 13:37:54.903592 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5757 13:37:54.906658 0 14 24 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
5758 13:37:54.909723 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5759 13:37:54.916712 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 13:37:54.919714 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 13:37:54.923662 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 13:37:54.929686 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 13:37:54.933235 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 13:37:54.936187 0 15 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5765 13:37:54.942976 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (0 0) (1 1)
5766 13:37:54.946708 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (1 1) (0 0)
5767 13:37:54.950132 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 13:37:54.953147 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 13:37:54.959897 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 13:37:54.963531 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 13:37:54.966887 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 13:37:54.973492 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5773 13:37:54.976515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5774 13:37:54.980221 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:37:54.986929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:37:54.989854 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:37:54.993716 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:37:55.000460 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:37:55.003441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 13:37:55.006622 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 13:37:55.013328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 13:37:55.016868 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 13:37:55.019907 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 13:37:55.023336 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 13:37:55.030061 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 13:37:55.033247 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 13:37:55.036986 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 13:37:55.043402 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 13:37:55.046527 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5790 13:37:55.049678 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:37:55.053543 Total UI for P1: 0, mck2ui 16
5792 13:37:55.056481 best dqsien dly found for B0: ( 1, 2, 24)
5793 13:37:55.060194 Total UI for P1: 0, mck2ui 16
5794 13:37:55.063325 best dqsien dly found for B1: ( 1, 2, 26)
5795 13:37:55.066528 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5796 13:37:55.070170 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5797 13:37:55.070300
5798 13:37:55.076786 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 13:37:55.079826 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5800 13:37:55.079941 [Gating] SW calibration Done
5801 13:37:55.083431 ==
5802 13:37:55.086466 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 13:37:55.089914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 13:37:55.090014 ==
5805 13:37:55.090105 RX Vref Scan: 0
5806 13:37:55.090207
5807 13:37:55.093160 RX Vref 0 -> 0, step: 1
5808 13:37:55.093274
5809 13:37:55.096605 RX Delay -80 -> 252, step: 8
5810 13:37:55.099785 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5811 13:37:55.103731 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5812 13:37:55.106744 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5813 13:37:55.113609 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5814 13:37:55.116618 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5815 13:37:55.120393 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5816 13:37:55.123416 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5817 13:37:55.126460 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5818 13:37:55.130046 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5819 13:37:55.136506 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5820 13:37:55.140265 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5821 13:37:55.143193 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5822 13:37:55.146594 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5823 13:37:55.150221 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5824 13:37:55.153227 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5825 13:37:55.160111 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5826 13:37:55.160218 ==
5827 13:37:55.163199 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 13:37:55.166396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 13:37:55.166514 ==
5830 13:37:55.166612 DQS Delay:
5831 13:37:55.169649 DQS0 = 0, DQS1 = 0
5832 13:37:55.169734 DQM Delay:
5833 13:37:55.173426 DQM0 = 93, DQM1 = 88
5834 13:37:55.173522 DQ Delay:
5835 13:37:55.176547 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5836 13:37:55.179623 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5837 13:37:55.183436 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5838 13:37:55.186322 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5839 13:37:55.186451
5840 13:37:55.186544
5841 13:37:55.186649 ==
5842 13:37:55.189917 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 13:37:55.193108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 13:37:55.193242 ==
5845 13:37:55.196649
5846 13:37:55.196786
5847 13:37:55.196888 TX Vref Scan disable
5848 13:37:55.200202 == TX Byte 0 ==
5849 13:37:55.203576 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5850 13:37:55.206362 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5851 13:37:55.209652 == TX Byte 1 ==
5852 13:37:55.213339 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5853 13:37:55.216551 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5854 13:37:55.216690 ==
5855 13:37:55.220112 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 13:37:55.226228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 13:37:55.226358 ==
5858 13:37:55.226471
5859 13:37:55.226549
5860 13:37:55.226637 TX Vref Scan disable
5861 13:37:55.230434 == TX Byte 0 ==
5862 13:37:55.234245 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 13:37:55.240788 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 13:37:55.240946 == TX Byte 1 ==
5865 13:37:55.243853 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5866 13:37:55.250663 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5867 13:37:55.250792
5868 13:37:55.250863 [DATLAT]
5869 13:37:55.250928 Freq=933, CH1 RK1
5870 13:37:55.250987
5871 13:37:55.253709 DATLAT Default: 0xb
5872 13:37:55.253796 0, 0xFFFF, sum = 0
5873 13:37:55.257254 1, 0xFFFF, sum = 0
5874 13:37:55.257366 2, 0xFFFF, sum = 0
5875 13:37:55.261014 3, 0xFFFF, sum = 0
5876 13:37:55.261108 4, 0xFFFF, sum = 0
5877 13:37:55.264262 5, 0xFFFF, sum = 0
5878 13:37:55.264357 6, 0xFFFF, sum = 0
5879 13:37:55.267350 7, 0xFFFF, sum = 0
5880 13:37:55.270525 8, 0xFFFF, sum = 0
5881 13:37:55.270612 9, 0xFFFF, sum = 0
5882 13:37:55.273768 10, 0x0, sum = 1
5883 13:37:55.273844 11, 0x0, sum = 2
5884 13:37:55.273907 12, 0x0, sum = 3
5885 13:37:55.277443 13, 0x0, sum = 4
5886 13:37:55.277517 best_step = 11
5887 13:37:55.277577
5888 13:37:55.277638 ==
5889 13:37:55.280640 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 13:37:55.287558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 13:37:55.287638 ==
5892 13:37:55.287700 RX Vref Scan: 0
5893 13:37:55.287759
5894 13:37:55.290750 RX Vref 0 -> 0, step: 1
5895 13:37:55.290820
5896 13:37:55.293850 RX Delay -61 -> 252, step: 4
5897 13:37:55.297573 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5898 13:37:55.300417 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5899 13:37:55.307654 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5900 13:37:55.310929 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5901 13:37:55.313957 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5902 13:37:55.317226 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5903 13:37:55.321137 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5904 13:37:55.324150 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5905 13:37:55.331041 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5906 13:37:55.334205 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5907 13:37:55.337923 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5908 13:37:55.341065 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5909 13:37:55.344105 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5910 13:37:55.350818 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5911 13:37:55.354369 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5912 13:37:55.357444 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5913 13:37:55.357533 ==
5914 13:37:55.361080 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 13:37:55.378821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 13:37:55.379045 ==
5917 13:37:55.379158 DQS Delay:
5918 13:37:55.379251 DQS0 = 0, DQS1 = 0
5919 13:37:55.379350 DQM Delay:
5920 13:37:55.379448 DQM0 = 95, DQM1 = 90
5921 13:37:55.379546 DQ Delay:
5922 13:37:55.379644 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5923 13:37:55.379740 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =92
5924 13:37:55.380855 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =84
5925 13:37:55.384028 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =96
5926 13:37:55.384115
5927 13:37:55.384201
5928 13:37:55.394237 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5929 13:37:55.398071 CH1 RK1: MR19=505, MR18=111A
5930 13:37:55.400659 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
5931 13:37:55.404343 [RxdqsGatingPostProcess] freq 933
5932 13:37:55.411217 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 13:37:55.414197 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 13:37:55.417884 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 13:37:55.420787 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 13:37:55.424292 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 13:37:55.427594 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 13:37:55.430790 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 13:37:55.434393 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 13:37:55.434557 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 13:37:55.437691 Pre-setting of DQS Precalculation
5942 13:37:55.444508 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 13:37:55.451263 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 13:37:55.457271 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 13:37:55.457403
5946 13:37:55.457471
5947 13:37:55.460865 [Calibration Summary] 1866 Mbps
5948 13:37:55.464044 CH 0, Rank 0
5949 13:37:55.464135 SW Impedance : PASS
5950 13:37:55.467660 DUTY Scan : NO K
5951 13:37:55.470915 ZQ Calibration : PASS
5952 13:37:55.471011 Jitter Meter : NO K
5953 13:37:55.474125 CBT Training : PASS
5954 13:37:55.474212 Write leveling : PASS
5955 13:37:55.477318 RX DQS gating : PASS
5956 13:37:55.481001 RX DQ/DQS(RDDQC) : PASS
5957 13:37:55.481093 TX DQ/DQS : PASS
5958 13:37:55.484188 RX DATLAT : PASS
5959 13:37:55.487252 RX DQ/DQS(Engine): PASS
5960 13:37:55.487373 TX OE : NO K
5961 13:37:55.491031 All Pass.
5962 13:37:55.491166
5963 13:37:55.491265 CH 0, Rank 1
5964 13:37:55.494211 SW Impedance : PASS
5965 13:37:55.494318 DUTY Scan : NO K
5966 13:37:55.497557 ZQ Calibration : PASS
5967 13:37:55.500757 Jitter Meter : NO K
5968 13:37:55.500886 CBT Training : PASS
5969 13:37:55.504492 Write leveling : PASS
5970 13:37:55.507708 RX DQS gating : PASS
5971 13:37:55.507816 RX DQ/DQS(RDDQC) : PASS
5972 13:37:55.510739 TX DQ/DQS : PASS
5973 13:37:55.510836 RX DATLAT : PASS
5974 13:37:55.513908 RX DQ/DQS(Engine): PASS
5975 13:37:55.517719 TX OE : NO K
5976 13:37:55.517810 All Pass.
5977 13:37:55.517877
5978 13:37:55.517939 CH 1, Rank 0
5979 13:37:55.520641 SW Impedance : PASS
5980 13:37:55.524151 DUTY Scan : NO K
5981 13:37:55.524267 ZQ Calibration : PASS
5982 13:37:55.527486 Jitter Meter : NO K
5983 13:37:55.530508 CBT Training : PASS
5984 13:37:55.530637 Write leveling : PASS
5985 13:37:55.534149 RX DQS gating : PASS
5986 13:37:55.537596 RX DQ/DQS(RDDQC) : PASS
5987 13:37:55.537686 TX DQ/DQS : PASS
5988 13:37:55.540588 RX DATLAT : PASS
5989 13:37:55.544433 RX DQ/DQS(Engine): PASS
5990 13:37:55.544520 TX OE : NO K
5991 13:37:55.547300 All Pass.
5992 13:37:55.547385
5993 13:37:55.547451 CH 1, Rank 1
5994 13:37:55.550932 SW Impedance : PASS
5995 13:37:55.551020 DUTY Scan : NO K
5996 13:37:55.553878 ZQ Calibration : PASS
5997 13:37:55.557220 Jitter Meter : NO K
5998 13:37:55.557315 CBT Training : PASS
5999 13:37:55.561135 Write leveling : PASS
6000 13:37:55.561271 RX DQS gating : PASS
6001 13:37:55.564274 RX DQ/DQS(RDDQC) : PASS
6002 13:37:55.567482 TX DQ/DQS : PASS
6003 13:37:55.567644 RX DATLAT : PASS
6004 13:37:55.570665 RX DQ/DQS(Engine): PASS
6005 13:37:55.574296 TX OE : NO K
6006 13:37:55.574434 All Pass.
6007 13:37:55.574534
6008 13:37:55.577638 DramC Write-DBI off
6009 13:37:55.577754 PER_BANK_REFRESH: Hybrid Mode
6010 13:37:55.580909 TX_TRACKING: ON
6011 13:37:55.587450 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 13:37:55.594322 [FAST_K] Save calibration result to emmc
6013 13:37:55.597492 dramc_set_vcore_voltage set vcore to 650000
6014 13:37:55.597616 Read voltage for 400, 6
6015 13:37:55.600658 Vio18 = 0
6016 13:37:55.600768 Vcore = 650000
6017 13:37:55.600863 Vdram = 0
6018 13:37:55.604602 Vddq = 0
6019 13:37:55.604712 Vmddr = 0
6020 13:37:55.607675 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 13:37:55.614292 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 13:37:55.617536 MEM_TYPE=3, freq_sel=20
6023 13:37:55.620739 sv_algorithm_assistance_LP4_800
6024 13:37:55.623863 ============ PULL DRAM RESETB DOWN ============
6025 13:37:55.627124 ========== PULL DRAM RESETB DOWN end =========
6026 13:37:55.630775 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 13:37:55.634131 ===================================
6028 13:37:55.637478 LPDDR4 DRAM CONFIGURATION
6029 13:37:55.640914 ===================================
6030 13:37:55.643889 EX_ROW_EN[0] = 0x0
6031 13:37:55.644002 EX_ROW_EN[1] = 0x0
6032 13:37:55.647635 LP4Y_EN = 0x0
6033 13:37:55.647745 WORK_FSP = 0x0
6034 13:37:55.650763 WL = 0x2
6035 13:37:55.650873 RL = 0x2
6036 13:37:55.653878 BL = 0x2
6037 13:37:55.653988 RPST = 0x0
6038 13:37:55.657626 RD_PRE = 0x0
6039 13:37:55.657736 WR_PRE = 0x1
6040 13:37:55.660662 WR_PST = 0x0
6041 13:37:55.660770 DBI_WR = 0x0
6042 13:37:55.664345 DBI_RD = 0x0
6043 13:37:55.667270 OTF = 0x1
6044 13:37:55.667384 ===================================
6045 13:37:55.671020 ===================================
6046 13:37:55.674311 ANA top config
6047 13:37:55.677687 ===================================
6048 13:37:55.681007 DLL_ASYNC_EN = 0
6049 13:37:55.681119 ALL_SLAVE_EN = 1
6050 13:37:55.683946 NEW_RANK_MODE = 1
6051 13:37:55.687241 DLL_IDLE_MODE = 1
6052 13:37:55.690849 LP45_APHY_COMB_EN = 1
6053 13:37:55.694140 TX_ODT_DIS = 1
6054 13:37:55.694252 NEW_8X_MODE = 1
6055 13:37:55.697601 ===================================
6056 13:37:55.700679 ===================================
6057 13:37:55.703859 data_rate = 800
6058 13:37:55.707666 CKR = 1
6059 13:37:55.710714 DQ_P2S_RATIO = 4
6060 13:37:55.713895 ===================================
6061 13:37:55.717604 CA_P2S_RATIO = 4
6062 13:37:55.717737 DQ_CA_OPEN = 0
6063 13:37:55.720705 DQ_SEMI_OPEN = 1
6064 13:37:55.723951 CA_SEMI_OPEN = 1
6065 13:37:55.727698 CA_FULL_RATE = 0
6066 13:37:55.730921 DQ_CKDIV4_EN = 0
6067 13:37:55.734203 CA_CKDIV4_EN = 1
6068 13:37:55.734330 CA_PREDIV_EN = 0
6069 13:37:55.737349 PH8_DLY = 0
6070 13:37:55.740933 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 13:37:55.744127 DQ_AAMCK_DIV = 0
6072 13:37:55.747565 CA_AAMCK_DIV = 0
6073 13:37:55.750958 CA_ADMCK_DIV = 4
6074 13:37:55.751097 DQ_TRACK_CA_EN = 0
6075 13:37:55.754102 CA_PICK = 800
6076 13:37:55.757717 CA_MCKIO = 400
6077 13:37:55.760786 MCKIO_SEMI = 400
6078 13:37:55.764483 PLL_FREQ = 3016
6079 13:37:55.767366 DQ_UI_PI_RATIO = 32
6080 13:37:55.771108 CA_UI_PI_RATIO = 32
6081 13:37:55.774209 ===================================
6082 13:37:55.777386 ===================================
6083 13:37:55.777499 memory_type:LPDDR4
6084 13:37:55.781141 GP_NUM : 10
6085 13:37:55.781254 SRAM_EN : 1
6086 13:37:55.784093 MD32_EN : 0
6087 13:37:55.787702 ===================================
6088 13:37:55.791193 [ANA_INIT] >>>>>>>>>>>>>>
6089 13:37:55.794281 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 13:37:55.797330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 13:37:55.800846 ===================================
6092 13:37:55.800958 data_rate = 800,PCW = 0X7400
6093 13:37:55.804433 ===================================
6094 13:37:55.807985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 13:37:55.814487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 13:37:55.827544 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 13:37:55.830645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 13:37:55.834391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 13:37:55.837502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 13:37:55.840595 [ANA_INIT] flow start
6101 13:37:55.840707 [ANA_INIT] PLL >>>>>>>>
6102 13:37:55.844396 [ANA_INIT] PLL <<<<<<<<
6103 13:37:55.847483 [ANA_INIT] MIDPI >>>>>>>>
6104 13:37:55.847596 [ANA_INIT] MIDPI <<<<<<<<
6105 13:37:55.850577 [ANA_INIT] DLL >>>>>>>>
6106 13:37:55.854500 [ANA_INIT] flow end
6107 13:37:55.857544 ============ LP4 DIFF to SE enter ============
6108 13:37:55.861123 ============ LP4 DIFF to SE exit ============
6109 13:37:55.863895 [ANA_INIT] <<<<<<<<<<<<<
6110 13:37:55.867850 [Flow] Enable top DCM control >>>>>
6111 13:37:55.871052 [Flow] Enable top DCM control <<<<<
6112 13:37:55.874318 Enable DLL master slave shuffle
6113 13:37:55.877824 ==============================================================
6114 13:37:55.880759 Gating Mode config
6115 13:37:55.887466 ==============================================================
6116 13:37:55.887593 Config description:
6117 13:37:55.897681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 13:37:55.904155 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 13:37:55.907753 SELPH_MODE 0: By rank 1: By Phase
6120 13:37:55.914140 ==============================================================
6121 13:37:55.917522 GAT_TRACK_EN = 0
6122 13:37:55.920658 RX_GATING_MODE = 2
6123 13:37:55.924168 RX_GATING_TRACK_MODE = 2
6124 13:37:55.927685 SELPH_MODE = 1
6125 13:37:55.930801 PICG_EARLY_EN = 1
6126 13:37:55.934603 VALID_LAT_VALUE = 1
6127 13:37:55.937739 ==============================================================
6128 13:37:55.941022 Enter into Gating configuration >>>>
6129 13:37:55.944870 Exit from Gating configuration <<<<
6130 13:37:55.947791 Enter into DVFS_PRE_config >>>>>
6131 13:37:55.957760 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 13:37:55.961047 Exit from DVFS_PRE_config <<<<<
6133 13:37:55.964136 Enter into PICG configuration >>>>
6134 13:37:55.967836 Exit from PICG configuration <<<<
6135 13:37:55.971060 [RX_INPUT] configuration >>>>>
6136 13:37:55.974254 [RX_INPUT] configuration <<<<<
6137 13:37:55.977765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 13:37:55.984469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 13:37:55.990953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 13:37:55.997278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 13:37:56.004227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 13:37:56.010687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 13:37:56.014388 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 13:37:56.017586 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 13:37:56.020770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 13:37:56.027648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 13:37:56.030901 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 13:37:56.034174 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 13:37:56.037720 ===================================
6150 13:37:56.040556 LPDDR4 DRAM CONFIGURATION
6151 13:37:56.044498 ===================================
6152 13:37:56.044631 EX_ROW_EN[0] = 0x0
6153 13:37:56.047640 EX_ROW_EN[1] = 0x0
6154 13:37:56.047723 LP4Y_EN = 0x0
6155 13:37:56.050727 WORK_FSP = 0x0
6156 13:37:56.053753 WL = 0x2
6157 13:37:56.053868 RL = 0x2
6158 13:37:56.057344 BL = 0x2
6159 13:37:56.057455 RPST = 0x0
6160 13:37:56.060478 RD_PRE = 0x0
6161 13:37:56.060586 WR_PRE = 0x1
6162 13:37:56.064203 WR_PST = 0x0
6163 13:37:56.064316 DBI_WR = 0x0
6164 13:37:56.067266 DBI_RD = 0x0
6165 13:37:56.067375 OTF = 0x1
6166 13:37:56.070431 ===================================
6167 13:37:56.073654 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 13:37:56.080455 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 13:37:56.083564 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 13:37:56.087433 ===================================
6171 13:37:56.090602 LPDDR4 DRAM CONFIGURATION
6172 13:37:56.093770 ===================================
6173 13:37:56.093882 EX_ROW_EN[0] = 0x10
6174 13:37:56.097357 EX_ROW_EN[1] = 0x0
6175 13:37:56.097466 LP4Y_EN = 0x0
6176 13:37:56.100823 WORK_FSP = 0x0
6177 13:37:56.100931 WL = 0x2
6178 13:37:56.103773 RL = 0x2
6179 13:37:56.103879 BL = 0x2
6180 13:37:56.107531 RPST = 0x0
6181 13:37:56.107657 RD_PRE = 0x0
6182 13:37:56.110620 WR_PRE = 0x1
6183 13:37:56.110727 WR_PST = 0x0
6184 13:37:56.113933 DBI_WR = 0x0
6185 13:37:56.114041 DBI_RD = 0x0
6186 13:37:56.117378 OTF = 0x1
6187 13:37:56.120522 ===================================
6188 13:37:56.127476 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 13:37:56.130648 nWR fixed to 30
6190 13:37:56.133823 [ModeRegInit_LP4] CH0 RK0
6191 13:37:56.133948 [ModeRegInit_LP4] CH0 RK1
6192 13:37:56.137478 [ModeRegInit_LP4] CH1 RK0
6193 13:37:56.140397 [ModeRegInit_LP4] CH1 RK1
6194 13:37:56.140509 match AC timing 19
6195 13:37:56.147149 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 13:37:56.150459 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 13:37:56.154091 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 13:37:56.160870 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 13:37:56.164185 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 13:37:56.164299 ==
6201 13:37:56.167209 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 13:37:56.170534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 13:37:56.170672 ==
6204 13:37:56.177398 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 13:37:56.184193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6206 13:37:56.187251 [CA 0] Center 36 (8~64) winsize 57
6207 13:37:56.190359 [CA 1] Center 36 (8~64) winsize 57
6208 13:37:56.190483 [CA 2] Center 36 (8~64) winsize 57
6209 13:37:56.194185 [CA 3] Center 36 (8~64) winsize 57
6210 13:37:56.197485 [CA 4] Center 36 (8~64) winsize 57
6211 13:37:56.200656 [CA 5] Center 36 (8~64) winsize 57
6212 13:37:56.200797
6213 13:37:56.204254 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6214 13:37:56.204402
6215 13:37:56.210657 [CATrainingPosCal] consider 1 rank data
6216 13:37:56.210824 u2DelayCellTimex100 = 270/100 ps
6217 13:37:56.217514 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 13:37:56.220338 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 13:37:56.223875 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 13:37:56.227205 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 13:37:56.230670 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 13:37:56.234022 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 13:37:56.234163
6224 13:37:56.237153 CA PerBit enable=1, Macro0, CA PI delay=36
6225 13:37:56.237304
6226 13:37:56.240925 [CBTSetCACLKResult] CA Dly = 36
6227 13:37:56.241056 CS Dly: 1 (0~32)
6228 13:37:56.244125 ==
6229 13:37:56.247645 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 13:37:56.250615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 13:37:56.250739 ==
6232 13:37:56.254282 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 13:37:56.260541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 13:37:56.264123 [CA 0] Center 36 (8~64) winsize 57
6235 13:37:56.267134 [CA 1] Center 36 (8~64) winsize 57
6236 13:37:56.270899 [CA 2] Center 36 (8~64) winsize 57
6237 13:37:56.274003 [CA 3] Center 36 (8~64) winsize 57
6238 13:37:56.277231 [CA 4] Center 36 (8~64) winsize 57
6239 13:37:56.281188 [CA 5] Center 36 (8~64) winsize 57
6240 13:37:56.281319
6241 13:37:56.284042 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 13:37:56.284156
6243 13:37:56.287838 [CATrainingPosCal] consider 2 rank data
6244 13:37:56.290953 u2DelayCellTimex100 = 270/100 ps
6245 13:37:56.294118 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 13:37:56.297467 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 13:37:56.300587 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 13:37:56.304515 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 13:37:56.307520 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 13:37:56.314227 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 13:37:56.314397
6252 13:37:56.317680 CA PerBit enable=1, Macro0, CA PI delay=36
6253 13:37:56.317834
6254 13:37:56.320696 [CBTSetCACLKResult] CA Dly = 36
6255 13:37:56.320805 CS Dly: 1 (0~32)
6256 13:37:56.320898
6257 13:37:56.323924 ----->DramcWriteLeveling(PI) begin...
6258 13:37:56.324019 ==
6259 13:37:56.327701 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 13:37:56.330726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 13:37:56.334381 ==
6262 13:37:56.334504 Write leveling (Byte 0): 40 => 8
6263 13:37:56.337344 Write leveling (Byte 1): 32 => 0
6264 13:37:56.341124 DramcWriteLeveling(PI) end<-----
6265 13:37:56.341250
6266 13:37:56.341347 ==
6267 13:37:56.344050 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 13:37:56.350849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 13:37:56.350986 ==
6270 13:37:56.351089 [Gating] SW mode calibration
6271 13:37:56.360640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 13:37:56.364134 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 13:37:56.367618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 13:37:56.374382 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 13:37:56.377667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 13:37:56.381144 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 13:37:56.387389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 13:37:56.391113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 13:37:56.394209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 13:37:56.401164 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 13:37:56.404256 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 13:37:56.407418 Total UI for P1: 0, mck2ui 16
6283 13:37:56.411117 best dqsien dly found for B0: ( 0, 14, 24)
6284 13:37:56.414412 Total UI for P1: 0, mck2ui 16
6285 13:37:56.417485 best dqsien dly found for B1: ( 0, 14, 24)
6286 13:37:56.421306 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 13:37:56.424441 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 13:37:56.424557
6289 13:37:56.427526 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 13:37:56.431413 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 13:37:56.434443 [Gating] SW calibration Done
6292 13:37:56.434555 ==
6293 13:37:56.437901 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 13:37:56.441061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 13:37:56.441184 ==
6296 13:37:56.444864 RX Vref Scan: 0
6297 13:37:56.444980
6298 13:37:56.447732 RX Vref 0 -> 0, step: 1
6299 13:37:56.447842
6300 13:37:56.447937 RX Delay -410 -> 252, step: 16
6301 13:37:56.454357 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6302 13:37:56.458219 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6303 13:37:56.461073 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6304 13:37:56.464573 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6305 13:37:56.471194 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6306 13:37:56.474288 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6307 13:37:56.477942 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6308 13:37:56.480910 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6309 13:37:56.487480 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6310 13:37:56.491072 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6311 13:37:56.494358 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6312 13:37:56.498020 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6313 13:37:56.504791 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6314 13:37:56.507905 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6315 13:37:56.511111 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6316 13:37:56.517917 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6317 13:37:56.518037 ==
6318 13:37:56.521268 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 13:37:56.524291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 13:37:56.524399 ==
6321 13:37:56.524490 DQS Delay:
6322 13:37:56.528101 DQS0 = 35, DQS1 = 51
6323 13:37:56.528211 DQM Delay:
6324 13:37:56.531350 DQM0 = 7, DQM1 = 10
6325 13:37:56.531462 DQ Delay:
6326 13:37:56.534415 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6327 13:37:56.537494 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6328 13:37:56.541167 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6329 13:37:56.544370 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6330 13:37:56.544456
6331 13:37:56.544521
6332 13:37:56.544583 ==
6333 13:37:56.548051 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 13:37:56.551161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 13:37:56.551268 ==
6336 13:37:56.551356
6337 13:37:56.551441
6338 13:37:56.554696 TX Vref Scan disable
6339 13:37:56.554796 == TX Byte 0 ==
6340 13:37:56.561230 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 13:37:56.564512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 13:37:56.564615 == TX Byte 1 ==
6343 13:37:56.571167 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6344 13:37:56.574480 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6345 13:37:56.574593 ==
6346 13:37:56.577538 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 13:37:56.581342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 13:37:56.581455 ==
6349 13:37:56.581550
6350 13:37:56.581642
6351 13:37:56.584283 TX Vref Scan disable
6352 13:37:56.584389 == TX Byte 0 ==
6353 13:37:56.591127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 13:37:56.594639 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 13:37:56.594753 == TX Byte 1 ==
6356 13:37:56.600832 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 13:37:56.604326 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 13:37:56.604434
6359 13:37:56.604525 [DATLAT]
6360 13:37:56.607559 Freq=400, CH0 RK0
6361 13:37:56.607668
6362 13:37:56.607761 DATLAT Default: 0xf
6363 13:37:56.611254 0, 0xFFFF, sum = 0
6364 13:37:56.611341 1, 0xFFFF, sum = 0
6365 13:37:56.614371 2, 0xFFFF, sum = 0
6366 13:37:56.614468 3, 0xFFFF, sum = 0
6367 13:37:56.617577 4, 0xFFFF, sum = 0
6368 13:37:56.617662 5, 0xFFFF, sum = 0
6369 13:37:56.620880 6, 0xFFFF, sum = 0
6370 13:37:56.620963 7, 0xFFFF, sum = 0
6371 13:37:56.624527 8, 0xFFFF, sum = 0
6372 13:37:56.624612 9, 0xFFFF, sum = 0
6373 13:37:56.627540 10, 0xFFFF, sum = 0
6374 13:37:56.631268 11, 0xFFFF, sum = 0
6375 13:37:56.631364 12, 0xFFFF, sum = 0
6376 13:37:56.634267 13, 0x0, sum = 1
6377 13:37:56.634352 14, 0x0, sum = 2
6378 13:37:56.634419 15, 0x0, sum = 3
6379 13:37:56.638145 16, 0x0, sum = 4
6380 13:37:56.638252 best_step = 14
6381 13:37:56.638344
6382 13:37:56.638431 ==
6383 13:37:56.641312 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 13:37:56.647944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 13:37:56.648055 ==
6386 13:37:56.648148 RX Vref Scan: 1
6387 13:37:56.648237
6388 13:37:56.651140 RX Vref 0 -> 0, step: 1
6389 13:37:56.651245
6390 13:37:56.654810 RX Delay -343 -> 252, step: 8
6391 13:37:56.654916
6392 13:37:56.657749 Set Vref, RX VrefLevel [Byte0]: 54
6393 13:37:56.661287 [Byte1]: 53
6394 13:37:56.664386
6395 13:37:56.664490 Final RX Vref Byte 0 = 54 to rank0
6396 13:37:56.667941 Final RX Vref Byte 1 = 53 to rank0
6397 13:37:56.671077 Final RX Vref Byte 0 = 54 to rank1
6398 13:37:56.674100 Final RX Vref Byte 1 = 53 to rank1==
6399 13:37:56.677810 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 13:37:56.684281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 13:37:56.684405 ==
6402 13:37:56.684500 DQS Delay:
6403 13:37:56.687918 DQS0 = 44, DQS1 = 60
6404 13:37:56.688025 DQM Delay:
6405 13:37:56.688117 DQM0 = 11, DQM1 = 14
6406 13:37:56.691087 DQ Delay:
6407 13:37:56.694282 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6408 13:37:56.694366 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6409 13:37:56.698108 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6410 13:37:56.701263 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6411 13:37:56.701346
6412 13:37:56.704331
6413 13:37:56.710976 [DQSOSCAuto] RK0, (LSB)MR18= 0x8856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6414 13:37:56.714603 CH0 RK0: MR19=C0C, MR18=8856
6415 13:37:56.721311 CH0_RK0: MR19=0xC0C, MR18=0x8856, DQSOSC=392, MR23=63, INC=384, DEC=256
6416 13:37:56.721404 ==
6417 13:37:56.724459 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 13:37:56.727539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 13:37:56.727621 ==
6420 13:37:56.730756 [Gating] SW mode calibration
6421 13:37:56.737795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 13:37:56.744640 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 13:37:56.747743 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 13:37:56.751437 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 13:37:56.754376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 13:37:56.761304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 13:37:56.764886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 13:37:56.767865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 13:37:56.774193 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 13:37:56.777957 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 13:37:56.780772 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 13:37:56.784458 Total UI for P1: 0, mck2ui 16
6433 13:37:56.788113 best dqsien dly found for B0: ( 0, 14, 24)
6434 13:37:56.791111 Total UI for P1: 0, mck2ui 16
6435 13:37:56.794597 best dqsien dly found for B1: ( 0, 14, 24)
6436 13:37:56.797720 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 13:37:56.800945 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 13:37:56.801059
6439 13:37:56.808025 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 13:37:56.810899 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 13:37:56.810985 [Gating] SW calibration Done
6442 13:37:56.814503 ==
6443 13:37:56.817623 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 13:37:56.821127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 13:37:56.821210 ==
6446 13:37:56.821287 RX Vref Scan: 0
6447 13:37:56.821349
6448 13:37:56.824591 RX Vref 0 -> 0, step: 1
6449 13:37:56.824672
6450 13:37:56.828179 RX Delay -410 -> 252, step: 16
6451 13:37:56.831274 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6452 13:37:56.834465 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6453 13:37:56.841316 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6454 13:37:56.844465 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6455 13:37:56.848154 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6456 13:37:56.851289 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6457 13:37:56.858175 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6458 13:37:56.861472 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6459 13:37:56.864998 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6460 13:37:56.868270 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6461 13:37:56.875363 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6462 13:37:56.878212 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6463 13:37:56.881300 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6464 13:37:56.884528 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6465 13:37:56.891370 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6466 13:37:56.894838 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6467 13:37:56.894926 ==
6468 13:37:56.898412 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 13:37:56.901244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 13:37:56.901330 ==
6471 13:37:56.904844 DQS Delay:
6472 13:37:56.904970 DQS0 = 35, DQS1 = 51
6473 13:37:56.908034 DQM Delay:
6474 13:37:56.908112 DQM0 = 4, DQM1 = 10
6475 13:37:56.908176 DQ Delay:
6476 13:37:56.911164 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6477 13:37:56.914369 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6478 13:37:56.917975 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6479 13:37:56.921061 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6480 13:37:56.921147
6481 13:37:56.921214
6482 13:37:56.921275 ==
6483 13:37:56.924788 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 13:37:56.928207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 13:37:56.931325 ==
6486 13:37:56.931440
6487 13:37:56.931534
6488 13:37:56.931625 TX Vref Scan disable
6489 13:37:56.934765 == TX Byte 0 ==
6490 13:37:56.937938 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 13:37:56.941491 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 13:37:56.944624 == TX Byte 1 ==
6493 13:37:56.947781 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6494 13:37:56.951641 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6495 13:37:56.951724 ==
6496 13:37:56.954658 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 13:37:56.958260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 13:37:56.961431 ==
6499 13:37:56.961513
6500 13:37:56.961577
6501 13:37:56.961637 TX Vref Scan disable
6502 13:37:56.964550 == TX Byte 0 ==
6503 13:37:56.967808 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 13:37:56.971477 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 13:37:56.974530 == TX Byte 1 ==
6506 13:37:56.978263 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6507 13:37:56.981474 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6508 13:37:56.981557
6509 13:37:56.981621 [DATLAT]
6510 13:37:56.984538 Freq=400, CH0 RK1
6511 13:37:56.984621
6512 13:37:56.984717 DATLAT Default: 0xe
6513 13:37:56.988381 0, 0xFFFF, sum = 0
6514 13:37:56.991563 1, 0xFFFF, sum = 0
6515 13:37:56.991646 2, 0xFFFF, sum = 0
6516 13:37:56.994543 3, 0xFFFF, sum = 0
6517 13:37:56.994627 4, 0xFFFF, sum = 0
6518 13:37:56.998200 5, 0xFFFF, sum = 0
6519 13:37:56.998283 6, 0xFFFF, sum = 0
6520 13:37:57.001176 7, 0xFFFF, sum = 0
6521 13:37:57.001259 8, 0xFFFF, sum = 0
6522 13:37:57.004479 9, 0xFFFF, sum = 0
6523 13:37:57.004562 10, 0xFFFF, sum = 0
6524 13:37:57.008414 11, 0xFFFF, sum = 0
6525 13:37:57.008497 12, 0xFFFF, sum = 0
6526 13:37:57.011764 13, 0x0, sum = 1
6527 13:37:57.011848 14, 0x0, sum = 2
6528 13:37:57.014713 15, 0x0, sum = 3
6529 13:37:57.014818 16, 0x0, sum = 4
6530 13:37:57.018405 best_step = 14
6531 13:37:57.018486
6532 13:37:57.018551 ==
6533 13:37:57.021320 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 13:37:57.025252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 13:37:57.025335 ==
6536 13:37:57.025419 RX Vref Scan: 0
6537 13:37:57.025483
6538 13:37:57.028328 RX Vref 0 -> 0, step: 1
6539 13:37:57.028409
6540 13:37:57.031431 RX Delay -343 -> 252, step: 8
6541 13:37:57.038621 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6542 13:37:57.042308 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6543 13:37:57.045285 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6544 13:37:57.048467 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6545 13:37:57.055402 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6546 13:37:57.058450 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6547 13:37:57.062031 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6548 13:37:57.065301 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6549 13:37:57.072307 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6550 13:37:57.075391 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6551 13:37:57.078495 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6552 13:37:57.082367 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6553 13:37:57.088582 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6554 13:37:57.092392 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6555 13:37:57.095613 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6556 13:37:57.098711 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6557 13:37:57.102396 ==
6558 13:37:57.105455 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 13:37:57.108570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 13:37:57.108699 ==
6561 13:37:57.108766 DQS Delay:
6562 13:37:57.112287 DQS0 = 48, DQS1 = 60
6563 13:37:57.112431 DQM Delay:
6564 13:37:57.115605 DQM0 = 13, DQM1 = 13
6565 13:37:57.115689 DQ Delay:
6566 13:37:57.119041 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6567 13:37:57.121923 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6568 13:37:57.125879 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6569 13:37:57.129195 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6570 13:37:57.129309
6571 13:37:57.129392
6572 13:37:57.135705 [DQSOSCAuto] RK1, (LSB)MR18= 0x986c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6573 13:37:57.139282 CH0 RK1: MR19=C0C, MR18=986C
6574 13:37:57.145853 CH0_RK1: MR19=0xC0C, MR18=0x986C, DQSOSC=390, MR23=63, INC=388, DEC=258
6575 13:37:57.148971 [RxdqsGatingPostProcess] freq 400
6576 13:37:57.152450 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 13:37:57.155739 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 13:37:57.159461 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 13:37:57.162543 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 13:37:57.166117 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 13:37:57.169127 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 13:37:57.172402 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 13:37:57.175525 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 13:37:57.179301 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 13:37:57.182559 Pre-setting of DQS Precalculation
6586 13:37:57.185614 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 13:37:57.185733 ==
6588 13:37:57.188840 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 13:37:57.195575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 13:37:57.195677 ==
6591 13:37:57.199296 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 13:37:57.205972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6593 13:37:57.208959 [CA 0] Center 36 (8~64) winsize 57
6594 13:37:57.212181 [CA 1] Center 36 (8~64) winsize 57
6595 13:37:57.215965 [CA 2] Center 36 (8~64) winsize 57
6596 13:37:57.218867 [CA 3] Center 36 (8~64) winsize 57
6597 13:37:57.222359 [CA 4] Center 36 (8~64) winsize 57
6598 13:37:57.225840 [CA 5] Center 36 (8~64) winsize 57
6599 13:37:57.225936
6600 13:37:57.228827 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6601 13:37:57.228933
6602 13:37:57.232572 [CATrainingPosCal] consider 1 rank data
6603 13:37:57.235592 u2DelayCellTimex100 = 270/100 ps
6604 13:37:57.239109 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 13:37:57.242138 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 13:37:57.245637 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 13:37:57.248911 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 13:37:57.252563 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 13:37:57.255589 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 13:37:57.255663
6611 13:37:57.262426 CA PerBit enable=1, Macro0, CA PI delay=36
6612 13:37:57.262534
6613 13:37:57.262628 [CBTSetCACLKResult] CA Dly = 36
6614 13:37:57.265986 CS Dly: 1 (0~32)
6615 13:37:57.266089 ==
6616 13:37:57.268950 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 13:37:57.272594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 13:37:57.272679 ==
6619 13:37:57.278995 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 13:37:57.285941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6621 13:37:57.288983 [CA 0] Center 36 (8~64) winsize 57
6622 13:37:57.292030 [CA 1] Center 36 (8~64) winsize 57
6623 13:37:57.295877 [CA 2] Center 36 (8~64) winsize 57
6624 13:37:57.295986 [CA 3] Center 36 (8~64) winsize 57
6625 13:37:57.298941 [CA 4] Center 36 (8~64) winsize 57
6626 13:37:57.302157 [CA 5] Center 36 (8~64) winsize 57
6627 13:37:57.302237
6628 13:37:57.308957 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6629 13:37:57.309079
6630 13:37:57.312272 [CATrainingPosCal] consider 2 rank data
6631 13:37:57.312377 u2DelayCellTimex100 = 270/100 ps
6632 13:37:57.318972 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 13:37:57.322801 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 13:37:57.325871 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 13:37:57.328952 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 13:37:57.332507 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 13:37:57.335643 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 13:37:57.335732
6639 13:37:57.339383 CA PerBit enable=1, Macro0, CA PI delay=36
6640 13:37:57.339463
6641 13:37:57.342391 [CBTSetCACLKResult] CA Dly = 36
6642 13:37:57.346061 CS Dly: 1 (0~32)
6643 13:37:57.346159
6644 13:37:57.349185 ----->DramcWriteLeveling(PI) begin...
6645 13:37:57.349264 ==
6646 13:37:57.352222 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 13:37:57.356190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 13:37:57.356271 ==
6649 13:37:57.359153 Write leveling (Byte 0): 40 => 8
6650 13:37:57.362625 Write leveling (Byte 1): 40 => 8
6651 13:37:57.365654 DramcWriteLeveling(PI) end<-----
6652 13:37:57.365764
6653 13:37:57.365869 ==
6654 13:37:57.369289 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 13:37:57.372621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 13:37:57.372735 ==
6657 13:37:57.376131 [Gating] SW mode calibration
6658 13:37:57.382252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 13:37:57.389530 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 13:37:57.392895 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6661 13:37:57.395938 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 13:37:57.399127 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 13:37:57.406019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 13:37:57.409168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 13:37:57.413165 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 13:37:57.419467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 13:37:57.422733 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 13:37:57.425706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 13:37:57.429538 Total UI for P1: 0, mck2ui 16
6670 13:37:57.432727 best dqsien dly found for B0: ( 0, 14, 24)
6671 13:37:57.436330 Total UI for P1: 0, mck2ui 16
6672 13:37:57.439253 best dqsien dly found for B1: ( 0, 14, 24)
6673 13:37:57.443151 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 13:37:57.446235 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 13:37:57.446339
6676 13:37:57.452795 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 13:37:57.455959 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 13:37:57.459276 [Gating] SW calibration Done
6679 13:37:57.459360 ==
6680 13:37:57.462924 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 13:37:57.466037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 13:37:57.466121 ==
6683 13:37:57.466187 RX Vref Scan: 0
6684 13:37:57.466249
6685 13:37:57.469183 RX Vref 0 -> 0, step: 1
6686 13:37:57.469266
6687 13:37:57.472927 RX Delay -410 -> 252, step: 16
6688 13:37:57.476197 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6689 13:37:57.479259 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6690 13:37:57.486362 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6691 13:37:57.489269 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6692 13:37:57.492710 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6693 13:37:57.496092 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6694 13:37:57.502814 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6695 13:37:57.505981 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6696 13:37:57.509459 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6697 13:37:57.512642 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6698 13:37:57.519567 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6699 13:37:57.522758 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6700 13:37:57.525912 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6701 13:37:57.529064 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6702 13:37:57.535959 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6703 13:37:57.539746 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6704 13:37:57.539832 ==
6705 13:37:57.543135 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 13:37:57.546021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 13:37:57.546106 ==
6708 13:37:57.549172 DQS Delay:
6709 13:37:57.549248 DQS0 = 51, DQS1 = 59
6710 13:37:57.552862 DQM Delay:
6711 13:37:57.552992 DQM0 = 18, DQM1 = 17
6712 13:37:57.553079 DQ Delay:
6713 13:37:57.555795 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6714 13:37:57.559659 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6715 13:37:57.562474 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6716 13:37:57.565677 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6717 13:37:57.565757
6718 13:37:57.565819
6719 13:37:57.565877 ==
6720 13:37:57.569465 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 13:37:57.576120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 13:37:57.576230 ==
6723 13:37:57.576310
6724 13:37:57.576372
6725 13:37:57.576429 TX Vref Scan disable
6726 13:37:57.579226 == TX Byte 0 ==
6727 13:37:57.582393 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 13:37:57.586282 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 13:37:57.589209 == TX Byte 1 ==
6730 13:37:57.592333 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 13:37:57.596192 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 13:37:57.596296 ==
6733 13:37:57.599369 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 13:37:57.606173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 13:37:57.606290 ==
6736 13:37:57.606356
6737 13:37:57.606416
6738 13:37:57.606473 TX Vref Scan disable
6739 13:37:57.609113 == TX Byte 0 ==
6740 13:37:57.612857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 13:37:57.615931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 13:37:57.619275 == TX Byte 1 ==
6743 13:37:57.622678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 13:37:57.626134 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 13:37:57.626238
6746 13:37:57.629393 [DATLAT]
6747 13:37:57.629493 Freq=400, CH1 RK0
6748 13:37:57.629626
6749 13:37:57.633077 DATLAT Default: 0xf
6750 13:37:57.633150 0, 0xFFFF, sum = 0
6751 13:37:57.636189 1, 0xFFFF, sum = 0
6752 13:37:57.636273 2, 0xFFFF, sum = 0
6753 13:37:57.639459 3, 0xFFFF, sum = 0
6754 13:37:57.639560 4, 0xFFFF, sum = 0
6755 13:37:57.642446 5, 0xFFFF, sum = 0
6756 13:37:57.642546 6, 0xFFFF, sum = 0
6757 13:37:57.646261 7, 0xFFFF, sum = 0
6758 13:37:57.646362 8, 0xFFFF, sum = 0
6759 13:37:57.649430 9, 0xFFFF, sum = 0
6760 13:37:57.649503 10, 0xFFFF, sum = 0
6761 13:37:57.652722 11, 0xFFFF, sum = 0
6762 13:37:57.656236 12, 0xFFFF, sum = 0
6763 13:37:57.656333 13, 0x0, sum = 1
6764 13:37:57.659565 14, 0x0, sum = 2
6765 13:37:57.659664 15, 0x0, sum = 3
6766 13:37:57.659759 16, 0x0, sum = 4
6767 13:37:57.663040 best_step = 14
6768 13:37:57.663138
6769 13:37:57.663232 ==
6770 13:37:57.665996 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 13:37:57.669011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 13:37:57.669098 ==
6773 13:37:57.672537 RX Vref Scan: 1
6774 13:37:57.672648
6775 13:37:57.672739 RX Vref 0 -> 0, step: 1
6776 13:37:57.676146
6777 13:37:57.676219 RX Delay -359 -> 252, step: 8
6778 13:37:57.676285
6779 13:37:57.679058 Set Vref, RX VrefLevel [Byte0]: 56
6780 13:37:57.682227 [Byte1]: 51
6781 13:37:57.687909
6782 13:37:57.688014 Final RX Vref Byte 0 = 56 to rank0
6783 13:37:57.691019 Final RX Vref Byte 1 = 51 to rank0
6784 13:37:57.694643 Final RX Vref Byte 0 = 56 to rank1
6785 13:37:57.697852 Final RX Vref Byte 1 = 51 to rank1==
6786 13:37:57.700906 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 13:37:57.707870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 13:37:57.707974 ==
6789 13:37:57.708057 DQS Delay:
6790 13:37:57.708117 DQS0 = 48, DQS1 = 60
6791 13:37:57.711016 DQM Delay:
6792 13:37:57.711115 DQM0 = 12, DQM1 = 13
6793 13:37:57.714168 DQ Delay:
6794 13:37:57.718039 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6795 13:37:57.718138 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6796 13:37:57.720916 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6797 13:37:57.724568 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6798 13:37:57.724667
6799 13:37:57.724758
6800 13:37:57.734229 [DQSOSCAuto] RK0, (LSB)MR18= 0x882f, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6801 13:37:57.737719 CH1 RK0: MR19=C0C, MR18=882F
6802 13:37:57.744338 CH1_RK0: MR19=0xC0C, MR18=0x882F, DQSOSC=392, MR23=63, INC=384, DEC=256
6803 13:37:57.744444 ==
6804 13:37:57.747898 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 13:37:57.751072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 13:37:57.751173 ==
6807 13:37:57.754214 [Gating] SW mode calibration
6808 13:37:57.760693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 13:37:57.764310 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 13:37:57.770842 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6811 13:37:57.774627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 13:37:57.777651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 13:37:57.784246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 13:37:57.787457 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 13:37:57.791171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 13:37:57.797354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 13:37:57.801145 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 13:37:57.804345 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 13:37:57.807530 Total UI for P1: 0, mck2ui 16
6820 13:37:57.810745 best dqsien dly found for B0: ( 0, 14, 24)
6821 13:37:57.814551 Total UI for P1: 0, mck2ui 16
6822 13:37:57.817861 best dqsien dly found for B1: ( 0, 14, 24)
6823 13:37:57.821014 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 13:37:57.824674 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 13:37:57.824780
6826 13:37:57.830834 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 13:37:57.834645 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 13:37:57.834717 [Gating] SW calibration Done
6829 13:37:57.837795 ==
6830 13:37:57.840747 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 13:37:57.844316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 13:37:57.844402 ==
6833 13:37:57.844462 RX Vref Scan: 0
6834 13:37:57.844519
6835 13:37:57.847967 RX Vref 0 -> 0, step: 1
6836 13:37:57.848066
6837 13:37:57.850915 RX Delay -410 -> 252, step: 16
6838 13:37:57.854393 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6839 13:37:57.857516 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6840 13:37:57.864273 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6841 13:37:57.867926 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6842 13:37:57.870754 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6843 13:37:57.874460 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6844 13:37:57.881192 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6845 13:37:57.884214 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6846 13:37:57.887893 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6847 13:37:57.891021 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6848 13:37:57.897373 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6849 13:37:57.901123 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6850 13:37:57.904116 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6851 13:37:57.911168 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6852 13:37:57.914505 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6853 13:37:57.917649 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6854 13:37:57.917722 ==
6855 13:37:57.920680 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 13:37:57.924444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 13:37:57.924541 ==
6858 13:37:57.927476 DQS Delay:
6859 13:37:57.927545 DQS0 = 43, DQS1 = 59
6860 13:37:57.930946 DQM Delay:
6861 13:37:57.931015 DQM0 = 10, DQM1 = 17
6862 13:37:57.931078 DQ Delay:
6863 13:37:57.934117 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6864 13:37:57.937288 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6865 13:37:57.940965 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6866 13:37:57.944126 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6867 13:37:57.944193
6868 13:37:57.944252
6869 13:37:57.944310 ==
6870 13:37:57.947293 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 13:37:57.954023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 13:37:57.954095 ==
6873 13:37:57.954154
6874 13:37:57.954211
6875 13:37:57.954265 TX Vref Scan disable
6876 13:37:57.957624 == TX Byte 0 ==
6877 13:37:57.960549 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 13:37:57.963923 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 13:37:57.967543 == TX Byte 1 ==
6880 13:37:57.970680 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6881 13:37:57.973740 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6882 13:37:57.973822 ==
6883 13:37:57.977526 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 13:37:57.983717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 13:37:57.983800 ==
6886 13:37:57.983870
6887 13:37:57.983982
6888 13:37:57.984053 TX Vref Scan disable
6889 13:37:57.987192 == TX Byte 0 ==
6890 13:37:57.990722 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 13:37:57.993813 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 13:37:57.997504 == TX Byte 1 ==
6893 13:37:58.000680 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6894 13:37:58.003676 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6895 13:37:58.003746
6896 13:37:58.007233 [DATLAT]
6897 13:37:58.007319 Freq=400, CH1 RK1
6898 13:37:58.007415
6899 13:37:58.010367 DATLAT Default: 0xe
6900 13:37:58.010455 0, 0xFFFF, sum = 0
6901 13:37:58.013533 1, 0xFFFF, sum = 0
6902 13:37:58.013618 2, 0xFFFF, sum = 0
6903 13:37:58.017361 3, 0xFFFF, sum = 0
6904 13:37:58.017451 4, 0xFFFF, sum = 0
6905 13:37:58.020528 5, 0xFFFF, sum = 0
6906 13:37:58.020619 6, 0xFFFF, sum = 0
6907 13:37:58.023585 7, 0xFFFF, sum = 0
6908 13:37:58.023673 8, 0xFFFF, sum = 0
6909 13:37:58.027408 9, 0xFFFF, sum = 0
6910 13:37:58.030609 10, 0xFFFF, sum = 0
6911 13:37:58.030699 11, 0xFFFF, sum = 0
6912 13:37:58.033766 12, 0xFFFF, sum = 0
6913 13:37:58.033852 13, 0x0, sum = 1
6914 13:37:58.037386 14, 0x0, sum = 2
6915 13:37:58.037479 15, 0x0, sum = 3
6916 13:37:58.037567 16, 0x0, sum = 4
6917 13:37:58.040499 best_step = 14
6918 13:37:58.040583
6919 13:37:58.040670 ==
6920 13:37:58.043575 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 13:37:58.047267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 13:37:58.047378 ==
6923 13:37:58.050406 RX Vref Scan: 0
6924 13:37:58.050523
6925 13:37:58.050622 RX Vref 0 -> 0, step: 1
6926 13:37:58.050739
6927 13:37:58.053521 RX Delay -359 -> 252, step: 8
6928 13:37:58.062315 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6929 13:37:58.065411 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6930 13:37:58.069085 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6931 13:37:58.072103 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6932 13:37:58.078661 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6933 13:37:58.082467 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6934 13:37:58.085438 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6935 13:37:58.089142 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6936 13:37:58.095578 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6937 13:37:58.098815 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6938 13:37:58.102221 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6939 13:37:58.105722 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6940 13:37:58.111920 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6941 13:37:58.115726 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6942 13:37:58.118962 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6943 13:37:58.121958 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6944 13:37:58.125811 ==
6945 13:37:58.128789 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 13:37:58.131955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 13:37:58.132038 ==
6948 13:37:58.132104 DQS Delay:
6949 13:37:58.135748 DQS0 = 48, DQS1 = 56
6950 13:37:58.135830 DQM Delay:
6951 13:37:58.139403 DQM0 = 9, DQM1 = 9
6952 13:37:58.139515 DQ Delay:
6953 13:37:58.142443 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6954 13:37:58.145478 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6955 13:37:58.145559 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6956 13:37:58.152487 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6957 13:37:58.152569
6958 13:37:58.152633
6959 13:37:58.158734 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6960 13:37:58.162401 CH1 RK1: MR19=C0C, MR18=748A
6961 13:37:58.168725 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
6962 13:37:58.172490 [RxdqsGatingPostProcess] freq 400
6963 13:37:58.175598 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 13:37:58.179209 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 13:37:58.182132 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 13:37:58.185597 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 13:37:58.189241 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 13:37:58.192241 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 13:37:58.195801 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 13:37:58.198896 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 13:37:58.202537 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 13:37:58.205446 Pre-setting of DQS Precalculation
6973 13:37:58.208766 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 13:37:58.215435 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 13:37:58.225378 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 13:37:58.225462
6977 13:37:58.225526
6978 13:37:58.229084 [Calibration Summary] 800 Mbps
6979 13:37:58.229165 CH 0, Rank 0
6980 13:37:58.232197 SW Impedance : PASS
6981 13:37:58.232278 DUTY Scan : NO K
6982 13:37:58.235365 ZQ Calibration : PASS
6983 13:37:58.235451 Jitter Meter : NO K
6984 13:37:58.239061 CBT Training : PASS
6985 13:37:58.242240 Write leveling : PASS
6986 13:37:58.242321 RX DQS gating : PASS
6987 13:37:58.245753 RX DQ/DQS(RDDQC) : PASS
6988 13:37:58.248792 TX DQ/DQS : PASS
6989 13:37:58.248900 RX DATLAT : PASS
6990 13:37:58.252681 RX DQ/DQS(Engine): PASS
6991 13:37:58.255679 TX OE : NO K
6992 13:37:58.255753 All Pass.
6993 13:37:58.255827
6994 13:37:58.255902 CH 0, Rank 1
6995 13:37:58.258934 SW Impedance : PASS
6996 13:37:58.262679 DUTY Scan : NO K
6997 13:37:58.262759 ZQ Calibration : PASS
6998 13:37:58.265905 Jitter Meter : NO K
6999 13:37:58.268797 CBT Training : PASS
7000 13:37:58.268904 Write leveling : NO K
7001 13:37:58.272637 RX DQS gating : PASS
7002 13:37:58.272719 RX DQ/DQS(RDDQC) : PASS
7003 13:37:58.275756 TX DQ/DQS : PASS
7004 13:37:58.278913 RX DATLAT : PASS
7005 13:37:58.278996 RX DQ/DQS(Engine): PASS
7006 13:37:58.282074 TX OE : NO K
7007 13:37:58.282157 All Pass.
7008 13:37:58.282253
7009 13:37:58.285770 CH 1, Rank 0
7010 13:37:58.285864 SW Impedance : PASS
7011 13:37:58.288807 DUTY Scan : NO K
7012 13:37:58.292401 ZQ Calibration : PASS
7013 13:37:58.292484 Jitter Meter : NO K
7014 13:37:58.295833 CBT Training : PASS
7015 13:37:58.298849 Write leveling : PASS
7016 13:37:58.298929 RX DQS gating : PASS
7017 13:37:58.302167 RX DQ/DQS(RDDQC) : PASS
7018 13:37:58.305761 TX DQ/DQS : PASS
7019 13:37:58.305837 RX DATLAT : PASS
7020 13:37:58.308902 RX DQ/DQS(Engine): PASS
7021 13:37:58.312518 TX OE : NO K
7022 13:37:58.312590 All Pass.
7023 13:37:58.312654
7024 13:37:58.312741 CH 1, Rank 1
7025 13:37:58.315476 SW Impedance : PASS
7026 13:37:58.318958 DUTY Scan : NO K
7027 13:37:58.319028 ZQ Calibration : PASS
7028 13:37:58.322501 Jitter Meter : NO K
7029 13:37:58.322566 CBT Training : PASS
7030 13:37:58.325406 Write leveling : NO K
7031 13:37:58.328886 RX DQS gating : PASS
7032 13:37:58.329012 RX DQ/DQS(RDDQC) : PASS
7033 13:37:58.332540 TX DQ/DQS : PASS
7034 13:37:58.335756 RX DATLAT : PASS
7035 13:37:58.335837 RX DQ/DQS(Engine): PASS
7036 13:37:58.338778 TX OE : NO K
7037 13:37:58.338851 All Pass.
7038 13:37:58.338912
7039 13:37:58.341981 DramC Write-DBI off
7040 13:37:58.345856 PER_BANK_REFRESH: Hybrid Mode
7041 13:37:58.345931 TX_TRACKING: ON
7042 13:37:58.355525 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 13:37:58.358758 [FAST_K] Save calibration result to emmc
7044 13:37:58.362538 dramc_set_vcore_voltage set vcore to 725000
7045 13:37:58.365759 Read voltage for 1600, 0
7046 13:37:58.365838 Vio18 = 0
7047 13:37:58.365908 Vcore = 725000
7048 13:37:58.368751 Vdram = 0
7049 13:37:58.368848 Vddq = 0
7050 13:37:58.368957 Vmddr = 0
7051 13:37:58.375700 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 13:37:58.378871 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 13:37:58.381918 MEM_TYPE=3, freq_sel=13
7054 13:37:58.385722 sv_algorithm_assistance_LP4_3733
7055 13:37:58.389001 ============ PULL DRAM RESETB DOWN ============
7056 13:37:58.392125 ========== PULL DRAM RESETB DOWN end =========
7057 13:37:58.399169 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 13:37:58.402145 ===================================
7059 13:37:58.402244 LPDDR4 DRAM CONFIGURATION
7060 13:37:58.405609 ===================================
7061 13:37:58.409035 EX_ROW_EN[0] = 0x0
7062 13:37:58.411855 EX_ROW_EN[1] = 0x0
7063 13:37:58.411952 LP4Y_EN = 0x0
7064 13:37:58.415376 WORK_FSP = 0x1
7065 13:37:58.415491 WL = 0x5
7066 13:37:58.418974 RL = 0x5
7067 13:37:58.419093 BL = 0x2
7068 13:37:58.421967 RPST = 0x0
7069 13:37:58.422079 RD_PRE = 0x0
7070 13:37:58.425432 WR_PRE = 0x1
7071 13:37:58.425517 WR_PST = 0x1
7072 13:37:58.428955 DBI_WR = 0x0
7073 13:37:58.429083 DBI_RD = 0x0
7074 13:37:58.432030 OTF = 0x1
7075 13:37:58.435353 ===================================
7076 13:37:58.438598 ===================================
7077 13:37:58.438692 ANA top config
7078 13:37:58.442184 ===================================
7079 13:37:58.445183 DLL_ASYNC_EN = 0
7080 13:37:58.449021 ALL_SLAVE_EN = 0
7081 13:37:58.452068 NEW_RANK_MODE = 1
7082 13:37:58.452194 DLL_IDLE_MODE = 1
7083 13:37:58.455760 LP45_APHY_COMB_EN = 1
7084 13:37:58.458913 TX_ODT_DIS = 0
7085 13:37:58.461857 NEW_8X_MODE = 1
7086 13:37:58.465666 ===================================
7087 13:37:58.468730 ===================================
7088 13:37:58.468830 data_rate = 3200
7089 13:37:58.472458 CKR = 1
7090 13:37:58.475701 DQ_P2S_RATIO = 8
7091 13:37:58.478675 ===================================
7092 13:37:58.482513 CA_P2S_RATIO = 8
7093 13:37:58.485715 DQ_CA_OPEN = 0
7094 13:37:58.488732 DQ_SEMI_OPEN = 0
7095 13:37:58.488829 CA_SEMI_OPEN = 0
7096 13:37:58.492541 CA_FULL_RATE = 0
7097 13:37:58.495695 DQ_CKDIV4_EN = 0
7098 13:37:58.499091 CA_CKDIV4_EN = 0
7099 13:37:58.502209 CA_PREDIV_EN = 0
7100 13:37:58.505533 PH8_DLY = 12
7101 13:37:58.505607 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 13:37:58.508729 DQ_AAMCK_DIV = 4
7103 13:37:58.512490 CA_AAMCK_DIV = 4
7104 13:37:58.515765 CA_ADMCK_DIV = 4
7105 13:37:58.519173 DQ_TRACK_CA_EN = 0
7106 13:37:58.522426 CA_PICK = 1600
7107 13:37:58.525556 CA_MCKIO = 1600
7108 13:37:58.525640 MCKIO_SEMI = 0
7109 13:37:58.529152 PLL_FREQ = 3068
7110 13:37:58.532085 DQ_UI_PI_RATIO = 32
7111 13:37:58.535475 CA_UI_PI_RATIO = 0
7112 13:37:58.539085 ===================================
7113 13:37:58.542203 ===================================
7114 13:37:58.545920 memory_type:LPDDR4
7115 13:37:58.545997 GP_NUM : 10
7116 13:37:58.549345 SRAM_EN : 1
7117 13:37:58.549420 MD32_EN : 0
7118 13:37:58.552710 ===================================
7119 13:37:58.555731 [ANA_INIT] >>>>>>>>>>>>>>
7120 13:37:58.559376 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 13:37:58.562662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 13:37:58.565859 ===================================
7123 13:37:58.568957 data_rate = 3200,PCW = 0X7600
7124 13:37:58.572364 ===================================
7125 13:37:58.575853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 13:37:58.582733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 13:37:58.585581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 13:37:58.592483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 13:37:58.595683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 13:37:58.599339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 13:37:58.599422 [ANA_INIT] flow start
7132 13:37:58.602559 [ANA_INIT] PLL >>>>>>>>
7133 13:37:58.602642 [ANA_INIT] PLL <<<<<<<<
7134 13:37:58.605946 [ANA_INIT] MIDPI >>>>>>>>
7135 13:37:58.609127 [ANA_INIT] MIDPI <<<<<<<<
7136 13:37:58.612969 [ANA_INIT] DLL >>>>>>>>
7137 13:37:58.613081 [ANA_INIT] DLL <<<<<<<<
7138 13:37:58.615945 [ANA_INIT] flow end
7139 13:37:58.619541 ============ LP4 DIFF to SE enter ============
7140 13:37:58.622567 ============ LP4 DIFF to SE exit ============
7141 13:37:58.626106 [ANA_INIT] <<<<<<<<<<<<<
7142 13:37:58.629030 [Flow] Enable top DCM control >>>>>
7143 13:37:58.632518 [Flow] Enable top DCM control <<<<<
7144 13:37:58.635896 Enable DLL master slave shuffle
7145 13:37:58.642511 ==============================================================
7146 13:37:58.642597 Gating Mode config
7147 13:37:58.648953 ==============================================================
7148 13:37:58.649047 Config description:
7149 13:37:58.659215 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 13:37:58.665728 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 13:37:58.672370 SELPH_MODE 0: By rank 1: By Phase
7152 13:37:58.676150 ==============================================================
7153 13:37:58.679271 GAT_TRACK_EN = 1
7154 13:37:58.682945 RX_GATING_MODE = 2
7155 13:37:58.685943 RX_GATING_TRACK_MODE = 2
7156 13:37:58.689617 SELPH_MODE = 1
7157 13:37:58.692558 PICG_EARLY_EN = 1
7158 13:37:58.696419 VALID_LAT_VALUE = 1
7159 13:37:58.699498 ==============================================================
7160 13:37:58.702694 Enter into Gating configuration >>>>
7161 13:37:58.706289 Exit from Gating configuration <<<<
7162 13:37:58.709536 Enter into DVFS_PRE_config >>>>>
7163 13:37:58.722842 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 13:37:58.722977 Exit from DVFS_PRE_config <<<<<
7165 13:37:58.726027 Enter into PICG configuration >>>>
7166 13:37:58.729445 Exit from PICG configuration <<<<
7167 13:37:58.732490 [RX_INPUT] configuration >>>>>
7168 13:37:58.735956 [RX_INPUT] configuration <<<<<
7169 13:37:58.742992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 13:37:58.745995 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 13:37:58.752533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 13:37:58.759440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 13:37:58.766384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 13:37:58.772678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 13:37:58.776141 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 13:37:58.779360 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 13:37:58.782719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 13:37:58.789410 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 13:37:58.793028 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 13:37:58.796166 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 13:37:58.799160 ===================================
7182 13:37:58.802918 LPDDR4 DRAM CONFIGURATION
7183 13:37:58.805895 ===================================
7184 13:37:58.806035 EX_ROW_EN[0] = 0x0
7185 13:37:58.809644 EX_ROW_EN[1] = 0x0
7186 13:37:58.809788 LP4Y_EN = 0x0
7187 13:37:58.812852 WORK_FSP = 0x1
7188 13:37:58.815893 WL = 0x5
7189 13:37:58.816030 RL = 0x5
7190 13:37:58.819698 BL = 0x2
7191 13:37:58.819833 RPST = 0x0
7192 13:37:58.822722 RD_PRE = 0x0
7193 13:37:58.822856 WR_PRE = 0x1
7194 13:37:58.826286 WR_PST = 0x1
7195 13:37:58.826426 DBI_WR = 0x0
7196 13:37:58.829273 DBI_RD = 0x0
7197 13:37:58.829407 OTF = 0x1
7198 13:37:58.833031 ===================================
7199 13:37:58.836146 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 13:37:58.842870 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 13:37:58.845808 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 13:37:58.849321 ===================================
7203 13:37:58.852436 LPDDR4 DRAM CONFIGURATION
7204 13:37:58.855914 ===================================
7205 13:37:58.856051 EX_ROW_EN[0] = 0x10
7206 13:37:58.859411 EX_ROW_EN[1] = 0x0
7207 13:37:58.859545 LP4Y_EN = 0x0
7208 13:37:58.862583 WORK_FSP = 0x1
7209 13:37:58.862726 WL = 0x5
7210 13:37:58.866209 RL = 0x5
7211 13:37:58.866344 BL = 0x2
7212 13:37:58.869613 RPST = 0x0
7213 13:37:58.869748 RD_PRE = 0x0
7214 13:37:58.872475 WR_PRE = 0x1
7215 13:37:58.875793 WR_PST = 0x1
7216 13:37:58.875934 DBI_WR = 0x0
7217 13:37:58.879740 DBI_RD = 0x0
7218 13:37:58.879883 OTF = 0x1
7219 13:37:58.882724 ===================================
7220 13:37:58.889126 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 13:37:58.889247 ==
7222 13:37:58.892490 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 13:37:58.895922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 13:37:58.896001 ==
7225 13:37:58.899467 [Duty_Offset_Calibration]
7226 13:37:58.899546 B0:2 B1:-1 CA:1
7227 13:37:58.902529
7228 13:37:58.902603 [DutyScan_Calibration_Flow] k_type=0
7229 13:37:58.912972
7230 13:37:58.913077 ==CLK 0==
7231 13:37:58.916730 Final CLK duty delay cell = -4
7232 13:37:58.919771 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7233 13:37:58.923552 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7234 13:37:58.926619 [-4] AVG Duty = 4937%(X100)
7235 13:37:58.926706
7236 13:37:58.930178 CH0 CLK Duty spec in!! Max-Min= 187%
7237 13:37:58.933325 [DutyScan_Calibration_Flow] ====Done====
7238 13:37:58.933408
7239 13:37:58.936377 [DutyScan_Calibration_Flow] k_type=1
7240 13:37:58.952565
7241 13:37:58.952662 ==DQS 0 ==
7242 13:37:58.955962 Final DQS duty delay cell = 0
7243 13:37:58.959410 [0] MAX Duty = 5125%(X100), DQS PI = 58
7244 13:37:58.962991 [0] MIN Duty = 5000%(X100), DQS PI = 14
7245 13:37:58.963083 [0] AVG Duty = 5062%(X100)
7246 13:37:58.966063
7247 13:37:58.966141 ==DQS 1 ==
7248 13:37:58.969216 Final DQS duty delay cell = -4
7249 13:37:58.972788 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7250 13:37:58.976393 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7251 13:37:58.979527 [-4] AVG Duty = 5046%(X100)
7252 13:37:58.979634
7253 13:37:58.982567 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7254 13:37:58.982675
7255 13:37:58.986097 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7256 13:37:58.989364 [DutyScan_Calibration_Flow] ====Done====
7257 13:37:58.989471
7258 13:37:58.992811 [DutyScan_Calibration_Flow] k_type=3
7259 13:37:59.010001
7260 13:37:59.010099 ==DQM 0 ==
7261 13:37:59.013926 Final DQM duty delay cell = 0
7262 13:37:59.016980 [0] MAX Duty = 5000%(X100), DQS PI = 20
7263 13:37:59.019892 [0] MIN Duty = 4875%(X100), DQS PI = 4
7264 13:37:59.019998 [0] AVG Duty = 4937%(X100)
7265 13:37:59.023678
7266 13:37:59.023783 ==DQM 1 ==
7267 13:37:59.026664 Final DQM duty delay cell = 0
7268 13:37:59.030321 [0] MAX Duty = 5187%(X100), DQS PI = 58
7269 13:37:59.033302 [0] MIN Duty = 4969%(X100), DQS PI = 18
7270 13:37:59.033377 [0] AVG Duty = 5078%(X100)
7271 13:37:59.037111
7272 13:37:59.040134 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7273 13:37:59.040212
7274 13:37:59.043164 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7275 13:37:59.046823 [DutyScan_Calibration_Flow] ====Done====
7276 13:37:59.046912
7277 13:37:59.049888 [DutyScan_Calibration_Flow] k_type=2
7278 13:37:59.067443
7279 13:37:59.067549 ==DQ 0 ==
7280 13:37:59.070445 Final DQ duty delay cell = 0
7281 13:37:59.074018 [0] MAX Duty = 5156%(X100), DQS PI = 0
7282 13:37:59.077602 [0] MIN Duty = 5031%(X100), DQS PI = 12
7283 13:37:59.077691 [0] AVG Duty = 5093%(X100)
7284 13:37:59.077778
7285 13:37:59.080663 ==DQ 1 ==
7286 13:37:59.083927 Final DQ duty delay cell = 0
7287 13:37:59.087453 [0] MAX Duty = 5000%(X100), DQS PI = 14
7288 13:37:59.090582 [0] MIN Duty = 4907%(X100), DQS PI = 18
7289 13:37:59.090669 [0] AVG Duty = 4953%(X100)
7290 13:37:59.090758
7291 13:37:59.094062 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7292 13:37:59.094149
7293 13:37:59.097349 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7294 13:37:59.104018 [DutyScan_Calibration_Flow] ====Done====
7295 13:37:59.104107 ==
7296 13:37:59.107416 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 13:37:59.110968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 13:37:59.111052 ==
7299 13:37:59.114267 [Duty_Offset_Calibration]
7300 13:37:59.114354 B0:1 B1:1 CA:2
7301 13:37:59.114420
7302 13:37:59.117486 [DutyScan_Calibration_Flow] k_type=0
7303 13:37:59.127201
7304 13:37:59.127309 ==CLK 0==
7305 13:37:59.130852 Final CLK duty delay cell = 0
7306 13:37:59.133891 [0] MAX Duty = 5187%(X100), DQS PI = 24
7307 13:37:59.137501 [0] MIN Duty = 4969%(X100), DQS PI = 40
7308 13:37:59.137589 [0] AVG Duty = 5078%(X100)
7309 13:37:59.137689
7310 13:37:59.140585 CH1 CLK Duty spec in!! Max-Min= 218%
7311 13:37:59.147337 [DutyScan_Calibration_Flow] ====Done====
7312 13:37:59.147445
7313 13:37:59.151059 [DutyScan_Calibration_Flow] k_type=1
7314 13:37:59.167079
7315 13:37:59.167249 ==DQS 0 ==
7316 13:37:59.170731 Final DQS duty delay cell = 0
7317 13:37:59.173572 [0] MAX Duty = 5031%(X100), DQS PI = 20
7318 13:37:59.176825 [0] MIN Duty = 4813%(X100), DQS PI = 50
7319 13:37:59.180675 [0] AVG Duty = 4922%(X100)
7320 13:37:59.180818
7321 13:37:59.180916 ==DQS 1 ==
7322 13:37:59.183891 Final DQS duty delay cell = 0
7323 13:37:59.187055 [0] MAX Duty = 5031%(X100), DQS PI = 56
7324 13:37:59.190473 [0] MIN Duty = 4938%(X100), DQS PI = 14
7325 13:37:59.190594 [0] AVG Duty = 4984%(X100)
7326 13:37:59.194234
7327 13:37:59.197253 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7328 13:37:59.197329
7329 13:37:59.200874 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7330 13:37:59.204314 [DutyScan_Calibration_Flow] ====Done====
7331 13:37:59.204393
7332 13:37:59.207294 [DutyScan_Calibration_Flow] k_type=3
7333 13:37:59.224063
7334 13:37:59.224149 ==DQM 0 ==
7335 13:37:59.227490 Final DQM duty delay cell = 0
7336 13:37:59.231083 [0] MAX Duty = 5156%(X100), DQS PI = 22
7337 13:37:59.234079 [0] MIN Duty = 4844%(X100), DQS PI = 50
7338 13:37:59.234187 [0] AVG Duty = 5000%(X100)
7339 13:37:59.237135
7340 13:37:59.237234 ==DQM 1 ==
7341 13:37:59.240714 Final DQM duty delay cell = 0
7342 13:37:59.243894 [0] MAX Duty = 5156%(X100), DQS PI = 60
7343 13:37:59.247454 [0] MIN Duty = 4907%(X100), DQS PI = 18
7344 13:37:59.247556 [0] AVG Duty = 5031%(X100)
7345 13:37:59.250613
7346 13:37:59.254238 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7347 13:37:59.254337
7348 13:37:59.257266 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7349 13:37:59.260949 [DutyScan_Calibration_Flow] ====Done====
7350 13:37:59.261039
7351 13:37:59.264031 [DutyScan_Calibration_Flow] k_type=2
7352 13:37:59.281385
7353 13:37:59.281475 ==DQ 0 ==
7354 13:37:59.284247 Final DQ duty delay cell = 0
7355 13:37:59.287721 [0] MAX Duty = 5156%(X100), DQS PI = 20
7356 13:37:59.291014 [0] MIN Duty = 4907%(X100), DQS PI = 52
7357 13:37:59.291094 [0] AVG Duty = 5031%(X100)
7358 13:37:59.294239
7359 13:37:59.294342 ==DQ 1 ==
7360 13:37:59.297516 Final DQ duty delay cell = 0
7361 13:37:59.301241 [0] MAX Duty = 5093%(X100), DQS PI = 8
7362 13:37:59.304274 [0] MIN Duty = 5031%(X100), DQS PI = 0
7363 13:37:59.304389 [0] AVG Duty = 5062%(X100)
7364 13:37:59.304485
7365 13:37:59.307711 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7366 13:37:59.307814
7367 13:37:59.310912 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7368 13:37:59.317439 [DutyScan_Calibration_Flow] ====Done====
7369 13:37:59.320904 nWR fixed to 30
7370 13:37:59.321012 [ModeRegInit_LP4] CH0 RK0
7371 13:37:59.324563 [ModeRegInit_LP4] CH0 RK1
7372 13:37:59.327870 [ModeRegInit_LP4] CH1 RK0
7373 13:37:59.327987 [ModeRegInit_LP4] CH1 RK1
7374 13:37:59.331368 match AC timing 5
7375 13:37:59.334260 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 13:37:59.337651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 13:37:59.344200 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 13:37:59.347853 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 13:37:59.354420 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 13:37:59.354527 [MiockJmeterHQA]
7381 13:37:59.354622
7382 13:37:59.357459 [DramcMiockJmeter] u1RxGatingPI = 0
7383 13:37:59.357557 0 : 4253, 4027
7384 13:37:59.361199 4 : 4363, 4138
7385 13:37:59.361300 8 : 4252, 4027
7386 13:37:59.364366 12 : 4252, 4027
7387 13:37:59.364476 16 : 4253, 4026
7388 13:37:59.367315 20 : 4252, 4027
7389 13:37:59.367424 24 : 4253, 4027
7390 13:37:59.371058 28 : 4363, 4138
7391 13:37:59.371141 32 : 4253, 4026
7392 13:37:59.371207 36 : 4363, 4137
7393 13:37:59.374023 40 : 4252, 4027
7394 13:37:59.374104 44 : 4253, 4027
7395 13:37:59.377684 48 : 4255, 4029
7396 13:37:59.377763 52 : 4363, 4137
7397 13:37:59.380889 56 : 4253, 4027
7398 13:37:59.381012 60 : 4360, 4138
7399 13:37:59.381108 64 : 4254, 4029
7400 13:37:59.384380 68 : 4250, 4026
7401 13:37:59.384480 72 : 4252, 4027
7402 13:37:59.387607 76 : 4250, 4027
7403 13:37:59.387707 80 : 4360, 4138
7404 13:37:59.390710 84 : 4250, 4027
7405 13:37:59.390783 88 : 4361, 4137
7406 13:37:59.394246 92 : 4250, 4027
7407 13:37:59.394322 96 : 4250, 3391
7408 13:37:59.394385 100 : 4250, 0
7409 13:37:59.397987 104 : 4252, 0
7410 13:37:59.398074 108 : 4250, 0
7411 13:37:59.401050 112 : 4249, 0
7412 13:37:59.401171 116 : 4252, 0
7413 13:37:59.401254 120 : 4363, 0
7414 13:37:59.404449 124 : 4360, 0
7415 13:37:59.404527 128 : 4361, 0
7416 13:37:59.404639 132 : 4252, 0
7417 13:37:59.407348 136 : 4253, 0
7418 13:37:59.407446 140 : 4249, 0
7419 13:37:59.411087 144 : 4252, 0
7420 13:37:59.411164 148 : 4253, 0
7421 13:37:59.411276 152 : 4250, 0
7422 13:37:59.414594 156 : 4250, 0
7423 13:37:59.414671 160 : 4250, 0
7424 13:37:59.417568 164 : 4250, 0
7425 13:37:59.417661 168 : 4252, 0
7426 13:37:59.417751 172 : 4361, 0
7427 13:37:59.421177 176 : 4360, 0
7428 13:37:59.421281 180 : 4363, 0
7429 13:37:59.421367 184 : 4250, 0
7430 13:37:59.424286 188 : 4250, 0
7431 13:37:59.424387 192 : 4250, 0
7432 13:37:59.427886 196 : 4250, 0
7433 13:37:59.427986 200 : 4250, 0
7434 13:37:59.428072 204 : 4250, 0
7435 13:37:59.430723 208 : 4252, 0
7436 13:37:59.430811 212 : 4250, 102
7437 13:37:59.434262 216 : 4250, 3633
7438 13:37:59.434365 220 : 4250, 4027
7439 13:37:59.437435 224 : 4250, 4027
7440 13:37:59.437522 228 : 4360, 4138
7441 13:37:59.441146 232 : 4250, 4026
7442 13:37:59.441232 236 : 4250, 4027
7443 13:37:59.444344 240 : 4361, 4138
7444 13:37:59.444431 244 : 4363, 4137
7445 13:37:59.444521 248 : 4248, 4024
7446 13:37:59.447917 252 : 4361, 4137
7447 13:37:59.448005 256 : 4361, 4138
7448 13:37:59.451137 260 : 4252, 4027
7449 13:37:59.451224 264 : 4250, 4026
7450 13:37:59.454584 268 : 4250, 4027
7451 13:37:59.454671 272 : 4253, 4029
7452 13:37:59.457704 276 : 4249, 4027
7453 13:37:59.457792 280 : 4250, 4026
7454 13:37:59.460696 284 : 4250, 4027
7455 13:37:59.460783 288 : 4250, 4027
7456 13:37:59.464529 292 : 4361, 4138
7457 13:37:59.464617 296 : 4361, 4137
7458 13:37:59.467474 300 : 4250, 4027
7459 13:37:59.467562 304 : 4361, 4137
7460 13:37:59.467650 308 : 4360, 4138
7461 13:37:59.471153 312 : 4253, 4027
7462 13:37:59.471243 316 : 4252, 4027
7463 13:37:59.474269 320 : 4250, 4026
7464 13:37:59.474360 324 : 4250, 4027
7465 13:37:59.477328 328 : 4252, 4027
7466 13:37:59.477407 332 : 4250, 3187
7467 13:37:59.481139 336 : 4250, 102
7468 13:37:59.481217
7469 13:37:59.481280 MIOCK jitter meter ch=0
7470 13:37:59.481340
7471 13:37:59.484200 1T = (336-100) = 236 dly cells
7472 13:37:59.490850 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7473 13:37:59.490939 ==
7474 13:37:59.494489 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 13:37:59.497401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7476 13:37:59.497489 ==
7477 13:37:59.504168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7478 13:37:59.507764 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7479 13:37:59.510841 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7480 13:37:59.517340 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7481 13:37:59.527766 [CA 0] Center 44 (14~75) winsize 62
7482 13:37:59.530885 [CA 1] Center 43 (13~74) winsize 62
7483 13:37:59.533931 [CA 2] Center 39 (10~68) winsize 59
7484 13:37:59.537582 [CA 3] Center 39 (10~68) winsize 59
7485 13:37:59.540537 [CA 4] Center 37 (7~67) winsize 61
7486 13:37:59.544243 [CA 5] Center 37 (7~67) winsize 61
7487 13:37:59.544330
7488 13:37:59.547519 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7489 13:37:59.547606
7490 13:37:59.550518 [CATrainingPosCal] consider 1 rank data
7491 13:37:59.554110 u2DelayCellTimex100 = 275/100 ps
7492 13:37:59.557642 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7493 13:37:59.563896 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7494 13:37:59.567358 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7495 13:37:59.570483 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7496 13:37:59.574332 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7497 13:37:59.577296 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7498 13:37:59.577385
7499 13:37:59.581065 CA PerBit enable=1, Macro0, CA PI delay=37
7500 13:37:59.581153
7501 13:37:59.584092 [CBTSetCACLKResult] CA Dly = 37
7502 13:37:59.587225 CS Dly: 11 (0~42)
7503 13:37:59.590997 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7504 13:37:59.594147 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7505 13:37:59.594221 ==
7506 13:37:59.597257 Dram Type= 6, Freq= 0, CH_0, rank 1
7507 13:37:59.600835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 13:37:59.603851 ==
7509 13:37:59.607616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 13:37:59.611219 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 13:37:59.617744 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 13:37:59.620886 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 13:37:59.631348 [CA 0] Center 44 (14~75) winsize 62
7514 13:37:59.634827 [CA 1] Center 44 (14~75) winsize 62
7515 13:37:59.637670 [CA 2] Center 40 (11~69) winsize 59
7516 13:37:59.641444 [CA 3] Center 39 (10~69) winsize 60
7517 13:37:59.644335 [CA 4] Center 38 (9~67) winsize 59
7518 13:37:59.647950 [CA 5] Center 37 (7~67) winsize 61
7519 13:37:59.648024
7520 13:37:59.651430 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 13:37:59.651506
7522 13:37:59.654471 [CATrainingPosCal] consider 2 rank data
7523 13:37:59.658256 u2DelayCellTimex100 = 275/100 ps
7524 13:37:59.661347 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7525 13:37:59.668017 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7526 13:37:59.671597 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7527 13:37:59.674562 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7528 13:37:59.678204 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7529 13:37:59.681417 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7530 13:37:59.681491
7531 13:37:59.684475 CA PerBit enable=1, Macro0, CA PI delay=37
7532 13:37:59.684548
7533 13:37:59.688230 [CBTSetCACLKResult] CA Dly = 37
7534 13:37:59.691160 CS Dly: 12 (0~44)
7535 13:37:59.695050 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 13:37:59.698112 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 13:37:59.698185
7538 13:37:59.701289 ----->DramcWriteLeveling(PI) begin...
7539 13:37:59.701360 ==
7540 13:37:59.704746 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 13:37:59.708308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 13:37:59.711351 ==
7543 13:37:59.711421 Write leveling (Byte 0): 31 => 31
7544 13:37:59.714910 Write leveling (Byte 1): 27 => 27
7545 13:37:59.718002 DramcWriteLeveling(PI) end<-----
7546 13:37:59.718071
7547 13:37:59.718130 ==
7548 13:37:59.721626 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 13:37:59.728447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 13:37:59.728523 ==
7551 13:37:59.728586 [Gating] SW mode calibration
7552 13:37:59.738047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7553 13:37:59.741412 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7554 13:37:59.744677 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 13:37:59.751418 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 13:37:59.755057 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 13:37:59.757983 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 13:37:59.764951 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7559 13:37:59.768357 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7560 13:37:59.771845 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7561 13:37:59.778290 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 13:37:59.781757 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 13:37:59.784870 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 13:37:59.791500 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 13:37:59.794667 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 13:37:59.798506 1 5 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7567 13:37:59.805201 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7568 13:37:59.808214 1 5 24 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7569 13:37:59.811764 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 13:37:59.818296 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 13:37:59.821465 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 13:37:59.825074 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 13:37:59.828127 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 13:37:59.834941 1 6 16 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7575 13:37:59.838444 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7576 13:37:59.841594 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7577 13:37:59.848686 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 13:37:59.851468 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 13:37:59.855044 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 13:37:59.861501 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 13:37:59.864996 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 13:37:59.868324 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 13:37:59.874820 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7584 13:37:59.878426 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 13:37:59.881923 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 13:37:59.888279 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 13:37:59.891788 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 13:37:59.894913 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 13:37:59.901580 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 13:37:59.905385 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 13:37:59.908454 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 13:37:59.911593 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 13:37:59.918302 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 13:37:59.921562 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 13:37:59.925100 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 13:37:59.931764 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 13:37:59.934930 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 13:37:59.938487 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 13:37:59.945249 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7600 13:37:59.948408 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 13:37:59.951421 Total UI for P1: 0, mck2ui 16
7602 13:37:59.955178 best dqsien dly found for B0: ( 1, 9, 16)
7603 13:37:59.958048 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 13:37:59.961606 Total UI for P1: 0, mck2ui 16
7605 13:37:59.964667 best dqsien dly found for B1: ( 1, 9, 22)
7606 13:37:59.968496 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7607 13:37:59.971855 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7608 13:37:59.971968
7609 13:37:59.978018 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7610 13:37:59.981474 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7611 13:37:59.984766 [Gating] SW calibration Done
7612 13:37:59.984882 ==
7613 13:37:59.988270 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 13:37:59.991946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 13:37:59.992027 ==
7616 13:37:59.992090 RX Vref Scan: 0
7617 13:37:59.992149
7618 13:37:59.995157 RX Vref 0 -> 0, step: 1
7619 13:37:59.995232
7620 13:37:59.998612 RX Delay 0 -> 252, step: 8
7621 13:38:00.001873 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7622 13:38:00.005084 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7623 13:38:00.008150 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7624 13:38:00.014846 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7625 13:38:00.018483 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7626 13:38:00.021527 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7627 13:38:00.025328 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7628 13:38:00.028491 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7629 13:38:00.035090 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7630 13:38:00.038869 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7631 13:38:00.041865 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7632 13:38:00.044961 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7633 13:38:00.048654 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7634 13:38:00.055255 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7635 13:38:00.058906 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7636 13:38:00.061871 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7637 13:38:00.061943 ==
7638 13:38:00.065295 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 13:38:00.068553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 13:38:00.068626 ==
7641 13:38:00.072071 DQS Delay:
7642 13:38:00.072170 DQS0 = 0, DQS1 = 0
7643 13:38:00.075168 DQM Delay:
7644 13:38:00.075275 DQM0 = 132, DQM1 = 123
7645 13:38:00.075368 DQ Delay:
7646 13:38:00.078377 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7647 13:38:00.082052 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7648 13:38:00.088553 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7649 13:38:00.092082 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7650 13:38:00.092161
7651 13:38:00.092226
7652 13:38:00.092286 ==
7653 13:38:00.095360 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 13:38:00.099029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 13:38:00.099117 ==
7656 13:38:00.099183
7657 13:38:00.099246
7658 13:38:00.101915 TX Vref Scan disable
7659 13:38:00.101996 == TX Byte 0 ==
7660 13:38:00.108744 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7661 13:38:00.112170 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7662 13:38:00.112259 == TX Byte 1 ==
7663 13:38:00.118588 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7664 13:38:00.121769 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7665 13:38:00.121856 ==
7666 13:38:00.125279 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 13:38:00.128219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 13:38:00.128300 ==
7669 13:38:00.143034
7670 13:38:00.146789 TX Vref early break, caculate TX vref
7671 13:38:00.149924 TX Vref=16, minBit 1, minWin=21, winSum=354
7672 13:38:00.153024 TX Vref=18, minBit 0, minWin=22, winSum=370
7673 13:38:00.156723 TX Vref=20, minBit 7, minWin=22, winSum=376
7674 13:38:00.159697 TX Vref=22, minBit 7, minWin=23, winSum=390
7675 13:38:00.163481 TX Vref=24, minBit 8, minWin=24, winSum=404
7676 13:38:00.169828 TX Vref=26, minBit 1, minWin=24, winSum=411
7677 13:38:00.173544 TX Vref=28, minBit 7, minWin=25, winSum=421
7678 13:38:00.176638 TX Vref=30, minBit 4, minWin=24, winSum=414
7679 13:38:00.179594 TX Vref=32, minBit 4, minWin=24, winSum=409
7680 13:38:00.183183 TX Vref=34, minBit 3, minWin=23, winSum=395
7681 13:38:00.189485 [TxChooseVref] Worse bit 7, Min win 25, Win sum 421, Final Vref 28
7682 13:38:00.189573
7683 13:38:00.193139 Final TX Range 0 Vref 28
7684 13:38:00.193224
7685 13:38:00.193311 ==
7686 13:38:00.196148 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 13:38:00.199682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 13:38:00.199760 ==
7689 13:38:00.199842
7690 13:38:00.199929
7691 13:38:00.203351 TX Vref Scan disable
7692 13:38:00.209806 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7693 13:38:00.209887 == TX Byte 0 ==
7694 13:38:00.212926 u2DelayCellOfst[0]=14 cells (4 PI)
7695 13:38:00.216538 u2DelayCellOfst[1]=24 cells (7 PI)
7696 13:38:00.219493 u2DelayCellOfst[2]=14 cells (4 PI)
7697 13:38:00.223082 u2DelayCellOfst[3]=17 cells (5 PI)
7698 13:38:00.226582 u2DelayCellOfst[4]=10 cells (3 PI)
7699 13:38:00.229790 u2DelayCellOfst[5]=0 cells (0 PI)
7700 13:38:00.233258 u2DelayCellOfst[6]=21 cells (6 PI)
7701 13:38:00.233336 u2DelayCellOfst[7]=21 cells (6 PI)
7702 13:38:00.239438 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7703 13:38:00.243124 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7704 13:38:00.243209 == TX Byte 1 ==
7705 13:38:00.246212 u2DelayCellOfst[8]=3 cells (1 PI)
7706 13:38:00.250091 u2DelayCellOfst[9]=0 cells (0 PI)
7707 13:38:00.253116 u2DelayCellOfst[10]=7 cells (2 PI)
7708 13:38:00.256109 u2DelayCellOfst[11]=0 cells (0 PI)
7709 13:38:00.259823 u2DelayCellOfst[12]=14 cells (4 PI)
7710 13:38:00.262902 u2DelayCellOfst[13]=10 cells (3 PI)
7711 13:38:00.266172 u2DelayCellOfst[14]=14 cells (4 PI)
7712 13:38:00.269962 u2DelayCellOfst[15]=10 cells (3 PI)
7713 13:38:00.272887 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7714 13:38:00.276121 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7715 13:38:00.279584 DramC Write-DBI on
7716 13:38:00.279694 ==
7717 13:38:00.283111 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 13:38:00.286099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 13:38:00.286174 ==
7720 13:38:00.286237
7721 13:38:00.289914
7722 13:38:00.289985 TX Vref Scan disable
7723 13:38:00.293098 == TX Byte 0 ==
7724 13:38:00.296042 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7725 13:38:00.299729 == TX Byte 1 ==
7726 13:38:00.303200 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7727 13:38:00.303298 DramC Write-DBI off
7728 13:38:00.303390
7729 13:38:00.306268 [DATLAT]
7730 13:38:00.306338 Freq=1600, CH0 RK0
7731 13:38:00.306402
7732 13:38:00.309818 DATLAT Default: 0xf
7733 13:38:00.309889 0, 0xFFFF, sum = 0
7734 13:38:00.312721 1, 0xFFFF, sum = 0
7735 13:38:00.312822 2, 0xFFFF, sum = 0
7736 13:38:00.316536 3, 0xFFFF, sum = 0
7737 13:38:00.316642 4, 0xFFFF, sum = 0
7738 13:38:00.319426 5, 0xFFFF, sum = 0
7739 13:38:00.319525 6, 0xFFFF, sum = 0
7740 13:38:00.323069 7, 0xFFFF, sum = 0
7741 13:38:00.326124 8, 0xFFFF, sum = 0
7742 13:38:00.326197 9, 0xFFFF, sum = 0
7743 13:38:00.329499 10, 0xFFFF, sum = 0
7744 13:38:00.329571 11, 0xFFFF, sum = 0
7745 13:38:00.332891 12, 0xFFFF, sum = 0
7746 13:38:00.332997 13, 0xFFFF, sum = 0
7747 13:38:00.336399 14, 0x0, sum = 1
7748 13:38:00.336471 15, 0x0, sum = 2
7749 13:38:00.339796 16, 0x0, sum = 3
7750 13:38:00.339895 17, 0x0, sum = 4
7751 13:38:00.339986 best_step = 15
7752 13:38:00.340072
7753 13:38:00.343042 ==
7754 13:38:00.346649 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 13:38:00.349831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 13:38:00.349905 ==
7757 13:38:00.349968 RX Vref Scan: 1
7758 13:38:00.350027
7759 13:38:00.352936 Set Vref Range= 24 -> 127
7760 13:38:00.353033
7761 13:38:00.356564 RX Vref 24 -> 127, step: 1
7762 13:38:00.356661
7763 13:38:00.359813 RX Delay 11 -> 252, step: 4
7764 13:38:00.359908
7765 13:38:00.362837 Set Vref, RX VrefLevel [Byte0]: 24
7766 13:38:00.366572 [Byte1]: 24
7767 13:38:00.366646
7768 13:38:00.369726 Set Vref, RX VrefLevel [Byte0]: 25
7769 13:38:00.373310 [Byte1]: 25
7770 13:38:00.373393
7771 13:38:00.376310 Set Vref, RX VrefLevel [Byte0]: 26
7772 13:38:00.380228 [Byte1]: 26
7773 13:38:00.383576
7774 13:38:00.383688 Set Vref, RX VrefLevel [Byte0]: 27
7775 13:38:00.386472 [Byte1]: 27
7776 13:38:00.390501
7777 13:38:00.390614 Set Vref, RX VrefLevel [Byte0]: 28
7778 13:38:00.394071 [Byte1]: 28
7779 13:38:00.398255
7780 13:38:00.398331 Set Vref, RX VrefLevel [Byte0]: 29
7781 13:38:00.401972 [Byte1]: 29
7782 13:38:00.406203
7783 13:38:00.406278 Set Vref, RX VrefLevel [Byte0]: 30
7784 13:38:00.409267 [Byte1]: 30
7785 13:38:00.413357
7786 13:38:00.413433 Set Vref, RX VrefLevel [Byte0]: 31
7787 13:38:00.416933 [Byte1]: 31
7788 13:38:00.421162
7789 13:38:00.421236 Set Vref, RX VrefLevel [Byte0]: 32
7790 13:38:00.424473 [Byte1]: 32
7791 13:38:00.428778
7792 13:38:00.428877 Set Vref, RX VrefLevel [Byte0]: 33
7793 13:38:00.432055 [Byte1]: 33
7794 13:38:00.436719
7795 13:38:00.436822 Set Vref, RX VrefLevel [Byte0]: 34
7796 13:38:00.439477 [Byte1]: 34
7797 13:38:00.444419
7798 13:38:00.444497 Set Vref, RX VrefLevel [Byte0]: 35
7799 13:38:00.447457 [Byte1]: 35
7800 13:38:00.451773
7801 13:38:00.451874 Set Vref, RX VrefLevel [Byte0]: 36
7802 13:38:00.455083 [Byte1]: 36
7803 13:38:00.459298
7804 13:38:00.459376 Set Vref, RX VrefLevel [Byte0]: 37
7805 13:38:00.462883 [Byte1]: 37
7806 13:38:00.466575
7807 13:38:00.466652 Set Vref, RX VrefLevel [Byte0]: 38
7808 13:38:00.470089 [Byte1]: 38
7809 13:38:00.474279
7810 13:38:00.474354 Set Vref, RX VrefLevel [Byte0]: 39
7811 13:38:00.478098 [Byte1]: 39
7812 13:38:00.482345
7813 13:38:00.482421 Set Vref, RX VrefLevel [Byte0]: 40
7814 13:38:00.485425 [Byte1]: 40
7815 13:38:00.490028
7816 13:38:00.490103 Set Vref, RX VrefLevel [Byte0]: 41
7817 13:38:00.492984 [Byte1]: 41
7818 13:38:00.497202
7819 13:38:00.497275 Set Vref, RX VrefLevel [Byte0]: 42
7820 13:38:00.500628 [Byte1]: 42
7821 13:38:00.504902
7822 13:38:00.505010 Set Vref, RX VrefLevel [Byte0]: 43
7823 13:38:00.508547 [Byte1]: 43
7824 13:38:00.512782
7825 13:38:00.512882 Set Vref, RX VrefLevel [Byte0]: 44
7826 13:38:00.515895 [Byte1]: 44
7827 13:38:00.520209
7828 13:38:00.520283 Set Vref, RX VrefLevel [Byte0]: 45
7829 13:38:00.523472 [Byte1]: 45
7830 13:38:00.527913
7831 13:38:00.528014 Set Vref, RX VrefLevel [Byte0]: 46
7832 13:38:00.530808 [Byte1]: 46
7833 13:38:00.535479
7834 13:38:00.535560 Set Vref, RX VrefLevel [Byte0]: 47
7835 13:38:00.538630 [Byte1]: 47
7836 13:38:00.542896
7837 13:38:00.542998 Set Vref, RX VrefLevel [Byte0]: 48
7838 13:38:00.546173 [Byte1]: 48
7839 13:38:00.550332
7840 13:38:00.550411 Set Vref, RX VrefLevel [Byte0]: 49
7841 13:38:00.553989 [Byte1]: 49
7842 13:38:00.557946
7843 13:38:00.558032 Set Vref, RX VrefLevel [Byte0]: 50
7844 13:38:00.561323 [Byte1]: 50
7845 13:38:00.565794
7846 13:38:00.565876 Set Vref, RX VrefLevel [Byte0]: 51
7847 13:38:00.568831 [Byte1]: 51
7848 13:38:00.573374
7849 13:38:00.573454 Set Vref, RX VrefLevel [Byte0]: 52
7850 13:38:00.576898 [Byte1]: 52
7851 13:38:00.581241
7852 13:38:00.581337 Set Vref, RX VrefLevel [Byte0]: 53
7853 13:38:00.584340 [Byte1]: 53
7854 13:38:00.588752
7855 13:38:00.588830 Set Vref, RX VrefLevel [Byte0]: 54
7856 13:38:00.591773 [Byte1]: 54
7857 13:38:00.596304
7858 13:38:00.596385 Set Vref, RX VrefLevel [Byte0]: 55
7859 13:38:00.599658 [Byte1]: 55
7860 13:38:00.603679
7861 13:38:00.603756 Set Vref, RX VrefLevel [Byte0]: 56
7862 13:38:00.607157 [Byte1]: 56
7863 13:38:00.611361
7864 13:38:00.611464 Set Vref, RX VrefLevel [Byte0]: 57
7865 13:38:00.614902 [Byte1]: 57
7866 13:38:00.619271
7867 13:38:00.619364 Set Vref, RX VrefLevel [Byte0]: 58
7868 13:38:00.622385 [Byte1]: 58
7869 13:38:00.626850
7870 13:38:00.626931 Set Vref, RX VrefLevel [Byte0]: 59
7871 13:38:00.629825 [Byte1]: 59
7872 13:38:00.634098
7873 13:38:00.634232 Set Vref, RX VrefLevel [Byte0]: 60
7874 13:38:00.637584 [Byte1]: 60
7875 13:38:00.642352
7876 13:38:00.642439 Set Vref, RX VrefLevel [Byte0]: 61
7877 13:38:00.645202 [Byte1]: 61
7878 13:38:00.649473
7879 13:38:00.649558 Set Vref, RX VrefLevel [Byte0]: 62
7880 13:38:00.652851 [Byte1]: 62
7881 13:38:00.657406
7882 13:38:00.657480 Set Vref, RX VrefLevel [Byte0]: 63
7883 13:38:00.660164 [Byte1]: 63
7884 13:38:00.664867
7885 13:38:00.664967 Set Vref, RX VrefLevel [Byte0]: 64
7886 13:38:00.667897 [Byte1]: 64
7887 13:38:00.672429
7888 13:38:00.672503 Set Vref, RX VrefLevel [Byte0]: 65
7889 13:38:00.675950 [Byte1]: 65
7890 13:38:00.680205
7891 13:38:00.680282 Set Vref, RX VrefLevel [Byte0]: 66
7892 13:38:00.683246 [Byte1]: 66
7893 13:38:00.687654
7894 13:38:00.687736 Set Vref, RX VrefLevel [Byte0]: 67
7895 13:38:00.690771 [Byte1]: 67
7896 13:38:00.694980
7897 13:38:00.695090 Set Vref, RX VrefLevel [Byte0]: 68
7898 13:38:00.698726 [Byte1]: 68
7899 13:38:00.702808
7900 13:38:00.702902 Set Vref, RX VrefLevel [Byte0]: 69
7901 13:38:00.705837 [Byte1]: 69
7902 13:38:00.710053
7903 13:38:00.710136 Set Vref, RX VrefLevel [Byte0]: 70
7904 13:38:00.713556 [Byte1]: 70
7905 13:38:00.718269
7906 13:38:00.718354 Set Vref, RX VrefLevel [Byte0]: 71
7907 13:38:00.721297 [Byte1]: 71
7908 13:38:00.725605
7909 13:38:00.725677 Set Vref, RX VrefLevel [Byte0]: 72
7910 13:38:00.728654 [Byte1]: 72
7911 13:38:00.732990
7912 13:38:00.733067 Set Vref, RX VrefLevel [Byte0]: 73
7913 13:38:00.736845 [Byte1]: 73
7914 13:38:00.741024
7915 13:38:00.741103 Set Vref, RX VrefLevel [Byte0]: 74
7916 13:38:00.743958 [Byte1]: 74
7917 13:38:00.748857
7918 13:38:00.748936 Set Vref, RX VrefLevel [Byte0]: 75
7919 13:38:00.751855 [Byte1]: 75
7920 13:38:00.755821
7921 13:38:00.755907 Set Vref, RX VrefLevel [Byte0]: 76
7922 13:38:00.759207 [Byte1]: 76
7923 13:38:00.763589
7924 13:38:00.763671 Set Vref, RX VrefLevel [Byte0]: 77
7925 13:38:00.767329 [Byte1]: 77
7926 13:38:00.771304
7927 13:38:00.771387 Final RX Vref Byte 0 = 58 to rank0
7928 13:38:00.774325 Final RX Vref Byte 1 = 61 to rank0
7929 13:38:00.777685 Final RX Vref Byte 0 = 58 to rank1
7930 13:38:00.781143 Final RX Vref Byte 1 = 61 to rank1==
7931 13:38:00.784889 Dram Type= 6, Freq= 0, CH_0, rank 0
7932 13:38:00.791524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7933 13:38:00.791615 ==
7934 13:38:00.791692 DQS Delay:
7935 13:38:00.791754 DQS0 = 0, DQS1 = 0
7936 13:38:00.794489 DQM Delay:
7937 13:38:00.794564 DQM0 = 129, DQM1 = 121
7938 13:38:00.798225 DQ Delay:
7939 13:38:00.801382 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
7940 13:38:00.804437 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
7941 13:38:00.807900 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7942 13:38:00.811455 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7943 13:38:00.811538
7944 13:38:00.811610
7945 13:38:00.811671
7946 13:38:00.814594 [DramC_TX_OE_Calibration] TA2
7947 13:38:00.818057 Original DQ_B0 (3 6) =30, OEN = 27
7948 13:38:00.821537 Original DQ_B1 (3 6) =30, OEN = 27
7949 13:38:00.824938 24, 0x0, End_B0=24 End_B1=24
7950 13:38:00.825036 25, 0x0, End_B0=25 End_B1=25
7951 13:38:00.827995 26, 0x0, End_B0=26 End_B1=26
7952 13:38:00.831258 27, 0x0, End_B0=27 End_B1=27
7953 13:38:00.834749 28, 0x0, End_B0=28 End_B1=28
7954 13:38:00.834832 29, 0x0, End_B0=29 End_B1=29
7955 13:38:00.837869 30, 0x0, End_B0=30 End_B1=30
7956 13:38:00.841619 31, 0x4141, End_B0=30 End_B1=30
7957 13:38:00.844424 Byte0 end_step=30 best_step=27
7958 13:38:00.848262 Byte1 end_step=30 best_step=27
7959 13:38:00.851343 Byte0 TX OE(2T, 0.5T) = (3, 3)
7960 13:38:00.851461 Byte1 TX OE(2T, 0.5T) = (3, 3)
7961 13:38:00.851556
7962 13:38:00.854908
7963 13:38:00.861497 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7964 13:38:00.864826 CH0 RK0: MR19=303, MR18=1509
7965 13:38:00.871033 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7966 13:38:00.871147
7967 13:38:00.874656 ----->DramcWriteLeveling(PI) begin...
7968 13:38:00.874764 ==
7969 13:38:00.878164 Dram Type= 6, Freq= 0, CH_0, rank 1
7970 13:38:00.881213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 13:38:00.881296 ==
7972 13:38:00.884922 Write leveling (Byte 0): 33 => 33
7973 13:38:00.888217 Write leveling (Byte 1): 26 => 26
7974 13:38:00.891271 DramcWriteLeveling(PI) end<-----
7975 13:38:00.891382
7976 13:38:00.891486 ==
7977 13:38:00.894455 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 13:38:00.898264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 13:38:00.898371 ==
7980 13:38:00.901193 [Gating] SW mode calibration
7981 13:38:00.908043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7982 13:38:00.914639 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7983 13:38:00.917818 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 13:38:00.921410 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 13:38:00.927684 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7986 13:38:00.931227 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7987 13:38:00.934878 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7988 13:38:00.941027 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7989 13:38:00.944843 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 13:38:00.947952 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 13:38:00.954780 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 13:38:00.957708 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 13:38:00.961484 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7994 13:38:00.964331 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7995 13:38:00.971321 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7996 13:38:00.974285 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7997 13:38:00.978125 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7998 13:38:00.984649 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 13:38:00.987505 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 13:38:00.991160 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 13:38:00.997753 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8002 13:38:01.001381 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8003 13:38:01.004556 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8004 13:38:01.010817 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
8005 13:38:01.014436 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 13:38:01.017495 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 13:38:01.024410 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 13:38:01.027879 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 13:38:01.030825 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 13:38:01.037771 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8011 13:38:01.041364 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8012 13:38:01.044260 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8013 13:38:01.051015 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8014 13:38:01.054670 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 13:38:01.057602 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 13:38:01.061223 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 13:38:01.067981 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 13:38:01.070969 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 13:38:01.074640 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 13:38:01.081206 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 13:38:01.084753 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 13:38:01.087764 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 13:38:01.094870 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 13:38:01.098123 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 13:38:01.101101 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8026 13:38:01.107898 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8027 13:38:01.108000 Total UI for P1: 0, mck2ui 16
8028 13:38:01.114598 best dqsien dly found for B0: ( 1, 9, 8)
8029 13:38:01.118441 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8030 13:38:01.121339 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8031 13:38:01.125140 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 13:38:01.128060 Total UI for P1: 0, mck2ui 16
8033 13:38:01.131679 best dqsien dly found for B1: ( 1, 9, 18)
8034 13:38:01.134719 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8035 13:38:01.138305 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8036 13:38:01.141382
8037 13:38:01.144931 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8038 13:38:01.147841 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8039 13:38:01.151576 [Gating] SW calibration Done
8040 13:38:01.151653 ==
8041 13:38:01.154626 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 13:38:01.158334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 13:38:01.158448 ==
8044 13:38:01.161256 RX Vref Scan: 0
8045 13:38:01.161326
8046 13:38:01.161385 RX Vref 0 -> 0, step: 1
8047 13:38:01.161445
8048 13:38:01.165127 RX Delay 0 -> 252, step: 8
8049 13:38:01.168167 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8050 13:38:01.171029 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8051 13:38:01.177909 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8052 13:38:01.181281 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8053 13:38:01.184795 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8054 13:38:01.187799 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8055 13:38:01.190945 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8056 13:38:01.197684 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8057 13:38:01.200984 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8058 13:38:01.204486 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8059 13:38:01.208007 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8060 13:38:01.211620 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8061 13:38:01.217621 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8062 13:38:01.220790 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8063 13:38:01.224325 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8064 13:38:01.227828 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8065 13:38:01.227927 ==
8066 13:38:01.230909 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 13:38:01.237593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 13:38:01.237669 ==
8069 13:38:01.237734 DQS Delay:
8070 13:38:01.241049 DQS0 = 0, DQS1 = 0
8071 13:38:01.241119 DQM Delay:
8072 13:38:01.241177 DQM0 = 131, DQM1 = 124
8073 13:38:01.244670 DQ Delay:
8074 13:38:01.247632 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8075 13:38:01.251169 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8076 13:38:01.254555 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8077 13:38:01.258107 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8078 13:38:01.258207
8079 13:38:01.258297
8080 13:38:01.258385 ==
8081 13:38:01.261227 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 13:38:01.264825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 13:38:01.264926 ==
8084 13:38:01.267834
8085 13:38:01.267943
8086 13:38:01.268049 TX Vref Scan disable
8087 13:38:01.270984 == TX Byte 0 ==
8088 13:38:01.274787 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8089 13:38:01.278031 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8090 13:38:01.281430 == TX Byte 1 ==
8091 13:38:01.284493 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8092 13:38:01.287936 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8093 13:38:01.288043 ==
8094 13:38:01.290901 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 13:38:01.297621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 13:38:01.297742 ==
8097 13:38:01.311680
8098 13:38:01.315168 TX Vref early break, caculate TX vref
8099 13:38:01.318043 TX Vref=16, minBit 3, minWin=22, winSum=374
8100 13:38:01.321576 TX Vref=18, minBit 9, minWin=22, winSum=379
8101 13:38:01.325303 TX Vref=20, minBit 8, minWin=23, winSum=392
8102 13:38:01.328110 TX Vref=22, minBit 9, minWin=23, winSum=397
8103 13:38:01.331666 TX Vref=24, minBit 1, minWin=25, winSum=407
8104 13:38:01.338405 TX Vref=26, minBit 3, minWin=25, winSum=417
8105 13:38:01.341465 TX Vref=28, minBit 3, minWin=25, winSum=422
8106 13:38:01.345196 TX Vref=30, minBit 10, minWin=25, winSum=421
8107 13:38:01.348217 TX Vref=32, minBit 0, minWin=25, winSum=412
8108 13:38:01.351231 TX Vref=34, minBit 4, minWin=24, winSum=404
8109 13:38:01.355105 TX Vref=36, minBit 0, minWin=24, winSum=392
8110 13:38:01.361348 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 28
8111 13:38:01.361426
8112 13:38:01.364729 Final TX Range 0 Vref 28
8113 13:38:01.364831
8114 13:38:01.364920 ==
8115 13:38:01.368020 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 13:38:01.371480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 13:38:01.371578 ==
8118 13:38:01.371667
8119 13:38:01.371752
8120 13:38:01.374618 TX Vref Scan disable
8121 13:38:01.381488 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8122 13:38:01.381649 == TX Byte 0 ==
8123 13:38:01.385122 u2DelayCellOfst[0]=14 cells (4 PI)
8124 13:38:01.387922 u2DelayCellOfst[1]=21 cells (6 PI)
8125 13:38:01.391483 u2DelayCellOfst[2]=10 cells (3 PI)
8126 13:38:01.395005 u2DelayCellOfst[3]=10 cells (3 PI)
8127 13:38:01.397929 u2DelayCellOfst[4]=10 cells (3 PI)
8128 13:38:01.401773 u2DelayCellOfst[5]=0 cells (0 PI)
8129 13:38:01.404913 u2DelayCellOfst[6]=21 cells (6 PI)
8130 13:38:01.408066 u2DelayCellOfst[7]=17 cells (5 PI)
8131 13:38:01.411640 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8132 13:38:01.415207 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8133 13:38:01.418132 == TX Byte 1 ==
8134 13:38:01.421882 u2DelayCellOfst[8]=0 cells (0 PI)
8135 13:38:01.421985 u2DelayCellOfst[9]=0 cells (0 PI)
8136 13:38:01.424719 u2DelayCellOfst[10]=3 cells (1 PI)
8137 13:38:01.428401 u2DelayCellOfst[11]=0 cells (0 PI)
8138 13:38:01.431378 u2DelayCellOfst[12]=10 cells (3 PI)
8139 13:38:01.435016 u2DelayCellOfst[13]=10 cells (3 PI)
8140 13:38:01.438453 u2DelayCellOfst[14]=14 cells (4 PI)
8141 13:38:01.441685 u2DelayCellOfst[15]=10 cells (3 PI)
8142 13:38:01.445263 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8143 13:38:01.451771 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8144 13:38:01.451867 DramC Write-DBI on
8145 13:38:01.451971 ==
8146 13:38:01.454840 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 13:38:01.458098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 13:38:01.461755 ==
8149 13:38:01.461876
8150 13:38:01.461969
8151 13:38:01.462070 TX Vref Scan disable
8152 13:38:01.465449 == TX Byte 0 ==
8153 13:38:01.468669 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8154 13:38:01.471497 == TX Byte 1 ==
8155 13:38:01.475056 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8156 13:38:01.478740 DramC Write-DBI off
8157 13:38:01.478871
8158 13:38:01.478994 [DATLAT]
8159 13:38:01.479094 Freq=1600, CH0 RK1
8160 13:38:01.479198
8161 13:38:01.481776 DATLAT Default: 0xf
8162 13:38:01.481900 0, 0xFFFF, sum = 0
8163 13:38:01.485423 1, 0xFFFF, sum = 0
8164 13:38:01.485542 2, 0xFFFF, sum = 0
8165 13:38:01.488498 3, 0xFFFF, sum = 0
8166 13:38:01.488615 4, 0xFFFF, sum = 0
8167 13:38:01.492307 5, 0xFFFF, sum = 0
8168 13:38:01.495194 6, 0xFFFF, sum = 0
8169 13:38:01.495299 7, 0xFFFF, sum = 0
8170 13:38:01.498596 8, 0xFFFF, sum = 0
8171 13:38:01.498683 9, 0xFFFF, sum = 0
8172 13:38:01.502080 10, 0xFFFF, sum = 0
8173 13:38:01.502212 11, 0xFFFF, sum = 0
8174 13:38:01.505123 12, 0xFFFF, sum = 0
8175 13:38:01.505267 13, 0xFFFF, sum = 0
8176 13:38:01.508825 14, 0x0, sum = 1
8177 13:38:01.508939 15, 0x0, sum = 2
8178 13:38:01.511816 16, 0x0, sum = 3
8179 13:38:01.511900 17, 0x0, sum = 4
8180 13:38:01.515548 best_step = 15
8181 13:38:01.515631
8182 13:38:01.515697 ==
8183 13:38:01.518535 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 13:38:01.522021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 13:38:01.522105 ==
8186 13:38:01.522171 RX Vref Scan: 0
8187 13:38:01.522233
8188 13:38:01.525562 RX Vref 0 -> 0, step: 1
8189 13:38:01.525645
8190 13:38:01.528530 RX Delay 11 -> 252, step: 4
8191 13:38:01.532132 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8192 13:38:01.538909 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8193 13:38:01.542049 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8194 13:38:01.544883 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8195 13:38:01.548311 iDelay=191, Bit 4, Center 126 (71 ~ 182) 112
8196 13:38:01.552071 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8197 13:38:01.558467 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8198 13:38:01.562052 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8199 13:38:01.565186 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8200 13:38:01.568722 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8201 13:38:01.571956 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8202 13:38:01.578233 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8203 13:38:01.581501 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8204 13:38:01.585106 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8205 13:38:01.588261 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8206 13:38:01.591834 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8207 13:38:01.595049 ==
8208 13:38:01.595134 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 13:38:01.601619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 13:38:01.601704 ==
8211 13:38:01.601771 DQS Delay:
8212 13:38:01.605057 DQS0 = 0, DQS1 = 0
8213 13:38:01.605141 DQM Delay:
8214 13:38:01.608611 DQM0 = 127, DQM1 = 122
8215 13:38:01.608721 DQ Delay:
8216 13:38:01.611607 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8217 13:38:01.614737 DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136
8218 13:38:01.618474 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8219 13:38:01.621556 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8220 13:38:01.621640
8221 13:38:01.621706
8222 13:38:01.621767
8223 13:38:01.625106 [DramC_TX_OE_Calibration] TA2
8224 13:38:01.628119 Original DQ_B0 (3 6) =30, OEN = 27
8225 13:38:01.631573 Original DQ_B1 (3 6) =30, OEN = 27
8226 13:38:01.635153 24, 0x0, End_B0=24 End_B1=24
8227 13:38:01.638280 25, 0x0, End_B0=25 End_B1=25
8228 13:38:01.638365 26, 0x0, End_B0=26 End_B1=26
8229 13:38:01.641848 27, 0x0, End_B0=27 End_B1=27
8230 13:38:01.644910 28, 0x0, End_B0=28 End_B1=28
8231 13:38:01.648740 29, 0x0, End_B0=29 End_B1=29
8232 13:38:01.648857 30, 0x0, End_B0=30 End_B1=30
8233 13:38:01.651716 31, 0x4545, End_B0=30 End_B1=30
8234 13:38:01.655305 Byte0 end_step=30 best_step=27
8235 13:38:01.658222 Byte1 end_step=30 best_step=27
8236 13:38:01.661837 Byte0 TX OE(2T, 0.5T) = (3, 3)
8237 13:38:01.664892 Byte1 TX OE(2T, 0.5T) = (3, 3)
8238 13:38:01.665016
8239 13:38:01.665083
8240 13:38:01.671769 [DQSOSCAuto] RK1, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8241 13:38:01.674752 CH0 RK1: MR19=303, MR18=180E
8242 13:38:01.681527 CH0_RK1: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8243 13:38:01.685427 [RxdqsGatingPostProcess] freq 1600
8244 13:38:01.688186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8245 13:38:01.691753 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 13:38:01.695181 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 13:38:01.698175 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 13:38:01.702036 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 13:38:01.705223 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 13:38:01.708602 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 13:38:01.711696 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 13:38:01.715700 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 13:38:01.718737 Pre-setting of DQS Precalculation
8254 13:38:01.721861 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8255 13:38:01.721952 ==
8256 13:38:01.725319 Dram Type= 6, Freq= 0, CH_1, rank 0
8257 13:38:01.728380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 13:38:01.728461 ==
8259 13:38:01.734995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 13:38:01.738587 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 13:38:01.745102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 13:38:01.748813 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 13:38:01.758224 [CA 0] Center 43 (14~72) winsize 59
8264 13:38:01.761851 [CA 1] Center 43 (14~72) winsize 59
8265 13:38:01.765107 [CA 2] Center 38 (10~67) winsize 58
8266 13:38:01.768525 [CA 3] Center 37 (8~66) winsize 59
8267 13:38:01.771469 [CA 4] Center 38 (9~68) winsize 60
8268 13:38:01.775354 [CA 5] Center 37 (8~66) winsize 59
8269 13:38:01.775438
8270 13:38:01.778327 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8271 13:38:01.778428
8272 13:38:01.781394 [CATrainingPosCal] consider 1 rank data
8273 13:38:01.785149 u2DelayCellTimex100 = 275/100 ps
8274 13:38:01.788223 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8275 13:38:01.794916 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8276 13:38:01.798573 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8277 13:38:01.801903 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8278 13:38:01.805352 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8279 13:38:01.808377 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8280 13:38:01.808461
8281 13:38:01.811542 CA PerBit enable=1, Macro0, CA PI delay=37
8282 13:38:01.811626
8283 13:38:01.814972 [CBTSetCACLKResult] CA Dly = 37
8284 13:38:01.818460 CS Dly: 8 (0~39)
8285 13:38:01.822080 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 13:38:01.825078 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 13:38:01.825163 ==
8288 13:38:01.828178 Dram Type= 6, Freq= 0, CH_1, rank 1
8289 13:38:01.831937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 13:38:01.832022 ==
8291 13:38:01.838601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 13:38:01.841600 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 13:38:01.848670 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 13:38:01.851784 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 13:38:01.861383 [CA 0] Center 42 (13~72) winsize 60
8296 13:38:01.865163 [CA 1] Center 43 (15~72) winsize 58
8297 13:38:01.868142 [CA 2] Center 37 (8~66) winsize 59
8298 13:38:01.871870 [CA 3] Center 37 (8~66) winsize 59
8299 13:38:01.874922 [CA 4] Center 37 (8~67) winsize 60
8300 13:38:01.878570 [CA 5] Center 36 (7~66) winsize 60
8301 13:38:01.878686
8302 13:38:01.881532 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 13:38:01.881632
8304 13:38:01.885220 [CATrainingPosCal] consider 2 rank data
8305 13:38:01.888272 u2DelayCellTimex100 = 275/100 ps
8306 13:38:01.892078 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8307 13:38:01.895222 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8308 13:38:01.902159 CA2 delay=38 (10~66),Diff = 1 PI (3 cell)
8309 13:38:01.904944 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8310 13:38:01.908523 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8311 13:38:01.912080 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8312 13:38:01.912164
8313 13:38:01.915039 CA PerBit enable=1, Macro0, CA PI delay=37
8314 13:38:01.915122
8315 13:38:01.918571 [CBTSetCACLKResult] CA Dly = 37
8316 13:38:01.918656 CS Dly: 11 (0~45)
8317 13:38:01.925129 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 13:38:01.928466 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 13:38:01.928587
8320 13:38:01.932098 ----->DramcWriteLeveling(PI) begin...
8321 13:38:01.932189 ==
8322 13:38:01.935173 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 13:38:01.938249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 13:38:01.938328 ==
8325 13:38:01.941962 Write leveling (Byte 0): 26 => 26
8326 13:38:01.944965 Write leveling (Byte 1): 29 => 29
8327 13:38:01.948600 DramcWriteLeveling(PI) end<-----
8328 13:38:01.948672
8329 13:38:01.948733 ==
8330 13:38:01.952019 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 13:38:01.955472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 13:38:01.958577 ==
8333 13:38:01.958654 [Gating] SW mode calibration
8334 13:38:01.965278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8335 13:38:01.972083 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8336 13:38:01.975705 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 13:38:01.982015 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 13:38:01.985426 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 13:38:01.988624 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 13:38:01.995814 1 4 16 | B1->B0 | 2c2c 2626 | 0 0 | (0 0) (0 0)
8341 13:38:01.998833 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8342 13:38:02.002061 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 13:38:02.005697 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 13:38:02.011834 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 13:38:02.015379 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 13:38:02.018969 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 13:38:02.025573 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8348 13:38:02.028710 1 5 16 | B1->B0 | 2f2f 3232 | 1 1 | (1 0) (1 0)
8349 13:38:02.032227 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8350 13:38:02.039114 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 13:38:02.042061 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 13:38:02.045060 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 13:38:02.052264 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 13:38:02.055199 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 13:38:02.058697 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8356 13:38:02.065501 1 6 16 | B1->B0 | 3d3d 3030 | 0 1 | (1 1) (0 0)
8357 13:38:02.068394 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 13:38:02.072183 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 13:38:02.079084 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 13:38:02.082031 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 13:38:02.085224 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 13:38:02.091814 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 13:38:02.095543 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 13:38:02.098990 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8365 13:38:02.105683 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8366 13:38:02.108639 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 13:38:02.112323 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 13:38:02.115322 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 13:38:02.122084 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 13:38:02.125648 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 13:38:02.128487 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 13:38:02.135510 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 13:38:02.139245 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 13:38:02.141980 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 13:38:02.149115 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 13:38:02.152235 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 13:38:02.155301 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 13:38:02.162312 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 13:38:02.165275 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8380 13:38:02.168680 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 13:38:02.175331 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 13:38:02.175463 Total UI for P1: 0, mck2ui 16
8383 13:38:02.182169 best dqsien dly found for B0: ( 1, 9, 16)
8384 13:38:02.182263 Total UI for P1: 0, mck2ui 16
8385 13:38:02.185790 best dqsien dly found for B1: ( 1, 9, 14)
8386 13:38:02.191935 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8387 13:38:02.195613 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8388 13:38:02.195696
8389 13:38:02.198717 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8390 13:38:02.202534 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8391 13:38:02.205584 [Gating] SW calibration Done
8392 13:38:02.205688 ==
8393 13:38:02.209007 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 13:38:02.212275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 13:38:02.212369 ==
8396 13:38:02.215939 RX Vref Scan: 0
8397 13:38:02.216023
8398 13:38:02.216085 RX Vref 0 -> 0, step: 1
8399 13:38:02.216144
8400 13:38:02.218846 RX Delay 0 -> 252, step: 8
8401 13:38:02.222588 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8402 13:38:02.225648 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8403 13:38:02.232336 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8404 13:38:02.235780 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8405 13:38:02.238923 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8406 13:38:02.242483 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8407 13:38:02.245763 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8408 13:38:02.252476 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8409 13:38:02.255533 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8410 13:38:02.259236 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8411 13:38:02.262298 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8412 13:38:02.265762 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8413 13:38:02.272369 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8414 13:38:02.275579 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8415 13:38:02.278795 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8416 13:38:02.282461 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8417 13:38:02.282544 ==
8418 13:38:02.285641 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 13:38:02.292346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 13:38:02.292429 ==
8421 13:38:02.292510 DQS Delay:
8422 13:38:02.292571 DQS0 = 0, DQS1 = 0
8423 13:38:02.295395 DQM Delay:
8424 13:38:02.295477 DQM0 = 134, DQM1 = 127
8425 13:38:02.298643 DQ Delay:
8426 13:38:02.302319 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8427 13:38:02.305416 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8428 13:38:02.308490 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8429 13:38:02.312495 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8430 13:38:02.312572
8431 13:38:02.312651
8432 13:38:02.312723 ==
8433 13:38:02.315312 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 13:38:02.318847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 13:38:02.322114 ==
8436 13:38:02.322198
8437 13:38:02.322271
8438 13:38:02.322369 TX Vref Scan disable
8439 13:38:02.325675 == TX Byte 0 ==
8440 13:38:02.328658 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8441 13:38:02.332524 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8442 13:38:02.335487 == TX Byte 1 ==
8443 13:38:02.338843 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8444 13:38:02.342394 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8445 13:38:02.342467 ==
8446 13:38:02.345546 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 13:38:02.351981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 13:38:02.352057 ==
8449 13:38:02.364112
8450 13:38:02.367198 TX Vref early break, caculate TX vref
8451 13:38:02.370200 TX Vref=16, minBit 8, minWin=21, winSum=361
8452 13:38:02.374113 TX Vref=18, minBit 8, minWin=21, winSum=368
8453 13:38:02.377368 TX Vref=20, minBit 8, minWin=22, winSum=379
8454 13:38:02.380799 TX Vref=22, minBit 8, minWin=22, winSum=391
8455 13:38:02.383597 TX Vref=24, minBit 8, minWin=23, winSum=399
8456 13:38:02.387240 TX Vref=26, minBit 8, minWin=24, winSum=407
8457 13:38:02.394076 TX Vref=28, minBit 3, minWin=25, winSum=417
8458 13:38:02.397147 TX Vref=30, minBit 8, minWin=25, winSum=416
8459 13:38:02.400896 TX Vref=32, minBit 0, minWin=24, winSum=403
8460 13:38:02.404038 TX Vref=34, minBit 9, minWin=23, winSum=395
8461 13:38:02.410914 [TxChooseVref] Worse bit 3, Min win 25, Win sum 417, Final Vref 28
8462 13:38:02.411028
8463 13:38:02.413843 Final TX Range 0 Vref 28
8464 13:38:02.413913
8465 13:38:02.413972 ==
8466 13:38:02.417445 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 13:38:02.420610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 13:38:02.420696 ==
8469 13:38:02.420756
8470 13:38:02.420812
8471 13:38:02.423610 TX Vref Scan disable
8472 13:38:02.427235 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8473 13:38:02.430724 == TX Byte 0 ==
8474 13:38:02.434038 u2DelayCellOfst[0]=14 cells (4 PI)
8475 13:38:02.437374 u2DelayCellOfst[1]=14 cells (4 PI)
8476 13:38:02.440494 u2DelayCellOfst[2]=0 cells (0 PI)
8477 13:38:02.444019 u2DelayCellOfst[3]=7 cells (2 PI)
8478 13:38:02.447371 u2DelayCellOfst[4]=7 cells (2 PI)
8479 13:38:02.450223 u2DelayCellOfst[5]=21 cells (6 PI)
8480 13:38:02.450352 u2DelayCellOfst[6]=17 cells (5 PI)
8481 13:38:02.454053 u2DelayCellOfst[7]=7 cells (2 PI)
8482 13:38:02.460665 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8483 13:38:02.463731 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8484 13:38:02.463823 == TX Byte 1 ==
8485 13:38:02.467094 u2DelayCellOfst[8]=0 cells (0 PI)
8486 13:38:02.470420 u2DelayCellOfst[9]=3 cells (1 PI)
8487 13:38:02.473917 u2DelayCellOfst[10]=7 cells (2 PI)
8488 13:38:02.476999 u2DelayCellOfst[11]=3 cells (1 PI)
8489 13:38:02.480622 u2DelayCellOfst[12]=10 cells (3 PI)
8490 13:38:02.483920 u2DelayCellOfst[13]=14 cells (4 PI)
8491 13:38:02.486969 u2DelayCellOfst[14]=14 cells (4 PI)
8492 13:38:02.490370 u2DelayCellOfst[15]=14 cells (4 PI)
8493 13:38:02.494058 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8494 13:38:02.497106 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8495 13:38:02.500832 DramC Write-DBI on
8496 13:38:02.500914 ==
8497 13:38:02.503891 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 13:38:02.506964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 13:38:02.507047 ==
8500 13:38:02.507123
8501 13:38:02.507187
8502 13:38:02.510771 TX Vref Scan disable
8503 13:38:02.514389 == TX Byte 0 ==
8504 13:38:02.517528 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8505 13:38:02.517652 == TX Byte 1 ==
8506 13:38:02.524148 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8507 13:38:02.524235 DramC Write-DBI off
8508 13:38:02.524301
8509 13:38:02.524363 [DATLAT]
8510 13:38:02.527583 Freq=1600, CH1 RK0
8511 13:38:02.527675
8512 13:38:02.530645 DATLAT Default: 0xf
8513 13:38:02.530742 0, 0xFFFF, sum = 0
8514 13:38:02.533876 1, 0xFFFF, sum = 0
8515 13:38:02.533950 2, 0xFFFF, sum = 0
8516 13:38:02.537067 3, 0xFFFF, sum = 0
8517 13:38:02.537154 4, 0xFFFF, sum = 0
8518 13:38:02.540991 5, 0xFFFF, sum = 0
8519 13:38:02.541092 6, 0xFFFF, sum = 0
8520 13:38:02.543889 7, 0xFFFF, sum = 0
8521 13:38:02.543964 8, 0xFFFF, sum = 0
8522 13:38:02.547220 9, 0xFFFF, sum = 0
8523 13:38:02.547292 10, 0xFFFF, sum = 0
8524 13:38:02.550482 11, 0xFFFF, sum = 0
8525 13:38:02.550556 12, 0xFFFF, sum = 0
8526 13:38:02.554144 13, 0xFFFF, sum = 0
8527 13:38:02.554224 14, 0x0, sum = 1
8528 13:38:02.557422 15, 0x0, sum = 2
8529 13:38:02.557501 16, 0x0, sum = 3
8530 13:38:02.560843 17, 0x0, sum = 4
8531 13:38:02.560925 best_step = 15
8532 13:38:02.560996
8533 13:38:02.561056 ==
8534 13:38:02.564228 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 13:38:02.571149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 13:38:02.571234 ==
8537 13:38:02.571304 RX Vref Scan: 1
8538 13:38:02.571366
8539 13:38:02.574082 Set Vref Range= 24 -> 127
8540 13:38:02.574165
8541 13:38:02.577491 RX Vref 24 -> 127, step: 1
8542 13:38:02.577574
8543 13:38:02.577639 RX Delay 19 -> 252, step: 4
8544 13:38:02.577699
8545 13:38:02.580874 Set Vref, RX VrefLevel [Byte0]: 24
8546 13:38:02.583822 [Byte1]: 24
8547 13:38:02.587831
8548 13:38:02.587911 Set Vref, RX VrefLevel [Byte0]: 25
8549 13:38:02.591124 [Byte1]: 25
8550 13:38:02.595700
8551 13:38:02.595774 Set Vref, RX VrefLevel [Byte0]: 26
8552 13:38:02.598867 [Byte1]: 26
8553 13:38:02.603156
8554 13:38:02.603239 Set Vref, RX VrefLevel [Byte0]: 27
8555 13:38:02.606250 [Byte1]: 27
8556 13:38:02.610693
8557 13:38:02.610776 Set Vref, RX VrefLevel [Byte0]: 28
8558 13:38:02.614263 [Byte1]: 28
8559 13:38:02.618650
8560 13:38:02.618727 Set Vref, RX VrefLevel [Byte0]: 29
8561 13:38:02.621782 [Byte1]: 29
8562 13:38:02.626034
8563 13:38:02.626109 Set Vref, RX VrefLevel [Byte0]: 30
8564 13:38:02.629047 [Byte1]: 30
8565 13:38:02.633252
8566 13:38:02.633332 Set Vref, RX VrefLevel [Byte0]: 31
8567 13:38:02.637075 [Byte1]: 31
8568 13:38:02.641255
8569 13:38:02.641328 Set Vref, RX VrefLevel [Byte0]: 32
8570 13:38:02.644283 [Byte1]: 32
8571 13:38:02.648583
8572 13:38:02.648656 Set Vref, RX VrefLevel [Byte0]: 33
8573 13:38:02.652322 [Byte1]: 33
8574 13:38:02.656634
8575 13:38:02.656755 Set Vref, RX VrefLevel [Byte0]: 34
8576 13:38:02.659333 [Byte1]: 34
8577 13:38:02.663902
8578 13:38:02.663999 Set Vref, RX VrefLevel [Byte0]: 35
8579 13:38:02.667179 [Byte1]: 35
8580 13:38:02.671855
8581 13:38:02.671958 Set Vref, RX VrefLevel [Byte0]: 36
8582 13:38:02.674573 [Byte1]: 36
8583 13:38:02.679369
8584 13:38:02.679473 Set Vref, RX VrefLevel [Byte0]: 37
8585 13:38:02.682291 [Byte1]: 37
8586 13:38:02.686360
8587 13:38:02.686457 Set Vref, RX VrefLevel [Byte0]: 38
8588 13:38:02.689682 [Byte1]: 38
8589 13:38:02.693899
8590 13:38:02.694012 Set Vref, RX VrefLevel [Byte0]: 39
8591 13:38:02.697279 [Byte1]: 39
8592 13:38:02.701705
8593 13:38:02.701823 Set Vref, RX VrefLevel [Byte0]: 40
8594 13:38:02.705172 [Byte1]: 40
8595 13:38:02.709339
8596 13:38:02.709420 Set Vref, RX VrefLevel [Byte0]: 41
8597 13:38:02.712512 [Byte1]: 41
8598 13:38:02.716645
8599 13:38:02.716726 Set Vref, RX VrefLevel [Byte0]: 42
8600 13:38:02.720390 [Byte1]: 42
8601 13:38:02.724082
8602 13:38:02.724182 Set Vref, RX VrefLevel [Byte0]: 43
8603 13:38:02.727713 [Byte1]: 43
8604 13:38:02.732144
8605 13:38:02.732241 Set Vref, RX VrefLevel [Byte0]: 44
8606 13:38:02.735213 [Byte1]: 44
8607 13:38:02.739302
8608 13:38:02.739385 Set Vref, RX VrefLevel [Byte0]: 45
8609 13:38:02.742464 [Byte1]: 45
8610 13:38:02.747265
8611 13:38:02.747348 Set Vref, RX VrefLevel [Byte0]: 46
8612 13:38:02.750447 [Byte1]: 46
8613 13:38:02.754938
8614 13:38:02.755050 Set Vref, RX VrefLevel [Byte0]: 47
8615 13:38:02.757918 [Byte1]: 47
8616 13:38:02.762013
8617 13:38:02.762092 Set Vref, RX VrefLevel [Byte0]: 48
8618 13:38:02.765689 [Byte1]: 48
8619 13:38:02.769982
8620 13:38:02.770063 Set Vref, RX VrefLevel [Byte0]: 49
8621 13:38:02.772839 [Byte1]: 49
8622 13:38:02.777574
8623 13:38:02.777664 Set Vref, RX VrefLevel [Byte0]: 50
8624 13:38:02.780890 [Byte1]: 50
8625 13:38:02.784647
8626 13:38:02.784726 Set Vref, RX VrefLevel [Byte0]: 51
8627 13:38:02.787985 [Byte1]: 51
8628 13:38:02.792293
8629 13:38:02.792373 Set Vref, RX VrefLevel [Byte0]: 52
8630 13:38:02.795882 [Byte1]: 52
8631 13:38:02.799835
8632 13:38:02.799914 Set Vref, RX VrefLevel [Byte0]: 53
8633 13:38:02.803346 [Byte1]: 53
8634 13:38:02.807425
8635 13:38:02.807501 Set Vref, RX VrefLevel [Byte0]: 54
8636 13:38:02.811302 [Byte1]: 54
8637 13:38:02.814964
8638 13:38:02.815038 Set Vref, RX VrefLevel [Byte0]: 55
8639 13:38:02.818434 [Byte1]: 55
8640 13:38:02.822653
8641 13:38:02.822734 Set Vref, RX VrefLevel [Byte0]: 56
8642 13:38:02.825806 [Byte1]: 56
8643 13:38:02.830087
8644 13:38:02.830166 Set Vref, RX VrefLevel [Byte0]: 57
8645 13:38:02.833843 [Byte1]: 57
8646 13:38:02.838177
8647 13:38:02.838253 Set Vref, RX VrefLevel [Byte0]: 58
8648 13:38:02.841069 [Byte1]: 58
8649 13:38:02.845452
8650 13:38:02.845527 Set Vref, RX VrefLevel [Byte0]: 59
8651 13:38:02.849140 [Byte1]: 59
8652 13:38:02.852829
8653 13:38:02.852934 Set Vref, RX VrefLevel [Byte0]: 60
8654 13:38:02.856599 [Byte1]: 60
8655 13:38:02.861075
8656 13:38:02.861158 Set Vref, RX VrefLevel [Byte0]: 61
8657 13:38:02.863925 [Byte1]: 61
8658 13:38:02.868165
8659 13:38:02.868248 Set Vref, RX VrefLevel [Byte0]: 62
8660 13:38:02.871651 [Byte1]: 62
8661 13:38:02.876046
8662 13:38:02.876126 Set Vref, RX VrefLevel [Byte0]: 63
8663 13:38:02.879166 [Byte1]: 63
8664 13:38:02.883398
8665 13:38:02.883480 Set Vref, RX VrefLevel [Byte0]: 64
8666 13:38:02.886460 [Byte1]: 64
8667 13:38:02.890933
8668 13:38:02.891022 Set Vref, RX VrefLevel [Byte0]: 65
8669 13:38:02.894144 [Byte1]: 65
8670 13:38:02.898572
8671 13:38:02.898656 Set Vref, RX VrefLevel [Byte0]: 66
8672 13:38:02.901791 [Byte1]: 66
8673 13:38:02.906244
8674 13:38:02.906327 Set Vref, RX VrefLevel [Byte0]: 67
8675 13:38:02.909199 [Byte1]: 67
8676 13:38:02.913710
8677 13:38:02.913794 Set Vref, RX VrefLevel [Byte0]: 68
8678 13:38:02.917048 [Byte1]: 68
8679 13:38:02.920990
8680 13:38:02.921084 Set Vref, RX VrefLevel [Byte0]: 69
8681 13:38:02.924264 [Byte1]: 69
8682 13:38:02.928971
8683 13:38:02.929067 Set Vref, RX VrefLevel [Byte0]: 70
8684 13:38:02.932119 [Byte1]: 70
8685 13:38:02.936255
8686 13:38:02.936339 Set Vref, RX VrefLevel [Byte0]: 71
8687 13:38:02.939421 [Byte1]: 71
8688 13:38:02.943878
8689 13:38:02.943968 Final RX Vref Byte 0 = 59 to rank0
8690 13:38:02.947526 Final RX Vref Byte 1 = 56 to rank0
8691 13:38:02.950719 Final RX Vref Byte 0 = 59 to rank1
8692 13:38:02.953856 Final RX Vref Byte 1 = 56 to rank1==
8693 13:38:02.957585 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 13:38:02.963822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 13:38:02.963924 ==
8696 13:38:02.963993 DQS Delay:
8697 13:38:02.964074 DQS0 = 0, DQS1 = 0
8698 13:38:02.967453 DQM Delay:
8699 13:38:02.967530 DQM0 = 130, DQM1 = 124
8700 13:38:02.970419 DQ Delay:
8701 13:38:02.974211 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =128
8702 13:38:02.977058 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8703 13:38:02.980734 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8704 13:38:02.983986 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8705 13:38:02.984074
8706 13:38:02.984140
8707 13:38:02.984201
8708 13:38:02.987562 [DramC_TX_OE_Calibration] TA2
8709 13:38:02.990710 Original DQ_B0 (3 6) =30, OEN = 27
8710 13:38:02.994147 Original DQ_B1 (3 6) =30, OEN = 27
8711 13:38:02.997341 24, 0x0, End_B0=24 End_B1=24
8712 13:38:02.997427 25, 0x0, End_B0=25 End_B1=25
8713 13:38:03.000836 26, 0x0, End_B0=26 End_B1=26
8714 13:38:03.004030 27, 0x0, End_B0=27 End_B1=27
8715 13:38:03.007453 28, 0x0, End_B0=28 End_B1=28
8716 13:38:03.007538 29, 0x0, End_B0=29 End_B1=29
8717 13:38:03.010605 30, 0x0, End_B0=30 End_B1=30
8718 13:38:03.013894 31, 0x4141, End_B0=30 End_B1=30
8719 13:38:03.017106 Byte0 end_step=30 best_step=27
8720 13:38:03.021155 Byte1 end_step=30 best_step=27
8721 13:38:03.023949 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 13:38:03.024034 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 13:38:03.024101
8724 13:38:03.027365
8725 13:38:03.034203 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8726 13:38:03.037443 CH1 RK0: MR19=302, MR18=14FE
8727 13:38:03.044104 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8728 13:38:03.044191
8729 13:38:03.047278 ----->DramcWriteLeveling(PI) begin...
8730 13:38:03.047364 ==
8731 13:38:03.050374 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 13:38:03.054237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 13:38:03.054351 ==
8734 13:38:03.057224 Write leveling (Byte 0): 25 => 25
8735 13:38:03.060503 Write leveling (Byte 1): 30 => 30
8736 13:38:03.064093 DramcWriteLeveling(PI) end<-----
8737 13:38:03.064171
8738 13:38:03.064236 ==
8739 13:38:03.067266 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 13:38:03.070329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 13:38:03.070414 ==
8742 13:38:03.074069 [Gating] SW mode calibration
8743 13:38:03.080688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 13:38:03.087582 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 13:38:03.090562 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 13:38:03.093756 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 13:38:03.100266 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8748 13:38:03.104056 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8749 13:38:03.107200 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 13:38:03.113865 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 13:38:03.117432 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 13:38:03.120416 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 13:38:03.127260 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 13:38:03.130671 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8755 13:38:03.133718 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8756 13:38:03.137263 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8757 13:38:03.144101 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 13:38:03.147142 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 13:38:03.150738 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 13:38:03.157294 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 13:38:03.160389 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 13:38:03.164165 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8763 13:38:03.170869 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8764 13:38:03.173890 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8765 13:38:03.176992 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 13:38:03.184068 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 13:38:03.187140 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 13:38:03.190939 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 13:38:03.197514 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 13:38:03.200618 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 13:38:03.204258 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8772 13:38:03.210922 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8773 13:38:03.213825 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8774 13:38:03.217332 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 13:38:03.220997 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 13:38:03.227774 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 13:38:03.230886 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 13:38:03.234417 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 13:38:03.240929 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 13:38:03.244422 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 13:38:03.247554 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 13:38:03.254019 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 13:38:03.257581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 13:38:03.260825 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 13:38:03.267696 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 13:38:03.271002 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8787 13:38:03.274607 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8788 13:38:03.280890 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8789 13:38:03.280982 Total UI for P1: 0, mck2ui 16
8790 13:38:03.284307 best dqsien dly found for B0: ( 1, 9, 6)
8791 13:38:03.290984 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8792 13:38:03.294001 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 13:38:03.297786 Total UI for P1: 0, mck2ui 16
8794 13:38:03.300758 best dqsien dly found for B1: ( 1, 9, 14)
8795 13:38:03.304423 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8796 13:38:03.307346 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8797 13:38:03.307419
8798 13:38:03.311027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8799 13:38:03.317656 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8800 13:38:03.317751 [Gating] SW calibration Done
8801 13:38:03.317818 ==
8802 13:38:03.320818 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 13:38:03.327428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 13:38:03.327519 ==
8805 13:38:03.327585 RX Vref Scan: 0
8806 13:38:03.327646
8807 13:38:03.330557 RX Vref 0 -> 0, step: 1
8808 13:38:03.330645
8809 13:38:03.334119 RX Delay 0 -> 252, step: 8
8810 13:38:03.337137 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8811 13:38:03.340858 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8812 13:38:03.344389 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8813 13:38:03.347294 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8814 13:38:03.354200 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8815 13:38:03.357374 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8816 13:38:03.360967 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8817 13:38:03.363972 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8818 13:38:03.367602 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8819 13:38:03.374070 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8820 13:38:03.377472 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8821 13:38:03.380762 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8822 13:38:03.384077 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8823 13:38:03.387575 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8824 13:38:03.394283 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8825 13:38:03.397705 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8826 13:38:03.397782 ==
8827 13:38:03.400707 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 13:38:03.404431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 13:38:03.404502 ==
8830 13:38:03.407477 DQS Delay:
8831 13:38:03.407558 DQS0 = 0, DQS1 = 0
8832 13:38:03.407622 DQM Delay:
8833 13:38:03.410935 DQM0 = 132, DQM1 = 127
8834 13:38:03.411017 DQ Delay:
8835 13:38:03.414032 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8836 13:38:03.417633 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8837 13:38:03.420728 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8838 13:38:03.427443 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8839 13:38:03.427523
8840 13:38:03.427592
8841 13:38:03.427650 ==
8842 13:38:03.431152 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 13:38:03.434185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 13:38:03.434257 ==
8845 13:38:03.434328
8846 13:38:03.434390
8847 13:38:03.438003 TX Vref Scan disable
8848 13:38:03.438094 == TX Byte 0 ==
8849 13:38:03.443890 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8850 13:38:03.447475 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8851 13:38:03.447557 == TX Byte 1 ==
8852 13:38:03.454524 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8853 13:38:03.457733 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8854 13:38:03.457821 ==
8855 13:38:03.460894 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 13:38:03.463883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 13:38:03.463969 ==
8858 13:38:03.478944
8859 13:38:03.482595 TX Vref early break, caculate TX vref
8860 13:38:03.485548 TX Vref=16, minBit 8, minWin=21, winSum=376
8861 13:38:03.489213 TX Vref=18, minBit 15, minWin=22, winSum=384
8862 13:38:03.492657 TX Vref=20, minBit 8, minWin=22, winSum=388
8863 13:38:03.496007 TX Vref=22, minBit 8, minWin=23, winSum=396
8864 13:38:03.499233 TX Vref=24, minBit 8, minWin=24, winSum=407
8865 13:38:03.505827 TX Vref=26, minBit 15, minWin=24, winSum=415
8866 13:38:03.509673 TX Vref=28, minBit 9, minWin=25, winSum=420
8867 13:38:03.512787 TX Vref=30, minBit 0, minWin=25, winSum=415
8868 13:38:03.516305 TX Vref=32, minBit 0, minWin=25, winSum=412
8869 13:38:03.519297 TX Vref=34, minBit 11, minWin=24, winSum=403
8870 13:38:03.522434 TX Vref=36, minBit 9, minWin=23, winSum=390
8871 13:38:03.529303 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8872 13:38:03.529380
8873 13:38:03.533014 Final TX Range 0 Vref 28
8874 13:38:03.533089
8875 13:38:03.533160 ==
8876 13:38:03.536043 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 13:38:03.539285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 13:38:03.539362 ==
8879 13:38:03.539422
8880 13:38:03.539485
8881 13:38:03.542909 TX Vref Scan disable
8882 13:38:03.549453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8883 13:38:03.549532 == TX Byte 0 ==
8884 13:38:03.552713 u2DelayCellOfst[0]=17 cells (5 PI)
8885 13:38:03.555887 u2DelayCellOfst[1]=14 cells (4 PI)
8886 13:38:03.559460 u2DelayCellOfst[2]=0 cells (0 PI)
8887 13:38:03.562660 u2DelayCellOfst[3]=7 cells (2 PI)
8888 13:38:03.565864 u2DelayCellOfst[4]=7 cells (2 PI)
8889 13:38:03.569147 u2DelayCellOfst[5]=17 cells (5 PI)
8890 13:38:03.572424 u2DelayCellOfst[6]=17 cells (5 PI)
8891 13:38:03.576375 u2DelayCellOfst[7]=7 cells (2 PI)
8892 13:38:03.579542 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8893 13:38:03.582675 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8894 13:38:03.585874 == TX Byte 1 ==
8895 13:38:03.585978 u2DelayCellOfst[8]=0 cells (0 PI)
8896 13:38:03.589012 u2DelayCellOfst[9]=0 cells (0 PI)
8897 13:38:03.592944 u2DelayCellOfst[10]=7 cells (2 PI)
8898 13:38:03.595700 u2DelayCellOfst[11]=3 cells (1 PI)
8899 13:38:03.599913 u2DelayCellOfst[12]=10 cells (3 PI)
8900 13:38:03.602861 u2DelayCellOfst[13]=14 cells (4 PI)
8901 13:38:03.606116 u2DelayCellOfst[14]=14 cells (4 PI)
8902 13:38:03.609172 u2DelayCellOfst[15]=14 cells (4 PI)
8903 13:38:03.613000 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8904 13:38:03.619265 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8905 13:38:03.619353 DramC Write-DBI on
8906 13:38:03.619422 ==
8907 13:38:03.622790 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 13:38:03.625756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 13:38:03.625838 ==
8910 13:38:03.629471
8911 13:38:03.629559
8912 13:38:03.629651 TX Vref Scan disable
8913 13:38:03.632638 == TX Byte 0 ==
8914 13:38:03.636263 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8915 13:38:03.639629 == TX Byte 1 ==
8916 13:38:03.643031 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8917 13:38:03.643153 DramC Write-DBI off
8918 13:38:03.646328
8919 13:38:03.646432 [DATLAT]
8920 13:38:03.646531 Freq=1600, CH1 RK1
8921 13:38:03.646630
8922 13:38:03.649392 DATLAT Default: 0xf
8923 13:38:03.649494 0, 0xFFFF, sum = 0
8924 13:38:03.652399 1, 0xFFFF, sum = 0
8925 13:38:03.652507 2, 0xFFFF, sum = 0
8926 13:38:03.656165 3, 0xFFFF, sum = 0
8927 13:38:03.656273 4, 0xFFFF, sum = 0
8928 13:38:03.659139 5, 0xFFFF, sum = 0
8929 13:38:03.659248 6, 0xFFFF, sum = 0
8930 13:38:03.662510 7, 0xFFFF, sum = 0
8931 13:38:03.666053 8, 0xFFFF, sum = 0
8932 13:38:03.666157 9, 0xFFFF, sum = 0
8933 13:38:03.669514 10, 0xFFFF, sum = 0
8934 13:38:03.669600 11, 0xFFFF, sum = 0
8935 13:38:03.672394 12, 0xFFFF, sum = 0
8936 13:38:03.672508 13, 0xFFFF, sum = 0
8937 13:38:03.675761 14, 0x0, sum = 1
8938 13:38:03.675876 15, 0x0, sum = 2
8939 13:38:03.679473 16, 0x0, sum = 3
8940 13:38:03.679583 17, 0x0, sum = 4
8941 13:38:03.679679 best_step = 15
8942 13:38:03.682859
8943 13:38:03.682978 ==
8944 13:38:03.686061 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 13:38:03.689354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 13:38:03.689468 ==
8947 13:38:03.689567 RX Vref Scan: 0
8948 13:38:03.689659
8949 13:38:03.693062 RX Vref 0 -> 0, step: 1
8950 13:38:03.693144
8951 13:38:03.696366 RX Delay 11 -> 252, step: 4
8952 13:38:03.699589 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8953 13:38:03.706036 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8954 13:38:03.709346 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8955 13:38:03.712668 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8956 13:38:03.715708 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8957 13:38:03.719597 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8958 13:38:03.722900 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8959 13:38:03.729678 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8960 13:38:03.732521 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8961 13:38:03.736120 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8962 13:38:03.739260 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8963 13:38:03.742684 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8964 13:38:03.749186 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8965 13:38:03.752635 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8966 13:38:03.756187 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8967 13:38:03.759632 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8968 13:38:03.759741 ==
8969 13:38:03.762614 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 13:38:03.769489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 13:38:03.769601 ==
8972 13:38:03.769703 DQS Delay:
8973 13:38:03.772766 DQS0 = 0, DQS1 = 0
8974 13:38:03.772876 DQM Delay:
8975 13:38:03.772980 DQM0 = 129, DQM1 = 126
8976 13:38:03.776393 DQ Delay:
8977 13:38:03.779608 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
8978 13:38:03.782512 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =124
8979 13:38:03.786179 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
8980 13:38:03.789274 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8981 13:38:03.789355
8982 13:38:03.789420
8983 13:38:03.789485
8984 13:38:03.792784 [DramC_TX_OE_Calibration] TA2
8985 13:38:03.796198 Original DQ_B0 (3 6) =30, OEN = 27
8986 13:38:03.799469 Original DQ_B1 (3 6) =30, OEN = 27
8987 13:38:03.803098 24, 0x0, End_B0=24 End_B1=24
8988 13:38:03.803209 25, 0x0, End_B0=25 End_B1=25
8989 13:38:03.806122 26, 0x0, End_B0=26 End_B1=26
8990 13:38:03.809933 27, 0x0, End_B0=27 End_B1=27
8991 13:38:03.812831 28, 0x0, End_B0=28 End_B1=28
8992 13:38:03.812938 29, 0x0, End_B0=29 End_B1=29
8993 13:38:03.816057 30, 0x0, End_B0=30 End_B1=30
8994 13:38:03.819844 31, 0x4141, End_B0=30 End_B1=30
8995 13:38:03.822873 Byte0 end_step=30 best_step=27
8996 13:38:03.826043 Byte1 end_step=30 best_step=27
8997 13:38:03.829803 Byte0 TX OE(2T, 0.5T) = (3, 3)
8998 13:38:03.829908 Byte1 TX OE(2T, 0.5T) = (3, 3)
8999 13:38:03.832873
9000 13:38:03.832978
9001 13:38:03.839594 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9002 13:38:03.842696 CH1 RK1: MR19=303, MR18=D13
9003 13:38:03.849437 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9004 13:38:03.849554 [RxdqsGatingPostProcess] freq 1600
9005 13:38:03.856044 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9006 13:38:03.859709 best DQS0 dly(2T, 0.5T) = (1, 1)
9007 13:38:03.862523 best DQS1 dly(2T, 0.5T) = (1, 1)
9008 13:38:03.866129 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9009 13:38:03.869251 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9010 13:38:03.872564 best DQS0 dly(2T, 0.5T) = (1, 1)
9011 13:38:03.876207 best DQS1 dly(2T, 0.5T) = (1, 1)
9012 13:38:03.879317 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9013 13:38:03.883016 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9014 13:38:03.883129 Pre-setting of DQS Precalculation
9015 13:38:03.889402 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9016 13:38:03.896087 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9017 13:38:03.902441 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9018 13:38:03.902553
9019 13:38:03.902648
9020 13:38:03.906020 [Calibration Summary] 3200 Mbps
9021 13:38:03.909102 CH 0, Rank 0
9022 13:38:03.909210 SW Impedance : PASS
9023 13:38:03.912811 DUTY Scan : NO K
9024 13:38:03.916093 ZQ Calibration : PASS
9025 13:38:03.916197 Jitter Meter : NO K
9026 13:38:03.919315 CBT Training : PASS
9027 13:38:03.919420 Write leveling : PASS
9028 13:38:03.923053 RX DQS gating : PASS
9029 13:38:03.926002 RX DQ/DQS(RDDQC) : PASS
9030 13:38:03.926105 TX DQ/DQS : PASS
9031 13:38:03.929098 RX DATLAT : PASS
9032 13:38:03.932904 RX DQ/DQS(Engine): PASS
9033 13:38:03.933021 TX OE : PASS
9034 13:38:03.935651 All Pass.
9035 13:38:03.935753
9036 13:38:03.935848 CH 0, Rank 1
9037 13:38:03.939350 SW Impedance : PASS
9038 13:38:03.939452 DUTY Scan : NO K
9039 13:38:03.942566 ZQ Calibration : PASS
9040 13:38:03.945754 Jitter Meter : NO K
9041 13:38:03.945863 CBT Training : PASS
9042 13:38:03.949312 Write leveling : PASS
9043 13:38:03.953070 RX DQS gating : PASS
9044 13:38:03.953180 RX DQ/DQS(RDDQC) : PASS
9045 13:38:03.955989 TX DQ/DQS : PASS
9046 13:38:03.956099 RX DATLAT : PASS
9047 13:38:03.959688 RX DQ/DQS(Engine): PASS
9048 13:38:03.963047 TX OE : PASS
9049 13:38:03.963155 All Pass.
9050 13:38:03.963260
9051 13:38:03.963353 CH 1, Rank 0
9052 13:38:03.966034 SW Impedance : PASS
9053 13:38:03.969428 DUTY Scan : NO K
9054 13:38:03.969551 ZQ Calibration : PASS
9055 13:38:03.972792 Jitter Meter : NO K
9056 13:38:03.975868 CBT Training : PASS
9057 13:38:03.975978 Write leveling : PASS
9058 13:38:03.979893 RX DQS gating : PASS
9059 13:38:03.982738 RX DQ/DQS(RDDQC) : PASS
9060 13:38:03.982865 TX DQ/DQS : PASS
9061 13:38:03.985826 RX DATLAT : PASS
9062 13:38:03.989242 RX DQ/DQS(Engine): PASS
9063 13:38:03.989359 TX OE : PASS
9064 13:38:03.992528 All Pass.
9065 13:38:03.992636
9066 13:38:03.992736 CH 1, Rank 1
9067 13:38:03.996202 SW Impedance : PASS
9068 13:38:03.996284 DUTY Scan : NO K
9069 13:38:03.999243 ZQ Calibration : PASS
9070 13:38:04.002779 Jitter Meter : NO K
9071 13:38:04.002888 CBT Training : PASS
9072 13:38:04.006230 Write leveling : PASS
9073 13:38:04.006332 RX DQS gating : PASS
9074 13:38:04.009143 RX DQ/DQS(RDDQC) : PASS
9075 13:38:04.012529 TX DQ/DQS : PASS
9076 13:38:04.012641 RX DATLAT : PASS
9077 13:38:04.016090 RX DQ/DQS(Engine): PASS
9078 13:38:04.019304 TX OE : PASS
9079 13:38:04.019410 All Pass.
9080 13:38:04.019507
9081 13:38:04.023000 DramC Write-DBI on
9082 13:38:04.023104 PER_BANK_REFRESH: Hybrid Mode
9083 13:38:04.026187 TX_TRACKING: ON
9084 13:38:04.033007 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9085 13:38:04.042541 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9086 13:38:04.049499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 13:38:04.052651 [FAST_K] Save calibration result to emmc
9088 13:38:04.056218 sync common calibartion params.
9089 13:38:04.059303 sync cbt_mode0:1, 1:1
9090 13:38:04.059416 dram_init: ddr_geometry: 2
9091 13:38:04.063061 dram_init: ddr_geometry: 2
9092 13:38:04.066122 dram_init: ddr_geometry: 2
9093 13:38:04.066205 0:dram_rank_size:100000000
9094 13:38:04.069321 1:dram_rank_size:100000000
9095 13:38:04.076297 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9096 13:38:04.079280 DFS_SHUFFLE_HW_MODE: ON
9097 13:38:04.082868 dramc_set_vcore_voltage set vcore to 725000
9098 13:38:04.082986 Read voltage for 1600, 0
9099 13:38:04.086008 Vio18 = 0
9100 13:38:04.086094 Vcore = 725000
9101 13:38:04.086161 Vdram = 0
9102 13:38:04.089159 Vddq = 0
9103 13:38:04.089243 Vmddr = 0
9104 13:38:04.092928 switch to 3200 Mbps bootup
9105 13:38:04.093035 [DramcRunTimeConfig]
9106 13:38:04.093104 PHYPLL
9107 13:38:04.095933 DPM_CONTROL_AFTERK: ON
9108 13:38:04.099423 PER_BANK_REFRESH: ON
9109 13:38:04.099508 REFRESH_OVERHEAD_REDUCTION: ON
9110 13:38:04.102594 CMD_PICG_NEW_MODE: OFF
9111 13:38:04.106339 XRTWTW_NEW_MODE: ON
9112 13:38:04.106421 XRTRTR_NEW_MODE: ON
9113 13:38:04.109146 TX_TRACKING: ON
9114 13:38:04.109260 RDSEL_TRACKING: OFF
9115 13:38:04.112759 DQS Precalculation for DVFS: ON
9116 13:38:04.112863 RX_TRACKING: OFF
9117 13:38:04.116293 HW_GATING DBG: ON
9118 13:38:04.116395 ZQCS_ENABLE_LP4: ON
9119 13:38:04.119086 RX_PICG_NEW_MODE: ON
9120 13:38:04.122691 TX_PICG_NEW_MODE: ON
9121 13:38:04.122796 ENABLE_RX_DCM_DPHY: ON
9122 13:38:04.126083 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9123 13:38:04.129331 DUMMY_READ_FOR_TRACKING: OFF
9124 13:38:04.132420 !!! SPM_CONTROL_AFTERK: OFF
9125 13:38:04.132532 !!! SPM could not control APHY
9126 13:38:04.136186 IMPEDANCE_TRACKING: ON
9127 13:38:04.139326 TEMP_SENSOR: ON
9128 13:38:04.139430 HW_SAVE_FOR_SR: OFF
9129 13:38:04.142622 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9130 13:38:04.146154 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9131 13:38:04.149478 Read ODT Tracking: ON
9132 13:38:04.149580 Refresh Rate DeBounce: ON
9133 13:38:04.152998 DFS_NO_QUEUE_FLUSH: ON
9134 13:38:04.156127 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9135 13:38:04.159831 ENABLE_DFS_RUNTIME_MRW: OFF
9136 13:38:04.159917 DDR_RESERVE_NEW_MODE: ON
9137 13:38:04.162857 MR_CBT_SWITCH_FREQ: ON
9138 13:38:04.166176 =========================
9139 13:38:04.183777 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9140 13:38:04.187193 dram_init: ddr_geometry: 2
9141 13:38:04.205231 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9142 13:38:04.208810 dram_init: dram init end (result: 0)
9143 13:38:04.215468 DRAM-K: Full calibration passed in 24497 msecs
9144 13:38:04.218438 MRC: failed to locate region type 0.
9145 13:38:04.218555 DRAM rank0 size:0x100000000,
9146 13:38:04.222009 DRAM rank1 size=0x100000000
9147 13:38:04.232050 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9148 13:38:04.238990 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9149 13:38:04.245696 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9150 13:38:04.251795 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9151 13:38:04.255821 DRAM rank0 size:0x100000000,
9152 13:38:04.258843 DRAM rank1 size=0x100000000
9153 13:38:04.258955 CBMEM:
9154 13:38:04.262101 IMD: root @ 0xfffff000 254 entries.
9155 13:38:04.265169 IMD: root @ 0xffffec00 62 entries.
9156 13:38:04.269043 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9157 13:38:04.272156 WARNING: RO_VPD is uninitialized or empty.
9158 13:38:04.278456 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9159 13:38:04.285502 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9160 13:38:04.298077 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9161 13:38:04.309888 BS: romstage times (exec / console): total (unknown) / 24013 ms
9162 13:38:04.310007
9163 13:38:04.310102
9164 13:38:04.319715 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9165 13:38:04.322783 ARM64: Exception handlers installed.
9166 13:38:04.326012 ARM64: Testing exception
9167 13:38:04.329465 ARM64: Done test exception
9168 13:38:04.329546 Enumerating buses...
9169 13:38:04.332528 Show all devs... Before device enumeration.
9170 13:38:04.335981 Root Device: enabled 1
9171 13:38:04.339381 CPU_CLUSTER: 0: enabled 1
9172 13:38:04.339502 CPU: 00: enabled 1
9173 13:38:04.342782 Compare with tree...
9174 13:38:04.342868 Root Device: enabled 1
9175 13:38:04.345831 CPU_CLUSTER: 0: enabled 1
9176 13:38:04.349302 CPU: 00: enabled 1
9177 13:38:04.349387 Root Device scanning...
9178 13:38:04.352924 scan_static_bus for Root Device
9179 13:38:04.355946 CPU_CLUSTER: 0 enabled
9180 13:38:04.359125 scan_static_bus for Root Device done
9181 13:38:04.362163 scan_bus: bus Root Device finished in 8 msecs
9182 13:38:04.362248 done
9183 13:38:04.368935 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9184 13:38:04.372845 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9185 13:38:04.379004 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9186 13:38:04.382803 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9187 13:38:04.385983 Allocating resources...
9188 13:38:04.388957 Reading resources...
9189 13:38:04.392579 Root Device read_resources bus 0 link: 0
9190 13:38:04.392663 DRAM rank0 size:0x100000000,
9191 13:38:04.396316 DRAM rank1 size=0x100000000
9192 13:38:04.399179 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9193 13:38:04.402806 CPU: 00 missing read_resources
9194 13:38:04.405669 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9195 13:38:04.412421 Root Device read_resources bus 0 link: 0 done
9196 13:38:04.412506 Done reading resources.
9197 13:38:04.419173 Show resources in subtree (Root Device)...After reading.
9198 13:38:04.422211 Root Device child on link 0 CPU_CLUSTER: 0
9199 13:38:04.425787 CPU_CLUSTER: 0 child on link 0 CPU: 00
9200 13:38:04.435590 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9201 13:38:04.435675 CPU: 00
9202 13:38:04.439125 Root Device assign_resources, bus 0 link: 0
9203 13:38:04.442563 CPU_CLUSTER: 0 missing set_resources
9204 13:38:04.446179 Root Device assign_resources, bus 0 link: 0 done
9205 13:38:04.448935 Done setting resources.
9206 13:38:04.455707 Show resources in subtree (Root Device)...After assigning values.
9207 13:38:04.459184 Root Device child on link 0 CPU_CLUSTER: 0
9208 13:38:04.462632 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 13:38:04.472273 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 13:38:04.472372 CPU: 00
9211 13:38:04.476013 Done allocating resources.
9212 13:38:04.479225 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9213 13:38:04.482768 Enabling resources...
9214 13:38:04.482856 done.
9215 13:38:04.489304 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9216 13:38:04.489406 Initializing devices...
9217 13:38:04.492592 Root Device init
9218 13:38:04.492666 init hardware done!
9219 13:38:04.495655 0x00000018: ctrlr->caps
9220 13:38:04.499281 52.000 MHz: ctrlr->f_max
9221 13:38:04.499360 0.400 MHz: ctrlr->f_min
9222 13:38:04.502385 0x40ff8080: ctrlr->voltages
9223 13:38:04.502459 sclk: 390625
9224 13:38:04.505981 Bus Width = 1
9225 13:38:04.506060 sclk: 390625
9226 13:38:04.506151 Bus Width = 1
9227 13:38:04.509491 Early init status = 3
9228 13:38:04.512357 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9229 13:38:04.518112 in-header: 03 fc 00 00 01 00 00 00
9230 13:38:04.521295 in-data: 00
9231 13:38:04.524521 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9232 13:38:04.530789 in-header: 03 fd 00 00 00 00 00 00
9233 13:38:04.533641 in-data:
9234 13:38:04.536677 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9235 13:38:04.541176 in-header: 03 fc 00 00 01 00 00 00
9236 13:38:04.544845 in-data: 00
9237 13:38:04.547915 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9238 13:38:04.553375 in-header: 03 fd 00 00 00 00 00 00
9239 13:38:04.556623 in-data:
9240 13:38:04.560405 [SSUSB] Setting up USB HOST controller...
9241 13:38:04.563627 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9242 13:38:04.566757 [SSUSB] phy power-on done.
9243 13:38:04.570213 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9244 13:38:04.576735 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9245 13:38:04.580168 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9246 13:38:04.587351 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9247 13:38:04.593904 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9248 13:38:04.600369 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9249 13:38:04.606577 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9250 13:38:04.613329 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9251 13:38:04.613415 SPM: binary array size = 0x9dc
9252 13:38:04.620137 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9253 13:38:04.627240 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9254 13:38:04.633277 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9255 13:38:04.637127 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9256 13:38:04.640343 configure_display: Starting display init
9257 13:38:04.676725 anx7625_power_on_init: Init interface.
9258 13:38:04.680187 anx7625_disable_pd_protocol: Disabled PD feature.
9259 13:38:04.683211 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9260 13:38:04.711558 anx7625_start_dp_work: Secure OCM version=00
9261 13:38:04.714666 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9262 13:38:04.729290 sp_tx_get_edid_block: EDID Block = 1
9263 13:38:04.831670 Extracted contents:
9264 13:38:04.835470 header: 00 ff ff ff ff ff ff 00
9265 13:38:04.838444 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9266 13:38:04.841671 version: 01 04
9267 13:38:04.845289 basic params: 95 1f 11 78 0a
9268 13:38:04.848263 chroma info: 76 90 94 55 54 90 27 21 50 54
9269 13:38:04.851936 established: 00 00 00
9270 13:38:04.858428 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9271 13:38:04.861632 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9272 13:38:04.868427 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9273 13:38:04.875264 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9274 13:38:04.881554 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9275 13:38:04.884663 extensions: 00
9276 13:38:04.884748 checksum: fb
9277 13:38:04.884814
9278 13:38:04.888468 Manufacturer: IVO Model 57d Serial Number 0
9279 13:38:04.891387 Made week 0 of 2020
9280 13:38:04.891498 EDID version: 1.4
9281 13:38:04.895042 Digital display
9282 13:38:04.898486 6 bits per primary color channel
9283 13:38:04.898569 DisplayPort interface
9284 13:38:04.901517 Maximum image size: 31 cm x 17 cm
9285 13:38:04.905261 Gamma: 220%
9286 13:38:04.905359 Check DPMS levels
9287 13:38:04.908340 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9288 13:38:04.911400 First detailed timing is preferred timing
9289 13:38:04.914931 Established timings supported:
9290 13:38:04.918369 Standard timings supported:
9291 13:38:04.918454 Detailed timings
9292 13:38:04.925230 Hex of detail: 383680a07038204018303c0035ae10000019
9293 13:38:04.928138 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9294 13:38:04.934956 0780 0798 07c8 0820 hborder 0
9295 13:38:04.938030 0438 043b 0447 0458 vborder 0
9296 13:38:04.941567 -hsync -vsync
9297 13:38:04.941650 Did detailed timing
9298 13:38:04.944634 Hex of detail: 000000000000000000000000000000000000
9299 13:38:04.948415 Manufacturer-specified data, tag 0
9300 13:38:04.955079 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9301 13:38:04.955162 ASCII string: InfoVision
9302 13:38:04.961417 Hex of detail: 000000fe00523134304e574635205248200a
9303 13:38:04.964669 ASCII string: R140NWF5 RH
9304 13:38:04.964752 Checksum
9305 13:38:04.964817 Checksum: 0xfb (valid)
9306 13:38:04.971270 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9307 13:38:04.974703 DSI data_rate: 832800000 bps
9308 13:38:04.978173 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9309 13:38:04.984947 anx7625_parse_edid: pixelclock(138800).
9310 13:38:04.988047 hactive(1920), hsync(48), hfp(24), hbp(88)
9311 13:38:04.991204 vactive(1080), vsync(12), vfp(3), vbp(17)
9312 13:38:04.994437 anx7625_dsi_config: config dsi.
9313 13:38:05.001414 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9314 13:38:05.013875 anx7625_dsi_config: success to config DSI
9315 13:38:05.017489 anx7625_dp_start: MIPI phy setup OK.
9316 13:38:05.020564 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9317 13:38:05.023918 mtk_ddp_mode_set invalid vrefresh 60
9318 13:38:05.027519 main_disp_path_setup
9319 13:38:05.027602 ovl_layer_smi_id_en
9320 13:38:05.031100 ovl_layer_smi_id_en
9321 13:38:05.031183 ccorr_config
9322 13:38:05.031248 aal_config
9323 13:38:05.034197 gamma_config
9324 13:38:05.034279 postmask_config
9325 13:38:05.034344 dither_config
9326 13:38:05.040840 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9327 13:38:05.047671 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9328 13:38:05.050876 Root Device init finished in 555 msecs
9329 13:38:05.050961 CPU_CLUSTER: 0 init
9330 13:38:05.060366 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9331 13:38:05.063829 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9332 13:38:05.067293 APU_MBOX 0x190000b0 = 0x10001
9333 13:38:05.070691 APU_MBOX 0x190001b0 = 0x10001
9334 13:38:05.074102 APU_MBOX 0x190005b0 = 0x10001
9335 13:38:05.077293 APU_MBOX 0x190006b0 = 0x10001
9336 13:38:05.080769 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9337 13:38:05.093004 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9338 13:38:05.105336 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9339 13:38:05.112157 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9340 13:38:05.123728 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9341 13:38:05.132886 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9342 13:38:05.136138 CPU_CLUSTER: 0 init finished in 81 msecs
9343 13:38:05.139799 Devices initialized
9344 13:38:05.142980 Show all devs... After init.
9345 13:38:05.143063 Root Device: enabled 1
9346 13:38:05.146366 CPU_CLUSTER: 0: enabled 1
9347 13:38:05.149439 CPU: 00: enabled 1
9348 13:38:05.153197 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9349 13:38:05.156090 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9350 13:38:05.159588 ELOG: NV offset 0x57f000 size 0x1000
9351 13:38:05.166323 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9352 13:38:05.172878 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9353 13:38:05.175963 ELOG: Event(17) added with size 13 at 2024-05-28 13:38:05 UTC
9354 13:38:05.179114 out: cmd=0x121: 03 db 21 01 00 00 00 00
9355 13:38:05.183829 in-header: 03 2a 00 00 2c 00 00 00
9356 13:38:05.197361 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 13:38:05.204170 ELOG: Event(A1) added with size 10 at 2024-05-28 13:38:05 UTC
9358 13:38:05.211073 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9359 13:38:05.217371 ELOG: Event(A0) added with size 9 at 2024-05-28 13:38:05 UTC
9360 13:38:05.220677 elog_add_boot_reason: Logged dev mode boot
9361 13:38:05.223772 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9362 13:38:05.227314 Finalize devices...
9363 13:38:05.227395 Devices finalized
9364 13:38:05.234120 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9365 13:38:05.237153 Writing coreboot table at 0xffe64000
9366 13:38:05.240645 0. 000000000010a000-0000000000113fff: RAMSTAGE
9367 13:38:05.243953 1. 0000000040000000-00000000400fffff: RAM
9368 13:38:05.247211 2. 0000000040100000-000000004032afff: RAMSTAGE
9369 13:38:05.254113 3. 000000004032b000-00000000545fffff: RAM
9370 13:38:05.257393 4. 0000000054600000-000000005465ffff: BL31
9371 13:38:05.260684 5. 0000000054660000-00000000ffe63fff: RAM
9372 13:38:05.264178 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9373 13:38:05.270463 7. 0000000100000000-000000023fffffff: RAM
9374 13:38:05.270543 Passing 5 GPIOs to payload:
9375 13:38:05.277661 NAME | PORT | POLARITY | VALUE
9376 13:38:05.280640 EC in RW | 0x000000aa | low | undefined
9377 13:38:05.284561 EC interrupt | 0x00000005 | low | undefined
9378 13:38:05.290824 TPM interrupt | 0x000000ab | high | undefined
9379 13:38:05.294646 SD card detect | 0x00000011 | high | undefined
9380 13:38:05.301162 speaker enable | 0x00000093 | high | undefined
9381 13:38:05.303930 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9382 13:38:05.307486 in-header: 03 f9 00 00 02 00 00 00
9383 13:38:05.307568 in-data: 02 00
9384 13:38:05.310818 ADC[4]: Raw value=899114 ID=7
9385 13:38:05.314119 ADC[3]: Raw value=212967 ID=1
9386 13:38:05.314251 RAM Code: 0x71
9387 13:38:05.317468 ADC[6]: Raw value=74557 ID=0
9388 13:38:05.320758 ADC[5]: Raw value=212229 ID=1
9389 13:38:05.320843 SKU Code: 0x1
9390 13:38:05.327442 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a3a8
9391 13:38:05.331005 coreboot table: 964 bytes.
9392 13:38:05.334531 IMD ROOT 0. 0xfffff000 0x00001000
9393 13:38:05.337592 IMD SMALL 1. 0xffffe000 0x00001000
9394 13:38:05.340636 RO MCACHE 2. 0xffffc000 0x00001104
9395 13:38:05.344330 CONSOLE 3. 0xfff7c000 0x00080000
9396 13:38:05.347286 FMAP 4. 0xfff7b000 0x00000452
9397 13:38:05.350774 TIME STAMP 5. 0xfff7a000 0x00000910
9398 13:38:05.350859 VBOOT WORK 6. 0xfff66000 0x00014000
9399 13:38:05.353893 RAMOOPS 7. 0xffe66000 0x00100000
9400 13:38:05.357739 COREBOOT 8. 0xffe64000 0x00002000
9401 13:38:05.361131 IMD small region:
9402 13:38:05.364275 IMD ROOT 0. 0xffffec00 0x00000400
9403 13:38:05.367219 VPD 1. 0xffffeb80 0x0000006c
9404 13:38:05.371129 MMC STATUS 2. 0xffffeb60 0x00000004
9405 13:38:05.377311 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9406 13:38:05.377401 Probing TPM: done!
9407 13:38:05.384385 Connected to device vid:did:rid of 1ae0:0028:00
9408 13:38:05.391591 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9409 13:38:05.394556 Initialized TPM device CR50 revision 0
9410 13:38:05.397973 Checking cr50 for pending updates
9411 13:38:05.403435 Reading cr50 TPM mode
9412 13:38:05.412021 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9413 13:38:05.418738 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9414 13:38:05.458688 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9415 13:38:05.462190 Checking segment from ROM address 0x40100000
9416 13:38:05.465330 Checking segment from ROM address 0x4010001c
9417 13:38:05.472359 Loading segment from ROM address 0x40100000
9418 13:38:05.472458 code (compression=0)
9419 13:38:05.478693 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9420 13:38:05.488554 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9421 13:38:05.488654 it's not compressed!
9422 13:38:05.495558 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9423 13:38:05.498933 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9424 13:38:05.518978 Loading segment from ROM address 0x4010001c
9425 13:38:05.519093 Entry Point 0x80000000
9426 13:38:05.522725 Loaded segments
9427 13:38:05.525954 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9428 13:38:05.532301 Jumping to boot code at 0x80000000(0xffe64000)
9429 13:38:05.539334 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9430 13:38:05.545739 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9431 13:38:05.553394 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9432 13:38:05.556492 Checking segment from ROM address 0x40100000
9433 13:38:05.560466 Checking segment from ROM address 0x4010001c
9434 13:38:05.567140 Loading segment from ROM address 0x40100000
9435 13:38:05.567227 code (compression=1)
9436 13:38:05.573347 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9437 13:38:05.583290 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9438 13:38:05.583387 using LZMA
9439 13:38:05.591844 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9440 13:38:05.598588 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9441 13:38:05.602272 Loading segment from ROM address 0x4010001c
9442 13:38:05.602349 Entry Point 0x54601000
9443 13:38:05.605487 Loaded segments
9444 13:38:05.608655 NOTICE: MT8192 bl31_setup
9445 13:38:05.615391 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9446 13:38:05.619077 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9447 13:38:05.622232 WARNING: region 0:
9448 13:38:05.625657 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 13:38:05.625745 WARNING: region 1:
9450 13:38:05.631996 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9451 13:38:05.635674 WARNING: region 2:
9452 13:38:05.638864 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9453 13:38:05.642418 WARNING: region 3:
9454 13:38:05.645748 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 13:38:05.649009 WARNING: region 4:
9456 13:38:05.652090 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 13:38:05.655910 WARNING: region 5:
9458 13:38:05.658806 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 13:38:05.662587 WARNING: region 6:
9460 13:38:05.665606 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 13:38:05.665712 WARNING: region 7:
9462 13:38:05.672516 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 13:38:05.679047 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9464 13:38:05.682503 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9465 13:38:05.685875 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9466 13:38:05.689064 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9467 13:38:05.696065 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9468 13:38:05.698989 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9469 13:38:05.705909 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9470 13:38:05.709194 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9471 13:38:05.712381 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9472 13:38:05.719226 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9473 13:38:05.722615 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9474 13:38:05.726244 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9475 13:38:05.732591 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9476 13:38:05.736168 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9477 13:38:05.743067 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9478 13:38:05.746147 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9479 13:38:05.749260 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9480 13:38:05.756128 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9481 13:38:05.759688 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9482 13:38:05.762556 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9483 13:38:05.769179 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9484 13:38:05.772667 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9485 13:38:05.779345 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9486 13:38:05.782699 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9487 13:38:05.786211 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9488 13:38:05.792571 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9489 13:38:05.796307 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9490 13:38:05.802798 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9491 13:38:05.806089 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9492 13:38:05.809512 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9493 13:38:05.816260 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9494 13:38:05.819368 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9495 13:38:05.823061 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9496 13:38:05.829373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9497 13:38:05.833040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9498 13:38:05.836137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9499 13:38:05.839426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9500 13:38:05.846621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9501 13:38:05.849594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9502 13:38:05.853191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9503 13:38:05.856351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9504 13:38:05.859478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9505 13:38:05.866820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9506 13:38:05.869891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9507 13:38:05.873039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9508 13:38:05.876462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9509 13:38:05.883469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9510 13:38:05.886558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9511 13:38:05.889911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9512 13:38:05.896996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9513 13:38:05.900025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9514 13:38:05.906784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9515 13:38:05.910512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9516 13:38:05.913579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9517 13:38:05.920102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9518 13:38:05.923428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9519 13:38:05.930334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9520 13:38:05.933870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9521 13:38:05.936931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9522 13:38:05.943770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9523 13:38:05.947612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9524 13:38:05.954054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9525 13:38:05.957155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9526 13:38:05.963977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9527 13:38:05.967089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9528 13:38:05.970774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9529 13:38:05.977284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9530 13:38:05.980777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9531 13:38:05.987587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9532 13:38:05.990550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9533 13:38:05.997273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9534 13:38:06.000595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9535 13:38:06.003856 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9536 13:38:06.010584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9537 13:38:06.014437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9538 13:38:06.021238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9539 13:38:06.024389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9540 13:38:06.030965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9541 13:38:06.034486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9542 13:38:06.038142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9543 13:38:06.044499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9544 13:38:06.049383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9545 13:38:06.054351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9546 13:38:06.058014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9547 13:38:06.061695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9548 13:38:06.067820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9549 13:38:06.071459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9550 13:38:06.078419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9551 13:38:06.081466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9552 13:38:06.088293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9553 13:38:06.091540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9554 13:38:06.095103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9555 13:38:06.101923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9556 13:38:06.105169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9557 13:38:06.111946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9558 13:38:06.114871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9559 13:38:06.118371 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9560 13:38:06.124683 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9561 13:38:06.128615 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9562 13:38:06.131710 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9563 13:38:06.135265 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9564 13:38:06.141679 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9565 13:38:06.145398 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9566 13:38:06.152070 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9567 13:38:06.155275 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9568 13:38:06.158826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9569 13:38:06.165453 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9570 13:38:06.168356 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9571 13:38:06.172127 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9572 13:38:06.178940 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9573 13:38:06.182129 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9574 13:38:06.188916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9575 13:38:06.192026 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9576 13:38:06.195823 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9577 13:38:06.202074 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9578 13:38:06.205744 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9579 13:38:06.208881 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9580 13:38:06.215426 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9581 13:38:06.219057 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9582 13:38:06.222055 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9583 13:38:06.225866 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9584 13:38:06.231982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9585 13:38:06.235632 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9586 13:38:06.239085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9587 13:38:06.245445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9588 13:38:06.249099 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9589 13:38:06.252231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9590 13:38:06.259109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9591 13:38:06.262559 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9592 13:38:06.265940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9593 13:38:06.272395 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9594 13:38:06.275779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9595 13:38:06.282427 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9596 13:38:06.286201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9597 13:38:06.289354 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9598 13:38:06.296165 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9599 13:38:06.299395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9600 13:38:06.303060 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9601 13:38:06.309500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9602 13:38:06.313199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9603 13:38:06.319513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9604 13:38:06.322905 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9605 13:38:06.326399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9606 13:38:06.333171 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9607 13:38:06.336433 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9608 13:38:06.339541 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9609 13:38:06.346174 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9610 13:38:06.349839 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9611 13:38:06.356323 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9612 13:38:06.360077 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9613 13:38:06.363044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9614 13:38:06.369910 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9615 13:38:06.373525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9616 13:38:06.376492 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9617 13:38:06.383221 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9618 13:38:06.386898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9619 13:38:06.393850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9620 13:38:06.396790 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9621 13:38:06.399905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9622 13:38:06.406729 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9623 13:38:06.410005 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9624 13:38:06.413579 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9625 13:38:06.419912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9626 13:38:06.423406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9627 13:38:06.430433 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9628 13:38:06.433776 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9629 13:38:06.436877 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9630 13:38:06.443816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9631 13:38:06.446910 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9632 13:38:06.453501 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9633 13:38:06.456672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9634 13:38:06.459919 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9635 13:38:06.467086 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9636 13:38:06.470236 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9637 13:38:06.473442 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9638 13:38:06.480331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9639 13:38:06.483405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9640 13:38:06.490257 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9641 13:38:06.493346 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9642 13:38:06.497161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9643 13:38:06.503409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9644 13:38:06.506967 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9645 13:38:06.513178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9646 13:38:06.516891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9647 13:38:06.520195 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9648 13:38:06.526433 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9649 13:38:06.529993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9650 13:38:06.536793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9651 13:38:06.540133 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9652 13:38:06.543265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9653 13:38:06.549994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9654 13:38:06.553579 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9655 13:38:06.560030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9656 13:38:06.563334 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9657 13:38:06.566931 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9658 13:38:06.573406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9659 13:38:06.576856 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9660 13:38:06.583589 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9661 13:38:06.586874 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9662 13:38:06.590475 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9663 13:38:06.596680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9664 13:38:06.600000 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9665 13:38:06.606724 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9666 13:38:06.610348 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9667 13:38:06.613732 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9668 13:38:06.620415 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9669 13:38:06.623576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9670 13:38:06.630566 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9671 13:38:06.633602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9672 13:38:06.636767 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9673 13:38:06.643266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9674 13:38:06.646757 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9675 13:38:06.653401 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9676 13:38:06.657069 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9677 13:38:06.663296 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9678 13:38:06.667166 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9679 13:38:06.670272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9680 13:38:06.677056 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9681 13:38:06.680377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9682 13:38:06.686947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9683 13:38:06.690469 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9684 13:38:06.693847 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9685 13:38:06.700110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9686 13:38:06.703547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9687 13:38:06.710340 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9688 13:38:06.713447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9689 13:38:06.719999 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9690 13:38:06.723599 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9691 13:38:06.726693 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9692 13:38:06.733538 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9693 13:38:06.736757 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9694 13:38:06.740419 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9695 13:38:06.743475 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9696 13:38:06.747064 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9697 13:38:06.753772 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9698 13:38:06.757208 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9699 13:38:06.763787 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9700 13:38:06.766713 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9701 13:38:06.770559 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9702 13:38:06.777291 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9703 13:38:06.780410 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9704 13:38:06.783528 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9705 13:38:06.790284 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9706 13:38:06.793527 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9707 13:38:06.797094 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9708 13:38:06.803834 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9709 13:38:06.806940 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9710 13:38:06.813768 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9711 13:38:06.816952 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9712 13:38:06.820067 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9713 13:38:06.826914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9714 13:38:06.830067 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9715 13:38:06.833623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9716 13:38:06.840512 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9717 13:38:06.843440 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9718 13:38:06.846713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9719 13:38:06.853997 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9720 13:38:06.857002 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9721 13:38:06.860105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9722 13:38:06.866804 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9723 13:38:06.870072 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9724 13:38:06.873559 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9725 13:38:06.880069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9726 13:38:06.883965 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9727 13:38:06.890727 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9728 13:38:06.893889 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9729 13:38:06.897191 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9730 13:38:06.904010 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9731 13:38:06.907233 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9732 13:38:06.910208 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9733 13:38:06.913854 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9734 13:38:06.920679 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9735 13:38:06.923856 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9736 13:38:06.926934 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9737 13:38:06.930494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9738 13:38:06.933903 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9739 13:38:06.940262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9740 13:38:06.943628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9741 13:38:06.947222 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9742 13:38:06.950372 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9743 13:38:06.957525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9744 13:38:06.960567 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9745 13:38:06.964113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9746 13:38:06.970229 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9747 13:38:06.974041 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9748 13:38:06.980906 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9749 13:38:06.983760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9750 13:38:06.990568 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9751 13:38:06.993602 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9752 13:38:06.996883 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9753 13:38:07.003689 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9754 13:38:07.007421 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9755 13:38:07.013817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9756 13:38:07.016967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9757 13:38:07.020712 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9758 13:38:07.026886 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9759 13:38:07.030565 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9760 13:38:07.033661 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9761 13:38:07.040453 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9762 13:38:07.044130 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9763 13:38:07.050931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9764 13:38:07.054337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9765 13:38:07.060692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9766 13:38:07.064140 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9767 13:38:07.067382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9768 13:38:07.073963 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9769 13:38:07.077166 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9770 13:38:07.083535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9771 13:38:07.087041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9772 13:38:07.090095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9773 13:38:07.097118 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9774 13:38:07.100176 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9775 13:38:07.106958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9776 13:38:07.110204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9777 13:38:07.113353 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9778 13:38:07.120151 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9779 13:38:07.123975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9780 13:38:07.130230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9781 13:38:07.133861 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9782 13:38:07.136903 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9783 13:38:07.143673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9784 13:38:07.146815 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9785 13:38:07.153597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9786 13:38:07.156841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9787 13:38:07.160551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9788 13:38:07.166707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9789 13:38:07.170457 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9790 13:38:07.176697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9791 13:38:07.180480 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9792 13:38:07.183567 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9793 13:38:07.190274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9794 13:38:07.193553 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9795 13:38:07.200105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9796 13:38:07.203420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9797 13:38:07.210112 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9798 13:38:07.213808 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9799 13:38:07.216838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9800 13:38:07.223493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9801 13:38:07.227179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9802 13:38:07.230217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9803 13:38:07.237150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9804 13:38:07.240358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9805 13:38:07.246939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9806 13:38:07.250621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9807 13:38:07.257303 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9808 13:38:07.260428 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9809 13:38:07.263646 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9810 13:38:07.270368 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9811 13:38:07.273505 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9812 13:38:07.280090 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9813 13:38:07.283858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9814 13:38:07.286872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9815 13:38:07.293809 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9816 13:38:07.296836 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9817 13:38:07.300562 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9818 13:38:07.306960 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9819 13:38:07.310085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9820 13:38:07.316971 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9821 13:38:07.320571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9822 13:38:07.327037 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9823 13:38:07.330389 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9824 13:38:07.333479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9825 13:38:07.340082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9826 13:38:07.344022 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9827 13:38:07.350124 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9828 13:38:07.353992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9829 13:38:07.360922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9830 13:38:07.363643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9831 13:38:07.370554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9832 13:38:07.374118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9833 13:38:07.377183 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9834 13:38:07.383973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9835 13:38:07.386960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9836 13:38:07.393665 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9837 13:38:07.397487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9838 13:38:07.400612 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9839 13:38:07.407481 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9840 13:38:07.410393 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9841 13:38:07.417105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9842 13:38:07.420776 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9843 13:38:07.427276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9844 13:38:07.430415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9845 13:38:07.434144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9846 13:38:07.440429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9847 13:38:07.443845 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9848 13:38:07.450646 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9849 13:38:07.454224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9850 13:38:07.460609 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9851 13:38:07.463762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9852 13:38:07.467553 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9853 13:38:07.474324 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9854 13:38:07.477443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9855 13:38:07.484207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9856 13:38:07.487287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9857 13:38:07.490920 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9858 13:38:07.497487 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9859 13:38:07.500739 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9860 13:38:07.507150 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9861 13:38:07.510685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9862 13:38:07.517542 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9863 13:38:07.520508 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9864 13:38:07.527089 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9865 13:38:07.530776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9866 13:38:07.534054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9867 13:38:07.540505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9868 13:38:07.543844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9869 13:38:07.550037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9870 13:38:07.553722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9871 13:38:07.560263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9872 13:38:07.563876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9873 13:38:07.570302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9874 13:38:07.573649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9875 13:38:07.580142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9876 13:38:07.583620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9877 13:38:07.590528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9878 13:38:07.593708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9879 13:38:07.596794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9880 13:38:07.604132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9881 13:38:07.607166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9882 13:38:07.613472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9883 13:38:07.617101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9884 13:38:07.623859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9885 13:38:07.626900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9886 13:38:07.633961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9887 13:38:07.636914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9888 13:38:07.643660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9889 13:38:07.646953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9890 13:38:07.653826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9891 13:38:07.656955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9892 13:38:07.663842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9893 13:38:07.667287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9894 13:38:07.674121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9895 13:38:07.677234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9896 13:38:07.683605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9897 13:38:07.687036 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9898 13:38:07.690338 INFO: [APUAPC] vio 0
9899 13:38:07.693697 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9900 13:38:07.700466 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9901 13:38:07.703805 INFO: [APUAPC] D0_APC_0: 0x400510
9902 13:38:07.703912 INFO: [APUAPC] D0_APC_1: 0x0
9903 13:38:07.707408 INFO: [APUAPC] D0_APC_2: 0x1540
9904 13:38:07.710523 INFO: [APUAPC] D0_APC_3: 0x0
9905 13:38:07.713594 INFO: [APUAPC] D1_APC_0: 0xffffffff
9906 13:38:07.717348 INFO: [APUAPC] D1_APC_1: 0xffffffff
9907 13:38:07.720472 INFO: [APUAPC] D1_APC_2: 0x3fffff
9908 13:38:07.723895 INFO: [APUAPC] D1_APC_3: 0x0
9909 13:38:07.727007 INFO: [APUAPC] D2_APC_0: 0xffffffff
9910 13:38:07.730720 INFO: [APUAPC] D2_APC_1: 0xffffffff
9911 13:38:07.734019 INFO: [APUAPC] D2_APC_2: 0x3fffff
9912 13:38:07.736898 INFO: [APUAPC] D2_APC_3: 0x0
9913 13:38:07.740403 INFO: [APUAPC] D3_APC_0: 0xffffffff
9914 13:38:07.743802 INFO: [APUAPC] D3_APC_1: 0xffffffff
9915 13:38:07.746927 INFO: [APUAPC] D3_APC_2: 0x3fffff
9916 13:38:07.750626 INFO: [APUAPC] D3_APC_3: 0x0
9917 13:38:07.753939 INFO: [APUAPC] D4_APC_0: 0xffffffff
9918 13:38:07.757566 INFO: [APUAPC] D4_APC_1: 0xffffffff
9919 13:38:07.760638 INFO: [APUAPC] D4_APC_2: 0x3fffff
9920 13:38:07.763851 INFO: [APUAPC] D4_APC_3: 0x0
9921 13:38:07.766946 INFO: [APUAPC] D5_APC_0: 0xffffffff
9922 13:38:07.770500 INFO: [APUAPC] D5_APC_1: 0xffffffff
9923 13:38:07.773949 INFO: [APUAPC] D5_APC_2: 0x3fffff
9924 13:38:07.777132 INFO: [APUAPC] D5_APC_3: 0x0
9925 13:38:07.780847 INFO: [APUAPC] D6_APC_0: 0xffffffff
9926 13:38:07.783829 INFO: [APUAPC] D6_APC_1: 0xffffffff
9927 13:38:07.787046 INFO: [APUAPC] D6_APC_2: 0x3fffff
9928 13:38:07.790869 INFO: [APUAPC] D6_APC_3: 0x0
9929 13:38:07.793894 INFO: [APUAPC] D7_APC_0: 0xffffffff
9930 13:38:07.797297 INFO: [APUAPC] D7_APC_1: 0xffffffff
9931 13:38:07.800341 INFO: [APUAPC] D7_APC_2: 0x3fffff
9932 13:38:07.800425 INFO: [APUAPC] D7_APC_3: 0x0
9933 13:38:07.807172 INFO: [APUAPC] D8_APC_0: 0xffffffff
9934 13:38:07.810570 INFO: [APUAPC] D8_APC_1: 0xffffffff
9935 13:38:07.813926 INFO: [APUAPC] D8_APC_2: 0x3fffff
9936 13:38:07.814009 INFO: [APUAPC] D8_APC_3: 0x0
9937 13:38:07.817246 INFO: [APUAPC] D9_APC_0: 0xffffffff
9938 13:38:07.820399 INFO: [APUAPC] D9_APC_1: 0xffffffff
9939 13:38:07.824016 INFO: [APUAPC] D9_APC_2: 0x3fffff
9940 13:38:07.827057 INFO: [APUAPC] D9_APC_3: 0x0
9941 13:38:07.830158 INFO: [APUAPC] D10_APC_0: 0xffffffff
9942 13:38:07.833950 INFO: [APUAPC] D10_APC_1: 0xffffffff
9943 13:38:07.837133 INFO: [APUAPC] D10_APC_2: 0x3fffff
9944 13:38:07.840244 INFO: [APUAPC] D10_APC_3: 0x0
9945 13:38:07.843942 INFO: [APUAPC] D11_APC_0: 0xffffffff
9946 13:38:07.847000 INFO: [APUAPC] D11_APC_1: 0xffffffff
9947 13:38:07.850332 INFO: [APUAPC] D11_APC_2: 0x3fffff
9948 13:38:07.853887 INFO: [APUAPC] D11_APC_3: 0x0
9949 13:38:07.856924 INFO: [APUAPC] D12_APC_0: 0xffffffff
9950 13:38:07.860662 INFO: [APUAPC] D12_APC_1: 0xffffffff
9951 13:38:07.863784 INFO: [APUAPC] D12_APC_2: 0x3fffff
9952 13:38:07.867027 INFO: [APUAPC] D12_APC_3: 0x0
9953 13:38:07.870691 INFO: [APUAPC] D13_APC_0: 0xffffffff
9954 13:38:07.873799 INFO: [APUAPC] D13_APC_1: 0xffffffff
9955 13:38:07.876936 INFO: [APUAPC] D13_APC_2: 0x3fffff
9956 13:38:07.880594 INFO: [APUAPC] D13_APC_3: 0x0
9957 13:38:07.883505 INFO: [APUAPC] D14_APC_0: 0xffffffff
9958 13:38:07.887350 INFO: [APUAPC] D14_APC_1: 0xffffffff
9959 13:38:07.890370 INFO: [APUAPC] D14_APC_2: 0x3fffff
9960 13:38:07.893556 INFO: [APUAPC] D14_APC_3: 0x0
9961 13:38:07.897373 INFO: [APUAPC] D15_APC_0: 0xffffffff
9962 13:38:07.900744 INFO: [APUAPC] D15_APC_1: 0xffffffff
9963 13:38:07.904032 INFO: [APUAPC] D15_APC_2: 0x3fffff
9964 13:38:07.906922 INFO: [APUAPC] D15_APC_3: 0x0
9965 13:38:07.910220 INFO: [APUAPC] APC_CON: 0x4
9966 13:38:07.914030 INFO: [NOCDAPC] D0_APC_0: 0x0
9967 13:38:07.917286 INFO: [NOCDAPC] D0_APC_1: 0x0
9968 13:38:07.920282 INFO: [NOCDAPC] D1_APC_0: 0x0
9969 13:38:07.923788 INFO: [NOCDAPC] D1_APC_1: 0xfff
9970 13:38:07.927086 INFO: [NOCDAPC] D2_APC_0: 0x0
9971 13:38:07.930606 INFO: [NOCDAPC] D2_APC_1: 0xfff
9972 13:38:07.930694 INFO: [NOCDAPC] D3_APC_0: 0x0
9973 13:38:07.934096 INFO: [NOCDAPC] D3_APC_1: 0xfff
9974 13:38:07.937244 INFO: [NOCDAPC] D4_APC_0: 0x0
9975 13:38:07.940458 INFO: [NOCDAPC] D4_APC_1: 0xfff
9976 13:38:07.943519 INFO: [NOCDAPC] D5_APC_0: 0x0
9977 13:38:07.947390 INFO: [NOCDAPC] D5_APC_1: 0xfff
9978 13:38:07.950465 INFO: [NOCDAPC] D6_APC_0: 0x0
9979 13:38:07.954051 INFO: [NOCDAPC] D6_APC_1: 0xfff
9980 13:38:07.957092 INFO: [NOCDAPC] D7_APC_0: 0x0
9981 13:38:07.960470 INFO: [NOCDAPC] D7_APC_1: 0xfff
9982 13:38:07.960556 INFO: [NOCDAPC] D8_APC_0: 0x0
9983 13:38:07.963878 INFO: [NOCDAPC] D8_APC_1: 0xfff
9984 13:38:07.967402 INFO: [NOCDAPC] D9_APC_0: 0x0
9985 13:38:07.970479 INFO: [NOCDAPC] D9_APC_1: 0xfff
9986 13:38:07.973690 INFO: [NOCDAPC] D10_APC_0: 0x0
9987 13:38:07.977440 INFO: [NOCDAPC] D10_APC_1: 0xfff
9988 13:38:07.980521 INFO: [NOCDAPC] D11_APC_0: 0x0
9989 13:38:07.984079 INFO: [NOCDAPC] D11_APC_1: 0xfff
9990 13:38:07.987059 INFO: [NOCDAPC] D12_APC_0: 0x0
9991 13:38:07.990539 INFO: [NOCDAPC] D12_APC_1: 0xfff
9992 13:38:07.994190 INFO: [NOCDAPC] D13_APC_0: 0x0
9993 13:38:07.997423 INFO: [NOCDAPC] D13_APC_1: 0xfff
9994 13:38:08.000439 INFO: [NOCDAPC] D14_APC_0: 0x0
9995 13:38:08.000564 INFO: [NOCDAPC] D14_APC_1: 0xfff
9996 13:38:08.004112 INFO: [NOCDAPC] D15_APC_0: 0x0
9997 13:38:08.007265 INFO: [NOCDAPC] D15_APC_1: 0xfff
9998 13:38:08.010466 INFO: [NOCDAPC] APC_CON: 0x4
9999 13:38:08.014098 INFO: [APUAPC] set_apusys_apc done
10000 13:38:08.017353 INFO: [DEVAPC] devapc_init done
10001 13:38:08.020418 INFO: GICv3 without legacy support detected.
10002 13:38:08.027272 INFO: ARM GICv3 driver initialized in EL3
10003 13:38:08.030415 INFO: Maximum SPI INTID supported: 639
10004 13:38:08.033796 INFO: BL31: Initializing runtime services
10005 13:38:08.040341 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10006 13:38:08.040421 INFO: SPM: enable CPC mode
10007 13:38:08.047616 INFO: mcdi ready for mcusys-off-idle and system suspend
10008 13:38:08.050699 INFO: BL31: Preparing for EL3 exit to normal world
10009 13:38:08.057011 INFO: Entry point address = 0x80000000
10010 13:38:08.057117 INFO: SPSR = 0x8
10011 13:38:08.063204
10012 13:38:08.063281
10013 13:38:08.063344
10014 13:38:08.064070 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10015 13:38:08.064190 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10016 13:38:08.064274 Setting prompt string to ['asurada:']
10017 13:38:08.064367 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10018 13:38:08.066977 Starting depthcharge on Spherion...
10019 13:38:08.067085
10020 13:38:08.067183 Wipe memory regions:
10021 13:38:08.067272
10022 13:38:08.070241 [0x00000040000000, 0x00000054600000)
10023 13:38:08.192438
10024 13:38:08.192576 [0x00000054660000, 0x00000080000000)
10025 13:38:08.452673
10026 13:38:08.452823 [0x000000821a7280, 0x000000ffe64000)
10027 13:38:09.197333
10028 13:38:09.197507 [0x00000100000000, 0x00000240000000)
10029 13:38:11.086743
10030 13:38:11.089899 Initializing XHCI USB controller at 0x11200000.
10031 13:38:12.127718
10032 13:38:12.130837 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10033 13:38:12.130962
10034 13:38:12.131027
10035 13:38:12.131318 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 13:38:12.231625 asurada: tftpboot 192.168.201.1 14063021/tftp-deploy-00ockxyd/kernel/image.itb 14063021/tftp-deploy-00ockxyd/kernel/cmdline
10038 13:38:12.231819 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 13:38:12.231949 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10040 13:38:12.236144 tftpboot 192.168.201.1 14063021/tftp-deploy-00ockxyd/kernel/image.itp-deploy-00ockxyd/kernel/cmdline
10041 13:38:12.236236
10042 13:38:12.236330 Waiting for link
10043 13:38:12.396610
10044 13:38:12.396772 R8152: Initializing
10045 13:38:12.396876
10046 13:38:12.400080 Version 6 (ocp_data = 5c30)
10047 13:38:12.400183
10048 13:38:12.403105 R8152: Done initializing
10049 13:38:12.403179
10050 13:38:12.403241 Adding net device
10051 13:38:14.337782
10052 13:38:14.337968 done.
10053 13:38:14.338084
10054 13:38:14.338177 MAC: 00:24:32:30:78:52
10055 13:38:14.338272
10056 13:38:14.341039 Sending DHCP discover... done.
10057 13:38:14.341218
10058 13:38:14.344800 Waiting for reply... done.
10059 13:38:14.344920
10060 13:38:14.347807 Sending DHCP request... done.
10061 13:38:14.347910
10062 13:38:14.352132 Waiting for reply... done.
10063 13:38:14.352254
10064 13:38:14.352348 My ip is 192.168.201.14
10065 13:38:14.352453
10066 13:38:14.355552 The DHCP server ip is 192.168.201.1
10067 13:38:14.355660
10068 13:38:14.362248 TFTP server IP predefined by user: 192.168.201.1
10069 13:38:14.362373
10070 13:38:14.368958 Bootfile predefined by user: 14063021/tftp-deploy-00ockxyd/kernel/image.itb
10071 13:38:14.369055
10072 13:38:14.369121 Sending tftp read request... done.
10073 13:38:14.372298
10074 13:38:14.375757 Waiting for the transfer...
10075 13:38:14.375849
10076 13:38:14.900515 00000000 ################################################################
10077 13:38:14.900657
10078 13:38:15.426686 00080000 ################################################################
10079 13:38:15.426827
10080 13:38:15.949527 00100000 ################################################################
10081 13:38:15.949668
10082 13:38:16.471393 00180000 ################################################################
10083 13:38:16.471540
10084 13:38:16.993024 00200000 ################################################################
10085 13:38:16.993161
10086 13:38:17.515993 00280000 ################################################################
10087 13:38:17.516154
10088 13:38:18.036775 00300000 ################################################################
10089 13:38:18.036918
10090 13:38:18.562481 00380000 ################################################################
10091 13:38:18.562630
10092 13:38:19.087261 00400000 ################################################################
10093 13:38:19.087395
10094 13:38:19.614358 00480000 ################################################################
10095 13:38:19.614510
10096 13:38:20.144373 00500000 ################################################################
10097 13:38:20.144514
10098 13:38:20.669345 00580000 ################################################################
10099 13:38:20.669532
10100 13:38:21.196242 00600000 ################################################################
10101 13:38:21.196377
10102 13:38:21.721743 00680000 ################################################################
10103 13:38:21.721895
10104 13:38:22.242889 00700000 ################################################################
10105 13:38:22.243025
10106 13:38:22.776205 00780000 ################################################################
10107 13:38:22.776386
10108 13:38:23.301075 00800000 ################################################################
10109 13:38:23.301214
10110 13:38:23.843081 00880000 ################################################################
10111 13:38:23.843256
10112 13:38:24.363241 00900000 ################################################################
10113 13:38:24.363416
10114 13:38:24.883879 00980000 ################################################################
10115 13:38:24.884018
10116 13:38:25.433962 00a00000 ################################################################
10117 13:38:25.434095
10118 13:38:25.961423 00a80000 ################################################################
10119 13:38:25.961589
10120 13:38:26.490276 00b00000 ################################################################
10121 13:38:26.490431
10122 13:38:27.024072 00b80000 ################################################################
10123 13:38:27.024237
10124 13:38:27.550851 00c00000 ################################################################
10125 13:38:27.551016
10126 13:38:28.091687 00c80000 ################################################################
10127 13:38:28.091853
10128 13:38:28.656982 00d00000 ################################################################
10129 13:38:28.657153
10130 13:38:29.206717 00d80000 ################################################################
10131 13:38:29.206861
10132 13:38:29.766459 00e00000 ################################################################
10133 13:38:29.766590
10134 13:38:30.322405 00e80000 ################################################################
10135 13:38:30.322550
10136 13:38:30.873292 00f00000 ################################################################
10137 13:38:30.873429
10138 13:38:31.426812 00f80000 ################################################################
10139 13:38:31.426980
10140 13:38:31.982367 01000000 ################################################################
10141 13:38:31.982526
10142 13:38:32.515662 01080000 ################################################################
10143 13:38:32.515799
10144 13:38:33.049427 01100000 ################################################################
10145 13:38:33.049570
10146 13:38:33.583916 01180000 ################################################################
10147 13:38:33.584072
10148 13:38:34.134961 01200000 ################################################################
10149 13:38:34.135110
10150 13:38:34.688901 01280000 ################################################################
10151 13:38:34.689077
10152 13:38:35.245609 01300000 ################################################################
10153 13:38:35.245745
10154 13:38:35.810137 01380000 ################################################################
10155 13:38:35.810270
10156 13:38:36.350680 01400000 ################################################################
10157 13:38:36.350891
10158 13:38:36.895813 01480000 ################################################################
10159 13:38:36.895980
10160 13:38:37.462232 01500000 ################################################################
10161 13:38:37.462376
10162 13:38:38.039097 01580000 ################################################################
10163 13:38:38.039238
10164 13:38:38.599881 01600000 ################################################################
10165 13:38:38.600022
10166 13:38:39.151318 01680000 ################################################################
10167 13:38:39.151454
10168 13:38:39.718655 01700000 ################################################################
10169 13:38:39.718791
10170 13:38:40.261271 01780000 ################################################################
10171 13:38:40.261428
10172 13:38:40.804851 01800000 ################################################################
10173 13:38:40.805010
10174 13:38:41.446461 01880000 ################################################################
10175 13:38:41.446599
10176 13:38:42.070593 01900000 ################################################################
10177 13:38:42.070772
10178 13:38:42.649446 01980000 ################################################################
10179 13:38:42.649583
10180 13:38:43.201959 01a00000 ################################################################
10181 13:38:43.202114
10182 13:38:43.825890 01a80000 ################################################################
10183 13:38:43.826042
10184 13:38:44.466321 01b00000 ################################################################
10185 13:38:44.466502
10186 13:38:45.086276 01b80000 ################################################################
10187 13:38:45.086467
10188 13:38:45.642498 01c00000 ################################################################
10189 13:38:45.642640
10190 13:38:46.209149 01c80000 ################################################################
10191 13:38:46.209283
10192 13:38:46.772965 01d00000 ################################################################
10193 13:38:46.773136
10194 13:38:47.330175 01d80000 ################################################################
10195 13:38:47.330313
10196 13:38:47.867887 01e00000 ################################################################
10197 13:38:47.868020
10198 13:38:48.415570 01e80000 ################################################################
10199 13:38:48.415741
10200 13:38:48.974833 01f00000 ################################################################
10201 13:38:48.974970
10202 13:38:49.542482 01f80000 ################################################################
10203 13:38:49.542692
10204 13:38:50.080082 02000000 ################################################################
10205 13:38:50.080238
10206 13:38:50.478510 02080000 ############################################### done.
10207 13:38:50.478639
10208 13:38:50.482015 The bootfile was 34456102 bytes long.
10209 13:38:50.482103
10210 13:38:50.485164 Sending tftp read request... done.
10211 13:38:50.485249
10212 13:38:50.488748 Waiting for the transfer...
10213 13:38:50.488849
10214 13:38:50.488954 00000000 # done.
10215 13:38:50.489051
10216 13:38:50.494687 Command line loaded dynamically from TFTP file: 14063021/tftp-deploy-00ockxyd/kernel/cmdline
10217 13:38:50.498328
10218 13:38:50.508675 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10219 13:38:50.511625
10220 13:38:50.511714 Loading FIT.
10221 13:38:50.511780
10222 13:38:50.514801 Image ramdisk-1 has 21345508 bytes.
10223 13:38:50.514879
10224 13:38:50.518537 Image fdt-1 has 47258 bytes.
10225 13:38:50.518620
10226 13:38:50.518754 Image kernel-1 has 13061303 bytes.
10227 13:38:50.522228
10228 13:38:50.528513 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10229 13:38:50.528599
10230 13:38:50.546066 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10231 13:38:50.546179
10232 13:38:50.552192 Choosing best match conf-1 for compat google,spherion-rev2.
10233 13:38:50.556046
10234 13:38:50.560694 Connected to device vid:did:rid of 1ae0:0028:00
10235 13:38:50.568935
10236 13:38:50.572665 tpm_get_response: command 0x17b, return code 0x0
10237 13:38:50.572758
10238 13:38:50.575823 ec_init: CrosEC protocol v3 supported (256, 248)
10239 13:38:50.580440
10240 13:38:50.584301 tpm_cleanup: add release locality here.
10241 13:38:50.584386
10242 13:38:50.584452 Shutting down all USB controllers.
10243 13:38:50.587297
10244 13:38:50.587381 Removing current net device
10245 13:38:50.587447
10246 13:38:50.594076 Exiting depthcharge with code 4 at timestamp: 71849923
10247 13:38:50.594163
10248 13:38:50.597513 LZMA decompressing kernel-1 to 0x821a6718
10249 13:38:50.597598
10250 13:38:50.600552 LZMA decompressing kernel-1 to 0x40000000
10251 13:38:52.210948
10252 13:38:52.211078 jumping to kernel
10253 13:38:52.211555 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10254 13:38:52.211659 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10255 13:38:52.211742 Setting prompt string to ['Linux version [0-9]']
10256 13:38:52.211813 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10257 13:38:52.211881 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10258 13:38:52.294469
10259 13:38:52.297358 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10260 13:38:52.301201 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10261 13:38:52.301310 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10262 13:38:52.301384 Setting prompt string to []
10263 13:38:52.301482 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10264 13:38:52.301593 Using line separator: #'\n'#
10265 13:38:52.301681 No login prompt set.
10266 13:38:52.301781 Parsing kernel messages
10267 13:38:52.301851 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10268 13:38:52.301951 [login-action] Waiting for messages, (timeout 00:03:41)
10269 13:38:52.302019 Waiting using forced prompt support (timeout 00:01:50)
10270 13:38:52.321135 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10271 13:38:52.324141 [ 0.000000] random: crng init done
10272 13:38:52.327798 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10273 13:38:52.330761 [ 0.000000] efi: UEFI not found.
10274 13:38:52.341106 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10275 13:38:52.347676 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10276 13:38:52.357574 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10277 13:38:52.367735 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10278 13:38:52.374557 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10279 13:38:52.377417 [ 0.000000] printk: bootconsole [mtk8250] enabled
10280 13:38:52.386144 [ 0.000000] NUMA: No NUMA configuration found
10281 13:38:52.392540 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10282 13:38:52.399344 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10283 13:38:52.399434 [ 0.000000] Zone ranges:
10284 13:38:52.406158 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10285 13:38:52.409655 [ 0.000000] DMA32 empty
10286 13:38:52.416164 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10287 13:38:52.419261 [ 0.000000] Movable zone start for each node
10288 13:38:52.422427 [ 0.000000] Early memory node ranges
10289 13:38:52.429092 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10290 13:38:52.435794 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10291 13:38:52.442841 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10292 13:38:52.449434 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10293 13:38:52.456133 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10294 13:38:52.462402 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10295 13:38:52.518846 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10296 13:38:52.525686 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10297 13:38:52.531719 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10298 13:38:52.535578 [ 0.000000] psci: probing for conduit method from DT.
10299 13:38:52.541980 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10300 13:38:52.545113 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10301 13:38:52.552314 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10302 13:38:52.555218 [ 0.000000] psci: SMC Calling Convention v1.2
10303 13:38:52.562041 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10304 13:38:52.565023 [ 0.000000] Detected VIPT I-cache on CPU0
10305 13:38:52.571752 [ 0.000000] CPU features: detected: GIC system register CPU interface
10306 13:38:52.578852 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10307 13:38:52.585383 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10308 13:38:52.592368 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10309 13:38:52.598860 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10310 13:38:52.605375 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10311 13:38:52.612168 [ 0.000000] alternatives: applying boot alternatives
10312 13:38:52.614975 [ 0.000000] Fallback order for Node 0: 0
10313 13:38:52.621905 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10314 13:38:52.625111 [ 0.000000] Policy zone: Normal
10315 13:38:52.641824 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10316 13:38:52.652115 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10317 13:38:52.663325 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10318 13:38:52.672890 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10319 13:38:52.679566 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10320 13:38:52.683243 <6>[ 0.000000] software IO TLB: area num 8.
10321 13:38:52.739457 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10322 13:38:52.888635 <6>[ 0.000000] Memory: 7943344K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 409424K reserved, 32768K cma-reserved)
10323 13:38:52.895935 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10324 13:38:52.902630 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10325 13:38:52.905529 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10326 13:38:52.912374 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10327 13:38:52.919005 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10328 13:38:52.922126 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10329 13:38:52.932712 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10330 13:38:52.938931 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10331 13:38:52.941916 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10332 13:38:52.949638 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10333 13:38:52.952970 <6>[ 0.000000] GICv3: 608 SPIs implemented
10334 13:38:52.959768 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10335 13:38:52.963207 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10336 13:38:52.966430 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10337 13:38:52.976998 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10338 13:38:52.987027 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10339 13:38:53.000074 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10340 13:38:53.006678 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10341 13:38:53.015302 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10342 13:38:53.028491 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10343 13:38:53.035127 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10344 13:38:53.042001 <6>[ 0.009172] Console: colour dummy device 80x25
10345 13:38:53.051603 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10346 13:38:53.055174 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10347 13:38:53.061740 <6>[ 0.029243] LSM: Security Framework initializing
10348 13:38:53.068136 <6>[ 0.034181] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10349 13:38:53.078657 <6>[ 0.042041] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 13:38:53.085361 <6>[ 0.051457] cblist_init_generic: Setting adjustable number of callback queues.
10351 13:38:53.091916 <6>[ 0.058947] cblist_init_generic: Setting shift to 3 and lim to 1.
10352 13:38:53.101992 <6>[ 0.065287] cblist_init_generic: Setting adjustable number of callback queues.
10353 13:38:53.104972 <6>[ 0.072713] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 13:38:53.111815 <6>[ 0.079113] rcu: Hierarchical SRCU implementation.
10355 13:38:53.118600 <6>[ 0.084128] rcu: Max phase no-delay instances is 1000.
10356 13:38:53.125355 <6>[ 0.091146] EFI services will not be available.
10357 13:38:53.128386 <6>[ 0.096132] smp: Bringing up secondary CPUs ...
10358 13:38:53.136249 <6>[ 0.101183] Detected VIPT I-cache on CPU1
10359 13:38:53.142559 <6>[ 0.101253] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10360 13:38:53.149443 <6>[ 0.101283] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10361 13:38:53.153041 <6>[ 0.101625] Detected VIPT I-cache on CPU2
10362 13:38:53.159417 <6>[ 0.101679] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10363 13:38:53.166054 <6>[ 0.101697] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10364 13:38:53.172492 <6>[ 0.101958] Detected VIPT I-cache on CPU3
10365 13:38:53.179482 <6>[ 0.102007] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10366 13:38:53.186254 <6>[ 0.102023] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10367 13:38:53.189069 <6>[ 0.102329] CPU features: detected: Spectre-v4
10368 13:38:53.196190 <6>[ 0.102335] CPU features: detected: Spectre-BHB
10369 13:38:53.199293 <6>[ 0.102340] Detected PIPT I-cache on CPU4
10370 13:38:53.205921 <6>[ 0.102400] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10371 13:38:53.212837 <6>[ 0.102416] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10372 13:38:53.219593 <6>[ 0.102714] Detected PIPT I-cache on CPU5
10373 13:38:53.226176 <6>[ 0.102779] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10374 13:38:53.233044 <6>[ 0.102795] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10375 13:38:53.236046 <6>[ 0.103076] Detected PIPT I-cache on CPU6
10376 13:38:53.242723 <6>[ 0.103142] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10377 13:38:53.249473 <6>[ 0.103158] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10378 13:38:53.252830 <6>[ 0.103457] Detected PIPT I-cache on CPU7
10379 13:38:53.262826 <6>[ 0.103524] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10380 13:38:53.268988 <6>[ 0.103540] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10381 13:38:53.272714 <6>[ 0.103588] smp: Brought up 1 node, 8 CPUs
10382 13:38:53.275654 <6>[ 0.245005] SMP: Total of 8 processors activated.
10383 13:38:53.282555 <6>[ 0.249926] CPU features: detected: 32-bit EL0 Support
10384 13:38:53.292396 <6>[ 0.255321] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10385 13:38:53.299144 <6>[ 0.264176] CPU features: detected: Common not Private translations
10386 13:38:53.302537 <6>[ 0.270692] CPU features: detected: CRC32 instructions
10387 13:38:53.309185 <6>[ 0.276076] CPU features: detected: RCpc load-acquire (LDAPR)
10388 13:38:53.315597 <6>[ 0.282037] CPU features: detected: LSE atomic instructions
10389 13:38:53.322386 <6>[ 0.287818] CPU features: detected: Privileged Access Never
10390 13:38:53.325792 <6>[ 0.293598] CPU features: detected: RAS Extension Support
10391 13:38:53.335633 <6>[ 0.299206] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10392 13:38:53.338659 <6>[ 0.306468] CPU: All CPU(s) started at EL2
10393 13:38:53.345648 <6>[ 0.310785] alternatives: applying system-wide alternatives
10394 13:38:53.354223 <6>[ 0.321628] devtmpfs: initialized
10395 13:38:53.369882 <6>[ 0.330471] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10396 13:38:53.375991 <6>[ 0.340426] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10397 13:38:53.382712 <6>[ 0.348442] pinctrl core: initialized pinctrl subsystem
10398 13:38:53.386465 <6>[ 0.355118] DMI not present or invalid.
10399 13:38:53.392947 <6>[ 0.359525] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10400 13:38:53.402703 <6>[ 0.366378] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10401 13:38:53.409249 <6>[ 0.373960] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10402 13:38:53.419556 <6>[ 0.382173] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10403 13:38:53.422939 <6>[ 0.390411] audit: initializing netlink subsys (disabled)
10404 13:38:53.433080 <5>[ 0.396103] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10405 13:38:53.436203 <6>[ 0.396804] thermal_sys: Registered thermal governor 'step_wise'
10406 13:38:53.446153 <6>[ 0.404072] thermal_sys: Registered thermal governor 'power_allocator'
10407 13:38:53.449905 <6>[ 0.410329] cpuidle: using governor menu
10408 13:38:53.452879 <6>[ 0.421289] NET: Registered PF_QIPCRTR protocol family
10409 13:38:53.462850 <6>[ 0.426767] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10410 13:38:53.465848 <6>[ 0.433866] ASID allocator initialised with 32768 entries
10411 13:38:53.473131 <6>[ 0.440445] Serial: AMBA PL011 UART driver
10412 13:38:53.482095 <4>[ 0.449258] Trying to register duplicate clock ID: 134
10413 13:38:53.539915 <6>[ 0.510538] KASLR enabled
10414 13:38:53.554125 <6>[ 0.518201] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10415 13:38:53.560724 <6>[ 0.525211] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10416 13:38:53.567369 <6>[ 0.531698] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10417 13:38:53.574294 <6>[ 0.538699] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10418 13:38:53.580782 <6>[ 0.545186] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10419 13:38:53.587426 <6>[ 0.552186] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10420 13:38:53.594032 <6>[ 0.558669] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10421 13:38:53.600785 <6>[ 0.565676] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10422 13:38:53.603843 <6>[ 0.573117] ACPI: Interpreter disabled.
10423 13:38:53.611776 <6>[ 0.579568] iommu: Default domain type: Translated
10424 13:38:53.618707 <6>[ 0.584681] iommu: DMA domain TLB invalidation policy: strict mode
10425 13:38:53.622200 <5>[ 0.591338] SCSI subsystem initialized
10426 13:38:53.629099 <6>[ 0.595582] usbcore: registered new interface driver usbfs
10427 13:38:53.635252 <6>[ 0.601310] usbcore: registered new interface driver hub
10428 13:38:53.638651 <6>[ 0.606861] usbcore: registered new device driver usb
10429 13:38:53.645199 <6>[ 0.612972] pps_core: LinuxPPS API ver. 1 registered
10430 13:38:53.655666 <6>[ 0.618167] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10431 13:38:53.659314 <6>[ 0.627514] PTP clock support registered
10432 13:38:53.662088 <6>[ 0.631755] EDAC MC: Ver: 3.0.0
10433 13:38:53.669665 <6>[ 0.636937] FPGA manager framework
10434 13:38:53.672513 <6>[ 0.640611] Advanced Linux Sound Architecture Driver Initialized.
10435 13:38:53.676336 <6>[ 0.647377] vgaarb: loaded
10436 13:38:53.683024 <6>[ 0.650531] clocksource: Switched to clocksource arch_sys_counter
10437 13:38:53.690055 <5>[ 0.656969] VFS: Disk quotas dquot_6.6.0
10438 13:38:53.696812 <6>[ 0.661156] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10439 13:38:53.699884 <6>[ 0.668345] pnp: PnP ACPI: disabled
10440 13:38:53.707478 <6>[ 0.674999] NET: Registered PF_INET protocol family
10441 13:38:53.717171 <6>[ 0.680594] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10442 13:38:53.728482 <6>[ 0.692862] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10443 13:38:53.738794 <6>[ 0.701680] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10444 13:38:53.745541 <6>[ 0.709655] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10445 13:38:53.752184 <6>[ 0.718350] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10446 13:38:53.763849 <6>[ 0.728064] TCP: Hash tables configured (established 65536 bind 65536)
10447 13:38:53.770345 <6>[ 0.734932] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 13:38:53.777030 <6>[ 0.742126] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10449 13:38:53.783651 <6>[ 0.749835] NET: Registered PF_UNIX/PF_LOCAL protocol family
10450 13:38:53.790344 <6>[ 0.755988] RPC: Registered named UNIX socket transport module.
10451 13:38:53.793853 <6>[ 0.762141] RPC: Registered udp transport module.
10452 13:38:53.800317 <6>[ 0.767071] RPC: Registered tcp transport module.
10453 13:38:53.806835 <6>[ 0.772000] RPC: Registered tcp NFSv4.1 backchannel transport module.
10454 13:38:53.810525 <6>[ 0.778668] PCI: CLS 0 bytes, default 64
10455 13:38:53.813491 <6>[ 0.783040] Unpacking initramfs...
10456 13:38:53.838173 <6>[ 0.802649] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10457 13:38:53.848072 <6>[ 0.811298] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10458 13:38:53.851347 <6>[ 0.820132] kvm [1]: IPA Size Limit: 40 bits
10459 13:38:53.858802 <6>[ 0.824657] kvm [1]: GICv3: no GICV resource entry
10460 13:38:53.861577 <6>[ 0.829678] kvm [1]: disabling GICv2 emulation
10461 13:38:53.867990 <6>[ 0.834363] kvm [1]: GIC system register CPU interface enabled
10462 13:38:53.871419 <6>[ 0.840524] kvm [1]: vgic interrupt IRQ18
10463 13:38:53.878175 <6>[ 0.844875] kvm [1]: VHE mode initialized successfully
10464 13:38:53.884853 <5>[ 0.851331] Initialise system trusted keyrings
10465 13:38:53.891684 <6>[ 0.856160] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10466 13:38:53.898443 <6>[ 0.866205] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10467 13:38:53.905540 <5>[ 0.872598] NFS: Registering the id_resolver key type
10468 13:38:53.909005 <5>[ 0.877902] Key type id_resolver registered
10469 13:38:53.915432 <5>[ 0.882317] Key type id_legacy registered
10470 13:38:53.922012 <6>[ 0.886593] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10471 13:38:53.928870 <6>[ 0.893519] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10472 13:38:53.935394 <6>[ 0.901227] 9p: Installing v9fs 9p2000 file system support
10473 13:38:53.973105 <5>[ 0.940334] Key type asymmetric registered
10474 13:38:53.975852 <5>[ 0.944663] Asymmetric key parser 'x509' registered
10475 13:38:53.986310 <6>[ 0.949794] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10476 13:38:53.989155 <6>[ 0.957407] io scheduler mq-deadline registered
10477 13:38:53.992930 <6>[ 0.962171] io scheduler kyber registered
10478 13:38:54.011532 <6>[ 0.979114] EINJ: ACPI disabled.
10479 13:38:54.044220 <4>[ 1.004883] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 13:38:54.053831 <4>[ 1.015506] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 13:38:54.068298 <6>[ 1.036218] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10482 13:38:54.076395 <6>[ 1.044173] printk: console [ttyS0] disabled
10483 13:38:54.104714 <6>[ 1.068801] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10484 13:38:54.111190 <6>[ 1.078271] printk: console [ttyS0] enabled
10485 13:38:54.114828 <6>[ 1.078271] printk: console [ttyS0] enabled
10486 13:38:54.121114 <6>[ 1.087168] printk: bootconsole [mtk8250] disabled
10487 13:38:54.124656 <6>[ 1.087168] printk: bootconsole [mtk8250] disabled
10488 13:38:54.131044 <6>[ 1.098178] SuperH (H)SCI(F) driver initialized
10489 13:38:54.134703 <6>[ 1.103456] msm_serial: driver initialized
10490 13:38:54.148362 <6>[ 1.112386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10491 13:38:54.158456 <6>[ 1.120932] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10492 13:38:54.164994 <6>[ 1.129473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10493 13:38:54.174780 <6>[ 1.138102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10494 13:38:54.184567 <6>[ 1.146808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10495 13:38:54.190928 <6>[ 1.155521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10496 13:38:54.201246 <6>[ 1.164068] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10497 13:38:54.207443 <6>[ 1.172866] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10498 13:38:54.217553 <6>[ 1.181410] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10499 13:38:54.229528 <6>[ 1.196970] loop: module loaded
10500 13:38:54.236189 <6>[ 1.202910] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10501 13:38:54.258329 <4>[ 1.226205] mtk-pmic-keys: Failed to locate of_node [id: -1]
10502 13:38:54.265284 <6>[ 1.233064] megasas: 07.719.03.00-rc1
10503 13:38:54.274716 <6>[ 1.242681] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10504 13:38:54.282520 <6>[ 1.249934] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10505 13:38:54.298950 <6>[ 1.266677] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10506 13:38:54.356031 <6>[ 1.316720] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10507 13:38:54.713719 <6>[ 1.681635] Freeing initrd memory: 20840K
10508 13:38:54.730141 <6>[ 1.697504] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10509 13:38:54.740939 <6>[ 1.708644] tun: Universal TUN/TAP device driver, 1.6
10510 13:38:54.744744 <6>[ 1.714725] thunder_xcv, ver 1.0
10511 13:38:54.747703 <6>[ 1.718220] thunder_bgx, ver 1.0
10512 13:38:54.750830 <6>[ 1.721717] nicpf, ver 1.0
10513 13:38:54.761933 <6>[ 1.725736] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10514 13:38:54.764838 <6>[ 1.733211] hns3: Copyright (c) 2017 Huawei Corporation.
10515 13:38:54.768082 <6>[ 1.738799] hclge is initializing
10516 13:38:54.774792 <6>[ 1.742378] e1000: Intel(R) PRO/1000 Network Driver
10517 13:38:54.781282 <6>[ 1.747507] e1000: Copyright (c) 1999-2006 Intel Corporation.
10518 13:38:54.784853 <6>[ 1.753520] e1000e: Intel(R) PRO/1000 Network Driver
10519 13:38:54.791686 <6>[ 1.758736] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10520 13:38:54.798602 <6>[ 1.764923] igb: Intel(R) Gigabit Ethernet Network Driver
10521 13:38:54.804886 <6>[ 1.770572] igb: Copyright (c) 2007-2014 Intel Corporation.
10522 13:38:54.811916 <6>[ 1.776409] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10523 13:38:54.814937 <6>[ 1.782926] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10524 13:38:54.821791 <6>[ 1.789387] sky2: driver version 1.30
10525 13:38:54.828517 <6>[ 1.794316] usbcore: registered new device driver r8152-cfgselector
10526 13:38:54.835130 <6>[ 1.800851] usbcore: registered new interface driver r8152
10527 13:38:54.838084 <6>[ 1.806668] VFIO - User Level meta-driver version: 0.3
10528 13:38:54.846976 <6>[ 1.814924] usbcore: registered new interface driver usb-storage
10529 13:38:54.853701 <6>[ 1.821368] usbcore: registered new device driver onboard-usb-hub
10530 13:38:54.863203 <6>[ 1.830545] mt6397-rtc mt6359-rtc: registered as rtc0
10531 13:38:54.873070 <6>[ 1.836005] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:38:55 UTC (1716903535)
10532 13:38:54.876032 <6>[ 1.845569] i2c_dev: i2c /dev entries driver
10533 13:38:54.893185 <6>[ 1.857364] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10534 13:38:54.899813 <4>[ 1.866094] cpu cpu0: supply cpu not found, using dummy regulator
10535 13:38:54.906351 <4>[ 1.872529] cpu cpu1: supply cpu not found, using dummy regulator
10536 13:38:54.913219 <4>[ 1.878936] cpu cpu2: supply cpu not found, using dummy regulator
10537 13:38:54.920104 <4>[ 1.885334] cpu cpu3: supply cpu not found, using dummy regulator
10538 13:38:54.926491 <4>[ 1.891739] cpu cpu4: supply cpu not found, using dummy regulator
10539 13:38:54.933678 <4>[ 1.898136] cpu cpu5: supply cpu not found, using dummy regulator
10540 13:38:54.936547 <4>[ 1.904569] cpu cpu6: supply cpu not found, using dummy regulator
10541 13:38:54.943180 <4>[ 1.910982] cpu cpu7: supply cpu not found, using dummy regulator
10542 13:38:54.964016 <6>[ 1.931610] cpu cpu0: EM: created perf domain
10543 13:38:54.967202 <6>[ 1.936540] cpu cpu4: EM: created perf domain
10544 13:38:54.974936 <6>[ 1.942171] sdhci: Secure Digital Host Controller Interface driver
10545 13:38:54.981729 <6>[ 1.948604] sdhci: Copyright(c) Pierre Ossman
10546 13:38:54.987951 <6>[ 1.953567] Synopsys Designware Multimedia Card Interface Driver
10547 13:38:54.994884 <6>[ 1.960202] sdhci-pltfm: SDHCI platform and OF driver helper
10548 13:38:54.998192 <6>[ 1.960244] mmc0: CQHCI version 5.10
10549 13:38:55.004769 <6>[ 1.970179] ledtrig-cpu: registered to indicate activity on CPUs
10550 13:38:55.011446 <6>[ 1.977181] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10551 13:38:55.018035 <6>[ 1.984229] usbcore: registered new interface driver usbhid
10552 13:38:55.021657 <6>[ 1.990051] usbhid: USB HID core driver
10553 13:38:55.027953 <6>[ 1.994250] spi_master spi0: will run message pump with realtime priority
10554 13:38:55.070415 <6>[ 2.031481] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10555 13:38:55.085690 <6>[ 2.046627] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10556 13:38:55.092858 <6>[ 2.060261] mmc0: Command Queue Engine enabled
10557 13:38:55.099761 <6>[ 2.065025] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10558 13:38:55.106509 <6>[ 2.072002] cros-ec-spi spi0.0: Chrome EC device registered
10559 13:38:55.109663 <6>[ 2.072459] mmcblk0: mmc0:0001 DA4128 116 GiB
10560 13:38:55.119923 <6>[ 2.087808] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10561 13:38:55.127567 <6>[ 2.095003] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10562 13:38:55.134298 <6>[ 2.100875] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10563 13:38:55.140696 <6>[ 2.106788] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10564 13:38:55.150547 <6>[ 2.112570] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10565 13:38:55.157091 <6>[ 2.123889] NET: Registered PF_PACKET protocol family
10566 13:38:55.160899 <6>[ 2.129288] 9pnet: Installing 9P2000 support
10567 13:38:55.164243 <5>[ 2.133836] Key type dns_resolver registered
10568 13:38:55.171435 <6>[ 2.138824] registered taskstats version 1
10569 13:38:55.174351 <5>[ 2.143216] Loading compiled-in X.509 certificates
10570 13:38:55.206631 <4>[ 2.167280] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 13:38:55.216078 <4>[ 2.177994] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 13:38:55.230127 <6>[ 2.197727] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10573 13:38:55.237206 <6>[ 2.204658] xhci-mtk 11200000.usb: xHCI Host Controller
10574 13:38:55.243595 <6>[ 2.210185] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10575 13:38:55.253931 <6>[ 2.218044] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10576 13:38:55.261039 <6>[ 2.227482] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10577 13:38:55.267755 <6>[ 2.233566] xhci-mtk 11200000.usb: xHCI Host Controller
10578 13:38:55.274424 <6>[ 2.239049] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10579 13:38:55.281154 <6>[ 2.246698] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10580 13:38:55.283970 <6>[ 2.254405] hub 1-0:1.0: USB hub found
10581 13:38:55.290753 <6>[ 2.258445] hub 1-0:1.0: 1 port detected
10582 13:38:55.297249 <6>[ 2.262756] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10583 13:38:55.304211 <6>[ 2.271290] hub 2-0:1.0: USB hub found
10584 13:38:55.307881 <6>[ 2.275310] hub 2-0:1.0: 1 port detected
10585 13:38:55.314351 <6>[ 2.282322] mtk-msdc 11f70000.mmc: Got CD GPIO
10586 13:38:55.328509 <6>[ 2.293186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10587 13:38:55.335367 <6>[ 2.301210] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10588 13:38:55.345373 <4>[ 2.309153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10589 13:38:55.355581 <6>[ 2.318721] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10590 13:38:55.362117 <6>[ 2.326799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10591 13:38:55.368685 <6>[ 2.334790] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10592 13:38:55.378601 <6>[ 2.342720] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10593 13:38:55.385823 <6>[ 2.350544] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10594 13:38:55.395563 <6>[ 2.358362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10595 13:38:55.405304 <6>[ 2.368465] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10596 13:38:55.412105 <6>[ 2.376847] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10597 13:38:55.422205 <6>[ 2.385192] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10598 13:38:55.428586 <6>[ 2.393530] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10599 13:38:55.438619 <6>[ 2.401869] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10600 13:38:55.444914 <6>[ 2.410207] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10601 13:38:55.454986 <6>[ 2.418546] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10602 13:38:55.461575 <6>[ 2.426883] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10603 13:38:55.471602 <6>[ 2.435220] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10604 13:38:55.478243 <6>[ 2.443558] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10605 13:38:55.488052 <6>[ 2.451896] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10606 13:38:55.494629 <6>[ 2.460234] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10607 13:38:55.504900 <6>[ 2.468572] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10608 13:38:55.511389 <6>[ 2.476910] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10609 13:38:55.521453 <6>[ 2.485247] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10610 13:38:55.528280 <6>[ 2.493979] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10611 13:38:55.535073 <6>[ 2.501142] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10612 13:38:55.541232 <6>[ 2.507907] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10613 13:38:55.548078 <6>[ 2.514675] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10614 13:38:55.554490 <6>[ 2.521612] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10615 13:38:55.564855 <6>[ 2.528464] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10616 13:38:55.574913 <6>[ 2.537598] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10617 13:38:55.584342 <6>[ 2.546717] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10618 13:38:55.594465 <6>[ 2.556011] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10619 13:38:55.601146 <6>[ 2.565479] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10620 13:38:55.610701 <6>[ 2.574950] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10621 13:38:55.621075 <6>[ 2.584070] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10622 13:38:55.631035 <6>[ 2.593535] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10623 13:38:55.641091 <6>[ 2.602661] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10624 13:38:55.651205 <6>[ 2.611956] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10625 13:38:55.660911 <6>[ 2.622117] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10626 13:38:55.670566 <6>[ 2.633567] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10627 13:38:55.722422 <6>[ 2.686677] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10628 13:38:55.876992 <6>[ 2.844945] hub 1-1:1.0: USB hub found
10629 13:38:55.880273 <6>[ 2.849459] hub 1-1:1.0: 4 ports detected
10630 13:38:55.890523 <6>[ 2.858119] hub 1-1:1.0: USB hub found
10631 13:38:55.893830 <6>[ 2.862487] hub 1-1:1.0: 4 ports detected
10632 13:38:56.002772 <6>[ 2.967144] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10633 13:38:56.028321 <6>[ 2.996217] hub 2-1:1.0: USB hub found
10634 13:38:56.031475 <6>[ 3.000713] hub 2-1:1.0: 3 ports detected
10635 13:38:56.040778 <6>[ 3.008773] hub 2-1:1.0: USB hub found
10636 13:38:56.044450 <6>[ 3.013258] hub 2-1:1.0: 3 ports detected
10637 13:38:56.218657 <6>[ 3.182832] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10638 13:38:56.350682 <6>[ 3.318382] hub 1-1.4:1.0: USB hub found
10639 13:38:56.353828 <6>[ 3.323027] hub 1-1.4:1.0: 2 ports detected
10640 13:38:56.363046 <6>[ 3.330640] hub 1-1.4:1.0: USB hub found
10641 13:38:56.365998 <6>[ 3.335260] hub 1-1.4:1.0: 2 ports detected
10642 13:38:56.430197 <6>[ 3.394968] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10643 13:38:56.538856 <6>[ 3.503411] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10644 13:38:56.575648 <4>[ 3.539969] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10645 13:38:56.585345 <4>[ 3.549060] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10646 13:38:56.620568 <6>[ 3.588454] r8152 2-1.3:1.0 eth0: v1.12.13
10647 13:38:56.662099 <6>[ 3.626847] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10648 13:38:56.854023 <6>[ 3.818695] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10649 13:38:58.296499 <6>[ 5.264799] r8152 2-1.3:1.0 eth0: carrier on
10650 13:38:58.334931 <5>[ 5.286646] Sending DHCP requests ., OK
10651 13:38:58.341593 <6>[ 5.306910] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10652 13:38:58.344493 <6>[ 5.315196] IP-Config: Complete:
10653 13:38:58.358087 <6>[ 5.318693] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10654 13:38:58.364427 <6>[ 5.329401] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10655 13:38:58.371112 <6>[ 5.338021] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10656 13:38:58.378245 <6>[ 5.338030] nameserver0=192.168.201.1
10657 13:38:58.381289 <6>[ 5.350166] clk: Disabling unused clocks
10658 13:38:58.384171 <6>[ 5.355727] ALSA device list:
10659 13:38:58.391058 <6>[ 5.359030] No soundcards found.
10660 13:38:58.398904 <6>[ 5.366812] Freeing unused kernel memory: 8512K
10661 13:38:58.402434 <6>[ 5.371725] Run /init as init process
10662 13:38:58.433381 Starting syslogd: OK
10663 13:38:58.436571 Starting klogd: OK
10664 13:38:58.445466 Running sysctl: OK
10665 13:38:58.452025 Populating /dev using udev: <30>[ 5.421236] udevd[200]: starting version 3.2.9
10666 13:38:58.460126 <27>[ 5.428133] udevd[200]: specified user 'tss' unknown
10667 13:38:58.466630 <27>[ 5.433502] udevd[200]: specified group 'tss' unknown
10668 13:38:58.473131 <30>[ 5.440253] udevd[201]: starting eudev-3.2.9
10669 13:38:58.490617 <27>[ 5.458491] udevd[201]: specified user 'tss' unknown
10670 13:38:58.497371 <27>[ 5.463898] udevd[201]: specified group 'tss' unknown
10671 13:38:58.620440 <6>[ 5.584638] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 13:38:58.650180 <6>[ 5.618226] remoteproc remoteproc0: scp is available
10673 13:38:58.656633 <6>[ 5.623853] remoteproc remoteproc0: powering up scp
10674 13:38:58.663768 <6>[ 5.629019] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10675 13:38:58.669866 <6>[ 5.637488] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10676 13:38:58.676964 <6>[ 5.638452] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10677 13:38:58.686634 <6>[ 5.650753] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10678 13:38:58.696829 <6>[ 5.659468] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10679 13:38:58.709056 <4>[ 5.673701] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10680 13:38:58.718814 <3>[ 5.683356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 13:38:58.725603 <4>[ 5.684221] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 13:38:58.732528 <6>[ 5.685930] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10683 13:38:58.742392 <3>[ 5.691635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 13:38:58.748920 <3>[ 5.714658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 13:38:58.755757 <6>[ 5.715921] mc: Linux media interface: v0.10
10686 13:38:58.762158 <3>[ 5.723041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 13:38:58.772183 <4>[ 5.733213] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10688 13:38:58.775845 <4>[ 5.733213] Fallback method does not support PEC.
10689 13:38:58.785522 <3>[ 5.749181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 13:38:58.792744 <3>[ 5.757526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 13:38:58.799501 <6>[ 5.764673] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10692 13:38:58.810210 <6>[ 5.764685] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10693 13:38:58.817088 <3>[ 5.765785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 13:38:58.824009 <3>[ 5.766151] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 13:38:58.830501 <6>[ 5.774337] remoteproc remoteproc0: remote processor scp is now up
10696 13:38:58.840047 <3>[ 5.781797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 13:38:58.846823 <3>[ 5.789500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10698 13:38:58.856542 <6>[ 5.796212] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10699 13:38:58.860569 <6>[ 5.796217] pci_bus 0000:00: root bus resource [bus 00-ff]
10700 13:38:58.866639 <6>[ 5.796221] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10701 13:38:58.876850 <6>[ 5.796223] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10702 13:38:58.883729 <6>[ 5.796249] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10703 13:38:58.893402 <6>[ 5.796262] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10704 13:38:58.896566 <6>[ 5.796337] pci 0000:00:00.0: supports D1 D2
10705 13:38:58.903103 <6>[ 5.796338] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10706 13:38:58.910319 <6>[ 5.797358] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10707 13:38:58.916797 <6>[ 5.797548] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10708 13:38:58.926622 <6>[ 5.797574] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10709 13:38:58.933475 <6>[ 5.797590] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10710 13:38:58.939843 <6>[ 5.797605] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10711 13:38:58.943030 <6>[ 5.797720] pci 0000:01:00.0: supports D1 D2
10712 13:38:58.953428 <6>[ 5.797722] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10713 13:38:58.959988 <3>[ 5.798654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 13:38:58.970008 <6>[ 5.807104] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10715 13:38:58.976381 <6>[ 5.812873] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10716 13:38:58.986881 <3>[ 5.812963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 13:38:58.993557 <3>[ 5.812967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 13:38:58.999585 <3>[ 5.812971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 13:38:59.009923 <3>[ 5.813036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 13:38:59.016366 <3>[ 5.813042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 13:38:59.026184 <3>[ 5.813046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 13:38:59.032646 <3>[ 5.813054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 13:38:59.042612 <3>[ 5.813058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 13:38:59.049730 <3>[ 5.813105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 13:38:59.059976 <6>[ 5.822719] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10726 13:38:59.065868 <6>[ 5.822738] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10727 13:38:59.076262 <6>[ 5.828701] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10728 13:38:59.085817 <6>[ 5.836077] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10729 13:38:59.092869 <6>[ 5.841336] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10730 13:38:59.099417 <6>[ 5.841347] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10731 13:38:59.109499 <6>[ 5.841360] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10732 13:38:59.116184 <6>[ 5.841373] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10733 13:38:59.122236 <6>[ 5.841385] pci 0000:00:00.0: PCI bridge to [bus 01]
10734 13:38:59.128979 <6>[ 5.853882] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 13:38:59.139161 <6>[ 5.857643] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10736 13:38:59.142719 <6>[ 5.858044] videodev: Linux video capture interface: v2.00
10737 13:38:59.148908 <6>[ 5.885278] Bluetooth: Core ver 2.22
10738 13:38:59.152734 <6>[ 5.891176] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10739 13:38:59.159372 <6>[ 5.898506] NET: Registered PF_BLUETOOTH protocol family
10740 13:38:59.165582 <6>[ 5.906438] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10741 13:38:59.172388 <6>[ 5.913383] Bluetooth: HCI device and connection manager initialized
10742 13:38:59.178875 <6>[ 5.913396] Bluetooth: HCI socket layer initialized
10743 13:38:59.185486 <6>[ 5.914342] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10744 13:38:59.195690 <6>[ 5.915666] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10745 13:38:59.202335 <6>[ 5.915870] usbcore: registered new interface driver uvcvideo
10746 13:38:59.208787 <6>[ 5.918493] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10747 13:38:59.215529 <6>[ 5.924814] Bluetooth: L2CAP socket layer initialized
10748 13:38:59.222447 <6>[ 5.943933] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10749 13:38:59.225372 <6>[ 5.949830] Bluetooth: SCO socket layer initialized
10750 13:38:59.232090 <5>[ 5.959890] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10751 13:38:59.238624 <6>[ 6.015383] usbcore: registered new interface driver btusb
10752 13:38:59.248937 <4>[ 6.023400] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10753 13:38:59.255234 <5>[ 6.042435] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10754 13:38:59.261817 <3>[ 6.048460] Bluetooth: hci0: Failed to load firmware file (-2)
10755 13:38:59.271992 <5>[ 6.058029] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10756 13:38:59.278676 <3>[ 6.065732] Bluetooth: hci0: Failed to set up firmware (-2)
10757 13:38:59.285042 <4>[ 6.073773] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10758 13:38:59.294706 <4>[ 6.081797] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10759 13:38:59.301835 <6>[ 6.089761] cfg80211: failed to load regulatory.db
10760 13:38:59.308052 <6>[ 6.184087] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10761 13:38:59.314787 <6>[ 6.281826] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10762 13:38:59.339006 <6>[ 6.306734] mt7921e 0000:01:00.0: ASIC revision: 79610010
10763 13:38:59.441528 <6>[ 6.406066] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10764 13:38:59.444194 <6>[ 6.406066]
10765 13:38:59.456419 done
10766 13:38:59.466911 Saving random seed: OK
10767 13:38:59.478520 Starting network: ip: RTNETLINK answers: File exists
10768 13:38:59.481507 FAIL
10769 13:38:59.512498 Starting dropbear sshd: <6>[ 6.480706] NET: Registered PF_INET6 protocol family
10770 13:38:59.519224 <6>[ 6.486890] Segment Routing with IPv6
10771 13:38:59.522994 <6>[ 6.490865] In-situ OAM (IOAM) with IPv6
10772 13:38:59.525717 OK
10773 13:38:59.535138 /bin/sh: can't access tty; job control turned off
10774 13:38:59.535474 Matched prompt #10: / #
10776 13:38:59.535675 Setting prompt string to ['/ #']
10777 13:38:59.535767 end: 2.2.5.1 login-action (duration 00:00:07) [common]
10779 13:38:59.535957 end: 2.2.5 auto-login-action (duration 00:00:07) [common]
10780 13:38:59.536042 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10781 13:38:59.536113 Setting prompt string to ['/ #']
10782 13:38:59.536172 Forcing a shell prompt, looking for ['/ #']
10784 13:38:59.586384 / #
10785 13:38:59.586517 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10786 13:38:59.586608 Waiting using forced prompt support (timeout 00:02:30)
10787 13:38:59.591841
10788 13:38:59.592111 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10789 13:38:59.592206 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10790 13:38:59.592296 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10791 13:38:59.592382 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10792 13:38:59.592469 end: 2 depthcharge-action (duration 00:01:26) [common]
10793 13:38:59.592555 start: 3 lava-test-retry (timeout 00:01:00) [common]
10794 13:38:59.592642 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10795 13:38:59.592716 Using namespace: common
10797 13:38:59.693031 / # #
10798 13:38:59.693190 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10799 13:38:59.698648 #
10800 13:38:59.698905 Using /lava-14063021
10802 13:38:59.799174 / # export SHELL=/bin/sh
10803 13:38:59.799348 <6>[ 6.674808] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10804 13:38:59.805258 export SHELL=/bin/sh
10806 13:38:59.905708 / # . /lava-14063021/environment
10807 13:38:59.911243 . /lava-14063021/environment
10809 13:39:00.011769 / # /lava-14063021/bin/lava-test-runner /lava-14063021/0
10810 13:39:00.011931 Test shell timeout: 10s (minimum of the action and connection timeout)
10811 13:39:00.017038 /lava-14063021/bin/lava-test-runner /lava-14063021/0
10812 13:39:00.036315 + export 'TESTRUN_ID=0_dmesg'
10813 13:39:00.043203 +<8>[ 7.010247] <LAVA_SIGNAL_STARTRUN 0_dmesg 14063021_1.5.2.3.1>
10814 13:39:00.043490 Received signal: <STARTRUN> 0_dmesg 14063021_1.5.2.3.1
10815 13:39:00.043564 Starting test lava.0_dmesg (14063021_1.5.2.3.1)
10816 13:39:00.043663 Skipping test definition patterns.
10817 13:39:00.046879 cd /lava-14063021/0/tests/0_dmesg
10818 13:39:00.046963 + cat uuid
10819 13:39:00.049835 + UUID=14063021_1.5.2.3.1
10820 13:39:00.049920 + set +x
10821 13:39:00.056541 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10822 13:39:00.066847 <8>[ 7.029970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10823 13:39:00.067116 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10825 13:39:00.085620 <8>[ 7.050418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10826 13:39:00.085935 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10828 13:39:00.108954 <8>[ 7.073627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10829 13:39:00.109301 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10831 13:39:00.111896 + set +x
10832 13:39:00.115535 <8>[ 7.083133] <LAVA_SIGNAL_ENDRUN 0_dmesg 14063021_1.5.2.3.1>
10833 13:39:00.115797 Received signal: <ENDRUN> 0_dmesg 14063021_1.5.2.3.1
10834 13:39:00.115882 Ending use of test pattern.
10835 13:39:00.115946 Ending test lava.0_dmesg (14063021_1.5.2.3.1), duration 0.07
10837 13:39:00.119067 <LAVA_TEST_RUNNER EXIT>
10838 13:39:00.119322 ok: lava_test_shell seems to have completed
10839 13:39:00.119429 alert: pass
crit: pass
emerg: pass
10840 13:39:00.119522 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10841 13:39:00.119608 end: 3 lava-test-retry (duration 00:00:01) [common]
10842 13:39:00.119698 start: 4 finalize (timeout 00:08:08) [common]
10843 13:39:00.119786 start: 4.1 power-off (timeout 00:00:30) [common]
10844 13:39:00.119940 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
10845 13:39:00.196786 >> Command sent successfully.
10846 13:39:00.199124 Returned 0 in 0 seconds
10847 13:39:00.299544 end: 4.1 power-off (duration 00:00:00) [common]
10849 13:39:00.299918 start: 4.2 read-feedback (timeout 00:08:08) [common]
10850 13:39:00.300200 Listened to connection for namespace 'common' for up to 1s
10851 13:39:01.301094 Finalising connection for namespace 'common'
10852 13:39:01.301269 Disconnecting from shell: Finalise
10853 13:39:01.301365 / #
10854 13:39:01.401678 end: 4.2 read-feedback (duration 00:00:01) [common]
10855 13:39:01.401883 end: 4 finalize (duration 00:00:01) [common]
10856 13:39:01.402015 Cleaning after the job
10857 13:39:01.402130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/ramdisk
10858 13:39:01.404678 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/kernel
10859 13:39:01.412493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/dtb
10860 13:39:01.412771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063021/tftp-deploy-00ockxyd/modules
10861 13:39:01.418911 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063021
10862 13:39:01.460147 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063021
10863 13:39:01.460336 Job finished correctly