Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:41:05.675792 lava-dispatcher, installed at version: 2024.03
2 13:41:05.676006 start: 0 validate
3 13:41:05.676149 Start time: 2024-05-28 13:41:05.676141+00:00 (UTC)
4 13:41:05.676318 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:41:05.676547 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:41:05.936334 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:41:05.936565 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:41:06.193505 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:41:06.193732 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:41:06.443052 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:41:06.443213 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:41:06.701657 validate duration: 1.03
14 13:41:06.702076 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:41:06.702263 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:41:06.702391 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:41:06.702571 Not decompressing ramdisk as can be used compressed.
18 13:41:06.702675 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 13:41:06.702779 saving as /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/ramdisk/rootfs.cpio.gz
20 13:41:06.702874 total size: 39026414 (37 MB)
21 13:41:06.704516 progress 0 % (0 MB)
22 13:41:06.715645 progress 5 % (1 MB)
23 13:41:06.726802 progress 10 % (3 MB)
24 13:41:06.737381 progress 15 % (5 MB)
25 13:41:06.748268 progress 20 % (7 MB)
26 13:41:06.758857 progress 25 % (9 MB)
27 13:41:06.769584 progress 30 % (11 MB)
28 13:41:06.780681 progress 35 % (13 MB)
29 13:41:06.791419 progress 40 % (14 MB)
30 13:41:06.802478 progress 45 % (16 MB)
31 13:41:06.813398 progress 50 % (18 MB)
32 13:41:06.824209 progress 55 % (20 MB)
33 13:41:06.835517 progress 60 % (22 MB)
34 13:41:06.847782 progress 65 % (24 MB)
35 13:41:06.858191 progress 70 % (26 MB)
36 13:41:06.868791 progress 75 % (27 MB)
37 13:41:06.879081 progress 80 % (29 MB)
38 13:41:06.889603 progress 85 % (31 MB)
39 13:41:06.900087 progress 90 % (33 MB)
40 13:41:06.910403 progress 95 % (35 MB)
41 13:41:06.920413 progress 100 % (37 MB)
42 13:41:06.920675 37 MB downloaded in 0.22 s (170.88 MB/s)
43 13:41:06.920838 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:41:06.921080 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:41:06.921165 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:41:06.921246 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:41:06.921384 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:41:06.921452 saving as /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/kernel/Image
50 13:41:06.921511 total size: 54682112 (52 MB)
51 13:41:06.921577 No compression specified
52 13:41:06.922813 progress 0 % (0 MB)
53 13:41:06.937130 progress 5 % (2 MB)
54 13:41:06.951907 progress 10 % (5 MB)
55 13:41:06.966872 progress 15 % (7 MB)
56 13:41:06.981506 progress 20 % (10 MB)
57 13:41:06.996026 progress 25 % (13 MB)
58 13:41:07.010871 progress 30 % (15 MB)
59 13:41:07.025571 progress 35 % (18 MB)
60 13:41:07.039794 progress 40 % (20 MB)
61 13:41:07.054579 progress 45 % (23 MB)
62 13:41:07.069761 progress 50 % (26 MB)
63 13:41:07.084525 progress 55 % (28 MB)
64 13:41:07.099695 progress 60 % (31 MB)
65 13:41:07.114589 progress 65 % (33 MB)
66 13:41:07.129129 progress 70 % (36 MB)
67 13:41:07.143932 progress 75 % (39 MB)
68 13:41:07.159220 progress 80 % (41 MB)
69 13:41:07.173669 progress 85 % (44 MB)
70 13:41:07.188093 progress 90 % (46 MB)
71 13:41:07.203252 progress 95 % (49 MB)
72 13:41:07.217674 progress 100 % (52 MB)
73 13:41:07.217963 52 MB downloaded in 0.30 s (175.91 MB/s)
74 13:41:07.218211 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:41:07.218452 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:41:07.218541 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:41:07.218625 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:41:07.218758 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:41:07.218828 saving as /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/dtb/mt8192-asurada-spherion-r0.dtb
81 13:41:07.218888 total size: 47258 (0 MB)
82 13:41:07.218948 No compression specified
83 13:41:07.220037 progress 69 % (0 MB)
84 13:41:07.220307 progress 100 % (0 MB)
85 13:41:07.220464 0 MB downloaded in 0.00 s (28.64 MB/s)
86 13:41:07.220588 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:41:07.220807 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:41:07.220896 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:41:07.220977 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:41:07.221086 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:41:07.221160 saving as /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/modules/modules.tar
93 13:41:07.221250 total size: 8607916 (8 MB)
94 13:41:07.221338 Using unxz to decompress xz
95 13:41:07.225475 progress 0 % (0 MB)
96 13:41:07.245411 progress 5 % (0 MB)
97 13:41:07.272411 progress 10 % (0 MB)
98 13:41:07.298267 progress 15 % (1 MB)
99 13:41:07.323518 progress 20 % (1 MB)
100 13:41:07.349605 progress 25 % (2 MB)
101 13:41:07.374745 progress 30 % (2 MB)
102 13:41:07.398476 progress 35 % (2 MB)
103 13:41:07.425093 progress 40 % (3 MB)
104 13:41:07.450313 progress 45 % (3 MB)
105 13:41:07.475965 progress 50 % (4 MB)
106 13:41:07.501907 progress 55 % (4 MB)
107 13:41:07.527435 progress 60 % (4 MB)
108 13:41:07.551633 progress 65 % (5 MB)
109 13:41:07.578673 progress 70 % (5 MB)
110 13:41:07.606843 progress 75 % (6 MB)
111 13:41:07.630672 progress 80 % (6 MB)
112 13:41:07.654580 progress 85 % (7 MB)
113 13:41:07.678557 progress 90 % (7 MB)
114 13:41:07.708126 progress 95 % (7 MB)
115 13:41:07.736750 progress 100 % (8 MB)
116 13:41:07.742492 8 MB downloaded in 0.52 s (15.75 MB/s)
117 13:41:07.742791 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:41:07.743126 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:41:07.743239 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:41:07.743341 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:41:07.743431 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:41:07.743525 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:41:07.743804 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr
125 13:41:07.743943 makedir: /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin
126 13:41:07.744050 makedir: /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/tests
127 13:41:07.744153 makedir: /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/results
128 13:41:07.744272 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-add-keys
129 13:41:07.744427 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-add-sources
130 13:41:07.744563 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-background-process-start
131 13:41:07.744703 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-background-process-stop
132 13:41:07.744832 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-common-functions
133 13:41:07.744968 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-echo-ipv4
134 13:41:07.745100 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-install-packages
135 13:41:07.745256 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-installed-packages
136 13:41:07.745420 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-os-build
137 13:41:07.745578 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-probe-channel
138 13:41:07.745740 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-probe-ip
139 13:41:07.745901 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-target-ip
140 13:41:07.746060 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-target-mac
141 13:41:07.746224 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-target-storage
142 13:41:07.746357 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-case
143 13:41:07.746487 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-event
144 13:41:07.746615 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-feedback
145 13:41:07.746740 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-raise
146 13:41:07.746864 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-reference
147 13:41:07.746993 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-runner
148 13:41:07.747120 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-set
149 13:41:07.747305 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-test-shell
150 13:41:07.747453 Updating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-install-packages (oe)
151 13:41:07.747610 Updating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/bin/lava-installed-packages (oe)
152 13:41:07.747743 Creating /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/environment
153 13:41:07.747856 LAVA metadata
154 13:41:07.747934 - LAVA_JOB_ID=14063115
155 13:41:07.748000 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:41:07.748111 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:41:07.748182 skipped lava-vland-overlay
158 13:41:07.748257 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:41:07.748342 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:41:07.748410 skipped lava-multinode-overlay
161 13:41:07.748484 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:41:07.748579 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:41:07.748659 Loading test definitions
164 13:41:07.748750 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:41:07.748824 Using /lava-14063115 at stage 0
166 13:41:07.749142 uuid=14063115_1.5.2.3.1 testdef=None
167 13:41:07.749233 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:41:07.749324 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:41:07.750046 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:41:07.750383 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:41:07.751017 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:41:07.751257 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:41:07.751868 runner path: /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/0/tests/0_cros-ec test_uuid 14063115_1.5.2.3.1
176 13:41:07.752030 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:41:07.752377 Creating lava-test-runner.conf files
179 13:41:07.752471 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063115/lava-overlay-ef9uxrnr/lava-14063115/0 for stage 0
180 13:41:07.752595 - 0_cros-ec
181 13:41:07.752724 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:41:07.752848 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:41:07.760648 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:41:07.760765 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:41:07.760853 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:41:07.760939 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:41:07.761030 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:41:09.005169 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:41:09.005580 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:41:09.005731 extracting modules file /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063115/extract-overlay-ramdisk-3_qb01u9/ramdisk
191 13:41:09.281014 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:41:09.281189 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 13:41:09.281315 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063115/compress-overlay-3bjcfb4x/overlay-1.5.2.4.tar.gz to ramdisk
194 13:41:09.281426 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063115/compress-overlay-3bjcfb4x/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063115/extract-overlay-ramdisk-3_qb01u9/ramdisk
195 13:41:09.290085 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:41:09.290251 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 13:41:09.290351 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:41:09.290451 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 13:41:09.290538 Building ramdisk /var/lib/lava/dispatcher/tmp/14063115/extract-overlay-ramdisk-3_qb01u9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063115/extract-overlay-ramdisk-3_qb01u9/ramdisk
200 13:41:10.246559 >> 335872 blocks
201 13:41:15.561385 rename /var/lib/lava/dispatcher/tmp/14063115/extract-overlay-ramdisk-3_qb01u9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/ramdisk/ramdisk.cpio.gz
202 13:41:15.561930 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 13:41:15.562107 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 13:41:15.562262 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 13:41:15.562414 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/kernel/Image']
206 13:41:29.432926 Returned 0 in 13 seconds
207 13:41:29.533578 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/kernel/image.itb
208 13:41:30.268521 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:41:30.268922 output: Created: Tue May 28 14:41:30 2024
210 13:41:30.269032 output: Image 0 (kernel-1)
211 13:41:30.269139 output: Description:
212 13:41:30.269243 output: Created: Tue May 28 14:41:30 2024
213 13:41:30.269348 output: Type: Kernel Image
214 13:41:30.269454 output: Compression: lzma compressed
215 13:41:30.269557 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:41:30.269662 output: Architecture: AArch64
217 13:41:30.269772 output: OS: Linux
218 13:41:30.269876 output: Load Address: 0x00000000
219 13:41:30.269978 output: Entry Point: 0x00000000
220 13:41:30.270078 output: Hash algo: crc32
221 13:41:30.270191 output: Hash value: 0578ee26
222 13:41:30.270298 output: Image 1 (fdt-1)
223 13:41:30.270395 output: Description: mt8192-asurada-spherion-r0
224 13:41:30.270498 output: Created: Tue May 28 14:41:30 2024
225 13:41:30.270595 output: Type: Flat Device Tree
226 13:41:30.270695 output: Compression: uncompressed
227 13:41:30.270793 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:41:30.270896 output: Architecture: AArch64
229 13:41:30.270985 output: Hash algo: crc32
230 13:41:30.271062 output: Hash value: 0f8e4d2e
231 13:41:30.271138 output: Image 2 (ramdisk-1)
232 13:41:30.271237 output: Description: unavailable
233 13:41:30.271338 output: Created: Tue May 28 14:41:30 2024
234 13:41:30.271428 output: Type: RAMDisk Image
235 13:41:30.271517 output: Compression: Unknown Compression
236 13:41:30.271613 output: Data Size: 52130606 Bytes = 50908.79 KiB = 49.72 MiB
237 13:41:30.271708 output: Architecture: AArch64
238 13:41:30.271808 output: OS: Linux
239 13:41:30.271905 output: Load Address: unavailable
240 13:41:30.272003 output: Entry Point: unavailable
241 13:41:30.272104 output: Hash algo: crc32
242 13:41:30.272204 output: Hash value: 4aa76d7e
243 13:41:30.272309 output: Default Configuration: 'conf-1'
244 13:41:30.272405 output: Configuration 0 (conf-1)
245 13:41:30.272500 output: Description: mt8192-asurada-spherion-r0
246 13:41:30.272597 output: Kernel: kernel-1
247 13:41:30.272695 output: Init Ramdisk: ramdisk-1
248 13:41:30.272791 output: FDT: fdt-1
249 13:41:30.272890 output: Loadables: kernel-1
250 13:41:30.272991 output:
251 13:41:30.273266 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:41:30.273404 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:41:30.273559 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 13:41:30.273706 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 13:41:30.273830 No LXC device requested
256 13:41:30.273960 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:41:30.274097 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 13:41:30.274223 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:41:30.274312 Checking files for TFTP limit of 4294967296 bytes.
260 13:41:30.275040 end: 1 tftp-deploy (duration 00:00:24) [common]
261 13:41:30.275186 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:41:30.275334 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:41:30.275516 substitutions:
264 13:41:30.275622 - {DTB}: 14063115/tftp-deploy-pc8phom8/dtb/mt8192-asurada-spherion-r0.dtb
265 13:41:30.275733 - {INITRD}: 14063115/tftp-deploy-pc8phom8/ramdisk/ramdisk.cpio.gz
266 13:41:30.275842 - {KERNEL}: 14063115/tftp-deploy-pc8phom8/kernel/Image
267 13:41:30.275949 - {LAVA_MAC}: None
268 13:41:30.276056 - {PRESEED_CONFIG}: None
269 13:41:30.276146 - {PRESEED_LOCAL}: None
270 13:41:30.276247 - {RAMDISK}: 14063115/tftp-deploy-pc8phom8/ramdisk/ramdisk.cpio.gz
271 13:41:30.276347 - {ROOT_PART}: None
272 13:41:30.276446 - {ROOT}: None
273 13:41:30.276548 - {SERVER_IP}: 192.168.201.1
274 13:41:30.276649 - {TEE}: None
275 13:41:30.276747 Parsed boot commands:
276 13:41:30.276844 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:41:30.277084 Parsed boot commands: tftpboot 192.168.201.1 14063115/tftp-deploy-pc8phom8/kernel/image.itb 14063115/tftp-deploy-pc8phom8/kernel/cmdline
278 13:41:30.277214 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:41:30.277347 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:41:30.277490 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:41:30.277624 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:41:30.277734 Not connected, no need to disconnect.
283 13:41:30.277856 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:41:30.277982 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:41:30.278094 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 13:41:30.282018 Setting prompt string to ['lava-test: # ']
287 13:41:30.282473 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:41:30.282624 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:41:30.282763 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:41:30.282902 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:41:30.283151 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 13:41:44.771100 Returned 0 in 14 seconds
293 13:41:44.871737 end: 2.2.2.1 pdu-reboot (duration 00:00:15) [common]
295 13:41:44.872394 end: 2.2.2 reset-device (duration 00:00:15) [common]
296 13:41:44.872503 start: 2.2.3 depthcharge-start (timeout 00:04:45) [common]
297 13:41:44.872608 Setting prompt string to 'Starting depthcharge on Spherion...'
298 13:41:44.872675 Changing prompt to 'Starting depthcharge on Spherion...'
299 13:41:44.872741 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 13:41:44.873159 [Enter `^Ec?' for help]
301 13:41:44.873239
302 13:41:44.873303
303 13:41:44.873365 F0: 102B 0000
304 13:41:44.873425
305 13:41:44.873483 F3: 1001 0000 [0200]
306 13:41:44.873543
307 13:41:44.873603 F3: 1001 0000
308 13:41:44.873685
309 13:41:44.873755 F7: 102D 0000
310 13:41:44.873810
311 13:41:44.873864 F1: 0000 0000
312 13:41:44.873917
313 13:41:44.873970 V0: 0000 0000 [0001]
314 13:41:44.874023
315 13:41:44.874075 00: 0007 8000
316 13:41:44.874132
317 13:41:44.874228 01: 0000 0000
318 13:41:44.874284
319 13:41:44.874337 BP: 0C00 0209 [0000]
320 13:41:44.874390
321 13:41:44.874442 G0: 1182 0000
322 13:41:44.874494
323 13:41:44.874546 EC: 0000 0021 [4000]
324 13:41:44.874598
325 13:41:44.874651 S7: 0000 0000 [0000]
326 13:41:44.874702
327 13:41:44.874754 CC: 0000 0000 [0001]
328 13:41:44.874806
329 13:41:44.874877 T0: 0000 0040 [010F]
330 13:41:44.874931
331 13:41:44.874984 Jump to BL
332 13:41:44.875037
333 13:41:44.875102
334 13:41:44.875158
335 13:41:44.875211 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 13:41:44.875267 ARM64: Exception handlers installed.
337 13:41:44.875321 ARM64: Testing exception
338 13:41:44.875392 ARM64: Done test exception
339 13:41:44.875448 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 13:41:44.875503 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 13:41:44.875557 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 13:41:44.875616 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 13:41:44.875680 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 13:41:44.875733 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 13:41:44.875801 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 13:41:44.875885 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 13:41:44.875972 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 13:41:44.876070 WDT: Last reset was cold boot
349 13:41:44.876176 SPI1(PAD0) initialized at 2873684 Hz
350 13:41:44.876261 SPI5(PAD0) initialized at 992727 Hz
351 13:41:44.876346 VBOOT: Loading verstage.
352 13:41:44.876436 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 13:41:44.876520 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 13:41:44.876612 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 13:41:44.876697 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 13:41:44.876800 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 13:41:44.876895 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 13:41:44.876981 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 13:41:44.877086
360 13:41:44.877171
361 13:41:44.877255 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 13:41:44.877348 ARM64: Exception handlers installed.
363 13:41:44.877432 ARM64: Testing exception
364 13:41:44.877514 ARM64: Done test exception
365 13:41:44.877620 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 13:41:44.877678 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 13:41:44.877732 Probing TPM: . done!
368 13:41:44.877785 TPM ready after 0 ms
369 13:41:44.877842 Connected to device vid:did:rid of 1ae0:0028:00
370 13:41:44.877906 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 13:41:44.877961 Initialized TPM device CR50 revision 0
372 13:41:44.878014 tlcl_send_startup: Startup return code is 0
373 13:41:44.878067 TPM: setup succeeded
374 13:41:44.878158 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 13:41:44.878254 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 13:41:44.878308 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 13:41:44.878374 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:41:44.878429 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 13:41:44.878482 in-header: 03 07 00 00 08 00 00 00
380 13:41:44.878535 in-data: aa e4 47 04 13 02 00 00
381 13:41:44.878591 Chrome EC: UHEPI supported
382 13:41:44.878662 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 13:41:44.878717 in-header: 03 a9 00 00 08 00 00 00
384 13:41:44.878803 in-data: 84 60 60 08 00 00 00 00
385 13:41:44.878894 Phase 1
386 13:41:44.878957 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 13:41:44.879011 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 13:41:44.879064 VB2:vb2_check_recovery() Recovery was requested manually
389 13:41:44.879119 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 13:41:44.879236 Recovery requested (1009000e)
391 13:41:44.879304 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:41:44.879361 tlcl_extend: response is 0
393 13:41:44.879431 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:41:44.879485 tlcl_extend: response is 0
395 13:41:44.879537 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:41:44.879591 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 13:41:44.879656 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 13:41:44.879712
399 13:41:44.879765
400 13:41:44.879817 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:41:44.879871 ARM64: Exception handlers installed.
402 13:41:44.879940 ARM64: Testing exception
403 13:41:44.879994 ARM64: Done test exception
404 13:41:44.880047 pmic_efuse_setting: Set efuses in 11 msecs
405 13:41:44.880099 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:41:44.880166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:41:44.880222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:41:44.880470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:41:44.880534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:41:44.880589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:41:44.880689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:41:44.880745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:41:44.880812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:41:44.880897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:41:44.880952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:41:44.881005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:41:44.881073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:41:44.881156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:41:44.881211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:41:44.881265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:41:44.881326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:41:44.881385 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:41:44.881438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:41:44.881491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:41:44.881543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:41:44.881612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:41:44.881668 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:41:44.881720 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:41:44.881794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:41:44.881878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:41:44.881933 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:41:44.881986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:41:44.882039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:41:44.882092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:41:44.882220 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:41:44.882306 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:41:44.882396 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:41:44.882483 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:41:44.882566 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:41:44.882687 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:41:44.882749 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:41:44.882809 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:41:44.882866 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:41:44.882923 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:41:44.882987 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:41:44.883043 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:41:44.883130 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:41:44.883218 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:41:44.883306 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:41:44.883390 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:41:44.883482 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:41:44.883566 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:41:44.883649 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:41:44.883728 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:41:44.883782 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:41:44.883835 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:41:44.883888 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 13:41:44.883954 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:41:44.884010 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:41:44.884063 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:41:44.884117 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:41:44.884178 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:41:44.884237 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:41:44.884289 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:41:44.884342 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1b
466 13:41:44.884394 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 13:41:44.884482 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 13:41:44.884567 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:41:44.884620 [RTC]rtc_get_frequency_meter,154: input=15, output=834
470 13:41:44.884674 [RTC]rtc_get_frequency_meter,154: input=7, output=709
471 13:41:44.884744 [RTC]rtc_get_frequency_meter,154: input=11, output=772
472 13:41:44.884800 [RTC]rtc_get_frequency_meter,154: input=13, output=803
473 13:41:44.884866 [RTC]rtc_get_frequency_meter,154: input=12, output=788
474 13:41:44.884918 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 13:41:44.884987 [RTC]rtc_get_frequency_meter,154: input=13, output=803
476 13:41:44.885042 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 13:41:44.885095 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 13:41:44.885333 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 13:41:44.885411 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 13:41:44.885494 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 13:41:44.885580 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 13:41:44.885664 ADC[4]: Raw value=904509 ID=7
483 13:41:44.885756 ADC[3]: Raw value=214021 ID=1
484 13:41:44.885840 RAM Code: 0x71
485 13:41:44.885924 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 13:41:44.886017 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 13:41:44.886103 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 13:41:44.886227 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 13:41:44.886295 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 13:41:44.886351 in-header: 03 07 00 00 08 00 00 00
491 13:41:44.886403 in-data: aa e4 47 04 13 02 00 00
492 13:41:44.886456 Chrome EC: UHEPI supported
493 13:41:44.886572 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 13:41:44.886641 in-header: 03 a9 00 00 08 00 00 00
495 13:41:44.886695 in-data: 84 60 60 08 00 00 00 00
496 13:41:44.886747 MRC: failed to locate region type 0.
497 13:41:44.886817 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 13:41:44.886872 DRAM-K: Running full calibration
499 13:41:44.886924 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 13:41:44.886979 header.status = 0x0
501 13:41:44.887031 header.version = 0x6 (expected: 0x6)
502 13:41:44.887100 header.size = 0xd00 (expected: 0xd00)
503 13:41:44.887155 header.flags = 0x0
504 13:41:44.887208 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 13:41:44.887261 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
506 13:41:44.887314 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 13:41:44.887380 dram_init: ddr_geometry: 2
508 13:41:44.887433 [EMI] MDL number = 2
509 13:41:44.887485 [EMI] Get MDL freq = 0
510 13:41:44.887538 dram_init: ddr_type: 0
511 13:41:44.887608 is_discrete_lpddr4: 1
512 13:41:44.887662 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 13:41:44.887715
514 13:41:44.887768
515 13:41:44.887836 [Bian_co] ETT version 0.0.0.1
516 13:41:44.887892 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 13:41:44.887945
518 13:41:44.887997 dramc_set_vcore_voltage set vcore to 650000
519 13:41:44.888068 Read voltage for 800, 4
520 13:41:44.888122 Vio18 = 0
521 13:41:44.888175 Vcore = 650000
522 13:41:44.888226 Vdram = 0
523 13:41:44.888293 Vddq = 0
524 13:41:44.888378 Vmddr = 0
525 13:41:44.888460 dram_init: config_dvfs: 1
526 13:41:44.888590 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 13:41:44.888692 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 13:41:44.888826 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
529 13:41:44.888911 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
530 13:41:44.888998 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 13:41:44.889079 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 13:41:44.889134 MEM_TYPE=3, freq_sel=18
533 13:41:44.889188 sv_algorithm_assistance_LP4_1600
534 13:41:44.889241 ============ PULL DRAM RESETB DOWN ============
535 13:41:44.889307 ========== PULL DRAM RESETB DOWN end =========
536 13:41:44.889367 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 13:41:44.889424 ===================================
538 13:41:44.889480 LPDDR4 DRAM CONFIGURATION
539 13:41:44.889551 ===================================
540 13:41:44.889636 EX_ROW_EN[0] = 0x0
541 13:41:44.889718 EX_ROW_EN[1] = 0x0
542 13:41:44.889808 LP4Y_EN = 0x0
543 13:41:44.889892 WORK_FSP = 0x0
544 13:41:44.889974 WL = 0x2
545 13:41:44.890064 RL = 0x2
546 13:41:44.890147 BL = 0x2
547 13:41:44.890250 RPST = 0x0
548 13:41:44.890321 RD_PRE = 0x0
549 13:41:44.890375 WR_PRE = 0x1
550 13:41:44.890428 WR_PST = 0x0
551 13:41:44.890480 DBI_WR = 0x0
552 13:41:44.890545 DBI_RD = 0x0
553 13:41:44.890599 OTF = 0x1
554 13:41:44.890653 ===================================
555 13:41:44.890705 ===================================
556 13:41:44.890757 ANA top config
557 13:41:44.890823 ===================================
558 13:41:44.890877 DLL_ASYNC_EN = 0
559 13:41:44.890929 ALL_SLAVE_EN = 1
560 13:41:44.890981 NEW_RANK_MODE = 1
561 13:41:44.891050 DLL_IDLE_MODE = 1
562 13:41:44.891104 LP45_APHY_COMB_EN = 1
563 13:41:44.891156 TX_ODT_DIS = 1
564 13:41:44.891209 NEW_8X_MODE = 1
565 13:41:44.891274 ===================================
566 13:41:44.891329 ===================================
567 13:41:44.891382 data_rate = 1600
568 13:41:44.891434 CKR = 1
569 13:41:44.891486 DQ_P2S_RATIO = 8
570 13:41:44.891555 ===================================
571 13:41:44.891609 CA_P2S_RATIO = 8
572 13:41:44.891661 DQ_CA_OPEN = 0
573 13:41:44.891713 DQ_SEMI_OPEN = 0
574 13:41:44.891813 CA_SEMI_OPEN = 0
575 13:41:44.891866 CA_FULL_RATE = 0
576 13:41:44.891919 DQ_CKDIV4_EN = 1
577 13:41:44.891971 CA_CKDIV4_EN = 1
578 13:41:44.892040 CA_PREDIV_EN = 0
579 13:41:44.892094 PH8_DLY = 0
580 13:41:44.892148 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 13:41:44.892200 DQ_AAMCK_DIV = 4
582 13:41:44.892263 CA_AAMCK_DIV = 4
583 13:41:44.892349 CA_ADMCK_DIV = 4
584 13:41:44.892432 DQ_TRACK_CA_EN = 0
585 13:41:44.892522 CA_PICK = 800
586 13:41:44.892606 CA_MCKIO = 800
587 13:41:44.892689 MCKIO_SEMI = 0
588 13:41:44.892779 PLL_FREQ = 3068
589 13:41:44.892863 DQ_UI_PI_RATIO = 32
590 13:41:44.892946 CA_UI_PI_RATIO = 0
591 13:41:44.893036 ===================================
592 13:41:44.893151 ===================================
593 13:41:44.893236 memory_type:LPDDR4
594 13:41:44.893311 GP_NUM : 10
595 13:41:44.893369 SRAM_EN : 1
596 13:41:44.893425 MD32_EN : 0
597 13:41:44.893696 ===================================
598 13:41:44.893798 [ANA_INIT] >>>>>>>>>>>>>>
599 13:41:44.893888 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 13:41:44.893986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 13:41:44.894079 ===================================
602 13:41:44.894178 data_rate = 1600,PCW = 0X7600
603 13:41:44.894309 ===================================
604 13:41:44.894422 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 13:41:44.894516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 13:41:44.894630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:41:44.894760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 13:41:44.894820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 13:41:44.894875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:41:44.894931 [ANA_INIT] flow start
611 13:41:44.895000 [ANA_INIT] PLL >>>>>>>>
612 13:41:44.895055 [ANA_INIT] PLL <<<<<<<<
613 13:41:44.895109 [ANA_INIT] MIDPI >>>>>>>>
614 13:41:44.895165 [ANA_INIT] MIDPI <<<<<<<<
615 13:41:44.895237 [ANA_INIT] DLL >>>>>>>>
616 13:41:44.895291 [ANA_INIT] flow end
617 13:41:44.895380 ============ LP4 DIFF to SE enter ============
618 13:41:44.895461 ============ LP4 DIFF to SE exit ============
619 13:41:44.895518 [ANA_INIT] <<<<<<<<<<<<<
620 13:41:44.895575 [Flow] Enable top DCM control >>>>>
621 13:41:44.895673 [Flow] Enable top DCM control <<<<<
622 13:41:44.895780 Enable DLL master slave shuffle
623 13:41:44.895883 ==============================================================
624 13:41:44.895990 Gating Mode config
625 13:41:44.896075 ==============================================================
626 13:41:44.896182 Config description:
627 13:41:44.896274 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 13:41:44.896364 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 13:41:44.896456 SELPH_MODE 0: By rank 1: By Phase
630 13:41:44.896543 ==============================================================
631 13:41:44.896625 GAT_TRACK_EN = 1
632 13:41:44.896721 RX_GATING_MODE = 2
633 13:41:44.896841 RX_GATING_TRACK_MODE = 2
634 13:41:44.896942 SELPH_MODE = 1
635 13:41:44.897044 PICG_EARLY_EN = 1
636 13:41:44.897129 VALID_LAT_VALUE = 1
637 13:41:44.897218 ==============================================================
638 13:41:44.897319 Enter into Gating configuration >>>>
639 13:41:44.897402 Exit from Gating configuration <<<<
640 13:41:44.897520 Enter into DVFS_PRE_config >>>>>
641 13:41:44.897606 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 13:41:44.897710 Exit from DVFS_PRE_config <<<<<
643 13:41:44.897810 Enter into PICG configuration >>>>
644 13:41:44.897913 Exit from PICG configuration <<<<
645 13:41:44.898026 [RX_INPUT] configuration >>>>>
646 13:41:44.898111 [RX_INPUT] configuration <<<<<
647 13:41:44.898211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 13:41:44.898288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 13:41:44.898350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:41:44.898406 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:41:44.898460 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 13:41:44.898545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 13:41:44.898600 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 13:41:44.898691 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 13:41:44.898761 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 13:41:44.898834 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 13:41:44.898895 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 13:41:44.898959 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 13:41:44.899060 ===================================
660 13:41:44.899193 LPDDR4 DRAM CONFIGURATION
661 13:41:44.899304 ===================================
662 13:41:44.899389 EX_ROW_EN[0] = 0x0
663 13:41:44.899475 EX_ROW_EN[1] = 0x0
664 13:41:44.899575 LP4Y_EN = 0x0
665 13:41:44.899672 WORK_FSP = 0x0
666 13:41:44.899757 WL = 0x2
667 13:41:44.899841 RL = 0x2
668 13:41:44.899924 BL = 0x2
669 13:41:44.900010 RPST = 0x0
670 13:41:44.900095 RD_PRE = 0x0
671 13:41:44.900181 WR_PRE = 0x1
672 13:41:44.900275 WR_PST = 0x0
673 13:41:44.900363 DBI_WR = 0x0
674 13:41:44.900447 DBI_RD = 0x0
675 13:41:44.900531 OTF = 0x1
676 13:41:44.900651 ===================================
677 13:41:44.900741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 13:41:44.900855 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 13:41:44.900945 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 13:41:44.901032 ===================================
681 13:41:44.901121 LPDDR4 DRAM CONFIGURATION
682 13:41:44.901210 ===================================
683 13:41:44.901305 EX_ROW_EN[0] = 0x10
684 13:41:44.901391 EX_ROW_EN[1] = 0x0
685 13:41:44.901479 LP4Y_EN = 0x0
686 13:41:44.901573 WORK_FSP = 0x0
687 13:41:44.901661 WL = 0x2
688 13:41:44.901786 RL = 0x2
689 13:41:44.901885 BL = 0x2
690 13:41:44.901970 RPST = 0x0
691 13:41:44.902055 RD_PRE = 0x0
692 13:41:44.902138 WR_PRE = 0x1
693 13:41:44.902230 WR_PST = 0x0
694 13:41:44.902316 DBI_WR = 0x0
695 13:41:44.902402 DBI_RD = 0x0
696 13:41:44.902486 OTF = 0x1
697 13:41:44.902571 ===================================
698 13:41:44.902657 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 13:41:44.902741 nWR fixed to 40
700 13:41:44.902827 [ModeRegInit_LP4] CH0 RK0
701 13:41:44.902914 [ModeRegInit_LP4] CH0 RK1
702 13:41:44.903041 [ModeRegInit_LP4] CH1 RK0
703 13:41:44.903146 [ModeRegInit_LP4] CH1 RK1
704 13:41:44.903247 match AC timing 13
705 13:41:44.903364 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 13:41:44.903656 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 13:41:44.903757 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 13:41:44.903846 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 13:41:44.903934 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 13:41:44.904028 [EMI DOE] emi_dcm 0
711 13:41:44.904114 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 13:41:44.904198 ==
713 13:41:44.904300 Dram Type= 6, Freq= 0, CH_0, rank 0
714 13:41:44.904389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 13:41:44.904474 ==
716 13:41:44.904566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 13:41:44.904654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 13:41:44.904739 [CA 0] Center 37 (6~68) winsize 63
719 13:41:44.904825 [CA 1] Center 37 (7~68) winsize 62
720 13:41:44.904912 [CA 2] Center 34 (4~65) winsize 62
721 13:41:44.904999 [CA 3] Center 34 (4~65) winsize 62
722 13:41:44.905084 [CA 4] Center 33 (3~64) winsize 62
723 13:41:44.905168 [CA 5] Center 33 (3~64) winsize 62
724 13:41:44.905252
725 13:41:44.905333 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 13:41:44.905404
727 13:41:44.905458 [CATrainingPosCal] consider 1 rank data
728 13:41:44.905563 u2DelayCellTimex100 = 270/100 ps
729 13:41:44.905651 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
730 13:41:44.905741 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 13:41:44.905828 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 13:41:44.905915 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:41:44.906001 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 13:41:44.906087 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:41:44.906182
736 13:41:44.906272 CA PerBit enable=1, Macro0, CA PI delay=33
737 13:41:44.906354
738 13:41:44.906427 [CBTSetCACLKResult] CA Dly = 33
739 13:41:44.906481 CS Dly: 6 (0~37)
740 13:41:44.906535 ==
741 13:41:44.906588 Dram Type= 6, Freq= 0, CH_0, rank 1
742 13:41:44.906676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 13:41:44.906762 ==
744 13:41:44.906846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 13:41:44.906917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 13:41:44.907005 [CA 0] Center 37 (6~68) winsize 63
747 13:41:44.907060 [CA 1] Center 37 (7~68) winsize 62
748 13:41:44.907127 [CA 2] Center 34 (4~65) winsize 62
749 13:41:44.907199 [CA 3] Center 34 (4~65) winsize 62
750 13:41:44.907309 [CA 4] Center 33 (3~64) winsize 62
751 13:41:44.907398 [CA 5] Center 33 (3~64) winsize 62
752 13:41:44.907490
753 13:41:44.907580 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 13:41:44.907676
755 13:41:44.907763 [CATrainingPosCal] consider 2 rank data
756 13:41:44.907898 u2DelayCellTimex100 = 270/100 ps
757 13:41:44.908001 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
758 13:41:44.908088 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:41:44.908187 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 13:41:44.908276 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:41:44.908361 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 13:41:44.908450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:41:44.908536
764 13:41:44.908664 CA PerBit enable=1, Macro0, CA PI delay=33
765 13:41:44.908765
766 13:41:44.908863 [CBTSetCACLKResult] CA Dly = 33
767 13:41:44.908956 CS Dly: 6 (0~38)
768 13:41:44.909051
769 13:41:44.909139 ----->DramcWriteLeveling(PI) begin...
770 13:41:44.909247 ==
771 13:41:44.909337 Dram Type= 6, Freq= 0, CH_0, rank 0
772 13:41:44.909422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 13:41:44.909539 ==
774 13:41:44.909672 Write leveling (Byte 0): 31 => 31
775 13:41:44.909765 Write leveling (Byte 1): 31 => 31
776 13:41:44.909856 DramcWriteLeveling(PI) end<-----
777 13:41:44.909942
778 13:41:44.910029 ==
779 13:41:44.910134 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:41:44.910282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:41:44.910399 ==
782 13:41:44.910483 [Gating] SW mode calibration
783 13:41:44.910587 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 13:41:44.910674 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 13:41:44.910760 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 13:41:44.910848 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:41:44.910949 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
788 13:41:44.911032 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 13:41:44.911144 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:41:44.911228 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:41:44.911281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:41:44.911334 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:41:44.911418 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:41:44.911506 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:41:44.911609 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:41:44.911693 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:41:44.911794 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:41:44.911916 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:41:44.912013 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:41:44.912152 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:41:44.912290 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:41:44.912378 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:41:44.912480 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 13:41:44.912566 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:41:44.912652 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:41:44.912737 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:41:44.912833 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:41:44.912929 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:41:44.913018 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:41:44.913104 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:41:44.913190 0 9 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
812 13:41:44.913287 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
813 13:41:44.913371 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:41:44.913743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:41:44.913885 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:41:44.913976 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:41:44.914067 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:41:44.914155 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
819 13:41:44.914242 0 10 8 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 0)
820 13:41:44.914323 0 10 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
821 13:41:44.914411 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:41:44.914493 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:41:44.914618 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:41:44.914711 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:41:44.914806 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:41:44.914892 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:41:44.914988 0 11 8 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (0 0)
828 13:41:44.915098 0 11 12 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
829 13:41:44.915185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:41:44.915285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:41:44.915423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:41:44.915508 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:41:44.915645 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:41:44.915769 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 13:41:44.915856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:41:44.915942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 13:41:44.916042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:41:44.916130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:41:44.916216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:41:44.916302 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:41:44.916402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:41:44.916490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:41:44.916576 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:41:44.916663 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:41:44.916735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:41:44.916820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:41:44.916925 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:41:44.916997 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:41:44.917077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:41:44.917166 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:41:44.917261 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 13:41:44.917348 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:41:44.917440 Total UI for P1: 0, mck2ui 16
854 13:41:44.917528 best dqsien dly found for B0: ( 0, 14, 8)
855 13:41:44.917652 Total UI for P1: 0, mck2ui 16
856 13:41:44.917781 best dqsien dly found for B1: ( 0, 14, 10)
857 13:41:44.917875 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 13:41:44.917972 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 13:41:44.918058
860 13:41:44.918145 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 13:41:44.918254 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 13:41:44.918338 [Gating] SW calibration Done
863 13:41:44.918421 ==
864 13:41:44.918505 Dram Type= 6, Freq= 0, CH_0, rank 0
865 13:41:44.918575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 13:41:44.918636 ==
867 13:41:44.918748 RX Vref Scan: 0
868 13:41:44.918848
869 13:41:44.918906 RX Vref 0 -> 0, step: 1
870 13:41:44.918975
871 13:41:44.919071 RX Delay -130 -> 252, step: 16
872 13:41:44.919126 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 13:41:44.919180 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 13:41:44.919245 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 13:41:44.919299 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 13:41:44.919353 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 13:41:44.919475 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 13:41:44.919533 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
879 13:41:44.919586 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 13:41:44.919640 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 13:41:44.919790 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
882 13:41:44.919913 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 13:41:44.919986 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 13:41:44.920099 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
885 13:41:44.920185 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 13:41:44.920269 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 13:41:44.920382 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 13:41:44.920465 ==
889 13:41:44.920549 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:41:44.920646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 13:41:44.920746 ==
892 13:41:44.920830 DQS Delay:
893 13:41:44.920913 DQS0 = 0, DQS1 = 0
894 13:41:44.921012 DQM Delay:
895 13:41:44.921096 DQM0 = 84, DQM1 = 71
896 13:41:44.921180 DQ Delay:
897 13:41:44.921280 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 13:41:44.921366 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
899 13:41:44.921452 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
900 13:41:44.921536 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
901 13:41:44.921618
902 13:41:44.921739
903 13:41:44.921822 ==
904 13:41:44.921905 Dram Type= 6, Freq= 0, CH_0, rank 0
905 13:41:44.921988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 13:41:44.922097 ==
907 13:41:44.922185
908 13:41:44.922254
909 13:41:44.922323 TX Vref Scan disable
910 13:41:44.922396 == TX Byte 0 ==
911 13:41:44.922453 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 13:41:44.922507 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 13:41:44.922560 == TX Byte 1 ==
914 13:41:44.922613 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
915 13:41:44.922680 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
916 13:41:44.922794 ==
917 13:41:44.922893 Dram Type= 6, Freq= 0, CH_0, rank 0
918 13:41:44.922950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 13:41:44.923004 ==
920 13:41:44.923057 TX Vref=22, minBit 5, minWin=27, winSum=445
921 13:41:44.923140 TX Vref=24, minBit 5, minWin=27, winSum=445
922 13:41:44.923401 TX Vref=26, minBit 14, minWin=27, winSum=448
923 13:41:44.923476 TX Vref=28, minBit 10, minWin=27, winSum=449
924 13:41:44.923616 TX Vref=30, minBit 10, minWin=27, winSum=448
925 13:41:44.923716 TX Vref=32, minBit 8, minWin=27, winSum=444
926 13:41:44.923816 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 28
927 13:41:44.923945
928 13:41:44.924047 Final TX Range 1 Vref 28
929 13:41:44.924136
930 13:41:44.924224 ==
931 13:41:44.924311 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:41:44.924425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:41:44.924513 ==
934 13:41:44.924597
935 13:41:44.924680
936 13:41:44.924764 TX Vref Scan disable
937 13:41:44.924850 == TX Byte 0 ==
938 13:41:44.924936 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 13:41:44.925022 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 13:41:44.925108 == TX Byte 1 ==
941 13:41:44.925211 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
942 13:41:44.925312 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
943 13:41:44.925398
944 13:41:44.925508 [DATLAT]
945 13:41:44.925592 Freq=800, CH0 RK0
946 13:41:44.925675
947 13:41:44.925756 DATLAT Default: 0xa
948 13:41:44.925841 0, 0xFFFF, sum = 0
949 13:41:44.925941 1, 0xFFFF, sum = 0
950 13:41:44.926028 2, 0xFFFF, sum = 0
951 13:41:44.926115 3, 0xFFFF, sum = 0
952 13:41:44.926226 4, 0xFFFF, sum = 0
953 13:41:44.926284 5, 0xFFFF, sum = 0
954 13:41:44.926414 6, 0xFFFF, sum = 0
955 13:41:44.926483 7, 0xFFFF, sum = 0
956 13:41:44.926537 8, 0xFFFF, sum = 0
957 13:41:44.926606 9, 0x0, sum = 1
958 13:41:44.926691 10, 0x0, sum = 2
959 13:41:44.926774 11, 0x0, sum = 3
960 13:41:44.926842 12, 0x0, sum = 4
961 13:41:44.926910 best_step = 10
962 13:41:44.926967
963 13:41:44.927026 ==
964 13:41:44.927098 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:41:44.927185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 13:41:44.927270 ==
967 13:41:44.927357 RX Vref Scan: 1
968 13:41:44.927442
969 13:41:44.927525 Set Vref Range= 32 -> 127
970 13:41:44.927639
971 13:41:44.927758 RX Vref 32 -> 127, step: 1
972 13:41:44.927844
973 13:41:44.927929 RX Delay -111 -> 252, step: 8
974 13:41:44.928013
975 13:41:44.928124 Set Vref, RX VrefLevel [Byte0]: 32
976 13:41:44.928221 [Byte1]: 32
977 13:41:44.928335
978 13:41:44.928449 Set Vref, RX VrefLevel [Byte0]: 33
979 13:41:44.928534 [Byte1]: 33
980 13:41:44.928618
981 13:41:44.928704 Set Vref, RX VrefLevel [Byte0]: 34
982 13:41:44.928789 [Byte1]: 34
983 13:41:44.928873
984 13:41:44.928942 Set Vref, RX VrefLevel [Byte0]: 35
985 13:41:44.929001 [Byte1]: 35
986 13:41:44.929056
987 13:41:44.929110 Set Vref, RX VrefLevel [Byte0]: 36
988 13:41:44.929164 [Byte1]: 36
989 13:41:44.929231
990 13:41:44.929299 Set Vref, RX VrefLevel [Byte0]: 37
991 13:41:44.929398 [Byte1]: 37
992 13:41:44.929547
993 13:41:44.929671 Set Vref, RX VrefLevel [Byte0]: 38
994 13:41:44.929765 [Byte1]: 38
995 13:41:44.929854
996 13:41:44.929946 Set Vref, RX VrefLevel [Byte0]: 39
997 13:41:44.930040 [Byte1]: 39
998 13:41:44.930133
999 13:41:44.930259 Set Vref, RX VrefLevel [Byte0]: 40
1000 13:41:44.930359 [Byte1]: 40
1001 13:41:44.930444
1002 13:41:44.930545 Set Vref, RX VrefLevel [Byte0]: 41
1003 13:41:44.930600 [Byte1]: 41
1004 13:41:44.930663
1005 13:41:44.930729 Set Vref, RX VrefLevel [Byte0]: 42
1006 13:41:44.930814 [Byte1]: 42
1007 13:41:44.930872
1008 13:41:44.930934 Set Vref, RX VrefLevel [Byte0]: 43
1009 13:41:44.930989 [Byte1]: 43
1010 13:41:44.931042
1011 13:41:44.931124 Set Vref, RX VrefLevel [Byte0]: 44
1012 13:41:44.931200 [Byte1]: 44
1013 13:41:44.931287
1014 13:41:44.931355 Set Vref, RX VrefLevel [Byte0]: 45
1015 13:41:44.931425 [Byte1]: 45
1016 13:41:44.931497
1017 13:41:44.931582 Set Vref, RX VrefLevel [Byte0]: 46
1018 13:41:44.931679 [Byte1]: 46
1019 13:41:44.931748
1020 13:41:44.931818 Set Vref, RX VrefLevel [Byte0]: 47
1021 13:41:44.931920 [Byte1]: 47
1022 13:41:44.931993
1023 13:41:44.932046 Set Vref, RX VrefLevel [Byte0]: 48
1024 13:41:44.932114 [Byte1]: 48
1025 13:41:44.932195
1026 13:41:44.932266 Set Vref, RX VrefLevel [Byte0]: 49
1027 13:41:44.932320 [Byte1]: 49
1028 13:41:44.932373
1029 13:41:44.932468 Set Vref, RX VrefLevel [Byte0]: 50
1030 13:41:44.932568 [Byte1]: 50
1031 13:41:44.932658
1032 13:41:44.932758 Set Vref, RX VrefLevel [Byte0]: 51
1033 13:41:44.932811 [Byte1]: 51
1034 13:41:44.932879
1035 13:41:44.932959 Set Vref, RX VrefLevel [Byte0]: 52
1036 13:41:44.933044 [Byte1]: 52
1037 13:41:44.933098
1038 13:41:44.933152 Set Vref, RX VrefLevel [Byte0]: 53
1039 13:41:44.933206 [Byte1]: 53
1040 13:41:44.933262
1041 13:41:44.933344 Set Vref, RX VrefLevel [Byte0]: 54
1042 13:41:44.933396 [Byte1]: 54
1043 13:41:44.933449
1044 13:41:44.933502 Set Vref, RX VrefLevel [Byte0]: 55
1045 13:41:44.933559 [Byte1]: 55
1046 13:41:44.933615
1047 13:41:44.933668 Set Vref, RX VrefLevel [Byte0]: 56
1048 13:41:44.933721 [Byte1]: 56
1049 13:41:44.933775
1050 13:41:44.933832 Set Vref, RX VrefLevel [Byte0]: 57
1051 13:41:44.933886 [Byte1]: 57
1052 13:41:44.933940
1053 13:41:44.933993 Set Vref, RX VrefLevel [Byte0]: 58
1054 13:41:44.934046 [Byte1]: 58
1055 13:41:44.934115
1056 13:41:44.934207 Set Vref, RX VrefLevel [Byte0]: 59
1057 13:41:44.934290 [Byte1]: 59
1058 13:41:44.934356
1059 13:41:44.934440 Set Vref, RX VrefLevel [Byte0]: 60
1060 13:41:44.934494 [Byte1]: 60
1061 13:41:44.934560
1062 13:41:44.934627 Set Vref, RX VrefLevel [Byte0]: 61
1063 13:41:44.934679 [Byte1]: 61
1064 13:41:44.934751
1065 13:41:44.934807 Set Vref, RX VrefLevel [Byte0]: 62
1066 13:41:44.934862 [Byte1]: 62
1067 13:41:44.934915
1068 13:41:44.934968 Set Vref, RX VrefLevel [Byte0]: 63
1069 13:41:44.935024 [Byte1]: 63
1070 13:41:44.935078
1071 13:41:44.935144 Set Vref, RX VrefLevel [Byte0]: 64
1072 13:41:44.935213 [Byte1]: 64
1073 13:41:44.935307
1074 13:41:44.935377 Set Vref, RX VrefLevel [Byte0]: 65
1075 13:41:44.935440 [Byte1]: 65
1076 13:41:44.935528
1077 13:41:44.935612 Set Vref, RX VrefLevel [Byte0]: 66
1078 13:41:44.935696 [Byte1]: 66
1079 13:41:44.935803
1080 13:41:44.935887 Set Vref, RX VrefLevel [Byte0]: 67
1081 13:41:44.935983 [Byte1]: 67
1082 13:41:44.936081
1083 13:41:44.936145 Set Vref, RX VrefLevel [Byte0]: 68
1084 13:41:44.936199 [Byte1]: 68
1085 13:41:44.936277
1086 13:41:44.936376 Set Vref, RX VrefLevel [Byte0]: 69
1087 13:41:44.936458 [Byte1]: 69
1088 13:41:44.936595
1089 13:41:44.936718 Set Vref, RX VrefLevel [Byte0]: 70
1090 13:41:44.937067 [Byte1]: 70
1091 13:41:44.937158
1092 13:41:44.937255 Set Vref, RX VrefLevel [Byte0]: 71
1093 13:41:44.937341 [Byte1]: 71
1094 13:41:44.937435
1095 13:41:44.937522 Set Vref, RX VrefLevel [Byte0]: 72
1096 13:41:44.937607 [Byte1]: 72
1097 13:41:44.937701
1098 13:41:44.937792 Set Vref, RX VrefLevel [Byte0]: 73
1099 13:41:44.937876 [Byte1]: 73
1100 13:41:44.937968
1101 13:41:44.938068 Set Vref, RX VrefLevel [Byte0]: 74
1102 13:41:44.938155 [Byte1]: 74
1103 13:41:44.938249
1104 13:41:44.938340 Set Vref, RX VrefLevel [Byte0]: 75
1105 13:41:44.938438 [Byte1]: 75
1106 13:41:44.938547
1107 13:41:44.938632 Set Vref, RX VrefLevel [Byte0]: 76
1108 13:41:44.938686 [Byte1]: 76
1109 13:41:44.938739
1110 13:41:44.938817 Set Vref, RX VrefLevel [Byte0]: 77
1111 13:41:44.938874 [Byte1]: 77
1112 13:41:44.938934
1113 13:41:44.939020 Set Vref, RX VrefLevel [Byte0]: 78
1114 13:41:44.939104 [Byte1]: 78
1115 13:41:44.939195
1116 13:41:44.939293 Set Vref, RX VrefLevel [Byte0]: 79
1117 13:41:44.939384 [Byte1]: 79
1118 13:41:44.939474
1119 13:41:44.939566 Set Vref, RX VrefLevel [Byte0]: 80
1120 13:41:44.939654 [Byte1]: 80
1121 13:41:44.939737
1122 13:41:44.939823 Set Vref, RX VrefLevel [Byte0]: 81
1123 13:41:44.939909 [Byte1]: 81
1124 13:41:44.939992
1125 13:41:44.940077 Final RX Vref Byte 0 = 63 to rank0
1126 13:41:44.940163 Final RX Vref Byte 1 = 57 to rank0
1127 13:41:44.940247 Final RX Vref Byte 0 = 63 to rank1
1128 13:41:44.940332 Final RX Vref Byte 1 = 57 to rank1==
1129 13:41:44.940419 Dram Type= 6, Freq= 0, CH_0, rank 0
1130 13:41:44.940504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 13:41:44.940588 ==
1132 13:41:44.940673 DQS Delay:
1133 13:41:44.940757 DQS0 = 0, DQS1 = 0
1134 13:41:44.940840 DQM Delay:
1135 13:41:44.940924 DQM0 = 86, DQM1 = 75
1136 13:41:44.941008 DQ Delay:
1137 13:41:44.941094 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1138 13:41:44.941179 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1139 13:41:44.941263 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1140 13:41:44.941359 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1141 13:41:44.941451
1142 13:41:44.941536
1143 13:41:44.941627 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1144 13:41:44.941720 CH0 RK0: MR19=606, MR18=4829
1145 13:41:44.941807 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1146 13:41:44.941892
1147 13:41:44.941986 ----->DramcWriteLeveling(PI) begin...
1148 13:41:44.942075 ==
1149 13:41:44.942164 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 13:41:44.942229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 13:41:44.942321 ==
1152 13:41:44.942410 Write leveling (Byte 0): 30 => 30
1153 13:41:44.942496 Write leveling (Byte 1): 29 => 29
1154 13:41:44.942583 DramcWriteLeveling(PI) end<-----
1155 13:41:44.942666
1156 13:41:44.942748 ==
1157 13:41:44.942833 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 13:41:44.942918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 13:41:44.943002 ==
1160 13:41:44.943085 [Gating] SW mode calibration
1161 13:41:44.943170 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1162 13:41:44.943241 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1163 13:41:44.943297 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 13:41:44.943355 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1165 13:41:44.943410 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1166 13:41:44.943464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:41:44.943518 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:41:44.943571 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:41:44.943625 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:41:44.943678 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:41:44.943732 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:41:44.943787 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:41:44.943884 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:41:44.943981 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:41:44.944069 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:41:44.944155 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:41:44.944240 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:41:44.944324 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:41:44.944410 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:41:44.944495 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1181 13:41:44.944579 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1182 13:41:44.944663 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:41:44.944749 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:41:44.944838 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:41:44.944923 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:41:44.945014 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:41:44.945106 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:41:44.945196 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:41:44.945283 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (0 0) (0 0)
1190 13:41:44.945380 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1191 13:41:44.945467 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 13:41:44.945561 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 13:41:44.945647 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 13:41:44.945732 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 13:41:44.945826 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 13:41:44.945917 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1197 13:41:44.946006 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (1 1) (1 0)
1198 13:41:44.946096 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1199 13:41:44.946188 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 13:41:44.946245 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 13:41:44.946322 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 13:41:44.946392 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:41:44.946682 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:41:44.946780 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:41:44.946867 0 11 8 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (0 0)
1206 13:41:44.946965 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1207 13:41:44.947058 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 13:41:44.947143 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 13:41:44.947229 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 13:41:44.947321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 13:41:44.947406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 13:41:44.947491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1213 13:41:44.947548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1214 13:41:44.947639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:41:44.947724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:41:44.947833 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:41:44.947933 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:41:44.948034 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 13:41:44.948121 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 13:41:44.948206 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 13:41:44.948302 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 13:41:44.948388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 13:41:44.948472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:41:44.948568 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 13:41:44.948655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 13:41:44.948744 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 13:41:44.948828 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 13:41:44.948924 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 13:41:44.949015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1230 13:41:44.949101 Total UI for P1: 0, mck2ui 16
1231 13:41:44.949191 best dqsien dly found for B0: ( 0, 14, 6)
1232 13:41:44.949281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 13:41:44.949373 Total UI for P1: 0, mck2ui 16
1234 13:41:44.949461 best dqsien dly found for B1: ( 0, 14, 8)
1235 13:41:44.949550 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1236 13:41:44.949645 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1237 13:41:44.949729
1238 13:41:44.949813 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1239 13:41:44.949906 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1240 13:41:44.949991 [Gating] SW calibration Done
1241 13:41:44.950075 ==
1242 13:41:44.950191 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 13:41:44.950252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 13:41:44.950308 ==
1245 13:41:44.950373 RX Vref Scan: 0
1246 13:41:44.950427
1247 13:41:44.950481 RX Vref 0 -> 0, step: 1
1248 13:41:44.950539
1249 13:41:44.950593 RX Delay -130 -> 252, step: 16
1250 13:41:44.950646 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1251 13:41:44.950750 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1252 13:41:44.950829 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1253 13:41:44.950890 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1254 13:41:44.950945 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1255 13:41:44.950999 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1256 13:41:44.951064 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1257 13:41:44.951118 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1258 13:41:44.951172 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1259 13:41:44.951240 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1260 13:41:44.951295 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1261 13:41:44.951349 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1262 13:41:44.951416 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1263 13:41:44.951509 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1264 13:41:44.951594 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1265 13:41:44.951686 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1266 13:41:44.951770 ==
1267 13:41:44.951872 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 13:41:44.951960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 13:41:44.952047 ==
1270 13:41:44.952131 DQS Delay:
1271 13:41:44.952216 DQS0 = 0, DQS1 = 0
1272 13:41:44.952303 DQM Delay:
1273 13:41:44.952389 DQM0 = 84, DQM1 = 78
1274 13:41:44.952474 DQ Delay:
1275 13:41:44.952558 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1276 13:41:44.952644 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1277 13:41:44.952727 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1278 13:41:44.952811 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1279 13:41:44.952894
1280 13:41:44.952977
1281 13:41:44.953061 ==
1282 13:41:44.953147 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 13:41:44.953232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 13:41:44.953317 ==
1285 13:41:44.953401
1286 13:41:44.953483
1287 13:41:44.953566 TX Vref Scan disable
1288 13:41:44.953650 == TX Byte 0 ==
1289 13:41:44.953737 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1290 13:41:44.953823 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1291 13:41:44.953907 == TX Byte 1 ==
1292 13:41:44.953992 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1293 13:41:44.954076 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1294 13:41:44.954158 ==
1295 13:41:44.954250 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 13:41:44.954334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 13:41:44.954419 ==
1298 13:41:44.954504 TX Vref=22, minBit 8, minWin=27, winSum=443
1299 13:41:44.954588 TX Vref=24, minBit 9, minWin=27, winSum=451
1300 13:41:44.954674 TX Vref=26, minBit 9, minWin=27, winSum=451
1301 13:41:44.954758 TX Vref=28, minBit 9, minWin=27, winSum=447
1302 13:41:44.954853 TX Vref=30, minBit 9, minWin=27, winSum=449
1303 13:41:44.954952 TX Vref=32, minBit 8, minWin=27, winSum=444
1304 13:41:44.955040 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 24
1305 13:41:44.955123
1306 13:41:44.955206 Final TX Range 1 Vref 24
1307 13:41:44.955291
1308 13:41:44.955375 ==
1309 13:41:44.955459 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 13:41:44.955542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 13:41:44.955626 ==
1312 13:41:44.955710
1313 13:41:44.955792
1314 13:41:44.955876 TX Vref Scan disable
1315 13:41:44.955959 == TX Byte 0 ==
1316 13:41:44.956042 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1317 13:41:44.956126 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1318 13:41:44.956211 == TX Byte 1 ==
1319 13:41:44.956499 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1320 13:41:44.956590 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1321 13:41:44.956676
1322 13:41:44.956745 [DATLAT]
1323 13:41:44.956799 Freq=800, CH0 RK1
1324 13:41:44.956854
1325 13:41:44.956907 DATLAT Default: 0xa
1326 13:41:44.956960 0, 0xFFFF, sum = 0
1327 13:41:44.957018 1, 0xFFFF, sum = 0
1328 13:41:44.957073 2, 0xFFFF, sum = 0
1329 13:41:44.957127 3, 0xFFFF, sum = 0
1330 13:41:44.957180 4, 0xFFFF, sum = 0
1331 13:41:44.957237 5, 0xFFFF, sum = 0
1332 13:41:44.957291 6, 0xFFFF, sum = 0
1333 13:41:44.957348 7, 0xFFFF, sum = 0
1334 13:41:44.957402 8, 0xFFFF, sum = 0
1335 13:41:44.957455 9, 0x0, sum = 1
1336 13:41:44.957510 10, 0x0, sum = 2
1337 13:41:44.957564 11, 0x0, sum = 3
1338 13:41:44.957617 12, 0x0, sum = 4
1339 13:41:44.957674 best_step = 10
1340 13:41:44.957730
1341 13:41:44.957787 ==
1342 13:41:44.957845 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 13:41:44.957901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 13:41:44.957957 ==
1345 13:41:44.958014 RX Vref Scan: 0
1346 13:41:44.958096
1347 13:41:44.958188 RX Vref 0 -> 0, step: 1
1348 13:41:44.958272
1349 13:41:44.958355 RX Delay -95 -> 252, step: 8
1350 13:41:44.958439 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1351 13:41:44.958524 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1352 13:41:44.958607 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1353 13:41:44.958690 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1354 13:41:44.958764 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1355 13:41:44.958819 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1356 13:41:44.958872 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1357 13:41:44.958928 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1358 13:41:44.958981 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1359 13:41:44.959034 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1360 13:41:44.959086 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1361 13:41:44.959139 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1362 13:41:44.959194 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1363 13:41:44.959248 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1364 13:41:44.959304 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1365 13:41:44.959356 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1366 13:41:44.959408 ==
1367 13:41:44.959460 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 13:41:44.959516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 13:41:44.959594 ==
1370 13:41:44.959649 DQS Delay:
1371 13:41:44.959702 DQS0 = 0, DQS1 = 0
1372 13:41:44.959754 DQM Delay:
1373 13:41:44.959806 DQM0 = 84, DQM1 = 77
1374 13:41:44.959861 DQ Delay:
1375 13:41:44.959916 DQ0 =80, DQ1 =92, DQ2 =76, DQ3 =84
1376 13:41:44.959969 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1377 13:41:44.960023 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1378 13:41:44.960075 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1379 13:41:44.960128
1380 13:41:44.960185
1381 13:41:44.960237 [DQSOSCAuto] RK1, (LSB)MR18= 0x4005, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1382 13:41:44.960299 CH0 RK1: MR19=606, MR18=4005
1383 13:41:44.960354 CH0_RK1: MR19=0x606, MR18=0x4005, DQSOSC=393, MR23=63, INC=95, DEC=63
1384 13:41:44.960407 [RxdqsGatingPostProcess] freq 800
1385 13:41:44.960478 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1386 13:41:44.960568 Pre-setting of DQS Precalculation
1387 13:41:44.960661 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1388 13:41:44.960747 ==
1389 13:41:44.960841 Dram Type= 6, Freq= 0, CH_1, rank 0
1390 13:41:44.960925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 13:41:44.961009 ==
1392 13:41:44.961102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 13:41:44.961189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 13:41:44.961279 [CA 0] Center 36 (6~67) winsize 62
1395 13:41:44.961363 [CA 1] Center 36 (6~67) winsize 62
1396 13:41:44.961456 [CA 2] Center 34 (4~65) winsize 62
1397 13:41:44.961541 [CA 3] Center 34 (3~65) winsize 63
1398 13:41:44.961631 [CA 4] Center 34 (4~65) winsize 62
1399 13:41:44.961716 [CA 5] Center 34 (3~65) winsize 63
1400 13:41:44.961823
1401 13:41:44.961911 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1402 13:41:44.962006
1403 13:41:44.962091 [CATrainingPosCal] consider 1 rank data
1404 13:41:44.962184 u2DelayCellTimex100 = 270/100 ps
1405 13:41:44.962277 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1406 13:41:44.962369 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1407 13:41:44.962442 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 13:41:44.962497 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1409 13:41:44.962551 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 13:41:44.962617 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 13:41:44.962675
1412 13:41:44.962727 CA PerBit enable=1, Macro0, CA PI delay=34
1413 13:41:44.962780
1414 13:41:44.962842 [CBTSetCACLKResult] CA Dly = 34
1415 13:41:44.962903 CS Dly: 4 (0~35)
1416 13:41:44.962956 ==
1417 13:41:44.963009 Dram Type= 6, Freq= 0, CH_1, rank 1
1418 13:41:44.963063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 13:41:44.963117 ==
1420 13:41:44.963172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 13:41:44.963226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 13:41:44.963279 [CA 0] Center 36 (6~67) winsize 62
1423 13:41:44.963332 [CA 1] Center 36 (6~67) winsize 62
1424 13:41:44.963384 [CA 2] Center 34 (4~65) winsize 62
1425 13:41:44.963436 [CA 3] Center 34 (3~65) winsize 63
1426 13:41:44.963492 [CA 4] Center 34 (4~65) winsize 62
1427 13:41:44.963545 [CA 5] Center 34 (3~65) winsize 63
1428 13:41:44.963598
1429 13:41:44.963653 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1430 13:41:44.963706
1431 13:41:44.963758 [CATrainingPosCal] consider 2 rank data
1432 13:41:44.963810 u2DelayCellTimex100 = 270/100 ps
1433 13:41:44.963862 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 13:41:44.963914 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 13:41:44.963969 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 13:41:44.964022 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1437 13:41:44.964074 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 13:41:44.964126 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 13:41:44.964194
1440 13:41:44.964247 CA PerBit enable=1, Macro0, CA PI delay=34
1441 13:41:44.964300
1442 13:41:44.964388 [CBTSetCACLKResult] CA Dly = 34
1443 13:41:44.964482 CS Dly: 5 (0~38)
1444 13:41:44.964571
1445 13:41:44.964663 ----->DramcWriteLeveling(PI) begin...
1446 13:41:44.964765 ==
1447 13:41:44.964855 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 13:41:44.964941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 13:41:44.965031 ==
1450 13:41:44.965120 Write leveling (Byte 0): 30 => 30
1451 13:41:44.965205 Write leveling (Byte 1): 30 => 30
1452 13:41:44.965298 DramcWriteLeveling(PI) end<-----
1453 13:41:44.965393
1454 13:41:44.965480 ==
1455 13:41:44.965782 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 13:41:44.965877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 13:41:44.965968 ==
1458 13:41:44.966061 [Gating] SW mode calibration
1459 13:41:44.966155 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1460 13:41:44.966263 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1461 13:41:44.966348 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 13:41:44.966443 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:41:44.966529 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:41:44.966625 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:41:44.966711 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:41:44.966800 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:41:44.966888 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:41:44.966977 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:41:44.967062 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:41:44.967155 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:41:44.967251 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:41:44.967355 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:41:44.967441 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:41:44.967501 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:41:44.967567 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:41:44.967654 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:41:44.967737 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:41:44.967820 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1479 13:41:44.967904 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1480 13:41:44.967989 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:41:44.968072 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:41:44.968155 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:41:44.968240 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:41:44.968323 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:41:44.968402 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:41:44.968457 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:41:44.968510 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1488 13:41:44.968566 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 13:41:44.968620 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 13:41:44.968673 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 13:41:44.968726 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 13:41:44.968779 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 13:41:44.968835 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 13:41:44.968888 0 10 4 | B1->B0 | 3232 3232 | 0 0 | (0 1) (0 0)
1495 13:41:44.968940 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
1496 13:41:44.969003 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 13:41:44.969086 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 13:41:44.969170 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 13:41:44.969253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 13:41:44.969336 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:41:44.969420 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:41:44.969505 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 1)
1503 13:41:44.969588 0 11 8 | B1->B0 | 3939 4545 | 0 0 | (1 1) (1 1)
1504 13:41:44.969671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 13:41:44.969757 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 13:41:44.969841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 13:41:44.969924 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 13:41:44.970008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 13:41:44.970093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 13:41:44.970184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1511 13:41:44.970244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1512 13:41:44.970302 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:41:44.970358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:41:44.970415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:41:44.970501 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 13:41:44.970586 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 13:41:44.970669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 13:41:44.970754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 13:41:44.970839 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 13:41:44.970922 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 13:41:44.971006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 13:41:44.971089 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 13:41:44.971175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 13:41:44.971260 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 13:41:44.971344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 13:41:44.971427 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1527 13:41:44.971512 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 13:41:44.971595 Total UI for P1: 0, mck2ui 16
1529 13:41:44.971679 best dqsien dly found for B0: ( 0, 14, 4)
1530 13:41:44.971762 Total UI for P1: 0, mck2ui 16
1531 13:41:44.971846 best dqsien dly found for B1: ( 0, 14, 6)
1532 13:41:44.971932 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1533 13:41:44.972015 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1534 13:41:44.972096
1535 13:41:44.972181 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1536 13:41:44.972264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1537 13:41:44.972346 [Gating] SW calibration Done
1538 13:41:44.972429 ==
1539 13:41:44.972514 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 13:41:44.972802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 13:41:44.972890 ==
1542 13:41:44.972981 RX Vref Scan: 0
1543 13:41:44.973077
1544 13:41:44.973164 RX Vref 0 -> 0, step: 1
1545 13:41:44.973249
1546 13:41:44.973332 RX Delay -130 -> 252, step: 16
1547 13:41:44.973414 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1548 13:41:44.973470 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1549 13:41:44.973523 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1550 13:41:44.973576 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1551 13:41:44.973658 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1552 13:41:44.973742 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1553 13:41:44.973825 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1554 13:41:44.973908 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1555 13:41:44.973992 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1556 13:41:44.974076 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1557 13:41:44.974168 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1558 13:41:44.974227 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1559 13:41:44.974280 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1560 13:41:44.974332 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1561 13:41:44.974415 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1562 13:41:44.974498 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1563 13:41:44.974582 ==
1564 13:41:44.974668 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 13:41:44.974752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 13:41:44.974834 ==
1567 13:41:44.974918 DQS Delay:
1568 13:41:44.975001 DQS0 = 0, DQS1 = 0
1569 13:41:44.975084 DQM Delay:
1570 13:41:44.975167 DQM0 = 89, DQM1 = 78
1571 13:41:44.975256 DQ Delay:
1572 13:41:44.975340 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1573 13:41:44.975423 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1574 13:41:44.975506 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1575 13:41:44.975591 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1576 13:41:44.975673
1577 13:41:44.975755
1578 13:41:44.975836 ==
1579 13:41:44.975921 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 13:41:44.976005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 13:41:44.976087 ==
1582 13:41:44.976170
1583 13:41:44.976253
1584 13:41:44.976336 TX Vref Scan disable
1585 13:41:44.976421 == TX Byte 0 ==
1586 13:41:44.976508 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1587 13:41:44.976594 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1588 13:41:44.976677 == TX Byte 1 ==
1589 13:41:44.976763 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1590 13:41:44.976846 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1591 13:41:44.976929 ==
1592 13:41:44.977012 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 13:41:44.977097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 13:41:44.977180 ==
1595 13:41:44.977264 TX Vref=22, minBit 10, minWin=26, winSum=441
1596 13:41:44.977344 TX Vref=24, minBit 8, minWin=26, winSum=447
1597 13:41:44.977404 TX Vref=26, minBit 9, minWin=27, winSum=448
1598 13:41:44.977462 TX Vref=28, minBit 10, minWin=27, winSum=449
1599 13:41:44.977541 TX Vref=30, minBit 8, minWin=27, winSum=447
1600 13:41:44.977625 TX Vref=32, minBit 8, minWin=27, winSum=443
1601 13:41:44.977711 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 28
1602 13:41:44.977795
1603 13:41:44.977878 Final TX Range 1 Vref 28
1604 13:41:44.977964
1605 13:41:44.978045 ==
1606 13:41:44.978128 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 13:41:44.978214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 13:41:44.978270 ==
1609 13:41:44.978326
1610 13:41:44.978379
1611 13:41:44.978430 TX Vref Scan disable
1612 13:41:44.978487 == TX Byte 0 ==
1613 13:41:44.978542 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1614 13:41:44.978596 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1615 13:41:44.978648 == TX Byte 1 ==
1616 13:41:44.978704 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1617 13:41:44.978757 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1618 13:41:44.978809
1619 13:41:44.978861 [DATLAT]
1620 13:41:44.978913 Freq=800, CH1 RK0
1621 13:41:44.978966
1622 13:41:44.979022 DATLAT Default: 0xa
1623 13:41:44.979079 0, 0xFFFF, sum = 0
1624 13:41:44.979164 1, 0xFFFF, sum = 0
1625 13:41:44.979249 2, 0xFFFF, sum = 0
1626 13:41:44.979317 3, 0xFFFF, sum = 0
1627 13:41:44.979372 4, 0xFFFF, sum = 0
1628 13:41:44.979426 5, 0xFFFF, sum = 0
1629 13:41:44.979479 6, 0xFFFF, sum = 0
1630 13:41:44.979532 7, 0xFFFF, sum = 0
1631 13:41:44.979584 8, 0xFFFF, sum = 0
1632 13:41:44.979642 9, 0x0, sum = 1
1633 13:41:44.979699 10, 0x0, sum = 2
1634 13:41:44.979753 11, 0x0, sum = 3
1635 13:41:44.979806 12, 0x0, sum = 4
1636 13:41:44.979859 best_step = 10
1637 13:41:44.979914
1638 13:41:44.979967 ==
1639 13:41:44.980019 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 13:41:44.980071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 13:41:44.980128 ==
1642 13:41:44.980186 RX Vref Scan: 1
1643 13:41:44.980239
1644 13:41:44.980311 Set Vref Range= 32 -> 127
1645 13:41:44.980402
1646 13:41:44.980486 RX Vref 32 -> 127, step: 1
1647 13:41:44.980560
1648 13:41:44.980615 RX Delay -95 -> 252, step: 8
1649 13:41:44.980669
1650 13:41:44.980721 Set Vref, RX VrefLevel [Byte0]: 32
1651 13:41:44.980784 [Byte1]: 32
1652 13:41:44.980840
1653 13:41:44.980905 Set Vref, RX VrefLevel [Byte0]: 33
1654 13:41:44.980989 [Byte1]: 33
1655 13:41:44.981058
1656 13:41:44.981113 Set Vref, RX VrefLevel [Byte0]: 34
1657 13:41:44.981165 [Byte1]: 34
1658 13:41:44.981218
1659 13:41:44.981270 Set Vref, RX VrefLevel [Byte0]: 35
1660 13:41:44.981322 [Byte1]: 35
1661 13:41:44.981375
1662 13:41:44.981426 Set Vref, RX VrefLevel [Byte0]: 36
1663 13:41:44.981482 [Byte1]: 36
1664 13:41:44.981534
1665 13:41:44.981586 Set Vref, RX VrefLevel [Byte0]: 37
1666 13:41:44.981637 [Byte1]: 37
1667 13:41:44.981690
1668 13:41:44.981741 Set Vref, RX VrefLevel [Byte0]: 38
1669 13:41:44.981793 [Byte1]: 38
1670 13:41:44.981850
1671 13:41:44.981902 Set Vref, RX VrefLevel [Byte0]: 39
1672 13:41:44.981955 [Byte1]: 39
1673 13:41:44.982006
1674 13:41:44.982058 Set Vref, RX VrefLevel [Byte0]: 40
1675 13:41:44.982109 [Byte1]: 40
1676 13:41:44.982172
1677 13:41:44.982226 Set Vref, RX VrefLevel [Byte0]: 41
1678 13:41:44.982283 [Byte1]: 41
1679 13:41:44.982340
1680 13:41:44.982392 Set Vref, RX VrefLevel [Byte0]: 42
1681 13:41:44.982444 [Byte1]: 42
1682 13:41:44.982496
1683 13:41:44.982547 Set Vref, RX VrefLevel [Byte0]: 43
1684 13:41:44.982599 [Byte1]: 43
1685 13:41:44.982656
1686 13:41:44.982709 Set Vref, RX VrefLevel [Byte0]: 44
1687 13:41:44.982761 [Byte1]: 44
1688 13:41:44.982813
1689 13:41:44.982865 Set Vref, RX VrefLevel [Byte0]: 45
1690 13:41:44.982921 [Byte1]: 45
1691 13:41:44.982977
1692 13:41:44.983034 Set Vref, RX VrefLevel [Byte0]: 46
1693 13:41:44.983091 [Byte1]: 46
1694 13:41:44.983172
1695 13:41:44.983256 Set Vref, RX VrefLevel [Byte0]: 47
1696 13:41:44.983339 [Byte1]: 47
1697 13:41:44.983420
1698 13:41:44.983703 Set Vref, RX VrefLevel [Byte0]: 48
1699 13:41:44.983792 [Byte1]: 48
1700 13:41:44.983862
1701 13:41:44.983917 Set Vref, RX VrefLevel [Byte0]: 49
1702 13:41:44.983970 [Byte1]: 49
1703 13:41:44.984024
1704 13:41:44.984095 Set Vref, RX VrefLevel [Byte0]: 50
1705 13:41:44.984150 [Byte1]: 50
1706 13:41:44.984219
1707 13:41:44.984302 Set Vref, RX VrefLevel [Byte0]: 51
1708 13:41:44.984386 [Byte1]: 51
1709 13:41:44.984468
1710 13:41:44.984550 Set Vref, RX VrefLevel [Byte0]: 52
1711 13:41:44.984633 [Byte1]: 52
1712 13:41:44.984691
1713 13:41:44.984774 Set Vref, RX VrefLevel [Byte0]: 53
1714 13:41:44.984840 [Byte1]: 53
1715 13:41:44.984892
1716 13:41:44.984944 Set Vref, RX VrefLevel [Byte0]: 54
1717 13:41:44.984997 [Byte1]: 54
1718 13:41:44.985049
1719 13:41:44.985102 Set Vref, RX VrefLevel [Byte0]: 55
1720 13:41:44.985154 [Byte1]: 55
1721 13:41:44.985209
1722 13:41:44.985263 Set Vref, RX VrefLevel [Byte0]: 56
1723 13:41:44.985316 [Byte1]: 56
1724 13:41:44.985368
1725 13:41:44.985420 Set Vref, RX VrefLevel [Byte0]: 57
1726 13:41:44.985472 [Byte1]: 57
1727 13:41:44.985524
1728 13:41:44.985589 Set Vref, RX VrefLevel [Byte0]: 58
1729 13:41:44.985677 [Byte1]: 58
1730 13:41:44.985760
1731 13:41:44.985842 Set Vref, RX VrefLevel [Byte0]: 59
1732 13:41:44.985930 [Byte1]: 59
1733 13:41:44.986015
1734 13:41:44.986099 Set Vref, RX VrefLevel [Byte0]: 60
1735 13:41:44.986187 [Byte1]: 60
1736 13:41:44.986243
1737 13:41:44.986296 Set Vref, RX VrefLevel [Byte0]: 61
1738 13:41:44.986353 [Byte1]: 61
1739 13:41:44.986406
1740 13:41:44.986459 Set Vref, RX VrefLevel [Byte0]: 62
1741 13:41:44.986511 [Byte1]: 62
1742 13:41:44.986564
1743 13:41:44.986616 Set Vref, RX VrefLevel [Byte0]: 63
1744 13:41:44.986672 [Byte1]: 63
1745 13:41:44.986728
1746 13:41:44.986781 Set Vref, RX VrefLevel [Byte0]: 64
1747 13:41:44.986833 [Byte1]: 64
1748 13:41:44.986886
1749 13:41:44.986939 Set Vref, RX VrefLevel [Byte0]: 65
1750 13:41:44.986991 [Byte1]: 65
1751 13:41:44.987047
1752 13:41:44.987104 Set Vref, RX VrefLevel [Byte0]: 66
1753 13:41:44.987161 [Byte1]: 66
1754 13:41:44.987216
1755 13:41:44.987268 Set Vref, RX VrefLevel [Byte0]: 67
1756 13:41:44.987333 [Byte1]: 67
1757 13:41:44.987423
1758 13:41:44.987508 Set Vref, RX VrefLevel [Byte0]: 68
1759 13:41:44.987592 [Byte1]: 68
1760 13:41:44.987674
1761 13:41:44.987757 Set Vref, RX VrefLevel [Byte0]: 69
1762 13:41:44.987826 [Byte1]: 69
1763 13:41:44.987880
1764 13:41:44.987933 Set Vref, RX VrefLevel [Byte0]: 70
1765 13:41:44.987986 [Byte1]: 70
1766 13:41:44.988038
1767 13:41:44.988091 Set Vref, RX VrefLevel [Byte0]: 71
1768 13:41:44.988146 [Byte1]: 71
1769 13:41:44.988199
1770 13:41:44.988251 Set Vref, RX VrefLevel [Byte0]: 72
1771 13:41:44.988303 [Byte1]: 72
1772 13:41:44.988355
1773 13:41:44.988406 Set Vref, RX VrefLevel [Byte0]: 73
1774 13:41:44.988465 [Byte1]: 73
1775 13:41:44.988551
1776 13:41:44.988609 Set Vref, RX VrefLevel [Byte0]: 74
1777 13:41:44.988662 [Byte1]: 74
1778 13:41:44.988715
1779 13:41:44.988770 Set Vref, RX VrefLevel [Byte0]: 75
1780 13:41:44.988825 [Byte1]: 75
1781 13:41:44.988880
1782 13:41:44.988933 Set Vref, RX VrefLevel [Byte0]: 76
1783 13:41:44.988985 [Byte1]: 76
1784 13:41:44.989038
1785 13:41:44.989090 Set Vref, RX VrefLevel [Byte0]: 77
1786 13:41:44.989142 [Byte1]: 77
1787 13:41:44.989194
1788 13:41:44.989250 Final RX Vref Byte 0 = 52 to rank0
1789 13:41:44.989304 Final RX Vref Byte 1 = 64 to rank0
1790 13:41:44.989356 Final RX Vref Byte 0 = 52 to rank1
1791 13:41:44.989408 Final RX Vref Byte 1 = 64 to rank1==
1792 13:41:44.989460 Dram Type= 6, Freq= 0, CH_1, rank 0
1793 13:41:44.989517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 13:41:44.989571 ==
1795 13:41:44.989623 DQS Delay:
1796 13:41:44.989680 DQS0 = 0, DQS1 = 0
1797 13:41:44.989752 DQM Delay:
1798 13:41:44.989809 DQM0 = 86, DQM1 = 79
1799 13:41:44.989871 DQ Delay:
1800 13:41:44.989957 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1801 13:41:44.990040 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1802 13:41:44.990123 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1803 13:41:44.990211 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1804 13:41:44.990295
1805 13:41:44.990377
1806 13:41:44.990435 [DQSOSCAuto] RK0, (LSB)MR18= 0x321e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1807 13:41:44.990490 CH1 RK0: MR19=606, MR18=321E
1808 13:41:44.990543 CH1_RK0: MR19=0x606, MR18=0x321E, DQSOSC=397, MR23=63, INC=93, DEC=62
1809 13:41:44.990597
1810 13:41:44.990663 ----->DramcWriteLeveling(PI) begin...
1811 13:41:44.990719 ==
1812 13:41:44.990775 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 13:41:44.990831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 13:41:44.990884 ==
1815 13:41:44.990937 Write leveling (Byte 0): 27 => 27
1816 13:41:44.990993 Write leveling (Byte 1): 29 => 29
1817 13:41:44.991079 DramcWriteLeveling(PI) end<-----
1818 13:41:44.991135
1819 13:41:44.991203 ==
1820 13:41:44.991262 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 13:41:44.991322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 13:41:44.991410 ==
1823 13:41:44.991493 [Gating] SW mode calibration
1824 13:41:44.991583 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1825 13:41:44.991668 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1826 13:41:44.991745 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1827 13:41:44.991801 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1828 13:41:44.991854 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1829 13:41:44.991908 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:41:44.991961 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:41:44.992018 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:41:44.992073 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:41:44.992125 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:41:44.992178 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:41:44.992230 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:41:44.992282 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:41:44.992339 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:41:44.992596 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:41:44.992658 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:41:44.992719 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:41:44.992806 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:41:44.992894 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:41:44.992979 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1844 13:41:44.993063 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1845 13:41:44.993148 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:41:44.993232 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:41:44.993315 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:41:44.993400 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:41:44.993483 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:41:44.993567 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:41:44.993652 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:41:44.993736 0 9 8 | B1->B0 | 3333 2b2b | 0 1 | (0 0) (1 1)
1853 13:41:44.993819 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 13:41:44.993904 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 13:41:44.993988 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 13:41:44.994071 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 13:41:44.994154 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 13:41:44.994223 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 13:41:44.994277 0 10 4 | B1->B0 | 3232 3333 | 0 0 | (0 0) (1 0)
1860 13:41:44.994329 0 10 8 | B1->B0 | 2525 2e2e | 0 1 | (0 0) (1 0)
1861 13:41:44.994382 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:41:44.994438 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:41:44.994491 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:41:44.994544 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:41:44.994596 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:41:44.994649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:41:44.994702 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1868 13:41:44.994754 0 11 8 | B1->B0 | 4545 3636 | 0 1 | (0 0) (0 0)
1869 13:41:44.994807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 13:41:44.994877 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 13:41:44.994961 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 13:41:44.995044 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 13:41:44.995129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 13:41:44.995213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 13:41:44.995283 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 13:41:44.995338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:41:44.995392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:41:44.995467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:41:44.995528 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:41:44.995586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:41:44.995643 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:41:44.995737 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 13:41:44.995823 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 13:41:44.995914 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 13:41:44.996000 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 13:41:44.996092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 13:41:44.996178 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 13:41:44.996267 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 13:41:44.996354 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 13:41:44.996440 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 13:41:44.996529 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 13:41:44.996613 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 13:41:44.996704 Total UI for P1: 0, mck2ui 16
1894 13:41:44.996788 best dqsien dly found for B0: ( 0, 14, 6)
1895 13:41:44.996883 Total UI for P1: 0, mck2ui 16
1896 13:41:44.996968 best dqsien dly found for B1: ( 0, 14, 6)
1897 13:41:44.997058 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1898 13:41:44.997144 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1899 13:41:44.997237
1900 13:41:44.997327 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1901 13:41:44.997411 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1902 13:41:44.997499 [Gating] SW calibration Done
1903 13:41:44.997602 ==
1904 13:41:44.997688 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 13:41:44.997777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 13:41:44.997868 ==
1907 13:41:44.997951 RX Vref Scan: 0
1908 13:41:44.998033
1909 13:41:44.998135 RX Vref 0 -> 0, step: 1
1910 13:41:44.998253
1911 13:41:44.998338 RX Delay -130 -> 252, step: 16
1912 13:41:44.998425 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1913 13:41:44.998512 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1914 13:41:44.998607 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1915 13:41:44.998693 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1916 13:41:44.998779 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1917 13:41:44.998862 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1918 13:41:44.998945 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1919 13:41:44.999031 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1920 13:41:45.461181 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1921 13:41:45.461382 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1922 13:41:45.461498 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1923 13:41:45.461606 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1924 13:41:45.461711 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1925 13:41:45.461815 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1926 13:41:45.461919 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1927 13:41:45.462023 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1928 13:41:45.462123 ==
1929 13:41:45.462240 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 13:41:45.462570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 13:41:45.462684 ==
1932 13:41:45.462791 DQS Delay:
1933 13:41:45.462893 DQS0 = 0, DQS1 = 0
1934 13:41:45.462996 DQM Delay:
1935 13:41:45.463097 DQM0 = 85, DQM1 = 77
1936 13:41:45.463197 DQ Delay:
1937 13:41:45.463299 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1938 13:41:45.463399 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1939 13:41:45.463499 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1940 13:41:45.463599 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1941 13:41:45.463699
1942 13:41:45.463798
1943 13:41:45.463895 ==
1944 13:41:45.463995 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 13:41:45.464094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 13:41:45.464195 ==
1947 13:41:45.464294
1948 13:41:45.464392
1949 13:41:45.464491 TX Vref Scan disable
1950 13:41:45.464589 == TX Byte 0 ==
1951 13:41:45.464688 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 13:41:45.464789 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 13:41:45.464888 == TX Byte 1 ==
1954 13:41:45.464986 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1955 13:41:45.465085 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1956 13:41:45.465184 ==
1957 13:41:45.465283 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 13:41:45.465384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 13:41:45.465485 ==
1960 13:41:45.465584 TX Vref=22, minBit 8, minWin=26, winSum=444
1961 13:41:45.465684 TX Vref=24, minBit 13, minWin=27, winSum=451
1962 13:41:45.465785 TX Vref=26, minBit 8, minWin=27, winSum=452
1963 13:41:45.465885 TX Vref=28, minBit 8, minWin=27, winSum=451
1964 13:41:45.465985 TX Vref=30, minBit 8, minWin=27, winSum=451
1965 13:41:45.466084 TX Vref=32, minBit 13, minWin=27, winSum=449
1966 13:41:45.466195 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 26
1967 13:41:45.466303
1968 13:41:45.466404 Final TX Range 1 Vref 26
1969 13:41:45.466506
1970 13:41:45.466606 ==
1971 13:41:45.466706 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 13:41:45.466806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 13:41:45.466907 ==
1974 13:41:45.467006
1975 13:41:45.467103
1976 13:41:45.467200 TX Vref Scan disable
1977 13:41:45.467309 == TX Byte 0 ==
1978 13:41:45.467420 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1979 13:41:45.467530 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1980 13:41:45.467640 == TX Byte 1 ==
1981 13:41:45.467749 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1982 13:41:45.467857 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1983 13:41:45.467962
1984 13:41:45.468062 [DATLAT]
1985 13:41:45.468163 Freq=800, CH1 RK1
1986 13:41:45.468265
1987 13:41:45.468364 DATLAT Default: 0xa
1988 13:41:45.468464 0, 0xFFFF, sum = 0
1989 13:41:45.468567 1, 0xFFFF, sum = 0
1990 13:41:45.468670 2, 0xFFFF, sum = 0
1991 13:41:45.468770 3, 0xFFFF, sum = 0
1992 13:41:45.468872 4, 0xFFFF, sum = 0
1993 13:41:45.468973 5, 0xFFFF, sum = 0
1994 13:41:45.469074 6, 0xFFFF, sum = 0
1995 13:41:45.469175 7, 0xFFFF, sum = 0
1996 13:41:45.469275 8, 0xFFFF, sum = 0
1997 13:41:45.469375 9, 0x0, sum = 1
1998 13:41:45.469476 10, 0x0, sum = 2
1999 13:41:45.469576 11, 0x0, sum = 3
2000 13:41:45.469677 12, 0x0, sum = 4
2001 13:41:45.469776 best_step = 10
2002 13:41:45.469873
2003 13:41:45.469971 ==
2004 13:41:45.470069 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 13:41:45.470175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 13:41:45.470275 ==
2007 13:41:45.470373 RX Vref Scan: 0
2008 13:41:45.470471
2009 13:41:45.470569 RX Vref 0 -> 0, step: 1
2010 13:41:45.470667
2011 13:41:45.470764 RX Delay -95 -> 252, step: 8
2012 13:41:45.470862 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2013 13:41:45.470961 iDelay=217, Bit 1, Center 84 (-23 ~ 192) 216
2014 13:41:45.471059 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2015 13:41:45.471157 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2016 13:41:45.471255 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2017 13:41:45.471354 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2018 13:41:45.471453 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2019 13:41:45.471552 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2020 13:41:45.471650 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2021 13:41:45.471748 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2022 13:41:45.471844 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2023 13:41:45.471942 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2024 13:41:45.472039 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2025 13:41:45.472137 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2026 13:41:45.472235 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2027 13:41:45.472334 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2028 13:41:45.472431 ==
2029 13:41:45.472529 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 13:41:45.472628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 13:41:45.472728 ==
2032 13:41:45.472826 DQS Delay:
2033 13:41:45.472923 DQS0 = 0, DQS1 = 0
2034 13:41:45.473021 DQM Delay:
2035 13:41:45.473118 DQM0 = 87, DQM1 = 78
2036 13:41:45.473194 DQ Delay:
2037 13:41:45.473273 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =84
2038 13:41:45.473350 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2039 13:41:45.473427 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2040 13:41:45.473524 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2041 13:41:45.473620
2042 13:41:45.473715
2043 13:41:45.473810 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2044 13:41:45.473907 CH1 RK1: MR19=606, MR18=1B13
2045 13:41:45.474003 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2046 13:41:45.474098 [RxdqsGatingPostProcess] freq 800
2047 13:41:45.474203 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2048 13:41:45.474301 Pre-setting of DQS Precalculation
2049 13:41:45.474397 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2050 13:41:45.474493 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2051 13:41:45.474590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2052 13:41:45.474686
2053 13:41:45.474780
2054 13:41:45.474874 [Calibration Summary] 1600 Mbps
2055 13:41:45.474970 CH 0, Rank 0
2056 13:41:45.475065 SW Impedance : PASS
2057 13:41:45.475159 DUTY Scan : NO K
2058 13:41:45.475254 ZQ Calibration : PASS
2059 13:41:45.475348 Jitter Meter : NO K
2060 13:41:45.475443 CBT Training : PASS
2061 13:41:45.475537 Write leveling : PASS
2062 13:41:45.475632 RX DQS gating : PASS
2063 13:41:45.475726 RX DQ/DQS(RDDQC) : PASS
2064 13:41:45.475820 TX DQ/DQS : PASS
2065 13:41:45.475921 RX DATLAT : PASS
2066 13:41:45.476015 RX DQ/DQS(Engine): PASS
2067 13:41:45.476102 TX OE : NO K
2068 13:41:45.476187 All Pass.
2069 13:41:45.476279
2070 13:41:45.476372 CH 0, Rank 1
2071 13:41:45.476467 SW Impedance : PASS
2072 13:41:45.476561 DUTY Scan : NO K
2073 13:41:45.476656 ZQ Calibration : PASS
2074 13:41:45.476750 Jitter Meter : NO K
2075 13:41:45.476845 CBT Training : PASS
2076 13:41:45.476939 Write leveling : PASS
2077 13:41:45.477032 RX DQS gating : PASS
2078 13:41:45.477341 RX DQ/DQS(RDDQC) : PASS
2079 13:41:45.477456 TX DQ/DQS : PASS
2080 13:41:45.477563 RX DATLAT : PASS
2081 13:41:45.477660 RX DQ/DQS(Engine): PASS
2082 13:41:45.477737 TX OE : NO K
2083 13:41:45.477815 All Pass.
2084 13:41:45.477892
2085 13:41:45.477987 CH 1, Rank 0
2086 13:41:45.478083 SW Impedance : PASS
2087 13:41:45.478186 DUTY Scan : NO K
2088 13:41:45.478286 ZQ Calibration : PASS
2089 13:41:45.478382 Jitter Meter : NO K
2090 13:41:45.478478 CBT Training : PASS
2091 13:41:45.478573 Write leveling : PASS
2092 13:41:45.478668 RX DQS gating : PASS
2093 13:41:45.478763 RX DQ/DQS(RDDQC) : PASS
2094 13:41:45.478857 TX DQ/DQS : PASS
2095 13:41:45.478952 RX DATLAT : PASS
2096 13:41:45.479046 RX DQ/DQS(Engine): PASS
2097 13:41:45.479140 TX OE : NO K
2098 13:41:45.479234 All Pass.
2099 13:41:45.479339
2100 13:41:45.479436 CH 1, Rank 1
2101 13:41:45.479531 SW Impedance : PASS
2102 13:41:45.479626 DUTY Scan : NO K
2103 13:41:45.479721 ZQ Calibration : PASS
2104 13:41:45.479814 Jitter Meter : NO K
2105 13:41:45.479908 CBT Training : PASS
2106 13:41:45.480002 Write leveling : PASS
2107 13:41:45.480096 RX DQS gating : PASS
2108 13:41:45.480190 RX DQ/DQS(RDDQC) : PASS
2109 13:41:45.480286 TX DQ/DQS : PASS
2110 13:41:45.480381 RX DATLAT : PASS
2111 13:41:45.480475 RX DQ/DQS(Engine): PASS
2112 13:41:45.480569 TX OE : NO K
2113 13:41:45.480663 All Pass.
2114 13:41:45.480758
2115 13:41:45.480852 DramC Write-DBI off
2116 13:41:45.480947 PER_BANK_REFRESH: Hybrid Mode
2117 13:41:45.481041 TX_TRACKING: ON
2118 13:41:45.481136 [GetDramInforAfterCalByMRR] Vendor 6.
2119 13:41:45.481231 [GetDramInforAfterCalByMRR] Revision 606.
2120 13:41:45.481325 [GetDramInforAfterCalByMRR] Revision 2 0.
2121 13:41:45.481421 MR0 0x3b3b
2122 13:41:45.481516 MR8 0x5151
2123 13:41:45.481610 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 13:41:45.481704
2125 13:41:45.481798 MR0 0x3b3b
2126 13:41:45.481892 MR8 0x5151
2127 13:41:45.481985 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2128 13:41:45.482079
2129 13:41:45.482187 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2130 13:41:45.482285 [FAST_K] Save calibration result to emmc
2131 13:41:45.482382 [FAST_K] Save calibration result to emmc
2132 13:41:45.482476 dram_init: config_dvfs: 1
2133 13:41:45.482570 dramc_set_vcore_voltage set vcore to 662500
2134 13:41:45.482665 Read voltage for 1200, 2
2135 13:41:45.482758 Vio18 = 0
2136 13:41:45.482852 Vcore = 662500
2137 13:41:45.482947 Vdram = 0
2138 13:41:45.483041 Vddq = 0
2139 13:41:45.483135 Vmddr = 0
2140 13:41:45.483229 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2141 13:41:45.483323 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2142 13:41:45.483417 MEM_TYPE=3, freq_sel=15
2143 13:41:45.483511 sv_algorithm_assistance_LP4_1600
2144 13:41:45.483605 ============ PULL DRAM RESETB DOWN ============
2145 13:41:45.483699 ========== PULL DRAM RESETB DOWN end =========
2146 13:41:45.483794 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 13:41:45.483888 ===================================
2148 13:41:45.483986 LPDDR4 DRAM CONFIGURATION
2149 13:41:45.484094 ===================================
2150 13:41:45.484178 EX_ROW_EN[0] = 0x0
2151 13:41:45.484258 EX_ROW_EN[1] = 0x0
2152 13:41:45.484344 LP4Y_EN = 0x0
2153 13:41:45.484425 WORK_FSP = 0x0
2154 13:41:45.484508 WL = 0x4
2155 13:41:45.484590 RL = 0x4
2156 13:41:45.484671 BL = 0x2
2157 13:41:45.484750 RPST = 0x0
2158 13:41:45.484838 RD_PRE = 0x0
2159 13:41:45.484933 WR_PRE = 0x1
2160 13:41:45.485021 WR_PST = 0x0
2161 13:41:45.485109 DBI_WR = 0x0
2162 13:41:45.485195 DBI_RD = 0x0
2163 13:41:45.485280 OTF = 0x1
2164 13:41:45.485366 ===================================
2165 13:41:45.485451 ===================================
2166 13:41:45.485537 ANA top config
2167 13:41:45.485622 ===================================
2168 13:41:45.485707 DLL_ASYNC_EN = 0
2169 13:41:45.485792 ALL_SLAVE_EN = 0
2170 13:41:45.485877 NEW_RANK_MODE = 1
2171 13:41:45.485963 DLL_IDLE_MODE = 1
2172 13:41:45.486047 LP45_APHY_COMB_EN = 1
2173 13:41:45.486133 TX_ODT_DIS = 1
2174 13:41:45.486216 NEW_8X_MODE = 1
2175 13:41:45.486274 ===================================
2176 13:41:45.486330 ===================================
2177 13:41:45.486385 data_rate = 2400
2178 13:41:45.486440 CKR = 1
2179 13:41:45.486495 DQ_P2S_RATIO = 8
2180 13:41:45.486549 ===================================
2181 13:41:45.486603 CA_P2S_RATIO = 8
2182 13:41:45.486658 DQ_CA_OPEN = 0
2183 13:41:45.486712 DQ_SEMI_OPEN = 0
2184 13:41:45.486767 CA_SEMI_OPEN = 0
2185 13:41:45.486828 CA_FULL_RATE = 0
2186 13:41:45.486888 DQ_CKDIV4_EN = 0
2187 13:41:45.486974 CA_CKDIV4_EN = 0
2188 13:41:45.487065 CA_PREDIV_EN = 0
2189 13:41:45.487154 PH8_DLY = 17
2190 13:41:45.487243 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2191 13:41:45.487332 DQ_AAMCK_DIV = 4
2192 13:41:45.487422 CA_AAMCK_DIV = 4
2193 13:41:45.487516 CA_ADMCK_DIV = 4
2194 13:41:45.487605 DQ_TRACK_CA_EN = 0
2195 13:41:45.487694 CA_PICK = 1200
2196 13:41:45.487782 CA_MCKIO = 1200
2197 13:41:45.487870 MCKIO_SEMI = 0
2198 13:41:45.487960 PLL_FREQ = 2366
2199 13:41:45.488048 DQ_UI_PI_RATIO = 32
2200 13:41:45.488137 CA_UI_PI_RATIO = 0
2201 13:41:45.488225 ===================================
2202 13:41:45.488314 ===================================
2203 13:41:45.488404 memory_type:LPDDR4
2204 13:41:45.488493 GP_NUM : 10
2205 13:41:45.488580 SRAM_EN : 1
2206 13:41:45.488669 MD32_EN : 0
2207 13:41:45.488758 ===================================
2208 13:41:45.488846 [ANA_INIT] >>>>>>>>>>>>>>
2209 13:41:45.488931 <<<<<< [CONFIGURE PHASE]: ANA_TX
2210 13:41:45.489016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2211 13:41:45.489104 ===================================
2212 13:41:45.489188 data_rate = 2400,PCW = 0X5b00
2213 13:41:45.489273 ===================================
2214 13:41:45.489357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2215 13:41:45.489443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 13:41:45.489528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 13:41:45.489614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2218 13:41:45.489699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2219 13:41:45.490001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2220 13:41:45.490116 [ANA_INIT] flow start
2221 13:41:45.490235 [ANA_INIT] PLL >>>>>>>>
2222 13:41:45.490345 [ANA_INIT] PLL <<<<<<<<
2223 13:41:45.490454 [ANA_INIT] MIDPI >>>>>>>>
2224 13:41:45.490553 [ANA_INIT] MIDPI <<<<<<<<
2225 13:41:45.490649 [ANA_INIT] DLL >>>>>>>>
2226 13:41:45.490710 [ANA_INIT] DLL <<<<<<<<
2227 13:41:45.490767 [ANA_INIT] flow end
2228 13:41:45.490824 ============ LP4 DIFF to SE enter ============
2229 13:41:45.490880 ============ LP4 DIFF to SE exit ============
2230 13:41:45.490935 [ANA_INIT] <<<<<<<<<<<<<
2231 13:41:45.490990 [Flow] Enable top DCM control >>>>>
2232 13:41:45.491045 [Flow] Enable top DCM control <<<<<
2233 13:41:45.491099 Enable DLL master slave shuffle
2234 13:41:45.491153 ==============================================================
2235 13:41:45.491209 Gating Mode config
2236 13:41:45.491263 ==============================================================
2237 13:41:45.491317 Config description:
2238 13:41:45.491372 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2239 13:41:45.491428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2240 13:41:45.491484 SELPH_MODE 0: By rank 1: By Phase
2241 13:41:45.491539 ==============================================================
2242 13:41:45.491593 GAT_TRACK_EN = 1
2243 13:41:45.491648 RX_GATING_MODE = 2
2244 13:41:45.491702 RX_GATING_TRACK_MODE = 2
2245 13:41:45.491760 SELPH_MODE = 1
2246 13:41:45.491853 PICG_EARLY_EN = 1
2247 13:41:45.491948 VALID_LAT_VALUE = 1
2248 13:41:45.492026 ==============================================================
2249 13:41:45.492103 Enter into Gating configuration >>>>
2250 13:41:45.492198 Exit from Gating configuration <<<<
2251 13:41:45.492292 Enter into DVFS_PRE_config >>>>>
2252 13:41:45.492387 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2253 13:41:45.492482 Exit from DVFS_PRE_config <<<<<
2254 13:41:45.492577 Enter into PICG configuration >>>>
2255 13:41:45.492671 Exit from PICG configuration <<<<
2256 13:41:45.492765 [RX_INPUT] configuration >>>>>
2257 13:41:45.492859 [RX_INPUT] configuration <<<<<
2258 13:41:45.492953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2259 13:41:45.493048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2260 13:41:45.493143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 13:41:45.493238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 13:41:45.493332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 13:41:45.493430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 13:41:45.493525 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2265 13:41:45.493619 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2266 13:41:45.493714 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2267 13:41:45.493809 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2268 13:41:45.493904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2269 13:41:45.493998 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 13:41:45.494092 ===================================
2271 13:41:45.494200 LPDDR4 DRAM CONFIGURATION
2272 13:41:45.494297 ===================================
2273 13:41:45.494392 EX_ROW_EN[0] = 0x0
2274 13:41:45.494487 EX_ROW_EN[1] = 0x0
2275 13:41:45.494582 LP4Y_EN = 0x0
2276 13:41:45.494676 WORK_FSP = 0x0
2277 13:41:45.494770 WL = 0x4
2278 13:41:45.494864 RL = 0x4
2279 13:41:45.494958 BL = 0x2
2280 13:41:45.495052 RPST = 0x0
2281 13:41:45.495145 RD_PRE = 0x0
2282 13:41:45.495238 WR_PRE = 0x1
2283 13:41:45.495333 WR_PST = 0x0
2284 13:41:45.495427 DBI_WR = 0x0
2285 13:41:45.495521 DBI_RD = 0x0
2286 13:41:45.495617 OTF = 0x1
2287 13:41:45.495704 ===================================
2288 13:41:45.495790 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2289 13:41:45.495876 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2290 13:41:45.495961 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 13:41:45.496046 ===================================
2292 13:41:45.496131 LPDDR4 DRAM CONFIGURATION
2293 13:41:45.496216 ===================================
2294 13:41:45.496300 EX_ROW_EN[0] = 0x10
2295 13:41:45.496384 EX_ROW_EN[1] = 0x0
2296 13:41:45.496467 LP4Y_EN = 0x0
2297 13:41:45.496551 WORK_FSP = 0x0
2298 13:41:45.496635 WL = 0x4
2299 13:41:45.496719 RL = 0x4
2300 13:41:45.496802 BL = 0x2
2301 13:41:45.496886 RPST = 0x0
2302 13:41:45.496970 RD_PRE = 0x0
2303 13:41:45.497053 WR_PRE = 0x1
2304 13:41:45.497137 WR_PST = 0x0
2305 13:41:45.497220 DBI_WR = 0x0
2306 13:41:45.497304 DBI_RD = 0x0
2307 13:41:45.497387 OTF = 0x1
2308 13:41:45.497472 ===================================
2309 13:41:45.497557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2310 13:41:45.497641 ==
2311 13:41:45.497725 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 13:41:45.497810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2313 13:41:45.497895 ==
2314 13:41:45.497979 [Duty_Offset_Calibration]
2315 13:41:45.498062 B0:1 B1:-1 CA:0
2316 13:41:45.498145
2317 13:41:45.498244 [DutyScan_Calibration_Flow] k_type=0
2318 13:41:45.498328
2319 13:41:45.498412 ==CLK 0==
2320 13:41:45.498496 Final CLK duty delay cell = 0
2321 13:41:45.498581 [0] MAX Duty = 5094%(X100), DQS PI = 16
2322 13:41:45.498670 [0] MIN Duty = 4875%(X100), DQS PI = 8
2323 13:41:45.498765 [0] AVG Duty = 4984%(X100)
2324 13:41:45.498849
2325 13:41:45.498933 CH0 CLK Duty spec in!! Max-Min= 219%
2326 13:41:45.499018 [DutyScan_Calibration_Flow] ====Done====
2327 13:41:45.499101
2328 13:41:45.499185 [DutyScan_Calibration_Flow] k_type=1
2329 13:41:45.499269
2330 13:41:45.499352 ==DQS 0 ==
2331 13:41:45.499437 Final DQS duty delay cell = -4
2332 13:41:45.499521 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2333 13:41:45.499612 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2334 13:41:45.499701 [-4] AVG Duty = 4968%(X100)
2335 13:41:45.499784
2336 13:41:45.499868 ==DQS 1 ==
2337 13:41:45.499954 Final DQS duty delay cell = 0
2338 13:41:45.500254 [0] MAX Duty = 5124%(X100), DQS PI = 6
2339 13:41:45.500344 [0] MIN Duty = 5000%(X100), DQS PI = 20
2340 13:41:45.500431 [0] AVG Duty = 5062%(X100)
2341 13:41:45.500518
2342 13:41:45.500621 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2343 13:41:45.500709
2344 13:41:45.500791 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2345 13:41:45.500873 [DutyScan_Calibration_Flow] ====Done====
2346 13:41:45.500957
2347 13:41:45.501023 [DutyScan_Calibration_Flow] k_type=3
2348 13:41:45.501079
2349 13:41:45.501135 ==DQM 0 ==
2350 13:41:45.501190 Final DQM duty delay cell = 0
2351 13:41:45.501245 [0] MAX Duty = 5062%(X100), DQS PI = 16
2352 13:41:45.501299 [0] MIN Duty = 4875%(X100), DQS PI = 8
2353 13:41:45.501354 [0] AVG Duty = 4968%(X100)
2354 13:41:45.501408
2355 13:41:45.501461 ==DQM 1 ==
2356 13:41:45.501515 Final DQM duty delay cell = 4
2357 13:41:45.501570 [4] MAX Duty = 5187%(X100), DQS PI = 16
2358 13:41:45.501624 [4] MIN Duty = 4969%(X100), DQS PI = 26
2359 13:41:45.501678 [4] AVG Duty = 5078%(X100)
2360 13:41:45.501731
2361 13:41:45.501785 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2362 13:41:45.501839
2363 13:41:45.501892 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2364 13:41:45.501946 [DutyScan_Calibration_Flow] ====Done====
2365 13:41:45.502000
2366 13:41:45.502053 [DutyScan_Calibration_Flow] k_type=2
2367 13:41:45.502107
2368 13:41:45.502170 ==DQ 0 ==
2369 13:41:45.502227 Final DQ duty delay cell = -4
2370 13:41:45.502282 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2371 13:41:45.502337 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2372 13:41:45.502390 [-4] AVG Duty = 4969%(X100)
2373 13:41:45.502444
2374 13:41:45.502497 ==DQ 1 ==
2375 13:41:45.502577 Final DQ duty delay cell = -4
2376 13:41:45.502637 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2377 13:41:45.502692 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2378 13:41:45.502746 [-4] AVG Duty = 4922%(X100)
2379 13:41:45.502801
2380 13:41:45.502855 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2381 13:41:45.502909
2382 13:41:45.502962 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2383 13:41:45.503016 [DutyScan_Calibration_Flow] ====Done====
2384 13:41:45.503074 ==
2385 13:41:45.503145 Dram Type= 6, Freq= 0, CH_1, rank 0
2386 13:41:45.503237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 13:41:45.503337 ==
2388 13:41:45.503395 [Duty_Offset_Calibration]
2389 13:41:45.503449 B0:-1 B1:1 CA:1
2390 13:41:45.503504
2391 13:41:45.503558 [DutyScan_Calibration_Flow] k_type=0
2392 13:41:45.503611
2393 13:41:45.503665 ==CLK 0==
2394 13:41:45.503719 Final CLK duty delay cell = 0
2395 13:41:45.503773 [0] MAX Duty = 5156%(X100), DQS PI = 22
2396 13:41:45.503835 [0] MIN Duty = 4969%(X100), DQS PI = 62
2397 13:41:45.503924 [0] AVG Duty = 5062%(X100)
2398 13:41:45.504013
2399 13:41:45.504111 CH1 CLK Duty spec in!! Max-Min= 187%
2400 13:41:45.504215 [DutyScan_Calibration_Flow] ====Done====
2401 13:41:45.504307
2402 13:41:45.504397 [DutyScan_Calibration_Flow] k_type=1
2403 13:41:45.504485
2404 13:41:45.504574 ==DQS 0 ==
2405 13:41:45.504665 Final DQS duty delay cell = 0
2406 13:41:45.504756 [0] MAX Duty = 5125%(X100), DQS PI = 48
2407 13:41:45.504845 [0] MIN Duty = 4875%(X100), DQS PI = 6
2408 13:41:45.504933 [0] AVG Duty = 5000%(X100)
2409 13:41:45.505017
2410 13:41:45.505103 ==DQS 1 ==
2411 13:41:45.505190 Final DQS duty delay cell = 0
2412 13:41:45.505278 [0] MAX Duty = 5062%(X100), DQS PI = 10
2413 13:41:45.505360 [0] MIN Duty = 4969%(X100), DQS PI = 56
2414 13:41:45.505441 [0] AVG Duty = 5015%(X100)
2415 13:41:45.505525
2416 13:41:45.505616 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2417 13:41:45.505702
2418 13:41:45.505790 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2419 13:41:45.505888 [DutyScan_Calibration_Flow] ====Done====
2420 13:41:45.505978
2421 13:41:45.506069 [DutyScan_Calibration_Flow] k_type=3
2422 13:41:45.506171
2423 13:41:45.506264 ==DQM 0 ==
2424 13:41:45.506359 Final DQM duty delay cell = -4
2425 13:41:45.506450 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2426 13:41:45.506543 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2427 13:41:45.506649 [-4] AVG Duty = 4937%(X100)
2428 13:41:45.506739
2429 13:41:45.506817 ==DQM 1 ==
2430 13:41:45.506894 Final DQM duty delay cell = 0
2431 13:41:45.506969 [0] MAX Duty = 5125%(X100), DQS PI = 2
2432 13:41:45.507050 [0] MIN Duty = 4969%(X100), DQS PI = 28
2433 13:41:45.507157 [0] AVG Duty = 5047%(X100)
2434 13:41:45.507250
2435 13:41:45.507338 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2436 13:41:45.507425
2437 13:41:45.507511 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2438 13:41:45.507597 [DutyScan_Calibration_Flow] ====Done====
2439 13:41:45.507682
2440 13:41:45.507767 [DutyScan_Calibration_Flow] k_type=2
2441 13:41:45.507851
2442 13:41:45.507935 ==DQ 0 ==
2443 13:41:45.508019 Final DQ duty delay cell = 0
2444 13:41:45.508104 [0] MAX Duty = 5156%(X100), DQS PI = 28
2445 13:41:45.508189 [0] MIN Duty = 4907%(X100), DQS PI = 6
2446 13:41:45.508273 [0] AVG Duty = 5031%(X100)
2447 13:41:45.508356
2448 13:41:45.508443 ==DQ 1 ==
2449 13:41:45.508528 Final DQ duty delay cell = 0
2450 13:41:45.508613 [0] MAX Duty = 5124%(X100), DQS PI = 8
2451 13:41:45.508697 [0] MIN Duty = 4969%(X100), DQS PI = 0
2452 13:41:45.508781 [0] AVG Duty = 5046%(X100)
2453 13:41:45.508871
2454 13:41:45.508959 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2455 13:41:45.509050
2456 13:41:45.509145 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2457 13:41:45.509230 [DutyScan_Calibration_Flow] ====Done====
2458 13:41:45.509315 nWR fixed to 30
2459 13:41:45.509400 [ModeRegInit_LP4] CH0 RK0
2460 13:41:45.509484 [ModeRegInit_LP4] CH0 RK1
2461 13:41:45.509568 [ModeRegInit_LP4] CH1 RK0
2462 13:41:45.509651 [ModeRegInit_LP4] CH1 RK1
2463 13:41:45.509735 match AC timing 7
2464 13:41:45.509821 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2465 13:41:45.509906 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2466 13:41:45.509992 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2467 13:41:45.510086 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2468 13:41:45.510181 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2469 13:41:45.510240 ==
2470 13:41:45.510295 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 13:41:45.510351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 13:41:45.510406 ==
2473 13:41:45.510460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 13:41:45.510515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2475 13:41:45.510571 [CA 0] Center 39 (9~70) winsize 62
2476 13:41:45.510625 [CA 1] Center 39 (9~69) winsize 61
2477 13:41:45.510680 [CA 2] Center 35 (5~66) winsize 62
2478 13:41:45.510735 [CA 3] Center 35 (5~66) winsize 62
2479 13:41:45.510789 [CA 4] Center 33 (4~63) winsize 60
2480 13:41:45.510842 [CA 5] Center 33 (3~63) winsize 61
2481 13:41:45.510896
2482 13:41:45.510973 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2483 13:41:45.511040
2484 13:41:45.511095 [CATrainingPosCal] consider 1 rank data
2485 13:41:45.511150 u2DelayCellTimex100 = 270/100 ps
2486 13:41:45.511205 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2487 13:41:45.511275 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2488 13:41:45.511388 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 13:41:45.511672 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 13:41:45.511738 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2491 13:41:45.511796 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2492 13:41:45.511853
2493 13:41:45.511907 CA PerBit enable=1, Macro0, CA PI delay=33
2494 13:41:45.511962
2495 13:41:45.512016 [CBTSetCACLKResult] CA Dly = 33
2496 13:41:45.512070 CS Dly: 8 (0~39)
2497 13:41:45.512124 ==
2498 13:41:45.512179 Dram Type= 6, Freq= 0, CH_0, rank 1
2499 13:41:45.512233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 13:41:45.512288 ==
2501 13:41:45.512342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2502 13:41:45.512432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2503 13:41:45.512492 [CA 0] Center 39 (9~70) winsize 62
2504 13:41:45.512547 [CA 1] Center 39 (9~70) winsize 62
2505 13:41:45.512601 [CA 2] Center 35 (5~66) winsize 62
2506 13:41:45.512656 [CA 3] Center 34 (4~65) winsize 62
2507 13:41:45.512710 [CA 4] Center 33 (3~64) winsize 62
2508 13:41:45.512764 [CA 5] Center 33 (3~63) winsize 61
2509 13:41:45.512835
2510 13:41:45.512922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2511 13:41:45.513012
2512 13:41:45.513097 [CATrainingPosCal] consider 2 rank data
2513 13:41:45.513178 u2DelayCellTimex100 = 270/100 ps
2514 13:41:45.513258 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 13:41:45.513340 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2516 13:41:45.513414 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2517 13:41:45.513471 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2518 13:41:45.513526 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2519 13:41:45.513581 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2520 13:41:45.513636
2521 13:41:45.513689 CA PerBit enable=1, Macro0, CA PI delay=33
2522 13:41:45.513744
2523 13:41:45.513796 [CBTSetCACLKResult] CA Dly = 33
2524 13:41:45.513850 CS Dly: 9 (0~41)
2525 13:41:45.513905
2526 13:41:45.513958 ----->DramcWriteLeveling(PI) begin...
2527 13:41:45.514029 ==
2528 13:41:45.514118 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 13:41:45.514222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 13:41:45.514313 ==
2531 13:41:45.514374 Write leveling (Byte 0): 33 => 33
2532 13:41:45.514431 Write leveling (Byte 1): 29 => 29
2533 13:41:45.514487 DramcWriteLeveling(PI) end<-----
2534 13:41:45.514543
2535 13:41:45.514597 ==
2536 13:41:45.514652 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 13:41:45.514724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 13:41:45.514804 ==
2539 13:41:45.514862 [Gating] SW mode calibration
2540 13:41:45.514918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2541 13:41:45.514974 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2542 13:41:45.515030 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2543 13:41:45.515087 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2544 13:41:45.515142 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
2545 13:41:45.515196 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 13:41:45.515250 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 13:41:45.515304 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 13:41:45.515358 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 13:41:45.515412 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
2550 13:41:45.515466 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2551 13:41:45.515520 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2552 13:41:45.515574 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 13:41:45.515628 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 13:41:45.515683 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 13:41:45.515765 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 13:41:45.515826 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 13:41:45.515880 1 0 28 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2558 13:41:45.515935 1 1 0 | B1->B0 | 2323 4444 | 1 0 | (0 0) (0 0)
2559 13:41:45.515989 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2560 13:41:45.516043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 13:41:45.516097 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 13:41:45.516151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 13:41:45.516236 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 13:41:45.516330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 13:41:45.516422 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2566 13:41:45.516484 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2567 13:41:45.516539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2568 13:41:45.516595 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:41:45.516650 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:41:45.516704 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:41:45.516758 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:41:45.516816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:41:45.516901 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:41:45.516987 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 13:41:45.517074 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 13:41:45.517158 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 13:41:45.517240 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 13:41:45.517321 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 13:41:45.517406 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 13:41:45.517466 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 13:41:45.517521 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2582 13:41:45.517577 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2583 13:41:45.517631 Total UI for P1: 0, mck2ui 16
2584 13:41:45.517686 best dqsien dly found for B0: ( 1, 3, 26)
2585 13:41:45.517741 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2586 13:41:45.517796 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 13:41:45.517850 Total UI for P1: 0, mck2ui 16
2588 13:41:45.517905 best dqsien dly found for B1: ( 1, 4, 2)
2589 13:41:45.517959 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2590 13:41:45.518013 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2591 13:41:45.518066
2592 13:41:45.518332 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2593 13:41:45.518396 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2594 13:41:45.518452 [Gating] SW calibration Done
2595 13:41:45.518508 ==
2596 13:41:45.518563 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 13:41:45.518618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 13:41:45.518674 ==
2599 13:41:45.518750 RX Vref Scan: 0
2600 13:41:45.518806
2601 13:41:45.518860 RX Vref 0 -> 0, step: 1
2602 13:41:45.518914
2603 13:41:45.518967 RX Delay -40 -> 252, step: 8
2604 13:41:45.519030 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2605 13:41:45.519111 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2606 13:41:45.519168 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2607 13:41:45.519223 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2608 13:41:45.519277 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2609 13:41:45.519331 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2610 13:41:45.519385 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2611 13:41:45.519439 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2612 13:41:45.519493 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2613 13:41:45.519549 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2614 13:41:45.519623 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2615 13:41:45.519679 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2616 13:41:45.519734 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2617 13:41:45.519788 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2618 13:41:45.519841 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2619 13:41:45.519895 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2620 13:41:45.519949 ==
2621 13:41:45.520004 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 13:41:45.520058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 13:41:45.520112 ==
2624 13:41:45.520170 DQS Delay:
2625 13:41:45.520255 DQS0 = 0, DQS1 = 0
2626 13:41:45.520346 DQM Delay:
2627 13:41:45.520426 DQM0 = 119, DQM1 = 107
2628 13:41:45.520483 DQ Delay:
2629 13:41:45.520538 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2630 13:41:45.520593 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2631 13:41:45.520647 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2632 13:41:45.520701 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2633 13:41:45.520754
2634 13:41:45.520817
2635 13:41:45.520905 ==
2636 13:41:45.520994 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 13:41:45.521080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 13:41:45.521162 ==
2639 13:41:45.521242
2640 13:41:45.521321
2641 13:41:45.521396 TX Vref Scan disable
2642 13:41:45.521453 == TX Byte 0 ==
2643 13:41:45.521509 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2644 13:41:45.521565 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2645 13:41:45.521620 == TX Byte 1 ==
2646 13:41:45.521674 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2647 13:41:45.521728 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2648 13:41:45.521782 ==
2649 13:41:45.521836 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 13:41:45.521891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 13:41:45.521945 ==
2652 13:41:45.521999 TX Vref=22, minBit 5, minWin=25, winSum=415
2653 13:41:45.522054 TX Vref=24, minBit 0, minWin=26, winSum=423
2654 13:41:45.522110 TX Vref=26, minBit 8, minWin=26, winSum=430
2655 13:41:45.522182 TX Vref=28, minBit 5, minWin=26, winSum=432
2656 13:41:45.522241 TX Vref=30, minBit 4, minWin=26, winSum=433
2657 13:41:45.522331 TX Vref=32, minBit 4, minWin=26, winSum=434
2658 13:41:45.522389 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 32
2659 13:41:45.522445
2660 13:41:45.522499 Final TX Range 1 Vref 32
2661 13:41:45.522553
2662 13:41:45.522608 ==
2663 13:41:45.522661 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 13:41:45.522716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 13:41:45.522771 ==
2666 13:41:45.522825
2667 13:41:45.522878
2668 13:41:45.522932 TX Vref Scan disable
2669 13:41:45.522986 == TX Byte 0 ==
2670 13:41:45.523040 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2671 13:41:45.523095 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2672 13:41:45.523149 == TX Byte 1 ==
2673 13:41:45.523203 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2674 13:41:45.523258 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2675 13:41:45.523312
2676 13:41:45.523398 [DATLAT]
2677 13:41:45.523456 Freq=1200, CH0 RK0
2678 13:41:45.523536
2679 13:41:45.523593 DATLAT Default: 0xd
2680 13:41:45.523647 0, 0xFFFF, sum = 0
2681 13:41:45.523704 1, 0xFFFF, sum = 0
2682 13:41:45.523759 2, 0xFFFF, sum = 0
2683 13:41:45.523814 3, 0xFFFF, sum = 0
2684 13:41:45.523869 4, 0xFFFF, sum = 0
2685 13:41:45.523924 5, 0xFFFF, sum = 0
2686 13:41:45.523979 6, 0xFFFF, sum = 0
2687 13:41:45.524034 7, 0xFFFF, sum = 0
2688 13:41:45.524088 8, 0xFFFF, sum = 0
2689 13:41:45.524143 9, 0xFFFF, sum = 0
2690 13:41:45.524198 10, 0xFFFF, sum = 0
2691 13:41:45.524253 11, 0xFFFF, sum = 0
2692 13:41:45.524307 12, 0x0, sum = 1
2693 13:41:45.524362 13, 0x0, sum = 2
2694 13:41:45.524417 14, 0x0, sum = 3
2695 13:41:45.524471 15, 0x0, sum = 4
2696 13:41:45.524525 best_step = 13
2697 13:41:45.524580
2698 13:41:45.524633 ==
2699 13:41:45.524687 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 13:41:45.524767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 13:41:45.524853 ==
2702 13:41:45.524941 RX Vref Scan: 1
2703 13:41:45.525024
2704 13:41:45.525104 Set Vref Range= 32 -> 127
2705 13:41:45.525184
2706 13:41:45.525269 RX Vref 32 -> 127, step: 1
2707 13:41:45.525330
2708 13:41:45.525386 RX Delay -21 -> 252, step: 4
2709 13:41:45.525441
2710 13:41:45.525495 Set Vref, RX VrefLevel [Byte0]: 32
2711 13:41:45.525550 [Byte1]: 32
2712 13:41:45.525604
2713 13:41:45.525658 Set Vref, RX VrefLevel [Byte0]: 33
2714 13:41:45.525718 [Byte1]: 33
2715 13:41:45.525797
2716 13:41:45.525852 Set Vref, RX VrefLevel [Byte0]: 34
2717 13:41:45.525908 [Byte1]: 34
2718 13:41:45.525962
2719 13:41:45.526016 Set Vref, RX VrefLevel [Byte0]: 35
2720 13:41:45.526070 [Byte1]: 35
2721 13:41:45.526124
2722 13:41:45.526191 Set Vref, RX VrefLevel [Byte0]: 36
2723 13:41:45.526251 [Byte1]: 36
2724 13:41:45.526305
2725 13:41:45.526359 Set Vref, RX VrefLevel [Byte0]: 37
2726 13:41:45.526413 [Byte1]: 37
2727 13:41:45.526467
2728 13:41:45.526521 Set Vref, RX VrefLevel [Byte0]: 38
2729 13:41:45.526575 [Byte1]: 38
2730 13:41:45.526628
2731 13:41:45.526682 Set Vref, RX VrefLevel [Byte0]: 39
2732 13:41:45.526735 [Byte1]: 39
2733 13:41:45.526788
2734 13:41:45.526841 Set Vref, RX VrefLevel [Byte0]: 40
2735 13:41:45.526895 [Byte1]: 40
2736 13:41:45.526949
2737 13:41:45.527002 Set Vref, RX VrefLevel [Byte0]: 41
2738 13:41:45.527056 [Byte1]: 41
2739 13:41:45.527109
2740 13:41:45.527163 Set Vref, RX VrefLevel [Byte0]: 42
2741 13:41:45.527217 [Byte1]: 42
2742 13:41:45.527271
2743 13:41:45.527324 Set Vref, RX VrefLevel [Byte0]: 43
2744 13:41:45.527402 [Byte1]: 43
2745 13:41:45.527459
2746 13:41:45.527513 Set Vref, RX VrefLevel [Byte0]: 44
2747 13:41:45.527568 [Byte1]: 44
2748 13:41:45.527622
2749 13:41:45.527885 Set Vref, RX VrefLevel [Byte0]: 45
2750 13:41:45.527946 [Byte1]: 45
2751 13:41:45.528002
2752 13:41:45.528055 Set Vref, RX VrefLevel [Byte0]: 46
2753 13:41:45.528109 [Byte1]: 46
2754 13:41:45.528163
2755 13:41:45.528217 Set Vref, RX VrefLevel [Byte0]: 47
2756 13:41:45.528271 [Byte1]: 47
2757 13:41:45.528325
2758 13:41:45.528379 Set Vref, RX VrefLevel [Byte0]: 48
2759 13:41:45.528432 [Byte1]: 48
2760 13:41:45.528486
2761 13:41:45.528539 Set Vref, RX VrefLevel [Byte0]: 49
2762 13:41:45.528593 [Byte1]: 49
2763 13:41:45.528647
2764 13:41:45.528707 Set Vref, RX VrefLevel [Byte0]: 50
2765 13:41:45.528797 [Byte1]: 50
2766 13:41:45.528885
2767 13:41:45.528970 Set Vref, RX VrefLevel [Byte0]: 51
2768 13:41:45.529051 [Byte1]: 51
2769 13:41:45.529131
2770 13:41:45.529210 Set Vref, RX VrefLevel [Byte0]: 52
2771 13:41:45.529307 [Byte1]: 52
2772 13:41:45.529370
2773 13:41:45.529426 Set Vref, RX VrefLevel [Byte0]: 53
2774 13:41:45.529481 [Byte1]: 53
2775 13:41:45.529536
2776 13:41:45.529590 Set Vref, RX VrefLevel [Byte0]: 54
2777 13:41:45.529644 [Byte1]: 54
2778 13:41:45.529699
2779 13:41:45.529753 Set Vref, RX VrefLevel [Byte0]: 55
2780 13:41:45.529807 [Byte1]: 55
2781 13:41:45.529862
2782 13:41:45.529915 Set Vref, RX VrefLevel [Byte0]: 56
2783 13:41:45.529971 [Byte1]: 56
2784 13:41:45.530025
2785 13:41:45.530078 Set Vref, RX VrefLevel [Byte0]: 57
2786 13:41:45.530131 [Byte1]: 57
2787 13:41:45.530200
2788 13:41:45.530256 Set Vref, RX VrefLevel [Byte0]: 58
2789 13:41:45.530311 [Byte1]: 58
2790 13:41:45.530364
2791 13:41:45.530418 Set Vref, RX VrefLevel [Byte0]: 59
2792 13:41:45.530472 [Byte1]: 59
2793 13:41:45.530525
2794 13:41:45.530579 Set Vref, RX VrefLevel [Byte0]: 60
2795 13:41:45.530633 [Byte1]: 60
2796 13:41:45.530686
2797 13:41:45.530740 Set Vref, RX VrefLevel [Byte0]: 61
2798 13:41:45.530793 [Byte1]: 61
2799 13:41:45.530846
2800 13:41:45.530900 Set Vref, RX VrefLevel [Byte0]: 62
2801 13:41:45.530954 [Byte1]: 62
2802 13:41:45.531007
2803 13:41:45.531061 Set Vref, RX VrefLevel [Byte0]: 63
2804 13:41:45.531114 [Byte1]: 63
2805 13:41:45.531167
2806 13:41:45.531220 Set Vref, RX VrefLevel [Byte0]: 64
2807 13:41:45.531274 [Byte1]: 64
2808 13:41:45.531329
2809 13:41:45.531382 Set Vref, RX VrefLevel [Byte0]: 65
2810 13:41:45.531436 [Byte1]: 65
2811 13:41:45.531490
2812 13:41:45.531544 Set Vref, RX VrefLevel [Byte0]: 66
2813 13:41:45.531598 [Byte1]: 66
2814 13:41:45.531652
2815 13:41:45.531712 Set Vref, RX VrefLevel [Byte0]: 67
2816 13:41:45.531780 [Byte1]: 67
2817 13:41:45.531836
2818 13:41:45.531890 Set Vref, RX VrefLevel [Byte0]: 68
2819 13:41:45.531944 [Byte1]: 68
2820 13:41:45.531998
2821 13:41:45.532051 Set Vref, RX VrefLevel [Byte0]: 69
2822 13:41:45.532104 [Byte1]: 69
2823 13:41:45.532158
2824 13:41:45.532211 Set Vref, RX VrefLevel [Byte0]: 70
2825 13:41:45.532266 [Byte1]: 70
2826 13:41:45.532320
2827 13:41:45.532374 Set Vref, RX VrefLevel [Byte0]: 71
2828 13:41:45.532427 [Byte1]: 71
2829 13:41:45.532481
2830 13:41:45.532556 Set Vref, RX VrefLevel [Byte0]: 72
2831 13:41:45.532642 [Byte1]: 72
2832 13:41:45.532730
2833 13:41:45.532811 Set Vref, RX VrefLevel [Byte0]: 73
2834 13:41:45.532892 [Byte1]: 73
2835 13:41:45.532972
2836 13:41:45.533057 Set Vref, RX VrefLevel [Byte0]: 74
2837 13:41:45.533118 [Byte1]: 74
2838 13:41:45.533202
2839 13:41:45.533299 Set Vref, RX VrefLevel [Byte0]: 75
2840 13:41:45.533390 [Byte1]: 75
2841 13:41:45.533451
2842 13:41:45.533508 Set Vref, RX VrefLevel [Byte0]: 76
2843 13:41:45.533564 [Byte1]: 76
2844 13:41:45.533619
2845 13:41:45.533673 Set Vref, RX VrefLevel [Byte0]: 77
2846 13:41:45.533728 [Byte1]: 77
2847 13:41:45.533782
2848 13:41:45.533836 Final RX Vref Byte 0 = 60 to rank0
2849 13:41:45.533891 Final RX Vref Byte 1 = 50 to rank0
2850 13:41:45.533945 Final RX Vref Byte 0 = 60 to rank1
2851 13:41:45.533999 Final RX Vref Byte 1 = 50 to rank1==
2852 13:41:45.534053 Dram Type= 6, Freq= 0, CH_0, rank 0
2853 13:41:45.534107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 13:41:45.534167 ==
2855 13:41:45.534230 DQS Delay:
2856 13:41:45.534284 DQS0 = 0, DQS1 = 0
2857 13:41:45.534338 DQM Delay:
2858 13:41:45.534392 DQM0 = 118, DQM1 = 107
2859 13:41:45.534447 DQ Delay:
2860 13:41:45.534501 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =114
2861 13:41:45.534554 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =124
2862 13:41:45.534607 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2863 13:41:45.534662 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2864 13:41:45.534715
2865 13:41:45.534768
2866 13:41:45.534822 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
2867 13:41:45.534887 CH0 RK0: MR19=403, MR18=10FB
2868 13:41:45.534979 CH0_RK0: MR19=0x403, MR18=0x10FB, DQSOSC=403, MR23=63, INC=40, DEC=26
2869 13:41:45.535052
2870 13:41:45.535108 ----->DramcWriteLeveling(PI) begin...
2871 13:41:45.535164 ==
2872 13:41:45.535218 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 13:41:45.535272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 13:41:45.535327 ==
2875 13:41:45.535381 Write leveling (Byte 0): 32 => 32
2876 13:41:45.535435 Write leveling (Byte 1): 29 => 29
2877 13:41:45.535489 DramcWriteLeveling(PI) end<-----
2878 13:41:45.535543
2879 13:41:45.535626 ==
2880 13:41:45.535706 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 13:41:45.535763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 13:41:45.535818 ==
2883 13:41:45.535872 [Gating] SW mode calibration
2884 13:41:45.535926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2885 13:41:45.535981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2886 13:41:45.536035 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2887 13:41:45.536089 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2888 13:41:45.536144 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 13:41:45.536198 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 13:41:45.536252 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 13:41:45.536307 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 13:41:45.536390 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 13:41:45.536475 0 15 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2894 13:41:45.536786 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2895 13:41:45.536881 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 13:41:45.536968 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 13:41:45.537029 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 13:41:45.537087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 13:41:45.537144 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 13:41:45.537200 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 13:41:45.537255 1 0 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
2902 13:41:45.537309 1 1 0 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
2903 13:41:45.537365 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 13:41:45.537419 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 13:41:45.537473 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 13:41:45.537528 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 13:41:45.537582 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 13:41:45.537636 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2909 13:41:45.537690 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2910 13:41:45.537744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 13:41:45.537798 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 13:41:45.537852 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 13:41:45.537905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 13:41:45.537959 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:41:45.538012 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:41:45.538065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:41:45.538118 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:41:45.538185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:41:45.538241 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:41:45.538295 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:41:45.538348 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:41:45.538402 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:41:45.538455 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:41:45.538508 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2925 13:41:45.538562 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2926 13:41:45.538616 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 13:41:45.538669 Total UI for P1: 0, mck2ui 16
2928 13:41:45.538724 best dqsien dly found for B0: ( 1, 3, 26)
2929 13:41:45.538777 Total UI for P1: 0, mck2ui 16
2930 13:41:45.538832 best dqsien dly found for B1: ( 1, 3, 30)
2931 13:41:45.538885 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2932 13:41:45.538939 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2933 13:41:45.538993
2934 13:41:45.539046 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2935 13:41:45.539100 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2936 13:41:45.539154 [Gating] SW calibration Done
2937 13:41:45.539208 ==
2938 13:41:46.748519 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 13:41:46.748661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 13:41:46.748727 ==
2941 13:41:46.748818 RX Vref Scan: 0
2942 13:41:46.748875
2943 13:41:46.748931 RX Vref 0 -> 0, step: 1
2944 13:41:46.748987
2945 13:41:46.749041 RX Delay -40 -> 252, step: 8
2946 13:41:46.749095 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2947 13:41:46.749149 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2948 13:41:46.749204 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2949 13:41:46.749257 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2950 13:41:46.749310 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2951 13:41:46.749363 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2952 13:41:46.749416 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2953 13:41:46.749469 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2954 13:41:46.749521 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2955 13:41:46.749574 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2956 13:41:46.749626 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2957 13:41:46.749679 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2958 13:41:46.749731 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2959 13:41:46.749784 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2960 13:41:46.749836 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2961 13:41:46.749888 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2962 13:41:46.749940 ==
2963 13:41:46.749991 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 13:41:46.750044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 13:41:46.750097 ==
2966 13:41:46.750149 DQS Delay:
2967 13:41:46.750242 DQS0 = 0, DQS1 = 0
2968 13:41:46.750295 DQM Delay:
2969 13:41:46.750349 DQM0 = 116, DQM1 = 108
2970 13:41:46.750401 DQ Delay:
2971 13:41:46.750453 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2972 13:41:46.750505 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2973 13:41:46.750558 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2974 13:41:46.750610 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2975 13:41:46.750662
2976 13:41:46.750714
2977 13:41:46.750766 ==
2978 13:41:46.750818 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 13:41:46.750871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 13:41:46.750923 ==
2981 13:41:46.750975
2982 13:41:46.751026
2983 13:41:46.751078 TX Vref Scan disable
2984 13:41:46.751130 == TX Byte 0 ==
2985 13:41:46.751181 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 13:41:46.751234 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 13:41:46.751286 == TX Byte 1 ==
2988 13:41:46.751338 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2989 13:41:46.751390 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2990 13:41:46.751442 ==
2991 13:41:46.751494 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 13:41:46.751547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 13:41:46.751599 ==
2994 13:41:46.751651 TX Vref=22, minBit 3, minWin=25, winSum=423
2995 13:41:46.751705 TX Vref=24, minBit 5, minWin=25, winSum=427
2996 13:41:46.751758 TX Vref=26, minBit 2, minWin=26, winSum=431
2997 13:41:46.751810 TX Vref=28, minBit 1, minWin=26, winSum=434
2998 13:41:46.751863 TX Vref=30, minBit 12, minWin=26, winSum=434
2999 13:41:46.751915 TX Vref=32, minBit 13, minWin=26, winSum=432
3000 13:41:46.751967 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
3001 13:41:46.752020
3002 13:41:46.752072 Final TX Range 1 Vref 28
3003 13:41:46.752124
3004 13:41:46.752382 ==
3005 13:41:46.752441 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 13:41:46.752496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 13:41:46.752550 ==
3008 13:41:46.752603
3009 13:41:46.752655
3010 13:41:46.752707 TX Vref Scan disable
3011 13:41:46.752759 == TX Byte 0 ==
3012 13:41:46.752812 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3013 13:41:46.752865 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3014 13:41:46.752918 == TX Byte 1 ==
3015 13:41:46.752970 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3016 13:41:46.753023 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3017 13:41:46.753075
3018 13:41:46.753127 [DATLAT]
3019 13:41:46.753179 Freq=1200, CH0 RK1
3020 13:41:46.753232
3021 13:41:46.753284 DATLAT Default: 0xd
3022 13:41:46.753336 0, 0xFFFF, sum = 0
3023 13:41:46.753389 1, 0xFFFF, sum = 0
3024 13:41:46.753441 2, 0xFFFF, sum = 0
3025 13:41:46.753494 3, 0xFFFF, sum = 0
3026 13:41:46.753547 4, 0xFFFF, sum = 0
3027 13:41:46.753600 5, 0xFFFF, sum = 0
3028 13:41:46.753653 6, 0xFFFF, sum = 0
3029 13:41:46.753705 7, 0xFFFF, sum = 0
3030 13:41:46.753758 8, 0xFFFF, sum = 0
3031 13:41:46.753811 9, 0xFFFF, sum = 0
3032 13:41:46.753863 10, 0xFFFF, sum = 0
3033 13:41:46.753916 11, 0xFFFF, sum = 0
3034 13:41:46.753969 12, 0x0, sum = 1
3035 13:41:46.754022 13, 0x0, sum = 2
3036 13:41:46.754074 14, 0x0, sum = 3
3037 13:41:46.754127 15, 0x0, sum = 4
3038 13:41:46.754208 best_step = 13
3039 13:41:46.754275
3040 13:41:46.754327 ==
3041 13:41:46.754379 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 13:41:46.754432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 13:41:46.754484 ==
3044 13:41:46.754537 RX Vref Scan: 0
3045 13:41:46.754589
3046 13:41:46.754641 RX Vref 0 -> 0, step: 1
3047 13:41:46.754693
3048 13:41:46.754745 RX Delay -21 -> 252, step: 4
3049 13:41:46.754797 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3050 13:41:46.754851 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3051 13:41:46.754903 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3052 13:41:46.754956 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3053 13:41:46.755008 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3054 13:41:46.755061 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3055 13:41:46.755113 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3056 13:41:46.755165 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3057 13:41:46.755218 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3058 13:41:46.755271 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3059 13:41:46.755323 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3060 13:41:46.755375 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3061 13:41:46.755428 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3062 13:41:46.755481 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3063 13:41:46.755533 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3064 13:41:46.755586 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3065 13:41:46.755638 ==
3066 13:41:46.755691 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 13:41:46.755744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 13:41:46.755797 ==
3069 13:41:46.755850 DQS Delay:
3070 13:41:46.755902 DQS0 = 0, DQS1 = 0
3071 13:41:46.755954 DQM Delay:
3072 13:41:46.756006 DQM0 = 116, DQM1 = 107
3073 13:41:46.756058 DQ Delay:
3074 13:41:46.756110 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3075 13:41:46.756163 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3076 13:41:46.756215 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3077 13:41:46.756267 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3078 13:41:46.756330
3079 13:41:46.756384
3080 13:41:46.756436 [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3081 13:41:46.756490 CH0 RK1: MR19=403, MR18=10EB
3082 13:41:46.756543 CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3083 13:41:46.756596 [RxdqsGatingPostProcess] freq 1200
3084 13:41:46.756649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3085 13:41:46.756702 best DQS0 dly(2T, 0.5T) = (0, 11)
3086 13:41:46.756755 best DQS1 dly(2T, 0.5T) = (0, 12)
3087 13:41:46.756808 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3088 13:41:46.756861 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3089 13:41:46.756913 best DQS0 dly(2T, 0.5T) = (0, 11)
3090 13:41:46.756966 best DQS1 dly(2T, 0.5T) = (0, 11)
3091 13:41:46.757032 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3092 13:41:46.757086 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3093 13:41:46.757139 Pre-setting of DQS Precalculation
3094 13:41:46.757192 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3095 13:41:46.757245 ==
3096 13:41:46.757298 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 13:41:46.757351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 13:41:46.757404 ==
3099 13:41:46.757457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 13:41:46.757511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3101 13:41:46.757564 [CA 0] Center 37 (7~68) winsize 62
3102 13:41:46.757617 [CA 1] Center 38 (8~68) winsize 61
3103 13:41:46.757670 [CA 2] Center 34 (4~64) winsize 61
3104 13:41:46.757738 [CA 3] Center 33 (3~64) winsize 62
3105 13:41:46.757804 [CA 4] Center 34 (4~64) winsize 61
3106 13:41:46.757856 [CA 5] Center 33 (3~64) winsize 62
3107 13:41:46.757909
3108 13:41:46.757961 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 13:41:46.758014
3110 13:41:46.758066 [CATrainingPosCal] consider 1 rank data
3111 13:41:46.758118 u2DelayCellTimex100 = 270/100 ps
3112 13:41:46.758195 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 13:41:46.758263 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3114 13:41:46.758315 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 13:41:46.758368 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 13:41:46.758421 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 13:41:46.758473 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3118 13:41:46.758525
3119 13:41:46.758578 CA PerBit enable=1, Macro0, CA PI delay=33
3120 13:41:46.758631
3121 13:41:46.758683 [CBTSetCACLKResult] CA Dly = 33
3122 13:41:46.758735 CS Dly: 6 (0~37)
3123 13:41:46.758787 ==
3124 13:41:46.758840 Dram Type= 6, Freq= 0, CH_1, rank 1
3125 13:41:46.758910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 13:41:46.758976 ==
3127 13:41:46.759054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 13:41:46.759141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3129 13:41:46.759199 [CA 0] Center 37 (7~68) winsize 62
3130 13:41:46.759253 [CA 1] Center 38 (8~68) winsize 61
3131 13:41:46.759306 [CA 2] Center 34 (4~65) winsize 62
3132 13:41:46.759360 [CA 3] Center 33 (3~64) winsize 62
3133 13:41:46.759412 [CA 4] Center 34 (4~65) winsize 62
3134 13:41:46.759465 [CA 5] Center 33 (3~64) winsize 62
3135 13:41:46.759518
3136 13:41:46.759570 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3137 13:41:46.759623
3138 13:41:46.759874 [CATrainingPosCal] consider 2 rank data
3139 13:41:46.759937 u2DelayCellTimex100 = 270/100 ps
3140 13:41:46.759992 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3141 13:41:46.760046 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3142 13:41:46.760100 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 13:41:46.760153 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3144 13:41:46.760236 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3145 13:41:46.760288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 13:41:46.760341
3147 13:41:46.760393 CA PerBit enable=1, Macro0, CA PI delay=33
3148 13:41:46.760446
3149 13:41:46.760498 [CBTSetCACLKResult] CA Dly = 33
3150 13:41:46.760551 CS Dly: 7 (0~40)
3151 13:41:46.760603
3152 13:41:46.760655 ----->DramcWriteLeveling(PI) begin...
3153 13:41:46.760708 ==
3154 13:41:46.760761 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 13:41:46.760814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 13:41:46.760866 ==
3157 13:41:46.760918 Write leveling (Byte 0): 26 => 26
3158 13:41:46.760971 Write leveling (Byte 1): 27 => 27
3159 13:41:46.761024 DramcWriteLeveling(PI) end<-----
3160 13:41:46.761076
3161 13:41:46.761128 ==
3162 13:41:46.761181 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 13:41:46.761234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 13:41:46.761286 ==
3165 13:41:46.761338 [Gating] SW mode calibration
3166 13:41:46.761391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3167 13:41:46.761445 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3168 13:41:46.761498 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3169 13:41:46.761551 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 13:41:46.761604 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 13:41:46.761657 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 13:41:46.761710 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 13:41:46.761786 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 13:41:46.761851 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
3175 13:41:46.761904 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3176 13:41:46.761957 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 13:41:46.762009 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 13:41:46.762062 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 13:41:46.762114 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 13:41:46.762194 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 13:41:46.762290 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 13:41:46.762343 1 0 24 | B1->B0 | 2828 3434 | 1 1 | (0 0) (0 0)
3183 13:41:46.762396 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 13:41:46.762448 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 13:41:46.762501 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 13:41:46.762553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 13:41:46.762605 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 13:41:46.762658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 13:41:46.762710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 13:41:46.762763 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:41:46.762815 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3192 13:41:46.762867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 13:41:46.762919 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 13:41:46.762972 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 13:41:46.763024 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 13:41:46.763077 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:41:46.763129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:41:46.763181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:41:46.763234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:41:46.763287 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:41:46.763340 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:41:46.763391 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:41:46.763444 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:41:46.763497 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:41:46.763549 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:41:46.763601 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3207 13:41:46.763654 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3208 13:41:46.763707 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 13:41:46.763760 Total UI for P1: 0, mck2ui 16
3210 13:41:46.763812 best dqsien dly found for B0: ( 1, 3, 26)
3211 13:41:46.763865 Total UI for P1: 0, mck2ui 16
3212 13:41:46.763918 best dqsien dly found for B1: ( 1, 3, 28)
3213 13:41:46.763971 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3214 13:41:46.764024 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3215 13:41:46.764076
3216 13:41:46.764128 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3217 13:41:46.764180 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3218 13:41:46.764233 [Gating] SW calibration Done
3219 13:41:46.764286 ==
3220 13:41:46.764339 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 13:41:46.764391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 13:41:46.764444 ==
3223 13:41:46.764496 RX Vref Scan: 0
3224 13:41:46.764548
3225 13:41:46.764601 RX Vref 0 -> 0, step: 1
3226 13:41:46.764653
3227 13:41:46.764706 RX Delay -40 -> 252, step: 8
3228 13:41:46.764758 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3229 13:41:46.764812 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3230 13:41:46.764865 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3231 13:41:46.764918 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3232 13:41:46.764971 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3233 13:41:46.765023 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3234 13:41:46.765076 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3235 13:41:46.765128 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3236 13:41:46.765181 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3237 13:41:46.765233 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3238 13:41:46.765285 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3239 13:41:46.765337 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3240 13:41:46.765584 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3241 13:41:46.765646 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3242 13:41:46.765714 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3243 13:41:46.765781 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3244 13:41:46.765834 ==
3245 13:41:46.765887 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 13:41:46.765940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 13:41:46.765994 ==
3248 13:41:46.766046 DQS Delay:
3249 13:41:46.766099 DQS0 = 0, DQS1 = 0
3250 13:41:46.766151 DQM Delay:
3251 13:41:46.766259 DQM0 = 118, DQM1 = 109
3252 13:41:46.766313 DQ Delay:
3253 13:41:46.766366 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3254 13:41:46.766419 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3255 13:41:46.766472 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3256 13:41:46.766525 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3257 13:41:46.766577
3258 13:41:46.766630
3259 13:41:46.766682 ==
3260 13:41:46.766735 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 13:41:46.766788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 13:41:46.766841 ==
3263 13:41:46.766893
3264 13:41:46.766946
3265 13:41:46.766998 TX Vref Scan disable
3266 13:41:46.767051 == TX Byte 0 ==
3267 13:41:46.767103 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3268 13:41:46.767156 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3269 13:41:46.767209 == TX Byte 1 ==
3270 13:41:46.767261 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3271 13:41:46.767314 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3272 13:41:46.767384 ==
3273 13:41:46.767450 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 13:41:46.767503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 13:41:46.767555 ==
3276 13:41:46.767608 TX Vref=22, minBit 9, minWin=25, winSum=417
3277 13:41:46.767661 TX Vref=24, minBit 9, minWin=25, winSum=425
3278 13:41:46.767714 TX Vref=26, minBit 2, minWin=26, winSum=432
3279 13:41:46.767767 TX Vref=28, minBit 10, minWin=25, winSum=434
3280 13:41:46.767820 TX Vref=30, minBit 9, minWin=26, winSum=433
3281 13:41:46.767873 TX Vref=32, minBit 7, minWin=26, winSum=429
3282 13:41:46.767925 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3283 13:41:46.767978
3284 13:41:46.768030 Final TX Range 1 Vref 30
3285 13:41:46.768083
3286 13:41:46.768135 ==
3287 13:41:46.768187 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 13:41:46.768239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 13:41:46.768292 ==
3290 13:41:46.768344
3291 13:41:46.768396
3292 13:41:46.768447 TX Vref Scan disable
3293 13:41:46.768499 == TX Byte 0 ==
3294 13:41:46.768551 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3295 13:41:46.768604 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3296 13:41:46.768656 == TX Byte 1 ==
3297 13:41:46.768708 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3298 13:41:46.768760 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3299 13:41:46.768812
3300 13:41:46.768863 [DATLAT]
3301 13:41:46.768915 Freq=1200, CH1 RK0
3302 13:41:46.768967
3303 13:41:46.769019 DATLAT Default: 0xd
3304 13:41:46.769070 0, 0xFFFF, sum = 0
3305 13:41:46.769123 1, 0xFFFF, sum = 0
3306 13:41:46.769177 2, 0xFFFF, sum = 0
3307 13:41:46.769230 3, 0xFFFF, sum = 0
3308 13:41:46.769289 4, 0xFFFF, sum = 0
3309 13:41:46.769375 5, 0xFFFF, sum = 0
3310 13:41:46.769457 6, 0xFFFF, sum = 0
3311 13:41:46.769509 7, 0xFFFF, sum = 0
3312 13:41:46.769561 8, 0xFFFF, sum = 0
3313 13:41:46.769614 9, 0xFFFF, sum = 0
3314 13:41:46.769666 10, 0xFFFF, sum = 0
3315 13:41:46.769719 11, 0xFFFF, sum = 0
3316 13:41:46.769771 12, 0x0, sum = 1
3317 13:41:46.769824 13, 0x0, sum = 2
3318 13:41:46.769876 14, 0x0, sum = 3
3319 13:41:46.769928 15, 0x0, sum = 4
3320 13:41:46.769980 best_step = 13
3321 13:41:46.770032
3322 13:41:46.770083 ==
3323 13:41:46.770134 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 13:41:46.770228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 13:41:46.770282 ==
3326 13:41:46.770334 RX Vref Scan: 1
3327 13:41:46.770386
3328 13:41:46.770437 Set Vref Range= 32 -> 127
3329 13:41:46.770489
3330 13:41:46.770541 RX Vref 32 -> 127, step: 1
3331 13:41:46.770593
3332 13:41:46.770644 RX Delay -21 -> 252, step: 4
3333 13:41:46.770696
3334 13:41:46.770747 Set Vref, RX VrefLevel [Byte0]: 32
3335 13:41:46.770800 [Byte1]: 32
3336 13:41:46.770851
3337 13:41:46.770903 Set Vref, RX VrefLevel [Byte0]: 33
3338 13:41:46.770955 [Byte1]: 33
3339 13:41:46.771008
3340 13:41:46.771060 Set Vref, RX VrefLevel [Byte0]: 34
3341 13:41:46.771112 [Byte1]: 34
3342 13:41:46.771164
3343 13:41:46.771215 Set Vref, RX VrefLevel [Byte0]: 35
3344 13:41:46.771267 [Byte1]: 35
3345 13:41:46.771318
3346 13:41:46.771370 Set Vref, RX VrefLevel [Byte0]: 36
3347 13:41:46.771421 [Byte1]: 36
3348 13:41:46.771473
3349 13:41:46.771524 Set Vref, RX VrefLevel [Byte0]: 37
3350 13:41:46.771576 [Byte1]: 37
3351 13:41:46.771627
3352 13:41:46.771678 Set Vref, RX VrefLevel [Byte0]: 38
3353 13:41:46.771730 [Byte1]: 38
3354 13:41:46.771782
3355 13:41:46.771833 Set Vref, RX VrefLevel [Byte0]: 39
3356 13:41:46.771885 [Byte1]: 39
3357 13:41:46.771937
3358 13:41:46.771988 Set Vref, RX VrefLevel [Byte0]: 40
3359 13:41:46.772040 [Byte1]: 40
3360 13:41:46.772091
3361 13:41:46.772143 Set Vref, RX VrefLevel [Byte0]: 41
3362 13:41:46.772194 [Byte1]: 41
3363 13:41:46.772246
3364 13:41:46.772297 Set Vref, RX VrefLevel [Byte0]: 42
3365 13:41:46.772349 [Byte1]: 42
3366 13:41:46.772401
3367 13:41:46.772453 Set Vref, RX VrefLevel [Byte0]: 43
3368 13:41:46.772504 [Byte1]: 43
3369 13:41:46.772557
3370 13:41:46.772607 Set Vref, RX VrefLevel [Byte0]: 44
3371 13:41:46.772659 [Byte1]: 44
3372 13:41:46.772711
3373 13:41:46.772762 Set Vref, RX VrefLevel [Byte0]: 45
3374 13:41:46.772814 [Byte1]: 45
3375 13:41:46.772865
3376 13:41:46.772917 Set Vref, RX VrefLevel [Byte0]: 46
3377 13:41:46.772969 [Byte1]: 46
3378 13:41:46.773020
3379 13:41:46.773071 Set Vref, RX VrefLevel [Byte0]: 47
3380 13:41:46.773124 [Byte1]: 47
3381 13:41:46.773176
3382 13:41:46.773228 Set Vref, RX VrefLevel [Byte0]: 48
3383 13:41:46.773288 [Byte1]: 48
3384 13:41:46.773359
3385 13:41:46.773424 Set Vref, RX VrefLevel [Byte0]: 49
3386 13:41:46.773476 [Byte1]: 49
3387 13:41:46.773527
3388 13:41:46.773579 Set Vref, RX VrefLevel [Byte0]: 50
3389 13:41:46.773631 [Byte1]: 50
3390 13:41:46.773682
3391 13:41:46.773734 Set Vref, RX VrefLevel [Byte0]: 51
3392 13:41:46.773786 [Byte1]: 51
3393 13:41:46.773837
3394 13:41:46.773888 Set Vref, RX VrefLevel [Byte0]: 52
3395 13:41:46.773940 [Byte1]: 52
3396 13:41:46.773991
3397 13:41:46.774043 Set Vref, RX VrefLevel [Byte0]: 53
3398 13:41:46.774095 [Byte1]: 53
3399 13:41:46.774146
3400 13:41:46.774240 Set Vref, RX VrefLevel [Byte0]: 54
3401 13:41:46.774293 [Byte1]: 54
3402 13:41:46.774345
3403 13:41:46.774396 Set Vref, RX VrefLevel [Byte0]: 55
3404 13:41:46.774447 [Byte1]: 55
3405 13:41:46.774498
3406 13:41:46.774743 Set Vref, RX VrefLevel [Byte0]: 56
3407 13:41:46.774802 [Byte1]: 56
3408 13:41:46.774855
3409 13:41:46.774907 Set Vref, RX VrefLevel [Byte0]: 57
3410 13:41:46.774960 [Byte1]: 57
3411 13:41:46.775011
3412 13:41:46.775063 Set Vref, RX VrefLevel [Byte0]: 58
3413 13:41:46.775116 [Byte1]: 58
3414 13:41:46.775168
3415 13:41:46.775219 Set Vref, RX VrefLevel [Byte0]: 59
3416 13:41:46.775271 [Byte1]: 59
3417 13:41:46.775322
3418 13:41:46.775374 Set Vref, RX VrefLevel [Byte0]: 60
3419 13:41:46.775432 [Byte1]: 60
3420 13:41:46.775495
3421 13:41:46.775548 Set Vref, RX VrefLevel [Byte0]: 61
3422 13:41:46.775600 [Byte1]: 61
3423 13:41:46.775653
3424 13:41:46.775705 Set Vref, RX VrefLevel [Byte0]: 62
3425 13:41:46.775756 [Byte1]: 62
3426 13:41:46.775808
3427 13:41:46.775860 Set Vref, RX VrefLevel [Byte0]: 63
3428 13:41:46.775912 [Byte1]: 63
3429 13:41:46.775964
3430 13:41:46.776016 Set Vref, RX VrefLevel [Byte0]: 64
3431 13:41:46.776085 [Byte1]: 64
3432 13:41:46.776150
3433 13:41:46.776202 Set Vref, RX VrefLevel [Byte0]: 65
3434 13:41:46.776254 [Byte1]: 65
3435 13:41:46.776305
3436 13:41:46.776357 Set Vref, RX VrefLevel [Byte0]: 66
3437 13:41:46.776408 [Byte1]: 66
3438 13:41:46.776460
3439 13:41:46.776511 Set Vref, RX VrefLevel [Byte0]: 67
3440 13:41:46.776563 [Byte1]: 67
3441 13:41:46.776614
3442 13:41:46.776665 Set Vref, RX VrefLevel [Byte0]: 68
3443 13:41:46.776717 [Byte1]: 68
3444 13:41:46.776768
3445 13:41:46.776820 Final RX Vref Byte 0 = 48 to rank0
3446 13:41:46.776872 Final RX Vref Byte 1 = 60 to rank0
3447 13:41:46.776924 Final RX Vref Byte 0 = 48 to rank1
3448 13:41:46.776976 Final RX Vref Byte 1 = 60 to rank1==
3449 13:41:46.777028 Dram Type= 6, Freq= 0, CH_1, rank 0
3450 13:41:46.777079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 13:41:46.777132 ==
3452 13:41:46.777183 DQS Delay:
3453 13:41:46.777235 DQS0 = 0, DQS1 = 0
3454 13:41:46.777286 DQM Delay:
3455 13:41:46.777338 DQM0 = 117, DQM1 = 112
3456 13:41:46.777389 DQ Delay:
3457 13:41:46.777441 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3458 13:41:46.777492 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =116
3459 13:41:46.777543 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =102
3460 13:41:46.777595 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3461 13:41:46.777647
3462 13:41:46.777697
3463 13:41:46.777748 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3464 13:41:46.777801 CH1 RK0: MR19=403, MR18=2F6
3465 13:41:46.777854 CH1_RK0: MR19=0x403, MR18=0x2F6, DQSOSC=409, MR23=63, INC=39, DEC=26
3466 13:41:46.777907
3467 13:41:46.777959 ----->DramcWriteLeveling(PI) begin...
3468 13:41:46.778012 ==
3469 13:41:46.778064 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 13:41:46.778115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 13:41:46.778195 ==
3472 13:41:46.778263 Write leveling (Byte 0): 25 => 25
3473 13:41:46.778315 Write leveling (Byte 1): 28 => 28
3474 13:41:46.778368 DramcWriteLeveling(PI) end<-----
3475 13:41:46.778419
3476 13:41:46.778471 ==
3477 13:41:46.778522 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 13:41:46.778574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 13:41:46.778626 ==
3480 13:41:46.778677 [Gating] SW mode calibration
3481 13:41:46.778734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3482 13:41:46.778794 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3483 13:41:46.778846 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3484 13:41:46.778899 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 13:41:46.778951 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 13:41:46.779003 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 13:41:46.779055 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 13:41:46.779107 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 13:41:46.779159 0 15 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 1)
3490 13:41:46.779210 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 1)
3491 13:41:46.779262 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 13:41:46.779314 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 13:41:46.779366 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 13:41:46.779417 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 13:41:46.779469 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 13:41:46.779521 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3497 13:41:46.779572 1 0 24 | B1->B0 | 3b3b 2626 | 1 0 | (0 0) (0 0)
3498 13:41:46.779624 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 13:41:46.779676 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 13:41:46.779728 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 13:41:46.779780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 13:41:46.779832 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 13:41:46.779884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 13:41:46.779936 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 13:41:46.779987 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3506 13:41:46.780039 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3507 13:41:46.780090 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 13:41:46.780141 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 13:41:46.780193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 13:41:46.780245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 13:41:46.780296 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 13:41:46.780347 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 13:41:46.780399 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 13:41:46.780451 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 13:41:46.780503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 13:41:46.780555 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 13:41:46.780607 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 13:41:46.780659 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 13:41:46.780710 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 13:41:46.780954 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 13:41:46.781013 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3522 13:41:46.781067 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 13:41:46.781119 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 13:41:46.781172 Total UI for P1: 0, mck2ui 16
3525 13:41:46.781225 best dqsien dly found for B0: ( 1, 3, 28)
3526 13:41:46.781277 Total UI for P1: 0, mck2ui 16
3527 13:41:46.781329 best dqsien dly found for B1: ( 1, 3, 26)
3528 13:41:46.781381 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3529 13:41:46.781434 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3530 13:41:46.781485
3531 13:41:46.781536 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3532 13:41:46.781589 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3533 13:41:46.781641 [Gating] SW calibration Done
3534 13:41:46.781693 ==
3535 13:41:46.781744 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 13:41:46.781797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 13:41:46.781850 ==
3538 13:41:46.781902 RX Vref Scan: 0
3539 13:41:46.781954
3540 13:41:46.782005 RX Vref 0 -> 0, step: 1
3541 13:41:46.782057
3542 13:41:46.782108 RX Delay -40 -> 252, step: 8
3543 13:41:46.782169 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3544 13:41:46.782254 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3545 13:41:46.782306 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3546 13:41:46.782359 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3547 13:41:46.782411 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3548 13:41:46.782463 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3549 13:41:46.782515 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3550 13:41:46.782567 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3551 13:41:46.782619 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3552 13:41:46.782671 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3553 13:41:46.782722 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3554 13:41:46.782774 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3555 13:41:46.782826 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3556 13:41:46.782878 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3557 13:41:46.782930 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3558 13:41:46.782981 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3559 13:41:46.783033 ==
3560 13:41:46.783085 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 13:41:46.783137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 13:41:46.783189 ==
3563 13:41:46.783241 DQS Delay:
3564 13:41:46.783293 DQS0 = 0, DQS1 = 0
3565 13:41:46.783345 DQM Delay:
3566 13:41:46.783396 DQM0 = 116, DQM1 = 110
3567 13:41:46.783448 DQ Delay:
3568 13:41:46.783500 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3569 13:41:46.783551 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3570 13:41:46.783603 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3571 13:41:46.783655 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3572 13:41:46.783706
3573 13:41:46.783757
3574 13:41:46.783808 ==
3575 13:41:46.783860 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 13:41:46.783913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 13:41:46.783965 ==
3578 13:41:46.784016
3579 13:41:46.784068
3580 13:41:46.784119 TX Vref Scan disable
3581 13:41:46.784171 == TX Byte 0 ==
3582 13:41:46.784223 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 13:41:46.784275 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 13:41:46.784327 == TX Byte 1 ==
3585 13:41:46.784379 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 13:41:46.784431 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 13:41:46.784482 ==
3588 13:41:46.784534 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 13:41:46.784586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 13:41:46.784637 ==
3591 13:41:46.784689 TX Vref=22, minBit 9, minWin=25, winSum=423
3592 13:41:46.784741 TX Vref=24, minBit 8, minWin=26, winSum=427
3593 13:41:46.784793 TX Vref=26, minBit 9, minWin=26, winSum=435
3594 13:41:46.784846 TX Vref=28, minBit 9, minWin=26, winSum=433
3595 13:41:46.784898 TX Vref=30, minBit 8, minWin=26, winSum=436
3596 13:41:46.784950 TX Vref=32, minBit 7, minWin=26, winSum=429
3597 13:41:46.785001 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3598 13:41:46.785054
3599 13:41:46.785105 Final TX Range 1 Vref 30
3600 13:41:46.785157
3601 13:41:46.785221 ==
3602 13:41:46.785275 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 13:41:46.785327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 13:41:46.785380 ==
3605 13:41:46.785432
3606 13:41:46.785483
3607 13:41:46.785535 TX Vref Scan disable
3608 13:41:46.785587 == TX Byte 0 ==
3609 13:41:46.785639 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 13:41:46.785711 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 13:41:46.785765 == TX Byte 1 ==
3612 13:41:46.785817 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 13:41:46.785886 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 13:41:46.785969
3615 13:41:46.786050 [DATLAT]
3616 13:41:46.786164 Freq=1200, CH1 RK1
3617 13:41:46.786255
3618 13:41:46.786316 DATLAT Default: 0xd
3619 13:41:46.786377 0, 0xFFFF, sum = 0
3620 13:41:46.786432 1, 0xFFFF, sum = 0
3621 13:41:46.786486 2, 0xFFFF, sum = 0
3622 13:41:46.786548 3, 0xFFFF, sum = 0
3623 13:41:46.786603 4, 0xFFFF, sum = 0
3624 13:41:46.786663 5, 0xFFFF, sum = 0
3625 13:41:46.786727 6, 0xFFFF, sum = 0
3626 13:41:46.786783 7, 0xFFFF, sum = 0
3627 13:41:46.786835 8, 0xFFFF, sum = 0
3628 13:41:46.786889 9, 0xFFFF, sum = 0
3629 13:41:46.786941 10, 0xFFFF, sum = 0
3630 13:41:46.786994 11, 0xFFFF, sum = 0
3631 13:41:46.787047 12, 0x0, sum = 1
3632 13:41:46.787100 13, 0x0, sum = 2
3633 13:41:46.787153 14, 0x0, sum = 3
3634 13:41:46.787206 15, 0x0, sum = 4
3635 13:41:46.787259 best_step = 13
3636 13:41:46.787311
3637 13:41:46.787363 ==
3638 13:41:46.787416 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 13:41:46.787468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 13:41:46.787520 ==
3641 13:41:46.787572 RX Vref Scan: 0
3642 13:41:46.787625
3643 13:41:46.787677 RX Vref 0 -> 0, step: 1
3644 13:41:46.787729
3645 13:41:46.787780 RX Delay -13 -> 252, step: 4
3646 13:41:46.787832 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3647 13:41:46.787885 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3648 13:41:46.787937 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3649 13:41:46.787989 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3650 13:41:46.788041 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3651 13:41:46.788092 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3652 13:41:46.788144 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3653 13:41:46.788196 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3654 13:41:46.788247 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3655 13:41:46.788299 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3656 13:41:46.788351 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3657 13:41:46.788403 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3658 13:41:46.788455 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3659 13:41:46.788703 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3660 13:41:46.788763 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3661 13:41:46.788830 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3662 13:41:46.788884 ==
3663 13:41:46.788936 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 13:41:46.788989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 13:41:46.789042 ==
3666 13:41:46.789094 DQS Delay:
3667 13:41:46.789146 DQS0 = 0, DQS1 = 0
3668 13:41:46.789198 DQM Delay:
3669 13:41:46.789250 DQM0 = 117, DQM1 = 111
3670 13:41:46.789302 DQ Delay:
3671 13:41:46.789354 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3672 13:41:46.789407 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3673 13:41:46.789458 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3674 13:41:46.789510 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =120
3675 13:41:46.789561
3676 13:41:46.789612
3677 13:41:46.789664 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3678 13:41:46.789717 CH1 RK1: MR19=303, MR18=F3EE
3679 13:41:46.789769 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3680 13:41:46.789822 [RxdqsGatingPostProcess] freq 1200
3681 13:41:46.789873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 13:41:46.789926 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 13:41:46.789978 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 13:41:46.790030 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 13:41:46.790082 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 13:41:46.790133 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 13:41:46.790225 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 13:41:46.790278 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 13:41:46.790330 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 13:41:46.790381 Pre-setting of DQS Precalculation
3691 13:41:46.790433 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 13:41:46.790486 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 13:41:46.790539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 13:41:46.790592
3695 13:41:46.790643
3696 13:41:46.790694 [Calibration Summary] 2400 Mbps
3697 13:41:46.790747 CH 0, Rank 0
3698 13:41:46.790799 SW Impedance : PASS
3699 13:41:46.790851 DUTY Scan : NO K
3700 13:41:46.790903 ZQ Calibration : PASS
3701 13:41:46.790955 Jitter Meter : NO K
3702 13:41:46.791007 CBT Training : PASS
3703 13:41:46.791059 Write leveling : PASS
3704 13:41:46.791111 RX DQS gating : PASS
3705 13:41:46.791163 RX DQ/DQS(RDDQC) : PASS
3706 13:41:46.791215 TX DQ/DQS : PASS
3707 13:41:46.791267 RX DATLAT : PASS
3708 13:41:46.791319 RX DQ/DQS(Engine): PASS
3709 13:41:46.791371 TX OE : NO K
3710 13:41:46.791423 All Pass.
3711 13:41:46.791475
3712 13:41:46.791526 CH 0, Rank 1
3713 13:41:46.791578 SW Impedance : PASS
3714 13:41:46.791630 DUTY Scan : NO K
3715 13:41:46.791681 ZQ Calibration : PASS
3716 13:41:46.791733 Jitter Meter : NO K
3717 13:41:46.791784 CBT Training : PASS
3718 13:41:46.791836 Write leveling : PASS
3719 13:41:46.791888 RX DQS gating : PASS
3720 13:41:46.791939 RX DQ/DQS(RDDQC) : PASS
3721 13:41:46.791991 TX DQ/DQS : PASS
3722 13:41:46.792043 RX DATLAT : PASS
3723 13:41:46.792094 RX DQ/DQS(Engine): PASS
3724 13:41:46.792145 TX OE : NO K
3725 13:41:46.792197 All Pass.
3726 13:41:46.792249
3727 13:41:46.792300 CH 1, Rank 0
3728 13:41:46.792352 SW Impedance : PASS
3729 13:41:46.792404 DUTY Scan : NO K
3730 13:41:46.792455 ZQ Calibration : PASS
3731 13:41:46.792507 Jitter Meter : NO K
3732 13:41:46.792558 CBT Training : PASS
3733 13:41:46.792609 Write leveling : PASS
3734 13:41:46.792661 RX DQS gating : PASS
3735 13:41:46.792713 RX DQ/DQS(RDDQC) : PASS
3736 13:41:46.792764 TX DQ/DQS : PASS
3737 13:41:46.792816 RX DATLAT : PASS
3738 13:41:46.792868 RX DQ/DQS(Engine): PASS
3739 13:41:46.792920 TX OE : NO K
3740 13:41:46.792971 All Pass.
3741 13:41:46.793024
3742 13:41:46.793076 CH 1, Rank 1
3743 13:41:46.793127 SW Impedance : PASS
3744 13:41:46.793179 DUTY Scan : NO K
3745 13:41:46.793230 ZQ Calibration : PASS
3746 13:41:46.793282 Jitter Meter : NO K
3747 13:41:46.793333 CBT Training : PASS
3748 13:41:46.793385 Write leveling : PASS
3749 13:41:46.793436 RX DQS gating : PASS
3750 13:41:46.793488 RX DQ/DQS(RDDQC) : PASS
3751 13:41:46.793539 TX DQ/DQS : PASS
3752 13:41:46.793591 RX DATLAT : PASS
3753 13:41:46.793642 RX DQ/DQS(Engine): PASS
3754 13:41:46.793693 TX OE : NO K
3755 13:41:46.793745 All Pass.
3756 13:41:46.793835
3757 13:41:46.793886 DramC Write-DBI off
3758 13:41:46.793938 PER_BANK_REFRESH: Hybrid Mode
3759 13:41:46.793990 TX_TRACKING: ON
3760 13:41:46.794041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 13:41:46.794096 [FAST_K] Save calibration result to emmc
3762 13:41:46.794148 dramc_set_vcore_voltage set vcore to 650000
3763 13:41:46.794244 Read voltage for 600, 5
3764 13:41:46.794296 Vio18 = 0
3765 13:41:46.794348 Vcore = 650000
3766 13:41:46.794400 Vdram = 0
3767 13:41:46.794452 Vddq = 0
3768 13:41:46.794504 Vmddr = 0
3769 13:41:46.794556 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 13:41:46.794608 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 13:41:46.794660 MEM_TYPE=3, freq_sel=19
3772 13:41:46.794711 sv_algorithm_assistance_LP4_1600
3773 13:41:46.794763 ============ PULL DRAM RESETB DOWN ============
3774 13:41:46.794815 ========== PULL DRAM RESETB DOWN end =========
3775 13:41:46.794867 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 13:41:46.794920 ===================================
3777 13:41:46.794971 LPDDR4 DRAM CONFIGURATION
3778 13:41:46.795024 ===================================
3779 13:41:46.795075 EX_ROW_EN[0] = 0x0
3780 13:41:46.795127 EX_ROW_EN[1] = 0x0
3781 13:41:46.795179 LP4Y_EN = 0x0
3782 13:41:46.795232 WORK_FSP = 0x0
3783 13:41:46.795284 WL = 0x2
3784 13:41:46.795335 RL = 0x2
3785 13:41:46.795387 BL = 0x2
3786 13:41:46.795439 RPST = 0x0
3787 13:41:46.795490 RD_PRE = 0x0
3788 13:41:46.795542 WR_PRE = 0x1
3789 13:41:46.795594 WR_PST = 0x0
3790 13:41:46.795646 DBI_WR = 0x0
3791 13:41:46.795697 DBI_RD = 0x0
3792 13:41:46.795748 OTF = 0x1
3793 13:41:46.795800 ===================================
3794 13:41:46.795852 ===================================
3795 13:41:46.795904 ANA top config
3796 13:41:46.795955 ===================================
3797 13:41:46.796007 DLL_ASYNC_EN = 0
3798 13:41:46.796059 ALL_SLAVE_EN = 1
3799 13:41:46.796111 NEW_RANK_MODE = 1
3800 13:41:46.796163 DLL_IDLE_MODE = 1
3801 13:41:46.796215 LP45_APHY_COMB_EN = 1
3802 13:41:46.796266 TX_ODT_DIS = 1
3803 13:41:46.796318 NEW_8X_MODE = 1
3804 13:41:46.796564 ===================================
3805 13:41:46.796622 ===================================
3806 13:41:46.796675 data_rate = 1200
3807 13:41:46.796728 CKR = 1
3808 13:41:46.796780 DQ_P2S_RATIO = 8
3809 13:41:46.796833 ===================================
3810 13:41:46.796885 CA_P2S_RATIO = 8
3811 13:41:46.796936 DQ_CA_OPEN = 0
3812 13:41:46.796988 DQ_SEMI_OPEN = 0
3813 13:41:46.797040 CA_SEMI_OPEN = 0
3814 13:41:46.797092 CA_FULL_RATE = 0
3815 13:41:46.797143 DQ_CKDIV4_EN = 1
3816 13:41:46.797195 CA_CKDIV4_EN = 1
3817 13:41:46.797247 CA_PREDIV_EN = 0
3818 13:41:46.797299 PH8_DLY = 0
3819 13:41:46.797367 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 13:41:46.797420 DQ_AAMCK_DIV = 4
3821 13:41:46.797472 CA_AAMCK_DIV = 4
3822 13:41:46.797543 CA_ADMCK_DIV = 4
3823 13:41:46.797610 DQ_TRACK_CA_EN = 0
3824 13:41:46.797666 CA_PICK = 600
3825 13:41:46.797718 CA_MCKIO = 600
3826 13:41:46.797807 MCKIO_SEMI = 0
3827 13:41:46.797896 PLL_FREQ = 2288
3828 13:41:46.797948 DQ_UI_PI_RATIO = 32
3829 13:41:46.798001 CA_UI_PI_RATIO = 0
3830 13:41:46.798053 ===================================
3831 13:41:46.798120 ===================================
3832 13:41:46.798233 memory_type:LPDDR4
3833 13:41:46.798287 GP_NUM : 10
3834 13:41:46.798340 SRAM_EN : 1
3835 13:41:46.798391 MD32_EN : 0
3836 13:41:46.798443 ===================================
3837 13:41:46.798496 [ANA_INIT] >>>>>>>>>>>>>>
3838 13:41:46.798548 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 13:41:46.798600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 13:41:46.798661 ===================================
3841 13:41:46.798713 data_rate = 1200,PCW = 0X5800
3842 13:41:46.798765 ===================================
3843 13:41:46.798817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 13:41:46.798869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 13:41:46.798921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 13:41:46.798974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 13:41:46.799026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 13:41:46.799079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 13:41:46.799131 [ANA_INIT] flow start
3850 13:41:46.799182 [ANA_INIT] PLL >>>>>>>>
3851 13:41:46.799234 [ANA_INIT] PLL <<<<<<<<
3852 13:41:46.799285 [ANA_INIT] MIDPI >>>>>>>>
3853 13:41:46.799337 [ANA_INIT] MIDPI <<<<<<<<
3854 13:41:46.799389 [ANA_INIT] DLL >>>>>>>>
3855 13:41:46.799440 [ANA_INIT] flow end
3856 13:41:46.799492 ============ LP4 DIFF to SE enter ============
3857 13:41:46.799544 ============ LP4 DIFF to SE exit ============
3858 13:41:46.799596 [ANA_INIT] <<<<<<<<<<<<<
3859 13:41:46.799647 [Flow] Enable top DCM control >>>>>
3860 13:41:46.799699 [Flow] Enable top DCM control <<<<<
3861 13:41:46.799750 Enable DLL master slave shuffle
3862 13:41:46.799803 ==============================================================
3863 13:41:46.799868 Gating Mode config
3864 13:41:46.799928 ==============================================================
3865 13:41:46.799981 Config description:
3866 13:41:46.800033 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 13:41:46.800086 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 13:41:46.800139 SELPH_MODE 0: By rank 1: By Phase
3869 13:41:46.800192 ==============================================================
3870 13:41:46.800244 GAT_TRACK_EN = 1
3871 13:41:46.800296 RX_GATING_MODE = 2
3872 13:41:46.800347 RX_GATING_TRACK_MODE = 2
3873 13:41:46.800399 SELPH_MODE = 1
3874 13:41:46.800451 PICG_EARLY_EN = 1
3875 13:41:46.800516 VALID_LAT_VALUE = 1
3876 13:41:46.800569 ==============================================================
3877 13:41:46.800622 Enter into Gating configuration >>>>
3878 13:41:46.800674 Exit from Gating configuration <<<<
3879 13:41:46.800740 Enter into DVFS_PRE_config >>>>>
3880 13:41:46.800794 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 13:41:46.800857 Exit from DVFS_PRE_config <<<<<
3882 13:41:46.800910 Enter into PICG configuration >>>>
3883 13:41:46.800962 Exit from PICG configuration <<<<
3884 13:41:46.801028 [RX_INPUT] configuration >>>>>
3885 13:41:46.801081 [RX_INPUT] configuration <<<<<
3886 13:41:46.801134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 13:41:46.801186 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 13:41:46.801239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 13:41:46.801292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 13:41:46.801344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 13:41:46.801396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 13:41:46.801449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 13:41:46.801502 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 13:41:46.801554 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 13:41:46.801608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 13:41:46.801660 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 13:41:46.801712 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 13:41:46.801764 ===================================
3899 13:41:46.801817 LPDDR4 DRAM CONFIGURATION
3900 13:41:46.801869 ===================================
3901 13:41:46.801921 EX_ROW_EN[0] = 0x0
3902 13:41:46.801974 EX_ROW_EN[1] = 0x0
3903 13:41:46.802025 LP4Y_EN = 0x0
3904 13:41:46.802077 WORK_FSP = 0x0
3905 13:41:46.802129 WL = 0x2
3906 13:41:46.802213 RL = 0x2
3907 13:41:46.802458 BL = 0x2
3908 13:41:46.802517 RPST = 0x0
3909 13:41:46.802570 RD_PRE = 0x0
3910 13:41:46.802622 WR_PRE = 0x1
3911 13:41:46.802675 WR_PST = 0x0
3912 13:41:46.802727 DBI_WR = 0x0
3913 13:41:46.802778 DBI_RD = 0x0
3914 13:41:46.802830 OTF = 0x1
3915 13:41:46.802882 ===================================
3916 13:41:46.802935 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 13:41:46.802987 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 13:41:46.803039 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 13:41:46.803091 ===================================
3920 13:41:46.803143 LPDDR4 DRAM CONFIGURATION
3921 13:41:46.803194 ===================================
3922 13:41:46.803246 EX_ROW_EN[0] = 0x10
3923 13:41:46.803297 EX_ROW_EN[1] = 0x0
3924 13:41:46.803349 LP4Y_EN = 0x0
3925 13:41:46.803400 WORK_FSP = 0x0
3926 13:41:46.803452 WL = 0x2
3927 13:41:46.803503 RL = 0x2
3928 13:41:46.803555 BL = 0x2
3929 13:41:46.803607 RPST = 0x0
3930 13:41:46.803659 RD_PRE = 0x0
3931 13:41:46.803710 WR_PRE = 0x1
3932 13:41:46.803781 WR_PST = 0x0
3933 13:41:46.803834 DBI_WR = 0x0
3934 13:41:46.803885 DBI_RD = 0x0
3935 13:41:46.803936 OTF = 0x1
3936 13:41:47.633707 ===================================
3937 13:41:47.633840 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 13:41:47.633906 nWR fixed to 30
3939 13:41:47.633967 [ModeRegInit_LP4] CH0 RK0
3940 13:41:47.634025 [ModeRegInit_LP4] CH0 RK1
3941 13:41:47.634099 [ModeRegInit_LP4] CH1 RK0
3942 13:41:47.634155 [ModeRegInit_LP4] CH1 RK1
3943 13:41:47.634234 match AC timing 17
3944 13:41:47.634289 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 13:41:47.634343 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 13:41:47.634397 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 13:41:47.634451 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 13:41:47.634505 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 13:41:47.634558 ==
3950 13:41:47.634611 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 13:41:47.634664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 13:41:47.634717 ==
3953 13:41:47.634819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 13:41:47.634908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3955 13:41:47.634965 [CA 0] Center 36 (6~66) winsize 61
3956 13:41:47.635019 [CA 1] Center 36 (6~66) winsize 61
3957 13:41:47.635072 [CA 2] Center 34 (4~65) winsize 62
3958 13:41:47.635125 [CA 3] Center 34 (3~65) winsize 63
3959 13:41:47.635177 [CA 4] Center 33 (3~64) winsize 62
3960 13:41:47.635230 [CA 5] Center 33 (3~64) winsize 62
3961 13:41:47.635282
3962 13:41:47.635334 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3963 13:41:47.635386
3964 13:41:47.635439 [CATrainingPosCal] consider 1 rank data
3965 13:41:47.635491 u2DelayCellTimex100 = 270/100 ps
3966 13:41:47.635544 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 13:41:47.635596 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 13:41:47.635648 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 13:41:47.635701 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3970 13:41:47.635753 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 13:41:47.635805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 13:41:47.635857
3973 13:41:47.635908 CA PerBit enable=1, Macro0, CA PI delay=33
3974 13:41:47.635961
3975 13:41:47.636025 [CBTSetCACLKResult] CA Dly = 33
3976 13:41:47.636083 CS Dly: 6 (0~37)
3977 13:41:47.636135 ==
3978 13:41:47.636188 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 13:41:47.636240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 13:41:47.636293 ==
3981 13:41:47.636345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 13:41:47.636398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3983 13:41:47.636450 [CA 0] Center 36 (6~66) winsize 61
3984 13:41:47.636502 [CA 1] Center 36 (6~66) winsize 61
3985 13:41:47.636554 [CA 2] Center 34 (3~65) winsize 63
3986 13:41:47.636605 [CA 3] Center 34 (4~64) winsize 61
3987 13:41:47.636657 [CA 4] Center 33 (3~64) winsize 62
3988 13:41:47.636709 [CA 5] Center 33 (3~64) winsize 62
3989 13:41:47.636761
3990 13:41:47.636848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3991 13:41:47.636900
3992 13:41:47.636975 [CATrainingPosCal] consider 2 rank data
3993 13:41:47.637031 u2DelayCellTimex100 = 270/100 ps
3994 13:41:47.637084 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3995 13:41:47.637136 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 13:41:47.637189 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 13:41:47.637241 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3998 13:41:47.637293 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 13:41:47.637346 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 13:41:47.637397
4001 13:41:47.637448 CA PerBit enable=1, Macro0, CA PI delay=33
4002 13:41:47.637501
4003 13:41:47.637552 [CBTSetCACLKResult] CA Dly = 33
4004 13:41:47.637604 CS Dly: 5 (0~36)
4005 13:41:47.637656
4006 13:41:47.637708 ----->DramcWriteLeveling(PI) begin...
4007 13:41:47.637761 ==
4008 13:41:47.637814 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 13:41:47.637866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 13:41:47.637919 ==
4011 13:41:47.637971 Write leveling (Byte 0): 32 => 32
4012 13:41:47.638024 Write leveling (Byte 1): 31 => 31
4013 13:41:47.638076 DramcWriteLeveling(PI) end<-----
4014 13:41:47.638128
4015 13:41:47.638203 ==
4016 13:41:47.638269 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 13:41:47.638322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 13:41:47.638374 ==
4019 13:41:47.638426 [Gating] SW mode calibration
4020 13:41:47.638478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 13:41:47.638531 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 13:41:47.638583 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 13:41:47.638635 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 13:41:47.638688 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 13:41:47.638740 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4026 13:41:47.638792 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
4027 13:41:47.638844 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 13:41:47.638895 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 13:41:47.638947 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 13:41:47.638999 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 13:41:47.639051 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 13:41:47.639309 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 13:41:47.639368 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4034 13:41:47.639422 0 10 16 | B1->B0 | 3434 4242 | 1 0 | (0 0) (0 0)
4035 13:41:47.639474 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 13:41:47.639527 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 13:41:47.639579 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 13:41:47.639632 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 13:41:47.639685 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 13:41:47.639737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 13:41:47.639789 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 13:41:47.639842 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4043 13:41:47.639893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 13:41:47.639945 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 13:41:47.639997 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 13:41:47.640050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 13:41:47.640102 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 13:41:47.640154 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 13:41:47.640206 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 13:41:47.640258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 13:41:47.640311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 13:41:47.640363 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:41:47.640415 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:41:47.640467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:41:47.640519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:41:47.640571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 13:41:47.640624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4058 13:41:47.640676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4059 13:41:47.640728 Total UI for P1: 0, mck2ui 16
4060 13:41:47.640782 best dqsien dly found for B0: ( 0, 13, 12)
4061 13:41:47.640834 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 13:41:47.640887 Total UI for P1: 0, mck2ui 16
4063 13:41:47.640941 best dqsien dly found for B1: ( 0, 13, 16)
4064 13:41:47.641030 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4065 13:41:47.641083 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4066 13:41:47.641135
4067 13:41:47.641187 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4068 13:41:47.641240 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4069 13:41:47.641293 [Gating] SW calibration Done
4070 13:41:47.641345 ==
4071 13:41:47.641397 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 13:41:47.641450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 13:41:47.641503 ==
4074 13:41:47.641555 RX Vref Scan: 0
4075 13:41:47.641607
4076 13:41:47.641658 RX Vref 0 -> 0, step: 1
4077 13:41:47.641710
4078 13:41:47.641763 RX Delay -230 -> 252, step: 16
4079 13:41:47.641815 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 13:41:47.641868 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4081 13:41:47.641920 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4082 13:41:47.641973 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4083 13:41:47.642025 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4084 13:41:47.642078 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4085 13:41:47.642130 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4086 13:41:47.642220 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 13:41:47.642273 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4088 13:41:47.642327 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 13:41:47.642379 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 13:41:47.642431 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4091 13:41:47.642484 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4092 13:41:47.642536 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4093 13:41:47.642588 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4094 13:41:47.642641 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4095 13:41:47.642693 ==
4096 13:41:47.642745 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 13:41:47.642798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 13:41:47.642851 ==
4099 13:41:47.642903 DQS Delay:
4100 13:41:47.642956 DQS0 = 0, DQS1 = 0
4101 13:41:47.643010 DQM Delay:
4102 13:41:47.643101 DQM0 = 42, DQM1 = 30
4103 13:41:47.643153 DQ Delay:
4104 13:41:47.643205 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4105 13:41:47.643257 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4106 13:41:47.643310 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4107 13:41:47.643362 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4108 13:41:47.643415
4109 13:41:47.643466
4110 13:41:47.643519 ==
4111 13:41:47.643571 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 13:41:47.643623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 13:41:47.643676 ==
4114 13:41:47.643728
4115 13:41:47.643780
4116 13:41:47.643832 TX Vref Scan disable
4117 13:41:47.643884 == TX Byte 0 ==
4118 13:41:47.643937 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4119 13:41:47.643989 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4120 13:41:47.644041 == TX Byte 1 ==
4121 13:41:47.644093 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4122 13:41:47.644145 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4123 13:41:47.644197 ==
4124 13:41:47.644249 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 13:41:47.644301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 13:41:47.644353 ==
4127 13:41:47.644405
4128 13:41:47.644457
4129 13:41:47.644509 TX Vref Scan disable
4130 13:41:47.644560 == TX Byte 0 ==
4131 13:41:47.644612 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4132 13:41:47.644665 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4133 13:41:47.644718 == TX Byte 1 ==
4134 13:41:47.644773 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4135 13:41:47.644826 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4136 13:41:47.644878
4137 13:41:47.644930 [DATLAT]
4138 13:41:47.644982 Freq=600, CH0 RK0
4139 13:41:47.645034
4140 13:41:47.645086 DATLAT Default: 0x9
4141 13:41:47.645138 0, 0xFFFF, sum = 0
4142 13:41:47.645192 1, 0xFFFF, sum = 0
4143 13:41:47.645245 2, 0xFFFF, sum = 0
4144 13:41:47.645298 3, 0xFFFF, sum = 0
4145 13:41:47.645351 4, 0xFFFF, sum = 0
4146 13:41:47.645404 5, 0xFFFF, sum = 0
4147 13:41:47.645458 6, 0xFFFF, sum = 0
4148 13:41:47.645511 7, 0xFFFF, sum = 0
4149 13:41:47.645564 8, 0x0, sum = 1
4150 13:41:47.645618 9, 0x0, sum = 2
4151 13:41:47.645671 10, 0x0, sum = 3
4152 13:41:47.645724 11, 0x0, sum = 4
4153 13:41:47.645777 best_step = 9
4154 13:41:47.645829
4155 13:41:47.645881 ==
4156 13:41:47.645933 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 13:41:47.646202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 13:41:47.646275 ==
4159 13:41:47.646330 RX Vref Scan: 1
4160 13:41:47.646384
4161 13:41:47.646442 RX Vref 0 -> 0, step: 1
4162 13:41:47.646513
4163 13:41:47.646567 RX Delay -195 -> 252, step: 8
4164 13:41:47.646621
4165 13:41:47.646673 Set Vref, RX VrefLevel [Byte0]: 60
4166 13:41:47.646726 [Byte1]: 50
4167 13:41:47.646779
4168 13:41:47.646831 Final RX Vref Byte 0 = 60 to rank0
4169 13:41:47.646884 Final RX Vref Byte 1 = 50 to rank0
4170 13:41:47.646937 Final RX Vref Byte 0 = 60 to rank1
4171 13:41:47.646990 Final RX Vref Byte 1 = 50 to rank1==
4172 13:41:47.647043 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 13:41:47.647095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 13:41:47.647148 ==
4175 13:41:47.647200 DQS Delay:
4176 13:41:47.647252 DQS0 = 0, DQS1 = 0
4177 13:41:47.647305 DQM Delay:
4178 13:41:47.647357 DQM0 = 43, DQM1 = 32
4179 13:41:47.647410 DQ Delay:
4180 13:41:47.647462 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4181 13:41:47.647514 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4182 13:41:47.647567 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4183 13:41:47.647619 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4184 13:41:47.647672
4185 13:41:47.647724
4186 13:41:47.647775 [DQSOSCAuto] RK0, (LSB)MR18= 0x673f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4187 13:41:47.647829 CH0 RK0: MR19=808, MR18=673F
4188 13:41:47.647882 CH0_RK0: MR19=0x808, MR18=0x673F, DQSOSC=390, MR23=63, INC=172, DEC=114
4189 13:41:47.647935
4190 13:41:47.647986 ----->DramcWriteLeveling(PI) begin...
4191 13:41:47.648040 ==
4192 13:41:47.648093 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 13:41:47.648145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 13:41:47.648198 ==
4195 13:41:47.648250 Write leveling (Byte 0): 33 => 33
4196 13:41:47.648303 Write leveling (Byte 1): 29 => 29
4197 13:41:47.648356 DramcWriteLeveling(PI) end<-----
4198 13:41:47.648408
4199 13:41:47.648460 ==
4200 13:41:47.648512 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 13:41:47.648564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 13:41:47.648617 ==
4203 13:41:47.648669 [Gating] SW mode calibration
4204 13:41:47.648721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 13:41:47.648775 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 13:41:47.648827 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 13:41:47.648881 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 13:41:47.648934 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 13:41:47.648988 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4210 13:41:47.649041 0 9 16 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
4211 13:41:47.649093 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 13:41:47.649146 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 13:41:47.649198 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 13:41:47.649251 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 13:41:47.649303 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 13:41:47.649355 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 13:41:47.649407 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4218 13:41:47.649460 0 10 16 | B1->B0 | 3636 3e3e | 0 1 | (0 0) (0 0)
4219 13:41:47.649512 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 13:41:47.649565 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 13:41:47.649617 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 13:41:47.649669 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 13:41:47.649721 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 13:41:47.649773 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 13:41:47.649825 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4226 13:41:47.649878 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4227 13:41:47.649930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 13:41:47.649983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 13:41:47.650035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 13:41:47.650087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 13:41:47.650139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 13:41:47.650235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 13:41:47.650289 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 13:41:47.650342 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 13:41:47.650394 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 13:41:47.650447 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 13:41:47.650500 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 13:41:47.650552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 13:41:47.650605 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 13:41:47.650658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 13:41:47.650710 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 13:41:47.650763 Total UI for P1: 0, mck2ui 16
4243 13:41:47.650816 best dqsien dly found for B0: ( 0, 13, 10)
4244 13:41:47.650869 Total UI for P1: 0, mck2ui 16
4245 13:41:47.650953 best dqsien dly found for B1: ( 0, 13, 10)
4246 13:41:47.651005 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4247 13:41:47.651058 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4248 13:41:47.651111
4249 13:41:47.651163 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4250 13:41:47.651215 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4251 13:41:47.651268 [Gating] SW calibration Done
4252 13:41:47.651319 ==
4253 13:41:47.651371 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 13:41:47.651424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 13:41:47.651477 ==
4256 13:41:47.651530 RX Vref Scan: 0
4257 13:41:47.651582
4258 13:41:47.651634 RX Vref 0 -> 0, step: 1
4259 13:41:47.651687
4260 13:41:47.651738 RX Delay -230 -> 252, step: 16
4261 13:41:47.651791 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4262 13:41:47.651843 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4263 13:41:47.651895 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4264 13:41:47.651947 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4265 13:41:47.651999 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4266 13:41:47.652051 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4267 13:41:47.652104 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4268 13:41:47.652156 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4269 13:41:47.652413 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4270 13:41:47.652474 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4271 13:41:47.652528 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4272 13:41:47.652581 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4273 13:41:47.652634 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4274 13:41:47.652687 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4275 13:41:47.652739 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4276 13:41:47.652792 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4277 13:41:47.652844 ==
4278 13:41:47.652926 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 13:41:47.653026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 13:41:47.653093 ==
4281 13:41:47.653146 DQS Delay:
4282 13:41:47.653199 DQS0 = 0, DQS1 = 0
4283 13:41:47.653251 DQM Delay:
4284 13:41:47.653303 DQM0 = 41, DQM1 = 34
4285 13:41:47.653355 DQ Delay:
4286 13:41:47.653408 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4287 13:41:47.653460 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4288 13:41:47.653513 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4289 13:41:47.653565 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =33
4290 13:41:47.653632
4291 13:41:47.653691
4292 13:41:47.653744 ==
4293 13:41:47.653796 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 13:41:47.653849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 13:41:47.653902 ==
4296 13:41:47.653953
4297 13:41:47.654005
4298 13:41:47.654057 TX Vref Scan disable
4299 13:41:47.654109 == TX Byte 0 ==
4300 13:41:47.654185 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4301 13:41:47.654259 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4302 13:41:47.654312 == TX Byte 1 ==
4303 13:41:47.654364 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4304 13:41:47.654416 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4305 13:41:47.654468 ==
4306 13:41:47.654519 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 13:41:47.654571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 13:41:47.654622 ==
4309 13:41:47.654674
4310 13:41:47.654725
4311 13:41:47.654776 TX Vref Scan disable
4312 13:41:47.654828 == TX Byte 0 ==
4313 13:41:47.654879 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4314 13:41:47.654931 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4315 13:41:47.654983 == TX Byte 1 ==
4316 13:41:47.655034 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4317 13:41:47.655085 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4318 13:41:47.655137
4319 13:41:47.655188 [DATLAT]
4320 13:41:47.655239 Freq=600, CH0 RK1
4321 13:41:47.655291
4322 13:41:47.655343 DATLAT Default: 0x9
4323 13:41:47.655395 0, 0xFFFF, sum = 0
4324 13:41:47.655448 1, 0xFFFF, sum = 0
4325 13:41:47.655500 2, 0xFFFF, sum = 0
4326 13:41:47.655553 3, 0xFFFF, sum = 0
4327 13:41:47.655606 4, 0xFFFF, sum = 0
4328 13:41:47.655659 5, 0xFFFF, sum = 0
4329 13:41:47.655711 6, 0xFFFF, sum = 0
4330 13:41:47.655763 7, 0xFFFF, sum = 0
4331 13:41:47.655815 8, 0x0, sum = 1
4332 13:41:47.655868 9, 0x0, sum = 2
4333 13:41:47.655920 10, 0x0, sum = 3
4334 13:41:47.655973 11, 0x0, sum = 4
4335 13:41:47.656026 best_step = 9
4336 13:41:47.656077
4337 13:41:47.656128 ==
4338 13:41:47.656181 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 13:41:47.656234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 13:41:47.656287 ==
4341 13:41:47.656339 RX Vref Scan: 0
4342 13:41:47.656390
4343 13:41:47.656442 RX Vref 0 -> 0, step: 1
4344 13:41:47.656493
4345 13:41:47.656544 RX Delay -195 -> 252, step: 8
4346 13:41:47.656596 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4347 13:41:47.656648 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4348 13:41:47.656700 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4349 13:41:47.656752 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4350 13:41:47.656804 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4351 13:41:47.656855 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4352 13:41:47.656907 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4353 13:41:47.656959 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4354 13:41:47.657010 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4355 13:41:47.657062 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4356 13:41:47.657113 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4357 13:41:47.657165 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4358 13:41:47.657217 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4359 13:41:47.657270 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4360 13:41:47.657321 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4361 13:41:47.657372 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4362 13:41:47.657424 ==
4363 13:41:47.657476 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 13:41:47.657528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 13:41:47.657580 ==
4366 13:41:47.657632 DQS Delay:
4367 13:41:47.657683 DQS0 = 0, DQS1 = 0
4368 13:41:47.657735 DQM Delay:
4369 13:41:47.657786 DQM0 = 41, DQM1 = 34
4370 13:41:47.657838 DQ Delay:
4371 13:41:47.657889 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4372 13:41:47.657941 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4373 13:41:47.657992 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4374 13:41:47.658044 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4375 13:41:47.658095
4376 13:41:47.658146
4377 13:41:47.658249 [DQSOSCAuto] RK1, (LSB)MR18= 0x6518, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4378 13:41:47.658305 CH0 RK1: MR19=808, MR18=6518
4379 13:41:47.658358 CH0_RK1: MR19=0x808, MR18=0x6518, DQSOSC=390, MR23=63, INC=172, DEC=114
4380 13:41:47.658411 [RxdqsGatingPostProcess] freq 600
4381 13:41:47.658464 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4382 13:41:47.658516 Pre-setting of DQS Precalculation
4383 13:41:47.658568 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4384 13:41:47.658620 ==
4385 13:41:47.658673 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 13:41:47.658724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 13:41:47.658777 ==
4388 13:41:47.658829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4389 13:41:47.658882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4390 13:41:47.658937 [CA 0] Center 36 (6~66) winsize 61
4391 13:41:47.659068 [CA 1] Center 35 (5~66) winsize 62
4392 13:41:47.659222 [CA 2] Center 34 (4~65) winsize 62
4393 13:41:47.659349 [CA 3] Center 33 (3~64) winsize 62
4394 13:41:47.659407 [CA 4] Center 34 (4~65) winsize 62
4395 13:41:47.659461 [CA 5] Center 33 (3~64) winsize 62
4396 13:41:47.659513
4397 13:41:47.659565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4398 13:41:47.659617
4399 13:41:47.659670 [CATrainingPosCal] consider 1 rank data
4400 13:41:47.659722 u2DelayCellTimex100 = 270/100 ps
4401 13:41:47.659774 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4402 13:41:47.659826 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 13:41:47.659878 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 13:41:47.659931 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 13:41:47.660179 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 13:41:47.660238 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 13:41:47.660291
4408 13:41:47.660344 CA PerBit enable=1, Macro0, CA PI delay=33
4409 13:41:47.660397
4410 13:41:47.660449 [CBTSetCACLKResult] CA Dly = 33
4411 13:41:47.660505 CS Dly: 4 (0~35)
4412 13:41:47.660600 ==
4413 13:41:47.660670 Dram Type= 6, Freq= 0, CH_1, rank 1
4414 13:41:47.660725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 13:41:47.660779 ==
4416 13:41:47.660848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 13:41:47.660916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4418 13:41:47.660969 [CA 0] Center 35 (5~66) winsize 62
4419 13:41:47.661021 [CA 1] Center 36 (6~66) winsize 61
4420 13:41:47.661073 [CA 2] Center 34 (4~65) winsize 62
4421 13:41:47.661125 [CA 3] Center 34 (3~65) winsize 63
4422 13:41:47.661176 [CA 4] Center 34 (4~65) winsize 62
4423 13:41:47.661228 [CA 5] Center 34 (3~65) winsize 63
4424 13:41:47.661280
4425 13:41:47.661331 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4426 13:41:47.661383
4427 13:41:47.661435 [CATrainingPosCal] consider 2 rank data
4428 13:41:47.661487 u2DelayCellTimex100 = 270/100 ps
4429 13:41:47.661539 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4430 13:41:47.661591 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 13:41:47.661643 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 13:41:47.661695 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 13:41:47.661746 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 13:41:47.661798 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 13:41:47.661850
4436 13:41:47.661901 CA PerBit enable=1, Macro0, CA PI delay=33
4437 13:41:47.661953
4438 13:41:47.662005 [CBTSetCACLKResult] CA Dly = 33
4439 13:41:47.662057 CS Dly: 4 (0~36)
4440 13:41:47.662108
4441 13:41:47.662159 ----->DramcWriteLeveling(PI) begin...
4442 13:41:47.662255 ==
4443 13:41:47.662308 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 13:41:47.662360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 13:41:47.662415 ==
4446 13:41:47.662467 Write leveling (Byte 0): 29 => 29
4447 13:41:47.662519 Write leveling (Byte 1): 29 => 29
4448 13:41:47.662571 DramcWriteLeveling(PI) end<-----
4449 13:41:47.662623
4450 13:41:47.662674 ==
4451 13:41:47.662727 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 13:41:47.662778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 13:41:47.662831 ==
4454 13:41:47.662882 [Gating] SW mode calibration
4455 13:41:47.662934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4456 13:41:47.662988 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4457 13:41:47.663041 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 13:41:47.663094 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 13:41:47.663146 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 13:41:47.663198 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 1)
4461 13:41:47.663251 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4462 13:41:47.663303 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 13:41:47.663354 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 13:41:47.663406 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 13:41:47.663458 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 13:41:47.663509 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 13:41:47.663561 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 13:41:47.663613 0 10 12 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
4469 13:41:47.663665 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 13:41:47.663716 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 13:41:47.663768 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 13:41:47.663820 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 13:41:47.663872 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:41:47.663923 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:41:47.663975 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 13:41:47.664027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4477 13:41:47.664079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 13:41:47.664131 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 13:41:47.664206 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 13:41:47.664263 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:41:47.664316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:41:47.664368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:41:47.664420 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:41:47.664473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:41:47.664525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:41:47.664577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 13:41:47.664629 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 13:41:47.664681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:41:47.664734 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:41:47.664786 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:41:47.664838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:41:47.664889 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4493 13:41:47.664941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 13:41:47.664993 Total UI for P1: 0, mck2ui 16
4495 13:41:47.665045 best dqsien dly found for B0: ( 0, 13, 14)
4496 13:41:47.665097 Total UI for P1: 0, mck2ui 16
4497 13:41:47.665149 best dqsien dly found for B1: ( 0, 13, 12)
4498 13:41:47.665200 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4499 13:41:47.665252 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4500 13:41:47.665303
4501 13:41:47.665355 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4502 13:41:47.665406 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4503 13:41:47.665458 [Gating] SW calibration Done
4504 13:41:47.665510 ==
4505 13:41:47.665562 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 13:41:47.665614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 13:41:47.665666 ==
4508 13:41:47.665718 RX Vref Scan: 0
4509 13:41:47.665771
4510 13:41:47.665822 RX Vref 0 -> 0, step: 1
4511 13:41:47.665874
4512 13:41:47.665925 RX Delay -230 -> 252, step: 16
4513 13:41:47.665977 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4514 13:41:47.666238 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4515 13:41:47.666298 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 13:41:47.666352 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 13:41:47.666405 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 13:41:47.666458 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4519 13:41:47.666510 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4520 13:41:47.666563 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4521 13:41:47.666615 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4522 13:41:47.666667 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4523 13:41:47.666719 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 13:41:47.666771 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4525 13:41:47.666823 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 13:41:47.666876 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4527 13:41:47.666928 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4528 13:41:47.666980 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4529 13:41:47.667032 ==
4530 13:41:47.667084 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 13:41:47.667136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 13:41:47.667188 ==
4533 13:41:47.667240 DQS Delay:
4534 13:41:47.667292 DQS0 = 0, DQS1 = 0
4535 13:41:47.667344 DQM Delay:
4536 13:41:47.667406 DQM0 = 46, DQM1 = 36
4537 13:41:47.667470 DQ Delay:
4538 13:41:47.667523 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4539 13:41:47.667576 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4540 13:41:47.667628 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4541 13:41:47.667681 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4542 13:41:47.667732
4543 13:41:47.667784
4544 13:41:47.667835 ==
4545 13:41:47.667888 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 13:41:47.667940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 13:41:47.667993 ==
4548 13:41:47.668045
4549 13:41:47.668096
4550 13:41:47.668147 TX Vref Scan disable
4551 13:41:47.668199 == TX Byte 0 ==
4552 13:41:47.668251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4553 13:41:47.668303 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4554 13:41:47.668356 == TX Byte 1 ==
4555 13:41:47.668407 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4556 13:41:47.668460 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4557 13:41:47.668512 ==
4558 13:41:47.668564 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 13:41:47.668617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 13:41:47.668670 ==
4561 13:41:47.668722
4562 13:41:47.668773
4563 13:41:47.668824 TX Vref Scan disable
4564 13:41:47.668876 == TX Byte 0 ==
4565 13:41:47.668927 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 13:41:47.668997 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 13:41:47.669052 == TX Byte 1 ==
4568 13:41:47.669104 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4569 13:41:47.669157 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4570 13:41:47.669224
4571 13:41:47.669277 [DATLAT]
4572 13:41:47.669328 Freq=600, CH1 RK0
4573 13:41:47.669405
4574 13:41:47.669461 DATLAT Default: 0x9
4575 13:41:47.669530 0, 0xFFFF, sum = 0
4576 13:41:47.669588 1, 0xFFFF, sum = 0
4577 13:41:47.669641 2, 0xFFFF, sum = 0
4578 13:41:47.669695 3, 0xFFFF, sum = 0
4579 13:41:47.669748 4, 0xFFFF, sum = 0
4580 13:41:47.669801 5, 0xFFFF, sum = 0
4581 13:41:47.669854 6, 0xFFFF, sum = 0
4582 13:41:47.669906 7, 0xFFFF, sum = 0
4583 13:41:47.669959 8, 0x0, sum = 1
4584 13:41:47.670011 9, 0x0, sum = 2
4585 13:41:47.670064 10, 0x0, sum = 3
4586 13:41:47.670116 11, 0x0, sum = 4
4587 13:41:47.670196 best_step = 9
4588 13:41:47.670264
4589 13:41:47.670316 ==
4590 13:41:47.670368 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 13:41:47.670421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 13:41:47.670473 ==
4593 13:41:47.670525 RX Vref Scan: 1
4594 13:41:47.670577
4595 13:41:47.670641 RX Vref 0 -> 0, step: 1
4596 13:41:47.670696
4597 13:41:47.670749 RX Delay -195 -> 252, step: 8
4598 13:41:47.670801
4599 13:41:47.671678 Set Vref, RX VrefLevel [Byte0]: 48
4600 13:41:47.675324 [Byte1]: 60
4601 13:41:47.680133
4602 13:41:47.680221 Final RX Vref Byte 0 = 48 to rank0
4603 13:41:47.683380 Final RX Vref Byte 1 = 60 to rank0
4604 13:41:47.686462 Final RX Vref Byte 0 = 48 to rank1
4605 13:41:47.689797 Final RX Vref Byte 1 = 60 to rank1==
4606 13:41:47.693119 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 13:41:47.699682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 13:41:47.699764 ==
4609 13:41:47.699828 DQS Delay:
4610 13:41:47.702934 DQS0 = 0, DQS1 = 0
4611 13:41:47.703016 DQM Delay:
4612 13:41:47.703080 DQM0 = 47, DQM1 = 37
4613 13:41:47.706120 DQ Delay:
4614 13:41:47.709558 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4615 13:41:47.713085 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4616 13:41:47.715787 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4617 13:41:47.719481 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4618 13:41:47.719561
4619 13:41:47.719625
4620 13:41:47.726063 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4621 13:41:47.729352 CH1 RK0: MR19=808, MR18=4F34
4622 13:41:47.736135 CH1_RK0: MR19=0x808, MR18=0x4F34, DQSOSC=394, MR23=63, INC=168, DEC=112
4623 13:41:47.736223
4624 13:41:47.739307 ----->DramcWriteLeveling(PI) begin...
4625 13:41:47.739390 ==
4626 13:41:47.742602 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 13:41:47.745810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 13:41:47.745892 ==
4629 13:41:47.749427 Write leveling (Byte 0): 31 => 31
4630 13:41:47.752277 Write leveling (Byte 1): 29 => 29
4631 13:41:47.755517 DramcWriteLeveling(PI) end<-----
4632 13:41:47.755597
4633 13:41:47.755661 ==
4634 13:41:47.758842 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 13:41:47.762614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 13:41:47.765402 ==
4637 13:41:47.765484 [Gating] SW mode calibration
4638 13:41:47.771986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4639 13:41:47.778886 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4640 13:41:47.782211 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 13:41:47.788955 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 13:41:47.792074 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 13:41:47.795569 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 0)
4644 13:41:47.802204 0 9 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4645 13:41:47.804918 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 13:41:47.808668 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 13:41:47.815072 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 13:41:47.818312 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 13:41:47.821695 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 13:41:47.828246 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 13:41:47.831544 0 10 12 | B1->B0 | 3737 2b2b | 0 1 | (1 1) (0 0)
4652 13:41:47.834813 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 13:41:47.841469 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 13:41:47.844813 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 13:41:47.848236 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 13:41:47.854369 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 13:41:47.858214 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 13:41:47.861496 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 13:41:47.867796 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4660 13:41:47.871090 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 13:41:47.874259 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 13:41:47.881071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 13:41:47.884705 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 13:41:47.887767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 13:41:47.894359 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 13:41:47.897417 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 13:41:47.900692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 13:41:47.907403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 13:41:47.910604 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 13:41:47.913857 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 13:41:47.920543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 13:41:47.923693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 13:41:47.926735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 13:41:47.934052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 13:41:47.937283 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4676 13:41:47.939942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 13:41:47.943336 Total UI for P1: 0, mck2ui 16
4678 13:41:47.947306 best dqsien dly found for B0: ( 0, 13, 14)
4679 13:41:47.949783 Total UI for P1: 0, mck2ui 16
4680 13:41:47.953194 best dqsien dly found for B1: ( 0, 13, 12)
4681 13:41:47.956526 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4682 13:41:47.963495 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4683 13:41:47.963580
4684 13:41:47.966784 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4685 13:41:47.970070 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4686 13:41:47.973518 [Gating] SW calibration Done
4687 13:41:47.973599 ==
4688 13:41:47.976710 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 13:41:47.979782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 13:41:47.979864 ==
4691 13:41:47.979928 RX Vref Scan: 0
4692 13:41:47.983305
4693 13:41:47.983386 RX Vref 0 -> 0, step: 1
4694 13:41:47.983450
4695 13:41:47.986437 RX Delay -230 -> 252, step: 16
4696 13:41:47.989792 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4697 13:41:47.995994 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4698 13:41:47.999440 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4699 13:41:48.002679 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4700 13:41:48.006283 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4701 13:41:48.009413 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4702 13:41:48.015945 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4703 13:41:48.019233 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4704 13:41:48.022544 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4705 13:41:48.025823 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4706 13:41:48.033003 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4707 13:41:48.036337 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4708 13:41:48.039488 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4709 13:41:48.042849 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4710 13:41:48.049117 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4711 13:41:48.052522 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4712 13:41:48.052604 ==
4713 13:41:48.055867 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 13:41:48.059282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 13:41:48.059365 ==
4716 13:41:48.062477 DQS Delay:
4717 13:41:48.062559 DQS0 = 0, DQS1 = 0
4718 13:41:48.062625 DQM Delay:
4719 13:41:48.065595 DQM0 = 44, DQM1 = 37
4720 13:41:48.065677 DQ Delay:
4721 13:41:48.068995 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4722 13:41:48.072207 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4723 13:41:48.075510 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4724 13:41:48.078873 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4725 13:41:48.078954
4726 13:41:48.079018
4727 13:41:48.079077 ==
4728 13:41:48.082054 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 13:41:48.089093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 13:41:48.089176 ==
4731 13:41:48.089241
4732 13:41:48.089302
4733 13:41:48.089359 TX Vref Scan disable
4734 13:41:48.092517 == TX Byte 0 ==
4735 13:41:48.095835 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4736 13:41:48.102535 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4737 13:41:48.102616 == TX Byte 1 ==
4738 13:41:48.106561 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4739 13:41:48.112562 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4740 13:41:48.112645 ==
4741 13:41:48.115673 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 13:41:48.118984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 13:41:48.119066 ==
4744 13:41:48.119131
4745 13:41:48.119191
4746 13:41:48.122119 TX Vref Scan disable
4747 13:41:48.125528 == TX Byte 0 ==
4748 13:41:48.129198 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4749 13:41:48.132222 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4750 13:41:48.135537 == TX Byte 1 ==
4751 13:41:48.138739 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4752 13:41:48.142050 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4753 13:41:48.142132
4754 13:41:48.145399 [DATLAT]
4755 13:41:48.145485 Freq=600, CH1 RK1
4756 13:41:48.145551
4757 13:41:48.148690 DATLAT Default: 0x9
4758 13:41:48.148774 0, 0xFFFF, sum = 0
4759 13:41:48.152132 1, 0xFFFF, sum = 0
4760 13:41:48.152215 2, 0xFFFF, sum = 0
4761 13:41:48.155589 3, 0xFFFF, sum = 0
4762 13:41:48.155673 4, 0xFFFF, sum = 0
4763 13:41:48.158278 5, 0xFFFF, sum = 0
4764 13:41:48.158361 6, 0xFFFF, sum = 0
4765 13:41:48.162056 7, 0xFFFF, sum = 0
4766 13:41:48.162188 8, 0x0, sum = 1
4767 13:41:48.165301 9, 0x0, sum = 2
4768 13:41:48.165385 10, 0x0, sum = 3
4769 13:41:48.168680 11, 0x0, sum = 4
4770 13:41:48.168763 best_step = 9
4771 13:41:48.168828
4772 13:41:48.168888 ==
4773 13:41:48.171964 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 13:41:48.175282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 13:41:48.178716 ==
4776 13:41:48.178798 RX Vref Scan: 0
4777 13:41:48.178863
4778 13:41:48.181843 RX Vref 0 -> 0, step: 1
4779 13:41:48.181926
4780 13:41:48.185204 RX Delay -195 -> 252, step: 8
4781 13:41:48.188012 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4782 13:41:48.191812 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4783 13:41:48.198482 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4784 13:41:48.201316 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4785 13:41:48.204479 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4786 13:41:48.207777 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4787 13:41:48.215014 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4788 13:41:48.217666 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4789 13:41:48.221326 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4790 13:41:48.224611 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4791 13:41:48.227668 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4792 13:41:48.234105 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4793 13:41:48.237561 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4794 13:41:48.240829 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4795 13:41:48.247490 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4796 13:41:48.250530 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4797 13:41:48.250614 ==
4798 13:41:48.254055 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 13:41:48.257323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 13:41:48.257407 ==
4801 13:41:48.260492 DQS Delay:
4802 13:41:48.260575 DQS0 = 0, DQS1 = 0
4803 13:41:48.260642 DQM Delay:
4804 13:41:48.263661 DQM0 = 45, DQM1 = 37
4805 13:41:48.263744 DQ Delay:
4806 13:41:48.267123 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4807 13:41:48.270451 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4808 13:41:48.273756 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4809 13:41:48.277175 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4810 13:41:48.277259
4811 13:41:48.277326
4812 13:41:48.286985 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4813 13:41:48.287070 CH1 RK1: MR19=808, MR18=2B20
4814 13:41:48.293828 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4815 13:41:48.297114 [RxdqsGatingPostProcess] freq 600
4816 13:41:48.303421 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4817 13:41:48.307054 Pre-setting of DQS Precalculation
4818 13:41:48.309626 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4819 13:41:48.320163 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4820 13:41:48.326692 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4821 13:41:48.326773
4822 13:41:48.326845
4823 13:41:48.329694 [Calibration Summary] 1200 Mbps
4824 13:41:48.329768 CH 0, Rank 0
4825 13:41:48.333158 SW Impedance : PASS
4826 13:41:48.333236 DUTY Scan : NO K
4827 13:41:48.336467 ZQ Calibration : PASS
4828 13:41:48.339644 Jitter Meter : NO K
4829 13:41:48.339718 CBT Training : PASS
4830 13:41:48.342953 Write leveling : PASS
4831 13:41:48.346310 RX DQS gating : PASS
4832 13:41:48.346392 RX DQ/DQS(RDDQC) : PASS
4833 13:41:48.349677 TX DQ/DQS : PASS
4834 13:41:48.352626 RX DATLAT : PASS
4835 13:41:48.352709 RX DQ/DQS(Engine): PASS
4836 13:41:48.355949 TX OE : NO K
4837 13:41:48.356033 All Pass.
4838 13:41:48.356099
4839 13:41:48.359751 CH 0, Rank 1
4840 13:41:48.359833 SW Impedance : PASS
4841 13:41:48.362712 DUTY Scan : NO K
4842 13:41:48.365917 ZQ Calibration : PASS
4843 13:41:48.366018 Jitter Meter : NO K
4844 13:41:48.369545 CBT Training : PASS
4845 13:41:48.369618 Write leveling : PASS
4846 13:41:48.372783 RX DQS gating : PASS
4847 13:41:48.375828 RX DQ/DQS(RDDQC) : PASS
4848 13:41:48.375911 TX DQ/DQS : PASS
4849 13:41:48.379340 RX DATLAT : PASS
4850 13:41:48.382361 RX DQ/DQS(Engine): PASS
4851 13:41:48.382443 TX OE : NO K
4852 13:41:48.386108 All Pass.
4853 13:41:48.386230
4854 13:41:48.386297 CH 1, Rank 0
4855 13:41:48.389472 SW Impedance : PASS
4856 13:41:48.389554 DUTY Scan : NO K
4857 13:41:48.392660 ZQ Calibration : PASS
4858 13:41:48.395828 Jitter Meter : NO K
4859 13:41:48.395911 CBT Training : PASS
4860 13:41:48.399127 Write leveling : PASS
4861 13:41:48.402305 RX DQS gating : PASS
4862 13:41:48.402388 RX DQ/DQS(RDDQC) : PASS
4863 13:41:48.405734 TX DQ/DQS : PASS
4864 13:41:48.408890 RX DATLAT : PASS
4865 13:41:48.408973 RX DQ/DQS(Engine): PASS
4866 13:41:48.412421 TX OE : NO K
4867 13:41:48.412503 All Pass.
4868 13:41:48.412569
4869 13:41:48.415697 CH 1, Rank 1
4870 13:41:48.415779 SW Impedance : PASS
4871 13:41:48.418953 DUTY Scan : NO K
4872 13:41:48.422371 ZQ Calibration : PASS
4873 13:41:48.422453 Jitter Meter : NO K
4874 13:41:48.425437 CBT Training : PASS
4875 13:41:48.429123 Write leveling : PASS
4876 13:41:48.429208 RX DQS gating : PASS
4877 13:41:48.432027 RX DQ/DQS(RDDQC) : PASS
4878 13:41:48.435204 TX DQ/DQS : PASS
4879 13:41:48.435289 RX DATLAT : PASS
4880 13:41:48.438848 RX DQ/DQS(Engine): PASS
4881 13:41:48.438960 TX OE : NO K
4882 13:41:48.442339 All Pass.
4883 13:41:48.442421
4884 13:41:48.442485 DramC Write-DBI off
4885 13:41:48.445536 PER_BANK_REFRESH: Hybrid Mode
4886 13:41:48.448867 TX_TRACKING: ON
4887 13:41:48.455332 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4888 13:41:48.458626 [FAST_K] Save calibration result to emmc
4889 13:41:48.465185 dramc_set_vcore_voltage set vcore to 662500
4890 13:41:48.465298 Read voltage for 933, 3
4891 13:41:48.465393 Vio18 = 0
4892 13:41:48.468506 Vcore = 662500
4893 13:41:48.468588 Vdram = 0
4894 13:41:48.468654 Vddq = 0
4895 13:41:48.471747 Vmddr = 0
4896 13:41:48.474780 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4897 13:41:48.481419 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4898 13:41:48.485002 MEM_TYPE=3, freq_sel=17
4899 13:41:48.485086 sv_algorithm_assistance_LP4_1600
4900 13:41:48.491507 ============ PULL DRAM RESETB DOWN ============
4901 13:41:48.494959 ========== PULL DRAM RESETB DOWN end =========
4902 13:41:48.498126 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4903 13:41:48.501396 ===================================
4904 13:41:48.504447 LPDDR4 DRAM CONFIGURATION
4905 13:41:48.508118 ===================================
4906 13:41:48.511563 EX_ROW_EN[0] = 0x0
4907 13:41:48.511646 EX_ROW_EN[1] = 0x0
4908 13:41:48.514743 LP4Y_EN = 0x0
4909 13:41:48.514856 WORK_FSP = 0x0
4910 13:41:48.517971 WL = 0x3
4911 13:41:48.518053 RL = 0x3
4912 13:41:48.521310 BL = 0x2
4913 13:41:48.521391 RPST = 0x0
4914 13:41:48.524672 RD_PRE = 0x0
4915 13:41:48.524764 WR_PRE = 0x1
4916 13:41:48.528150 WR_PST = 0x0
4917 13:41:48.528232 DBI_WR = 0x0
4918 13:41:48.531229 DBI_RD = 0x0
4919 13:41:48.534536 OTF = 0x1
4920 13:41:48.537856 ===================================
4921 13:41:48.541149 ===================================
4922 13:41:48.541232 ANA top config
4923 13:41:48.544360 ===================================
4924 13:41:48.547907 DLL_ASYNC_EN = 0
4925 13:41:48.547989 ALL_SLAVE_EN = 1
4926 13:41:48.550974 NEW_RANK_MODE = 1
4927 13:41:48.554091 DLL_IDLE_MODE = 1
4928 13:41:48.557457 LP45_APHY_COMB_EN = 1
4929 13:41:48.561303 TX_ODT_DIS = 1
4930 13:41:48.561385 NEW_8X_MODE = 1
4931 13:41:48.564416 ===================================
4932 13:41:48.567267 ===================================
4933 13:41:48.570615 data_rate = 1866
4934 13:41:48.574350 CKR = 1
4935 13:41:48.577792 DQ_P2S_RATIO = 8
4936 13:41:48.580926 ===================================
4937 13:41:48.583939 CA_P2S_RATIO = 8
4938 13:41:48.587444 DQ_CA_OPEN = 0
4939 13:41:48.587533 DQ_SEMI_OPEN = 0
4940 13:41:48.590443 CA_SEMI_OPEN = 0
4941 13:41:48.594263 CA_FULL_RATE = 0
4942 13:41:48.597384 DQ_CKDIV4_EN = 1
4943 13:41:48.600307 CA_CKDIV4_EN = 1
4944 13:41:48.604063 CA_PREDIV_EN = 0
4945 13:41:48.607114 PH8_DLY = 0
4946 13:41:48.607191 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4947 13:41:48.610147 DQ_AAMCK_DIV = 4
4948 13:41:48.613699 CA_AAMCK_DIV = 4
4949 13:41:48.616946 CA_ADMCK_DIV = 4
4950 13:41:48.620320 DQ_TRACK_CA_EN = 0
4951 13:41:48.623608 CA_PICK = 933
4952 13:41:48.623689 CA_MCKIO = 933
4953 13:41:48.626863 MCKIO_SEMI = 0
4954 13:41:48.630429 PLL_FREQ = 3732
4955 13:41:48.633615 DQ_UI_PI_RATIO = 32
4956 13:41:48.636898 CA_UI_PI_RATIO = 0
4957 13:41:48.639710 ===================================
4958 13:41:48.643650 ===================================
4959 13:41:48.646756 memory_type:LPDDR4
4960 13:41:48.646836 GP_NUM : 10
4961 13:41:48.650019 SRAM_EN : 1
4962 13:41:48.653318 MD32_EN : 0
4963 13:41:48.653399 ===================================
4964 13:41:48.656343 [ANA_INIT] >>>>>>>>>>>>>>
4965 13:41:48.659401 <<<<<< [CONFIGURE PHASE]: ANA_TX
4966 13:41:48.662846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4967 13:41:48.665916 ===================================
4968 13:41:48.669660 data_rate = 1866,PCW = 0X8f00
4969 13:41:48.672930 ===================================
4970 13:41:48.676151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4971 13:41:48.682619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 13:41:48.685961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 13:41:48.692438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4974 13:41:48.695805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4975 13:41:48.698838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4976 13:41:48.698920 [ANA_INIT] flow start
4977 13:41:48.702634 [ANA_INIT] PLL >>>>>>>>
4978 13:41:48.706100 [ANA_INIT] PLL <<<<<<<<
4979 13:41:48.709133 [ANA_INIT] MIDPI >>>>>>>>
4980 13:41:48.709215 [ANA_INIT] MIDPI <<<<<<<<
4981 13:41:48.712435 [ANA_INIT] DLL >>>>>>>>
4982 13:41:48.715631 [ANA_INIT] flow end
4983 13:41:48.718696 ============ LP4 DIFF to SE enter ============
4984 13:41:48.722656 ============ LP4 DIFF to SE exit ============
4985 13:41:48.725629 [ANA_INIT] <<<<<<<<<<<<<
4986 13:41:48.728948 [Flow] Enable top DCM control >>>>>
4987 13:41:48.732259 [Flow] Enable top DCM control <<<<<
4988 13:41:48.735674 Enable DLL master slave shuffle
4989 13:41:48.738420 ==============================================================
4990 13:41:48.741661 Gating Mode config
4991 13:41:48.748296 ==============================================================
4992 13:41:48.748378 Config description:
4993 13:41:48.758881 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4994 13:41:48.765495 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4995 13:41:48.771497 SELPH_MODE 0: By rank 1: By Phase
4996 13:41:48.774661 ==============================================================
4997 13:41:48.778430 GAT_TRACK_EN = 1
4998 13:41:48.781943 RX_GATING_MODE = 2
4999 13:41:48.784995 RX_GATING_TRACK_MODE = 2
5000 13:41:48.788337 SELPH_MODE = 1
5001 13:41:48.791462 PICG_EARLY_EN = 1
5002 13:41:48.794802 VALID_LAT_VALUE = 1
5003 13:41:48.798446 ==============================================================
5004 13:41:48.801431 Enter into Gating configuration >>>>
5005 13:41:48.804558 Exit from Gating configuration <<<<
5006 13:41:48.807678 Enter into DVFS_PRE_config >>>>>
5007 13:41:48.820801 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5008 13:41:48.824820 Exit from DVFS_PRE_config <<<<<
5009 13:41:48.827833 Enter into PICG configuration >>>>
5010 13:41:48.831075 Exit from PICG configuration <<<<
5011 13:41:48.831157 [RX_INPUT] configuration >>>>>
5012 13:41:48.834385 [RX_INPUT] configuration <<<<<
5013 13:41:48.841282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5014 13:41:48.843907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5015 13:41:48.850526 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 13:41:48.857372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 13:41:48.863858 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 13:41:48.870488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 13:41:48.873712 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5020 13:41:48.877420 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5021 13:41:48.883990 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5022 13:41:48.887437 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5023 13:41:48.890734 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5024 13:41:48.893800 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5025 13:41:48.896770 ===================================
5026 13:41:48.900301 LPDDR4 DRAM CONFIGURATION
5027 13:41:48.903567 ===================================
5028 13:41:48.906725 EX_ROW_EN[0] = 0x0
5029 13:41:48.906807 EX_ROW_EN[1] = 0x0
5030 13:41:48.910423 LP4Y_EN = 0x0
5031 13:41:48.910504 WORK_FSP = 0x0
5032 13:41:48.913419 WL = 0x3
5033 13:41:48.913500 RL = 0x3
5034 13:41:48.916673 BL = 0x2
5035 13:41:48.919915 RPST = 0x0
5036 13:41:48.919996 RD_PRE = 0x0
5037 13:41:48.923271 WR_PRE = 0x1
5038 13:41:48.923352 WR_PST = 0x0
5039 13:41:48.926475 DBI_WR = 0x0
5040 13:41:48.926556 DBI_RD = 0x0
5041 13:41:48.929838 OTF = 0x1
5042 13:41:48.933191 ===================================
5043 13:41:48.936852 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5044 13:41:48.940191 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5045 13:41:48.943453 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5046 13:41:48.947034 ===================================
5047 13:41:48.949559 LPDDR4 DRAM CONFIGURATION
5048 13:41:48.952890 ===================================
5049 13:41:48.956248 EX_ROW_EN[0] = 0x10
5050 13:41:48.956329 EX_ROW_EN[1] = 0x0
5051 13:41:48.959473 LP4Y_EN = 0x0
5052 13:41:48.959554 WORK_FSP = 0x0
5053 13:41:48.962698 WL = 0x3
5054 13:41:48.966047 RL = 0x3
5055 13:41:48.966153 BL = 0x2
5056 13:41:48.969495 RPST = 0x0
5057 13:41:48.969578 RD_PRE = 0x0
5058 13:41:48.972597 WR_PRE = 0x1
5059 13:41:48.972678 WR_PST = 0x0
5060 13:41:48.976089 DBI_WR = 0x0
5061 13:41:48.976170 DBI_RD = 0x0
5062 13:41:48.979417 OTF = 0x1
5063 13:41:48.982631 ===================================
5064 13:41:48.988854 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5065 13:41:48.992393 nWR fixed to 30
5066 13:41:48.992502 [ModeRegInit_LP4] CH0 RK0
5067 13:41:48.995968 [ModeRegInit_LP4] CH0 RK1
5068 13:41:48.999115 [ModeRegInit_LP4] CH1 RK0
5069 13:41:49.002384 [ModeRegInit_LP4] CH1 RK1
5070 13:41:49.002511 match AC timing 9
5071 13:41:49.005422 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5072 13:41:49.012169 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5073 13:41:49.015299 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5074 13:41:49.022082 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5075 13:41:49.025104 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5076 13:41:49.025219 ==
5077 13:41:49.028548 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 13:41:49.031895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 13:41:49.032006 ==
5080 13:41:49.038344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 13:41:49.045267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5082 13:41:49.048151 [CA 0] Center 37 (7~68) winsize 62
5083 13:41:49.051907 [CA 1] Center 37 (7~68) winsize 62
5084 13:41:49.055235 [CA 2] Center 34 (4~65) winsize 62
5085 13:41:49.058043 [CA 3] Center 34 (4~65) winsize 62
5086 13:41:49.061379 [CA 4] Center 33 (3~64) winsize 62
5087 13:41:49.064472 [CA 5] Center 33 (3~63) winsize 61
5088 13:41:49.064614
5089 13:41:49.068458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5090 13:41:49.068580
5091 13:41:49.071110 [CATrainingPosCal] consider 1 rank data
5092 13:41:49.074589 u2DelayCellTimex100 = 270/100 ps
5093 13:41:49.077825 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5094 13:41:49.081071 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5095 13:41:49.084478 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5096 13:41:49.087934 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5097 13:41:49.091351 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5098 13:41:49.094731 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5099 13:41:49.094850
5100 13:41:49.100977 CA PerBit enable=1, Macro0, CA PI delay=33
5101 13:41:49.101089
5102 13:41:49.104110 [CBTSetCACLKResult] CA Dly = 33
5103 13:41:49.104215 CS Dly: 7 (0~38)
5104 13:41:49.104314 ==
5105 13:41:49.108024 Dram Type= 6, Freq= 0, CH_0, rank 1
5106 13:41:49.110922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 13:41:49.111027 ==
5108 13:41:49.117362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 13:41:49.124111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5110 13:41:49.127569 [CA 0] Center 37 (7~68) winsize 62
5111 13:41:49.130485 [CA 1] Center 37 (7~68) winsize 62
5112 13:41:49.134289 [CA 2] Center 34 (4~65) winsize 62
5113 13:41:49.137428 [CA 3] Center 34 (4~65) winsize 62
5114 13:41:49.141169 [CA 4] Center 33 (3~64) winsize 62
5115 13:41:49.144300 [CA 5] Center 32 (2~63) winsize 62
5116 13:41:49.144403
5117 13:41:49.147533 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5118 13:41:49.147610
5119 13:41:49.150609 [CATrainingPosCal] consider 2 rank data
5120 13:41:49.154288 u2DelayCellTimex100 = 270/100 ps
5121 13:41:49.157428 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 13:41:49.160990 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 13:41:49.164239 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 13:41:49.167517 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 13:41:49.173719 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5126 13:41:49.176913 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5127 13:41:49.177022
5128 13:41:49.180388 CA PerBit enable=1, Macro0, CA PI delay=33
5129 13:41:49.180489
5130 13:41:49.183696 [CBTSetCACLKResult] CA Dly = 33
5131 13:41:49.183797 CS Dly: 7 (0~39)
5132 13:41:49.183891
5133 13:41:49.186968 ----->DramcWriteLeveling(PI) begin...
5134 13:41:49.187073 ==
5135 13:41:49.190309 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 13:41:49.197074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 13:41:49.197182 ==
5138 13:41:49.200231 Write leveling (Byte 0): 32 => 32
5139 13:41:49.203404 Write leveling (Byte 1): 27 => 27
5140 13:41:49.203485 DramcWriteLeveling(PI) end<-----
5141 13:41:49.206614
5142 13:41:49.206690 ==
5143 13:41:49.210357 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 13:41:49.213715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 13:41:49.213819 ==
5146 13:41:49.216463 [Gating] SW mode calibration
5147 13:41:49.223168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5148 13:41:49.226844 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5149 13:41:49.233228 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5150 13:41:49.236312 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5151 13:41:49.243178 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 13:41:49.246081 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 13:41:49.249297 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 13:41:49.255776 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 13:41:49.259539 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 13:41:49.262542 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5157 13:41:49.269146 0 15 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
5158 13:41:49.272550 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5159 13:41:49.275930 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 13:41:49.282459 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 13:41:49.285953 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 13:41:49.288673 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 13:41:49.295106 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 13:41:49.298960 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
5165 13:41:49.302299 1 0 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5166 13:41:49.308921 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 13:41:49.311646 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 13:41:49.315416 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 13:41:49.321765 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 13:41:49.325193 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 13:41:49.328374 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 13:41:49.334786 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5173 13:41:49.338168 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 13:41:49.341920 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 13:41:49.347809 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 13:41:49.351543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 13:41:49.354857 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 13:41:49.361350 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 13:41:49.364525 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:41:49.367589 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:41:49.374773 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:41:49.378286 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 13:41:49.381541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 13:41:49.387477 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 13:41:49.390794 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 13:41:49.394118 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 13:41:49.401234 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5188 13:41:49.403966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5189 13:41:49.407193 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5190 13:41:49.410526 Total UI for P1: 0, mck2ui 16
5191 13:41:49.414457 best dqsien dly found for B0: ( 1, 2, 26)
5192 13:41:49.420925 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 13:41:49.421007 Total UI for P1: 0, mck2ui 16
5194 13:41:49.424286 best dqsien dly found for B1: ( 1, 3, 0)
5195 13:41:49.430850 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5196 13:41:49.433574 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5197 13:41:49.433653
5198 13:41:49.437527 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5199 13:41:49.440266 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5200 13:41:49.443989 [Gating] SW calibration Done
5201 13:41:49.444070 ==
5202 13:41:49.447095 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 13:41:49.450439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 13:41:49.450549 ==
5205 13:41:49.453646 RX Vref Scan: 0
5206 13:41:49.453757
5207 13:41:49.453853 RX Vref 0 -> 0, step: 1
5208 13:41:49.453947
5209 13:41:49.456840 RX Delay -80 -> 252, step: 8
5210 13:41:49.460573 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5211 13:41:49.463741 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 13:41:49.470669 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5213 13:41:49.473556 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5214 13:41:49.476794 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5215 13:41:49.480159 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5216 13:41:49.483950 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5217 13:41:49.487124 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5218 13:41:49.493782 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5219 13:41:49.496469 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5220 13:41:49.499782 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5221 13:41:49.503086 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 13:41:49.509752 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5223 13:41:49.513374 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5224 13:41:49.516511 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5225 13:41:49.519808 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5226 13:41:49.519903 ==
5227 13:41:49.523120 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 13:41:49.526220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 13:41:49.526366 ==
5230 13:41:49.529611 DQS Delay:
5231 13:41:49.529769 DQS0 = 0, DQS1 = 0
5232 13:41:49.533060 DQM Delay:
5233 13:41:49.533230 DQM0 = 96, DQM1 = 87
5234 13:41:49.533306 DQ Delay:
5235 13:41:49.536557 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5236 13:41:49.539777 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5237 13:41:49.543118 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5238 13:41:49.546525 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5239 13:41:49.549759
5240 13:41:49.549881
5241 13:41:49.549954 ==
5242 13:41:49.552842 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 13:41:49.556284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 13:41:49.556405 ==
5245 13:41:49.556471
5246 13:41:49.556532
5247 13:41:49.559682 TX Vref Scan disable
5248 13:41:49.559761 == TX Byte 0 ==
5249 13:41:49.566255 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5250 13:41:49.569588 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5251 13:41:49.569683 == TX Byte 1 ==
5252 13:41:49.576123 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5253 13:41:49.579597 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5254 13:41:49.579745 ==
5255 13:41:49.582302 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 13:41:49.586029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 13:41:49.586191 ==
5258 13:41:49.586272
5259 13:41:49.586373
5260 13:41:49.588909 TX Vref Scan disable
5261 13:41:49.592274 == TX Byte 0 ==
5262 13:41:49.595666 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5263 13:41:49.598891 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5264 13:41:49.602023 == TX Byte 1 ==
5265 13:41:49.605334 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5266 13:41:49.608694 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5267 13:41:49.612020
5268 13:41:49.612152 [DATLAT]
5269 13:41:49.612221 Freq=933, CH0 RK0
5270 13:41:49.612284
5271 13:41:49.615370 DATLAT Default: 0xd
5272 13:41:49.615469 0, 0xFFFF, sum = 0
5273 13:41:49.618981 1, 0xFFFF, sum = 0
5274 13:41:49.619070 2, 0xFFFF, sum = 0
5275 13:41:49.622047 3, 0xFFFF, sum = 0
5276 13:41:49.622155 4, 0xFFFF, sum = 0
5277 13:41:49.625669 5, 0xFFFF, sum = 0
5278 13:41:49.628932 6, 0xFFFF, sum = 0
5279 13:41:49.629063 7, 0xFFFF, sum = 0
5280 13:41:49.632322 8, 0xFFFF, sum = 0
5281 13:41:49.632421 9, 0xFFFF, sum = 0
5282 13:41:49.635509 10, 0x0, sum = 1
5283 13:41:49.635639 11, 0x0, sum = 2
5284 13:41:49.638188 12, 0x0, sum = 3
5285 13:41:49.638297 13, 0x0, sum = 4
5286 13:41:49.638400 best_step = 11
5287 13:41:49.638492
5288 13:41:49.642176 ==
5289 13:41:49.645555 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 13:41:49.648283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 13:41:49.648426 ==
5292 13:41:49.648525 RX Vref Scan: 1
5293 13:41:49.648621
5294 13:41:49.651584 RX Vref 0 -> 0, step: 1
5295 13:41:49.651716
5296 13:41:49.654706 RX Delay -61 -> 252, step: 4
5297 13:41:49.654801
5298 13:41:49.657986 Set Vref, RX VrefLevel [Byte0]: 60
5299 13:41:49.661452 [Byte1]: 50
5300 13:41:49.661592
5301 13:41:49.664952 Final RX Vref Byte 0 = 60 to rank0
5302 13:41:49.668190 Final RX Vref Byte 1 = 50 to rank0
5303 13:41:49.671301 Final RX Vref Byte 0 = 60 to rank1
5304 13:41:49.675090 Final RX Vref Byte 1 = 50 to rank1==
5305 13:41:49.678143 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 13:41:49.685011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 13:41:49.685127 ==
5308 13:41:49.685223 DQS Delay:
5309 13:41:49.685313 DQS0 = 0, DQS1 = 0
5310 13:41:49.688180 DQM Delay:
5311 13:41:49.688263 DQM0 = 96, DQM1 = 85
5312 13:41:49.691550 DQ Delay:
5313 13:41:49.694183 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5314 13:41:49.698041 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5315 13:41:49.701092 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5316 13:41:49.704075 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =92
5317 13:41:49.704187
5318 13:41:49.704282
5319 13:41:49.711071 [DQSOSCAuto] RK0, (LSB)MR18= 0x290f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5320 13:41:49.714097 CH0 RK0: MR19=505, MR18=290F
5321 13:41:49.720911 CH0_RK0: MR19=0x505, MR18=0x290F, DQSOSC=408, MR23=63, INC=65, DEC=43
5322 13:41:49.721030
5323 13:41:49.724392 ----->DramcWriteLeveling(PI) begin...
5324 13:41:49.724474 ==
5325 13:41:49.727708 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 13:41:49.730968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 13:41:49.731070 ==
5328 13:41:49.733859 Write leveling (Byte 0): 34 => 34
5329 13:41:49.737130 Write leveling (Byte 1): 31 => 31
5330 13:41:49.740279 DramcWriteLeveling(PI) end<-----
5331 13:41:49.740387
5332 13:41:49.740453 ==
5333 13:41:49.744127 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 13:41:49.747106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 13:41:49.750379 ==
5336 13:41:49.750458 [Gating] SW mode calibration
5337 13:41:49.760337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 13:41:49.763432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 13:41:49.766730 0 14 0 | B1->B0 | 2c2b 3131 | 1 0 | (0 0) (0 0)
5340 13:41:49.773278 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 13:41:49.777200 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 13:41:49.780226 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 13:41:49.787039 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 13:41:49.790345 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 13:41:49.793558 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 13:41:49.800039 0 14 28 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
5347 13:41:49.803472 0 15 0 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (1 0)
5348 13:41:49.806931 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5349 13:41:49.813068 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 13:41:49.816417 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 13:41:49.819852 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 13:41:49.826279 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 13:41:49.829449 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 13:41:49.832757 0 15 28 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5355 13:41:49.839524 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5356 13:41:49.842936 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 13:41:49.846320 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 13:41:49.852836 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 13:41:49.856173 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 13:41:49.859496 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 13:41:49.865905 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5362 13:41:49.869448 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5363 13:41:49.872745 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5364 13:41:49.879371 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 13:41:49.882681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 13:41:49.885931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 13:41:49.892239 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 13:41:49.895877 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 13:41:49.898928 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 13:41:49.905410 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 13:41:49.908828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 13:41:49.912214 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 13:41:49.918730 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 13:41:49.921636 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 13:41:49.925292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 13:41:49.931827 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 13:41:49.935201 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 13:41:49.938470 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5379 13:41:49.944861 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 13:41:49.944942 Total UI for P1: 0, mck2ui 16
5381 13:41:49.951987 best dqsien dly found for B0: ( 1, 2, 28)
5382 13:41:49.952068 Total UI for P1: 0, mck2ui 16
5383 13:41:49.958697 best dqsien dly found for B1: ( 1, 2, 30)
5384 13:41:49.961817 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5385 13:41:49.964492 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5386 13:41:49.964575
5387 13:41:49.968400 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5388 13:41:49.971423 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5389 13:41:49.974781 [Gating] SW calibration Done
5390 13:41:49.974872 ==
5391 13:41:49.978131 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 13:41:49.980994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 13:41:49.981090 ==
5394 13:41:49.984422 RX Vref Scan: 0
5395 13:41:49.984521
5396 13:41:49.987586 RX Vref 0 -> 0, step: 1
5397 13:41:49.987660
5398 13:41:49.987722 RX Delay -80 -> 252, step: 8
5399 13:41:49.994270 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5400 13:41:49.997533 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5401 13:41:50.001357 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5402 13:41:50.004468 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5403 13:41:50.007558 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5404 13:41:50.011221 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5405 13:41:50.017210 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5406 13:41:50.021078 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5407 13:41:50.024337 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5408 13:41:50.027629 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5409 13:41:50.030702 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5410 13:41:50.037252 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5411 13:41:50.040279 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5412 13:41:50.043665 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5413 13:41:50.046973 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5414 13:41:50.050639 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5415 13:41:50.050739 ==
5416 13:41:50.053968 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 13:41:50.060318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 13:41:50.060419 ==
5419 13:41:50.060519 DQS Delay:
5420 13:41:50.063574 DQS0 = 0, DQS1 = 0
5421 13:41:50.063655 DQM Delay:
5422 13:41:50.063719 DQM0 = 97, DQM1 = 88
5423 13:41:50.066862 DQ Delay:
5424 13:41:50.070101 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5425 13:41:50.073503 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5426 13:41:50.076959 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5427 13:41:50.080102 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5428 13:41:50.080183
5429 13:41:50.080250
5430 13:41:50.080310 ==
5431 13:41:50.083411 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 13:41:50.086636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 13:41:50.086718 ==
5434 13:41:50.086783
5435 13:41:50.086844
5436 13:41:50.089960 TX Vref Scan disable
5437 13:41:50.093341 == TX Byte 0 ==
5438 13:41:50.096475 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5439 13:41:50.100097 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5440 13:41:50.103381 == TX Byte 1 ==
5441 13:41:50.106621 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5442 13:41:50.110059 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5443 13:41:50.110144 ==
5444 13:41:50.113367 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 13:41:50.116342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 13:41:50.119934 ==
5447 13:41:50.120017
5448 13:41:50.120082
5449 13:41:50.120142 TX Vref Scan disable
5450 13:41:50.123659 == TX Byte 0 ==
5451 13:41:50.126857 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5452 13:41:50.133214 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5453 13:41:50.133337 == TX Byte 1 ==
5454 13:41:50.136614 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5455 13:41:50.142917 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5456 13:41:50.143032
5457 13:41:50.143123 [DATLAT]
5458 13:41:50.143186 Freq=933, CH0 RK1
5459 13:41:50.143245
5460 13:41:50.146636 DATLAT Default: 0xb
5461 13:41:50.146710 0, 0xFFFF, sum = 0
5462 13:41:50.149551 1, 0xFFFF, sum = 0
5463 13:41:50.153311 2, 0xFFFF, sum = 0
5464 13:41:50.153391 3, 0xFFFF, sum = 0
5465 13:41:50.156155 4, 0xFFFF, sum = 0
5466 13:41:50.156237 5, 0xFFFF, sum = 0
5467 13:41:50.160082 6, 0xFFFF, sum = 0
5468 13:41:50.160156 7, 0xFFFF, sum = 0
5469 13:41:50.163268 8, 0xFFFF, sum = 0
5470 13:41:50.163351 9, 0xFFFF, sum = 0
5471 13:41:50.165943 10, 0x0, sum = 1
5472 13:41:50.166026 11, 0x0, sum = 2
5473 13:41:50.169251 12, 0x0, sum = 3
5474 13:41:50.169334 13, 0x0, sum = 4
5475 13:41:50.172458 best_step = 11
5476 13:41:50.172540
5477 13:41:50.172606 ==
5478 13:41:50.175802 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 13:41:50.178914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 13:41:50.178997 ==
5481 13:41:50.179060 RX Vref Scan: 0
5482 13:41:50.182214
5483 13:41:50.182296 RX Vref 0 -> 0, step: 1
5484 13:41:50.182360
5485 13:41:50.185776 RX Delay -61 -> 252, step: 4
5486 13:41:50.192432 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5487 13:41:50.195728 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5488 13:41:50.198826 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5489 13:41:50.202152 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5490 13:41:50.205534 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5491 13:41:50.212226 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5492 13:41:50.215575 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5493 13:41:50.218648 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5494 13:41:50.221793 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5495 13:41:50.225700 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5496 13:41:50.231628 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5497 13:41:50.235174 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5498 13:41:50.238675 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5499 13:41:50.241512 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5500 13:41:50.244942 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5501 13:41:50.251432 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5502 13:41:50.251514 ==
5503 13:41:50.255183 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 13:41:50.258365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 13:41:50.258448 ==
5506 13:41:50.258541 DQS Delay:
5507 13:41:50.261382 DQS0 = 0, DQS1 = 0
5508 13:41:50.261464 DQM Delay:
5509 13:41:50.265199 DQM0 = 95, DQM1 = 86
5510 13:41:50.265316 DQ Delay:
5511 13:41:50.268352 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5512 13:41:50.271459 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5513 13:41:50.274729 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5514 13:41:50.277929 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5515 13:41:50.278012
5516 13:41:50.278076
5517 13:41:50.288184 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5518 13:41:50.288267 CH0 RK1: MR19=504, MR18=25F5
5519 13:41:50.294761 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5520 13:41:50.298012 [RxdqsGatingPostProcess] freq 933
5521 13:41:50.304184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5522 13:41:50.308164 best DQS0 dly(2T, 0.5T) = (0, 10)
5523 13:41:50.310798 best DQS1 dly(2T, 0.5T) = (0, 11)
5524 13:41:50.314080 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5525 13:41:50.317418 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5526 13:41:50.320679 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 13:41:50.320781 best DQS1 dly(2T, 0.5T) = (0, 10)
5528 13:41:50.324120 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 13:41:50.327392 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5530 13:41:50.331078 Pre-setting of DQS Precalculation
5531 13:41:50.337601 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5532 13:41:50.337703 ==
5533 13:41:50.341084 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 13:41:50.344349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 13:41:50.344433 ==
5536 13:41:50.350869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 13:41:50.356923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 13:41:50.360580 [CA 0] Center 36 (6~67) winsize 62
5539 13:41:50.363568 [CA 1] Center 37 (6~68) winsize 63
5540 13:41:50.366706 [CA 2] Center 34 (4~65) winsize 62
5541 13:41:50.370240 [CA 3] Center 33 (3~64) winsize 62
5542 13:41:50.373992 [CA 4] Center 34 (4~64) winsize 61
5543 13:41:50.377108 [CA 5] Center 33 (3~64) winsize 62
5544 13:41:50.377203
5545 13:41:50.380690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 13:41:50.380792
5547 13:41:50.383473 [CATrainingPosCal] consider 1 rank data
5548 13:41:50.387120 u2DelayCellTimex100 = 270/100 ps
5549 13:41:50.390259 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 13:41:50.393653 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5551 13:41:50.396996 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 13:41:50.399827 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 13:41:50.403172 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5554 13:41:50.407161 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 13:41:50.410444
5556 13:41:50.413423 CA PerBit enable=1, Macro0, CA PI delay=33
5557 13:41:50.413506
5558 13:41:50.416832 [CBTSetCACLKResult] CA Dly = 33
5559 13:41:50.416932 CS Dly: 6 (0~37)
5560 13:41:50.417011 ==
5561 13:41:50.420264 Dram Type= 6, Freq= 0, CH_1, rank 1
5562 13:41:50.422901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 13:41:50.426750 ==
5564 13:41:50.430027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5565 13:41:50.436162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5566 13:41:50.439390 [CA 0] Center 36 (6~67) winsize 62
5567 13:41:50.442843 [CA 1] Center 37 (7~67) winsize 61
5568 13:41:50.446317 [CA 2] Center 34 (4~65) winsize 62
5569 13:41:50.449523 [CA 3] Center 33 (3~64) winsize 62
5570 13:41:50.452709 [CA 4] Center 34 (3~65) winsize 63
5571 13:41:50.456279 [CA 5] Center 33 (3~64) winsize 62
5572 13:41:50.456361
5573 13:41:50.459547 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5574 13:41:50.459630
5575 13:41:50.462673 [CATrainingPosCal] consider 2 rank data
5576 13:41:50.466250 u2DelayCellTimex100 = 270/100 ps
5577 13:41:50.469248 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5578 13:41:50.473073 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5579 13:41:50.476324 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 13:41:50.482448 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 13:41:50.485818 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5582 13:41:50.489215 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5583 13:41:50.489297
5584 13:41:50.492537 CA PerBit enable=1, Macro0, CA PI delay=33
5585 13:41:50.492620
5586 13:41:50.495513 [CBTSetCACLKResult] CA Dly = 33
5587 13:41:50.495595 CS Dly: 7 (0~39)
5588 13:41:50.495662
5589 13:41:50.498951 ----->DramcWriteLeveling(PI) begin...
5590 13:41:50.499045 ==
5591 13:41:50.502600 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 13:41:50.508818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 13:41:50.508909 ==
5594 13:41:50.512229 Write leveling (Byte 0): 26 => 26
5595 13:41:50.515534 Write leveling (Byte 1): 27 => 27
5596 13:41:50.518778 DramcWriteLeveling(PI) end<-----
5597 13:41:50.518861
5598 13:41:50.518926 ==
5599 13:41:50.522143 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 13:41:50.525642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 13:41:50.525725 ==
5602 13:41:50.528862 [Gating] SW mode calibration
5603 13:41:50.535450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5604 13:41:50.538484 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5605 13:41:50.545779 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5606 13:41:50.548486 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 13:41:50.551917 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 13:41:50.558600 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 13:41:50.561748 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 13:41:50.565190 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 13:41:50.571806 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5612 13:41:50.575101 0 14 28 | B1->B0 | 2d2d 2929 | 0 0 | (1 0) (1 1)
5613 13:41:50.581599 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5614 13:41:50.584818 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 13:41:50.588324 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 13:41:50.594452 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 13:41:50.598011 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 13:41:50.601493 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 13:41:50.604426 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5620 13:41:50.610854 0 15 28 | B1->B0 | 3232 3939 | 1 1 | (0 0) (0 0)
5621 13:41:50.614406 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 13:41:50.617786 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 13:41:50.624752 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:41:50.628078 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 13:41:50.631514 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 13:41:50.637396 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:41:50.641207 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5628 13:41:50.644659 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5629 13:41:50.650480 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:41:50.654403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:41:50.657068 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:41:50.664317 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:41:50.667100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:41:50.670564 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:41:50.677092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:41:50.680214 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:41:50.684267 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 13:41:50.690218 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 13:41:50.693836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 13:41:50.696961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 13:41:50.703736 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 13:41:50.706884 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:41:50.710721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5644 13:41:50.717235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 13:41:50.720361 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 13:41:50.723634 Total UI for P1: 0, mck2ui 16
5647 13:41:50.727185 best dqsien dly found for B0: ( 1, 2, 26)
5648 13:41:50.730203 Total UI for P1: 0, mck2ui 16
5649 13:41:50.733255 best dqsien dly found for B1: ( 1, 2, 26)
5650 13:41:50.736617 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5651 13:41:50.739900 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5652 13:41:50.739981
5653 13:41:50.743377 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5654 13:41:50.746338 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 13:41:50.750224 [Gating] SW calibration Done
5656 13:41:50.750309 ==
5657 13:41:50.753448 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 13:41:50.760061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 13:41:50.760171 ==
5660 13:41:50.760262 RX Vref Scan: 0
5661 13:41:50.760347
5662 13:41:50.762876 RX Vref 0 -> 0, step: 1
5663 13:41:50.762957
5664 13:41:50.766065 RX Delay -80 -> 252, step: 8
5665 13:41:50.770009 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5666 13:41:50.772645 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5667 13:41:50.776125 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5668 13:41:50.779470 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5669 13:41:50.786003 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5670 13:41:50.789413 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5671 13:41:50.792485 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5672 13:41:50.795902 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5673 13:41:50.799588 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5674 13:41:50.806114 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5675 13:41:50.809286 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5676 13:41:50.812374 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5677 13:41:50.815671 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5678 13:41:50.818890 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5679 13:41:50.822789 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5680 13:41:50.828869 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5681 13:41:50.828950 ==
5682 13:41:50.832119 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 13:41:50.835385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 13:41:50.835495 ==
5685 13:41:50.835561 DQS Delay:
5686 13:41:50.839096 DQS0 = 0, DQS1 = 0
5687 13:41:50.839178 DQM Delay:
5688 13:41:50.842141 DQM0 = 100, DQM1 = 90
5689 13:41:50.842255 DQ Delay:
5690 13:41:50.845757 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95
5691 13:41:50.848992 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5692 13:41:50.852199 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5693 13:41:50.855414 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5694 13:41:50.855495
5695 13:41:50.855559
5696 13:41:50.855618 ==
5697 13:41:50.858861 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 13:41:50.865470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 13:41:50.865556 ==
5700 13:41:50.865623
5701 13:41:50.865684
5702 13:41:50.865741 TX Vref Scan disable
5703 13:41:50.868861 == TX Byte 0 ==
5704 13:41:50.872206 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5705 13:41:50.878405 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5706 13:41:50.878487 == TX Byte 1 ==
5707 13:41:50.882364 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 13:41:50.888195 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 13:41:50.888300 ==
5710 13:41:50.891487 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 13:41:50.894754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 13:41:50.894852 ==
5713 13:41:50.894915
5714 13:41:50.894990
5715 13:41:50.897914 TX Vref Scan disable
5716 13:41:50.901422 == TX Byte 0 ==
5717 13:41:50.904568 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5718 13:41:50.908093 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5719 13:41:50.911227 == TX Byte 1 ==
5720 13:41:50.915143 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 13:41:50.918275 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 13:41:50.918353
5723 13:41:50.918425 [DATLAT]
5724 13:41:50.921460 Freq=933, CH1 RK0
5725 13:41:50.921533
5726 13:41:50.924711 DATLAT Default: 0xd
5727 13:41:50.924812 0, 0xFFFF, sum = 0
5728 13:41:50.927931 1, 0xFFFF, sum = 0
5729 13:41:50.928036 2, 0xFFFF, sum = 0
5730 13:41:50.931206 3, 0xFFFF, sum = 0
5731 13:41:50.931306 4, 0xFFFF, sum = 0
5732 13:41:50.934606 5, 0xFFFF, sum = 0
5733 13:41:50.934690 6, 0xFFFF, sum = 0
5734 13:41:50.937883 7, 0xFFFF, sum = 0
5735 13:41:50.937966 8, 0xFFFF, sum = 0
5736 13:41:50.941128 9, 0xFFFF, sum = 0
5737 13:41:50.941210 10, 0x0, sum = 1
5738 13:41:50.944396 11, 0x0, sum = 2
5739 13:41:50.944504 12, 0x0, sum = 3
5740 13:41:50.947614 13, 0x0, sum = 4
5741 13:41:50.947696 best_step = 11
5742 13:41:50.947760
5743 13:41:50.947820 ==
5744 13:41:50.951349 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 13:41:50.954395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 13:41:50.957348 ==
5747 13:41:50.957429 RX Vref Scan: 1
5748 13:41:50.957493
5749 13:41:50.960674 RX Vref 0 -> 0, step: 1
5750 13:41:50.960755
5751 13:41:50.964012 RX Delay -69 -> 252, step: 4
5752 13:41:50.964111
5753 13:41:50.967173 Set Vref, RX VrefLevel [Byte0]: 48
5754 13:41:50.970560 [Byte1]: 60
5755 13:41:50.970643
5756 13:41:50.973884 Final RX Vref Byte 0 = 48 to rank0
5757 13:41:50.977268 Final RX Vref Byte 1 = 60 to rank0
5758 13:41:50.980504 Final RX Vref Byte 0 = 48 to rank1
5759 13:41:50.983973 Final RX Vref Byte 1 = 60 to rank1==
5760 13:41:50.986762 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 13:41:50.990123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 13:41:50.990232 ==
5763 13:41:50.994081 DQS Delay:
5764 13:41:50.994202 DQS0 = 0, DQS1 = 0
5765 13:41:50.994274 DQM Delay:
5766 13:41:50.996848 DQM0 = 101, DQM1 = 95
5767 13:41:50.996931 DQ Delay:
5768 13:41:51.000731 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5769 13:41:51.003447 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5770 13:41:51.006831 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =84
5771 13:41:51.010673 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5772 13:41:51.010771
5773 13:41:51.013720
5774 13:41:51.019958 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5775 13:41:51.023556 CH1 RK0: MR19=505, MR18=1909
5776 13:41:51.030065 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5777 13:41:51.030149
5778 13:41:51.032914 ----->DramcWriteLeveling(PI) begin...
5779 13:41:51.033015 ==
5780 13:41:51.036858 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 13:41:51.039985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:41:51.040062 ==
5783 13:41:51.043358 Write leveling (Byte 0): 26 => 26
5784 13:41:51.046723 Write leveling (Byte 1): 26 => 26
5785 13:41:51.050064 DramcWriteLeveling(PI) end<-----
5786 13:41:51.050168
5787 13:41:51.050234 ==
5788 13:41:51.053421 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 13:41:51.056541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 13:41:51.056649 ==
5791 13:41:51.059336 [Gating] SW mode calibration
5792 13:41:51.065972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5793 13:41:51.072689 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5794 13:41:51.076120 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5795 13:41:51.082827 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 13:41:51.086060 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 13:41:51.089463 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 13:41:51.096242 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 13:41:51.099331 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 13:41:51.102557 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5801 13:41:51.109335 0 14 28 | B1->B0 | 2929 2f2f | 1 1 | (1 0) (1 0)
5802 13:41:51.112559 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5803 13:41:51.115356 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 13:41:51.121981 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 13:41:51.125365 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 13:41:51.129236 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 13:41:51.135613 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 13:41:51.138437 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5809 13:41:51.142097 0 15 28 | B1->B0 | 3a39 3434 | 1 0 | (1 1) (0 0)
5810 13:41:51.148442 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 13:41:51.151983 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 13:41:51.155263 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 13:41:51.161552 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 13:41:51.164776 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 13:41:51.167948 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 13:41:51.174642 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5817 13:41:51.177929 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5818 13:41:51.181806 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 13:41:51.188459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 13:41:51.191466 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 13:41:51.194901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 13:41:51.201425 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 13:41:51.204743 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 13:41:51.208111 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 13:41:51.214777 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 13:41:51.217574 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 13:41:51.220818 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 13:41:51.227654 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 13:41:51.230870 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 13:41:51.234127 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 13:41:51.240806 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 13:41:51.244151 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5833 13:41:51.247311 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:41:51.250572 Total UI for P1: 0, mck2ui 16
5835 13:41:51.253664 best dqsien dly found for B0: ( 1, 2, 24)
5836 13:41:51.257299 Total UI for P1: 0, mck2ui 16
5837 13:41:51.260444 best dqsien dly found for B1: ( 1, 2, 24)
5838 13:41:51.263917 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5839 13:41:51.267217 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5840 13:41:51.267330
5841 13:41:51.273566 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5842 13:41:51.277368 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5843 13:41:51.277444 [Gating] SW calibration Done
5844 13:41:51.280168 ==
5845 13:41:51.283425 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 13:41:51.286874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 13:41:51.286946 ==
5848 13:41:51.287008 RX Vref Scan: 0
5849 13:41:51.287066
5850 13:41:51.290098 RX Vref 0 -> 0, step: 1
5851 13:41:51.290232
5852 13:41:51.293325 RX Delay -80 -> 252, step: 8
5853 13:41:51.296968 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5854 13:41:51.300231 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5855 13:41:51.303138 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5856 13:41:51.309859 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5857 13:41:51.313039 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5858 13:41:51.316430 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5859 13:41:51.319788 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5860 13:41:51.323190 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5861 13:41:51.329776 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5862 13:41:51.333215 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5863 13:41:51.336412 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5864 13:41:51.339562 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5865 13:41:51.343063 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5866 13:41:51.346119 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5867 13:41:51.352602 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5868 13:41:51.355890 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5869 13:41:51.355972 ==
5870 13:41:51.359126 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 13:41:51.362315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 13:41:51.362397 ==
5873 13:41:51.365553 DQS Delay:
5874 13:41:51.365659 DQS0 = 0, DQS1 = 0
5875 13:41:51.365753 DQM Delay:
5876 13:41:51.369070 DQM0 = 99, DQM1 = 92
5877 13:41:51.369172 DQ Delay:
5878 13:41:51.372593 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =95
5879 13:41:51.375407 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5880 13:41:51.379035 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5881 13:41:51.382105 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5882 13:41:51.382235
5883 13:41:51.382326
5884 13:41:51.385437 ==
5885 13:41:51.388733 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 13:41:51.392089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 13:41:51.392164 ==
5888 13:41:51.392226
5889 13:41:51.392285
5890 13:41:51.395298 TX Vref Scan disable
5891 13:41:51.395368 == TX Byte 0 ==
5892 13:41:51.401872 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5893 13:41:51.405151 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5894 13:41:51.405255 == TX Byte 1 ==
5895 13:41:51.411435 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5896 13:41:51.415025 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5897 13:41:51.415110 ==
5898 13:41:51.418311 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 13:41:51.421811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 13:41:51.421917 ==
5901 13:41:51.422009
5902 13:41:51.422095
5903 13:41:51.424434 TX Vref Scan disable
5904 13:41:51.427792 == TX Byte 0 ==
5905 13:41:51.430943 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5906 13:41:51.434270 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5907 13:41:51.437671 == TX Byte 1 ==
5908 13:41:51.440984 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5909 13:41:51.444296 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5910 13:41:51.444394
5911 13:41:51.447543 [DATLAT]
5912 13:41:51.447613 Freq=933, CH1 RK1
5913 13:41:51.447675
5914 13:41:51.450804 DATLAT Default: 0xb
5915 13:41:51.450910 0, 0xFFFF, sum = 0
5916 13:41:51.454314 1, 0xFFFF, sum = 0
5917 13:41:51.454422 2, 0xFFFF, sum = 0
5918 13:41:51.457521 3, 0xFFFF, sum = 0
5919 13:41:51.457618 4, 0xFFFF, sum = 0
5920 13:41:51.460764 5, 0xFFFF, sum = 0
5921 13:41:51.464148 6, 0xFFFF, sum = 0
5922 13:41:51.464248 7, 0xFFFF, sum = 0
5923 13:41:51.467356 8, 0xFFFF, sum = 0
5924 13:41:51.467436 9, 0xFFFF, sum = 0
5925 13:41:51.471101 10, 0x0, sum = 1
5926 13:41:51.471186 11, 0x0, sum = 2
5927 13:41:51.474409 12, 0x0, sum = 3
5928 13:41:51.474510 13, 0x0, sum = 4
5929 13:41:51.474610 best_step = 11
5930 13:41:51.474731
5931 13:41:51.477393 ==
5932 13:41:51.480400 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 13:41:51.483878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 13:41:51.483961 ==
5935 13:41:51.484026 RX Vref Scan: 0
5936 13:41:51.484086
5937 13:41:51.487425 RX Vref 0 -> 0, step: 1
5938 13:41:51.487507
5939 13:41:51.490709 RX Delay -61 -> 252, step: 4
5940 13:41:51.497254 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5941 13:41:51.500574 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5942 13:41:51.503816 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5943 13:41:51.507279 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5944 13:41:51.510443 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5945 13:41:51.513683 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
5946 13:41:51.520274 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5947 13:41:51.523669 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5948 13:41:51.526940 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5949 13:41:51.530217 iDelay=207, Bit 9, Center 82 (-5 ~ 170) 176
5950 13:41:51.533431 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5951 13:41:51.536757 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5952 13:41:51.543533 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5953 13:41:51.546838 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5954 13:41:51.549901 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5955 13:41:51.553134 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5956 13:41:51.553237 ==
5957 13:41:51.556506 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 13:41:51.563230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 13:41:51.563339 ==
5960 13:41:51.563433 DQS Delay:
5961 13:41:51.566366 DQS0 = 0, DQS1 = 0
5962 13:41:51.566437 DQM Delay:
5963 13:41:51.566513 DQM0 = 101, DQM1 = 93
5964 13:41:51.569700 DQ Delay:
5965 13:41:51.573507 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5966 13:41:51.576242 DQ4 =98, DQ5 =112, DQ6 =116, DQ7 =96
5967 13:41:51.579677 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
5968 13:41:51.582933 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5969 13:41:51.583016
5970 13:41:51.583080
5971 13:41:51.589909 [DQSOSCAuto] RK1, (LSB)MR18= 0x500, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5972 13:41:51.592925 CH1 RK1: MR19=505, MR18=500
5973 13:41:51.599572 CH1_RK1: MR19=0x505, MR18=0x500, DQSOSC=420, MR23=63, INC=61, DEC=40
5974 13:41:51.602913 [RxdqsGatingPostProcess] freq 933
5975 13:41:51.609959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5976 13:41:51.610041 best DQS0 dly(2T, 0.5T) = (0, 10)
5977 13:41:51.613260 best DQS1 dly(2T, 0.5T) = (0, 10)
5978 13:41:51.616498 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5979 13:41:51.619386 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5980 13:41:51.622544 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 13:41:51.626528 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 13:41:51.629591 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 13:41:51.632402 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 13:41:51.636131 Pre-setting of DQS Precalculation
5985 13:41:51.642554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5986 13:41:51.649224 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5987 13:41:51.655597 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5988 13:41:51.655678
5989 13:41:51.655749
5990 13:41:51.658913 [Calibration Summary] 1866 Mbps
5991 13:41:51.658997 CH 0, Rank 0
5992 13:41:51.662129 SW Impedance : PASS
5993 13:41:51.665335 DUTY Scan : NO K
5994 13:41:51.665418 ZQ Calibration : PASS
5995 13:41:51.668625 Jitter Meter : NO K
5996 13:41:51.671839 CBT Training : PASS
5997 13:41:51.671941 Write leveling : PASS
5998 13:41:51.675270 RX DQS gating : PASS
5999 13:41:51.678523 RX DQ/DQS(RDDQC) : PASS
6000 13:41:51.678596 TX DQ/DQS : PASS
6001 13:41:51.681807 RX DATLAT : PASS
6002 13:41:51.685366 RX DQ/DQS(Engine): PASS
6003 13:41:51.685447 TX OE : NO K
6004 13:41:51.685511 All Pass.
6005 13:41:51.688600
6006 13:41:51.688670 CH 0, Rank 1
6007 13:41:51.691816 SW Impedance : PASS
6008 13:41:51.691890 DUTY Scan : NO K
6009 13:41:51.695041 ZQ Calibration : PASS
6010 13:41:51.698306 Jitter Meter : NO K
6011 13:41:51.698430 CBT Training : PASS
6012 13:41:51.702087 Write leveling : PASS
6013 13:41:51.702233 RX DQS gating : PASS
6014 13:41:51.705168 RX DQ/DQS(RDDQC) : PASS
6015 13:41:51.708084 TX DQ/DQS : PASS
6016 13:41:51.708160 RX DATLAT : PASS
6017 13:41:51.711809 RX DQ/DQS(Engine): PASS
6018 13:41:51.715001 TX OE : NO K
6019 13:41:51.715075 All Pass.
6020 13:41:51.715138
6021 13:41:51.715203 CH 1, Rank 0
6022 13:41:51.718071 SW Impedance : PASS
6023 13:41:51.721510 DUTY Scan : NO K
6024 13:41:51.721591 ZQ Calibration : PASS
6025 13:41:51.724675 Jitter Meter : NO K
6026 13:41:51.728024 CBT Training : PASS
6027 13:41:51.728095 Write leveling : PASS
6028 13:41:51.731498 RX DQS gating : PASS
6029 13:41:51.734703 RX DQ/DQS(RDDQC) : PASS
6030 13:41:51.734779 TX DQ/DQS : PASS
6031 13:41:51.737943 RX DATLAT : PASS
6032 13:41:51.741203 RX DQ/DQS(Engine): PASS
6033 13:41:51.741284 TX OE : NO K
6034 13:41:51.744418 All Pass.
6035 13:41:51.744498
6036 13:41:51.744561 CH 1, Rank 1
6037 13:41:51.748001 SW Impedance : PASS
6038 13:41:51.748111 DUTY Scan : NO K
6039 13:41:51.751232 ZQ Calibration : PASS
6040 13:41:51.754442 Jitter Meter : NO K
6041 13:41:51.754524 CBT Training : PASS
6042 13:41:51.757917 Write leveling : PASS
6043 13:41:51.761047 RX DQS gating : PASS
6044 13:41:51.761129 RX DQ/DQS(RDDQC) : PASS
6045 13:41:51.764193 TX DQ/DQS : PASS
6046 13:41:51.767568 RX DATLAT : PASS
6047 13:41:51.767653 RX DQ/DQS(Engine): PASS
6048 13:41:51.770858 TX OE : NO K
6049 13:41:51.770940 All Pass.
6050 13:41:51.771005
6051 13:41:51.774061 DramC Write-DBI off
6052 13:41:51.777406 PER_BANK_REFRESH: Hybrid Mode
6053 13:41:51.777489 TX_TRACKING: ON
6054 13:41:51.787356 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6055 13:41:51.790666 [FAST_K] Save calibration result to emmc
6056 13:41:51.793877 dramc_set_vcore_voltage set vcore to 650000
6057 13:41:51.797262 Read voltage for 400, 6
6058 13:41:51.797344 Vio18 = 0
6059 13:41:51.797426 Vcore = 650000
6060 13:41:51.800522 Vdram = 0
6061 13:41:51.800642 Vddq = 0
6062 13:41:51.800750 Vmddr = 0
6063 13:41:51.807134 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6064 13:41:51.810380 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6065 13:41:51.813936 MEM_TYPE=3, freq_sel=20
6066 13:41:51.817363 sv_algorithm_assistance_LP4_800
6067 13:41:51.820294 ============ PULL DRAM RESETB DOWN ============
6068 13:41:51.824071 ========== PULL DRAM RESETB DOWN end =========
6069 13:41:51.830080 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6070 13:41:51.833396 ===================================
6071 13:41:51.833479 LPDDR4 DRAM CONFIGURATION
6072 13:41:51.836699 ===================================
6073 13:41:51.840577 EX_ROW_EN[0] = 0x0
6074 13:41:51.844133 EX_ROW_EN[1] = 0x0
6075 13:41:51.844215 LP4Y_EN = 0x0
6076 13:41:51.847185 WORK_FSP = 0x0
6077 13:41:51.847267 WL = 0x2
6078 13:41:51.850707 RL = 0x2
6079 13:41:51.850789 BL = 0x2
6080 13:41:51.853400 RPST = 0x0
6081 13:41:51.853482 RD_PRE = 0x0
6082 13:41:51.856421 WR_PRE = 0x1
6083 13:41:51.856502 WR_PST = 0x0
6084 13:41:51.860442 DBI_WR = 0x0
6085 13:41:51.860545 DBI_RD = 0x0
6086 13:41:51.863116 OTF = 0x1
6087 13:41:51.866848 ===================================
6088 13:41:51.870113 ===================================
6089 13:41:51.870237 ANA top config
6090 13:41:51.873554 ===================================
6091 13:41:51.876878 DLL_ASYNC_EN = 0
6092 13:41:51.880280 ALL_SLAVE_EN = 1
6093 13:41:51.883365 NEW_RANK_MODE = 1
6094 13:41:51.883448 DLL_IDLE_MODE = 1
6095 13:41:51.886536 LP45_APHY_COMB_EN = 1
6096 13:41:51.889876 TX_ODT_DIS = 1
6097 13:41:51.893231 NEW_8X_MODE = 1
6098 13:41:51.896487 ===================================
6099 13:41:51.899808 ===================================
6100 13:41:51.903136 data_rate = 800
6101 13:41:51.906150 CKR = 1
6102 13:41:51.906253 DQ_P2S_RATIO = 4
6103 13:41:51.909464 ===================================
6104 13:41:51.912662 CA_P2S_RATIO = 4
6105 13:41:51.916473 DQ_CA_OPEN = 0
6106 13:41:51.919640 DQ_SEMI_OPEN = 1
6107 13:41:51.923081 CA_SEMI_OPEN = 1
6108 13:41:51.926358 CA_FULL_RATE = 0
6109 13:41:51.926440 DQ_CKDIV4_EN = 0
6110 13:41:51.929171 CA_CKDIV4_EN = 1
6111 13:41:51.932776 CA_PREDIV_EN = 0
6112 13:41:51.935851 PH8_DLY = 0
6113 13:41:51.939522 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6114 13:41:51.942846 DQ_AAMCK_DIV = 0
6115 13:41:51.942928 CA_AAMCK_DIV = 0
6116 13:41:51.945548 CA_ADMCK_DIV = 4
6117 13:41:51.948798 DQ_TRACK_CA_EN = 0
6118 13:41:51.952094 CA_PICK = 800
6119 13:41:51.955921 CA_MCKIO = 400
6120 13:41:51.959299 MCKIO_SEMI = 400
6121 13:41:51.962350 PLL_FREQ = 3016
6122 13:41:51.965727 DQ_UI_PI_RATIO = 32
6123 13:41:51.965809 CA_UI_PI_RATIO = 32
6124 13:41:51.969164 ===================================
6125 13:41:51.972214 ===================================
6126 13:41:51.975118 memory_type:LPDDR4
6127 13:41:51.978349 GP_NUM : 10
6128 13:41:51.978430 SRAM_EN : 1
6129 13:41:51.982124 MD32_EN : 0
6130 13:41:51.985318 ===================================
6131 13:41:51.988794 [ANA_INIT] >>>>>>>>>>>>>>
6132 13:41:51.991917 <<<<<< [CONFIGURE PHASE]: ANA_TX
6133 13:41:51.995189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6134 13:41:51.998523 ===================================
6135 13:41:51.998606 data_rate = 800,PCW = 0X7400
6136 13:41:52.001702 ===================================
6137 13:41:52.005051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6138 13:41:52.011544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 13:41:52.024541 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6140 13:41:52.027669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6141 13:41:52.030969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6142 13:41:52.034311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6143 13:41:52.037635 [ANA_INIT] flow start
6144 13:41:52.037716 [ANA_INIT] PLL >>>>>>>>
6145 13:41:52.040970 [ANA_INIT] PLL <<<<<<<<
6146 13:41:52.044131 [ANA_INIT] MIDPI >>>>>>>>
6147 13:41:52.047652 [ANA_INIT] MIDPI <<<<<<<<
6148 13:41:52.047733 [ANA_INIT] DLL >>>>>>>>
6149 13:41:52.050865 [ANA_INIT] flow end
6150 13:41:52.053867 ============ LP4 DIFF to SE enter ============
6151 13:41:52.057290 ============ LP4 DIFF to SE exit ============
6152 13:41:52.060484 [ANA_INIT] <<<<<<<<<<<<<
6153 13:41:52.064535 [Flow] Enable top DCM control >>>>>
6154 13:41:52.067057 [Flow] Enable top DCM control <<<<<
6155 13:41:52.070958 Enable DLL master slave shuffle
6156 13:41:52.077337 ==============================================================
6157 13:41:52.077421 Gating Mode config
6158 13:41:52.083783 ==============================================================
6159 13:41:52.083866 Config description:
6160 13:41:52.094016 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6161 13:41:52.100595 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6162 13:41:52.107236 SELPH_MODE 0: By rank 1: By Phase
6163 13:41:52.113746 ==============================================================
6164 13:41:52.113831 GAT_TRACK_EN = 0
6165 13:41:52.117002 RX_GATING_MODE = 2
6166 13:41:52.120368 RX_GATING_TRACK_MODE = 2
6167 13:41:52.123771 SELPH_MODE = 1
6168 13:41:52.126709 PICG_EARLY_EN = 1
6169 13:41:52.129912 VALID_LAT_VALUE = 1
6170 13:41:52.136493 ==============================================================
6171 13:41:52.139787 Enter into Gating configuration >>>>
6172 13:41:52.142990 Exit from Gating configuration <<<<
6173 13:41:52.146351 Enter into DVFS_PRE_config >>>>>
6174 13:41:52.156397 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6175 13:41:52.159690 Exit from DVFS_PRE_config <<<<<
6176 13:41:52.162688 Enter into PICG configuration >>>>
6177 13:41:52.166341 Exit from PICG configuration <<<<
6178 13:41:52.169139 [RX_INPUT] configuration >>>>>
6179 13:41:52.172803 [RX_INPUT] configuration <<<<<
6180 13:41:52.175819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6181 13:41:52.182814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6182 13:41:52.189446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 13:41:52.195742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 13:41:52.199048 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 13:41:52.205635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 13:41:52.208827 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6187 13:41:52.215423 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6188 13:41:52.218621 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6189 13:41:52.222522 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6190 13:41:52.225336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6191 13:41:52.232394 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 13:41:52.235660 ===================================
6193 13:41:52.239066 LPDDR4 DRAM CONFIGURATION
6194 13:41:52.242376 ===================================
6195 13:41:52.242458 EX_ROW_EN[0] = 0x0
6196 13:41:52.245517 EX_ROW_EN[1] = 0x0
6197 13:41:52.245599 LP4Y_EN = 0x0
6198 13:41:52.248296 WORK_FSP = 0x0
6199 13:41:52.248376 WL = 0x2
6200 13:41:52.252041 RL = 0x2
6201 13:41:52.252122 BL = 0x2
6202 13:41:52.255331 RPST = 0x0
6203 13:41:52.255412 RD_PRE = 0x0
6204 13:41:52.258061 WR_PRE = 0x1
6205 13:41:52.258141 WR_PST = 0x0
6206 13:41:52.262052 DBI_WR = 0x0
6207 13:41:52.264839 DBI_RD = 0x0
6208 13:41:52.264944 OTF = 0x1
6209 13:41:52.267969 ===================================
6210 13:41:52.271435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6211 13:41:52.274938 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6212 13:41:52.281747 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 13:41:52.284906 ===================================
6214 13:41:52.287828 LPDDR4 DRAM CONFIGURATION
6215 13:41:52.291705 ===================================
6216 13:41:52.291785 EX_ROW_EN[0] = 0x10
6217 13:41:52.294933 EX_ROW_EN[1] = 0x0
6218 13:41:52.295015 LP4Y_EN = 0x0
6219 13:41:52.298113 WORK_FSP = 0x0
6220 13:41:52.298233 WL = 0x2
6221 13:41:52.301374 RL = 0x2
6222 13:41:52.301455 BL = 0x2
6223 13:41:52.304561 RPST = 0x0
6224 13:41:52.304642 RD_PRE = 0x0
6225 13:41:52.307915 WR_PRE = 0x1
6226 13:41:52.311329 WR_PST = 0x0
6227 13:41:52.311410 DBI_WR = 0x0
6228 13:41:52.314056 DBI_RD = 0x0
6229 13:41:52.314137 OTF = 0x1
6230 13:41:52.317979 ===================================
6231 13:41:52.324445 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6232 13:41:52.328411 nWR fixed to 30
6233 13:41:52.331144 [ModeRegInit_LP4] CH0 RK0
6234 13:41:52.331225 [ModeRegInit_LP4] CH0 RK1
6235 13:41:52.334285 [ModeRegInit_LP4] CH1 RK0
6236 13:41:52.337695 [ModeRegInit_LP4] CH1 RK1
6237 13:41:52.337776 match AC timing 19
6238 13:41:52.344226 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6239 13:41:52.347473 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6240 13:41:52.351465 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6241 13:41:52.358044 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6242 13:41:52.360783 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6243 13:41:52.360864 ==
6244 13:41:52.364177 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 13:41:52.367426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 13:41:52.367508 ==
6247 13:41:52.373952 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 13:41:52.380896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6249 13:41:52.383849 [CA 0] Center 36 (8~64) winsize 57
6250 13:41:52.387581 [CA 1] Center 36 (8~64) winsize 57
6251 13:41:52.390524 [CA 2] Center 36 (8~64) winsize 57
6252 13:41:52.394040 [CA 3] Center 36 (8~64) winsize 57
6253 13:41:52.397127 [CA 4] Center 36 (8~64) winsize 57
6254 13:41:52.400637 [CA 5] Center 36 (8~64) winsize 57
6255 13:41:52.400718
6256 13:41:52.403544 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6257 13:41:52.403651
6258 13:41:52.406848 [CATrainingPosCal] consider 1 rank data
6259 13:41:52.410131 u2DelayCellTimex100 = 270/100 ps
6260 13:41:52.413624 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 13:41:52.416962 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 13:41:52.420248 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 13:41:52.423461 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 13:41:52.426510 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:41:52.430593 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 13:41:52.430674
6267 13:41:52.436496 CA PerBit enable=1, Macro0, CA PI delay=36
6268 13:41:52.436577
6269 13:41:52.436640 [CBTSetCACLKResult] CA Dly = 36
6270 13:41:52.440406 CS Dly: 1 (0~32)
6271 13:41:52.440487 ==
6272 13:41:52.443496 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 13:41:52.446656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 13:41:52.446766 ==
6275 13:41:52.452785 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 13:41:52.459821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6277 13:41:52.463311 [CA 0] Center 36 (8~64) winsize 57
6278 13:41:52.466391 [CA 1] Center 36 (8~64) winsize 57
6279 13:41:52.469761 [CA 2] Center 36 (8~64) winsize 57
6280 13:41:52.473257 [CA 3] Center 36 (8~64) winsize 57
6281 13:41:52.476377 [CA 4] Center 36 (8~64) winsize 57
6282 13:41:52.476458 [CA 5] Center 36 (8~64) winsize 57
6283 13:41:52.479812
6284 13:41:52.482485 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6285 13:41:52.482566
6286 13:41:52.485859 [CATrainingPosCal] consider 2 rank data
6287 13:41:52.489579 u2DelayCellTimex100 = 270/100 ps
6288 13:41:52.492667 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 13:41:52.495707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 13:41:52.499329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 13:41:52.502843 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 13:41:52.506011 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 13:41:52.509332 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 13:41:52.509414
6295 13:41:52.512471 CA PerBit enable=1, Macro0, CA PI delay=36
6296 13:41:52.515870
6297 13:41:52.515958 [CBTSetCACLKResult] CA Dly = 36
6298 13:41:52.518888 CS Dly: 1 (0~32)
6299 13:41:52.518969
6300 13:41:52.521969 ----->DramcWriteLeveling(PI) begin...
6301 13:41:52.522051 ==
6302 13:41:52.525483 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 13:41:52.528798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 13:41:52.528952 ==
6305 13:41:52.532268 Write leveling (Byte 0): 40 => 8
6306 13:41:52.535458 Write leveling (Byte 1): 32 => 0
6307 13:41:52.538596 DramcWriteLeveling(PI) end<-----
6308 13:41:52.538677
6309 13:41:52.538740 ==
6310 13:41:52.541935 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 13:41:52.545078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 13:41:52.548390 ==
6313 13:41:52.548472 [Gating] SW mode calibration
6314 13:41:52.555136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6315 13:41:52.561521 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6316 13:41:52.564989 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 13:41:52.572234 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6318 13:41:52.575348 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 13:41:52.578146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 13:41:52.584730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 13:41:52.588043 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 13:41:52.591248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 13:41:52.598544 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 13:41:52.601553 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 13:41:52.604585 Total UI for P1: 0, mck2ui 16
6326 13:41:52.608242 best dqsien dly found for B0: ( 0, 14, 24)
6327 13:41:52.611384 Total UI for P1: 0, mck2ui 16
6328 13:41:52.614865 best dqsien dly found for B1: ( 0, 14, 24)
6329 13:41:52.617795 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6330 13:41:52.621137 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6331 13:41:52.621219
6332 13:41:52.624406 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 13:41:52.627803 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6334 13:41:52.631130 [Gating] SW calibration Done
6335 13:41:52.631211 ==
6336 13:41:52.634492 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 13:41:52.641061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 13:41:52.641144 ==
6339 13:41:52.641207 RX Vref Scan: 0
6340 13:41:52.641275
6341 13:41:52.644322 RX Vref 0 -> 0, step: 1
6342 13:41:52.644403
6343 13:41:52.647750 RX Delay -410 -> 252, step: 16
6344 13:41:52.650451 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6345 13:41:52.654127 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6346 13:41:52.660882 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6347 13:41:52.664037 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6348 13:41:52.667178 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6349 13:41:52.670454 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6350 13:41:52.676913 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6351 13:41:52.680495 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6352 13:41:52.683651 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6353 13:41:52.687188 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6354 13:41:52.693495 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6355 13:41:52.696932 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6356 13:41:52.700181 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6357 13:41:52.706555 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6358 13:41:52.709711 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6359 13:41:52.713405 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6360 13:41:52.713486 ==
6361 13:41:52.716555 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 13:41:52.719654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 13:41:52.722832 ==
6364 13:41:52.722914 DQS Delay:
6365 13:41:52.722977 DQS0 = 43, DQS1 = 59
6366 13:41:52.726123 DQM Delay:
6367 13:41:52.726212 DQM0 = 9, DQM1 = 11
6368 13:41:52.729496 DQ Delay:
6369 13:41:52.729576 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6370 13:41:52.732855 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6371 13:41:52.736133 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6372 13:41:52.739322 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6373 13:41:52.739404
6374 13:41:52.739468
6375 13:41:52.743340 ==
6376 13:41:52.743422 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 13:41:52.749357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 13:41:52.749440 ==
6379 13:41:52.749505
6380 13:41:52.749565
6381 13:41:52.753029 TX Vref Scan disable
6382 13:41:52.753111 == TX Byte 0 ==
6383 13:41:52.755895 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 13:41:52.762222 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 13:41:52.762317 == TX Byte 1 ==
6386 13:41:52.765610 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 13:41:52.772023 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 13:41:52.772106 ==
6389 13:41:52.775394 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 13:41:52.778875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 13:41:52.778958 ==
6392 13:41:52.779042
6393 13:41:52.779117
6394 13:41:52.781956 TX Vref Scan disable
6395 13:41:52.782037 == TX Byte 0 ==
6396 13:41:52.789306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 13:41:52.792034 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 13:41:52.792127 == TX Byte 1 ==
6399 13:41:52.798987 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6400 13:41:52.801924 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6401 13:41:52.802007
6402 13:41:52.802072 [DATLAT]
6403 13:41:52.805230 Freq=400, CH0 RK0
6404 13:41:52.805312
6405 13:41:52.805376 DATLAT Default: 0xf
6406 13:41:52.808530 0, 0xFFFF, sum = 0
6407 13:41:52.808614 1, 0xFFFF, sum = 0
6408 13:41:52.811900 2, 0xFFFF, sum = 0
6409 13:41:52.811982 3, 0xFFFF, sum = 0
6410 13:41:52.815447 4, 0xFFFF, sum = 0
6411 13:41:52.815531 5, 0xFFFF, sum = 0
6412 13:41:52.818777 6, 0xFFFF, sum = 0
6413 13:41:52.818861 7, 0xFFFF, sum = 0
6414 13:41:52.821966 8, 0xFFFF, sum = 0
6415 13:41:52.822048 9, 0xFFFF, sum = 0
6416 13:41:52.825100 10, 0xFFFF, sum = 0
6417 13:41:52.828397 11, 0xFFFF, sum = 0
6418 13:41:52.828480 12, 0xFFFF, sum = 0
6419 13:41:52.831771 13, 0x0, sum = 1
6420 13:41:52.831853 14, 0x0, sum = 2
6421 13:41:52.835101 15, 0x0, sum = 3
6422 13:41:52.835184 16, 0x0, sum = 4
6423 13:41:52.835250 best_step = 14
6424 13:41:52.838442
6425 13:41:52.838531 ==
6426 13:41:52.841558 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 13:41:52.844977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 13:41:52.845058 ==
6429 13:41:52.845123 RX Vref Scan: 1
6430 13:41:52.845184
6431 13:41:52.848421 RX Vref 0 -> 0, step: 1
6432 13:41:52.848503
6433 13:41:52.851080 RX Delay -359 -> 252, step: 8
6434 13:41:52.851162
6435 13:41:52.854361 Set Vref, RX VrefLevel [Byte0]: 60
6436 13:41:52.858092 [Byte1]: 50
6437 13:41:52.862104
6438 13:41:52.862193 Final RX Vref Byte 0 = 60 to rank0
6439 13:41:52.865264 Final RX Vref Byte 1 = 50 to rank0
6440 13:41:52.868409 Final RX Vref Byte 0 = 60 to rank1
6441 13:41:52.871881 Final RX Vref Byte 1 = 50 to rank1==
6442 13:41:52.875049 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 13:41:52.881970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 13:41:52.882054 ==
6445 13:41:52.882120 DQS Delay:
6446 13:41:52.884918 DQS0 = 48, DQS1 = 60
6447 13:41:52.885017 DQM Delay:
6448 13:41:52.885083 DQM0 = 11, DQM1 = 11
6449 13:41:52.888788 DQ Delay:
6450 13:41:52.891617 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6451 13:41:52.894869 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6452 13:41:52.894951 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6453 13:41:52.898576 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6454 13:41:52.901750
6455 13:41:52.901832
6456 13:41:52.908499 [DQSOSCAuto] RK0, (LSB)MR18= 0xba7c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6457 13:41:52.911628 CH0 RK0: MR19=C0C, MR18=BA7C
6458 13:41:52.918072 CH0_RK0: MR19=0xC0C, MR18=0xBA7C, DQSOSC=386, MR23=63, INC=396, DEC=264
6459 13:41:52.918155 ==
6460 13:41:52.921303 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 13:41:52.924579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 13:41:52.924673 ==
6463 13:41:52.927596 [Gating] SW mode calibration
6464 13:41:52.934516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6465 13:41:52.941078 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6466 13:41:52.944564 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 13:41:52.947696 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6468 13:41:52.954250 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 13:41:52.957601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 13:41:52.961062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 13:41:52.967385 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 13:41:52.970749 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 13:41:52.973979 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 13:41:52.980366 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 13:41:52.984184 Total UI for P1: 0, mck2ui 16
6476 13:41:52.987221 best dqsien dly found for B0: ( 0, 14, 24)
6477 13:41:52.987304 Total UI for P1: 0, mck2ui 16
6478 13:41:52.993786 best dqsien dly found for B1: ( 0, 14, 24)
6479 13:41:52.997056 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6480 13:41:53.000174 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6481 13:41:53.000257
6482 13:41:53.003719 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 13:41:53.007431 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6484 13:41:53.010352 [Gating] SW calibration Done
6485 13:41:53.010434 ==
6486 13:41:53.013540 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 13:41:53.016701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 13:41:53.016783 ==
6489 13:41:53.019939 RX Vref Scan: 0
6490 13:41:53.020021
6491 13:41:53.023168 RX Vref 0 -> 0, step: 1
6492 13:41:53.023250
6493 13:41:53.023314 RX Delay -410 -> 252, step: 16
6494 13:41:53.029768 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6495 13:41:53.033380 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6496 13:41:53.036510 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6497 13:41:53.043065 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6498 13:41:53.046383 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6499 13:41:53.049786 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6500 13:41:53.053109 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6501 13:41:53.059829 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6502 13:41:53.063217 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6503 13:41:53.066592 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6504 13:41:53.069805 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6505 13:41:53.076285 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6506 13:41:53.079613 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6507 13:41:53.082397 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6508 13:41:53.089543 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6509 13:41:53.092139 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6510 13:41:53.092240 ==
6511 13:41:53.095546 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 13:41:53.099025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 13:41:53.099140 ==
6514 13:41:53.102501 DQS Delay:
6515 13:41:53.102575 DQS0 = 35, DQS1 = 59
6516 13:41:53.102638 DQM Delay:
6517 13:41:53.105708 DQM0 = 3, DQM1 = 17
6518 13:41:53.105813 DQ Delay:
6519 13:41:53.109178 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6520 13:41:53.112102 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6521 13:41:53.115737 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6522 13:41:53.118566 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6523 13:41:53.118641
6524 13:41:53.118703
6525 13:41:53.118762 ==
6526 13:41:53.122102 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 13:41:53.125273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 13:41:53.125350 ==
6529 13:41:53.128450
6530 13:41:53.128520
6531 13:41:53.128581 TX Vref Scan disable
6532 13:41:53.132185 == TX Byte 0 ==
6533 13:41:53.135360 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6534 13:41:53.138398 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6535 13:41:53.141706 == TX Byte 1 ==
6536 13:41:53.145285 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6537 13:41:53.148106 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6538 13:41:53.148213 ==
6539 13:41:53.151284 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 13:41:53.157990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 13:41:53.158092 ==
6542 13:41:53.158229
6543 13:41:53.158292
6544 13:41:53.158353 TX Vref Scan disable
6545 13:41:53.161280 == TX Byte 0 ==
6546 13:41:53.164513 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6547 13:41:53.167956 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6548 13:41:53.171553 == TX Byte 1 ==
6549 13:41:53.174467 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6550 13:41:53.177660 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6551 13:41:53.177738
6552 13:41:53.181600 [DATLAT]
6553 13:41:53.181700 Freq=400, CH0 RK1
6554 13:41:53.181790
6555 13:41:53.184252 DATLAT Default: 0xe
6556 13:41:53.184349 0, 0xFFFF, sum = 0
6557 13:41:53.187458 1, 0xFFFF, sum = 0
6558 13:41:53.187565 2, 0xFFFF, sum = 0
6559 13:41:53.191411 3, 0xFFFF, sum = 0
6560 13:41:53.191486 4, 0xFFFF, sum = 0
6561 13:41:53.194142 5, 0xFFFF, sum = 0
6562 13:41:53.194280 6, 0xFFFF, sum = 0
6563 13:41:53.197366 7, 0xFFFF, sum = 0
6564 13:41:53.197449 8, 0xFFFF, sum = 0
6565 13:41:53.200600 9, 0xFFFF, sum = 0
6566 13:41:53.200703 10, 0xFFFF, sum = 0
6567 13:41:53.204356 11, 0xFFFF, sum = 0
6568 13:41:53.207268 12, 0xFFFF, sum = 0
6569 13:41:53.207352 13, 0x0, sum = 1
6570 13:41:53.211201 14, 0x0, sum = 2
6571 13:41:53.211278 15, 0x0, sum = 3
6572 13:41:53.211340 16, 0x0, sum = 4
6573 13:41:53.213921 best_step = 14
6574 13:41:53.214018
6575 13:41:53.214105 ==
6576 13:41:53.217146 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 13:41:53.221046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 13:41:53.221150 ==
6579 13:41:53.224249 RX Vref Scan: 0
6580 13:41:53.224347
6581 13:41:53.224436 RX Vref 0 -> 0, step: 1
6582 13:41:53.227259
6583 13:41:53.227356 RX Delay -359 -> 252, step: 8
6584 13:41:53.236141 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6585 13:41:53.239059 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6586 13:41:53.242594 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6587 13:41:53.248864 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6588 13:41:53.252121 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6589 13:41:53.255393 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6590 13:41:53.258665 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6591 13:41:53.265610 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6592 13:41:53.268931 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6593 13:41:53.272182 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6594 13:41:53.275567 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6595 13:41:53.281958 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6596 13:41:53.285265 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6597 13:41:53.288436 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6598 13:41:53.292508 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6599 13:41:53.298651 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6600 13:41:53.298733 ==
6601 13:41:53.301883 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 13:41:53.305141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 13:41:53.305257 ==
6604 13:41:53.305350 DQS Delay:
6605 13:41:53.308298 DQS0 = 44, DQS1 = 60
6606 13:41:53.308412 DQM Delay:
6607 13:41:53.311653 DQM0 = 7, DQM1 = 14
6608 13:41:53.311754 DQ Delay:
6609 13:41:53.315260 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6610 13:41:53.318359 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6611 13:41:53.321210 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6612 13:41:53.324521 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6613 13:41:53.324603
6614 13:41:53.324668
6615 13:41:53.331631 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23d, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6616 13:41:53.334814 CH0 RK1: MR19=C0C, MR18=B23D
6617 13:41:53.341486 CH0_RK1: MR19=0xC0C, MR18=0xB23D, DQSOSC=387, MR23=63, INC=394, DEC=262
6618 13:41:53.344809 [RxdqsGatingPostProcess] freq 400
6619 13:41:53.350867 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6620 13:41:53.354676 best DQS0 dly(2T, 0.5T) = (0, 10)
6621 13:41:53.357688 best DQS1 dly(2T, 0.5T) = (0, 10)
6622 13:41:53.360585 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6623 13:41:53.364265 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6624 13:41:53.367760 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 13:41:53.367842 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 13:41:53.370523 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 13:41:53.374317 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 13:41:53.376968 Pre-setting of DQS Precalculation
6629 13:41:53.383689 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6630 13:41:53.383771 ==
6631 13:41:53.387347 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 13:41:53.390509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 13:41:53.390592 ==
6634 13:41:53.397181 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 13:41:53.403695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6636 13:41:53.407121 [CA 0] Center 36 (8~64) winsize 57
6637 13:41:53.410351 [CA 1] Center 36 (8~64) winsize 57
6638 13:41:53.413476 [CA 2] Center 36 (8~64) winsize 57
6639 13:41:53.413558 [CA 3] Center 36 (8~64) winsize 57
6640 13:41:53.417089 [CA 4] Center 36 (8~64) winsize 57
6641 13:41:53.420367 [CA 5] Center 36 (8~64) winsize 57
6642 13:41:53.420449
6643 13:41:53.426653 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6644 13:41:53.426735
6645 13:41:53.430544 [CATrainingPosCal] consider 1 rank data
6646 13:41:53.433242 u2DelayCellTimex100 = 270/100 ps
6647 13:41:53.437015 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 13:41:53.440320 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 13:41:53.443500 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 13:41:53.446495 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 13:41:53.450362 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:41:53.453004 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 13:41:53.453086
6654 13:41:53.456504 CA PerBit enable=1, Macro0, CA PI delay=36
6655 13:41:53.456585
6656 13:41:53.460138 [CBTSetCACLKResult] CA Dly = 36
6657 13:41:53.463089 CS Dly: 1 (0~32)
6658 13:41:53.463171 ==
6659 13:41:53.466148 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 13:41:53.469474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 13:41:53.469558 ==
6662 13:41:53.476634 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 13:41:53.483276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6664 13:41:53.485844 [CA 0] Center 36 (8~64) winsize 57
6665 13:41:53.489073 [CA 1] Center 36 (8~64) winsize 57
6666 13:41:53.489155 [CA 2] Center 36 (8~64) winsize 57
6667 13:41:53.493076 [CA 3] Center 36 (8~64) winsize 57
6668 13:41:53.496197 [CA 4] Center 36 (8~64) winsize 57
6669 13:41:53.499480 [CA 5] Center 36 (8~64) winsize 57
6670 13:41:53.499562
6671 13:41:53.502882 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6672 13:41:53.506136
6673 13:41:53.509456 [CATrainingPosCal] consider 2 rank data
6674 13:41:53.509538 u2DelayCellTimex100 = 270/100 ps
6675 13:41:53.515463 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 13:41:53.519003 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 13:41:53.522194 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 13:41:53.525531 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 13:41:53.528811 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 13:41:53.532167 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 13:41:53.532249
6682 13:41:53.535582 CA PerBit enable=1, Macro0, CA PI delay=36
6683 13:41:53.535663
6684 13:41:53.538628 [CBTSetCACLKResult] CA Dly = 36
6685 13:41:53.542071 CS Dly: 1 (0~32)
6686 13:41:53.542152
6687 13:41:53.545376 ----->DramcWriteLeveling(PI) begin...
6688 13:41:53.545459 ==
6689 13:41:53.548685 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 13:41:53.551926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 13:41:53.552052 ==
6692 13:41:53.555419 Write leveling (Byte 0): 40 => 8
6693 13:41:53.558431 Write leveling (Byte 1): 32 => 0
6694 13:41:53.562041 DramcWriteLeveling(PI) end<-----
6695 13:41:53.562122
6696 13:41:53.562228 ==
6697 13:41:53.565377 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 13:41:53.568397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 13:41:53.568479 ==
6700 13:41:53.571598 [Gating] SW mode calibration
6701 13:41:53.578658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6702 13:41:53.585019 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6703 13:41:53.588238 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 13:41:53.594838 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6705 13:41:53.598114 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 13:41:53.601501 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 13:41:53.607912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 13:41:53.611146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 13:41:53.614284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 13:41:53.620980 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 13:41:53.624275 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 13:41:53.627644 Total UI for P1: 0, mck2ui 16
6713 13:41:53.631083 best dqsien dly found for B0: ( 0, 14, 24)
6714 13:41:53.634391 Total UI for P1: 0, mck2ui 16
6715 13:41:53.637502 best dqsien dly found for B1: ( 0, 14, 24)
6716 13:41:53.640888 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6717 13:41:53.644091 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6718 13:41:53.644173
6719 13:41:53.647474 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 13:41:53.650964 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6721 13:41:53.654136 [Gating] SW calibration Done
6722 13:41:53.654264 ==
6723 13:41:53.657415 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 13:41:53.660648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 13:41:53.663751 ==
6726 13:41:53.663832 RX Vref Scan: 0
6727 13:41:53.663897
6728 13:41:53.667154 RX Vref 0 -> 0, step: 1
6729 13:41:53.667235
6730 13:41:53.670309 RX Delay -410 -> 252, step: 16
6731 13:41:53.674059 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6732 13:41:53.677224 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6733 13:41:53.680342 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6734 13:41:53.686874 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6735 13:41:53.690061 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6736 13:41:53.693421 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6737 13:41:53.696904 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6738 13:41:53.703287 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6739 13:41:53.706451 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6740 13:41:53.710374 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6741 13:41:53.713141 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6742 13:41:53.720227 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6743 13:41:53.722988 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6744 13:41:53.726828 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6745 13:41:53.733705 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6746 13:41:53.736844 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6747 13:41:53.736926 ==
6748 13:41:53.740224 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 13:41:53.742842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 13:41:53.742924 ==
6751 13:41:53.746091 DQS Delay:
6752 13:41:53.746200 DQS0 = 43, DQS1 = 51
6753 13:41:53.750044 DQM Delay:
6754 13:41:53.750156 DQM0 = 12, DQM1 = 14
6755 13:41:53.750263 DQ Delay:
6756 13:41:53.753001 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6757 13:41:53.756373 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6758 13:41:53.759659 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6759 13:41:53.762844 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6760 13:41:53.762925
6761 13:41:53.762989
6762 13:41:53.763049 ==
6763 13:41:53.765923 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 13:41:53.773034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 13:41:53.773117 ==
6766 13:41:53.773182
6767 13:41:53.773241
6768 13:41:53.773298 TX Vref Scan disable
6769 13:41:53.776222 == TX Byte 0 ==
6770 13:41:53.779566 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 13:41:53.782705 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 13:41:53.786042 == TX Byte 1 ==
6773 13:41:53.788921 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6774 13:41:53.792704 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6775 13:41:53.792786 ==
6776 13:41:53.796001 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 13:41:53.802620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 13:41:53.802703 ==
6779 13:41:53.802767
6780 13:41:53.802826
6781 13:41:53.802884 TX Vref Scan disable
6782 13:41:53.805761 == TX Byte 0 ==
6783 13:41:53.809069 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 13:41:53.812155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 13:41:53.815396 == TX Byte 1 ==
6786 13:41:53.818706 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6787 13:41:53.825404 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6788 13:41:53.825486
6789 13:41:53.825550 [DATLAT]
6790 13:41:53.825610 Freq=400, CH1 RK0
6791 13:41:53.825669
6792 13:41:53.828668 DATLAT Default: 0xf
6793 13:41:53.828749 0, 0xFFFF, sum = 0
6794 13:41:53.832134 1, 0xFFFF, sum = 0
6795 13:41:53.835491 2, 0xFFFF, sum = 0
6796 13:41:53.835574 3, 0xFFFF, sum = 0
6797 13:41:53.838672 4, 0xFFFF, sum = 0
6798 13:41:53.838755 5, 0xFFFF, sum = 0
6799 13:41:53.842119 6, 0xFFFF, sum = 0
6800 13:41:53.842241 7, 0xFFFF, sum = 0
6801 13:41:53.845409 8, 0xFFFF, sum = 0
6802 13:41:53.845492 9, 0xFFFF, sum = 0
6803 13:41:53.848706 10, 0xFFFF, sum = 0
6804 13:41:53.848789 11, 0xFFFF, sum = 0
6805 13:41:53.852060 12, 0xFFFF, sum = 0
6806 13:41:53.852144 13, 0x0, sum = 1
6807 13:41:53.855342 14, 0x0, sum = 2
6808 13:41:53.855424 15, 0x0, sum = 3
6809 13:41:53.858525 16, 0x0, sum = 4
6810 13:41:53.858607 best_step = 14
6811 13:41:53.858673
6812 13:41:53.858740 ==
6813 13:41:53.861720 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 13:41:53.868569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 13:41:53.868652 ==
6816 13:41:53.868716 RX Vref Scan: 1
6817 13:41:53.868776
6818 13:41:53.871758 RX Vref 0 -> 0, step: 1
6819 13:41:53.871845
6820 13:41:53.875043 RX Delay -343 -> 252, step: 8
6821 13:41:53.875125
6822 13:41:53.878342 Set Vref, RX VrefLevel [Byte0]: 48
6823 13:41:53.881394 [Byte1]: 60
6824 13:41:53.881502
6825 13:41:53.884657 Final RX Vref Byte 0 = 48 to rank0
6826 13:41:53.887943 Final RX Vref Byte 1 = 60 to rank0
6827 13:41:53.891186 Final RX Vref Byte 0 = 48 to rank1
6828 13:41:53.894408 Final RX Vref Byte 1 = 60 to rank1==
6829 13:41:53.898067 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 13:41:53.900812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 13:41:53.904646 ==
6832 13:41:53.904728 DQS Delay:
6833 13:41:53.904793 DQS0 = 44, DQS1 = 56
6834 13:41:53.907989 DQM Delay:
6835 13:41:53.908071 DQM0 = 8, DQM1 = 12
6836 13:41:53.911443 DQ Delay:
6837 13:41:53.914455 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6838 13:41:53.914537 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6839 13:41:53.917538 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6840 13:41:53.920935 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6841 13:41:53.921017
6842 13:41:53.921086
6843 13:41:53.930660 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6844 13:41:53.933966 CH1 RK0: MR19=C0C, MR18=9B71
6845 13:41:53.940634 CH1_RK0: MR19=0xC0C, MR18=0x9B71, DQSOSC=390, MR23=63, INC=388, DEC=258
6846 13:41:53.940716 ==
6847 13:41:53.943879 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 13:41:53.947427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 13:41:53.947509 ==
6850 13:41:53.950584 [Gating] SW mode calibration
6851 13:41:53.957153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6852 13:41:53.963801 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6853 13:41:53.966856 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 13:41:53.970098 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6855 13:41:53.976840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 13:41:53.979867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 13:41:53.983509 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 13:41:53.989681 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 13:41:53.993433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 13:41:53.996808 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 13:41:54.003571 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 13:41:54.003654 Total UI for P1: 0, mck2ui 16
6863 13:41:54.009901 best dqsien dly found for B0: ( 0, 14, 24)
6864 13:41:54.009983 Total UI for P1: 0, mck2ui 16
6865 13:41:54.013061 best dqsien dly found for B1: ( 0, 14, 24)
6866 13:41:54.019696 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6867 13:41:54.023520 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6868 13:41:54.023602
6869 13:41:54.026645 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 13:41:54.029464 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6871 13:41:54.032836 [Gating] SW calibration Done
6872 13:41:54.032918 ==
6873 13:41:54.036111 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 13:41:54.039494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 13:41:54.039591 ==
6876 13:41:54.042822 RX Vref Scan: 0
6877 13:41:54.042903
6878 13:41:54.042967 RX Vref 0 -> 0, step: 1
6879 13:41:54.043028
6880 13:41:54.046056 RX Delay -410 -> 252, step: 16
6881 13:41:54.052587 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6882 13:41:54.055805 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6883 13:41:54.059101 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6884 13:41:54.062484 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6885 13:41:54.069280 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6886 13:41:54.072513 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6887 13:41:54.075608 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6888 13:41:54.079064 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6889 13:41:54.085592 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6890 13:41:54.088974 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6891 13:41:54.092596 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6892 13:41:54.095498 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6893 13:41:54.102317 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6894 13:41:54.105356 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6895 13:41:54.108722 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6896 13:41:54.115142 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6897 13:41:54.115224 ==
6898 13:41:54.119111 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 13:41:54.121964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 13:41:54.122046 ==
6901 13:41:54.122111 DQS Delay:
6902 13:41:54.125283 DQS0 = 51, DQS1 = 59
6903 13:41:54.125365 DQM Delay:
6904 13:41:54.128621 DQM0 = 18, DQM1 = 21
6905 13:41:54.128727 DQ Delay:
6906 13:41:54.131623 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6907 13:41:54.135657 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6908 13:41:54.138291 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6909 13:41:54.141569 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6910 13:41:54.141649
6911 13:41:54.141714
6912 13:41:54.141774 ==
6913 13:41:54.144951 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 13:41:54.148273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 13:41:54.148355 ==
6916 13:41:54.148419
6917 13:41:54.151520
6918 13:41:54.151601 TX Vref Scan disable
6919 13:41:54.155076 == TX Byte 0 ==
6920 13:41:54.158299 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6921 13:41:54.161578 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6922 13:41:54.164951 == TX Byte 1 ==
6923 13:41:54.168236 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6924 13:41:54.171616 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6925 13:41:54.171705 ==
6926 13:41:54.174919 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 13:41:54.178350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 13:41:54.181514 ==
6929 13:41:54.181590
6930 13:41:54.181665
6931 13:41:54.181736 TX Vref Scan disable
6932 13:41:54.184926 == TX Byte 0 ==
6933 13:41:54.188447 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6934 13:41:54.191740 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6935 13:41:54.194992 == TX Byte 1 ==
6936 13:41:54.197854 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6937 13:41:54.201109 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6938 13:41:54.201188
6939 13:41:54.201262 [DATLAT]
6940 13:41:54.204653 Freq=400, CH1 RK1
6941 13:41:54.204739
6942 13:41:54.208054 DATLAT Default: 0xe
6943 13:41:54.208136 0, 0xFFFF, sum = 0
6944 13:41:54.211213 1, 0xFFFF, sum = 0
6945 13:41:54.211301 2, 0xFFFF, sum = 0
6946 13:41:54.214557 3, 0xFFFF, sum = 0
6947 13:41:54.214642 4, 0xFFFF, sum = 0
6948 13:41:54.217799 5, 0xFFFF, sum = 0
6949 13:41:54.217912 6, 0xFFFF, sum = 0
6950 13:41:54.221103 7, 0xFFFF, sum = 0
6951 13:41:54.221187 8, 0xFFFF, sum = 0
6952 13:41:54.224316 9, 0xFFFF, sum = 0
6953 13:41:54.224400 10, 0xFFFF, sum = 0
6954 13:41:54.227698 11, 0xFFFF, sum = 0
6955 13:41:54.227793 12, 0xFFFF, sum = 0
6956 13:41:54.230923 13, 0x0, sum = 1
6957 13:41:54.231006 14, 0x0, sum = 2
6958 13:41:54.233924 15, 0x0, sum = 3
6959 13:41:54.234006 16, 0x0, sum = 4
6960 13:41:54.237327 best_step = 14
6961 13:41:54.237435
6962 13:41:54.237528 ==
6963 13:41:54.240835 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 13:41:54.244300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 13:41:54.244397 ==
6966 13:41:54.247522 RX Vref Scan: 0
6967 13:41:54.247603
6968 13:41:54.247667 RX Vref 0 -> 0, step: 1
6969 13:41:54.247729
6970 13:41:54.251171 RX Delay -359 -> 252, step: 8
6971 13:41:54.258915 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6972 13:41:54.262334 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6973 13:41:54.265527 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6974 13:41:54.268897 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6975 13:41:54.275512 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6976 13:41:54.278906 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6977 13:41:54.282279 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6978 13:41:54.285552 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6979 13:41:54.292057 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
6980 13:41:54.295390 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6981 13:41:54.298843 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6982 13:41:54.305434 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
6983 13:41:54.308129 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6984 13:41:54.311952 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6985 13:41:54.315174 iDelay=225, Bit 14, Center -36 (-287 ~ 216) 504
6986 13:41:54.321659 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6987 13:41:54.321740 ==
6988 13:41:54.325370 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 13:41:54.328280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 13:41:54.328358 ==
6991 13:41:54.328452 DQS Delay:
6992 13:41:54.331765 DQS0 = 48, DQS1 = 60
6993 13:41:54.331852 DQM Delay:
6994 13:41:54.334838 DQM0 = 12, DQM1 = 15
6995 13:41:54.334943 DQ Delay:
6996 13:41:54.338099 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6997 13:41:54.341328 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6998 13:41:54.344533 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6999 13:41:54.347938 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
7000 13:41:54.348046
7001 13:41:54.348138
7002 13:41:54.354567 [DQSOSCAuto] RK1, (LSB)MR18= 0x6756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7003 13:41:54.358377 CH1 RK1: MR19=C0C, MR18=6756
7004 13:41:54.364796 CH1_RK1: MR19=0xC0C, MR18=0x6756, DQSOSC=396, MR23=63, INC=376, DEC=251
7005 13:41:54.368148 [RxdqsGatingPostProcess] freq 400
7006 13:41:54.374704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7007 13:41:54.377994 best DQS0 dly(2T, 0.5T) = (0, 10)
7008 13:41:54.381314 best DQS1 dly(2T, 0.5T) = (0, 10)
7009 13:41:54.384516 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7010 13:41:54.387726 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7011 13:41:54.387801 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 13:41:54.391129 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 13:41:54.394462 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 13:41:54.397843 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 13:41:54.401114 Pre-setting of DQS Precalculation
7016 13:41:54.407847 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7017 13:41:54.414115 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7018 13:41:54.420654 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7019 13:41:54.420759
7020 13:41:54.420850
7021 13:41:54.424479 [Calibration Summary] 800 Mbps
7022 13:41:54.424593 CH 0, Rank 0
7023 13:41:54.427617 SW Impedance : PASS
7024 13:41:54.430836 DUTY Scan : NO K
7025 13:41:54.430911 ZQ Calibration : PASS
7026 13:41:54.433917 Jitter Meter : NO K
7027 13:41:54.437128 CBT Training : PASS
7028 13:41:54.437236 Write leveling : PASS
7029 13:41:54.440523 RX DQS gating : PASS
7030 13:41:54.444293 RX DQ/DQS(RDDQC) : PASS
7031 13:41:54.444369 TX DQ/DQS : PASS
7032 13:41:54.447059 RX DATLAT : PASS
7033 13:41:54.450673 RX DQ/DQS(Engine): PASS
7034 13:41:54.450755 TX OE : NO K
7035 13:41:54.453589 All Pass.
7036 13:41:54.453670
7037 13:41:54.453734 CH 0, Rank 1
7038 13:41:54.456758 SW Impedance : PASS
7039 13:41:54.456840 DUTY Scan : NO K
7040 13:41:54.460429 ZQ Calibration : PASS
7041 13:41:54.463863 Jitter Meter : NO K
7042 13:41:54.463943 CBT Training : PASS
7043 13:41:54.466863 Write leveling : NO K
7044 13:41:54.470402 RX DQS gating : PASS
7045 13:41:54.470498 RX DQ/DQS(RDDQC) : PASS
7046 13:41:54.473543 TX DQ/DQS : PASS
7047 13:41:54.476948 RX DATLAT : PASS
7048 13:41:54.477032 RX DQ/DQS(Engine): PASS
7049 13:41:54.480136 TX OE : NO K
7050 13:41:54.480244 All Pass.
7051 13:41:54.480337
7052 13:41:54.482991 CH 1, Rank 0
7053 13:41:54.483073 SW Impedance : PASS
7054 13:41:54.486934 DUTY Scan : NO K
7055 13:41:54.489595 ZQ Calibration : PASS
7056 13:41:54.489677 Jitter Meter : NO K
7057 13:41:54.493495 CBT Training : PASS
7058 13:41:54.496039 Write leveling : PASS
7059 13:41:54.496148 RX DQS gating : PASS
7060 13:41:54.499409 RX DQ/DQS(RDDQC) : PASS
7061 13:41:54.499491 TX DQ/DQS : PASS
7062 13:41:54.503502 RX DATLAT : PASS
7063 13:41:54.506042 RX DQ/DQS(Engine): PASS
7064 13:41:54.506123 TX OE : NO K
7065 13:41:54.509339 All Pass.
7066 13:41:54.509420
7067 13:41:54.509483 CH 1, Rank 1
7068 13:41:54.513376 SW Impedance : PASS
7069 13:41:54.513457 DUTY Scan : NO K
7070 13:41:54.516573 ZQ Calibration : PASS
7071 13:41:54.519566 Jitter Meter : NO K
7072 13:41:54.519673 CBT Training : PASS
7073 13:41:54.522966 Write leveling : NO K
7074 13:41:54.526196 RX DQS gating : PASS
7075 13:41:54.526292 RX DQ/DQS(RDDQC) : PASS
7076 13:41:54.529315 TX DQ/DQS : PASS
7077 13:41:54.532857 RX DATLAT : PASS
7078 13:41:54.532938 RX DQ/DQS(Engine): PASS
7079 13:41:54.536170 TX OE : NO K
7080 13:41:54.536251 All Pass.
7081 13:41:54.536317
7082 13:41:54.539502 DramC Write-DBI off
7083 13:41:54.542541 PER_BANK_REFRESH: Hybrid Mode
7084 13:41:54.542629 TX_TRACKING: ON
7085 13:41:54.552758 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7086 13:41:54.555952 [FAST_K] Save calibration result to emmc
7087 13:41:54.559642 dramc_set_vcore_voltage set vcore to 725000
7088 13:41:54.562428 Read voltage for 1600, 0
7089 13:41:54.562509 Vio18 = 0
7090 13:41:54.562586 Vcore = 725000
7091 13:41:54.566028 Vdram = 0
7092 13:41:54.566135 Vddq = 0
7093 13:41:54.566247 Vmddr = 0
7094 13:41:54.572150 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7095 13:41:54.575768 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7096 13:41:54.578801 MEM_TYPE=3, freq_sel=13
7097 13:41:54.582123 sv_algorithm_assistance_LP4_3733
7098 13:41:54.585353 ============ PULL DRAM RESETB DOWN ============
7099 13:41:54.591956 ========== PULL DRAM RESETB DOWN end =========
7100 13:41:54.595536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7101 13:41:54.598870 ===================================
7102 13:41:54.602094 LPDDR4 DRAM CONFIGURATION
7103 13:41:54.605607 ===================================
7104 13:41:54.605709 EX_ROW_EN[0] = 0x0
7105 13:41:54.608284 EX_ROW_EN[1] = 0x0
7106 13:41:54.608365 LP4Y_EN = 0x0
7107 13:41:54.611530 WORK_FSP = 0x1
7108 13:41:54.611612 WL = 0x5
7109 13:41:54.615522 RL = 0x5
7110 13:41:54.618755 BL = 0x2
7111 13:41:54.618836 RPST = 0x0
7112 13:41:54.621850 RD_PRE = 0x0
7113 13:41:54.621931 WR_PRE = 0x1
7114 13:41:54.625012 WR_PST = 0x1
7115 13:41:54.625128 DBI_WR = 0x0
7116 13:41:54.628525 DBI_RD = 0x0
7117 13:41:54.628606 OTF = 0x1
7118 13:41:54.631728 ===================================
7119 13:41:54.634915 ===================================
7120 13:41:54.638078 ANA top config
7121 13:41:54.641099 ===================================
7122 13:41:54.641181 DLL_ASYNC_EN = 0
7123 13:41:54.645115 ALL_SLAVE_EN = 0
7124 13:41:54.648338 NEW_RANK_MODE = 1
7125 13:41:54.651423 DLL_IDLE_MODE = 1
7126 13:41:54.651505 LP45_APHY_COMB_EN = 1
7127 13:41:54.654745 TX_ODT_DIS = 0
7128 13:41:54.658073 NEW_8X_MODE = 1
7129 13:41:54.661544 ===================================
7130 13:41:54.664595 ===================================
7131 13:41:54.667801 data_rate = 3200
7132 13:41:54.671325 CKR = 1
7133 13:41:54.674291 DQ_P2S_RATIO = 8
7134 13:41:54.677544 ===================================
7135 13:41:54.677626 CA_P2S_RATIO = 8
7136 13:41:54.681003 DQ_CA_OPEN = 0
7137 13:41:54.683880 DQ_SEMI_OPEN = 0
7138 13:41:54.687547 CA_SEMI_OPEN = 0
7139 13:41:54.690719 CA_FULL_RATE = 0
7140 13:41:54.694448 DQ_CKDIV4_EN = 0
7141 13:41:54.694530 CA_CKDIV4_EN = 0
7142 13:41:54.697622 CA_PREDIV_EN = 0
7143 13:41:54.700900 PH8_DLY = 12
7144 13:41:54.704072 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7145 13:41:54.707354 DQ_AAMCK_DIV = 4
7146 13:41:54.710729 CA_AAMCK_DIV = 4
7147 13:41:54.714016 CA_ADMCK_DIV = 4
7148 13:41:54.714097 DQ_TRACK_CA_EN = 0
7149 13:41:54.717547 CA_PICK = 1600
7150 13:41:54.720597 CA_MCKIO = 1600
7151 13:41:54.723891 MCKIO_SEMI = 0
7152 13:41:54.727245 PLL_FREQ = 3068
7153 13:41:54.730514 DQ_UI_PI_RATIO = 32
7154 13:41:54.733756 CA_UI_PI_RATIO = 0
7155 13:41:54.737093 ===================================
7156 13:41:54.740334 ===================================
7157 13:41:54.740416 memory_type:LPDDR4
7158 13:41:54.743645 GP_NUM : 10
7159 13:41:54.746940 SRAM_EN : 1
7160 13:41:54.747021 MD32_EN : 0
7161 13:41:54.750113 ===================================
7162 13:41:54.753554 [ANA_INIT] >>>>>>>>>>>>>>
7163 13:41:54.756637 <<<<<< [CONFIGURE PHASE]: ANA_TX
7164 13:41:54.759970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7165 13:41:54.763437 ===================================
7166 13:41:54.766790 data_rate = 3200,PCW = 0X7600
7167 13:41:54.770157 ===================================
7168 13:41:54.773319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7169 13:41:54.776517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 13:41:54.783204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7171 13:41:54.786056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7172 13:41:54.789744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7173 13:41:54.796140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7174 13:41:54.796225 [ANA_INIT] flow start
7175 13:41:54.799381 [ANA_INIT] PLL >>>>>>>>
7176 13:41:54.802934 [ANA_INIT] PLL <<<<<<<<
7177 13:41:54.803016 [ANA_INIT] MIDPI >>>>>>>>
7178 13:41:54.806563 [ANA_INIT] MIDPI <<<<<<<<
7179 13:41:54.809234 [ANA_INIT] DLL >>>>>>>>
7180 13:41:54.809316 [ANA_INIT] DLL <<<<<<<<
7181 13:41:54.812633 [ANA_INIT] flow end
7182 13:41:54.816076 ============ LP4 DIFF to SE enter ============
7183 13:41:54.819282 ============ LP4 DIFF to SE exit ============
7184 13:41:54.822621 [ANA_INIT] <<<<<<<<<<<<<
7185 13:41:54.826097 [Flow] Enable top DCM control >>>>>
7186 13:41:54.829378 [Flow] Enable top DCM control <<<<<
7187 13:41:54.832486 Enable DLL master slave shuffle
7188 13:41:54.839055 ==============================================================
7189 13:41:54.839143 Gating Mode config
7190 13:41:54.845686 ==============================================================
7191 13:41:54.845772 Config description:
7192 13:41:54.855547 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7193 13:41:54.862309 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7194 13:41:54.868962 SELPH_MODE 0: By rank 1: By Phase
7195 13:41:54.875641 ==============================================================
7196 13:41:54.875734 GAT_TRACK_EN = 1
7197 13:41:54.878939 RX_GATING_MODE = 2
7198 13:41:54.882327 RX_GATING_TRACK_MODE = 2
7199 13:41:54.885572 SELPH_MODE = 1
7200 13:41:54.888867 PICG_EARLY_EN = 1
7201 13:41:54.892340 VALID_LAT_VALUE = 1
7202 13:41:54.898869 ==============================================================
7203 13:41:54.901350 Enter into Gating configuration >>>>
7204 13:41:54.905409 Exit from Gating configuration <<<<
7205 13:41:54.908486 Enter into DVFS_PRE_config >>>>>
7206 13:41:54.918042 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7207 13:41:54.921684 Exit from DVFS_PRE_config <<<<<
7208 13:41:54.924626 Enter into PICG configuration >>>>
7209 13:41:54.928124 Exit from PICG configuration <<<<
7210 13:41:54.931407 [RX_INPUT] configuration >>>>>
7211 13:41:54.934528 [RX_INPUT] configuration <<<<<
7212 13:41:54.937853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7213 13:41:54.944354 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7214 13:41:54.950916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 13:41:54.957922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 13:41:54.961128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 13:41:54.967550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 13:41:54.970750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7219 13:41:54.977671 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7220 13:41:54.981062 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7221 13:41:54.983606 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7222 13:41:54.990397 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7223 13:41:54.993602 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 13:41:54.996776 ===================================
7225 13:41:55.000150 LPDDR4 DRAM CONFIGURATION
7226 13:41:55.003430 ===================================
7227 13:41:55.003512 EX_ROW_EN[0] = 0x0
7228 13:41:55.007345 EX_ROW_EN[1] = 0x0
7229 13:41:55.007427 LP4Y_EN = 0x0
7230 13:41:55.010484 WORK_FSP = 0x1
7231 13:41:55.010566 WL = 0x5
7232 13:41:55.013711 RL = 0x5
7233 13:41:55.013793 BL = 0x2
7234 13:41:55.016431 RPST = 0x0
7235 13:41:55.020203 RD_PRE = 0x0
7236 13:41:55.020284 WR_PRE = 0x1
7237 13:41:55.023447 WR_PST = 0x1
7238 13:41:55.023529 DBI_WR = 0x0
7239 13:41:55.026820 DBI_RD = 0x0
7240 13:41:55.026901 OTF = 0x1
7241 13:41:55.030038 ===================================
7242 13:41:55.033641 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7243 13:41:55.039772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7244 13:41:55.043254 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 13:41:55.046397 ===================================
7246 13:41:55.049649 LPDDR4 DRAM CONFIGURATION
7247 13:41:55.052803 ===================================
7248 13:41:55.052885 EX_ROW_EN[0] = 0x10
7249 13:41:55.056116 EX_ROW_EN[1] = 0x0
7250 13:41:55.056198 LP4Y_EN = 0x0
7251 13:41:55.059422 WORK_FSP = 0x1
7252 13:41:55.062842 WL = 0x5
7253 13:41:55.062949 RL = 0x5
7254 13:41:55.066204 BL = 0x2
7255 13:41:55.066286 RPST = 0x0
7256 13:41:55.069525 RD_PRE = 0x0
7257 13:41:55.069606 WR_PRE = 0x1
7258 13:41:55.072274 WR_PST = 0x1
7259 13:41:55.072356 DBI_WR = 0x0
7260 13:41:55.075696 DBI_RD = 0x0
7261 13:41:55.075804 OTF = 0x1
7262 13:41:55.079104 ===================================
7263 13:41:55.085626 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7264 13:41:55.085708 ==
7265 13:41:55.088596 Dram Type= 6, Freq= 0, CH_0, rank 0
7266 13:41:55.091903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7267 13:41:55.095476 ==
7268 13:41:55.095587 [Duty_Offset_Calibration]
7269 13:41:55.098806 B0:1 B1:-1 CA:0
7270 13:41:55.098888
7271 13:41:55.102021 [DutyScan_Calibration_Flow] k_type=0
7272 13:41:55.111069
7273 13:41:55.111176 ==CLK 0==
7274 13:41:55.114400 Final CLK duty delay cell = 0
7275 13:41:55.117568 [0] MAX Duty = 5124%(X100), DQS PI = 22
7276 13:41:55.121016 [0] MIN Duty = 4907%(X100), DQS PI = 4
7277 13:41:55.121098 [0] AVG Duty = 5015%(X100)
7278 13:41:55.124272
7279 13:41:55.127583 CH0 CLK Duty spec in!! Max-Min= 217%
7280 13:41:55.130859 [DutyScan_Calibration_Flow] ====Done====
7281 13:41:55.130967
7282 13:41:55.134273 [DutyScan_Calibration_Flow] k_type=1
7283 13:41:55.150233
7284 13:41:55.150340 ==DQS 0 ==
7285 13:41:55.153299 Final DQS duty delay cell = -4
7286 13:41:55.156905 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7287 13:41:55.160204 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7288 13:41:55.163508 [-4] AVG Duty = 4922%(X100)
7289 13:41:55.163616
7290 13:41:55.163710 ==DQS 1 ==
7291 13:41:55.166843 Final DQS duty delay cell = 0
7292 13:41:55.170092 [0] MAX Duty = 5156%(X100), DQS PI = 2
7293 13:41:55.173342 [0] MIN Duty = 5000%(X100), DQS PI = 20
7294 13:41:55.176746 [0] AVG Duty = 5078%(X100)
7295 13:41:55.176831
7296 13:41:55.180134 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7297 13:41:55.180216
7298 13:41:55.183536 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7299 13:41:55.186793 [DutyScan_Calibration_Flow] ====Done====
7300 13:41:55.186881
7301 13:41:55.190060 [DutyScan_Calibration_Flow] k_type=3
7302 13:41:55.207532
7303 13:41:55.207617 ==DQM 0 ==
7304 13:41:55.211053 Final DQM duty delay cell = 0
7305 13:41:55.214354 [0] MAX Duty = 5124%(X100), DQS PI = 24
7306 13:41:55.217643 [0] MIN Duty = 4907%(X100), DQS PI = 10
7307 13:41:55.220480 [0] AVG Duty = 5015%(X100)
7308 13:41:55.220586
7309 13:41:55.220679 ==DQM 1 ==
7310 13:41:55.224536 Final DQM duty delay cell = 0
7311 13:41:55.227095 [0] MAX Duty = 5000%(X100), DQS PI = 4
7312 13:41:55.230389 [0] MIN Duty = 4782%(X100), DQS PI = 20
7313 13:41:55.233925 [0] AVG Duty = 4891%(X100)
7314 13:41:55.234030
7315 13:41:55.237190 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7316 13:41:55.237271
7317 13:41:55.240459 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7318 13:41:55.243809 [DutyScan_Calibration_Flow] ====Done====
7319 13:41:55.243890
7320 13:41:55.247097 [DutyScan_Calibration_Flow] k_type=2
7321 13:41:55.264436
7322 13:41:55.264529 ==DQ 0 ==
7323 13:41:55.267350 Final DQ duty delay cell = -4
7324 13:41:55.270319 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7325 13:41:55.273993 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7326 13:41:55.277122 [-4] AVG Duty = 4953%(X100)
7327 13:41:55.277204
7328 13:41:55.277268 ==DQ 1 ==
7329 13:41:55.280558 Final DQ duty delay cell = 0
7330 13:41:55.283417 [0] MAX Duty = 5125%(X100), DQS PI = 4
7331 13:41:55.287447 [0] MIN Duty = 5000%(X100), DQS PI = 34
7332 13:41:55.290002 [0] AVG Duty = 5062%(X100)
7333 13:41:55.290115
7334 13:41:55.293287 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7335 13:41:55.293413
7336 13:41:55.297094 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7337 13:41:55.300635 [DutyScan_Calibration_Flow] ====Done====
7338 13:41:55.300777 ==
7339 13:41:55.303241 Dram Type= 6, Freq= 0, CH_1, rank 0
7340 13:41:55.306895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 13:41:55.307041 ==
7342 13:41:55.310080 [Duty_Offset_Calibration]
7343 13:41:55.310201 B0:-1 B1:1 CA:1
7344 13:41:55.313367
7345 13:41:55.316453 [DutyScan_Calibration_Flow] k_type=0
7346 13:41:55.324860
7347 13:41:55.325035 ==CLK 0==
7348 13:41:55.327943 Final CLK duty delay cell = 0
7349 13:41:55.331337 [0] MAX Duty = 5187%(X100), DQS PI = 24
7350 13:41:55.334626 [0] MIN Duty = 5000%(X100), DQS PI = 0
7351 13:41:55.334762 [0] AVG Duty = 5093%(X100)
7352 13:41:55.338180
7353 13:41:55.341462 CH1 CLK Duty spec in!! Max-Min= 187%
7354 13:41:55.344724 [DutyScan_Calibration_Flow] ====Done====
7355 13:41:55.344858
7356 13:41:55.348180 [DutyScan_Calibration_Flow] k_type=1
7357 13:41:55.365012
7358 13:41:55.365521 ==DQS 0 ==
7359 13:41:55.367607 Final DQS duty delay cell = 0
7360 13:41:55.371470 [0] MAX Duty = 5124%(X100), DQS PI = 18
7361 13:41:55.374823 [0] MIN Duty = 4907%(X100), DQS PI = 10
7362 13:41:55.377969 [0] AVG Duty = 5015%(X100)
7363 13:41:55.378438
7364 13:41:55.378772 ==DQS 1 ==
7365 13:41:55.381017 Final DQS duty delay cell = 0
7366 13:41:55.384551 [0] MAX Duty = 5093%(X100), DQS PI = 28
7367 13:41:55.387994 [0] MIN Duty = 4969%(X100), DQS PI = 54
7368 13:41:55.391531 [0] AVG Duty = 5031%(X100)
7369 13:41:55.391949
7370 13:41:55.394234 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7371 13:41:55.394660
7372 13:41:55.397785 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7373 13:41:55.400905 [DutyScan_Calibration_Flow] ====Done====
7374 13:41:55.401323
7375 13:41:55.404161 [DutyScan_Calibration_Flow] k_type=3
7376 13:41:55.420740
7377 13:41:55.421330 ==DQM 0 ==
7378 13:41:55.424005 Final DQM duty delay cell = -4
7379 13:41:55.427391 [-4] MAX Duty = 5031%(X100), DQS PI = 34
7380 13:41:55.430505 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7381 13:41:55.434513 [-4] AVG Duty = 4906%(X100)
7382 13:41:55.434932
7383 13:41:55.435262 ==DQM 1 ==
7384 13:41:55.437597 Final DQM duty delay cell = 0
7385 13:41:55.440622 [0] MAX Duty = 5125%(X100), DQS PI = 0
7386 13:41:55.444151 [0] MIN Duty = 4938%(X100), DQS PI = 34
7387 13:41:55.446963 [0] AVG Duty = 5031%(X100)
7388 13:41:55.447447
7389 13:41:55.450504 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7390 13:41:55.450971
7391 13:41:55.453773 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7392 13:41:55.457075 [DutyScan_Calibration_Flow] ====Done====
7393 13:41:55.457497
7394 13:41:55.460141 [DutyScan_Calibration_Flow] k_type=2
7395 13:41:55.477951
7396 13:41:55.478419 ==DQ 0 ==
7397 13:41:55.481491 Final DQ duty delay cell = 0
7398 13:41:55.484613 [0] MAX Duty = 5156%(X100), DQS PI = 30
7399 13:41:55.488077 [0] MIN Duty = 4906%(X100), DQS PI = 8
7400 13:41:55.491319 [0] AVG Duty = 5031%(X100)
7401 13:41:55.492041
7402 13:41:55.492622 ==DQ 1 ==
7403 13:41:55.494378 Final DQ duty delay cell = 0
7404 13:41:55.497282 [0] MAX Duty = 5156%(X100), DQS PI = 8
7405 13:41:55.500867 [0] MIN Duty = 4969%(X100), DQS PI = 56
7406 13:41:55.503940 [0] AVG Duty = 5062%(X100)
7407 13:41:55.504487
7408 13:41:55.507214 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7409 13:41:55.507635
7410 13:41:55.510713 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7411 13:41:55.513920 [DutyScan_Calibration_Flow] ====Done====
7412 13:41:55.517103 nWR fixed to 30
7413 13:41:55.520383 [ModeRegInit_LP4] CH0 RK0
7414 13:41:55.520807 [ModeRegInit_LP4] CH0 RK1
7415 13:41:55.524050 [ModeRegInit_LP4] CH1 RK0
7416 13:41:55.527346 [ModeRegInit_LP4] CH1 RK1
7417 13:41:55.527766 match AC timing 5
7418 13:41:55.533903 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7419 13:41:55.537231 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7420 13:41:55.540335 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7421 13:41:55.546904 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7422 13:41:55.550120 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7423 13:41:55.550588 [MiockJmeterHQA]
7424 13:41:55.553946
7425 13:41:55.554588 [DramcMiockJmeter] u1RxGatingPI = 0
7426 13:41:55.557104 0 : 4255, 4029
7427 13:41:55.557620 4 : 4252, 4027
7428 13:41:55.559739 8 : 4253, 4027
7429 13:41:55.560306 12 : 4363, 4137
7430 13:41:55.563145 16 : 4252, 4027
7431 13:41:55.563574 20 : 4255, 4029
7432 13:41:55.566909 24 : 4253, 4027
7433 13:41:55.567434 28 : 4363, 4138
7434 13:41:55.567774 32 : 4252, 4027
7435 13:41:55.570226 36 : 4363, 4137
7436 13:41:55.570745 40 : 4253, 4027
7437 13:41:55.573364 44 : 4252, 4026
7438 13:41:55.573809 48 : 4252, 4027
7439 13:41:55.576662 52 : 4253, 4027
7440 13:41:55.577084 56 : 4363, 4137
7441 13:41:55.579845 60 : 4253, 4029
7442 13:41:55.580273 64 : 4361, 4137
7443 13:41:55.580656 68 : 4250, 4027
7444 13:41:55.583643 72 : 4250, 4027
7445 13:41:55.584349 76 : 4250, 4026
7446 13:41:55.586467 80 : 4360, 4138
7447 13:41:55.586891 84 : 4250, 4027
7448 13:41:55.589665 88 : 4361, 4138
7449 13:41:55.590090 92 : 4250, 751
7450 13:41:55.590489 96 : 4361, 0
7451 13:41:55.593104 100 : 4250, 0
7452 13:41:55.593668 104 : 4250, 0
7453 13:41:55.595845 108 : 4250, 0
7454 13:41:55.596271 112 : 4250, 0
7455 13:41:55.596609 116 : 4252, 0
7456 13:41:55.599043 120 : 4250, 0
7457 13:41:55.599469 124 : 4250, 0
7458 13:41:55.603067 128 : 4253, 0
7459 13:41:55.603492 132 : 4361, 0
7460 13:41:55.603828 136 : 4360, 0
7461 13:41:55.606120 140 : 4363, 0
7462 13:41:55.606578 144 : 4250, 0
7463 13:41:55.609568 148 : 4250, 0
7464 13:41:55.610089 152 : 4250, 0
7465 13:41:55.610474 156 : 4250, 0
7466 13:41:55.612434 160 : 4250, 0
7467 13:41:55.612857 164 : 4250, 0
7468 13:41:55.615560 168 : 4253, 0
7469 13:41:55.615985 172 : 4253, 0
7470 13:41:55.616320 176 : 4250, 0
7471 13:41:55.618996 180 : 4252, 0
7472 13:41:55.619433 184 : 4363, 0
7473 13:41:55.622547 188 : 4360, 0
7474 13:41:55.623075 192 : 4363, 0
7475 13:41:55.623421 196 : 4250, 0
7476 13:41:55.625675 200 : 4250, 0
7477 13:41:55.626100 204 : 4250, 0
7478 13:41:55.626491 208 : 4250, 0
7479 13:41:55.629162 212 : 4250, 0
7480 13:41:55.629676 216 : 4250, 0
7481 13:41:55.632350 220 : 4253, 0
7482 13:41:55.632935 224 : 4250, 167
7483 13:41:55.635328 228 : 4249, 3120
7484 13:41:55.635754 232 : 4250, 4027
7485 13:41:55.638776 236 : 4250, 4026
7486 13:41:55.639200 240 : 4361, 4137
7487 13:41:55.639636 244 : 4250, 4027
7488 13:41:55.641901 248 : 4250, 4026
7489 13:41:55.642367 252 : 4361, 4138
7490 13:41:55.645632 256 : 4360, 4137
7491 13:41:55.646058 260 : 4363, 4137
7492 13:41:55.648866 264 : 4361, 4137
7493 13:41:55.649293 268 : 4361, 4137
7494 13:41:55.652578 272 : 4250, 4027
7495 13:41:55.653121 276 : 4250, 4027
7496 13:41:55.655964 280 : 4250, 4027
7497 13:41:55.656482 284 : 4250, 4027
7498 13:41:55.659113 288 : 4250, 4027
7499 13:41:55.659823 292 : 4250, 4027
7500 13:41:55.661524 296 : 4249, 4027
7501 13:41:55.661949 300 : 4250, 4026
7502 13:41:55.665713 304 : 4361, 4137
7503 13:41:55.666137 308 : 4360, 4137
7504 13:41:55.666527 312 : 4248, 4024
7505 13:41:55.668700 316 : 4360, 4137
7506 13:41:55.669124 320 : 4361, 4138
7507 13:41:55.671770 324 : 4250, 4027
7508 13:41:55.672195 328 : 4250, 4026
7509 13:41:55.674642 332 : 4250, 4027
7510 13:41:55.675078 336 : 4252, 3921
7511 13:41:55.678453 340 : 4250, 2313
7512 13:41:55.678878 344 : 4250, 18
7513 13:41:55.679218
7514 13:41:55.681168 MIOCK jitter meter ch=0
7515 13:41:55.681583
7516 13:41:55.684695 1T = (344-92) = 252 dly cells
7517 13:41:55.691510 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7518 13:41:55.691931 ==
7519 13:41:55.694766 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 13:41:55.698083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 13:41:55.698548 ==
7522 13:41:55.704736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 13:41:55.708189 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 13:41:55.711275 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 13:41:55.718015 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 13:41:55.726480 [CA 0] Center 43 (13~74) winsize 62
7527 13:41:55.729387 [CA 1] Center 43 (13~74) winsize 62
7528 13:41:55.732937 [CA 2] Center 39 (10~69) winsize 60
7529 13:41:55.736094 [CA 3] Center 38 (9~68) winsize 60
7530 13:41:55.739279 [CA 4] Center 37 (8~66) winsize 59
7531 13:41:55.742532 [CA 5] Center 36 (7~66) winsize 60
7532 13:41:55.742953
7533 13:41:55.745878 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7534 13:41:55.749518
7535 13:41:55.752266 [CATrainingPosCal] consider 1 rank data
7536 13:41:55.752824 u2DelayCellTimex100 = 258/100 ps
7537 13:41:55.759430 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7538 13:41:55.762726 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7539 13:41:55.765791 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7540 13:41:55.768770 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7541 13:41:55.772086 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7542 13:41:55.775328 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7543 13:41:55.775895
7544 13:41:55.778470 CA PerBit enable=1, Macro0, CA PI delay=36
7545 13:41:55.778905
7546 13:41:55.781778 [CBTSetCACLKResult] CA Dly = 36
7547 13:41:55.785711 CS Dly: 12 (0~43)
7548 13:41:55.788682 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 13:41:55.791906 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 13:41:55.792268 ==
7551 13:41:55.795265 Dram Type= 6, Freq= 0, CH_0, rank 1
7552 13:41:55.801824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 13:41:55.802201 ==
7554 13:41:55.805203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 13:41:55.812088 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 13:41:55.814707 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 13:41:55.821989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 13:41:55.829794 [CA 0] Center 43 (13~74) winsize 62
7559 13:41:55.832905 [CA 1] Center 44 (14~74) winsize 61
7560 13:41:55.836362 [CA 2] Center 38 (9~68) winsize 60
7561 13:41:55.840028 [CA 3] Center 38 (9~68) winsize 60
7562 13:41:55.843015 [CA 4] Center 36 (7~66) winsize 60
7563 13:41:55.846521 [CA 5] Center 36 (6~66) winsize 61
7564 13:41:55.847055
7565 13:41:55.849499 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 13:41:55.849917
7567 13:41:55.852954 [CATrainingPosCal] consider 2 rank data
7568 13:41:55.856172 u2DelayCellTimex100 = 258/100 ps
7569 13:41:55.863152 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7570 13:41:55.866478 CA1 delay=44 (14~74),Diff = 8 PI (30 cell)
7571 13:41:55.869315 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7572 13:41:55.872624 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7573 13:41:55.876380 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7574 13:41:55.879615 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7575 13:41:55.880033
7576 13:41:55.882903 CA PerBit enable=1, Macro0, CA PI delay=36
7577 13:41:55.883324
7578 13:41:55.886283 [CBTSetCACLKResult] CA Dly = 36
7579 13:41:55.889564 CS Dly: 12 (0~44)
7580 13:41:55.892903 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 13:41:55.896099 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 13:41:55.896614
7583 13:41:55.899310 ----->DramcWriteLeveling(PI) begin...
7584 13:41:55.899733 ==
7585 13:41:55.902649 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 13:41:55.909615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 13:41:55.910135 ==
7588 13:41:55.911983 Write leveling (Byte 0): 36 => 36
7589 13:41:55.915690 Write leveling (Byte 1): 26 => 26
7590 13:41:55.919028 DramcWriteLeveling(PI) end<-----
7591 13:41:55.919448
7592 13:41:55.919776 ==
7593 13:41:55.922297 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 13:41:55.925706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 13:41:55.926274 ==
7596 13:41:55.928922 [Gating] SW mode calibration
7597 13:41:55.935488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7598 13:41:55.938889 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7599 13:41:55.945399 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 13:41:55.948767 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 13:41:55.952344 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 13:41:55.958741 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7603 13:41:55.961975 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7604 13:41:55.965044 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7605 13:41:55.972146 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7606 13:41:55.975344 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 13:41:55.981665 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 13:41:55.984952 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 13:41:55.988284 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 13:41:55.994892 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7611 13:41:55.998087 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7612 13:41:56.001651 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7613 13:41:56.004861 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7614 13:41:56.011713 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 13:41:56.014780 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 13:41:56.017981 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 13:41:56.024550 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 13:41:56.028181 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7619 13:41:56.031493 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7620 13:41:56.037951 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7621 13:41:56.041490 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7622 13:41:56.044759 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 13:41:56.051308 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 13:41:56.053964 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 13:41:56.058145 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 13:41:56.064435 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7627 13:41:56.067406 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 13:41:56.074428 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 13:41:56.076905 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 13:41:56.080782 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 13:41:56.087307 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 13:41:56.090623 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 13:41:56.093723 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 13:41:56.097235 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 13:41:56.104016 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 13:41:56.107220 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 13:41:56.110523 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 13:41:56.116554 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 13:41:56.120666 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 13:41:56.123341 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 13:41:56.129995 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 13:41:56.133628 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 13:41:56.140028 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 13:41:56.143191 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 13:41:56.146654 Total UI for P1: 0, mck2ui 16
7646 13:41:56.149884 best dqsien dly found for B0: ( 1, 9, 12)
7647 13:41:56.153338 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 13:41:56.156556 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 13:41:56.159984 Total UI for P1: 0, mck2ui 16
7650 13:41:56.163245 best dqsien dly found for B1: ( 1, 9, 22)
7651 13:41:56.166587 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7652 13:41:56.173462 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7653 13:41:56.173882
7654 13:41:56.175964 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7655 13:41:56.179409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7656 13:41:56.183284 [Gating] SW calibration Done
7657 13:41:56.183700 ==
7658 13:41:56.186462 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 13:41:56.189658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 13:41:56.190082 ==
7661 13:41:56.192829 RX Vref Scan: 0
7662 13:41:56.193247
7663 13:41:56.193595 RX Vref 0 -> 0, step: 1
7664 13:41:56.193907
7665 13:41:56.196274 RX Delay 0 -> 252, step: 8
7666 13:41:56.199503 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7667 13:41:56.202417 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7668 13:41:56.209809 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7669 13:41:56.212454 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7670 13:41:56.215735 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7671 13:41:56.219310 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7672 13:41:56.222484 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7673 13:41:56.229396 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7674 13:41:56.232666 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7675 13:41:56.235973 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7676 13:41:56.238599 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7677 13:41:56.245035 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7678 13:41:56.248687 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7679 13:41:56.251977 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7680 13:41:56.255435 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7681 13:41:56.258721 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7682 13:41:56.262287 ==
7683 13:41:56.265093 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 13:41:56.268660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 13:41:56.268856 ==
7686 13:41:56.268996 DQS Delay:
7687 13:41:56.271789 DQS0 = 0, DQS1 = 0
7688 13:41:56.271921 DQM Delay:
7689 13:41:56.275240 DQM0 = 133, DQM1 = 126
7690 13:41:56.275374 DQ Delay:
7691 13:41:56.278358 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131
7692 13:41:56.281495 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7693 13:41:56.285266 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7694 13:41:56.288300 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7695 13:41:56.288537
7696 13:41:56.288749
7697 13:41:56.288922 ==
7698 13:41:56.291540 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 13:41:56.298278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 13:41:56.298591 ==
7701 13:41:56.298842
7702 13:41:56.299068
7703 13:41:56.301521 TX Vref Scan disable
7704 13:41:56.301753 == TX Byte 0 ==
7705 13:41:56.304615 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7706 13:41:56.311890 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7707 13:41:56.312360 == TX Byte 1 ==
7708 13:41:56.314902 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7709 13:41:56.321666 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7710 13:41:56.322206 ==
7711 13:41:56.325444 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 13:41:56.328274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 13:41:56.328712 ==
7714 13:41:56.342526
7715 13:41:56.345937 TX Vref early break, caculate TX vref
7716 13:41:56.349110 TX Vref=16, minBit 4, minWin=22, winSum=376
7717 13:41:56.352233 TX Vref=18, minBit 1, minWin=23, winSum=380
7718 13:41:56.355481 TX Vref=20, minBit 1, minWin=24, winSum=391
7719 13:41:56.359040 TX Vref=22, minBit 3, minWin=24, winSum=398
7720 13:41:56.362311 TX Vref=24, minBit 5, minWin=24, winSum=406
7721 13:41:56.368587 TX Vref=26, minBit 4, minWin=25, winSum=416
7722 13:41:56.371858 TX Vref=28, minBit 0, minWin=25, winSum=416
7723 13:41:56.375241 TX Vref=30, minBit 4, minWin=24, winSum=411
7724 13:41:56.378153 TX Vref=32, minBit 0, minWin=24, winSum=399
7725 13:41:56.381407 TX Vref=34, minBit 4, minWin=23, winSum=389
7726 13:41:56.387990 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 26
7727 13:41:56.388408
7728 13:41:56.391849 Final TX Range 0 Vref 26
7729 13:41:56.392265
7730 13:41:56.392593 ==
7731 13:41:56.394589 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 13:41:56.397938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 13:41:56.398602 ==
7734 13:41:56.399147
7735 13:41:56.399666
7736 13:41:56.401410 TX Vref Scan disable
7737 13:41:56.408090 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7738 13:41:56.408620 == TX Byte 0 ==
7739 13:41:56.411320 u2DelayCellOfst[0]=15 cells (4 PI)
7740 13:41:56.414758 u2DelayCellOfst[1]=18 cells (5 PI)
7741 13:41:56.417841 u2DelayCellOfst[2]=15 cells (4 PI)
7742 13:41:56.421512 u2DelayCellOfst[3]=15 cells (4 PI)
7743 13:41:56.424691 u2DelayCellOfst[4]=11 cells (3 PI)
7744 13:41:56.427830 u2DelayCellOfst[5]=0 cells (0 PI)
7745 13:41:56.430772 u2DelayCellOfst[6]=22 cells (6 PI)
7746 13:41:56.434111 u2DelayCellOfst[7]=22 cells (6 PI)
7747 13:41:56.437624 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7748 13:41:56.441140 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7749 13:41:56.443851 == TX Byte 1 ==
7750 13:41:56.447571 u2DelayCellOfst[8]=0 cells (0 PI)
7751 13:41:56.450575 u2DelayCellOfst[9]=3 cells (1 PI)
7752 13:41:56.453880 u2DelayCellOfst[10]=7 cells (2 PI)
7753 13:41:56.457746 u2DelayCellOfst[11]=3 cells (1 PI)
7754 13:41:56.458186 u2DelayCellOfst[12]=15 cells (4 PI)
7755 13:41:56.460173 u2DelayCellOfst[13]=15 cells (4 PI)
7756 13:41:56.463455 u2DelayCellOfst[14]=15 cells (4 PI)
7757 13:41:56.466851 u2DelayCellOfst[15]=11 cells (3 PI)
7758 13:41:56.473540 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7759 13:41:56.476966 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7760 13:41:56.477438 DramC Write-DBI on
7761 13:41:56.480306 ==
7762 13:41:56.483486 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 13:41:56.486737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 13:41:56.487159 ==
7765 13:41:56.487488
7766 13:41:56.487838
7767 13:41:56.490089 TX Vref Scan disable
7768 13:41:56.490547 == TX Byte 0 ==
7769 13:41:56.496674 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7770 13:41:56.497092 == TX Byte 1 ==
7771 13:41:56.499627 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7772 13:41:56.503022 DramC Write-DBI off
7773 13:41:56.503574
7774 13:41:56.504052 [DATLAT]
7775 13:41:56.506743 Freq=1600, CH0 RK0
7776 13:41:56.507165
7777 13:41:56.507580 DATLAT Default: 0xf
7778 13:41:56.510020 0, 0xFFFF, sum = 0
7779 13:41:56.513380 1, 0xFFFF, sum = 0
7780 13:41:56.513801 2, 0xFFFF, sum = 0
7781 13:41:56.516243 3, 0xFFFF, sum = 0
7782 13:41:56.516819 4, 0xFFFF, sum = 0
7783 13:41:56.519443 5, 0xFFFF, sum = 0
7784 13:41:56.520068 6, 0xFFFF, sum = 0
7785 13:41:56.523144 7, 0xFFFF, sum = 0
7786 13:41:56.523567 8, 0xFFFF, sum = 0
7787 13:41:56.526452 9, 0xFFFF, sum = 0
7788 13:41:56.526875 10, 0xFFFF, sum = 0
7789 13:41:56.529649 11, 0xFFFF, sum = 0
7790 13:41:56.530212 12, 0xFFFF, sum = 0
7791 13:41:56.532769 13, 0xFFFF, sum = 0
7792 13:41:56.533193 14, 0x0, sum = 1
7793 13:41:56.536571 15, 0x0, sum = 2
7794 13:41:56.537110 16, 0x0, sum = 3
7795 13:41:56.539275 17, 0x0, sum = 4
7796 13:41:56.539702 best_step = 15
7797 13:41:56.540032
7798 13:41:56.540339 ==
7799 13:41:56.542987 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 13:41:56.549434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 13:41:56.550150 ==
7802 13:41:56.550771 RX Vref Scan: 1
7803 13:41:56.551239
7804 13:41:56.552881 Set Vref Range= 24 -> 127
7805 13:41:56.553368
7806 13:41:56.556048 RX Vref 24 -> 127, step: 1
7807 13:41:56.556488
7808 13:41:56.559413 RX Delay 11 -> 252, step: 4
7809 13:41:56.559829
7810 13:41:56.562910 Set Vref, RX VrefLevel [Byte0]: 24
7811 13:41:56.563328 [Byte1]: 24
7812 13:41:56.566661
7813 13:41:56.570000 Set Vref, RX VrefLevel [Byte0]: 25
7814 13:41:56.573136 [Byte1]: 25
7815 13:41:56.573591
7816 13:41:56.576290 Set Vref, RX VrefLevel [Byte0]: 26
7817 13:41:56.579751 [Byte1]: 26
7818 13:41:56.580169
7819 13:41:56.583238 Set Vref, RX VrefLevel [Byte0]: 27
7820 13:41:56.586679 [Byte1]: 27
7821 13:41:56.587352
7822 13:41:56.589692 Set Vref, RX VrefLevel [Byte0]: 28
7823 13:41:56.592738 [Byte1]: 28
7824 13:41:56.597045
7825 13:41:56.597456 Set Vref, RX VrefLevel [Byte0]: 29
7826 13:41:56.600868 [Byte1]: 29
7827 13:41:56.604911
7828 13:41:56.605322 Set Vref, RX VrefLevel [Byte0]: 30
7829 13:41:56.608256 [Byte1]: 30
7830 13:41:56.612379
7831 13:41:56.612931 Set Vref, RX VrefLevel [Byte0]: 31
7832 13:41:56.615885 [Byte1]: 31
7833 13:41:56.620287
7834 13:41:56.620702 Set Vref, RX VrefLevel [Byte0]: 32
7835 13:41:56.623322 [Byte1]: 32
7836 13:41:56.628003
7837 13:41:56.628417 Set Vref, RX VrefLevel [Byte0]: 33
7838 13:41:56.630974 [Byte1]: 33
7839 13:41:56.635345
7840 13:41:56.635893 Set Vref, RX VrefLevel [Byte0]: 34
7841 13:41:56.638633 [Byte1]: 34
7842 13:41:56.642763
7843 13:41:56.643177 Set Vref, RX VrefLevel [Byte0]: 35
7844 13:41:56.646480 [Byte1]: 35
7845 13:41:56.650763
7846 13:41:56.651211 Set Vref, RX VrefLevel [Byte0]: 36
7847 13:41:56.653838 [Byte1]: 36
7848 13:41:56.658550
7849 13:41:56.658965 Set Vref, RX VrefLevel [Byte0]: 37
7850 13:41:56.661242 [Byte1]: 37
7851 13:41:56.665841
7852 13:41:56.666285 Set Vref, RX VrefLevel [Byte0]: 38
7853 13:41:56.669083 [Byte1]: 38
7854 13:41:56.673846
7855 13:41:56.674398 Set Vref, RX VrefLevel [Byte0]: 39
7856 13:41:56.677239 [Byte1]: 39
7857 13:41:56.680986
7858 13:41:56.681421 Set Vref, RX VrefLevel [Byte0]: 40
7859 13:41:56.684422 [Byte1]: 40
7860 13:41:56.689147
7861 13:41:56.689566 Set Vref, RX VrefLevel [Byte0]: 41
7862 13:41:56.692206 [Byte1]: 41
7863 13:41:56.695918
7864 13:41:56.696334 Set Vref, RX VrefLevel [Byte0]: 42
7865 13:41:56.699335 [Byte1]: 42
7866 13:41:56.703887
7867 13:41:56.704304 Set Vref, RX VrefLevel [Byte0]: 43
7868 13:41:56.707189 [Byte1]: 43
7869 13:41:56.711556
7870 13:41:56.712073 Set Vref, RX VrefLevel [Byte0]: 44
7871 13:41:56.714638 [Byte1]: 44
7872 13:41:56.719103
7873 13:41:56.719521 Set Vref, RX VrefLevel [Byte0]: 45
7874 13:41:56.722462 [Byte1]: 45
7875 13:41:56.727013
7876 13:41:56.727431 Set Vref, RX VrefLevel [Byte0]: 46
7877 13:41:56.730232 [Byte1]: 46
7878 13:41:56.734701
7879 13:41:56.735117 Set Vref, RX VrefLevel [Byte0]: 47
7880 13:41:56.737368 [Byte1]: 47
7881 13:41:56.742148
7882 13:41:56.742598 Set Vref, RX VrefLevel [Byte0]: 48
7883 13:41:56.744911 [Byte1]: 48
7884 13:41:56.749255
7885 13:41:56.749681 Set Vref, RX VrefLevel [Byte0]: 49
7886 13:41:56.752707 [Byte1]: 49
7887 13:41:56.757074
7888 13:41:56.757593 Set Vref, RX VrefLevel [Byte0]: 50
7889 13:41:56.760349 [Byte1]: 50
7890 13:41:56.764759
7891 13:41:56.768563 Set Vref, RX VrefLevel [Byte0]: 51
7892 13:41:56.769081 [Byte1]: 51
7893 13:41:56.772267
7894 13:41:56.772853 Set Vref, RX VrefLevel [Byte0]: 52
7895 13:41:56.776042 [Byte1]: 52
7896 13:41:56.779792
7897 13:41:56.780324 Set Vref, RX VrefLevel [Byte0]: 53
7898 13:41:56.783685 [Byte1]: 53
7899 13:41:56.787608
7900 13:41:56.788023 Set Vref, RX VrefLevel [Byte0]: 54
7901 13:41:56.790733 [Byte1]: 54
7902 13:41:56.794873
7903 13:41:56.795290 Set Vref, RX VrefLevel [Byte0]: 55
7904 13:41:56.798250 [Byte1]: 55
7905 13:41:56.802943
7906 13:41:56.803370 Set Vref, RX VrefLevel [Byte0]: 56
7907 13:41:56.805899 [Byte1]: 56
7908 13:41:56.811097
7909 13:41:56.811606 Set Vref, RX VrefLevel [Byte0]: 57
7910 13:41:56.814387 [Byte1]: 57
7911 13:41:56.818378
7912 13:41:56.818887 Set Vref, RX VrefLevel [Byte0]: 58
7913 13:41:56.821773 [Byte1]: 58
7914 13:41:56.825921
7915 13:41:56.826545 Set Vref, RX VrefLevel [Byte0]: 59
7916 13:41:56.829389 [Byte1]: 59
7917 13:41:56.832951
7918 13:41:56.833369 Set Vref, RX VrefLevel [Byte0]: 60
7919 13:41:56.836460 [Byte1]: 60
7920 13:41:56.841041
7921 13:41:56.841516 Set Vref, RX VrefLevel [Byte0]: 61
7922 13:41:56.844251 [Byte1]: 61
7923 13:41:56.848244
7924 13:41:56.848660 Set Vref, RX VrefLevel [Byte0]: 62
7925 13:41:56.851859 [Byte1]: 62
7926 13:41:56.855990
7927 13:41:56.856408 Set Vref, RX VrefLevel [Byte0]: 63
7928 13:41:56.859514 [Byte1]: 63
7929 13:41:56.863820
7930 13:41:56.866824 Set Vref, RX VrefLevel [Byte0]: 64
7931 13:41:56.870251 [Byte1]: 64
7932 13:41:56.870693
7933 13:41:56.873357 Set Vref, RX VrefLevel [Byte0]: 65
7934 13:41:56.876964 [Byte1]: 65
7935 13:41:56.877497
7936 13:41:56.879855 Set Vref, RX VrefLevel [Byte0]: 66
7937 13:41:56.883460 [Byte1]: 66
7938 13:41:56.886493
7939 13:41:56.886910 Set Vref, RX VrefLevel [Byte0]: 67
7940 13:41:56.889528 [Byte1]: 67
7941 13:41:56.894147
7942 13:41:56.894610 Set Vref, RX VrefLevel [Byte0]: 68
7943 13:41:56.897880 [Byte1]: 68
7944 13:41:56.902224
7945 13:41:56.902646 Set Vref, RX VrefLevel [Byte0]: 69
7946 13:41:56.904746 [Byte1]: 69
7947 13:41:56.909359
7948 13:41:56.909879 Set Vref, RX VrefLevel [Byte0]: 70
7949 13:41:56.913046 [Byte1]: 70
7950 13:41:56.917390
7951 13:41:56.917956 Set Vref, RX VrefLevel [Byte0]: 71
7952 13:41:56.920137 [Byte1]: 71
7953 13:41:56.924637
7954 13:41:56.925054 Set Vref, RX VrefLevel [Byte0]: 72
7955 13:41:56.927914 [Byte1]: 72
7956 13:41:56.932625
7957 13:41:56.933220 Set Vref, RX VrefLevel [Byte0]: 73
7958 13:41:56.935955 [Byte1]: 73
7959 13:41:56.939833
7960 13:41:56.940257 Set Vref, RX VrefLevel [Byte0]: 74
7961 13:41:56.943166 [Byte1]: 74
7962 13:41:56.947855
7963 13:41:56.948394 Set Vref, RX VrefLevel [Byte0]: 75
7964 13:41:56.950629 [Byte1]: 75
7965 13:41:56.955054
7966 13:41:56.955612 Set Vref, RX VrefLevel [Byte0]: 76
7967 13:41:56.958259 [Byte1]: 76
7968 13:41:56.962886
7969 13:41:56.963407 Set Vref, RX VrefLevel [Byte0]: 77
7970 13:41:56.966072 [Byte1]: 77
7971 13:41:56.970583
7972 13:41:56.971022 Set Vref, RX VrefLevel [Byte0]: 78
7973 13:41:56.973614 [Byte1]: 78
7974 13:41:56.977787
7975 13:41:56.978273 Set Vref, RX VrefLevel [Byte0]: 79
7976 13:41:56.981027 [Byte1]: 79
7977 13:41:56.985638
7978 13:41:56.986075 Set Vref, RX VrefLevel [Byte0]: 80
7979 13:41:56.988686 [Byte1]: 80
7980 13:41:56.993589
7981 13:41:56.994101 Final RX Vref Byte 0 = 63 to rank0
7982 13:41:56.996278 Final RX Vref Byte 1 = 59 to rank0
7983 13:41:56.999677 Final RX Vref Byte 0 = 63 to rank1
7984 13:41:57.002777 Final RX Vref Byte 1 = 59 to rank1==
7985 13:41:57.006387 Dram Type= 6, Freq= 0, CH_0, rank 0
7986 13:41:57.012752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 13:41:57.013310 ==
7988 13:41:57.013760 DQS Delay:
7989 13:41:57.015884 DQS0 = 0, DQS1 = 0
7990 13:41:57.016341 DQM Delay:
7991 13:41:57.016777 DQM0 = 132, DQM1 = 123
7992 13:41:57.019744 DQ Delay:
7993 13:41:57.023089 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =130
7994 13:41:57.026424 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
7995 13:41:57.029329 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
7996 13:41:57.032756 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
7997 13:41:57.033286
7998 13:41:57.033734
7999 13:41:57.034152
8000 13:41:57.036334 [DramC_TX_OE_Calibration] TA2
8001 13:41:57.039347 Original DQ_B0 (3 6) =30, OEN = 27
8002 13:41:57.042870 Original DQ_B1 (3 6) =30, OEN = 27
8003 13:41:57.045452 24, 0x0, End_B0=24 End_B1=24
8004 13:41:57.048908 25, 0x0, End_B0=25 End_B1=25
8005 13:41:57.049333 26, 0x0, End_B0=26 End_B1=26
8006 13:41:57.052179 27, 0x0, End_B0=27 End_B1=27
8007 13:41:57.055667 28, 0x0, End_B0=28 End_B1=28
8008 13:41:57.058908 29, 0x0, End_B0=29 End_B1=29
8009 13:41:57.059332 30, 0x0, End_B0=30 End_B1=30
8010 13:41:57.062632 31, 0x4141, End_B0=30 End_B1=30
8011 13:41:57.066047 Byte0 end_step=30 best_step=27
8012 13:41:57.069262 Byte1 end_step=30 best_step=27
8013 13:41:57.072725 Byte0 TX OE(2T, 0.5T) = (3, 3)
8014 13:41:57.075723 Byte1 TX OE(2T, 0.5T) = (3, 3)
8015 13:41:57.076145
8016 13:41:57.076586
8017 13:41:57.081913 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8018 13:41:57.084979 CH0 RK0: MR19=303, MR18=2314
8019 13:41:57.091590 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8020 13:41:57.092110
8021 13:41:57.095285 ----->DramcWriteLeveling(PI) begin...
8022 13:41:57.095726 ==
8023 13:41:57.098817 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 13:41:57.101952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 13:41:57.102452 ==
8026 13:41:57.105230 Write leveling (Byte 0): 34 => 34
8027 13:41:57.108843 Write leveling (Byte 1): 26 => 26
8028 13:41:57.111782 DramcWriteLeveling(PI) end<-----
8029 13:41:57.112221
8030 13:41:57.112658 ==
8031 13:41:57.114742 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 13:41:57.121687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 13:41:57.122130 ==
8034 13:41:57.122613 [Gating] SW mode calibration
8035 13:41:57.131370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8036 13:41:57.134526 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8037 13:41:57.137697 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 13:41:57.144783 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 13:41:57.148060 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 13:41:57.151580 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8041 13:41:57.157985 1 4 16 | B1->B0 | 2524 3434 | 1 1 | (1 1) (1 1)
8042 13:41:57.161703 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
8043 13:41:57.164817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 13:41:57.171288 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 13:41:57.174446 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 13:41:57.178051 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 13:41:57.184305 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8048 13:41:57.187715 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8049 13:41:57.190899 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 1)
8050 13:41:57.197385 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8051 13:41:57.200469 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 13:41:57.203829 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 13:41:57.210789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 13:41:57.214044 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 13:41:57.217125 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 13:41:57.223706 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8057 13:41:57.227297 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8058 13:41:57.230375 1 6 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
8059 13:41:57.237230 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 13:41:57.240187 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 13:41:57.243180 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 13:41:57.250112 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 13:41:57.253575 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 13:41:57.256435 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 13:41:57.263605 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8066 13:41:57.266850 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 13:41:57.270261 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 13:41:57.276920 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 13:41:57.279670 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:41:57.283651 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:41:57.290202 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 13:41:57.292860 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 13:41:57.296414 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 13:41:57.302700 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 13:41:57.306518 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:41:57.309860 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 13:41:57.316530 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 13:41:57.319269 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 13:41:57.322992 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 13:41:57.329755 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8081 13:41:57.332942 Total UI for P1: 0, mck2ui 16
8082 13:41:57.336087 best dqsien dly found for B0: ( 1, 9, 10)
8083 13:41:57.339534 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8084 13:41:57.342763 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 13:41:57.345808 Total UI for P1: 0, mck2ui 16
8086 13:41:57.348970 best dqsien dly found for B1: ( 1, 9, 14)
8087 13:41:57.352624 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8088 13:41:57.356037 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8089 13:41:57.356593
8090 13:41:57.361980 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8091 13:41:57.365581 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8092 13:41:57.368758 [Gating] SW calibration Done
8093 13:41:57.368990 ==
8094 13:41:57.371822 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 13:41:57.375088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 13:41:57.375326 ==
8097 13:41:57.378801 RX Vref Scan: 0
8098 13:41:57.379103
8099 13:41:57.379342 RX Vref 0 -> 0, step: 1
8100 13:41:57.379567
8101 13:41:57.382392 RX Delay 0 -> 252, step: 8
8102 13:41:57.385505 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8103 13:41:57.389002 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8104 13:41:57.395118 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8105 13:41:57.398502 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8106 13:41:57.401761 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8107 13:41:57.405601 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8108 13:41:57.408505 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8109 13:41:57.415054 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8110 13:41:57.418361 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8111 13:41:57.422040 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8112 13:41:57.425900 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8113 13:41:57.428600 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8114 13:41:57.435205 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8115 13:41:57.438543 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8116 13:41:57.441634 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8117 13:41:57.445150 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8118 13:41:57.445570 ==
8119 13:41:57.448854 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 13:41:57.454899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 13:41:57.455420 ==
8122 13:41:57.455756 DQS Delay:
8123 13:41:57.458120 DQS0 = 0, DQS1 = 0
8124 13:41:57.458586 DQM Delay:
8125 13:41:57.461094 DQM0 = 132, DQM1 = 127
8126 13:41:57.461510 DQ Delay:
8127 13:41:57.464580 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8128 13:41:57.467885 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8129 13:41:57.471145 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8130 13:41:57.475001 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8131 13:41:57.475421
8132 13:41:57.475749
8133 13:41:57.476112 ==
8134 13:41:57.477863 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 13:41:57.484458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 13:41:57.485045 ==
8137 13:41:57.485497
8138 13:41:57.485912
8139 13:41:57.486387 TX Vref Scan disable
8140 13:41:57.488392 == TX Byte 0 ==
8141 13:41:57.491199 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8142 13:41:57.498018 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8143 13:41:57.498624 == TX Byte 1 ==
8144 13:41:57.501686 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8145 13:41:57.508194 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8146 13:41:57.508731 ==
8147 13:41:57.511153 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 13:41:57.514704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 13:41:57.515278 ==
8150 13:41:57.528016
8151 13:41:57.531175 TX Vref early break, caculate TX vref
8152 13:41:57.534514 TX Vref=16, minBit 1, minWin=22, winSum=376
8153 13:41:57.537596 TX Vref=18, minBit 1, minWin=22, winSum=382
8154 13:41:57.541238 TX Vref=20, minBit 1, minWin=23, winSum=391
8155 13:41:57.544684 TX Vref=22, minBit 1, minWin=24, winSum=398
8156 13:41:57.547340 TX Vref=24, minBit 6, minWin=24, winSum=407
8157 13:41:57.554612 TX Vref=26, minBit 1, minWin=24, winSum=412
8158 13:41:57.557882 TX Vref=28, minBit 1, minWin=24, winSum=409
8159 13:41:57.561117 TX Vref=30, minBit 0, minWin=24, winSum=397
8160 13:41:57.564161 TX Vref=32, minBit 0, minWin=24, winSum=392
8161 13:41:57.567475 TX Vref=34, minBit 4, minWin=23, winSum=383
8162 13:41:57.574459 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 26
8163 13:41:57.574986
8164 13:41:57.577476 Final TX Range 0 Vref 26
8165 13:41:57.577899
8166 13:41:57.578275 ==
8167 13:41:57.580661 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 13:41:57.583834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 13:41:57.584271 ==
8170 13:41:57.584622
8171 13:41:57.584938
8172 13:41:57.587194 TX Vref Scan disable
8173 13:41:57.594011 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8174 13:41:57.594593 == TX Byte 0 ==
8175 13:41:57.597151 u2DelayCellOfst[0]=15 cells (4 PI)
8176 13:41:57.600395 u2DelayCellOfst[1]=18 cells (5 PI)
8177 13:41:57.603505 u2DelayCellOfst[2]=15 cells (4 PI)
8178 13:41:57.606701 u2DelayCellOfst[3]=18 cells (5 PI)
8179 13:41:57.610218 u2DelayCellOfst[4]=11 cells (3 PI)
8180 13:41:57.613551 u2DelayCellOfst[5]=0 cells (0 PI)
8181 13:41:57.616833 u2DelayCellOfst[6]=22 cells (6 PI)
8182 13:41:57.619933 u2DelayCellOfst[7]=18 cells (5 PI)
8183 13:41:57.623451 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8184 13:41:57.626529 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8185 13:41:57.630020 == TX Byte 1 ==
8186 13:41:57.633324 u2DelayCellOfst[8]=0 cells (0 PI)
8187 13:41:57.636651 u2DelayCellOfst[9]=0 cells (0 PI)
8188 13:41:57.640095 u2DelayCellOfst[10]=7 cells (2 PI)
8189 13:41:57.642951 u2DelayCellOfst[11]=0 cells (0 PI)
8190 13:41:57.643392 u2DelayCellOfst[12]=11 cells (3 PI)
8191 13:41:57.646150 u2DelayCellOfst[13]=11 cells (3 PI)
8192 13:41:57.649637 u2DelayCellOfst[14]=15 cells (4 PI)
8193 13:41:57.652821 u2DelayCellOfst[15]=11 cells (3 PI)
8194 13:41:57.659351 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8195 13:41:57.662643 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8196 13:41:57.665669 DramC Write-DBI on
8197 13:41:57.666088 ==
8198 13:41:57.669244 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 13:41:57.672414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 13:41:57.673012 ==
8201 13:41:57.673558
8202 13:41:57.674063
8203 13:41:57.675794 TX Vref Scan disable
8204 13:41:57.676263 == TX Byte 0 ==
8205 13:41:57.682437 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8206 13:41:57.683146 == TX Byte 1 ==
8207 13:41:57.685787 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8208 13:41:57.689114 DramC Write-DBI off
8209 13:41:57.689535
8210 13:41:57.689867 [DATLAT]
8211 13:41:57.692356 Freq=1600, CH0 RK1
8212 13:41:57.692813
8213 13:41:57.693332 DATLAT Default: 0xf
8214 13:41:57.695667 0, 0xFFFF, sum = 0
8215 13:41:57.696137 1, 0xFFFF, sum = 0
8216 13:41:57.699200 2, 0xFFFF, sum = 0
8217 13:41:57.702492 3, 0xFFFF, sum = 0
8218 13:41:57.703085 4, 0xFFFF, sum = 0
8219 13:41:57.705789 5, 0xFFFF, sum = 0
8220 13:41:57.706295 6, 0xFFFF, sum = 0
8221 13:41:57.709108 7, 0xFFFF, sum = 0
8222 13:41:57.709672 8, 0xFFFF, sum = 0
8223 13:41:57.712182 9, 0xFFFF, sum = 0
8224 13:41:57.712610 10, 0xFFFF, sum = 0
8225 13:41:57.715445 11, 0xFFFF, sum = 0
8226 13:41:57.715875 12, 0xFFFF, sum = 0
8227 13:41:57.718799 13, 0xFFFF, sum = 0
8228 13:41:57.719232 14, 0x0, sum = 1
8229 13:41:57.722360 15, 0x0, sum = 2
8230 13:41:57.722908 16, 0x0, sum = 3
8231 13:41:57.725281 17, 0x0, sum = 4
8232 13:41:57.725743 best_step = 15
8233 13:41:57.726344
8234 13:41:57.726753 ==
8235 13:41:57.728968 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 13:41:57.732030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 13:41:57.735499 ==
8238 13:41:57.735955 RX Vref Scan: 0
8239 13:41:57.736425
8240 13:41:57.738974 RX Vref 0 -> 0, step: 1
8241 13:41:57.739391
8242 13:41:57.742042 RX Delay 11 -> 252, step: 4
8243 13:41:57.745362 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8244 13:41:57.748785 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8245 13:41:57.752063 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8246 13:41:57.758851 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8247 13:41:57.761510 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8248 13:41:57.764858 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8249 13:41:57.768084 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8250 13:41:57.771498 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8251 13:41:57.778402 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8252 13:41:57.781645 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8253 13:41:57.784792 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8254 13:41:57.788194 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8255 13:41:57.794439 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8256 13:41:57.797683 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8257 13:41:57.801606 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8258 13:41:57.804245 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8259 13:41:57.804934 ==
8260 13:41:57.807941 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 13:41:57.814417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 13:41:57.814929 ==
8263 13:41:57.815269 DQS Delay:
8264 13:41:57.815582 DQS0 = 0, DQS1 = 0
8265 13:41:57.817690 DQM Delay:
8266 13:41:57.818111 DQM0 = 129, DQM1 = 125
8267 13:41:57.820966 DQ Delay:
8268 13:41:57.824163 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =128
8269 13:41:57.827395 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8270 13:41:57.830611 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8271 13:41:57.834338 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8272 13:41:57.834768
8273 13:41:57.835104
8274 13:41:57.835579
8275 13:41:57.837439 [DramC_TX_OE_Calibration] TA2
8276 13:41:57.840674 Original DQ_B0 (3 6) =30, OEN = 27
8277 13:41:57.844096 Original DQ_B1 (3 6) =30, OEN = 27
8278 13:41:57.847333 24, 0x0, End_B0=24 End_B1=24
8279 13:41:57.847731 25, 0x0, End_B0=25 End_B1=25
8280 13:41:57.850532 26, 0x0, End_B0=26 End_B1=26
8281 13:41:57.853911 27, 0x0, End_B0=27 End_B1=27
8282 13:41:57.857392 28, 0x0, End_B0=28 End_B1=28
8283 13:41:57.860247 29, 0x0, End_B0=29 End_B1=29
8284 13:41:57.860660 30, 0x0, End_B0=30 End_B1=30
8285 13:41:57.864073 31, 0x4141, End_B0=30 End_B1=30
8286 13:41:57.867457 Byte0 end_step=30 best_step=27
8287 13:41:57.870303 Byte1 end_step=30 best_step=27
8288 13:41:57.873481 Byte0 TX OE(2T, 0.5T) = (3, 3)
8289 13:41:57.876765 Byte1 TX OE(2T, 0.5T) = (3, 3)
8290 13:41:57.877079
8291 13:41:57.877334
8292 13:41:57.883660 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8293 13:41:57.887064 CH0 RK1: MR19=303, MR18=2104
8294 13:41:57.893542 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8295 13:41:57.897000 [RxdqsGatingPostProcess] freq 1600
8296 13:41:57.900298 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8297 13:41:57.903589 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 13:41:57.906516 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 13:41:57.909826 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 13:41:57.913093 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 13:41:57.916388 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 13:41:57.919719 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 13:41:57.922863 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 13:41:57.926128 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 13:41:57.929804 Pre-setting of DQS Precalculation
8306 13:41:57.932951 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8307 13:41:57.933283 ==
8308 13:41:57.936163 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 13:41:57.943170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 13:41:57.943548 ==
8311 13:41:57.946485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 13:41:57.953013 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 13:41:57.956483 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 13:41:57.963269 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 13:41:57.970604 [CA 0] Center 42 (13~72) winsize 60
8316 13:41:57.973791 [CA 1] Center 42 (13~72) winsize 60
8317 13:41:57.977231 [CA 2] Center 37 (9~66) winsize 58
8318 13:41:57.980733 [CA 3] Center 37 (8~67) winsize 60
8319 13:41:57.983718 [CA 4] Center 37 (8~67) winsize 60
8320 13:41:57.986886 [CA 5] Center 37 (8~67) winsize 60
8321 13:41:57.987309
8322 13:41:57.990317 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8323 13:41:57.990741
8324 13:41:57.993707 [CATrainingPosCal] consider 1 rank data
8325 13:41:57.996788 u2DelayCellTimex100 = 258/100 ps
8326 13:41:58.003379 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8327 13:41:58.006766 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8328 13:41:58.010036 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8329 13:41:58.013747 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8330 13:41:58.016640 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8331 13:41:58.020118 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8332 13:41:58.020562
8333 13:41:58.023695 CA PerBit enable=1, Macro0, CA PI delay=37
8334 13:41:58.024264
8335 13:41:58.027102 [CBTSetCACLKResult] CA Dly = 37
8336 13:41:58.029834 CS Dly: 9 (0~40)
8337 13:41:58.033589 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 13:41:58.037187 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 13:41:58.037739 ==
8340 13:41:58.040067 Dram Type= 6, Freq= 0, CH_1, rank 1
8341 13:41:58.043123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 13:41:58.046151 ==
8343 13:41:58.049472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8344 13:41:58.052730 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8345 13:41:58.059867 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8346 13:41:58.066499 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8347 13:41:58.073340 [CA 0] Center 43 (14~72) winsize 59
8348 13:41:58.076687 [CA 1] Center 43 (13~73) winsize 61
8349 13:41:58.080279 [CA 2] Center 38 (9~67) winsize 59
8350 13:41:58.083694 [CA 3] Center 37 (8~67) winsize 60
8351 13:41:58.087095 [CA 4] Center 37 (8~67) winsize 60
8352 13:41:58.089573 [CA 5] Center 37 (8~67) winsize 60
8353 13:41:58.089736
8354 13:41:58.092775 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8355 13:41:58.092971
8356 13:41:58.099621 [CATrainingPosCal] consider 2 rank data
8357 13:41:58.099820 u2DelayCellTimex100 = 258/100 ps
8358 13:41:58.106223 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8359 13:41:58.109699 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8360 13:41:58.113346 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8361 13:41:58.116717 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8362 13:41:58.119883 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8363 13:41:58.123374 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8364 13:41:58.123799
8365 13:41:58.126577 CA PerBit enable=1, Macro0, CA PI delay=37
8366 13:41:58.127012
8367 13:41:58.129892 [CBTSetCACLKResult] CA Dly = 37
8368 13:41:58.133103 CS Dly: 10 (0~43)
8369 13:41:58.136721 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8370 13:41:58.139531 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8371 13:41:58.140084
8372 13:41:58.142760 ----->DramcWriteLeveling(PI) begin...
8373 13:41:58.143307 ==
8374 13:41:58.146383 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 13:41:58.153168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 13:41:58.153592 ==
8377 13:41:58.156376 Write leveling (Byte 0): 23 => 23
8378 13:41:58.158967 Write leveling (Byte 1): 29 => 29
8379 13:41:58.162644 DramcWriteLeveling(PI) end<-----
8380 13:41:58.162881
8381 13:41:58.163060 ==
8382 13:41:58.165281 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 13:41:58.169226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 13:41:58.169473 ==
8385 13:41:58.172384 [Gating] SW mode calibration
8386 13:41:58.178890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8387 13:41:58.185114 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8388 13:41:58.188398 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 13:41:58.191927 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 13:41:58.198637 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8391 13:41:58.202127 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8392 13:41:58.204922 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 13:41:58.211481 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 13:41:58.214876 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 13:41:58.218376 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 13:41:58.224983 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 13:41:58.228427 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 13:41:58.231541 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
8399 13:41:58.238052 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8400 13:41:58.241306 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8401 13:41:58.244937 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 13:41:58.251099 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 13:41:58.254285 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 13:41:58.257499 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 13:41:58.264062 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 13:41:58.267292 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8407 13:41:58.270851 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8408 13:41:58.277603 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8409 13:41:58.281012 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 13:41:58.284317 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 13:41:58.290678 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 13:41:58.293785 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 13:41:58.297116 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 13:41:58.303792 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8415 13:41:58.307299 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8416 13:41:58.310679 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8417 13:41:58.317578 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:41:58.320088 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:41:58.323423 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 13:41:58.330195 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:41:58.333447 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:41:58.336919 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:41:58.343302 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:41:58.346686 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 13:41:58.350175 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 13:41:58.356643 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:41:58.359991 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 13:41:58.363409 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 13:41:58.370112 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 13:41:58.372865 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8431 13:41:58.376283 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8432 13:41:58.382845 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 13:41:58.383031 Total UI for P1: 0, mck2ui 16
8434 13:41:58.389515 best dqsien dly found for B0: ( 1, 9, 10)
8435 13:41:58.389697 Total UI for P1: 0, mck2ui 16
8436 13:41:58.395844 best dqsien dly found for B1: ( 1, 9, 12)
8437 13:41:58.399411 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8438 13:41:58.402527 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8439 13:41:58.402738
8440 13:41:58.406085 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8441 13:41:58.409369 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8442 13:41:58.412616 [Gating] SW calibration Done
8443 13:41:58.412830 ==
8444 13:41:58.415999 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 13:41:58.419343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 13:41:58.419621 ==
8447 13:41:58.422677 RX Vref Scan: 0
8448 13:41:58.422889
8449 13:41:58.423057 RX Vref 0 -> 0, step: 1
8450 13:41:58.423214
8451 13:41:58.425947 RX Delay 0 -> 252, step: 8
8452 13:41:58.429193 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8453 13:41:58.435746 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8454 13:41:58.438629 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8455 13:41:58.441934 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8456 13:41:58.445380 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8457 13:41:58.448461 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8458 13:41:58.455156 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8459 13:41:58.458391 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8460 13:41:58.461648 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8461 13:41:58.465622 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8462 13:41:58.468939 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8463 13:41:58.475107 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8464 13:41:58.478236 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8465 13:41:58.481619 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8466 13:41:58.485219 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8467 13:41:58.491383 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8468 13:41:58.491646 ==
8469 13:41:58.494835 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 13:41:58.498031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 13:41:58.498299 ==
8472 13:41:58.498560 DQS Delay:
8473 13:41:58.501413 DQS0 = 0, DQS1 = 0
8474 13:41:58.501634 DQM Delay:
8475 13:41:58.504743 DQM0 = 138, DQM1 = 129
8476 13:41:58.504965 DQ Delay:
8477 13:41:58.508100 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8478 13:41:58.511256 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8479 13:41:58.515055 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8480 13:41:58.521080 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8481 13:41:58.521299
8482 13:41:58.521518
8483 13:41:58.521725 ==
8484 13:41:58.524698 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 13:41:58.527781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 13:41:58.528002 ==
8487 13:41:58.528225
8488 13:41:58.528432
8489 13:41:58.531013 TX Vref Scan disable
8490 13:41:58.531232 == TX Byte 0 ==
8491 13:41:58.537470 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8492 13:41:58.541601 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8493 13:41:58.541822 == TX Byte 1 ==
8494 13:41:58.547398 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8495 13:41:58.550733 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8496 13:41:58.550949 ==
8497 13:41:58.554138 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 13:41:58.557363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 13:41:58.557578 ==
8500 13:41:58.571382
8501 13:41:58.575264 TX Vref early break, caculate TX vref
8502 13:41:58.578568 TX Vref=16, minBit 0, minWin=22, winSum=376
8503 13:41:58.581429 TX Vref=18, minBit 0, minWin=23, winSum=383
8504 13:41:58.584561 TX Vref=20, minBit 0, minWin=23, winSum=393
8505 13:41:58.588571 TX Vref=22, minBit 0, minWin=24, winSum=408
8506 13:41:58.591373 TX Vref=24, minBit 5, minWin=24, winSum=413
8507 13:41:58.597895 TX Vref=26, minBit 0, minWin=25, winSum=419
8508 13:41:58.601340 TX Vref=28, minBit 0, minWin=25, winSum=419
8509 13:41:58.604809 TX Vref=30, minBit 1, minWin=24, winSum=413
8510 13:41:58.608084 TX Vref=32, minBit 0, minWin=23, winSum=399
8511 13:41:58.610801 TX Vref=34, minBit 0, minWin=23, winSum=391
8512 13:41:58.617561 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8513 13:41:58.617843
8514 13:41:58.620779 Final TX Range 0 Vref 26
8515 13:41:58.620999
8516 13:41:58.621223 ==
8517 13:41:58.624071 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 13:41:58.627331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 13:41:58.627553 ==
8520 13:41:58.627773
8521 13:41:58.627983
8522 13:41:58.631103 TX Vref Scan disable
8523 13:41:58.637410 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8524 13:41:58.637639 == TX Byte 0 ==
8525 13:41:58.640689 u2DelayCellOfst[0]=18 cells (5 PI)
8526 13:41:58.643635 u2DelayCellOfst[1]=11 cells (3 PI)
8527 13:41:58.646969 u2DelayCellOfst[2]=0 cells (0 PI)
8528 13:41:58.650282 u2DelayCellOfst[3]=3 cells (1 PI)
8529 13:41:58.653554 u2DelayCellOfst[4]=7 cells (2 PI)
8530 13:41:58.656861 u2DelayCellOfst[5]=18 cells (5 PI)
8531 13:41:58.660201 u2DelayCellOfst[6]=18 cells (5 PI)
8532 13:41:58.663528 u2DelayCellOfst[7]=3 cells (1 PI)
8533 13:41:58.666693 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8534 13:41:58.670014 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8535 13:41:58.673382 == TX Byte 1 ==
8536 13:41:58.676705 u2DelayCellOfst[8]=0 cells (0 PI)
8537 13:41:58.679842 u2DelayCellOfst[9]=3 cells (1 PI)
8538 13:41:58.683244 u2DelayCellOfst[10]=11 cells (3 PI)
8539 13:41:58.686634 u2DelayCellOfst[11]=3 cells (1 PI)
8540 13:41:58.689864 u2DelayCellOfst[12]=15 cells (4 PI)
8541 13:41:58.690190 u2DelayCellOfst[13]=15 cells (4 PI)
8542 13:41:58.693165 u2DelayCellOfst[14]=18 cells (5 PI)
8543 13:41:58.696540 u2DelayCellOfst[15]=18 cells (5 PI)
8544 13:41:58.703516 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8545 13:41:58.706101 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8546 13:41:58.706332 DramC Write-DBI on
8547 13:41:58.709554 ==
8548 13:41:58.712918 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 13:41:58.716230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 13:41:58.716421 ==
8551 13:41:58.716581
8552 13:41:58.716730
8553 13:41:58.719342 TX Vref Scan disable
8554 13:41:58.719545 == TX Byte 0 ==
8555 13:41:58.726083 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8556 13:41:58.726356 == TX Byte 1 ==
8557 13:41:58.729465 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8558 13:41:58.732642 DramC Write-DBI off
8559 13:41:58.732852
8560 13:41:58.733045 [DATLAT]
8561 13:41:58.736024 Freq=1600, CH1 RK0
8562 13:41:58.736261
8563 13:41:58.736437 DATLAT Default: 0xf
8564 13:41:58.739163 0, 0xFFFF, sum = 0
8565 13:41:58.739419 1, 0xFFFF, sum = 0
8566 13:41:58.742756 2, 0xFFFF, sum = 0
8567 13:41:58.742997 3, 0xFFFF, sum = 0
8568 13:41:58.745874 4, 0xFFFF, sum = 0
8569 13:41:58.749013 5, 0xFFFF, sum = 0
8570 13:41:58.749324 6, 0xFFFF, sum = 0
8571 13:41:58.752640 7, 0xFFFF, sum = 0
8572 13:41:58.752969 8, 0xFFFF, sum = 0
8573 13:41:58.755885 9, 0xFFFF, sum = 0
8574 13:41:58.756182 10, 0xFFFF, sum = 0
8575 13:41:58.759206 11, 0xFFFF, sum = 0
8576 13:41:58.759506 12, 0xFFFF, sum = 0
8577 13:41:58.762589 13, 0xFFFF, sum = 0
8578 13:41:58.762801 14, 0x0, sum = 1
8579 13:41:58.765973 15, 0x0, sum = 2
8580 13:41:58.766212 16, 0x0, sum = 3
8581 13:41:58.769221 17, 0x0, sum = 4
8582 13:41:58.769483 best_step = 15
8583 13:41:58.769722
8584 13:41:58.769954 ==
8585 13:41:58.772368 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 13:41:58.775784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 13:41:58.779018 ==
8588 13:41:58.779309 RX Vref Scan: 1
8589 13:41:58.779547
8590 13:41:58.782191 Set Vref Range= 24 -> 127
8591 13:41:58.782513
8592 13:41:58.785365 RX Vref 24 -> 127, step: 1
8593 13:41:58.785451
8594 13:41:58.785515 RX Delay 11 -> 252, step: 4
8595 13:41:58.785575
8596 13:41:58.788696 Set Vref, RX VrefLevel [Byte0]: 24
8597 13:41:58.791958 [Byte1]: 24
8598 13:41:58.795863
8599 13:41:58.795943 Set Vref, RX VrefLevel [Byte0]: 25
8600 13:41:58.799446 [Byte1]: 25
8601 13:41:58.803622
8602 13:41:58.803702 Set Vref, RX VrefLevel [Byte0]: 26
8603 13:41:58.806961 [Byte1]: 26
8604 13:41:58.811049
8605 13:41:58.811129 Set Vref, RX VrefLevel [Byte0]: 27
8606 13:41:58.814455 [Byte1]: 27
8607 13:41:58.818493
8608 13:41:58.818574 Set Vref, RX VrefLevel [Byte0]: 28
8609 13:41:58.822428 [Byte1]: 28
8610 13:41:58.826450
8611 13:41:58.826562 Set Vref, RX VrefLevel [Byte0]: 29
8612 13:41:58.829489 [Byte1]: 29
8613 13:41:58.833804
8614 13:41:58.833979 Set Vref, RX VrefLevel [Byte0]: 30
8615 13:41:58.837663 [Byte1]: 30
8616 13:41:58.841598
8617 13:41:58.841678 Set Vref, RX VrefLevel [Byte0]: 31
8618 13:41:58.844862 [Byte1]: 31
8619 13:41:58.849351
8620 13:41:58.849471 Set Vref, RX VrefLevel [Byte0]: 32
8621 13:41:58.852666 [Byte1]: 32
8622 13:41:58.857058
8623 13:41:58.857191 Set Vref, RX VrefLevel [Byte0]: 33
8624 13:41:58.860072 [Byte1]: 33
8625 13:41:58.864144
8626 13:41:58.864276 Set Vref, RX VrefLevel [Byte0]: 34
8627 13:41:58.867857 [Byte1]: 34
8628 13:41:58.872366
8629 13:41:58.872478 Set Vref, RX VrefLevel [Byte0]: 35
8630 13:41:58.878442 [Byte1]: 35
8631 13:41:58.878555
8632 13:41:58.882134 Set Vref, RX VrefLevel [Byte0]: 36
8633 13:41:58.885066 [Byte1]: 36
8634 13:41:58.885205
8635 13:41:58.888347 Set Vref, RX VrefLevel [Byte0]: 37
8636 13:41:58.892347 [Byte1]: 37
8637 13:41:58.892488
8638 13:41:58.894930 Set Vref, RX VrefLevel [Byte0]: 38
8639 13:41:58.898342 [Byte1]: 38
8640 13:41:58.902649
8641 13:41:58.902784 Set Vref, RX VrefLevel [Byte0]: 39
8642 13:41:58.906091 [Byte1]: 39
8643 13:41:58.909939
8644 13:41:58.910122 Set Vref, RX VrefLevel [Byte0]: 40
8645 13:41:58.913443 [Byte1]: 40
8646 13:41:58.917604
8647 13:41:58.917762 Set Vref, RX VrefLevel [Byte0]: 41
8648 13:41:58.920987 [Byte1]: 41
8649 13:41:58.925401
8650 13:41:58.925576 Set Vref, RX VrefLevel [Byte0]: 42
8651 13:41:58.928736 [Byte1]: 42
8652 13:41:58.932800
8653 13:41:58.932979 Set Vref, RX VrefLevel [Byte0]: 43
8654 13:41:58.936041 [Byte1]: 43
8655 13:41:58.940705
8656 13:41:58.940840 Set Vref, RX VrefLevel [Byte0]: 44
8657 13:41:58.943948 [Byte1]: 44
8658 13:41:58.948604
8659 13:41:58.948747 Set Vref, RX VrefLevel [Byte0]: 45
8660 13:41:58.951584 [Byte1]: 45
8661 13:41:58.956081
8662 13:41:58.956216 Set Vref, RX VrefLevel [Byte0]: 46
8663 13:41:58.959136 [Byte1]: 46
8664 13:41:58.963649
8665 13:41:58.963794 Set Vref, RX VrefLevel [Byte0]: 47
8666 13:41:58.966786 [Byte1]: 47
8667 13:41:58.971493
8668 13:41:58.971630 Set Vref, RX VrefLevel [Byte0]: 48
8669 13:41:58.974651 [Byte1]: 48
8670 13:41:58.979226
8671 13:41:58.979446 Set Vref, RX VrefLevel [Byte0]: 49
8672 13:41:58.982435 [Byte1]: 49
8673 13:41:58.986753
8674 13:41:58.987034 Set Vref, RX VrefLevel [Byte0]: 50
8675 13:41:58.989984 [Byte1]: 50
8676 13:41:58.993987
8677 13:41:58.994219 Set Vref, RX VrefLevel [Byte0]: 51
8678 13:41:58.997124 [Byte1]: 51
8679 13:41:59.001752
8680 13:41:59.001996 Set Vref, RX VrefLevel [Byte0]: 52
8681 13:41:59.005045 [Byte1]: 52
8682 13:41:59.009233
8683 13:41:59.009599 Set Vref, RX VrefLevel [Byte0]: 53
8684 13:41:59.012441 [Byte1]: 53
8685 13:41:59.017072
8686 13:41:59.017315 Set Vref, RX VrefLevel [Byte0]: 54
8687 13:41:59.020407 [Byte1]: 54
8688 13:41:59.024311
8689 13:41:59.024600 Set Vref, RX VrefLevel [Byte0]: 55
8690 13:41:59.027634 [Byte1]: 55
8691 13:41:59.031899
8692 13:41:59.032135 Set Vref, RX VrefLevel [Byte0]: 56
8693 13:41:59.035155 [Byte1]: 56
8694 13:41:59.039799
8695 13:41:59.040035 Set Vref, RX VrefLevel [Byte0]: 57
8696 13:41:59.043009 [Byte1]: 57
8697 13:41:59.047169
8698 13:41:59.047405 Set Vref, RX VrefLevel [Byte0]: 58
8699 13:41:59.050534 [Byte1]: 58
8700 13:41:59.055102
8701 13:41:59.055340 Set Vref, RX VrefLevel [Byte0]: 59
8702 13:41:59.058553 [Byte1]: 59
8703 13:41:59.062536
8704 13:41:59.062828 Set Vref, RX VrefLevel [Byte0]: 60
8705 13:41:59.065893 [Byte1]: 60
8706 13:41:59.070609
8707 13:41:59.070913 Set Vref, RX VrefLevel [Byte0]: 61
8708 13:41:59.073700 [Byte1]: 61
8709 13:41:59.078259
8710 13:41:59.078785 Set Vref, RX VrefLevel [Byte0]: 62
8711 13:41:59.081348 [Byte1]: 62
8712 13:41:59.085908
8713 13:41:59.086445 Set Vref, RX VrefLevel [Byte0]: 63
8714 13:41:59.088828 [Byte1]: 63
8715 13:41:59.093345
8716 13:41:59.093771 Set Vref, RX VrefLevel [Byte0]: 64
8717 13:41:59.096322 [Byte1]: 64
8718 13:41:59.100872
8719 13:41:59.101299 Set Vref, RX VrefLevel [Byte0]: 65
8720 13:41:59.104190 [Byte1]: 65
8721 13:41:59.108853
8722 13:41:59.109275 Set Vref, RX VrefLevel [Byte0]: 66
8723 13:41:59.111565 [Byte1]: 66
8724 13:41:59.115898
8725 13:41:59.116314 Set Vref, RX VrefLevel [Byte0]: 67
8726 13:41:59.119246 [Byte1]: 67
8727 13:41:59.123889
8728 13:41:59.124302 Set Vref, RX VrefLevel [Byte0]: 68
8729 13:41:59.126780 [Byte1]: 68
8730 13:41:59.131189
8731 13:41:59.131607 Set Vref, RX VrefLevel [Byte0]: 69
8732 13:41:59.134555 [Byte1]: 69
8733 13:41:59.139208
8734 13:41:59.139768 Set Vref, RX VrefLevel [Byte0]: 70
8735 13:41:59.141869 [Byte1]: 70
8736 13:41:59.146762
8737 13:41:59.147314 Set Vref, RX VrefLevel [Byte0]: 71
8738 13:41:59.149655 [Byte1]: 71
8739 13:41:59.154265
8740 13:41:59.154829 Set Vref, RX VrefLevel [Byte0]: 72
8741 13:41:59.157242 [Byte1]: 72
8742 13:41:59.162004
8743 13:41:59.162624 Set Vref, RX VrefLevel [Byte0]: 73
8744 13:41:59.165274 [Byte1]: 73
8745 13:41:59.169548
8746 13:41:59.169967 Set Vref, RX VrefLevel [Byte0]: 74
8747 13:41:59.175642 [Byte1]: 74
8748 13:41:59.176204
8749 13:41:59.179457 Set Vref, RX VrefLevel [Byte0]: 75
8750 13:41:59.182500 [Byte1]: 75
8751 13:41:59.183140
8752 13:41:59.185833 Final RX Vref Byte 0 = 53 to rank0
8753 13:41:59.189022 Final RX Vref Byte 1 = 59 to rank0
8754 13:41:59.192789 Final RX Vref Byte 0 = 53 to rank1
8755 13:41:59.195538 Final RX Vref Byte 1 = 59 to rank1==
8756 13:41:59.199366 Dram Type= 6, Freq= 0, CH_1, rank 0
8757 13:41:59.202362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 13:41:59.202780 ==
8759 13:41:59.205822 DQS Delay:
8760 13:41:59.206296 DQS0 = 0, DQS1 = 0
8761 13:41:59.206709 DQM Delay:
8762 13:41:59.208870 DQM0 = 134, DQM1 = 127
8763 13:41:59.209328 DQ Delay:
8764 13:41:59.212414 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8765 13:41:59.215753 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8766 13:41:59.222022 DQ8 =114, DQ9 =114, DQ10 =130, DQ11 =116
8767 13:41:59.225380 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =138
8768 13:41:59.225887
8769 13:41:59.226403
8770 13:41:59.226860
8771 13:41:59.228725 [DramC_TX_OE_Calibration] TA2
8772 13:41:59.232236 Original DQ_B0 (3 6) =30, OEN = 27
8773 13:41:59.235406 Original DQ_B1 (3 6) =30, OEN = 27
8774 13:41:59.235864 24, 0x0, End_B0=24 End_B1=24
8775 13:41:59.238694 25, 0x0, End_B0=25 End_B1=25
8776 13:41:59.241808 26, 0x0, End_B0=26 End_B1=26
8777 13:41:59.245157 27, 0x0, End_B0=27 End_B1=27
8778 13:41:59.245695 28, 0x0, End_B0=28 End_B1=28
8779 13:41:59.248590 29, 0x0, End_B0=29 End_B1=29
8780 13:41:59.251931 30, 0x0, End_B0=30 End_B1=30
8781 13:41:59.255407 31, 0x5151, End_B0=30 End_B1=30
8782 13:41:59.258849 Byte0 end_step=30 best_step=27
8783 13:41:59.261934 Byte1 end_step=30 best_step=27
8784 13:41:59.262392 Byte0 TX OE(2T, 0.5T) = (3, 3)
8785 13:41:59.265240 Byte1 TX OE(2T, 0.5T) = (3, 3)
8786 13:41:59.265759
8787 13:41:59.266091
8788 13:41:59.275121 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8789 13:41:59.278620 CH1 RK0: MR19=303, MR18=190F
8790 13:41:59.282000 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8791 13:41:59.282628
8792 13:41:59.285436 ----->DramcWriteLeveling(PI) begin...
8793 13:41:59.288599 ==
8794 13:41:59.291905 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 13:41:59.294728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 13:41:59.295148 ==
8797 13:41:59.298530 Write leveling (Byte 0): 23 => 23
8798 13:41:59.301669 Write leveling (Byte 1): 28 => 28
8799 13:41:59.304995 DramcWriteLeveling(PI) end<-----
8800 13:41:59.305412
8801 13:41:59.305740 ==
8802 13:41:59.308455 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 13:41:59.311381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 13:41:59.311808 ==
8805 13:41:59.314766 [Gating] SW mode calibration
8806 13:41:59.321457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8807 13:41:59.327750 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8808 13:41:59.331273 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 13:41:59.334286 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 13:41:59.341822 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 13:41:59.344733 1 4 12 | B1->B0 | 3232 2525 | 0 0 | (0 0) (0 0)
8812 13:41:59.348187 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 13:41:59.354743 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 13:41:59.357918 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 13:41:59.361177 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 13:41:59.367458 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 13:41:59.371366 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 13:41:59.374361 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8819 13:41:59.380820 1 5 12 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 1)
8820 13:41:59.384244 1 5 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
8821 13:41:59.387325 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 13:41:59.394354 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 13:41:59.397707 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 13:41:59.400842 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 13:41:59.407092 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 13:41:59.410524 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 13:41:59.413759 1 6 12 | B1->B0 | 4444 2929 | 0 0 | (0 0) (0 0)
8828 13:41:59.420915 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 13:41:59.424388 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 13:41:59.427399 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 13:41:59.433720 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 13:41:59.437456 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 13:41:59.440424 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 13:41:59.446887 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8835 13:41:59.450453 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8836 13:41:59.453768 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 13:41:59.460282 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 13:41:59.463462 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 13:41:59.466780 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 13:41:59.473407 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 13:41:59.476911 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 13:41:59.480526 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 13:41:59.486849 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 13:41:59.489887 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 13:41:59.493148 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 13:41:59.499835 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 13:41:59.502821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 13:41:59.506123 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 13:41:59.513142 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 13:41:59.516093 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8851 13:41:59.519428 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8852 13:41:59.526246 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8853 13:41:59.526761 Total UI for P1: 0, mck2ui 16
8854 13:41:59.529931 best dqsien dly found for B1: ( 1, 9, 10)
8855 13:41:59.535979 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 13:41:59.538990 Total UI for P1: 0, mck2ui 16
8857 13:41:59.543084 best dqsien dly found for B0: ( 1, 9, 14)
8858 13:41:59.546224 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8859 13:41:59.549595 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8860 13:41:59.550123
8861 13:41:59.552624 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8862 13:41:59.555672 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8863 13:41:59.559040 [Gating] SW calibration Done
8864 13:41:59.559454 ==
8865 13:41:59.562567 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 13:41:59.565991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 13:41:59.566481 ==
8868 13:41:59.569200 RX Vref Scan: 0
8869 13:41:59.569709
8870 13:41:59.572635 RX Vref 0 -> 0, step: 1
8871 13:41:59.573052
8872 13:41:59.573379 RX Delay 0 -> 252, step: 8
8873 13:41:59.579335 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8874 13:41:59.582038 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8875 13:41:59.585410 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8876 13:41:59.588623 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8877 13:41:59.591859 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8878 13:41:59.599088 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8879 13:41:59.602201 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8880 13:41:59.605357 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8881 13:41:59.609073 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8882 13:41:59.612152 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8883 13:41:59.618332 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8884 13:41:59.622249 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8885 13:41:59.625175 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8886 13:41:59.628685 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8887 13:41:59.634918 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8888 13:41:59.637996 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8889 13:41:59.638440 ==
8890 13:41:59.641394 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 13:41:59.644842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 13:41:59.645265 ==
8893 13:41:59.648279 DQS Delay:
8894 13:41:59.648702 DQS0 = 0, DQS1 = 0
8895 13:41:59.649034 DQM Delay:
8896 13:41:59.651559 DQM0 = 138, DQM1 = 130
8897 13:41:59.651975 DQ Delay:
8898 13:41:59.654814 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8899 13:41:59.658347 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8900 13:41:59.665084 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8901 13:41:59.668236 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8902 13:41:59.668811
8903 13:41:59.669161
8904 13:41:59.669469 ==
8905 13:41:59.671195 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 13:41:59.674530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 13:41:59.675049 ==
8908 13:41:59.675386
8909 13:41:59.675694
8910 13:41:59.677816 TX Vref Scan disable
8911 13:41:59.681307 == TX Byte 0 ==
8912 13:41:59.684815 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8913 13:41:59.687598 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 13:41:59.691062 == TX Byte 1 ==
8915 13:41:59.694202 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8916 13:41:59.697354 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8917 13:41:59.697774 ==
8918 13:41:59.700699 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 13:41:59.703938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 13:41:59.707225 ==
8921 13:41:59.720598
8922 13:41:59.723116 TX Vref early break, caculate TX vref
8923 13:41:59.727068 TX Vref=16, minBit 0, minWin=23, winSum=382
8924 13:41:59.730749 TX Vref=18, minBit 1, minWin=22, winSum=397
8925 13:41:59.733758 TX Vref=20, minBit 0, minWin=24, winSum=402
8926 13:41:59.736808 TX Vref=22, minBit 0, minWin=24, winSum=411
8927 13:41:59.739808 TX Vref=24, minBit 4, minWin=25, winSum=418
8928 13:41:59.746428 TX Vref=26, minBit 5, minWin=25, winSum=425
8929 13:41:59.749854 TX Vref=28, minBit 1, minWin=25, winSum=424
8930 13:41:59.752897 TX Vref=30, minBit 0, minWin=25, winSum=418
8931 13:41:59.756271 TX Vref=32, minBit 0, minWin=23, winSum=410
8932 13:41:59.759504 TX Vref=34, minBit 0, minWin=24, winSum=403
8933 13:41:59.763029 TX Vref=36, minBit 0, minWin=22, winSum=395
8934 13:41:59.769209 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 26
8935 13:41:59.769756
8936 13:41:59.772455 Final TX Range 0 Vref 26
8937 13:41:59.772884
8938 13:41:59.773207 ==
8939 13:41:59.776308 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 13:41:59.779500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 13:41:59.779924 ==
8942 13:41:59.782812
8943 13:41:59.783225
8944 13:41:59.783552 TX Vref Scan disable
8945 13:41:59.789421 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8946 13:41:59.789835 == TX Byte 0 ==
8947 13:41:59.792383 u2DelayCellOfst[0]=18 cells (5 PI)
8948 13:41:59.795901 u2DelayCellOfst[1]=15 cells (4 PI)
8949 13:41:59.799338 u2DelayCellOfst[2]=0 cells (0 PI)
8950 13:41:59.802268 u2DelayCellOfst[3]=3 cells (1 PI)
8951 13:41:59.805907 u2DelayCellOfst[4]=7 cells (2 PI)
8952 13:41:59.808806 u2DelayCellOfst[5]=18 cells (5 PI)
8953 13:41:59.813040 u2DelayCellOfst[6]=18 cells (5 PI)
8954 13:41:59.815670 u2DelayCellOfst[7]=3 cells (1 PI)
8955 13:41:59.818732 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8956 13:41:59.822414 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8957 13:41:59.825682 == TX Byte 1 ==
8958 13:41:59.828954 u2DelayCellOfst[8]=0 cells (0 PI)
8959 13:41:59.831825 u2DelayCellOfst[9]=3 cells (1 PI)
8960 13:41:59.835098 u2DelayCellOfst[10]=15 cells (4 PI)
8961 13:41:59.838477 u2DelayCellOfst[11]=3 cells (1 PI)
8962 13:41:59.842011 u2DelayCellOfst[12]=15 cells (4 PI)
8963 13:41:59.845445 u2DelayCellOfst[13]=15 cells (4 PI)
8964 13:41:59.848922 u2DelayCellOfst[14]=18 cells (5 PI)
8965 13:41:59.849343 u2DelayCellOfst[15]=18 cells (5 PI)
8966 13:41:59.855302 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8967 13:41:59.858621 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8968 13:41:59.861725 DramC Write-DBI on
8969 13:41:59.862144 ==
8970 13:41:59.864740 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 13:41:59.868454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 13:41:59.868780 ==
8973 13:41:59.869027
8974 13:41:59.869248
8975 13:41:59.871259 TX Vref Scan disable
8976 13:41:59.871485 == TX Byte 0 ==
8977 13:41:59.878102 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8978 13:41:59.878419 == TX Byte 1 ==
8979 13:41:59.884701 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8980 13:41:59.884966 DramC Write-DBI off
8981 13:41:59.885121
8982 13:41:59.885260 [DATLAT]
8983 13:41:59.888158 Freq=1600, CH1 RK1
8984 13:41:59.888341
8985 13:41:59.888485 DATLAT Default: 0xf
8986 13:41:59.891392 0, 0xFFFF, sum = 0
8987 13:41:59.894206 1, 0xFFFF, sum = 0
8988 13:41:59.894460 2, 0xFFFF, sum = 0
8989 13:41:59.897395 3, 0xFFFF, sum = 0
8990 13:41:59.897580 4, 0xFFFF, sum = 0
8991 13:41:59.900684 5, 0xFFFF, sum = 0
8992 13:41:59.900867 6, 0xFFFF, sum = 0
8993 13:41:59.904496 7, 0xFFFF, sum = 0
8994 13:41:59.904716 8, 0xFFFF, sum = 0
8995 13:41:59.907529 9, 0xFFFF, sum = 0
8996 13:41:59.907743 10, 0xFFFF, sum = 0
8997 13:41:59.910709 11, 0xFFFF, sum = 0
8998 13:41:59.910967 12, 0xFFFF, sum = 0
8999 13:41:59.914333 13, 0xFFFF, sum = 0
9000 13:41:59.914742 14, 0x0, sum = 1
9001 13:41:59.917627 15, 0x0, sum = 2
9002 13:41:59.918114 16, 0x0, sum = 3
9003 13:41:59.920731 17, 0x0, sum = 4
9004 13:41:59.921169 best_step = 15
9005 13:41:59.921601
9006 13:41:59.922010 ==
9007 13:41:59.924090 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 13:41:59.930895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 13:41:59.931419 ==
9010 13:41:59.931864 RX Vref Scan: 0
9011 13:41:59.932277
9012 13:41:59.933977 RX Vref 0 -> 0, step: 1
9013 13:41:59.934431
9014 13:41:59.937456 RX Delay 11 -> 252, step: 4
9015 13:41:59.940904 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9016 13:41:59.943960 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9017 13:41:59.947657 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9018 13:41:59.954342 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9019 13:41:59.957712 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9020 13:41:59.960942 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9021 13:41:59.964499 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9022 13:41:59.967660 iDelay=203, Bit 7, Center 132 (83 ~ 182) 100
9023 13:41:59.973705 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9024 13:41:59.977323 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9025 13:41:59.980232 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9026 13:41:59.983577 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9027 13:41:59.989975 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9028 13:41:59.993720 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9029 13:41:59.996498 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9030 13:41:59.999734 iDelay=203, Bit 15, Center 136 (79 ~ 194) 116
9031 13:42:00.000193 ==
9032 13:42:00.003515 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 13:42:00.009890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 13:42:00.010343 ==
9035 13:42:00.010679 DQS Delay:
9036 13:42:00.013087 DQS0 = 0, DQS1 = 0
9037 13:42:00.013502 DQM Delay:
9038 13:42:00.016393 DQM0 = 135, DQM1 = 125
9039 13:42:00.016805 DQ Delay:
9040 13:42:00.019437 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
9041 13:42:00.023110 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
9042 13:42:00.026831 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9043 13:42:00.029704 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =136
9044 13:42:00.030119
9045 13:42:00.030599
9046 13:42:00.030938
9047 13:42:00.033064 [DramC_TX_OE_Calibration] TA2
9048 13:42:00.036169 Original DQ_B0 (3 6) =30, OEN = 27
9049 13:42:00.039410 Original DQ_B1 (3 6) =30, OEN = 27
9050 13:42:00.042892 24, 0x0, End_B0=24 End_B1=24
9051 13:42:00.045931 25, 0x0, End_B0=25 End_B1=25
9052 13:42:00.046453 26, 0x0, End_B0=26 End_B1=26
9053 13:42:00.049209 27, 0x0, End_B0=27 End_B1=27
9054 13:42:00.053003 28, 0x0, End_B0=28 End_B1=28
9055 13:42:00.056005 29, 0x0, End_B0=29 End_B1=29
9056 13:42:00.059477 30, 0x0, End_B0=30 End_B1=30
9057 13:42:00.059903 31, 0x4545, End_B0=30 End_B1=30
9058 13:42:00.062760 Byte0 end_step=30 best_step=27
9059 13:42:00.065955 Byte1 end_step=30 best_step=27
9060 13:42:00.068991 Byte0 TX OE(2T, 0.5T) = (3, 3)
9061 13:42:00.072340 Byte1 TX OE(2T, 0.5T) = (3, 3)
9062 13:42:00.072755
9063 13:42:00.073115
9064 13:42:00.078746 [DQSOSCAuto] RK1, (LSB)MR18= 0xd08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9065 13:42:00.082117 CH1 RK1: MR19=303, MR18=D08
9066 13:42:00.088991 CH1_RK1: MR19=0x303, MR18=0xD08, DQSOSC=403, MR23=63, INC=22, DEC=15
9067 13:42:00.092283 [RxdqsGatingPostProcess] freq 1600
9068 13:42:00.098334 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9069 13:42:00.098885 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 13:42:00.101841 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 13:42:00.105280 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 13:42:00.108600 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 13:42:00.112004 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 13:42:00.115137 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 13:42:00.118624 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 13:42:00.121911 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 13:42:00.125057 Pre-setting of DQS Precalculation
9078 13:42:00.128415 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9079 13:42:00.138092 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9080 13:42:00.144650 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 13:42:00.145424
9082 13:42:00.145776
9083 13:42:00.147607 [Calibration Summary] 3200 Mbps
9084 13:42:00.148294 CH 0, Rank 0
9085 13:42:00.150974 SW Impedance : PASS
9086 13:42:00.154739 DUTY Scan : NO K
9087 13:42:00.155153 ZQ Calibration : PASS
9088 13:42:00.157835 Jitter Meter : NO K
9089 13:42:00.158279 CBT Training : PASS
9090 13:42:00.161002 Write leveling : PASS
9091 13:42:00.164059 RX DQS gating : PASS
9092 13:42:00.164655 RX DQ/DQS(RDDQC) : PASS
9093 13:42:00.167450 TX DQ/DQS : PASS
9094 13:42:00.170694 RX DATLAT : PASS
9095 13:42:00.171108 RX DQ/DQS(Engine): PASS
9096 13:42:00.174080 TX OE : PASS
9097 13:42:00.174752 All Pass.
9098 13:42:00.175105
9099 13:42:00.177483 CH 0, Rank 1
9100 13:42:00.178151 SW Impedance : PASS
9101 13:42:00.180944 DUTY Scan : NO K
9102 13:42:00.184082 ZQ Calibration : PASS
9103 13:42:00.184503 Jitter Meter : NO K
9104 13:42:00.187074 CBT Training : PASS
9105 13:42:00.191091 Write leveling : PASS
9106 13:42:00.191507 RX DQS gating : PASS
9107 13:42:00.193908 RX DQ/DQS(RDDQC) : PASS
9108 13:42:00.197366 TX DQ/DQS : PASS
9109 13:42:00.197889 RX DATLAT : PASS
9110 13:42:00.200271 RX DQ/DQS(Engine): PASS
9111 13:42:00.204015 TX OE : PASS
9112 13:42:00.204481 All Pass.
9113 13:42:00.204812
9114 13:42:00.205116 CH 1, Rank 0
9115 13:42:00.207054 SW Impedance : PASS
9116 13:42:00.210313 DUTY Scan : NO K
9117 13:42:00.210731 ZQ Calibration : PASS
9118 13:42:00.213532 Jitter Meter : NO K
9119 13:42:00.216768 CBT Training : PASS
9120 13:42:00.217185 Write leveling : PASS
9121 13:42:00.220347 RX DQS gating : PASS
9122 13:42:00.223565 RX DQ/DQS(RDDQC) : PASS
9123 13:42:00.224053 TX DQ/DQS : PASS
9124 13:42:00.226674 RX DATLAT : PASS
9125 13:42:00.230649 RX DQ/DQS(Engine): PASS
9126 13:42:00.231348 TX OE : PASS
9127 13:42:00.231862 All Pass.
9128 13:42:00.233087
9129 13:42:00.233629 CH 1, Rank 1
9130 13:42:00.236590 SW Impedance : PASS
9131 13:42:00.237251 DUTY Scan : NO K
9132 13:42:00.240718 ZQ Calibration : PASS
9133 13:42:00.241634 Jitter Meter : NO K
9134 13:42:00.243312 CBT Training : PASS
9135 13:42:00.246502 Write leveling : PASS
9136 13:42:00.247162 RX DQS gating : PASS
9137 13:42:00.250383 RX DQ/DQS(RDDQC) : PASS
9138 13:42:00.253548 TX DQ/DQS : PASS
9139 13:42:00.254302 RX DATLAT : PASS
9140 13:42:00.256433 RX DQ/DQS(Engine): PASS
9141 13:42:00.259656 TX OE : PASS
9142 13:42:00.260074 All Pass.
9143 13:42:00.260405
9144 13:42:00.263095 DramC Write-DBI on
9145 13:42:00.263507 PER_BANK_REFRESH: Hybrid Mode
9146 13:42:00.266536 TX_TRACKING: ON
9147 13:42:00.276633 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9148 13:42:00.283215 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9149 13:42:00.289838 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9150 13:42:00.292998 [FAST_K] Save calibration result to emmc
9151 13:42:00.296390 sync common calibartion params.
9152 13:42:00.299689 sync cbt_mode0:1, 1:1
9153 13:42:00.302698 dram_init: ddr_geometry: 2
9154 13:42:00.303114 dram_init: ddr_geometry: 2
9155 13:42:00.305750 dram_init: ddr_geometry: 2
9156 13:42:00.309518 0:dram_rank_size:100000000
9157 13:42:00.310007 1:dram_rank_size:100000000
9158 13:42:00.316304 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9159 13:42:00.319681 DFS_SHUFFLE_HW_MODE: ON
9160 13:42:00.322464 dramc_set_vcore_voltage set vcore to 725000
9161 13:42:00.326248 Read voltage for 1600, 0
9162 13:42:00.326761 Vio18 = 0
9163 13:42:00.327129 Vcore = 725000
9164 13:42:00.328850 Vdram = 0
9165 13:42:00.329267 Vddq = 0
9166 13:42:00.329596 Vmddr = 0
9167 13:42:00.332670 switch to 3200 Mbps bootup
9168 13:42:00.333247 [DramcRunTimeConfig]
9169 13:42:00.336006 PHYPLL
9170 13:42:00.336523 DPM_CONTROL_AFTERK: ON
9171 13:42:00.338988 PER_BANK_REFRESH: ON
9172 13:42:00.342583 REFRESH_OVERHEAD_REDUCTION: ON
9173 13:42:00.343096 CMD_PICG_NEW_MODE: OFF
9174 13:42:00.345973 XRTWTW_NEW_MODE: ON
9175 13:42:00.346516 XRTRTR_NEW_MODE: ON
9176 13:42:00.348939 TX_TRACKING: ON
9177 13:42:00.349360 RDSEL_TRACKING: OFF
9178 13:42:00.352245 DQS Precalculation for DVFS: ON
9179 13:42:00.355410 RX_TRACKING: OFF
9180 13:42:00.355990 HW_GATING DBG: ON
9181 13:42:00.358963 ZQCS_ENABLE_LP4: ON
9182 13:42:00.359381 RX_PICG_NEW_MODE: ON
9183 13:42:00.362291 TX_PICG_NEW_MODE: ON
9184 13:42:00.365068 ENABLE_RX_DCM_DPHY: ON
9185 13:42:00.368984 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9186 13:42:00.369403 DUMMY_READ_FOR_TRACKING: OFF
9187 13:42:00.372237 !!! SPM_CONTROL_AFTERK: OFF
9188 13:42:00.375099 !!! SPM could not control APHY
9189 13:42:00.378523 IMPEDANCE_TRACKING: ON
9190 13:42:00.378978 TEMP_SENSOR: ON
9191 13:42:00.381430 HW_SAVE_FOR_SR: OFF
9192 13:42:00.381847 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9193 13:42:00.388269 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9194 13:42:00.388697 Read ODT Tracking: ON
9195 13:42:00.391612 Refresh Rate DeBounce: ON
9196 13:42:00.395092 DFS_NO_QUEUE_FLUSH: ON
9197 13:42:00.395510 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9198 13:42:00.398291 ENABLE_DFS_RUNTIME_MRW: OFF
9199 13:42:00.401557 DDR_RESERVE_NEW_MODE: ON
9200 13:42:00.405054 MR_CBT_SWITCH_FREQ: ON
9201 13:42:00.405473 =========================
9202 13:42:00.424547 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9203 13:42:00.427399 dram_init: ddr_geometry: 2
9204 13:42:00.446091 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9205 13:42:00.449136 dram_init: dram init end (result: 0)
9206 13:42:00.455806 DRAM-K: Full calibration passed in 24646 msecs
9207 13:42:00.458981 MRC: failed to locate region type 0.
9208 13:42:00.459579 DRAM rank0 size:0x100000000,
9209 13:42:00.462277 DRAM rank1 size=0x100000000
9210 13:42:00.472144 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9211 13:42:00.479233 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9212 13:42:00.485660 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9213 13:42:00.495557 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9214 13:42:00.495979 DRAM rank0 size:0x100000000,
9215 13:42:00.498881 DRAM rank1 size=0x100000000
9216 13:42:00.499294 CBMEM:
9217 13:42:00.502012 IMD: root @ 0xfffff000 254 entries.
9218 13:42:00.505514 IMD: root @ 0xffffec00 62 entries.
9219 13:42:00.508618 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9220 13:42:00.515522 WARNING: RO_VPD is uninitialized or empty.
9221 13:42:00.518870 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9222 13:42:00.525931 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9223 13:42:00.539129 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9224 13:42:00.550155 BS: romstage times (exec / console): total (unknown) / 24131 ms
9225 13:42:00.550700
9226 13:42:00.551031
9227 13:42:00.560261 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9228 13:42:00.563523 ARM64: Exception handlers installed.
9229 13:42:00.566703 ARM64: Testing exception
9230 13:42:00.570116 ARM64: Done test exception
9231 13:42:00.570682 Enumerating buses...
9232 13:42:00.573868 Show all devs... Before device enumeration.
9233 13:42:00.576345 Root Device: enabled 1
9234 13:42:00.579871 CPU_CLUSTER: 0: enabled 1
9235 13:42:00.580293 CPU: 00: enabled 1
9236 13:42:00.583153 Compare with tree...
9237 13:42:00.583573 Root Device: enabled 1
9238 13:42:00.586412 CPU_CLUSTER: 0: enabled 1
9239 13:42:00.590017 CPU: 00: enabled 1
9240 13:42:00.590497 Root Device scanning...
9241 13:42:00.593317 scan_static_bus for Root Device
9242 13:42:00.596773 CPU_CLUSTER: 0 enabled
9243 13:42:00.599776 scan_static_bus for Root Device done
9244 13:42:00.602982 scan_bus: bus Root Device finished in 8 msecs
9245 13:42:00.603403 done
9246 13:42:00.609556 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9247 13:42:00.612653 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9248 13:42:00.619411 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9249 13:42:00.626026 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9250 13:42:00.626486 Allocating resources...
9251 13:42:00.629448 Reading resources...
9252 13:42:00.632765 Root Device read_resources bus 0 link: 0
9253 13:42:00.635518 DRAM rank0 size:0x100000000,
9254 13:42:00.635935 DRAM rank1 size=0x100000000
9255 13:42:00.642151 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9256 13:42:00.642683 CPU: 00 missing read_resources
9257 13:42:00.649062 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9258 13:42:00.652060 Root Device read_resources bus 0 link: 0 done
9259 13:42:00.655622 Done reading resources.
9260 13:42:00.658866 Show resources in subtree (Root Device)...After reading.
9261 13:42:00.662604 Root Device child on link 0 CPU_CLUSTER: 0
9262 13:42:00.665420 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 13:42:00.675340 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 13:42:00.675846 CPU: 00
9265 13:42:00.681989 Root Device assign_resources, bus 0 link: 0
9266 13:42:00.685233 CPU_CLUSTER: 0 missing set_resources
9267 13:42:00.689131 Root Device assign_resources, bus 0 link: 0 done
9268 13:42:00.689549 Done setting resources.
9269 13:42:00.695556 Show resources in subtree (Root Device)...After assigning values.
9270 13:42:00.698891 Root Device child on link 0 CPU_CLUSTER: 0
9271 13:42:00.705388 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 13:42:00.711794 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 13:42:00.715048 CPU: 00
9274 13:42:00.715510 Done allocating resources.
9275 13:42:00.721960 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9276 13:42:00.722526 Enabling resources...
9277 13:42:00.724942 done.
9278 13:42:00.728224 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9279 13:42:00.731940 Initializing devices...
9280 13:42:00.732607 Root Device init
9281 13:42:00.734776 init hardware done!
9282 13:42:00.735194 0x00000018: ctrlr->caps
9283 13:42:00.738407 52.000 MHz: ctrlr->f_max
9284 13:42:00.741804 0.400 MHz: ctrlr->f_min
9285 13:42:00.745261 0x40ff8080: ctrlr->voltages
9286 13:42:00.745962 sclk: 390625
9287 13:42:00.746420 Bus Width = 1
9288 13:42:00.747840 sclk: 390625
9289 13:42:00.748380 Bus Width = 1
9290 13:42:00.750980 Early init status = 3
9291 13:42:00.754491 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9292 13:42:00.759023 in-header: 03 fc 00 00 01 00 00 00
9293 13:42:00.761872 in-data: 00
9294 13:42:00.765165 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9295 13:42:00.771076 in-header: 03 fd 00 00 00 00 00 00
9296 13:42:00.774244 in-data:
9297 13:42:00.777633 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9298 13:42:00.782399 in-header: 03 fc 00 00 01 00 00 00
9299 13:42:00.785712 in-data: 00
9300 13:42:00.788604 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9301 13:42:00.794700 in-header: 03 fd 00 00 00 00 00 00
9302 13:42:00.798010 in-data:
9303 13:42:00.801052 [SSUSB] Setting up USB HOST controller...
9304 13:42:00.804160 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9305 13:42:00.807422 [SSUSB] phy power-on done.
9306 13:42:00.810723 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9307 13:42:00.817665 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9308 13:42:00.820738 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9309 13:42:00.827579 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9310 13:42:00.833571 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9311 13:42:00.840753 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9312 13:42:00.847486 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9313 13:42:00.853893 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9314 13:42:00.857505 SPM: binary array size = 0x9dc
9315 13:42:00.860841 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9316 13:42:00.866876 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9317 13:42:00.873848 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9318 13:42:00.880001 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9319 13:42:00.883225 configure_display: Starting display init
9320 13:42:00.917706 anx7625_power_on_init: Init interface.
9321 13:42:00.920922 anx7625_disable_pd_protocol: Disabled PD feature.
9322 13:42:00.924041 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9323 13:42:00.951627 anx7625_start_dp_work: Secure OCM version=00
9324 13:42:00.954948 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9325 13:42:00.970023 sp_tx_get_edid_block: EDID Block = 1
9326 13:42:01.072433 Extracted contents:
9327 13:42:01.075520 header: 00 ff ff ff ff ff ff 00
9328 13:42:01.079022 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9329 13:42:01.082430 version: 01 04
9330 13:42:01.085812 basic params: 95 1f 11 78 0a
9331 13:42:01.089057 chroma info: 76 90 94 55 54 90 27 21 50 54
9332 13:42:01.092523 established: 00 00 00
9333 13:42:01.099112 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9334 13:42:01.105891 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9335 13:42:01.108987 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 13:42:01.115271 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9337 13:42:01.121922 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9338 13:42:01.125275 extensions: 00
9339 13:42:01.125804 checksum: fb
9340 13:42:01.126140
9341 13:42:01.131901 Manufacturer: IVO Model 57d Serial Number 0
9342 13:42:01.132407 Made week 0 of 2020
9343 13:42:01.135101 EDID version: 1.4
9344 13:42:01.135520 Digital display
9345 13:42:01.138725 6 bits per primary color channel
9346 13:42:01.141298 DisplayPort interface
9347 13:42:01.141714 Maximum image size: 31 cm x 17 cm
9348 13:42:01.144987 Gamma: 220%
9349 13:42:01.145404 Check DPMS levels
9350 13:42:01.151817 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9351 13:42:01.154860 First detailed timing is preferred timing
9352 13:42:01.157886 Established timings supported:
9353 13:42:01.158355 Standard timings supported:
9354 13:42:01.161276 Detailed timings
9355 13:42:01.164734 Hex of detail: 383680a07038204018303c0035ae10000019
9356 13:42:01.171367 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9357 13:42:01.174640 0780 0798 07c8 0820 hborder 0
9358 13:42:01.177693 0438 043b 0447 0458 vborder 0
9359 13:42:01.180996 -hsync -vsync
9360 13:42:01.181439 Did detailed timing
9361 13:42:01.187549 Hex of detail: 000000000000000000000000000000000000
9362 13:42:01.190946 Manufacturer-specified data, tag 0
9363 13:42:01.194392 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9364 13:42:01.197651 ASCII string: InfoVision
9365 13:42:01.201062 Hex of detail: 000000fe00523134304e574635205248200a
9366 13:42:01.204514 ASCII string: R140NWF5 RH
9367 13:42:01.204947 Checksum
9368 13:42:01.207859 Checksum: 0xfb (valid)
9369 13:42:01.211070 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9370 13:42:01.214326 DSI data_rate: 832800000 bps
9371 13:42:01.221082 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9372 13:42:01.223665 anx7625_parse_edid: pixelclock(138800).
9373 13:42:01.227067 hactive(1920), hsync(48), hfp(24), hbp(88)
9374 13:42:01.230242 vactive(1080), vsync(12), vfp(3), vbp(17)
9375 13:42:01.233489 anx7625_dsi_config: config dsi.
9376 13:42:01.240174 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9377 13:42:01.254795 anx7625_dsi_config: success to config DSI
9378 13:42:01.257974 anx7625_dp_start: MIPI phy setup OK.
9379 13:42:01.260827 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9380 13:42:01.264335 mtk_ddp_mode_set invalid vrefresh 60
9381 13:42:01.267278 main_disp_path_setup
9382 13:42:01.267553 ovl_layer_smi_id_en
9383 13:42:01.270868 ovl_layer_smi_id_en
9384 13:42:01.271092 ccorr_config
9385 13:42:01.271276 aal_config
9386 13:42:01.274351 gamma_config
9387 13:42:01.274660 postmask_config
9388 13:42:01.277439 dither_config
9389 13:42:01.280732 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9390 13:42:01.287359 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9391 13:42:01.290681 Root Device init finished in 555 msecs
9392 13:42:01.294064 CPU_CLUSTER: 0 init
9393 13:42:01.300710 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9394 13:42:01.307508 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9395 13:42:01.307660 APU_MBOX 0x190000b0 = 0x10001
9396 13:42:01.310213 APU_MBOX 0x190001b0 = 0x10001
9397 13:42:01.313600 APU_MBOX 0x190005b0 = 0x10001
9398 13:42:01.317268 APU_MBOX 0x190006b0 = 0x10001
9399 13:42:01.320248 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9400 13:42:01.333299 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9401 13:42:01.345889 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9402 13:42:01.352967 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9403 13:42:01.364374 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9404 13:42:01.373405 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9405 13:42:01.376973 CPU_CLUSTER: 0 init finished in 81 msecs
9406 13:42:01.379881 Devices initialized
9407 13:42:01.383370 Show all devs... After init.
9408 13:42:01.383787 Root Device: enabled 1
9409 13:42:01.386128 CPU_CLUSTER: 0: enabled 1
9410 13:42:01.389645 CPU: 00: enabled 1
9411 13:42:01.392893 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9412 13:42:01.396582 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9413 13:42:01.399526 ELOG: NV offset 0x57f000 size 0x1000
9414 13:42:01.406532 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9415 13:42:01.413069 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9416 13:42:01.416436 ELOG: Event(17) added with size 13 at 2024-05-28 13:42:01 UTC
9417 13:42:01.422919 out: cmd=0x121: 03 db 21 01 00 00 00 00
9418 13:42:01.426129 in-header: 03 27 00 00 2c 00 00 00
9419 13:42:01.440066 in-data: 15 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9420 13:42:01.442525 ELOG: Event(A1) added with size 10 at 2024-05-28 13:42:01 UTC
9421 13:42:01.452611 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9422 13:42:01.455772 ELOG: Event(A0) added with size 9 at 2024-05-28 13:42:01 UTC
9423 13:42:01.459034 elog_add_boot_reason: Logged dev mode boot
9424 13:42:01.465598 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9425 13:42:01.466045 Finalize devices...
9426 13:42:01.468799 Devices finalized
9427 13:42:01.472173 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9428 13:42:01.475503 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9429 13:42:01.479467 in-header: 03 07 00 00 08 00 00 00
9430 13:42:01.482751 in-data: aa e4 47 04 13 02 00 00
9431 13:42:01.485831 Chrome EC: UHEPI supported
9432 13:42:01.492717 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9433 13:42:01.495805 in-header: 03 a9 00 00 08 00 00 00
9434 13:42:01.499159 in-data: 84 60 60 08 00 00 00 00
9435 13:42:01.505626 ELOG: Event(91) added with size 10 at 2024-05-28 13:42:01 UTC
9436 13:42:01.509039 Chrome EC: clear events_b mask to 0x0000000020004000
9437 13:42:01.516008 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9438 13:42:01.519105 in-header: 03 fd 00 00 00 00 00 00
9439 13:42:01.522373 in-data:
9440 13:42:01.525811 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9441 13:42:01.529077 Writing coreboot table at 0xffe64000
9442 13:42:01.535499 0. 000000000010a000-0000000000113fff: RAMSTAGE
9443 13:42:01.538765 1. 0000000040000000-00000000400fffff: RAM
9444 13:42:01.542117 2. 0000000040100000-000000004032afff: RAMSTAGE
9445 13:42:01.545377 3. 000000004032b000-00000000545fffff: RAM
9446 13:42:01.548729 4. 0000000054600000-000000005465ffff: BL31
9447 13:42:01.551990 5. 0000000054660000-00000000ffe63fff: RAM
9448 13:42:01.558643 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9449 13:42:01.562137 7. 0000000100000000-000000023fffffff: RAM
9450 13:42:01.565353 Passing 5 GPIOs to payload:
9451 13:42:01.568465 NAME | PORT | POLARITY | VALUE
9452 13:42:01.575159 EC in RW | 0x000000aa | low | undefined
9453 13:42:01.579012 EC interrupt | 0x00000005 | low | undefined
9454 13:42:01.584880 TPM interrupt | 0x000000ab | high | undefined
9455 13:42:01.588207 SD card detect | 0x00000011 | high | undefined
9456 13:42:01.591496 speaker enable | 0x00000093 | high | undefined
9457 13:42:01.594708 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9458 13:42:01.598966 in-header: 03 f9 00 00 02 00 00 00
9459 13:42:01.602422 in-data: 02 00
9460 13:42:01.605573 ADC[4]: Raw value=904879 ID=7
9461 13:42:01.609303 ADC[3]: Raw value=212912 ID=1
9462 13:42:01.609499 RAM Code: 0x71
9463 13:42:01.612072 ADC[6]: Raw value=75406 ID=0
9464 13:42:01.615763 ADC[5]: Raw value=212543 ID=1
9465 13:42:01.615893 SKU Code: 0x1
9466 13:42:01.621931 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bab8
9467 13:42:01.622082 coreboot table: 964 bytes.
9468 13:42:01.625608 IMD ROOT 0. 0xfffff000 0x00001000
9469 13:42:01.629255 IMD SMALL 1. 0xffffe000 0x00001000
9470 13:42:01.632071 RO MCACHE 2. 0xffffc000 0x00001104
9471 13:42:01.635168 CONSOLE 3. 0xfff7c000 0x00080000
9472 13:42:01.638404 FMAP 4. 0xfff7b000 0x00000452
9473 13:42:01.642501 TIME STAMP 5. 0xfff7a000 0x00000910
9474 13:42:01.645482 VBOOT WORK 6. 0xfff66000 0x00014000
9475 13:42:01.648676 RAMOOPS 7. 0xffe66000 0x00100000
9476 13:42:01.652046 COREBOOT 8. 0xffe64000 0x00002000
9477 13:42:01.655427 IMD small region:
9478 13:42:01.658637 IMD ROOT 0. 0xffffec00 0x00000400
9479 13:42:01.662129 VPD 1. 0xffffeb80 0x0000006c
9480 13:42:01.665322 MMC STATUS 2. 0xffffeb60 0x00000004
9481 13:42:01.672114 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9482 13:42:01.677849 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 13:42:01.716824 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9484 13:42:01.720055 Checking segment from ROM address 0x40100000
9485 13:42:01.726482 Checking segment from ROM address 0x4010001c
9486 13:42:01.729941 Loading segment from ROM address 0x40100000
9487 13:42:01.730127 code (compression=0)
9488 13:42:01.740055 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 13:42:01.746568 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 13:42:01.746741 it's not compressed!
9491 13:42:01.753300 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 13:42:01.760059 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 13:42:01.777489 Loading segment from ROM address 0x4010001c
9494 13:42:01.777688 Entry Point 0x80000000
9495 13:42:01.780721 Loaded segments
9496 13:42:01.784068 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 13:42:01.790444 Jumping to boot code at 0x80000000(0xffe64000)
9498 13:42:01.797041 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 13:42:01.803844 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 13:42:01.811909 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9501 13:42:01.815311 Checking segment from ROM address 0x40100000
9502 13:42:01.818384 Checking segment from ROM address 0x4010001c
9503 13:42:01.825063 Loading segment from ROM address 0x40100000
9504 13:42:01.825563 code (compression=1)
9505 13:42:01.831698 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 13:42:01.841718 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 13:42:01.842257 using LZMA
9508 13:42:01.849981 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 13:42:01.857044 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 13:42:01.860190 Loading segment from ROM address 0x4010001c
9511 13:42:01.860590 Entry Point 0x54601000
9512 13:42:01.863427 Loaded segments
9513 13:42:01.866605 NOTICE: MT8192 bl31_setup
9514 13:42:01.874263 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 13:42:01.877400 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 13:42:01.880330 WARNING: region 0:
9517 13:42:01.883451 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 13:42:01.883869 WARNING: region 1:
9519 13:42:01.890281 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 13:42:01.893660 WARNING: region 2:
9521 13:42:01.896954 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 13:42:01.900025 WARNING: region 3:
9523 13:42:01.903828 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 13:42:01.906556 WARNING: region 4:
9525 13:42:01.913396 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 13:42:01.913902 WARNING: region 5:
9527 13:42:01.916686 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 13:42:01.919968 WARNING: region 6:
9529 13:42:01.923473 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 13:42:01.926577 WARNING: region 7:
9531 13:42:01.929873 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 13:42:01.936486 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 13:42:01.939909 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 13:42:01.946563 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 13:42:01.950030 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 13:42:01.953339 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 13:42:01.959661 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 13:42:01.962744 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 13:42:01.966321 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 13:42:01.973201 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 13:42:01.976001 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 13:42:01.982957 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 13:42:01.986416 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 13:42:01.989690 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 13:42:01.996177 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 13:42:01.999390 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 13:42:02.002987 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 13:42:02.009316 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 13:42:02.012632 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 13:42:02.019158 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 13:42:02.022183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 13:42:02.025835 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 13:42:02.032379 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 13:42:02.035479 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 13:42:02.042583 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 13:42:02.045326 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 13:42:02.048568 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 13:42:02.055507 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 13:42:02.058718 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 13:42:02.064970 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 13:42:02.068341 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 13:42:02.074913 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 13:42:02.078290 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 13:42:02.081402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 13:42:02.084478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 13:42:02.091515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 13:42:02.094320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 13:42:02.097791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 13:42:02.101324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 13:42:02.107966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 13:42:02.111378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 13:42:02.114486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 13:42:02.117686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 13:42:02.124236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 13:42:02.127709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 13:42:02.130891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 13:42:02.137785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 13:42:02.140738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 13:42:02.144457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 13:42:02.150683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 13:42:02.154123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 13:42:02.157258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 13:42:02.164070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 13:42:02.167340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 13:42:02.173886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 13:42:02.177276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 13:42:02.183890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 13:42:02.187168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 13:42:02.190391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 13:42:02.196803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 13:42:02.200080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 13:42:02.206797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 13:42:02.210166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 13:42:02.216730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 13:42:02.220117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 13:42:02.226399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 13:42:02.229734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 13:42:02.236435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 13:42:02.239700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 13:42:02.243371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 13:42:02.249405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 13:42:02.253264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 13:42:02.259851 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 13:42:02.263418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 13:42:02.269330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 13:42:02.272839 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 13:42:02.276361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 13:42:02.282971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 13:42:02.286573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 13:42:02.293125 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 13:42:02.296190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 13:42:02.302727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 13:42:02.306052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 13:42:02.312755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 13:42:02.316615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 13:42:02.319432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 13:42:02.325810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 13:42:02.329480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 13:42:02.336421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 13:42:02.339674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 13:42:02.345600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 13:42:02.349352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 13:42:02.355707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 13:42:02.358895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 13:42:02.362105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 13:42:02.369266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 13:42:02.372438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 13:42:02.379244 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 13:42:02.382549 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 13:42:02.385723 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 13:42:02.389182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 13:42:02.395901 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 13:42:02.398629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 13:42:02.402436 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 13:42:02.408925 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 13:42:02.412173 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 13:42:02.418673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 13:42:02.422143 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 13:42:02.425442 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 13:42:02.431923 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 13:42:02.435463 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 13:42:02.442110 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 13:42:02.445439 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 13:42:02.448379 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 13:42:02.455077 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 13:42:02.459027 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 13:42:02.464998 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 13:42:02.468195 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 13:42:02.471894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 13:42:02.478359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 13:42:02.481673 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 13:42:02.484974 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 13:42:02.488381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 13:42:02.494503 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 13:42:02.498061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 13:42:02.501255 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 13:42:02.507750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 13:42:02.511006 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 13:42:02.517636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 13:42:02.520902 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 13:42:02.524129 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 13:42:02.531436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 13:42:02.534783 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 13:42:02.537922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 13:42:02.544584 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 13:42:02.547742 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 13:42:02.554505 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 13:42:02.557795 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 13:42:02.561250 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 13:42:02.568031 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 13:42:02.570742 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 13:42:02.577250 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 13:42:02.581105 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 13:42:02.584069 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 13:42:02.590543 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 13:42:02.594523 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 13:42:02.600571 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 13:42:02.604045 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 13:42:02.607428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 13:42:02.613738 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 13:42:02.617122 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 13:42:02.623595 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 13:42:02.626854 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 13:42:02.630312 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 13:42:02.636894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 13:42:02.640154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 13:42:02.647139 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 13:42:02.650266 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 13:42:02.653549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 13:42:02.660268 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 13:42:02.663655 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 13:42:02.670201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 13:42:02.673374 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 13:42:02.676677 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 13:42:02.683105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 13:42:02.686291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 13:42:02.692832 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 13:42:02.696227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 13:42:02.699517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 13:42:02.706148 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 13:42:02.709513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 13:42:02.716146 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 13:42:02.719392 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 13:42:02.722557 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 13:42:02.729025 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 13:42:02.732457 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 13:42:02.739025 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 13:42:02.742330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 13:42:02.745811 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 13:42:02.752309 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 13:42:02.755773 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 13:42:02.762528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 13:42:02.765731 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 13:42:02.768690 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 13:42:02.775134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 13:42:02.778950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 13:42:02.785607 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 13:42:02.788856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 13:42:02.792140 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 13:42:02.798636 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 13:42:02.801876 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 13:42:02.808447 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 13:42:02.812060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 13:42:02.818424 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 13:42:02.821478 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 13:42:02.824818 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 13:42:02.831453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 13:42:02.834626 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 13:42:02.841588 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 13:42:02.844819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 13:42:02.851349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 13:42:02.854571 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 13:42:02.857953 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 13:42:02.864741 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 13:42:02.868007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 13:42:02.874352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 13:42:02.877823 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 13:42:02.884479 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 13:42:02.887548 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 13:42:02.891169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 13:42:02.897478 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 13:42:02.901450 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 13:42:02.907453 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 13:42:02.910669 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 13:42:02.914646 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 13:42:02.920627 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 13:42:02.924260 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 13:42:02.930626 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 13:42:02.934047 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 13:42:02.940596 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 13:42:02.943524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 13:42:02.947191 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 13:42:02.953855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 13:42:02.957163 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 13:42:02.963886 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 13:42:02.967243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 13:42:02.970543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 13:42:02.977034 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 13:42:02.980294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 13:42:02.986852 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 13:42:02.990045 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 13:42:02.993837 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 13:42:02.997025 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 13:42:03.003720 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 13:42:03.007188 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 13:42:03.010372 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 13:42:03.017206 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 13:42:03.020585 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 13:42:03.023731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 13:42:03.030325 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 13:42:03.033512 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 13:42:03.036672 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 13:42:03.044197 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 13:42:03.046980 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 13:42:03.053531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 13:42:03.056433 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 13:42:03.060108 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 13:42:03.066427 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 13:42:03.069772 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 13:42:03.073010 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 13:42:03.079918 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 13:42:03.083389 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 13:42:03.090076 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 13:42:03.093246 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 13:42:03.096504 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 13:42:03.102820 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 13:42:03.106724 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 13:42:03.109643 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 13:42:03.116274 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 13:42:03.119262 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 13:42:03.125889 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 13:42:03.129156 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 13:42:03.133130 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 13:42:03.139659 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 13:42:03.142582 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 13:42:03.145985 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 13:42:03.152407 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 13:42:03.155891 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 13:42:03.162437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 13:42:03.165969 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 13:42:03.169119 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 13:42:03.172729 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 13:42:03.175559 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 13:42:03.182062 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 13:42:03.185376 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 13:42:03.188753 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 13:42:03.192141 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 13:42:03.198580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 13:42:03.202022 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 13:42:03.205260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 13:42:03.208592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 13:42:03.215126 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 13:42:03.218714 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 13:42:03.224981 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 13:42:03.228410 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 13:42:03.231995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 13:42:03.238272 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 13:42:03.241618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 13:42:03.248200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 13:42:03.251567 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 13:42:03.254817 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 13:42:03.261506 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 13:42:03.264718 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 13:42:03.271252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 13:42:03.275071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 13:42:03.281017 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 13:42:03.284662 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 13:42:03.291494 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 13:42:03.294403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 13:42:03.297725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 13:42:03.304893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 13:42:03.307762 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 13:42:03.314323 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 13:42:03.317813 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 13:42:03.320881 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 13:42:03.327461 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 13:42:03.331091 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 13:42:03.337535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 13:42:03.340993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 13:42:03.344298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 13:42:03.350683 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 13:42:03.353706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 13:42:03.360901 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 13:42:03.364033 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 13:42:03.367356 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 13:42:03.374420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 13:42:03.377534 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 13:42:03.384109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 13:42:03.387298 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 13:42:03.393835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 13:42:03.397132 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 13:42:03.400761 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 13:42:03.407222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 13:42:03.410704 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 13:42:03.417220 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 13:42:03.420359 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 13:42:03.423721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 13:42:03.430100 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 13:42:03.433407 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 13:42:03.439936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 13:42:03.443244 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 13:42:03.447235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 13:42:03.454029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 13:42:03.456902 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 13:42:03.462986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 13:42:03.466637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 13:42:03.473226 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 13:42:03.476899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 13:42:03.479841 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 13:42:03.486235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 13:42:03.489899 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 13:42:03.496780 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 13:42:03.499575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 13:42:03.502734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 13:42:03.509943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 13:42:03.512639 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 13:42:03.519432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 13:42:03.522496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 13:42:03.526466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 13:42:03.532687 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 13:42:03.535554 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 13:42:03.542932 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 13:42:03.546067 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 13:42:03.552595 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 13:42:03.555938 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 13:42:03.559240 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 13:42:03.565407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 13:42:03.569292 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 13:42:03.575701 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 13:42:03.578778 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 13:42:03.585764 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 13:42:03.588985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 13:42:03.592180 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 13:42:03.598608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 13:42:03.601925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 13:42:03.609023 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 13:42:03.612171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 13:42:03.618298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 13:42:03.622384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 13:42:03.628823 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 13:42:03.631461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 13:42:03.635328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 13:42:03.641619 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 13:42:03.644940 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 13:42:03.651398 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 13:42:03.654733 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 13:42:03.661288 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 13:42:03.664693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 13:42:03.671176 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 13:42:03.674777 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 13:42:03.677851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 13:42:03.684315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 13:42:03.688299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 13:42:03.694740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 13:42:03.697556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 13:42:03.704296 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 13:42:03.707577 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 13:42:03.714492 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 13:42:03.717416 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 13:42:03.721120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 13:42:03.727607 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 13:42:03.730988 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 13:42:03.736961 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 13:42:03.740823 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 13:42:03.747090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 13:42:03.750382 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 13:42:03.757271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 13:42:03.760440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 13:42:03.763899 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 13:42:03.770321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 13:42:03.773703 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 13:42:03.780854 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 13:42:03.783688 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 13:42:03.786803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 13:42:03.793667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 13:42:03.797154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 13:42:03.803927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 13:42:03.806796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 13:42:03.813227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 13:42:03.817075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 13:42:03.823514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 13:42:03.826881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 13:42:03.833345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 13:42:03.836835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 13:42:03.843622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 13:42:03.846562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 13:42:03.853146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 13:42:03.856897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 13:42:03.863297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 13:42:03.866591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 13:42:03.872709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 13:42:03.876391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 13:42:03.882780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 13:42:03.886039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 13:42:03.892537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 13:42:03.895599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 13:42:03.902437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 13:42:03.906226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 13:42:03.912719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 13:42:03.915389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 13:42:03.922297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 13:42:03.926225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 13:42:03.932061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 13:42:03.935945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 13:42:03.941885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 13:42:03.945634 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 13:42:03.948657 INFO: [APUAPC] vio 0
9968 13:42:03.952516 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 13:42:03.958856 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 13:42:03.962254 INFO: [APUAPC] D0_APC_0: 0x400510
9971 13:42:03.962784 INFO: [APUAPC] D0_APC_1: 0x0
9972 13:42:03.965425 INFO: [APUAPC] D0_APC_2: 0x1540
9973 13:42:03.968595 INFO: [APUAPC] D0_APC_3: 0x0
9974 13:42:03.971712 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 13:42:03.975001 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 13:42:03.978624 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 13:42:03.981799 INFO: [APUAPC] D1_APC_3: 0x0
9978 13:42:03.985277 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 13:42:03.988423 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 13:42:03.991743 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 13:42:03.994993 INFO: [APUAPC] D2_APC_3: 0x0
9982 13:42:03.998429 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 13:42:04.001677 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 13:42:04.005488 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 13:42:04.008719 INFO: [APUAPC] D3_APC_3: 0x0
9986 13:42:04.011624 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 13:42:04.015228 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 13:42:04.018433 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 13:42:04.021939 INFO: [APUAPC] D4_APC_3: 0x0
9990 13:42:04.025092 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 13:42:04.028278 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 13:42:04.031379 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 13:42:04.034540 INFO: [APUAPC] D5_APC_3: 0x0
9994 13:42:04.038018 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 13:42:04.041791 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 13:42:04.044610 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 13:42:04.047693 INFO: [APUAPC] D6_APC_3: 0x0
9998 13:42:04.051731 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 13:42:04.054474 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 13:42:04.058310 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 13:42:04.060933 INFO: [APUAPC] D7_APC_3: 0x0
10002 13:42:04.064647 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 13:42:04.067825 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 13:42:04.071428 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 13:42:04.074131 INFO: [APUAPC] D8_APC_3: 0x0
10006 13:42:04.077970 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 13:42:04.081059 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 13:42:04.084571 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 13:42:04.087946 INFO: [APUAPC] D9_APC_3: 0x0
10010 13:42:04.091231 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 13:42:04.094619 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 13:42:04.097733 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 13:42:04.100914 INFO: [APUAPC] D10_APC_3: 0x0
10014 13:42:04.103775 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 13:42:04.107508 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 13:42:04.110742 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 13:42:04.113989 INFO: [APUAPC] D11_APC_3: 0x0
10018 13:42:04.117631 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 13:42:04.120623 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 13:42:04.123790 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 13:42:04.127126 INFO: [APUAPC] D12_APC_3: 0x0
10022 13:42:04.130575 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 13:42:04.133485 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 13:42:04.136960 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 13:42:04.140201 INFO: [APUAPC] D13_APC_3: 0x0
10026 13:42:04.143905 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 13:42:04.146861 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 13:42:04.150373 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 13:42:04.153897 INFO: [APUAPC] D14_APC_3: 0x0
10030 13:42:04.156994 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 13:42:04.160303 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 13:42:04.163424 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 13:42:04.166525 INFO: [APUAPC] D15_APC_3: 0x0
10034 13:42:04.169798 INFO: [APUAPC] APC_CON: 0x4
10035 13:42:04.173690 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 13:42:04.176941 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 13:42:04.180200 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 13:42:04.180768 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 13:42:04.183592 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 13:42:04.186242 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 13:42:04.189673 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 13:42:04.193384 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 13:42:04.196738 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 13:42:04.199969 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 13:42:04.203071 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 13:42:04.206400 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 13:42:04.209903 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 13:42:04.213208 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 13:42:04.213645 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 13:42:04.216733 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 13:42:04.219807 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 13:42:04.222834 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 13:42:04.226246 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 13:42:04.229467 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 13:42:04.232820 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 13:42:04.236051 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 13:42:04.239972 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 13:42:04.242562 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 13:42:04.246509 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 13:42:04.249613 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 13:42:04.252887 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 13:42:04.256003 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 13:42:04.256453 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 13:42:04.259108 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 13:42:04.262611 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 13:42:04.266251 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 13:42:04.268987 INFO: [NOCDAPC] APC_CON: 0x4
10068 13:42:04.272122 INFO: [APUAPC] set_apusys_apc done
10069 13:42:04.275715 INFO: [DEVAPC] devapc_init done
10070 13:42:04.278711 INFO: GICv3 without legacy support detected.
10071 13:42:04.285487 INFO: ARM GICv3 driver initialized in EL3
10072 13:42:04.288748 INFO: Maximum SPI INTID supported: 639
10073 13:42:04.292015 INFO: BL31: Initializing runtime services
10074 13:42:04.298741 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 13:42:04.301991 INFO: SPM: enable CPC mode
10076 13:42:04.305107 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 13:42:04.312379 INFO: BL31: Preparing for EL3 exit to normal world
10078 13:42:04.314776 INFO: Entry point address = 0x80000000
10079 13:42:04.315205 INFO: SPSR = 0x8
10080 13:42:04.322214
10081 13:42:04.322666
10082 13:42:04.323016
10083 13:42:04.325218 Starting depthcharge on Spherion...
10084 13:42:04.325779
10085 13:42:04.326362 Wipe memory regions:
10086 13:42:04.326721
10087 13:42:04.329403 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10088 13:42:04.329982 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10089 13:42:04.330466 Setting prompt string to ['asurada:']
10090 13:42:04.330867 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10091 13:42:04.331549 [0x00000040000000, 0x00000054600000)
10092 13:42:04.450866
10093 13:42:04.451528 [0x00000054660000, 0x00000080000000)
10094 13:42:04.711422
10095 13:42:04.711910 [0x000000821a7280, 0x000000ffe64000)
10096 13:42:05.455878
10097 13:42:05.456363 [0x00000100000000, 0x00000240000000)
10098 13:42:07.346018
10099 13:42:07.349467 Initializing XHCI USB controller at 0x11200000.
10100 13:42:08.387883
10101 13:42:08.391085 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10102 13:42:08.391522
10103 13:42:08.391860
10104 13:42:08.392661 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 13:42:08.493759 asurada: tftpboot 192.168.201.1 14063115/tftp-deploy-pc8phom8/kernel/image.itb 14063115/tftp-deploy-pc8phom8/kernel/cmdline
10107 13:42:08.494001 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10108 13:42:08.494152 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10109 13:42:08.498067 tftpboot 192.168.201.1 14063115/tftp-deploy-pc8phom8/kernel/image.itp-deploy-pc8phom8/kernel/cmdline
10110 13:42:08.498240
10111 13:42:08.498476 Waiting for link
10112 13:42:08.656864
10113 13:42:08.657347 R8152: Initializing
10114 13:42:08.657685
10115 13:42:08.659904 Version 6 (ocp_data = 5c30)
10116 13:42:08.660321
10117 13:42:08.663327 R8152: Done initializing
10118 13:42:08.663744
10119 13:42:08.664074 Adding net device
10120 13:42:10.567164
10121 13:42:10.567670 done.
10122 13:42:10.568081
10123 13:42:10.568452 MAC: 00:e0:4c:68:02:81
10124 13:42:10.568845
10125 13:42:10.570341 Sending DHCP discover... done.
10126 13:42:10.570892
10127 13:42:10.573869 Waiting for reply... done.
10128 13:42:10.574465
10129 13:42:10.576993 Sending DHCP request... done.
10130 13:42:10.577415
10131 13:42:10.580036 Waiting for reply... done.
10132 13:42:10.580454
10133 13:42:10.580786 My ip is 192.168.201.14
10134 13:42:10.581097
10135 13:42:10.583232 The DHCP server ip is 192.168.201.1
10136 13:42:10.583756
10137 13:42:10.589867 TFTP server IP predefined by user: 192.168.201.1
10138 13:42:10.590325
10139 13:42:10.596701 Bootfile predefined by user: 14063115/tftp-deploy-pc8phom8/kernel/image.itb
10140 13:42:10.597222
10141 13:42:10.597554 Sending tftp read request... done.
10142 13:42:10.599741
10143 13:42:10.605973 Waiting for the transfer...
10144 13:42:10.606524
10145 13:42:11.213964 00000000 ################################################################
10146 13:42:11.214512
10147 13:42:11.850861 00080000 ################################################################
10148 13:42:11.850998
10149 13:42:12.505706 00100000 ################################################################
10150 13:42:12.506074
10151 13:42:13.161766 00180000 ################################################################
10152 13:42:13.162317
10153 13:42:13.847768 00200000 ################################################################
10154 13:42:13.848290
10155 13:42:14.540682 00280000 ################################################################
10156 13:42:14.541183
10157 13:42:15.225812 00300000 ################################################################
10158 13:42:15.226538
10159 13:42:15.911007 00380000 ################################################################
10160 13:42:15.911158
10161 13:42:16.539722 00400000 ################################################################
10162 13:42:16.539863
10163 13:42:17.139264 00480000 ################################################################
10164 13:42:17.139443
10165 13:42:17.763424 00500000 ################################################################
10166 13:42:17.763938
10167 13:42:18.434619 00580000 ################################################################
10168 13:42:18.435162
10169 13:42:19.053387 00600000 ################################################################
10170 13:42:19.053530
10171 13:42:19.715563 00680000 ################################################################
10172 13:42:19.716089
10173 13:42:20.340567 00700000 ################################################################
10174 13:42:20.340718
10175 13:42:21.003388 00780000 ################################################################
10176 13:42:21.003922
10177 13:42:21.682925 00800000 ################################################################
10178 13:42:21.683604
10179 13:42:22.403620 00880000 ################################################################
10180 13:42:22.404131
10181 13:42:23.060434 00900000 ################################################################
10182 13:42:23.060586
10183 13:42:23.720964 00980000 ################################################################
10184 13:42:23.721528
10185 13:42:24.409202 00a00000 ################################################################
10186 13:42:24.409725
10187 13:42:24.997129 00a80000 ################################################################
10188 13:42:24.997287
10189 13:42:25.611115 00b00000 ################################################################
10190 13:42:25.611651
10191 13:42:26.315879 00b80000 ################################################################
10192 13:42:26.316428
10193 13:42:27.021164 00c00000 ################################################################
10194 13:42:27.021668
10195 13:42:27.727228 00c80000 ################################################################
10196 13:42:27.727723
10197 13:42:28.339179 00d00000 ################################################################
10198 13:42:28.339332
10199 13:42:28.914625 00d80000 ################################################################
10200 13:42:28.914777
10201 13:42:29.489532 00e00000 ################################################################
10202 13:42:29.489671
10203 13:42:30.048348 00e80000 ################################################################
10204 13:42:30.048500
10205 13:42:30.616767 00f00000 ################################################################
10206 13:42:30.616910
10207 13:42:31.199936 00f80000 ################################################################
10208 13:42:31.200105
10209 13:42:31.789174 01000000 ################################################################
10210 13:42:31.789321
10211 13:42:32.372446 01080000 ################################################################
10212 13:42:32.372599
10213 13:42:32.963695 01100000 ################################################################
10214 13:42:32.963962
10215 13:42:33.536507 01180000 ################################################################
10216 13:42:33.536658
10217 13:42:34.107648 01200000 ################################################################
10218 13:42:34.107798
10219 13:42:34.681405 01280000 ################################################################
10220 13:42:34.681558
10221 13:42:35.259201 01300000 ################################################################
10222 13:42:35.259355
10223 13:42:35.829605 01380000 ################################################################
10224 13:42:35.829784
10225 13:42:36.390639 01400000 ################################################################
10226 13:42:36.390792
10227 13:42:36.948561 01480000 ################################################################
10228 13:42:36.948709
10229 13:42:37.510904 01500000 ################################################################
10230 13:42:37.511056
10231 13:42:38.065864 01580000 ################################################################
10232 13:42:38.066024
10233 13:42:38.625223 01600000 ################################################################
10234 13:42:38.625443
10235 13:42:39.178440 01680000 ################################################################
10236 13:42:39.178573
10237 13:42:39.741759 01700000 ################################################################
10238 13:42:39.741906
10239 13:42:40.314400 01780000 ################################################################
10240 13:42:40.314559
10241 13:42:40.893156 01800000 ################################################################
10242 13:42:40.893304
10243 13:42:41.436645 01880000 ################################################################
10244 13:42:41.436787
10245 13:42:42.013620 01900000 ################################################################
10246 13:42:42.013777
10247 13:42:42.566122 01980000 ################################################################
10248 13:42:42.566300
10249 13:42:43.113376 01a00000 ################################################################
10250 13:42:43.113534
10251 13:42:43.657915 01a80000 ################################################################
10252 13:42:43.658081
10253 13:42:44.220916 01b00000 ################################################################
10254 13:42:44.221102
10255 13:42:44.766381 01b80000 ################################################################
10256 13:42:44.766536
10257 13:42:45.313483 01c00000 ################################################################
10258 13:42:45.313635
10259 13:42:45.859218 01c80000 ################################################################
10260 13:42:45.859371
10261 13:42:46.416279 01d00000 ################################################################
10262 13:42:46.416464
10263 13:42:46.990856 01d80000 ################################################################
10264 13:42:46.991034
10265 13:42:47.539350 01e00000 ################################################################
10266 13:42:47.539502
10267 13:42:48.078685 01e80000 ################################################################
10268 13:42:48.078828
10269 13:42:48.650332 01f00000 ################################################################
10270 13:42:48.650503
10271 13:42:49.221640 01f80000 ################################################################
10272 13:42:49.221800
10273 13:42:49.783862 02000000 ################################################################
10274 13:42:49.783997
10275 13:42:50.329050 02080000 ################################################################
10276 13:42:50.329209
10277 13:42:50.865876 02100000 ################################################################
10278 13:42:50.866016
10279 13:42:51.390918 02180000 ################################################################
10280 13:42:51.391056
10281 13:42:51.922593 02200000 ################################################################
10282 13:42:51.922730
10283 13:42:52.577543 02280000 ################################################################
10284 13:42:52.578035
10285 13:42:53.246659 02300000 ################################################################
10286 13:42:53.246798
10287 13:42:53.910824 02380000 ################################################################
10288 13:42:53.911403
10289 13:42:54.553640 02400000 ################################################################
10290 13:42:54.554141
10291 13:42:55.171096 02480000 ################################################################
10292 13:42:55.171230
10293 13:42:55.783397 02500000 ################################################################
10294 13:42:55.783535
10295 13:42:56.388600 02580000 ################################################################
10296 13:42:56.389106
10297 13:42:57.056587 02600000 ################################################################
10298 13:42:57.057086
10299 13:42:57.690497 02680000 ################################################################
10300 13:42:57.690670
10301 13:42:58.363003 02700000 ################################################################
10302 13:42:58.363513
10303 13:42:59.056493 02780000 ################################################################
10304 13:42:59.057168
10305 13:42:59.689539 02800000 ################################################################
10306 13:42:59.690155
10307 13:43:00.366499 02880000 ################################################################
10308 13:43:00.366997
10309 13:43:01.040451 02900000 ################################################################
10310 13:43:01.040738
10311 13:43:01.635433 02980000 ################################################################
10312 13:43:01.635635
10313 13:43:02.239692 02a00000 ################################################################
10314 13:43:02.240199
10315 13:43:02.945192 02a80000 ################################################################
10316 13:43:02.945774
10317 13:43:03.623432 02b00000 ################################################################
10318 13:43:03.624053
10319 13:43:04.277394 02b80000 ################################################################
10320 13:43:04.278014
10321 13:43:04.831513 02c00000 ################################################################
10322 13:43:04.831654
10323 13:43:05.378546 02c80000 ################################################################
10324 13:43:05.378715
10325 13:43:05.919518 02d00000 ################################################################
10326 13:43:05.919659
10327 13:43:06.454051 02d80000 ################################################################
10328 13:43:06.454229
10329 13:43:06.981267 02e00000 ################################################################
10330 13:43:06.981414
10331 13:43:07.524728 02e80000 ################################################################
10332 13:43:07.524902
10333 13:43:08.076305 02f00000 ################################################################
10334 13:43:08.076475
10335 13:43:08.618539 02f80000 ################################################################
10336 13:43:08.618702
10337 13:43:09.148101 03000000 ################################################################
10338 13:43:09.148273
10339 13:43:09.677340 03080000 ################################################################
10340 13:43:09.677478
10341 13:43:10.210670 03100000 ################################################################
10342 13:43:10.210812
10343 13:43:10.737752 03180000 ################################################################
10344 13:43:10.737884
10345 13:43:11.282970 03200000 ################################################################
10346 13:43:11.283115
10347 13:43:11.815838 03280000 ################################################################
10348 13:43:11.815987
10349 13:43:12.473747 03300000 ################################################################
10350 13:43:12.474573
10351 13:43:13.165461 03380000 ################################################################
10352 13:43:13.165956
10353 13:43:13.851806 03400000 ################################################################
10354 13:43:13.852324
10355 13:43:14.553487 03480000 ################################################################
10356 13:43:14.554063
10357 13:43:15.250625 03500000 ################################################################
10358 13:43:15.251125
10359 13:43:15.937044 03580000 ################################################################
10360 13:43:15.937597
10361 13:43:16.615298 03600000 ################################################################
10362 13:43:16.615795
10363 13:43:17.319861 03680000 ################################################################
10364 13:43:17.320512
10365 13:43:18.008392 03700000 ################################################################
10366 13:43:18.008930
10367 13:43:18.700179 03780000 ################################################################
10368 13:43:18.700686
10369 13:43:19.404285 03800000 ################################################################
10370 13:43:19.404805
10371 13:43:20.094154 03880000 ################################################################
10372 13:43:20.094707
10373 13:43:20.801806 03900000 ################################################################
10374 13:43:20.802341
10375 13:43:21.488370 03980000 ################################################################
10376 13:43:21.488670
10377 13:43:22.182685 03a00000 ################################################################
10378 13:43:22.183046
10379 13:43:22.865076 03a80000 ################################################################
10380 13:43:22.865588
10381 13:43:23.513312 03b00000 ################################################################
10382 13:43:23.513803
10383 13:43:24.079982 03b80000 ################################################################
10384 13:43:24.080134
10385 13:43:24.657365 03c00000 ################################################################
10386 13:43:24.657506
10387 13:43:25.293680 03c80000 ################################################################
10388 13:43:25.294256
10389 13:43:25.976944 03d00000 ################################################################
10390 13:43:25.977469
10391 13:43:26.609662 03d80000 ################################################################
10392 13:43:26.610329
10393 13:43:26.906220 03e00000 ############################# done.
10394 13:43:26.906716
10395 13:43:26.909244 The bootfile was 65241202 bytes long.
10396 13:43:26.909669
10397 13:43:26.912993 Sending tftp read request... done.
10398 13:43:26.913455
10399 13:43:26.916388 Waiting for the transfer...
10400 13:43:26.917056
10401 13:43:26.917632 00000000 # done.
10402 13:43:26.918218
10403 13:43:26.924277 Command line loaded dynamically from TFTP file: 14063115/tftp-deploy-pc8phom8/kernel/cmdline
10404 13:43:26.927129
10405 13:43:26.939579 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10406 13:43:26.940010
10407 13:43:26.940440 Loading FIT.
10408 13:43:26.940777
10409 13:43:26.943513 Image ramdisk-1 has 52130606 bytes.
10410 13:43:26.943904
10411 13:43:26.946501 Image fdt-1 has 47258 bytes.
10412 13:43:26.946759
10413 13:43:26.949354 Image kernel-1 has 13061303 bytes.
10414 13:43:26.949677
10415 13:43:26.955821 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10416 13:43:26.956073
10417 13:43:26.975638 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10418 13:43:26.975869
10419 13:43:26.978863 Choosing best match conf-1 for compat google,spherion-rev2.
10420 13:43:26.984156
10421 13:43:26.988436 Connected to device vid:did:rid of 1ae0:0028:00
10422 13:43:26.995904
10423 13:43:26.999174 tpm_get_response: command 0x17b, return code 0x0
10424 13:43:26.999358
10425 13:43:27.002404 ec_init: CrosEC protocol v3 supported (256, 248)
10426 13:43:27.006235
10427 13:43:27.010099 tpm_cleanup: add release locality here.
10428 13:43:27.010301
10429 13:43:27.010446 Shutting down all USB controllers.
10430 13:43:27.013502
10431 13:43:27.013681 Removing current net device
10432 13:43:27.013826
10433 13:43:27.019609 Exiting depthcharge with code 4 at timestamp: 112164955
10434 13:43:27.019792
10435 13:43:27.022855 LZMA decompressing kernel-1 to 0x821a6718
10436 13:43:27.023038
10437 13:43:27.025854 LZMA decompressing kernel-1 to 0x40000000
10438 13:43:28.637495
10439 13:43:28.638111 jumping to kernel
10440 13:43:28.641288 end: 2.2.4 bootloader-commands (duration 00:01:24) [common]
10441 13:43:28.641950 start: 2.2.5 auto-login-action (timeout 00:03:02) [common]
10442 13:43:28.642546 Setting prompt string to ['Linux version [0-9]']
10443 13:43:28.643068 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10444 13:43:28.643586 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10445 13:43:28.719450
10446 13:43:28.722589 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10447 13:43:28.726107 start: 2.2.5.1 login-action (timeout 00:03:02) [common]
10448 13:43:28.726252 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10449 13:43:28.726326 Setting prompt string to []
10450 13:43:28.726403 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10451 13:43:28.726475 Using line separator: #'\n'#
10452 13:43:28.726534 No login prompt set.
10453 13:43:28.726625 Parsing kernel messages
10454 13:43:28.726679 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10455 13:43:28.726795 [login-action] Waiting for messages, (timeout 00:03:02)
10456 13:43:28.726860 Waiting using forced prompt support (timeout 00:01:31)
10457 13:43:28.745758 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10458 13:43:28.749135 [ 0.000000] random: crng init done
10459 13:43:28.755544 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10460 13:43:28.758707 [ 0.000000] efi: UEFI not found.
10461 13:43:28.765720 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10462 13:43:28.775183 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10463 13:43:28.785168 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10464 13:43:28.791599 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10465 13:43:28.798432 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10466 13:43:28.804539 [ 0.000000] printk: bootconsole [mtk8250] enabled
10467 13:43:28.811666 [ 0.000000] NUMA: No NUMA configuration found
10468 13:43:28.818092 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10469 13:43:28.824857 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10470 13:43:28.824973 [ 0.000000] Zone ranges:
10471 13:43:28.831406 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10472 13:43:28.834454 [ 0.000000] DMA32 empty
10473 13:43:28.840624 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10474 13:43:28.844115 [ 0.000000] Movable zone start for each node
10475 13:43:28.847909 [ 0.000000] Early memory node ranges
10476 13:43:28.854511 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10477 13:43:28.860771 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10478 13:43:28.867384 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10479 13:43:28.873932 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10480 13:43:28.880303 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10481 13:43:28.886649 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10482 13:43:28.944082 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10483 13:43:28.950637 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10484 13:43:28.957305 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10485 13:43:28.960277 [ 0.000000] psci: probing for conduit method from DT.
10486 13:43:28.967113 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10487 13:43:28.970374 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10488 13:43:28.976925 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10489 13:43:28.980493 [ 0.000000] psci: SMC Calling Convention v1.2
10490 13:43:28.986958 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10491 13:43:28.989985 [ 0.000000] Detected VIPT I-cache on CPU0
10492 13:43:28.996549 [ 0.000000] CPU features: detected: GIC system register CPU interface
10493 13:43:29.003153 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10494 13:43:29.010129 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10495 13:43:29.016364 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10496 13:43:29.026806 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10497 13:43:29.033261 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10498 13:43:29.036132 [ 0.000000] alternatives: applying boot alternatives
10499 13:43:29.042967 [ 0.000000] Fallback order for Node 0: 0
10500 13:43:29.049471 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10501 13:43:29.052525 [ 0.000000] Policy zone: Normal
10502 13:43:29.066028 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10503 13:43:29.075771 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10504 13:43:29.088118 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10505 13:43:29.098148 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10506 13:43:29.104566 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10507 13:43:29.107970 <6>[ 0.000000] software IO TLB: area num 8.
10508 13:43:29.164415 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10509 13:43:29.313960 <6>[ 0.000000] Memory: 7913280K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 439488K reserved, 32768K cma-reserved)
10510 13:43:29.320845 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10511 13:43:29.327316 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10512 13:43:29.330934 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10513 13:43:29.337507 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10514 13:43:29.344212 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10515 13:43:29.347505 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10516 13:43:29.357129 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10517 13:43:29.363699 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10518 13:43:29.370390 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10519 13:43:29.377684 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10520 13:43:29.380326 <6>[ 0.000000] GICv3: 608 SPIs implemented
10521 13:43:29.383980 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10522 13:43:29.390342 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10523 13:43:29.393691 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10524 13:43:29.400525 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10525 13:43:29.413468 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10526 13:43:29.426730 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10527 13:43:29.432896 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10528 13:43:29.441245 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10529 13:43:29.453855 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10530 13:43:29.460988 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10531 13:43:29.467582 <6>[ 0.009175] Console: colour dummy device 80x25
10532 13:43:29.477268 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10533 13:43:29.483927 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10534 13:43:29.487198 <6>[ 0.029245] LSM: Security Framework initializing
10535 13:43:29.493817 <6>[ 0.034196] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10536 13:43:29.503926 <6>[ 0.042010] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10537 13:43:29.510618 <6>[ 0.051433] cblist_init_generic: Setting adjustable number of callback queues.
10538 13:43:29.517022 <6>[ 0.058876] cblist_init_generic: Setting shift to 3 and lim to 1.
10539 13:43:29.526830 <6>[ 0.065215] cblist_init_generic: Setting adjustable number of callback queues.
10540 13:43:29.533517 <6>[ 0.072687] cblist_init_generic: Setting shift to 3 and lim to 1.
10541 13:43:29.536626 <6>[ 0.079091] rcu: Hierarchical SRCU implementation.
10542 13:43:29.543388 <6>[ 0.084137] rcu: Max phase no-delay instances is 1000.
10543 13:43:29.550455 <6>[ 0.091189] EFI services will not be available.
10544 13:43:29.553499 <6>[ 0.096175] smp: Bringing up secondary CPUs ...
10545 13:43:29.561856 <6>[ 0.101222] Detected VIPT I-cache on CPU1
10546 13:43:29.568185 <6>[ 0.101293] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10547 13:43:29.575461 <6>[ 0.101323] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10548 13:43:29.578114 <6>[ 0.101656] Detected VIPT I-cache on CPU2
10549 13:43:29.588178 <6>[ 0.101703] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10550 13:43:29.594603 <6>[ 0.101719] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10551 13:43:29.597981 <6>[ 0.101974] Detected VIPT I-cache on CPU3
10552 13:43:29.604847 <6>[ 0.102021] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10553 13:43:29.611475 <6>[ 0.102034] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10554 13:43:29.618294 <6>[ 0.102338] CPU features: detected: Spectre-v4
10555 13:43:29.621338 <6>[ 0.102344] CPU features: detected: Spectre-BHB
10556 13:43:29.624609 <6>[ 0.102349] Detected PIPT I-cache on CPU4
10557 13:43:29.631035 <6>[ 0.102407] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10558 13:43:29.640971 <6>[ 0.102423] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10559 13:43:29.644085 <6>[ 0.102716] Detected PIPT I-cache on CPU5
10560 13:43:29.650657 <6>[ 0.102779] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10561 13:43:29.657580 <6>[ 0.102795] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10562 13:43:29.660793 <6>[ 0.103079] Detected PIPT I-cache on CPU6
10563 13:43:29.670565 <6>[ 0.103145] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10564 13:43:29.676695 <6>[ 0.103161] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10565 13:43:29.679903 <6>[ 0.103459] Detected PIPT I-cache on CPU7
10566 13:43:29.687184 <6>[ 0.103524] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10567 13:43:29.693422 <6>[ 0.103540] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10568 13:43:29.696597 <6>[ 0.103588] smp: Brought up 1 node, 8 CPUs
10569 13:43:29.702897 <6>[ 0.244960] SMP: Total of 8 processors activated.
10570 13:43:29.709942 <6>[ 0.249881] CPU features: detected: 32-bit EL0 Support
10571 13:43:29.716356 <6>[ 0.255244] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10572 13:43:29.723279 <6>[ 0.264099] CPU features: detected: Common not Private translations
10573 13:43:29.729509 <6>[ 0.270575] CPU features: detected: CRC32 instructions
10574 13:43:29.736581 <6>[ 0.275926] CPU features: detected: RCpc load-acquire (LDAPR)
10575 13:43:29.739692 <6>[ 0.281923] CPU features: detected: LSE atomic instructions
10576 13:43:29.746482 <6>[ 0.287704] CPU features: detected: Privileged Access Never
10577 13:43:29.752724 <6>[ 0.293520] CPU features: detected: RAS Extension Support
10578 13:43:29.759765 <6>[ 0.299128] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10579 13:43:29.762203 <6>[ 0.306347] CPU: All CPU(s) started at EL2
10580 13:43:29.768963 <6>[ 0.310663] alternatives: applying system-wide alternatives
10581 13:43:29.779369 <6>[ 0.321515] devtmpfs: initialized
10582 13:43:29.795580 <6>[ 0.330609] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10583 13:43:29.802041 <6>[ 0.340572] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10584 13:43:29.808165 <6>[ 0.348594] pinctrl core: initialized pinctrl subsystem
10585 13:43:29.811548 <6>[ 0.355264] DMI not present or invalid.
10586 13:43:29.818299 <6>[ 0.359675] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10587 13:43:29.828253 <6>[ 0.366533] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10588 13:43:29.834311 <6>[ 0.374115] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10589 13:43:29.844228 <6>[ 0.382335] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10590 13:43:29.847327 <6>[ 0.390581] audit: initializing netlink subsys (disabled)
10591 13:43:29.858044 <5>[ 0.396278] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10592 13:43:29.864023 <6>[ 0.396992] thermal_sys: Registered thermal governor 'step_wise'
10593 13:43:29.871143 <6>[ 0.404248] thermal_sys: Registered thermal governor 'power_allocator'
10594 13:43:29.873965 <6>[ 0.410502] cpuidle: using governor menu
10595 13:43:29.880789 <6>[ 0.421469] NET: Registered PF_QIPCRTR protocol family
10596 13:43:29.887116 <6>[ 0.426945] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10597 13:43:29.893828 <6>[ 0.434043] ASID allocator initialised with 32768 entries
10598 13:43:29.897029 <6>[ 0.440637] Serial: AMBA PL011 UART driver
10599 13:43:29.907919 <4>[ 0.449482] Trying to register duplicate clock ID: 134
10600 13:43:29.965931 <6>[ 0.511266] KASLR enabled
10601 13:43:29.980750 <6>[ 0.519123] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10602 13:43:29.987129 <6>[ 0.526138] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10603 13:43:29.993411 <6>[ 0.532625] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10604 13:43:29.999907 <6>[ 0.539632] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10605 13:43:30.006873 <6>[ 0.546121] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10606 13:43:30.013744 <6>[ 0.553127] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10607 13:43:30.020226 <6>[ 0.559610] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10608 13:43:30.026481 <6>[ 0.566612] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10609 13:43:30.029369 <6>[ 0.574070] ACPI: Interpreter disabled.
10610 13:43:30.038336 <6>[ 0.580522] iommu: Default domain type: Translated
10611 13:43:30.045061 <6>[ 0.585632] iommu: DMA domain TLB invalidation policy: strict mode
10612 13:43:30.048508 <5>[ 0.592289] SCSI subsystem initialized
10613 13:43:30.054830 <6>[ 0.596457] usbcore: registered new interface driver usbfs
10614 13:43:30.061264 <6>[ 0.602187] usbcore: registered new interface driver hub
10615 13:43:30.065009 <6>[ 0.607737] usbcore: registered new device driver usb
10616 13:43:30.071767 <6>[ 0.613839] pps_core: LinuxPPS API ver. 1 registered
10617 13:43:30.081453 <6>[ 0.619034] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10618 13:43:30.084738 <6>[ 0.628380] PTP clock support registered
10619 13:43:30.088068 <6>[ 0.632625] EDAC MC: Ver: 3.0.0
10620 13:43:30.095999 <6>[ 0.637789] FPGA manager framework
10621 13:43:30.102227 <6>[ 0.641473] Advanced Linux Sound Architecture Driver Initialized.
10622 13:43:30.105288 <6>[ 0.648256] vgaarb: loaded
10623 13:43:30.112089 <6>[ 0.651409] clocksource: Switched to clocksource arch_sys_counter
10624 13:43:30.115368 <5>[ 0.657858] VFS: Disk quotas dquot_6.6.0
10625 13:43:30.121708 <6>[ 0.662042] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10626 13:43:30.124978 <6>[ 0.669234] pnp: PnP ACPI: disabled
10627 13:43:30.133760 <6>[ 0.675946] NET: Registered PF_INET protocol family
10628 13:43:30.143944 <6>[ 0.681546] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10629 13:43:30.155068 <6>[ 0.693855] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10630 13:43:30.165396 <6>[ 0.702669] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10631 13:43:30.171425 <6>[ 0.710643] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10632 13:43:30.181201 <6>[ 0.719343] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10633 13:43:30.187810 <6>[ 0.729094] TCP: Hash tables configured (established 65536 bind 65536)
10634 13:43:30.194327 <6>[ 0.735956] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10635 13:43:30.204256 <6>[ 0.743155] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10636 13:43:30.210564 <6>[ 0.750857] NET: Registered PF_UNIX/PF_LOCAL protocol family
10637 13:43:30.217468 <6>[ 0.757010] RPC: Registered named UNIX socket transport module.
10638 13:43:30.220322 <6>[ 0.763161] RPC: Registered udp transport module.
10639 13:43:30.227328 <6>[ 0.768091] RPC: Registered tcp transport module.
10640 13:43:30.234028 <6>[ 0.773025] RPC: Registered tcp NFSv4.1 backchannel transport module.
10641 13:43:30.237371 <6>[ 0.779687] PCI: CLS 0 bytes, default 64
10642 13:43:30.240462 <6>[ 0.784003] Unpacking initramfs...
10643 13:43:30.257585 <6>[ 0.795946] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10644 13:43:30.267587 <6>[ 0.804594] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10645 13:43:30.271109 <6>[ 0.813423] kvm [1]: IPA Size Limit: 40 bits
10646 13:43:30.277166 <6>[ 0.817952] kvm [1]: GICv3: no GICV resource entry
10647 13:43:30.280805 <6>[ 0.822973] kvm [1]: disabling GICv2 emulation
10648 13:43:30.287229 <6>[ 0.827664] kvm [1]: GIC system register CPU interface enabled
10649 13:43:30.290468 <6>[ 0.833824] kvm [1]: vgic interrupt IRQ18
10650 13:43:30.296629 <6>[ 0.838202] kvm [1]: VHE mode initialized successfully
10651 13:43:30.303421 <5>[ 0.844709] Initialise system trusted keyrings
10652 13:43:30.309721 <6>[ 0.849505] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10653 13:43:30.317359 <6>[ 0.859680] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10654 13:43:30.324104 <5>[ 0.866067] NFS: Registering the id_resolver key type
10655 13:43:30.327180 <5>[ 0.871368] Key type id_resolver registered
10656 13:43:30.333778 <5>[ 0.875784] Key type id_legacy registered
10657 13:43:30.340652 <6>[ 0.880062] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10658 13:43:30.347182 <6>[ 0.886983] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10659 13:43:30.353580 <6>[ 0.894695] 9p: Installing v9fs 9p2000 file system support
10660 13:43:30.391099 <5>[ 0.933197] Key type asymmetric registered
10661 13:43:30.394067 <5>[ 0.937528] Asymmetric key parser 'x509' registered
10662 13:43:30.404232 <6>[ 0.942670] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10663 13:43:30.407390 <6>[ 0.950287] io scheduler mq-deadline registered
10664 13:43:30.410552 <6>[ 0.955048] io scheduler kyber registered
10665 13:43:30.429874 <6>[ 0.972164] EINJ: ACPI disabled.
10666 13:43:30.462436 <4>[ 0.998158] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10667 13:43:30.472481 <4>[ 1.008853] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 13:43:30.487869 <6>[ 1.029705] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10669 13:43:30.495206 <6>[ 1.037697] printk: console [ttyS0] disabled
10670 13:43:30.523519 <6>[ 1.062332] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10671 13:43:30.530768 <6>[ 1.071806] printk: console [ttyS0] enabled
10672 13:43:30.533341 <6>[ 1.071806] printk: console [ttyS0] enabled
10673 13:43:30.540467 <6>[ 1.080702] printk: bootconsole [mtk8250] disabled
10674 13:43:30.543592 <6>[ 1.080702] printk: bootconsole [mtk8250] disabled
10675 13:43:30.550211 <6>[ 1.091736] SuperH (H)SCI(F) driver initialized
10676 13:43:30.553092 <6>[ 1.097002] msm_serial: driver initialized
10677 13:43:30.567098 <6>[ 1.105949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10678 13:43:30.577421 <6>[ 1.114498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10679 13:43:30.583975 <6>[ 1.123039] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10680 13:43:30.593906 <6>[ 1.131668] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10681 13:43:30.600571 <6>[ 1.140376] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10682 13:43:30.610544 <6>[ 1.149097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10683 13:43:30.620857 <6>[ 1.157637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10684 13:43:30.627557 <6>[ 1.166434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10685 13:43:30.636671 <6>[ 1.174979] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10686 13:43:30.649317 <6>[ 1.190640] loop: module loaded
10687 13:43:30.655286 <6>[ 1.196580] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10688 13:43:30.678436 <4>[ 1.220016] mtk-pmic-keys: Failed to locate of_node [id: -1]
10689 13:43:30.684927 <6>[ 1.226784] megasas: 07.719.03.00-rc1
10690 13:43:30.694793 <6>[ 1.236467] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10691 13:43:30.705337 <6>[ 1.246777] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10692 13:43:30.721874 <6>[ 1.263357] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10693 13:43:30.781952 <6>[ 1.317033] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10694 13:43:32.461398 <6>[ 3.003357] Freeing initrd memory: 50904K
10695 13:43:32.472891 <6>[ 3.015179] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10696 13:43:32.484331 <6>[ 3.026257] tun: Universal TUN/TAP device driver, 1.6
10697 13:43:32.487519 <6>[ 3.032338] thunder_xcv, ver 1.0
10698 13:43:32.490944 <6>[ 3.035845] thunder_bgx, ver 1.0
10699 13:43:32.494390 <6>[ 3.039334] nicpf, ver 1.0
10700 13:43:32.504840 <6>[ 3.043364] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10701 13:43:32.507912 <6>[ 3.050842] hns3: Copyright (c) 2017 Huawei Corporation.
10702 13:43:32.514372 <6>[ 3.056432] hclge is initializing
10703 13:43:32.517630 <6>[ 3.060006] e1000: Intel(R) PRO/1000 Network Driver
10704 13:43:32.523804 <6>[ 3.065135] e1000: Copyright (c) 1999-2006 Intel Corporation.
10705 13:43:32.531020 <6>[ 3.071148] e1000e: Intel(R) PRO/1000 Network Driver
10706 13:43:32.534132 <6>[ 3.076363] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10707 13:43:32.540355 <6>[ 3.082550] igb: Intel(R) Gigabit Ethernet Network Driver
10708 13:43:32.547062 <6>[ 3.088201] igb: Copyright (c) 2007-2014 Intel Corporation.
10709 13:43:32.554125 <6>[ 3.094037] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10710 13:43:32.560339 <6>[ 3.100555] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10711 13:43:32.563424 <6>[ 3.107019] sky2: driver version 1.30
10712 13:43:32.570069 <6>[ 3.111956] usbcore: registered new device driver r8152-cfgselector
10713 13:43:32.576883 <6>[ 3.118493] usbcore: registered new interface driver r8152
10714 13:43:32.583653 <6>[ 3.124320] VFIO - User Level meta-driver version: 0.3
10715 13:43:32.590357 <6>[ 3.132577] usbcore: registered new interface driver usb-storage
10716 13:43:32.597023 <6>[ 3.139024] usbcore: registered new device driver onboard-usb-hub
10717 13:43:32.606307 <6>[ 3.148240] mt6397-rtc mt6359-rtc: registered as rtc0
10718 13:43:32.616204 <6>[ 3.153735] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:43:32 UTC (1716903812)
10719 13:43:32.619560 <6>[ 3.163341] i2c_dev: i2c /dev entries driver
10720 13:43:32.636701 <6>[ 3.175174] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10721 13:43:32.642861 <4>[ 3.183911] cpu cpu0: supply cpu not found, using dummy regulator
10722 13:43:32.650005 <4>[ 3.190338] cpu cpu1: supply cpu not found, using dummy regulator
10723 13:43:32.655621 <4>[ 3.196744] cpu cpu2: supply cpu not found, using dummy regulator
10724 13:43:32.662513 <4>[ 3.203144] cpu cpu3: supply cpu not found, using dummy regulator
10725 13:43:32.668832 <4>[ 3.209563] cpu cpu4: supply cpu not found, using dummy regulator
10726 13:43:32.675904 <4>[ 3.215968] cpu cpu5: supply cpu not found, using dummy regulator
10727 13:43:32.682210 <4>[ 3.222365] cpu cpu6: supply cpu not found, using dummy regulator
10728 13:43:32.688856 <4>[ 3.228761] cpu cpu7: supply cpu not found, using dummy regulator
10729 13:43:32.708039 <6>[ 3.250418] cpu cpu0: EM: created perf domain
10730 13:43:32.711532 <6>[ 3.255356] cpu cpu4: EM: created perf domain
10731 13:43:32.718504 <6>[ 3.260955] sdhci: Secure Digital Host Controller Interface driver
10732 13:43:32.725358 <6>[ 3.267388] sdhci: Copyright(c) Pierre Ossman
10733 13:43:32.731531 <6>[ 3.272351] Synopsys Designware Multimedia Card Interface Driver
10734 13:43:32.738236 <6>[ 3.278980] sdhci-pltfm: SDHCI platform and OF driver helper
10735 13:43:32.741517 <6>[ 3.279029] mmc0: CQHCI version 5.10
10736 13:43:32.748156 <6>[ 3.289170] ledtrig-cpu: registered to indicate activity on CPUs
10737 13:43:32.755299 <6>[ 3.296140] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10738 13:43:32.761547 <6>[ 3.303202] usbcore: registered new interface driver usbhid
10739 13:43:32.764684 <6>[ 3.309024] usbhid: USB HID core driver
10740 13:43:32.771754 <6>[ 3.313235] spi_master spi0: will run message pump with realtime priority
10741 13:43:32.816760 <6>[ 3.352639] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10742 13:43:32.836290 <6>[ 3.368319] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10743 13:43:32.839176 <6>[ 3.381946] mmc0: Command Queue Engine enabled
10744 13:43:32.845805 <6>[ 3.386755] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10745 13:43:32.852647 <6>[ 3.394031] mmcblk0: mmc0:0001 DA4128 116 GiB
10746 13:43:32.858909 <6>[ 3.398999] cros-ec-spi spi0.0: Chrome EC device registered
10747 13:43:32.861973 <6>[ 3.403155] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10748 13:43:32.870085 <6>[ 3.412531] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10749 13:43:32.876467 <6>[ 3.418760] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10750 13:43:32.882947 <6>[ 3.424722] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10751 13:43:32.901613 <6>[ 3.441098] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10752 13:43:32.909139 <6>[ 3.451718] NET: Registered PF_PACKET protocol family
10753 13:43:32.916088 <6>[ 3.457118] 9pnet: Installing 9P2000 support
10754 13:43:32.919499 <5>[ 3.461684] Key type dns_resolver registered
10755 13:43:32.922464 <6>[ 3.466682] registered taskstats version 1
10756 13:43:32.929146 <5>[ 3.471073] Loading compiled-in X.509 certificates
10757 13:43:32.959737 <4>[ 3.495697] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10758 13:43:32.969862 <4>[ 3.506436] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10759 13:43:32.986541 <6>[ 3.528439] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10760 13:43:32.992871 <6>[ 3.535213] xhci-mtk 11200000.usb: xHCI Host Controller
10761 13:43:32.999752 <6>[ 3.540713] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10762 13:43:33.010043 <6>[ 3.548562] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10763 13:43:33.016700 <6>[ 3.557995] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10764 13:43:33.023019 <6>[ 3.564183] xhci-mtk 11200000.usb: xHCI Host Controller
10765 13:43:33.029501 <6>[ 3.569686] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10766 13:43:33.036774 <6>[ 3.577342] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10767 13:43:33.043342 <6>[ 3.585153] hub 1-0:1.0: USB hub found
10768 13:43:33.046508 <6>[ 3.589185] hub 1-0:1.0: 1 port detected
10769 13:43:33.056852 <6>[ 3.593488] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10770 13:43:33.059691 <6>[ 3.602233] hub 2-0:1.0: USB hub found
10771 13:43:33.063510 <6>[ 3.606260] hub 2-0:1.0: 1 port detected
10772 13:43:33.071092 <6>[ 3.612858] mtk-msdc 11f70000.mmc: Got CD GPIO
10773 13:43:33.084183 <6>[ 3.622946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10774 13:43:33.090974 <6>[ 3.630975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10775 13:43:33.100485 <4>[ 3.638914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10776 13:43:33.110976 <6>[ 3.648448] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10777 13:43:33.117321 <6>[ 3.656525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10778 13:43:33.124130 <6>[ 3.664544] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10779 13:43:33.133982 <6>[ 3.672468] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10780 13:43:33.140693 <6>[ 3.680285] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10781 13:43:33.150453 <6>[ 3.688104] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10782 13:43:33.160156 <6>[ 3.698387] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10783 13:43:33.166877 <6>[ 3.706745] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10784 13:43:33.176556 <6>[ 3.715091] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10785 13:43:33.183269 <6>[ 3.723429] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10786 13:43:33.193044 <6>[ 3.731767] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10787 13:43:33.199527 <6>[ 3.740106] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10788 13:43:33.209967 <6>[ 3.748444] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10789 13:43:33.219459 <6>[ 3.756782] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10790 13:43:33.226079 <6>[ 3.765119] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10791 13:43:33.236068 <6>[ 3.773457] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10792 13:43:33.243032 <6>[ 3.781797] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10793 13:43:33.252602 <6>[ 3.790136] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10794 13:43:33.258857 <6>[ 3.798474] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10795 13:43:33.268953 <6>[ 3.806812] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10796 13:43:33.275886 <6>[ 3.815149] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10797 13:43:33.282685 <6>[ 3.823891] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10798 13:43:33.288940 <6>[ 3.831144] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10799 13:43:33.295976 <6>[ 3.838006] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10800 13:43:33.305726 <6>[ 3.844839] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10801 13:43:33.312799 <6>[ 3.851841] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10802 13:43:33.319164 <6>[ 3.858699] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10803 13:43:33.329473 <6>[ 3.867830] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10804 13:43:33.339302 <6>[ 3.876951] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10805 13:43:33.349327 <6>[ 3.886246] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10806 13:43:33.358859 <6>[ 3.895713] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10807 13:43:33.368814 <6>[ 3.905180] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10808 13:43:33.374788 <6>[ 3.914300] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10809 13:43:33.385490 <6>[ 3.923769] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10810 13:43:33.394693 <6>[ 3.932888] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10811 13:43:33.405310 <6>[ 3.942185] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10812 13:43:33.414663 <6>[ 3.952345] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10813 13:43:33.425112 <6>[ 3.963979] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10814 13:43:33.472750 <6>[ 4.011682] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10815 13:43:33.626042 <6>[ 4.168385] hub 1-1:1.0: USB hub found
10816 13:43:33.629796 <6>[ 4.172788] hub 1-1:1.0: 4 ports detected
10817 13:43:33.638296 <6>[ 4.180323] hub 1-1:1.0: USB hub found
10818 13:43:33.641523 <6>[ 4.184696] hub 1-1:1.0: 4 ports detected
10819 13:43:33.753042 <6>[ 4.292092] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10820 13:43:33.779042 <6>[ 4.321384] hub 2-1:1.0: USB hub found
10821 13:43:33.783093 <6>[ 4.325882] hub 2-1:1.0: 3 ports detected
10822 13:43:33.791535 <6>[ 4.333895] hub 2-1:1.0: USB hub found
10823 13:43:33.795211 <6>[ 4.338348] hub 2-1:1.0: 3 ports detected
10824 13:43:33.968790 <6>[ 4.507727] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10825 13:43:34.101675 <6>[ 4.643616] hub 1-1.4:1.0: USB hub found
10826 13:43:34.104850 <6>[ 4.648283] hub 1-1.4:1.0: 2 ports detected
10827 13:43:34.114443 <6>[ 4.656478] hub 1-1.4:1.0: USB hub found
10828 13:43:34.117790 <6>[ 4.661073] hub 1-1.4:1.0: 2 ports detected
10829 13:43:34.180480 <6>[ 4.719924] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10830 13:43:34.288998 <6>[ 4.828373] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10831 13:43:34.325876 <4>[ 4.864832] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10832 13:43:34.335997 <4>[ 4.873996] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10833 13:43:34.375044 <6>[ 4.917065] r8152 2-1.3:1.0 eth0: v1.12.13
10834 13:43:34.416779 <6>[ 4.955781] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10835 13:43:34.608888 <6>[ 5.147536] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10836 13:43:36.037247 <6>[ 6.579674] r8152 2-1.3:1.0 eth0: carrier on
10837 13:43:38.152764 <5>[ 6.607503] Sending DHCP requests .., OK
10838 13:43:38.159016 <6>[ 8.699866] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10839 13:43:38.162547 <6>[ 8.708161] IP-Config: Complete:
10840 13:43:38.175662 <6>[ 8.711663] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10841 13:43:38.182578 <6>[ 8.722397] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10842 13:43:38.192459 <6>[ 8.731018] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10843 13:43:38.195513 <6>[ 8.731027] nameserver0=192.168.201.1
10844 13:43:38.198931 <6>[ 8.743161] clk: Disabling unused clocks
10845 13:43:38.202118 <6>[ 8.748654] ALSA device list:
10846 13:43:38.208830 <6>[ 8.751922] No soundcards found.
10847 13:43:38.216660 <6>[ 8.759688] Freeing unused kernel memory: 8512K
10848 13:43:38.220270 <6>[ 8.764614] Run /init as init process
10849 13:43:38.249662 <6>[ 8.792728] NET: Registered PF_INET6 protocol family
10850 13:43:38.256659 <6>[ 8.799502] Segment Routing with IPv6
10851 13:43:38.260014 <6>[ 8.803439] In-situ OAM (IOAM) with IPv6
10852 13:43:38.301423 <30>[ 8.817917] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10853 13:43:38.307710 <30>[ 8.850966] systemd[1]: Detected architecture arm64.
10854 13:43:38.307838
10855 13:43:38.314924 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10856 13:43:38.315029
10857 13:43:38.328638 <30>[ 8.871790] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10858 13:43:38.445185 <30>[ 8.984849] systemd[1]: Queued start job for default target graphical.target.
10859 13:43:38.505718 <30>[ 9.045611] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10860 13:43:38.512720 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10861 13:43:38.532760 <30>[ 9.072477] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10862 13:43:38.542098 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10863 13:43:38.561224 <30>[ 9.100781] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10864 13:43:38.570745 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10865 13:43:38.589743 <30>[ 9.129631] systemd[1]: Created slice user.slice - User and Session Slice.
10866 13:43:38.596598 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10867 13:43:38.619454 <30>[ 9.156052] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10868 13:43:38.626191 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10869 13:43:38.647300 <30>[ 9.183925] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10870 13:43:38.654134 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10871 13:43:38.682058 <30>[ 9.212252] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10872 13:43:38.692622 <30>[ 9.232132] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10873 13:43:38.699117 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10874 13:43:38.715844 <30>[ 9.255706] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10875 13:43:38.722515 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10876 13:43:38.739958 <30>[ 9.279772] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10877 13:43:38.749582 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10878 13:43:38.764541 <30>[ 9.307812] systemd[1]: Reached target paths.target - Path Units.
10879 13:43:38.774937 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10880 13:43:38.792396 <30>[ 9.332058] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10881 13:43:38.799243 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10882 13:43:38.815980 <30>[ 9.355687] systemd[1]: Reached target slices.target - Slice Units.
10883 13:43:38.822565 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10884 13:43:38.836570 <30>[ 9.379782] systemd[1]: Reached target swap.target - Swaps.
10885 13:43:38.843361 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10886 13:43:38.864306 <30>[ 9.403774] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10887 13:43:38.874277 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10888 13:43:38.892538 <30>[ 9.432298] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10889 13:43:38.902335 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10890 13:43:38.921461 <30>[ 9.461046] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10891 13:43:38.930908 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10892 13:43:38.948820 <30>[ 9.488291] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10893 13:43:38.958074 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10894 13:43:38.977351 <30>[ 9.517022] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10895 13:43:38.983840 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10896 13:43:39.004542 <30>[ 9.544456] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10897 13:43:39.014352 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10898 13:43:39.033178 <30>[ 9.573080] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10899 13:43:39.043085 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10900 13:43:39.061027 <30>[ 9.600858] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10901 13:43:39.071221 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10902 13:43:39.124343 <30>[ 9.663930] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10903 13:43:39.131066 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10904 13:43:39.143421 <30>[ 9.683339] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10905 13:43:39.150284 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10906 13:43:39.172328 <30>[ 9.712035] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10907 13:43:39.178851 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10908 13:43:39.202853 <30>[ 9.736118] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10909 13:43:39.216111 <30>[ 9.756360] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10910 13:43:39.226322 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10911 13:43:39.249453 <30>[ 9.788672] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10912 13:43:39.255741 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10913 13:43:39.316217 <30>[ 9.856032] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10914 13:43:39.329504 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 9.869867] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10915 13:43:39.332908 Module dm_mod...
10916 13:43:39.357480 <30>[ 9.897098] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10917 13:43:39.363703 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10918 13:43:39.388651 <30>[ 9.928682] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10919 13:43:39.398558 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10920 13:43:39.460500 <30>[ 10.000111] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10921 13:43:39.467007 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10922 13:43:39.496560 <30>[ 10.036353] systemd[1]: Starting systemd-journald.service - Journal Service...
10923 13:43:39.503261 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10924 13:43:39.522541 <30>[ 10.062361] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10925 13:43:39.528833 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10926 13:43:39.554766 <30>[ 10.090894] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10927 13:43:39.561109 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10928 13:43:39.583550 <30>[ 10.123554] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10929 13:43:39.593693 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10930 13:43:39.614878 <30>[ 10.154902] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10931 13:43:39.621341 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10932 13:43:39.643605 <30>[ 10.183717] systemd[1]: Started systemd-journald.service - Journal Service.
10933 13:43:39.650487 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10934 13:43:39.670948 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10935 13:43:39.689243 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10936 13:43:39.708805 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10937 13:43:39.728957 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10938 13:43:39.750793 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10939 13:43:39.771373 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10940 13:43:39.790643 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10941 13:43:39.810875 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10942 13:43:39.831278 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10943 13:43:39.850381 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10944 13:43:39.870658 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10945 13:43:39.890227 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10946 13:43:39.897184 See 'systemctl status systemd-remount-fs.service' for details.
10947 13:43:39.907173 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10948 13:43:39.926907 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10949 13:43:39.976315 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10950 13:43:39.998320 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10951 13:43:40.012836 <46>[ 10.552648] systemd-journald[194]: Received client request to flush runtime journal.
10952 13:43:40.024762 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10953 13:43:40.048395 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10954 13:43:40.073329 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10955 13:43:40.102244 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10956 13:43:40.124879 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10957 13:43:40.149517 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10958 13:43:40.173150 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10959 13:43:40.193111 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10960 13:43:40.236954 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10961 13:43:40.262966 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10962 13:43:40.284035 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10963 13:43:40.304016 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10964 13:43:40.360673 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10965 13:43:40.384655 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10966 13:43:40.407773 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10967 13:43:40.446812 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10968 13:43:40.476245 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10969 13:43:40.501460 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10970 13:43:40.526801 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10971 13:43:40.570042 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10972 13:43:40.593969 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10973 13:43:40.705051 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10974 13:43:40.725431 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10975 13:43:40.745315 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10976 13:43:40.765483 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10977 13:43:40.784767 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10978 13:43:40.802072 <6>[ 11.342244] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10979 13:43:40.812063 <6>[ 11.350952] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10980 13:43:40.822351 [[0;32m OK [<6>[ 11.361536] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10981 13:43:40.831492 0m] Listening on<3>[ 11.365735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10982 13:43:40.841471 [0;1;39mdbus.s<3>[ 11.380786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10983 13:43:40.851974 ocket[…- D-Bu<6>[ 11.381536] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10984 13:43:40.858602 s System Message<3>[ 11.389741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10985 13:43:40.861495 Bus Socket.
10986 13:43:40.868417 <4>[ 11.393485] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10987 13:43:40.871678 <6>[ 11.393656] mc: Linux media interface: v0.10
10988 13:43:40.881234 <4>[ 11.408635] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10989 13:43:40.887729 [[0;32m OK [<6>[ 11.428566] remoteproc remoteproc0: scp is available
10990 13:43:40.894665 <3>[ 11.434242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10991 13:43:40.901093 0m] Reached targ<6>[ 11.435570] remoteproc remoteproc0: powering up scp
10992 13:43:40.911037 <3>[ 11.443351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 13:43:40.920605 et [0;1;39msock<6>[ 11.449671] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10994 13:43:40.927319 <3>[ 11.457907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10995 13:43:40.934024 ets.target[0m -<6>[ 11.467613] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10996 13:43:40.937189 Socket Units.
10997 13:43:40.943961 <3>[ 11.475673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10998 13:43:40.944082
10999 13:43:40.950934 <3>[ 11.492217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11000 13:43:40.960151 <6>[ 11.500211] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11001 13:43:40.966858 <3>[ 11.500390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11002 13:43:40.973730 <6>[ 11.500531] videodev: Linux video capture interface: v2.00
11003 13:43:40.976751 <6>[ 11.507495] pci_bus 0000:00: root bus resource [bus 00-ff]
11004 13:43:40.986929 <6>[ 11.511003] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11005 13:43:40.993627 <3>[ 11.515395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 13:43:41.000647 <6>[ 11.521813] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11007 13:43:41.010973 <3>[ 11.526834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11008 13:43:41.017712 <3>[ 11.526849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11009 13:43:41.024245 <3>[ 11.526954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11010 13:43:41.033689 <4>[ 11.532667] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11011 13:43:41.040845 <4>[ 11.532667] Fallback method does not support PEC.
11012 13:43:41.047940 <6>[ 11.535024] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11013 13:43:41.058099 <3>[ 11.542618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11014 13:43:41.064644 <3>[ 11.542622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11015 13:43:41.074896 <6>[ 11.546677] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11016 13:43:41.084160 <3>[ 11.549723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 13:43:41.090760 <6>[ 11.549785] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11018 13:43:41.097530 <3>[ 11.557838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11019 13:43:41.104306 <6>[ 11.566191] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11020 13:43:41.114523 <3>[ 11.573990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11021 13:43:41.120913 <3>[ 11.574021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11022 13:43:41.124609 <6>[ 11.587689] pci 0000:00:00.0: supports D1 D2
11023 13:43:41.134534 <3>[ 11.591472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 13:43:41.141478 <3>[ 11.592352] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11025 13:43:41.152472 <6>[ 11.604549] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11026 13:43:41.158791 <6>[ 11.605600] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11027 13:43:41.165244 <6>[ 11.613739] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11028 13:43:41.175674 <6>[ 11.613858] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11029 13:43:41.182013 <6>[ 11.613876] remoteproc remoteproc0: remote processor scp is now up
11030 13:43:41.188883 <6>[ 11.614163] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11031 13:43:41.199098 <6>[ 11.624342] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11032 13:43:41.206049 <6>[ 11.647745] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11033 13:43:41.212500 <6>[ 11.653934] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11034 13:43:41.215671 <6>[ 11.654435] Bluetooth: Core ver 2.22
11035 13:43:41.222606 <6>[ 11.654535] NET: Registered PF_BLUETOOTH protocol family
11036 13:43:41.228788 <6>[ 11.654539] Bluetooth: HCI device and connection manager initialized
11037 13:43:41.235648 <6>[ 11.654599] Bluetooth: HCI socket layer initialized
11038 13:43:41.239280 <6>[ 11.654607] Bluetooth: L2CAP socket layer initialized
11039 13:43:41.246041 <6>[ 11.654622] Bluetooth: SCO socket layer initialized
11040 13:43:41.252280 <3>[ 11.661850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11041 13:43:41.262870 <3>[ 11.662519] power_supply sbs-5-000b: driver failed to report `health' property: -6
11042 13:43:41.269460 <6>[ 11.665706] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11043 13:43:41.278904 <6>[ 11.669938] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11044 13:43:41.285622 <3>[ 11.678092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 13:43:41.292398 <6>[ 11.683242] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11046 13:43:41.302522 <3>[ 11.698164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 13:43:41.309511 <6>[ 11.700975] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11048 13:43:41.316395 <6>[ 11.701097] pci 0000:01:00.0: supports D1 D2
11049 13:43:41.323443 <6>[ 11.708370] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11050 13:43:41.329769 <6>[ 11.714885] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11051 13:43:41.333703 <6>[ 11.715797] usbcore: registered new interface driver btusb
11052 13:43:41.340217 <6>[ 11.715946] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11053 13:43:41.350420 <4>[ 11.716494] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11054 13:43:41.357043 <3>[ 11.716511] Bluetooth: hci0: Failed to load firmware file (-2)
11055 13:43:41.363506 <3>[ 11.716516] Bluetooth: hci0: Failed to set up firmware (-2)
11056 13:43:41.373350 <4>[ 11.716520] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11057 13:43:41.386600 <6>[ 11.724757] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11058 13:43:41.393183 <6>[ 11.730838] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11059 13:43:41.402929 <3>[ 11.733166] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 13:43:41.406286 <6>[ 11.739413] usbcore: registered new interface driver uvcvideo
11061 13:43:41.416594 <6>[ 11.747349] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11062 13:43:41.422671 <6>[ 11.747354] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11063 13:43:41.432674 <6>[ 11.747367] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11064 13:43:41.439484 <6>[ 11.747379] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11065 13:43:41.446362 <6>[ 11.747392] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11066 13:43:41.452365 <6>[ 11.747405] pci 0000:00:00.0: PCI bridge to [bus 01]
11067 13:43:41.459279 <6>[ 11.747412] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11068 13:43:41.466306 <6>[ 11.747629] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11069 13:43:41.475779 <3>[ 11.755784] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11070 13:43:41.482073 <6>[ 11.762584] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11071 13:43:41.492187 <3>[ 11.787633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11072 13:43:41.495817 <6>[ 11.788661] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11073 13:43:41.505218 <5>[ 11.853903] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11074 13:43:41.512035 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11075 13:43:41.529278 <5>[ 12.068912] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11076 13:43:41.535229 <5>[ 12.075988] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11077 13:43:41.545408 <4>[ 12.084427] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11078 13:43:41.548512 <6>[ 12.093325] cfg80211: failed to load regulatory.db
11079 13:43:41.558394 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11080 13:43:41.594473 <6>[ 12.134486] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11081 13:43:41.601353 <6>[ 12.142000] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11082 13:43:41.618907 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11083 13:43:41.625541 <6>[ 12.168501] mt7921e 0000:01:00.0: ASIC revision: 79610010
11084 13:43:41.650845 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11085 13:43:41.673434 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11086 13:43:41.692929 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11087 13:43:41.733539 <6>[ 12.273612] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11088 13:43:41.737153 <6>[ 12.273612]
11089 13:43:41.743130 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11090 13:43:41.763248 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11091 13:43:41.779991 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11092 13:43:41.799594 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11093 13:43:41.815807 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11094 13:43:41.868043 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11095 13:43:41.892482 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11096 13:43:41.915280 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11097 13:43:41.936253 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11098 13:43:41.982444 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11099 13:43:42.000547 <6>[ 12.540568] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11100 13:43:42.010872 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11101 13:43:42.028972 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11102 13:43:42.044688 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11103 13:43:42.064042 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11104 13:43:42.124675 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11105 13:43:42.149309 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11106 13:43:42.172329 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11107 13:43:42.212120 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11108 13:43:42.259441
11109 13:43:42.263027 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11110 13:43:42.263145
11111 13:43:42.266034 debian-bookworm-arm64 login: root (automatic login)
11112 13:43:42.266122
11113 13:43:42.284660 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11114 13:43:42.284819
11115 13:43:42.290834 The programs included with the Debian GNU/Linux system are free software;
11116 13:43:42.297643 the exact distribution terms for each program are described in the
11117 13:43:42.300795 individual files in /usr/share/doc/*/copyright.
11118 13:43:42.300882
11119 13:43:42.307101 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11120 13:43:42.310438 permitted by applicable law.
11121 13:43:42.310857 Matched prompt #10: / #
11123 13:43:42.311075 Setting prompt string to ['/ #']
11124 13:43:42.311168 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11126 13:43:42.311360 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11127 13:43:42.311448 start: 2.2.6 expect-shell-connection (timeout 00:02:48) [common]
11128 13:43:42.311520 Setting prompt string to ['/ #']
11129 13:43:42.311580 Forcing a shell prompt, looking for ['/ #']
11131 13:43:42.361810 / #
11132 13:43:42.361982 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11133 13:43:42.362059 Waiting using forced prompt support (timeout 00:02:30)
11134 13:43:42.366671
11135 13:43:42.366989 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11136 13:43:42.367109 start: 2.2.7 export-device-env (timeout 00:02:48) [common]
11137 13:43:42.367200 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11138 13:43:42.367287 end: 2.2 depthcharge-retry (duration 00:02:12) [common]
11139 13:43:42.367370 end: 2 depthcharge-action (duration 00:02:12) [common]
11140 13:43:42.367457 start: 3 lava-test-retry (timeout 00:05:00) [common]
11141 13:43:42.367545 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11142 13:43:42.367619 Using namespace: common
11144 13:43:42.467940 / # #
11145 13:43:42.468121 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11146 13:43:42.473274 #
11147 13:43:42.473549 Using /lava-14063115
11149 13:43:42.573920 / # export SHELL=/bin/sh
11150 13:43:42.579756 export SHELL=/bin/sh
11152 13:43:42.680372 / # . /lava-14063115/environment
11153 13:43:42.685519 . /lava-14063115/environment
11155 13:43:42.786115 / # /lava-14063115/bin/lava-test-runner /lava-14063115/0
11156 13:43:42.786339 Test shell timeout: 10s (minimum of the action and connection timeout)
11157 13:43:42.791389 /lava-14063115/bin/lava-test-runner /lava-14063115/0
11158 13:43:42.816924 + export TESTRUN<8>[ 13.358334] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14063115_1.5.2.3.1>
11159 13:43:42.817076 _ID=0_cros-ec
11160 13:43:42.817330 Received signal: <STARTRUN> 0_cros-ec 14063115_1.5.2.3.1
11161 13:43:42.817410 Starting test lava.0_cros-ec (14063115_1.5.2.3.1)
11162 13:43:42.817493 Skipping test definition patterns.
11163 13:43:42.820286 + cd /lava-14063115/0/tests/0_cros-ec
11164 13:43:42.823032 + cat uuid
11165 13:43:42.823117 + UUID=14063115_1.5.2.3.1
11166 13:43:42.826873 + set +x
11167 13:43:42.829832 + python3 -m cros.runners.lava_runner -v
11168 13:43:42.863530 <6>[ 13.407150] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11169 13:43:43.283826 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11170 13:43:43.289901 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11171 13:43:43.289997
11172 13:43:43.296847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11173 13:43:43.297111 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11175 13:43:43.306825 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11176 13:43:43.316595 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11177 13:43:43.316713
11178 13:43:43.322931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11179 13:43:43.323193 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11181 13:43:43.333097 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11182 13:43:43.339252 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11183 13:43:43.339347
11184 13:43:43.345879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11185 13:43:43.346143 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11187 13:43:43.352698 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11188 13:43:43.359126 Checks the standard ABI for the main Embedded Controller. ... ok
11189 13:43:43.359226
11190 13:43:43.362390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11191 13:43:43.362656 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11193 13:43:43.369130 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11194 13:43:43.375787 Checks the main Embedded controller character device. ... ok
11195 13:43:43.375884
11196 13:43:43.382840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11197 13:43:43.383107 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11199 13:43:43.389006 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11200 13:43:43.395177 Checks basic comunication with the main Embedded controller. ... ok
11201 13:43:43.395277
11202 13:43:43.402281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11203 13:43:43.402551 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11205 13:43:43.408933 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11206 13:43:43.415034 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11207 13:43:43.415146
11208 13:43:43.421803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11209 13:43:43.422075 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11211 13:43:43.428557 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11212 13:43:43.435010 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11213 13:43:43.435114
11214 13:43:43.441437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11215 13:43:43.441716 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11217 13:43:43.448135 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11218 13:43:43.454998 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11219 13:43:43.455109
11220 13:43:43.461815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11221 13:43:43.462097 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11223 13:43:43.467974 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11224 13:43:43.477811 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11225 13:43:43.477943
11226 13:43:43.481274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11227 13:43:43.481534 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11229 13:43:43.487945 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11230 13:43:43.497701 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11231 13:43:43.497819
11232 13:43:43.504277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11233 13:43:43.504573 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11235 13:43:43.511159 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11236 13:43:43.517541 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11237 13:43:43.517657
11238 13:43:43.524088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11239 13:43:43.524366 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11241 13:43:43.530901 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11242 13:43:43.537305 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11243 13:43:43.537540
11244 13:43:43.543719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11245 13:43:43.544144 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11247 13:43:43.553745 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11248 13:43:43.560401 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11249 13:43:43.560505
11250 13:43:43.567042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11251 13:43:43.567362 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11253 13:43:43.577157 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11254 13:43:43.580326 Check the cros battery ABI. ... skipped 'No BAT found'
11255 13:43:43.580415
11256 13:43:43.586671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11257 13:43:43.586939 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11259 13:43:43.596789 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11260 13:43:43.603370 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11261 13:43:43.603472
11262 13:43:43.610139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11263 13:43:43.610450 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11265 13:43:43.619739 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11266 13:43:43.626913 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11267 13:43:43.627014
11268 13:43:43.629712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11269 13:43:43.630006 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11271 13:43:43.639757 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11272 13:43:43.646387 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11273 13:43:43.646487
11274 13:43:43.653048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11275 13:43:43.653140
11276 13:43:43.653381 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11278 13:43:43.663035 --------------------------<8>[ 14.203419] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14063115_1.5.2.3.1>
11279 13:43:43.663340 Received signal: <ENDRUN> 0_cros-ec 14063115_1.5.2.3.1
11280 13:43:43.663423 Ending use of test pattern.
11281 13:43:43.663486 Ending test lava.0_cros-ec (14063115_1.5.2.3.1), duration 0.85
11283 13:43:43.666034 --------------------------------------------
11284 13:43:43.669588 Ran 18 tests in 0.341s
11285 13:43:43.669675
11286 13:43:43.669739 OK (skipped=15)
11287 13:43:43.669800 + set +x
11288 13:43:43.672413 <LAVA_TEST_RUNNER EXIT>
11289 13:43:43.672667 ok: lava_test_shell seems to have completed
11290 13:43:43.672843 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11291 13:43:43.672938 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11292 13:43:43.673025 end: 3 lava-test-retry (duration 00:00:01) [common]
11293 13:43:43.673112 start: 4 finalize (timeout 00:07:23) [common]
11294 13:43:43.673202 start: 4.1 power-off (timeout 00:00:30) [common]
11295 13:43:43.673345 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11296 13:43:43.873529 >> Command sent successfully.
11297 13:43:43.875956 Returned 0 in 0 seconds
11298 13:43:43.976346 end: 4.1 power-off (duration 00:00:00) [common]
11300 13:43:43.976697 start: 4.2 read-feedback (timeout 00:07:23) [common]
11301 13:43:43.977002 Listened to connection for namespace 'common' for up to 1s
11302 13:43:44.977974 Finalising connection for namespace 'common'
11303 13:43:44.978165 Disconnecting from shell: Finalise
11304 13:43:44.978284 / #
11305 13:43:45.078638 end: 4.2 read-feedback (duration 00:00:01) [common]
11306 13:43:45.078829 end: 4 finalize (duration 00:00:01) [common]
11307 13:43:45.078945 Cleaning after the job
11308 13:43:45.079044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/ramdisk
11309 13:43:45.084861 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/kernel
11310 13:43:45.098881 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/dtb
11311 13:43:45.099124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063115/tftp-deploy-pc8phom8/modules
11312 13:43:45.104592 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063115
11313 13:43:45.193335 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063115
11314 13:43:45.193516 Job finished correctly