Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 13:44:06.269080 lava-dispatcher, installed at version: 2024.03
2 13:44:06.269298 start: 0 validate
3 13:44:06.269440 Start time: 2024-05-28 13:44:06.269432+00:00 (UTC)
4 13:44:06.269570 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:44:06.269698 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:44:06.544576 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:44:06.544750 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:44:06.816105 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:44:06.816296 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:44:07.088582 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:44:07.088748 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:44:07.355945 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:44:07.356146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:44:08.023774 validate duration: 1.75
16 13:44:08.024063 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:44:08.024170 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:44:08.024255 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:44:08.024411 Not decompressing ramdisk as can be used compressed.
20 13:44:08.024515 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:44:08.024582 saving as /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/ramdisk/initrd.cpio.gz
22 13:44:08.024647 total size: 5628169 (5 MB)
23 13:44:08.025747 progress 0 % (0 MB)
24 13:44:08.027516 progress 5 % (0 MB)
25 13:44:08.029131 progress 10 % (0 MB)
26 13:44:08.030554 progress 15 % (0 MB)
27 13:44:08.032116 progress 20 % (1 MB)
28 13:44:08.033571 progress 25 % (1 MB)
29 13:44:08.035141 progress 30 % (1 MB)
30 13:44:08.036773 progress 35 % (1 MB)
31 13:44:08.038136 progress 40 % (2 MB)
32 13:44:08.039656 progress 45 % (2 MB)
33 13:44:08.041108 progress 50 % (2 MB)
34 13:44:08.042633 progress 55 % (2 MB)
35 13:44:08.044165 progress 60 % (3 MB)
36 13:44:08.045576 progress 65 % (3 MB)
37 13:44:08.047138 progress 70 % (3 MB)
38 13:44:08.048550 progress 75 % (4 MB)
39 13:44:08.050097 progress 80 % (4 MB)
40 13:44:08.051466 progress 85 % (4 MB)
41 13:44:08.053057 progress 90 % (4 MB)
42 13:44:08.054609 progress 95 % (5 MB)
43 13:44:08.056048 progress 100 % (5 MB)
44 13:44:08.056278 5 MB downloaded in 0.03 s (169.70 MB/s)
45 13:44:08.056495 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:44:08.056736 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:44:08.056821 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:44:08.056904 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:44:08.057040 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:44:08.057109 saving as /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/kernel/Image
52 13:44:08.057169 total size: 54682112 (52 MB)
53 13:44:08.057231 No compression specified
54 13:44:08.058349 progress 0 % (0 MB)
55 13:44:08.072380 progress 5 % (2 MB)
56 13:44:08.086333 progress 10 % (5 MB)
57 13:44:08.100595 progress 15 % (7 MB)
58 13:44:08.114548 progress 20 % (10 MB)
59 13:44:08.128689 progress 25 % (13 MB)
60 13:44:08.142656 progress 30 % (15 MB)
61 13:44:08.156810 progress 35 % (18 MB)
62 13:44:08.170823 progress 40 % (20 MB)
63 13:44:08.184873 progress 45 % (23 MB)
64 13:44:08.199038 progress 50 % (26 MB)
65 13:44:08.213063 progress 55 % (28 MB)
66 13:44:08.227319 progress 60 % (31 MB)
67 13:44:08.241312 progress 65 % (33 MB)
68 13:44:08.255442 progress 70 % (36 MB)
69 13:44:08.269379 progress 75 % (39 MB)
70 13:44:08.283356 progress 80 % (41 MB)
71 13:44:08.297450 progress 85 % (44 MB)
72 13:44:08.311502 progress 90 % (46 MB)
73 13:44:08.325575 progress 95 % (49 MB)
74 13:44:08.339847 progress 100 % (52 MB)
75 13:44:08.340157 52 MB downloaded in 0.28 s (184.28 MB/s)
76 13:44:08.340399 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:44:08.340637 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:44:08.340723 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:44:08.340807 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:44:08.340947 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:44:08.341017 saving as /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/dtb/mt8192-asurada-spherion-r0.dtb
83 13:44:08.341077 total size: 47258 (0 MB)
84 13:44:08.341138 No compression specified
85 13:44:08.342285 progress 69 % (0 MB)
86 13:44:08.342560 progress 100 % (0 MB)
87 13:44:08.342716 0 MB downloaded in 0.00 s (27.54 MB/s)
88 13:44:08.342838 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:44:08.343068 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:44:08.343153 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:44:08.343236 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:44:08.343350 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:44:08.343417 saving as /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/nfsrootfs/full.rootfs.tar
95 13:44:08.343478 total size: 120894716 (115 MB)
96 13:44:08.343540 Using unxz to decompress xz
97 13:44:08.347666 progress 0 % (0 MB)
98 13:44:08.692278 progress 5 % (5 MB)
99 13:44:09.050797 progress 10 % (11 MB)
100 13:44:09.399917 progress 15 % (17 MB)
101 13:44:09.724715 progress 20 % (23 MB)
102 13:44:10.015991 progress 25 % (28 MB)
103 13:44:10.374813 progress 30 % (34 MB)
104 13:44:10.712010 progress 35 % (40 MB)
105 13:44:10.881554 progress 40 % (46 MB)
106 13:44:11.061328 progress 45 % (51 MB)
107 13:44:11.378737 progress 50 % (57 MB)
108 13:44:11.754514 progress 55 % (63 MB)
109 13:44:12.095296 progress 60 % (69 MB)
110 13:44:12.436980 progress 65 % (74 MB)
111 13:44:12.779274 progress 70 % (80 MB)
112 13:44:13.134349 progress 75 % (86 MB)
113 13:44:13.479913 progress 80 % (92 MB)
114 13:44:13.824268 progress 85 % (98 MB)
115 13:44:14.187308 progress 90 % (103 MB)
116 13:44:14.526975 progress 95 % (109 MB)
117 13:44:14.901323 progress 100 % (115 MB)
118 13:44:14.906674 115 MB downloaded in 6.56 s (17.57 MB/s)
119 13:44:14.906967 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:44:14.907267 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:44:14.907374 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:44:14.907503 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:44:14.907705 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:44:14.907782 saving as /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/modules/modules.tar
126 13:44:14.907864 total size: 8607916 (8 MB)
127 13:44:14.907968 Using unxz to decompress xz
128 13:44:14.912603 progress 0 % (0 MB)
129 13:44:14.933783 progress 5 % (0 MB)
130 13:44:14.958660 progress 10 % (0 MB)
131 13:44:14.984948 progress 15 % (1 MB)
132 13:44:15.009942 progress 20 % (1 MB)
133 13:44:15.035901 progress 25 % (2 MB)
134 13:44:15.061106 progress 30 % (2 MB)
135 13:44:15.084713 progress 35 % (2 MB)
136 13:44:15.110964 progress 40 % (3 MB)
137 13:44:15.136303 progress 45 % (3 MB)
138 13:44:15.161352 progress 50 % (4 MB)
139 13:44:15.187119 progress 55 % (4 MB)
140 13:44:15.212717 progress 60 % (4 MB)
141 13:44:15.236775 progress 65 % (5 MB)
142 13:44:15.265098 progress 70 % (5 MB)
143 13:44:15.295710 progress 75 % (6 MB)
144 13:44:15.319700 progress 80 % (6 MB)
145 13:44:15.344628 progress 85 % (7 MB)
146 13:44:15.369332 progress 90 % (7 MB)
147 13:44:15.399726 progress 95 % (7 MB)
148 13:44:15.428582 progress 100 % (8 MB)
149 13:44:15.434431 8 MB downloaded in 0.53 s (15.59 MB/s)
150 13:44:15.434693 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:44:15.434970 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:44:15.435062 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:44:15.435155 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:44:19.397131 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e
156 13:44:19.397321 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:44:19.397418 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 13:44:19.397592 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse
159 13:44:19.397722 makedir: /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin
160 13:44:19.397823 makedir: /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/tests
161 13:44:19.397919 makedir: /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/results
162 13:44:19.398017 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-add-keys
163 13:44:19.398155 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-add-sources
164 13:44:19.398283 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-background-process-start
165 13:44:19.398410 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-background-process-stop
166 13:44:19.398535 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-common-functions
167 13:44:19.398658 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-echo-ipv4
168 13:44:19.398781 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-install-packages
169 13:44:19.398904 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-installed-packages
170 13:44:19.399059 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-os-build
171 13:44:19.399182 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-probe-channel
172 13:44:19.399305 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-probe-ip
173 13:44:19.399427 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-target-ip
174 13:44:19.399551 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-target-mac
175 13:44:19.399674 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-target-storage
176 13:44:19.399800 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-case
177 13:44:19.399925 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-event
178 13:44:19.400047 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-feedback
179 13:44:19.400169 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-raise
180 13:44:19.400292 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-reference
181 13:44:19.400462 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-runner
182 13:44:19.400585 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-set
183 13:44:19.400710 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-test-shell
184 13:44:19.400834 Updating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-add-keys (debian)
185 13:44:19.400982 Updating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-add-sources (debian)
186 13:44:19.401119 Updating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-install-packages (debian)
187 13:44:19.401255 Updating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-installed-packages (debian)
188 13:44:19.401389 Updating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/bin/lava-os-build (debian)
189 13:44:19.401507 Creating /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/environment
190 13:44:19.401602 LAVA metadata
191 13:44:19.401666 - LAVA_JOB_ID=14063055
192 13:44:19.401726 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:44:19.401824 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 13:44:19.401899 skipped lava-vland-overlay
195 13:44:19.401972 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:44:19.402051 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 13:44:19.402111 skipped lava-multinode-overlay
198 13:44:19.402182 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:44:19.402258 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 13:44:19.402329 Loading test definitions
201 13:44:19.402415 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 13:44:19.402483 Using /lava-14063055 at stage 0
203 13:44:19.402763 uuid=14063055_1.6.2.3.1 testdef=None
204 13:44:19.402850 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:44:19.402933 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 13:44:19.403390 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:44:19.403603 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 13:44:19.404150 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:44:19.404422 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 13:44:19.404995 runner path: /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/0/tests/0_timesync-off test_uuid 14063055_1.6.2.3.1
213 13:44:19.405151 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:44:19.405465 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 13:44:19.405538 Using /lava-14063055 at stage 0
217 13:44:19.405637 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:44:19.405722 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/0/tests/1_kselftest-alsa'
219 13:44:21.480042 Running '/usr/bin/git checkout kernelci.org
220 13:44:21.630726 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 13:44:21.631450 uuid=14063055_1.6.2.3.5 testdef=None
222 13:44:21.631620 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 13:44:21.631863 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 13:44:21.632656 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:44:21.632892 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 13:44:21.633889 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:44:21.634130 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 13:44:21.635140 runner path: /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/0/tests/1_kselftest-alsa test_uuid 14063055_1.6.2.3.5
232 13:44:21.635234 BOARD='mt8192-asurada-spherion-r0'
233 13:44:21.635299 BRANCH='cip'
234 13:44:21.635359 SKIPFILE='/dev/null'
235 13:44:21.635419 SKIP_INSTALL='True'
236 13:44:21.635495 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:44:21.635556 TST_CASENAME=''
238 13:44:21.635611 TST_CMDFILES='alsa'
239 13:44:21.635751 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:44:21.635957 Creating lava-test-runner.conf files
242 13:44:21.636023 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063055/lava-overlay-wouhupse/lava-14063055/0 for stage 0
243 13:44:21.636147 - 0_timesync-off
244 13:44:21.636247 - 1_kselftest-alsa
245 13:44:21.636409 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 13:44:21.636499 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 13:44:29.362452 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:44:29.362614 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 13:44:29.362712 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:44:29.362812 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 13:44:29.362928 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 13:44:29.534531 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:44:29.534920 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 13:44:29.535038 extracting modules file /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e
255 13:44:29.765564 extracting modules file /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063055/extract-overlay-ramdisk-77ajc50l/ramdisk
256 13:44:29.991721 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:44:29.991896 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 13:44:29.991996 [common] Applying overlay to NFS
259 13:44:29.992068 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063055/compress-overlay-53ccxfrb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e
260 13:44:30.968885 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:44:30.969084 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 13:44:30.969220 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:44:30.969338 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 13:44:30.969444 Building ramdisk /var/lib/lava/dispatcher/tmp/14063055/extract-overlay-ramdisk-77ajc50l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063055/extract-overlay-ramdisk-77ajc50l/ramdisk
265 13:44:31.323272 >> 130335 blocks
266 13:44:33.510457 rename /var/lib/lava/dispatcher/tmp/14063055/extract-overlay-ramdisk-77ajc50l/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/ramdisk/ramdisk.cpio.gz
267 13:44:33.510907 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 13:44:33.511046 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 13:44:33.511146 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 13:44:33.511266 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/kernel/Image']
271 13:44:47.818821 Returned 0 in 14 seconds
272 13:44:47.919431 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/kernel/image.itb
273 13:44:48.294293 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:44:48.294692 output: Created: Tue May 28 14:44:48 2024
275 13:44:48.294770 output: Image 0 (kernel-1)
276 13:44:48.294837 output: Description:
277 13:44:48.294900 output: Created: Tue May 28 14:44:48 2024
278 13:44:48.294960 output: Type: Kernel Image
279 13:44:48.295022 output: Compression: lzma compressed
280 13:44:48.295080 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
281 13:44:48.295137 output: Architecture: AArch64
282 13:44:48.295193 output: OS: Linux
283 13:44:48.295249 output: Load Address: 0x00000000
284 13:44:48.295304 output: Entry Point: 0x00000000
285 13:44:48.295358 output: Hash algo: crc32
286 13:44:48.295412 output: Hash value: 0578ee26
287 13:44:48.295467 output: Image 1 (fdt-1)
288 13:44:48.295522 output: Description: mt8192-asurada-spherion-r0
289 13:44:48.295577 output: Created: Tue May 28 14:44:48 2024
290 13:44:48.295733 output: Type: Flat Device Tree
291 13:44:48.295851 output: Compression: uncompressed
292 13:44:48.295939 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:44:48.296030 output: Architecture: AArch64
294 13:44:48.296121 output: Hash algo: crc32
295 13:44:48.296205 output: Hash value: 0f8e4d2e
296 13:44:48.296299 output: Image 2 (ramdisk-1)
297 13:44:48.296449 output: Description: unavailable
298 13:44:48.296558 output: Created: Tue May 28 14:44:48 2024
299 13:44:48.296645 output: Type: RAMDisk Image
300 13:44:48.296733 output: Compression: Unknown Compression
301 13:44:48.296818 output: Data Size: 18731685 Bytes = 18292.66 KiB = 17.86 MiB
302 13:44:48.296878 output: Architecture: AArch64
303 13:44:48.296934 output: OS: Linux
304 13:44:48.296989 output: Load Address: unavailable
305 13:44:48.297043 output: Entry Point: unavailable
306 13:44:48.297096 output: Hash algo: crc32
307 13:44:48.297149 output: Hash value: 3c72cac8
308 13:44:48.297202 output: Default Configuration: 'conf-1'
309 13:44:48.297255 output: Configuration 0 (conf-1)
310 13:44:48.297307 output: Description: mt8192-asurada-spherion-r0
311 13:44:48.297360 output: Kernel: kernel-1
312 13:44:48.297411 output: Init Ramdisk: ramdisk-1
313 13:44:48.297464 output: FDT: fdt-1
314 13:44:48.297515 output: Loadables: kernel-1
315 13:44:48.297567 output:
316 13:44:48.297775 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 13:44:48.297874 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 13:44:48.297985 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 13:44:48.298074 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 13:44:48.298150 No LXC device requested
321 13:44:48.298227 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:44:48.298314 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 13:44:48.298391 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:44:48.298491 Checking files for TFTP limit of 4294967296 bytes.
325 13:44:48.298985 end: 1 tftp-deploy (duration 00:00:40) [common]
326 13:44:48.299095 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:44:48.299187 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:44:48.299310 substitutions:
329 13:44:48.299382 - {DTB}: 14063055/tftp-deploy-2ustgt69/dtb/mt8192-asurada-spherion-r0.dtb
330 13:44:48.299447 - {INITRD}: 14063055/tftp-deploy-2ustgt69/ramdisk/ramdisk.cpio.gz
331 13:44:48.299506 - {KERNEL}: 14063055/tftp-deploy-2ustgt69/kernel/Image
332 13:44:48.299563 - {LAVA_MAC}: None
333 13:44:48.299618 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e
334 13:44:48.299673 - {NFS_SERVER_IP}: 192.168.201.1
335 13:44:48.299727 - {PRESEED_CONFIG}: None
336 13:44:48.299780 - {PRESEED_LOCAL}: None
337 13:44:48.299833 - {RAMDISK}: 14063055/tftp-deploy-2ustgt69/ramdisk/ramdisk.cpio.gz
338 13:44:48.299886 - {ROOT_PART}: None
339 13:44:48.299939 - {ROOT}: None
340 13:44:48.299992 - {SERVER_IP}: 192.168.201.1
341 13:44:48.300044 - {TEE}: None
342 13:44:48.300097 Parsed boot commands:
343 13:44:48.300149 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:44:48.300326 Parsed boot commands: tftpboot 192.168.201.1 14063055/tftp-deploy-2ustgt69/kernel/image.itb 14063055/tftp-deploy-2ustgt69/kernel/cmdline
345 13:44:48.300452 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:44:48.300539 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:44:48.300633 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:44:48.300716 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:44:48.300787 Not connected, no need to disconnect.
350 13:44:48.300859 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:44:48.300943 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:44:48.301008 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 13:44:48.304897 Setting prompt string to ['lava-test: # ']
354 13:44:48.305292 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:44:48.305411 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:44:48.305509 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:44:48.305594 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:44:48.305794 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 13:44:53.440172 >> Command sent successfully.
360 13:44:53.442508 Returned 0 in 5 seconds
361 13:44:53.542914 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 13:44:53.543258 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 13:44:53.543359 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 13:44:53.543450 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:44:53.543519 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:44:53.543586 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:44:53.544005 [Enter `^Ec?' for help]
369 13:44:53.716528
370 13:44:53.716698
371 13:44:53.716804 F0: 102B 0000
372 13:44:53.716897
373 13:44:53.716995 F3: 1001 0000 [0200]
374 13:44:53.719830
375 13:44:53.719900 F3: 1001 0000
376 13:44:53.719962
377 13:44:53.720025 F7: 102D 0000
378 13:44:53.720082
379 13:44:53.723279 F1: 0000 0000
380 13:44:53.723360
381 13:44:53.723426 V0: 0000 0000 [0001]
382 13:44:53.723486
383 13:44:53.726612 00: 0007 8000
384 13:44:53.726691
385 13:44:53.726751 01: 0000 0000
386 13:44:53.726816
387 13:44:53.729730 BP: 0C00 0209 [0000]
388 13:44:53.729830
389 13:44:53.729896 G0: 1182 0000
390 13:44:53.729957
391 13:44:53.733418 EC: 0000 0021 [4000]
392 13:44:53.733490
393 13:44:53.733554 S7: 0000 0000 [0000]
394 13:44:53.733614
395 13:44:53.736886 CC: 0000 0000 [0001]
396 13:44:53.736961
397 13:44:53.737022 T0: 0000 0040 [010F]
398 13:44:53.737088
399 13:44:53.737148 Jump to BL
400 13:44:53.737204
401 13:44:53.763928
402 13:44:53.764038
403 13:44:53.771513 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 13:44:53.775224 ARM64: Exception handlers installed.
405 13:44:53.778704 ARM64: Testing exception
406 13:44:53.782070 ARM64: Done test exception
407 13:44:53.788605 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 13:44:53.799225 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 13:44:53.805344 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 13:44:53.815770 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 13:44:53.822204 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 13:44:53.829230 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 13:44:53.840660 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 13:44:53.847028 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 13:44:53.866284 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 13:44:53.869729 WDT: Last reset was cold boot
417 13:44:53.872944 SPI1(PAD0) initialized at 2873684 Hz
418 13:44:53.876246 SPI5(PAD0) initialized at 992727 Hz
419 13:44:53.879965 VBOOT: Loading verstage.
420 13:44:53.887151 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 13:44:53.890469 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 13:44:53.894326 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 13:44:53.897245 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 13:44:53.904491 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 13:44:53.910737 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 13:44:53.922352 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 13:44:53.922447
428 13:44:53.922514
429 13:44:53.932423 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 13:44:53.935250 ARM64: Exception handlers installed.
431 13:44:53.935329 ARM64: Testing exception
432 13:44:53.938833 ARM64: Done test exception
433 13:44:53.942275 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 13:44:53.948724 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 13:44:53.962177 Probing TPM: . done!
436 13:44:53.962252 TPM ready after 0 ms
437 13:44:53.970011 Connected to device vid:did:rid of 1ae0:0028:00
438 13:44:53.976526 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 13:44:54.033916 Initialized TPM device CR50 revision 0
440 13:44:54.045886 tlcl_send_startup: Startup return code is 0
441 13:44:54.045984 TPM: setup succeeded
442 13:44:54.057335 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 13:44:54.066010 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:44:54.078475 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 13:44:54.088749 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 13:44:54.092321 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 13:44:54.095987 in-header: 03 07 00 00 08 00 00 00
448 13:44:54.100143 in-data: aa e4 47 04 13 02 00 00
449 13:44:54.100258 Chrome EC: UHEPI supported
450 13:44:54.106472 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 13:44:54.110659 in-header: 03 95 00 00 08 00 00 00
452 13:44:54.114299 in-data: 18 20 20 08 00 00 00 00
453 13:44:54.114401 Phase 1
454 13:44:54.118526 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 13:44:54.125745 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 13:44:54.133040 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 13:44:54.133163 Recovery requested (1009000e)
458 13:44:54.144250 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 13:44:54.149206 tlcl_extend: response is 0
460 13:44:54.159549 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 13:44:54.164564 tlcl_extend: response is 0
462 13:44:54.171279 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 13:44:54.191350 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 13:44:54.198122 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 13:44:54.198210
466 13:44:54.198275
467 13:44:54.208193 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 13:44:54.211153 ARM64: Exception handlers installed.
469 13:44:54.214651 ARM64: Testing exception
470 13:44:54.214734 ARM64: Done test exception
471 13:44:54.236214 pmic_efuse_setting: Set efuses in 11 msecs
472 13:44:54.239732 pmwrap_interface_init: Select PMIF_VLD_RDY
473 13:44:54.246691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 13:44:54.250014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 13:44:54.257180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 13:44:54.260725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 13:44:54.265057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 13:44:54.268498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 13:44:54.275919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 13:44:54.279171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 13:44:54.282818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 13:44:54.290034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 13:44:54.294078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 13:44:54.297515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 13:44:54.301005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 13:44:54.309397 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 13:44:54.312949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 13:44:54.320643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 13:44:54.327924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 13:44:54.331506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 13:44:54.339335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 13:44:54.342484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 13:44:54.350203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 13:44:54.353698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 13:44:54.361257 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 13:44:54.364791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 13:44:54.369140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 13:44:54.376483 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 13:44:54.380015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 13:44:54.387145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 13:44:54.390501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 13:44:54.394645 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 13:44:54.401899 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 13:44:54.405689 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 13:44:54.409448 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 13:44:54.416470 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 13:44:54.420202 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 13:44:54.427641 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 13:44:54.430876 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 13:44:54.434456 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 13:44:54.441817 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 13:44:54.445347 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 13:44:54.449321 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 13:44:54.452665 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 13:44:54.456322 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 13:44:54.464082 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 13:44:54.467512 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 13:44:54.471441 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 13:44:54.475059 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 13:44:54.478652 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 13:44:54.482201 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 13:44:54.486359 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 13:44:54.493008 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 13:44:54.500837 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 13:44:54.508026 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 13:44:54.511577 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 13:44:54.522914 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 13:44:54.529718 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 13:44:54.533238 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 13:44:54.537466 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 13:44:54.541017 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:44:54.549988 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x14
533 13:44:54.553855 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 13:44:54.558796 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 13:44:54.565450 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 13:44:54.573990 [RTC]rtc_get_frequency_meter,154: input=15, output=759
537 13:44:54.583469 [RTC]rtc_get_frequency_meter,154: input=23, output=942
538 13:44:54.593478 [RTC]rtc_get_frequency_meter,154: input=19, output=850
539 13:44:54.602855 [RTC]rtc_get_frequency_meter,154: input=17, output=804
540 13:44:54.612124 [RTC]rtc_get_frequency_meter,154: input=16, output=782
541 13:44:54.621831 [RTC]rtc_get_frequency_meter,154: input=16, output=780
542 13:44:54.631807 [RTC]rtc_get_frequency_meter,154: input=17, output=804
543 13:44:54.635358 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 13:44:54.638926 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
545 13:44:54.643253 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 13:44:54.650446 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 13:44:54.653816 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 13:44:54.657615 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 13:44:54.661450 ADC[4]: Raw value=906573 ID=7
550 13:44:54.661543 ADC[3]: Raw value=213441 ID=1
551 13:44:54.665285 RAM Code: 0x71
552 13:44:54.669157 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 13:44:54.672748 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 13:44:54.684035 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 13:44:54.687649 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 13:44:54.691316 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 13:44:54.695812 in-header: 03 07 00 00 08 00 00 00
558 13:44:54.699967 in-data: aa e4 47 04 13 02 00 00
559 13:44:54.704064 Chrome EC: UHEPI supported
560 13:44:54.707611 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 13:44:54.711187 in-header: 03 95 00 00 08 00 00 00
562 13:44:54.714801 in-data: 18 20 20 08 00 00 00 00
563 13:44:54.719130 MRC: failed to locate region type 0.
564 13:44:54.726166 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 13:44:54.729820 DRAM-K: Running full calibration
566 13:44:54.734095 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 13:44:54.737768 header.status = 0x0
568 13:44:54.741412 header.version = 0x6 (expected: 0x6)
569 13:44:54.744941 header.size = 0xd00 (expected: 0xd00)
570 13:44:54.745028 header.flags = 0x0
571 13:44:54.752329 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 13:44:54.769972 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
573 13:44:54.776993 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 13:44:54.777081 dram_init: ddr_geometry: 2
575 13:44:54.781118 [EMI] MDL number = 2
576 13:44:54.781205 [EMI] Get MDL freq = 0
577 13:44:54.784480 dram_init: ddr_type: 0
578 13:44:54.788234 is_discrete_lpddr4: 1
579 13:44:54.788320 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 13:44:54.788446
581 13:44:54.792201
582 13:44:54.792287 [Bian_co] ETT version 0.0.0.1
583 13:44:54.795570 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 13:44:54.799607
585 13:44:54.803544 dramc_set_vcore_voltage set vcore to 650000
586 13:44:54.803629 Read voltage for 800, 4
587 13:44:54.803717 Vio18 = 0
588 13:44:54.806743 Vcore = 650000
589 13:44:54.806862 Vdram = 0
590 13:44:54.806949 Vddq = 0
591 13:44:54.810363 Vmddr = 0
592 13:44:54.810448 dram_init: config_dvfs: 1
593 13:44:54.814197 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 13:44:54.821908 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 13:44:54.825972 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
596 13:44:54.829465 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
597 13:44:54.833711 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 13:44:54.837277 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 13:44:54.840166 MEM_TYPE=3, freq_sel=18
600 13:44:54.840252 sv_algorithm_assistance_LP4_1600
601 13:44:54.846685 ============ PULL DRAM RESETB DOWN ============
602 13:44:54.850239 ========== PULL DRAM RESETB DOWN end =========
603 13:44:54.853823 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 13:44:54.857408 ===================================
605 13:44:54.861030 LPDDR4 DRAM CONFIGURATION
606 13:44:54.864610 ===================================
607 13:44:54.864697 EX_ROW_EN[0] = 0x0
608 13:44:54.868132 EX_ROW_EN[1] = 0x0
609 13:44:54.868219 LP4Y_EN = 0x0
610 13:44:54.871786 WORK_FSP = 0x0
611 13:44:54.871873 WL = 0x2
612 13:44:54.875339 RL = 0x2
613 13:44:54.875425 BL = 0x2
614 13:44:54.878924 RPST = 0x0
615 13:44:54.879011 RD_PRE = 0x0
616 13:44:54.882921 WR_PRE = 0x1
617 13:44:54.883008 WR_PST = 0x0
618 13:44:54.885742 DBI_WR = 0x0
619 13:44:54.885828 DBI_RD = 0x0
620 13:44:54.889293 OTF = 0x1
621 13:44:54.892843 ===================================
622 13:44:54.896144 ===================================
623 13:44:54.896231 ANA top config
624 13:44:54.899629 ===================================
625 13:44:54.902832 DLL_ASYNC_EN = 0
626 13:44:54.905838 ALL_SLAVE_EN = 1
627 13:44:54.905925 NEW_RANK_MODE = 1
628 13:44:54.909363 DLL_IDLE_MODE = 1
629 13:44:54.912997 LP45_APHY_COMB_EN = 1
630 13:44:54.916551 TX_ODT_DIS = 1
631 13:44:54.916638 NEW_8X_MODE = 1
632 13:44:54.920179 ===================================
633 13:44:54.923559 ===================================
634 13:44:54.926797 data_rate = 1600
635 13:44:54.930024 CKR = 1
636 13:44:54.933884 DQ_P2S_RATIO = 8
637 13:44:54.936799 ===================================
638 13:44:54.939979 CA_P2S_RATIO = 8
639 13:44:54.940072 DQ_CA_OPEN = 0
640 13:44:54.943718 DQ_SEMI_OPEN = 0
641 13:44:54.947080 CA_SEMI_OPEN = 0
642 13:44:54.950131 CA_FULL_RATE = 0
643 13:44:54.953379 DQ_CKDIV4_EN = 1
644 13:44:54.957045 CA_CKDIV4_EN = 1
645 13:44:54.957124 CA_PREDIV_EN = 0
646 13:44:54.960632 PH8_DLY = 0
647 13:44:54.963577 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 13:44:54.967157 DQ_AAMCK_DIV = 4
649 13:44:54.970042 CA_AAMCK_DIV = 4
650 13:44:54.973651 CA_ADMCK_DIV = 4
651 13:44:54.973721 DQ_TRACK_CA_EN = 0
652 13:44:54.976631 CA_PICK = 800
653 13:44:54.980156 CA_MCKIO = 800
654 13:44:54.983830 MCKIO_SEMI = 0
655 13:44:54.987363 PLL_FREQ = 3068
656 13:44:54.987441 DQ_UI_PI_RATIO = 32
657 13:44:54.990820 CA_UI_PI_RATIO = 0
658 13:44:54.994984 ===================================
659 13:44:54.999371 ===================================
660 13:44:55.002691 memory_type:LPDDR4
661 13:44:55.002772 GP_NUM : 10
662 13:44:55.006261 SRAM_EN : 1
663 13:44:55.006337 MD32_EN : 0
664 13:44:55.010421 ===================================
665 13:44:55.014603 [ANA_INIT] >>>>>>>>>>>>>>
666 13:44:55.014712 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 13:44:55.017790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 13:44:55.021294 ===================================
669 13:44:55.024845 data_rate = 1600,PCW = 0X7600
670 13:44:55.028475 ===================================
671 13:44:55.031245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 13:44:55.038465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 13:44:55.041286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:44:55.048317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 13:44:55.051468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 13:44:55.054665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:44:55.054752 [ANA_INIT] flow start
678 13:44:55.058212 [ANA_INIT] PLL >>>>>>>>
679 13:44:55.061832 [ANA_INIT] PLL <<<<<<<<
680 13:44:55.061919 [ANA_INIT] MIDPI >>>>>>>>
681 13:44:55.064788 [ANA_INIT] MIDPI <<<<<<<<
682 13:44:55.068220 [ANA_INIT] DLL >>>>>>>>
683 13:44:55.068308 [ANA_INIT] flow end
684 13:44:55.074607 ============ LP4 DIFF to SE enter ============
685 13:44:55.078118 ============ LP4 DIFF to SE exit ============
686 13:44:55.081646 [ANA_INIT] <<<<<<<<<<<<<
687 13:44:55.084633 [Flow] Enable top DCM control >>>>>
688 13:44:55.088043 [Flow] Enable top DCM control <<<<<
689 13:44:55.088122 Enable DLL master slave shuffle
690 13:44:55.094639 ==============================================================
691 13:44:55.098162 Gating Mode config
692 13:44:55.101669 ==============================================================
693 13:44:55.104365 Config description:
694 13:44:55.114925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 13:44:55.121043 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 13:44:55.124499 SELPH_MODE 0: By rank 1: By Phase
697 13:44:55.131370 ==============================================================
698 13:44:55.134889 GAT_TRACK_EN = 1
699 13:44:55.137783 RX_GATING_MODE = 2
700 13:44:55.141362 RX_GATING_TRACK_MODE = 2
701 13:44:55.144911 SELPH_MODE = 1
702 13:44:55.144982 PICG_EARLY_EN = 1
703 13:44:55.147660 VALID_LAT_VALUE = 1
704 13:44:55.154910 ==============================================================
705 13:44:55.157682 Enter into Gating configuration >>>>
706 13:44:55.161161 Exit from Gating configuration <<<<
707 13:44:55.164785 Enter into DVFS_PRE_config >>>>>
708 13:44:55.174691 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 13:44:55.178109 Exit from DVFS_PRE_config <<<<<
710 13:44:55.181324 Enter into PICG configuration >>>>
711 13:44:55.184320 Exit from PICG configuration <<<<
712 13:44:55.188103 [RX_INPUT] configuration >>>>>
713 13:44:55.191578 [RX_INPUT] configuration <<<<<
714 13:44:55.194820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 13:44:55.201112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 13:44:55.208294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 13:44:55.214606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 13:44:55.221325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 13:44:55.224946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 13:44:55.228213 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 13:44:55.234864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 13:44:55.238272 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 13:44:55.241543 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 13:44:55.244895 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 13:44:55.251298 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 13:44:55.254933 ===================================
727 13:44:55.255017 LPDDR4 DRAM CONFIGURATION
728 13:44:55.258427 ===================================
729 13:44:55.261363 EX_ROW_EN[0] = 0x0
730 13:44:55.264910 EX_ROW_EN[1] = 0x0
731 13:44:55.264993 LP4Y_EN = 0x0
732 13:44:55.268160 WORK_FSP = 0x0
733 13:44:55.268243 WL = 0x2
734 13:44:55.271650 RL = 0x2
735 13:44:55.271734 BL = 0x2
736 13:44:55.274633 RPST = 0x0
737 13:44:55.274716 RD_PRE = 0x0
738 13:44:55.278290 WR_PRE = 0x1
739 13:44:55.278373 WR_PST = 0x0
740 13:44:55.281829 DBI_WR = 0x0
741 13:44:55.281912 DBI_RD = 0x0
742 13:44:55.284759 OTF = 0x1
743 13:44:55.288360 ===================================
744 13:44:55.291847 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 13:44:55.295113 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 13:44:55.301441 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 13:44:55.304670 ===================================
748 13:44:55.304754 LPDDR4 DRAM CONFIGURATION
749 13:44:55.307962 ===================================
750 13:44:55.311758 EX_ROW_EN[0] = 0x10
751 13:44:55.311841 EX_ROW_EN[1] = 0x0
752 13:44:55.314964 LP4Y_EN = 0x0
753 13:44:55.318513 WORK_FSP = 0x0
754 13:44:55.318597 WL = 0x2
755 13:44:55.321429 RL = 0x2
756 13:44:55.321511 BL = 0x2
757 13:44:55.325036 RPST = 0x0
758 13:44:55.325118 RD_PRE = 0x0
759 13:44:55.328491 WR_PRE = 0x1
760 13:44:55.328574 WR_PST = 0x0
761 13:44:55.331998 DBI_WR = 0x0
762 13:44:55.332081 DBI_RD = 0x0
763 13:44:55.335363 OTF = 0x1
764 13:44:55.338408 ===================================
765 13:44:55.341519 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 13:44:55.347268 nWR fixed to 40
767 13:44:55.350380 [ModeRegInit_LP4] CH0 RK0
768 13:44:55.350457 [ModeRegInit_LP4] CH0 RK1
769 13:44:55.353491 [ModeRegInit_LP4] CH1 RK0
770 13:44:55.357332 [ModeRegInit_LP4] CH1 RK1
771 13:44:55.357415 match AC timing 13
772 13:44:55.363592 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 13:44:55.367133 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 13:44:55.370771 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 13:44:55.377028 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 13:44:55.380681 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 13:44:55.380764 [EMI DOE] emi_dcm 0
778 13:44:55.387400 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 13:44:55.387484 ==
780 13:44:55.390346 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:44:55.393913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 13:44:55.394004 ==
783 13:44:55.400764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 13:44:55.404277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 13:44:55.414612 [CA 0] Center 36 (6~67) winsize 62
786 13:44:55.418113 [CA 1] Center 36 (6~67) winsize 62
787 13:44:55.420999 [CA 2] Center 34 (4~65) winsize 62
788 13:44:55.424276 [CA 3] Center 33 (3~64) winsize 62
789 13:44:55.427479 [CA 4] Center 33 (3~63) winsize 61
790 13:44:55.430951 [CA 5] Center 32 (3~62) winsize 60
791 13:44:55.431062
792 13:44:55.434512 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 13:44:55.434600
794 13:44:55.438202 [CATrainingPosCal] consider 1 rank data
795 13:44:55.440976 u2DelayCellTimex100 = 270/100 ps
796 13:44:55.444643 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
797 13:44:55.448185 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
798 13:44:55.454729 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
799 13:44:55.457945 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
800 13:44:55.461367 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
801 13:44:55.464800 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
802 13:44:55.464910
803 13:44:55.468142 CA PerBit enable=1, Macro0, CA PI delay=32
804 13:44:55.468232
805 13:44:55.471462 [CBTSetCACLKResult] CA Dly = 32
806 13:44:55.471567 CS Dly: 4 (0~35)
807 13:44:55.471667 ==
808 13:44:55.474469 Dram Type= 6, Freq= 0, CH_0, rank 1
809 13:44:55.481585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 13:44:55.481674 ==
811 13:44:55.485263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 13:44:55.490925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 13:44:55.500982 [CA 0] Center 36 (6~67) winsize 62
814 13:44:55.504029 [CA 1] Center 36 (6~67) winsize 62
815 13:44:55.507592 [CA 2] Center 34 (4~65) winsize 62
816 13:44:55.511168 [CA 3] Center 33 (3~64) winsize 62
817 13:44:55.513927 [CA 4] Center 32 (2~63) winsize 62
818 13:44:55.517319 [CA 5] Center 32 (2~63) winsize 62
819 13:44:55.517447
820 13:44:55.520505 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 13:44:55.520646
822 13:44:55.524132 [CATrainingPosCal] consider 2 rank data
823 13:44:55.527510 u2DelayCellTimex100 = 270/100 ps
824 13:44:55.530618 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
825 13:44:55.534131 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
826 13:44:55.540968 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
827 13:44:55.545010 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
828 13:44:55.547717 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
829 13:44:55.551320 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
830 13:44:55.551728
831 13:44:55.554524 CA PerBit enable=1, Macro0, CA PI delay=32
832 13:44:55.555069
833 13:44:55.557786 [CBTSetCACLKResult] CA Dly = 32
834 13:44:55.558226 CS Dly: 5 (0~37)
835 13:44:55.558669
836 13:44:55.561540 ----->DramcWriteLeveling(PI) begin...
837 13:44:55.565426 ==
838 13:44:55.565871 Dram Type= 6, Freq= 0, CH_0, rank 0
839 13:44:55.568881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 13:44:55.572420 ==
841 13:44:55.573019 Write leveling (Byte 0): 35 => 35
842 13:44:55.576018 Write leveling (Byte 1): 28 => 28
843 13:44:55.579514 DramcWriteLeveling(PI) end<-----
844 13:44:55.579954
845 13:44:55.580425 ==
846 13:44:55.582723 Dram Type= 6, Freq= 0, CH_0, rank 0
847 13:44:55.586700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 13:44:55.587145 ==
849 13:44:55.589873 [Gating] SW mode calibration
850 13:44:55.597156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 13:44:55.603665 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 13:44:55.607209 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 13:44:55.609988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 13:44:55.617123 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 13:44:55.620624 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:44:55.623352 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:44:55.629959 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:44:55.633922 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:44:55.636820 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:44:55.643893 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:44:55.647435 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:44:55.650267 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:44:55.654227 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:44:55.660206 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:44:55.663721 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:44:55.667260 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:44:55.673729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:44:55.677019 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 13:44:55.680679 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 13:44:55.686900 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
871 13:44:55.690362 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:44:55.693841 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:44:55.700242 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:44:55.703517 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:44:55.707383 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:44:55.713912 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:44:55.717077 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:44:55.720234 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
879 13:44:55.727339 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
880 13:44:55.730920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 13:44:55.733718 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:44:55.737234 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 13:44:55.743641 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 13:44:55.747337 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 13:44:55.750117 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
886 13:44:55.757111 0 10 8 | B1->B0 | 2f2f 2828 | 0 0 | (1 0) (0 0)
887 13:44:55.760737 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:44:55.763577 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 13:44:55.770821 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:44:55.773734 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 13:44:55.776901 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 13:44:55.783556 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 13:44:55.787123 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
894 13:44:55.790643 0 11 8 | B1->B0 | 2929 4242 | 0 1 | (0 0) (0 0)
895 13:44:55.797086 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
896 13:44:55.800685 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 13:44:55.804279 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:44:55.810560 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 13:44:55.814102 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 13:44:55.817542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 13:44:55.820407 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 13:44:55.827833 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 13:44:55.830474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 13:44:55.834256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:44:55.840939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:44:55.843762 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:44:55.847275 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:44:55.854216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:44:55.856897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:44:55.860776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:44:55.867079 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:44:55.870529 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:44:55.874240 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:44:55.880433 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 13:44:55.883484 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 13:44:55.887349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 13:44:55.893945 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 13:44:55.897300 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 13:44:55.900429 Total UI for P1: 0, mck2ui 16
920 13:44:55.903591 best dqsien dly found for B0: ( 0, 14, 6)
921 13:44:55.906943 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 13:44:55.910705 Total UI for P1: 0, mck2ui 16
923 13:44:55.914314 best dqsien dly found for B1: ( 0, 14, 8)
924 13:44:55.917843 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 13:44:55.921285 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 13:44:55.921718
927 13:44:55.924832 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 13:44:55.927753 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 13:44:55.931278 [Gating] SW calibration Done
930 13:44:55.931710 ==
931 13:44:55.934973 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:44:55.937928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:44:55.938361 ==
934 13:44:55.941646 RX Vref Scan: 0
935 13:44:55.942072
936 13:44:55.944704 RX Vref 0 -> 0, step: 1
937 13:44:55.945147
938 13:44:55.945517 RX Delay -130 -> 252, step: 16
939 13:44:55.951853 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
940 13:44:55.954528 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
941 13:44:55.958150 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
942 13:44:55.961102 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
943 13:44:55.964562 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
944 13:44:55.971169 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
945 13:44:55.974906 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
946 13:44:55.977671 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
947 13:44:55.981182 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
948 13:44:55.984930 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
949 13:44:55.991642 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
950 13:44:55.994750 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
951 13:44:55.998037 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
952 13:44:56.001137 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
953 13:44:56.004893 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
954 13:44:56.011712 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
955 13:44:56.012222 ==
956 13:44:56.014939 Dram Type= 6, Freq= 0, CH_0, rank 0
957 13:44:56.018041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 13:44:56.018471 ==
959 13:44:56.018810 DQS Delay:
960 13:44:56.021806 DQS0 = 0, DQS1 = 0
961 13:44:56.022333 DQM Delay:
962 13:44:56.024907 DQM0 = 88, DQM1 = 82
963 13:44:56.025494 DQ Delay:
964 13:44:56.028237 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
965 13:44:56.031808 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
966 13:44:56.035343 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
967 13:44:56.038447 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
968 13:44:56.038973
969 13:44:56.039311
970 13:44:56.039625 ==
971 13:44:56.041810 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:44:56.044683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:44:56.045115 ==
974 13:44:56.045517
975 13:44:56.045840
976 13:44:56.048229 TX Vref Scan disable
977 13:44:56.051623 == TX Byte 0 ==
978 13:44:56.054978 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
979 13:44:56.058231 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
980 13:44:56.061465 == TX Byte 1 ==
981 13:44:56.065046 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
982 13:44:56.068710 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
983 13:44:56.069142 ==
984 13:44:56.071561 Dram Type= 6, Freq= 0, CH_0, rank 0
985 13:44:56.077968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 13:44:56.078433 ==
987 13:44:56.090944 TX Vref=22, minBit 14, minWin=27, winSum=450
988 13:44:56.094067 TX Vref=24, minBit 9, minWin=27, winSum=451
989 13:44:56.097552 TX Vref=26, minBit 8, minWin=27, winSum=453
990 13:44:56.100453 TX Vref=28, minBit 9, minWin=28, winSum=459
991 13:44:56.104137 TX Vref=30, minBit 7, minWin=28, winSum=459
992 13:44:56.110939 TX Vref=32, minBit 8, minWin=27, winSum=452
993 13:44:56.114128 [TxChooseVref] Worse bit 9, Min win 28, Win sum 459, Final Vref 28
994 13:44:56.114746
995 13:44:56.117691 Final TX Range 1 Vref 28
996 13:44:56.118122
997 13:44:56.118460 ==
998 13:44:56.120446 Dram Type= 6, Freq= 0, CH_0, rank 0
999 13:44:56.123934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 13:44:56.124428 ==
1001 13:44:56.124781
1002 13:44:56.127312
1003 13:44:56.127736 TX Vref Scan disable
1004 13:44:56.130493 == TX Byte 0 ==
1005 13:44:56.133802 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1006 13:44:56.137123 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1007 13:44:56.140604 == TX Byte 1 ==
1008 13:44:56.143771 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1009 13:44:56.147000 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1010 13:44:56.150273
1011 13:44:56.150549 [DATLAT]
1012 13:44:56.150738 Freq=800, CH0 RK0
1013 13:44:56.150911
1014 13:44:56.153878 DATLAT Default: 0xa
1015 13:44:56.154107 0, 0xFFFF, sum = 0
1016 13:44:56.157460 1, 0xFFFF, sum = 0
1017 13:44:56.157693 2, 0xFFFF, sum = 0
1018 13:44:56.161015 3, 0xFFFF, sum = 0
1019 13:44:56.161251 4, 0xFFFF, sum = 0
1020 13:44:56.163838 5, 0xFFFF, sum = 0
1021 13:44:56.164073 6, 0xFFFF, sum = 0
1022 13:44:56.167334 7, 0xFFFF, sum = 0
1023 13:44:56.167567 8, 0xFFFF, sum = 0
1024 13:44:56.170767 9, 0x0, sum = 1
1025 13:44:56.171074 10, 0x0, sum = 2
1026 13:44:56.173839 11, 0x0, sum = 3
1027 13:44:56.174205 12, 0x0, sum = 4
1028 13:44:56.177592 best_step = 10
1029 13:44:56.178052
1030 13:44:56.178348 ==
1031 13:44:56.181138 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 13:44:56.183966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 13:44:56.184524 ==
1034 13:44:56.187632 RX Vref Scan: 1
1035 13:44:56.188056
1036 13:44:56.188439 Set Vref Range= 32 -> 127
1037 13:44:56.188759
1038 13:44:56.191167 RX Vref 32 -> 127, step: 1
1039 13:44:56.191590
1040 13:44:56.194525 RX Delay -79 -> 252, step: 8
1041 13:44:56.194947
1042 13:44:56.197892 Set Vref, RX VrefLevel [Byte0]: 32
1043 13:44:56.200877 [Byte1]: 32
1044 13:44:56.201301
1045 13:44:56.204801 Set Vref, RX VrefLevel [Byte0]: 33
1046 13:44:56.207561 [Byte1]: 33
1047 13:44:56.208081
1048 13:44:56.211327 Set Vref, RX VrefLevel [Byte0]: 34
1049 13:44:56.214827 [Byte1]: 34
1050 13:44:56.218851
1051 13:44:56.219273 Set Vref, RX VrefLevel [Byte0]: 35
1052 13:44:56.221661 [Byte1]: 35
1053 13:44:56.226454
1054 13:44:56.227119 Set Vref, RX VrefLevel [Byte0]: 36
1055 13:44:56.229360 [Byte1]: 36
1056 13:44:56.234179
1057 13:44:56.234637 Set Vref, RX VrefLevel [Byte0]: 37
1058 13:44:56.236915 [Byte1]: 37
1059 13:44:56.241505
1060 13:44:56.242131 Set Vref, RX VrefLevel [Byte0]: 38
1061 13:44:56.244816 [Byte1]: 38
1062 13:44:56.249087
1063 13:44:56.249510 Set Vref, RX VrefLevel [Byte0]: 39
1064 13:44:56.252302 [Byte1]: 39
1065 13:44:56.256463
1066 13:44:56.256894 Set Vref, RX VrefLevel [Byte0]: 40
1067 13:44:56.259793 [Byte1]: 40
1068 13:44:56.264286
1069 13:44:56.264766 Set Vref, RX VrefLevel [Byte0]: 41
1070 13:44:56.267314 [Byte1]: 41
1071 13:44:56.271644
1072 13:44:56.272158 Set Vref, RX VrefLevel [Byte0]: 42
1073 13:44:56.274443 [Byte1]: 42
1074 13:44:56.278521
1075 13:44:56.278970 Set Vref, RX VrefLevel [Byte0]: 43
1076 13:44:56.281901 [Byte1]: 43
1077 13:44:56.286413
1078 13:44:56.286834 Set Vref, RX VrefLevel [Byte0]: 44
1079 13:44:56.289533 [Byte1]: 44
1080 13:44:56.293937
1081 13:44:56.294363 Set Vref, RX VrefLevel [Byte0]: 45
1082 13:44:56.297948 [Byte1]: 45
1083 13:44:56.301239
1084 13:44:56.301538 Set Vref, RX VrefLevel [Byte0]: 46
1085 13:44:56.304895 [Byte1]: 46
1086 13:44:56.309106
1087 13:44:56.309437 Set Vref, RX VrefLevel [Byte0]: 47
1088 13:44:56.312326 [Byte1]: 47
1089 13:44:56.316196
1090 13:44:56.316535 Set Vref, RX VrefLevel [Byte0]: 48
1091 13:44:56.319862 [Byte1]: 48
1092 13:44:56.324121
1093 13:44:56.324572 Set Vref, RX VrefLevel [Byte0]: 49
1094 13:44:56.327561 [Byte1]: 49
1095 13:44:56.331691
1096 13:44:56.332019 Set Vref, RX VrefLevel [Byte0]: 50
1097 13:44:56.334696 [Byte1]: 50
1098 13:44:56.338858
1099 13:44:56.339224 Set Vref, RX VrefLevel [Byte0]: 51
1100 13:44:56.342487 [Byte1]: 51
1101 13:44:56.346777
1102 13:44:56.347176 Set Vref, RX VrefLevel [Byte0]: 52
1103 13:44:56.350067 [Byte1]: 52
1104 13:44:56.354116
1105 13:44:56.354543 Set Vref, RX VrefLevel [Byte0]: 53
1106 13:44:56.357258 [Byte1]: 53
1107 13:44:56.362159
1108 13:44:56.362647 Set Vref, RX VrefLevel [Byte0]: 54
1109 13:44:56.365008 [Byte1]: 54
1110 13:44:56.369337
1111 13:44:56.369751 Set Vref, RX VrefLevel [Byte0]: 55
1112 13:44:56.372727 [Byte1]: 55
1113 13:44:56.377180
1114 13:44:56.377470 Set Vref, RX VrefLevel [Byte0]: 56
1115 13:44:56.380647 [Byte1]: 56
1116 13:44:56.384206
1117 13:44:56.384527 Set Vref, RX VrefLevel [Byte0]: 57
1118 13:44:56.387667 [Byte1]: 57
1119 13:44:56.391848
1120 13:44:56.392141 Set Vref, RX VrefLevel [Byte0]: 58
1121 13:44:56.395248 [Byte1]: 58
1122 13:44:56.399751
1123 13:44:56.400129 Set Vref, RX VrefLevel [Byte0]: 59
1124 13:44:56.402632 [Byte1]: 59
1125 13:44:56.407475
1126 13:44:56.407851 Set Vref, RX VrefLevel [Byte0]: 60
1127 13:44:56.410392 [Byte1]: 60
1128 13:44:56.414647
1129 13:44:56.415081 Set Vref, RX VrefLevel [Byte0]: 61
1130 13:44:56.418178 [Byte1]: 61
1131 13:44:56.422545
1132 13:44:56.423053 Set Vref, RX VrefLevel [Byte0]: 62
1133 13:44:56.425600 [Byte1]: 62
1134 13:44:56.429876
1135 13:44:56.430322 Set Vref, RX VrefLevel [Byte0]: 63
1136 13:44:56.432977 [Byte1]: 63
1137 13:44:56.437933
1138 13:44:56.438466 Set Vref, RX VrefLevel [Byte0]: 64
1139 13:44:56.440594 [Byte1]: 64
1140 13:44:56.444827
1141 13:44:56.445246 Set Vref, RX VrefLevel [Byte0]: 65
1142 13:44:56.448500 [Byte1]: 65
1143 13:44:56.452725
1144 13:44:56.453246 Set Vref, RX VrefLevel [Byte0]: 66
1145 13:44:56.456239 [Byte1]: 66
1146 13:44:56.460496
1147 13:44:56.461061 Set Vref, RX VrefLevel [Byte0]: 67
1148 13:44:56.464125 [Byte1]: 67
1149 13:44:56.467755
1150 13:44:56.468215 Set Vref, RX VrefLevel [Byte0]: 68
1151 13:44:56.471000 [Byte1]: 68
1152 13:44:56.475632
1153 13:44:56.476198 Set Vref, RX VrefLevel [Byte0]: 69
1154 13:44:56.478819 [Byte1]: 69
1155 13:44:56.482339
1156 13:44:56.485817 Set Vref, RX VrefLevel [Byte0]: 70
1157 13:44:56.489092 [Byte1]: 70
1158 13:44:56.489795
1159 13:44:56.492414 Set Vref, RX VrefLevel [Byte0]: 71
1160 13:44:56.495976 [Byte1]: 71
1161 13:44:56.496428
1162 13:44:56.499414 Set Vref, RX VrefLevel [Byte0]: 72
1163 13:44:56.502275 [Byte1]: 72
1164 13:44:56.502691
1165 13:44:56.505518 Set Vref, RX VrefLevel [Byte0]: 73
1166 13:44:56.508884 [Byte1]: 73
1167 13:44:56.512804
1168 13:44:56.513299 Set Vref, RX VrefLevel [Byte0]: 74
1169 13:44:56.516417 [Byte1]: 74
1170 13:44:56.521010
1171 13:44:56.521535 Set Vref, RX VrefLevel [Byte0]: 75
1172 13:44:56.523425 [Byte1]: 75
1173 13:44:56.527871
1174 13:44:56.528282 Set Vref, RX VrefLevel [Byte0]: 76
1175 13:44:56.531614 [Byte1]: 76
1176 13:44:56.535549
1177 13:44:56.536105 Set Vref, RX VrefLevel [Byte0]: 77
1178 13:44:56.538615 [Byte1]: 77
1179 13:44:56.542761
1180 13:44:56.543175 Set Vref, RX VrefLevel [Byte0]: 78
1181 13:44:56.546333 [Byte1]: 78
1182 13:44:56.550969
1183 13:44:56.551487 Final RX Vref Byte 0 = 60 to rank0
1184 13:44:56.554284 Final RX Vref Byte 1 = 61 to rank0
1185 13:44:56.557618 Final RX Vref Byte 0 = 60 to rank1
1186 13:44:56.560419 Final RX Vref Byte 1 = 61 to rank1==
1187 13:44:56.564154 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 13:44:56.570481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 13:44:56.570947 ==
1190 13:44:56.571311 DQS Delay:
1191 13:44:56.571648 DQS0 = 0, DQS1 = 0
1192 13:44:56.573998 DQM Delay:
1193 13:44:56.574412 DQM0 = 91, DQM1 = 86
1194 13:44:56.577423 DQ Delay:
1195 13:44:56.580901 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1196 13:44:56.584106 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1197 13:44:56.587329 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1198 13:44:56.590511 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1199 13:44:56.591030
1200 13:44:56.591360
1201 13:44:56.597372 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1202 13:44:56.600860 CH0 RK0: MR19=606, MR18=4B41
1203 13:44:56.607274 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1204 13:44:56.607787
1205 13:44:56.610686 ----->DramcWriteLeveling(PI) begin...
1206 13:44:56.611105 ==
1207 13:44:56.614400 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 13:44:56.617542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 13:44:56.617959 ==
1210 13:44:56.620959 Write leveling (Byte 0): 32 => 32
1211 13:44:56.624240 Write leveling (Byte 1): 30 => 30
1212 13:44:56.627671 DramcWriteLeveling(PI) end<-----
1213 13:44:56.628090
1214 13:44:56.628469 ==
1215 13:44:56.630567 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 13:44:56.634313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 13:44:56.634740 ==
1218 13:44:56.678475 [Gating] SW mode calibration
1219 13:44:56.679027 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 13:44:56.679398 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 13:44:56.679742 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 13:44:56.680469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 13:44:56.680844 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1224 13:44:56.681170 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:44:56.681485 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:44:56.681794 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:44:56.722231 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:44:56.722782 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:44:56.723281 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:44:56.724131 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:44:56.724584 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:44:56.724934 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:44:56.725260 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:44:56.725582 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:44:56.725925 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:44:56.726295 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:44:56.733354 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:44:56.734001 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1239 13:44:56.734985 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1240 13:44:56.736818 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:44:56.743302 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:44:56.746957 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:44:56.750529 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 13:44:56.753478 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:44:56.760490 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:44:56.763415 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 13:44:56.766856 0 9 8 | B1->B0 | 2d2d 2626 | 0 1 | (0 0) (1 1)
1248 13:44:56.773578 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 13:44:56.777076 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 13:44:56.780251 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 13:44:56.786883 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 13:44:56.789939 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 13:44:56.793428 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 13:44:56.800387 0 10 4 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
1255 13:44:56.803707 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1256 13:44:56.806946 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:44:56.811398 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 13:44:56.818403 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 13:44:56.822018 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 13:44:56.825475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 13:44:56.829051 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 13:44:56.835769 0 11 4 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
1263 13:44:56.839678 0 11 8 | B1->B0 | 4141 3b3b | 0 1 | (1 1) (0 0)
1264 13:44:56.843114 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 13:44:56.846333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 13:44:56.853134 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 13:44:56.856253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 13:44:56.859863 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 13:44:56.865923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 13:44:56.869624 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 13:44:56.872867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 13:44:56.879276 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:44:56.882836 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:44:56.886526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:44:56.892840 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 13:44:56.895989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 13:44:56.899702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 13:44:56.902677 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 13:44:56.909593 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 13:44:56.912846 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 13:44:56.916153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 13:44:56.922582 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 13:44:56.926113 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 13:44:56.929653 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 13:44:56.936218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 13:44:56.939541 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 13:44:56.942923 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1288 13:44:56.949576 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 13:44:56.950078 Total UI for P1: 0, mck2ui 16
1290 13:44:56.956162 best dqsien dly found for B0: ( 0, 14, 8)
1291 13:44:56.956650 Total UI for P1: 0, mck2ui 16
1292 13:44:56.962786 best dqsien dly found for B1: ( 0, 14, 8)
1293 13:44:56.966377 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 13:44:56.969815 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1295 13:44:56.970240
1296 13:44:56.972724 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 13:44:56.976540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 13:44:56.980238 [Gating] SW calibration Done
1299 13:44:56.980850 ==
1300 13:44:56.983656 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 13:44:56.986470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 13:44:56.987035 ==
1303 13:44:56.989929 RX Vref Scan: 0
1304 13:44:56.990398
1305 13:44:56.990761 RX Vref 0 -> 0, step: 1
1306 13:44:56.991101
1307 13:44:56.992834 RX Delay -130 -> 252, step: 16
1308 13:44:56.996437 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1309 13:44:57.000004 iDelay=222, Bit 1, Center 101 (-2 ~ 205) 208
1310 13:44:57.006751 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1311 13:44:57.010091 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1312 13:44:57.012875 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1313 13:44:57.016987 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1314 13:44:57.019951 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1315 13:44:57.026297 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1316 13:44:57.029760 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1317 13:44:57.033046 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1318 13:44:57.036806 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1319 13:44:57.039895 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1320 13:44:57.046274 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1321 13:44:57.049769 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1322 13:44:57.052926 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1323 13:44:57.056652 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1324 13:44:57.057065 ==
1325 13:44:57.060487 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 13:44:57.066524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 13:44:57.067043 ==
1328 13:44:57.067383 DQS Delay:
1329 13:44:57.067694 DQS0 = 0, DQS1 = 0
1330 13:44:57.069846 DQM Delay:
1331 13:44:57.070263 DQM0 = 95, DQM1 = 86
1332 13:44:57.073686 DQ Delay:
1333 13:44:57.076895 DQ0 =93, DQ1 =101, DQ2 =93, DQ3 =93
1334 13:44:57.079739 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1335 13:44:57.080158 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1336 13:44:57.086854 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1337 13:44:57.087292
1338 13:44:57.087675
1339 13:44:57.087990 ==
1340 13:44:57.090400 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 13:44:57.093238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 13:44:57.093657 ==
1343 13:44:57.093986
1344 13:44:57.094286
1345 13:44:57.096786 TX Vref Scan disable
1346 13:44:57.097203 == TX Byte 0 ==
1347 13:44:57.103450 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1348 13:44:57.106910 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1349 13:44:57.107431 == TX Byte 1 ==
1350 13:44:57.113803 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1351 13:44:57.116540 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1352 13:44:57.117358 ==
1353 13:44:57.120111 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 13:44:57.123652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 13:44:57.124075 ==
1356 13:44:57.137296 TX Vref=22, minBit 10, minWin=27, winSum=451
1357 13:44:57.140750 TX Vref=24, minBit 10, minWin=27, winSum=452
1358 13:44:57.144036 TX Vref=26, minBit 10, minWin=27, winSum=455
1359 13:44:57.147336 TX Vref=28, minBit 5, minWin=28, winSum=458
1360 13:44:57.150453 TX Vref=30, minBit 4, minWin=28, winSum=457
1361 13:44:57.157199 TX Vref=32, minBit 7, minWin=28, winSum=458
1362 13:44:57.160501 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
1363 13:44:57.160922
1364 13:44:57.163889 Final TX Range 1 Vref 28
1365 13:44:57.164314
1366 13:44:57.164681 ==
1367 13:44:57.167423 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 13:44:57.170281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 13:44:57.173789 ==
1370 13:44:57.174221
1371 13:44:57.174551
1372 13:44:57.174856 TX Vref Scan disable
1373 13:44:57.177424 == TX Byte 0 ==
1374 13:44:57.180945 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1375 13:44:57.184510 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1376 13:44:57.187547 == TX Byte 1 ==
1377 13:44:57.190788 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1378 13:44:57.197734 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1379 13:44:57.198157
1380 13:44:57.198488 [DATLAT]
1381 13:44:57.198795 Freq=800, CH0 RK1
1382 13:44:57.199111
1383 13:44:57.200697 DATLAT Default: 0xa
1384 13:44:57.201115 0, 0xFFFF, sum = 0
1385 13:44:57.204206 1, 0xFFFF, sum = 0
1386 13:44:57.204694 2, 0xFFFF, sum = 0
1387 13:44:57.207946 3, 0xFFFF, sum = 0
1388 13:44:57.208737 4, 0xFFFF, sum = 0
1389 13:44:57.210678 5, 0xFFFF, sum = 0
1390 13:44:57.214444 6, 0xFFFF, sum = 0
1391 13:44:57.214872 7, 0xFFFF, sum = 0
1392 13:44:57.217208 8, 0xFFFF, sum = 0
1393 13:44:57.217633 9, 0x0, sum = 1
1394 13:44:57.217970 10, 0x0, sum = 2
1395 13:44:57.220750 11, 0x0, sum = 3
1396 13:44:57.221252 12, 0x0, sum = 4
1397 13:44:57.224433 best_step = 10
1398 13:44:57.224851
1399 13:44:57.225179 ==
1400 13:44:57.227226 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 13:44:57.230675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 13:44:57.231155 ==
1403 13:44:57.234015 RX Vref Scan: 0
1404 13:44:57.234450
1405 13:44:57.234780 RX Vref 0 -> 0, step: 1
1406 13:44:57.235085
1407 13:44:57.237499 RX Delay -79 -> 252, step: 8
1408 13:44:57.244316 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1409 13:44:57.247605 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1410 13:44:57.250915 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1411 13:44:57.254525 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1412 13:44:57.257304 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1413 13:44:57.264454 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1414 13:44:57.267506 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1415 13:44:57.270613 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 13:44:57.274619 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1417 13:44:57.278107 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1418 13:44:57.284408 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1419 13:44:57.287737 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1420 13:44:57.291044 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1421 13:44:57.294426 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1422 13:44:57.297613 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 13:44:57.304537 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1424 13:44:57.305000 ==
1425 13:44:57.307656 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 13:44:57.311174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 13:44:57.311614 ==
1428 13:44:57.311941 DQS Delay:
1429 13:44:57.314721 DQS0 = 0, DQS1 = 0
1430 13:44:57.315459 DQM Delay:
1431 13:44:57.317609 DQM0 = 92, DQM1 = 84
1432 13:44:57.318029 DQ Delay:
1433 13:44:57.321113 DQ0 =92, DQ1 =92, DQ2 =92, DQ3 =92
1434 13:44:57.324496 DQ4 =92, DQ5 =84, DQ6 =96, DQ7 =100
1435 13:44:57.327454 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1436 13:44:57.331088 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1437 13:44:57.331713
1438 13:44:57.332538
1439 13:44:57.337615 [DQSOSCAuto] RK1, (LSB)MR18= 0x4818, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1440 13:44:57.340891 CH0 RK1: MR19=606, MR18=4818
1441 13:44:57.347696 CH0_RK1: MR19=0x606, MR18=0x4818, DQSOSC=391, MR23=63, INC=96, DEC=64
1442 13:44:57.351201 [RxdqsGatingPostProcess] freq 800
1443 13:44:57.357664 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 13:44:57.358075 Pre-setting of DQS Precalculation
1445 13:44:57.364617 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 13:44:57.365031 ==
1447 13:44:57.367556 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 13:44:57.370972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 13:44:57.371589 ==
1450 13:44:57.377758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 13:44:57.384037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 13:44:57.392506 [CA 0] Center 36 (6~67) winsize 62
1453 13:44:57.395766 [CA 1] Center 36 (6~67) winsize 62
1454 13:44:57.399093 [CA 2] Center 35 (5~66) winsize 62
1455 13:44:57.402696 [CA 3] Center 34 (4~65) winsize 62
1456 13:44:57.405399 [CA 4] Center 35 (5~65) winsize 61
1457 13:44:57.409429 [CA 5] Center 34 (4~65) winsize 62
1458 13:44:57.409958
1459 13:44:57.412718 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1460 13:44:57.413153
1461 13:44:57.415814 [CATrainingPosCal] consider 1 rank data
1462 13:44:57.419329 u2DelayCellTimex100 = 270/100 ps
1463 13:44:57.422838 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 13:44:57.425881 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 13:44:57.432951 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1466 13:44:57.435678 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 13:44:57.439208 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1468 13:44:57.442758 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 13:44:57.443187
1470 13:44:57.445616 CA PerBit enable=1, Macro0, CA PI delay=34
1471 13:44:57.446092
1472 13:44:57.449033 [CBTSetCACLKResult] CA Dly = 34
1473 13:44:57.449462 CS Dly: 6 (0~37)
1474 13:44:57.449895 ==
1475 13:44:57.452657 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 13:44:57.459536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 13:44:57.460074 ==
1478 13:44:57.463030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 13:44:57.469147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 13:44:57.478704 [CA 0] Center 36 (6~67) winsize 62
1481 13:44:57.482497 [CA 1] Center 37 (6~68) winsize 63
1482 13:44:57.486069 [CA 2] Center 35 (5~66) winsize 62
1483 13:44:57.490281 [CA 3] Center 34 (4~65) winsize 62
1484 13:44:57.493781 [CA 4] Center 35 (5~66) winsize 62
1485 13:44:57.497290 [CA 5] Center 34 (4~65) winsize 62
1486 13:44:57.497802
1487 13:44:57.501124 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1488 13:44:57.501559
1489 13:44:57.504595 [CATrainingPosCal] consider 2 rank data
1490 13:44:57.505026 u2DelayCellTimex100 = 270/100 ps
1491 13:44:57.508608 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 13:44:57.511740 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 13:44:57.518553 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1494 13:44:57.521699 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 13:44:57.525430 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1496 13:44:57.528693 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 13:44:57.529110
1498 13:44:57.531804 CA PerBit enable=1, Macro0, CA PI delay=34
1499 13:44:57.532221
1500 13:44:57.535704 [CBTSetCACLKResult] CA Dly = 34
1501 13:44:57.536305 CS Dly: 6 (0~38)
1502 13:44:57.536697
1503 13:44:57.538989 ----->DramcWriteLeveling(PI) begin...
1504 13:44:57.541870 ==
1505 13:44:57.542289 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 13:44:57.548901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 13:44:57.549319 ==
1508 13:44:57.552491 Write leveling (Byte 0): 26 => 26
1509 13:44:57.555539 Write leveling (Byte 1): 27 => 27
1510 13:44:57.556060 DramcWriteLeveling(PI) end<-----
1511 13:44:57.558827
1512 13:44:57.559343 ==
1513 13:44:57.562589 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 13:44:57.565063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 13:44:57.565490 ==
1516 13:44:57.568958 [Gating] SW mode calibration
1517 13:44:57.576048 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 13:44:57.579398 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 13:44:57.585476 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1520 13:44:57.589190 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1521 13:44:57.592154 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:44:57.599412 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:44:57.602274 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:44:57.605731 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:44:57.611951 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:44:57.615449 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:44:57.618665 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:44:57.625612 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:44:57.628884 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:44:57.632031 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:44:57.635377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:44:57.642441 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:44:57.645651 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:44:57.649234 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:44:57.655633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1536 13:44:57.659097 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 13:44:57.662222 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:44:57.668906 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:44:57.672447 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:44:57.676086 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:44:57.682567 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:44:57.686006 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:44:57.689156 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 13:44:57.695968 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1545 13:44:57.699168 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1546 13:44:57.702796 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 13:44:57.706028 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 13:44:57.712732 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 13:44:57.715578 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 13:44:57.719091 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 13:44:57.726209 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 13:44:57.729421 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 1)
1553 13:44:57.732745 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1554 13:44:57.739835 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:44:57.742458 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 13:44:57.746053 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 13:44:57.753105 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 13:44:57.755882 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 13:44:57.759342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 13:44:57.765943 0 11 4 | B1->B0 | 2a2a 3737 | 0 1 | (0 0) (0 0)
1561 13:44:57.769578 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (1 1) (1 1)
1562 13:44:57.772645 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 13:44:57.779513 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 13:44:57.782795 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 13:44:57.786329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 13:44:57.789057 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 13:44:57.796164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 13:44:57.799598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1569 13:44:57.802814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:44:57.809153 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:44:57.812846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:44:57.816496 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:44:57.822952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 13:44:57.826466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 13:44:57.829270 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 13:44:57.835988 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 13:44:57.839351 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:44:57.842701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:44:57.849817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 13:44:57.852623 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 13:44:57.856406 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 13:44:57.859792 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 13:44:57.866635 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 13:44:57.869932 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 13:44:57.872720 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 13:44:57.876846 Total UI for P1: 0, mck2ui 16
1587 13:44:57.880076 best dqsien dly found for B0: ( 0, 14, 4)
1588 13:44:57.883421 Total UI for P1: 0, mck2ui 16
1589 13:44:57.886372 best dqsien dly found for B1: ( 0, 14, 4)
1590 13:44:57.889333 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1591 13:44:57.892959 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1592 13:44:57.895939
1593 13:44:57.899283 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 13:44:57.902648 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 13:44:57.906291 [Gating] SW calibration Done
1596 13:44:57.906721 ==
1597 13:44:57.909866 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 13:44:57.913289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 13:44:57.913723 ==
1600 13:44:57.914163 RX Vref Scan: 0
1601 13:44:57.914573
1602 13:44:57.916415 RX Vref 0 -> 0, step: 1
1603 13:44:57.916847
1604 13:44:57.919779 RX Delay -130 -> 252, step: 16
1605 13:44:57.923142 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 13:44:57.926324 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1607 13:44:57.933197 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 13:44:57.936006 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1609 13:44:57.939606 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1610 13:44:57.942971 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1611 13:44:57.946278 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1612 13:44:57.953061 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1613 13:44:57.956374 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1614 13:44:57.959736 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1615 13:44:57.962865 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1616 13:44:57.966224 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1617 13:44:57.969695 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1618 13:44:57.976154 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1619 13:44:57.979688 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1620 13:44:57.983530 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1621 13:44:57.984106 ==
1622 13:44:57.986164 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 13:44:57.989801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 13:44:57.993463 ==
1625 13:44:57.994018 DQS Delay:
1626 13:44:57.994381 DQS0 = 0, DQS1 = 0
1627 13:44:57.996167 DQM Delay:
1628 13:44:57.996844 DQM0 = 93, DQM1 = 87
1629 13:44:57.997242 DQ Delay:
1630 13:44:57.999696 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1631 13:44:58.002892 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1632 13:44:58.006856 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1633 13:44:58.010129 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1634 13:44:58.010546
1635 13:44:58.012989
1636 13:44:58.013449 ==
1637 13:44:58.016638 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 13:44:58.019820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 13:44:58.020430 ==
1640 13:44:58.020784
1641 13:44:58.021090
1642 13:44:58.023127 TX Vref Scan disable
1643 13:44:58.023540 == TX Byte 0 ==
1644 13:44:58.029592 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1645 13:44:58.033528 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1646 13:44:58.033954 == TX Byte 1 ==
1647 13:44:58.036828 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1648 13:44:58.043346 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1649 13:44:58.043768 ==
1650 13:44:58.046878 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 13:44:58.049480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 13:44:58.049882 ==
1653 13:44:58.063186 TX Vref=22, minBit 0, minWin=26, winSum=434
1654 13:44:58.066428 TX Vref=24, minBit 0, minWin=27, winSum=440
1655 13:44:58.069783 TX Vref=26, minBit 1, minWin=26, winSum=445
1656 13:44:58.072669 TX Vref=28, minBit 0, minWin=27, winSum=447
1657 13:44:58.076498 TX Vref=30, minBit 3, minWin=26, winSum=445
1658 13:44:58.080296 TX Vref=32, minBit 7, minWin=26, winSum=441
1659 13:44:58.086390 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 28
1660 13:44:58.086914
1661 13:44:58.089847 Final TX Range 1 Vref 28
1662 13:44:58.090272
1663 13:44:58.090605 ==
1664 13:44:58.093528 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 13:44:58.096394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 13:44:58.096824 ==
1667 13:44:58.097157
1668 13:44:58.100189
1669 13:44:58.100763 TX Vref Scan disable
1670 13:44:58.102886 == TX Byte 0 ==
1671 13:44:58.106235 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1672 13:44:58.109813 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1673 13:44:58.112676 == TX Byte 1 ==
1674 13:44:58.116384 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1675 13:44:58.119662 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1676 13:44:58.120207
1677 13:44:58.122962 [DATLAT]
1678 13:44:58.123381 Freq=800, CH1 RK0
1679 13:44:58.123724
1680 13:44:58.126405 DATLAT Default: 0xa
1681 13:44:58.126824 0, 0xFFFF, sum = 0
1682 13:44:58.129762 1, 0xFFFF, sum = 0
1683 13:44:58.130187 2, 0xFFFF, sum = 0
1684 13:44:58.133191 3, 0xFFFF, sum = 0
1685 13:44:58.133639 4, 0xFFFF, sum = 0
1686 13:44:58.136241 5, 0xFFFF, sum = 0
1687 13:44:58.136704 6, 0xFFFF, sum = 0
1688 13:44:58.139612 7, 0xFFFF, sum = 0
1689 13:44:58.140124 8, 0xFFFF, sum = 0
1690 13:44:58.142828 9, 0x0, sum = 1
1691 13:44:58.143355 10, 0x0, sum = 2
1692 13:44:58.146670 11, 0x0, sum = 3
1693 13:44:58.147155 12, 0x0, sum = 4
1694 13:44:58.149886 best_step = 10
1695 13:44:58.150321
1696 13:44:58.150657 ==
1697 13:44:58.152732 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 13:44:58.156328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 13:44:58.156789 ==
1700 13:44:58.159532 RX Vref Scan: 1
1701 13:44:58.160124
1702 13:44:58.160709 Set Vref Range= 32 -> 127
1703 13:44:58.161313
1704 13:44:58.163098 RX Vref 32 -> 127, step: 1
1705 13:44:58.163665
1706 13:44:58.166596 RX Delay -79 -> 252, step: 8
1707 13:44:58.167016
1708 13:44:58.169512 Set Vref, RX VrefLevel [Byte0]: 32
1709 13:44:58.173093 [Byte1]: 32
1710 13:44:58.173677
1711 13:44:58.176420 Set Vref, RX VrefLevel [Byte0]: 33
1712 13:44:58.179542 [Byte1]: 33
1713 13:44:58.183003
1714 13:44:58.183229 Set Vref, RX VrefLevel [Byte0]: 34
1715 13:44:58.186506 [Byte1]: 34
1716 13:44:58.190523
1717 13:44:58.190604 Set Vref, RX VrefLevel [Byte0]: 35
1718 13:44:58.193499 [Byte1]: 35
1719 13:44:58.198002
1720 13:44:58.198084 Set Vref, RX VrefLevel [Byte0]: 36
1721 13:44:58.200886 [Byte1]: 36
1722 13:44:58.205507
1723 13:44:58.205589 Set Vref, RX VrefLevel [Byte0]: 37
1724 13:44:58.208938 [Byte1]: 37
1725 13:44:58.213312
1726 13:44:58.213394 Set Vref, RX VrefLevel [Byte0]: 38
1727 13:44:58.216386 [Byte1]: 38
1728 13:44:58.220699
1729 13:44:58.220781 Set Vref, RX VrefLevel [Byte0]: 39
1730 13:44:58.223672 [Byte1]: 39
1731 13:44:58.228307
1732 13:44:58.228495 Set Vref, RX VrefLevel [Byte0]: 40
1733 13:44:58.231753 [Byte1]: 40
1734 13:44:58.235320
1735 13:44:58.235482 Set Vref, RX VrefLevel [Byte0]: 41
1736 13:44:58.239018 [Byte1]: 41
1737 13:44:58.243013
1738 13:44:58.243165 Set Vref, RX VrefLevel [Byte0]: 42
1739 13:44:58.246652 [Byte1]: 42
1740 13:44:58.251047
1741 13:44:58.251183 Set Vref, RX VrefLevel [Byte0]: 43
1742 13:44:58.253918 [Byte1]: 43
1743 13:44:58.258598
1744 13:44:58.258770 Set Vref, RX VrefLevel [Byte0]: 44
1745 13:44:58.261581 [Byte1]: 44
1746 13:44:58.265811
1747 13:44:58.266012 Set Vref, RX VrefLevel [Byte0]: 45
1748 13:44:58.269049 [Byte1]: 45
1749 13:44:58.273149
1750 13:44:58.273442 Set Vref, RX VrefLevel [Byte0]: 46
1751 13:44:58.276767 [Byte1]: 46
1752 13:44:58.281217
1753 13:44:58.281468 Set Vref, RX VrefLevel [Byte0]: 47
1754 13:44:58.284172 [Byte1]: 47
1755 13:44:58.288469
1756 13:44:58.288711 Set Vref, RX VrefLevel [Byte0]: 48
1757 13:44:58.291692 [Byte1]: 48
1758 13:44:58.295721
1759 13:44:58.296079 Set Vref, RX VrefLevel [Byte0]: 49
1760 13:44:58.299353 [Byte1]: 49
1761 13:44:58.303689
1762 13:44:58.303937 Set Vref, RX VrefLevel [Byte0]: 50
1763 13:44:58.306723 [Byte1]: 50
1764 13:44:58.311126
1765 13:44:58.311434 Set Vref, RX VrefLevel [Byte0]: 51
1766 13:44:58.314681 [Byte1]: 51
1767 13:44:58.319126
1768 13:44:58.319381 Set Vref, RX VrefLevel [Byte0]: 52
1769 13:44:58.322115 [Byte1]: 52
1770 13:44:58.326390
1771 13:44:58.326695 Set Vref, RX VrefLevel [Byte0]: 53
1772 13:44:58.329302 [Byte1]: 53
1773 13:44:58.333476
1774 13:44:58.333726 Set Vref, RX VrefLevel [Byte0]: 54
1775 13:44:58.337116 [Byte1]: 54
1776 13:44:58.341470
1777 13:44:58.341710 Set Vref, RX VrefLevel [Byte0]: 55
1778 13:44:58.344400 [Byte1]: 55
1779 13:44:58.349305
1780 13:44:58.349545 Set Vref, RX VrefLevel [Byte0]: 56
1781 13:44:58.352385 [Byte1]: 56
1782 13:44:58.356735
1783 13:44:58.356975 Set Vref, RX VrefLevel [Byte0]: 57
1784 13:44:58.359608 [Byte1]: 57
1785 13:44:58.363967
1786 13:44:58.364312 Set Vref, RX VrefLevel [Byte0]: 58
1787 13:44:58.367490 [Byte1]: 58
1788 13:44:58.371898
1789 13:44:58.372250 Set Vref, RX VrefLevel [Byte0]: 59
1790 13:44:58.374624 [Byte1]: 59
1791 13:44:58.379275
1792 13:44:58.379618 Set Vref, RX VrefLevel [Byte0]: 60
1793 13:44:58.382426 [Byte1]: 60
1794 13:44:58.386759
1795 13:44:58.387156 Set Vref, RX VrefLevel [Byte0]: 61
1796 13:44:58.389667 [Byte1]: 61
1797 13:44:58.394106
1798 13:44:58.394549 Set Vref, RX VrefLevel [Byte0]: 62
1799 13:44:58.397359 [Byte1]: 62
1800 13:44:58.402063
1801 13:44:58.402307 Set Vref, RX VrefLevel [Byte0]: 63
1802 13:44:58.405401 [Byte1]: 63
1803 13:44:58.409161
1804 13:44:58.409398 Set Vref, RX VrefLevel [Byte0]: 64
1805 13:44:58.412460 [Byte1]: 64
1806 13:44:58.416605
1807 13:44:58.416990 Set Vref, RX VrefLevel [Byte0]: 65
1808 13:44:58.420269 [Byte1]: 65
1809 13:44:58.424554
1810 13:44:58.424972 Set Vref, RX VrefLevel [Byte0]: 66
1811 13:44:58.427472 [Byte1]: 66
1812 13:44:58.431718
1813 13:44:58.431958 Set Vref, RX VrefLevel [Byte0]: 67
1814 13:44:58.435319 [Byte1]: 67
1815 13:44:58.439379
1816 13:44:58.439667 Set Vref, RX VrefLevel [Byte0]: 68
1817 13:44:58.442625 [Byte1]: 68
1818 13:44:58.446842
1819 13:44:58.447198 Set Vref, RX VrefLevel [Byte0]: 69
1820 13:44:58.450355 [Byte1]: 69
1821 13:44:58.454535
1822 13:44:58.454797 Set Vref, RX VrefLevel [Byte0]: 70
1823 13:44:58.457485 [Byte1]: 70
1824 13:44:58.461977
1825 13:44:58.462241 Set Vref, RX VrefLevel [Byte0]: 71
1826 13:44:58.465482 [Byte1]: 71
1827 13:44:58.469953
1828 13:44:58.470293 Final RX Vref Byte 0 = 59 to rank0
1829 13:44:58.472913 Final RX Vref Byte 1 = 55 to rank0
1830 13:44:58.476515 Final RX Vref Byte 0 = 59 to rank1
1831 13:44:58.479328 Final RX Vref Byte 1 = 55 to rank1==
1832 13:44:58.483025 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 13:44:58.486634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 13:44:58.489689 ==
1835 13:44:58.490029 DQS Delay:
1836 13:44:58.490330 DQS0 = 0, DQS1 = 0
1837 13:44:58.493144 DQM Delay:
1838 13:44:58.493422 DQM0 = 95, DQM1 = 89
1839 13:44:58.496705 DQ Delay:
1840 13:44:58.500032 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1841 13:44:58.503315 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1842 13:44:58.503598 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1843 13:44:58.509885 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1844 13:44:58.510130
1845 13:44:58.510320
1846 13:44:58.516333 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1847 13:44:58.519691 CH1 RK0: MR19=606, MR18=2D49
1848 13:44:58.526176 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1849 13:44:58.526420
1850 13:44:58.529791 ----->DramcWriteLeveling(PI) begin...
1851 13:44:58.530116 ==
1852 13:44:58.532839 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 13:44:58.536046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 13:44:58.536130 ==
1855 13:44:58.539677 Write leveling (Byte 0): 26 => 26
1856 13:44:58.542595 Write leveling (Byte 1): 27 => 27
1857 13:44:58.546182 DramcWriteLeveling(PI) end<-----
1858 13:44:58.546267
1859 13:44:58.546333 ==
1860 13:44:58.549552 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 13:44:58.552886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 13:44:58.552994 ==
1863 13:44:58.556476 [Gating] SW mode calibration
1864 13:44:58.562848 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 13:44:58.569447 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 13:44:58.573139 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1867 13:44:58.576869 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1868 13:44:58.583437 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 13:44:58.586411 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:44:58.590058 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:44:58.597047 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:44:58.600092 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:44:58.603698 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:44:58.606617 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:44:58.613778 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:44:58.617145 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:44:58.620522 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:44:58.627099 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:44:58.630539 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:44:58.633959 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:44:58.640620 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:44:58.644132 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1883 13:44:58.647294 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 13:44:58.653715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:44:58.656975 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:44:58.660782 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:44:58.667315 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:44:58.670530 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:44:58.673934 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:44:58.677472 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:44:58.683910 0 9 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1892 13:44:58.687518 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1893 13:44:58.690544 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 13:44:58.697461 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 13:44:58.700433 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 13:44:58.704072 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 13:44:58.710771 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 13:44:58.714181 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 13:44:58.717882 0 10 4 | B1->B0 | 2525 3131 | 0 1 | (0 0) (1 0)
1900 13:44:58.723809 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 13:44:58.727614 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 13:44:58.730842 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 13:44:58.737496 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 13:44:58.740533 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 13:44:58.744023 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 13:44:58.750789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 13:44:58.753928 0 11 4 | B1->B0 | 3a3a 3030 | 0 0 | (0 0) (0 0)
1908 13:44:58.757143 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 13:44:58.760455 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 13:44:58.767723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 13:44:58.770460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 13:44:58.774490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 13:44:58.780594 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 13:44:58.784260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 13:44:58.787677 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 13:44:58.794062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 13:44:58.797261 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 13:44:58.800944 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 13:44:58.807471 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 13:44:58.811170 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 13:44:58.813852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:44:58.820523 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 13:44:58.824160 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 13:44:58.827674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 13:44:58.834427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 13:44:58.837139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 13:44:58.840694 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 13:44:58.844351 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 13:44:58.850390 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 13:44:58.854116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 13:44:58.857011 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1932 13:44:58.864235 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 13:44:58.867437 Total UI for P1: 0, mck2ui 16
1934 13:44:58.870587 best dqsien dly found for B0: ( 0, 14, 4)
1935 13:44:58.873589 Total UI for P1: 0, mck2ui 16
1936 13:44:58.877176 best dqsien dly found for B1: ( 0, 14, 4)
1937 13:44:58.880996 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1938 13:44:58.883887 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1939 13:44:58.884124
1940 13:44:58.887430 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 13:44:58.890893 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1942 13:44:58.894361 [Gating] SW calibration Done
1943 13:44:58.894547 ==
1944 13:44:58.897382 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 13:44:58.900932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 13:44:58.901113 ==
1947 13:44:58.904225 RX Vref Scan: 0
1948 13:44:58.904481
1949 13:44:58.904723 RX Vref 0 -> 0, step: 1
1950 13:44:58.904870
1951 13:44:58.907559 RX Delay -130 -> 252, step: 16
1952 13:44:58.910878 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1953 13:44:58.917453 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1954 13:44:58.920457 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1955 13:44:58.924220 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1956 13:44:58.927107 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1957 13:44:58.930935 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1958 13:44:58.937163 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1959 13:44:58.940904 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1960 13:44:58.944398 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1961 13:44:58.947275 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1962 13:44:58.950877 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1963 13:44:58.957607 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1964 13:44:58.960745 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1965 13:44:58.964408 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1966 13:44:58.967421 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1967 13:44:58.971098 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1968 13:44:58.971285 ==
1969 13:44:58.973986 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 13:44:58.981119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 13:44:58.981342 ==
1972 13:44:58.981566 DQS Delay:
1973 13:44:58.984412 DQS0 = 0, DQS1 = 0
1974 13:44:58.984630 DQM Delay:
1975 13:44:58.984851 DQM0 = 91, DQM1 = 88
1976 13:44:58.987621 DQ Delay:
1977 13:44:58.991038 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1978 13:44:58.994597 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1979 13:44:58.997572 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1980 13:44:59.001174 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1981 13:44:59.001433
1982 13:44:59.001637
1983 13:44:59.001828 ==
1984 13:44:59.004676 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 13:44:59.007951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 13:44:59.008212 ==
1987 13:44:59.008449
1988 13:44:59.008646
1989 13:44:59.011194 TX Vref Scan disable
1990 13:44:59.011454 == TX Byte 0 ==
1991 13:44:59.017712 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 13:44:59.020831 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 13:44:59.021150 == TX Byte 1 ==
1994 13:44:59.027776 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1995 13:44:59.031165 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1996 13:44:59.031528 ==
1997 13:44:59.034216 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 13:44:59.037527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 13:44:59.037913 ==
2000 13:44:59.052127 TX Vref=22, minBit 1, minWin=26, winSum=442
2001 13:44:59.055139 TX Vref=24, minBit 0, minWin=27, winSum=442
2002 13:44:59.058651 TX Vref=26, minBit 0, minWin=27, winSum=447
2003 13:44:59.062290 TX Vref=28, minBit 0, minWin=27, winSum=448
2004 13:44:59.065173 TX Vref=30, minBit 2, minWin=27, winSum=448
2005 13:44:59.069020 TX Vref=32, minBit 0, minWin=27, winSum=445
2006 13:44:59.075486 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 28
2007 13:44:59.075757
2008 13:44:59.078633 Final TX Range 1 Vref 28
2009 13:44:59.078979
2010 13:44:59.079264 ==
2011 13:44:59.082307 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 13:44:59.085913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 13:44:59.086204 ==
2014 13:44:59.086404
2015 13:44:59.086590
2016 13:44:59.088821 TX Vref Scan disable
2017 13:44:59.092291 == TX Byte 0 ==
2018 13:44:59.095748 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2019 13:44:59.099160 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2020 13:44:59.102396 == TX Byte 1 ==
2021 13:44:59.105799 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2022 13:44:59.108885 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2023 13:44:59.109204
2024 13:44:59.112586 [DATLAT]
2025 13:44:59.112872 Freq=800, CH1 RK1
2026 13:44:59.113080
2027 13:44:59.115621 DATLAT Default: 0xa
2028 13:44:59.115976 0, 0xFFFF, sum = 0
2029 13:44:59.118958 1, 0xFFFF, sum = 0
2030 13:44:59.119232 2, 0xFFFF, sum = 0
2031 13:44:59.122637 3, 0xFFFF, sum = 0
2032 13:44:59.122917 4, 0xFFFF, sum = 0
2033 13:44:59.125427 5, 0xFFFF, sum = 0
2034 13:44:59.125698 6, 0xFFFF, sum = 0
2035 13:44:59.128980 7, 0xFFFF, sum = 0
2036 13:44:59.129300 8, 0xFFFF, sum = 0
2037 13:44:59.132380 9, 0x0, sum = 1
2038 13:44:59.132643 10, 0x0, sum = 2
2039 13:44:59.135527 11, 0x0, sum = 3
2040 13:44:59.135889 12, 0x0, sum = 4
2041 13:44:59.139171 best_step = 10
2042 13:44:59.139515
2043 13:44:59.139797 ==
2044 13:44:59.142679 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 13:44:59.145438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 13:44:59.145803 ==
2047 13:44:59.149018 RX Vref Scan: 0
2048 13:44:59.149343
2049 13:44:59.149549 RX Vref 0 -> 0, step: 1
2050 13:44:59.149733
2051 13:44:59.152382 RX Delay -79 -> 252, step: 8
2052 13:44:59.158435 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
2053 13:44:59.161942 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2054 13:44:59.165773 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2055 13:44:59.168839 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2056 13:44:59.172209 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2057 13:44:59.175780 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2058 13:44:59.178799 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2059 13:44:59.185439 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2060 13:44:59.188964 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2061 13:44:59.192630 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2062 13:44:59.195573 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2063 13:44:59.199099 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2064 13:44:59.205774 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2065 13:44:59.209327 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2066 13:44:59.212579 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2067 13:44:59.215329 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2068 13:44:59.215491 ==
2069 13:44:59.219121 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 13:44:59.222131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 13:44:59.225573 ==
2072 13:44:59.225740 DQS Delay:
2073 13:44:59.225872 DQS0 = 0, DQS1 = 0
2074 13:44:59.229197 DQM Delay:
2075 13:44:59.229284 DQM0 = 96, DQM1 = 90
2076 13:44:59.232253 DQ Delay:
2077 13:44:59.236000 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2078 13:44:59.236085 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2079 13:44:59.238849 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2080 13:44:59.245939 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2081 13:44:59.246028
2082 13:44:59.246094
2083 13:44:59.252233 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2084 13:44:59.255894 CH1 RK1: MR19=606, MR18=460F
2085 13:44:59.262535 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2086 13:44:59.266071 [RxdqsGatingPostProcess] freq 800
2087 13:44:59.269461 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 13:44:59.272863 Pre-setting of DQS Precalculation
2089 13:44:59.279100 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 13:44:59.285889 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 13:44:59.292458 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 13:44:59.292546
2093 13:44:59.292613
2094 13:44:59.295589 [Calibration Summary] 1600 Mbps
2095 13:44:59.295675 CH 0, Rank 0
2096 13:44:59.299342 SW Impedance : PASS
2097 13:44:59.299426 DUTY Scan : NO K
2098 13:44:59.302344 ZQ Calibration : PASS
2099 13:44:59.305995 Jitter Meter : NO K
2100 13:44:59.306085 CBT Training : PASS
2101 13:44:59.309623 Write leveling : PASS
2102 13:44:59.312564 RX DQS gating : PASS
2103 13:44:59.312648 RX DQ/DQS(RDDQC) : PASS
2104 13:44:59.316075 TX DQ/DQS : PASS
2105 13:44:59.319488 RX DATLAT : PASS
2106 13:44:59.319572 RX DQ/DQS(Engine): PASS
2107 13:44:59.322961 TX OE : NO K
2108 13:44:59.323045 All Pass.
2109 13:44:59.323112
2110 13:44:59.325852 CH 0, Rank 1
2111 13:44:59.325936 SW Impedance : PASS
2112 13:44:59.329394 DUTY Scan : NO K
2113 13:44:59.333083 ZQ Calibration : PASS
2114 13:44:59.333165 Jitter Meter : NO K
2115 13:44:59.335924 CBT Training : PASS
2116 13:44:59.338890 Write leveling : PASS
2117 13:44:59.338984 RX DQS gating : PASS
2118 13:44:59.342488 RX DQ/DQS(RDDQC) : PASS
2119 13:44:59.342613 TX DQ/DQS : PASS
2120 13:44:59.346252 RX DATLAT : PASS
2121 13:44:59.349022 RX DQ/DQS(Engine): PASS
2122 13:44:59.349173 TX OE : NO K
2123 13:44:59.352561 All Pass.
2124 13:44:59.352672
2125 13:44:59.352759 CH 1, Rank 0
2126 13:44:59.356033 SW Impedance : PASS
2127 13:44:59.356203 DUTY Scan : NO K
2128 13:44:59.359600 ZQ Calibration : PASS
2129 13:44:59.362453 Jitter Meter : NO K
2130 13:44:59.362634 CBT Training : PASS
2131 13:44:59.366175 Write leveling : PASS
2132 13:44:59.369190 RX DQS gating : PASS
2133 13:44:59.369425 RX DQ/DQS(RDDQC) : PASS
2134 13:44:59.372956 TX DQ/DQS : PASS
2135 13:44:59.375838 RX DATLAT : PASS
2136 13:44:59.376042 RX DQ/DQS(Engine): PASS
2137 13:44:59.378903 TX OE : NO K
2138 13:44:59.379113 All Pass.
2139 13:44:59.379269
2140 13:44:59.382341 CH 1, Rank 1
2141 13:44:59.382577 SW Impedance : PASS
2142 13:44:59.386137 DUTY Scan : NO K
2143 13:44:59.389031 ZQ Calibration : PASS
2144 13:44:59.389269 Jitter Meter : NO K
2145 13:44:59.392105 CBT Training : PASS
2146 13:44:59.392359 Write leveling : PASS
2147 13:44:59.395714 RX DQS gating : PASS
2148 13:44:59.399415 RX DQ/DQS(RDDQC) : PASS
2149 13:44:59.399652 TX DQ/DQS : PASS
2150 13:44:59.402618 RX DATLAT : PASS
2151 13:44:59.405497 RX DQ/DQS(Engine): PASS
2152 13:44:59.405740 TX OE : NO K
2153 13:44:59.409417 All Pass.
2154 13:44:59.409659
2155 13:44:59.409861 DramC Write-DBI off
2156 13:44:59.412613 PER_BANK_REFRESH: Hybrid Mode
2157 13:44:59.415608 TX_TRACKING: ON
2158 13:44:59.419481 [GetDramInforAfterCalByMRR] Vendor 6.
2159 13:44:59.422355 [GetDramInforAfterCalByMRR] Revision 606.
2160 13:44:59.425923 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 13:44:59.426161 MR0 0x3b3b
2162 13:44:59.426310 MR8 0x5151
2163 13:44:59.429225 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 13:44:59.432542
2165 13:44:59.432624 MR0 0x3b3b
2166 13:44:59.432688 MR8 0x5151
2167 13:44:59.435467 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 13:44:59.435549
2169 13:44:59.445686 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 13:44:59.449431 [FAST_K] Save calibration result to emmc
2171 13:44:59.452412 [FAST_K] Save calibration result to emmc
2172 13:44:59.456180 dram_init: config_dvfs: 1
2173 13:44:59.459040 dramc_set_vcore_voltage set vcore to 662500
2174 13:44:59.462490 Read voltage for 1200, 2
2175 13:44:59.462572 Vio18 = 0
2176 13:44:59.462637 Vcore = 662500
2177 13:44:59.465938 Vdram = 0
2178 13:44:59.466062 Vddq = 0
2179 13:44:59.466164 Vmddr = 0
2180 13:44:59.472576 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 13:44:59.476620 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 13:44:59.479614 MEM_TYPE=3, freq_sel=15
2183 13:44:59.483302 sv_algorithm_assistance_LP4_1600
2184 13:44:59.486225 ============ PULL DRAM RESETB DOWN ============
2185 13:44:59.489517 ========== PULL DRAM RESETB DOWN end =========
2186 13:44:59.496609 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 13:44:59.499207 ===================================
2188 13:44:59.499642 LPDDR4 DRAM CONFIGURATION
2189 13:44:59.502961 ===================================
2190 13:44:59.506546 EX_ROW_EN[0] = 0x0
2191 13:44:59.509451 EX_ROW_EN[1] = 0x0
2192 13:44:59.510066 LP4Y_EN = 0x0
2193 13:44:59.513220 WORK_FSP = 0x0
2194 13:44:59.513687 WL = 0x4
2195 13:44:59.516007 RL = 0x4
2196 13:44:59.516519 BL = 0x2
2197 13:44:59.519334 RPST = 0x0
2198 13:44:59.519766 RD_PRE = 0x0
2199 13:44:59.522658 WR_PRE = 0x1
2200 13:44:59.523094 WR_PST = 0x0
2201 13:44:59.525760 DBI_WR = 0x0
2202 13:44:59.526193 DBI_RD = 0x0
2203 13:44:59.529768 OTF = 0x1
2204 13:44:59.533253 ===================================
2205 13:44:59.535990 ===================================
2206 13:44:59.536669 ANA top config
2207 13:44:59.539488 ===================================
2208 13:44:59.543024 DLL_ASYNC_EN = 0
2209 13:44:59.546302 ALL_SLAVE_EN = 0
2210 13:44:59.546543 NEW_RANK_MODE = 1
2211 13:44:59.549802 DLL_IDLE_MODE = 1
2212 13:44:59.552602 LP45_APHY_COMB_EN = 1
2213 13:44:59.555950 TX_ODT_DIS = 1
2214 13:44:59.559698 NEW_8X_MODE = 1
2215 13:44:59.559852 ===================================
2216 13:44:59.562666 ===================================
2217 13:44:59.566157 data_rate = 2400
2218 13:44:59.569797 CKR = 1
2219 13:44:59.573203 DQ_P2S_RATIO = 8
2220 13:44:59.576522 ===================================
2221 13:44:59.579617 CA_P2S_RATIO = 8
2222 13:44:59.583091 DQ_CA_OPEN = 0
2223 13:44:59.583244 DQ_SEMI_OPEN = 0
2224 13:44:59.586096 CA_SEMI_OPEN = 0
2225 13:44:59.589686 CA_FULL_RATE = 0
2226 13:44:59.592590 DQ_CKDIV4_EN = 0
2227 13:44:59.596228 CA_CKDIV4_EN = 0
2228 13:44:59.599912 CA_PREDIV_EN = 0
2229 13:44:59.600061 PH8_DLY = 17
2230 13:44:59.603335 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 13:44:59.606351 DQ_AAMCK_DIV = 4
2232 13:44:59.609982 CA_AAMCK_DIV = 4
2233 13:44:59.612922 CA_ADMCK_DIV = 4
2234 13:44:59.616587 DQ_TRACK_CA_EN = 0
2235 13:44:59.616795 CA_PICK = 1200
2236 13:44:59.619687 CA_MCKIO = 1200
2237 13:44:59.623348 MCKIO_SEMI = 0
2238 13:44:59.626269 PLL_FREQ = 2366
2239 13:44:59.629843 DQ_UI_PI_RATIO = 32
2240 13:44:59.632744 CA_UI_PI_RATIO = 0
2241 13:44:59.636261 ===================================
2242 13:44:59.640016 ===================================
2243 13:44:59.642802 memory_type:LPDDR4
2244 13:44:59.643007 GP_NUM : 10
2245 13:44:59.646439 SRAM_EN : 1
2246 13:44:59.646668 MD32_EN : 0
2247 13:44:59.649160 ===================================
2248 13:44:59.653711 [ANA_INIT] >>>>>>>>>>>>>>
2249 13:44:59.656390 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 13:44:59.659779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 13:44:59.662823 ===================================
2252 13:44:59.666311 data_rate = 2400,PCW = 0X5b00
2253 13:44:59.669560 ===================================
2254 13:44:59.672744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 13:44:59.676464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 13:44:59.683232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 13:44:59.686577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 13:44:59.689392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 13:44:59.693145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 13:44:59.696062 [ANA_INIT] flow start
2261 13:44:59.699490 [ANA_INIT] PLL >>>>>>>>
2262 13:44:59.699648 [ANA_INIT] PLL <<<<<<<<
2263 13:44:59.703110 [ANA_INIT] MIDPI >>>>>>>>
2264 13:44:59.705874 [ANA_INIT] MIDPI <<<<<<<<
2265 13:44:59.709345 [ANA_INIT] DLL >>>>>>>>
2266 13:44:59.709476 [ANA_INIT] DLL <<<<<<<<
2267 13:44:59.712920 [ANA_INIT] flow end
2268 13:44:59.716594 ============ LP4 DIFF to SE enter ============
2269 13:44:59.719396 ============ LP4 DIFF to SE exit ============
2270 13:44:59.723157 [ANA_INIT] <<<<<<<<<<<<<
2271 13:44:59.726061 [Flow] Enable top DCM control >>>>>
2272 13:44:59.729765 [Flow] Enable top DCM control <<<<<
2273 13:44:59.733338 Enable DLL master slave shuffle
2274 13:44:59.736185 ==============================================================
2275 13:44:59.739711 Gating Mode config
2276 13:44:59.746160 ==============================================================
2277 13:44:59.746287 Config description:
2278 13:44:59.756517 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 13:44:59.763120 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 13:44:59.770086 SELPH_MODE 0: By rank 1: By Phase
2281 13:44:59.773268 ==============================================================
2282 13:44:59.776630 GAT_TRACK_EN = 1
2283 13:44:59.779866 RX_GATING_MODE = 2
2284 13:44:59.782934 RX_GATING_TRACK_MODE = 2
2285 13:44:59.786514 SELPH_MODE = 1
2286 13:44:59.789842 PICG_EARLY_EN = 1
2287 13:44:59.792821 VALID_LAT_VALUE = 1
2288 13:44:59.796594 ==============================================================
2289 13:44:59.799804 Enter into Gating configuration >>>>
2290 13:44:59.803321 Exit from Gating configuration <<<<
2291 13:44:59.806674 Enter into DVFS_PRE_config >>>>>
2292 13:44:59.816398 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 13:44:59.820085 Exit from DVFS_PRE_config <<<<<
2294 13:44:59.822947 Enter into PICG configuration >>>>
2295 13:44:59.826803 Exit from PICG configuration <<<<
2296 13:44:59.829678 [RX_INPUT] configuration >>>>>
2297 13:44:59.833302 [RX_INPUT] configuration <<<<<
2298 13:44:59.839878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 13:44:59.842848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 13:44:59.849686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 13:44:59.856908 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 13:44:59.863555 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 13:44:59.870356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 13:44:59.873222 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 13:44:59.876880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 13:44:59.879931 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 13:44:59.886557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 13:44:59.890183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 13:44:59.893087 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 13:44:59.896569 ===================================
2311 13:44:59.900322 LPDDR4 DRAM CONFIGURATION
2312 13:44:59.903629 ===================================
2313 13:44:59.903783 EX_ROW_EN[0] = 0x0
2314 13:44:59.906985 EX_ROW_EN[1] = 0x0
2315 13:44:59.907146 LP4Y_EN = 0x0
2316 13:44:59.910180 WORK_FSP = 0x0
2317 13:44:59.910338 WL = 0x4
2318 13:44:59.913426 RL = 0x4
2319 13:44:59.913580 BL = 0x2
2320 13:44:59.916416 RPST = 0x0
2321 13:44:59.916569 RD_PRE = 0x0
2322 13:44:59.919849 WR_PRE = 0x1
2323 13:44:59.920057 WR_PST = 0x0
2324 13:44:59.923716 DBI_WR = 0x0
2325 13:44:59.926828 DBI_RD = 0x0
2326 13:44:59.927035 OTF = 0x1
2327 13:44:59.930122 ===================================
2328 13:44:59.933552 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 13:44:59.936686 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 13:44:59.943468 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 13:44:59.946888 ===================================
2332 13:44:59.947046 LPDDR4 DRAM CONFIGURATION
2333 13:44:59.950139 ===================================
2334 13:44:59.953573 EX_ROW_EN[0] = 0x10
2335 13:44:59.957016 EX_ROW_EN[1] = 0x0
2336 13:44:59.957208 LP4Y_EN = 0x0
2337 13:44:59.960370 WORK_FSP = 0x0
2338 13:44:59.960577 WL = 0x4
2339 13:44:59.963306 RL = 0x4
2340 13:44:59.963464 BL = 0x2
2341 13:44:59.966961 RPST = 0x0
2342 13:44:59.967173 RD_PRE = 0x0
2343 13:44:59.970639 WR_PRE = 0x1
2344 13:44:59.970867 WR_PST = 0x0
2345 13:44:59.973468 DBI_WR = 0x0
2346 13:44:59.973759 DBI_RD = 0x0
2347 13:44:59.977498 OTF = 0x1
2348 13:44:59.980237 ===================================
2349 13:44:59.987171 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 13:44:59.987593 ==
2351 13:44:59.990690 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 13:44:59.993662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 13:44:59.994055 ==
2354 13:44:59.997531 [Duty_Offset_Calibration]
2355 13:44:59.997921 B0:2 B1:1 CA:1
2356 13:44:59.998229
2357 13:45:00.000263 [DutyScan_Calibration_Flow] k_type=0
2358 13:45:00.011499
2359 13:45:00.011983 ==CLK 0==
2360 13:45:00.013905 Final CLK duty delay cell = 0
2361 13:45:00.017320 [0] MAX Duty = 5187%(X100), DQS PI = 24
2362 13:45:00.020935 [0] MIN Duty = 4844%(X100), DQS PI = 48
2363 13:45:00.021377 [0] AVG Duty = 5015%(X100)
2364 13:45:00.024413
2365 13:45:00.024802 CH0 CLK Duty spec in!! Max-Min= 343%
2366 13:45:00.031187 [DutyScan_Calibration_Flow] ====Done====
2367 13:45:00.031576
2368 13:45:00.033824 [DutyScan_Calibration_Flow] k_type=1
2369 13:45:00.049529
2370 13:45:00.049817 ==DQS 0 ==
2371 13:45:00.052871 Final DQS duty delay cell = -4
2372 13:45:00.056398 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2373 13:45:00.058988 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2374 13:45:00.062327 [-4] AVG Duty = 4937%(X100)
2375 13:45:00.062712
2376 13:45:00.063018 ==DQS 1 ==
2377 13:45:00.065469 Final DQS duty delay cell = 0
2378 13:45:00.069290 [0] MAX Duty = 5156%(X100), DQS PI = 62
2379 13:45:00.072683 [0] MIN Duty = 5000%(X100), DQS PI = 32
2380 13:45:00.075840 [0] AVG Duty = 5078%(X100)
2381 13:45:00.076119
2382 13:45:00.079247 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2383 13:45:00.079574
2384 13:45:00.082521 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2385 13:45:00.085625 [DutyScan_Calibration_Flow] ====Done====
2386 13:45:00.086010
2387 13:45:00.089388 [DutyScan_Calibration_Flow] k_type=3
2388 13:45:00.106218
2389 13:45:00.106494 ==DQM 0 ==
2390 13:45:00.109758 Final DQM duty delay cell = 0
2391 13:45:00.112657 [0] MAX Duty = 5156%(X100), DQS PI = 30
2392 13:45:00.116210 [0] MIN Duty = 4875%(X100), DQS PI = 58
2393 13:45:00.116519 [0] AVG Duty = 5015%(X100)
2394 13:45:00.119545
2395 13:45:00.119820 ==DQM 1 ==
2396 13:45:00.123057 Final DQM duty delay cell = 0
2397 13:45:00.126125 [0] MAX Duty = 5093%(X100), DQS PI = 0
2398 13:45:00.129546 [0] MIN Duty = 5031%(X100), DQS PI = 14
2399 13:45:00.129854 [0] AVG Duty = 5062%(X100)
2400 13:45:00.130074
2401 13:45:00.133263 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2402 13:45:00.136095
2403 13:45:00.139391 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2404 13:45:00.142763 [DutyScan_Calibration_Flow] ====Done====
2405 13:45:00.143040
2406 13:45:00.146201 [DutyScan_Calibration_Flow] k_type=2
2407 13:45:00.162960
2408 13:45:00.163231 ==DQ 0 ==
2409 13:45:00.166199 Final DQ duty delay cell = 0
2410 13:45:00.169481 [0] MAX Duty = 5062%(X100), DQS PI = 32
2411 13:45:00.172517 [0] MIN Duty = 4844%(X100), DQS PI = 62
2412 13:45:00.172727 [0] AVG Duty = 4953%(X100)
2413 13:45:00.172894
2414 13:45:00.175798 ==DQ 1 ==
2415 13:45:00.179287 Final DQ duty delay cell = 0
2416 13:45:00.182418 [0] MAX Duty = 5093%(X100), DQS PI = 26
2417 13:45:00.185876 [0] MIN Duty = 4907%(X100), DQS PI = 36
2418 13:45:00.186088 [0] AVG Duty = 5000%(X100)
2419 13:45:00.186255
2420 13:45:00.189066 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2421 13:45:00.192278
2422 13:45:00.195490 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2423 13:45:00.199440 [DutyScan_Calibration_Flow] ====Done====
2424 13:45:00.199651 ==
2425 13:45:00.202589 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 13:45:00.205633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 13:45:00.205910 ==
2428 13:45:00.208993 [Duty_Offset_Calibration]
2429 13:45:00.209203 B0:1 B1:0 CA:0
2430 13:45:00.209370
2431 13:45:00.212261 [DutyScan_Calibration_Flow] k_type=0
2432 13:45:00.221577
2433 13:45:00.221787 ==CLK 0==
2434 13:45:00.225056 Final CLK duty delay cell = -4
2435 13:45:00.228492 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2436 13:45:00.231527 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2437 13:45:00.235272 [-4] AVG Duty = 4953%(X100)
2438 13:45:00.235482
2439 13:45:00.238697 CH1 CLK Duty spec in!! Max-Min= 156%
2440 13:45:00.241525 [DutyScan_Calibration_Flow] ====Done====
2441 13:45:00.241780
2442 13:45:00.245051 [DutyScan_Calibration_Flow] k_type=1
2443 13:45:00.261646
2444 13:45:00.262160 ==DQS 0 ==
2445 13:45:00.265280 Final DQS duty delay cell = 0
2446 13:45:00.268936 [0] MAX Duty = 5062%(X100), DQS PI = 22
2447 13:45:00.271587 [0] MIN Duty = 4844%(X100), DQS PI = 0
2448 13:45:00.272098 [0] AVG Duty = 4953%(X100)
2449 13:45:00.274853
2450 13:45:00.275411 ==DQS 1 ==
2451 13:45:00.278770 Final DQS duty delay cell = 0
2452 13:45:00.281339 [0] MAX Duty = 5187%(X100), DQS PI = 20
2453 13:45:00.284818 [0] MIN Duty = 4969%(X100), DQS PI = 8
2454 13:45:00.285235 [0] AVG Duty = 5078%(X100)
2455 13:45:00.288586
2456 13:45:00.291623 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2457 13:45:00.292155
2458 13:45:00.294878 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2459 13:45:00.298542 [DutyScan_Calibration_Flow] ====Done====
2460 13:45:00.299052
2461 13:45:00.301709 [DutyScan_Calibration_Flow] k_type=3
2462 13:45:00.317848
2463 13:45:00.318300 ==DQM 0 ==
2464 13:45:00.321617 Final DQM duty delay cell = 0
2465 13:45:00.324622 [0] MAX Duty = 5156%(X100), DQS PI = 6
2466 13:45:00.328124 [0] MIN Duty = 5031%(X100), DQS PI = 0
2467 13:45:00.328904 [0] AVG Duty = 5093%(X100)
2468 13:45:00.329343
2469 13:45:00.331419 ==DQM 1 ==
2470 13:45:00.334579 Final DQM duty delay cell = 0
2471 13:45:00.338575 [0] MAX Duty = 5031%(X100), DQS PI = 16
2472 13:45:00.341343 [0] MIN Duty = 4907%(X100), DQS PI = 36
2473 13:45:00.341764 [0] AVG Duty = 4969%(X100)
2474 13:45:00.342091
2475 13:45:00.348332 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2476 13:45:00.348829
2477 13:45:00.351177 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2478 13:45:00.354945 [DutyScan_Calibration_Flow] ====Done====
2479 13:45:00.355616
2480 13:45:00.358080 [DutyScan_Calibration_Flow] k_type=2
2481 13:45:00.374267
2482 13:45:00.374769 ==DQ 0 ==
2483 13:45:00.376986 Final DQ duty delay cell = -4
2484 13:45:00.380519 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2485 13:45:00.383855 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2486 13:45:00.387492 [-4] AVG Duty = 4984%(X100)
2487 13:45:00.388007
2488 13:45:00.388336 ==DQ 1 ==
2489 13:45:00.390078 Final DQ duty delay cell = 0
2490 13:45:00.393818 [0] MAX Duty = 5125%(X100), DQS PI = 20
2491 13:45:00.397066 [0] MIN Duty = 4969%(X100), DQS PI = 12
2492 13:45:00.397482 [0] AVG Duty = 5047%(X100)
2493 13:45:00.400587
2494 13:45:00.404037 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2495 13:45:00.404536
2496 13:45:00.406732 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2497 13:45:00.410644 [DutyScan_Calibration_Flow] ====Done====
2498 13:45:00.413925 nWR fixed to 30
2499 13:45:00.414342 [ModeRegInit_LP4] CH0 RK0
2500 13:45:00.417782 [ModeRegInit_LP4] CH0 RK1
2501 13:45:00.420501 [ModeRegInit_LP4] CH1 RK0
2502 13:45:00.424098 [ModeRegInit_LP4] CH1 RK1
2503 13:45:00.424562 match AC timing 7
2504 13:45:00.427838 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 13:45:00.433786 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 13:45:00.437181 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 13:45:00.440320 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 13:45:00.447457 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 13:45:00.447877 ==
2510 13:45:00.450478 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 13:45:00.453746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 13:45:00.454162 ==
2513 13:45:00.460599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 13:45:00.464169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 13:45:00.474256 [CA 0] Center 39 (8~70) winsize 63
2516 13:45:00.477550 [CA 1] Center 39 (8~70) winsize 63
2517 13:45:00.480994 [CA 2] Center 35 (5~66) winsize 62
2518 13:45:00.484037 [CA 3] Center 34 (4~65) winsize 62
2519 13:45:00.487643 [CA 4] Center 33 (3~64) winsize 62
2520 13:45:00.490522 [CA 5] Center 32 (3~62) winsize 60
2521 13:45:00.490944
2522 13:45:00.494129 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2523 13:45:00.494551
2524 13:45:00.497021 [CATrainingPosCal] consider 1 rank data
2525 13:45:00.500917 u2DelayCellTimex100 = 270/100 ps
2526 13:45:00.504149 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2527 13:45:00.507547 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2528 13:45:00.514540 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2529 13:45:00.517119 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2530 13:45:00.520941 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2531 13:45:00.524465 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2532 13:45:00.524886
2533 13:45:00.527600 CA PerBit enable=1, Macro0, CA PI delay=32
2534 13:45:00.528114
2535 13:45:00.530943 [CBTSetCACLKResult] CA Dly = 32
2536 13:45:00.531358 CS Dly: 6 (0~37)
2537 13:45:00.531685 ==
2538 13:45:00.533856 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 13:45:00.541125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 13:45:00.541597 ==
2541 13:45:00.544089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 13:45:00.550795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2543 13:45:00.559994 [CA 0] Center 38 (8~69) winsize 62
2544 13:45:00.563163 [CA 1] Center 38 (8~69) winsize 62
2545 13:45:00.566575 [CA 2] Center 35 (4~66) winsize 63
2546 13:45:00.569936 [CA 3] Center 34 (4~65) winsize 62
2547 13:45:00.573022 [CA 4] Center 33 (3~64) winsize 62
2548 13:45:00.575955 [CA 5] Center 32 (2~62) winsize 61
2549 13:45:00.576428
2550 13:45:00.579653 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 13:45:00.580067
2552 13:45:00.582752 [CATrainingPosCal] consider 2 rank data
2553 13:45:00.586259 u2DelayCellTimex100 = 270/100 ps
2554 13:45:00.589474 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2555 13:45:00.593079 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2556 13:45:00.599671 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2557 13:45:00.602585 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2558 13:45:00.606230 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2559 13:45:00.609873 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2560 13:45:00.610459
2561 13:45:00.613068 CA PerBit enable=1, Macro0, CA PI delay=32
2562 13:45:00.613673
2563 13:45:00.616332 [CBTSetCACLKResult] CA Dly = 32
2564 13:45:00.617043 CS Dly: 6 (0~38)
2565 13:45:00.617567
2566 13:45:00.619706 ----->DramcWriteLeveling(PI) begin...
2567 13:45:00.622902 ==
2568 13:45:00.623438 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 13:45:00.629704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 13:45:00.630318 ==
2571 13:45:00.633368 Write leveling (Byte 0): 33 => 33
2572 13:45:00.636140 Write leveling (Byte 1): 29 => 29
2573 13:45:00.636606 DramcWriteLeveling(PI) end<-----
2574 13:45:00.639852
2575 13:45:00.640267 ==
2576 13:45:00.643446 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 13:45:00.646628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 13:45:00.647150 ==
2579 13:45:00.649921 [Gating] SW mode calibration
2580 13:45:00.657033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 13:45:00.660475 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 13:45:00.667065 0 15 0 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
2583 13:45:00.670782 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2584 13:45:00.673297 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 13:45:00.680797 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 13:45:00.683260 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 13:45:00.686814 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 13:45:00.693725 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2589 13:45:00.696526 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (0 0) (1 0)
2590 13:45:00.700069 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2591 13:45:00.706829 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 13:45:00.710104 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 13:45:00.713752 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 13:45:00.716749 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 13:45:00.723564 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 13:45:00.726716 1 0 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2597 13:45:00.730054 1 0 28 | B1->B0 | 2828 4343 | 0 0 | (0 0) (1 1)
2598 13:45:00.736833 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2599 13:45:00.740071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 13:45:00.743486 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 13:45:00.750203 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 13:45:00.753342 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 13:45:00.756579 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 13:45:00.763687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 13:45:00.767119 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2606 13:45:00.770195 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 13:45:00.776863 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 13:45:00.780536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 13:45:00.783925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 13:45:00.790043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 13:45:00.793669 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 13:45:00.797180 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:45:00.800135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 13:45:00.807322 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 13:45:00.810863 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 13:45:00.813567 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 13:45:00.820559 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 13:45:00.823954 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 13:45:00.826880 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 13:45:00.833311 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 13:45:00.837174 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 13:45:00.840117 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2623 13:45:00.843619 Total UI for P1: 0, mck2ui 16
2624 13:45:00.847077 best dqsien dly found for B0: ( 1, 3, 26)
2625 13:45:00.853590 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 13:45:00.854038 Total UI for P1: 0, mck2ui 16
2627 13:45:00.860566 best dqsien dly found for B1: ( 1, 4, 0)
2628 13:45:00.863473 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2629 13:45:00.867051 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2630 13:45:00.867475
2631 13:45:00.870375 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2632 13:45:00.873511 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2633 13:45:00.876976 [Gating] SW calibration Done
2634 13:45:00.877414 ==
2635 13:45:00.879980 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 13:45:00.883442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 13:45:00.883882 ==
2638 13:45:00.886701 RX Vref Scan: 0
2639 13:45:00.887153
2640 13:45:00.887486 RX Vref 0 -> 0, step: 1
2641 13:45:00.887796
2642 13:45:00.890286 RX Delay -40 -> 252, step: 8
2643 13:45:00.893684 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2644 13:45:00.900160 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2645 13:45:00.903488 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2646 13:45:00.906913 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2647 13:45:00.910469 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2648 13:45:00.913470 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2649 13:45:00.917281 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2650 13:45:00.923489 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2651 13:45:00.927037 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2652 13:45:00.930765 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2653 13:45:00.933396 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2654 13:45:00.936909 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2655 13:45:00.943775 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2656 13:45:00.947165 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2657 13:45:00.950696 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2658 13:45:00.953501 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2659 13:45:00.953927 ==
2660 13:45:00.957047 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 13:45:00.963557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 13:45:00.963984 ==
2663 13:45:00.964320 DQS Delay:
2664 13:45:00.964684 DQS0 = 0, DQS1 = 0
2665 13:45:00.967024 DQM Delay:
2666 13:45:00.967444 DQM0 = 121, DQM1 = 113
2667 13:45:00.970823 DQ Delay:
2668 13:45:00.973633 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2669 13:45:00.977003 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2670 13:45:00.980606 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2671 13:45:00.983829 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2672 13:45:00.984265
2673 13:45:00.984735
2674 13:45:00.985156 ==
2675 13:45:00.987313 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 13:45:00.990545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 13:45:00.991078 ==
2678 13:45:00.991519
2679 13:45:00.993608
2680 13:45:00.994041 TX Vref Scan disable
2681 13:45:00.997304 == TX Byte 0 ==
2682 13:45:01.000703 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2683 13:45:01.004014 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2684 13:45:01.006930 == TX Byte 1 ==
2685 13:45:01.010492 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2686 13:45:01.013661 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2687 13:45:01.014201 ==
2688 13:45:01.017103 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 13:45:01.023852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 13:45:01.024412 ==
2691 13:45:01.035006 TX Vref=22, minBit 13, minWin=24, winSum=405
2692 13:45:01.037809 TX Vref=24, minBit 0, minWin=25, winSum=414
2693 13:45:01.041295 TX Vref=26, minBit 7, minWin=25, winSum=420
2694 13:45:01.044236 TX Vref=28, minBit 3, minWin=26, winSum=423
2695 13:45:01.047758 TX Vref=30, minBit 0, minWin=26, winSum=428
2696 13:45:01.054653 TX Vref=32, minBit 12, minWin=25, winSum=423
2697 13:45:01.058177 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2698 13:45:01.058597
2699 13:45:01.061024 Final TX Range 1 Vref 30
2700 13:45:01.061444
2701 13:45:01.061776 ==
2702 13:45:01.064631 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 13:45:01.068424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 13:45:01.068939 ==
2705 13:45:01.069272
2706 13:45:01.071041
2707 13:45:01.071456 TX Vref Scan disable
2708 13:45:01.074673 == TX Byte 0 ==
2709 13:45:01.078189 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2710 13:45:01.081681 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2711 13:45:01.084533 == TX Byte 1 ==
2712 13:45:01.087925 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2713 13:45:01.091486 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2714 13:45:01.091907
2715 13:45:01.095065 [DATLAT]
2716 13:45:01.095616 Freq=1200, CH0 RK0
2717 13:45:01.096091
2718 13:45:01.097765 DATLAT Default: 0xd
2719 13:45:01.098321 0, 0xFFFF, sum = 0
2720 13:45:01.101311 1, 0xFFFF, sum = 0
2721 13:45:01.101733 2, 0xFFFF, sum = 0
2722 13:45:01.104792 3, 0xFFFF, sum = 0
2723 13:45:01.105433 4, 0xFFFF, sum = 0
2724 13:45:01.108167 5, 0xFFFF, sum = 0
2725 13:45:01.108850 6, 0xFFFF, sum = 0
2726 13:45:01.111630 7, 0xFFFF, sum = 0
2727 13:45:01.112082 8, 0xFFFF, sum = 0
2728 13:45:01.114384 9, 0xFFFF, sum = 0
2729 13:45:01.118249 10, 0xFFFF, sum = 0
2730 13:45:01.118860 11, 0xFFFF, sum = 0
2731 13:45:01.121273 12, 0x0, sum = 1
2732 13:45:01.121729 13, 0x0, sum = 2
2733 13:45:01.122205 14, 0x0, sum = 3
2734 13:45:01.124319 15, 0x0, sum = 4
2735 13:45:01.124800 best_step = 13
2736 13:45:01.125129
2737 13:45:01.125438 ==
2738 13:45:01.127891 Dram Type= 6, Freq= 0, CH_0, rank 0
2739 13:45:01.134559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2740 13:45:01.135189 ==
2741 13:45:01.135618 RX Vref Scan: 1
2742 13:45:01.135935
2743 13:45:01.138329 Set Vref Range= 32 -> 127
2744 13:45:01.138747
2745 13:45:01.141587 RX Vref 32 -> 127, step: 1
2746 13:45:01.142005
2747 13:45:01.144850 RX Delay -13 -> 252, step: 4
2748 13:45:01.145271
2749 13:45:01.147873 Set Vref, RX VrefLevel [Byte0]: 32
2750 13:45:01.151290 [Byte1]: 32
2751 13:45:01.151710
2752 13:45:01.154802 Set Vref, RX VrefLevel [Byte0]: 33
2753 13:45:01.157656 [Byte1]: 33
2754 13:45:01.158076
2755 13:45:01.161118 Set Vref, RX VrefLevel [Byte0]: 34
2756 13:45:01.164617 [Byte1]: 34
2757 13:45:01.168889
2758 13:45:01.169313 Set Vref, RX VrefLevel [Byte0]: 35
2759 13:45:01.171794 [Byte1]: 35
2760 13:45:01.176758
2761 13:45:01.177213 Set Vref, RX VrefLevel [Byte0]: 36
2762 13:45:01.179659 [Byte1]: 36
2763 13:45:01.184944
2764 13:45:01.185457 Set Vref, RX VrefLevel [Byte0]: 37
2765 13:45:01.188002 [Byte1]: 37
2766 13:45:01.192857
2767 13:45:01.193498 Set Vref, RX VrefLevel [Byte0]: 38
2768 13:45:01.195402 [Byte1]: 38
2769 13:45:01.200417
2770 13:45:01.200905 Set Vref, RX VrefLevel [Byte0]: 39
2771 13:45:01.203472 [Byte1]: 39
2772 13:45:01.208376
2773 13:45:01.208996 Set Vref, RX VrefLevel [Byte0]: 40
2774 13:45:01.211701 [Byte1]: 40
2775 13:45:01.215854
2776 13:45:01.216272 Set Vref, RX VrefLevel [Byte0]: 41
2777 13:45:01.219335 [Byte1]: 41
2778 13:45:01.224111
2779 13:45:01.224616 Set Vref, RX VrefLevel [Byte0]: 42
2780 13:45:01.226867 [Byte1]: 42
2781 13:45:01.231462
2782 13:45:01.231999 Set Vref, RX VrefLevel [Byte0]: 43
2783 13:45:01.234815 [Byte1]: 43
2784 13:45:01.239662
2785 13:45:01.240092 Set Vref, RX VrefLevel [Byte0]: 44
2786 13:45:01.243307 [Byte1]: 44
2787 13:45:01.247802
2788 13:45:01.248245 Set Vref, RX VrefLevel [Byte0]: 45
2789 13:45:01.251154 [Byte1]: 45
2790 13:45:01.255546
2791 13:45:01.255844 Set Vref, RX VrefLevel [Byte0]: 46
2792 13:45:01.258790 [Byte1]: 46
2793 13:45:01.263055
2794 13:45:01.263357 Set Vref, RX VrefLevel [Byte0]: 47
2795 13:45:01.266636 [Byte1]: 47
2796 13:45:01.270796
2797 13:45:01.270977 Set Vref, RX VrefLevel [Byte0]: 48
2798 13:45:01.273971 [Byte1]: 48
2799 13:45:01.278636
2800 13:45:01.278874 Set Vref, RX VrefLevel [Byte0]: 49
2801 13:45:01.285344 [Byte1]: 49
2802 13:45:01.285603
2803 13:45:01.289012 Set Vref, RX VrefLevel [Byte0]: 50
2804 13:45:01.291862 [Byte1]: 50
2805 13:45:01.292190
2806 13:45:01.295622 Set Vref, RX VrefLevel [Byte0]: 51
2807 13:45:01.298962 [Byte1]: 51
2808 13:45:01.302434
2809 13:45:01.302755 Set Vref, RX VrefLevel [Byte0]: 52
2810 13:45:01.306071 [Byte1]: 52
2811 13:45:01.310396
2812 13:45:01.310922 Set Vref, RX VrefLevel [Byte0]: 53
2813 13:45:01.314103 [Byte1]: 53
2814 13:45:01.319096
2815 13:45:01.319608 Set Vref, RX VrefLevel [Byte0]: 54
2816 13:45:01.322382 [Byte1]: 54
2817 13:45:01.326206
2818 13:45:01.326651 Set Vref, RX VrefLevel [Byte0]: 55
2819 13:45:01.329615 [Byte1]: 55
2820 13:45:01.334440
2821 13:45:01.335025 Set Vref, RX VrefLevel [Byte0]: 56
2822 13:45:01.337319 [Byte1]: 56
2823 13:45:01.341894
2824 13:45:01.342410 Set Vref, RX VrefLevel [Byte0]: 57
2825 13:45:01.345155 [Byte1]: 57
2826 13:45:01.350223
2827 13:45:01.350644 Set Vref, RX VrefLevel [Byte0]: 58
2828 13:45:01.353683 [Byte1]: 58
2829 13:45:01.358091
2830 13:45:01.358717 Set Vref, RX VrefLevel [Byte0]: 59
2831 13:45:01.361671 [Byte1]: 59
2832 13:45:01.366042
2833 13:45:01.366662 Set Vref, RX VrefLevel [Byte0]: 60
2834 13:45:01.368920 [Byte1]: 60
2835 13:45:01.373754
2836 13:45:01.374106 Set Vref, RX VrefLevel [Byte0]: 61
2837 13:45:01.377075 [Byte1]: 61
2838 13:45:01.381508
2839 13:45:01.381803 Set Vref, RX VrefLevel [Byte0]: 62
2840 13:45:01.384771 [Byte1]: 62
2841 13:45:01.389297
2842 13:45:01.389749 Set Vref, RX VrefLevel [Byte0]: 63
2843 13:45:01.392719 [Byte1]: 63
2844 13:45:01.397419
2845 13:45:01.397714 Set Vref, RX VrefLevel [Byte0]: 64
2846 13:45:01.400724 [Byte1]: 64
2847 13:45:01.405220
2848 13:45:01.405518 Set Vref, RX VrefLevel [Byte0]: 65
2849 13:45:01.408664 [Byte1]: 65
2850 13:45:01.412805
2851 13:45:01.413279 Set Vref, RX VrefLevel [Byte0]: 66
2852 13:45:01.416322 [Byte1]: 66
2853 13:45:01.421667
2854 13:45:01.422146 Set Vref, RX VrefLevel [Byte0]: 67
2855 13:45:01.424407 [Byte1]: 67
2856 13:45:01.429200
2857 13:45:01.429582 Set Vref, RX VrefLevel [Byte0]: 68
2858 13:45:01.432657 [Byte1]: 68
2859 13:45:01.437088
2860 13:45:01.437480 Set Vref, RX VrefLevel [Byte0]: 69
2861 13:45:01.440284 [Byte1]: 69
2862 13:45:01.444889
2863 13:45:01.445273 Final RX Vref Byte 0 = 54 to rank0
2864 13:45:01.448662 Final RX Vref Byte 1 = 51 to rank0
2865 13:45:01.451587 Final RX Vref Byte 0 = 54 to rank1
2866 13:45:01.455057 Final RX Vref Byte 1 = 51 to rank1==
2867 13:45:01.457938 Dram Type= 6, Freq= 0, CH_0, rank 0
2868 13:45:01.464963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 13:45:01.465439 ==
2870 13:45:01.465824 DQS Delay:
2871 13:45:01.466122 DQS0 = 0, DQS1 = 0
2872 13:45:01.468471 DQM Delay:
2873 13:45:01.468875 DQM0 = 120, DQM1 = 112
2874 13:45:01.471308 DQ Delay:
2875 13:45:01.475251 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2876 13:45:01.477814 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2877 13:45:01.481470 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2878 13:45:01.484939 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2879 13:45:01.485451
2880 13:45:01.485947
2881 13:45:01.491196 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2882 13:45:01.494658 CH0 RK0: MR19=404, MR18=1710
2883 13:45:01.501385 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2884 13:45:01.501902
2885 13:45:01.504900 ----->DramcWriteLeveling(PI) begin...
2886 13:45:01.505307 ==
2887 13:45:01.508216 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 13:45:01.511184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 13:45:01.515196 ==
2890 13:45:01.515714 Write leveling (Byte 0): 37 => 37
2891 13:45:01.518247 Write leveling (Byte 1): 28 => 28
2892 13:45:01.521709 DramcWriteLeveling(PI) end<-----
2893 13:45:01.522091
2894 13:45:01.522392 ==
2895 13:45:01.525205 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 13:45:01.531400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 13:45:01.531789 ==
2898 13:45:01.532093 [Gating] SW mode calibration
2899 13:45:01.541454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2900 13:45:01.544776 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2901 13:45:01.548409 0 15 0 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
2902 13:45:01.554667 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 13:45:01.558128 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 13:45:01.561302 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 13:45:01.568404 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 13:45:01.571854 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 13:45:01.574920 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2908 13:45:01.582118 0 15 28 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)
2909 13:45:01.584793 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2910 13:45:01.588314 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 13:45:01.594500 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 13:45:01.598044 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 13:45:01.601673 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 13:45:01.608500 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 13:45:01.611917 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 13:45:01.614730 1 0 28 | B1->B0 | 3f3f 3e3e | 0 1 | (0 0) (0 0)
2917 13:45:01.621851 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 13:45:01.624618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 13:45:01.628260 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 13:45:01.631644 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 13:45:01.638403 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 13:45:01.641514 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 13:45:01.644876 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 13:45:01.651470 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2925 13:45:01.654920 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2926 13:45:01.658290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 13:45:01.664754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 13:45:01.668451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 13:45:01.671538 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 13:45:01.678260 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 13:45:01.681283 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 13:45:01.685082 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 13:45:01.691730 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 13:45:01.694648 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 13:45:01.698062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 13:45:01.704639 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 13:45:01.707578 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 13:45:01.711358 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 13:45:01.717661 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 13:45:01.721348 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2941 13:45:01.724940 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2942 13:45:01.727836 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 13:45:01.731575 Total UI for P1: 0, mck2ui 16
2944 13:45:01.734353 best dqsien dly found for B0: ( 1, 3, 30)
2945 13:45:01.738215 Total UI for P1: 0, mck2ui 16
2946 13:45:01.741084 best dqsien dly found for B1: ( 1, 3, 30)
2947 13:45:01.744640 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2948 13:45:01.748253 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2949 13:45:01.751170
2950 13:45:01.754812 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2951 13:45:01.757847 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2952 13:45:01.761397 [Gating] SW calibration Done
2953 13:45:01.761629 ==
2954 13:45:01.764800 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 13:45:01.768037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 13:45:01.768262 ==
2957 13:45:01.768469 RX Vref Scan: 0
2958 13:45:01.768647
2959 13:45:01.771383 RX Vref 0 -> 0, step: 1
2960 13:45:01.771699
2961 13:45:01.774485 RX Delay -40 -> 252, step: 8
2962 13:45:01.777816 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2963 13:45:01.781001 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2964 13:45:01.787730 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2965 13:45:01.791308 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2966 13:45:01.794645 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2967 13:45:01.797883 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2968 13:45:01.801443 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2969 13:45:01.808389 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2970 13:45:01.811233 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2971 13:45:01.814989 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2972 13:45:01.818081 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2973 13:45:01.821144 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2974 13:45:01.824528 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2975 13:45:01.831209 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2976 13:45:01.834729 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2977 13:45:01.838399 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2978 13:45:01.838567 ==
2979 13:45:01.841275 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 13:45:01.844948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 13:45:01.847933 ==
2982 13:45:01.848079 DQS Delay:
2983 13:45:01.848182 DQS0 = 0, DQS1 = 0
2984 13:45:01.851475 DQM Delay:
2985 13:45:01.851648 DQM0 = 122, DQM1 = 113
2986 13:45:01.854959 DQ Delay:
2987 13:45:01.858189 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2988 13:45:01.861860 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2989 13:45:01.864818 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2990 13:45:01.867824 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2991 13:45:01.868001
2992 13:45:01.868169
2993 13:45:01.868318 ==
2994 13:45:01.871417 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 13:45:01.874868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 13:45:01.874978 ==
2997 13:45:01.875071
2998 13:45:01.875159
2999 13:45:01.877984 TX Vref Scan disable
3000 13:45:01.881444 == TX Byte 0 ==
3001 13:45:01.884876 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
3002 13:45:01.887644 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
3003 13:45:01.891446 == TX Byte 1 ==
3004 13:45:01.894461 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3005 13:45:01.897892 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3006 13:45:01.898012 ==
3007 13:45:01.901472 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 13:45:01.904828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 13:45:01.908117 ==
3010 13:45:01.918813 TX Vref=22, minBit 5, minWin=25, winSum=424
3011 13:45:01.922328 TX Vref=24, minBit 13, minWin=25, winSum=422
3012 13:45:01.925668 TX Vref=26, minBit 0, minWin=26, winSum=425
3013 13:45:01.928986 TX Vref=28, minBit 7, minWin=26, winSum=434
3014 13:45:01.932517 TX Vref=30, minBit 5, minWin=26, winSum=433
3015 13:45:01.935781 TX Vref=32, minBit 0, minWin=27, winSum=436
3016 13:45:01.942476 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
3017 13:45:01.942588
3018 13:45:01.945884 Final TX Range 1 Vref 32
3019 13:45:01.945967
3020 13:45:01.946030 ==
3021 13:45:01.948787 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 13:45:01.952561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 13:45:01.952642 ==
3024 13:45:01.952706
3025 13:45:01.955633
3026 13:45:01.955713 TX Vref Scan disable
3027 13:45:01.959233 == TX Byte 0 ==
3028 13:45:01.962295 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
3029 13:45:01.965910 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
3030 13:45:01.969446 == TX Byte 1 ==
3031 13:45:01.972410 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3032 13:45:01.976065 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3033 13:45:01.976174
3034 13:45:01.979004 [DATLAT]
3035 13:45:01.979083 Freq=1200, CH0 RK1
3036 13:45:01.979157
3037 13:45:01.982588 DATLAT Default: 0xd
3038 13:45:01.982675 0, 0xFFFF, sum = 0
3039 13:45:01.986184 1, 0xFFFF, sum = 0
3040 13:45:01.986265 2, 0xFFFF, sum = 0
3041 13:45:01.989183 3, 0xFFFF, sum = 0
3042 13:45:01.989265 4, 0xFFFF, sum = 0
3043 13:45:01.992469 5, 0xFFFF, sum = 0
3044 13:45:01.992550 6, 0xFFFF, sum = 0
3045 13:45:01.995916 7, 0xFFFF, sum = 0
3046 13:45:01.998846 8, 0xFFFF, sum = 0
3047 13:45:01.998958 9, 0xFFFF, sum = 0
3048 13:45:02.002496 10, 0xFFFF, sum = 0
3049 13:45:02.002607 11, 0xFFFF, sum = 0
3050 13:45:02.006096 12, 0x0, sum = 1
3051 13:45:02.006195 13, 0x0, sum = 2
3052 13:45:02.006261 14, 0x0, sum = 3
3053 13:45:02.009060 15, 0x0, sum = 4
3054 13:45:02.009166 best_step = 13
3055 13:45:02.009261
3056 13:45:02.012757 ==
3057 13:45:02.012838 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 13:45:02.019407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 13:45:02.019489 ==
3060 13:45:02.019553 RX Vref Scan: 0
3061 13:45:02.019611
3062 13:45:02.022336 RX Vref 0 -> 0, step: 1
3063 13:45:02.022442
3064 13:45:02.026041 RX Delay -13 -> 252, step: 4
3065 13:45:02.029272 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3066 13:45:02.032638 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3067 13:45:02.038956 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3068 13:45:02.042889 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3069 13:45:02.046156 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3070 13:45:02.049371 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3071 13:45:02.052562 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3072 13:45:02.059372 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3073 13:45:02.062750 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3074 13:45:02.065861 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3075 13:45:02.069126 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3076 13:45:02.072865 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3077 13:45:02.079612 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3078 13:45:02.082360 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3079 13:45:02.086046 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3080 13:45:02.089839 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3081 13:45:02.090015 ==
3082 13:45:02.092454 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 13:45:02.099875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 13:45:02.100494 ==
3085 13:45:02.101022 DQS Delay:
3086 13:45:02.101442 DQS0 = 0, DQS1 = 0
3087 13:45:02.103251 DQM Delay:
3088 13:45:02.103814 DQM0 = 120, DQM1 = 111
3089 13:45:02.106197 DQ Delay:
3090 13:45:02.109258 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3091 13:45:02.113091 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3092 13:45:02.116718 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3093 13:45:02.119508 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3094 13:45:02.119924
3095 13:45:02.120249
3096 13:45:02.129292 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3097 13:45:02.129717 CH0 RK1: MR19=403, MR18=11F2
3098 13:45:02.136246 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3099 13:45:02.139020 [RxdqsGatingPostProcess] freq 1200
3100 13:45:02.146399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3101 13:45:02.149336 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 13:45:02.152844 best DQS1 dly(2T, 0.5T) = (0, 12)
3103 13:45:02.156261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 13:45:02.159140 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3105 13:45:02.159439 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 13:45:02.163190 best DQS1 dly(2T, 0.5T) = (0, 11)
3107 13:45:02.166409 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 13:45:02.169498 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3109 13:45:02.172928 Pre-setting of DQS Precalculation
3110 13:45:02.179536 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3111 13:45:02.179834 ==
3112 13:45:02.182848 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 13:45:02.186761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 13:45:02.187155 ==
3115 13:45:02.192726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 13:45:02.195993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 13:45:02.205987 [CA 0] Center 37 (7~68) winsize 62
3118 13:45:02.209318 [CA 1] Center 37 (7~68) winsize 62
3119 13:45:02.212387 [CA 2] Center 35 (5~65) winsize 61
3120 13:45:02.215956 [CA 3] Center 34 (4~64) winsize 61
3121 13:45:02.219692 [CA 4] Center 34 (4~64) winsize 61
3122 13:45:02.222843 [CA 5] Center 33 (3~63) winsize 61
3123 13:45:02.223323
3124 13:45:02.226344 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3125 13:45:02.226782
3126 13:45:02.229156 [CATrainingPosCal] consider 1 rank data
3127 13:45:02.232774 u2DelayCellTimex100 = 270/100 ps
3128 13:45:02.236280 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 13:45:02.239487 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 13:45:02.245884 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3131 13:45:02.249291 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 13:45:02.253040 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 13:45:02.256117 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3134 13:45:02.256680
3135 13:45:02.259534 CA PerBit enable=1, Macro0, CA PI delay=33
3136 13:45:02.259976
3137 13:45:02.262950 [CBTSetCACLKResult] CA Dly = 33
3138 13:45:02.263495 CS Dly: 7 (0~38)
3139 13:45:02.263966 ==
3140 13:45:02.265885 Dram Type= 6, Freq= 0, CH_1, rank 1
3141 13:45:02.272473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 13:45:02.272775 ==
3143 13:45:02.275802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 13:45:02.282636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3145 13:45:02.291516 [CA 0] Center 37 (7~68) winsize 62
3146 13:45:02.294924 [CA 1] Center 38 (8~69) winsize 62
3147 13:45:02.297835 [CA 2] Center 35 (5~66) winsize 62
3148 13:45:02.301209 [CA 3] Center 34 (4~65) winsize 62
3149 13:45:02.304851 [CA 4] Center 34 (4~65) winsize 62
3150 13:45:02.308405 [CA 5] Center 34 (4~64) winsize 61
3151 13:45:02.308584
3152 13:45:02.311546 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3153 13:45:02.311724
3154 13:45:02.315082 [CATrainingPosCal] consider 2 rank data
3155 13:45:02.318109 u2DelayCellTimex100 = 270/100 ps
3156 13:45:02.321654 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 13:45:02.324856 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3158 13:45:02.331326 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3159 13:45:02.334498 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 13:45:02.338291 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 13:45:02.341809 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3162 13:45:02.342050
3163 13:45:02.344750 CA PerBit enable=1, Macro0, CA PI delay=33
3164 13:45:02.345054
3165 13:45:02.348466 [CBTSetCACLKResult] CA Dly = 33
3166 13:45:02.348774 CS Dly: 8 (0~41)
3167 13:45:02.348973
3168 13:45:02.351302 ----->DramcWriteLeveling(PI) begin...
3169 13:45:02.354797 ==
3170 13:45:02.355167 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 13:45:02.361577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 13:45:02.361834 ==
3173 13:45:02.365241 Write leveling (Byte 0): 25 => 25
3174 13:45:02.368023 Write leveling (Byte 1): 28 => 28
3175 13:45:02.368274 DramcWriteLeveling(PI) end<-----
3176 13:45:02.371388
3177 13:45:02.371639 ==
3178 13:45:02.375106 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 13:45:02.377959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 13:45:02.378226 ==
3181 13:45:02.381715 [Gating] SW mode calibration
3182 13:45:02.388618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3183 13:45:02.391358 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3184 13:45:02.398004 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 13:45:02.401596 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 13:45:02.405205 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 13:45:02.411692 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 13:45:02.415287 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 13:45:02.418102 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3190 13:45:02.424511 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
3191 13:45:02.428232 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3192 13:45:02.431888 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 13:45:02.438435 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 13:45:02.441759 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 13:45:02.445161 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 13:45:02.451762 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 13:45:02.454664 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 13:45:02.457864 1 0 24 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
3199 13:45:02.464964 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 13:45:02.468575 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 13:45:02.471683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 13:45:02.475263 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 13:45:02.481576 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 13:45:02.485475 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 13:45:02.488428 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 13:45:02.495122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3207 13:45:02.498512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 13:45:02.501577 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 13:45:02.508764 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 13:45:02.511724 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 13:45:02.515384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 13:45:02.521941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 13:45:02.524718 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 13:45:02.528264 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 13:45:02.534725 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 13:45:02.538426 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 13:45:02.541407 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 13:45:02.545148 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 13:45:02.551794 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 13:45:02.555309 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 13:45:02.558620 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 13:45:02.565159 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 13:45:02.568487 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 13:45:02.571691 Total UI for P1: 0, mck2ui 16
3225 13:45:02.575498 best dqsien dly found for B0: ( 1, 3, 24)
3226 13:45:02.578459 Total UI for P1: 0, mck2ui 16
3227 13:45:02.581848 best dqsien dly found for B1: ( 1, 3, 24)
3228 13:45:02.585207 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3229 13:45:02.588607 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3230 13:45:02.588786
3231 13:45:02.592211 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3232 13:45:02.595201 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3233 13:45:02.598994 [Gating] SW calibration Done
3234 13:45:02.599157 ==
3235 13:45:02.602377 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 13:45:02.605078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 13:45:02.605269 ==
3238 13:45:02.609009 RX Vref Scan: 0
3239 13:45:02.609223
3240 13:45:02.611869 RX Vref 0 -> 0, step: 1
3241 13:45:02.612089
3242 13:45:02.612265 RX Delay -40 -> 252, step: 8
3243 13:45:02.618430 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3244 13:45:02.622091 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3245 13:45:02.625715 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3246 13:45:02.628603 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3247 13:45:02.632171 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3248 13:45:02.638867 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3249 13:45:02.642465 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3250 13:45:02.645858 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3251 13:45:02.648621 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3252 13:45:02.652301 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3253 13:45:02.658872 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3254 13:45:02.662383 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3255 13:45:02.665855 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3256 13:45:02.668661 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3257 13:45:02.672205 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3258 13:45:02.679329 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3259 13:45:02.679626 ==
3260 13:45:02.682296 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 13:45:02.685695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 13:45:02.686114 ==
3263 13:45:02.686442 DQS Delay:
3264 13:45:02.688988 DQS0 = 0, DQS1 = 0
3265 13:45:02.689527 DQM Delay:
3266 13:45:02.692799 DQM0 = 119, DQM1 = 116
3267 13:45:02.693253 DQ Delay:
3268 13:45:02.695875 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3269 13:45:02.699470 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3270 13:45:02.702340 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3271 13:45:02.705757 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3272 13:45:02.706211
3273 13:45:02.706545
3274 13:45:02.708922 ==
3275 13:45:02.709490 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 13:45:02.715696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 13:45:02.716124 ==
3278 13:45:02.716508
3279 13:45:02.716888
3280 13:45:02.719485 TX Vref Scan disable
3281 13:45:02.719925 == TX Byte 0 ==
3282 13:45:02.722757 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3283 13:45:02.729184 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3284 13:45:02.729696 == TX Byte 1 ==
3285 13:45:02.732181 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 13:45:02.739360 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 13:45:02.739788 ==
3288 13:45:02.742048 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 13:45:02.745478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 13:45:02.746077 ==
3291 13:45:02.757640 TX Vref=22, minBit 9, minWin=24, winSum=409
3292 13:45:02.761330 TX Vref=24, minBit 9, minWin=25, winSum=415
3293 13:45:02.764186 TX Vref=26, minBit 9, minWin=24, winSum=422
3294 13:45:02.767655 TX Vref=28, minBit 1, minWin=26, winSum=425
3295 13:45:02.771260 TX Vref=30, minBit 3, minWin=26, winSum=431
3296 13:45:02.774620 TX Vref=32, minBit 9, minWin=26, winSum=431
3297 13:45:02.780886 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 30
3298 13:45:02.781331
3299 13:45:02.784624 Final TX Range 1 Vref 30
3300 13:45:02.785064
3301 13:45:02.785425 ==
3302 13:45:02.787562 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 13:45:02.791144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 13:45:02.791571 ==
3305 13:45:02.791904
3306 13:45:02.792211
3307 13:45:02.794734 TX Vref Scan disable
3308 13:45:02.797896 == TX Byte 0 ==
3309 13:45:02.801217 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3310 13:45:02.804929 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3311 13:45:02.808233 == TX Byte 1 ==
3312 13:45:02.811238 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3313 13:45:02.815006 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3314 13:45:02.815525
3315 13:45:02.818009 [DATLAT]
3316 13:45:02.818435 Freq=1200, CH1 RK0
3317 13:45:02.818840
3318 13:45:02.821181 DATLAT Default: 0xd
3319 13:45:02.821603 0, 0xFFFF, sum = 0
3320 13:45:02.824789 1, 0xFFFF, sum = 0
3321 13:45:02.825220 2, 0xFFFF, sum = 0
3322 13:45:02.828320 3, 0xFFFF, sum = 0
3323 13:45:02.828804 4, 0xFFFF, sum = 0
3324 13:45:02.831487 5, 0xFFFF, sum = 0
3325 13:45:02.832012 6, 0xFFFF, sum = 0
3326 13:45:02.834684 7, 0xFFFF, sum = 0
3327 13:45:02.835113 8, 0xFFFF, sum = 0
3328 13:45:02.837979 9, 0xFFFF, sum = 0
3329 13:45:02.838410 10, 0xFFFF, sum = 0
3330 13:45:02.840964 11, 0xFFFF, sum = 0
3331 13:45:02.841536 12, 0x0, sum = 1
3332 13:45:02.844618 13, 0x0, sum = 2
3333 13:45:02.845014 14, 0x0, sum = 3
3334 13:45:02.848004 15, 0x0, sum = 4
3335 13:45:02.848477 best_step = 13
3336 13:45:02.848824
3337 13:45:02.849136 ==
3338 13:45:02.851525 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 13:45:02.858099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 13:45:02.858723 ==
3341 13:45:02.859179 RX Vref Scan: 1
3342 13:45:02.859641
3343 13:45:02.861172 Set Vref Range= 32 -> 127
3344 13:45:02.861576
3345 13:45:02.864550 RX Vref 32 -> 127, step: 1
3346 13:45:02.864972
3347 13:45:02.865303 RX Delay -5 -> 252, step: 4
3348 13:45:02.865651
3349 13:45:02.867939 Set Vref, RX VrefLevel [Byte0]: 32
3350 13:45:02.871535 [Byte1]: 32
3351 13:45:02.875637
3352 13:45:02.876061 Set Vref, RX VrefLevel [Byte0]: 33
3353 13:45:02.879202 [Byte1]: 33
3354 13:45:02.883864
3355 13:45:02.884291 Set Vref, RX VrefLevel [Byte0]: 34
3356 13:45:02.886868 [Byte1]: 34
3357 13:45:02.891717
3358 13:45:02.892142 Set Vref, RX VrefLevel [Byte0]: 35
3359 13:45:02.894504 [Byte1]: 35
3360 13:45:02.899473
3361 13:45:02.899917 Set Vref, RX VrefLevel [Byte0]: 36
3362 13:45:02.902321 [Byte1]: 36
3363 13:45:02.907442
3364 13:45:02.907865 Set Vref, RX VrefLevel [Byte0]: 37
3365 13:45:02.910393 [Byte1]: 37
3366 13:45:02.914639
3367 13:45:02.914939 Set Vref, RX VrefLevel [Byte0]: 38
3368 13:45:02.918170 [Byte1]: 38
3369 13:45:02.922376
3370 13:45:02.922604 Set Vref, RX VrefLevel [Byte0]: 39
3371 13:45:02.926081 [Byte1]: 39
3372 13:45:02.930445
3373 13:45:02.930598 Set Vref, RX VrefLevel [Byte0]: 40
3374 13:45:02.933901 [Byte1]: 40
3375 13:45:02.938138
3376 13:45:02.938294 Set Vref, RX VrefLevel [Byte0]: 41
3377 13:45:02.941690 [Byte1]: 41
3378 13:45:02.946058
3379 13:45:02.946209 Set Vref, RX VrefLevel [Byte0]: 42
3380 13:45:02.949513 [Byte1]: 42
3381 13:45:02.954296
3382 13:45:02.954447 Set Vref, RX VrefLevel [Byte0]: 43
3383 13:45:02.957077 [Byte1]: 43
3384 13:45:02.961838
3385 13:45:02.962063 Set Vref, RX VrefLevel [Byte0]: 44
3386 13:45:02.964962 [Byte1]: 44
3387 13:45:02.970122
3388 13:45:02.970419 Set Vref, RX VrefLevel [Byte0]: 45
3389 13:45:02.973465 [Byte1]: 45
3390 13:45:02.977628
3391 13:45:02.978017 Set Vref, RX VrefLevel [Byte0]: 46
3392 13:45:02.981371 [Byte1]: 46
3393 13:45:02.985898
3394 13:45:02.986354 Set Vref, RX VrefLevel [Byte0]: 47
3395 13:45:02.989097 [Byte1]: 47
3396 13:45:02.993503
3397 13:45:02.993940 Set Vref, RX VrefLevel [Byte0]: 48
3398 13:45:02.996963 [Byte1]: 48
3399 13:45:03.001316
3400 13:45:03.001755 Set Vref, RX VrefLevel [Byte0]: 49
3401 13:45:03.004713 [Byte1]: 49
3402 13:45:03.009293
3403 13:45:03.009715 Set Vref, RX VrefLevel [Byte0]: 50
3404 13:45:03.012179 [Byte1]: 50
3405 13:45:03.017098
3406 13:45:03.017747 Set Vref, RX VrefLevel [Byte0]: 51
3407 13:45:03.020639 [Byte1]: 51
3408 13:45:03.024968
3409 13:45:03.025260 Set Vref, RX VrefLevel [Byte0]: 52
3410 13:45:03.028472 [Byte1]: 52
3411 13:45:03.032613
3412 13:45:03.032833 Set Vref, RX VrefLevel [Byte0]: 53
3413 13:45:03.035569 [Byte1]: 53
3414 13:45:03.040569
3415 13:45:03.040789 Set Vref, RX VrefLevel [Byte0]: 54
3416 13:45:03.043393 [Byte1]: 54
3417 13:45:03.048061
3418 13:45:03.048283 Set Vref, RX VrefLevel [Byte0]: 55
3419 13:45:03.051664 [Byte1]: 55
3420 13:45:03.055892
3421 13:45:03.056204 Set Vref, RX VrefLevel [Byte0]: 56
3422 13:45:03.059502 [Byte1]: 56
3423 13:45:03.063743
3424 13:45:03.063983 Set Vref, RX VrefLevel [Byte0]: 57
3425 13:45:03.067221 [Byte1]: 57
3426 13:45:03.071469
3427 13:45:03.071691 Set Vref, RX VrefLevel [Byte0]: 58
3428 13:45:03.074818 [Byte1]: 58
3429 13:45:03.079795
3430 13:45:03.080005 Set Vref, RX VrefLevel [Byte0]: 59
3431 13:45:03.082763 [Byte1]: 59
3432 13:45:03.087876
3433 13:45:03.088132 Set Vref, RX VrefLevel [Byte0]: 60
3434 13:45:03.090719 [Byte1]: 60
3435 13:45:03.095310
3436 13:45:03.095599 Set Vref, RX VrefLevel [Byte0]: 61
3437 13:45:03.098579 [Byte1]: 61
3438 13:45:03.103187
3439 13:45:03.103416 Set Vref, RX VrefLevel [Byte0]: 62
3440 13:45:03.106516 [Byte1]: 62
3441 13:45:03.111379
3442 13:45:03.111601 Set Vref, RX VrefLevel [Byte0]: 63
3443 13:45:03.114086 [Byte1]: 63
3444 13:45:03.118858
3445 13:45:03.119078 Set Vref, RX VrefLevel [Byte0]: 64
3446 13:45:03.122206 [Byte1]: 64
3447 13:45:03.126819
3448 13:45:03.127040 Set Vref, RX VrefLevel [Byte0]: 65
3449 13:45:03.129963 [Byte1]: 65
3450 13:45:03.134415
3451 13:45:03.134644 Set Vref, RX VrefLevel [Byte0]: 66
3452 13:45:03.138068 [Byte1]: 66
3453 13:45:03.142149
3454 13:45:03.142481 Set Vref, RX VrefLevel [Byte0]: 67
3455 13:45:03.145709 [Byte1]: 67
3456 13:45:03.150025
3457 13:45:03.150252 Set Vref, RX VrefLevel [Byte0]: 68
3458 13:45:03.153495 [Byte1]: 68
3459 13:45:03.157715
3460 13:45:03.157825 Set Vref, RX VrefLevel [Byte0]: 69
3461 13:45:03.161198 [Byte1]: 69
3462 13:45:03.166184
3463 13:45:03.166268 Final RX Vref Byte 0 = 56 to rank0
3464 13:45:03.169219 Final RX Vref Byte 1 = 53 to rank0
3465 13:45:03.172710 Final RX Vref Byte 0 = 56 to rank1
3466 13:45:03.175838 Final RX Vref Byte 1 = 53 to rank1==
3467 13:45:03.179261 Dram Type= 6, Freq= 0, CH_1, rank 0
3468 13:45:03.182692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 13:45:03.186276 ==
3470 13:45:03.186376 DQS Delay:
3471 13:45:03.186466 DQS0 = 0, DQS1 = 0
3472 13:45:03.189123 DQM Delay:
3473 13:45:03.189217 DQM0 = 120, DQM1 = 117
3474 13:45:03.192656 DQ Delay:
3475 13:45:03.196205 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3476 13:45:03.199074 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =122
3477 13:45:03.202558 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3478 13:45:03.206132 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3479 13:45:03.206206
3480 13:45:03.206269
3481 13:45:03.213062 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3482 13:45:03.216244 CH1 RK0: MR19=304, MR18=FF12
3483 13:45:03.222699 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3484 13:45:03.222848
3485 13:45:03.226250 ----->DramcWriteLeveling(PI) begin...
3486 13:45:03.226413 ==
3487 13:45:03.229893 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 13:45:03.233289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 13:45:03.233470 ==
3490 13:45:03.235997 Write leveling (Byte 0): 26 => 26
3491 13:45:03.239978 Write leveling (Byte 1): 29 => 29
3492 13:45:03.243227 DramcWriteLeveling(PI) end<-----
3493 13:45:03.243397
3494 13:45:03.243531 ==
3495 13:45:03.246259 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 13:45:03.250049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 13:45:03.253199 ==
3498 13:45:03.253451 [Gating] SW mode calibration
3499 13:45:03.263004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3500 13:45:03.266589 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3501 13:45:03.270061 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 13:45:03.276662 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 13:45:03.280159 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 13:45:03.283467 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 13:45:03.289502 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 13:45:03.292944 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 13:45:03.296353 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (0 1) (1 0)
3508 13:45:03.303501 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3509 13:45:03.306300 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 13:45:03.309822 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 13:45:03.316792 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 13:45:03.319647 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 13:45:03.323159 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 13:45:03.330170 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3515 13:45:03.332924 1 0 24 | B1->B0 | 4242 2c2c | 0 0 | (1 1) (0 0)
3516 13:45:03.336359 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3517 13:45:03.339888 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 13:45:03.346184 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 13:45:03.350124 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 13:45:03.353062 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 13:45:03.360194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 13:45:03.362911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3523 13:45:03.366385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3524 13:45:03.373382 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3525 13:45:03.376297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 13:45:03.379429 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 13:45:03.386304 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 13:45:03.389671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 13:45:03.392968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 13:45:03.399819 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 13:45:03.402940 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 13:45:03.406340 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 13:45:03.412677 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 13:45:03.416116 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 13:45:03.419445 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:45:03.425949 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:45:03.429486 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 13:45:03.432989 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3539 13:45:03.439354 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3540 13:45:03.442890 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3541 13:45:03.445688 Total UI for P1: 0, mck2ui 16
3542 13:45:03.449318 best dqsien dly found for B1: ( 1, 3, 22)
3543 13:45:03.452884 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 13:45:03.456289 Total UI for P1: 0, mck2ui 16
3545 13:45:03.459017 best dqsien dly found for B0: ( 1, 3, 28)
3546 13:45:03.462482 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3547 13:45:03.466167 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3548 13:45:03.466577
3549 13:45:03.469655 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3550 13:45:03.475974 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3551 13:45:03.476279 [Gating] SW calibration Done
3552 13:45:03.476561 ==
3553 13:45:03.479374 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 13:45:03.486192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 13:45:03.486498 ==
3556 13:45:03.486739 RX Vref Scan: 0
3557 13:45:03.486960
3558 13:45:03.489411 RX Vref 0 -> 0, step: 1
3559 13:45:03.489752
3560 13:45:03.493096 RX Delay -40 -> 252, step: 8
3561 13:45:03.496308 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3562 13:45:03.499571 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3563 13:45:03.502809 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3564 13:45:03.505741 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3565 13:45:03.512410 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3566 13:45:03.516109 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3567 13:45:03.518888 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3568 13:45:03.522304 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3569 13:45:03.525668 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3570 13:45:03.532543 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3571 13:45:03.536074 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3572 13:45:03.538749 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3573 13:45:03.542155 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3574 13:45:03.549205 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3575 13:45:03.552138 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3576 13:45:03.555953 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3577 13:45:03.556410 ==
3578 13:45:03.559438 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 13:45:03.562937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 13:45:03.563358 ==
3581 13:45:03.566416 DQS Delay:
3582 13:45:03.567318 DQS0 = 0, DQS1 = 0
3583 13:45:03.569279 DQM Delay:
3584 13:45:03.569983 DQM0 = 120, DQM1 = 117
3585 13:45:03.570775 DQ Delay:
3586 13:45:03.572336 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3587 13:45:03.579442 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3588 13:45:03.582188 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3589 13:45:03.585572 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3590 13:45:03.586243
3591 13:45:03.586804
3592 13:45:03.587319 ==
3593 13:45:03.589220 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 13:45:03.592049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 13:45:03.592381 ==
3596 13:45:03.592695
3597 13:45:03.592987
3598 13:45:03.595552 TX Vref Scan disable
3599 13:45:03.598641 == TX Byte 0 ==
3600 13:45:03.602273 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 13:45:03.605628 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 13:45:03.608957 == TX Byte 1 ==
3603 13:45:03.612464 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 13:45:03.615220 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 13:45:03.615463 ==
3606 13:45:03.618369 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 13:45:03.624992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 13:45:03.625232 ==
3609 13:45:03.635398 TX Vref=22, minBit 9, minWin=25, winSum=419
3610 13:45:03.638600 TX Vref=24, minBit 9, minWin=25, winSum=424
3611 13:45:03.642157 TX Vref=26, minBit 10, minWin=25, winSum=427
3612 13:45:03.645871 TX Vref=28, minBit 2, minWin=26, winSum=431
3613 13:45:03.648618 TX Vref=30, minBit 8, minWin=26, winSum=437
3614 13:45:03.655520 TX Vref=32, minBit 9, minWin=26, winSum=433
3615 13:45:03.658326 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30
3616 13:45:03.658580
3617 13:45:03.661861 Final TX Range 1 Vref 30
3618 13:45:03.662041
3619 13:45:03.662188 ==
3620 13:45:03.665420 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 13:45:03.668219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 13:45:03.671554 ==
3623 13:45:03.671738
3624 13:45:03.671886
3625 13:45:03.672025 TX Vref Scan disable
3626 13:45:03.675089 == TX Byte 0 ==
3627 13:45:03.678373 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3628 13:45:03.681701 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3629 13:45:03.685385 == TX Byte 1 ==
3630 13:45:03.688841 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3631 13:45:03.695393 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3632 13:45:03.695640
3633 13:45:03.695855 [DATLAT]
3634 13:45:03.696060 Freq=1200, CH1 RK1
3635 13:45:03.696261
3636 13:45:03.698230 DATLAT Default: 0xd
3637 13:45:03.698497 0, 0xFFFF, sum = 0
3638 13:45:03.701617 1, 0xFFFF, sum = 0
3639 13:45:03.701810 2, 0xFFFF, sum = 0
3640 13:45:03.705160 3, 0xFFFF, sum = 0
3641 13:45:03.708626 4, 0xFFFF, sum = 0
3642 13:45:03.708734 5, 0xFFFF, sum = 0
3643 13:45:03.712111 6, 0xFFFF, sum = 0
3644 13:45:03.712210 7, 0xFFFF, sum = 0
3645 13:45:03.714881 8, 0xFFFF, sum = 0
3646 13:45:03.714968 9, 0xFFFF, sum = 0
3647 13:45:03.718228 10, 0xFFFF, sum = 0
3648 13:45:03.718312 11, 0xFFFF, sum = 0
3649 13:45:03.722399 12, 0x0, sum = 1
3650 13:45:03.722875 13, 0x0, sum = 2
3651 13:45:03.725276 14, 0x0, sum = 3
3652 13:45:03.725753 15, 0x0, sum = 4
3653 13:45:03.726096 best_step = 13
3654 13:45:03.728498
3655 13:45:03.729056 ==
3656 13:45:03.731932 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 13:45:03.735515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 13:45:03.736088 ==
3659 13:45:03.736502 RX Vref Scan: 0
3660 13:45:03.736987
3661 13:45:03.738482 RX Vref 0 -> 0, step: 1
3662 13:45:03.738920
3663 13:45:03.741809 RX Delay -5 -> 252, step: 4
3664 13:45:03.744946 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3665 13:45:03.751595 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3666 13:45:03.755100 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3667 13:45:03.758577 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3668 13:45:03.761828 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3669 13:45:03.764721 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3670 13:45:03.771193 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3671 13:45:03.774904 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3672 13:45:03.778397 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3673 13:45:03.781189 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3674 13:45:03.784642 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3675 13:45:03.791287 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3676 13:45:03.794755 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3677 13:45:03.798447 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3678 13:45:03.801471 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3679 13:45:03.805089 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3680 13:45:03.807755 ==
3681 13:45:03.811386 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 13:45:03.815128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 13:45:03.815259 ==
3684 13:45:03.815361 DQS Delay:
3685 13:45:03.817865 DQS0 = 0, DQS1 = 0
3686 13:45:03.817993 DQM Delay:
3687 13:45:03.821275 DQM0 = 120, DQM1 = 118
3688 13:45:03.821436 DQ Delay:
3689 13:45:03.824933 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3690 13:45:03.828126 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3691 13:45:03.831334 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3692 13:45:03.834795 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3693 13:45:03.834983
3694 13:45:03.835132
3695 13:45:03.844474 [DQSOSCAuto] RK1, (LSB)MR18= 0x13ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 402 ps
3696 13:45:03.847716 CH1 RK1: MR19=403, MR18=13EF
3697 13:45:03.851189 CH1_RK1: MR19=0x403, MR18=0x13EF, DQSOSC=402, MR23=63, INC=40, DEC=27
3698 13:45:03.854426 [RxdqsGatingPostProcess] freq 1200
3699 13:45:03.861330 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3700 13:45:03.864461 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 13:45:03.868118 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 13:45:03.871413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 13:45:03.874348 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 13:45:03.877737 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 13:45:03.881439 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 13:45:03.884953 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 13:45:03.887899 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 13:45:03.891524 Pre-setting of DQS Precalculation
3709 13:45:03.895014 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3710 13:45:03.901025 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3711 13:45:03.907658 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3712 13:45:03.908085
3713 13:45:03.911181
3714 13:45:03.911708 [Calibration Summary] 2400 Mbps
3715 13:45:03.914793 CH 0, Rank 0
3716 13:45:03.915231 SW Impedance : PASS
3717 13:45:03.917597 DUTY Scan : NO K
3718 13:45:03.921178 ZQ Calibration : PASS
3719 13:45:03.921739 Jitter Meter : NO K
3720 13:45:03.924870 CBT Training : PASS
3721 13:45:03.927772 Write leveling : PASS
3722 13:45:03.928207 RX DQS gating : PASS
3723 13:45:03.931460 RX DQ/DQS(RDDQC) : PASS
3724 13:45:03.934801 TX DQ/DQS : PASS
3725 13:45:03.935252 RX DATLAT : PASS
3726 13:45:03.937591 RX DQ/DQS(Engine): PASS
3727 13:45:03.938068 TX OE : NO K
3728 13:45:03.940856 All Pass.
3729 13:45:03.941373
3730 13:45:03.941705 CH 0, Rank 1
3731 13:45:03.945006 SW Impedance : PASS
3732 13:45:03.945432 DUTY Scan : NO K
3733 13:45:03.947704 ZQ Calibration : PASS
3734 13:45:03.951407 Jitter Meter : NO K
3735 13:45:03.951822 CBT Training : PASS
3736 13:45:03.954647 Write leveling : PASS
3737 13:45:03.958297 RX DQS gating : PASS
3738 13:45:03.958711 RX DQ/DQS(RDDQC) : PASS
3739 13:45:03.961152 TX DQ/DQS : PASS
3740 13:45:03.964456 RX DATLAT : PASS
3741 13:45:03.964866 RX DQ/DQS(Engine): PASS
3742 13:45:03.967728 TX OE : NO K
3743 13:45:03.968142 All Pass.
3744 13:45:03.968530
3745 13:45:03.971519 CH 1, Rank 0
3746 13:45:03.971934 SW Impedance : PASS
3747 13:45:03.975015 DUTY Scan : NO K
3748 13:45:03.978062 ZQ Calibration : PASS
3749 13:45:03.978480 Jitter Meter : NO K
3750 13:45:03.981031 CBT Training : PASS
3751 13:45:03.981444 Write leveling : PASS
3752 13:45:03.984642 RX DQS gating : PASS
3753 13:45:03.988067 RX DQ/DQS(RDDQC) : PASS
3754 13:45:03.988675 TX DQ/DQS : PASS
3755 13:45:03.990908 RX DATLAT : PASS
3756 13:45:03.994591 RX DQ/DQS(Engine): PASS
3757 13:45:03.995005 TX OE : NO K
3758 13:45:03.998205 All Pass.
3759 13:45:03.998617
3760 13:45:03.998942 CH 1, Rank 1
3761 13:45:04.001134 SW Impedance : PASS
3762 13:45:04.001550 DUTY Scan : NO K
3763 13:45:04.004642 ZQ Calibration : PASS
3764 13:45:04.008019 Jitter Meter : NO K
3765 13:45:04.008476 CBT Training : PASS
3766 13:45:04.011400 Write leveling : PASS
3767 13:45:04.014543 RX DQS gating : PASS
3768 13:45:04.014957 RX DQ/DQS(RDDQC) : PASS
3769 13:45:04.017698 TX DQ/DQS : PASS
3770 13:45:04.021314 RX DATLAT : PASS
3771 13:45:04.021729 RX DQ/DQS(Engine): PASS
3772 13:45:04.024182 TX OE : NO K
3773 13:45:04.024623 All Pass.
3774 13:45:04.024949
3775 13:45:04.028085 DramC Write-DBI off
3776 13:45:04.031360 PER_BANK_REFRESH: Hybrid Mode
3777 13:45:04.031816 TX_TRACKING: ON
3778 13:45:04.040602 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3779 13:45:04.044243 [FAST_K] Save calibration result to emmc
3780 13:45:04.047651 dramc_set_vcore_voltage set vcore to 650000
3781 13:45:04.051173 Read voltage for 600, 5
3782 13:45:04.051589 Vio18 = 0
3783 13:45:04.051918 Vcore = 650000
3784 13:45:04.054475 Vdram = 0
3785 13:45:04.054889 Vddq = 0
3786 13:45:04.055218 Vmddr = 0
3787 13:45:04.061177 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3788 13:45:04.064321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3789 13:45:04.067175 MEM_TYPE=3, freq_sel=19
3790 13:45:04.070929 sv_algorithm_assistance_LP4_1600
3791 13:45:04.074479 ============ PULL DRAM RESETB DOWN ============
3792 13:45:04.077698 ========== PULL DRAM RESETB DOWN end =========
3793 13:45:04.084192 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3794 13:45:04.087532 ===================================
3795 13:45:04.087945 LPDDR4 DRAM CONFIGURATION
3796 13:45:04.090826 ===================================
3797 13:45:04.093939 EX_ROW_EN[0] = 0x0
3798 13:45:04.097571 EX_ROW_EN[1] = 0x0
3799 13:45:04.097984 LP4Y_EN = 0x0
3800 13:45:04.100795 WORK_FSP = 0x0
3801 13:45:04.101210 WL = 0x2
3802 13:45:04.104047 RL = 0x2
3803 13:45:04.104510 BL = 0x2
3804 13:45:04.108015 RPST = 0x0
3805 13:45:04.108566 RD_PRE = 0x0
3806 13:45:04.110637 WR_PRE = 0x1
3807 13:45:04.111050 WR_PST = 0x0
3808 13:45:04.114209 DBI_WR = 0x0
3809 13:45:04.114628 DBI_RD = 0x0
3810 13:45:04.117558 OTF = 0x1
3811 13:45:04.120459 ===================================
3812 13:45:04.123726 ===================================
3813 13:45:04.124172 ANA top config
3814 13:45:04.127568 ===================================
3815 13:45:04.130787 DLL_ASYNC_EN = 0
3816 13:45:04.134395 ALL_SLAVE_EN = 1
3817 13:45:04.137499 NEW_RANK_MODE = 1
3818 13:45:04.138027 DLL_IDLE_MODE = 1
3819 13:45:04.140805 LP45_APHY_COMB_EN = 1
3820 13:45:04.144249 TX_ODT_DIS = 1
3821 13:45:04.147084 NEW_8X_MODE = 1
3822 13:45:04.150728 ===================================
3823 13:45:04.153655 ===================================
3824 13:45:04.157254 data_rate = 1200
3825 13:45:04.157667 CKR = 1
3826 13:45:04.160586 DQ_P2S_RATIO = 8
3827 13:45:04.163787 ===================================
3828 13:45:04.167191 CA_P2S_RATIO = 8
3829 13:45:04.170335 DQ_CA_OPEN = 0
3830 13:45:04.173369 DQ_SEMI_OPEN = 0
3831 13:45:04.173788 CA_SEMI_OPEN = 0
3832 13:45:04.176872 CA_FULL_RATE = 0
3833 13:45:04.180446 DQ_CKDIV4_EN = 1
3834 13:45:04.183839 CA_CKDIV4_EN = 1
3835 13:45:04.187581 CA_PREDIV_EN = 0
3836 13:45:04.190397 PH8_DLY = 0
3837 13:45:04.190815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 13:45:04.194119 DQ_AAMCK_DIV = 4
3839 13:45:04.197393 CA_AAMCK_DIV = 4
3840 13:45:04.200237 CA_ADMCK_DIV = 4
3841 13:45:04.203622 DQ_TRACK_CA_EN = 0
3842 13:45:04.206963 CA_PICK = 600
3843 13:45:04.210555 CA_MCKIO = 600
3844 13:45:04.211051 MCKIO_SEMI = 0
3845 13:45:04.213771 PLL_FREQ = 2288
3846 13:45:04.216867 DQ_UI_PI_RATIO = 32
3847 13:45:04.220061 CA_UI_PI_RATIO = 0
3848 13:45:04.223645 ===================================
3849 13:45:04.227285 ===================================
3850 13:45:04.230011 memory_type:LPDDR4
3851 13:45:04.230425 GP_NUM : 10
3852 13:45:04.233428 SRAM_EN : 1
3853 13:45:04.236888 MD32_EN : 0
3854 13:45:04.240117 ===================================
3855 13:45:04.240687 [ANA_INIT] >>>>>>>>>>>>>>
3856 13:45:04.243390 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 13:45:04.246862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 13:45:04.250422 ===================================
3859 13:45:04.253239 data_rate = 1200,PCW = 0X5800
3860 13:45:04.256919 ===================================
3861 13:45:04.260409 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 13:45:04.266974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 13:45:04.270456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 13:45:04.276757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 13:45:04.280059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 13:45:04.283221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 13:45:04.283640 [ANA_INIT] flow start
3868 13:45:04.287278 [ANA_INIT] PLL >>>>>>>>
3869 13:45:04.289986 [ANA_INIT] PLL <<<<<<<<
3870 13:45:04.290491 [ANA_INIT] MIDPI >>>>>>>>
3871 13:45:04.293396 [ANA_INIT] MIDPI <<<<<<<<
3872 13:45:04.296885 [ANA_INIT] DLL >>>>>>>>
3873 13:45:04.297298 [ANA_INIT] flow end
3874 13:45:04.303480 ============ LP4 DIFF to SE enter ============
3875 13:45:04.306425 ============ LP4 DIFF to SE exit ============
3876 13:45:04.310156 [ANA_INIT] <<<<<<<<<<<<<
3877 13:45:04.313652 [Flow] Enable top DCM control >>>>>
3878 13:45:04.316504 [Flow] Enable top DCM control <<<<<
3879 13:45:04.316918 Enable DLL master slave shuffle
3880 13:45:04.323460 ==============================================================
3881 13:45:04.326715 Gating Mode config
3882 13:45:04.329385 ==============================================================
3883 13:45:04.333278 Config description:
3884 13:45:04.343025 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3885 13:45:04.349938 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3886 13:45:04.353162 SELPH_MODE 0: By rank 1: By Phase
3887 13:45:04.359398 ==============================================================
3888 13:45:04.362870 GAT_TRACK_EN = 1
3889 13:45:04.365716 RX_GATING_MODE = 2
3890 13:45:04.369297 RX_GATING_TRACK_MODE = 2
3891 13:45:04.373199 SELPH_MODE = 1
3892 13:45:04.373441 PICG_EARLY_EN = 1
3893 13:45:04.376075 VALID_LAT_VALUE = 1
3894 13:45:04.382653 ==============================================================
3895 13:45:04.386067 Enter into Gating configuration >>>>
3896 13:45:04.388869 Exit from Gating configuration <<<<
3897 13:45:04.392353 Enter into DVFS_PRE_config >>>>>
3898 13:45:04.402429 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3899 13:45:04.405502 Exit from DVFS_PRE_config <<<<<
3900 13:45:04.409306 Enter into PICG configuration >>>>
3901 13:45:04.412138 Exit from PICG configuration <<<<
3902 13:45:04.415768 [RX_INPUT] configuration >>>>>
3903 13:45:04.419219 [RX_INPUT] configuration <<<<<
3904 13:45:04.423069 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3905 13:45:04.429046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3906 13:45:04.435546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 13:45:04.442390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 13:45:04.449181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 13:45:04.452634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 13:45:04.459236 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3911 13:45:04.462408 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3912 13:45:04.465617 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3913 13:45:04.468820 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3914 13:45:04.476483 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3915 13:45:04.479584 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 13:45:04.482246 ===================================
3917 13:45:04.485956 LPDDR4 DRAM CONFIGURATION
3918 13:45:04.488803 ===================================
3919 13:45:04.489228 EX_ROW_EN[0] = 0x0
3920 13:45:04.492418 EX_ROW_EN[1] = 0x0
3921 13:45:04.492844 LP4Y_EN = 0x0
3922 13:45:04.496249 WORK_FSP = 0x0
3923 13:45:04.496884 WL = 0x2
3924 13:45:04.498791 RL = 0x2
3925 13:45:04.499212 BL = 0x2
3926 13:45:04.502585 RPST = 0x0
3927 13:45:04.505677 RD_PRE = 0x0
3928 13:45:04.506202 WR_PRE = 0x1
3929 13:45:04.508919 WR_PST = 0x0
3930 13:45:04.509344 DBI_WR = 0x0
3931 13:45:04.512285 DBI_RD = 0x0
3932 13:45:04.512779 OTF = 0x1
3933 13:45:04.515791 ===================================
3934 13:45:04.519191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3935 13:45:04.525480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3936 13:45:04.528790 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 13:45:04.532137 ===================================
3938 13:45:04.535372 LPDDR4 DRAM CONFIGURATION
3939 13:45:04.538966 ===================================
3940 13:45:04.539389 EX_ROW_EN[0] = 0x10
3941 13:45:04.541936 EX_ROW_EN[1] = 0x0
3942 13:45:04.542359 LP4Y_EN = 0x0
3943 13:45:04.545499 WORK_FSP = 0x0
3944 13:45:04.545936 WL = 0x2
3945 13:45:04.548877 RL = 0x2
3946 13:45:04.549390 BL = 0x2
3947 13:45:04.552471 RPST = 0x0
3948 13:45:04.552893 RD_PRE = 0x0
3949 13:45:04.555184 WR_PRE = 0x1
3950 13:45:04.555604 WR_PST = 0x0
3951 13:45:04.558543 DBI_WR = 0x0
3952 13:45:04.561984 DBI_RD = 0x0
3953 13:45:04.562482 OTF = 0x1
3954 13:45:04.564903 ===================================
3955 13:45:04.571952 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3956 13:45:04.575593 nWR fixed to 30
3957 13:45:04.579373 [ModeRegInit_LP4] CH0 RK0
3958 13:45:04.579993 [ModeRegInit_LP4] CH0 RK1
3959 13:45:04.582437 [ModeRegInit_LP4] CH1 RK0
3960 13:45:04.585497 [ModeRegInit_LP4] CH1 RK1
3961 13:45:04.585916 match AC timing 17
3962 13:45:04.592301 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3963 13:45:04.595122 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3964 13:45:04.598726 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3965 13:45:04.605010 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3966 13:45:04.608921 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3967 13:45:04.609465 ==
3968 13:45:04.611465 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 13:45:04.614983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 13:45:04.615408 ==
3971 13:45:04.621847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 13:45:04.628965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 13:45:04.631535 [CA 0] Center 35 (5~66) winsize 62
3974 13:45:04.634973 [CA 1] Center 35 (5~66) winsize 62
3975 13:45:04.638359 [CA 2] Center 33 (3~64) winsize 62
3976 13:45:04.641884 [CA 3] Center 33 (2~64) winsize 63
3977 13:45:04.644884 [CA 4] Center 33 (2~64) winsize 63
3978 13:45:04.648514 [CA 5] Center 32 (2~63) winsize 62
3979 13:45:04.648968
3980 13:45:04.651635 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 13:45:04.652057
3982 13:45:04.655109 [CATrainingPosCal] consider 1 rank data
3983 13:45:04.658369 u2DelayCellTimex100 = 270/100 ps
3984 13:45:04.661737 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3985 13:45:04.664924 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3986 13:45:04.668409 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3987 13:45:04.671904 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 13:45:04.675156 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3989 13:45:04.681736 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 13:45:04.682158
3991 13:45:04.685103 CA PerBit enable=1, Macro0, CA PI delay=32
3992 13:45:04.685525
3993 13:45:04.688310 [CBTSetCACLKResult] CA Dly = 32
3994 13:45:04.688771 CS Dly: 4 (0~35)
3995 13:45:04.689102 ==
3996 13:45:04.691783 Dram Type= 6, Freq= 0, CH_0, rank 1
3997 13:45:04.695186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 13:45:04.698401 ==
3999 13:45:04.701909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 13:45:04.708253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4001 13:45:04.711816 [CA 0] Center 36 (5~67) winsize 63
4002 13:45:04.714764 [CA 1] Center 36 (5~67) winsize 63
4003 13:45:04.718293 [CA 2] Center 34 (3~65) winsize 63
4004 13:45:04.721539 [CA 3] Center 34 (3~65) winsize 63
4005 13:45:04.724925 [CA 4] Center 33 (2~64) winsize 63
4006 13:45:04.728764 [CA 5] Center 32 (2~63) winsize 62
4007 13:45:04.729282
4008 13:45:04.731609 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4009 13:45:04.732075
4010 13:45:04.735076 [CATrainingPosCal] consider 2 rank data
4011 13:45:04.739082 u2DelayCellTimex100 = 270/100 ps
4012 13:45:04.741750 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 13:45:04.745444 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4014 13:45:04.748495 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 13:45:04.751621 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4016 13:45:04.755065 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4017 13:45:04.761948 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4018 13:45:04.762486
4019 13:45:04.764924 CA PerBit enable=1, Macro0, CA PI delay=32
4020 13:45:04.765350
4021 13:45:04.768414 [CBTSetCACLKResult] CA Dly = 32
4022 13:45:04.768839 CS Dly: 5 (0~37)
4023 13:45:04.769171
4024 13:45:04.771926 ----->DramcWriteLeveling(PI) begin...
4025 13:45:04.772530 ==
4026 13:45:04.775281 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 13:45:04.778870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 13:45:04.781538 ==
4029 13:45:04.781963 Write leveling (Byte 0): 31 => 31
4030 13:45:04.785009 Write leveling (Byte 1): 30 => 30
4031 13:45:04.788569 DramcWriteLeveling(PI) end<-----
4032 13:45:04.789120
4033 13:45:04.789575 ==
4034 13:45:04.791782 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 13:45:04.798272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 13:45:04.798711 ==
4037 13:45:04.799150 [Gating] SW mode calibration
4038 13:45:04.808421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 13:45:04.811557 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4040 13:45:04.815255 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 13:45:04.821373 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 13:45:04.825027 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 13:45:04.827976 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
4044 13:45:04.835185 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
4045 13:45:04.837964 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 13:45:04.841552 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:45:04.848063 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 13:45:04.851555 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 13:45:04.855273 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 13:45:04.861654 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4051 13:45:04.864541 0 10 12 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
4052 13:45:04.868085 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
4053 13:45:04.874565 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:45:04.878674 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:45:04.881590 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 13:45:04.887941 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 13:45:04.891190 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 13:45:04.894933 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 13:45:04.900985 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 13:45:04.905004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4061 13:45:04.908291 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:45:04.914503 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:45:04.917882 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:45:04.921180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:45:04.927842 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:45:04.930971 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:45:04.934120 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:45:04.941517 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:45:04.944378 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:45:04.947866 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:45:04.954226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 13:45:04.957828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 13:45:04.961522 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 13:45:04.964170 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 13:45:04.971297 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 13:45:04.974174 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4077 13:45:04.977897 Total UI for P1: 0, mck2ui 16
4078 13:45:04.981455 best dqsien dly found for B0: ( 0, 13, 14)
4079 13:45:04.984373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 13:45:04.987933 Total UI for P1: 0, mck2ui 16
4081 13:45:04.991339 best dqsien dly found for B1: ( 0, 13, 16)
4082 13:45:04.994821 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4083 13:45:05.000629 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4084 13:45:05.001050
4085 13:45:05.004198 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4086 13:45:05.007770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4087 13:45:05.011060 [Gating] SW calibration Done
4088 13:45:05.011563 ==
4089 13:45:05.014241 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 13:45:05.017643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 13:45:05.018193 ==
4092 13:45:05.018650 RX Vref Scan: 0
4093 13:45:05.021203
4094 13:45:05.021926 RX Vref 0 -> 0, step: 1
4095 13:45:05.022343
4096 13:45:05.023964 RX Delay -230 -> 252, step: 16
4097 13:45:05.027848 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4098 13:45:05.033736 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4099 13:45:05.037141 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4100 13:45:05.040791 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4101 13:45:05.043756 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4102 13:45:05.047392 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4103 13:45:05.053667 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4104 13:45:05.057309 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4105 13:45:05.060419 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4106 13:45:05.063689 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4107 13:45:05.070758 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4108 13:45:05.073738 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4109 13:45:05.077208 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4110 13:45:05.080830 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4111 13:45:05.087419 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4112 13:45:05.090384 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4113 13:45:05.091020 ==
4114 13:45:05.093869 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 13:45:05.097446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 13:45:05.097974 ==
4117 13:45:05.098524 DQS Delay:
4118 13:45:05.100383 DQS0 = 0, DQS1 = 0
4119 13:45:05.100868 DQM Delay:
4120 13:45:05.103538 DQM0 = 53, DQM1 = 46
4121 13:45:05.104091 DQ Delay:
4122 13:45:05.107022 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4123 13:45:05.110399 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4124 13:45:05.114192 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4125 13:45:05.117086 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4126 13:45:05.117504
4127 13:45:05.117833
4128 13:45:05.118136 ==
4129 13:45:05.120443 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 13:45:05.124131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 13:45:05.127310 ==
4132 13:45:05.127847
4133 13:45:05.128221
4134 13:45:05.128663 TX Vref Scan disable
4135 13:45:05.130499 == TX Byte 0 ==
4136 13:45:05.133808 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4137 13:45:05.137176 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4138 13:45:05.140147 == TX Byte 1 ==
4139 13:45:05.144038 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4140 13:45:05.147051 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4141 13:45:05.150647 ==
4142 13:45:05.153757 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 13:45:05.156942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 13:45:05.157463 ==
4145 13:45:05.157931
4146 13:45:05.158380
4147 13:45:05.160080 TX Vref Scan disable
4148 13:45:05.160561 == TX Byte 0 ==
4149 13:45:05.167051 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4150 13:45:05.170403 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4151 13:45:05.170949 == TX Byte 1 ==
4152 13:45:05.176666 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4153 13:45:05.179937 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4154 13:45:05.180398
4155 13:45:05.180744 [DATLAT]
4156 13:45:05.183601 Freq=600, CH0 RK0
4157 13:45:05.184056
4158 13:45:05.184505 DATLAT Default: 0x9
4159 13:45:05.187121 0, 0xFFFF, sum = 0
4160 13:45:05.187546 1, 0xFFFF, sum = 0
4161 13:45:05.190150 2, 0xFFFF, sum = 0
4162 13:45:05.193725 3, 0xFFFF, sum = 0
4163 13:45:05.194156 4, 0xFFFF, sum = 0
4164 13:45:05.196683 5, 0xFFFF, sum = 0
4165 13:45:05.197114 6, 0xFFFF, sum = 0
4166 13:45:05.200114 7, 0xFFFF, sum = 0
4167 13:45:05.200591 8, 0x0, sum = 1
4168 13:45:05.200943 9, 0x0, sum = 2
4169 13:45:05.203113 10, 0x0, sum = 3
4170 13:45:05.203539 11, 0x0, sum = 4
4171 13:45:05.206437 best_step = 9
4172 13:45:05.206978
4173 13:45:05.207446 ==
4174 13:45:05.209789 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 13:45:05.213325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 13:45:05.213751 ==
4177 13:45:05.216728 RX Vref Scan: 1
4178 13:45:05.217148
4179 13:45:05.217480 RX Vref 0 -> 0, step: 1
4180 13:45:05.217791
4181 13:45:05.220332 RX Delay -163 -> 252, step: 8
4182 13:45:05.220932
4183 13:45:05.223216 Set Vref, RX VrefLevel [Byte0]: 54
4184 13:45:05.226768 [Byte1]: 51
4185 13:45:05.230360
4186 13:45:05.230779 Final RX Vref Byte 0 = 54 to rank0
4187 13:45:05.234038 Final RX Vref Byte 1 = 51 to rank0
4188 13:45:05.237079 Final RX Vref Byte 0 = 54 to rank1
4189 13:45:05.240547 Final RX Vref Byte 1 = 51 to rank1==
4190 13:45:05.244227 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 13:45:05.250497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 13:45:05.250923 ==
4193 13:45:05.251306 DQS Delay:
4194 13:45:05.253929 DQS0 = 0, DQS1 = 0
4195 13:45:05.254350 DQM Delay:
4196 13:45:05.254683 DQM0 = 53, DQM1 = 47
4197 13:45:05.257397 DQ Delay:
4198 13:45:05.260183 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4199 13:45:05.263455 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4200 13:45:05.266990 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4201 13:45:05.270474 DQ12 =56, DQ13 =56, DQ14 =56, DQ15 =52
4202 13:45:05.270948
4203 13:45:05.271363
4204 13:45:05.277208 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4205 13:45:05.280652 CH0 RK0: MR19=808, MR18=7164
4206 13:45:05.287048 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4207 13:45:05.287610
4208 13:45:05.290148 ----->DramcWriteLeveling(PI) begin...
4209 13:45:05.290584 ==
4210 13:45:05.293553 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 13:45:05.296994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 13:45:05.297450 ==
4213 13:45:05.300180 Write leveling (Byte 0): 34 => 34
4214 13:45:05.303592 Write leveling (Byte 1): 29 => 29
4215 13:45:05.307272 DramcWriteLeveling(PI) end<-----
4216 13:45:05.307693
4217 13:45:05.308026 ==
4218 13:45:05.310025 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 13:45:05.313326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 13:45:05.313752 ==
4221 13:45:05.316766 [Gating] SW mode calibration
4222 13:45:05.324122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 13:45:05.330104 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 13:45:05.333754 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 13:45:05.340335 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 13:45:05.343481 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 13:45:05.346805 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
4228 13:45:05.350091 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
4229 13:45:05.356528 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 13:45:05.359868 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 13:45:05.363471 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 13:45:05.370257 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 13:45:05.373886 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 13:45:05.376421 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 13:45:05.383664 0 10 12 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
4236 13:45:05.386599 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
4237 13:45:05.390100 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 13:45:05.396453 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 13:45:05.399875 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 13:45:05.403253 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 13:45:05.410275 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 13:45:05.413489 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 13:45:05.416586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 13:45:05.423382 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4245 13:45:05.426757 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 13:45:05.429897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 13:45:05.436473 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:45:05.440006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:45:05.442851 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:45:05.450020 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 13:45:05.452849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 13:45:05.456578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:45:05.462874 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:45:05.466447 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:45:05.470116 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:45:05.472866 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:45:05.479549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:45:05.483023 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:45:05.486505 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:45:05.492906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4261 13:45:05.496748 Total UI for P1: 0, mck2ui 16
4262 13:45:05.499389 best dqsien dly found for B1: ( 0, 13, 14)
4263 13:45:05.502950 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 13:45:05.506566 Total UI for P1: 0, mck2ui 16
4265 13:45:05.509401 best dqsien dly found for B0: ( 0, 13, 16)
4266 13:45:05.513058 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4267 13:45:05.516514 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4268 13:45:05.516954
4269 13:45:05.519218 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4270 13:45:05.525871 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4271 13:45:05.526407 [Gating] SW calibration Done
4272 13:45:05.526853 ==
4273 13:45:05.529453 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 13:45:05.536155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 13:45:05.536718 ==
4276 13:45:05.537053 RX Vref Scan: 0
4277 13:45:05.537361
4278 13:45:05.539534 RX Vref 0 -> 0, step: 1
4279 13:45:05.539946
4280 13:45:05.542679 RX Delay -230 -> 252, step: 16
4281 13:45:05.546439 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4282 13:45:05.549622 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4283 13:45:05.552841 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4284 13:45:05.559417 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4285 13:45:05.562278 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4286 13:45:05.565922 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4287 13:45:05.569378 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4288 13:45:05.575666 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4289 13:45:05.579255 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4290 13:45:05.582719 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4291 13:45:05.586112 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4292 13:45:05.589475 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4293 13:45:05.595798 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4294 13:45:05.599380 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4295 13:45:05.602123 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4296 13:45:05.605741 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4297 13:45:05.609344 ==
4298 13:45:05.612268 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 13:45:05.616011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 13:45:05.616622 ==
4301 13:45:05.617170 DQS Delay:
4302 13:45:05.619395 DQS0 = 0, DQS1 = 0
4303 13:45:05.619813 DQM Delay:
4304 13:45:05.622324 DQM0 = 51, DQM1 = 43
4305 13:45:05.622838 DQ Delay:
4306 13:45:05.625735 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4307 13:45:05.629379 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4308 13:45:05.632551 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4309 13:45:05.635960 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4310 13:45:05.636407
4311 13:45:05.636746
4312 13:45:05.637054 ==
4313 13:45:05.638807 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 13:45:05.642764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 13:45:05.643280 ==
4316 13:45:05.643613
4317 13:45:05.643915
4318 13:45:05.645514 TX Vref Scan disable
4319 13:45:05.649004 == TX Byte 0 ==
4320 13:45:05.652567 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4321 13:45:05.655775 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4322 13:45:05.659133 == TX Byte 1 ==
4323 13:45:05.662272 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 13:45:05.665499 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 13:45:05.665949 ==
4326 13:45:05.669050 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 13:45:05.675895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 13:45:05.676465 ==
4329 13:45:05.676807
4330 13:45:05.677112
4331 13:45:05.677429 TX Vref Scan disable
4332 13:45:05.679676 == TX Byte 0 ==
4333 13:45:05.683053 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4334 13:45:05.689650 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4335 13:45:05.690202 == TX Byte 1 ==
4336 13:45:05.693105 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4337 13:45:05.699798 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4338 13:45:05.700444
4339 13:45:05.700880 [DATLAT]
4340 13:45:05.701288 Freq=600, CH0 RK1
4341 13:45:05.701688
4342 13:45:05.703131 DATLAT Default: 0x9
4343 13:45:05.703558 0, 0xFFFF, sum = 0
4344 13:45:05.706061 1, 0xFFFF, sum = 0
4345 13:45:05.709266 2, 0xFFFF, sum = 0
4346 13:45:05.709767 3, 0xFFFF, sum = 0
4347 13:45:05.712902 4, 0xFFFF, sum = 0
4348 13:45:05.713324 5, 0xFFFF, sum = 0
4349 13:45:05.716667 6, 0xFFFF, sum = 0
4350 13:45:05.717294 7, 0xFFFF, sum = 0
4351 13:45:05.719492 8, 0x0, sum = 1
4352 13:45:05.719875 9, 0x0, sum = 2
4353 13:45:05.720198 10, 0x0, sum = 3
4354 13:45:05.722984 11, 0x0, sum = 4
4355 13:45:05.723405 best_step = 9
4356 13:45:05.723799
4357 13:45:05.724114 ==
4358 13:45:05.726557 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 13:45:05.732796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 13:45:05.733369 ==
4361 13:45:05.733914 RX Vref Scan: 0
4362 13:45:05.734489
4363 13:45:05.736264 RX Vref 0 -> 0, step: 1
4364 13:45:05.736762
4365 13:45:05.739718 RX Delay -163 -> 252, step: 8
4366 13:45:05.742538 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4367 13:45:05.749304 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4368 13:45:05.752217 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4369 13:45:05.755987 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4370 13:45:05.759613 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4371 13:45:05.762388 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4372 13:45:05.769671 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4373 13:45:05.772217 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4374 13:45:05.775602 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4375 13:45:05.778940 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4376 13:45:05.782366 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4377 13:45:05.789473 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4378 13:45:05.792650 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4379 13:45:05.796318 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4380 13:45:05.799430 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4381 13:45:05.802747 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4382 13:45:05.803157 ==
4383 13:45:05.806155 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 13:45:05.813058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 13:45:05.813528 ==
4386 13:45:05.813860 DQS Delay:
4387 13:45:05.816022 DQS0 = 0, DQS1 = 0
4388 13:45:05.816469 DQM Delay:
4389 13:45:05.819613 DQM0 = 52, DQM1 = 47
4390 13:45:05.820018 DQ Delay:
4391 13:45:05.822437 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4392 13:45:05.826012 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4393 13:45:05.829517 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4394 13:45:05.832307 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4395 13:45:05.832737
4396 13:45:05.833061
4397 13:45:05.839357 [DQSOSCAuto] RK1, (LSB)MR18= 0x6626, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4398 13:45:05.842723 CH0 RK1: MR19=808, MR18=6626
4399 13:45:05.849623 CH0_RK1: MR19=0x808, MR18=0x6626, DQSOSC=390, MR23=63, INC=172, DEC=114
4400 13:45:05.852400 [RxdqsGatingPostProcess] freq 600
4401 13:45:05.856264 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 13:45:05.858880 Pre-setting of DQS Precalculation
4403 13:45:05.865796 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 13:45:05.866234 ==
4405 13:45:05.869303 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 13:45:05.872865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 13:45:05.873288 ==
4408 13:45:05.879152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 13:45:05.885253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4410 13:45:05.888770 [CA 0] Center 35 (5~66) winsize 62
4411 13:45:05.892402 [CA 1] Center 35 (5~66) winsize 62
4412 13:45:05.895634 [CA 2] Center 34 (4~65) winsize 62
4413 13:45:05.898586 [CA 3] Center 34 (4~65) winsize 62
4414 13:45:05.902073 [CA 4] Center 34 (4~65) winsize 62
4415 13:45:05.905484 [CA 5] Center 33 (3~64) winsize 62
4416 13:45:05.906070
4417 13:45:05.908631 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4418 13:45:05.909214
4419 13:45:05.912371 [CATrainingPosCal] consider 1 rank data
4420 13:45:05.915289 u2DelayCellTimex100 = 270/100 ps
4421 13:45:05.918252 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 13:45:05.921870 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4423 13:45:05.924904 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 13:45:05.928700 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 13:45:05.931951 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 13:45:05.935082 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 13:45:05.935586
4428 13:45:05.941652 CA PerBit enable=1, Macro0, CA PI delay=33
4429 13:45:05.942120
4430 13:45:05.945243 [CBTSetCACLKResult] CA Dly = 33
4431 13:45:05.945654 CS Dly: 5 (0~36)
4432 13:45:05.945981 ==
4433 13:45:05.948763 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 13:45:05.951445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 13:45:05.951889 ==
4436 13:45:05.958481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 13:45:05.965012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4438 13:45:05.968693 [CA 0] Center 36 (6~67) winsize 62
4439 13:45:05.971515 [CA 1] Center 36 (6~67) winsize 62
4440 13:45:05.974911 [CA 2] Center 35 (4~66) winsize 63
4441 13:45:05.979036 [CA 3] Center 35 (4~66) winsize 63
4442 13:45:05.981982 [CA 4] Center 35 (4~66) winsize 63
4443 13:45:05.984624 [CA 5] Center 34 (4~65) winsize 62
4444 13:45:05.985049
4445 13:45:05.988062 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4446 13:45:05.988650
4447 13:45:05.991538 [CATrainingPosCal] consider 2 rank data
4448 13:45:05.995047 u2DelayCellTimex100 = 270/100 ps
4449 13:45:05.998438 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4450 13:45:06.001835 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4451 13:45:06.004674 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4452 13:45:06.008315 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4453 13:45:06.014921 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4454 13:45:06.018487 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4455 13:45:06.018904
4456 13:45:06.022078 CA PerBit enable=1, Macro0, CA PI delay=34
4457 13:45:06.022606
4458 13:45:06.024720 [CBTSetCACLKResult] CA Dly = 34
4459 13:45:06.025136 CS Dly: 6 (0~38)
4460 13:45:06.025465
4461 13:45:06.028372 ----->DramcWriteLeveling(PI) begin...
4462 13:45:06.028894 ==
4463 13:45:06.031942 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 13:45:06.038130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 13:45:06.038679 ==
4466 13:45:06.041563 Write leveling (Byte 0): 31 => 31
4467 13:45:06.042005 Write leveling (Byte 1): 31 => 31
4468 13:45:06.044819 DramcWriteLeveling(PI) end<-----
4469 13:45:06.045376
4470 13:45:06.048196 ==
4471 13:45:06.048695 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 13:45:06.055064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 13:45:06.055523 ==
4474 13:45:06.057807 [Gating] SW mode calibration
4475 13:45:06.064599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 13:45:06.067764 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 13:45:06.075191 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 13:45:06.077820 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 13:45:06.081269 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4480 13:45:06.087773 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
4481 13:45:06.091332 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 13:45:06.094982 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 13:45:06.101254 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 13:45:06.103925 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 13:45:06.107445 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 13:45:06.114254 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 13:45:06.117770 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4488 13:45:06.120589 0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
4489 13:45:06.124216 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 13:45:06.131235 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 13:45:06.134152 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 13:45:06.137846 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 13:45:06.144097 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 13:45:06.147564 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 13:45:06.151054 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 13:45:06.157407 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4497 13:45:06.160795 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4498 13:45:06.164282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:45:06.171473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:45:06.174364 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:45:06.177939 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:45:06.184671 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:45:06.187701 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:45:06.190984 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:45:06.197597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:45:06.201037 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:45:06.204470 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 13:45:06.210957 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 13:45:06.213847 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 13:45:06.217190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 13:45:06.224259 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 13:45:06.227084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4513 13:45:06.231110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 13:45:06.233749 Total UI for P1: 0, mck2ui 16
4515 13:45:06.236975 best dqsien dly found for B0: ( 0, 13, 12)
4516 13:45:06.240623 Total UI for P1: 0, mck2ui 16
4517 13:45:06.244136 best dqsien dly found for B1: ( 0, 13, 12)
4518 13:45:06.247194 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4519 13:45:06.250830 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4520 13:45:06.251260
4521 13:45:06.254302 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4522 13:45:06.260517 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4523 13:45:06.260944 [Gating] SW calibration Done
4524 13:45:06.261284 ==
4525 13:45:06.264050 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 13:45:06.270884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 13:45:06.271315 ==
4528 13:45:06.271652 RX Vref Scan: 0
4529 13:45:06.271963
4530 13:45:06.274819 RX Vref 0 -> 0, step: 1
4531 13:45:06.275176
4532 13:45:06.277475 RX Delay -230 -> 252, step: 16
4533 13:45:06.280885 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4534 13:45:06.283855 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4535 13:45:06.287096 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4536 13:45:06.293591 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4537 13:45:06.297052 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4538 13:45:06.300018 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4539 13:45:06.303434 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4540 13:45:06.310418 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4541 13:45:06.313350 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4542 13:45:06.316617 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4543 13:45:06.319839 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4544 13:45:06.323223 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4545 13:45:06.330171 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4546 13:45:06.333040 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4547 13:45:06.336583 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4548 13:45:06.340090 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4549 13:45:06.340186 ==
4550 13:45:06.342859 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 13:45:06.350032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 13:45:06.350144 ==
4553 13:45:06.350236 DQS Delay:
4554 13:45:06.352923 DQS0 = 0, DQS1 = 0
4555 13:45:06.353010 DQM Delay:
4556 13:45:06.353097 DQM0 = 55, DQM1 = 53
4557 13:45:06.356499 DQ Delay:
4558 13:45:06.360199 DQ0 =65, DQ1 =49, DQ2 =49, DQ3 =49
4559 13:45:06.362919 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4560 13:45:06.366419 DQ8 =41, DQ9 =41, DQ10 =57, DQ11 =49
4561 13:45:06.369953 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =57
4562 13:45:06.370049
4563 13:45:06.370134
4564 13:45:06.370213 ==
4565 13:45:06.373462 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 13:45:06.376304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 13:45:06.376432 ==
4568 13:45:06.376500
4569 13:45:06.376561
4570 13:45:06.379886 TX Vref Scan disable
4571 13:45:06.382768 == TX Byte 0 ==
4572 13:45:06.386403 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4573 13:45:06.389949 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4574 13:45:06.393310 == TX Byte 1 ==
4575 13:45:06.396127 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 13:45:06.399902 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 13:45:06.399991 ==
4578 13:45:06.402674 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 13:45:06.406248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 13:45:06.409830 ==
4581 13:45:06.409916
4582 13:45:06.409981
4583 13:45:06.410042 TX Vref Scan disable
4584 13:45:06.413382 == TX Byte 0 ==
4585 13:45:06.416758 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4586 13:45:06.423265 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4587 13:45:06.423360 == TX Byte 1 ==
4588 13:45:06.427097 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 13:45:06.430077 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 13:45:06.433179
4591 13:45:06.433285 [DATLAT]
4592 13:45:06.433375 Freq=600, CH1 RK0
4593 13:45:06.433457
4594 13:45:06.436650 DATLAT Default: 0x9
4595 13:45:06.436739 0, 0xFFFF, sum = 0
4596 13:45:06.439563 1, 0xFFFF, sum = 0
4597 13:45:06.439667 2, 0xFFFF, sum = 0
4598 13:45:06.443263 3, 0xFFFF, sum = 0
4599 13:45:06.446650 4, 0xFFFF, sum = 0
4600 13:45:06.446747 5, 0xFFFF, sum = 0
4601 13:45:06.449996 6, 0xFFFF, sum = 0
4602 13:45:06.450096 7, 0xFFFF, sum = 0
4603 13:45:06.452943 8, 0x0, sum = 1
4604 13:45:06.453091 9, 0x0, sum = 2
4605 13:45:06.453252 10, 0x0, sum = 3
4606 13:45:06.456163 11, 0x0, sum = 4
4607 13:45:06.456248 best_step = 9
4608 13:45:06.456314
4609 13:45:06.456419 ==
4610 13:45:06.459481 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 13:45:06.466657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 13:45:06.466748 ==
4613 13:45:06.466816 RX Vref Scan: 1
4614 13:45:06.466877
4615 13:45:06.469477 RX Vref 0 -> 0, step: 1
4616 13:45:06.469563
4617 13:45:06.472862 RX Delay -147 -> 252, step: 8
4618 13:45:06.472948
4619 13:45:06.476517 Set Vref, RX VrefLevel [Byte0]: 56
4620 13:45:06.479789 [Byte1]: 53
4621 13:45:06.479922
4622 13:45:06.482678 Final RX Vref Byte 0 = 56 to rank0
4623 13:45:06.486254 Final RX Vref Byte 1 = 53 to rank0
4624 13:45:06.489848 Final RX Vref Byte 0 = 56 to rank1
4625 13:45:06.492703 Final RX Vref Byte 1 = 53 to rank1==
4626 13:45:06.496171 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 13:45:06.499655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 13:45:06.499739 ==
4629 13:45:06.503250 DQS Delay:
4630 13:45:06.503341 DQS0 = 0, DQS1 = 0
4631 13:45:06.503408 DQM Delay:
4632 13:45:06.506128 DQM0 = 49, DQM1 = 45
4633 13:45:06.506210 DQ Delay:
4634 13:45:06.509726 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4635 13:45:06.512601 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4636 13:45:06.516256 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4637 13:45:06.519759 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4638 13:45:06.519842
4639 13:45:06.519907
4640 13:45:06.529724 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4641 13:45:06.532475 CH1 RK0: MR19=808, MR18=4C72
4642 13:45:06.535809 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4643 13:45:06.535893
4644 13:45:06.539464 ----->DramcWriteLeveling(PI) begin...
4645 13:45:06.543216 ==
4646 13:45:06.545771 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 13:45:06.549201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 13:45:06.549320 ==
4649 13:45:06.552828 Write leveling (Byte 0): 28 => 28
4650 13:45:06.556220 Write leveling (Byte 1): 31 => 31
4651 13:45:06.559366 DramcWriteLeveling(PI) end<-----
4652 13:45:06.559489
4653 13:45:06.559586 ==
4654 13:45:06.562680 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 13:45:06.565894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 13:45:06.566032 ==
4657 13:45:06.569758 [Gating] SW mode calibration
4658 13:45:06.575894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4659 13:45:06.583102 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4660 13:45:06.586312 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 13:45:06.589668 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 13:45:06.593124 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
4663 13:45:06.599677 0 9 12 | B1->B0 | 2f2f 3030 | 1 0 | (1 1) (1 1)
4664 13:45:06.603120 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 13:45:06.606680 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 13:45:06.613264 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 13:45:06.616835 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 13:45:06.619638 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 13:45:06.626947 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 13:45:06.629947 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4671 13:45:06.633379 0 10 12 | B1->B0 | 3939 3535 | 0 0 | (0 0) (1 1)
4672 13:45:06.640251 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 13:45:06.642820 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 13:45:06.646786 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 13:45:06.653121 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 13:45:06.656760 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 13:45:06.660318 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 13:45:06.666577 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4679 13:45:06.670142 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 13:45:06.673468 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 13:45:06.676459 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 13:45:06.682678 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 13:45:06.686785 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 13:45:06.693033 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 13:45:06.696244 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 13:45:06.699228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 13:45:06.705964 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:45:06.709291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:45:06.712688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:45:06.718955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 13:45:06.722663 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 13:45:06.725960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 13:45:06.729526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 13:45:06.736189 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 13:45:06.739906 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4696 13:45:06.742540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 13:45:06.746091 Total UI for P1: 0, mck2ui 16
4698 13:45:06.749567 best dqsien dly found for B0: ( 0, 13, 12)
4699 13:45:06.752394 Total UI for P1: 0, mck2ui 16
4700 13:45:06.756315 best dqsien dly found for B1: ( 0, 13, 12)
4701 13:45:06.759324 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4702 13:45:06.762695 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4703 13:45:06.765529
4704 13:45:06.769104 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4705 13:45:06.772704 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4706 13:45:06.776094 [Gating] SW calibration Done
4707 13:45:06.776685 ==
4708 13:45:06.778871 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 13:45:06.782377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 13:45:06.782796 ==
4711 13:45:06.783147 RX Vref Scan: 0
4712 13:45:06.786034
4713 13:45:06.786448 RX Vref 0 -> 0, step: 1
4714 13:45:06.786776
4715 13:45:06.788861 RX Delay -230 -> 252, step: 16
4716 13:45:06.792457 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4717 13:45:06.798749 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4718 13:45:06.802254 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4719 13:45:06.805783 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4720 13:45:06.808687 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4721 13:45:06.812427 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4722 13:45:06.819022 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4723 13:45:06.822227 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4724 13:45:06.825287 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4725 13:45:06.828465 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4726 13:45:06.835149 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4727 13:45:06.838651 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4728 13:45:06.842092 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4729 13:45:06.845313 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4730 13:45:06.852118 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4731 13:45:06.854960 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4732 13:45:06.855427 ==
4733 13:45:06.858457 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 13:45:06.861927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 13:45:06.862392 ==
4736 13:45:06.865202 DQS Delay:
4737 13:45:06.865616 DQS0 = 0, DQS1 = 0
4738 13:45:06.865986 DQM Delay:
4739 13:45:06.868264 DQM0 = 50, DQM1 = 48
4740 13:45:06.868872 DQ Delay:
4741 13:45:06.872018 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4742 13:45:06.875186 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4743 13:45:06.878797 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4744 13:45:06.882153 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4745 13:45:06.882630
4746 13:45:06.882957
4747 13:45:06.883304 ==
4748 13:45:06.885028 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 13:45:06.891379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 13:45:06.891881 ==
4751 13:45:06.892215
4752 13:45:06.892695
4753 13:45:06.893038 TX Vref Scan disable
4754 13:45:06.894997 == TX Byte 0 ==
4755 13:45:06.898465 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4756 13:45:06.905238 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4757 13:45:06.905674 == TX Byte 1 ==
4758 13:45:06.908839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4759 13:45:06.915348 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4760 13:45:06.915781 ==
4761 13:45:06.918214 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 13:45:06.921725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 13:45:06.922161 ==
4764 13:45:06.922598
4765 13:45:06.923007
4766 13:45:06.925557 TX Vref Scan disable
4767 13:45:06.928398 == TX Byte 0 ==
4768 13:45:06.931680 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4769 13:45:06.935010 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4770 13:45:06.938558 == TX Byte 1 ==
4771 13:45:06.941493 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4772 13:45:06.945043 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4773 13:45:06.945697
4774 13:45:06.946063 [DATLAT]
4775 13:45:06.947652 Freq=600, CH1 RK1
4776 13:45:06.948095
4777 13:45:06.951384 DATLAT Default: 0x9
4778 13:45:06.952061 0, 0xFFFF, sum = 0
4779 13:45:06.954436 1, 0xFFFF, sum = 0
4780 13:45:06.954860 2, 0xFFFF, sum = 0
4781 13:45:06.958441 3, 0xFFFF, sum = 0
4782 13:45:06.958863 4, 0xFFFF, sum = 0
4783 13:45:06.961334 5, 0xFFFF, sum = 0
4784 13:45:06.962066 6, 0xFFFF, sum = 0
4785 13:45:06.964880 7, 0xFFFF, sum = 0
4786 13:45:06.965300 8, 0x0, sum = 1
4787 13:45:06.967681 9, 0x0, sum = 2
4788 13:45:06.968380 10, 0x0, sum = 3
4789 13:45:06.971697 11, 0x0, sum = 4
4790 13:45:06.972469 best_step = 9
4791 13:45:06.972879
4792 13:45:06.973293 ==
4793 13:45:06.974623 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 13:45:06.978091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 13:45:06.978666 ==
4796 13:45:06.981268 RX Vref Scan: 0
4797 13:45:06.981680
4798 13:45:06.984301 RX Vref 0 -> 0, step: 1
4799 13:45:06.984756
4800 13:45:06.985080 RX Delay -163 -> 252, step: 8
4801 13:45:06.992525 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4802 13:45:06.995403 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4803 13:45:06.999081 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4804 13:45:07.001837 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4805 13:45:07.005407 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4806 13:45:07.012234 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4807 13:45:07.015793 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4808 13:45:07.018638 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4809 13:45:07.022361 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4810 13:45:07.025189 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4811 13:45:07.032259 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4812 13:45:07.035180 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4813 13:45:07.038500 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4814 13:45:07.042473 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4815 13:45:07.048865 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4816 13:45:07.051782 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4817 13:45:07.052209 ==
4818 13:45:07.055318 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 13:45:07.058861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 13:45:07.059092 ==
4821 13:45:07.061685 DQS Delay:
4822 13:45:07.061912 DQS0 = 0, DQS1 = 0
4823 13:45:07.062154 DQM Delay:
4824 13:45:07.065207 DQM0 = 49, DQM1 = 45
4825 13:45:07.065389 DQ Delay:
4826 13:45:07.068598 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4827 13:45:07.072106 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4828 13:45:07.075349 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4829 13:45:07.078079 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4830 13:45:07.078211
4831 13:45:07.078314
4832 13:45:07.088302 [DQSOSCAuto] RK1, (LSB)MR18= 0x681e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4833 13:45:07.088428 CH1 RK1: MR19=808, MR18=681E
4834 13:45:07.094600 CH1_RK1: MR19=0x808, MR18=0x681E, DQSOSC=390, MR23=63, INC=172, DEC=114
4835 13:45:07.097840 [RxdqsGatingPostProcess] freq 600
4836 13:45:07.104618 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4837 13:45:07.108083 Pre-setting of DQS Precalculation
4838 13:45:07.110931 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4839 13:45:07.120899 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4840 13:45:07.127926 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4841 13:45:07.128022
4842 13:45:07.128087
4843 13:45:07.130717 [Calibration Summary] 1200 Mbps
4844 13:45:07.130801 CH 0, Rank 0
4845 13:45:07.134393 SW Impedance : PASS
4846 13:45:07.134476 DUTY Scan : NO K
4847 13:45:07.137345 ZQ Calibration : PASS
4848 13:45:07.140931 Jitter Meter : NO K
4849 13:45:07.141014 CBT Training : PASS
4850 13:45:07.144414 Write leveling : PASS
4851 13:45:07.147653 RX DQS gating : PASS
4852 13:45:07.147736 RX DQ/DQS(RDDQC) : PASS
4853 13:45:07.151206 TX DQ/DQS : PASS
4854 13:45:07.154110 RX DATLAT : PASS
4855 13:45:07.154193 RX DQ/DQS(Engine): PASS
4856 13:45:07.157687 TX OE : NO K
4857 13:45:07.157770 All Pass.
4858 13:45:07.157836
4859 13:45:07.160623 CH 0, Rank 1
4860 13:45:07.160706 SW Impedance : PASS
4861 13:45:07.164310 DUTY Scan : NO K
4862 13:45:07.164429 ZQ Calibration : PASS
4863 13:45:07.167262 Jitter Meter : NO K
4864 13:45:07.170861 CBT Training : PASS
4865 13:45:07.170943 Write leveling : PASS
4866 13:45:07.174309 RX DQS gating : PASS
4867 13:45:07.177117 RX DQ/DQS(RDDQC) : PASS
4868 13:45:07.177200 TX DQ/DQS : PASS
4869 13:45:07.180603 RX DATLAT : PASS
4870 13:45:07.184269 RX DQ/DQS(Engine): PASS
4871 13:45:07.184377 TX OE : NO K
4872 13:45:07.186886 All Pass.
4873 13:45:07.186969
4874 13:45:07.187033 CH 1, Rank 0
4875 13:45:07.190464 SW Impedance : PASS
4876 13:45:07.190547 DUTY Scan : NO K
4877 13:45:07.194208 ZQ Calibration : PASS
4878 13:45:07.196861 Jitter Meter : NO K
4879 13:45:07.196944 CBT Training : PASS
4880 13:45:07.200294 Write leveling : PASS
4881 13:45:07.203927 RX DQS gating : PASS
4882 13:45:07.204010 RX DQ/DQS(RDDQC) : PASS
4883 13:45:07.206871 TX DQ/DQS : PASS
4884 13:45:07.210576 RX DATLAT : PASS
4885 13:45:07.210658 RX DQ/DQS(Engine): PASS
4886 13:45:07.214041 TX OE : NO K
4887 13:45:07.214124 All Pass.
4888 13:45:07.214189
4889 13:45:07.217383 CH 1, Rank 1
4890 13:45:07.217466 SW Impedance : PASS
4891 13:45:07.220574 DUTY Scan : NO K
4892 13:45:07.220659 ZQ Calibration : PASS
4893 13:45:07.223768 Jitter Meter : NO K
4894 13:45:07.227290 CBT Training : PASS
4895 13:45:07.227400 Write leveling : PASS
4896 13:45:07.230470 RX DQS gating : PASS
4897 13:45:07.233793 RX DQ/DQS(RDDQC) : PASS
4898 13:45:07.233879 TX DQ/DQS : PASS
4899 13:45:07.236873 RX DATLAT : PASS
4900 13:45:07.239909 RX DQ/DQS(Engine): PASS
4901 13:45:07.239992 TX OE : NO K
4902 13:45:07.243387 All Pass.
4903 13:45:07.243469
4904 13:45:07.243534 DramC Write-DBI off
4905 13:45:07.246860 PER_BANK_REFRESH: Hybrid Mode
4906 13:45:07.250099 TX_TRACKING: ON
4907 13:45:07.256656 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4908 13:45:07.260272 [FAST_K] Save calibration result to emmc
4909 13:45:07.263271 dramc_set_vcore_voltage set vcore to 662500
4910 13:45:07.266857 Read voltage for 933, 3
4911 13:45:07.266941 Vio18 = 0
4912 13:45:07.269715 Vcore = 662500
4913 13:45:07.269798 Vdram = 0
4914 13:45:07.269864 Vddq = 0
4915 13:45:07.273394 Vmddr = 0
4916 13:45:07.276382 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4917 13:45:07.283227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4918 13:45:07.283315 MEM_TYPE=3, freq_sel=17
4919 13:45:07.286810 sv_algorithm_assistance_LP4_1600
4920 13:45:07.293166 ============ PULL DRAM RESETB DOWN ============
4921 13:45:07.296733 ========== PULL DRAM RESETB DOWN end =========
4922 13:45:07.299619 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4923 13:45:07.303182 ===================================
4924 13:45:07.306687 LPDDR4 DRAM CONFIGURATION
4925 13:45:07.309446 ===================================
4926 13:45:07.313080 EX_ROW_EN[0] = 0x0
4927 13:45:07.313163 EX_ROW_EN[1] = 0x0
4928 13:45:07.316686 LP4Y_EN = 0x0
4929 13:45:07.316768 WORK_FSP = 0x0
4930 13:45:07.319491 WL = 0x3
4931 13:45:07.319573 RL = 0x3
4932 13:45:07.323106 BL = 0x2
4933 13:45:07.323188 RPST = 0x0
4934 13:45:07.326640 RD_PRE = 0x0
4935 13:45:07.326722 WR_PRE = 0x1
4936 13:45:07.330083 WR_PST = 0x0
4937 13:45:07.330165 DBI_WR = 0x0
4938 13:45:07.332688 DBI_RD = 0x0
4939 13:45:07.332771 OTF = 0x1
4940 13:45:07.336168 ===================================
4941 13:45:07.339851 ===================================
4942 13:45:07.343303 ANA top config
4943 13:45:07.346061 ===================================
4944 13:45:07.346144 DLL_ASYNC_EN = 0
4945 13:45:07.349741 ALL_SLAVE_EN = 1
4946 13:45:07.353102 NEW_RANK_MODE = 1
4947 13:45:07.356448 DLL_IDLE_MODE = 1
4948 13:45:07.359617 LP45_APHY_COMB_EN = 1
4949 13:45:07.359699 TX_ODT_DIS = 1
4950 13:45:07.363359 NEW_8X_MODE = 1
4951 13:45:07.366147 ===================================
4952 13:45:07.369897 ===================================
4953 13:45:07.372959 data_rate = 1866
4954 13:45:07.376230 CKR = 1
4955 13:45:07.379917 DQ_P2S_RATIO = 8
4956 13:45:07.382635 ===================================
4957 13:45:07.382725 CA_P2S_RATIO = 8
4958 13:45:07.386247 DQ_CA_OPEN = 0
4959 13:45:07.389778 DQ_SEMI_OPEN = 0
4960 13:45:07.392607 CA_SEMI_OPEN = 0
4961 13:45:07.396227 CA_FULL_RATE = 0
4962 13:45:07.399749 DQ_CKDIV4_EN = 1
4963 13:45:07.399831 CA_CKDIV4_EN = 1
4964 13:45:07.403114 CA_PREDIV_EN = 0
4965 13:45:07.406360 PH8_DLY = 0
4966 13:45:07.409931 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4967 13:45:07.413313 DQ_AAMCK_DIV = 4
4968 13:45:07.416245 CA_AAMCK_DIV = 4
4969 13:45:07.416327 CA_ADMCK_DIV = 4
4970 13:45:07.419825 DQ_TRACK_CA_EN = 0
4971 13:45:07.423412 CA_PICK = 933
4972 13:45:07.426316 CA_MCKIO = 933
4973 13:45:07.429828 MCKIO_SEMI = 0
4974 13:45:07.432682 PLL_FREQ = 3732
4975 13:45:07.436147 DQ_UI_PI_RATIO = 32
4976 13:45:07.436229 CA_UI_PI_RATIO = 0
4977 13:45:07.439548 ===================================
4978 13:45:07.442994 ===================================
4979 13:45:07.446529 memory_type:LPDDR4
4980 13:45:07.449382 GP_NUM : 10
4981 13:45:07.449465 SRAM_EN : 1
4982 13:45:07.452863 MD32_EN : 0
4983 13:45:07.456324 ===================================
4984 13:45:07.459272 [ANA_INIT] >>>>>>>>>>>>>>
4985 13:45:07.462834 <<<<<< [CONFIGURE PHASE]: ANA_TX
4986 13:45:07.466401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4987 13:45:07.469180 ===================================
4988 13:45:07.469273 data_rate = 1866,PCW = 0X8f00
4989 13:45:07.472634 ===================================
4990 13:45:07.475990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4991 13:45:07.482879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 13:45:07.489937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 13:45:07.492867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4994 13:45:07.495868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4995 13:45:07.499357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4996 13:45:07.502799 [ANA_INIT] flow start
4997 13:45:07.502889 [ANA_INIT] PLL >>>>>>>>
4998 13:45:07.506381 [ANA_INIT] PLL <<<<<<<<
4999 13:45:07.509860 [ANA_INIT] MIDPI >>>>>>>>
5000 13:45:07.509947 [ANA_INIT] MIDPI <<<<<<<<
5001 13:45:07.512604 [ANA_INIT] DLL >>>>>>>>
5002 13:45:07.515999 [ANA_INIT] flow end
5003 13:45:07.519396 ============ LP4 DIFF to SE enter ============
5004 13:45:07.522824 ============ LP4 DIFF to SE exit ============
5005 13:45:07.526271 [ANA_INIT] <<<<<<<<<<<<<
5006 13:45:07.529715 [Flow] Enable top DCM control >>>>>
5007 13:45:07.532632 [Flow] Enable top DCM control <<<<<
5008 13:45:07.536116 Enable DLL master slave shuffle
5009 13:45:07.539696 ==============================================================
5010 13:45:07.542414 Gating Mode config
5011 13:45:07.549462 ==============================================================
5012 13:45:07.549550 Config description:
5013 13:45:07.559247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5014 13:45:07.565738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5015 13:45:07.572173 SELPH_MODE 0: By rank 1: By Phase
5016 13:45:07.575828 ==============================================================
5017 13:45:07.579386 GAT_TRACK_EN = 1
5018 13:45:07.582225 RX_GATING_MODE = 2
5019 13:45:07.585789 RX_GATING_TRACK_MODE = 2
5020 13:45:07.589240 SELPH_MODE = 1
5021 13:45:07.592603 PICG_EARLY_EN = 1
5022 13:45:07.595825 VALID_LAT_VALUE = 1
5023 13:45:07.599264 ==============================================================
5024 13:45:07.602092 Enter into Gating configuration >>>>
5025 13:45:07.605628 Exit from Gating configuration <<<<
5026 13:45:07.608802 Enter into DVFS_PRE_config >>>>>
5027 13:45:07.621834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5028 13:45:07.625858 Exit from DVFS_PRE_config <<<<<
5029 13:45:07.628725 Enter into PICG configuration >>>>
5030 13:45:07.632177 Exit from PICG configuration <<<<
5031 13:45:07.632306 [RX_INPUT] configuration >>>>>
5032 13:45:07.635237 [RX_INPUT] configuration <<<<<
5033 13:45:07.641680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5034 13:45:07.645048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5035 13:45:07.652113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 13:45:07.658266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 13:45:07.665294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 13:45:07.671759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 13:45:07.675300 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5040 13:45:07.678955 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5041 13:45:07.685411 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5042 13:45:07.688218 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5043 13:45:07.691935 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5044 13:45:07.695481 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 13:45:07.698290 ===================================
5046 13:45:07.701638 LPDDR4 DRAM CONFIGURATION
5047 13:45:07.704902 ===================================
5048 13:45:07.708280 EX_ROW_EN[0] = 0x0
5049 13:45:07.708400 EX_ROW_EN[1] = 0x0
5050 13:45:07.711698 LP4Y_EN = 0x0
5051 13:45:07.711781 WORK_FSP = 0x0
5052 13:45:07.715235 WL = 0x3
5053 13:45:07.715316 RL = 0x3
5054 13:45:07.718694 BL = 0x2
5055 13:45:07.718780 RPST = 0x0
5056 13:45:07.721603 RD_PRE = 0x0
5057 13:45:07.721687 WR_PRE = 0x1
5058 13:45:07.725065 WR_PST = 0x0
5059 13:45:07.725149 DBI_WR = 0x0
5060 13:45:07.728731 DBI_RD = 0x0
5061 13:45:07.728815 OTF = 0x1
5062 13:45:07.731532 ===================================
5063 13:45:07.738397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5064 13:45:07.741643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5065 13:45:07.744919 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5066 13:45:07.748253 ===================================
5067 13:45:07.751500 LPDDR4 DRAM CONFIGURATION
5068 13:45:07.754628 ===================================
5069 13:45:07.758332 EX_ROW_EN[0] = 0x10
5070 13:45:07.758481 EX_ROW_EN[1] = 0x0
5071 13:45:07.761263 LP4Y_EN = 0x0
5072 13:45:07.761344 WORK_FSP = 0x0
5073 13:45:07.764582 WL = 0x3
5074 13:45:07.764663 RL = 0x3
5075 13:45:07.768052 BL = 0x2
5076 13:45:07.768133 RPST = 0x0
5077 13:45:07.771869 RD_PRE = 0x0
5078 13:45:07.771951 WR_PRE = 0x1
5079 13:45:07.774813 WR_PST = 0x0
5080 13:45:07.774894 DBI_WR = 0x0
5081 13:45:07.777670 DBI_RD = 0x0
5082 13:45:07.777752 OTF = 0x1
5083 13:45:07.781297 ===================================
5084 13:45:07.787703 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5085 13:45:07.792745 nWR fixed to 30
5086 13:45:07.796360 [ModeRegInit_LP4] CH0 RK0
5087 13:45:07.796460 [ModeRegInit_LP4] CH0 RK1
5088 13:45:07.799258 [ModeRegInit_LP4] CH1 RK0
5089 13:45:07.802684 [ModeRegInit_LP4] CH1 RK1
5090 13:45:07.802766 match AC timing 9
5091 13:45:07.809102 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5092 13:45:07.812485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5093 13:45:07.815862 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5094 13:45:07.822728 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5095 13:45:07.826085 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5096 13:45:07.826168 ==
5097 13:45:07.829384 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 13:45:07.832277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 13:45:07.832398 ==
5100 13:45:07.839327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 13:45:07.845630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5102 13:45:07.849056 [CA 0] Center 37 (6~68) winsize 63
5103 13:45:07.852396 [CA 1] Center 37 (7~68) winsize 62
5104 13:45:07.855271 [CA 2] Center 34 (4~65) winsize 62
5105 13:45:07.858792 [CA 3] Center 34 (3~65) winsize 63
5106 13:45:07.862251 [CA 4] Center 33 (3~64) winsize 62
5107 13:45:07.865111 [CA 5] Center 32 (2~62) winsize 61
5108 13:45:07.865195
5109 13:45:07.868664 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5110 13:45:07.868747
5111 13:45:07.872137 [CATrainingPosCal] consider 1 rank data
5112 13:45:07.875315 u2DelayCellTimex100 = 270/100 ps
5113 13:45:07.878510 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5114 13:45:07.881894 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5115 13:45:07.884956 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5116 13:45:07.891474 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5117 13:45:07.895196 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5118 13:45:07.898236 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5119 13:45:07.898318
5120 13:45:07.901748 CA PerBit enable=1, Macro0, CA PI delay=32
5121 13:45:07.901843
5122 13:45:07.905321 [CBTSetCACLKResult] CA Dly = 32
5123 13:45:07.905403 CS Dly: 5 (0~36)
5124 13:45:07.905469 ==
5125 13:45:07.908171 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 13:45:07.915130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 13:45:07.915215 ==
5128 13:45:07.917993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 13:45:07.925136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5130 13:45:07.928434 [CA 0] Center 37 (6~68) winsize 63
5131 13:45:07.932060 [CA 1] Center 37 (6~68) winsize 63
5132 13:45:07.935333 [CA 2] Center 34 (4~65) winsize 62
5133 13:45:07.938058 [CA 3] Center 34 (4~65) winsize 62
5134 13:45:07.941417 [CA 4] Center 33 (3~64) winsize 62
5135 13:45:07.945100 [CA 5] Center 32 (2~62) winsize 61
5136 13:45:07.945183
5137 13:45:07.948600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5138 13:45:07.948692
5139 13:45:07.951483 [CATrainingPosCal] consider 2 rank data
5140 13:45:07.954895 u2DelayCellTimex100 = 270/100 ps
5141 13:45:07.958382 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5142 13:45:07.961257 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5143 13:45:07.968482 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5144 13:45:07.971384 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5145 13:45:07.974931 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5146 13:45:07.977700 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5147 13:45:07.977784
5148 13:45:07.981146 CA PerBit enable=1, Macro0, CA PI delay=32
5149 13:45:07.981230
5150 13:45:07.984655 [CBTSetCACLKResult] CA Dly = 32
5151 13:45:07.984738 CS Dly: 5 (0~37)
5152 13:45:07.984841
5153 13:45:07.988286 ----->DramcWriteLeveling(PI) begin...
5154 13:45:07.991798 ==
5155 13:45:07.991935 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 13:45:07.997979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 13:45:07.998064 ==
5158 13:45:08.001730 Write leveling (Byte 0): 33 => 33
5159 13:45:08.005028 Write leveling (Byte 1): 28 => 28
5160 13:45:08.007740 DramcWriteLeveling(PI) end<-----
5161 13:45:08.007826
5162 13:45:08.007891 ==
5163 13:45:08.011097 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 13:45:08.014848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 13:45:08.014938 ==
5166 13:45:08.017873 [Gating] SW mode calibration
5167 13:45:08.025050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 13:45:08.027930 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5169 13:45:08.034849 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5170 13:45:08.038123 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 13:45:08.041561 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 13:45:08.048083 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 13:45:08.051597 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 13:45:08.054424 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5175 13:45:08.061502 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5176 13:45:08.064890 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
5177 13:45:08.068298 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5178 13:45:08.074832 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 13:45:08.077698 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 13:45:08.081492 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 13:45:08.087724 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 13:45:08.091274 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 13:45:08.094888 0 15 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5184 13:45:08.101289 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5185 13:45:08.104783 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5186 13:45:08.108128 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 13:45:08.114351 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 13:45:08.117961 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 13:45:08.120859 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 13:45:08.127865 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 13:45:08.131040 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5192 13:45:08.134330 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5193 13:45:08.140938 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5194 13:45:08.144398 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:45:08.147364 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:45:08.154462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:45:08.157473 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:45:08.161156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:45:08.164308 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:45:08.170796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:45:08.174108 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:45:08.177562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:45:08.184127 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 13:45:08.187571 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 13:45:08.191240 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 13:45:08.197665 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 13:45:08.201145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5208 13:45:08.204726 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5209 13:45:08.207587 Total UI for P1: 0, mck2ui 16
5210 13:45:08.211198 best dqsien dly found for B0: ( 1, 2, 24)
5211 13:45:08.217809 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5212 13:45:08.221101 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 13:45:08.224680 Total UI for P1: 0, mck2ui 16
5214 13:45:08.227524 best dqsien dly found for B1: ( 1, 3, 0)
5215 13:45:08.231066 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5216 13:45:08.234110 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5217 13:45:08.234193
5218 13:45:08.237649 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5219 13:45:08.241271 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5220 13:45:08.244159 [Gating] SW calibration Done
5221 13:45:08.244244 ==
5222 13:45:08.247629 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 13:45:08.251078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 13:45:08.251162 ==
5225 13:45:08.254557 RX Vref Scan: 0
5226 13:45:08.254647
5227 13:45:08.257870 RX Vref 0 -> 0, step: 1
5228 13:45:08.257975
5229 13:45:08.258040 RX Delay -80 -> 252, step: 8
5230 13:45:08.264351 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5231 13:45:08.267122 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5232 13:45:08.270700 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5233 13:45:08.274286 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5234 13:45:08.277449 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5235 13:45:08.280892 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5236 13:45:08.287353 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5237 13:45:08.290734 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5238 13:45:08.293984 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5239 13:45:08.296884 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5240 13:45:08.300563 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5241 13:45:08.307067 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5242 13:45:08.310760 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5243 13:45:08.313683 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5244 13:45:08.317349 iDelay=200, Bit 14, Center 107 (16 ~ 199) 184
5245 13:45:08.320152 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5246 13:45:08.320233 ==
5247 13:45:08.323559 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 13:45:08.330162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 13:45:08.330246 ==
5250 13:45:08.330311 DQS Delay:
5251 13:45:08.333614 DQS0 = 0, DQS1 = 0
5252 13:45:08.333723 DQM Delay:
5253 13:45:08.333821 DQM0 = 103, DQM1 = 96
5254 13:45:08.337228 DQ Delay:
5255 13:45:08.340085 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5256 13:45:08.343653 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5257 13:45:08.347228 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5258 13:45:08.350208 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5259 13:45:08.350290
5260 13:45:08.350355
5261 13:45:08.350414 ==
5262 13:45:08.353656 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 13:45:08.357196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 13:45:08.357280 ==
5265 13:45:08.357345
5266 13:45:08.357405
5267 13:45:08.359944 TX Vref Scan disable
5268 13:45:08.363477 == TX Byte 0 ==
5269 13:45:08.366896 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5270 13:45:08.370149 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5271 13:45:08.373686 == TX Byte 1 ==
5272 13:45:08.376477 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5273 13:45:08.380057 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5274 13:45:08.380139 ==
5275 13:45:08.383601 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 13:45:08.389853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 13:45:08.389939 ==
5278 13:45:08.390005
5279 13:45:08.390065
5280 13:45:08.390123 TX Vref Scan disable
5281 13:45:08.393913 == TX Byte 0 ==
5282 13:45:08.397329 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5283 13:45:08.403926 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5284 13:45:08.404032 == TX Byte 1 ==
5285 13:45:08.407560 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5286 13:45:08.414127 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5287 13:45:08.414211
5288 13:45:08.414276 [DATLAT]
5289 13:45:08.414336 Freq=933, CH0 RK0
5290 13:45:08.414394
5291 13:45:08.417242 DATLAT Default: 0xd
5292 13:45:08.417323 0, 0xFFFF, sum = 0
5293 13:45:08.420312 1, 0xFFFF, sum = 0
5294 13:45:08.420436 2, 0xFFFF, sum = 0
5295 13:45:08.424111 3, 0xFFFF, sum = 0
5296 13:45:08.426918 4, 0xFFFF, sum = 0
5297 13:45:08.427012 5, 0xFFFF, sum = 0
5298 13:45:08.430477 6, 0xFFFF, sum = 0
5299 13:45:08.430560 7, 0xFFFF, sum = 0
5300 13:45:08.433765 8, 0xFFFF, sum = 0
5301 13:45:08.433849 9, 0xFFFF, sum = 0
5302 13:45:08.437082 10, 0x0, sum = 1
5303 13:45:08.437165 11, 0x0, sum = 2
5304 13:45:08.437231 12, 0x0, sum = 3
5305 13:45:08.440627 13, 0x0, sum = 4
5306 13:45:08.440711 best_step = 11
5307 13:45:08.440774
5308 13:45:08.444204 ==
5309 13:45:08.444286 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 13:45:08.450592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 13:45:08.450675 ==
5312 13:45:08.450740 RX Vref Scan: 1
5313 13:45:08.450800
5314 13:45:08.453535 RX Vref 0 -> 0, step: 1
5315 13:45:08.453617
5316 13:45:08.457056 RX Delay -45 -> 252, step: 4
5317 13:45:08.457138
5318 13:45:08.460568 Set Vref, RX VrefLevel [Byte0]: 54
5319 13:45:08.463372 [Byte1]: 51
5320 13:45:08.463483
5321 13:45:08.466981 Final RX Vref Byte 0 = 54 to rank0
5322 13:45:08.470621 Final RX Vref Byte 1 = 51 to rank0
5323 13:45:08.473344 Final RX Vref Byte 0 = 54 to rank1
5324 13:45:08.476579 Final RX Vref Byte 1 = 51 to rank1==
5325 13:45:08.480268 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 13:45:08.483818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 13:45:08.483902 ==
5328 13:45:08.486701 DQS Delay:
5329 13:45:08.486783 DQS0 = 0, DQS1 = 0
5330 13:45:08.490351 DQM Delay:
5331 13:45:08.490434 DQM0 = 104, DQM1 = 97
5332 13:45:08.490499 DQ Delay:
5333 13:45:08.497274 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5334 13:45:08.500133 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5335 13:45:08.503813 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5336 13:45:08.506812 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =106
5337 13:45:08.506894
5338 13:45:08.506959
5339 13:45:08.513865 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5340 13:45:08.517158 CH0 RK0: MR19=505, MR18=2F26
5341 13:45:08.523484 CH0_RK0: MR19=0x505, MR18=0x2F26, DQSOSC=407, MR23=63, INC=65, DEC=43
5342 13:45:08.523569
5343 13:45:08.527005 ----->DramcWriteLeveling(PI) begin...
5344 13:45:08.527089 ==
5345 13:45:08.530312 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 13:45:08.533413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 13:45:08.533496 ==
5348 13:45:08.536689 Write leveling (Byte 0): 31 => 31
5349 13:45:08.539976 Write leveling (Byte 1): 27 => 27
5350 13:45:08.543560 DramcWriteLeveling(PI) end<-----
5351 13:45:08.543644
5352 13:45:08.543709 ==
5353 13:45:08.546481 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 13:45:08.550217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 13:45:08.552934 ==
5356 13:45:08.553017 [Gating] SW mode calibration
5357 13:45:08.560048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 13:45:08.566655 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5359 13:45:08.570240 0 14 0 | B1->B0 | 3232 302f | 1 1 | (1 1) (0 0)
5360 13:45:08.576564 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 13:45:08.580100 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 13:45:08.582836 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 13:45:08.589462 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 13:45:08.592926 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 13:45:08.596403 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 13:45:08.603383 0 14 28 | B1->B0 | 2929 2f2f | 0 0 | (0 1) (0 1)
5367 13:45:08.606230 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (1 0) (0 0)
5368 13:45:08.609938 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 13:45:08.616196 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 13:45:08.619861 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 13:45:08.623162 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 13:45:08.626323 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 13:45:08.633466 0 15 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5374 13:45:08.636252 0 15 28 | B1->B0 | 3a3a 3534 | 0 1 | (0 0) (0 0)
5375 13:45:08.639854 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5376 13:45:08.646257 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 13:45:08.649715 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 13:45:08.653055 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 13:45:08.659322 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 13:45:08.662605 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 13:45:08.666084 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5382 13:45:08.672823 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5383 13:45:08.676215 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 13:45:08.679720 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 13:45:08.686265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 13:45:08.689717 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:45:08.692458 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:45:08.699220 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:45:08.702621 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:45:08.706072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:45:08.712880 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:45:08.715813 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 13:45:08.719444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:45:08.726016 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:45:08.728875 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:45:08.732207 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:45:08.738886 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 13:45:08.742433 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 13:45:08.745837 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 13:45:08.748711 Total UI for P1: 0, mck2ui 16
5401 13:45:08.752265 best dqsien dly found for B0: ( 1, 2, 28)
5402 13:45:08.755348 Total UI for P1: 0, mck2ui 16
5403 13:45:08.758949 best dqsien dly found for B1: ( 1, 2, 28)
5404 13:45:08.762532 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5405 13:45:08.765477 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5406 13:45:08.765566
5407 13:45:08.772279 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5408 13:45:08.775293 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5409 13:45:08.775376 [Gating] SW calibration Done
5410 13:45:08.778454 ==
5411 13:45:08.782241 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 13:45:08.785333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 13:45:08.785443 ==
5414 13:45:08.785533 RX Vref Scan: 0
5415 13:45:08.785596
5416 13:45:08.788453 RX Vref 0 -> 0, step: 1
5417 13:45:08.788536
5418 13:45:08.792152 RX Delay -80 -> 252, step: 8
5419 13:45:08.795583 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5420 13:45:08.798358 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5421 13:45:08.802119 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5422 13:45:08.808859 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5423 13:45:08.812256 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5424 13:45:08.814957 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5425 13:45:08.818285 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5426 13:45:08.821673 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5427 13:45:08.825390 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5428 13:45:08.831939 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5429 13:45:08.835448 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5430 13:45:08.838415 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5431 13:45:08.841877 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5432 13:45:08.845121 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5433 13:45:08.848536 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5434 13:45:08.854872 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5435 13:45:08.854955 ==
5436 13:45:08.858462 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 13:45:08.862208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 13:45:08.862292 ==
5439 13:45:08.862357 DQS Delay:
5440 13:45:08.865004 DQS0 = 0, DQS1 = 0
5441 13:45:08.865086 DQM Delay:
5442 13:45:08.868485 DQM0 = 106, DQM1 = 93
5443 13:45:08.868567 DQ Delay:
5444 13:45:08.872058 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5445 13:45:08.874962 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5446 13:45:08.878502 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5447 13:45:08.881953 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5448 13:45:08.882093
5449 13:45:08.882211
5450 13:45:08.882329 ==
5451 13:45:08.885778 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 13:45:08.888532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 13:45:08.891977 ==
5454 13:45:08.892059
5455 13:45:08.892123
5456 13:45:08.892182 TX Vref Scan disable
5457 13:45:08.894747 == TX Byte 0 ==
5458 13:45:08.898102 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5459 13:45:08.901924 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5460 13:45:08.905098 == TX Byte 1 ==
5461 13:45:08.908241 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5462 13:45:08.912110 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5463 13:45:08.914852 ==
5464 13:45:08.918011 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 13:45:08.921830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 13:45:08.921914 ==
5467 13:45:08.921979
5468 13:45:08.922039
5469 13:45:08.924889 TX Vref Scan disable
5470 13:45:08.924971 == TX Byte 0 ==
5471 13:45:08.931709 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5472 13:45:08.934621 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5473 13:45:08.934704 == TX Byte 1 ==
5474 13:45:08.941749 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5475 13:45:08.944715 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5476 13:45:08.944800
5477 13:45:08.944866 [DATLAT]
5478 13:45:08.948097 Freq=933, CH0 RK1
5479 13:45:08.948178
5480 13:45:08.948243 DATLAT Default: 0xb
5481 13:45:08.951529 0, 0xFFFF, sum = 0
5482 13:45:08.951619 1, 0xFFFF, sum = 0
5483 13:45:08.954851 2, 0xFFFF, sum = 0
5484 13:45:08.954934 3, 0xFFFF, sum = 0
5485 13:45:08.958304 4, 0xFFFF, sum = 0
5486 13:45:08.958388 5, 0xFFFF, sum = 0
5487 13:45:08.961781 6, 0xFFFF, sum = 0
5488 13:45:08.961868 7, 0xFFFF, sum = 0
5489 13:45:08.964720 8, 0xFFFF, sum = 0
5490 13:45:08.968252 9, 0xFFFF, sum = 0
5491 13:45:08.968335 10, 0x0, sum = 1
5492 13:45:08.968445 11, 0x0, sum = 2
5493 13:45:08.971915 12, 0x0, sum = 3
5494 13:45:08.971998 13, 0x0, sum = 4
5495 13:45:08.974837 best_step = 11
5496 13:45:08.974918
5497 13:45:08.974983 ==
5498 13:45:08.978454 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 13:45:08.981241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 13:45:08.981396 ==
5501 13:45:08.984827 RX Vref Scan: 0
5502 13:45:08.984909
5503 13:45:08.984975 RX Vref 0 -> 0, step: 1
5504 13:45:08.985036
5505 13:45:08.988325 RX Delay -45 -> 252, step: 4
5506 13:45:08.995159 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5507 13:45:08.998809 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5508 13:45:09.001675 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5509 13:45:09.005251 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5510 13:45:09.008723 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5511 13:45:09.015124 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5512 13:45:09.018614 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5513 13:45:09.022035 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5514 13:45:09.025388 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5515 13:45:09.028765 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5516 13:45:09.031900 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5517 13:45:09.038696 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5518 13:45:09.041834 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5519 13:45:09.045365 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5520 13:45:09.048252 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5521 13:45:09.051960 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5522 13:45:09.055180 ==
5523 13:45:09.058357 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 13:45:09.061654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 13:45:09.061740 ==
5526 13:45:09.061805 DQS Delay:
5527 13:45:09.065283 DQS0 = 0, DQS1 = 0
5528 13:45:09.065368 DQM Delay:
5529 13:45:09.068350 DQM0 = 104, DQM1 = 95
5530 13:45:09.068449 DQ Delay:
5531 13:45:09.071641 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5532 13:45:09.075236 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5533 13:45:09.078206 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =88
5534 13:45:09.081681 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5535 13:45:09.081765
5536 13:45:09.081829
5537 13:45:09.091756 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5538 13:45:09.091845 CH0 RK1: MR19=505, MR18=2A02
5539 13:45:09.098568 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5540 13:45:09.101316 [RxdqsGatingPostProcess] freq 933
5541 13:45:09.108566 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5542 13:45:09.111375 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 13:45:09.115004 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 13:45:09.117844 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 13:45:09.121450 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 13:45:09.125019 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 13:45:09.127963 best DQS1 dly(2T, 0.5T) = (0, 10)
5548 13:45:09.128045 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 13:45:09.131498 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5550 13:45:09.134448 Pre-setting of DQS Precalculation
5551 13:45:09.141473 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5552 13:45:09.141555 ==
5553 13:45:09.144229 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 13:45:09.147652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 13:45:09.147730 ==
5556 13:45:09.154607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 13:45:09.161221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5558 13:45:09.164292 [CA 0] Center 36 (6~67) winsize 62
5559 13:45:09.167584 [CA 1] Center 36 (6~67) winsize 62
5560 13:45:09.170894 [CA 2] Center 34 (4~65) winsize 62
5561 13:45:09.174098 [CA 3] Center 34 (4~65) winsize 62
5562 13:45:09.177367 [CA 4] Center 34 (4~64) winsize 61
5563 13:45:09.181033 [CA 5] Center 33 (3~64) winsize 62
5564 13:45:09.181117
5565 13:45:09.184116 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5566 13:45:09.184198
5567 13:45:09.187772 [CATrainingPosCal] consider 1 rank data
5568 13:45:09.191041 u2DelayCellTimex100 = 270/100 ps
5569 13:45:09.194009 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 13:45:09.197633 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 13:45:09.201160 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 13:45:09.204106 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5573 13:45:09.207321 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 13:45:09.210764 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 13:45:09.210846
5576 13:45:09.217829 CA PerBit enable=1, Macro0, CA PI delay=33
5577 13:45:09.217912
5578 13:45:09.217976 [CBTSetCACLKResult] CA Dly = 33
5579 13:45:09.220555 CS Dly: 6 (0~37)
5580 13:45:09.220636 ==
5581 13:45:09.224225 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 13:45:09.227797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 13:45:09.227880 ==
5584 13:45:09.234359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 13:45:09.240818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5586 13:45:09.244266 [CA 0] Center 36 (6~67) winsize 62
5587 13:45:09.247575 [CA 1] Center 37 (7~68) winsize 62
5588 13:45:09.250910 [CA 2] Center 35 (4~66) winsize 63
5589 13:45:09.253682 [CA 3] Center 34 (4~65) winsize 62
5590 13:45:09.256991 [CA 4] Center 34 (4~65) winsize 62
5591 13:45:09.260575 [CA 5] Center 33 (3~64) winsize 62
5592 13:45:09.260671
5593 13:45:09.264143 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5594 13:45:09.264253
5595 13:45:09.266906 [CATrainingPosCal] consider 2 rank data
5596 13:45:09.270236 u2DelayCellTimex100 = 270/100 ps
5597 13:45:09.274089 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5598 13:45:09.276972 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5599 13:45:09.280331 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5600 13:45:09.283681 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5601 13:45:09.287250 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5602 13:45:09.293546 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5603 13:45:09.293631
5604 13:45:09.296967 CA PerBit enable=1, Macro0, CA PI delay=33
5605 13:45:09.297050
5606 13:45:09.300096 [CBTSetCACLKResult] CA Dly = 33
5607 13:45:09.300178 CS Dly: 7 (0~39)
5608 13:45:09.300244
5609 13:45:09.303452 ----->DramcWriteLeveling(PI) begin...
5610 13:45:09.303538 ==
5611 13:45:09.306549 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 13:45:09.310085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 13:45:09.313521 ==
5614 13:45:09.316970 Write leveling (Byte 0): 25 => 25
5615 13:45:09.317055 Write leveling (Byte 1): 28 => 28
5616 13:45:09.319933 DramcWriteLeveling(PI) end<-----
5617 13:45:09.320016
5618 13:45:09.320081 ==
5619 13:45:09.323105 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 13:45:09.329967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 13:45:09.330055 ==
5622 13:45:09.333516 [Gating] SW mode calibration
5623 13:45:09.340034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 13:45:09.343569 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5625 13:45:09.350192 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 13:45:09.353497 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 13:45:09.356745 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 13:45:09.363303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 13:45:09.366701 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 13:45:09.370244 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 13:45:09.372986 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (1 0) (0 0)
5632 13:45:09.379950 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
5633 13:45:09.383441 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 13:45:09.386970 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 13:45:09.393154 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 13:45:09.396792 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 13:45:09.400310 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 13:45:09.406785 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 13:45:09.409647 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (0 0) (1 1)
5640 13:45:09.413223 0 15 28 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
5641 13:45:09.420215 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 13:45:09.423499 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 13:45:09.426756 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 13:45:09.433456 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 13:45:09.436829 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 13:45:09.439843 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 13:45:09.446751 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 13:45:09.450091 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 13:45:09.453101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 13:45:09.459494 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 13:45:09.462932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 13:45:09.466335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 13:45:09.473011 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 13:45:09.476601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 13:45:09.479475 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 13:45:09.486563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 13:45:09.489916 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 13:45:09.492783 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 13:45:09.499685 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 13:45:09.503249 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 13:45:09.506030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 13:45:09.509675 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 13:45:09.516126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5664 13:45:09.519666 Total UI for P1: 0, mck2ui 16
5665 13:45:09.523129 best dqsien dly found for B0: ( 1, 2, 22)
5666 13:45:09.526129 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5667 13:45:09.529493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 13:45:09.533069 Total UI for P1: 0, mck2ui 16
5669 13:45:09.536402 best dqsien dly found for B1: ( 1, 2, 26)
5670 13:45:09.539928 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5671 13:45:09.542903 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5672 13:45:09.542984
5673 13:45:09.549884 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5674 13:45:09.553126 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5675 13:45:09.556386 [Gating] SW calibration Done
5676 13:45:09.556465 ==
5677 13:45:09.559559 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 13:45:09.562803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 13:45:09.562882 ==
5680 13:45:09.562946 RX Vref Scan: 0
5681 13:45:09.563006
5682 13:45:09.566023 RX Vref 0 -> 0, step: 1
5683 13:45:09.566099
5684 13:45:09.569460 RX Delay -80 -> 252, step: 8
5685 13:45:09.572879 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5686 13:45:09.576259 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5687 13:45:09.579487 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5688 13:45:09.586355 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5689 13:45:09.589272 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5690 13:45:09.592735 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5691 13:45:09.596080 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5692 13:45:09.599548 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5693 13:45:09.603018 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5694 13:45:09.609463 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5695 13:45:09.613001 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5696 13:45:09.615841 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5697 13:45:09.619410 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5698 13:45:09.623060 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5699 13:45:09.629591 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5700 13:45:09.632325 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5701 13:45:09.632444 ==
5702 13:45:09.635853 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 13:45:09.639340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 13:45:09.639423 ==
5705 13:45:09.642823 DQS Delay:
5706 13:45:09.642930 DQS0 = 0, DQS1 = 0
5707 13:45:09.643043 DQM Delay:
5708 13:45:09.645673 DQM0 = 103, DQM1 = 98
5709 13:45:09.645759 DQ Delay:
5710 13:45:09.649336 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5711 13:45:09.653308 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =107
5712 13:45:09.656196 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5713 13:45:09.659126 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5714 13:45:09.659208
5715 13:45:09.659272
5716 13:45:09.662431 ==
5717 13:45:09.666025 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 13:45:09.669413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 13:45:09.669495 ==
5720 13:45:09.669560
5721 13:45:09.669619
5722 13:45:09.672722 TX Vref Scan disable
5723 13:45:09.672803 == TX Byte 0 ==
5724 13:45:09.675898 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5725 13:45:09.682276 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5726 13:45:09.682362 == TX Byte 1 ==
5727 13:45:09.685739 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5728 13:45:09.691996 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5729 13:45:09.692089 ==
5730 13:45:09.696049 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 13:45:09.698909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 13:45:09.698985 ==
5733 13:45:09.699059
5734 13:45:09.699117
5735 13:45:09.702294 TX Vref Scan disable
5736 13:45:09.705629 == TX Byte 0 ==
5737 13:45:09.708916 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5738 13:45:09.712395 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5739 13:45:09.715864 == TX Byte 1 ==
5740 13:45:09.718632 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5741 13:45:09.722171 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5742 13:45:09.722253
5743 13:45:09.725688 [DATLAT]
5744 13:45:09.725770 Freq=933, CH1 RK0
5745 13:45:09.725835
5746 13:45:09.728674 DATLAT Default: 0xd
5747 13:45:09.728761 0, 0xFFFF, sum = 0
5748 13:45:09.732188 1, 0xFFFF, sum = 0
5749 13:45:09.732270 2, 0xFFFF, sum = 0
5750 13:45:09.735838 3, 0xFFFF, sum = 0
5751 13:45:09.735921 4, 0xFFFF, sum = 0
5752 13:45:09.739231 5, 0xFFFF, sum = 0
5753 13:45:09.739314 6, 0xFFFF, sum = 0
5754 13:45:09.742128 7, 0xFFFF, sum = 0
5755 13:45:09.742212 8, 0xFFFF, sum = 0
5756 13:45:09.745498 9, 0xFFFF, sum = 0
5757 13:45:09.745581 10, 0x0, sum = 1
5758 13:45:09.749033 11, 0x0, sum = 2
5759 13:45:09.749116 12, 0x0, sum = 3
5760 13:45:09.751910 13, 0x0, sum = 4
5761 13:45:09.751993 best_step = 11
5762 13:45:09.752058
5763 13:45:09.752117 ==
5764 13:45:09.755521 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 13:45:09.759072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 13:45:09.761972 ==
5767 13:45:09.762054 RX Vref Scan: 1
5768 13:45:09.762120
5769 13:45:09.765396 RX Vref 0 -> 0, step: 1
5770 13:45:09.765478
5771 13:45:09.768850 RX Delay -45 -> 252, step: 4
5772 13:45:09.768932
5773 13:45:09.772358 Set Vref, RX VrefLevel [Byte0]: 56
5774 13:45:09.772462 [Byte1]: 53
5775 13:45:09.777428
5776 13:45:09.777510 Final RX Vref Byte 0 = 56 to rank0
5777 13:45:09.780236 Final RX Vref Byte 1 = 53 to rank0
5778 13:45:09.783775 Final RX Vref Byte 0 = 56 to rank1
5779 13:45:09.787203 Final RX Vref Byte 1 = 53 to rank1==
5780 13:45:09.790323 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 13:45:09.796953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 13:45:09.797042 ==
5783 13:45:09.797108 DQS Delay:
5784 13:45:09.800151 DQS0 = 0, DQS1 = 0
5785 13:45:09.800234 DQM Delay:
5786 13:45:09.800298 DQM0 = 103, DQM1 = 98
5787 13:45:09.803263 DQ Delay:
5788 13:45:09.806477 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5789 13:45:09.809829 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5790 13:45:09.813468 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5791 13:45:09.816395 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =104
5792 13:45:09.816479
5793 13:45:09.816543
5794 13:45:09.823327 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5795 13:45:09.826755 CH1 RK0: MR19=505, MR18=172E
5796 13:45:09.833247 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5797 13:45:09.833332
5798 13:45:09.836502 ----->DramcWriteLeveling(PI) begin...
5799 13:45:09.836581 ==
5800 13:45:09.840060 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 13:45:09.842882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 13:45:09.846481 ==
5803 13:45:09.849982 Write leveling (Byte 0): 31 => 31
5804 13:45:09.850064 Write leveling (Byte 1): 30 => 30
5805 13:45:09.852872 DramcWriteLeveling(PI) end<-----
5806 13:45:09.852954
5807 13:45:09.853018 ==
5808 13:45:09.856446 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 13:45:09.862873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 13:45:09.862956 ==
5811 13:45:09.866423 [Gating] SW mode calibration
5812 13:45:09.872874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5813 13:45:09.876242 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5814 13:45:09.882695 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 13:45:09.886176 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 13:45:09.889071 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 13:45:09.895630 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 13:45:09.898965 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 13:45:09.902191 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 13:45:09.909015 0 14 24 | B1->B0 | 2e2e 3030 | 0 1 | (0 1) (0 1)
5821 13:45:09.912461 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
5822 13:45:09.915804 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5823 13:45:09.922216 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 13:45:09.925666 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 13:45:09.928950 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 13:45:09.935471 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 13:45:09.938719 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5828 13:45:09.941916 0 15 24 | B1->B0 | 3434 2929 | 0 1 | (1 1) (0 0)
5829 13:45:09.948565 0 15 28 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
5830 13:45:09.951938 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 13:45:09.955516 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 13:45:09.961938 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 13:45:09.965588 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 13:45:09.968520 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 13:45:09.975038 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 13:45:09.978509 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5837 13:45:09.981809 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5838 13:45:09.988954 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 13:45:09.991833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 13:45:09.995394 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 13:45:09.998964 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 13:45:10.005326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 13:45:10.008617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 13:45:10.012030 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:45:10.018207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 13:45:10.021640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 13:45:10.025005 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 13:45:10.032180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 13:45:10.034931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 13:45:10.038483 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 13:45:10.045275 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 13:45:10.048177 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5853 13:45:10.051689 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 13:45:10.055201 Total UI for P1: 0, mck2ui 16
5855 13:45:10.058522 best dqsien dly found for B0: ( 1, 2, 24)
5856 13:45:10.061547 Total UI for P1: 0, mck2ui 16
5857 13:45:10.065268 best dqsien dly found for B1: ( 1, 2, 24)
5858 13:45:10.068609 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5859 13:45:10.071598 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5860 13:45:10.071675
5861 13:45:10.078064 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5862 13:45:10.081620 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5863 13:45:10.081701 [Gating] SW calibration Done
5864 13:45:10.085209 ==
5865 13:45:10.087890 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 13:45:10.091264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 13:45:10.091372 ==
5868 13:45:10.091518 RX Vref Scan: 0
5869 13:45:10.091614
5870 13:45:10.094865 RX Vref 0 -> 0, step: 1
5871 13:45:10.094944
5872 13:45:10.097756 RX Delay -80 -> 252, step: 8
5873 13:45:10.101370 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5874 13:45:10.105048 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5875 13:45:10.107933 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5876 13:45:10.114809 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5877 13:45:10.118403 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5878 13:45:10.121149 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5879 13:45:10.124518 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5880 13:45:10.128467 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5881 13:45:10.131272 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5882 13:45:10.134632 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5883 13:45:10.141492 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5884 13:45:10.144845 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5885 13:45:10.148210 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5886 13:45:10.151690 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5887 13:45:10.155010 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5888 13:45:10.161443 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5889 13:45:10.161530 ==
5890 13:45:10.165151 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 13:45:10.167855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 13:45:10.167938 ==
5893 13:45:10.168004 DQS Delay:
5894 13:45:10.171254 DQS0 = 0, DQS1 = 0
5895 13:45:10.171336 DQM Delay:
5896 13:45:10.174593 DQM0 = 102, DQM1 = 98
5897 13:45:10.174675 DQ Delay:
5898 13:45:10.178228 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5899 13:45:10.181370 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5900 13:45:10.184704 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5901 13:45:10.187686 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5902 13:45:10.187769
5903 13:45:10.187833
5904 13:45:10.187894 ==
5905 13:45:10.191174 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 13:45:10.198142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 13:45:10.198227 ==
5908 13:45:10.198293
5909 13:45:10.198353
5910 13:45:10.198411 TX Vref Scan disable
5911 13:45:10.201119 == TX Byte 0 ==
5912 13:45:10.204698 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5913 13:45:10.211254 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5914 13:45:10.211341 == TX Byte 1 ==
5915 13:45:10.214926 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5916 13:45:10.221116 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5917 13:45:10.221200 ==
5918 13:45:10.224599 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 13:45:10.228128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 13:45:10.228236 ==
5921 13:45:10.228329
5922 13:45:10.228434
5923 13:45:10.230906 TX Vref Scan disable
5924 13:45:10.230988 == TX Byte 0 ==
5925 13:45:10.237597 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5926 13:45:10.240885 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5927 13:45:10.240968 == TX Byte 1 ==
5928 13:45:10.247416 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5929 13:45:10.251415 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5930 13:45:10.251497
5931 13:45:10.251562 [DATLAT]
5932 13:45:10.254561 Freq=933, CH1 RK1
5933 13:45:10.254644
5934 13:45:10.254708 DATLAT Default: 0xb
5935 13:45:10.257610 0, 0xFFFF, sum = 0
5936 13:45:10.257693 1, 0xFFFF, sum = 0
5937 13:45:10.260950 2, 0xFFFF, sum = 0
5938 13:45:10.261033 3, 0xFFFF, sum = 0
5939 13:45:10.264428 4, 0xFFFF, sum = 0
5940 13:45:10.264512 5, 0xFFFF, sum = 0
5941 13:45:10.268017 6, 0xFFFF, sum = 0
5942 13:45:10.270786 7, 0xFFFF, sum = 0
5943 13:45:10.270899 8, 0xFFFF, sum = 0
5944 13:45:10.274499 9, 0xFFFF, sum = 0
5945 13:45:10.274582 10, 0x0, sum = 1
5946 13:45:10.274648 11, 0x0, sum = 2
5947 13:45:10.277446 12, 0x0, sum = 3
5948 13:45:10.277529 13, 0x0, sum = 4
5949 13:45:10.280986 best_step = 11
5950 13:45:10.281068
5951 13:45:10.281133 ==
5952 13:45:10.284523 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 13:45:10.287776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 13:45:10.287892 ==
5955 13:45:10.291099 RX Vref Scan: 0
5956 13:45:10.291180
5957 13:45:10.291245 RX Vref 0 -> 0, step: 1
5958 13:45:10.291305
5959 13:45:10.294398 RX Delay -45 -> 252, step: 4
5960 13:45:10.301331 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5961 13:45:10.304850 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5962 13:45:10.308347 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5963 13:45:10.311247 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5964 13:45:10.314815 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5965 13:45:10.321279 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5966 13:45:10.324898 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5967 13:45:10.328446 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5968 13:45:10.331229 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5969 13:45:10.334809 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5970 13:45:10.341010 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5971 13:45:10.344540 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5972 13:45:10.347823 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5973 13:45:10.351279 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5974 13:45:10.354710 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5975 13:45:10.360927 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5976 13:45:10.361014 ==
5977 13:45:10.364794 Dram Type= 6, Freq= 0, CH_1, rank 1
5978 13:45:10.368030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5979 13:45:10.368116 ==
5980 13:45:10.368182 DQS Delay:
5981 13:45:10.371190 DQS0 = 0, DQS1 = 0
5982 13:45:10.371272 DQM Delay:
5983 13:45:10.374633 DQM0 = 105, DQM1 = 100
5984 13:45:10.374715 DQ Delay:
5985 13:45:10.378240 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5986 13:45:10.381089 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5987 13:45:10.384713 DQ8 =92, DQ9 =92, DQ10 =100, DQ11 =94
5988 13:45:10.387506 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5989 13:45:10.387589
5990 13:45:10.387653
5991 13:45:10.397431 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5992 13:45:10.400961 CH1 RK1: MR19=505, MR18=3003
5993 13:45:10.404306 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5994 13:45:10.407886 [RxdqsGatingPostProcess] freq 933
5995 13:45:10.414519 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5996 13:45:10.417625 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 13:45:10.420876 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 13:45:10.424292 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 13:45:10.427996 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 13:45:10.430888 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 13:45:10.434184 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 13:45:10.437750 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 13:45:10.441254 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 13:45:10.444213 Pre-setting of DQS Precalculation
6005 13:45:10.447743 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6006 13:45:10.454214 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6007 13:45:10.460790 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6008 13:45:10.460884
6009 13:45:10.460951
6010 13:45:10.464068 [Calibration Summary] 1866 Mbps
6011 13:45:10.467420 CH 0, Rank 0
6012 13:45:10.467528 SW Impedance : PASS
6013 13:45:10.470973 DUTY Scan : NO K
6014 13:45:10.474536 ZQ Calibration : PASS
6015 13:45:10.474652 Jitter Meter : NO K
6016 13:45:10.477348 CBT Training : PASS
6017 13:45:10.480628 Write leveling : PASS
6018 13:45:10.480710 RX DQS gating : PASS
6019 13:45:10.484046 RX DQ/DQS(RDDQC) : PASS
6020 13:45:10.484128 TX DQ/DQS : PASS
6021 13:45:10.487593 RX DATLAT : PASS
6022 13:45:10.491345 RX DQ/DQS(Engine): PASS
6023 13:45:10.491427 TX OE : NO K
6024 13:45:10.494035 All Pass.
6025 13:45:10.494117
6026 13:45:10.494181 CH 0, Rank 1
6027 13:45:10.497524 SW Impedance : PASS
6028 13:45:10.497606 DUTY Scan : NO K
6029 13:45:10.501156 ZQ Calibration : PASS
6030 13:45:10.504115 Jitter Meter : NO K
6031 13:45:10.504197 CBT Training : PASS
6032 13:45:10.507579 Write leveling : PASS
6033 13:45:10.510465 RX DQS gating : PASS
6034 13:45:10.510546 RX DQ/DQS(RDDQC) : PASS
6035 13:45:10.513947 TX DQ/DQS : PASS
6036 13:45:10.517571 RX DATLAT : PASS
6037 13:45:10.517653 RX DQ/DQS(Engine): PASS
6038 13:45:10.520948 TX OE : NO K
6039 13:45:10.521030 All Pass.
6040 13:45:10.521094
6041 13:45:10.523826 CH 1, Rank 0
6042 13:45:10.523907 SW Impedance : PASS
6043 13:45:10.527258 DUTY Scan : NO K
6044 13:45:10.530543 ZQ Calibration : PASS
6045 13:45:10.530625 Jitter Meter : NO K
6046 13:45:10.533798 CBT Training : PASS
6047 13:45:10.537377 Write leveling : PASS
6048 13:45:10.537484 RX DQS gating : PASS
6049 13:45:10.540830 RX DQ/DQS(RDDQC) : PASS
6050 13:45:10.543654 TX DQ/DQS : PASS
6051 13:45:10.543741 RX DATLAT : PASS
6052 13:45:10.547160 RX DQ/DQS(Engine): PASS
6053 13:45:10.547245 TX OE : NO K
6054 13:45:10.550558 All Pass.
6055 13:45:10.550644
6056 13:45:10.550708 CH 1, Rank 1
6057 13:45:10.554224 SW Impedance : PASS
6058 13:45:10.554306 DUTY Scan : NO K
6059 13:45:10.557140 ZQ Calibration : PASS
6060 13:45:10.560713 Jitter Meter : NO K
6061 13:45:10.560795 CBT Training : PASS
6062 13:45:10.564030 Write leveling : PASS
6063 13:45:10.566761 RX DQS gating : PASS
6064 13:45:10.566865 RX DQ/DQS(RDDQC) : PASS
6065 13:45:10.570664 TX DQ/DQS : PASS
6066 13:45:10.574256 RX DATLAT : PASS
6067 13:45:10.574362 RX DQ/DQS(Engine): PASS
6068 13:45:10.576918 TX OE : NO K
6069 13:45:10.576995 All Pass.
6070 13:45:10.577057
6071 13:45:10.580143 DramC Write-DBI off
6072 13:45:10.583376 PER_BANK_REFRESH: Hybrid Mode
6073 13:45:10.583481 TX_TRACKING: ON
6074 13:45:10.593554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6075 13:45:10.597018 [FAST_K] Save calibration result to emmc
6076 13:45:10.600325 dramc_set_vcore_voltage set vcore to 650000
6077 13:45:10.603322 Read voltage for 400, 6
6078 13:45:10.603427 Vio18 = 0
6079 13:45:10.603493 Vcore = 650000
6080 13:45:10.606983 Vdram = 0
6081 13:45:10.607057 Vddq = 0
6082 13:45:10.607118 Vmddr = 0
6083 13:45:10.613380 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6084 13:45:10.616960 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6085 13:45:10.620610 MEM_TYPE=3, freq_sel=20
6086 13:45:10.623357 sv_algorithm_assistance_LP4_800
6087 13:45:10.626980 ============ PULL DRAM RESETB DOWN ============
6088 13:45:10.630477 ========== PULL DRAM RESETB DOWN end =========
6089 13:45:10.636962 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6090 13:45:10.640279 ===================================
6091 13:45:10.640411 LPDDR4 DRAM CONFIGURATION
6092 13:45:10.643032 ===================================
6093 13:45:10.646968 EX_ROW_EN[0] = 0x0
6094 13:45:10.650193 EX_ROW_EN[1] = 0x0
6095 13:45:10.650277 LP4Y_EN = 0x0
6096 13:45:10.653526 WORK_FSP = 0x0
6097 13:45:10.653609 WL = 0x2
6098 13:45:10.657073 RL = 0x2
6099 13:45:10.657156 BL = 0x2
6100 13:45:10.659866 RPST = 0x0
6101 13:45:10.659948 RD_PRE = 0x0
6102 13:45:10.663427 WR_PRE = 0x1
6103 13:45:10.663510 WR_PST = 0x0
6104 13:45:10.666946 DBI_WR = 0x0
6105 13:45:10.667047 DBI_RD = 0x0
6106 13:45:10.669838 OTF = 0x1
6107 13:45:10.673423 ===================================
6108 13:45:10.676219 ===================================
6109 13:45:10.676302 ANA top config
6110 13:45:10.680205 ===================================
6111 13:45:10.682984 DLL_ASYNC_EN = 0
6112 13:45:10.686863 ALL_SLAVE_EN = 1
6113 13:45:10.690116 NEW_RANK_MODE = 1
6114 13:45:10.690200 DLL_IDLE_MODE = 1
6115 13:45:10.693410 LP45_APHY_COMB_EN = 1
6116 13:45:10.696522 TX_ODT_DIS = 1
6117 13:45:10.699791 NEW_8X_MODE = 1
6118 13:45:10.703185 ===================================
6119 13:45:10.706393 ===================================
6120 13:45:10.709894 data_rate = 800
6121 13:45:10.710000 CKR = 1
6122 13:45:10.713486 DQ_P2S_RATIO = 4
6123 13:45:10.716375 ===================================
6124 13:45:10.719942 CA_P2S_RATIO = 4
6125 13:45:10.722895 DQ_CA_OPEN = 0
6126 13:45:10.726253 DQ_SEMI_OPEN = 1
6127 13:45:10.729786 CA_SEMI_OPEN = 1
6128 13:45:10.729864 CA_FULL_RATE = 0
6129 13:45:10.732827 DQ_CKDIV4_EN = 0
6130 13:45:10.736334 CA_CKDIV4_EN = 1
6131 13:45:10.739891 CA_PREDIV_EN = 0
6132 13:45:10.743459 PH8_DLY = 0
6133 13:45:10.743545 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6134 13:45:10.746284 DQ_AAMCK_DIV = 0
6135 13:45:10.749829 CA_AAMCK_DIV = 0
6136 13:45:10.753329 CA_ADMCK_DIV = 4
6137 13:45:10.756100 DQ_TRACK_CA_EN = 0
6138 13:45:10.759700 CA_PICK = 800
6139 13:45:10.763214 CA_MCKIO = 400
6140 13:45:10.763297 MCKIO_SEMI = 400
6141 13:45:10.766438 PLL_FREQ = 3016
6142 13:45:10.769798 DQ_UI_PI_RATIO = 32
6143 13:45:10.773292 CA_UI_PI_RATIO = 32
6144 13:45:10.776248 ===================================
6145 13:45:10.779869 ===================================
6146 13:45:10.783336 memory_type:LPDDR4
6147 13:45:10.783418 GP_NUM : 10
6148 13:45:10.786197 SRAM_EN : 1
6149 13:45:10.789561 MD32_EN : 0
6150 13:45:10.792941 ===================================
6151 13:45:10.793025 [ANA_INIT] >>>>>>>>>>>>>>
6152 13:45:10.796614 <<<<<< [CONFIGURE PHASE]: ANA_TX
6153 13:45:10.799398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6154 13:45:10.802876 ===================================
6155 13:45:10.806124 data_rate = 800,PCW = 0X7400
6156 13:45:10.809946 ===================================
6157 13:45:10.813307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6158 13:45:10.819643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 13:45:10.829409 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 13:45:10.832802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6161 13:45:10.839361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6162 13:45:10.842952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6163 13:45:10.843060 [ANA_INIT] flow start
6164 13:45:10.845822 [ANA_INIT] PLL >>>>>>>>
6165 13:45:10.849483 [ANA_INIT] PLL <<<<<<<<
6166 13:45:10.849565 [ANA_INIT] MIDPI >>>>>>>>
6167 13:45:10.852864 [ANA_INIT] MIDPI <<<<<<<<
6168 13:45:10.856208 [ANA_INIT] DLL >>>>>>>>
6169 13:45:10.856320 [ANA_INIT] flow end
6170 13:45:10.859685 ============ LP4 DIFF to SE enter ============
6171 13:45:10.866233 ============ LP4 DIFF to SE exit ============
6172 13:45:10.866319 [ANA_INIT] <<<<<<<<<<<<<
6173 13:45:10.869206 [Flow] Enable top DCM control >>>>>
6174 13:45:10.872837 [Flow] Enable top DCM control <<<<<
6175 13:45:10.876194 Enable DLL master slave shuffle
6176 13:45:10.883138 ==============================================================
6177 13:45:10.883223 Gating Mode config
6178 13:45:10.889496 ==============================================================
6179 13:45:10.892425 Config description:
6180 13:45:10.902558 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6181 13:45:10.908979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6182 13:45:10.912460 SELPH_MODE 0: By rank 1: By Phase
6183 13:45:10.919073 ==============================================================
6184 13:45:10.922388 GAT_TRACK_EN = 0
6185 13:45:10.925821 RX_GATING_MODE = 2
6186 13:45:10.929040 RX_GATING_TRACK_MODE = 2
6187 13:45:10.929124 SELPH_MODE = 1
6188 13:45:10.932063 PICG_EARLY_EN = 1
6189 13:45:10.935668 VALID_LAT_VALUE = 1
6190 13:45:10.942503 ==============================================================
6191 13:45:10.945373 Enter into Gating configuration >>>>
6192 13:45:10.948980 Exit from Gating configuration <<<<
6193 13:45:10.951970 Enter into DVFS_PRE_config >>>>>
6194 13:45:10.962487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6195 13:45:10.965437 Exit from DVFS_PRE_config <<<<<
6196 13:45:10.968949 Enter into PICG configuration >>>>
6197 13:45:10.972336 Exit from PICG configuration <<<<
6198 13:45:10.975222 [RX_INPUT] configuration >>>>>
6199 13:45:10.978891 [RX_INPUT] configuration <<<<<
6200 13:45:10.982398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6201 13:45:10.988601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6202 13:45:10.995476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 13:45:11.001845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 13:45:11.008543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 13:45:11.012180 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 13:45:11.018688 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6207 13:45:11.021548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6208 13:45:11.025028 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6209 13:45:11.028471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6210 13:45:11.031958 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6211 13:45:11.038325 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 13:45:11.041788 ===================================
6213 13:45:11.045107 LPDDR4 DRAM CONFIGURATION
6214 13:45:11.048293 ===================================
6215 13:45:11.048401 EX_ROW_EN[0] = 0x0
6216 13:45:11.052080 EX_ROW_EN[1] = 0x0
6217 13:45:11.052162 LP4Y_EN = 0x0
6218 13:45:11.055163 WORK_FSP = 0x0
6219 13:45:11.055284 WL = 0x2
6220 13:45:11.058625 RL = 0x2
6221 13:45:11.058708 BL = 0x2
6222 13:45:11.061438 RPST = 0x0
6223 13:45:11.061521 RD_PRE = 0x0
6224 13:45:11.065113 WR_PRE = 0x1
6225 13:45:11.065195 WR_PST = 0x0
6226 13:45:11.068503 DBI_WR = 0x0
6227 13:45:11.068610 DBI_RD = 0x0
6228 13:45:11.071937 OTF = 0x1
6229 13:45:11.074635 ===================================
6230 13:45:11.078173 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6231 13:45:11.081708 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6232 13:45:11.088256 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 13:45:11.091683 ===================================
6234 13:45:11.091774 LPDDR4 DRAM CONFIGURATION
6235 13:45:11.095137 ===================================
6236 13:45:11.098600 EX_ROW_EN[0] = 0x10
6237 13:45:11.101425 EX_ROW_EN[1] = 0x0
6238 13:45:11.101503 LP4Y_EN = 0x0
6239 13:45:11.105104 WORK_FSP = 0x0
6240 13:45:11.105186 WL = 0x2
6241 13:45:11.107932 RL = 0x2
6242 13:45:11.108040 BL = 0x2
6243 13:45:11.111434 RPST = 0x0
6244 13:45:11.111518 RD_PRE = 0x0
6245 13:45:11.114850 WR_PRE = 0x1
6246 13:45:11.114954 WR_PST = 0x0
6247 13:45:11.118224 DBI_WR = 0x0
6248 13:45:11.118303 DBI_RD = 0x0
6249 13:45:11.121692 OTF = 0x1
6250 13:45:11.124607 ===================================
6251 13:45:11.131587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6252 13:45:11.134875 nWR fixed to 30
6253 13:45:11.137562 [ModeRegInit_LP4] CH0 RK0
6254 13:45:11.137645 [ModeRegInit_LP4] CH0 RK1
6255 13:45:11.141106 [ModeRegInit_LP4] CH1 RK0
6256 13:45:11.144628 [ModeRegInit_LP4] CH1 RK1
6257 13:45:11.144710 match AC timing 19
6258 13:45:11.151090 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6259 13:45:11.154526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6260 13:45:11.158061 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6261 13:45:11.164595 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6262 13:45:11.167867 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6263 13:45:11.167977 ==
6264 13:45:11.171390 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 13:45:11.174920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 13:45:11.175002 ==
6267 13:45:11.181115 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 13:45:11.187913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6269 13:45:11.191413 [CA 0] Center 36 (8~64) winsize 57
6270 13:45:11.194837 [CA 1] Center 36 (8~64) winsize 57
6271 13:45:11.194951 [CA 2] Center 36 (8~64) winsize 57
6272 13:45:11.197750 [CA 3] Center 36 (8~64) winsize 57
6273 13:45:11.201213 [CA 4] Center 36 (8~64) winsize 57
6274 13:45:11.204641 [CA 5] Center 36 (8~64) winsize 57
6275 13:45:11.204729
6276 13:45:11.208265 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6277 13:45:11.208374
6278 13:45:11.214368 [CATrainingPosCal] consider 1 rank data
6279 13:45:11.214456 u2DelayCellTimex100 = 270/100 ps
6280 13:45:11.221508 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 13:45:11.224072 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 13:45:11.227457 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 13:45:11.230729 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 13:45:11.234381 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 13:45:11.237839 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 13:45:11.237921
6287 13:45:11.240648 CA PerBit enable=1, Macro0, CA PI delay=36
6288 13:45:11.240736
6289 13:45:11.244128 [CBTSetCACLKResult] CA Dly = 36
6290 13:45:11.247982 CS Dly: 1 (0~32)
6291 13:45:11.248068 ==
6292 13:45:11.250606 Dram Type= 6, Freq= 0, CH_0, rank 1
6293 13:45:11.254221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 13:45:11.254305 ==
6295 13:45:11.260663 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 13:45:11.264174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6297 13:45:11.267613 [CA 0] Center 36 (8~64) winsize 57
6298 13:45:11.270922 [CA 1] Center 36 (8~64) winsize 57
6299 13:45:11.274099 [CA 2] Center 36 (8~64) winsize 57
6300 13:45:11.277569 [CA 3] Center 36 (8~64) winsize 57
6301 13:45:11.280857 [CA 4] Center 36 (8~64) winsize 57
6302 13:45:11.283705 [CA 5] Center 36 (8~64) winsize 57
6303 13:45:11.283792
6304 13:45:11.287058 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6305 13:45:11.287163
6306 13:45:11.290312 [CATrainingPosCal] consider 2 rank data
6307 13:45:11.293841 u2DelayCellTimex100 = 270/100 ps
6308 13:45:11.297357 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 13:45:11.300485 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 13:45:11.303879 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 13:45:11.310822 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 13:45:11.313692 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 13:45:11.317383 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 13:45:11.317467
6315 13:45:11.320288 CA PerBit enable=1, Macro0, CA PI delay=36
6316 13:45:11.320394
6317 13:45:11.324026 [CBTSetCACLKResult] CA Dly = 36
6318 13:45:11.324109 CS Dly: 1 (0~32)
6319 13:45:11.324173
6320 13:45:11.327587 ----->DramcWriteLeveling(PI) begin...
6321 13:45:11.327671 ==
6322 13:45:11.330415 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 13:45:11.337122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 13:45:11.337207 ==
6325 13:45:11.340538 Write leveling (Byte 0): 40 => 8
6326 13:45:11.343947 Write leveling (Byte 1): 40 => 8
6327 13:45:11.344029 DramcWriteLeveling(PI) end<-----
6328 13:45:11.344095
6329 13:45:11.346766 ==
6330 13:45:11.350115 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 13:45:11.353464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 13:45:11.353626 ==
6333 13:45:11.357294 [Gating] SW mode calibration
6334 13:45:11.363724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6335 13:45:11.367229 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6336 13:45:11.373893 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 13:45:11.376612 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 13:45:11.380090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 13:45:11.387140 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 13:45:11.390374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 13:45:11.393589 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 13:45:11.400467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 13:45:11.403874 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 13:45:11.406630 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 13:45:11.409901 Total UI for P1: 0, mck2ui 16
6346 13:45:11.413322 best dqsien dly found for B0: ( 0, 14, 24)
6347 13:45:11.416621 Total UI for P1: 0, mck2ui 16
6348 13:45:11.420158 best dqsien dly found for B1: ( 0, 14, 24)
6349 13:45:11.423064 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6350 13:45:11.426784 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6351 13:45:11.426867
6352 13:45:11.433104 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 13:45:11.436786 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 13:45:11.439600 [Gating] SW calibration Done
6355 13:45:11.439708 ==
6356 13:45:11.442971 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 13:45:11.446549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 13:45:11.446633 ==
6359 13:45:11.446699 RX Vref Scan: 0
6360 13:45:11.446759
6361 13:45:11.449921 RX Vref 0 -> 0, step: 1
6362 13:45:11.450003
6363 13:45:11.453017 RX Delay -410 -> 252, step: 16
6364 13:45:11.456774 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6365 13:45:11.460053 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6366 13:45:11.466483 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6367 13:45:11.470150 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6368 13:45:11.473053 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6369 13:45:11.476602 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6370 13:45:11.483053 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6371 13:45:11.486709 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6372 13:45:11.490272 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6373 13:45:11.492867 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6374 13:45:11.500095 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6375 13:45:11.502824 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6376 13:45:11.506143 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6377 13:45:11.513196 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6378 13:45:11.516584 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6379 13:45:11.520021 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6380 13:45:11.520102 ==
6381 13:45:11.523375 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 13:45:11.526079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 13:45:11.529339 ==
6384 13:45:11.529420 DQS Delay:
6385 13:45:11.529483 DQS0 = 27, DQS1 = 35
6386 13:45:11.532598 DQM Delay:
6387 13:45:11.532680 DQM0 = 10, DQM1 = 11
6388 13:45:11.536205 DQ Delay:
6389 13:45:11.536313 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6390 13:45:11.539934 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6391 13:45:11.542663 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6392 13:45:11.546177 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6393 13:45:11.546258
6394 13:45:11.546324
6395 13:45:11.546397 ==
6396 13:45:11.549851 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 13:45:11.556277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 13:45:11.556409 ==
6399 13:45:11.556475
6400 13:45:11.556536
6401 13:45:11.556592 TX Vref Scan disable
6402 13:45:11.559740 == TX Byte 0 ==
6403 13:45:11.563142 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 13:45:11.566463 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 13:45:11.569608 == TX Byte 1 ==
6406 13:45:11.572610 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 13:45:11.576240 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 13:45:11.576323 ==
6409 13:45:11.579212 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 13:45:11.586339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 13:45:11.586426 ==
6412 13:45:11.586492
6413 13:45:11.586552
6414 13:45:11.586609 TX Vref Scan disable
6415 13:45:11.589224 == TX Byte 0 ==
6416 13:45:11.592832 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 13:45:11.596458 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 13:45:11.599241 == TX Byte 1 ==
6419 13:45:11.602734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 13:45:11.605868 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 13:45:11.605949
6422 13:45:11.609431 [DATLAT]
6423 13:45:11.609512 Freq=400, CH0 RK0
6424 13:45:11.609577
6425 13:45:11.612672 DATLAT Default: 0xf
6426 13:45:11.612754 0, 0xFFFF, sum = 0
6427 13:45:11.616078 1, 0xFFFF, sum = 0
6428 13:45:11.616161 2, 0xFFFF, sum = 0
6429 13:45:11.619373 3, 0xFFFF, sum = 0
6430 13:45:11.619456 4, 0xFFFF, sum = 0
6431 13:45:11.622771 5, 0xFFFF, sum = 0
6432 13:45:11.622855 6, 0xFFFF, sum = 0
6433 13:45:11.626303 7, 0xFFFF, sum = 0
6434 13:45:11.626387 8, 0xFFFF, sum = 0
6435 13:45:11.629545 9, 0xFFFF, sum = 0
6436 13:45:11.632866 10, 0xFFFF, sum = 0
6437 13:45:11.632950 11, 0xFFFF, sum = 0
6438 13:45:11.636397 12, 0xFFFF, sum = 0
6439 13:45:11.636480 13, 0x0, sum = 1
6440 13:45:11.639128 14, 0x0, sum = 2
6441 13:45:11.639211 15, 0x0, sum = 3
6442 13:45:11.639276 16, 0x0, sum = 4
6443 13:45:11.642482 best_step = 14
6444 13:45:11.642566
6445 13:45:11.642630 ==
6446 13:45:11.645855 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 13:45:11.649579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 13:45:11.649662 ==
6449 13:45:11.652470 RX Vref Scan: 1
6450 13:45:11.652553
6451 13:45:11.655989 RX Vref 0 -> 0, step: 1
6452 13:45:11.656071
6453 13:45:11.656136 RX Delay -311 -> 252, step: 8
6454 13:45:11.656196
6455 13:45:11.659555 Set Vref, RX VrefLevel [Byte0]: 54
6456 13:45:11.662379 [Byte1]: 51
6457 13:45:11.667918
6458 13:45:11.668000 Final RX Vref Byte 0 = 54 to rank0
6459 13:45:11.670861 Final RX Vref Byte 1 = 51 to rank0
6460 13:45:11.674497 Final RX Vref Byte 0 = 54 to rank1
6461 13:45:11.677433 Final RX Vref Byte 1 = 51 to rank1==
6462 13:45:11.681029 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 13:45:11.687580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 13:45:11.687664 ==
6465 13:45:11.687729 DQS Delay:
6466 13:45:11.690679 DQS0 = 28, DQS1 = 36
6467 13:45:11.690779 DQM Delay:
6468 13:45:11.690847 DQM0 = 11, DQM1 = 13
6469 13:45:11.694211 DQ Delay:
6470 13:45:11.697131 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6471 13:45:11.700597 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6472 13:45:11.700684 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6473 13:45:11.704306 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6474 13:45:11.707199
6475 13:45:11.707286
6476 13:45:11.714183 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6477 13:45:11.717075 CH0 RK0: MR19=C0C, MR18=D1BF
6478 13:45:11.723904 CH0_RK0: MR19=0xC0C, MR18=0xD1BF, DQSOSC=384, MR23=63, INC=400, DEC=267
6479 13:45:11.723990 ==
6480 13:45:11.727405 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 13:45:11.730172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 13:45:11.730259 ==
6483 13:45:11.733841 [Gating] SW mode calibration
6484 13:45:11.740705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6485 13:45:11.746841 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6486 13:45:11.750357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 13:45:11.753544 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 13:45:11.760345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 13:45:11.763168 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 13:45:11.766931 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 13:45:11.773220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 13:45:11.776859 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 13:45:11.779817 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 13:45:11.787162 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 13:45:11.787246 Total UI for P1: 0, mck2ui 16
6496 13:45:11.793666 best dqsien dly found for B0: ( 0, 14, 24)
6497 13:45:11.793753 Total UI for P1: 0, mck2ui 16
6498 13:45:11.796502 best dqsien dly found for B1: ( 0, 14, 24)
6499 13:45:11.803359 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6500 13:45:11.806691 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6501 13:45:11.806775
6502 13:45:11.810151 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 13:45:11.813139 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 13:45:11.816562 [Gating] SW calibration Done
6505 13:45:11.816678 ==
6506 13:45:11.820160 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 13:45:11.823332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 13:45:11.823419 ==
6509 13:45:11.826697 RX Vref Scan: 0
6510 13:45:11.826780
6511 13:45:11.826846 RX Vref 0 -> 0, step: 1
6512 13:45:11.826906
6513 13:45:11.829934 RX Delay -410 -> 252, step: 16
6514 13:45:11.836481 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6515 13:45:11.839933 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6516 13:45:11.843441 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6517 13:45:11.846825 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6518 13:45:11.852768 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6519 13:45:11.856322 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6520 13:45:11.859959 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6521 13:45:11.863396 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6522 13:45:11.866729 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6523 13:45:11.873087 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6524 13:45:11.876613 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6525 13:45:11.879457 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6526 13:45:11.886725 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6527 13:45:11.889591 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6528 13:45:11.893234 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6529 13:45:11.896678 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6530 13:45:11.896762 ==
6531 13:45:11.899500 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 13:45:11.906056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 13:45:11.906141 ==
6534 13:45:11.906207 DQS Delay:
6535 13:45:11.909856 DQS0 = 27, DQS1 = 35
6536 13:45:11.909939 DQM Delay:
6537 13:45:11.910004 DQM0 = 13, DQM1 = 11
6538 13:45:11.912734 DQ Delay:
6539 13:45:11.916242 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6540 13:45:11.919655 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6541 13:45:11.919756 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6542 13:45:11.923150 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6543 13:45:11.926481
6544 13:45:11.926562
6545 13:45:11.926627 ==
6546 13:45:11.929737 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 13:45:11.932889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 13:45:11.932973 ==
6549 13:45:11.933039
6550 13:45:11.933099
6551 13:45:11.936530 TX Vref Scan disable
6552 13:45:11.936613 == TX Byte 0 ==
6553 13:45:11.939995 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6554 13:45:11.946000 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6555 13:45:11.946083 == TX Byte 1 ==
6556 13:45:11.949865 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6557 13:45:11.956296 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6558 13:45:11.956430 ==
6559 13:45:11.959650 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 13:45:11.962953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 13:45:11.963037 ==
6562 13:45:11.963102
6563 13:45:11.963163
6564 13:45:11.966136 TX Vref Scan disable
6565 13:45:11.966219 == TX Byte 0 ==
6566 13:45:11.973064 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6567 13:45:11.976376 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6568 13:45:11.976475 == TX Byte 1 ==
6569 13:45:11.982940 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6570 13:45:11.986406 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6571 13:45:11.986495
6572 13:45:11.986559 [DATLAT]
6573 13:45:11.989360 Freq=400, CH0 RK1
6574 13:45:11.989443
6575 13:45:11.989507 DATLAT Default: 0xe
6576 13:45:11.992970 0, 0xFFFF, sum = 0
6577 13:45:11.993054 1, 0xFFFF, sum = 0
6578 13:45:11.996454 2, 0xFFFF, sum = 0
6579 13:45:11.996538 3, 0xFFFF, sum = 0
6580 13:45:11.999372 4, 0xFFFF, sum = 0
6581 13:45:11.999455 5, 0xFFFF, sum = 0
6582 13:45:12.002996 6, 0xFFFF, sum = 0
6583 13:45:12.003080 7, 0xFFFF, sum = 0
6584 13:45:12.005922 8, 0xFFFF, sum = 0
6585 13:45:12.006006 9, 0xFFFF, sum = 0
6586 13:45:12.009539 10, 0xFFFF, sum = 0
6587 13:45:12.012305 11, 0xFFFF, sum = 0
6588 13:45:12.012428 12, 0xFFFF, sum = 0
6589 13:45:12.016005 13, 0x0, sum = 1
6590 13:45:12.016079 14, 0x0, sum = 2
6591 13:45:12.016141 15, 0x0, sum = 3
6592 13:45:12.019468 16, 0x0, sum = 4
6593 13:45:12.019537 best_step = 14
6594 13:45:12.019595
6595 13:45:12.022936 ==
6596 13:45:12.023019 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 13:45:12.029435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 13:45:12.029517 ==
6599 13:45:12.029582 RX Vref Scan: 0
6600 13:45:12.029642
6601 13:45:12.032262 RX Vref 0 -> 0, step: 1
6602 13:45:12.032366
6603 13:45:12.035751 RX Delay -311 -> 252, step: 8
6604 13:45:12.042617 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6605 13:45:12.045938 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6606 13:45:12.048956 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6607 13:45:12.052848 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6608 13:45:12.059018 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6609 13:45:12.062723 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6610 13:45:12.065986 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6611 13:45:12.069175 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6612 13:45:12.075912 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6613 13:45:12.078742 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6614 13:45:12.082566 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6615 13:45:12.085817 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6616 13:45:12.092648 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6617 13:45:12.095813 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6618 13:45:12.099133 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6619 13:45:12.102798 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6620 13:45:12.105612 ==
6621 13:45:12.109220 Dram Type= 6, Freq= 0, CH_0, rank 1
6622 13:45:12.112683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 13:45:12.112766 ==
6624 13:45:12.112832 DQS Delay:
6625 13:45:12.115544 DQS0 = 24, DQS1 = 32
6626 13:45:12.115627 DQM Delay:
6627 13:45:12.119067 DQM0 = 8, DQM1 = 9
6628 13:45:12.119149 DQ Delay:
6629 13:45:12.122546 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6630 13:45:12.125996 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6631 13:45:12.126079 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6632 13:45:12.132474 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6633 13:45:12.132557
6634 13:45:12.132622
6635 13:45:12.139471 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6636 13:45:12.142376 CH0 RK1: MR19=C0C, MR18=BF5F
6637 13:45:12.148900 CH0_RK1: MR19=0xC0C, MR18=0xBF5F, DQSOSC=386, MR23=63, INC=396, DEC=264
6638 13:45:12.152412 [RxdqsGatingPostProcess] freq 400
6639 13:45:12.155794 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6640 13:45:12.159039 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 13:45:12.162344 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 13:45:12.165463 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 13:45:12.168830 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 13:45:12.172298 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 13:45:12.175896 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 13:45:12.178690 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 13:45:12.182188 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 13:45:12.185387 Pre-setting of DQS Precalculation
6649 13:45:12.189246 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6650 13:45:12.189350 ==
6651 13:45:12.192276 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 13:45:12.198995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 13:45:12.199084 ==
6654 13:45:12.202308 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 13:45:12.208652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6656 13:45:12.212102 [CA 0] Center 36 (8~64) winsize 57
6657 13:45:12.215329 [CA 1] Center 36 (8~64) winsize 57
6658 13:45:12.218594 [CA 2] Center 36 (8~64) winsize 57
6659 13:45:12.222246 [CA 3] Center 36 (8~64) winsize 57
6660 13:45:12.225856 [CA 4] Center 36 (8~64) winsize 57
6661 13:45:12.228626 [CA 5] Center 36 (8~64) winsize 57
6662 13:45:12.228708
6663 13:45:12.232146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6664 13:45:12.232244
6665 13:45:12.235786 [CATrainingPosCal] consider 1 rank data
6666 13:45:12.238683 u2DelayCellTimex100 = 270/100 ps
6667 13:45:12.242194 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 13:45:12.245572 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 13:45:12.249018 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 13:45:12.251996 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 13:45:12.255571 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 13:45:12.258534 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 13:45:12.262097
6674 13:45:12.265646 CA PerBit enable=1, Macro0, CA PI delay=36
6675 13:45:12.265733
6676 13:45:12.268428 [CBTSetCACLKResult] CA Dly = 36
6677 13:45:12.268534 CS Dly: 1 (0~32)
6678 13:45:12.268626 ==
6679 13:45:12.271751 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 13:45:12.275112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 13:45:12.275198 ==
6682 13:45:12.282125 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 13:45:12.288578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6684 13:45:12.292220 [CA 0] Center 36 (8~64) winsize 57
6685 13:45:12.295086 [CA 1] Center 36 (8~64) winsize 57
6686 13:45:12.298718 [CA 2] Center 36 (8~64) winsize 57
6687 13:45:12.302145 [CA 3] Center 36 (8~64) winsize 57
6688 13:45:12.305198 [CA 4] Center 36 (8~64) winsize 57
6689 13:45:12.305280 [CA 5] Center 36 (8~64) winsize 57
6690 13:45:12.308217
6691 13:45:12.311684 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6692 13:45:12.311767
6693 13:45:12.315033 [CATrainingPosCal] consider 2 rank data
6694 13:45:12.318398 u2DelayCellTimex100 = 270/100 ps
6695 13:45:12.322158 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 13:45:12.324807 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 13:45:12.328569 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 13:45:12.331993 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 13:45:12.335311 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 13:45:12.338524 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 13:45:12.338605
6702 13:45:12.341595 CA PerBit enable=1, Macro0, CA PI delay=36
6703 13:45:12.341677
6704 13:45:12.345197 [CBTSetCACLKResult] CA Dly = 36
6705 13:45:12.348681 CS Dly: 1 (0~32)
6706 13:45:12.348766
6707 13:45:12.351536 ----->DramcWriteLeveling(PI) begin...
6708 13:45:12.351619 ==
6709 13:45:12.354865 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 13:45:12.358512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 13:45:12.358595 ==
6712 13:45:12.362111 Write leveling (Byte 0): 40 => 8
6713 13:45:12.364984 Write leveling (Byte 1): 40 => 8
6714 13:45:12.368623 DramcWriteLeveling(PI) end<-----
6715 13:45:12.368731
6716 13:45:12.368828 ==
6717 13:45:12.372125 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 13:45:12.374960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 13:45:12.375037 ==
6720 13:45:12.378596 [Gating] SW mode calibration
6721 13:45:12.384812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6722 13:45:12.391892 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6723 13:45:12.395102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 13:45:12.398592 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 13:45:12.405069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 13:45:12.408646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 13:45:12.411507 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 13:45:12.418077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 13:45:12.421390 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 13:45:12.425039 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 13:45:12.431412 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 13:45:12.431498 Total UI for P1: 0, mck2ui 16
6733 13:45:12.438107 best dqsien dly found for B0: ( 0, 14, 24)
6734 13:45:12.438191 Total UI for P1: 0, mck2ui 16
6735 13:45:12.445308 best dqsien dly found for B1: ( 0, 14, 24)
6736 13:45:12.448754 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6737 13:45:12.452098 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6738 13:45:12.452182
6739 13:45:12.455350 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 13:45:12.458459 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 13:45:12.461824 [Gating] SW calibration Done
6742 13:45:12.461933 ==
6743 13:45:12.465281 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 13:45:12.468174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 13:45:12.468257 ==
6746 13:45:12.471685 RX Vref Scan: 0
6747 13:45:12.471767
6748 13:45:12.471845 RX Vref 0 -> 0, step: 1
6749 13:45:12.471918
6750 13:45:12.475387 RX Delay -410 -> 252, step: 16
6751 13:45:12.481758 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6752 13:45:12.484579 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6753 13:45:12.488240 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6754 13:45:12.491870 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6755 13:45:12.498204 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6756 13:45:12.501552 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6757 13:45:12.504829 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6758 13:45:12.508598 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6759 13:45:12.511449 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6760 13:45:12.517996 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6761 13:45:12.521412 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6762 13:45:12.524908 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6763 13:45:12.531283 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6764 13:45:12.534845 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6765 13:45:12.538451 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6766 13:45:12.541414 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6767 13:45:12.541497 ==
6768 13:45:12.545046 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 13:45:12.551645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 13:45:12.551728 ==
6771 13:45:12.551794 DQS Delay:
6772 13:45:12.554700 DQS0 = 35, DQS1 = 35
6773 13:45:12.554782 DQM Delay:
6774 13:45:12.554847 DQM0 = 17, DQM1 = 12
6775 13:45:12.558146 DQ Delay:
6776 13:45:12.561817 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6777 13:45:12.565005 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6778 13:45:12.568388 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6779 13:45:12.571113 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6780 13:45:12.571195
6781 13:45:12.571259
6782 13:45:12.571319 ==
6783 13:45:12.574931 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 13:45:12.578111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 13:45:12.578195 ==
6786 13:45:12.578259
6787 13:45:12.578319
6788 13:45:12.581728 TX Vref Scan disable
6789 13:45:12.581814 == TX Byte 0 ==
6790 13:45:12.584685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 13:45:12.591284 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 13:45:12.591368 == TX Byte 1 ==
6793 13:45:12.594748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 13:45:12.601063 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 13:45:12.601148 ==
6796 13:45:12.604651 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 13:45:12.607502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 13:45:12.607620 ==
6799 13:45:12.607721
6800 13:45:12.607783
6801 13:45:12.610854 TX Vref Scan disable
6802 13:45:12.610962 == TX Byte 0 ==
6803 13:45:12.617506 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 13:45:12.621441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 13:45:12.621551 == TX Byte 1 ==
6806 13:45:12.627770 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 13:45:12.631348 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 13:45:12.631450
6809 13:45:12.631540 [DATLAT]
6810 13:45:12.634167 Freq=400, CH1 RK0
6811 13:45:12.634239
6812 13:45:12.634310 DATLAT Default: 0xf
6813 13:45:12.637577 0, 0xFFFF, sum = 0
6814 13:45:12.637651 1, 0xFFFF, sum = 0
6815 13:45:12.640837 2, 0xFFFF, sum = 0
6816 13:45:12.640914 3, 0xFFFF, sum = 0
6817 13:45:12.644251 4, 0xFFFF, sum = 0
6818 13:45:12.644392 5, 0xFFFF, sum = 0
6819 13:45:12.647526 6, 0xFFFF, sum = 0
6820 13:45:12.647629 7, 0xFFFF, sum = 0
6821 13:45:12.651076 8, 0xFFFF, sum = 0
6822 13:45:12.651182 9, 0xFFFF, sum = 0
6823 13:45:12.654589 10, 0xFFFF, sum = 0
6824 13:45:12.654664 11, 0xFFFF, sum = 0
6825 13:45:12.657468 12, 0xFFFF, sum = 0
6826 13:45:12.657540 13, 0x0, sum = 1
6827 13:45:12.660938 14, 0x0, sum = 2
6828 13:45:12.661021 15, 0x0, sum = 3
6829 13:45:12.664253 16, 0x0, sum = 4
6830 13:45:12.664344 best_step = 14
6831 13:45:12.664425
6832 13:45:12.664486 ==
6833 13:45:12.667375 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 13:45:12.674584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 13:45:12.674671 ==
6836 13:45:12.674736 RX Vref Scan: 1
6837 13:45:12.674797
6838 13:45:12.677426 RX Vref 0 -> 0, step: 1
6839 13:45:12.677508
6840 13:45:12.680919 RX Delay -311 -> 252, step: 8
6841 13:45:12.681001
6842 13:45:12.684473 Set Vref, RX VrefLevel [Byte0]: 56
6843 13:45:12.687741 [Byte1]: 53
6844 13:45:12.687824
6845 13:45:12.691001 Final RX Vref Byte 0 = 56 to rank0
6846 13:45:12.694223 Final RX Vref Byte 1 = 53 to rank0
6847 13:45:12.697713 Final RX Vref Byte 0 = 56 to rank1
6848 13:45:12.700559 Final RX Vref Byte 1 = 53 to rank1==
6849 13:45:12.704149 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 13:45:12.707132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 13:45:12.710725 ==
6852 13:45:12.710809 DQS Delay:
6853 13:45:12.710874 DQS0 = 28, DQS1 = 32
6854 13:45:12.714273 DQM Delay:
6855 13:45:12.714355 DQM0 = 9, DQM1 = 10
6856 13:45:12.717095 DQ Delay:
6857 13:45:12.717176 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6858 13:45:12.720669 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6859 13:45:12.724070 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6860 13:45:12.727437 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6861 13:45:12.727526
6862 13:45:12.727592
6863 13:45:12.737076 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6864 13:45:12.740777 CH1 RK0: MR19=C0C, MR18=93CD
6865 13:45:12.743633 CH1_RK0: MR19=0xC0C, MR18=0x93CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6866 13:45:12.746901 ==
6867 13:45:12.750281 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 13:45:12.753609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 13:45:12.753720 ==
6870 13:45:12.757169 [Gating] SW mode calibration
6871 13:45:12.763566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6872 13:45:12.767116 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6873 13:45:12.773638 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 13:45:12.777050 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 13:45:12.780289 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 13:45:12.786693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 13:45:12.790262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 13:45:12.793999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 13:45:12.800006 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 13:45:12.803969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 13:45:12.807067 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 13:45:12.810023 Total UI for P1: 0, mck2ui 16
6883 13:45:12.813964 best dqsien dly found for B0: ( 0, 14, 24)
6884 13:45:12.816726 Total UI for P1: 0, mck2ui 16
6885 13:45:12.820448 best dqsien dly found for B1: ( 0, 14, 24)
6886 13:45:12.823368 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6887 13:45:12.826916 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6888 13:45:12.827003
6889 13:45:12.833568 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 13:45:12.836989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 13:45:12.837077 [Gating] SW calibration Done
6892 13:45:12.840493 ==
6893 13:45:12.843811 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 13:45:12.846973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 13:45:12.847057 ==
6896 13:45:12.847121 RX Vref Scan: 0
6897 13:45:12.847181
6898 13:45:12.850075 RX Vref 0 -> 0, step: 1
6899 13:45:12.850179
6900 13:45:12.853397 RX Delay -410 -> 252, step: 16
6901 13:45:12.856877 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6902 13:45:12.860068 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6903 13:45:12.867395 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6904 13:45:12.870244 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6905 13:45:12.873849 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6906 13:45:12.876711 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6907 13:45:12.883064 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6908 13:45:12.886715 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6909 13:45:12.890320 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6910 13:45:12.892959 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6911 13:45:12.900224 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6912 13:45:12.903068 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6913 13:45:12.906619 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6914 13:45:12.912975 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6915 13:45:12.916559 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6916 13:45:12.919825 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6917 13:45:12.920022 ==
6918 13:45:12.923037 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 13:45:12.926257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 13:45:12.926358 ==
6921 13:45:12.929969 DQS Delay:
6922 13:45:12.930103 DQS0 = 35, DQS1 = 35
6923 13:45:12.932857 DQM Delay:
6924 13:45:12.932940 DQM0 = 18, DQM1 = 14
6925 13:45:12.933005 DQ Delay:
6926 13:45:12.936545 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6927 13:45:12.940134 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6928 13:45:12.943034 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6929 13:45:12.946665 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6930 13:45:12.946747
6931 13:45:12.946812
6932 13:45:12.949472 ==
6933 13:45:12.953134 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 13:45:12.955934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 13:45:12.956023 ==
6936 13:45:12.956118
6937 13:45:12.956209
6938 13:45:12.959236 TX Vref Scan disable
6939 13:45:12.959317 == TX Byte 0 ==
6940 13:45:12.962495 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6941 13:45:12.969291 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6942 13:45:12.969409 == TX Byte 1 ==
6943 13:45:12.972505 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6944 13:45:12.979398 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6945 13:45:12.979510 ==
6946 13:45:12.982830 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 13:45:12.985662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 13:45:12.985774 ==
6949 13:45:12.985872
6950 13:45:12.985965
6951 13:45:12.989093 TX Vref Scan disable
6952 13:45:12.989203 == TX Byte 0 ==
6953 13:45:12.992693 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6954 13:45:12.999218 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6955 13:45:12.999328 == TX Byte 1 ==
6956 13:45:13.002711 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6957 13:45:13.009076 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6958 13:45:13.009189
6959 13:45:13.009288 [DATLAT]
6960 13:45:13.012324 Freq=400, CH1 RK1
6961 13:45:13.012468
6962 13:45:13.012563 DATLAT Default: 0xe
6963 13:45:13.015753 0, 0xFFFF, sum = 0
6964 13:45:13.015865 1, 0xFFFF, sum = 0
6965 13:45:13.019311 2, 0xFFFF, sum = 0
6966 13:45:13.019421 3, 0xFFFF, sum = 0
6967 13:45:13.022866 4, 0xFFFF, sum = 0
6968 13:45:13.022977 5, 0xFFFF, sum = 0
6969 13:45:13.025648 6, 0xFFFF, sum = 0
6970 13:45:13.025758 7, 0xFFFF, sum = 0
6971 13:45:13.029211 8, 0xFFFF, sum = 0
6972 13:45:13.029321 9, 0xFFFF, sum = 0
6973 13:45:13.032627 10, 0xFFFF, sum = 0
6974 13:45:13.032738 11, 0xFFFF, sum = 0
6975 13:45:13.036073 12, 0xFFFF, sum = 0
6976 13:45:13.036183 13, 0x0, sum = 1
6977 13:45:13.039461 14, 0x0, sum = 2
6978 13:45:13.039572 15, 0x0, sum = 3
6979 13:45:13.042508 16, 0x0, sum = 4
6980 13:45:13.042618 best_step = 14
6981 13:45:13.042715
6982 13:45:13.042811 ==
6983 13:45:13.045545 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 13:45:13.052194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 13:45:13.052323 ==
6986 13:45:13.052440 RX Vref Scan: 0
6987 13:45:13.052535
6988 13:45:13.055838 RX Vref 0 -> 0, step: 1
6989 13:45:13.055946
6990 13:45:13.059347 RX Delay -311 -> 252, step: 8
6991 13:45:13.065991 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6992 13:45:13.069351 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6993 13:45:13.072057 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6994 13:45:13.075494 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6995 13:45:13.082610 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6996 13:45:13.085743 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6997 13:45:13.088993 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6998 13:45:13.092067 iDelay=217, Bit 7, Center -20 (-247 ~ 208) 456
6999 13:45:13.098911 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7000 13:45:13.102364 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7001 13:45:13.105223 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7002 13:45:13.108845 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7003 13:45:13.115061 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7004 13:45:13.119001 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7005 13:45:13.122104 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7006 13:45:13.125424 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7007 13:45:13.129034 ==
7008 13:45:13.131983 Dram Type= 6, Freq= 0, CH_1, rank 1
7009 13:45:13.135590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7010 13:45:13.135700 ==
7011 13:45:13.135796 DQS Delay:
7012 13:45:13.138573 DQS0 = 28, DQS1 = 36
7013 13:45:13.138682 DQM Delay:
7014 13:45:13.142168 DQM0 = 10, DQM1 = 15
7015 13:45:13.142278 DQ Delay:
7016 13:45:13.145082 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7017 13:45:13.148431 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7018 13:45:13.151958 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7019 13:45:13.155604 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7020 13:45:13.155713
7021 13:45:13.155807
7022 13:45:13.162113 [DQSOSCAuto] RK1, (LSB)MR18= 0xc757, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7023 13:45:13.165308 CH1 RK1: MR19=C0C, MR18=C757
7024 13:45:13.171735 CH1_RK1: MR19=0xC0C, MR18=0xC757, DQSOSC=385, MR23=63, INC=398, DEC=265
7025 13:45:13.175111 [RxdqsGatingPostProcess] freq 400
7026 13:45:13.178408 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7027 13:45:13.182025 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 13:45:13.185344 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 13:45:13.188224 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 13:45:13.191796 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 13:45:13.194591 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 13:45:13.198149 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 13:45:13.201568 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 13:45:13.204792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 13:45:13.207996 Pre-setting of DQS Precalculation
7036 13:45:13.211312 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7037 13:45:13.221689 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7038 13:45:13.228013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7039 13:45:13.228140
7040 13:45:13.228252
7041 13:45:13.231327 [Calibration Summary] 800 Mbps
7042 13:45:13.231439 CH 0, Rank 0
7043 13:45:13.234365 SW Impedance : PASS
7044 13:45:13.234475 DUTY Scan : NO K
7045 13:45:13.237847 ZQ Calibration : PASS
7046 13:45:13.241415 Jitter Meter : NO K
7047 13:45:13.241531 CBT Training : PASS
7048 13:45:13.245053 Write leveling : PASS
7049 13:45:13.247876 RX DQS gating : PASS
7050 13:45:13.247992 RX DQ/DQS(RDDQC) : PASS
7051 13:45:13.251411 TX DQ/DQS : PASS
7052 13:45:13.255053 RX DATLAT : PASS
7053 13:45:13.255163 RX DQ/DQS(Engine): PASS
7054 13:45:13.257980 TX OE : NO K
7055 13:45:13.258091 All Pass.
7056 13:45:13.258189
7057 13:45:13.261540 CH 0, Rank 1
7058 13:45:13.261648 SW Impedance : PASS
7059 13:45:13.264415 DUTY Scan : NO K
7060 13:45:13.264524 ZQ Calibration : PASS
7061 13:45:13.267714 Jitter Meter : NO K
7062 13:45:13.271350 CBT Training : PASS
7063 13:45:13.271460 Write leveling : NO K
7064 13:45:13.274767 RX DQS gating : PASS
7065 13:45:13.278097 RX DQ/DQS(RDDQC) : PASS
7066 13:45:13.278207 TX DQ/DQS : PASS
7067 13:45:13.281376 RX DATLAT : PASS
7068 13:45:13.284500 RX DQ/DQS(Engine): PASS
7069 13:45:13.284609 TX OE : NO K
7070 13:45:13.288578 All Pass.
7071 13:45:13.288689
7072 13:45:13.288786 CH 1, Rank 0
7073 13:45:13.291345 SW Impedance : PASS
7074 13:45:13.291453 DUTY Scan : NO K
7075 13:45:13.294375 ZQ Calibration : PASS
7076 13:45:13.298171 Jitter Meter : NO K
7077 13:45:13.298281 CBT Training : PASS
7078 13:45:13.300876 Write leveling : PASS
7079 13:45:13.304492 RX DQS gating : PASS
7080 13:45:13.304600 RX DQ/DQS(RDDQC) : PASS
7081 13:45:13.308162 TX DQ/DQS : PASS
7082 13:45:13.308272 RX DATLAT : PASS
7083 13:45:13.310999 RX DQ/DQS(Engine): PASS
7084 13:45:13.314463 TX OE : NO K
7085 13:45:13.314573 All Pass.
7086 13:45:13.314669
7087 13:45:13.314761 CH 1, Rank 1
7088 13:45:13.317849 SW Impedance : PASS
7089 13:45:13.320994 DUTY Scan : NO K
7090 13:45:13.321103 ZQ Calibration : PASS
7091 13:45:13.324181 Jitter Meter : NO K
7092 13:45:13.327607 CBT Training : PASS
7093 13:45:13.327719 Write leveling : NO K
7094 13:45:13.331238 RX DQS gating : PASS
7095 13:45:13.334757 RX DQ/DQS(RDDQC) : PASS
7096 13:45:13.334866 TX DQ/DQS : PASS
7097 13:45:13.337443 RX DATLAT : PASS
7098 13:45:13.340983 RX DQ/DQS(Engine): PASS
7099 13:45:13.341093 TX OE : NO K
7100 13:45:13.344127 All Pass.
7101 13:45:13.344236
7102 13:45:13.344334 DramC Write-DBI off
7103 13:45:13.347441 PER_BANK_REFRESH: Hybrid Mode
7104 13:45:13.347546 TX_TRACKING: ON
7105 13:45:13.357683 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7106 13:45:13.361314 [FAST_K] Save calibration result to emmc
7107 13:45:13.364281 dramc_set_vcore_voltage set vcore to 725000
7108 13:45:13.367756 Read voltage for 1600, 0
7109 13:45:13.367865 Vio18 = 0
7110 13:45:13.370674 Vcore = 725000
7111 13:45:13.370782 Vdram = 0
7112 13:45:13.370876 Vddq = 0
7113 13:45:13.374219 Vmddr = 0
7114 13:45:13.377683 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7115 13:45:13.384243 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7116 13:45:13.384391 MEM_TYPE=3, freq_sel=13
7117 13:45:13.387810 sv_algorithm_assistance_LP4_3733
7118 13:45:13.394146 ============ PULL DRAM RESETB DOWN ============
7119 13:45:13.397638 ========== PULL DRAM RESETB DOWN end =========
7120 13:45:13.401043 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7121 13:45:13.404494 ===================================
7122 13:45:13.407528 LPDDR4 DRAM CONFIGURATION
7123 13:45:13.410658 ===================================
7124 13:45:13.410770 EX_ROW_EN[0] = 0x0
7125 13:45:13.414024 EX_ROW_EN[1] = 0x0
7126 13:45:13.417110 LP4Y_EN = 0x0
7127 13:45:13.417260 WORK_FSP = 0x1
7128 13:45:13.420860 WL = 0x5
7129 13:45:13.420967 RL = 0x5
7130 13:45:13.424099 BL = 0x2
7131 13:45:13.424227 RPST = 0x0
7132 13:45:13.427518 RD_PRE = 0x0
7133 13:45:13.427656 WR_PRE = 0x1
7134 13:45:13.430968 WR_PST = 0x1
7135 13:45:13.431068 DBI_WR = 0x0
7136 13:45:13.434243 DBI_RD = 0x0
7137 13:45:13.434337 OTF = 0x1
7138 13:45:13.437599 ===================================
7139 13:45:13.440524 ===================================
7140 13:45:13.444113 ANA top config
7141 13:45:13.447663 ===================================
7142 13:45:13.447774 DLL_ASYNC_EN = 0
7143 13:45:13.450891 ALL_SLAVE_EN = 0
7144 13:45:13.454037 NEW_RANK_MODE = 1
7145 13:45:13.456952 DLL_IDLE_MODE = 1
7146 13:45:13.460574 LP45_APHY_COMB_EN = 1
7147 13:45:13.460691 TX_ODT_DIS = 0
7148 13:45:13.464046 NEW_8X_MODE = 1
7149 13:45:13.466913 ===================================
7150 13:45:13.470526 ===================================
7151 13:45:13.473405 data_rate = 3200
7152 13:45:13.476891 CKR = 1
7153 13:45:13.480444 DQ_P2S_RATIO = 8
7154 13:45:13.483814 ===================================
7155 13:45:13.486759 CA_P2S_RATIO = 8
7156 13:45:13.486865 DQ_CA_OPEN = 0
7157 13:45:13.490347 DQ_SEMI_OPEN = 0
7158 13:45:13.493197 CA_SEMI_OPEN = 0
7159 13:45:13.496800 CA_FULL_RATE = 0
7160 13:45:13.500364 DQ_CKDIV4_EN = 0
7161 13:45:13.503354 CA_CKDIV4_EN = 0
7162 13:45:13.503437 CA_PREDIV_EN = 0
7163 13:45:13.506796 PH8_DLY = 12
7164 13:45:13.510546 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7165 13:45:13.513443 DQ_AAMCK_DIV = 4
7166 13:45:13.517089 CA_AAMCK_DIV = 4
7167 13:45:13.520491 CA_ADMCK_DIV = 4
7168 13:45:13.520575 DQ_TRACK_CA_EN = 0
7169 13:45:13.523190 CA_PICK = 1600
7170 13:45:13.526453 CA_MCKIO = 1600
7171 13:45:13.530380 MCKIO_SEMI = 0
7172 13:45:13.533422 PLL_FREQ = 3068
7173 13:45:13.537052 DQ_UI_PI_RATIO = 32
7174 13:45:13.539903 CA_UI_PI_RATIO = 0
7175 13:45:13.543706 ===================================
7176 13:45:13.546705 ===================================
7177 13:45:13.546787 memory_type:LPDDR4
7178 13:45:13.549927 GP_NUM : 10
7179 13:45:13.550009 SRAM_EN : 1
7180 13:45:13.553570 MD32_EN : 0
7181 13:45:13.556584 ===================================
7182 13:45:13.559905 [ANA_INIT] >>>>>>>>>>>>>>
7183 13:45:13.563610 <<<<<< [CONFIGURE PHASE]: ANA_TX
7184 13:45:13.566548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7185 13:45:13.570424 ===================================
7186 13:45:13.570509 data_rate = 3200,PCW = 0X7600
7187 13:45:13.573314 ===================================
7188 13:45:13.580312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7189 13:45:13.583176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 13:45:13.590160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 13:45:13.593054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7192 13:45:13.596645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7193 13:45:13.600201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7194 13:45:13.603078 [ANA_INIT] flow start
7195 13:45:13.606700 [ANA_INIT] PLL >>>>>>>>
7196 13:45:13.606783 [ANA_INIT] PLL <<<<<<<<
7197 13:45:13.610371 [ANA_INIT] MIDPI >>>>>>>>
7198 13:45:13.613264 [ANA_INIT] MIDPI <<<<<<<<
7199 13:45:13.613346 [ANA_INIT] DLL >>>>>>>>
7200 13:45:13.616896 [ANA_INIT] DLL <<<<<<<<
7201 13:45:13.619618 [ANA_INIT] flow end
7202 13:45:13.623154 ============ LP4 DIFF to SE enter ============
7203 13:45:13.626767 ============ LP4 DIFF to SE exit ============
7204 13:45:13.629581 [ANA_INIT] <<<<<<<<<<<<<
7205 13:45:13.633114 [Flow] Enable top DCM control >>>>>
7206 13:45:13.636775 [Flow] Enable top DCM control <<<<<
7207 13:45:13.639558 Enable DLL master slave shuffle
7208 13:45:13.643090 ==============================================================
7209 13:45:13.646668 Gating Mode config
7210 13:45:13.652838 ==============================================================
7211 13:45:13.652969 Config description:
7212 13:45:13.662845 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7213 13:45:13.669752 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7214 13:45:13.672982 SELPH_MODE 0: By rank 1: By Phase
7215 13:45:13.679459 ==============================================================
7216 13:45:13.682968 GAT_TRACK_EN = 1
7217 13:45:13.686376 RX_GATING_MODE = 2
7218 13:45:13.689464 RX_GATING_TRACK_MODE = 2
7219 13:45:13.692683 SELPH_MODE = 1
7220 13:45:13.696063 PICG_EARLY_EN = 1
7221 13:45:13.699414 VALID_LAT_VALUE = 1
7222 13:45:13.702835 ==============================================================
7223 13:45:13.706411 Enter into Gating configuration >>>>
7224 13:45:13.709341 Exit from Gating configuration <<<<
7225 13:45:13.712949 Enter into DVFS_PRE_config >>>>>
7226 13:45:13.726557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7227 13:45:13.726643 Exit from DVFS_PRE_config <<<<<
7228 13:45:13.729381 Enter into PICG configuration >>>>
7229 13:45:13.732924 Exit from PICG configuration <<<<
7230 13:45:13.736479 [RX_INPUT] configuration >>>>>
7231 13:45:13.739431 [RX_INPUT] configuration <<<<<
7232 13:45:13.745875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7233 13:45:13.749374 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7234 13:45:13.756476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 13:45:13.762920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 13:45:13.769367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 13:45:13.776273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 13:45:13.779628 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7239 13:45:13.782578 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7240 13:45:13.786050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7241 13:45:13.792849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7242 13:45:13.795905 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7243 13:45:13.799259 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 13:45:13.802470 ===================================
7245 13:45:13.806365 LPDDR4 DRAM CONFIGURATION
7246 13:45:13.809544 ===================================
7247 13:45:13.809625 EX_ROW_EN[0] = 0x0
7248 13:45:13.812891 EX_ROW_EN[1] = 0x0
7249 13:45:13.815984 LP4Y_EN = 0x0
7250 13:45:13.816065 WORK_FSP = 0x1
7251 13:45:13.819025 WL = 0x5
7252 13:45:13.819106 RL = 0x5
7253 13:45:13.822844 BL = 0x2
7254 13:45:13.822925 RPST = 0x0
7255 13:45:13.825661 RD_PRE = 0x0
7256 13:45:13.825768 WR_PRE = 0x1
7257 13:45:13.829203 WR_PST = 0x1
7258 13:45:13.829284 DBI_WR = 0x0
7259 13:45:13.832164 DBI_RD = 0x0
7260 13:45:13.832271 OTF = 0x1
7261 13:45:13.835920 ===================================
7262 13:45:13.839349 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7263 13:45:13.846011 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7264 13:45:13.848941 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 13:45:13.852511 ===================================
7266 13:45:13.856018 LPDDR4 DRAM CONFIGURATION
7267 13:45:13.859377 ===================================
7268 13:45:13.859461 EX_ROW_EN[0] = 0x10
7269 13:45:13.862279 EX_ROW_EN[1] = 0x0
7270 13:45:13.862359 LP4Y_EN = 0x0
7271 13:45:13.865778 WORK_FSP = 0x1
7272 13:45:13.865860 WL = 0x5
7273 13:45:13.869318 RL = 0x5
7274 13:45:13.872193 BL = 0x2
7275 13:45:13.872274 RPST = 0x0
7276 13:45:13.875735 RD_PRE = 0x0
7277 13:45:13.875815 WR_PRE = 0x1
7278 13:45:13.879212 WR_PST = 0x1
7279 13:45:13.879294 DBI_WR = 0x0
7280 13:45:13.882852 DBI_RD = 0x0
7281 13:45:13.882933 OTF = 0x1
7282 13:45:13.885401 ===================================
7283 13:45:13.892376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7284 13:45:13.892458 ==
7285 13:45:13.896002 Dram Type= 6, Freq= 0, CH_0, rank 0
7286 13:45:13.898703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 13:45:13.898784 ==
7288 13:45:13.902085 [Duty_Offset_Calibration]
7289 13:45:13.905440 B0:2 B1:1 CA:1
7290 13:45:13.905520
7291 13:45:13.908964 [DutyScan_Calibration_Flow] k_type=0
7292 13:45:13.917187
7293 13:45:13.917293 ==CLK 0==
7294 13:45:13.920698 Final CLK duty delay cell = 0
7295 13:45:13.924099 [0] MAX Duty = 5156%(X100), DQS PI = 22
7296 13:45:13.927477 [0] MIN Duty = 4876%(X100), DQS PI = 48
7297 13:45:13.927559 [0] AVG Duty = 5016%(X100)
7298 13:45:13.930645
7299 13:45:13.933764 CH0 CLK Duty spec in!! Max-Min= 280%
7300 13:45:13.936975 [DutyScan_Calibration_Flow] ====Done====
7301 13:45:13.937080
7302 13:45:13.940248 [DutyScan_Calibration_Flow] k_type=1
7303 13:45:13.956503
7304 13:45:13.956584 ==DQS 0 ==
7305 13:45:13.959978 Final DQS duty delay cell = -4
7306 13:45:13.962837 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7307 13:45:13.966204 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7308 13:45:13.969714 [-4] AVG Duty = 4906%(X100)
7309 13:45:13.969821
7310 13:45:13.969912 ==DQS 1 ==
7311 13:45:13.973212 Final DQS duty delay cell = 0
7312 13:45:13.976814 [0] MAX Duty = 5187%(X100), DQS PI = 22
7313 13:45:13.979770 [0] MIN Duty = 5031%(X100), DQS PI = 52
7314 13:45:13.983367 [0] AVG Duty = 5109%(X100)
7315 13:45:13.983448
7316 13:45:13.986145 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7317 13:45:13.986226
7318 13:45:13.989601 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7319 13:45:13.993012 [DutyScan_Calibration_Flow] ====Done====
7320 13:45:13.993093
7321 13:45:13.996508 [DutyScan_Calibration_Flow] k_type=3
7322 13:45:14.013578
7323 13:45:14.013658 ==DQM 0 ==
7324 13:45:14.017403 Final DQM duty delay cell = 0
7325 13:45:14.020644 [0] MAX Duty = 5218%(X100), DQS PI = 34
7326 13:45:14.023986 [0] MIN Duty = 4844%(X100), DQS PI = 60
7327 13:45:14.027061 [0] AVG Duty = 5031%(X100)
7328 13:45:14.027143
7329 13:45:14.027207 ==DQM 1 ==
7330 13:45:14.030459 Final DQM duty delay cell = 0
7331 13:45:14.034001 [0] MAX Duty = 5187%(X100), DQS PI = 6
7332 13:45:14.036786 [0] MIN Duty = 5062%(X100), DQS PI = 12
7333 13:45:14.040282 [0] AVG Duty = 5124%(X100)
7334 13:45:14.040406
7335 13:45:14.043772 CH0 DQM 0 Duty spec in!! Max-Min= 374%
7336 13:45:14.043854
7337 13:45:14.047144 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7338 13:45:14.050051 [DutyScan_Calibration_Flow] ====Done====
7339 13:45:14.050133
7340 13:45:14.053253 [DutyScan_Calibration_Flow] k_type=2
7341 13:45:14.071180
7342 13:45:14.071265 ==DQ 0 ==
7343 13:45:14.074580 Final DQ duty delay cell = 0
7344 13:45:14.077812 [0] MAX Duty = 5062%(X100), DQS PI = 24
7345 13:45:14.080704 [0] MIN Duty = 4907%(X100), DQS PI = 0
7346 13:45:14.080787 [0] AVG Duty = 4984%(X100)
7347 13:45:14.084374
7348 13:45:14.084468 ==DQ 1 ==
7349 13:45:14.088042 Final DQ duty delay cell = 0
7350 13:45:14.090957 [0] MAX Duty = 5125%(X100), DQS PI = 6
7351 13:45:14.094454 [0] MIN Duty = 4938%(X100), DQS PI = 34
7352 13:45:14.094535 [0] AVG Duty = 5031%(X100)
7353 13:45:14.094612
7354 13:45:14.097708 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7355 13:45:14.097791
7356 13:45:14.101243 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7357 13:45:14.107695 [DutyScan_Calibration_Flow] ====Done====
7358 13:45:14.107777 ==
7359 13:45:14.111239 Dram Type= 6, Freq= 0, CH_1, rank 0
7360 13:45:14.114118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7361 13:45:14.114202 ==
7362 13:45:14.117515 [Duty_Offset_Calibration]
7363 13:45:14.117621 B0:1 B1:0 CA:0
7364 13:45:14.117712
7365 13:45:14.121002 [DutyScan_Calibration_Flow] k_type=0
7366 13:45:14.130487
7367 13:45:14.130567 ==CLK 0==
7368 13:45:14.133290 Final CLK duty delay cell = -4
7369 13:45:14.136652 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7370 13:45:14.139899 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7371 13:45:14.143210 [-4] AVG Duty = 4922%(X100)
7372 13:45:14.143290
7373 13:45:14.147300 CH1 CLK Duty spec in!! Max-Min= 156%
7374 13:45:14.150216 [DutyScan_Calibration_Flow] ====Done====
7375 13:45:14.150296
7376 13:45:14.153771 [DutyScan_Calibration_Flow] k_type=1
7377 13:45:14.170591
7378 13:45:14.170671 ==DQS 0 ==
7379 13:45:14.173853 Final DQS duty delay cell = 0
7380 13:45:14.176740 [0] MAX Duty = 5094%(X100), DQS PI = 16
7381 13:45:14.180286 [0] MIN Duty = 4875%(X100), DQS PI = 0
7382 13:45:14.180420 [0] AVG Duty = 4984%(X100)
7383 13:45:14.183682
7384 13:45:14.183761 ==DQS 1 ==
7385 13:45:14.187070 Final DQS duty delay cell = 0
7386 13:45:14.190455 [0] MAX Duty = 5249%(X100), DQS PI = 16
7387 13:45:14.193347 [0] MIN Duty = 4969%(X100), DQS PI = 6
7388 13:45:14.193427 [0] AVG Duty = 5109%(X100)
7389 13:45:14.196832
7390 13:45:14.200368 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7391 13:45:14.200463
7392 13:45:14.203858 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7393 13:45:14.206657 [DutyScan_Calibration_Flow] ====Done====
7394 13:45:14.206737
7395 13:45:14.210272 [DutyScan_Calibration_Flow] k_type=3
7396 13:45:14.227333
7397 13:45:14.227413 ==DQM 0 ==
7398 13:45:14.230928 Final DQM duty delay cell = 0
7399 13:45:14.233642 [0] MAX Duty = 5218%(X100), DQS PI = 20
7400 13:45:14.237048 [0] MIN Duty = 4969%(X100), DQS PI = 48
7401 13:45:14.237128 [0] AVG Duty = 5093%(X100)
7402 13:45:14.240654
7403 13:45:14.240734 ==DQM 1 ==
7404 13:45:14.243878 Final DQM duty delay cell = 0
7405 13:45:14.247404 [0] MAX Duty = 5093%(X100), DQS PI = 16
7406 13:45:14.250742 [0] MIN Duty = 4876%(X100), DQS PI = 52
7407 13:45:14.254065 [0] AVG Duty = 4984%(X100)
7408 13:45:14.254145
7409 13:45:14.257303 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7410 13:45:14.257386
7411 13:45:14.260189 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7412 13:45:14.263492 [DutyScan_Calibration_Flow] ====Done====
7413 13:45:14.263578
7414 13:45:14.267064 [DutyScan_Calibration_Flow] k_type=2
7415 13:45:14.283442
7416 13:45:14.283526 ==DQ 0 ==
7417 13:45:14.286597 Final DQ duty delay cell = -4
7418 13:45:14.290119 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7419 13:45:14.293445 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7420 13:45:14.296834 [-4] AVG Duty = 4968%(X100)
7421 13:45:14.296915
7422 13:45:14.296987 ==DQ 1 ==
7423 13:45:14.300261 Final DQ duty delay cell = 0
7424 13:45:14.302970 [0] MAX Duty = 5124%(X100), DQS PI = 16
7425 13:45:14.306466 [0] MIN Duty = 4938%(X100), DQS PI = 8
7426 13:45:14.309916 [0] AVG Duty = 5031%(X100)
7427 13:45:14.309997
7428 13:45:14.313395 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7429 13:45:14.313476
7430 13:45:14.316918 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7431 13:45:14.319748 [DutyScan_Calibration_Flow] ====Done====
7432 13:45:14.323394 nWR fixed to 30
7433 13:45:14.323475 [ModeRegInit_LP4] CH0 RK0
7434 13:45:14.326321 [ModeRegInit_LP4] CH0 RK1
7435 13:45:14.329789 [ModeRegInit_LP4] CH1 RK0
7436 13:45:14.333389 [ModeRegInit_LP4] CH1 RK1
7437 13:45:14.333470 match AC timing 5
7438 13:45:14.339592 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7439 13:45:14.342851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7440 13:45:14.346302 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7441 13:45:14.352623 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7442 13:45:14.356265 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7443 13:45:14.356410 [MiockJmeterHQA]
7444 13:45:14.356502
7445 13:45:14.359875 [DramcMiockJmeter] u1RxGatingPI = 0
7446 13:45:14.362501 0 : 4252, 4027
7447 13:45:14.362584 4 : 4252, 4027
7448 13:45:14.365821 8 : 4252, 4027
7449 13:45:14.365903 12 : 4366, 4140
7450 13:45:14.369174 16 : 4253, 4027
7451 13:45:14.369255 20 : 4257, 4029
7452 13:45:14.369319 24 : 4252, 4026
7453 13:45:14.372873 28 : 4255, 4029
7454 13:45:14.372954 32 : 4368, 4142
7455 13:45:14.375789 36 : 4252, 4026
7456 13:45:14.375870 40 : 4252, 4027
7457 13:45:14.379227 44 : 4252, 4027
7458 13:45:14.379309 48 : 4365, 4140
7459 13:45:14.379373 52 : 4252, 4027
7460 13:45:14.382790 56 : 4363, 4137
7461 13:45:14.382872 60 : 4250, 4026
7462 13:45:14.386249 64 : 4250, 4027
7463 13:45:14.386331 68 : 4252, 4027
7464 13:45:14.389101 72 : 4255, 4031
7465 13:45:14.389185 76 : 4249, 4027
7466 13:45:14.392516 80 : 4360, 4138
7467 13:45:14.392598 84 : 4361, 4137
7468 13:45:14.392662 88 : 4250, 280
7469 13:45:14.395785 92 : 4250, 0
7470 13:45:14.395869 96 : 4255, 0
7471 13:45:14.399203 100 : 4363, 0
7472 13:45:14.399285 104 : 4361, 0
7473 13:45:14.399350 108 : 4360, 0
7474 13:45:14.402431 112 : 4250, 0
7475 13:45:14.402513 116 : 4360, 0
7476 13:45:14.402578 120 : 4250, 0
7477 13:45:14.405807 124 : 4253, 0
7478 13:45:14.405889 128 : 4250, 0
7479 13:45:14.409307 132 : 4250, 0
7480 13:45:14.409389 136 : 4252, 0
7481 13:45:14.409453 140 : 4250, 0
7482 13:45:14.412623 144 : 4255, 0
7483 13:45:14.412732 148 : 4254, 0
7484 13:45:14.415997 152 : 4250, 0
7485 13:45:14.416078 156 : 4250, 0
7486 13:45:14.416143 160 : 4360, 0
7487 13:45:14.418721 164 : 4250, 0
7488 13:45:14.418803 168 : 4250, 0
7489 13:45:14.422197 172 : 4250, 0
7490 13:45:14.422279 176 : 4250, 0
7491 13:45:14.422343 180 : 4250, 0
7492 13:45:14.425805 184 : 4250, 0
7493 13:45:14.425887 188 : 4253, 0
7494 13:45:14.429371 192 : 4250, 0
7495 13:45:14.429452 196 : 4250, 0
7496 13:45:14.429517 200 : 4250, 0
7497 13:45:14.432199 204 : 4250, 1098
7498 13:45:14.432308 208 : 4249, 3973
7499 13:45:14.435853 212 : 4361, 4137
7500 13:45:14.435934 216 : 4360, 4138
7501 13:45:14.439140 220 : 4252, 4029
7502 13:45:14.439222 224 : 4253, 4029
7503 13:45:14.442063 228 : 4361, 4137
7504 13:45:14.442145 232 : 4361, 4137
7505 13:45:14.445660 236 : 4250, 4027
7506 13:45:14.445741 240 : 4249, 4027
7507 13:45:14.445807 244 : 4250, 4027
7508 13:45:14.448988 248 : 4250, 4027
7509 13:45:14.449070 252 : 4250, 4027
7510 13:45:14.452497 256 : 4250, 4027
7511 13:45:14.452579 260 : 4253, 4029
7512 13:45:14.455348 264 : 4250, 4027
7513 13:45:14.455456 268 : 4360, 4137
7514 13:45:14.458861 272 : 4361, 4137
7515 13:45:14.458946 276 : 4247, 4025
7516 13:45:14.462562 280 : 4360, 4138
7517 13:45:14.462644 284 : 4250, 4027
7518 13:45:14.465499 288 : 4250, 4026
7519 13:45:14.465581 292 : 4249, 4027
7520 13:45:14.469058 296 : 4253, 4029
7521 13:45:14.469140 300 : 4252, 4030
7522 13:45:14.469204 304 : 4250, 4027
7523 13:45:14.472456 308 : 4249, 3993
7524 13:45:14.472538 312 : 4250, 2296
7525 13:45:14.475830 316 : 4250, 6
7526 13:45:14.475912
7527 13:45:14.475976 MIOCK jitter meter ch=0
7528 13:45:14.478935
7529 13:45:14.479016 1T = (316-88) = 228 dly cells
7530 13:45:14.485633 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7531 13:45:14.485717 ==
7532 13:45:14.488606 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 13:45:14.492227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 13:45:14.492310 ==
7535 13:45:14.499181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7536 13:45:14.501976 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7537 13:45:14.508627 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7538 13:45:14.511901 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7539 13:45:14.522173 [CA 0] Center 43 (13~73) winsize 61
7540 13:45:14.525531 [CA 1] Center 43 (12~74) winsize 63
7541 13:45:14.528839 [CA 2] Center 38 (8~68) winsize 61
7542 13:45:14.532297 [CA 3] Center 37 (8~67) winsize 60
7543 13:45:14.535811 [CA 4] Center 36 (7~66) winsize 60
7544 13:45:14.538735 [CA 5] Center 35 (6~65) winsize 60
7545 13:45:14.538817
7546 13:45:14.542309 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7547 13:45:14.542392
7548 13:45:14.545676 [CATrainingPosCal] consider 1 rank data
7549 13:45:14.548609 u2DelayCellTimex100 = 285/100 ps
7550 13:45:14.552123 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7551 13:45:14.558907 CA1 delay=43 (12~74),Diff = 8 PI (27 cell)
7552 13:45:14.562274 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7553 13:45:14.565255 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7554 13:45:14.568845 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7555 13:45:14.572474 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7556 13:45:14.572558
7557 13:45:14.575305 CA PerBit enable=1, Macro0, CA PI delay=35
7558 13:45:14.575389
7559 13:45:14.578374 [CBTSetCACLKResult] CA Dly = 35
7560 13:45:14.582019 CS Dly: 9 (0~40)
7561 13:45:14.585274 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7562 13:45:14.588661 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7563 13:45:14.588744 ==
7564 13:45:14.591882 Dram Type= 6, Freq= 0, CH_0, rank 1
7565 13:45:14.595293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 13:45:14.598710 ==
7567 13:45:14.601429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7568 13:45:14.605035 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7569 13:45:14.611487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7570 13:45:14.614856 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7571 13:45:14.625547 [CA 0] Center 42 (12~72) winsize 61
7572 13:45:14.629016 [CA 1] Center 42 (12~73) winsize 62
7573 13:45:14.631953 [CA 2] Center 38 (8~68) winsize 61
7574 13:45:14.635766 [CA 3] Center 38 (8~68) winsize 61
7575 13:45:14.639086 [CA 4] Center 35 (6~65) winsize 60
7576 13:45:14.642337 [CA 5] Center 35 (5~65) winsize 61
7577 13:45:14.642426
7578 13:45:14.645665 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7579 13:45:14.645751
7580 13:45:14.649126 [CATrainingPosCal] consider 2 rank data
7581 13:45:14.652078 u2DelayCellTimex100 = 285/100 ps
7582 13:45:14.655772 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7583 13:45:14.662043 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7584 13:45:14.665345 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7585 13:45:14.668745 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7586 13:45:14.672198 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7587 13:45:14.675664 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7588 13:45:14.675754
7589 13:45:14.679220 CA PerBit enable=1, Macro0, CA PI delay=35
7590 13:45:14.679307
7591 13:45:14.682118 [CBTSetCACLKResult] CA Dly = 35
7592 13:45:14.685676 CS Dly: 10 (0~42)
7593 13:45:14.688521 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7594 13:45:14.692042 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7595 13:45:14.692127
7596 13:45:14.695577 ----->DramcWriteLeveling(PI) begin...
7597 13:45:14.695662 ==
7598 13:45:14.698396 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 13:45:14.701774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 13:45:14.705643 ==
7601 13:45:14.705727 Write leveling (Byte 0): 33 => 33
7602 13:45:14.708769 Write leveling (Byte 1): 27 => 27
7603 13:45:14.712109 DramcWriteLeveling(PI) end<-----
7604 13:45:14.712192
7605 13:45:14.712257 ==
7606 13:45:14.715763 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 13:45:14.721956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 13:45:14.722040 ==
7609 13:45:14.725401 [Gating] SW mode calibration
7610 13:45:14.731588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7611 13:45:14.735518 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7612 13:45:14.741660 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 13:45:14.745248 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 13:45:14.748571 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7615 13:45:14.755149 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7616 13:45:14.758387 1 4 16 | B1->B0 | 2424 3736 | 0 1 | (0 0) (1 1)
7617 13:45:14.761904 1 4 20 | B1->B0 | 3434 3636 | 0 0 | (0 0) (0 0)
7618 13:45:14.768255 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7619 13:45:14.771821 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7620 13:45:14.775101 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7621 13:45:14.778417 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7622 13:45:14.784971 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 0)
7623 13:45:14.788654 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
7624 13:45:14.791537 1 5 16 | B1->B0 | 3434 2626 | 0 0 | (0 0) (0 0)
7625 13:45:14.797961 1 5 20 | B1->B0 | 2525 2525 | 0 0 | (1 0) (0 0)
7626 13:45:14.801617 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
7627 13:45:14.805247 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7628 13:45:14.811383 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 13:45:14.814980 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 13:45:14.818227 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7631 13:45:14.824898 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7632 13:45:14.828255 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7633 13:45:14.831826 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7634 13:45:14.838230 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 13:45:14.841570 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 13:45:14.844830 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 13:45:14.851411 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 13:45:14.855030 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 13:45:14.857852 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7640 13:45:14.864786 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 13:45:14.868034 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7642 13:45:14.871362 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 13:45:14.877842 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 13:45:14.881275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 13:45:14.884593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 13:45:14.891001 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 13:45:14.894675 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 13:45:14.898215 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 13:45:14.904680 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 13:45:14.907619 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 13:45:14.911112 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 13:45:14.914848 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 13:45:14.920807 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 13:45:14.924460 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 13:45:14.928011 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7656 13:45:14.934537 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 13:45:14.937874 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7658 13:45:14.940774 Total UI for P1: 0, mck2ui 16
7659 13:45:14.944513 best dqsien dly found for B0: ( 1, 9, 14)
7660 13:45:14.947361 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 13:45:14.951017 Total UI for P1: 0, mck2ui 16
7662 13:45:14.954575 best dqsien dly found for B1: ( 1, 9, 20)
7663 13:45:14.957380 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7664 13:45:14.960589 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7665 13:45:14.964537
7666 13:45:14.967900 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7667 13:45:14.971160 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7668 13:45:14.974459 [Gating] SW calibration Done
7669 13:45:14.974544 ==
7670 13:45:14.977721 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 13:45:14.981008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 13:45:14.981095 ==
7673 13:45:14.981181 RX Vref Scan: 0
7674 13:45:14.984193
7675 13:45:14.984277 RX Vref 0 -> 0, step: 1
7676 13:45:14.984411
7677 13:45:14.987636 RX Delay 0 -> 252, step: 8
7678 13:45:14.991021 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7679 13:45:14.994444 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7680 13:45:15.000740 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7681 13:45:15.004324 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7682 13:45:15.007943 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7683 13:45:15.010814 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7684 13:45:15.014432 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7685 13:45:15.017378 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7686 13:45:15.023919 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7687 13:45:15.027613 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7688 13:45:15.030542 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7689 13:45:15.034242 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7690 13:45:15.037138 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7691 13:45:15.044037 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7692 13:45:15.047685 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7693 13:45:15.050761 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7694 13:45:15.050853 ==
7695 13:45:15.054697 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 13:45:15.057601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 13:45:15.057698 ==
7698 13:45:15.061267 DQS Delay:
7699 13:45:15.061360 DQS0 = 0, DQS1 = 0
7700 13:45:15.064112 DQM Delay:
7701 13:45:15.064198 DQM0 = 136, DQM1 = 129
7702 13:45:15.064300 DQ Delay:
7703 13:45:15.071187 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7704 13:45:15.073968 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7705 13:45:15.077453 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7706 13:45:15.080832 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7707 13:45:15.080919
7708 13:45:15.080984
7709 13:45:15.081043 ==
7710 13:45:15.084111 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 13:45:15.087585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 13:45:15.087670 ==
7713 13:45:15.087734
7714 13:45:15.087794
7715 13:45:15.091029 TX Vref Scan disable
7716 13:45:15.094658 == TX Byte 0 ==
7717 13:45:15.097482 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7718 13:45:15.100808 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7719 13:45:15.104402 == TX Byte 1 ==
7720 13:45:15.107606 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7721 13:45:15.110968 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7722 13:45:15.111050 ==
7723 13:45:15.114485 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 13:45:15.120772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 13:45:15.120858 ==
7726 13:45:15.132277
7727 13:45:15.136026 TX Vref early break, caculate TX vref
7728 13:45:15.138960 TX Vref=16, minBit 0, minWin=23, winSum=377
7729 13:45:15.142482 TX Vref=18, minBit 7, minWin=23, winSum=389
7730 13:45:15.146179 TX Vref=20, minBit 7, minWin=24, winSum=400
7731 13:45:15.148983 TX Vref=22, minBit 0, minWin=25, winSum=408
7732 13:45:15.152560 TX Vref=24, minBit 0, minWin=26, winSum=420
7733 13:45:15.159220 TX Vref=26, minBit 8, minWin=25, winSum=424
7734 13:45:15.162516 TX Vref=28, minBit 1, minWin=25, winSum=426
7735 13:45:15.165592 TX Vref=30, minBit 0, minWin=25, winSum=417
7736 13:45:15.168703 TX Vref=32, minBit 6, minWin=24, winSum=406
7737 13:45:15.172223 TX Vref=34, minBit 1, minWin=23, winSum=397
7738 13:45:15.179131 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 24
7739 13:45:15.179257
7740 13:45:15.182613 Final TX Range 0 Vref 24
7741 13:45:15.182706
7742 13:45:15.182770 ==
7743 13:45:15.185534 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 13:45:15.188967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 13:45:15.189058 ==
7746 13:45:15.189129
7747 13:45:15.189189
7748 13:45:15.192246 TX Vref Scan disable
7749 13:45:15.198915 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7750 13:45:15.199059 == TX Byte 0 ==
7751 13:45:15.202274 u2DelayCellOfst[0]=13 cells (4 PI)
7752 13:45:15.205854 u2DelayCellOfst[1]=13 cells (4 PI)
7753 13:45:15.208610 u2DelayCellOfst[2]=10 cells (3 PI)
7754 13:45:15.212125 u2DelayCellOfst[3]=10 cells (3 PI)
7755 13:45:15.215451 u2DelayCellOfst[4]=6 cells (2 PI)
7756 13:45:15.218688 u2DelayCellOfst[5]=0 cells (0 PI)
7757 13:45:15.222393 u2DelayCellOfst[6]=17 cells (5 PI)
7758 13:45:15.225477 u2DelayCellOfst[7]=13 cells (4 PI)
7759 13:45:15.228593 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7760 13:45:15.232271 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7761 13:45:15.235824 == TX Byte 1 ==
7762 13:45:15.235924 u2DelayCellOfst[8]=3 cells (1 PI)
7763 13:45:15.238754 u2DelayCellOfst[9]=0 cells (0 PI)
7764 13:45:15.242354 u2DelayCellOfst[10]=6 cells (2 PI)
7765 13:45:15.245259 u2DelayCellOfst[11]=3 cells (1 PI)
7766 13:45:15.248846 u2DelayCellOfst[12]=10 cells (3 PI)
7767 13:45:15.251767 u2DelayCellOfst[13]=10 cells (3 PI)
7768 13:45:15.255371 u2DelayCellOfst[14]=13 cells (4 PI)
7769 13:45:15.259007 u2DelayCellOfst[15]=10 cells (3 PI)
7770 13:45:15.261755 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7771 13:45:15.268836 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7772 13:45:15.268933 DramC Write-DBI on
7773 13:45:15.269019 ==
7774 13:45:15.272289 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 13:45:15.275556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 13:45:15.278090 ==
7777 13:45:15.278174
7778 13:45:15.278258
7779 13:45:15.278337 TX Vref Scan disable
7780 13:45:15.282106 == TX Byte 0 ==
7781 13:45:15.285771 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7782 13:45:15.288465 == TX Byte 1 ==
7783 13:45:15.291959 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7784 13:45:15.295528 DramC Write-DBI off
7785 13:45:15.295624
7786 13:45:15.295710 [DATLAT]
7787 13:45:15.295790 Freq=1600, CH0 RK0
7788 13:45:15.295887
7789 13:45:15.298363 DATLAT Default: 0xf
7790 13:45:15.298473 0, 0xFFFF, sum = 0
7791 13:45:15.301854 1, 0xFFFF, sum = 0
7792 13:45:15.301949 2, 0xFFFF, sum = 0
7793 13:45:15.304970 3, 0xFFFF, sum = 0
7794 13:45:15.308258 4, 0xFFFF, sum = 0
7795 13:45:15.308402 5, 0xFFFF, sum = 0
7796 13:45:15.311736 6, 0xFFFF, sum = 0
7797 13:45:15.311862 7, 0xFFFF, sum = 0
7798 13:45:15.315125 8, 0xFFFF, sum = 0
7799 13:45:15.315244 9, 0xFFFF, sum = 0
7800 13:45:15.318588 10, 0xFFFF, sum = 0
7801 13:45:15.318752 11, 0xFFFF, sum = 0
7802 13:45:15.321443 12, 0xFFFF, sum = 0
7803 13:45:15.321531 13, 0xFFFF, sum = 0
7804 13:45:15.325099 14, 0x0, sum = 1
7805 13:45:15.325221 15, 0x0, sum = 2
7806 13:45:15.328027 16, 0x0, sum = 3
7807 13:45:15.328117 17, 0x0, sum = 4
7808 13:45:15.331478 best_step = 15
7809 13:45:15.331563
7810 13:45:15.331628 ==
7811 13:45:15.334889 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 13:45:15.338056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 13:45:15.338134 ==
7814 13:45:15.341746 RX Vref Scan: 1
7815 13:45:15.341833
7816 13:45:15.341898 Set Vref Range= 24 -> 127
7817 13:45:15.341958
7818 13:45:15.345049 RX Vref 24 -> 127, step: 1
7819 13:45:15.345145
7820 13:45:15.348697 RX Delay 19 -> 252, step: 4
7821 13:45:15.348788
7822 13:45:15.351506 Set Vref, RX VrefLevel [Byte0]: 24
7823 13:45:15.355183 [Byte1]: 24
7824 13:45:15.355265
7825 13:45:15.358243 Set Vref, RX VrefLevel [Byte0]: 25
7826 13:45:15.361283 [Byte1]: 25
7827 13:45:15.361391
7828 13:45:15.364756 Set Vref, RX VrefLevel [Byte0]: 26
7829 13:45:15.368316 [Byte1]: 26
7830 13:45:15.372064
7831 13:45:15.372159 Set Vref, RX VrefLevel [Byte0]: 27
7832 13:45:15.375820 [Byte1]: 27
7833 13:45:15.379978
7834 13:45:15.380061 Set Vref, RX VrefLevel [Byte0]: 28
7835 13:45:15.382845 [Byte1]: 28
7836 13:45:15.387561
7837 13:45:15.387656 Set Vref, RX VrefLevel [Byte0]: 29
7838 13:45:15.390492 [Byte1]: 29
7839 13:45:15.394643
7840 13:45:15.394760 Set Vref, RX VrefLevel [Byte0]: 30
7841 13:45:15.398305 [Byte1]: 30
7842 13:45:15.402704
7843 13:45:15.402815 Set Vref, RX VrefLevel [Byte0]: 31
7844 13:45:15.406261 [Byte1]: 31
7845 13:45:15.410386
7846 13:45:15.410507 Set Vref, RX VrefLevel [Byte0]: 32
7847 13:45:15.413248 [Byte1]: 32
7848 13:45:15.417811
7849 13:45:15.417910 Set Vref, RX VrefLevel [Byte0]: 33
7850 13:45:15.421118 [Byte1]: 33
7851 13:45:15.425137
7852 13:45:15.425241 Set Vref, RX VrefLevel [Byte0]: 34
7853 13:45:15.428534 [Byte1]: 34
7854 13:45:15.432968
7855 13:45:15.433057 Set Vref, RX VrefLevel [Byte0]: 35
7856 13:45:15.436623 [Byte1]: 35
7857 13:45:15.440239
7858 13:45:15.440321 Set Vref, RX VrefLevel [Byte0]: 36
7859 13:45:15.443808 [Byte1]: 36
7860 13:45:15.448063
7861 13:45:15.448144 Set Vref, RX VrefLevel [Byte0]: 37
7862 13:45:15.451369 [Byte1]: 37
7863 13:45:15.455355
7864 13:45:15.455439 Set Vref, RX VrefLevel [Byte0]: 38
7865 13:45:15.458612 [Byte1]: 38
7866 13:45:15.463274
7867 13:45:15.463358 Set Vref, RX VrefLevel [Byte0]: 39
7868 13:45:15.466078 [Byte1]: 39
7869 13:45:15.470925
7870 13:45:15.471008 Set Vref, RX VrefLevel [Byte0]: 40
7871 13:45:15.473843 [Byte1]: 40
7872 13:45:15.478236
7873 13:45:15.478320 Set Vref, RX VrefLevel [Byte0]: 41
7874 13:45:15.481289 [Byte1]: 41
7875 13:45:15.485563
7876 13:45:15.485646 Set Vref, RX VrefLevel [Byte0]: 42
7877 13:45:15.489123 [Byte1]: 42
7878 13:45:15.493350
7879 13:45:15.493436 Set Vref, RX VrefLevel [Byte0]: 43
7880 13:45:15.496944 [Byte1]: 43
7881 13:45:15.501337
7882 13:45:15.501441 Set Vref, RX VrefLevel [Byte0]: 44
7883 13:45:15.504266 [Byte1]: 44
7884 13:45:15.508463
7885 13:45:15.508546 Set Vref, RX VrefLevel [Byte0]: 45
7886 13:45:15.511808 [Byte1]: 45
7887 13:45:15.516023
7888 13:45:15.516108 Set Vref, RX VrefLevel [Byte0]: 46
7889 13:45:15.519100 [Byte1]: 46
7890 13:45:15.523472
7891 13:45:15.523556 Set Vref, RX VrefLevel [Byte0]: 47
7892 13:45:15.526997 [Byte1]: 47
7893 13:45:15.531430
7894 13:45:15.531524 Set Vref, RX VrefLevel [Byte0]: 48
7895 13:45:15.534346 [Byte1]: 48
7896 13:45:15.538903
7897 13:45:15.538985 Set Vref, RX VrefLevel [Byte0]: 49
7898 13:45:15.542083 [Byte1]: 49
7899 13:45:15.546401
7900 13:45:15.546485 Set Vref, RX VrefLevel [Byte0]: 50
7901 13:45:15.549325 [Byte1]: 50
7902 13:45:15.553970
7903 13:45:15.554053 Set Vref, RX VrefLevel [Byte0]: 51
7904 13:45:15.556960 [Byte1]: 51
7905 13:45:15.561124
7906 13:45:15.561255 Set Vref, RX VrefLevel [Byte0]: 52
7907 13:45:15.564903 [Byte1]: 52
7908 13:45:15.569482
7909 13:45:15.569593 Set Vref, RX VrefLevel [Byte0]: 53
7910 13:45:15.572856 [Byte1]: 53
7911 13:45:15.576778
7912 13:45:15.576882 Set Vref, RX VrefLevel [Byte0]: 54
7913 13:45:15.579856 [Byte1]: 54
7914 13:45:15.584221
7915 13:45:15.584333 Set Vref, RX VrefLevel [Byte0]: 55
7916 13:45:15.587211 [Byte1]: 55
7917 13:45:15.591598
7918 13:45:15.591711 Set Vref, RX VrefLevel [Byte0]: 56
7919 13:45:15.595173 [Byte1]: 56
7920 13:45:15.599292
7921 13:45:15.599404 Set Vref, RX VrefLevel [Byte0]: 57
7922 13:45:15.602928 [Byte1]: 57
7923 13:45:15.607371
7924 13:45:15.607488 Set Vref, RX VrefLevel [Byte0]: 58
7925 13:45:15.610281 [Byte1]: 58
7926 13:45:15.614653
7927 13:45:15.614775 Set Vref, RX VrefLevel [Byte0]: 59
7928 13:45:15.618140 [Byte1]: 59
7929 13:45:15.622300
7930 13:45:15.622385 Set Vref, RX VrefLevel [Byte0]: 60
7931 13:45:15.625524 [Byte1]: 60
7932 13:45:15.629622
7933 13:45:15.629725 Set Vref, RX VrefLevel [Byte0]: 61
7934 13:45:15.633095 [Byte1]: 61
7935 13:45:15.637628
7936 13:45:15.637734 Set Vref, RX VrefLevel [Byte0]: 62
7937 13:45:15.640578 [Byte1]: 62
7938 13:45:15.644926
7939 13:45:15.645008 Set Vref, RX VrefLevel [Byte0]: 63
7940 13:45:15.648388 [Byte1]: 63
7941 13:45:15.652470
7942 13:45:15.652560 Set Vref, RX VrefLevel [Byte0]: 64
7943 13:45:15.656040 [Byte1]: 64
7944 13:45:15.660220
7945 13:45:15.660337 Set Vref, RX VrefLevel [Byte0]: 65
7946 13:45:15.663241 [Byte1]: 65
7947 13:45:15.667444
7948 13:45:15.667563 Set Vref, RX VrefLevel [Byte0]: 66
7949 13:45:15.671115 [Byte1]: 66
7950 13:45:15.675390
7951 13:45:15.675473 Set Vref, RX VrefLevel [Byte0]: 67
7952 13:45:15.678333 [Byte1]: 67
7953 13:45:15.682517
7954 13:45:15.682592 Set Vref, RX VrefLevel [Byte0]: 68
7955 13:45:15.686037 [Byte1]: 68
7956 13:45:15.690431
7957 13:45:15.690505 Set Vref, RX VrefLevel [Byte0]: 69
7958 13:45:15.693439 [Byte1]: 69
7959 13:45:15.697998
7960 13:45:15.698116 Set Vref, RX VrefLevel [Byte0]: 70
7961 13:45:15.700874 [Byte1]: 70
7962 13:45:15.705469
7963 13:45:15.705551 Set Vref, RX VrefLevel [Byte0]: 71
7964 13:45:15.708372 [Byte1]: 71
7965 13:45:15.712735
7966 13:45:15.712813 Set Vref, RX VrefLevel [Byte0]: 72
7967 13:45:15.716309 [Byte1]: 72
7968 13:45:15.720634
7969 13:45:15.720707 Set Vref, RX VrefLevel [Byte0]: 73
7970 13:45:15.724068 [Byte1]: 73
7971 13:45:15.728303
7972 13:45:15.728410 Set Vref, RX VrefLevel [Byte0]: 74
7973 13:45:15.731293 [Byte1]: 74
7974 13:45:15.735393
7975 13:45:15.735470 Set Vref, RX VrefLevel [Byte0]: 75
7976 13:45:15.738769 [Byte1]: 75
7977 13:45:15.743161
7978 13:45:15.743237 Final RX Vref Byte 0 = 57 to rank0
7979 13:45:15.746749 Final RX Vref Byte 1 = 57 to rank0
7980 13:45:15.750326 Final RX Vref Byte 0 = 57 to rank1
7981 13:45:15.753298 Final RX Vref Byte 1 = 57 to rank1==
7982 13:45:15.756751 Dram Type= 6, Freq= 0, CH_0, rank 0
7983 13:45:15.760337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 13:45:15.763145 ==
7985 13:45:15.763247 DQS Delay:
7986 13:45:15.763337 DQS0 = 0, DQS1 = 0
7987 13:45:15.766553 DQM Delay:
7988 13:45:15.766662 DQM0 = 133, DQM1 = 127
7989 13:45:15.770268 DQ Delay:
7990 13:45:15.773052 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7991 13:45:15.776604 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =140
7992 13:45:15.780111 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7993 13:45:15.783709 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7994 13:45:15.783790
7995 13:45:15.783854
7996 13:45:15.783912
7997 13:45:15.786567 [DramC_TX_OE_Calibration] TA2
7998 13:45:15.790150 Original DQ_B0 (3 6) =30, OEN = 27
7999 13:45:15.793141 Original DQ_B1 (3 6) =30, OEN = 27
8000 13:45:15.796758 24, 0x0, End_B0=24 End_B1=24
8001 13:45:15.796867 25, 0x0, End_B0=25 End_B1=25
8002 13:45:15.799901 26, 0x0, End_B0=26 End_B1=26
8003 13:45:15.803240 27, 0x0, End_B0=27 End_B1=27
8004 13:45:15.806572 28, 0x0, End_B0=28 End_B1=28
8005 13:45:15.806650 29, 0x0, End_B0=29 End_B1=29
8006 13:45:15.809680 30, 0x0, End_B0=30 End_B1=30
8007 13:45:15.813329 31, 0x4545, End_B0=30 End_B1=30
8008 13:45:15.816215 Byte0 end_step=30 best_step=27
8009 13:45:15.820091 Byte1 end_step=30 best_step=27
8010 13:45:15.822597 Byte0 TX OE(2T, 0.5T) = (3, 3)
8011 13:45:15.826222 Byte1 TX OE(2T, 0.5T) = (3, 3)
8012 13:45:15.826304
8013 13:45:15.826369
8014 13:45:15.832827 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
8015 13:45:15.836318 CH0 RK0: MR19=303, MR18=241F
8016 13:45:15.842659 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
8017 13:45:15.842741
8018 13:45:15.846231 ----->DramcWriteLeveling(PI) begin...
8019 13:45:15.846314 ==
8020 13:45:15.849808 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 13:45:15.852631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 13:45:15.852715 ==
8023 13:45:15.856224 Write leveling (Byte 0): 35 => 35
8024 13:45:15.859908 Write leveling (Byte 1): 28 => 28
8025 13:45:15.862912 DramcWriteLeveling(PI) end<-----
8026 13:45:15.862996
8027 13:45:15.863061 ==
8028 13:45:15.866547 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 13:45:15.869325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 13:45:15.869408 ==
8031 13:45:15.872937 [Gating] SW mode calibration
8032 13:45:15.879631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8033 13:45:15.886026 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8034 13:45:15.889694 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8035 13:45:15.892568 1 4 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8036 13:45:15.899670 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8037 13:45:15.902564 1 4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8038 13:45:15.906295 1 4 16 | B1->B0 | 3131 3737 | 1 0 | (1 1) (1 1)
8039 13:45:15.912922 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8040 13:45:15.915817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 13:45:15.919320 1 4 28 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
8042 13:45:15.926229 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
8043 13:45:15.929356 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8044 13:45:15.932289 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8045 13:45:15.939209 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8046 13:45:15.942430 1 5 16 | B1->B0 | 2d2d 2c2b | 0 1 | (0 1) (1 0)
8047 13:45:15.946216 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8048 13:45:15.952592 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8049 13:45:15.955972 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8050 13:45:15.959578 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8051 13:45:15.965827 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8052 13:45:15.969401 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8053 13:45:15.972955 1 6 12 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
8054 13:45:15.975864 1 6 16 | B1->B0 | 3939 4545 | 1 1 | (0 0) (0 0)
8055 13:45:15.982459 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 13:45:15.986143 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8057 13:45:15.989649 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 13:45:15.995816 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 13:45:15.998959 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 13:45:16.002825 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8061 13:45:16.009248 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8062 13:45:16.012226 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8063 13:45:16.015898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 13:45:16.022378 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:45:16.025934 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:45:16.028795 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 13:45:16.035374 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 13:45:16.038889 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 13:45:16.042344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:45:16.048694 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:45:16.052206 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 13:45:16.055739 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 13:45:16.061941 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 13:45:16.065727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 13:45:16.068948 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:45:16.075645 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8077 13:45:16.078529 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8078 13:45:16.082099 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8079 13:45:16.088743 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 13:45:16.088874 Total UI for P1: 0, mck2ui 16
8081 13:45:16.095500 best dqsien dly found for B0: ( 1, 9, 12)
8082 13:45:16.095640 Total UI for P1: 0, mck2ui 16
8083 13:45:16.101910 best dqsien dly found for B1: ( 1, 9, 14)
8084 13:45:16.105241 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8085 13:45:16.108787 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8086 13:45:16.108884
8087 13:45:16.112428 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8088 13:45:16.115358 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8089 13:45:16.118632 [Gating] SW calibration Done
8090 13:45:16.118715 ==
8091 13:45:16.122291 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 13:45:16.125182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 13:45:16.125264 ==
8094 13:45:16.128968 RX Vref Scan: 0
8095 13:45:16.129054
8096 13:45:16.129141 RX Vref 0 -> 0, step: 1
8097 13:45:16.129222
8098 13:45:16.131969 RX Delay 0 -> 252, step: 8
8099 13:45:16.135396 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8100 13:45:16.142394 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8101 13:45:16.145168 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8102 13:45:16.149110 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8103 13:45:16.151642 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8104 13:45:16.155230 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8105 13:45:16.159033 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8106 13:45:16.165503 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8107 13:45:16.168544 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8108 13:45:16.171906 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8109 13:45:16.175453 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8110 13:45:16.182094 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8111 13:45:16.185425 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8112 13:45:16.188713 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8113 13:45:16.192011 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8114 13:45:16.194919 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8115 13:45:16.198459 ==
8116 13:45:16.198545 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 13:45:16.204879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 13:45:16.204967 ==
8119 13:45:16.205053 DQS Delay:
8120 13:45:16.208601 DQS0 = 0, DQS1 = 0
8121 13:45:16.208686 DQM Delay:
8122 13:45:16.211540 DQM0 = 136, DQM1 = 128
8123 13:45:16.211625 DQ Delay:
8124 13:45:16.215170 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8125 13:45:16.218185 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8126 13:45:16.221808 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8127 13:45:16.225194 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8128 13:45:16.225279
8129 13:45:16.225342
8130 13:45:16.225400 ==
8131 13:45:16.228512 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 13:45:16.234797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 13:45:16.234879 ==
8134 13:45:16.234944
8135 13:45:16.235003
8136 13:45:16.235059 TX Vref Scan disable
8137 13:45:16.238169 == TX Byte 0 ==
8138 13:45:16.241940 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8139 13:45:16.244842 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8140 13:45:16.248313 == TX Byte 1 ==
8141 13:45:16.251798 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8142 13:45:16.255483 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8143 13:45:16.258228 ==
8144 13:45:16.261563 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 13:45:16.265006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 13:45:16.265093 ==
8147 13:45:16.278080
8148 13:45:16.281081 TX Vref early break, caculate TX vref
8149 13:45:16.284746 TX Vref=16, minBit 1, minWin=22, winSum=384
8150 13:45:16.288217 TX Vref=18, minBit 1, minWin=23, winSum=394
8151 13:45:16.291726 TX Vref=20, minBit 1, minWin=23, winSum=404
8152 13:45:16.294447 TX Vref=22, minBit 0, minWin=24, winSum=408
8153 13:45:16.297769 TX Vref=24, minBit 1, minWin=25, winSum=421
8154 13:45:16.304692 TX Vref=26, minBit 1, minWin=25, winSum=426
8155 13:45:16.308201 TX Vref=28, minBit 7, minWin=25, winSum=425
8156 13:45:16.311164 TX Vref=30, minBit 3, minWin=24, winSum=413
8157 13:45:16.314859 TX Vref=32, minBit 0, minWin=25, winSum=412
8158 13:45:16.317778 TX Vref=34, minBit 1, minWin=24, winSum=403
8159 13:45:16.324096 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8160 13:45:16.324178
8161 13:45:16.327883 Final TX Range 0 Vref 26
8162 13:45:16.327989
8163 13:45:16.328080 ==
8164 13:45:16.330677 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 13:45:16.334292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 13:45:16.334387 ==
8167 13:45:16.334465
8168 13:45:16.334603
8169 13:45:16.337581 TX Vref Scan disable
8170 13:45:16.344436 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8171 13:45:16.344520 == TX Byte 0 ==
8172 13:45:16.347784 u2DelayCellOfst[0]=13 cells (4 PI)
8173 13:45:16.351017 u2DelayCellOfst[1]=13 cells (4 PI)
8174 13:45:16.353997 u2DelayCellOfst[2]=10 cells (3 PI)
8175 13:45:16.357467 u2DelayCellOfst[3]=6 cells (2 PI)
8176 13:45:16.360847 u2DelayCellOfst[4]=6 cells (2 PI)
8177 13:45:16.364093 u2DelayCellOfst[5]=0 cells (0 PI)
8178 13:45:16.367395 u2DelayCellOfst[6]=13 cells (4 PI)
8179 13:45:16.370535 u2DelayCellOfst[7]=17 cells (5 PI)
8180 13:45:16.374142 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8181 13:45:16.378027 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8182 13:45:16.380846 == TX Byte 1 ==
8183 13:45:16.384457 u2DelayCellOfst[8]=0 cells (0 PI)
8184 13:45:16.384538 u2DelayCellOfst[9]=0 cells (0 PI)
8185 13:45:16.387259 u2DelayCellOfst[10]=6 cells (2 PI)
8186 13:45:16.390871 u2DelayCellOfst[11]=3 cells (1 PI)
8187 13:45:16.394413 u2DelayCellOfst[12]=10 cells (3 PI)
8188 13:45:16.397304 u2DelayCellOfst[13]=10 cells (3 PI)
8189 13:45:16.400903 u2DelayCellOfst[14]=13 cells (4 PI)
8190 13:45:16.404316 u2DelayCellOfst[15]=10 cells (3 PI)
8191 13:45:16.407063 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8192 13:45:16.414162 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8193 13:45:16.414245 DramC Write-DBI on
8194 13:45:16.414310 ==
8195 13:45:16.417144 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 13:45:16.420788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 13:45:16.424159 ==
8198 13:45:16.424239
8199 13:45:16.424304
8200 13:45:16.424402 TX Vref Scan disable
8201 13:45:16.427577 == TX Byte 0 ==
8202 13:45:16.431184 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8203 13:45:16.434091 == TX Byte 1 ==
8204 13:45:16.437815 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8205 13:45:16.440793 DramC Write-DBI off
8206 13:45:16.440879
8207 13:45:16.440945 [DATLAT]
8208 13:45:16.441005 Freq=1600, CH0 RK1
8209 13:45:16.441064
8210 13:45:16.443825 DATLAT Default: 0xf
8211 13:45:16.443934 0, 0xFFFF, sum = 0
8212 13:45:16.447635 1, 0xFFFF, sum = 0
8213 13:45:16.450483 2, 0xFFFF, sum = 0
8214 13:45:16.450596 3, 0xFFFF, sum = 0
8215 13:45:16.454201 4, 0xFFFF, sum = 0
8216 13:45:16.454285 5, 0xFFFF, sum = 0
8217 13:45:16.457904 6, 0xFFFF, sum = 0
8218 13:45:16.457988 7, 0xFFFF, sum = 0
8219 13:45:16.460653 8, 0xFFFF, sum = 0
8220 13:45:16.460737 9, 0xFFFF, sum = 0
8221 13:45:16.464362 10, 0xFFFF, sum = 0
8222 13:45:16.464447 11, 0xFFFF, sum = 0
8223 13:45:16.467417 12, 0xFFFF, sum = 0
8224 13:45:16.467525 13, 0xFFFF, sum = 0
8225 13:45:16.470816 14, 0x0, sum = 1
8226 13:45:16.470899 15, 0x0, sum = 2
8227 13:45:16.473753 16, 0x0, sum = 3
8228 13:45:16.473867 17, 0x0, sum = 4
8229 13:45:16.477040 best_step = 15
8230 13:45:16.477123
8231 13:45:16.477188 ==
8232 13:45:16.480720 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 13:45:16.483880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 13:45:16.483989 ==
8235 13:45:16.487052 RX Vref Scan: 0
8236 13:45:16.487135
8237 13:45:16.487200 RX Vref 0 -> 0, step: 1
8238 13:45:16.487262
8239 13:45:16.490709 RX Delay 19 -> 252, step: 4
8240 13:45:16.494205 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8241 13:45:16.500686 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8242 13:45:16.503643 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8243 13:45:16.507248 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8244 13:45:16.510694 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8245 13:45:16.513632 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8246 13:45:16.520861 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8247 13:45:16.524202 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8248 13:45:16.527307 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8249 13:45:16.530528 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8250 13:45:16.533935 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8251 13:45:16.540239 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8252 13:45:16.544081 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8253 13:45:16.547135 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8254 13:45:16.550610 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8255 13:45:16.553618 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8256 13:45:16.557339 ==
8257 13:45:16.557421 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 13:45:16.563883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 13:45:16.563966 ==
8260 13:45:16.564030 DQS Delay:
8261 13:45:16.566854 DQS0 = 0, DQS1 = 0
8262 13:45:16.566935 DQM Delay:
8263 13:45:16.570445 DQM0 = 135, DQM1 = 126
8264 13:45:16.570526 DQ Delay:
8265 13:45:16.574197 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =134
8266 13:45:16.577017 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8267 13:45:16.580688 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =118
8268 13:45:16.584105 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =134
8269 13:45:16.584187
8270 13:45:16.584251
8271 13:45:16.584325
8272 13:45:16.587475 [DramC_TX_OE_Calibration] TA2
8273 13:45:16.590525 Original DQ_B0 (3 6) =30, OEN = 27
8274 13:45:16.594049 Original DQ_B1 (3 6) =30, OEN = 27
8275 13:45:16.597477 24, 0x0, End_B0=24 End_B1=24
8276 13:45:16.600658 25, 0x0, End_B0=25 End_B1=25
8277 13:45:16.600757 26, 0x0, End_B0=26 End_B1=26
8278 13:45:16.603603 27, 0x0, End_B0=27 End_B1=27
8279 13:45:16.606848 28, 0x0, End_B0=28 End_B1=28
8280 13:45:16.610501 29, 0x0, End_B0=29 End_B1=29
8281 13:45:16.610583 30, 0x0, End_B0=30 End_B1=30
8282 13:45:16.613533 31, 0x4545, End_B0=30 End_B1=30
8283 13:45:16.617090 Byte0 end_step=30 best_step=27
8284 13:45:16.620242 Byte1 end_step=30 best_step=27
8285 13:45:16.624004 Byte0 TX OE(2T, 0.5T) = (3, 3)
8286 13:45:16.626698 Byte1 TX OE(2T, 0.5T) = (3, 3)
8287 13:45:16.626780
8288 13:45:16.626844
8289 13:45:16.633979 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8290 13:45:16.637242 CH0 RK1: MR19=303, MR18=210A
8291 13:45:16.643675 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8292 13:45:16.647034 [RxdqsGatingPostProcess] freq 1600
8293 13:45:16.650232 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8294 13:45:16.653955 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 13:45:16.656931 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 13:45:16.660443 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 13:45:16.663467 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 13:45:16.667132 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 13:45:16.670114 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 13:45:16.673704 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 13:45:16.677312 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 13:45:16.680060 Pre-setting of DQS Precalculation
8303 13:45:16.683574 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8304 13:45:16.683655 ==
8305 13:45:16.687217 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 13:45:16.690126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 13:45:16.693474 ==
8308 13:45:16.696527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 13:45:16.700148 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 13:45:16.706550 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 13:45:16.713580 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 13:45:16.720472 [CA 0] Center 42 (13~72) winsize 60
8313 13:45:16.723924 [CA 1] Center 42 (13~72) winsize 60
8314 13:45:16.727456 [CA 2] Center 39 (10~68) winsize 59
8315 13:45:16.730837 [CA 3] Center 39 (10~68) winsize 59
8316 13:45:16.734124 [CA 4] Center 38 (9~68) winsize 60
8317 13:45:16.737211 [CA 5] Center 37 (8~67) winsize 60
8318 13:45:16.737292
8319 13:45:16.740468 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8320 13:45:16.740549
8321 13:45:16.743790 [CATrainingPosCal] consider 1 rank data
8322 13:45:16.747418 u2DelayCellTimex100 = 285/100 ps
8323 13:45:16.750724 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8324 13:45:16.757078 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8325 13:45:16.760350 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8326 13:45:16.763584 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8327 13:45:16.767030 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8328 13:45:16.770954 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8329 13:45:16.771037
8330 13:45:16.774431 CA PerBit enable=1, Macro0, CA PI delay=37
8331 13:45:16.774513
8332 13:45:16.777256 [CBTSetCACLKResult] CA Dly = 37
8333 13:45:16.780787 CS Dly: 10 (0~41)
8334 13:45:16.784251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 13:45:16.787200 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 13:45:16.787281 ==
8337 13:45:16.790922 Dram Type= 6, Freq= 0, CH_1, rank 1
8338 13:45:16.793751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 13:45:16.797244 ==
8340 13:45:16.800611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 13:45:16.804248 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 13:45:16.810909 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 13:45:16.813627 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 13:45:16.823894 [CA 0] Center 42 (12~72) winsize 61
8345 13:45:16.827527 [CA 1] Center 42 (12~72) winsize 61
8346 13:45:16.830508 [CA 2] Center 38 (9~68) winsize 60
8347 13:45:16.834038 [CA 3] Center 38 (8~68) winsize 61
8348 13:45:16.837627 [CA 4] Center 38 (9~68) winsize 60
8349 13:45:16.840563 [CA 5] Center 37 (7~67) winsize 61
8350 13:45:16.840643
8351 13:45:16.844111 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 13:45:16.844217
8353 13:45:16.847469 [CATrainingPosCal] consider 2 rank data
8354 13:45:16.850675 u2DelayCellTimex100 = 285/100 ps
8355 13:45:16.853888 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8356 13:45:16.860597 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8357 13:45:16.863982 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8358 13:45:16.867359 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8359 13:45:16.870665 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8360 13:45:16.873996 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8361 13:45:16.874079
8362 13:45:16.876744 CA PerBit enable=1, Macro0, CA PI delay=37
8363 13:45:16.876826
8364 13:45:16.880546 [CBTSetCACLKResult] CA Dly = 37
8365 13:45:16.883922 CS Dly: 11 (0~44)
8366 13:45:16.887432 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 13:45:16.890295 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 13:45:16.890376
8369 13:45:16.893925 ----->DramcWriteLeveling(PI) begin...
8370 13:45:16.894008 ==
8371 13:45:16.896820 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 13:45:16.903823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 13:45:16.903967 ==
8374 13:45:16.907345 Write leveling (Byte 0): 25 => 25
8375 13:45:16.907427 Write leveling (Byte 1): 27 => 27
8376 13:45:16.910307 DramcWriteLeveling(PI) end<-----
8377 13:45:16.910388
8378 13:45:16.913942 ==
8379 13:45:16.914024 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 13:45:16.920184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 13:45:16.920267 ==
8382 13:45:16.923905 [Gating] SW mode calibration
8383 13:45:16.929989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8384 13:45:16.933581 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8385 13:45:16.940100 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 13:45:16.943166 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 13:45:16.946879 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8388 13:45:16.953462 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8389 13:45:16.956302 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 13:45:16.960101 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 13:45:16.966695 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 13:45:16.970130 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 13:45:16.973108 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 13:45:16.979958 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 13:45:16.982953 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
8396 13:45:16.986183 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8397 13:45:16.992933 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 13:45:16.996606 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 13:45:16.999535 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 13:45:17.006403 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 13:45:17.009945 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 13:45:17.013386 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 13:45:17.020001 1 6 8 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
8404 13:45:17.022852 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 13:45:17.026344 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 13:45:17.033271 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 13:45:17.035882 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 13:45:17.039630 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 13:45:17.043159 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 13:45:17.049760 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 13:45:17.052626 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8412 13:45:17.056214 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 13:45:17.062723 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8414 13:45:17.066407 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 13:45:17.069951 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 13:45:17.076137 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:45:17.079786 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:45:17.083232 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:45:17.089828 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 13:45:17.092572 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:45:17.096257 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:45:17.102384 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:45:17.105920 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:45:17.109278 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 13:45:17.116130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 13:45:17.119402 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:45:17.122937 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 13:45:17.129242 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 13:45:17.132715 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 13:45:17.136302 Total UI for P1: 0, mck2ui 16
8431 13:45:17.139028 best dqsien dly found for B0: ( 1, 9, 10)
8432 13:45:17.142573 Total UI for P1: 0, mck2ui 16
8433 13:45:17.145863 best dqsien dly found for B1: ( 1, 9, 10)
8434 13:45:17.149323 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8435 13:45:17.152275 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8436 13:45:17.152392
8437 13:45:17.155853 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 13:45:17.158811 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8439 13:45:17.162477 [Gating] SW calibration Done
8440 13:45:17.162557 ==
8441 13:45:17.165451 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 13:45:17.172072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 13:45:17.172154 ==
8444 13:45:17.172218 RX Vref Scan: 0
8445 13:45:17.172277
8446 13:45:17.175674 RX Vref 0 -> 0, step: 1
8447 13:45:17.175755
8448 13:45:17.179224 RX Delay 0 -> 252, step: 8
8449 13:45:17.181992 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8450 13:45:17.185853 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8451 13:45:17.188676 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8452 13:45:17.192261 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8453 13:45:17.198612 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8454 13:45:17.202261 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8455 13:45:17.205054 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8456 13:45:17.208491 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8457 13:45:17.212093 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8458 13:45:17.215593 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8459 13:45:17.222328 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8460 13:45:17.225197 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8461 13:45:17.228471 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8462 13:45:17.231798 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8463 13:45:17.238770 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8464 13:45:17.241969 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8465 13:45:17.242051 ==
8466 13:45:17.245212 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 13:45:17.248218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 13:45:17.248299 ==
8469 13:45:17.251571 DQS Delay:
8470 13:45:17.251652 DQS0 = 0, DQS1 = 0
8471 13:45:17.251716 DQM Delay:
8472 13:45:17.255065 DQM0 = 137, DQM1 = 133
8473 13:45:17.255145 DQ Delay:
8474 13:45:17.258352 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8475 13:45:17.261986 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8476 13:45:17.264999 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8477 13:45:17.271699 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8478 13:45:17.271795
8479 13:45:17.271861
8480 13:45:17.271919 ==
8481 13:45:17.275316 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 13:45:17.278162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 13:45:17.278269 ==
8484 13:45:17.278336
8485 13:45:17.278395
8486 13:45:17.282104 TX Vref Scan disable
8487 13:45:17.282201 == TX Byte 0 ==
8488 13:45:17.288328 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8489 13:45:17.291921 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8490 13:45:17.292010 == TX Byte 1 ==
8491 13:45:17.298601 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8492 13:45:17.301484 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8493 13:45:17.301575 ==
8494 13:45:17.305121 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 13:45:17.307959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 13:45:17.308065 ==
8497 13:45:17.321827
8498 13:45:17.324716 TX Vref early break, caculate TX vref
8499 13:45:17.328342 TX Vref=16, minBit 1, minWin=22, winSum=379
8500 13:45:17.332152 TX Vref=18, minBit 1, minWin=23, winSum=387
8501 13:45:17.335254 TX Vref=20, minBit 0, minWin=24, winSum=395
8502 13:45:17.338735 TX Vref=22, minBit 1, minWin=24, winSum=404
8503 13:45:17.342336 TX Vref=24, minBit 0, minWin=24, winSum=412
8504 13:45:17.349049 TX Vref=26, minBit 1, minWin=25, winSum=425
8505 13:45:17.352007 TX Vref=28, minBit 2, minWin=25, winSum=429
8506 13:45:17.355663 TX Vref=30, minBit 0, minWin=24, winSum=420
8507 13:45:17.359263 TX Vref=32, minBit 6, minWin=24, winSum=417
8508 13:45:17.361986 TX Vref=34, minBit 0, minWin=24, winSum=404
8509 13:45:17.368567 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 28
8510 13:45:17.369038
8511 13:45:17.372045 Final TX Range 0 Vref 28
8512 13:45:17.372508
8513 13:45:17.372957 ==
8514 13:45:17.375422 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 13:45:17.378393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 13:45:17.378756 ==
8517 13:45:17.379042
8518 13:45:17.379305
8519 13:45:17.382258 TX Vref Scan disable
8520 13:45:17.388283 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8521 13:45:17.388718 == TX Byte 0 ==
8522 13:45:17.391521 u2DelayCellOfst[0]=17 cells (5 PI)
8523 13:45:17.395048 u2DelayCellOfst[1]=10 cells (3 PI)
8524 13:45:17.398431 u2DelayCellOfst[2]=0 cells (0 PI)
8525 13:45:17.401820 u2DelayCellOfst[3]=6 cells (2 PI)
8526 13:45:17.405355 u2DelayCellOfst[4]=6 cells (2 PI)
8527 13:45:17.408273 u2DelayCellOfst[5]=17 cells (5 PI)
8528 13:45:17.408937 u2DelayCellOfst[6]=17 cells (5 PI)
8529 13:45:17.411808 u2DelayCellOfst[7]=3 cells (1 PI)
8530 13:45:17.418389 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8531 13:45:17.421695 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8532 13:45:17.422049 == TX Byte 1 ==
8533 13:45:17.425506 u2DelayCellOfst[8]=0 cells (0 PI)
8534 13:45:17.428445 u2DelayCellOfst[9]=3 cells (1 PI)
8535 13:45:17.432465 u2DelayCellOfst[10]=13 cells (4 PI)
8536 13:45:17.435502 u2DelayCellOfst[11]=3 cells (1 PI)
8537 13:45:17.439082 u2DelayCellOfst[12]=17 cells (5 PI)
8538 13:45:17.441862 u2DelayCellOfst[13]=17 cells (5 PI)
8539 13:45:17.445347 u2DelayCellOfst[14]=17 cells (5 PI)
8540 13:45:17.448815 u2DelayCellOfst[15]=17 cells (5 PI)
8541 13:45:17.451699 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8542 13:45:17.455528 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8543 13:45:17.458501 DramC Write-DBI on
8544 13:45:17.459006 ==
8545 13:45:17.462177 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 13:45:17.465602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 13:45:17.466022 ==
8548 13:45:17.466428
8549 13:45:17.466819
8550 13:45:17.468452 TX Vref Scan disable
8551 13:45:17.472024 == TX Byte 0 ==
8552 13:45:17.475260 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8553 13:45:17.478586 == TX Byte 1 ==
8554 13:45:17.482023 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8555 13:45:17.482552 DramC Write-DBI off
8556 13:45:17.482899
8557 13:45:17.485184 [DATLAT]
8558 13:45:17.485656 Freq=1600, CH1 RK0
8559 13:45:17.486045
8560 13:45:17.488641 DATLAT Default: 0xf
8561 13:45:17.489151 0, 0xFFFF, sum = 0
8562 13:45:17.491505 1, 0xFFFF, sum = 0
8563 13:45:17.491913 2, 0xFFFF, sum = 0
8564 13:45:17.495105 3, 0xFFFF, sum = 0
8565 13:45:17.495512 4, 0xFFFF, sum = 0
8566 13:45:17.498715 5, 0xFFFF, sum = 0
8567 13:45:17.499123 6, 0xFFFF, sum = 0
8568 13:45:17.502135 7, 0xFFFF, sum = 0
8569 13:45:17.502659 8, 0xFFFF, sum = 0
8570 13:45:17.505286 9, 0xFFFF, sum = 0
8571 13:45:17.505694 10, 0xFFFF, sum = 0
8572 13:45:17.508514 11, 0xFFFF, sum = 0
8573 13:45:17.511813 12, 0xFFFF, sum = 0
8574 13:45:17.512169 13, 0xFFFF, sum = 0
8575 13:45:17.515292 14, 0x0, sum = 1
8576 13:45:17.515647 15, 0x0, sum = 2
8577 13:45:17.515932 16, 0x0, sum = 3
8578 13:45:17.518886 17, 0x0, sum = 4
8579 13:45:17.519515 best_step = 15
8580 13:45:17.519911
8581 13:45:17.521372 ==
8582 13:45:17.521745 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 13:45:17.528370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 13:45:17.528854 ==
8585 13:45:17.529233 RX Vref Scan: 1
8586 13:45:17.529592
8587 13:45:17.531849 Set Vref Range= 24 -> 127
8588 13:45:17.532195
8589 13:45:17.534836 RX Vref 24 -> 127, step: 1
8590 13:45:17.535188
8591 13:45:17.538414 RX Delay 27 -> 252, step: 4
8592 13:45:17.538768
8593 13:45:17.541424 Set Vref, RX VrefLevel [Byte0]: 24
8594 13:45:17.545099 [Byte1]: 24
8595 13:45:17.545449
8596 13:45:17.548108 Set Vref, RX VrefLevel [Byte0]: 25
8597 13:45:17.551789 [Byte1]: 25
8598 13:45:17.552240
8599 13:45:17.554848 Set Vref, RX VrefLevel [Byte0]: 26
8600 13:45:17.558134 [Byte1]: 26
8601 13:45:17.562206
8602 13:45:17.562714 Set Vref, RX VrefLevel [Byte0]: 27
8603 13:45:17.564656 [Byte1]: 27
8604 13:45:17.569108
8605 13:45:17.569567 Set Vref, RX VrefLevel [Byte0]: 28
8606 13:45:17.572053 [Byte1]: 28
8607 13:45:17.576646
8608 13:45:17.577032 Set Vref, RX VrefLevel [Byte0]: 29
8609 13:45:17.580270 [Byte1]: 29
8610 13:45:17.584188
8611 13:45:17.584740 Set Vref, RX VrefLevel [Byte0]: 30
8612 13:45:17.587748 [Byte1]: 30
8613 13:45:17.591404
8614 13:45:17.591803 Set Vref, RX VrefLevel [Byte0]: 31
8615 13:45:17.594959 [Byte1]: 31
8616 13:45:17.598926
8617 13:45:17.599439 Set Vref, RX VrefLevel [Byte0]: 32
8618 13:45:17.602782 [Byte1]: 32
8619 13:45:17.606215
8620 13:45:17.606610 Set Vref, RX VrefLevel [Byte0]: 33
8621 13:45:17.609877 [Byte1]: 33
8622 13:45:17.614265
8623 13:45:17.614685 Set Vref, RX VrefLevel [Byte0]: 34
8624 13:45:17.617231 [Byte1]: 34
8625 13:45:17.621700
8626 13:45:17.622086 Set Vref, RX VrefLevel [Byte0]: 35
8627 13:45:17.624666 [Byte1]: 35
8628 13:45:17.628753
8629 13:45:17.629161 Set Vref, RX VrefLevel [Byte0]: 36
8630 13:45:17.632443 [Byte1]: 36
8631 13:45:17.636739
8632 13:45:17.637140 Set Vref, RX VrefLevel [Byte0]: 37
8633 13:45:17.639883 [Byte1]: 37
8634 13:45:17.644270
8635 13:45:17.644569 Set Vref, RX VrefLevel [Byte0]: 38
8636 13:45:17.647556 [Byte1]: 38
8637 13:45:17.651461
8638 13:45:17.651740 Set Vref, RX VrefLevel [Byte0]: 39
8639 13:45:17.655257 [Byte1]: 39
8640 13:45:17.659615
8641 13:45:17.660009 Set Vref, RX VrefLevel [Byte0]: 40
8642 13:45:17.662446 [Byte1]: 40
8643 13:45:17.666440
8644 13:45:17.666829 Set Vref, RX VrefLevel [Byte0]: 41
8645 13:45:17.670123 [Byte1]: 41
8646 13:45:17.674023
8647 13:45:17.674544 Set Vref, RX VrefLevel [Byte0]: 42
8648 13:45:17.677443 [Byte1]: 42
8649 13:45:17.681953
8650 13:45:17.682339 Set Vref, RX VrefLevel [Byte0]: 43
8651 13:45:17.685364 [Byte1]: 43
8652 13:45:17.690019
8653 13:45:17.690509 Set Vref, RX VrefLevel [Byte0]: 44
8654 13:45:17.693126 [Byte1]: 44
8655 13:45:17.697110
8656 13:45:17.697502 Set Vref, RX VrefLevel [Byte0]: 45
8657 13:45:17.699910 [Byte1]: 45
8658 13:45:17.704326
8659 13:45:17.704853 Set Vref, RX VrefLevel [Byte0]: 46
8660 13:45:17.708142 [Byte1]: 46
8661 13:45:17.712729
8662 13:45:17.713216 Set Vref, RX VrefLevel [Byte0]: 47
8663 13:45:17.715366 [Byte1]: 47
8664 13:45:17.719907
8665 13:45:17.720411 Set Vref, RX VrefLevel [Byte0]: 48
8666 13:45:17.722697 [Byte1]: 48
8667 13:45:17.727195
8668 13:45:17.727671 Set Vref, RX VrefLevel [Byte0]: 49
8669 13:45:17.730665 [Byte1]: 49
8670 13:45:17.735044
8671 13:45:17.735529 Set Vref, RX VrefLevel [Byte0]: 50
8672 13:45:17.737901 [Byte1]: 50
8673 13:45:17.742373
8674 13:45:17.742735 Set Vref, RX VrefLevel [Byte0]: 51
8675 13:45:17.745293 [Byte1]: 51
8676 13:45:17.750003
8677 13:45:17.750510 Set Vref, RX VrefLevel [Byte0]: 52
8678 13:45:17.753490 [Byte1]: 52
8679 13:45:17.757373
8680 13:45:17.757934 Set Vref, RX VrefLevel [Byte0]: 53
8681 13:45:17.760140 [Byte1]: 53
8682 13:45:17.764458
8683 13:45:17.764934 Set Vref, RX VrefLevel [Byte0]: 54
8684 13:45:17.768277 [Byte1]: 54
8685 13:45:17.772577
8686 13:45:17.772965 Set Vref, RX VrefLevel [Byte0]: 55
8687 13:45:17.775855 [Byte1]: 55
8688 13:45:17.779946
8689 13:45:17.780496 Set Vref, RX VrefLevel [Byte0]: 56
8690 13:45:17.782902 [Byte1]: 56
8691 13:45:17.787364
8692 13:45:17.787796 Set Vref, RX VrefLevel [Byte0]: 57
8693 13:45:17.790280 [Byte1]: 57
8694 13:45:17.794777
8695 13:45:17.795176 Set Vref, RX VrefLevel [Byte0]: 58
8696 13:45:17.798193 [Byte1]: 58
8697 13:45:17.802412
8698 13:45:17.802819 Set Vref, RX VrefLevel [Byte0]: 59
8699 13:45:17.805549 [Byte1]: 59
8700 13:45:17.809802
8701 13:45:17.810200 Set Vref, RX VrefLevel [Byte0]: 60
8702 13:45:17.813626 [Byte1]: 60
8703 13:45:17.817570
8704 13:45:17.817955 Set Vref, RX VrefLevel [Byte0]: 61
8705 13:45:17.820454 [Byte1]: 61
8706 13:45:17.824781
8707 13:45:17.825167 Set Vref, RX VrefLevel [Byte0]: 62
8708 13:45:17.828244 [Byte1]: 62
8709 13:45:17.832622
8710 13:45:17.833039 Set Vref, RX VrefLevel [Byte0]: 63
8711 13:45:17.835471 [Byte1]: 63
8712 13:45:17.839833
8713 13:45:17.840235 Set Vref, RX VrefLevel [Byte0]: 64
8714 13:45:17.843856 [Byte1]: 64
8715 13:45:17.847879
8716 13:45:17.848255 Set Vref, RX VrefLevel [Byte0]: 65
8717 13:45:17.850976 [Byte1]: 65
8718 13:45:17.855298
8719 13:45:17.855798 Set Vref, RX VrefLevel [Byte0]: 66
8720 13:45:17.858170 [Byte1]: 66
8721 13:45:17.862809
8722 13:45:17.863328 Set Vref, RX VrefLevel [Byte0]: 67
8723 13:45:17.865729 [Byte1]: 67
8724 13:45:17.869931
8725 13:45:17.870332 Set Vref, RX VrefLevel [Byte0]: 68
8726 13:45:17.873552 [Byte1]: 68
8727 13:45:17.877511
8728 13:45:17.877913 Set Vref, RX VrefLevel [Byte0]: 69
8729 13:45:17.881345 [Byte1]: 69
8730 13:45:17.885075
8731 13:45:17.885475 Set Vref, RX VrefLevel [Byte0]: 70
8732 13:45:17.888678 [Byte1]: 70
8733 13:45:17.892439
8734 13:45:17.892841 Set Vref, RX VrefLevel [Byte0]: 71
8735 13:45:17.896267 [Byte1]: 71
8736 13:45:17.899930
8737 13:45:17.900331 Set Vref, RX VrefLevel [Byte0]: 72
8738 13:45:17.903702 [Byte1]: 72
8739 13:45:17.908004
8740 13:45:17.908406 Set Vref, RX VrefLevel [Byte0]: 73
8741 13:45:17.910879 [Byte1]: 73
8742 13:45:17.915587
8743 13:45:17.915935 Set Vref, RX VrefLevel [Byte0]: 74
8744 13:45:17.918799 [Byte1]: 74
8745 13:45:17.922781
8746 13:45:17.923128 Set Vref, RX VrefLevel [Byte0]: 75
8747 13:45:17.925894 [Byte1]: 75
8748 13:45:17.930289
8749 13:45:17.930635 Set Vref, RX VrefLevel [Byte0]: 76
8750 13:45:17.933260 [Byte1]: 76
8751 13:45:17.937971
8752 13:45:17.938344 Final RX Vref Byte 0 = 57 to rank0
8753 13:45:17.941144 Final RX Vref Byte 1 = 55 to rank0
8754 13:45:17.944938 Final RX Vref Byte 0 = 57 to rank1
8755 13:45:17.947653 Final RX Vref Byte 1 = 55 to rank1==
8756 13:45:17.951065 Dram Type= 6, Freq= 0, CH_1, rank 0
8757 13:45:17.958077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 13:45:17.958450 ==
8759 13:45:17.958731 DQS Delay:
8760 13:45:17.959009 DQS0 = 0, DQS1 = 0
8761 13:45:17.961067 DQM Delay:
8762 13:45:17.961420 DQM0 = 134, DQM1 = 131
8763 13:45:17.964716 DQ Delay:
8764 13:45:17.967686 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8765 13:45:17.971415 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8766 13:45:17.974219 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8767 13:45:17.977622 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8768 13:45:17.978004
8769 13:45:17.978377
8770 13:45:17.978732
8771 13:45:17.981194 [DramC_TX_OE_Calibration] TA2
8772 13:45:17.984254 Original DQ_B0 (3 6) =30, OEN = 27
8773 13:45:17.988120 Original DQ_B1 (3 6) =30, OEN = 27
8774 13:45:17.990964 24, 0x0, End_B0=24 End_B1=24
8775 13:45:17.991333 25, 0x0, End_B0=25 End_B1=25
8776 13:45:17.993926 26, 0x0, End_B0=26 End_B1=26
8777 13:45:17.997709 27, 0x0, End_B0=27 End_B1=27
8778 13:45:18.000899 28, 0x0, End_B0=28 End_B1=28
8779 13:45:18.004458 29, 0x0, End_B0=29 End_B1=29
8780 13:45:18.004881 30, 0x0, End_B0=30 End_B1=30
8781 13:45:18.007398 31, 0x4141, End_B0=30 End_B1=30
8782 13:45:18.011110 Byte0 end_step=30 best_step=27
8783 13:45:18.013934 Byte1 end_step=30 best_step=27
8784 13:45:18.017738 Byte0 TX OE(2T, 0.5T) = (3, 3)
8785 13:45:18.020784 Byte1 TX OE(2T, 0.5T) = (3, 3)
8786 13:45:18.021146
8787 13:45:18.021512
8788 13:45:18.027432 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8789 13:45:18.031176 CH1 RK0: MR19=303, MR18=1927
8790 13:45:18.037392 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8791 13:45:18.037747
8792 13:45:18.041028 ----->DramcWriteLeveling(PI) begin...
8793 13:45:18.041383 ==
8794 13:45:18.044676 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 13:45:18.047424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 13:45:18.047800 ==
8797 13:45:18.050828 Write leveling (Byte 0): 25 => 25
8798 13:45:18.054142 Write leveling (Byte 1): 27 => 27
8799 13:45:18.057781 DramcWriteLeveling(PI) end<-----
8800 13:45:18.058141
8801 13:45:18.058506 ==
8802 13:45:18.061145 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 13:45:18.064417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 13:45:18.064962 ==
8805 13:45:18.067921 [Gating] SW mode calibration
8806 13:45:18.073994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8807 13:45:18.080988 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8808 13:45:18.084037 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 13:45:18.087392 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 13:45:18.094296 1 4 8 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
8811 13:45:18.097608 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8812 13:45:18.100571 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 13:45:18.107697 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 13:45:18.110352 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 13:45:18.114266 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 13:45:18.121005 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 13:45:18.124637 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8818 13:45:18.127861 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8819 13:45:18.134299 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8820 13:45:18.137337 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8821 13:45:18.141043 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 13:45:18.147627 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 13:45:18.150669 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 13:45:18.154434 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 13:45:18.160309 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 13:45:18.164151 1 6 8 | B1->B0 | 3d3d 2424 | 0 0 | (1 1) (0 0)
8827 13:45:18.167015 1 6 12 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
8828 13:45:18.173948 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 13:45:18.176703 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 13:45:18.180435 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 13:45:18.186920 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 13:45:18.189900 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 13:45:18.193098 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 13:45:18.199968 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8835 13:45:18.202863 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8836 13:45:18.206434 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8837 13:45:18.212942 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 13:45:18.216074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 13:45:18.219269 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 13:45:18.226445 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 13:45:18.229452 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 13:45:18.232788 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 13:45:18.239381 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 13:45:18.243119 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 13:45:18.246033 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 13:45:18.252215 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 13:45:18.256140 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 13:45:18.259194 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 13:45:18.265978 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8850 13:45:18.268955 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8851 13:45:18.272707 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8852 13:45:18.275702 Total UI for P1: 0, mck2ui 16
8853 13:45:18.279400 best dqsien dly found for B1: ( 1, 9, 6)
8854 13:45:18.282461 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8855 13:45:18.288865 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 13:45:18.292479 Total UI for P1: 0, mck2ui 16
8857 13:45:18.295582 best dqsien dly found for B0: ( 1, 9, 12)
8858 13:45:18.299151 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8859 13:45:18.302102 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8860 13:45:18.302317
8861 13:45:18.305521 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8862 13:45:18.309183 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8863 13:45:18.312255 [Gating] SW calibration Done
8864 13:45:18.312455 ==
8865 13:45:18.315850 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 13:45:18.318571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 13:45:18.318753 ==
8868 13:45:18.322296 RX Vref Scan: 0
8869 13:45:18.322475
8870 13:45:18.325329 RX Vref 0 -> 0, step: 1
8871 13:45:18.325527
8872 13:45:18.325708 RX Delay 0 -> 252, step: 8
8873 13:45:18.332144 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8874 13:45:18.335498 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8875 13:45:18.338894 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8876 13:45:18.342191 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8877 13:45:18.345291 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8878 13:45:18.352399 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8879 13:45:18.355381 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8880 13:45:18.358359 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8881 13:45:18.362383 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8882 13:45:18.365421 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8883 13:45:18.372033 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8884 13:45:18.375547 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8885 13:45:18.378450 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8886 13:45:18.382032 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8887 13:45:18.385678 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8888 13:45:18.392244 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8889 13:45:18.392457 ==
8890 13:45:18.395181 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 13:45:18.398720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 13:45:18.398891 ==
8893 13:45:18.399028 DQS Delay:
8894 13:45:18.402418 DQS0 = 0, DQS1 = 0
8895 13:45:18.402616 DQM Delay:
8896 13:45:18.405408 DQM0 = 136, DQM1 = 134
8897 13:45:18.405613 DQ Delay:
8898 13:45:18.408403 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8899 13:45:18.412129 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8900 13:45:18.415337 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8901 13:45:18.419247 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8902 13:45:18.419665
8903 13:45:18.420264
8904 13:45:18.422168 ==
8905 13:45:18.425527 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 13:45:18.428407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 13:45:18.428779 ==
8908 13:45:18.429080
8909 13:45:18.429393
8910 13:45:18.432106 TX Vref Scan disable
8911 13:45:18.432523 == TX Byte 0 ==
8912 13:45:18.435792 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8913 13:45:18.442196 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 13:45:18.442592 == TX Byte 1 ==
8915 13:45:18.445208 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8916 13:45:18.452003 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 13:45:18.452553 ==
8918 13:45:18.455640 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 13:45:18.458702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 13:45:18.459345 ==
8921 13:45:18.472438
8922 13:45:18.475618 TX Vref early break, caculate TX vref
8923 13:45:18.479153 TX Vref=16, minBit 0, minWin=23, winSum=384
8924 13:45:18.482229 TX Vref=18, minBit 0, minWin=23, winSum=391
8925 13:45:18.485675 TX Vref=20, minBit 0, minWin=24, winSum=401
8926 13:45:18.489559 TX Vref=22, minBit 0, minWin=25, winSum=414
8927 13:45:18.492497 TX Vref=24, minBit 0, minWin=25, winSum=419
8928 13:45:18.499104 TX Vref=26, minBit 0, minWin=25, winSum=425
8929 13:45:18.502581 TX Vref=28, minBit 0, minWin=25, winSum=426
8930 13:45:18.506084 TX Vref=30, minBit 0, minWin=24, winSum=421
8931 13:45:18.509160 TX Vref=32, minBit 6, minWin=24, winSum=411
8932 13:45:18.512313 TX Vref=34, minBit 0, minWin=24, winSum=408
8933 13:45:18.516141 TX Vref=36, minBit 0, minWin=24, winSum=402
8934 13:45:18.522414 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8935 13:45:18.522831
8936 13:45:18.526090 Final TX Range 0 Vref 28
8937 13:45:18.526637
8938 13:45:18.527087 ==
8939 13:45:18.529491 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 13:45:18.532944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 13:45:18.533488 ==
8942 13:45:18.533824
8943 13:45:18.534128
8944 13:45:18.535795 TX Vref Scan disable
8945 13:45:18.543071 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8946 13:45:18.543590 == TX Byte 0 ==
8947 13:45:18.546155 u2DelayCellOfst[0]=17 cells (5 PI)
8948 13:45:18.549833 u2DelayCellOfst[1]=10 cells (3 PI)
8949 13:45:18.552795 u2DelayCellOfst[2]=0 cells (0 PI)
8950 13:45:18.556490 u2DelayCellOfst[3]=6 cells (2 PI)
8951 13:45:18.559433 u2DelayCellOfst[4]=10 cells (3 PI)
8952 13:45:18.562997 u2DelayCellOfst[5]=17 cells (5 PI)
8953 13:45:18.566206 u2DelayCellOfst[6]=20 cells (6 PI)
8954 13:45:18.569003 u2DelayCellOfst[7]=6 cells (2 PI)
8955 13:45:18.572713 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8956 13:45:18.575810 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8957 13:45:18.579543 == TX Byte 1 ==
8958 13:45:18.582859 u2DelayCellOfst[8]=0 cells (0 PI)
8959 13:45:18.583273 u2DelayCellOfst[9]=6 cells (2 PI)
8960 13:45:18.586072 u2DelayCellOfst[10]=13 cells (4 PI)
8961 13:45:18.589427 u2DelayCellOfst[11]=6 cells (2 PI)
8962 13:45:18.592904 u2DelayCellOfst[12]=17 cells (5 PI)
8963 13:45:18.596444 u2DelayCellOfst[13]=17 cells (5 PI)
8964 13:45:18.599526 u2DelayCellOfst[14]=20 cells (6 PI)
8965 13:45:18.603141 u2DelayCellOfst[15]=20 cells (6 PI)
8966 13:45:18.606096 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8967 13:45:18.612469 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8968 13:45:18.612979 DramC Write-DBI on
8969 13:45:18.613439 ==
8970 13:45:18.615514 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 13:45:18.619244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 13:45:18.622149 ==
8973 13:45:18.622560
8974 13:45:18.622902
8975 13:45:18.623321 TX Vref Scan disable
8976 13:45:18.625759 == TX Byte 0 ==
8977 13:45:18.629279 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8978 13:45:18.632863 == TX Byte 1 ==
8979 13:45:18.635983 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8980 13:45:18.639566 DramC Write-DBI off
8981 13:45:18.640080
8982 13:45:18.640458 [DATLAT]
8983 13:45:18.640772 Freq=1600, CH1 RK1
8984 13:45:18.641072
8985 13:45:18.642936 DATLAT Default: 0xf
8986 13:45:18.643466 0, 0xFFFF, sum = 0
8987 13:45:18.646255 1, 0xFFFF, sum = 0
8988 13:45:18.648906 2, 0xFFFF, sum = 0
8989 13:45:18.649329 3, 0xFFFF, sum = 0
8990 13:45:18.652979 4, 0xFFFF, sum = 0
8991 13:45:18.653498 5, 0xFFFF, sum = 0
8992 13:45:18.656440 6, 0xFFFF, sum = 0
8993 13:45:18.656861 7, 0xFFFF, sum = 0
8994 13:45:18.659687 8, 0xFFFF, sum = 0
8995 13:45:18.660207 9, 0xFFFF, sum = 0
8996 13:45:18.662334 10, 0xFFFF, sum = 0
8997 13:45:18.662755 11, 0xFFFF, sum = 0
8998 13:45:18.666179 12, 0xFFFF, sum = 0
8999 13:45:18.666697 13, 0xFFFF, sum = 0
9000 13:45:18.669646 14, 0x0, sum = 1
9001 13:45:18.670065 15, 0x0, sum = 2
9002 13:45:18.672333 16, 0x0, sum = 3
9003 13:45:18.672794 17, 0x0, sum = 4
9004 13:45:18.676111 best_step = 15
9005 13:45:18.676673
9006 13:45:18.677003 ==
9007 13:45:18.678978 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 13:45:18.682655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 13:45:18.683068 ==
9010 13:45:18.685763 RX Vref Scan: 0
9011 13:45:18.686278
9012 13:45:18.686608 RX Vref 0 -> 0, step: 1
9013 13:45:18.686914
9014 13:45:18.689095 RX Delay 19 -> 252, step: 4
9015 13:45:18.692770 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9016 13:45:18.698637 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9017 13:45:18.702819 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
9018 13:45:18.706002 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9019 13:45:18.708703 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9020 13:45:18.712469 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9021 13:45:18.715345 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9022 13:45:18.723100 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9023 13:45:18.725762 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9024 13:45:18.729154 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9025 13:45:18.732620 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9026 13:45:18.735847 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9027 13:45:18.742589 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9028 13:45:18.745884 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9029 13:45:18.749092 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9030 13:45:18.752263 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9031 13:45:18.752932 ==
9032 13:45:18.755803 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 13:45:18.762217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 13:45:18.762728 ==
9035 13:45:18.763065 DQS Delay:
9036 13:45:18.765731 DQS0 = 0, DQS1 = 0
9037 13:45:18.766393 DQM Delay:
9038 13:45:18.766841 DQM0 = 134, DQM1 = 131
9039 13:45:18.769014 DQ Delay:
9040 13:45:18.771972 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =130
9041 13:45:18.775709 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9042 13:45:18.779653 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =124
9043 13:45:18.782347 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9044 13:45:18.782767
9045 13:45:18.783095
9046 13:45:18.783398
9047 13:45:18.785413 [DramC_TX_OE_Calibration] TA2
9048 13:45:18.789146 Original DQ_B0 (3 6) =30, OEN = 27
9049 13:45:18.792037 Original DQ_B1 (3 6) =30, OEN = 27
9050 13:45:18.795989 24, 0x0, End_B0=24 End_B1=24
9051 13:45:18.796564 25, 0x0, End_B0=25 End_B1=25
9052 13:45:18.798669 26, 0x0, End_B0=26 End_B1=26
9053 13:45:18.802720 27, 0x0, End_B0=27 End_B1=27
9054 13:45:18.805367 28, 0x0, End_B0=28 End_B1=28
9055 13:45:18.808824 29, 0x0, End_B0=29 End_B1=29
9056 13:45:18.809248 30, 0x0, End_B0=30 End_B1=30
9057 13:45:18.811973 31, 0x4141, End_B0=30 End_B1=30
9058 13:45:18.815522 Byte0 end_step=30 best_step=27
9059 13:45:18.818961 Byte1 end_step=30 best_step=27
9060 13:45:18.822755 Byte0 TX OE(2T, 0.5T) = (3, 3)
9061 13:45:18.825289 Byte1 TX OE(2T, 0.5T) = (3, 3)
9062 13:45:18.825823
9063 13:45:18.826264
9064 13:45:18.832444 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9065 13:45:18.835313 CH1 RK1: MR19=303, MR18=250A
9066 13:45:18.841984 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9067 13:45:18.845738 [RxdqsGatingPostProcess] freq 1600
9068 13:45:18.848791 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9069 13:45:18.852401 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 13:45:18.855612 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 13:45:18.858208 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 13:45:18.861842 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 13:45:18.865330 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 13:45:18.868445 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 13:45:18.871505 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 13:45:18.874978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 13:45:18.877973 Pre-setting of DQS Precalculation
9078 13:45:18.881667 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9079 13:45:18.887927 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9080 13:45:18.894793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 13:45:18.898191
9082 13:45:18.898296
9083 13:45:18.898388 [Calibration Summary] 3200 Mbps
9084 13:45:18.901050 CH 0, Rank 0
9085 13:45:18.901131 SW Impedance : PASS
9086 13:45:18.904486 DUTY Scan : NO K
9087 13:45:18.907775 ZQ Calibration : PASS
9088 13:45:18.907928 Jitter Meter : NO K
9089 13:45:18.911470 CBT Training : PASS
9090 13:45:18.914477 Write leveling : PASS
9091 13:45:18.914558 RX DQS gating : PASS
9092 13:45:18.917509 RX DQ/DQS(RDDQC) : PASS
9093 13:45:18.921190 TX DQ/DQS : PASS
9094 13:45:18.921272 RX DATLAT : PASS
9095 13:45:18.924846 RX DQ/DQS(Engine): PASS
9096 13:45:18.927723 TX OE : PASS
9097 13:45:18.927804 All Pass.
9098 13:45:18.927867
9099 13:45:18.927926 CH 0, Rank 1
9100 13:45:18.931156 SW Impedance : PASS
9101 13:45:18.934730 DUTY Scan : NO K
9102 13:45:18.934810 ZQ Calibration : PASS
9103 13:45:18.937411 Jitter Meter : NO K
9104 13:45:18.941233 CBT Training : PASS
9105 13:45:18.941313 Write leveling : PASS
9106 13:45:18.944289 RX DQS gating : PASS
9107 13:45:18.947416 RX DQ/DQS(RDDQC) : PASS
9108 13:45:18.947496 TX DQ/DQS : PASS
9109 13:45:18.951054 RX DATLAT : PASS
9110 13:45:18.954146 RX DQ/DQS(Engine): PASS
9111 13:45:18.954226 TX OE : PASS
9112 13:45:18.954289 All Pass.
9113 13:45:18.954348
9114 13:45:18.957878 CH 1, Rank 0
9115 13:45:18.960878 SW Impedance : PASS
9116 13:45:18.960957 DUTY Scan : NO K
9117 13:45:18.963964 ZQ Calibration : PASS
9118 13:45:18.964044 Jitter Meter : NO K
9119 13:45:18.967721 CBT Training : PASS
9120 13:45:18.970792 Write leveling : PASS
9121 13:45:18.970872 RX DQS gating : PASS
9122 13:45:18.973715 RX DQ/DQS(RDDQC) : PASS
9123 13:45:18.977491 TX DQ/DQS : PASS
9124 13:45:18.977572 RX DATLAT : PASS
9125 13:45:18.980936 RX DQ/DQS(Engine): PASS
9126 13:45:18.983954 TX OE : PASS
9127 13:45:18.984035 All Pass.
9128 13:45:18.984098
9129 13:45:18.984156 CH 1, Rank 1
9130 13:45:18.987511 SW Impedance : PASS
9131 13:45:18.990476 DUTY Scan : NO K
9132 13:45:18.990557 ZQ Calibration : PASS
9133 13:45:18.994040 Jitter Meter : NO K
9134 13:45:18.997533 CBT Training : PASS
9135 13:45:18.997613 Write leveling : PASS
9136 13:45:19.000362 RX DQS gating : PASS
9137 13:45:19.004196 RX DQ/DQS(RDDQC) : PASS
9138 13:45:19.004302 TX DQ/DQS : PASS
9139 13:45:19.006994 RX DATLAT : PASS
9140 13:45:19.007074 RX DQ/DQS(Engine): PASS
9141 13:45:19.010584 TX OE : PASS
9142 13:45:19.010663 All Pass.
9143 13:45:19.010726
9144 13:45:19.013891 DramC Write-DBI on
9145 13:45:19.017162 PER_BANK_REFRESH: Hybrid Mode
9146 13:45:19.017243 TX_TRACKING: ON
9147 13:45:19.027258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9148 13:45:19.033875 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9149 13:45:19.043385 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9150 13:45:19.046865 [FAST_K] Save calibration result to emmc
9151 13:45:19.046947 sync common calibartion params.
9152 13:45:19.050185 sync cbt_mode0:1, 1:1
9153 13:45:19.053727 dram_init: ddr_geometry: 2
9154 13:45:19.056713 dram_init: ddr_geometry: 2
9155 13:45:19.056794 dram_init: ddr_geometry: 2
9156 13:45:19.060587 0:dram_rank_size:100000000
9157 13:45:19.063551 1:dram_rank_size:100000000
9158 13:45:19.067297 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9159 13:45:19.070406 DFS_SHUFFLE_HW_MODE: ON
9160 13:45:19.073301 dramc_set_vcore_voltage set vcore to 725000
9161 13:45:19.077112 Read voltage for 1600, 0
9162 13:45:19.077193 Vio18 = 0
9163 13:45:19.080183 Vcore = 725000
9164 13:45:19.080264 Vdram = 0
9165 13:45:19.080327 Vddq = 0
9166 13:45:19.080425 Vmddr = 0
9167 13:45:19.083878 switch to 3200 Mbps bootup
9168 13:45:19.086746 [DramcRunTimeConfig]
9169 13:45:19.086826 PHYPLL
9170 13:45:19.090079 DPM_CONTROL_AFTERK: ON
9171 13:45:19.090185 PER_BANK_REFRESH: ON
9172 13:45:19.093869 REFRESH_OVERHEAD_REDUCTION: ON
9173 13:45:19.096878 CMD_PICG_NEW_MODE: OFF
9174 13:45:19.096959 XRTWTW_NEW_MODE: ON
9175 13:45:19.100472 XRTRTR_NEW_MODE: ON
9176 13:45:19.100556 TX_TRACKING: ON
9177 13:45:19.103442 RDSEL_TRACKING: OFF
9178 13:45:19.106756 DQS Precalculation for DVFS: ON
9179 13:45:19.106839 RX_TRACKING: OFF
9180 13:45:19.106902 HW_GATING DBG: ON
9181 13:45:19.110416 ZQCS_ENABLE_LP4: ON
9182 13:45:19.113519 RX_PICG_NEW_MODE: ON
9183 13:45:19.113599 TX_PICG_NEW_MODE: ON
9184 13:45:19.116549 ENABLE_RX_DCM_DPHY: ON
9185 13:45:19.120266 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9186 13:45:19.120385 DUMMY_READ_FOR_TRACKING: OFF
9187 13:45:19.123286 !!! SPM_CONTROL_AFTERK: OFF
9188 13:45:19.127138 !!! SPM could not control APHY
9189 13:45:19.130044 IMPEDANCE_TRACKING: ON
9190 13:45:19.130162 TEMP_SENSOR: ON
9191 13:45:19.133050 HW_SAVE_FOR_SR: OFF
9192 13:45:19.136559 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9193 13:45:19.139945 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9194 13:45:19.140025 Read ODT Tracking: ON
9195 13:45:19.143209 Refresh Rate DeBounce: ON
9196 13:45:19.146733 DFS_NO_QUEUE_FLUSH: ON
9197 13:45:19.150276 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9198 13:45:19.150350 ENABLE_DFS_RUNTIME_MRW: OFF
9199 13:45:19.153088 DDR_RESERVE_NEW_MODE: ON
9200 13:45:19.156320 MR_CBT_SWITCH_FREQ: ON
9201 13:45:19.156432 =========================
9202 13:45:19.176610 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9203 13:45:19.180180 dram_init: ddr_geometry: 2
9204 13:45:19.198319 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9205 13:45:19.202130 dram_init: dram init end (result: 0)
9206 13:45:19.208118 DRAM-K: Full calibration passed in 24467 msecs
9207 13:45:19.211739 MRC: failed to locate region type 0.
9208 13:45:19.212030 DRAM rank0 size:0x100000000,
9209 13:45:19.215222 DRAM rank1 size=0x100000000
9210 13:45:19.224727 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9211 13:45:19.231444 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9212 13:45:19.238359 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9213 13:45:19.244968 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9214 13:45:19.248379 DRAM rank0 size:0x100000000,
9215 13:45:19.251324 DRAM rank1 size=0x100000000
9216 13:45:19.251560 CBMEM:
9217 13:45:19.254690 IMD: root @ 0xfffff000 254 entries.
9218 13:45:19.258496 IMD: root @ 0xffffec00 62 entries.
9219 13:45:19.261618 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9220 13:45:19.264566 WARNING: RO_VPD is uninitialized or empty.
9221 13:45:19.271344 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9222 13:45:19.300594 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9223 13:45:19.300806 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9224 13:45:19.302473 BS: romstage times (exec / console): total (unknown) / 23998 ms
9225 13:45:19.302599
9226 13:45:19.302668
9227 13:45:19.312654 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9228 13:45:19.316058 ARM64: Exception handlers installed.
9229 13:45:19.319454 ARM64: Testing exception
9230 13:45:19.322158 ARM64: Done test exception
9231 13:45:19.322268 Enumerating buses...
9232 13:45:19.325667 Show all devs... Before device enumeration.
9233 13:45:19.329068 Root Device: enabled 1
9234 13:45:19.332075 CPU_CLUSTER: 0: enabled 1
9235 13:45:19.332208 CPU: 00: enabled 1
9236 13:45:19.335648 Compare with tree...
9237 13:45:19.335799 Root Device: enabled 1
9238 13:45:19.338591 CPU_CLUSTER: 0: enabled 1
9239 13:45:19.342384 CPU: 00: enabled 1
9240 13:45:19.342555 Root Device scanning...
9241 13:45:19.345445 scan_static_bus for Root Device
9242 13:45:19.349235 CPU_CLUSTER: 0 enabled
9243 13:45:19.352192 scan_static_bus for Root Device done
9244 13:45:19.355859 scan_bus: bus Root Device finished in 8 msecs
9245 13:45:19.356155 done
9246 13:45:19.362735 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9247 13:45:19.366187 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9248 13:45:19.372861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9249 13:45:19.375618 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9250 13:45:19.379426 Allocating resources...
9251 13:45:19.379943 Reading resources...
9252 13:45:19.386211 Root Device read_resources bus 0 link: 0
9253 13:45:19.386633 DRAM rank0 size:0x100000000,
9254 13:45:19.389284 DRAM rank1 size=0x100000000
9255 13:45:19.392961 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9256 13:45:19.395711 CPU: 00 missing read_resources
9257 13:45:19.399191 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9258 13:45:19.405749 Root Device read_resources bus 0 link: 0 done
9259 13:45:19.406168 Done reading resources.
9260 13:45:19.412664 Show resources in subtree (Root Device)...After reading.
9261 13:45:19.415573 Root Device child on link 0 CPU_CLUSTER: 0
9262 13:45:19.419243 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 13:45:19.428842 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 13:45:19.429294 CPU: 00
9265 13:45:19.431854 Root Device assign_resources, bus 0 link: 0
9266 13:45:19.435383 CPU_CLUSTER: 0 missing set_resources
9267 13:45:19.439092 Root Device assign_resources, bus 0 link: 0 done
9268 13:45:19.441900 Done setting resources.
9269 13:45:19.448647 Show resources in subtree (Root Device)...After assigning values.
9270 13:45:19.452468 Root Device child on link 0 CPU_CLUSTER: 0
9271 13:45:19.455488 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 13:45:19.465082 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 13:45:19.465423 CPU: 00
9274 13:45:19.468558 Done allocating resources.
9275 13:45:19.471956 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9276 13:45:19.475331 Enabling resources...
9277 13:45:19.475524 done.
9278 13:45:19.481991 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9279 13:45:19.482143 Initializing devices...
9280 13:45:19.484994 Root Device init
9281 13:45:19.485125 init hardware done!
9282 13:45:19.488794 0x00000018: ctrlr->caps
9283 13:45:19.491554 52.000 MHz: ctrlr->f_max
9284 13:45:19.491670 0.400 MHz: ctrlr->f_min
9285 13:45:19.495322 0x40ff8080: ctrlr->voltages
9286 13:45:19.495425 sclk: 390625
9287 13:45:19.498220 Bus Width = 1
9288 13:45:19.498352 sclk: 390625
9289 13:45:19.501992 Bus Width = 1
9290 13:45:19.502123 Early init status = 3
9291 13:45:19.508527 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9292 13:45:19.511306 in-header: 03 fc 00 00 01 00 00 00
9293 13:45:19.511415 in-data: 00
9294 13:45:19.517795 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9295 13:45:19.521472 in-header: 03 fd 00 00 00 00 00 00
9296 13:45:19.525266 in-data:
9297 13:45:19.528233 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9298 13:45:19.532660 in-header: 03 fc 00 00 01 00 00 00
9299 13:45:19.535673 in-data: 00
9300 13:45:19.539043 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9301 13:45:19.544752 in-header: 03 fd 00 00 00 00 00 00
9302 13:45:19.548096 in-data:
9303 13:45:19.551357 [SSUSB] Setting up USB HOST controller...
9304 13:45:19.554467 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9305 13:45:19.557933 [SSUSB] phy power-on done.
9306 13:45:19.561490 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9307 13:45:19.568143 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9308 13:45:19.571132 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9309 13:45:19.578153 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9310 13:45:19.584637 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9311 13:45:19.591259 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9312 13:45:19.598326 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9313 13:45:19.604263 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9314 13:45:19.604397 SPM: binary array size = 0x9dc
9315 13:45:19.611818 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9316 13:45:19.618088 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9317 13:45:19.624673 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9318 13:45:19.627701 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9319 13:45:19.634492 configure_display: Starting display init
9320 13:45:19.668492 anx7625_power_on_init: Init interface.
9321 13:45:19.671651 anx7625_disable_pd_protocol: Disabled PD feature.
9322 13:45:19.675207 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9323 13:45:19.702598 anx7625_start_dp_work: Secure OCM version=00
9324 13:45:19.706238 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9325 13:45:19.720855 sp_tx_get_edid_block: EDID Block = 1
9326 13:45:19.823507 Extracted contents:
9327 13:45:19.826793 header: 00 ff ff ff ff ff ff 00
9328 13:45:19.830234 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9329 13:45:19.833432 version: 01 04
9330 13:45:19.836587 basic params: 95 1f 11 78 0a
9331 13:45:19.840257 chroma info: 76 90 94 55 54 90 27 21 50 54
9332 13:45:19.843701 established: 00 00 00
9333 13:45:19.850178 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9334 13:45:19.853245 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9335 13:45:19.860070 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 13:45:19.866825 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9337 13:45:19.873282 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9338 13:45:19.876120 extensions: 00
9339 13:45:19.876575 checksum: fb
9340 13:45:19.876906
9341 13:45:19.880117 Manufacturer: IVO Model 57d Serial Number 0
9342 13:45:19.883448 Made week 0 of 2020
9343 13:45:19.883863 EDID version: 1.4
9344 13:45:19.886300 Digital display
9345 13:45:19.890217 6 bits per primary color channel
9346 13:45:19.890763 DisplayPort interface
9347 13:45:19.892883 Maximum image size: 31 cm x 17 cm
9348 13:45:19.896505 Gamma: 220%
9349 13:45:19.896918 Check DPMS levels
9350 13:45:19.900126 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9351 13:45:19.903139 First detailed timing is preferred timing
9352 13:45:19.906066 Established timings supported:
9353 13:45:19.909755 Standard timings supported:
9354 13:45:19.912832 Detailed timings
9355 13:45:19.916691 Hex of detail: 383680a07038204018303c0035ae10000019
9356 13:45:19.919299 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9357 13:45:19.926156 0780 0798 07c8 0820 hborder 0
9358 13:45:19.929837 0438 043b 0447 0458 vborder 0
9359 13:45:19.932706 -hsync -vsync
9360 13:45:19.933117 Did detailed timing
9361 13:45:19.939270 Hex of detail: 000000000000000000000000000000000000
9362 13:45:19.939678 Manufacturer-specified data, tag 0
9363 13:45:19.946416 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9364 13:45:19.949275 ASCII string: InfoVision
9365 13:45:19.952734 Hex of detail: 000000fe00523134304e574635205248200a
9366 13:45:19.955941 ASCII string: R140NWF5 RH
9367 13:45:19.956388 Checksum
9368 13:45:19.959264 Checksum: 0xfb (valid)
9369 13:45:19.962574 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9370 13:45:19.965754 DSI data_rate: 832800000 bps
9371 13:45:19.972381 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9372 13:45:19.976030 anx7625_parse_edid: pixelclock(138800).
9373 13:45:19.978988 hactive(1920), hsync(48), hfp(24), hbp(88)
9374 13:45:19.982989 vactive(1080), vsync(12), vfp(3), vbp(17)
9375 13:45:19.985952 anx7625_dsi_config: config dsi.
9376 13:45:19.992110 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9377 13:45:20.005573 anx7625_dsi_config: success to config DSI
9378 13:45:20.008316 anx7625_dp_start: MIPI phy setup OK.
9379 13:45:20.011880 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9380 13:45:20.015604 mtk_ddp_mode_set invalid vrefresh 60
9381 13:45:20.018752 main_disp_path_setup
9382 13:45:20.019267 ovl_layer_smi_id_en
9383 13:45:20.021739 ovl_layer_smi_id_en
9384 13:45:20.022152 ccorr_config
9385 13:45:20.022478 aal_config
9386 13:45:20.025619 gamma_config
9387 13:45:20.026035 postmask_config
9388 13:45:20.028427 dither_config
9389 13:45:20.031995 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9390 13:45:20.038722 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9391 13:45:20.042637 Root Device init finished in 553 msecs
9392 13:45:20.045101 CPU_CLUSTER: 0 init
9393 13:45:20.051547 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9394 13:45:20.055148 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9395 13:45:20.058313 APU_MBOX 0x190000b0 = 0x10001
9396 13:45:20.061819 APU_MBOX 0x190001b0 = 0x10001
9397 13:45:20.065235 APU_MBOX 0x190005b0 = 0x10001
9398 13:45:20.068023 APU_MBOX 0x190006b0 = 0x10001
9399 13:45:20.074543 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9400 13:45:20.084686 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9401 13:45:20.097199 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9402 13:45:20.103370 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9403 13:45:20.114832 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9404 13:45:20.124380 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9405 13:45:20.127304 CPU_CLUSTER: 0 init finished in 81 msecs
9406 13:45:20.130839 Devices initialized
9407 13:45:20.134509 Show all devs... After init.
9408 13:45:20.134949 Root Device: enabled 1
9409 13:45:20.137749 CPU_CLUSTER: 0: enabled 1
9410 13:45:20.141283 CPU: 00: enabled 1
9411 13:45:20.144171 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9412 13:45:20.147698 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9413 13:45:20.150923 ELOG: NV offset 0x57f000 size 0x1000
9414 13:45:20.157403 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9415 13:45:20.164096 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9416 13:45:20.167201 ELOG: Event(17) added with size 13 at 2024-05-28 13:40:40 UTC
9417 13:45:20.173835 out: cmd=0x121: 03 db 21 01 00 00 00 00
9418 13:45:20.177264 in-header: 03 d6 00 00 2c 00 00 00
9419 13:45:20.187636 in-data: 89 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9420 13:45:20.193933 ELOG: Event(A1) added with size 10 at 2024-05-28 13:40:40 UTC
9421 13:45:20.200921 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9422 13:45:20.207653 ELOG: Event(A0) added with size 9 at 2024-05-28 13:40:40 UTC
9423 13:45:20.210089 elog_add_boot_reason: Logged dev mode boot
9424 13:45:20.216989 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9425 13:45:20.217512 Finalize devices...
9426 13:45:20.220524 Devices finalized
9427 13:45:20.223579 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9428 13:45:20.226843 Writing coreboot table at 0xffe64000
9429 13:45:20.230051 0. 000000000010a000-0000000000113fff: RAMSTAGE
9430 13:45:20.233465 1. 0000000040000000-00000000400fffff: RAM
9431 13:45:20.239922 2. 0000000040100000-000000004032afff: RAMSTAGE
9432 13:45:20.243707 3. 000000004032b000-00000000545fffff: RAM
9433 13:45:20.246525 4. 0000000054600000-000000005465ffff: BL31
9434 13:45:20.250434 5. 0000000054660000-00000000ffe63fff: RAM
9435 13:45:20.256769 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9436 13:45:20.260388 7. 0000000100000000-000000023fffffff: RAM
9437 13:45:20.263422 Passing 5 GPIOs to payload:
9438 13:45:20.267222 NAME | PORT | POLARITY | VALUE
9439 13:45:20.269773 EC in RW | 0x000000aa | low | undefined
9440 13:45:20.277268 EC interrupt | 0x00000005 | low | undefined
9441 13:45:20.280058 TPM interrupt | 0x000000ab | high | undefined
9442 13:45:20.287052 SD card detect | 0x00000011 | high | undefined
9443 13:45:20.289942 speaker enable | 0x00000093 | high | undefined
9444 13:45:20.292792 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9445 13:45:20.296585 in-header: 03 f9 00 00 02 00 00 00
9446 13:45:20.300045 in-data: 02 00
9447 13:45:20.303002 ADC[4]: Raw value=904726 ID=7
9448 13:45:20.303423 ADC[3]: Raw value=213441 ID=1
9449 13:45:20.306719 RAM Code: 0x71
9450 13:45:20.309786 ADC[6]: Raw value=75701 ID=0
9451 13:45:20.310205 ADC[5]: Raw value=213072 ID=1
9452 13:45:20.313463 SKU Code: 0x1
9453 13:45:20.316331 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cba
9454 13:45:20.319841 coreboot table: 964 bytes.
9455 13:45:20.322899 IMD ROOT 0. 0xfffff000 0x00001000
9456 13:45:20.326736 IMD SMALL 1. 0xffffe000 0x00001000
9457 13:45:20.329541 RO MCACHE 2. 0xffffc000 0x00001104
9458 13:45:20.333235 CONSOLE 3. 0xfff7c000 0x00080000
9459 13:45:20.336162 FMAP 4. 0xfff7b000 0x00000452
9460 13:45:20.339934 TIME STAMP 5. 0xfff7a000 0x00000910
9461 13:45:20.343026 VBOOT WORK 6. 0xfff66000 0x00014000
9462 13:45:20.346521 RAMOOPS 7. 0xffe66000 0x00100000
9463 13:45:20.349893 COREBOOT 8. 0xffe64000 0x00002000
9464 13:45:20.353524 IMD small region:
9465 13:45:20.356434 IMD ROOT 0. 0xffffec00 0x00000400
9466 13:45:20.359784 VPD 1. 0xffffeb80 0x0000006c
9467 13:45:20.362602 MMC STATUS 2. 0xffffeb60 0x00000004
9468 13:45:20.366793 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9469 13:45:20.369872 Probing TPM: done!
9470 13:45:20.373667 Connected to device vid:did:rid of 1ae0:0028:00
9471 13:45:20.383840 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9472 13:45:20.386724 Initialized TPM device CR50 revision 0
9473 13:45:20.391171 Checking cr50 for pending updates
9474 13:45:20.394591 Reading cr50 TPM mode
9475 13:45:20.402990 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9476 13:45:20.409733 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9477 13:45:20.450607 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9478 13:45:20.453358 Checking segment from ROM address 0x40100000
9479 13:45:20.456261 Checking segment from ROM address 0x4010001c
9480 13:45:20.463553 Loading segment from ROM address 0x40100000
9481 13:45:20.464079 code (compression=0)
9482 13:45:20.473439 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9483 13:45:20.479981 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9484 13:45:20.480558 it's not compressed!
9485 13:45:20.486689 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9486 13:45:20.489978 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9487 13:45:20.510377 Loading segment from ROM address 0x4010001c
9488 13:45:20.510993 Entry Point 0x80000000
9489 13:45:20.513755 Loaded segments
9490 13:45:20.517132 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9491 13:45:20.523370 Jumping to boot code at 0x80000000(0xffe64000)
9492 13:45:20.529910 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9493 13:45:20.536278 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9494 13:45:20.544426 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9495 13:45:20.548023 Checking segment from ROM address 0x40100000
9496 13:45:20.551028 Checking segment from ROM address 0x4010001c
9497 13:45:20.557733 Loading segment from ROM address 0x40100000
9498 13:45:20.558151 code (compression=1)
9499 13:45:20.564185 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9500 13:45:20.574503 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9501 13:45:20.575177 using LZMA
9502 13:45:20.582679 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9503 13:45:20.589688 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9504 13:45:20.593690 Loading segment from ROM address 0x4010001c
9505 13:45:20.594204 Entry Point 0x54601000
9506 13:45:20.596258 Loaded segments
9507 13:45:20.599137 NOTICE: MT8192 bl31_setup
9508 13:45:20.606575 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9509 13:45:20.609994 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9510 13:45:20.613071 WARNING: region 0:
9511 13:45:20.616306 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 13:45:20.616782 WARNING: region 1:
9513 13:45:20.623435 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9514 13:45:20.627356 WARNING: region 2:
9515 13:45:20.630292 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9516 13:45:20.633603 WARNING: region 3:
9517 13:45:20.636405 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9518 13:45:20.639827 WARNING: region 4:
9519 13:45:20.643329 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 13:45:20.646623 WARNING: region 5:
9521 13:45:20.650598 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 13:45:20.653458 WARNING: region 6:
9523 13:45:20.656559 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 13:45:20.657085 WARNING: region 7:
9525 13:45:20.663187 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 13:45:20.669900 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9527 13:45:20.673763 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9528 13:45:20.676938 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9529 13:45:20.683358 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9530 13:45:20.687350 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9531 13:45:20.690321 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9532 13:45:20.697121 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9533 13:45:20.700206 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9534 13:45:20.703362 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9535 13:45:20.710685 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9536 13:45:20.713352 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9537 13:45:20.719949 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9538 13:45:20.723592 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9539 13:45:20.726619 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9540 13:45:20.733463 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9541 13:45:20.736374 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9542 13:45:20.740325 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9543 13:45:20.746817 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9544 13:45:20.750486 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9545 13:45:20.753611 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9546 13:45:20.760400 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9547 13:45:20.763532 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9548 13:45:20.769868 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9549 13:45:20.773298 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9550 13:45:20.776640 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9551 13:45:20.783417 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9552 13:45:20.786666 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9553 13:45:20.793069 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9554 13:45:20.796715 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9555 13:45:20.799770 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9556 13:45:20.807010 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9557 13:45:20.809959 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9558 13:45:20.813589 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9559 13:45:20.820208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9560 13:45:20.823181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9561 13:45:20.826804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9562 13:45:20.829827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9563 13:45:20.836856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9564 13:45:20.840848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9565 13:45:20.843853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9566 13:45:20.846695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9567 13:45:20.853310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9568 13:45:20.857314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9569 13:45:20.859832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9570 13:45:20.863653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9571 13:45:20.870147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9572 13:45:20.873180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9573 13:45:20.876629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9574 13:45:20.883434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9575 13:45:20.887206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9576 13:45:20.893219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9577 13:45:20.896675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9578 13:45:20.900454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9579 13:45:20.906873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9580 13:45:20.910377 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9581 13:45:20.917307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9582 13:45:20.919964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9583 13:45:20.923344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9584 13:45:20.930004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9585 13:45:20.933706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9586 13:45:20.940426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9587 13:45:20.943953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9588 13:45:20.950497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9589 13:45:20.953814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9590 13:45:20.959830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9591 13:45:20.963096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9592 13:45:20.966814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9593 13:45:20.973700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9594 13:45:20.976643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9595 13:45:20.983750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9596 13:45:20.986822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9597 13:45:20.990603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9598 13:45:20.996493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9599 13:45:21.000115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9600 13:45:21.006944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9601 13:45:21.009936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9602 13:45:21.016688 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9603 13:45:21.019665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9604 13:45:21.026943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9605 13:45:21.029794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9606 13:45:21.032988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9607 13:45:21.040169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9608 13:45:21.043365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9609 13:45:21.050059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9610 13:45:21.053264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9611 13:45:21.059934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9612 13:45:21.063421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9613 13:45:21.067031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9614 13:45:21.073158 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9615 13:45:21.076547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9616 13:45:21.083331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9617 13:45:21.086317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9618 13:45:21.093600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9619 13:45:21.096657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9620 13:45:21.099651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9621 13:45:21.106436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9622 13:45:21.109865 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9623 13:45:21.113279 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9624 13:45:21.120046 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9625 13:45:21.123142 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9626 13:45:21.126900 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9627 13:45:21.132997 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9628 13:45:21.136763 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9629 13:45:21.139696 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9630 13:45:21.146487 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9631 13:45:21.150015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9632 13:45:21.156569 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9633 13:45:21.159910 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9634 13:45:21.163246 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9635 13:45:21.169621 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9636 13:45:21.172635 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9637 13:45:21.179372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9638 13:45:21.182795 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9639 13:45:21.186282 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9640 13:45:21.192906 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9641 13:45:21.195814 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9642 13:45:21.199411 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9643 13:45:21.206410 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9644 13:45:21.209430 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9645 13:45:21.212367 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9646 13:45:21.219772 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9647 13:45:21.222914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9648 13:45:21.226329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9649 13:45:21.229312 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9650 13:45:21.236114 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9651 13:45:21.239917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9652 13:45:21.243038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9653 13:45:21.250017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9654 13:45:21.253030 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9655 13:45:21.259605 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9656 13:45:21.262995 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9657 13:45:21.266056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9658 13:45:21.272844 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9659 13:45:21.276664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9660 13:45:21.279669 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9661 13:45:21.286529 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9662 13:45:21.290071 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9663 13:45:21.296494 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9664 13:45:21.299741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9665 13:45:21.302974 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9666 13:45:21.309985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9667 13:45:21.313436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9668 13:45:21.319890 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9669 13:45:21.323235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9670 13:45:21.326727 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9671 13:45:21.333033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9672 13:45:21.336631 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9673 13:45:21.339608 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9674 13:45:21.346343 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9675 13:45:21.350219 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9676 13:45:21.356804 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9677 13:45:21.359777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9678 13:45:21.363443 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9679 13:45:21.370122 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9680 13:45:21.373120 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9681 13:45:21.379826 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9682 13:45:21.383580 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9683 13:45:21.386687 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9684 13:45:21.393569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9685 13:45:21.396549 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9686 13:45:21.400174 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9687 13:45:21.406403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9688 13:45:21.409754 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9689 13:45:21.416437 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9690 13:45:21.420186 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9691 13:45:21.423382 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9692 13:45:21.429922 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9693 13:45:21.433026 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9694 13:45:21.439476 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9695 13:45:21.442863 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9696 13:45:21.446224 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9697 13:45:21.453068 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9698 13:45:21.455995 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9699 13:45:21.462523 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9700 13:45:21.466197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9701 13:45:21.469006 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9702 13:45:21.476265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9703 13:45:21.479442 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9704 13:45:21.486361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9705 13:45:21.489137 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9706 13:45:21.492330 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9707 13:45:21.499719 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9708 13:45:21.502886 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9709 13:45:21.509406 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9710 13:45:21.512533 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9711 13:45:21.515860 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9712 13:45:21.522799 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9713 13:45:21.526203 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9714 13:45:21.529005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9715 13:45:21.535689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9716 13:45:21.539148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9717 13:45:21.545834 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9718 13:45:21.549535 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9719 13:45:21.556014 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9720 13:45:21.558960 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9721 13:45:21.562876 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9722 13:45:21.569050 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9723 13:45:21.572877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9724 13:45:21.578880 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9725 13:45:21.582462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9726 13:45:21.585700 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9727 13:45:21.592782 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9728 13:45:21.595590 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9729 13:45:21.602105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9730 13:45:21.605759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9731 13:45:21.612335 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9732 13:45:21.615307 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9733 13:45:21.618942 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9734 13:45:21.625476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9735 13:45:21.628502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9736 13:45:21.635628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9737 13:45:21.638662 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9738 13:45:21.645129 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9739 13:45:21.648948 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9740 13:45:21.652373 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9741 13:45:21.659318 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9742 13:45:21.661909 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9743 13:45:21.668491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9744 13:45:21.672282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9745 13:45:21.675625 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9746 13:45:21.682249 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9747 13:45:21.685080 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9748 13:45:21.691677 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9749 13:45:21.695590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9750 13:45:21.698692 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9751 13:45:21.705223 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9752 13:45:21.708477 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9753 13:45:21.715627 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9754 13:45:21.718746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9755 13:45:21.722125 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9756 13:45:21.728892 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9757 13:45:21.731961 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9758 13:45:21.734763 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9759 13:45:21.738435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9760 13:45:21.745177 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9761 13:45:21.748867 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9762 13:45:21.751945 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9763 13:45:21.759127 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9764 13:45:21.761640 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9765 13:45:21.765392 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9766 13:45:21.771689 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9767 13:45:21.774667 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9768 13:45:21.782023 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9769 13:45:21.785040 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9770 13:45:21.788073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9771 13:45:21.794703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9772 13:45:21.798747 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9773 13:45:21.805227 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9774 13:45:21.808025 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9775 13:45:21.811289 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9776 13:45:21.818104 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9777 13:45:21.821551 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9778 13:45:21.824905 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9779 13:45:21.831368 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9780 13:45:21.834779 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9781 13:45:21.837625 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9782 13:45:21.844680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9783 13:45:21.847437 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9784 13:45:21.850814 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9785 13:45:21.858061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9786 13:45:21.860773 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9787 13:45:21.867647 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9788 13:45:21.871161 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9789 13:45:21.874017 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9790 13:45:21.880823 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9791 13:45:21.884283 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9792 13:45:21.887973 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9793 13:45:21.894056 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9794 13:45:21.897987 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9795 13:45:21.900801 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9796 13:45:21.907162 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9797 13:45:21.910963 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9798 13:45:21.914447 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9799 13:45:21.917367 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9800 13:45:21.920904 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9801 13:45:21.927887 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9802 13:45:21.930566 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9803 13:45:21.933945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9804 13:45:21.937482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9805 13:45:21.944310 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9806 13:45:21.947518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9807 13:45:21.950811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9808 13:45:21.957631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9809 13:45:21.960630 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9810 13:45:21.967413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9811 13:45:21.970893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9812 13:45:21.973727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9813 13:45:21.980837 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9814 13:45:21.984161 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9815 13:45:21.990645 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9816 13:45:21.994458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9817 13:45:21.997277 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9818 13:45:22.004084 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9819 13:45:22.007742 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9820 13:45:22.014077 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9821 13:45:22.017895 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9822 13:45:22.024533 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9823 13:45:22.027064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9824 13:45:22.030716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9825 13:45:22.037552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9826 13:45:22.040989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9827 13:45:22.044248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9828 13:45:22.050550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9829 13:45:22.054266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9830 13:45:22.060980 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9831 13:45:22.063628 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9832 13:45:22.067004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9833 13:45:22.074187 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9834 13:45:22.076883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9835 13:45:22.083615 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9836 13:45:22.086800 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9837 13:45:22.093399 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9838 13:45:22.097088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9839 13:45:22.100831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9840 13:45:22.106915 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9841 13:45:22.110485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9842 13:45:22.116999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9843 13:45:22.120752 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9844 13:45:22.123860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9845 13:45:22.130595 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9846 13:45:22.133813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9847 13:45:22.140123 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9848 13:45:22.143532 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9849 13:45:22.147334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9850 13:45:22.153441 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9851 13:45:22.157230 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9852 13:45:22.163589 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9853 13:45:22.166563 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9854 13:45:22.173212 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9855 13:45:22.176900 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9856 13:45:22.179875 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9857 13:45:22.186390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9858 13:45:22.189897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9859 13:45:22.197282 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9860 13:45:22.200318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9861 13:45:22.203191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9862 13:45:22.209745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9863 13:45:22.213225 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9864 13:45:22.216573 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9865 13:45:22.223225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9866 13:45:22.227058 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9867 13:45:22.233197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9868 13:45:22.236847 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9869 13:45:22.243708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9870 13:45:22.246322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9871 13:45:22.249600 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9872 13:45:22.256882 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9873 13:45:22.259464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9874 13:45:22.266590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9875 13:45:22.269705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9876 13:45:22.273367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9877 13:45:22.280118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9878 13:45:22.283128 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9879 13:45:22.290373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9880 13:45:22.293054 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9881 13:45:22.296881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9882 13:45:22.303737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9883 13:45:22.306633 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9884 13:45:22.312908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9885 13:45:22.315954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9886 13:45:22.322748 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9887 13:45:22.326220 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9888 13:45:22.333054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9889 13:45:22.335739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9890 13:45:22.339029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9891 13:45:22.345690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9892 13:45:22.349643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9893 13:45:22.355970 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9894 13:45:22.358993 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9895 13:45:22.365889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9896 13:45:22.369293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9897 13:45:22.372244 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9898 13:45:22.378780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9899 13:45:22.382457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9900 13:45:22.388849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9901 13:45:22.392687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9902 13:45:22.399262 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9903 13:45:22.402119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9904 13:45:22.405787 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9905 13:45:22.412492 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9906 13:45:22.416100 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9907 13:45:22.422658 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9908 13:45:22.425553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9909 13:45:22.432557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9910 13:45:22.435806 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9911 13:45:22.439224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9912 13:45:22.445852 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9913 13:45:22.449116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9914 13:45:22.455305 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9915 13:45:22.458958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9916 13:45:22.465554 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9917 13:45:22.468972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9918 13:45:22.475700 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9919 13:45:22.479089 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9920 13:45:22.481906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9921 13:45:22.488731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9922 13:45:22.491700 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9923 13:45:22.498949 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9924 13:45:22.501857 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9925 13:45:22.508481 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9926 13:45:22.511975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9927 13:45:22.515594 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9928 13:45:22.522162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9929 13:45:22.525067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9930 13:45:22.531895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9931 13:45:22.535462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9932 13:45:22.541944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9933 13:45:22.545403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9934 13:45:22.552243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9935 13:45:22.554996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9936 13:45:22.562069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9937 13:45:22.564961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9938 13:45:22.571863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9939 13:45:22.574935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9940 13:45:22.581284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9941 13:45:22.584791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9942 13:45:22.588313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9943 13:45:22.615942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9944 13:45:22.616511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9945 13:45:22.616966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9946 13:45:22.617386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9947 13:45:22.617797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9948 13:45:22.618549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9949 13:45:22.624984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9950 13:45:22.627527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9951 13:45:22.634842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9952 13:45:22.637956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9953 13:45:22.644612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9954 13:45:22.648164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9955 13:45:22.654835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9956 13:45:22.658177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9957 13:45:22.664785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9958 13:45:22.668034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9959 13:45:22.674582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9960 13:45:22.677939 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9961 13:45:22.681139 INFO: [APUAPC] vio 0
9962 13:45:22.684747 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9963 13:45:22.691271 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9964 13:45:22.694275 INFO: [APUAPC] D0_APC_0: 0x400510
9965 13:45:22.697994 INFO: [APUAPC] D0_APC_1: 0x0
9966 13:45:22.698659 INFO: [APUAPC] D0_APC_2: 0x1540
9967 13:45:22.700976 INFO: [APUAPC] D0_APC_3: 0x0
9968 13:45:22.704522 INFO: [APUAPC] D1_APC_0: 0xffffffff
9969 13:45:22.708107 INFO: [APUAPC] D1_APC_1: 0xffffffff
9970 13:45:22.710817 INFO: [APUAPC] D1_APC_2: 0x3fffff
9971 13:45:22.714316 INFO: [APUAPC] D1_APC_3: 0x0
9972 13:45:22.717820 INFO: [APUAPC] D2_APC_0: 0xffffffff
9973 13:45:22.720508 INFO: [APUAPC] D2_APC_1: 0xffffffff
9974 13:45:22.723961 INFO: [APUAPC] D2_APC_2: 0x3fffff
9975 13:45:22.727189 INFO: [APUAPC] D2_APC_3: 0x0
9976 13:45:22.730673 INFO: [APUAPC] D3_APC_0: 0xffffffff
9977 13:45:22.734245 INFO: [APUAPC] D3_APC_1: 0xffffffff
9978 13:45:22.737282 INFO: [APUAPC] D3_APC_2: 0x3fffff
9979 13:45:22.740947 INFO: [APUAPC] D3_APC_3: 0x0
9980 13:45:22.743970 INFO: [APUAPC] D4_APC_0: 0xffffffff
9981 13:45:22.747100 INFO: [APUAPC] D4_APC_1: 0xffffffff
9982 13:45:22.750525 INFO: [APUAPC] D4_APC_2: 0x3fffff
9983 13:45:22.754297 INFO: [APUAPC] D4_APC_3: 0x0
9984 13:45:22.757244 INFO: [APUAPC] D5_APC_0: 0xffffffff
9985 13:45:22.760142 INFO: [APUAPC] D5_APC_1: 0xffffffff
9986 13:45:22.763759 INFO: [APUAPC] D5_APC_2: 0x3fffff
9987 13:45:22.767148 INFO: [APUAPC] D5_APC_3: 0x0
9988 13:45:22.770211 INFO: [APUAPC] D6_APC_0: 0xffffffff
9989 13:45:22.773952 INFO: [APUAPC] D6_APC_1: 0xffffffff
9990 13:45:22.776948 INFO: [APUAPC] D6_APC_2: 0x3fffff
9991 13:45:22.780255 INFO: [APUAPC] D6_APC_3: 0x0
9992 13:45:22.783549 INFO: [APUAPC] D7_APC_0: 0xffffffff
9993 13:45:22.786811 INFO: [APUAPC] D7_APC_1: 0xffffffff
9994 13:45:22.789987 INFO: [APUAPC] D7_APC_2: 0x3fffff
9995 13:45:22.793687 INFO: [APUAPC] D7_APC_3: 0x0
9996 13:45:22.796774 INFO: [APUAPC] D8_APC_0: 0xffffffff
9997 13:45:22.800261 INFO: [APUAPC] D8_APC_1: 0xffffffff
9998 13:45:22.803969 INFO: [APUAPC] D8_APC_2: 0x3fffff
9999 13:45:22.806955 INFO: [APUAPC] D8_APC_3: 0x0
10000 13:45:22.809910 INFO: [APUAPC] D9_APC_0: 0xffffffff
10001 13:45:22.813547 INFO: [APUAPC] D9_APC_1: 0xffffffff
10002 13:45:22.817114 INFO: [APUAPC] D9_APC_2: 0x3fffff
10003 13:45:22.819936 INFO: [APUAPC] D9_APC_3: 0x0
10004 13:45:22.823467 INFO: [APUAPC] D10_APC_0: 0xffffffff
10005 13:45:22.827101 INFO: [APUAPC] D10_APC_1: 0xffffffff
10006 13:45:22.830369 INFO: [APUAPC] D10_APC_2: 0x3fffff
10007 13:45:22.833756 INFO: [APUAPC] D10_APC_3: 0x0
10008 13:45:22.836488 INFO: [APUAPC] D11_APC_0: 0xffffffff
10009 13:45:22.840295 INFO: [APUAPC] D11_APC_1: 0xffffffff
10010 13:45:22.843833 INFO: [APUAPC] D11_APC_2: 0x3fffff
10011 13:45:22.846664 INFO: [APUAPC] D11_APC_3: 0x0
10012 13:45:22.850319 INFO: [APUAPC] D12_APC_0: 0xffffffff
10013 13:45:22.853212 INFO: [APUAPC] D12_APC_1: 0xffffffff
10014 13:45:22.857117 INFO: [APUAPC] D12_APC_2: 0x3fffff
10015 13:45:22.860712 INFO: [APUAPC] D12_APC_3: 0x0
10016 13:45:22.863350 INFO: [APUAPC] D13_APC_0: 0xffffffff
10017 13:45:22.866775 INFO: [APUAPC] D13_APC_1: 0xffffffff
10018 13:45:22.870305 INFO: [APUAPC] D13_APC_2: 0x3fffff
10019 13:45:22.873354 INFO: [APUAPC] D13_APC_3: 0x0
10020 13:45:22.876922 INFO: [APUAPC] D14_APC_0: 0xffffffff
10021 13:45:22.880124 INFO: [APUAPC] D14_APC_1: 0xffffffff
10022 13:45:22.883753 INFO: [APUAPC] D14_APC_2: 0x3fffff
10023 13:45:22.886616 INFO: [APUAPC] D14_APC_3: 0x0
10024 13:45:22.890590 INFO: [APUAPC] D15_APC_0: 0xffffffff
10025 13:45:22.893561 INFO: [APUAPC] D15_APC_1: 0xffffffff
10026 13:45:22.896903 INFO: [APUAPC] D15_APC_2: 0x3fffff
10027 13:45:22.899761 INFO: [APUAPC] D15_APC_3: 0x0
10028 13:45:22.902943 INFO: [APUAPC] APC_CON: 0x4
10029 13:45:22.903139 INFO: [NOCDAPC] D0_APC_0: 0x0
10030 13:45:22.906321 INFO: [NOCDAPC] D0_APC_1: 0x0
10031 13:45:22.909703 INFO: [NOCDAPC] D1_APC_0: 0x0
10032 13:45:22.913470 INFO: [NOCDAPC] D1_APC_1: 0xfff
10033 13:45:22.916306 INFO: [NOCDAPC] D2_APC_0: 0x0
10034 13:45:22.920036 INFO: [NOCDAPC] D2_APC_1: 0xfff
10035 13:45:22.923099 INFO: [NOCDAPC] D3_APC_0: 0x0
10036 13:45:22.926373 INFO: [NOCDAPC] D3_APC_1: 0xfff
10037 13:45:22.929942 INFO: [NOCDAPC] D4_APC_0: 0x0
10038 13:45:22.933525 INFO: [NOCDAPC] D4_APC_1: 0xfff
10039 13:45:22.936357 INFO: [NOCDAPC] D5_APC_0: 0x0
10040 13:45:22.936784 INFO: [NOCDAPC] D5_APC_1: 0xfff
10041 13:45:22.939983 INFO: [NOCDAPC] D6_APC_0: 0x0
10042 13:45:22.943518 INFO: [NOCDAPC] D6_APC_1: 0xfff
10043 13:45:22.946439 INFO: [NOCDAPC] D7_APC_0: 0x0
10044 13:45:22.950057 INFO: [NOCDAPC] D7_APC_1: 0xfff
10045 13:45:22.953783 INFO: [NOCDAPC] D8_APC_0: 0x0
10046 13:45:22.956872 INFO: [NOCDAPC] D8_APC_1: 0xfff
10047 13:45:22.960694 INFO: [NOCDAPC] D9_APC_0: 0x0
10048 13:45:22.963720 INFO: [NOCDAPC] D9_APC_1: 0xfff
10049 13:45:22.966959 INFO: [NOCDAPC] D10_APC_0: 0x0
10050 13:45:22.970200 INFO: [NOCDAPC] D10_APC_1: 0xfff
10051 13:45:22.970619 INFO: [NOCDAPC] D11_APC_0: 0x0
10052 13:45:22.973620 INFO: [NOCDAPC] D11_APC_1: 0xfff
10053 13:45:22.976405 INFO: [NOCDAPC] D12_APC_0: 0x0
10054 13:45:22.980195 INFO: [NOCDAPC] D12_APC_1: 0xfff
10055 13:45:22.983117 INFO: [NOCDAPC] D13_APC_0: 0x0
10056 13:45:22.986337 INFO: [NOCDAPC] D13_APC_1: 0xfff
10057 13:45:22.989836 INFO: [NOCDAPC] D14_APC_0: 0x0
10058 13:45:22.993899 INFO: [NOCDAPC] D14_APC_1: 0xfff
10059 13:45:22.997072 INFO: [NOCDAPC] D15_APC_0: 0x0
10060 13:45:23.000446 INFO: [NOCDAPC] D15_APC_1: 0xfff
10061 13:45:23.003926 INFO: [NOCDAPC] APC_CON: 0x4
10062 13:45:23.006997 INFO: [APUAPC] set_apusys_apc done
10063 13:45:23.010206 INFO: [DEVAPC] devapc_init done
10064 13:45:23.013676 INFO: GICv3 without legacy support detected.
10065 13:45:23.016889 INFO: ARM GICv3 driver initialized in EL3
10066 13:45:23.020452 INFO: Maximum SPI INTID supported: 639
10067 13:45:23.022967 INFO: BL31: Initializing runtime services
10068 13:45:23.029548 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10069 13:45:23.033014 INFO: SPM: enable CPC mode
10070 13:45:23.039550 INFO: mcdi ready for mcusys-off-idle and system suspend
10071 13:45:23.042938 INFO: BL31: Preparing for EL3 exit to normal world
10072 13:45:23.046469 INFO: Entry point address = 0x80000000
10073 13:45:23.049341 INFO: SPSR = 0x8
10074 13:45:23.054586
10075 13:45:23.055026
10076 13:45:23.055357
10077 13:45:23.057418 Starting depthcharge on Spherion...
10078 13:45:23.057839
10079 13:45:23.058170 Wipe memory regions:
10080 13:45:23.058478
10081 13:45:23.060846 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10082 13:45:23.061333 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10083 13:45:23.061731 Setting prompt string to ['asurada:']
10084 13:45:23.062133 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10085 13:45:23.062854 [0x00000040000000, 0x00000054600000)
10086 13:45:23.183324
10087 13:45:23.183834 [0x00000054660000, 0x00000080000000)
10088 13:45:23.442907
10089 13:45:23.443061 [0x000000821a7280, 0x000000ffe64000)
10090 13:45:24.187885
10091 13:45:24.188455 [0x00000100000000, 0x00000240000000)
10092 13:45:26.074462
10093 13:45:26.076977 Initializing XHCI USB controller at 0x11200000.
10094 13:45:27.115318
10095 13:45:27.118474 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10096 13:45:27.118952
10097 13:45:27.119293
10098 13:45:27.120056 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10100 13:45:27.221349 asurada: tftpboot 192.168.201.1 14063055/tftp-deploy-2ustgt69/kernel/image.itb 14063055/tftp-deploy-2ustgt69/kernel/cmdline
10101 13:45:27.221952 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 13:45:27.222421 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10103 13:45:27.226733 tftpboot 192.168.201.1 14063055/tftp-deploy-2ustgt69/kernel/image.ittp-deploy-2ustgt69/kernel/cmdline
10104 13:45:27.227206
10105 13:45:27.227542 Waiting for link
10106 13:45:27.387548
10107 13:45:27.388051 R8152: Initializing
10108 13:45:27.388476
10109 13:45:27.390802 Version 9 (ocp_data = 6010)
10110 13:45:27.391384
10111 13:45:27.393687 R8152: Done initializing
10112 13:45:27.394100
10113 13:45:27.394427 Adding net device
10114 13:45:29.337252
10115 13:45:29.337882 done.
10116 13:45:29.338358
10117 13:45:29.338811 MAC: 00:e0:4c:78:7a:aa
10118 13:45:29.339253
10119 13:45:29.340118 Sending DHCP discover... done.
10120 13:45:29.340577
10121 13:45:38.001641 Waiting for reply... done.
10122 13:45:38.002129
10123 13:45:38.002463 Sending DHCP request... done.
10124 13:45:38.005035
10125 13:45:38.008849 Waiting for reply... done.
10126 13:45:38.009274
10127 13:45:38.009605 My ip is 192.168.201.12
10128 13:45:38.009915
10129 13:45:38.012154 The DHCP server ip is 192.168.201.1
10130 13:45:38.012625
10131 13:45:38.018444 TFTP server IP predefined by user: 192.168.201.1
10132 13:45:38.018865
10133 13:45:38.025399 Bootfile predefined by user: 14063055/tftp-deploy-2ustgt69/kernel/image.itb
10134 13:45:38.026035
10135 13:45:38.026384 Sending tftp read request... done.
10136 13:45:38.028461
10137 13:45:38.034386 Waiting for the transfer...
10138 13:45:38.034851
10139 13:45:38.381803 00000000 ################################################################
10140 13:45:38.381952
10141 13:45:38.637589 00080000 ################################################################
10142 13:45:38.637725
10143 13:45:38.881321 00100000 ################################################################
10144 13:45:38.881457
10145 13:45:39.136986 00180000 ################################################################
10146 13:45:39.137148
10147 13:45:39.384532 00200000 ################################################################
10148 13:45:39.384693
10149 13:45:39.640931 00280000 ################################################################
10150 13:45:39.641086
10151 13:45:39.911840 00300000 ################################################################
10152 13:45:39.911999
10153 13:45:40.165363 00380000 ################################################################
10154 13:45:40.165531
10155 13:45:40.422410 00400000 ################################################################
10156 13:45:40.422567
10157 13:45:40.699786 00480000 ################################################################
10158 13:45:40.699973
10159 13:45:40.967856 00500000 ################################################################
10160 13:45:40.967999
10161 13:45:41.218843 00580000 ################################################################
10162 13:45:41.219001
10163 13:45:41.466515 00600000 ################################################################
10164 13:45:41.466680
10165 13:45:41.715443 00680000 ################################################################
10166 13:45:41.715600
10167 13:45:41.971819 00700000 ################################################################
10168 13:45:41.971985
10169 13:45:42.221238 00780000 ################################################################
10170 13:45:42.221413
10171 13:45:42.464205 00800000 ################################################################
10172 13:45:42.464409
10173 13:45:42.711191 00880000 ################################################################
10174 13:45:42.711335
10175 13:45:42.964103 00900000 ################################################################
10176 13:45:42.964265
10177 13:45:43.209353 00980000 ################################################################
10178 13:45:43.209510
10179 13:45:43.463350 00a00000 ################################################################
10180 13:45:43.463527
10181 13:45:43.720822 00a80000 ################################################################
10182 13:45:43.720967
10183 13:45:43.966486 00b00000 ################################################################
10184 13:45:43.966632
10185 13:45:44.214077 00b80000 ################################################################
10186 13:45:44.214223
10187 13:45:44.474189 00c00000 ################################################################
10188 13:45:44.474338
10189 13:45:44.743159 00c80000 ################################################################
10190 13:45:44.743301
10191 13:45:44.995111 00d00000 ################################################################
10192 13:45:44.995276
10193 13:45:45.246542 00d80000 ################################################################
10194 13:45:45.246699
10195 13:45:45.492769 00e00000 ################################################################
10196 13:45:45.492915
10197 13:45:45.741552 00e80000 ################################################################
10198 13:45:45.741713
10199 13:45:45.986222 00f00000 ################################################################
10200 13:45:45.986387
10201 13:45:46.230993 00f80000 ################################################################
10202 13:45:46.231157
10203 13:45:46.477818 01000000 ################################################################
10204 13:45:46.477993
10205 13:45:46.723223 01080000 ################################################################
10206 13:45:46.723370
10207 13:45:46.969602 01100000 ################################################################
10208 13:45:46.969753
10209 13:45:47.218668 01180000 ################################################################
10210 13:45:47.218816
10211 13:45:47.465792 01200000 ################################################################
10212 13:45:47.465938
10213 13:45:47.712234 01280000 ################################################################
10214 13:45:47.712437
10215 13:45:47.965438 01300000 ################################################################
10216 13:45:47.965618
10217 13:45:48.214157 01380000 ################################################################
10218 13:45:48.214299
10219 13:45:48.467924 01400000 ################################################################
10220 13:45:48.468096
10221 13:45:48.706136 01480000 ################################################################
10222 13:45:48.706276
10223 13:45:48.956330 01500000 ################################################################
10224 13:45:48.956506
10225 13:45:49.213315 01580000 ################################################################
10226 13:45:49.213492
10227 13:45:49.468472 01600000 ################################################################
10228 13:45:49.468635
10229 13:45:49.726657 01680000 ################################################################
10230 13:45:49.726825
10231 13:45:49.981446 01700000 ################################################################
10232 13:45:49.981605
10233 13:45:50.247349 01780000 ################################################################
10234 13:45:50.247572
10235 13:45:50.519413 01800000 ################################################################
10236 13:45:50.519575
10237 13:45:50.793692 01880000 ################################################################
10238 13:45:50.793865
10239 13:45:51.045751 01900000 ################################################################
10240 13:45:51.045920
10241 13:45:51.300352 01980000 ################################################################
10242 13:45:51.300549
10243 13:45:51.543541 01a00000 ################################################################
10244 13:45:51.543736
10245 13:45:51.788903 01a80000 ################################################################
10246 13:45:51.789094
10247 13:45:52.055263 01b00000 ################################################################
10248 13:45:52.055454
10249 13:45:52.319760 01b80000 ################################################################
10250 13:45:52.319892
10251 13:45:52.588032 01c00000 ################################################################
10252 13:45:52.588198
10253 13:45:52.865834 01c80000 ################################################################
10254 13:45:52.865987
10255 13:45:53.137335 01d00000 ################################################################
10256 13:45:53.137485
10257 13:45:53.424873 01d80000 ################################################################
10258 13:45:53.425022
10259 13:45:53.614428 01e00000 ############################################### done.
10260 13:45:53.614577
10261 13:45:53.618025 The bootfile was 31842282 bytes long.
10262 13:45:53.618111
10263 13:45:53.620831 Sending tftp read request... done.
10264 13:45:53.620951
10265 13:45:53.621049 Waiting for the transfer...
10266 13:45:53.621168
10267 13:45:53.623586 00000000 # done.
10268 13:45:53.623672
10269 13:45:53.630645 Command line loaded dynamically from TFTP file: 14063055/tftp-deploy-2ustgt69/kernel/cmdline
10270 13:45:53.630730
10271 13:45:53.653805 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10272 13:45:53.653905
10273 13:45:53.653972 Loading FIT.
10274 13:45:53.654032
10275 13:45:53.657232 Image ramdisk-1 has 18731685 bytes.
10276 13:45:53.657314
10277 13:45:53.660659 Image fdt-1 has 47258 bytes.
10278 13:45:53.660741
10279 13:45:53.663720 Image kernel-1 has 13061303 bytes.
10280 13:45:53.663809
10281 13:45:53.673433 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10282 13:45:53.673521
10283 13:45:53.690560 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10284 13:45:53.690661
10285 13:45:53.696996 Choosing best match conf-1 for compat google,spherion-rev2.
10286 13:45:53.700424
10287 13:45:53.705173 Connected to device vid:did:rid of 1ae0:0028:00
10288 13:45:53.712904
10289 13:45:53.716445 tpm_get_response: command 0x17b, return code 0x0
10290 13:45:53.716526
10291 13:45:53.719344 ec_init: CrosEC protocol v3 supported (256, 248)
10292 13:45:53.724235
10293 13:45:53.727974 tpm_cleanup: add release locality here.
10294 13:45:53.728056
10295 13:45:53.728120 Shutting down all USB controllers.
10296 13:45:53.730898
10297 13:45:53.730980 Removing current net device
10298 13:45:53.731045
10299 13:45:53.737996 Exiting depthcharge with code 4 at timestamp: 59970289
10300 13:45:53.738078
10301 13:45:53.740908 LZMA decompressing kernel-1 to 0x821a6718
10302 13:45:53.740989
10303 13:45:53.744267 LZMA decompressing kernel-1 to 0x40000000
10304 13:45:55.356197
10305 13:45:55.356386 jumping to kernel
10306 13:45:55.356894 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10307 13:45:55.356994 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10308 13:45:55.357069 Setting prompt string to ['Linux version [0-9]']
10309 13:45:55.357137 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10310 13:45:55.357204 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10311 13:45:55.438813
10312 13:45:55.442682 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10313 13:45:55.445959 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10314 13:45:55.446088 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10315 13:45:55.446189 Setting prompt string to []
10316 13:45:55.446294 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10317 13:45:55.446396 Using line separator: #'\n'#
10318 13:45:55.446482 No login prompt set.
10319 13:45:55.446574 Parsing kernel messages
10320 13:45:55.446656 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10321 13:45:55.446827 [login-action] Waiting for messages, (timeout 00:03:53)
10322 13:45:55.446920 Waiting using forced prompt support (timeout 00:01:56)
10323 13:45:55.465570 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10324 13:45:55.469035 [ 0.000000] random: crng init done
10325 13:45:55.475413 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 13:45:55.478885 [ 0.000000] efi: UEFI not found.
10327 13:45:55.485123 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 13:45:55.492192 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 13:45:55.501839 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 13:45:55.512060 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 13:45:55.518758 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 13:45:55.525046 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 13:45:55.531913 [ 0.000000] NUMA: No NUMA configuration found
10334 13:45:55.538296 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 13:45:55.541997 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10336 13:45:55.545435 [ 0.000000] Zone ranges:
10337 13:45:55.551809 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 13:45:55.555087 [ 0.000000] DMA32 empty
10339 13:45:55.561782 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 13:45:55.565389 [ 0.000000] Movable zone start for each node
10341 13:45:55.568104 [ 0.000000] Early memory node ranges
10342 13:45:55.575121 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 13:45:55.581263 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 13:45:55.588343 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 13:45:55.594618 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 13:45:55.598223 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 13:45:55.607526 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 13:45:55.662902 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 13:45:55.670121 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 13:45:55.676652 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 13:45:55.679954 [ 0.000000] psci: probing for conduit method from DT.
10352 13:45:55.686730 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 13:45:55.690050 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 13:45:55.696387 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 13:45:55.699543 [ 0.000000] psci: SMC Calling Convention v1.2
10356 13:45:55.706049 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10357 13:45:55.709640 [ 0.000000] Detected VIPT I-cache on CPU0
10358 13:45:55.715855 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 13:45:55.723035 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 13:45:55.729365 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 13:45:55.735712 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 13:45:55.745688 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 13:45:55.752771 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 13:45:55.756057 [ 0.000000] alternatives: applying boot alternatives
10365 13:45:55.762471 [ 0.000000] Fallback order for Node 0: 0
10366 13:45:55.768897 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 13:45:55.772485 [ 0.000000] Policy zone: Normal
10368 13:45:55.795280 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10369 13:45:55.805266 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 13:45:55.816114 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 13:45:55.826794 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 13:45:55.833061 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 13:45:55.836462 <6>[ 0.000000] software IO TLB: area num 8.
10374 13:45:55.892237 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 13:45:56.041753 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10376 13:45:56.048535 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10377 13:45:56.055001 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10378 13:45:56.057864 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10379 13:45:56.064946 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10380 13:45:56.071299 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10381 13:45:56.074684 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10382 13:45:56.084363 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10383 13:45:56.091098 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10384 13:45:56.098040 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10385 13:45:56.104244 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10386 13:45:56.107859 <6>[ 0.000000] GICv3: 608 SPIs implemented
10387 13:45:56.111325 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10388 13:45:56.117745 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10389 13:45:56.120678 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10390 13:45:56.127628 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10391 13:45:56.140526 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10392 13:45:56.153822 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10393 13:45:56.160857 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10394 13:45:56.168518 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10395 13:45:56.181210 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10396 13:45:56.188066 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10397 13:45:56.194816 <6>[ 0.009178] Console: colour dummy device 80x25
10398 13:45:56.204475 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10399 13:45:56.207895 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10400 13:45:56.214647 <6>[ 0.029249] LSM: Security Framework initializing
10401 13:45:56.221671 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 13:45:56.231404 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 13:45:56.237758 <6>[ 0.051413] cblist_init_generic: Setting adjustable number of callback queues.
10404 13:45:56.244782 <6>[ 0.058857] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 13:45:56.254846 <6>[ 0.065235] cblist_init_generic: Setting adjustable number of callback queues.
10406 13:45:56.257580 <6>[ 0.072662] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 13:45:56.264306 <6>[ 0.079064] rcu: Hierarchical SRCU implementation.
10408 13:45:56.271436 <6>[ 0.084103] rcu: Max phase no-delay instances is 1000.
10409 13:45:56.277866 <6>[ 0.091166] EFI services will not be available.
10410 13:45:56.281101 <6>[ 0.096126] smp: Bringing up secondary CPUs ...
10411 13:45:56.288923 <6>[ 0.101204] Detected VIPT I-cache on CPU1
10412 13:45:56.296024 <6>[ 0.101275] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10413 13:45:56.302275 <6>[ 0.101307] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10414 13:45:56.305795 <6>[ 0.101645] Detected VIPT I-cache on CPU2
10415 13:45:56.312545 <6>[ 0.101698] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10416 13:45:56.319032 <6>[ 0.101714] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10417 13:45:56.326012 <6>[ 0.101972] Detected VIPT I-cache on CPU3
10418 13:45:56.332264 <6>[ 0.102019] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10419 13:45:56.338528 <6>[ 0.102033] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10420 13:45:56.342100 <6>[ 0.102335] CPU features: detected: Spectre-v4
10421 13:45:56.348540 <6>[ 0.102342] CPU features: detected: Spectre-BHB
10422 13:45:56.352159 <6>[ 0.102347] Detected PIPT I-cache on CPU4
10423 13:45:56.358672 <6>[ 0.102404] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10424 13:45:56.365839 <6>[ 0.102420] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10425 13:45:56.372257 <6>[ 0.102713] Detected PIPT I-cache on CPU5
10426 13:45:56.378461 <6>[ 0.102777] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10427 13:45:56.385224 <6>[ 0.102793] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10428 13:45:56.388520 <6>[ 0.103077] Detected PIPT I-cache on CPU6
10429 13:45:56.395632 <6>[ 0.103145] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10430 13:45:56.401989 <6>[ 0.103161] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10431 13:45:56.405061 <6>[ 0.103458] Detected PIPT I-cache on CPU7
10432 13:45:56.414994 <6>[ 0.103523] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10433 13:45:56.421888 <6>[ 0.103538] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10434 13:45:56.425052 <6>[ 0.103586] smp: Brought up 1 node, 8 CPUs
10435 13:45:56.428283 <6>[ 0.244783] SMP: Total of 8 processors activated.
10436 13:45:56.435122 <6>[ 0.249704] CPU features: detected: 32-bit EL0 Support
10437 13:45:56.444905 <6>[ 0.255101] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10438 13:45:56.452787 <6>[ 0.263901] CPU features: detected: Common not Private translations
10439 13:45:56.454993 <6>[ 0.270377] CPU features: detected: CRC32 instructions
10440 13:45:56.461419 <6>[ 0.275728] CPU features: detected: RCpc load-acquire (LDAPR)
10441 13:45:56.468384 <6>[ 0.281688] CPU features: detected: LSE atomic instructions
10442 13:45:56.474854 <6>[ 0.287468] CPU features: detected: Privileged Access Never
10443 13:45:56.478347 <6>[ 0.293248] CPU features: detected: RAS Extension Support
10444 13:45:56.488081 <6>[ 0.298891] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10445 13:45:56.491464 <6>[ 0.306112] CPU: All CPU(s) started at EL2
10446 13:45:56.497909 <6>[ 0.310455] alternatives: applying system-wide alternatives
10447 13:45:56.506664 <6>[ 0.321301] devtmpfs: initialized
10448 13:45:56.518994 <6>[ 0.330402] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10449 13:45:56.529061 <6>[ 0.340365] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10450 13:45:56.535929 <6>[ 0.348387] pinctrl core: initialized pinctrl subsystem
10451 13:45:56.539159 <6>[ 0.355071] DMI not present or invalid.
10452 13:45:56.545528 <6>[ 0.359483] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10453 13:45:56.555407 <6>[ 0.366306] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10454 13:45:56.561792 <6>[ 0.373900] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10455 13:45:56.572291 <6>[ 0.382117] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10456 13:45:56.575144 <6>[ 0.390360] audit: initializing netlink subsys (disabled)
10457 13:45:56.585187 <5>[ 0.396052] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10458 13:45:56.591591 <6>[ 0.396765] thermal_sys: Registered thermal governor 'step_wise'
10459 13:45:56.598810 <6>[ 0.404016] thermal_sys: Registered thermal governor 'power_allocator'
10460 13:45:56.602191 <6>[ 0.410271] cpuidle: using governor menu
10461 13:45:56.608329 <6>[ 0.421230] NET: Registered PF_QIPCRTR protocol family
10462 13:45:56.615489 <6>[ 0.426719] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10463 13:45:56.618389 <6>[ 0.433822] ASID allocator initialised with 32768 entries
10464 13:45:56.625549 <6>[ 0.440416] Serial: AMBA PL011 UART driver
10465 13:45:56.634595 <4>[ 0.449274] Trying to register duplicate clock ID: 134
10466 13:45:56.694305 <6>[ 0.512610] KASLR enabled
10467 13:45:56.709392 <6>[ 0.520429] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10468 13:45:56.716013 <6>[ 0.527443] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10469 13:45:56.722315 <6>[ 0.533929] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10470 13:45:56.728908 <6>[ 0.540934] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10471 13:45:56.735403 <6>[ 0.547420] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10472 13:45:56.742385 <6>[ 0.554423] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10473 13:45:56.748893 <6>[ 0.560913] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10474 13:45:56.755980 <6>[ 0.567918] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10475 13:45:56.759278 <6>[ 0.575457] ACPI: Interpreter disabled.
10476 13:45:56.767744 <6>[ 0.581909] iommu: Default domain type: Translated
10477 13:45:56.773658 <6>[ 0.587021] iommu: DMA domain TLB invalidation policy: strict mode
10478 13:45:56.776940 <5>[ 0.593682] SCSI subsystem initialized
10479 13:45:56.783918 <6>[ 0.597846] usbcore: registered new interface driver usbfs
10480 13:45:56.790410 <6>[ 0.603578] usbcore: registered new interface driver hub
10481 13:45:56.793507 <6>[ 0.609128] usbcore: registered new device driver usb
10482 13:45:56.800866 <6>[ 0.615236] pps_core: LinuxPPS API ver. 1 registered
10483 13:45:56.810516 <6>[ 0.620428] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10484 13:45:56.814096 <6>[ 0.629774] PTP clock support registered
10485 13:45:56.817598 <6>[ 0.634016] EDAC MC: Ver: 3.0.0
10486 13:45:56.824895 <6>[ 0.639177] FPGA manager framework
10487 13:45:56.828263 <6>[ 0.642865] Advanced Linux Sound Architecture Driver Initialized.
10488 13:45:56.832024 <6>[ 0.649648] vgaarb: loaded
10489 13:45:56.838513 <6>[ 0.652811] clocksource: Switched to clocksource arch_sys_counter
10490 13:45:56.844861 <5>[ 0.659253] VFS: Disk quotas dquot_6.6.0
10491 13:45:56.851893 <6>[ 0.663439] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10492 13:45:56.854748 <6>[ 0.670631] pnp: PnP ACPI: disabled
10493 13:45:56.862840 <6>[ 0.677368] NET: Registered PF_INET protocol family
10494 13:45:56.872746 <6>[ 0.682965] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10495 13:45:56.884145 <6>[ 0.695281] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10496 13:45:56.894320 <6>[ 0.704097] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10497 13:45:56.900675 <6>[ 0.712068] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10498 13:45:56.907183 <6>[ 0.720768] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10499 13:45:56.919053 <6>[ 0.730520] TCP: Hash tables configured (established 65536 bind 65536)
10500 13:45:56.925919 <6>[ 0.737387] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 13:45:56.932582 <6>[ 0.744584] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10502 13:45:56.939471 <6>[ 0.752290] NET: Registered PF_UNIX/PF_LOCAL protocol family
10503 13:45:56.945917 <6>[ 0.758449] RPC: Registered named UNIX socket transport module.
10504 13:45:56.949415 <6>[ 0.764602] RPC: Registered udp transport module.
10505 13:45:56.955870 <6>[ 0.769534] RPC: Registered tcp transport module.
10506 13:45:56.962364 <6>[ 0.774466] RPC: Registered tcp NFSv4.1 backchannel transport module.
10507 13:45:56.965894 <6>[ 0.781131] PCI: CLS 0 bytes, default 64
10508 13:45:56.968810 <6>[ 0.785456] Unpacking initramfs...
10509 13:45:56.985760 <6>[ 0.797331] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10510 13:45:56.995781 <6>[ 0.805979] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10511 13:45:56.999069 <6>[ 0.814803] kvm [1]: IPA Size Limit: 40 bits
10512 13:45:57.006167 <6>[ 0.819329] kvm [1]: GICv3: no GICV resource entry
10513 13:45:57.009037 <6>[ 0.824349] kvm [1]: disabling GICv2 emulation
10514 13:45:57.016037 <6>[ 0.829036] kvm [1]: GIC system register CPU interface enabled
10515 13:45:57.018972 <6>[ 0.835195] kvm [1]: vgic interrupt IRQ18
10516 13:45:57.025874 <6>[ 0.839553] kvm [1]: VHE mode initialized successfully
10517 13:45:57.032620 <5>[ 0.846042] Initialise system trusted keyrings
10518 13:45:57.038917 <6>[ 0.850873] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10519 13:45:57.046549 <6>[ 0.861013] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10520 13:45:57.052826 <5>[ 0.867427] NFS: Registering the id_resolver key type
10521 13:45:57.056537 <5>[ 0.872728] Key type id_resolver registered
10522 13:45:57.062701 <5>[ 0.877146] Key type id_legacy registered
10523 13:45:57.069296 <6>[ 0.881433] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10524 13:45:57.075794 <6>[ 0.888353] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10525 13:45:57.082889 <6>[ 0.896073] 9p: Installing v9fs 9p2000 file system support
10526 13:45:57.119215 <5>[ 0.933785] Key type asymmetric registered
10527 13:45:57.122706 <5>[ 0.938119] Asymmetric key parser 'x509' registered
10528 13:45:57.132365 <6>[ 0.943265] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10529 13:45:57.135967 <6>[ 0.950877] io scheduler mq-deadline registered
10530 13:45:57.138774 <6>[ 0.955653] io scheduler kyber registered
10531 13:45:57.157959 <6>[ 0.972784] EINJ: ACPI disabled.
10532 13:45:57.191412 <4>[ 0.999322] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 13:45:57.201158 <4>[ 1.009984] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10534 13:45:57.216448 <6>[ 1.031140] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10535 13:45:57.224240 <6>[ 1.039150] printk: console [ttyS0] disabled
10536 13:45:57.252846 <6>[ 1.063787] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10537 13:45:57.259243 <6>[ 1.073271] printk: console [ttyS0] enabled
10538 13:45:57.262888 <6>[ 1.073271] printk: console [ttyS0] enabled
10539 13:45:57.269468 <6>[ 1.082167] printk: bootconsole [mtk8250] disabled
10540 13:45:57.272685 <6>[ 1.082167] printk: bootconsole [mtk8250] disabled
10541 13:45:57.278784 <6>[ 1.093503] SuperH (H)SCI(F) driver initialized
10542 13:45:57.282123 <6>[ 1.098780] msm_serial: driver initialized
10543 13:45:57.296785 <6>[ 1.107842] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10544 13:45:57.306930 <6>[ 1.116393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10545 13:45:57.313180 <6>[ 1.124937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10546 13:45:57.323096 <6>[ 1.133566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10547 13:45:57.330073 <6>[ 1.142272] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10548 13:45:57.339896 <6>[ 1.150988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10549 13:45:57.349566 <6>[ 1.159537] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10550 13:45:57.356534 <6>[ 1.168340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10551 13:45:57.366492 <6>[ 1.176887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10552 13:45:57.377927 <6>[ 1.192732] loop: module loaded
10553 13:45:57.384623 <6>[ 1.198816] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10554 13:45:57.408042 <4>[ 1.222408] mtk-pmic-keys: Failed to locate of_node [id: -1]
10555 13:45:57.414738 <6>[ 1.229521] megasas: 07.719.03.00-rc1
10556 13:45:57.424539 <6>[ 1.239276] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10557 13:45:57.433818 <6>[ 1.248233] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10558 13:45:57.450566 <6>[ 1.265010] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10559 13:45:57.506955 <6>[ 1.315167] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10560 13:45:57.760699 <6>[ 1.575229] Freeing initrd memory: 18288K
10561 13:45:57.772104 <6>[ 1.586901] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10562 13:45:57.783443 <6>[ 1.598032] tun: Universal TUN/TAP device driver, 1.6
10563 13:45:57.786937 <6>[ 1.604110] thunder_xcv, ver 1.0
10564 13:45:57.790258 <6>[ 1.607618] thunder_bgx, ver 1.0
10565 13:45:57.793374 <6>[ 1.611114] nicpf, ver 1.0
10566 13:45:57.803473 <6>[ 1.615146] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10567 13:45:57.807247 <6>[ 1.622622] hns3: Copyright (c) 2017 Huawei Corporation.
10568 13:45:57.810561 <6>[ 1.628214] hclge is initializing
10569 13:45:57.817607 <6>[ 1.631796] e1000: Intel(R) PRO/1000 Network Driver
10570 13:45:57.823953 <6>[ 1.636925] e1000: Copyright (c) 1999-2006 Intel Corporation.
10571 13:45:57.827509 <6>[ 1.642939] e1000e: Intel(R) PRO/1000 Network Driver
10572 13:45:57.834043 <6>[ 1.648155] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10573 13:45:57.840980 <6>[ 1.654343] igb: Intel(R) Gigabit Ethernet Network Driver
10574 13:45:57.847265 <6>[ 1.659995] igb: Copyright (c) 2007-2014 Intel Corporation.
10575 13:45:57.853769 <6>[ 1.665833] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10576 13:45:57.856941 <6>[ 1.672350] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10577 13:45:57.863612 <6>[ 1.678812] sky2: driver version 1.30
10578 13:45:57.870636 <6>[ 1.683753] usbcore: registered new device driver r8152-cfgselector
10579 13:45:57.877219 <6>[ 1.690291] usbcore: registered new interface driver r8152
10580 13:45:57.880565 <6>[ 1.696111] VFIO - User Level meta-driver version: 0.3
10581 13:45:57.889859 <6>[ 1.704363] usbcore: registered new interface driver usb-storage
10582 13:45:57.896253 <6>[ 1.710813] usbcore: registered new device driver onboard-usb-hub
10583 13:45:57.905228 <6>[ 1.719984] mt6397-rtc mt6359-rtc: registered as rtc0
10584 13:45:57.915418 <6>[ 1.725449] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:41:17 UTC (1716903677)
10585 13:45:57.918540 <6>[ 1.735018] i2c_dev: i2c /dev entries driver
10586 13:45:57.935398 <6>[ 1.746913] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10587 13:45:57.942269 <4>[ 1.755647] cpu cpu0: supply cpu not found, using dummy regulator
10588 13:45:57.948820 <4>[ 1.762077] cpu cpu1: supply cpu not found, using dummy regulator
10589 13:45:57.955501 <4>[ 1.768480] cpu cpu2: supply cpu not found, using dummy regulator
10590 13:45:57.962872 <4>[ 1.774880] cpu cpu3: supply cpu not found, using dummy regulator
10591 13:45:57.969090 <4>[ 1.781299] cpu cpu4: supply cpu not found, using dummy regulator
10592 13:45:57.972433 <4>[ 1.787697] cpu cpu5: supply cpu not found, using dummy regulator
10593 13:45:57.979759 <4>[ 1.794095] cpu cpu6: supply cpu not found, using dummy regulator
10594 13:45:57.986441 <4>[ 1.800490] cpu cpu7: supply cpu not found, using dummy regulator
10595 13:45:58.006574 <6>[ 1.821112] cpu cpu0: EM: created perf domain
10596 13:45:58.009435 <6>[ 1.826064] cpu cpu4: EM: created perf domain
10597 13:45:58.017259 <6>[ 1.831729] sdhci: Secure Digital Host Controller Interface driver
10598 13:45:58.023773 <6>[ 1.838162] sdhci: Copyright(c) Pierre Ossman
10599 13:45:58.030139 <6>[ 1.843121] Synopsys Designware Multimedia Card Interface Driver
10600 13:45:58.037120 <6>[ 1.849757] sdhci-pltfm: SDHCI platform and OF driver helper
10601 13:45:58.040061 <6>[ 1.849813] mmc0: CQHCI version 5.10
10602 13:45:58.047199 <6>[ 1.860114] ledtrig-cpu: registered to indicate activity on CPUs
10603 13:45:58.053717 <6>[ 1.867236] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10604 13:45:58.060233 <6>[ 1.874302] usbcore: registered new interface driver usbhid
10605 13:45:58.063198 <6>[ 1.880124] usbhid: USB HID core driver
10606 13:45:58.069820 <6>[ 1.884318] spi_master spi0: will run message pump with realtime priority
10607 13:45:58.116512 <6>[ 1.924479] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10608 13:45:58.136008 <6>[ 1.940258] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10609 13:45:58.142539 <6>[ 1.955130] cros-ec-spi spi0.0: Chrome EC device registered
10610 13:45:58.146026 <6>[ 1.961253] mmc0: Command Queue Engine enabled
10611 13:45:58.152572 <6>[ 1.966066] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10612 13:45:58.159089 <6>[ 1.973571] mmcblk0: mmc0:0001 DA4128 116 GiB
10613 13:45:58.169160 <6>[ 1.975384] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10614 13:45:58.172588 <6>[ 1.983669] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 13:45:58.179739 <6>[ 1.988785] NET: Registered PF_PACKET protocol family
10616 13:45:58.182813 <6>[ 1.994950] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10617 13:45:58.189333 <6>[ 1.998911] 9pnet: Installing 9P2000 support
10618 13:45:58.192697 <6>[ 2.004690] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10619 13:45:58.199187 <5>[ 2.008597] Key type dns_resolver registered
10620 13:45:58.205928 <6>[ 2.014460] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10621 13:45:58.209445 <6>[ 2.018859] registered taskstats version 1
10622 13:45:58.215941 <5>[ 2.029190] Loading compiled-in X.509 certificates
10623 13:45:58.243837 <4>[ 2.051849] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10624 13:45:58.253645 <4>[ 2.062559] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 13:45:58.267382 <6>[ 2.082038] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10626 13:45:58.274415 <6>[ 2.088945] xhci-mtk 11200000.usb: xHCI Host Controller
10627 13:45:58.280773 <6>[ 2.094466] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10628 13:45:58.291194 <6>[ 2.102318] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10629 13:45:58.297642 <6>[ 2.111751] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10630 13:45:58.304468 <6>[ 2.117984] xhci-mtk 11200000.usb: xHCI Host Controller
10631 13:45:58.310930 <6>[ 2.123486] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10632 13:45:58.317370 <6>[ 2.131140] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10633 13:45:58.324158 <6>[ 2.138947] hub 1-0:1.0: USB hub found
10634 13:45:58.328017 <6>[ 2.142976] hub 1-0:1.0: 1 port detected
10635 13:45:58.334374 <6>[ 2.147267] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10636 13:45:58.341470 <6>[ 2.155975] hub 2-0:1.0: USB hub found
10637 13:45:58.344262 <6>[ 2.159997] hub 2-0:1.0: 1 port detected
10638 13:45:58.352116 <6>[ 2.167032] mtk-msdc 11f70000.mmc: Got CD GPIO
10639 13:45:58.365772 <6>[ 2.177186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10640 13:45:58.372213 <6>[ 2.185207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10641 13:45:58.382211 <4>[ 2.193138] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10642 13:45:58.392694 <6>[ 2.202667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10643 13:45:58.399002 <6>[ 2.210744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10644 13:45:58.405899 <6>[ 2.218879] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10645 13:45:58.415531 <6>[ 2.226810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10646 13:45:58.422233 <6>[ 2.234628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10647 13:45:58.432294 <6>[ 2.242443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10648 13:45:58.442821 <6>[ 2.252916] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10649 13:45:58.449292 <6>[ 2.261286] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10650 13:45:58.458929 <6>[ 2.269625] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10651 13:45:58.466045 <6>[ 2.277963] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10652 13:45:58.476124 <6>[ 2.286301] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10653 13:45:58.482413 <6>[ 2.294638] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10654 13:45:58.492670 <6>[ 2.302988] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10655 13:45:58.499062 <6>[ 2.311326] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10656 13:45:58.508859 <6>[ 2.319665] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10657 13:45:58.515670 <6>[ 2.328002] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10658 13:45:58.525675 <6>[ 2.336339] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10659 13:45:58.532567 <6>[ 2.344676] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10660 13:45:58.542048 <6>[ 2.353014] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10661 13:45:58.549367 <6>[ 2.361352] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10662 13:45:58.558724 <6>[ 2.369691] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10663 13:45:58.565489 <6>[ 2.378432] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10664 13:45:58.572177 <6>[ 2.385579] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10665 13:45:58.578539 <6>[ 2.392356] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10666 13:45:58.585008 <6>[ 2.399119] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10667 13:45:58.591903 <6>[ 2.406050] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10668 13:45:58.601582 <6>[ 2.412900] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10669 13:45:58.611644 <6>[ 2.422029] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10670 13:45:58.621506 <6>[ 2.431151] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10671 13:45:58.631731 <6>[ 2.440445] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10672 13:45:58.638397 <6>[ 2.449912] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10673 13:45:58.648471 <6>[ 2.459379] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10674 13:45:58.658445 <6>[ 2.468499] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10675 13:45:58.668083 <6>[ 2.477965] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10676 13:45:58.678175 <6>[ 2.487083] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10677 13:45:58.688309 <6>[ 2.496377] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10678 13:45:58.697668 <6>[ 2.506562] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10679 13:45:58.707899 <6>[ 2.518568] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10680 13:45:58.714378 <6>[ 2.527849] Trying to probe devices needed for running init ...
10681 13:45:58.733504 <6>[ 2.545144] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10682 13:45:58.762075 <6>[ 2.576752] hub 2-1:1.0: USB hub found
10683 13:45:58.765295 <6>[ 2.581235] hub 2-1:1.0: 3 ports detected
10684 13:45:58.773914 <6>[ 2.588491] hub 2-1:1.0: USB hub found
10685 13:45:58.776606 <6>[ 2.592931] hub 2-1:1.0: 3 ports detected
10686 13:45:58.885748 <6>[ 2.697081] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 13:45:59.039855 <6>[ 2.854903] hub 1-1:1.0: USB hub found
10688 13:45:59.043413 <6>[ 2.859356] hub 1-1:1.0: 4 ports detected
10689 13:45:59.054097 <6>[ 2.868588] hub 1-1:1.0: USB hub found
10690 13:45:59.057247 <6>[ 2.873087] hub 1-1:1.0: 4 ports detected
10691 13:45:59.126109 <6>[ 2.937364] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 13:45:59.235254 <6>[ 3.045768] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10693 13:45:59.270964 <4>[ 3.082281] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10694 13:45:59.280908 <4>[ 3.091398] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10695 13:45:59.325019 <6>[ 3.138720] r8152 2-1.3:1.0 eth0: v1.12.13
10696 13:45:59.377648 <6>[ 3.189128] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10697 13:45:59.511209 <6>[ 3.325121] hub 1-1.4:1.0: USB hub found
10698 13:45:59.513805 <6>[ 3.329798] hub 1-1.4:1.0: 2 ports detected
10699 13:45:59.524166 <6>[ 3.338485] hub 1-1.4:1.0: USB hub found
10700 13:45:59.527795 <6>[ 3.343094] hub 1-1.4:1.0: 2 ports detected
10701 13:45:59.829866 <6>[ 3.640938] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10702 13:46:00.021450 <6>[ 3.832937] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10703 13:46:00.936233 <6>[ 4.751399] r8152 2-1.3:1.0 eth0: carrier on
10704 13:46:03.477641 <5>[ 4.780870] Sending DHCP requests .., OK
10705 13:46:03.484553 <6>[ 7.297348] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10706 13:46:03.487945 <6>[ 7.305645] IP-Config: Complete:
10707 13:46:03.500466 <6>[ 7.309150] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10708 13:46:03.507530 <6>[ 7.319860] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10709 13:46:03.513831 <6>[ 7.328479] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10710 13:46:03.520875 <6>[ 7.328489] nameserver0=192.168.201.1
10711 13:46:03.523729 <6>[ 7.340667] clk: Disabling unused clocks
10712 13:46:03.527251 <6>[ 7.346163] ALSA device list:
10713 13:46:03.534209 <6>[ 7.349413] No soundcards found.
10714 13:46:03.541957 <6>[ 7.357068] Freeing unused kernel memory: 8512K
10715 13:46:03.544950 <6>[ 7.362038] Run /init as init process
10716 13:46:03.555132 Loading, please wait...
10717 13:46:03.581425 Starting systemd-udevd version 252.22-1~deb12u1
10718 13:46:03.830339 <6>[ 7.642124] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10719 13:46:03.839927 <6>[ 7.650269] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10720 13:46:03.846725 <3>[ 7.655800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 13:46:03.856902 <6>[ 7.658991] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 13:46:03.863209 <6>[ 7.660704] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10723 13:46:03.870349 <3>[ 7.667289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 13:46:03.876527 <4>[ 7.676588] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10725 13:46:03.886920 <6>[ 7.676970] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10726 13:46:03.890292 <6>[ 7.679133] remoteproc remoteproc0: scp is available
10727 13:46:03.896805 <6>[ 7.680212] remoteproc remoteproc0: powering up scp
10728 13:46:03.903018 <6>[ 7.680218] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10729 13:46:03.910608 <6>[ 7.680237] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10730 13:46:03.917597 <3>[ 7.683170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 13:46:03.927615 <3>[ 7.685929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 13:46:03.931076 <6>[ 7.687199] mc: Linux media interface: v0.10
10733 13:46:03.940460 <4>[ 7.704863] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10734 13:46:03.943881 <4>[ 7.704863] Fallback method does not support PEC.
10735 13:46:03.954038 <3>[ 7.706432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 13:46:03.960432 <4>[ 7.722235] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10737 13:46:03.970671 <3>[ 7.725303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 13:46:03.977027 <3>[ 7.725355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 13:46:03.983799 <3>[ 7.725369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 13:46:03.993643 <3>[ 7.726066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 13:46:04.000322 <6>[ 7.726950] videodev: Linux video capture interface: v2.00
10742 13:46:04.007031 <3>[ 7.737337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10743 13:46:04.016661 <3>[ 7.739599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 13:46:04.023789 <6>[ 7.778143] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10745 13:46:04.029802 <3>[ 7.781358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 13:46:04.036920 <6>[ 7.789382] pci_bus 0000:00: root bus resource [bus 00-ff]
10747 13:46:04.043428 <3>[ 7.797569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 13:46:04.053357 <6>[ 7.805733] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10749 13:46:04.059758 <6>[ 7.808950] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10750 13:46:04.066581 <6>[ 7.813724] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10751 13:46:04.076268 <3>[ 7.813816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 13:46:04.083278 <3>[ 7.813821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 13:46:04.093066 <3>[ 7.813824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 13:46:04.099696 <3>[ 7.813831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 13:46:04.106691 <3>[ 7.813834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 13:46:04.116777 <3>[ 7.813859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 13:46:04.126476 <6>[ 7.819413] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10758 13:46:04.137012 <6>[ 7.822846] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10759 13:46:04.144081 <6>[ 7.823239] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10760 13:46:04.150422 <6>[ 7.828239] remoteproc remoteproc0: remote processor scp is now up
10761 13:46:04.156903 <6>[ 7.836491] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10762 13:46:04.166845 <6>[ 7.841911] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10763 13:46:04.173280 <6>[ 7.859414] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10764 13:46:04.183309 <6>[ 7.865062] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10765 13:46:04.186540 <6>[ 7.865588] Bluetooth: Core ver 2.22
10766 13:46:04.193277 <6>[ 7.865645] NET: Registered PF_BLUETOOTH protocol family
10767 13:46:04.200281 <6>[ 7.865646] Bluetooth: HCI device and connection manager initialized
10768 13:46:04.203387 <6>[ 7.865662] Bluetooth: HCI socket layer initialized
10769 13:46:04.210145 <6>[ 7.865678] Bluetooth: L2CAP socket layer initialized
10770 13:46:04.212956 <6>[ 7.865684] Bluetooth: SCO socket layer initialized
10771 13:46:04.222885 <6>[ 7.874779] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10772 13:46:04.226240 <6>[ 7.879305] pci 0000:00:00.0: supports D1 D2
10773 13:46:04.233164 <6>[ 7.896820] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10774 13:46:04.239396 <6>[ 7.903905] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 13:46:04.249787 <6>[ 7.905642] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10776 13:46:04.262531 <6>[ 7.913377] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10777 13:46:04.269635 <6>[ 7.920188] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10778 13:46:04.272477 <6>[ 7.928416] usbcore: registered new interface driver uvcvideo
10779 13:46:04.282333 <6>[ 7.936269] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10780 13:46:04.285836 <6>[ 7.936919] usbcore: registered new interface driver btusb
10781 13:46:04.292862 <6>[ 7.937147] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10782 13:46:04.302028 <4>[ 7.938312] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10783 13:46:04.309007 <3>[ 7.938325] Bluetooth: hci0: Failed to load firmware file (-2)
10784 13:46:04.315768 <3>[ 7.938328] Bluetooth: hci0: Failed to set up firmware (-2)
10785 13:46:04.325227 <4>[ 7.938333] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10786 13:46:04.335194 <3>[ 7.950561] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 13:46:04.341807 <6>[ 7.956246] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10788 13:46:04.348939 <6>[ 8.162838] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10789 13:46:04.355337 <6>[ 8.170426] pci 0000:01:00.0: supports D1 D2
10790 13:46:04.361737 <6>[ 8.174948] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10791 13:46:04.380975 <6>[ 8.192856] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10792 13:46:04.387317 <6>[ 8.199743] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10793 13:46:04.394079 <6>[ 8.207822] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10794 13:46:04.403787 <6>[ 8.215821] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10795 13:46:04.410553 <6>[ 8.223822] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10796 13:46:04.420726 <6>[ 8.231822] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10797 13:46:04.424187 <6>[ 8.239822] pci 0000:00:00.0: PCI bridge to [bus 01]
10798 13:46:04.433539 <6>[ 8.245037] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10799 13:46:04.440601 <6>[ 8.253139] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10800 13:46:04.446596 <6>[ 8.259949] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10801 13:46:04.453441 <6>[ 8.266553] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10802 13:46:04.468682 <5>[ 8.280512] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10803 13:46:04.492456 <5>[ 8.304720] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10804 13:46:04.499252 <5>[ 8.312163] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10805 13:46:04.509292 <4>[ 8.320627] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10806 13:46:04.512784 <6>[ 8.329514] cfg80211: failed to load regulatory.db
10807 13:46:04.562095 <6>[ 8.374291] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10808 13:46:04.568791 <6>[ 8.381814] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10809 13:46:04.592938 <6>[ 8.408483] mt7921e 0000:01:00.0: ASIC revision: 79610010
10810 13:46:04.697217 <6>[ 8.509108] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10811 13:46:04.700050 <6>[ 8.509108]
10812 13:46:04.707756 Begin: Loading essential drivers ... done.
10813 13:46:04.711123 Begin: Running /scripts/init-premount ... done.
10814 13:46:04.717510 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10815 13:46:04.727229 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10816 13:46:04.730749 Device /sys/class/net/eth0 found
10817 13:46:04.730828 done.
10818 13:46:04.737190 Begin: Waiting up to 180 secs for any network device to become available ... done.
10819 13:46:04.793479 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10820 13:46:04.800284 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10821 13:46:04.806727 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10822 13:46:04.813885 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10823 13:46:04.820099 host : mt8192-asurada-spherion-r0-cbg-0
10824 13:46:04.827125 domain : lava-rack
10825 13:46:04.829929 rootserver: 192.168.201.1 rootpath:
10826 13:46:04.830011 filename :
10827 13:46:04.966925 <6>[ 8.779433] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10828 13:46:05.005301 done.
10829 13:46:05.012067 Begin: Running /scripts/nfs-bottom ... done.
10830 13:46:05.026529 Begin: Running /scripts/init-bottom ... done.
10831 13:46:06.334795 <6>[ 10.150789] NET: Registered PF_INET6 protocol family
10832 13:46:06.342498 <6>[ 10.158231] Segment Routing with IPv6
10833 13:46:06.346031 <6>[ 10.162233] In-situ OAM (IOAM) with IPv6
10834 13:46:06.512884 <30>[ 10.302305] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10835 13:46:06.519421 <30>[ 10.335420] systemd[1]: Detected architecture arm64.
10836 13:46:06.526386
10837 13:46:06.529373 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10838 13:46:06.529453
10839 13:46:06.557902 <30>[ 10.373888] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10840 13:46:07.489798 <30>[ 11.302308] systemd[1]: Queued start job for default target graphical.target.
10841 13:46:07.525288 <30>[ 11.337806] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10842 13:46:07.532376 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10843 13:46:07.554416 <30>[ 11.366835] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10844 13:46:07.561004 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10845 13:46:07.582421 <30>[ 11.394876] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10846 13:46:07.592290 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10847 13:46:07.610168 <30>[ 11.422521] systemd[1]: Created slice user.slice - User and Session Slice.
10848 13:46:07.617091 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10849 13:46:07.640755 <30>[ 11.449973] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10850 13:46:07.650615 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10851 13:46:07.668241 <30>[ 11.477335] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10852 13:46:07.674742 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10853 13:46:07.703546 <30>[ 11.505763] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10854 13:46:07.712979 <30>[ 11.525683] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10855 13:46:07.719655 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10856 13:46:07.736857 <30>[ 11.549504] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10857 13:46:07.746718 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10858 13:46:07.765230 <30>[ 11.577631] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10859 13:46:07.775207 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10860 13:46:07.789553 <30>[ 11.605646] systemd[1]: Reached target paths.target - Path Units.
10861 13:46:07.800231 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10862 13:46:07.817119 <30>[ 11.629484] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10863 13:46:07.823988 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10864 13:46:07.837283 <30>[ 11.653082] systemd[1]: Reached target slices.target - Slice Units.
10865 13:46:07.847342 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10866 13:46:07.861918 <30>[ 11.677604] systemd[1]: Reached target swap.target - Swaps.
10867 13:46:07.868377 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10868 13:46:07.888849 <30>[ 11.701605] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10869 13:46:07.899322 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10870 13:46:07.917101 <30>[ 11.729563] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10871 13:46:07.926988 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10872 13:46:07.946890 <30>[ 11.759925] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10873 13:46:07.957252 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10874 13:46:07.974108 <30>[ 11.786446] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10875 13:46:07.983629 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10876 13:46:08.001593 <30>[ 11.813783] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10877 13:46:08.007899 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10878 13:46:08.025533 <30>[ 11.838430] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10879 13:46:08.035464 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10880 13:46:08.055475 <30>[ 11.868183] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10881 13:46:08.065479 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10882 13:46:08.081206 <30>[ 11.893574] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10883 13:46:08.090490 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10884 13:46:08.149245 <30>[ 11.961562] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10885 13:46:08.155717 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10886 13:46:08.175524 <30>[ 11.987863] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10887 13:46:08.181740 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10888 13:46:08.203925 <30>[ 12.016330] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10889 13:46:08.210211 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10890 13:46:08.235725 <30>[ 12.041798] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10891 13:46:08.250837 <30>[ 12.063625] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10892 13:46:08.261171 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10893 13:46:08.282474 <30>[ 12.094863] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10894 13:46:08.289186 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10895 13:46:08.313985 <30>[ 12.126659] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10896 13:46:08.320521 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10897 13:46:08.353114 <6>[ 12.166034] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10898 13:46:08.381779 <30>[ 12.194145] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10899 13:46:08.388056 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10900 13:46:08.414745 <30>[ 12.226901] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10901 13:46:08.421196 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10902 13:46:08.446014 <30>[ 12.258736] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10903 13:46:08.452498 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10904 13:46:08.478443 <30>[ 12.290898] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10905 13:46:08.484907 Startin<6>[ 12.300267] fuse: init (API version 7.37)
10906 13:46:08.491774 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10907 13:46:08.518411 <30>[ 12.330732] systemd[1]: Starting systemd-journald.service - Journal Service...
10908 13:46:08.524823 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10909 13:46:08.593532 <30>[ 12.406159] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10910 13:46:08.600277 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10911 13:46:08.627872 <30>[ 12.437036] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10912 13:46:08.634351 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10913 13:46:08.655488 <3>[ 12.467730] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 13:46:08.665164 <30>[ 12.469025] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10915 13:46:08.671600 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10916 13:46:08.694755 <3>[ 12.507426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 13:46:08.704427 <30>[ 12.508175] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10918 13:46:08.711093 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10919 13:46:08.733077 <30>[ 12.545297] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10920 13:46:08.739352 <3>[ 12.548002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 13:46:08.749232 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10922 13:46:08.766132 <30>[ 12.577769] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10923 13:46:08.772477 <3>[ 12.584167] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 13:46:08.782451 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10925 13:46:08.804355 <3>[ 12.617264] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 13:46:08.814773 <30>[ 12.617439] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10927 13:46:08.821649 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10928 13:46:08.834769 <3>[ 12.647406] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 13:46:08.845921 <30>[ 12.658451] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10930 13:46:08.855847 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10931 13:46:08.865800 <3>[ 12.678022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 13:46:08.876054 <30>[ 12.688532] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10933 13:46:08.883102 <30>[ 12.696939] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10934 13:46:08.896926 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 12.708821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:46:08.903223 onfigfs…[0m - Load Kernel Module configfs.
10936 13:46:08.921875 <30>[ 12.734096] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10937 13:46:08.928999 <30>[ 12.741817] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10938 13:46:08.939283 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10939 13:46:08.945707 <4>[ 12.761220] power_supply_show_property: 1 callbacks suppressed
10940 13:46:08.955797 <3>[ 12.761237] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 13:46:08.965840 <30>[ 12.778272] systemd[1]: modprobe@drm.service: Deactivated successfully.
10942 13:46:08.972594 <30>[ 12.786524] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10943 13:46:08.989830 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 12.800136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 13:46:08.989943 ule drm.
10945 13:46:09.015034 <30>[ 12.826994] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10946 13:46:09.021806 <3>[ 12.831506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 13:46:09.031626 <30>[ 12.835838] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10948 13:46:09.037970 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10949 13:46:09.056721 <3>[ 12.869201] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 13:46:09.063155 <30>[ 12.870229] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10951 13:46:09.072990 <30>[ 12.885613] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10952 13:46:09.080183 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10953 13:46:09.094861 <30>[ 12.909956] systemd[1]: modprobe@loop.service: Deactivated successfully.
10954 13:46:09.104244 <3>[ 12.913367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 13:46:09.111257 <30>[ 12.917377] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10956 13:46:09.121003 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10957 13:46:09.142106 <30>[ 12.953930] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10958 13:46:09.152459 [[0;32m OK [0m] Finished [0<3>[ 12.963897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 13:46:09.162165 <3>[ 12.964692] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10960 13:46:09.176286 <4>[ 12.982911] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10961 13:46:09.186207 <3>[ 12.998539] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10962 13:46:09.192654 <3>[ 12.999022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 13:46:09.199455 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10964 13:46:09.222888 <30>[ 13.031099] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10965 13:46:09.229134 <3>[ 13.041445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 13:46:09.239101 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10967 13:46:09.258538 <30>[ 13.070700] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10968 13:46:09.268551 <3>[ 13.079928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 13:46:09.275408 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10970 13:46:09.294282 <30>[ 13.106215] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10971 13:46:09.300641 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10972 13:46:09.322428 <30>[ 13.134842] systemd[1]: Reached target network-pre.target - Preparation for Network.
10973 13:46:09.329371 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10974 13:46:09.384985 <30>[ 13.197453] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10975 13:46:09.391228 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10976 13:46:09.417755 <30>[ 13.230212] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10977 13:46:09.424169 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10978 13:46:09.447858 <30>[ 13.257199] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10979 13:46:09.464741 <30>[ 13.270855] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10980 13:46:09.479711 <30>[ 13.292052] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10981 13:46:09.486113 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10982 13:46:09.510405 <30>[ 13.319720] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10983 13:46:09.544921 <30>[ 13.357940] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10984 13:46:09.552103 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10985 13:46:09.577411 <30>[ 13.389694] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10986 13:46:09.583842 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10987 13:46:09.612517 <30>[ 13.425112] systemd[1]: Started systemd-journald.service - Journal Service.
10988 13:46:09.619109 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10989 13:46:09.641888 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10990 13:46:09.661468 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10991 13:46:09.677788 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10992 13:46:09.697717 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10993 13:46:09.717541 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10994 13:46:09.773368 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10995 13:46:09.796014 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10996 13:46:09.825409 <46>[ 13.638078] systemd-journald[307]: Received client request to flush runtime journal.
10997 13:46:10.918464 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10998 13:46:10.936816 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10999 13:46:10.956188 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11000 13:46:11.224416 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11001 13:46:11.246389 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11002 13:46:11.272329 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11003 13:46:11.454830 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11004 13:46:11.510349 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11005 13:46:11.581024 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11006 13:46:11.730573 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11007 13:46:11.903545 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11008 13:46:11.909574 <6>[ 15.725510] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11009 13:46:11.932108 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11010 13:46:12.041571 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11011 13:46:12.060443 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11012 13:46:12.116604 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11013 13:46:12.136270 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11014 13:46:12.185587 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11015 13:46:12.206997 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11016 13:46:12.222223 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11017 13:46:12.240823 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11018 13:46:12.256670 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11019 13:46:12.273733 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11020 13:46:12.294113 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11021 13:46:12.317757 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11022 13:46:12.338929 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11023 13:46:12.356592 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11024 13:46:12.376081 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11025 13:46:12.395526 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11026 13:46:12.412283 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11027 13:46:12.428205 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11028 13:46:12.446329 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11029 13:46:12.464413 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11030 13:46:12.470821 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11031 13:46:12.525803 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11032 13:46:12.589509 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11033 13:46:12.669347 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11034 13:46:12.694046 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11035 13:46:12.717691 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11036 13:46:12.792859 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11037 13:46:12.818108 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11038 13:46:12.842416 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11039 13:46:12.880967 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11040 13:46:12.941453 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11041 13:46:12.960377 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11042 13:46:12.981411 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11043 13:46:13.036946 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11044 13:46:13.063103 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11045 13:46:13.085370 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11046 13:46:13.142291 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11047 13:46:13.205314 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11048 13:46:13.280571
11049 13:46:13.284117 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11050 13:46:13.284264
11051 13:46:13.287707 debian-bookworm-arm64 login: root (automatic login)
11052 13:46:13.287817
11053 13:46:13.544870 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11054 13:46:13.545060
11055 13:46:13.551517 The programs included with the Debian GNU/Linux system are free software;
11056 13:46:13.558545 the exact distribution terms for each program are described in the
11057 13:46:13.561995 individual files in /usr/share/doc/*/copyright.
11058 13:46:13.562095
11059 13:46:13.569059 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11060 13:46:13.571927 permitted by applicable law.
11061 13:46:14.490568 Matched prompt #10: / #
11063 13:46:14.490857 Setting prompt string to ['/ #']
11064 13:46:14.490954 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11066 13:46:14.491148 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11067 13:46:14.491241 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11068 13:46:14.491311 Setting prompt string to ['/ #']
11069 13:46:14.491372 Forcing a shell prompt, looking for ['/ #']
11071 13:46:14.541612 / #
11072 13:46:14.541803 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11073 13:46:14.541883 Waiting using forced prompt support (timeout 00:02:30)
11074 13:46:14.546338
11075 13:46:14.546634 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11076 13:46:14.546732 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11078 13:46:14.647126 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e'
11079 13:46:14.652409 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063055/extract-nfsrootfs-ipjfen2e'
11081 13:46:14.753011 / # export NFS_SERVER_IP='192.168.201.1'
11082 13:46:14.759008 export NFS_SERVER_IP='192.168.201.1'
11083 13:46:14.759329 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11084 13:46:14.759465 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11085 13:46:14.759570 end: 2 depthcharge-action (duration 00:01:26) [common]
11086 13:46:14.759662 start: 3 lava-test-retry (timeout 00:07:53) [common]
11087 13:46:14.759752 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
11088 13:46:14.759831 Using namespace: common
11090 13:46:14.860222 / # #
11091 13:46:14.860487 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11092 13:46:14.866020 #
11093 13:46:14.866309 Using /lava-14063055
11095 13:46:14.966657 / # export SHELL=/bin/bash
11096 13:46:14.971642 export SHELL=/bin/bash
11098 13:46:15.072225 / # . /lava-14063055/environment
11099 13:46:15.077466 . /lava-14063055/environment
11101 13:46:15.183131 / # /lava-14063055/bin/lava-test-runner /lava-14063055/0
11102 13:46:15.183314 Test shell timeout: 10s (minimum of the action and connection timeout)
11103 13:46:15.188604 /lava-14063055/bin/lava-test-runner /lava-14063055/0
11104 13:46:15.390743 + export TESTRUN_ID=0_timesync-off
11105 13:46:15.393813 + TESTRUN_ID=0_timesync-off
11106 13:46:15.397734 + cd /lava-14063055/0/tests/0_timesync-off
11107 13:46:15.400656 ++ cat uuid
11108 13:46:15.400746 + UUID=14063055_1.6.2.3.1
11109 13:46:15.404039 + set +x
11110 13:46:15.407477 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14063055_1.6.2.3.1>
11111 13:46:15.407789 Received signal: <STARTRUN> 0_timesync-off 14063055_1.6.2.3.1
11112 13:46:15.407909 Starting test lava.0_timesync-off (14063055_1.6.2.3.1)
11113 13:46:15.408064 Skipping test definition patterns.
11114 13:46:15.410346 + systemctl stop systemd-timesyncd
11115 13:46:15.460464 + set +x
11116 13:46:15.463521 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14063055_1.6.2.3.1>
11117 13:46:15.463867 Received signal: <ENDRUN> 0_timesync-off 14063055_1.6.2.3.1
11118 13:46:15.464015 Ending use of test pattern.
11119 13:46:15.464134 Ending test lava.0_timesync-off (14063055_1.6.2.3.1), duration 0.06
11121 13:46:15.522363 + export TESTRUN_ID=1_kselftest-alsa
11122 13:46:15.525820 + TESTRUN_ID=1_kselftest-alsa
11123 13:46:15.528893 + cd /lava-14063055/0/tests/1_kselftest-alsa
11124 13:46:15.532195 ++ cat uuid
11125 13:46:15.535961 + UUID=14063055_1.6.2.3.5
11126 13:46:15.536081 + set +x
11127 13:46:15.538738 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14063055_1.6.2.3.5>
11128 13:46:15.539009 Received signal: <STARTRUN> 1_kselftest-alsa 14063055_1.6.2.3.5
11129 13:46:15.539083 Starting test lava.1_kselftest-alsa (14063055_1.6.2.3.5)
11130 13:46:15.539167 Skipping test definition patterns.
11131 13:46:15.542368 + cd ./automated/linux/kselftest/
11132 13:46:15.568560 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11133 13:46:15.593547 INFO: install_deps skipped
11134 13:46:16.075654 --2024-05-28 13:41:35-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11135 13:46:16.086538 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11136 13:46:16.210841 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11137 13:46:16.335059 HTTP request sent, awaiting response... 200 OK
11138 13:46:16.337881 Length: 1642660 (1.6M) [application/octet-stream]
11139 13:46:16.341287 Saving to: 'kselftest_armhf.tar.gz'
11140 13:46:16.341381
11141 13:46:16.341448
11142 13:46:16.582574 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11143 13:46:16.830414 kselftest_armhf.tar 2%[ ] 47.81K 193KB/s
11144 13:46:17.129507 kselftest_armhf.tar 13%[=> ] 216.08K 436KB/s
11145 13:46:17.248877 kselftest_armhf.tar 51%[=========> ] 825.54K 1.01MB/s
11146 13:46:17.255009 kselftest_armhf.tar 100%[===================>] 1.57M 1.71MB/s in 0.9s
11147 13:46:17.255157
11148 13:46:17.398772 2024-05-28 13:41:36 (1.71 MB/s) - 'kselftest_armhf.tar.gz' saved [1642660/1642660]
11149 13:46:17.398927
11150 13:46:20.925497 skiplist:
11151 13:46:20.928822 ========================================
11152 13:46:20.932042 ========================================
11153 13:46:20.969685 alsa:mixer-test
11154 13:46:20.986904 ============== Tests to run ===============
11155 13:46:20.987061 alsa:mixer-test
11156 13:46:20.990377 ===========End Tests to run ===============
11157 13:46:20.993877 shardfile-alsa pass
11158 13:46:21.084733 <12>[ 24.901735] kselftest: Running tests in alsa
11159 13:46:21.093291 TAP version 13
11160 13:46:21.107247 1..1
11161 13:46:21.124404 # selftests: alsa: mixer-test
11162 13:46:21.617458 # TAP version 13
11163 13:46:21.617617 # 1..0
11164 13:46:21.623777 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11165 13:46:21.626785 ok 1 selftests: alsa: mixer-test
11166 13:46:23.055883 alsa_mixer-test pass
11167 13:46:23.132763 + ../../utils/send-to-lava.sh ./output/result.txt
11168 13:46:23.191249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11169 13:46:23.191598 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11171 13:46:23.226582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11172 13:46:23.226731 + set +x
11173 13:46:23.226982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11175 13:46:23.232576 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14063055_1.6.2.3.5>
11176 13:46:23.232867 Received signal: <ENDRUN> 1_kselftest-alsa 14063055_1.6.2.3.5
11177 13:46:23.232949 Ending use of test pattern.
11178 13:46:23.233012 Ending test lava.1_kselftest-alsa (14063055_1.6.2.3.5), duration 7.69
11180 13:46:23.236199 <LAVA_TEST_RUNNER EXIT>
11181 13:46:23.236458 ok: lava_test_shell seems to have completed
11182 13:46:23.236563 alsa_mixer-test: pass
shardfile-alsa: pass
11183 13:46:23.236655 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11184 13:46:23.236741 end: 3 lava-test-retry (duration 00:00:08) [common]
11185 13:46:23.236829 start: 4 finalize (timeout 00:07:45) [common]
11186 13:46:23.236918 start: 4.1 power-off (timeout 00:00:30) [common]
11187 13:46:23.237068 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11188 13:46:23.315764 >> Command sent successfully.
11189 13:46:23.318205 Returned 0 in 0 seconds
11190 13:46:23.418632 end: 4.1 power-off (duration 00:00:00) [common]
11192 13:46:23.418965 start: 4.2 read-feedback (timeout 00:07:45) [common]
11193 13:46:23.419222 Listened to connection for namespace 'common' for up to 1s
11194 13:46:24.420198 Finalising connection for namespace 'common'
11195 13:46:24.420391 Disconnecting from shell: Finalise
11196 13:46:24.420474 / #
11197 13:46:24.520798 end: 4.2 read-feedback (duration 00:00:01) [common]
11198 13:46:24.520979 end: 4 finalize (duration 00:00:01) [common]
11199 13:46:24.521096 Cleaning after the job
11200 13:46:24.521199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/ramdisk
11201 13:46:24.523334 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/kernel
11202 13:46:24.534017 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/dtb
11203 13:46:24.534253 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/nfsrootfs
11204 13:46:24.598058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063055/tftp-deploy-2ustgt69/modules
11205 13:46:24.603729 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063055
11206 13:46:25.172236 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063055
11207 13:46:25.172483 Job finished correctly