Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:36:27.034810 lava-dispatcher, installed at version: 2024.03
2 13:36:27.035017 start: 0 validate
3 13:36:27.035153 Start time: 2024-05-28 13:36:27.035145+00:00 (UTC)
4 13:36:27.035270 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:36:27.035394 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:36:27.294978 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:36:27.295147 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:37:45.375319 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:37:45.375480 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:37:45.625370 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:37:45.626247 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:37:46.131475 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:37:46.131635 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:37:46.134087 validate duration: 79.10
16 13:37:46.134606 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:37:46.134751 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:37:46.134860 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:37:46.134991 Not decompressing ramdisk as can be used compressed.
20 13:37:46.135074 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:37:46.135138 saving as /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/ramdisk/initrd.cpio.gz
22 13:37:46.135201 total size: 5628169 (5 MB)
23 13:37:46.397443 progress 0 % (0 MB)
24 13:37:46.399093 progress 5 % (0 MB)
25 13:37:46.400656 progress 10 % (0 MB)
26 13:37:46.402061 progress 15 % (0 MB)
27 13:37:46.403609 progress 20 % (1 MB)
28 13:37:46.405005 progress 25 % (1 MB)
29 13:37:46.406590 progress 30 % (1 MB)
30 13:37:46.408163 progress 35 % (1 MB)
31 13:37:46.409533 progress 40 % (2 MB)
32 13:37:46.411065 progress 45 % (2 MB)
33 13:37:46.412417 progress 50 % (2 MB)
34 13:37:46.413972 progress 55 % (2 MB)
35 13:37:46.415525 progress 60 % (3 MB)
36 13:37:46.416881 progress 65 % (3 MB)
37 13:37:46.418434 progress 70 % (3 MB)
38 13:37:46.419786 progress 75 % (4 MB)
39 13:37:46.421313 progress 80 % (4 MB)
40 13:37:46.422719 progress 85 % (4 MB)
41 13:37:46.424257 progress 90 % (4 MB)
42 13:37:46.425808 progress 95 % (5 MB)
43 13:37:46.427179 progress 100 % (5 MB)
44 13:37:46.427382 5 MB downloaded in 0.29 s (18.37 MB/s)
45 13:37:46.427537 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:37:46.427773 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:37:46.427860 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:37:46.427944 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:37:46.428082 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:37:46.428150 saving as /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/kernel/Image
52 13:37:46.428209 total size: 54682112 (52 MB)
53 13:37:46.428270 No compression specified
54 13:37:46.429473 progress 0 % (0 MB)
55 13:37:46.443524 progress 5 % (2 MB)
56 13:37:46.457802 progress 10 % (5 MB)
57 13:37:46.472116 progress 15 % (7 MB)
58 13:37:46.486064 progress 20 % (10 MB)
59 13:37:46.500262 progress 25 % (13 MB)
60 13:37:46.514119 progress 30 % (15 MB)
61 13:37:46.528168 progress 35 % (18 MB)
62 13:37:46.542112 progress 40 % (20 MB)
63 13:37:46.555975 progress 45 % (23 MB)
64 13:37:46.570428 progress 50 % (26 MB)
65 13:37:46.584660 progress 55 % (28 MB)
66 13:37:46.598706 progress 60 % (31 MB)
67 13:37:46.612546 progress 65 % (33 MB)
68 13:37:46.626586 progress 70 % (36 MB)
69 13:37:46.640425 progress 75 % (39 MB)
70 13:37:46.654467 progress 80 % (41 MB)
71 13:37:46.668317 progress 85 % (44 MB)
72 13:37:46.682501 progress 90 % (46 MB)
73 13:37:46.696496 progress 95 % (49 MB)
74 13:37:46.710195 progress 100 % (52 MB)
75 13:37:46.710449 52 MB downloaded in 0.28 s (184.77 MB/s)
76 13:37:46.710601 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:37:46.710831 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:37:46.710919 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:37:46.711001 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:37:46.711126 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:37:46.711193 saving as /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/dtb/mt8192-asurada-spherion-r0.dtb
83 13:37:46.711253 total size: 47258 (0 MB)
84 13:37:46.711314 No compression specified
85 13:37:46.712409 progress 69 % (0 MB)
86 13:37:46.712698 progress 100 % (0 MB)
87 13:37:46.712850 0 MB downloaded in 0.00 s (28.27 MB/s)
88 13:37:46.712988 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:37:46.713213 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:37:46.713323 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:37:46.713424 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:37:46.713537 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:37:46.713604 saving as /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/nfsrootfs/full.rootfs.tar
95 13:37:46.713664 total size: 120894716 (115 MB)
96 13:37:46.713725 Using unxz to decompress xz
97 13:37:46.717644 progress 0 % (0 MB)
98 13:37:47.067922 progress 5 % (5 MB)
99 13:37:47.427602 progress 10 % (11 MB)
100 13:37:47.776399 progress 15 % (17 MB)
101 13:37:48.103131 progress 20 % (23 MB)
102 13:37:48.396356 progress 25 % (28 MB)
103 13:37:48.753085 progress 30 % (34 MB)
104 13:37:49.089453 progress 35 % (40 MB)
105 13:37:49.262221 progress 40 % (46 MB)
106 13:37:49.444341 progress 45 % (51 MB)
107 13:37:49.759162 progress 50 % (57 MB)
108 13:37:50.130691 progress 55 % (63 MB)
109 13:37:50.474615 progress 60 % (69 MB)
110 13:37:50.815351 progress 65 % (74 MB)
111 13:37:51.157705 progress 70 % (80 MB)
112 13:37:51.516777 progress 75 % (86 MB)
113 13:37:51.876294 progress 80 % (92 MB)
114 13:37:52.240238 progress 85 % (98 MB)
115 13:37:52.620524 progress 90 % (103 MB)
116 13:37:52.971692 progress 95 % (109 MB)
117 13:37:53.345723 progress 100 % (115 MB)
118 13:37:53.351313 115 MB downloaded in 6.64 s (17.37 MB/s)
119 13:37:53.351597 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:37:53.351975 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:37:53.352083 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:37:53.352186 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:37:53.352387 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:37:53.352467 saving as /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/modules/modules.tar
126 13:37:53.352569 total size: 8607916 (8 MB)
127 13:37:53.352674 Using unxz to decompress xz
128 13:37:53.357330 progress 0 % (0 MB)
129 13:37:53.378720 progress 5 % (0 MB)
130 13:37:53.406289 progress 10 % (0 MB)
131 13:37:53.435066 progress 15 % (1 MB)
132 13:37:53.463331 progress 20 % (1 MB)
133 13:37:53.492080 progress 25 % (2 MB)
134 13:37:53.520105 progress 30 % (2 MB)
135 13:37:53.546940 progress 35 % (2 MB)
136 13:37:53.576918 progress 40 % (3 MB)
137 13:37:53.605232 progress 45 % (3 MB)
138 13:37:53.632596 progress 50 % (4 MB)
139 13:37:53.660651 progress 55 % (4 MB)
140 13:37:53.688301 progress 60 % (4 MB)
141 13:37:53.715191 progress 65 % (5 MB)
142 13:37:53.745208 progress 70 % (5 MB)
143 13:37:53.776043 progress 75 % (6 MB)
144 13:37:53.802359 progress 80 % (6 MB)
145 13:37:53.829916 progress 85 % (7 MB)
146 13:37:53.856923 progress 90 % (7 MB)
147 13:37:53.890628 progress 95 % (7 MB)
148 13:37:53.922994 progress 100 % (8 MB)
149 13:37:53.929545 8 MB downloaded in 0.58 s (14.23 MB/s)
150 13:37:53.929935 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:37:53.930371 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:37:53.930510 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:37:53.930651 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:37:57.818216 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx
156 13:37:57.818441 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:37:57.818586 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 13:37:57.818833 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t
159 13:37:57.819022 makedir: /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin
160 13:37:57.819168 makedir: /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/tests
161 13:37:57.819320 makedir: /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/results
162 13:37:57.819472 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-add-keys
163 13:37:57.819681 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-add-sources
164 13:37:57.819876 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-background-process-start
165 13:37:57.820025 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-background-process-stop
166 13:37:57.820168 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-common-functions
167 13:37:57.820339 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-echo-ipv4
168 13:37:57.820508 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-install-packages
169 13:37:57.820643 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-installed-packages
170 13:37:57.820773 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-os-build
171 13:37:57.820901 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-probe-channel
172 13:37:57.821030 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-probe-ip
173 13:37:57.821156 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-target-ip
174 13:37:57.821282 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-target-mac
175 13:37:57.821590 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-target-storage
176 13:37:57.821721 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-case
177 13:37:57.821850 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-event
178 13:37:57.821976 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-feedback
179 13:37:57.822103 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-raise
180 13:37:57.822251 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-reference
181 13:37:57.822380 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-runner
182 13:37:57.822508 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-set
183 13:37:57.822637 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-test-shell
184 13:37:57.822764 Updating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-add-keys (debian)
185 13:37:57.822918 Updating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-add-sources (debian)
186 13:37:57.823059 Updating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-install-packages (debian)
187 13:37:57.823198 Updating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-installed-packages (debian)
188 13:37:57.823336 Updating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/bin/lava-os-build (debian)
189 13:37:57.823457 Creating /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/environment
190 13:37:57.823555 LAVA metadata
191 13:37:57.823622 - LAVA_JOB_ID=14063009
192 13:37:57.823687 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:37:57.823796 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 13:37:57.823864 skipped lava-vland-overlay
195 13:37:57.823939 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:37:57.824019 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 13:37:57.824093 skipped lava-multinode-overlay
198 13:37:57.824176 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:37:57.824292 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 13:37:57.824402 Loading test definitions
201 13:37:57.824522 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 13:37:57.824596 Using /lava-14063009 at stage 0
203 13:37:57.824892 uuid=14063009_1.6.2.3.1 testdef=None
204 13:37:57.824981 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:37:57.825066 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 13:37:57.825530 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:37:57.825754 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 13:37:57.826316 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:37:57.826568 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 13:37:57.827160 runner path: /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/0/tests/0_timesync-off test_uuid 14063009_1.6.2.3.1
213 13:37:57.827324 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:37:57.827570 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 13:37:57.827679 Using /lava-14063009 at stage 0
217 13:37:57.827822 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:37:57.827949 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/0/tests/1_kselftest-arm64'
219 13:38:01.866652 Running '/usr/bin/git checkout kernelci.org
220 13:38:02.017860 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 13:38:02.018624 uuid=14063009_1.6.2.3.5 testdef=None
222 13:38:02.018786 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 13:38:02.019043 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 13:38:02.019830 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:38:02.020072 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 13:38:02.021090 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:38:02.021351 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 13:38:02.022319 runner path: /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/0/tests/1_kselftest-arm64 test_uuid 14063009_1.6.2.3.5
232 13:38:02.022417 BOARD='mt8192-asurada-spherion-r0'
233 13:38:02.022484 BRANCH='cip'
234 13:38:02.022545 SKIPFILE='/dev/null'
235 13:38:02.022605 SKIP_INSTALL='True'
236 13:38:02.022663 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:38:02.022725 TST_CASENAME=''
238 13:38:02.022781 TST_CMDFILES='arm64'
239 13:38:02.022927 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:38:02.023161 Creating lava-test-runner.conf files
242 13:38:02.023228 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063009/lava-overlay-3z8wdm7t/lava-14063009/0 for stage 0
243 13:38:02.023326 - 0_timesync-off
244 13:38:02.023400 - 1_kselftest-arm64
245 13:38:02.023500 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 13:38:02.023592 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 13:38:09.871007 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:38:09.871147 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 13:38:09.871238 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:38:09.871332 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 13:38:09.871419 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 13:38:10.037090 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:38:10.037553 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 13:38:10.037705 extracting modules file /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx
255 13:38:10.260227 extracting modules file /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063009/extract-overlay-ramdisk-mg0fom2s/ramdisk
256 13:38:10.481862 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:38:10.482021 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 13:38:10.482117 [common] Applying overlay to NFS
259 13:38:10.482186 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063009/compress-overlay-qas3jn_4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx
260 13:38:11.396619 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:38:11.396776 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 13:38:11.396876 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:38:11.396964 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 13:38:11.397045 Building ramdisk /var/lib/lava/dispatcher/tmp/14063009/extract-overlay-ramdisk-mg0fom2s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063009/extract-overlay-ramdisk-mg0fom2s/ramdisk
265 13:38:11.711838 >> 130335 blocks
266 13:38:13.791208 rename /var/lib/lava/dispatcher/tmp/14063009/extract-overlay-ramdisk-mg0fom2s/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/ramdisk/ramdisk.cpio.gz
267 13:38:13.791705 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:38:13.791873 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 13:38:13.792023 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 13:38:13.792176 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/kernel/Image']
271 13:38:27.952713 Returned 0 in 14 seconds
272 13:38:28.053464 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/kernel/image.itb
273 13:38:28.413745 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:38:28.414105 output: Created: Tue May 28 14:38:28 2024
275 13:38:28.414184 output: Image 0 (kernel-1)
276 13:38:28.414254 output: Description:
277 13:38:28.414318 output: Created: Tue May 28 14:38:28 2024
278 13:38:28.414379 output: Type: Kernel Image
279 13:38:28.414441 output: Compression: lzma compressed
280 13:38:28.414501 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
281 13:38:28.414559 output: Architecture: AArch64
282 13:38:28.414618 output: OS: Linux
283 13:38:28.414676 output: Load Address: 0x00000000
284 13:38:28.414736 output: Entry Point: 0x00000000
285 13:38:28.414799 output: Hash algo: crc32
286 13:38:28.414861 output: Hash value: 0578ee26
287 13:38:28.414916 output: Image 1 (fdt-1)
288 13:38:28.414973 output: Description: mt8192-asurada-spherion-r0
289 13:38:28.415026 output: Created: Tue May 28 14:38:28 2024
290 13:38:28.415084 output: Type: Flat Device Tree
291 13:38:28.415139 output: Compression: uncompressed
292 13:38:28.415192 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:38:28.415279 output: Architecture: AArch64
294 13:38:28.415359 output: Hash algo: crc32
295 13:38:28.415436 output: Hash value: 0f8e4d2e
296 13:38:28.415496 output: Image 2 (ramdisk-1)
297 13:38:28.415549 output: Description: unavailable
298 13:38:28.415602 output: Created: Tue May 28 14:38:28 2024
299 13:38:28.415656 output: Type: RAMDisk Image
300 13:38:28.415713 output: Compression: Unknown Compression
301 13:38:28.415767 output: Data Size: 18729896 Bytes = 18290.91 KiB = 17.86 MiB
302 13:38:28.415823 output: Architecture: AArch64
303 13:38:28.415878 output: OS: Linux
304 13:38:28.415937 output: Load Address: unavailable
305 13:38:28.415991 output: Entry Point: unavailable
306 13:38:28.416044 output: Hash algo: crc32
307 13:38:28.416096 output: Hash value: bed33cb8
308 13:38:28.416149 output: Default Configuration: 'conf-1'
309 13:38:28.416209 output: Configuration 0 (conf-1)
310 13:38:28.416263 output: Description: mt8192-asurada-spherion-r0
311 13:38:28.416315 output: Kernel: kernel-1
312 13:38:28.416367 output: Init Ramdisk: ramdisk-1
313 13:38:28.416419 output: FDT: fdt-1
314 13:38:28.416471 output: Loadables: kernel-1
315 13:38:28.416523 output:
316 13:38:28.416727 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 13:38:28.416826 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 13:38:28.416940 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 13:38:28.417028 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 13:38:28.417108 No LXC device requested
321 13:38:28.417213 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:38:28.417373 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 13:38:28.417473 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:38:28.417543 Checking files for TFTP limit of 4294967296 bytes.
325 13:38:28.418076 end: 1 tftp-deploy (duration 00:00:42) [common]
326 13:38:28.418179 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:38:28.418279 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:38:28.418405 substitutions:
329 13:38:28.418473 - {DTB}: 14063009/tftp-deploy-umrz_1vp/dtb/mt8192-asurada-spherion-r0.dtb
330 13:38:28.418538 - {INITRD}: 14063009/tftp-deploy-umrz_1vp/ramdisk/ramdisk.cpio.gz
331 13:38:28.418597 - {KERNEL}: 14063009/tftp-deploy-umrz_1vp/kernel/Image
332 13:38:28.418655 - {LAVA_MAC}: None
333 13:38:28.418714 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx
334 13:38:28.418774 - {NFS_SERVER_IP}: 192.168.201.1
335 13:38:28.418828 - {PRESEED_CONFIG}: None
336 13:38:28.418884 - {PRESEED_LOCAL}: None
337 13:38:28.418938 - {RAMDISK}: 14063009/tftp-deploy-umrz_1vp/ramdisk/ramdisk.cpio.gz
338 13:38:28.418992 - {ROOT_PART}: None
339 13:38:28.419045 - {ROOT}: None
340 13:38:28.419098 - {SERVER_IP}: 192.168.201.1
341 13:38:28.419151 - {TEE}: None
342 13:38:28.419205 Parsed boot commands:
343 13:38:28.419289 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:38:28.419517 Parsed boot commands: tftpboot 192.168.201.1 14063009/tftp-deploy-umrz_1vp/kernel/image.itb 14063009/tftp-deploy-umrz_1vp/kernel/cmdline
345 13:38:28.419613 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:38:28.419700 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:38:28.419798 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:38:28.419881 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:38:28.419957 Not connected, no need to disconnect.
350 13:38:28.420032 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:38:28.420116 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:38:28.420187 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 13:38:28.424187 Setting prompt string to ['lava-test: # ']
354 13:38:28.424574 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:38:28.424686 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:38:28.424787 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:38:28.424894 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:38:28.425112 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 13:38:33.561170 >> Command sent successfully.
360 13:38:33.564194 Returned 0 in 5 seconds
361 13:38:33.664694 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 13:38:33.665138 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 13:38:33.665275 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 13:38:33.665408 Setting prompt string to 'Starting depthcharge on Spherion...'
366 13:38:33.665489 Changing prompt to 'Starting depthcharge on Spherion...'
367 13:38:33.665577 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 13:38:33.665978 [Enter `^Ec?' for help]
369 13:38:33.843877
370 13:38:33.844163
371 13:38:33.844256 F0: 102B 0000
372 13:38:33.844378
373 13:38:33.844472 F3: 1001 0000 [0200]
374 13:38:33.844558
375 13:38:33.847402 F3: 1001 0000
376 13:38:33.847498
377 13:38:33.847584 F7: 102D 0000
378 13:38:33.847698
379 13:38:33.851816 F1: 0000 0000
380 13:38:33.851943
381 13:38:33.852045 V0: 0000 0000 [0001]
382 13:38:33.852126
383 13:38:33.852206 00: 0007 8000
384 13:38:33.852310
385 13:38:33.855381 01: 0000 0000
386 13:38:33.855470
387 13:38:33.855557 BP: 0C00 0209 [0000]
388 13:38:33.855638
389 13:38:33.859322 G0: 1182 0000
390 13:38:33.859409
391 13:38:33.859476 EC: 0000 0021 [4000]
392 13:38:33.859540
393 13:38:33.862662 S7: 0000 0000 [0000]
394 13:38:33.862783
395 13:38:33.862888 CC: 0000 0000 [0001]
396 13:38:33.862990
397 13:38:33.866295 T0: 0000 0040 [010F]
398 13:38:33.866404
399 13:38:33.866569 Jump to BL
400 13:38:33.866693
401 13:38:33.891367
402 13:38:33.891492
403 13:38:33.898587 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 13:38:33.901460 ARM64: Exception handlers installed.
405 13:38:33.905086 ARM64: Testing exception
406 13:38:33.908711 ARM64: Done test exception
407 13:38:33.916362 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 13:38:33.927271 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 13:38:33.930853 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 13:38:33.941411 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 13:38:33.948038 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 13:38:33.958472 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 13:38:33.968995 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 13:38:33.976160 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 13:38:33.993534 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 13:38:33.997207 WDT: Last reset was cold boot
417 13:38:34.000243 SPI1(PAD0) initialized at 2873684 Hz
418 13:38:34.003885 SPI5(PAD0) initialized at 992727 Hz
419 13:38:34.006935 VBOOT: Loading verstage.
420 13:38:34.013972 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 13:38:34.016788 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 13:38:34.020098 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 13:38:34.023581 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 13:38:34.030852 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 13:38:34.037988 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 13:38:34.048537 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 13:38:34.048617
428 13:38:34.048682
429 13:38:34.058663 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 13:38:34.061795 ARM64: Exception handlers installed.
431 13:38:34.065257 ARM64: Testing exception
432 13:38:34.065387 ARM64: Done test exception
433 13:38:34.071890 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 13:38:34.075369 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 13:38:34.089884 Probing TPM: . done!
436 13:38:34.089974 TPM ready after 0 ms
437 13:38:34.097203 Connected to device vid:did:rid of 1ae0:0028:00
438 13:38:34.103925 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 13:38:34.151157 Initialized TPM device CR50 revision 0
440 13:38:34.166865 tlcl_send_startup: Startup return code is 0
441 13:38:34.166994 TPM: setup succeeded
442 13:38:34.177595 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 13:38:34.187061 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:38:34.196676 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 13:38:34.205589 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 13:38:34.208582 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 13:38:34.212196 in-header: 03 07 00 00 08 00 00 00
448 13:38:34.215329 in-data: aa e4 47 04 13 02 00 00
449 13:38:34.218413 Chrome EC: UHEPI supported
450 13:38:34.224957 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 13:38:34.228953 in-header: 03 95 00 00 08 00 00 00
452 13:38:34.232653 in-data: 18 20 20 08 00 00 00 00
453 13:38:34.232735 Phase 1
454 13:38:34.236121 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 13:38:34.243904 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 13:38:34.247233 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 13:38:34.251129 Recovery requested (1009000e)
458 13:38:34.260298 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 13:38:34.265672 tlcl_extend: response is 0
460 13:38:34.274730 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 13:38:34.280419 tlcl_extend: response is 0
462 13:38:34.287484 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 13:38:34.307932 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 13:38:34.315408 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 13:38:34.315502
466 13:38:34.315573
467 13:38:34.322124 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 13:38:34.325827 ARM64: Exception handlers installed.
469 13:38:34.329417 ARM64: Testing exception
470 13:38:34.332859 ARM64: Done test exception
471 13:38:34.353074 pmic_efuse_setting: Set efuses in 11 msecs
472 13:38:34.356578 pmwrap_interface_init: Select PMIF_VLD_RDY
473 13:38:34.362836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 13:38:34.366397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 13:38:34.373052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 13:38:34.376087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 13:38:34.383299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 13:38:34.386223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 13:38:34.389624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 13:38:34.396562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 13:38:34.399504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 13:38:34.406220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 13:38:34.409737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 13:38:34.412825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 13:38:34.419673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 13:38:34.426286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 13:38:34.429953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 13:38:34.437125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 13:38:34.441268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 13:38:34.448929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 13:38:34.451979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 13:38:34.459744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 13:38:34.463312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 13:38:34.470734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 13:38:34.474294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 13:38:34.481607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 13:38:34.485195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 13:38:34.491807 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 13:38:34.495898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 13:38:34.502879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 13:38:34.506643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 13:38:34.510300 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 13:38:34.517664 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 13:38:34.521264 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 13:38:34.528451 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 13:38:34.532640 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 13:38:34.535852 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 13:38:34.543023 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 13:38:34.546556 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 13:38:34.550365 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 13:38:34.557760 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 13:38:34.562090 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 13:38:34.565673 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 13:38:34.569004 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 13:38:34.572675 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 13:38:34.580377 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 13:38:34.584107 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 13:38:34.587695 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 13:38:34.591267 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 13:38:34.595057 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 13:38:34.598597 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 13:38:34.606116 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 13:38:34.609471 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 13:38:34.617180 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 13:38:34.624658 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 13:38:34.627694 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 13:38:34.639034 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 13:38:34.646422 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 13:38:34.649427 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 13:38:34.653100 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 13:38:34.659909 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:38:34.667454 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
533 13:38:34.670933 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 13:38:34.674947 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 13:38:34.681821 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 13:38:34.690336 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 13:38:34.699951 [RTC]rtc_get_frequency_meter,154: input=23, output=949
538 13:38:34.709486 [RTC]rtc_get_frequency_meter,154: input=19, output=857
539 13:38:34.718812 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 13:38:34.727965 [RTC]rtc_get_frequency_meter,154: input=16, output=787
541 13:38:34.737621 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 13:38:34.747929 [RTC]rtc_get_frequency_meter,154: input=17, output=811
543 13:38:34.751607 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 13:38:34.755785 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 13:38:34.759360 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 13:38:34.766458 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 13:38:34.770115 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 13:38:34.773854 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 13:38:34.777345 ADC[4]: Raw value=670432 ID=5
550 13:38:34.777454 ADC[3]: Raw value=212549 ID=1
551 13:38:34.780988 RAM Code: 0x51
552 13:38:34.784573 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 13:38:34.788868 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 13:38:34.799133 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 13:38:34.803257 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 13:38:34.806319 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 13:38:34.809912 in-header: 03 07 00 00 08 00 00 00
558 13:38:34.813618 in-data: aa e4 47 04 13 02 00 00
559 13:38:34.817642 Chrome EC: UHEPI supported
560 13:38:34.825361 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 13:38:34.828445 in-header: 03 95 00 00 08 00 00 00
562 13:38:34.828536 in-data: 18 20 20 08 00 00 00 00
563 13:38:34.832070 MRC: failed to locate region type 0.
564 13:38:34.840006 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 13:38:34.843096 DRAM-K: Running full calibration
566 13:38:34.850431 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 13:38:34.850529 header.status = 0x0
568 13:38:34.854123 header.version = 0x6 (expected: 0x6)
569 13:38:34.857800 header.size = 0xd00 (expected: 0xd00)
570 13:38:34.857890 header.flags = 0x0
571 13:38:34.865141 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 13:38:34.883604 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 13:38:34.890838 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 13:38:34.894895 dram_init: ddr_geometry: 0
575 13:38:34.894994 [EMI] MDL number = 0
576 13:38:34.898467 [EMI] Get MDL freq = 0
577 13:38:34.898555 dram_init: ddr_type: 0
578 13:38:34.901883 is_discrete_lpddr4: 1
579 13:38:34.905925 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 13:38:34.906016
581 13:38:34.906104
582 13:38:34.906186 [Bian_co] ETT version 0.0.0.1
583 13:38:34.913301 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 13:38:34.913396
585 13:38:34.916837 dramc_set_vcore_voltage set vcore to 650000
586 13:38:34.916928 Read voltage for 800, 4
587 13:38:34.920447 Vio18 = 0
588 13:38:34.920535 Vcore = 650000
589 13:38:34.920623 Vdram = 0
590 13:38:34.920706 Vddq = 0
591 13:38:34.924492 Vmddr = 0
592 13:38:34.924582 dram_init: config_dvfs: 1
593 13:38:34.931343 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 13:38:34.934996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 13:38:34.938792 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 13:38:34.942468 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 13:38:34.946123 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 13:38:34.949898 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 13:38:34.953526 MEM_TYPE=3, freq_sel=18
600 13:38:34.957812 sv_algorithm_assistance_LP4_1600
601 13:38:34.961506 ============ PULL DRAM RESETB DOWN ============
602 13:38:34.965058 ========== PULL DRAM RESETB DOWN end =========
603 13:38:34.968753 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 13:38:34.972472 ===================================
605 13:38:34.976654 LPDDR4 DRAM CONFIGURATION
606 13:38:34.976744 ===================================
607 13:38:34.979619 EX_ROW_EN[0] = 0x0
608 13:38:34.983816 EX_ROW_EN[1] = 0x0
609 13:38:34.983904 LP4Y_EN = 0x0
610 13:38:34.983974 WORK_FSP = 0x0
611 13:38:34.987486 WL = 0x2
612 13:38:34.987580 RL = 0x2
613 13:38:34.991074 BL = 0x2
614 13:38:34.991158 RPST = 0x0
615 13:38:34.994708 RD_PRE = 0x0
616 13:38:34.994809 WR_PRE = 0x1
617 13:38:34.998436 WR_PST = 0x0
618 13:38:34.998523 DBI_WR = 0x0
619 13:38:35.002222 DBI_RD = 0x0
620 13:38:35.002323 OTF = 0x1
621 13:38:35.005791 ===================================
622 13:38:35.009640 ===================================
623 13:38:35.009732 ANA top config
624 13:38:35.013201 ===================================
625 13:38:35.017566 DLL_ASYNC_EN = 0
626 13:38:35.017650 ALL_SLAVE_EN = 1
627 13:38:35.020783 NEW_RANK_MODE = 1
628 13:38:35.023912 DLL_IDLE_MODE = 1
629 13:38:35.027326 LP45_APHY_COMB_EN = 1
630 13:38:35.030458 TX_ODT_DIS = 1
631 13:38:35.030543 NEW_8X_MODE = 1
632 13:38:35.034046 ===================================
633 13:38:35.037641 ===================================
634 13:38:35.041112 data_rate = 1600
635 13:38:35.044199 CKR = 1
636 13:38:35.047976 DQ_P2S_RATIO = 8
637 13:38:35.051759 ===================================
638 13:38:35.051844 CA_P2S_RATIO = 8
639 13:38:35.054787 DQ_CA_OPEN = 0
640 13:38:35.058544 DQ_SEMI_OPEN = 0
641 13:38:35.062187 CA_SEMI_OPEN = 0
642 13:38:35.065343 CA_FULL_RATE = 0
643 13:38:35.065443 DQ_CKDIV4_EN = 1
644 13:38:35.069046 CA_CKDIV4_EN = 1
645 13:38:35.072087 CA_PREDIV_EN = 0
646 13:38:35.075172 PH8_DLY = 0
647 13:38:35.079379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 13:38:35.079464 DQ_AAMCK_DIV = 4
649 13:38:35.082892 CA_AAMCK_DIV = 4
650 13:38:35.086896 CA_ADMCK_DIV = 4
651 13:38:35.089905 DQ_TRACK_CA_EN = 0
652 13:38:35.093402 CA_PICK = 800
653 13:38:35.093486 CA_MCKIO = 800
654 13:38:35.096900 MCKIO_SEMI = 0
655 13:38:35.100618 PLL_FREQ = 3068
656 13:38:35.103759 DQ_UI_PI_RATIO = 32
657 13:38:35.106766 CA_UI_PI_RATIO = 0
658 13:38:35.110441 ===================================
659 13:38:35.114436 ===================================
660 13:38:35.114532 memory_type:LPDDR4
661 13:38:35.118142 GP_NUM : 10
662 13:38:35.118226 SRAM_EN : 1
663 13:38:35.121087 MD32_EN : 0
664 13:38:35.125155 ===================================
665 13:38:35.125269 [ANA_INIT] >>>>>>>>>>>>>>
666 13:38:35.128971 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 13:38:35.132666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 13:38:35.136315 ===================================
669 13:38:35.139937 data_rate = 1600,PCW = 0X7600
670 13:38:35.143319 ===================================
671 13:38:35.147436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 13:38:35.150176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 13:38:35.156807 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 13:38:35.160453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 13:38:35.163560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 13:38:35.166618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 13:38:35.170213 [ANA_INIT] flow start
678 13:38:35.173809 [ANA_INIT] PLL >>>>>>>>
679 13:38:35.173893 [ANA_INIT] PLL <<<<<<<<
680 13:38:35.176749 [ANA_INIT] MIDPI >>>>>>>>
681 13:38:35.179921 [ANA_INIT] MIDPI <<<<<<<<
682 13:38:35.180004 [ANA_INIT] DLL >>>>>>>>
683 13:38:35.183559 [ANA_INIT] flow end
684 13:38:35.186888 ============ LP4 DIFF to SE enter ============
685 13:38:35.193220 ============ LP4 DIFF to SE exit ============
686 13:38:35.193347 [ANA_INIT] <<<<<<<<<<<<<
687 13:38:35.196660 [Flow] Enable top DCM control >>>>>
688 13:38:35.200165 [Flow] Enable top DCM control <<<<<
689 13:38:35.203654 Enable DLL master slave shuffle
690 13:38:35.210467 ==============================================================
691 13:38:35.210553 Gating Mode config
692 13:38:35.217102 ==============================================================
693 13:38:35.220254 Config description:
694 13:38:35.227080 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 13:38:35.233613 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 13:38:35.239973 SELPH_MODE 0: By rank 1: By Phase
697 13:38:35.243351 ==============================================================
698 13:38:35.246609 GAT_TRACK_EN = 1
699 13:38:35.250348 RX_GATING_MODE = 2
700 13:38:35.253340 RX_GATING_TRACK_MODE = 2
701 13:38:35.257101 SELPH_MODE = 1
702 13:38:35.260393 PICG_EARLY_EN = 1
703 13:38:35.263231 VALID_LAT_VALUE = 1
704 13:38:35.270382 ==============================================================
705 13:38:35.273319 Enter into Gating configuration >>>>
706 13:38:35.277062 Exit from Gating configuration <<<<
707 13:38:35.280142 Enter into DVFS_PRE_config >>>>>
708 13:38:35.290331 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 13:38:35.293320 Exit from DVFS_PRE_config <<<<<
710 13:38:35.296981 Enter into PICG configuration >>>>
711 13:38:35.299939 Exit from PICG configuration <<<<
712 13:38:35.300024 [RX_INPUT] configuration >>>>>
713 13:38:35.303445 [RX_INPUT] configuration <<<<<
714 13:38:35.309877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 13:38:35.313573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 13:38:35.320324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 13:38:35.326546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 13:38:35.333232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 13:38:35.339960 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 13:38:35.343658 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 13:38:35.346592 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 13:38:35.353439 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 13:38:35.356956 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 13:38:35.359960 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 13:38:35.363492 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 13:38:35.366548 ===================================
727 13:38:35.370033 LPDDR4 DRAM CONFIGURATION
728 13:38:35.373349 ===================================
729 13:38:35.376714 EX_ROW_EN[0] = 0x0
730 13:38:35.376798 EX_ROW_EN[1] = 0x0
731 13:38:35.380247 LP4Y_EN = 0x0
732 13:38:35.380331 WORK_FSP = 0x0
733 13:38:35.383732 WL = 0x2
734 13:38:35.383816 RL = 0x2
735 13:38:35.386806 BL = 0x2
736 13:38:35.386891 RPST = 0x0
737 13:38:35.389897 RD_PRE = 0x0
738 13:38:35.389982 WR_PRE = 0x1
739 13:38:35.393660 WR_PST = 0x0
740 13:38:35.393743 DBI_WR = 0x0
741 13:38:35.396542 DBI_RD = 0x0
742 13:38:35.396655 OTF = 0x1
743 13:38:35.400015 ===================================
744 13:38:35.406457 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 13:38:35.409973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 13:38:35.413281 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 13:38:35.416866 ===================================
748 13:38:35.419919 LPDDR4 DRAM CONFIGURATION
749 13:38:35.423084 ===================================
750 13:38:35.426777 EX_ROW_EN[0] = 0x10
751 13:38:35.426861 EX_ROW_EN[1] = 0x0
752 13:38:35.429807 LP4Y_EN = 0x0
753 13:38:35.429891 WORK_FSP = 0x0
754 13:38:35.433463 WL = 0x2
755 13:38:35.433548 RL = 0x2
756 13:38:35.436575 BL = 0x2
757 13:38:35.436659 RPST = 0x0
758 13:38:35.440163 RD_PRE = 0x0
759 13:38:35.440246 WR_PRE = 0x1
760 13:38:35.443179 WR_PST = 0x0
761 13:38:35.443263 DBI_WR = 0x0
762 13:38:35.446797 DBI_RD = 0x0
763 13:38:35.446880 OTF = 0x1
764 13:38:35.450266 ===================================
765 13:38:35.456904 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 13:38:35.461365 nWR fixed to 40
767 13:38:35.464667 [ModeRegInit_LP4] CH0 RK0
768 13:38:35.464759 [ModeRegInit_LP4] CH0 RK1
769 13:38:35.467752 [ModeRegInit_LP4] CH1 RK0
770 13:38:35.471458 [ModeRegInit_LP4] CH1 RK1
771 13:38:35.471564 match AC timing 12
772 13:38:35.478138 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 13:38:35.481096 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 13:38:35.484200 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 13:38:35.490777 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 13:38:35.494524 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 13:38:35.494609 [EMI DOE] emi_dcm 0
778 13:38:35.500840 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 13:38:35.500955 ==
780 13:38:35.504559 Dram Type= 6, Freq= 0, CH_0, rank 0
781 13:38:35.507579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 13:38:35.507680 ==
783 13:38:35.514472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 13:38:35.521171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 13:38:35.528560 [CA 0] Center 37 (7~68) winsize 62
786 13:38:35.531559 [CA 1] Center 37 (7~68) winsize 62
787 13:38:35.535241 [CA 2] Center 35 (5~66) winsize 62
788 13:38:35.538261 [CA 3] Center 35 (4~66) winsize 63
789 13:38:35.541793 [CA 4] Center 34 (4~65) winsize 62
790 13:38:35.544945 [CA 5] Center 34 (4~64) winsize 61
791 13:38:35.545029
792 13:38:35.548658 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 13:38:35.548742
794 13:38:35.551764 [CATrainingPosCal] consider 1 rank data
795 13:38:35.554820 u2DelayCellTimex100 = 270/100 ps
796 13:38:35.558398 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
797 13:38:35.561540 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
798 13:38:35.568471 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
799 13:38:35.571871 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
800 13:38:35.575096 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
801 13:38:35.578603 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
802 13:38:35.578688
803 13:38:35.581761 CA PerBit enable=1, Macro0, CA PI delay=34
804 13:38:35.581846
805 13:38:35.584987 [CBTSetCACLKResult] CA Dly = 34
806 13:38:35.585072 CS Dly: 5 (0~36)
807 13:38:35.585139 ==
808 13:38:35.588562 Dram Type= 6, Freq= 0, CH_0, rank 1
809 13:38:35.594715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 13:38:35.594801 ==
811 13:38:35.598280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 13:38:35.605039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 13:38:35.614195 [CA 0] Center 37 (7~68) winsize 62
814 13:38:35.617532 [CA 1] Center 37 (6~68) winsize 63
815 13:38:35.621081 [CA 2] Center 35 (5~66) winsize 62
816 13:38:35.624485 [CA 3] Center 35 (5~66) winsize 62
817 13:38:35.627333 [CA 4] Center 33 (3~64) winsize 62
818 13:38:35.630876 [CA 5] Center 34 (3~65) winsize 63
819 13:38:35.630961
820 13:38:35.634441 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 13:38:35.634526
822 13:38:35.637567 [CATrainingPosCal] consider 2 rank data
823 13:38:35.640732 u2DelayCellTimex100 = 270/100 ps
824 13:38:35.644333 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
825 13:38:35.647319 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
826 13:38:35.654013 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
827 13:38:35.657706 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
828 13:38:35.660674 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
829 13:38:35.664316 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 13:38:35.664403
831 13:38:35.667343 CA PerBit enable=1, Macro0, CA PI delay=34
832 13:38:35.667427
833 13:38:35.670931 [CBTSetCACLKResult] CA Dly = 34
834 13:38:35.671009 CS Dly: 5 (0~37)
835 13:38:35.671089
836 13:38:35.674064 ----->DramcWriteLeveling(PI) begin...
837 13:38:35.677548 ==
838 13:38:35.677624 Dram Type= 6, Freq= 0, CH_0, rank 0
839 13:38:35.684308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 13:38:35.684393 ==
841 13:38:35.687675 Write leveling (Byte 0): 30 => 30
842 13:38:35.691367 Write leveling (Byte 1): 30 => 30
843 13:38:35.691451 DramcWriteLeveling(PI) end<-----
844 13:38:35.691536
845 13:38:35.694529 ==
846 13:38:35.694612 Dram Type= 6, Freq= 0, CH_0, rank 0
847 13:38:35.701903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 13:38:35.702002 ==
849 13:38:35.702070 [Gating] SW mode calibration
850 13:38:35.709070 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 13:38:35.715798 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 13:38:35.719680 0 6 0 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
853 13:38:35.722850 0 6 4 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
854 13:38:35.729621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:38:35.733273 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:38:35.736513 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:38:35.743019 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:38:35.746588 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:38:35.749660 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:38:35.756362 0 7 0 | B1->B0 | 2a2a 3030 | 0 0 | (1 1) (0 0)
861 13:38:35.759488 0 7 4 | B1->B0 | 3b3b 4242 | 1 1 | (0 0) (0 0)
862 13:38:35.763103 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 13:38:35.769588 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 13:38:35.773245 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 13:38:35.776359 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 13:38:35.782962 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 13:38:35.786479 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 13:38:35.789963 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
869 13:38:35.793259 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 13:38:35.799845 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 13:38:35.802951 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 13:38:35.806534 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 13:38:35.813165 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 13:38:35.816149 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 13:38:35.819852 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 13:38:35.826153 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 13:38:35.829935 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 13:38:35.832710 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 13:38:35.839897 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 13:38:35.842858 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 13:38:35.846257 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 13:38:35.853235 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 13:38:35.856216 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 13:38:35.859946 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 13:38:35.866212 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 13:38:35.866302 Total UI for P1: 0, mck2ui 16
887 13:38:35.872882 best dqsien dly found for B0: ( 0, 10, 0)
888 13:38:35.872968 Total UI for P1: 0, mck2ui 16
889 13:38:35.876583 best dqsien dly found for B1: ( 0, 10, 0)
890 13:38:35.883329 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
891 13:38:35.886349 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
892 13:38:35.886434
893 13:38:35.889922 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
894 13:38:35.892967 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 13:38:35.896566 [Gating] SW calibration Done
896 13:38:35.896661 ==
897 13:38:35.900095 Dram Type= 6, Freq= 0, CH_0, rank 0
898 13:38:35.903370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 13:38:35.903463 ==
900 13:38:35.906412 RX Vref Scan: 0
901 13:38:35.906496
902 13:38:35.906595 RX Vref 0 -> 0, step: 1
903 13:38:35.906688
904 13:38:35.909965 RX Delay -130 -> 252, step: 16
905 13:38:35.913041 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 13:38:35.916632 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 13:38:35.923332 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 13:38:35.926355 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 13:38:35.929802 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 13:38:35.933295 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 13:38:35.936474 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 13:38:35.943254 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 13:38:35.946695 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 13:38:35.949691 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 13:38:35.953078 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 13:38:35.956350 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 13:38:35.963268 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
918 13:38:35.966268 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 13:38:35.969912 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 13:38:35.972851 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 13:38:35.972935 ==
922 13:38:35.976444 Dram Type= 6, Freq= 0, CH_0, rank 0
923 13:38:35.983352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 13:38:35.983438 ==
925 13:38:35.983505 DQS Delay:
926 13:38:35.986419 DQS0 = 0, DQS1 = 0
927 13:38:35.986503 DQM Delay:
928 13:38:35.986570 DQM0 = 82, DQM1 = 74
929 13:38:35.989502 DQ Delay:
930 13:38:35.993207 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 13:38:35.996092 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 13:38:35.999787 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 13:38:36.002794 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
934 13:38:36.002878
935 13:38:36.002944
936 13:38:36.003005 ==
937 13:38:36.006440 Dram Type= 6, Freq= 0, CH_0, rank 0
938 13:38:36.009990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 13:38:36.010075 ==
940 13:38:36.010141
941 13:38:36.010202
942 13:38:36.013342 TX Vref Scan disable
943 13:38:36.013427 == TX Byte 0 ==
944 13:38:36.019551 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
945 13:38:36.023242 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
946 13:38:36.023326 == TX Byte 1 ==
947 13:38:36.029876 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
948 13:38:36.033271 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
949 13:38:36.033380 ==
950 13:38:36.036161 Dram Type= 6, Freq= 0, CH_0, rank 0
951 13:38:36.039793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 13:38:36.039878 ==
953 13:38:36.053575 TX Vref=22, minBit 0, minWin=27, winSum=444
954 13:38:36.056991 TX Vref=24, minBit 0, minWin=27, winSum=447
955 13:38:36.060046 TX Vref=26, minBit 4, minWin=27, winSum=453
956 13:38:36.063557 TX Vref=28, minBit 0, minWin=28, winSum=456
957 13:38:36.066680 TX Vref=30, minBit 0, minWin=28, winSum=455
958 13:38:36.070372 TX Vref=32, minBit 0, minWin=28, winSum=453
959 13:38:36.077006 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
960 13:38:36.077091
961 13:38:36.079893 Final TX Range 1 Vref 28
962 13:38:36.079978
963 13:38:36.080044 ==
964 13:38:36.083433 Dram Type= 6, Freq= 0, CH_0, rank 0
965 13:38:36.087172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 13:38:36.087256 ==
967 13:38:36.087330
968 13:38:36.087407
969 13:38:36.090798 TX Vref Scan disable
970 13:38:36.093896 == TX Byte 0 ==
971 13:38:36.097313 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
972 13:38:36.101044 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
973 13:38:36.104281 == TX Byte 1 ==
974 13:38:36.107356 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
975 13:38:36.111000 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
976 13:38:36.111084
977 13:38:36.113921 [DATLAT]
978 13:38:36.114028 Freq=800, CH0 RK0
979 13:38:36.114096
980 13:38:36.117517 DATLAT Default: 0xa
981 13:38:36.117600 0, 0xFFFF, sum = 0
982 13:38:36.120766 1, 0xFFFF, sum = 0
983 13:38:36.120852 2, 0xFFFF, sum = 0
984 13:38:36.124311 3, 0xFFFF, sum = 0
985 13:38:36.124412 4, 0xFFFF, sum = 0
986 13:38:36.127417 5, 0xFFFF, sum = 0
987 13:38:36.127503 6, 0xFFFF, sum = 0
988 13:38:36.131046 7, 0xFFFF, sum = 0
989 13:38:36.131131 8, 0x0, sum = 1
990 13:38:36.134074 9, 0x0, sum = 2
991 13:38:36.134158 10, 0x0, sum = 3
992 13:38:36.137571 11, 0x0, sum = 4
993 13:38:36.137655 best_step = 9
994 13:38:36.137739
995 13:38:36.137805 ==
996 13:38:36.141081 Dram Type= 6, Freq= 0, CH_0, rank 0
997 13:38:36.144191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 13:38:36.144276 ==
999 13:38:36.147719 RX Vref Scan: 1
1000 13:38:36.147803
1001 13:38:36.150591 Set Vref Range= 32 -> 127
1002 13:38:36.150675
1003 13:38:36.150741 RX Vref 32 -> 127, step: 1
1004 13:38:36.150804
1005 13:38:36.154254 RX Delay -111 -> 252, step: 8
1006 13:38:36.154338
1007 13:38:36.157330 Set Vref, RX VrefLevel [Byte0]: 32
1008 13:38:36.160843 [Byte1]: 32
1009 13:38:36.164333
1010 13:38:36.164418 Set Vref, RX VrefLevel [Byte0]: 33
1011 13:38:36.167470 [Byte1]: 33
1012 13:38:36.172134
1013 13:38:36.172217 Set Vref, RX VrefLevel [Byte0]: 34
1014 13:38:36.175488 [Byte1]: 34
1015 13:38:36.179777
1016 13:38:36.179860 Set Vref, RX VrefLevel [Byte0]: 35
1017 13:38:36.182848 [Byte1]: 35
1018 13:38:36.186926
1019 13:38:36.187009 Set Vref, RX VrefLevel [Byte0]: 36
1020 13:38:36.190621 [Byte1]: 36
1021 13:38:36.194874
1022 13:38:36.194958 Set Vref, RX VrefLevel [Byte0]: 37
1023 13:38:36.198501 [Byte1]: 37
1024 13:38:36.202654
1025 13:38:36.202759 Set Vref, RX VrefLevel [Byte0]: 38
1026 13:38:36.206174 [Byte1]: 38
1027 13:38:36.209913
1028 13:38:36.209995 Set Vref, RX VrefLevel [Byte0]: 39
1029 13:38:36.213647 [Byte1]: 39
1030 13:38:36.217893
1031 13:38:36.217974 Set Vref, RX VrefLevel [Byte0]: 40
1032 13:38:36.220851 [Byte1]: 40
1033 13:38:36.225585
1034 13:38:36.225667 Set Vref, RX VrefLevel [Byte0]: 41
1035 13:38:36.228876 [Byte1]: 41
1036 13:38:36.232764
1037 13:38:36.232848 Set Vref, RX VrefLevel [Byte0]: 42
1038 13:38:36.236183 [Byte1]: 42
1039 13:38:36.241022
1040 13:38:36.241104 Set Vref, RX VrefLevel [Byte0]: 43
1041 13:38:36.243951 [Byte1]: 43
1042 13:38:36.248697
1043 13:38:36.248778 Set Vref, RX VrefLevel [Byte0]: 44
1044 13:38:36.251759 [Byte1]: 44
1045 13:38:36.255894
1046 13:38:36.255977 Set Vref, RX VrefLevel [Byte0]: 45
1047 13:38:36.259302 [Byte1]: 45
1048 13:38:36.263475
1049 13:38:36.263558 Set Vref, RX VrefLevel [Byte0]: 46
1050 13:38:36.266960 [Byte1]: 46
1051 13:38:36.271660
1052 13:38:36.271742 Set Vref, RX VrefLevel [Byte0]: 47
1053 13:38:36.274710 [Byte1]: 47
1054 13:38:36.278829
1055 13:38:36.278907 Set Vref, RX VrefLevel [Byte0]: 48
1056 13:38:36.282176 [Byte1]: 48
1057 13:38:36.286764
1058 13:38:36.286846 Set Vref, RX VrefLevel [Byte0]: 49
1059 13:38:36.289603 [Byte1]: 49
1060 13:38:36.294554
1061 13:38:36.294636 Set Vref, RX VrefLevel [Byte0]: 50
1062 13:38:36.297576 [Byte1]: 50
1063 13:38:36.301855
1064 13:38:36.301937 Set Vref, RX VrefLevel [Byte0]: 51
1065 13:38:36.304847 [Byte1]: 51
1066 13:38:36.309680
1067 13:38:36.309762 Set Vref, RX VrefLevel [Byte0]: 52
1068 13:38:36.312859 [Byte1]: 52
1069 13:38:36.317138
1070 13:38:36.317219 Set Vref, RX VrefLevel [Byte0]: 53
1071 13:38:36.320160 [Byte1]: 53
1072 13:38:36.324832
1073 13:38:36.324910 Set Vref, RX VrefLevel [Byte0]: 54
1074 13:38:36.327987 [Byte1]: 54
1075 13:38:36.332675
1076 13:38:36.332758 Set Vref, RX VrefLevel [Byte0]: 55
1077 13:38:36.335699 [Byte1]: 55
1078 13:38:36.340247
1079 13:38:36.340328 Set Vref, RX VrefLevel [Byte0]: 56
1080 13:38:36.343714 [Byte1]: 56
1081 13:38:36.347715
1082 13:38:36.347797 Set Vref, RX VrefLevel [Byte0]: 57
1083 13:38:36.351053 [Byte1]: 57
1084 13:38:36.355840
1085 13:38:36.355922 Set Vref, RX VrefLevel [Byte0]: 58
1086 13:38:36.358902 [Byte1]: 58
1087 13:38:36.363602
1088 13:38:36.363713 Set Vref, RX VrefLevel [Byte0]: 59
1089 13:38:36.366662 [Byte1]: 59
1090 13:38:36.371451
1091 13:38:36.371538 Set Vref, RX VrefLevel [Byte0]: 60
1092 13:38:36.374443 [Byte1]: 60
1093 13:38:36.378644
1094 13:38:36.378727 Set Vref, RX VrefLevel [Byte0]: 61
1095 13:38:36.382336 [Byte1]: 61
1096 13:38:36.386578
1097 13:38:36.386661 Set Vref, RX VrefLevel [Byte0]: 62
1098 13:38:36.389931 [Byte1]: 62
1099 13:38:36.393701
1100 13:38:36.393786 Set Vref, RX VrefLevel [Byte0]: 63
1101 13:38:36.396765 [Byte1]: 63
1102 13:38:36.401620
1103 13:38:36.401702 Set Vref, RX VrefLevel [Byte0]: 64
1104 13:38:36.404761 [Byte1]: 64
1105 13:38:36.409003
1106 13:38:36.409108 Set Vref, RX VrefLevel [Byte0]: 65
1107 13:38:36.412024 [Byte1]: 65
1108 13:38:36.416366
1109 13:38:36.416449 Set Vref, RX VrefLevel [Byte0]: 66
1110 13:38:36.420040 [Byte1]: 66
1111 13:38:36.424317
1112 13:38:36.424416 Set Vref, RX VrefLevel [Byte0]: 67
1113 13:38:36.427462 [Byte1]: 67
1114 13:38:36.431709
1115 13:38:36.431809 Set Vref, RX VrefLevel [Byte0]: 68
1116 13:38:36.435366 [Byte1]: 68
1117 13:38:36.439664
1118 13:38:36.439745 Set Vref, RX VrefLevel [Byte0]: 69
1119 13:38:36.442635 [Byte1]: 69
1120 13:38:36.447417
1121 13:38:36.447500 Set Vref, RX VrefLevel [Byte0]: 70
1122 13:38:36.450448 [Byte1]: 70
1123 13:38:36.454601
1124 13:38:36.454683 Set Vref, RX VrefLevel [Byte0]: 71
1125 13:38:36.458018 [Byte1]: 71
1126 13:38:36.462214
1127 13:38:36.462295 Set Vref, RX VrefLevel [Byte0]: 72
1128 13:38:36.465606 [Byte1]: 72
1129 13:38:36.470325
1130 13:38:36.470418 Set Vref, RX VrefLevel [Byte0]: 73
1131 13:38:36.473238 [Byte1]: 73
1132 13:38:36.477380
1133 13:38:36.477462 Final RX Vref Byte 0 = 53 to rank0
1134 13:38:36.480874 Final RX Vref Byte 1 = 55 to rank0
1135 13:38:36.484551 Final RX Vref Byte 0 = 53 to rank1
1136 13:38:36.487568 Final RX Vref Byte 1 = 55 to rank1==
1137 13:38:36.491200 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 13:38:36.497513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1139 13:38:36.497623 ==
1140 13:38:36.497723 DQS Delay:
1141 13:38:36.497813 DQS0 = 0, DQS1 = 0
1142 13:38:36.500822 DQM Delay:
1143 13:38:36.500902 DQM0 = 83, DQM1 = 73
1144 13:38:36.504156 DQ Delay:
1145 13:38:36.507881 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1146 13:38:36.507979 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1147 13:38:36.510992 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1148 13:38:36.514457 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1149 13:38:36.517507
1150 13:38:36.517577
1151 13:38:36.524165 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1152 13:38:36.527875 CH0 RK0: MR19=606, MR18=3E3E
1153 13:38:36.534509 CH0_RK0: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1154 13:38:36.534608
1155 13:38:36.537613 ----->DramcWriteLeveling(PI) begin...
1156 13:38:36.537698 ==
1157 13:38:36.540699 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 13:38:36.544264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1159 13:38:36.544363 ==
1160 13:38:36.547870 Write leveling (Byte 0): 31 => 31
1161 13:38:36.550684 Write leveling (Byte 1): 26 => 26
1162 13:38:36.554499 DramcWriteLeveling(PI) end<-----
1163 13:38:36.554603
1164 13:38:36.554695 ==
1165 13:38:36.557519 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 13:38:36.560614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1167 13:38:36.560711 ==
1168 13:38:36.564162 [Gating] SW mode calibration
1169 13:38:36.570970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 13:38:36.577576 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 13:38:36.580987 0 6 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
1172 13:38:36.583977 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
1173 13:38:36.591019 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:38:36.594124 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:38:36.597132 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:38:36.603784 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:38:36.607160 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:38:36.610496 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:38:36.617130 0 7 0 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
1180 13:38:36.620474 0 7 4 | B1->B0 | 4040 4545 | 1 0 | (0 0) (0 0)
1181 13:38:36.624056 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 13:38:36.630665 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 13:38:36.634292 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 13:38:36.637217 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 13:38:36.643864 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 13:38:36.647665 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1187 13:38:36.650636 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1188 13:38:36.657181 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1189 13:38:36.660845 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 13:38:36.663969 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 13:38:36.667592 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 13:38:36.674203 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 13:38:36.677238 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 13:38:36.680899 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 13:38:36.687503 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 13:38:36.690786 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:38:36.694311 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:38:36.700704 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:38:36.704363 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:38:36.707350 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:38:36.714014 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:38:36.717609 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:38:36.721037 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1204 13:38:36.727768 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 13:38:36.727851 Total UI for P1: 0, mck2ui 16
1206 13:38:36.730741 best dqsien dly found for B0: ( 0, 10, 0)
1207 13:38:36.734360 Total UI for P1: 0, mck2ui 16
1208 13:38:36.737312 best dqsien dly found for B1: ( 0, 10, 0)
1209 13:38:36.741220 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1210 13:38:36.747762 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1211 13:38:36.747846
1212 13:38:36.750847 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1213 13:38:36.754476 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1214 13:38:36.757503 [Gating] SW calibration Done
1215 13:38:36.757585 ==
1216 13:38:36.760917 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 13:38:36.763836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1218 13:38:36.763955 ==
1219 13:38:36.767604 RX Vref Scan: 0
1220 13:38:36.767706
1221 13:38:36.767796 RX Vref 0 -> 0, step: 1
1222 13:38:36.767881
1223 13:38:36.771260 RX Delay -130 -> 252, step: 16
1224 13:38:36.814798 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1225 13:38:36.815489 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1226 13:38:36.815582 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1227 13:38:36.815872 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1228 13:38:36.815971 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1229 13:38:36.816060 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1230 13:38:36.816152 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1231 13:38:36.816239 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1232 13:38:36.816337 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1233 13:38:36.816423 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1234 13:38:36.816545 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1235 13:38:36.819534 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1236 13:38:36.822800 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1237 13:38:36.826321 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1238 13:38:36.829857 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1239 13:38:36.836309 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1240 13:38:36.836386 ==
1241 13:38:36.839355 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 13:38:36.842998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1243 13:38:36.843085 ==
1244 13:38:36.843147 DQS Delay:
1245 13:38:36.846023 DQS0 = 0, DQS1 = 0
1246 13:38:36.846107 DQM Delay:
1247 13:38:36.849576 DQM0 = 82, DQM1 = 72
1248 13:38:36.849659 DQ Delay:
1249 13:38:36.853171 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1250 13:38:36.856234 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1251 13:38:36.859418 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1252 13:38:36.863142 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1253 13:38:36.863214
1254 13:38:36.863286
1255 13:38:36.863373 ==
1256 13:38:36.866051 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 13:38:36.869725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1258 13:38:36.869798 ==
1259 13:38:36.872755
1260 13:38:36.872833
1261 13:38:36.872933 TX Vref Scan disable
1262 13:38:36.876431 == TX Byte 0 ==
1263 13:38:36.879503 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1264 13:38:36.882895 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1265 13:38:36.885872 == TX Byte 1 ==
1266 13:38:36.889463 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1267 13:38:36.892546 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1268 13:38:36.892666 ==
1269 13:38:36.896229 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 13:38:36.902467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1271 13:38:36.902552 ==
1272 13:38:36.915025 TX Vref=22, minBit 13, minWin=26, winSum=443
1273 13:38:36.918441 TX Vref=24, minBit 14, minWin=27, winSum=448
1274 13:38:36.921773 TX Vref=26, minBit 0, minWin=28, winSum=450
1275 13:38:36.925189 TX Vref=28, minBit 0, minWin=28, winSum=449
1276 13:38:36.928345 TX Vref=30, minBit 0, minWin=28, winSum=456
1277 13:38:36.935488 TX Vref=32, minBit 2, minWin=28, winSum=456
1278 13:38:36.939224 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1279 13:38:36.939299
1280 13:38:36.942398 Final TX Range 1 Vref 30
1281 13:38:36.942473
1282 13:38:36.942545 ==
1283 13:38:36.946035 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 13:38:36.949740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1285 13:38:36.949834 ==
1286 13:38:36.949912
1287 13:38:36.949970
1288 13:38:36.953356 TX Vref Scan disable
1289 13:38:36.956503 == TX Byte 0 ==
1290 13:38:36.960187 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1291 13:38:36.963773 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1292 13:38:36.963879 == TX Byte 1 ==
1293 13:38:36.970575 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1294 13:38:36.973417 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1295 13:38:36.973497
1296 13:38:36.973561 [DATLAT]
1297 13:38:36.977096 Freq=800, CH0 RK1
1298 13:38:36.977192
1299 13:38:36.977283 DATLAT Default: 0x9
1300 13:38:36.980074 0, 0xFFFF, sum = 0
1301 13:38:36.980157 1, 0xFFFF, sum = 0
1302 13:38:36.983843 2, 0xFFFF, sum = 0
1303 13:38:36.983925 3, 0xFFFF, sum = 0
1304 13:38:36.986879 4, 0xFFFF, sum = 0
1305 13:38:36.986962 5, 0xFFFF, sum = 0
1306 13:38:36.990595 6, 0xFFFF, sum = 0
1307 13:38:36.993535 7, 0xFFFF, sum = 0
1308 13:38:36.993618 8, 0x0, sum = 1
1309 13:38:36.993684 9, 0x0, sum = 2
1310 13:38:36.997039 10, 0x0, sum = 3
1311 13:38:36.997121 11, 0x0, sum = 4
1312 13:38:37.000136 best_step = 9
1313 13:38:37.000230
1314 13:38:37.000306 ==
1315 13:38:37.003754 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 13:38:37.007016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1317 13:38:37.007098 ==
1318 13:38:37.010683 RX Vref Scan: 0
1319 13:38:37.010765
1320 13:38:37.010828 RX Vref 0 -> 0, step: 1
1321 13:38:37.010889
1322 13:38:37.013669 RX Delay -111 -> 252, step: 8
1323 13:38:37.020347 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1324 13:38:37.023767 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1325 13:38:37.027119 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1326 13:38:37.030425 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1327 13:38:37.033848 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1328 13:38:37.040528 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1329 13:38:37.044075 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1330 13:38:37.046941 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1331 13:38:37.050405 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1332 13:38:37.053573 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1333 13:38:37.060060 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1334 13:38:37.063760 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1335 13:38:37.066857 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1336 13:38:37.070000 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1337 13:38:37.073731 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1338 13:38:37.080349 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1339 13:38:37.080458 ==
1340 13:38:37.083301 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 13:38:37.086947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1342 13:38:37.087062 ==
1343 13:38:37.087160 DQS Delay:
1344 13:38:37.090388 DQS0 = 0, DQS1 = 0
1345 13:38:37.090488 DQM Delay:
1346 13:38:37.093299 DQM0 = 86, DQM1 = 73
1347 13:38:37.093412 DQ Delay:
1348 13:38:37.096546 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1349 13:38:37.100010 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1350 13:38:37.103205 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1351 13:38:37.106786 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1352 13:38:37.106887
1353 13:38:37.106976
1354 13:38:37.116674 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1355 13:38:37.116776 CH0 RK1: MR19=606, MR18=4242
1356 13:38:37.123333 CH0_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1357 13:38:37.126709 [RxdqsGatingPostProcess] freq 800
1358 13:38:37.133199 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1359 13:38:37.136683 Pre-setting of DQS Precalculation
1360 13:38:37.139606 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1361 13:38:37.139708 ==
1362 13:38:37.143056 Dram Type= 6, Freq= 0, CH_1, rank 0
1363 13:38:37.146697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 13:38:37.146802 ==
1365 13:38:37.153406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1366 13:38:37.159831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1367 13:38:37.168143 [CA 0] Center 37 (6~68) winsize 63
1368 13:38:37.171672 [CA 1] Center 37 (6~68) winsize 63
1369 13:38:37.174652 [CA 2] Center 34 (4~65) winsize 62
1370 13:38:37.178253 [CA 3] Center 34 (4~65) winsize 62
1371 13:38:37.181242 [CA 4] Center 33 (3~64) winsize 62
1372 13:38:37.184886 [CA 5] Center 33 (3~64) winsize 62
1373 13:38:37.184988
1374 13:38:37.187910 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1375 13:38:37.188004
1376 13:38:37.191507 [CATrainingPosCal] consider 1 rank data
1377 13:38:37.194472 u2DelayCellTimex100 = 270/100 ps
1378 13:38:37.198140 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1379 13:38:37.201081 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1380 13:38:37.207606 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1381 13:38:37.211309 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1382 13:38:37.214368 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1383 13:38:37.218080 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1384 13:38:37.218157
1385 13:38:37.221108 CA PerBit enable=1, Macro0, CA PI delay=33
1386 13:38:37.221204
1387 13:38:37.224836 [CBTSetCACLKResult] CA Dly = 33
1388 13:38:37.224930 CS Dly: 5 (0~36)
1389 13:38:37.225024 ==
1390 13:38:37.227971 Dram Type= 6, Freq= 0, CH_1, rank 1
1391 13:38:37.234509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1392 13:38:37.234589 ==
1393 13:38:37.238151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 13:38:37.244949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 13:38:37.253892 [CA 0] Center 36 (6~67) winsize 62
1396 13:38:37.257406 [CA 1] Center 36 (5~68) winsize 64
1397 13:38:37.260629 [CA 2] Center 34 (4~65) winsize 62
1398 13:38:37.263700 [CA 3] Center 34 (4~65) winsize 62
1399 13:38:37.266966 [CA 4] Center 33 (3~64) winsize 62
1400 13:38:37.270573 [CA 5] Center 33 (3~63) winsize 61
1401 13:38:37.270676
1402 13:38:37.273552 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1403 13:38:37.273658
1404 13:38:37.276857 [CATrainingPosCal] consider 2 rank data
1405 13:38:37.280351 u2DelayCellTimex100 = 270/100 ps
1406 13:38:37.283889 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1407 13:38:37.286962 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1408 13:38:37.293701 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 13:38:37.296769 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 13:38:37.300488 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 13:38:37.303433 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1412 13:38:37.303539
1413 13:38:37.306990 CA PerBit enable=1, Macro0, CA PI delay=33
1414 13:38:37.307087
1415 13:38:37.310095 [CBTSetCACLKResult] CA Dly = 33
1416 13:38:37.310204 CS Dly: 5 (0~36)
1417 13:38:37.310304
1418 13:38:37.313572 ----->DramcWriteLeveling(PI) begin...
1419 13:38:37.316759 ==
1420 13:38:37.320403 Dram Type= 6, Freq= 0, CH_1, rank 0
1421 13:38:37.323361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1422 13:38:37.323467 ==
1423 13:38:37.327140 Write leveling (Byte 0): 22 => 22
1424 13:38:37.330276 Write leveling (Byte 1): 22 => 22
1425 13:38:37.333747 DramcWriteLeveling(PI) end<-----
1426 13:38:37.333829
1427 13:38:37.333894 ==
1428 13:38:37.336729 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 13:38:37.340119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1430 13:38:37.340219 ==
1431 13:38:37.343367 [Gating] SW mode calibration
1432 13:38:37.350423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1433 13:38:37.356522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1434 13:38:37.360214 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
1435 13:38:37.363247 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 13:38:37.366774 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 13:38:37.373665 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 13:38:37.376954 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 13:38:37.380291 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 13:38:37.386889 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 13:38:37.390095 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1442 13:38:37.393429 0 7 0 | B1->B0 | 2e2e 3d3d | 0 0 | (1 1) (0 0)
1443 13:38:37.400205 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1444 13:38:37.403832 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 13:38:37.407297 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 13:38:37.413780 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 13:38:37.417642 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 13:38:37.420598 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 13:38:37.427323 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1450 13:38:37.430938 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1451 13:38:37.433991 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 13:38:37.440829 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 13:38:37.443764 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 13:38:37.447208 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 13:38:37.450594 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 13:38:37.457541 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 13:38:37.460781 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 13:38:37.464244 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 13:38:37.470307 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 13:38:37.473862 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 13:38:37.477404 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 13:38:37.484395 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 13:38:37.487296 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 13:38:37.490873 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 13:38:37.497356 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1466 13:38:37.500578 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1467 13:38:37.503734 Total UI for P1: 0, mck2ui 16
1468 13:38:37.507675 best dqsien dly found for B1: ( 0, 9, 30)
1469 13:38:37.510552 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1470 13:38:37.514104 Total UI for P1: 0, mck2ui 16
1471 13:38:37.517608 best dqsien dly found for B0: ( 0, 9, 30)
1472 13:38:37.520573 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1473 13:38:37.523765 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1474 13:38:37.524172
1475 13:38:37.530519 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1476 13:38:37.534286 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1477 13:38:37.535010 [Gating] SW calibration Done
1478 13:38:37.537160 ==
1479 13:38:37.540874 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 13:38:37.543782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1481 13:38:37.544196 ==
1482 13:38:37.544519 RX Vref Scan: 0
1483 13:38:37.544817
1484 13:38:37.547412 RX Vref 0 -> 0, step: 1
1485 13:38:37.547855
1486 13:38:37.550395 RX Delay -130 -> 252, step: 16
1487 13:38:37.554049 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1488 13:38:37.557569 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1489 13:38:37.560733 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1490 13:38:37.567216 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1491 13:38:37.570780 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1492 13:38:37.573861 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1493 13:38:37.577274 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1494 13:38:37.580821 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1495 13:38:37.587136 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1496 13:38:37.590761 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1497 13:38:37.593952 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1498 13:38:37.597585 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1499 13:38:37.601065 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1500 13:38:37.604788 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1501 13:38:37.612008 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1502 13:38:37.615736 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1503 13:38:37.616158 ==
1504 13:38:37.619116 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 13:38:37.622506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1506 13:38:37.622922 ==
1507 13:38:37.623248 DQS Delay:
1508 13:38:37.625834 DQS0 = 0, DQS1 = 0
1509 13:38:37.626246 DQM Delay:
1510 13:38:37.629382 DQM0 = 81, DQM1 = 71
1511 13:38:37.629798 DQ Delay:
1512 13:38:37.632597 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1513 13:38:37.636747 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1514 13:38:37.640046 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1515 13:38:37.643371 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1516 13:38:37.643796
1517 13:38:37.644122
1518 13:38:37.644422 ==
1519 13:38:37.646512 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 13:38:37.650140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1521 13:38:37.650630 ==
1522 13:38:37.650959
1523 13:38:37.651288
1524 13:38:37.653453 TX Vref Scan disable
1525 13:38:37.653960 == TX Byte 0 ==
1526 13:38:37.659940 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1527 13:38:37.663603 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1528 13:38:37.664102 == TX Byte 1 ==
1529 13:38:37.670175 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1530 13:38:37.673338 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1531 13:38:37.673757 ==
1532 13:38:37.676324 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 13:38:37.679962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1534 13:38:37.680421 ==
1535 13:38:37.693577 TX Vref=22, minBit 3, minWin=27, winSum=447
1536 13:38:37.697181 TX Vref=24, minBit 0, minWin=28, winSum=454
1537 13:38:37.700059 TX Vref=26, minBit 0, minWin=28, winSum=456
1538 13:38:37.703588 TX Vref=28, minBit 0, minWin=28, winSum=457
1539 13:38:37.706902 TX Vref=30, minBit 0, minWin=28, winSum=460
1540 13:38:37.710072 TX Vref=32, minBit 0, minWin=28, winSum=459
1541 13:38:37.717204 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1542 13:38:37.717678
1543 13:38:37.720150 Final TX Range 1 Vref 30
1544 13:38:37.720561
1545 13:38:37.720882 ==
1546 13:38:37.723857 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 13:38:37.726810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1548 13:38:37.727246 ==
1549 13:38:37.727569
1550 13:38:37.727865
1551 13:38:37.730535 TX Vref Scan disable
1552 13:38:37.733480 == TX Byte 0 ==
1553 13:38:37.736884 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1554 13:38:37.740162 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1555 13:38:37.743456 == TX Byte 1 ==
1556 13:38:37.746929 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1557 13:38:37.750091 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1558 13:38:37.750503
1559 13:38:37.753626 [DATLAT]
1560 13:38:37.754174 Freq=800, CH1 RK0
1561 13:38:37.754510
1562 13:38:37.756815 DATLAT Default: 0xa
1563 13:38:37.757342 0, 0xFFFF, sum = 0
1564 13:38:37.760207 1, 0xFFFF, sum = 0
1565 13:38:37.760594 2, 0xFFFF, sum = 0
1566 13:38:37.763394 3, 0xFFFF, sum = 0
1567 13:38:37.763889 4, 0xFFFF, sum = 0
1568 13:38:37.767018 5, 0xFFFF, sum = 0
1569 13:38:37.767438 6, 0xFFFF, sum = 0
1570 13:38:37.770116 7, 0xFFFF, sum = 0
1571 13:38:37.770516 8, 0x0, sum = 1
1572 13:38:37.773600 9, 0x0, sum = 2
1573 13:38:37.774018 10, 0x0, sum = 3
1574 13:38:37.776876 11, 0x0, sum = 4
1575 13:38:37.777315 best_step = 9
1576 13:38:37.777650
1577 13:38:37.777951 ==
1578 13:38:37.779815 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 13:38:37.786553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1580 13:38:37.786970 ==
1581 13:38:37.787299 RX Vref Scan: 1
1582 13:38:37.787602
1583 13:38:37.790339 Set Vref Range= 32 -> 127
1584 13:38:37.790751
1585 13:38:37.793250 RX Vref 32 -> 127, step: 1
1586 13:38:37.793701
1587 13:38:37.794080 RX Delay -111 -> 252, step: 8
1588 13:38:37.796799
1589 13:38:37.797243 Set Vref, RX VrefLevel [Byte0]: 32
1590 13:38:37.799904 [Byte1]: 32
1591 13:38:37.804771
1592 13:38:37.805181 Set Vref, RX VrefLevel [Byte0]: 33
1593 13:38:37.807837 [Byte1]: 33
1594 13:38:37.811803
1595 13:38:37.812252 Set Vref, RX VrefLevel [Byte0]: 34
1596 13:38:37.815199 [Byte1]: 34
1597 13:38:37.819533
1598 13:38:37.819948 Set Vref, RX VrefLevel [Byte0]: 35
1599 13:38:37.822989 [Byte1]: 35
1600 13:38:37.827140
1601 13:38:37.827623 Set Vref, RX VrefLevel [Byte0]: 36
1602 13:38:37.830954 [Byte1]: 36
1603 13:38:37.835223
1604 13:38:37.835634 Set Vref, RX VrefLevel [Byte0]: 37
1605 13:38:37.838416 [Byte1]: 37
1606 13:38:37.842554
1607 13:38:37.843077 Set Vref, RX VrefLevel [Byte0]: 38
1608 13:38:37.845740 [Byte1]: 38
1609 13:38:37.850606
1610 13:38:37.851089 Set Vref, RX VrefLevel [Byte0]: 39
1611 13:38:37.853559 [Byte1]: 39
1612 13:38:37.857950
1613 13:38:37.858433 Set Vref, RX VrefLevel [Byte0]: 40
1614 13:38:37.861314 [Byte1]: 40
1615 13:38:37.865487
1616 13:38:37.865898 Set Vref, RX VrefLevel [Byte0]: 41
1617 13:38:37.868977 [Byte1]: 41
1618 13:38:37.873223
1619 13:38:37.873680 Set Vref, RX VrefLevel [Byte0]: 42
1620 13:38:37.876776 [Byte1]: 42
1621 13:38:37.880623
1622 13:38:37.881110 Set Vref, RX VrefLevel [Byte0]: 43
1623 13:38:37.884334 [Byte1]: 43
1624 13:38:37.888661
1625 13:38:37.889076 Set Vref, RX VrefLevel [Byte0]: 44
1626 13:38:37.891752 [Byte1]: 44
1627 13:38:37.896125
1628 13:38:37.896545 Set Vref, RX VrefLevel [Byte0]: 45
1629 13:38:37.899651 [Byte1]: 45
1630 13:38:37.903830
1631 13:38:37.904248 Set Vref, RX VrefLevel [Byte0]: 46
1632 13:38:37.907304 [Byte1]: 46
1633 13:38:37.911925
1634 13:38:37.912470 Set Vref, RX VrefLevel [Byte0]: 47
1635 13:38:37.914826 [Byte1]: 47
1636 13:38:37.919091
1637 13:38:37.919507 Set Vref, RX VrefLevel [Byte0]: 48
1638 13:38:37.922859 [Byte1]: 48
1639 13:38:37.926790
1640 13:38:37.927255 Set Vref, RX VrefLevel [Byte0]: 49
1641 13:38:37.930158 [Byte1]: 49
1642 13:38:37.934695
1643 13:38:37.935129 Set Vref, RX VrefLevel [Byte0]: 50
1644 13:38:37.937770 [Byte1]: 50
1645 13:38:37.941790
1646 13:38:37.942205 Set Vref, RX VrefLevel [Byte0]: 51
1647 13:38:37.945534 [Byte1]: 51
1648 13:38:37.949841
1649 13:38:37.950258 Set Vref, RX VrefLevel [Byte0]: 52
1650 13:38:37.952884 [Byte1]: 52
1651 13:38:37.957167
1652 13:38:37.957623 Set Vref, RX VrefLevel [Byte0]: 53
1653 13:38:37.960858 [Byte1]: 53
1654 13:38:37.965081
1655 13:38:37.965539 Set Vref, RX VrefLevel [Byte0]: 54
1656 13:38:37.968111 [Byte1]: 54
1657 13:38:37.972459
1658 13:38:37.972876 Set Vref, RX VrefLevel [Byte0]: 55
1659 13:38:37.976121 [Byte1]: 55
1660 13:38:37.980107
1661 13:38:37.980521 Set Vref, RX VrefLevel [Byte0]: 56
1662 13:38:37.983557 [Byte1]: 56
1663 13:38:37.988248
1664 13:38:37.988747 Set Vref, RX VrefLevel [Byte0]: 57
1665 13:38:37.991518 [Byte1]: 57
1666 13:38:37.995611
1667 13:38:37.996025 Set Vref, RX VrefLevel [Byte0]: 58
1668 13:38:37.998816 [Byte1]: 58
1669 13:38:38.003418
1670 13:38:38.003831 Set Vref, RX VrefLevel [Byte0]: 59
1671 13:38:38.006372 [Byte1]: 59
1672 13:38:38.011349
1673 13:38:38.011905 Set Vref, RX VrefLevel [Byte0]: 60
1674 13:38:38.014191 [Byte1]: 60
1675 13:38:38.018802
1676 13:38:38.019260 Set Vref, RX VrefLevel [Byte0]: 61
1677 13:38:38.021817 [Byte1]: 61
1678 13:38:38.026276
1679 13:38:38.026724 Set Vref, RX VrefLevel [Byte0]: 62
1680 13:38:38.029208 [Byte1]: 62
1681 13:38:38.033924
1682 13:38:38.034342 Set Vref, RX VrefLevel [Byte0]: 63
1683 13:38:38.037038 [Byte1]: 63
1684 13:38:38.041494
1685 13:38:38.041913 Set Vref, RX VrefLevel [Byte0]: 64
1686 13:38:38.045061 [Byte1]: 64
1687 13:38:38.049433
1688 13:38:38.049924 Set Vref, RX VrefLevel [Byte0]: 65
1689 13:38:38.052465 [Byte1]: 65
1690 13:38:38.056702
1691 13:38:38.057186 Set Vref, RX VrefLevel [Byte0]: 66
1692 13:38:38.060242 [Byte1]: 66
1693 13:38:38.064795
1694 13:38:38.065359 Set Vref, RX VrefLevel [Byte0]: 67
1695 13:38:38.067597 [Byte1]: 67
1696 13:38:38.072343
1697 13:38:38.072774 Set Vref, RX VrefLevel [Byte0]: 68
1698 13:38:38.075410 [Byte1]: 68
1699 13:38:38.079693
1700 13:38:38.080154 Set Vref, RX VrefLevel [Byte0]: 69
1701 13:38:38.082649 [Byte1]: 69
1702 13:38:38.087613
1703 13:38:38.088053 Set Vref, RX VrefLevel [Byte0]: 70
1704 13:38:38.090672 [Byte1]: 70
1705 13:38:38.095024
1706 13:38:38.095479 Set Vref, RX VrefLevel [Byte0]: 71
1707 13:38:38.098455 [Byte1]: 71
1708 13:38:38.102565
1709 13:38:38.102986 Set Vref, RX VrefLevel [Byte0]: 72
1710 13:38:38.105708 [Byte1]: 72
1711 13:38:38.110668
1712 13:38:38.111091 Set Vref, RX VrefLevel [Byte0]: 73
1713 13:38:38.113757 [Byte1]: 73
1714 13:38:38.117810
1715 13:38:38.118232 Set Vref, RX VrefLevel [Byte0]: 74
1716 13:38:38.121231 [Byte1]: 74
1717 13:38:38.125581
1718 13:38:38.126161 Set Vref, RX VrefLevel [Byte0]: 75
1719 13:38:38.128841 [Byte1]: 75
1720 13:38:38.133225
1721 13:38:38.133674 Set Vref, RX VrefLevel [Byte0]: 76
1722 13:38:38.136380 [Byte1]: 76
1723 13:38:38.141093
1724 13:38:38.141578 Set Vref, RX VrefLevel [Byte0]: 77
1725 13:38:38.144376 [Byte1]: 77
1726 13:38:38.148795
1727 13:38:38.149257 Set Vref, RX VrefLevel [Byte0]: 78
1728 13:38:38.151860 [Byte1]: 78
1729 13:38:38.155937
1730 13:38:38.156485 Final RX Vref Byte 0 = 59 to rank0
1731 13:38:38.159751 Final RX Vref Byte 1 = 55 to rank0
1732 13:38:38.162697 Final RX Vref Byte 0 = 59 to rank1
1733 13:38:38.165822 Final RX Vref Byte 1 = 55 to rank1==
1734 13:38:38.169557 Dram Type= 6, Freq= 0, CH_1, rank 0
1735 13:38:38.176210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1736 13:38:38.176781 ==
1737 13:38:38.177379 DQS Delay:
1738 13:38:38.177765 DQS0 = 0, DQS1 = 0
1739 13:38:38.179230 DQM Delay:
1740 13:38:38.179775 DQM0 = 81, DQM1 = 75
1741 13:38:38.183056 DQ Delay:
1742 13:38:38.183480 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1743 13:38:38.186693 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1744 13:38:38.190210 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1745 13:38:38.193268 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1746 13:38:38.193710
1747 13:38:38.194035
1748 13:38:38.203756 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1749 13:38:38.206737 CH1 RK0: MR19=606, MR18=5151
1750 13:38:38.210091 CH1_RK0: MR19=0x606, MR18=0x5151, DQSOSC=389, MR23=63, INC=97, DEC=65
1751 13:38:38.212993
1752 13:38:38.216580 ----->DramcWriteLeveling(PI) begin...
1753 13:38:38.217023 ==
1754 13:38:38.220193 Dram Type= 6, Freq= 0, CH_1, rank 1
1755 13:38:38.223283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1756 13:38:38.223704 ==
1757 13:38:38.226352 Write leveling (Byte 0): 24 => 24
1758 13:38:38.229996 Write leveling (Byte 1): 25 => 25
1759 13:38:38.233071 DramcWriteLeveling(PI) end<-----
1760 13:38:38.233543
1761 13:38:38.233983 ==
1762 13:38:38.236284 Dram Type= 6, Freq= 0, CH_1, rank 1
1763 13:38:38.239806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1764 13:38:38.240387 ==
1765 13:38:38.243175 [Gating] SW mode calibration
1766 13:38:38.249920 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1767 13:38:38.256538 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1768 13:38:38.260049 0 6 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1769 13:38:38.263037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 13:38:38.270093 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1771 13:38:38.273067 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 13:38:38.276811 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1773 13:38:38.279819 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 13:38:38.286406 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 13:38:38.290091 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 13:38:38.293174 0 7 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1777 13:38:38.299826 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 13:38:38.303484 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1779 13:38:38.306489 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 13:38:38.313524 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 13:38:38.316243 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 13:38:38.320072 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 13:38:38.326580 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1784 13:38:38.329798 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 13:38:38.333605 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 13:38:38.339665 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 13:38:38.343272 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 13:38:38.346790 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 13:38:38.353061 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 13:38:38.356323 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 13:38:38.359941 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 13:38:38.366539 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 13:38:38.369791 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 13:38:38.373258 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 13:38:38.379943 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 13:38:38.382916 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 13:38:38.386441 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 13:38:38.389475 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 13:38:38.396300 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1800 13:38:38.399471 Total UI for P1: 0, mck2ui 16
1801 13:38:38.403247 best dqsien dly found for B0: ( 0, 9, 26)
1802 13:38:38.406214 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1803 13:38:38.409794 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1804 13:38:38.413087 Total UI for P1: 0, mck2ui 16
1805 13:38:38.416123 best dqsien dly found for B1: ( 0, 9, 30)
1806 13:38:38.419467 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1807 13:38:38.423122 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1808 13:38:38.426280
1809 13:38:38.429757 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1810 13:38:38.432848 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1811 13:38:38.436041 [Gating] SW calibration Done
1812 13:38:38.436553 ==
1813 13:38:38.439225 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 13:38:38.442893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1815 13:38:38.443568 ==
1816 13:38:38.445974 RX Vref Scan: 0
1817 13:38:38.446516
1818 13:38:38.446965 RX Vref 0 -> 0, step: 1
1819 13:38:38.447283
1820 13:38:38.449547 RX Delay -130 -> 252, step: 16
1821 13:38:38.452568 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1822 13:38:38.459288 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1823 13:38:38.462904 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1824 13:38:38.465883 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1825 13:38:38.468993 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1826 13:38:38.472010 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1827 13:38:38.479308 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1828 13:38:38.482082 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1829 13:38:38.485586 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1830 13:38:38.489000 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1831 13:38:38.492141 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1832 13:38:38.498905 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1833 13:38:38.502006 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1834 13:38:38.505561 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1835 13:38:38.508776 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1836 13:38:38.515183 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1837 13:38:38.515787 ==
1838 13:38:38.518806 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 13:38:38.522290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1840 13:38:38.522911 ==
1841 13:38:38.523466 DQS Delay:
1842 13:38:38.525195 DQS0 = 0, DQS1 = 0
1843 13:38:38.525845 DQM Delay:
1844 13:38:38.528677 DQM0 = 87, DQM1 = 73
1845 13:38:38.529266 DQ Delay:
1846 13:38:38.532420 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1847 13:38:38.535300 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1848 13:38:38.538693 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1849 13:38:38.542159 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1850 13:38:38.542585
1851 13:38:38.542917
1852 13:38:38.543254 ==
1853 13:38:38.545156 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 13:38:38.548765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1855 13:38:38.549190 ==
1856 13:38:38.549577
1857 13:38:38.549935
1858 13:38:38.551775 TX Vref Scan disable
1859 13:38:38.555820 == TX Byte 0 ==
1860 13:38:38.558578 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1861 13:38:38.562136 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1862 13:38:38.565517 == TX Byte 1 ==
1863 13:38:38.568833 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1864 13:38:38.571889 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1865 13:38:38.572446 ==
1866 13:38:38.575762 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 13:38:38.578920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 13:38:38.581915 ==
1869 13:38:38.593644 TX Vref=22, minBit 2, minWin=27, winSum=450
1870 13:38:38.596816 TX Vref=24, minBit 8, minWin=27, winSum=452
1871 13:38:38.599896 TX Vref=26, minBit 5, minWin=28, winSum=455
1872 13:38:38.603508 TX Vref=28, minBit 1, minWin=28, winSum=458
1873 13:38:38.606601 TX Vref=30, minBit 0, minWin=28, winSum=458
1874 13:38:38.610175 TX Vref=32, minBit 0, minWin=27, winSum=455
1875 13:38:38.616653 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
1876 13:38:38.617077
1877 13:38:38.620092 Final TX Range 1 Vref 28
1878 13:38:38.620513
1879 13:38:38.620841 ==
1880 13:38:38.623272 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 13:38:38.626428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1882 13:38:38.626866 ==
1883 13:38:38.627199
1884 13:38:38.629888
1885 13:38:38.630286 TX Vref Scan disable
1886 13:38:38.633382 == TX Byte 0 ==
1887 13:38:38.636448 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1888 13:38:38.640197 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1889 13:38:38.643145 == TX Byte 1 ==
1890 13:38:38.646873 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1891 13:38:38.649881 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1892 13:38:38.653588
1893 13:38:38.654005 [DATLAT]
1894 13:38:38.654333 Freq=800, CH1 RK1
1895 13:38:38.654642
1896 13:38:38.656649 DATLAT Default: 0x9
1897 13:38:38.657068 0, 0xFFFF, sum = 0
1898 13:38:38.660191 1, 0xFFFF, sum = 0
1899 13:38:38.660617 2, 0xFFFF, sum = 0
1900 13:38:38.663166 3, 0xFFFF, sum = 0
1901 13:38:38.663593 4, 0xFFFF, sum = 0
1902 13:38:38.666924 5, 0xFFFF, sum = 0
1903 13:38:38.669840 6, 0xFFFF, sum = 0
1904 13:38:38.670273 7, 0xFFFF, sum = 0
1905 13:38:38.670623 8, 0x0, sum = 1
1906 13:38:38.673075 9, 0x0, sum = 2
1907 13:38:38.673560 10, 0x0, sum = 3
1908 13:38:38.676687 11, 0x0, sum = 4
1909 13:38:38.677114 best_step = 9
1910 13:38:38.677499
1911 13:38:38.677819 ==
1912 13:38:38.679827 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 13:38:38.686678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1914 13:38:38.687101 ==
1915 13:38:38.687434 RX Vref Scan: 0
1916 13:38:38.687741
1917 13:38:38.689831 RX Vref 0 -> 0, step: 1
1918 13:38:38.690250
1919 13:38:38.693404 RX Delay -111 -> 252, step: 8
1920 13:38:38.696413 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1921 13:38:38.699886 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1922 13:38:38.706481 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1923 13:38:38.710305 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1924 13:38:38.713250 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1925 13:38:38.716419 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1926 13:38:38.720006 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1927 13:38:38.723174 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1928 13:38:38.729728 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1929 13:38:38.733054 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1930 13:38:38.736564 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1931 13:38:38.739909 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1932 13:38:38.743216 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1933 13:38:38.749891 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1934 13:38:38.753349 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1935 13:38:38.756353 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1936 13:38:38.756746 ==
1937 13:38:38.759624 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 13:38:38.763208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1939 13:38:38.766331 ==
1940 13:38:38.766752 DQS Delay:
1941 13:38:38.767086 DQS0 = 0, DQS1 = 0
1942 13:38:38.769858 DQM Delay:
1943 13:38:38.770294 DQM0 = 84, DQM1 = 74
1944 13:38:38.773661 DQ Delay:
1945 13:38:38.776542 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1946 13:38:38.777014 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1947 13:38:38.779641 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1948 13:38:38.783330 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1949 13:38:38.783750
1950 13:38:38.786377
1951 13:38:38.793171 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1952 13:38:38.797006 CH1 RK1: MR19=606, MR18=3636
1953 13:38:38.803100 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1954 13:38:38.803525 [RxdqsGatingPostProcess] freq 800
1955 13:38:38.810121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1956 13:38:38.812990 Pre-setting of DQS Precalculation
1957 13:38:38.816377 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1958 13:38:38.826542 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1959 13:38:38.833108 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1960 13:38:38.833562
1961 13:38:38.833897
1962 13:38:38.836529 [Calibration Summary] 1600 Mbps
1963 13:38:38.836950 CH 0, Rank 0
1964 13:38:38.840101 SW Impedance : PASS
1965 13:38:38.840526 DUTY Scan : NO K
1966 13:38:38.843156 ZQ Calibration : PASS
1967 13:38:38.846595 Jitter Meter : NO K
1968 13:38:38.847059 CBT Training : PASS
1969 13:38:38.849513 Write leveling : PASS
1970 13:38:38.852917 RX DQS gating : PASS
1971 13:38:38.853389 RX DQ/DQS(RDDQC) : PASS
1972 13:38:38.856425 TX DQ/DQS : PASS
1973 13:38:38.859328 RX DATLAT : PASS
1974 13:38:38.859732 RX DQ/DQS(Engine): PASS
1975 13:38:38.862768 TX OE : NO K
1976 13:38:38.863326 All Pass.
1977 13:38:38.863842
1978 13:38:38.866014 CH 0, Rank 1
1979 13:38:38.866510 SW Impedance : PASS
1980 13:38:38.869744 DUTY Scan : NO K
1981 13:38:38.872918 ZQ Calibration : PASS
1982 13:38:38.873402 Jitter Meter : NO K
1983 13:38:38.875999 CBT Training : PASS
1984 13:38:38.879738 Write leveling : PASS
1985 13:38:38.880157 RX DQS gating : PASS
1986 13:38:38.882630 RX DQ/DQS(RDDQC) : PASS
1987 13:38:38.883051 TX DQ/DQS : PASS
1988 13:38:38.886324 RX DATLAT : PASS
1989 13:38:38.889315 RX DQ/DQS(Engine): PASS
1990 13:38:38.889764 TX OE : NO K
1991 13:38:38.893048 All Pass.
1992 13:38:38.893521
1993 13:38:38.893858 CH 1, Rank 0
1994 13:38:38.896096 SW Impedance : PASS
1995 13:38:38.896533 DUTY Scan : NO K
1996 13:38:38.899671 ZQ Calibration : PASS
1997 13:38:38.902813 Jitter Meter : NO K
1998 13:38:38.903234 CBT Training : PASS
1999 13:38:38.906518 Write leveling : PASS
2000 13:38:38.909538 RX DQS gating : PASS
2001 13:38:38.909986 RX DQ/DQS(RDDQC) : PASS
2002 13:38:38.913127 TX DQ/DQS : PASS
2003 13:38:38.916263 RX DATLAT : PASS
2004 13:38:38.916724 RX DQ/DQS(Engine): PASS
2005 13:38:38.919757 TX OE : NO K
2006 13:38:38.920322 All Pass.
2007 13:38:38.920811
2008 13:38:38.922600 CH 1, Rank 1
2009 13:38:38.922978 SW Impedance : PASS
2010 13:38:38.925967 DUTY Scan : NO K
2011 13:38:38.926385 ZQ Calibration : PASS
2012 13:38:38.929330 Jitter Meter : NO K
2013 13:38:38.932977 CBT Training : PASS
2014 13:38:38.933283 Write leveling : PASS
2015 13:38:38.936043 RX DQS gating : PASS
2016 13:38:38.939521 RX DQ/DQS(RDDQC) : PASS
2017 13:38:38.939746 TX DQ/DQS : PASS
2018 13:38:38.942564 RX DATLAT : PASS
2019 13:38:38.946379 RX DQ/DQS(Engine): PASS
2020 13:38:38.946615 TX OE : NO K
2021 13:38:38.949971 All Pass.
2022 13:38:38.950384
2023 13:38:38.950707 DramC Write-DBI off
2024 13:38:38.952822 PER_BANK_REFRESH: Hybrid Mode
2025 13:38:38.953236 TX_TRACKING: ON
2026 13:38:38.956452 [GetDramInforAfterCalByMRR] Vendor 6.
2027 13:38:38.962894 [GetDramInforAfterCalByMRR] Revision 606.
2028 13:38:38.966697 [GetDramInforAfterCalByMRR] Revision 2 0.
2029 13:38:38.967110 MR0 0x3939
2030 13:38:38.967434 MR8 0x1111
2031 13:38:38.969787 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2032 13:38:38.970202
2033 13:38:38.973159 MR0 0x3939
2034 13:38:38.973780 MR8 0x1111
2035 13:38:38.976179 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2036 13:38:38.976823
2037 13:38:38.986014 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2038 13:38:38.989283 [FAST_K] Save calibration result to emmc
2039 13:38:38.993061 [FAST_K] Save calibration result to emmc
2040 13:38:38.996128 dram_init: config_dvfs: 1
2041 13:38:38.999266 dramc_set_vcore_voltage set vcore to 662500
2042 13:38:39.002959 Read voltage for 1200, 2
2043 13:38:39.003376 Vio18 = 0
2044 13:38:39.003707 Vcore = 662500
2045 13:38:39.006005 Vdram = 0
2046 13:38:39.006561 Vddq = 0
2047 13:38:39.006898 Vmddr = 0
2048 13:38:39.012658 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2049 13:38:39.016429 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2050 13:38:39.019335 MEM_TYPE=3, freq_sel=15
2051 13:38:39.022960 sv_algorithm_assistance_LP4_1600
2052 13:38:39.026150 ============ PULL DRAM RESETB DOWN ============
2053 13:38:39.029675 ========== PULL DRAM RESETB DOWN end =========
2054 13:38:39.035988 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2055 13:38:39.039587 ===================================
2056 13:38:39.040186 LPDDR4 DRAM CONFIGURATION
2057 13:38:39.043017 ===================================
2058 13:38:39.046035 EX_ROW_EN[0] = 0x0
2059 13:38:39.049721 EX_ROW_EN[1] = 0x0
2060 13:38:39.050168 LP4Y_EN = 0x0
2061 13:38:39.052637 WORK_FSP = 0x0
2062 13:38:39.053058 WL = 0x4
2063 13:38:39.056189 RL = 0x4
2064 13:38:39.056640 BL = 0x2
2065 13:38:39.059548 RPST = 0x0
2066 13:38:39.060132 RD_PRE = 0x0
2067 13:38:39.062963 WR_PRE = 0x1
2068 13:38:39.063503 WR_PST = 0x0
2069 13:38:39.066518 DBI_WR = 0x0
2070 13:38:39.066935 DBI_RD = 0x0
2071 13:38:39.069558 OTF = 0x1
2072 13:38:39.072470 ===================================
2073 13:38:39.075995 ===================================
2074 13:38:39.076423 ANA top config
2075 13:38:39.079839 ===================================
2076 13:38:39.082586 DLL_ASYNC_EN = 0
2077 13:38:39.086192 ALL_SLAVE_EN = 0
2078 13:38:39.086612 NEW_RANK_MODE = 1
2079 13:38:39.089908 DLL_IDLE_MODE = 1
2080 13:38:39.092771 LP45_APHY_COMB_EN = 1
2081 13:38:39.096354 TX_ODT_DIS = 1
2082 13:38:39.099280 NEW_8X_MODE = 1
2083 13:38:39.103110 ===================================
2084 13:38:39.106028 ===================================
2085 13:38:39.106450 data_rate = 2400
2086 13:38:39.109148 CKR = 1
2087 13:38:39.112794 DQ_P2S_RATIO = 8
2088 13:38:39.115824 ===================================
2089 13:38:39.119498 CA_P2S_RATIO = 8
2090 13:38:39.122571 DQ_CA_OPEN = 0
2091 13:38:39.126079 DQ_SEMI_OPEN = 0
2092 13:38:39.126556 CA_SEMI_OPEN = 0
2093 13:38:39.129215 CA_FULL_RATE = 0
2094 13:38:39.132923 DQ_CKDIV4_EN = 0
2095 13:38:39.136032 CA_CKDIV4_EN = 0
2096 13:38:39.139697 CA_PREDIV_EN = 0
2097 13:38:39.143191 PH8_DLY = 17
2098 13:38:39.143624 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2099 13:38:39.146337 DQ_AAMCK_DIV = 4
2100 13:38:39.149607 CA_AAMCK_DIV = 4
2101 13:38:39.152915 CA_ADMCK_DIV = 4
2102 13:38:39.155902 DQ_TRACK_CA_EN = 0
2103 13:38:39.159593 CA_PICK = 1200
2104 13:38:39.160030 CA_MCKIO = 1200
2105 13:38:39.162690 MCKIO_SEMI = 0
2106 13:38:39.166108 PLL_FREQ = 2366
2107 13:38:39.169185 DQ_UI_PI_RATIO = 32
2108 13:38:39.172411 CA_UI_PI_RATIO = 0
2109 13:38:39.175549 ===================================
2110 13:38:39.179343 ===================================
2111 13:38:39.182798 memory_type:LPDDR4
2112 13:38:39.183227 GP_NUM : 10
2113 13:38:39.186051 SRAM_EN : 1
2114 13:38:39.186471 MD32_EN : 0
2115 13:38:39.188964 ===================================
2116 13:38:39.192490 [ANA_INIT] >>>>>>>>>>>>>>
2117 13:38:39.195571 <<<<<< [CONFIGURE PHASE]: ANA_TX
2118 13:38:39.199175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2119 13:38:39.202583 ===================================
2120 13:38:39.205883 data_rate = 2400,PCW = 0X5b00
2121 13:38:39.209055 ===================================
2122 13:38:39.212797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2123 13:38:39.219604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2124 13:38:39.222507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2125 13:38:39.229275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2126 13:38:39.232895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2127 13:38:39.235889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2128 13:38:39.236320 [ANA_INIT] flow start
2129 13:38:39.238800 [ANA_INIT] PLL >>>>>>>>
2130 13:38:39.242421 [ANA_INIT] PLL <<<<<<<<
2131 13:38:39.242851 [ANA_INIT] MIDPI >>>>>>>>
2132 13:38:39.246112 [ANA_INIT] MIDPI <<<<<<<<
2133 13:38:39.249210 [ANA_INIT] DLL >>>>>>>>
2134 13:38:39.249702 [ANA_INIT] DLL <<<<<<<<
2135 13:38:39.252782 [ANA_INIT] flow end
2136 13:38:39.256132 ============ LP4 DIFF to SE enter ============
2137 13:38:39.259281 ============ LP4 DIFF to SE exit ============
2138 13:38:39.262689 [ANA_INIT] <<<<<<<<<<<<<
2139 13:38:39.266010 [Flow] Enable top DCM control >>>>>
2140 13:38:39.269349 [Flow] Enable top DCM control <<<<<
2141 13:38:39.272743 Enable DLL master slave shuffle
2142 13:38:39.279278 ==============================================================
2143 13:38:39.279740 Gating Mode config
2144 13:38:39.285701 ==============================================================
2145 13:38:39.286180 Config description:
2146 13:38:39.295645 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2147 13:38:39.302202 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2148 13:38:39.309026 SELPH_MODE 0: By rank 1: By Phase
2149 13:38:39.312701 ==============================================================
2150 13:38:39.315606 GAT_TRACK_EN = 1
2151 13:38:39.318639 RX_GATING_MODE = 2
2152 13:38:39.322371 RX_GATING_TRACK_MODE = 2
2153 13:38:39.325325 SELPH_MODE = 1
2154 13:38:39.328936 PICG_EARLY_EN = 1
2155 13:38:39.332049 VALID_LAT_VALUE = 1
2156 13:38:39.338864 ==============================================================
2157 13:38:39.342000 Enter into Gating configuration >>>>
2158 13:38:39.345636 Exit from Gating configuration <<<<
2159 13:38:39.348709 Enter into DVFS_PRE_config >>>>>
2160 13:38:39.359028 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2161 13:38:39.362005 Exit from DVFS_PRE_config <<<<<
2162 13:38:39.365650 Enter into PICG configuration >>>>
2163 13:38:39.368696 Exit from PICG configuration <<<<
2164 13:38:39.372249 [RX_INPUT] configuration >>>>>
2165 13:38:39.372667 [RX_INPUT] configuration <<<<<
2166 13:38:39.378742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2167 13:38:39.382120 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2168 13:38:39.389015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2169 13:38:39.395174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2170 13:38:39.402149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2171 13:38:39.408605 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2172 13:38:39.412198 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2173 13:38:39.415441 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2174 13:38:39.422191 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2175 13:38:39.425482 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2176 13:38:39.428424 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2177 13:38:39.432192 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 13:38:39.435271 ===================================
2179 13:38:39.438989 LPDDR4 DRAM CONFIGURATION
2180 13:38:39.441969 ===================================
2181 13:38:39.445563 EX_ROW_EN[0] = 0x0
2182 13:38:39.445982 EX_ROW_EN[1] = 0x0
2183 13:38:39.448712 LP4Y_EN = 0x0
2184 13:38:39.449128 WORK_FSP = 0x0
2185 13:38:39.452393 WL = 0x4
2186 13:38:39.452807 RL = 0x4
2187 13:38:39.455445 BL = 0x2
2188 13:38:39.456043 RPST = 0x0
2189 13:38:39.458540 RD_PRE = 0x0
2190 13:38:39.458963 WR_PRE = 0x1
2191 13:38:39.461949 WR_PST = 0x0
2192 13:38:39.462371 DBI_WR = 0x0
2193 13:38:39.465775 DBI_RD = 0x0
2194 13:38:39.468815 OTF = 0x1
2195 13:38:39.471844 ===================================
2196 13:38:39.475303 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2197 13:38:39.478466 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2198 13:38:39.482107 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 13:38:39.485623 ===================================
2200 13:38:39.488666 LPDDR4 DRAM CONFIGURATION
2201 13:38:39.492043 ===================================
2202 13:38:39.495376 EX_ROW_EN[0] = 0x10
2203 13:38:39.495919 EX_ROW_EN[1] = 0x0
2204 13:38:39.498703 LP4Y_EN = 0x0
2205 13:38:39.499127 WORK_FSP = 0x0
2206 13:38:39.501975 WL = 0x4
2207 13:38:39.502396 RL = 0x4
2208 13:38:39.505673 BL = 0x2
2209 13:38:39.506251 RPST = 0x0
2210 13:38:39.508863 RD_PRE = 0x0
2211 13:38:39.509276 WR_PRE = 0x1
2212 13:38:39.511646 WR_PST = 0x0
2213 13:38:39.512121 DBI_WR = 0x0
2214 13:38:39.515246 DBI_RD = 0x0
2215 13:38:39.515665 OTF = 0x1
2216 13:38:39.518829 ===================================
2217 13:38:39.525252 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2218 13:38:39.525718 ==
2219 13:38:39.528888 Dram Type= 6, Freq= 0, CH_0, rank 0
2220 13:38:39.535238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2221 13:38:39.535678 ==
2222 13:38:39.536015 [Duty_Offset_Calibration]
2223 13:38:39.538727 B0:0 B1:2 CA:1
2224 13:38:39.539241
2225 13:38:39.541858 [DutyScan_Calibration_Flow] k_type=0
2226 13:38:39.550910
2227 13:38:39.551346 ==CLK 0==
2228 13:38:39.553969 Final CLK duty delay cell = 0
2229 13:38:39.557003 [0] MAX Duty = 5093%(X100), DQS PI = 12
2230 13:38:39.560580 [0] MIN Duty = 4938%(X100), DQS PI = 54
2231 13:38:39.561163 [0] AVG Duty = 5015%(X100)
2232 13:38:39.563846
2233 13:38:39.567438 CH0 CLK Duty spec in!! Max-Min= 155%
2234 13:38:39.570582 [DutyScan_Calibration_Flow] ====Done====
2235 13:38:39.571191
2236 13:38:39.574042 [DutyScan_Calibration_Flow] k_type=1
2237 13:38:39.590098
2238 13:38:39.590707 ==DQS 0 ==
2239 13:38:39.592910 Final DQS duty delay cell = 0
2240 13:38:39.596287 [0] MAX Duty = 5125%(X100), DQS PI = 30
2241 13:38:39.599948 [0] MIN Duty = 5031%(X100), DQS PI = 6
2242 13:38:39.600585 [0] AVG Duty = 5078%(X100)
2243 13:38:39.603632
2244 13:38:39.604110 ==DQS 1 ==
2245 13:38:39.606497 Final DQS duty delay cell = 0
2246 13:38:39.609668 [0] MAX Duty = 5062%(X100), DQS PI = 56
2247 13:38:39.613043 [0] MIN Duty = 4906%(X100), DQS PI = 16
2248 13:38:39.613516 [0] AVG Duty = 4984%(X100)
2249 13:38:39.616702
2250 13:38:39.619874 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2251 13:38:39.620396
2252 13:38:39.622885 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2253 13:38:39.626504 [DutyScan_Calibration_Flow] ====Done====
2254 13:38:39.627096
2255 13:38:39.629980 [DutyScan_Calibration_Flow] k_type=3
2256 13:38:39.647179
2257 13:38:39.647606 ==DQM 0 ==
2258 13:38:39.650199 Final DQM duty delay cell = 0
2259 13:38:39.653841 [0] MAX Duty = 5156%(X100), DQS PI = 20
2260 13:38:39.657103 [0] MIN Duty = 4969%(X100), DQS PI = 40
2261 13:38:39.660185 [0] AVG Duty = 5062%(X100)
2262 13:38:39.660778
2263 13:38:39.661186 ==DQM 1 ==
2264 13:38:39.663961 Final DQM duty delay cell = 4
2265 13:38:39.667045 [4] MAX Duty = 5187%(X100), DQS PI = 54
2266 13:38:39.670276 [4] MIN Duty = 5000%(X100), DQS PI = 18
2267 13:38:39.673673 [4] AVG Duty = 5093%(X100)
2268 13:38:39.674207
2269 13:38:39.676747 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2270 13:38:39.677391
2271 13:38:39.680355 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2272 13:38:39.683271 [DutyScan_Calibration_Flow] ====Done====
2273 13:38:39.683702
2274 13:38:39.687162 [DutyScan_Calibration_Flow] k_type=2
2275 13:38:39.701864
2276 13:38:39.702291 ==DQ 0 ==
2277 13:38:39.705255 Final DQ duty delay cell = -4
2278 13:38:39.709046 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2279 13:38:39.712283 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2280 13:38:39.715107 [-4] AVG Duty = 4937%(X100)
2281 13:38:39.715539
2282 13:38:39.715964 ==DQ 1 ==
2283 13:38:39.720784 Final DQ duty delay cell = -4
2284 13:38:39.722198 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2285 13:38:39.725524 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2286 13:38:39.728876 [-4] AVG Duty = 4969%(X100)
2287 13:38:39.729366
2288 13:38:39.731913 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2289 13:38:39.732331
2290 13:38:39.735622 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2291 13:38:39.738386 [DutyScan_Calibration_Flow] ====Done====
2292 13:38:39.738967 ==
2293 13:38:39.742030 Dram Type= 6, Freq= 0, CH_1, rank 0
2294 13:38:39.745155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2295 13:38:39.745743 ==
2296 13:38:39.748775 [Duty_Offset_Calibration]
2297 13:38:39.749184 B0:0 B1:5 CA:-5
2298 13:38:39.749585
2299 13:38:39.751783 [DutyScan_Calibration_Flow] k_type=0
2300 13:38:39.762772
2301 13:38:39.763303 ==CLK 0==
2302 13:38:39.765879 Final CLK duty delay cell = 0
2303 13:38:39.769404 [0] MAX Duty = 5094%(X100), DQS PI = 24
2304 13:38:39.772592 [0] MIN Duty = 4876%(X100), DQS PI = 52
2305 13:38:39.773181 [0] AVG Duty = 4985%(X100)
2306 13:38:39.775853
2307 13:38:39.779443 CH1 CLK Duty spec in!! Max-Min= 218%
2308 13:38:39.782629 [DutyScan_Calibration_Flow] ====Done====
2309 13:38:39.783048
2310 13:38:39.785742 [DutyScan_Calibration_Flow] k_type=1
2311 13:38:39.800795
2312 13:38:39.801359 ==DQS 0 ==
2313 13:38:39.804615 Final DQS duty delay cell = 0
2314 13:38:39.807613 [0] MAX Duty = 5125%(X100), DQS PI = 16
2315 13:38:39.811342 [0] MIN Duty = 4875%(X100), DQS PI = 42
2316 13:38:39.814183 [0] AVG Duty = 5000%(X100)
2317 13:38:39.814700
2318 13:38:39.815220 ==DQS 1 ==
2319 13:38:39.817752 Final DQS duty delay cell = -4
2320 13:38:39.821332 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2321 13:38:39.824595 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2322 13:38:39.827723 [-4] AVG Duty = 4953%(X100)
2323 13:38:39.828164
2324 13:38:39.831201 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2325 13:38:39.831664
2326 13:38:39.834025 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2327 13:38:39.837704 [DutyScan_Calibration_Flow] ====Done====
2328 13:38:39.838247
2329 13:38:39.841245 [DutyScan_Calibration_Flow] k_type=3
2330 13:38:39.856610
2331 13:38:39.857247 ==DQM 0 ==
2332 13:38:39.859561 Final DQM duty delay cell = -4
2333 13:38:39.862605 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2334 13:38:39.866196 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2335 13:38:39.869355 [-4] AVG Duty = 4953%(X100)
2336 13:38:39.869784
2337 13:38:39.870118 ==DQM 1 ==
2338 13:38:39.873009 Final DQM duty delay cell = -4
2339 13:38:39.876133 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2340 13:38:39.879328 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2341 13:38:39.882546 [-4] AVG Duty = 4968%(X100)
2342 13:38:39.882968
2343 13:38:39.886243 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2344 13:38:39.886664
2345 13:38:39.889155 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2346 13:38:39.892583 [DutyScan_Calibration_Flow] ====Done====
2347 13:38:39.893120
2348 13:38:39.896282 [DutyScan_Calibration_Flow] k_type=2
2349 13:38:39.913885
2350 13:38:39.914328 ==DQ 0 ==
2351 13:38:39.916829 Final DQ duty delay cell = 0
2352 13:38:39.919889 [0] MAX Duty = 5062%(X100), DQS PI = 0
2353 13:38:39.923504 [0] MIN Duty = 4969%(X100), DQS PI = 42
2354 13:38:39.923955 [0] AVG Duty = 5015%(X100)
2355 13:38:39.924306
2356 13:38:39.927100 ==DQ 1 ==
2357 13:38:39.930013 Final DQ duty delay cell = 0
2358 13:38:39.933581 [0] MAX Duty = 5031%(X100), DQS PI = 8
2359 13:38:39.936944 [0] MIN Duty = 4907%(X100), DQS PI = 0
2360 13:38:39.937497 [0] AVG Duty = 4969%(X100)
2361 13:38:39.937896
2362 13:38:39.940031 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2363 13:38:39.940465
2364 13:38:39.943739 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2365 13:38:39.950216 [DutyScan_Calibration_Flow] ====Done====
2366 13:38:39.953609 nWR fixed to 30
2367 13:38:39.953927 [ModeRegInit_LP4] CH0 RK0
2368 13:38:39.956705 [ModeRegInit_LP4] CH0 RK1
2369 13:38:39.959854 [ModeRegInit_LP4] CH1 RK0
2370 13:38:39.960146 [ModeRegInit_LP4] CH1 RK1
2371 13:38:39.963335 match AC timing 6
2372 13:38:39.967081 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2373 13:38:39.969724 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2374 13:38:39.976629 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2375 13:38:39.979660 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2376 13:38:39.986434 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2377 13:38:39.986668 ==
2378 13:38:39.989518 Dram Type= 6, Freq= 0, CH_0, rank 0
2379 13:38:39.993160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2380 13:38:39.993451 ==
2381 13:38:39.999704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2382 13:38:40.003120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2383 13:38:40.012771 [CA 0] Center 39 (9~70) winsize 62
2384 13:38:40.015907 [CA 1] Center 39 (8~70) winsize 63
2385 13:38:40.019372 [CA 2] Center 36 (5~67) winsize 63
2386 13:38:40.022603 [CA 3] Center 35 (5~66) winsize 62
2387 13:38:40.026449 [CA 4] Center 34 (3~65) winsize 63
2388 13:38:40.029513 [CA 5] Center 33 (3~64) winsize 62
2389 13:38:40.029738
2390 13:38:40.033157 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2391 13:38:40.033514
2392 13:38:40.035995 [CATrainingPosCal] consider 1 rank data
2393 13:38:40.039602 u2DelayCellTimex100 = 270/100 ps
2394 13:38:40.043354 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2395 13:38:40.046340 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2396 13:38:40.053207 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2397 13:38:40.056184 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2398 13:38:40.059469 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2399 13:38:40.062894 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2400 13:38:40.063486
2401 13:38:40.066161 CA PerBit enable=1, Macro0, CA PI delay=33
2402 13:38:40.066745
2403 13:38:40.069690 [CBTSetCACLKResult] CA Dly = 33
2404 13:38:40.070250 CS Dly: 7 (0~38)
2405 13:38:40.073063 ==
2406 13:38:40.073718 Dram Type= 6, Freq= 0, CH_0, rank 1
2407 13:38:40.079338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2408 13:38:40.079773 ==
2409 13:38:40.082916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2410 13:38:40.089739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2411 13:38:40.098393 [CA 0] Center 39 (8~70) winsize 63
2412 13:38:40.101864 [CA 1] Center 39 (8~70) winsize 63
2413 13:38:40.104954 [CA 2] Center 36 (5~67) winsize 63
2414 13:38:40.108678 [CA 3] Center 35 (4~66) winsize 63
2415 13:38:40.111996 [CA 4] Center 33 (3~64) winsize 62
2416 13:38:40.114959 [CA 5] Center 34 (3~65) winsize 63
2417 13:38:40.115500
2418 13:38:40.118627 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2419 13:38:40.119045
2420 13:38:40.121556 [CATrainingPosCal] consider 2 rank data
2421 13:38:40.125027 u2DelayCellTimex100 = 270/100 ps
2422 13:38:40.128746 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2423 13:38:40.131833 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2424 13:38:40.138118 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2425 13:38:40.141660 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2426 13:38:40.144795 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2427 13:38:40.148049 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2428 13:38:40.148235
2429 13:38:40.151862 CA PerBit enable=1, Macro0, CA PI delay=33
2430 13:38:40.152043
2431 13:38:40.154880 [CBTSetCACLKResult] CA Dly = 33
2432 13:38:40.155061 CS Dly: 7 (0~39)
2433 13:38:40.155229
2434 13:38:40.157965 ----->DramcWriteLeveling(PI) begin...
2435 13:38:40.161587 ==
2436 13:38:40.164618 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 13:38:40.168297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2438 13:38:40.168479 ==
2439 13:38:40.171245 Write leveling (Byte 0): 27 => 27
2440 13:38:40.174637 Write leveling (Byte 1): 27 => 27
2441 13:38:40.178151 DramcWriteLeveling(PI) end<-----
2442 13:38:40.178339
2443 13:38:40.178479 ==
2444 13:38:40.181708 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 13:38:40.184793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2446 13:38:40.184975 ==
2447 13:38:40.188268 [Gating] SW mode calibration
2448 13:38:40.194841 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2449 13:38:40.198108 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2450 13:38:40.204857 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2451 13:38:40.207807 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2452 13:38:40.211635 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2453 13:38:40.218473 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2454 13:38:40.221573 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2455 13:38:40.224558 0 11 20 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 1)
2456 13:38:40.231201 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 13:38:40.235088 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2458 13:38:40.238137 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 13:38:40.245258 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 13:38:40.248257 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2461 13:38:40.251833 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 13:38:40.258348 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2463 13:38:40.261825 0 12 20 | B1->B0 | 3636 3c3c | 1 0 | (0 0) (0 0)
2464 13:38:40.264941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 13:38:40.271497 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 13:38:40.275424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 13:38:40.278397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 13:38:40.285002 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 13:38:40.288428 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 13:38:40.292119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2471 13:38:40.295444 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2472 13:38:40.301857 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 13:38:40.305039 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 13:38:40.308502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 13:38:40.315295 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 13:38:40.318255 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 13:38:40.322099 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 13:38:40.328230 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 13:38:40.331957 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 13:38:40.335145 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 13:38:40.341774 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 13:38:40.344731 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 13:38:40.348466 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 13:38:40.354754 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 13:38:40.358163 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 13:38:40.361483 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 13:38:40.368269 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2488 13:38:40.371287 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2489 13:38:40.374870 Total UI for P1: 0, mck2ui 16
2490 13:38:40.378070 best dqsien dly found for B0: ( 0, 15, 20)
2491 13:38:40.381194 Total UI for P1: 0, mck2ui 16
2492 13:38:40.384998 best dqsien dly found for B1: ( 0, 15, 20)
2493 13:38:40.387866 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2494 13:38:40.391237 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2495 13:38:40.391465
2496 13:38:40.394816 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2497 13:38:40.398451 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2498 13:38:40.401416 [Gating] SW calibration Done
2499 13:38:40.401695 ==
2500 13:38:40.404896 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 13:38:40.407708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2502 13:38:40.407937 ==
2503 13:38:40.411387 RX Vref Scan: 0
2504 13:38:40.411614
2505 13:38:40.414966 RX Vref 0 -> 0, step: 1
2506 13:38:40.415318
2507 13:38:40.415640 RX Delay -40 -> 252, step: 8
2508 13:38:40.421204 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2509 13:38:40.424833 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2510 13:38:40.427886 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2511 13:38:40.431145 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2512 13:38:40.434773 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2513 13:38:40.441487 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2514 13:38:40.444670 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2515 13:38:40.448154 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2516 13:38:40.450643 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2517 13:38:40.454438 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2518 13:38:40.460743 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2519 13:38:40.464408 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2520 13:38:40.467520 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2521 13:38:40.470978 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2522 13:38:40.477462 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2523 13:38:40.480772 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2524 13:38:40.480870 ==
2525 13:38:40.484212 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 13:38:40.487472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2527 13:38:40.487560 ==
2528 13:38:40.487627 DQS Delay:
2529 13:38:40.490980 DQS0 = 0, DQS1 = 0
2530 13:38:40.491100 DQM Delay:
2531 13:38:40.493897 DQM0 = 115, DQM1 = 106
2532 13:38:40.493986 DQ Delay:
2533 13:38:40.497546 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2534 13:38:40.500811 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2535 13:38:40.504496 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2536 13:38:40.507332 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2537 13:38:40.510890
2538 13:38:40.511002
2539 13:38:40.511088 ==
2540 13:38:40.514487 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 13:38:40.517617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 13:38:40.517753 ==
2543 13:38:40.517861
2544 13:38:40.517960
2545 13:38:40.521005 TX Vref Scan disable
2546 13:38:40.521140 == TX Byte 0 ==
2547 13:38:40.527728 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2548 13:38:40.530797 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2549 13:38:40.530972 == TX Byte 1 ==
2550 13:38:40.537663 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2551 13:38:40.540711 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2552 13:38:40.540954 ==
2553 13:38:40.544364 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 13:38:40.547367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2555 13:38:40.547668 ==
2556 13:38:40.559756 TX Vref=22, minBit 8, minWin=25, winSum=418
2557 13:38:40.562821 TX Vref=24, minBit 5, minWin=25, winSum=423
2558 13:38:40.566378 TX Vref=26, minBit 8, minWin=25, winSum=429
2559 13:38:40.569568 TX Vref=28, minBit 9, minWin=26, winSum=437
2560 13:38:40.573178 TX Vref=30, minBit 5, minWin=26, winSum=431
2561 13:38:40.576367 TX Vref=32, minBit 5, minWin=26, winSum=432
2562 13:38:40.582948 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
2563 13:38:40.583299
2564 13:38:40.586509 Final TX Range 1 Vref 28
2565 13:38:40.586888
2566 13:38:40.587234 ==
2567 13:38:40.589653 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 13:38:40.592769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2569 13:38:40.593083 ==
2570 13:38:40.593346
2571 13:38:40.596350
2572 13:38:40.596732 TX Vref Scan disable
2573 13:38:40.599865 == TX Byte 0 ==
2574 13:38:40.602876 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2575 13:38:40.606390 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2576 13:38:40.609531 == TX Byte 1 ==
2577 13:38:40.613283 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2578 13:38:40.616123 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2579 13:38:40.616416
2580 13:38:40.619650 [DATLAT]
2581 13:38:40.620014 Freq=1200, CH0 RK0
2582 13:38:40.620348
2583 13:38:40.622576 DATLAT Default: 0xd
2584 13:38:40.622868 0, 0xFFFF, sum = 0
2585 13:38:40.626164 1, 0xFFFF, sum = 0
2586 13:38:40.626548 2, 0xFFFF, sum = 0
2587 13:38:40.629670 3, 0xFFFF, sum = 0
2588 13:38:40.629947 4, 0xFFFF, sum = 0
2589 13:38:40.632794 5, 0xFFFF, sum = 0
2590 13:38:40.633090 6, 0xFFFF, sum = 0
2591 13:38:40.635961 7, 0xFFFF, sum = 0
2592 13:38:40.639544 8, 0xFFFF, sum = 0
2593 13:38:40.639828 9, 0xFFFF, sum = 0
2594 13:38:40.642668 10, 0xFFFF, sum = 0
2595 13:38:40.643042 11, 0x0, sum = 1
2596 13:38:40.646468 12, 0x0, sum = 2
2597 13:38:40.646797 13, 0x0, sum = 3
2598 13:38:40.647036 14, 0x0, sum = 4
2599 13:38:40.649401 best_step = 12
2600 13:38:40.649794
2601 13:38:40.650124 ==
2602 13:38:40.653126 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 13:38:40.656421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2604 13:38:40.656716 ==
2605 13:38:40.659491 RX Vref Scan: 1
2606 13:38:40.659805
2607 13:38:40.660038 Set Vref Range= 32 -> 127
2608 13:38:40.663239
2609 13:38:40.663530 RX Vref 32 -> 127, step: 1
2610 13:38:40.663760
2611 13:38:40.666212 RX Delay -21 -> 252, step: 4
2612 13:38:40.666505
2613 13:38:40.669261 Set Vref, RX VrefLevel [Byte0]: 32
2614 13:38:40.673012 [Byte1]: 32
2615 13:38:40.676123
2616 13:38:40.676417 Set Vref, RX VrefLevel [Byte0]: 33
2617 13:38:40.679203 [Byte1]: 33
2618 13:38:40.683744
2619 13:38:40.684148 Set Vref, RX VrefLevel [Byte0]: 34
2620 13:38:40.687462 [Byte1]: 34
2621 13:38:40.692199
2622 13:38:40.692523 Set Vref, RX VrefLevel [Byte0]: 35
2623 13:38:40.695228 [Byte1]: 35
2624 13:38:40.699970
2625 13:38:40.700314 Set Vref, RX VrefLevel [Byte0]: 36
2626 13:38:40.703289 [Byte1]: 36
2627 13:38:40.707553
2628 13:38:40.707920 Set Vref, RX VrefLevel [Byte0]: 37
2629 13:38:40.711100 [Byte1]: 37
2630 13:38:40.715499
2631 13:38:40.715905 Set Vref, RX VrefLevel [Byte0]: 38
2632 13:38:40.719298 [Byte1]: 38
2633 13:38:40.723577
2634 13:38:40.724026 Set Vref, RX VrefLevel [Byte0]: 39
2635 13:38:40.727038 [Byte1]: 39
2636 13:38:40.731312
2637 13:38:40.731626 Set Vref, RX VrefLevel [Byte0]: 40
2638 13:38:40.734686 [Byte1]: 40
2639 13:38:40.739364
2640 13:38:40.739673 Set Vref, RX VrefLevel [Byte0]: 41
2641 13:38:40.743028 [Byte1]: 41
2642 13:38:40.747450
2643 13:38:40.747921 Set Vref, RX VrefLevel [Byte0]: 42
2644 13:38:40.750605 [Byte1]: 42
2645 13:38:40.755330
2646 13:38:40.755727 Set Vref, RX VrefLevel [Byte0]: 43
2647 13:38:40.758415 [Byte1]: 43
2648 13:38:40.763400
2649 13:38:40.763817 Set Vref, RX VrefLevel [Byte0]: 44
2650 13:38:40.766374 [Byte1]: 44
2651 13:38:40.771458
2652 13:38:40.771755 Set Vref, RX VrefLevel [Byte0]: 45
2653 13:38:40.774536 [Byte1]: 45
2654 13:38:40.779357
2655 13:38:40.779750 Set Vref, RX VrefLevel [Byte0]: 46
2656 13:38:40.782534 [Byte1]: 46
2657 13:38:40.787106
2658 13:38:40.787544 Set Vref, RX VrefLevel [Byte0]: 47
2659 13:38:40.790047 [Byte1]: 47
2660 13:38:40.794957
2661 13:38:40.795250 Set Vref, RX VrefLevel [Byte0]: 48
2662 13:38:40.797919 [Byte1]: 48
2663 13:38:40.802963
2664 13:38:40.803387 Set Vref, RX VrefLevel [Byte0]: 49
2665 13:38:40.805897 [Byte1]: 49
2666 13:38:40.810830
2667 13:38:40.811245 Set Vref, RX VrefLevel [Byte0]: 50
2668 13:38:40.814227 [Byte1]: 50
2669 13:38:40.819010
2670 13:38:40.819430 Set Vref, RX VrefLevel [Byte0]: 51
2671 13:38:40.822242 [Byte1]: 51
2672 13:38:40.826612
2673 13:38:40.827022 Set Vref, RX VrefLevel [Byte0]: 52
2674 13:38:40.829917 [Byte1]: 52
2675 13:38:40.834335
2676 13:38:40.834629 Set Vref, RX VrefLevel [Byte0]: 53
2677 13:38:40.837923 [Byte1]: 53
2678 13:38:40.842522
2679 13:38:40.842830 Set Vref, RX VrefLevel [Byte0]: 54
2680 13:38:40.845753 [Byte1]: 54
2681 13:38:40.850246
2682 13:38:40.850646 Set Vref, RX VrefLevel [Byte0]: 55
2683 13:38:40.853780 [Byte1]: 55
2684 13:38:40.858578
2685 13:38:40.858884 Set Vref, RX VrefLevel [Byte0]: 56
2686 13:38:40.861411 [Byte1]: 56
2687 13:38:40.866513
2688 13:38:40.866865 Set Vref, RX VrefLevel [Byte0]: 57
2689 13:38:40.869585 [Byte1]: 57
2690 13:38:40.874440
2691 13:38:40.874780 Set Vref, RX VrefLevel [Byte0]: 58
2692 13:38:40.877584 [Byte1]: 58
2693 13:38:40.881847
2694 13:38:40.882149 Set Vref, RX VrefLevel [Byte0]: 59
2695 13:38:40.885609 [Byte1]: 59
2696 13:38:40.889962
2697 13:38:40.890508 Set Vref, RX VrefLevel [Byte0]: 60
2698 13:38:40.893606 [Byte1]: 60
2699 13:38:40.897842
2700 13:38:40.898253 Set Vref, RX VrefLevel [Byte0]: 61
2701 13:38:40.901466 [Byte1]: 61
2702 13:38:40.905837
2703 13:38:40.906302 Set Vref, RX VrefLevel [Byte0]: 62
2704 13:38:40.909393 [Byte1]: 62
2705 13:38:40.913866
2706 13:38:40.914281 Set Vref, RX VrefLevel [Byte0]: 63
2707 13:38:40.917437 [Byte1]: 63
2708 13:38:40.922151
2709 13:38:40.922630 Set Vref, RX VrefLevel [Byte0]: 64
2710 13:38:40.925063 [Byte1]: 64
2711 13:38:40.929831
2712 13:38:40.930247 Final RX Vref Byte 0 = 50 to rank0
2713 13:38:40.933387 Final RX Vref Byte 1 = 55 to rank0
2714 13:38:40.936277 Final RX Vref Byte 0 = 50 to rank1
2715 13:38:40.940115 Final RX Vref Byte 1 = 55 to rank1==
2716 13:38:40.942991 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 13:38:40.949803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2718 13:38:40.950227 ==
2719 13:38:40.950559 DQS Delay:
2720 13:38:40.950865 DQS0 = 0, DQS1 = 0
2721 13:38:40.952781 DQM Delay:
2722 13:38:40.953191 DQM0 = 114, DQM1 = 107
2723 13:38:40.956175 DQ Delay:
2724 13:38:40.959902 DQ0 =112, DQ1 =114, DQ2 =114, DQ3 =110
2725 13:38:40.963060 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2726 13:38:40.966436 DQ8 =98, DQ9 =90, DQ10 =108, DQ11 =100
2727 13:38:40.969450 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =118
2728 13:38:40.970019
2729 13:38:40.970519
2730 13:38:40.976536 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2731 13:38:40.979690 CH0 RK0: MR19=404, MR18=505
2732 13:38:40.986502 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2733 13:38:40.987131
2734 13:38:40.989550 ----->DramcWriteLeveling(PI) begin...
2735 13:38:40.989974 ==
2736 13:38:40.993191 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 13:38:40.996383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 13:38:40.996772 ==
2739 13:38:40.999453 Write leveling (Byte 0): 28 => 28
2740 13:38:41.003208 Write leveling (Byte 1): 24 => 24
2741 13:38:41.006259 DramcWriteLeveling(PI) end<-----
2742 13:38:41.006673
2743 13:38:41.006997 ==
2744 13:38:41.009350 Dram Type= 6, Freq= 0, CH_0, rank 1
2745 13:38:41.016216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2746 13:38:41.016700 ==
2747 13:38:41.017033 [Gating] SW mode calibration
2748 13:38:41.026258 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2749 13:38:41.029280 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2750 13:38:41.033111 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 13:38:41.039605 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 13:38:41.042549 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 13:38:41.049244 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 13:38:41.052250 0 11 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2755 13:38:41.055686 0 11 20 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
2756 13:38:41.058700 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 13:38:41.065561 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 13:38:41.068834 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 13:38:41.072364 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 13:38:41.078627 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 13:38:41.082014 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 13:38:41.085464 0 12 16 | B1->B0 | 2525 3534 | 0 1 | (0 0) (0 0)
2763 13:38:41.092091 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2764 13:38:41.095385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 13:38:41.098891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 13:38:41.105529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 13:38:41.108545 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 13:38:41.111742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 13:38:41.118558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2770 13:38:41.122243 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2771 13:38:41.125341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2772 13:38:41.132059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 13:38:41.135177 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 13:38:41.139073 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 13:38:41.145263 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 13:38:41.148384 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 13:38:41.152008 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 13:38:41.158493 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 13:38:41.162074 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 13:38:41.165121 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 13:38:41.171878 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 13:38:41.174981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 13:38:41.178702 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 13:38:41.181767 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 13:38:41.188600 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 13:38:41.191701 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2787 13:38:41.195063 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2788 13:38:41.201989 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2789 13:38:41.205423 Total UI for P1: 0, mck2ui 16
2790 13:38:41.208673 best dqsien dly found for B0: ( 0, 15, 18)
2791 13:38:41.208861 Total UI for P1: 0, mck2ui 16
2792 13:38:41.215337 best dqsien dly found for B1: ( 0, 15, 18)
2793 13:38:41.218849 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2794 13:38:41.221924 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2795 13:38:41.222135
2796 13:38:41.225637 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2797 13:38:41.228808 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2798 13:38:41.231751 [Gating] SW calibration Done
2799 13:38:41.232031 ==
2800 13:38:41.235410 Dram Type= 6, Freq= 0, CH_0, rank 1
2801 13:38:41.239126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2802 13:38:41.239456 ==
2803 13:38:41.242095 RX Vref Scan: 0
2804 13:38:41.242440
2805 13:38:41.242768 RX Vref 0 -> 0, step: 1
2806 13:38:41.243126
2807 13:38:41.245851 RX Delay -40 -> 252, step: 8
2808 13:38:41.248546 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2809 13:38:41.255745 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2810 13:38:41.258702 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2811 13:38:41.262239 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2812 13:38:41.265942 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2813 13:38:41.268939 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2814 13:38:41.275660 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2815 13:38:41.278729 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2816 13:38:41.281939 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2817 13:38:41.285664 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2818 13:38:41.288843 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2819 13:38:41.295379 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2820 13:38:41.298599 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2821 13:38:41.302064 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2822 13:38:41.305183 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2823 13:38:41.308782 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2824 13:38:41.312060 ==
2825 13:38:41.312489 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 13:38:41.318978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2827 13:38:41.319397 ==
2828 13:38:41.319728 DQS Delay:
2829 13:38:41.322426 DQS0 = 0, DQS1 = 0
2830 13:38:41.323003 DQM Delay:
2831 13:38:41.325191 DQM0 = 116, DQM1 = 105
2832 13:38:41.325803 DQ Delay:
2833 13:38:41.328471 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2834 13:38:41.332231 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2835 13:38:41.335196 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2836 13:38:41.338970 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
2837 13:38:41.339548
2838 13:38:41.339894
2839 13:38:41.340301 ==
2840 13:38:41.341758 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 13:38:41.348462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2842 13:38:41.348889 ==
2843 13:38:41.349249
2844 13:38:41.349610
2845 13:38:41.349959 TX Vref Scan disable
2846 13:38:41.351960 == TX Byte 0 ==
2847 13:38:41.355416 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2848 13:38:41.358826 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2849 13:38:41.362319 == TX Byte 1 ==
2850 13:38:41.365285 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2851 13:38:41.368628 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2852 13:38:41.372080 ==
2853 13:38:41.375237 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 13:38:41.378484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2855 13:38:41.379027 ==
2856 13:38:41.389731 TX Vref=22, minBit 8, minWin=25, winSum=419
2857 13:38:41.393371 TX Vref=24, minBit 8, minWin=25, winSum=426
2858 13:38:41.396553 TX Vref=26, minBit 13, minWin=25, winSum=429
2859 13:38:41.399623 TX Vref=28, minBit 8, minWin=25, winSum=428
2860 13:38:41.403216 TX Vref=30, minBit 8, minWin=26, winSum=435
2861 13:38:41.409938 TX Vref=32, minBit 8, minWin=25, winSum=436
2862 13:38:41.413509 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2863 13:38:41.413835
2864 13:38:41.416399 Final TX Range 1 Vref 30
2865 13:38:41.416721
2866 13:38:41.416962 ==
2867 13:38:41.419562 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 13:38:41.423177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 13:38:41.423492 ==
2870 13:38:41.423747
2871 13:38:41.426660
2872 13:38:41.426960 TX Vref Scan disable
2873 13:38:41.429715 == TX Byte 0 ==
2874 13:38:41.433233 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2875 13:38:41.436786 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2876 13:38:41.439577 == TX Byte 1 ==
2877 13:38:41.443285 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2878 13:38:41.446223 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2879 13:38:41.449803
2880 13:38:41.450104 [DATLAT]
2881 13:38:41.450340 Freq=1200, CH0 RK1
2882 13:38:41.450565
2883 13:38:41.453040 DATLAT Default: 0xc
2884 13:38:41.453450 0, 0xFFFF, sum = 0
2885 13:38:41.456664 1, 0xFFFF, sum = 0
2886 13:38:41.457041 2, 0xFFFF, sum = 0
2887 13:38:41.459599 3, 0xFFFF, sum = 0
2888 13:38:41.459903 4, 0xFFFF, sum = 0
2889 13:38:41.463042 5, 0xFFFF, sum = 0
2890 13:38:41.463480 6, 0xFFFF, sum = 0
2891 13:38:41.466481 7, 0xFFFF, sum = 0
2892 13:38:41.470141 8, 0xFFFF, sum = 0
2893 13:38:41.470460 9, 0xFFFF, sum = 0
2894 13:38:41.472988 10, 0xFFFF, sum = 0
2895 13:38:41.473410 11, 0x0, sum = 1
2896 13:38:41.476339 12, 0x0, sum = 2
2897 13:38:41.476736 13, 0x0, sum = 3
2898 13:38:41.477082 14, 0x0, sum = 4
2899 13:38:41.479896 best_step = 12
2900 13:38:41.480292
2901 13:38:41.480635 ==
2902 13:38:41.482926 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 13:38:41.486560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2904 13:38:41.486878 ==
2905 13:38:41.489689 RX Vref Scan: 0
2906 13:38:41.490105
2907 13:38:41.490499 RX Vref 0 -> 0, step: 1
2908 13:38:41.493268
2909 13:38:41.493599 RX Delay -21 -> 252, step: 4
2910 13:38:41.500049 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2911 13:38:41.503696 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2912 13:38:41.506866 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2913 13:38:41.509749 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2914 13:38:41.513536 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2915 13:38:41.520228 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2916 13:38:41.523381 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2917 13:38:41.527060 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2918 13:38:41.529882 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2919 13:38:41.533517 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2920 13:38:41.540045 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
2921 13:38:41.543635 iDelay=199, Bit 11, Center 98 (35 ~ 162) 128
2922 13:38:41.547031 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2923 13:38:41.550086 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2924 13:38:41.553594 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2925 13:38:41.559988 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
2926 13:38:41.560386 ==
2927 13:38:41.563611 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 13:38:41.567142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2929 13:38:41.567563 ==
2930 13:38:41.567840 DQS Delay:
2931 13:38:41.570600 DQS0 = 0, DQS1 = 0
2932 13:38:41.570900 DQM Delay:
2933 13:38:41.573350 DQM0 = 114, DQM1 = 106
2934 13:38:41.573697 DQ Delay:
2935 13:38:41.576804 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2936 13:38:41.579898 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2937 13:38:41.583250 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =98
2938 13:38:41.587248 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2939 13:38:41.587575
2940 13:38:41.587842
2941 13:38:41.596933 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2942 13:38:41.600081 CH0 RK1: MR19=404, MR18=1010
2943 13:38:41.603772 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2944 13:38:41.607004 [RxdqsGatingPostProcess] freq 1200
2945 13:38:41.613446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2946 13:38:41.617341 Pre-setting of DQS Precalculation
2947 13:38:41.620400 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2948 13:38:41.620772 ==
2949 13:38:41.624060 Dram Type= 6, Freq= 0, CH_1, rank 0
2950 13:38:41.630758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2951 13:38:41.631070 ==
2952 13:38:41.633770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2953 13:38:41.640505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2954 13:38:41.648837 [CA 0] Center 37 (7~68) winsize 62
2955 13:38:41.652359 [CA 1] Center 37 (6~68) winsize 63
2956 13:38:41.655289 [CA 2] Center 34 (4~65) winsize 62
2957 13:38:41.658924 [CA 3] Center 33 (3~64) winsize 62
2958 13:38:41.661826 [CA 4] Center 32 (1~63) winsize 63
2959 13:38:41.665632 [CA 5] Center 32 (2~63) winsize 62
2960 13:38:41.665944
2961 13:38:41.668730 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2962 13:38:41.669041
2963 13:38:41.672398 [CATrainingPosCal] consider 1 rank data
2964 13:38:41.675241 u2DelayCellTimex100 = 270/100 ps
2965 13:38:41.678909 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2966 13:38:41.682362 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2967 13:38:41.689064 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2968 13:38:41.691954 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2969 13:38:41.695376 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2970 13:38:41.698686 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2971 13:38:41.698994
2972 13:38:41.701993 CA PerBit enable=1, Macro0, CA PI delay=32
2973 13:38:41.702294
2974 13:38:41.705513 [CBTSetCACLKResult] CA Dly = 32
2975 13:38:41.705815 CS Dly: 5 (0~36)
2976 13:38:41.708549 ==
2977 13:38:41.708862 Dram Type= 6, Freq= 0, CH_1, rank 1
2978 13:38:41.715575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2979 13:38:41.715896 ==
2980 13:38:41.718408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2981 13:38:41.725378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2982 13:38:41.733870 [CA 0] Center 37 (7~68) winsize 62
2983 13:38:41.737089 [CA 1] Center 37 (6~68) winsize 63
2984 13:38:41.740703 [CA 2] Center 33 (3~64) winsize 62
2985 13:38:41.744333 [CA 3] Center 33 (3~64) winsize 62
2986 13:38:41.747256 [CA 4] Center 32 (2~63) winsize 62
2987 13:38:41.750988 [CA 5] Center 32 (1~63) winsize 63
2988 13:38:41.751301
2989 13:38:41.754060 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2990 13:38:41.754371
2991 13:38:41.757602 [CATrainingPosCal] consider 2 rank data
2992 13:38:41.760620 u2DelayCellTimex100 = 270/100 ps
2993 13:38:41.763950 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2994 13:38:41.767531 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2995 13:38:41.773759 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2996 13:38:41.777263 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2997 13:38:41.780422 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2998 13:38:41.784019 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2999 13:38:41.784335
3000 13:38:41.787103 CA PerBit enable=1, Macro0, CA PI delay=32
3001 13:38:41.787427
3002 13:38:41.790684 [CBTSetCACLKResult] CA Dly = 32
3003 13:38:41.791052 CS Dly: 6 (0~38)
3004 13:38:41.791370
3005 13:38:41.794099 ----->DramcWriteLeveling(PI) begin...
3006 13:38:41.797193 ==
3007 13:38:41.800340 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 13:38:41.803733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 13:38:41.804049 ==
3010 13:38:41.807685 Write leveling (Byte 0): 20 => 20
3011 13:38:41.810811 Write leveling (Byte 1): 21 => 21
3012 13:38:41.813891 DramcWriteLeveling(PI) end<-----
3013 13:38:41.814217
3014 13:38:41.814452 ==
3015 13:38:41.816972 Dram Type= 6, Freq= 0, CH_1, rank 0
3016 13:38:41.820570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3017 13:38:41.820882 ==
3018 13:38:41.823706 [Gating] SW mode calibration
3019 13:38:41.830546 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3020 13:38:41.833527 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3021 13:38:41.840380 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3022 13:38:41.843858 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 13:38:41.846937 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 13:38:41.854011 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 13:38:41.857180 0 11 16 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
3026 13:38:41.860146 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3027 13:38:41.867149 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 13:38:41.870478 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 13:38:41.873699 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 13:38:41.880542 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 13:38:41.883385 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 13:38:41.887202 0 12 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
3033 13:38:41.893759 0 12 16 | B1->B0 | 3232 3f3f | 0 1 | (0 0) (0 0)
3034 13:38:41.897238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 13:38:41.900170 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 13:38:41.906938 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 13:38:41.910562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 13:38:41.913926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 13:38:41.920307 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 13:38:41.923929 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3041 13:38:41.926947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3042 13:38:41.933712 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3043 13:38:41.936782 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 13:38:41.940434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 13:38:41.946657 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 13:38:41.950437 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 13:38:41.953505 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 13:38:41.957149 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 13:38:41.963281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 13:38:41.966960 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 13:38:41.970625 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 13:38:41.976887 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 13:38:41.980247 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 13:38:41.983627 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 13:38:41.990284 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 13:38:41.993905 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3057 13:38:41.996975 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3058 13:38:42.003493 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3059 13:38:42.003800 Total UI for P1: 0, mck2ui 16
3060 13:38:42.010155 best dqsien dly found for B0: ( 0, 15, 14)
3061 13:38:42.013869 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3062 13:38:42.016969 Total UI for P1: 0, mck2ui 16
3063 13:38:42.019983 best dqsien dly found for B1: ( 0, 15, 18)
3064 13:38:42.023413 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3065 13:38:42.027005 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3066 13:38:42.027310
3067 13:38:42.029995 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3068 13:38:42.033595 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3069 13:38:42.036817 [Gating] SW calibration Done
3070 13:38:42.037116 ==
3071 13:38:42.040474 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 13:38:42.043488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3073 13:38:42.046544 ==
3074 13:38:42.046844 RX Vref Scan: 0
3075 13:38:42.047078
3076 13:38:42.050246 RX Vref 0 -> 0, step: 1
3077 13:38:42.050546
3078 13:38:42.053075 RX Delay -40 -> 252, step: 8
3079 13:38:42.056826 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3080 13:38:42.059908 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3081 13:38:42.063481 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3082 13:38:42.066560 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3083 13:38:42.073331 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3084 13:38:42.077045 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3085 13:38:42.080267 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3086 13:38:42.083322 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3087 13:38:42.086832 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3088 13:38:42.090297 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3089 13:38:42.096910 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3090 13:38:42.100225 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3091 13:38:42.103481 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3092 13:38:42.106381 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3093 13:38:42.112990 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3094 13:38:42.116527 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3095 13:38:42.116825 ==
3096 13:38:42.120093 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 13:38:42.123176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3098 13:38:42.123499 ==
3099 13:38:42.123796 DQS Delay:
3100 13:38:42.126772 DQS0 = 0, DQS1 = 0
3101 13:38:42.127093 DQM Delay:
3102 13:38:42.129757 DQM0 = 116, DQM1 = 106
3103 13:38:42.130072 DQ Delay:
3104 13:38:42.133035 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3105 13:38:42.136335 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3106 13:38:42.139932 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =99
3107 13:38:42.143617 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3108 13:38:42.143951
3109 13:38:42.144207
3110 13:38:42.146691 ==
3111 13:38:42.150435 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 13:38:42.153490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3113 13:38:42.153786 ==
3114 13:38:42.154019
3115 13:38:42.154232
3116 13:38:42.156436 TX Vref Scan disable
3117 13:38:42.156726 == TX Byte 0 ==
3118 13:38:42.159792 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3119 13:38:42.166603 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3120 13:38:42.166992 == TX Byte 1 ==
3121 13:38:42.169929 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3122 13:38:42.176684 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3123 13:38:42.177078 ==
3124 13:38:42.179678 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 13:38:42.183434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3126 13:38:42.183792 ==
3127 13:38:42.194894 TX Vref=22, minBit 3, minWin=24, winSum=411
3128 13:38:42.198637 TX Vref=24, minBit 7, minWin=25, winSum=419
3129 13:38:42.201949 TX Vref=26, minBit 0, minWin=26, winSum=423
3130 13:38:42.205382 TX Vref=28, minBit 0, minWin=26, winSum=427
3131 13:38:42.208628 TX Vref=30, minBit 3, minWin=26, winSum=426
3132 13:38:42.212045 TX Vref=32, minBit 3, minWin=26, winSum=431
3133 13:38:42.218287 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 32
3134 13:38:42.218586
3135 13:38:42.221920 Final TX Range 1 Vref 32
3136 13:38:42.222240
3137 13:38:42.222473 ==
3138 13:38:42.225154 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 13:38:42.228082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3140 13:38:42.228378 ==
3141 13:38:42.228612
3142 13:38:42.231817
3143 13:38:42.232172 TX Vref Scan disable
3144 13:38:42.234752 == TX Byte 0 ==
3145 13:38:42.238255 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3146 13:38:42.241519 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3147 13:38:42.245016 == TX Byte 1 ==
3148 13:38:42.247908 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3149 13:38:42.251585 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3150 13:38:42.254584
3151 13:38:42.254876 [DATLAT]
3152 13:38:42.255167 Freq=1200, CH1 RK0
3153 13:38:42.255402
3154 13:38:42.258312 DATLAT Default: 0xd
3155 13:38:42.258614 0, 0xFFFF, sum = 0
3156 13:38:42.261434 1, 0xFFFF, sum = 0
3157 13:38:42.261734 2, 0xFFFF, sum = 0
3158 13:38:42.264585 3, 0xFFFF, sum = 0
3159 13:38:42.264991 4, 0xFFFF, sum = 0
3160 13:38:42.267999 5, 0xFFFF, sum = 0
3161 13:38:42.271426 6, 0xFFFF, sum = 0
3162 13:38:42.271828 7, 0xFFFF, sum = 0
3163 13:38:42.274911 8, 0xFFFF, sum = 0
3164 13:38:42.275381 9, 0xFFFF, sum = 0
3165 13:38:42.277978 10, 0xFFFF, sum = 0
3166 13:38:42.278292 11, 0x0, sum = 1
3167 13:38:42.281026 12, 0x0, sum = 2
3168 13:38:42.281370 13, 0x0, sum = 3
3169 13:38:42.284797 14, 0x0, sum = 4
3170 13:38:42.285356 best_step = 12
3171 13:38:42.285795
3172 13:38:42.286210 ==
3173 13:38:42.287787 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 13:38:42.291389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3175 13:38:42.291774 ==
3176 13:38:42.294497 RX Vref Scan: 1
3177 13:38:42.294792
3178 13:38:42.298037 Set Vref Range= 32 -> 127
3179 13:38:42.298341
3180 13:38:42.298611 RX Vref 32 -> 127, step: 1
3181 13:38:42.298887
3182 13:38:42.300998 RX Delay -29 -> 252, step: 4
3183 13:38:42.301440
3184 13:38:42.304650 Set Vref, RX VrefLevel [Byte0]: 32
3185 13:38:42.307601 [Byte1]: 32
3186 13:38:42.311677
3187 13:38:42.312145 Set Vref, RX VrefLevel [Byte0]: 33
3188 13:38:42.314502 [Byte1]: 33
3189 13:38:42.319500
3190 13:38:42.319768 Set Vref, RX VrefLevel [Byte0]: 34
3191 13:38:42.322933 [Byte1]: 34
3192 13:38:42.327202
3193 13:38:42.327407 Set Vref, RX VrefLevel [Byte0]: 35
3194 13:38:42.330824 [Byte1]: 35
3195 13:38:42.335042
3196 13:38:42.335274 Set Vref, RX VrefLevel [Byte0]: 36
3197 13:38:42.338555 [Byte1]: 36
3198 13:38:42.343025
3199 13:38:42.343205 Set Vref, RX VrefLevel [Byte0]: 37
3200 13:38:42.346538 [Byte1]: 37
3201 13:38:42.351291
3202 13:38:42.351471 Set Vref, RX VrefLevel [Byte0]: 38
3203 13:38:42.354216 [Byte1]: 38
3204 13:38:42.359101
3205 13:38:42.359279 Set Vref, RX VrefLevel [Byte0]: 39
3206 13:38:42.362688 [Byte1]: 39
3207 13:38:42.366927
3208 13:38:42.370461 Set Vref, RX VrefLevel [Byte0]: 40
3209 13:38:42.373645 [Byte1]: 40
3210 13:38:42.373824
3211 13:38:42.376668 Set Vref, RX VrefLevel [Byte0]: 41
3212 13:38:42.380017 [Byte1]: 41
3213 13:38:42.380197
3214 13:38:42.383499 Set Vref, RX VrefLevel [Byte0]: 42
3215 13:38:42.386593 [Byte1]: 42
3216 13:38:42.390929
3217 13:38:42.391110 Set Vref, RX VrefLevel [Byte0]: 43
3218 13:38:42.394075 [Byte1]: 43
3219 13:38:42.398958
3220 13:38:42.399265 Set Vref, RX VrefLevel [Byte0]: 44
3221 13:38:42.402581 [Byte1]: 44
3222 13:38:42.406985
3223 13:38:42.407382 Set Vref, RX VrefLevel [Byte0]: 45
3224 13:38:42.410583 [Byte1]: 45
3225 13:38:42.414645
3226 13:38:42.414972 Set Vref, RX VrefLevel [Byte0]: 46
3227 13:38:42.418234 [Byte1]: 46
3228 13:38:42.423334
3229 13:38:42.423654 Set Vref, RX VrefLevel [Byte0]: 47
3230 13:38:42.426558 [Byte1]: 47
3231 13:38:42.430695
3232 13:38:42.431031 Set Vref, RX VrefLevel [Byte0]: 48
3233 13:38:42.434193 [Byte1]: 48
3234 13:38:42.438855
3235 13:38:42.439177 Set Vref, RX VrefLevel [Byte0]: 49
3236 13:38:42.442026 [Byte1]: 49
3237 13:38:42.446978
3238 13:38:42.447301 Set Vref, RX VrefLevel [Byte0]: 50
3239 13:38:42.449944 [Byte1]: 50
3240 13:38:42.454583
3241 13:38:42.455049 Set Vref, RX VrefLevel [Byte0]: 51
3242 13:38:42.458156 [Byte1]: 51
3243 13:38:42.462568
3244 13:38:42.462889 Set Vref, RX VrefLevel [Byte0]: 52
3245 13:38:42.465960 [Byte1]: 52
3246 13:38:42.470862
3247 13:38:42.471254 Set Vref, RX VrefLevel [Byte0]: 53
3248 13:38:42.473978 [Byte1]: 53
3249 13:38:42.478791
3250 13:38:42.479133 Set Vref, RX VrefLevel [Byte0]: 54
3251 13:38:42.481740 [Byte1]: 54
3252 13:38:42.486408
3253 13:38:42.486809 Set Vref, RX VrefLevel [Byte0]: 55
3254 13:38:42.490150 [Byte1]: 55
3255 13:38:42.494461
3256 13:38:42.494803 Set Vref, RX VrefLevel [Byte0]: 56
3257 13:38:42.497587 [Byte1]: 56
3258 13:38:42.502461
3259 13:38:42.502791 Set Vref, RX VrefLevel [Byte0]: 57
3260 13:38:42.506137 [Byte1]: 57
3261 13:38:42.510439
3262 13:38:42.510842 Set Vref, RX VrefLevel [Byte0]: 58
3263 13:38:42.513402 [Byte1]: 58
3264 13:38:42.518465
3265 13:38:42.518885 Set Vref, RX VrefLevel [Byte0]: 59
3266 13:38:42.521497 [Byte1]: 59
3267 13:38:42.526264
3268 13:38:42.526588 Set Vref, RX VrefLevel [Byte0]: 60
3269 13:38:42.529978 [Byte1]: 60
3270 13:38:42.534207
3271 13:38:42.534520 Set Vref, RX VrefLevel [Byte0]: 61
3272 13:38:42.537807 [Byte1]: 61
3273 13:38:42.542396
3274 13:38:42.542719 Set Vref, RX VrefLevel [Byte0]: 62
3275 13:38:42.545767 [Byte1]: 62
3276 13:38:42.550277
3277 13:38:42.550636 Set Vref, RX VrefLevel [Byte0]: 63
3278 13:38:42.553199 [Byte1]: 63
3279 13:38:42.557997
3280 13:38:42.558310 Set Vref, RX VrefLevel [Byte0]: 64
3281 13:38:42.561590 [Byte1]: 64
3282 13:38:42.565892
3283 13:38:42.566217 Set Vref, RX VrefLevel [Byte0]: 65
3284 13:38:42.569056 [Byte1]: 65
3285 13:38:42.573921
3286 13:38:42.574253 Final RX Vref Byte 0 = 55 to rank0
3287 13:38:42.577279 Final RX Vref Byte 1 = 48 to rank0
3288 13:38:42.580543 Final RX Vref Byte 0 = 55 to rank1
3289 13:38:42.584346 Final RX Vref Byte 1 = 48 to rank1==
3290 13:38:42.587116 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 13:38:42.594100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3292 13:38:42.594430 ==
3293 13:38:42.594686 DQS Delay:
3294 13:38:42.594928 DQS0 = 0, DQS1 = 0
3295 13:38:42.597190 DQM Delay:
3296 13:38:42.597550 DQM0 = 115, DQM1 = 105
3297 13:38:42.600909 DQ Delay:
3298 13:38:42.604000 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3299 13:38:42.607158 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3300 13:38:42.610704 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3301 13:38:42.613772 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =116
3302 13:38:42.614335
3303 13:38:42.614746
3304 13:38:42.620661 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3305 13:38:42.624158 CH1 RK0: MR19=404, MR18=1414
3306 13:38:42.630720 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3307 13:38:42.631172
3308 13:38:42.634333 ----->DramcWriteLeveling(PI) begin...
3309 13:38:42.634807 ==
3310 13:38:42.637586 Dram Type= 6, Freq= 0, CH_1, rank 1
3311 13:38:42.641098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3312 13:38:42.641563 ==
3313 13:38:42.644041 Write leveling (Byte 0): 22 => 22
3314 13:38:42.647671 Write leveling (Byte 1): 21 => 21
3315 13:38:42.650907 DramcWriteLeveling(PI) end<-----
3316 13:38:42.651341
3317 13:38:42.651848 ==
3318 13:38:42.654483 Dram Type= 6, Freq= 0, CH_1, rank 1
3319 13:38:42.660577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3320 13:38:42.661006 ==
3321 13:38:42.661379 [Gating] SW mode calibration
3322 13:38:42.670800 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3323 13:38:42.673898 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3324 13:38:42.677606 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3325 13:38:42.684144 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3326 13:38:42.687670 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3327 13:38:42.691014 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
3328 13:38:42.697162 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3329 13:38:42.700561 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3330 13:38:42.703704 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3331 13:38:42.710818 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 13:38:42.714368 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 13:38:42.717339 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3334 13:38:42.723960 0 12 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3335 13:38:42.727681 0 12 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
3336 13:38:42.730741 0 12 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3337 13:38:42.737243 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 13:38:42.740847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 13:38:42.744018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 13:38:42.750555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 13:38:42.754148 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 13:38:42.757511 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 13:38:42.760980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3344 13:38:42.767522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3345 13:38:42.770852 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3346 13:38:42.773999 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 13:38:42.780644 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 13:38:42.783850 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 13:38:42.787625 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 13:38:42.793663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 13:38:42.797322 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 13:38:42.800785 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 13:38:42.807435 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 13:38:42.810389 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 13:38:42.813600 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 13:38:42.820279 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 13:38:42.823395 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 13:38:42.826991 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3359 13:38:42.833590 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3360 13:38:42.837223 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3361 13:38:42.840036 Total UI for P1: 0, mck2ui 16
3362 13:38:42.843833 best dqsien dly found for B0: ( 0, 15, 10)
3363 13:38:42.847024 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3364 13:38:42.850101 Total UI for P1: 0, mck2ui 16
3365 13:38:42.853712 best dqsien dly found for B1: ( 0, 15, 16)
3366 13:38:42.857370 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3367 13:38:42.860252 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3368 13:38:42.860663
3369 13:38:42.866755 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3370 13:38:42.870170 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3371 13:38:42.873414 [Gating] SW calibration Done
3372 13:38:42.873717 ==
3373 13:38:42.876545 Dram Type= 6, Freq= 0, CH_1, rank 1
3374 13:38:42.880345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3375 13:38:42.880645 ==
3376 13:38:42.880882 RX Vref Scan: 0
3377 13:38:42.881189
3378 13:38:42.883440 RX Vref 0 -> 0, step: 1
3379 13:38:42.883735
3380 13:38:42.887021 RX Delay -40 -> 252, step: 8
3381 13:38:42.890162 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3382 13:38:42.893219 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3383 13:38:42.896948 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3384 13:38:42.903696 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3385 13:38:42.906614 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3386 13:38:42.910342 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3387 13:38:42.913353 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3388 13:38:42.916884 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3389 13:38:42.923528 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3390 13:38:42.926877 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3391 13:38:42.930188 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3392 13:38:42.933443 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3393 13:38:42.936739 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3394 13:38:42.943657 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3395 13:38:42.947081 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3396 13:38:42.950077 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3397 13:38:42.950389 ==
3398 13:38:42.953663 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 13:38:42.956596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3400 13:38:42.956946 ==
3401 13:38:42.960152 DQS Delay:
3402 13:38:42.960452 DQS0 = 0, DQS1 = 0
3403 13:38:42.963293 DQM Delay:
3404 13:38:42.963599 DQM0 = 115, DQM1 = 104
3405 13:38:42.967114 DQ Delay:
3406 13:38:42.970101 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3407 13:38:42.973152 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3408 13:38:42.976852 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
3409 13:38:42.980366 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3410 13:38:42.980750
3411 13:38:42.981055
3412 13:38:42.981375 ==
3413 13:38:42.983302 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 13:38:42.986896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3415 13:38:42.987280 ==
3416 13:38:42.987586
3417 13:38:42.987867
3418 13:38:42.989974 TX Vref Scan disable
3419 13:38:42.993767 == TX Byte 0 ==
3420 13:38:42.996651 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3421 13:38:43.000334 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3422 13:38:43.003465 == TX Byte 1 ==
3423 13:38:43.006692 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3424 13:38:43.010278 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3425 13:38:43.010664 ==
3426 13:38:43.013266 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 13:38:43.017051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3428 13:38:43.017608 ==
3429 13:38:43.030014 TX Vref=22, minBit 3, minWin=25, winSum=419
3430 13:38:43.033075 TX Vref=24, minBit 0, minWin=26, winSum=427
3431 13:38:43.036504 TX Vref=26, minBit 3, minWin=26, winSum=431
3432 13:38:43.039613 TX Vref=28, minBit 8, minWin=26, winSum=433
3433 13:38:43.043102 TX Vref=30, minBit 0, minWin=26, winSum=434
3434 13:38:43.046107 TX Vref=32, minBit 0, minWin=26, winSum=430
3435 13:38:43.053139 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 30
3436 13:38:43.053632
3437 13:38:43.056362 Final TX Range 1 Vref 30
3438 13:38:43.056924
3439 13:38:43.057448 ==
3440 13:38:43.059647 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 13:38:43.063175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3442 13:38:43.063631 ==
3443 13:38:43.064025
3444 13:38:43.066110
3445 13:38:43.066498 TX Vref Scan disable
3446 13:38:43.069783 == TX Byte 0 ==
3447 13:38:43.072809 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3448 13:38:43.076609 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3449 13:38:43.079572 == TX Byte 1 ==
3450 13:38:43.083306 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3451 13:38:43.086371 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3452 13:38:43.086764
3453 13:38:43.089746 [DATLAT]
3454 13:38:43.090288 Freq=1200, CH1 RK1
3455 13:38:43.090632
3456 13:38:43.093145 DATLAT Default: 0xc
3457 13:38:43.093569 0, 0xFFFF, sum = 0
3458 13:38:43.096427 1, 0xFFFF, sum = 0
3459 13:38:43.096826 2, 0xFFFF, sum = 0
3460 13:38:43.100059 3, 0xFFFF, sum = 0
3461 13:38:43.100459 4, 0xFFFF, sum = 0
3462 13:38:43.103025 5, 0xFFFF, sum = 0
3463 13:38:43.103421 6, 0xFFFF, sum = 0
3464 13:38:43.106745 7, 0xFFFF, sum = 0
3465 13:38:43.107142 8, 0xFFFF, sum = 0
3466 13:38:43.109845 9, 0xFFFF, sum = 0
3467 13:38:43.110244 10, 0xFFFF, sum = 0
3468 13:38:43.113398 11, 0x0, sum = 1
3469 13:38:43.113795 12, 0x0, sum = 2
3470 13:38:43.116431 13, 0x0, sum = 3
3471 13:38:43.116831 14, 0x0, sum = 4
3472 13:38:43.120131 best_step = 12
3473 13:38:43.120532
3474 13:38:43.120905 ==
3475 13:38:43.123242 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 13:38:43.126101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3477 13:38:43.126493 ==
3478 13:38:43.129936 RX Vref Scan: 0
3479 13:38:43.130465
3480 13:38:43.130826 RX Vref 0 -> 0, step: 1
3481 13:38:43.131194
3482 13:38:43.132879 RX Delay -29 -> 252, step: 4
3483 13:38:43.139698 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3484 13:38:43.143056 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3485 13:38:43.146400 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3486 13:38:43.150094 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3487 13:38:43.153152 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3488 13:38:43.160291 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3489 13:38:43.162957 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3490 13:38:43.166655 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3491 13:38:43.169877 iDelay=199, Bit 8, Center 84 (19 ~ 150) 132
3492 13:38:43.173200 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3493 13:38:43.179635 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3494 13:38:43.183138 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3495 13:38:43.186271 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3496 13:38:43.189886 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3497 13:38:43.193052 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3498 13:38:43.199871 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3499 13:38:43.200058 ==
3500 13:38:43.203301 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 13:38:43.206335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3502 13:38:43.206506 ==
3503 13:38:43.206642 DQS Delay:
3504 13:38:43.209915 DQS0 = 0, DQS1 = 0
3505 13:38:43.210085 DQM Delay:
3506 13:38:43.212978 DQM0 = 114, DQM1 = 103
3507 13:38:43.213155 DQ Delay:
3508 13:38:43.216074 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3509 13:38:43.219702 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3510 13:38:43.223370 DQ8 =84, DQ9 =92, DQ10 =106, DQ11 =96
3511 13:38:43.226382 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3512 13:38:43.226809
3513 13:38:43.227235
3514 13:38:43.236951 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3515 13:38:43.239763 CH1 RK1: MR19=404, MR18=C0C
3516 13:38:43.243688 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3517 13:38:43.246438 [RxdqsGatingPostProcess] freq 1200
3518 13:38:43.253337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3519 13:38:43.256440 Pre-setting of DQS Precalculation
3520 13:38:43.260068 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3521 13:38:43.269939 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3522 13:38:43.276316 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3523 13:38:43.276813
3524 13:38:43.277229
3525 13:38:43.279762 [Calibration Summary] 2400 Mbps
3526 13:38:43.280209 CH 0, Rank 0
3527 13:38:43.282996 SW Impedance : PASS
3528 13:38:43.283412 DUTY Scan : NO K
3529 13:38:43.286354 ZQ Calibration : PASS
3530 13:38:43.289784 Jitter Meter : NO K
3531 13:38:43.290450 CBT Training : PASS
3532 13:38:43.293238 Write leveling : PASS
3533 13:38:43.296829 RX DQS gating : PASS
3534 13:38:43.297244 RX DQ/DQS(RDDQC) : PASS
3535 13:38:43.299917 TX DQ/DQS : PASS
3536 13:38:43.300368 RX DATLAT : PASS
3537 13:38:43.302902 RX DQ/DQS(Engine): PASS
3538 13:38:43.306363 TX OE : NO K
3539 13:38:43.306788 All Pass.
3540 13:38:43.307294
3541 13:38:43.307619 CH 0, Rank 1
3542 13:38:43.309674 SW Impedance : PASS
3543 13:38:43.313140 DUTY Scan : NO K
3544 13:38:43.313658 ZQ Calibration : PASS
3545 13:38:43.316885 Jitter Meter : NO K
3546 13:38:43.319880 CBT Training : PASS
3547 13:38:43.320378 Write leveling : PASS
3548 13:38:43.322913 RX DQS gating : PASS
3549 13:38:43.326519 RX DQ/DQS(RDDQC) : PASS
3550 13:38:43.326953 TX DQ/DQS : PASS
3551 13:38:43.330275 RX DATLAT : PASS
3552 13:38:43.333415 RX DQ/DQS(Engine): PASS
3553 13:38:43.333849 TX OE : NO K
3554 13:38:43.336165 All Pass.
3555 13:38:43.336694
3556 13:38:43.337124 CH 1, Rank 0
3557 13:38:43.339793 SW Impedance : PASS
3558 13:38:43.340226 DUTY Scan : NO K
3559 13:38:43.343563 ZQ Calibration : PASS
3560 13:38:43.346371 Jitter Meter : NO K
3561 13:38:43.346810 CBT Training : PASS
3562 13:38:43.350021 Write leveling : PASS
3563 13:38:43.350456 RX DQS gating : PASS
3564 13:38:43.352960 RX DQ/DQS(RDDQC) : PASS
3565 13:38:43.356668 TX DQ/DQS : PASS
3566 13:38:43.357107 RX DATLAT : PASS
3567 13:38:43.359684 RX DQ/DQS(Engine): PASS
3568 13:38:43.363200 TX OE : NO K
3569 13:38:43.363721 All Pass.
3570 13:38:43.364223
3571 13:38:43.364554 CH 1, Rank 1
3572 13:38:43.366326 SW Impedance : PASS
3573 13:38:43.370055 DUTY Scan : NO K
3574 13:38:43.370478 ZQ Calibration : PASS
3575 13:38:43.373126 Jitter Meter : NO K
3576 13:38:43.376623 CBT Training : PASS
3577 13:38:43.377014 Write leveling : PASS
3578 13:38:43.379593 RX DQS gating : PASS
3579 13:38:43.383167 RX DQ/DQS(RDDQC) : PASS
3580 13:38:43.383675 TX DQ/DQS : PASS
3581 13:38:43.386289 RX DATLAT : PASS
3582 13:38:43.386705 RX DQ/DQS(Engine): PASS
3583 13:38:43.389856 TX OE : NO K
3584 13:38:43.390342 All Pass.
3585 13:38:43.390838
3586 13:38:43.393014 DramC Write-DBI off
3587 13:38:43.396750 PER_BANK_REFRESH: Hybrid Mode
3588 13:38:43.397168 TX_TRACKING: ON
3589 13:38:43.406563 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3590 13:38:43.410195 [FAST_K] Save calibration result to emmc
3591 13:38:43.413008 dramc_set_vcore_voltage set vcore to 650000
3592 13:38:43.416599 Read voltage for 600, 5
3593 13:38:43.417018 Vio18 = 0
3594 13:38:43.417393 Vcore = 650000
3595 13:38:43.420042 Vdram = 0
3596 13:38:43.420460 Vddq = 0
3597 13:38:43.420792 Vmddr = 0
3598 13:38:43.426597 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3599 13:38:43.430037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3600 13:38:43.433284 MEM_TYPE=3, freq_sel=19
3601 13:38:43.436485 sv_algorithm_assistance_LP4_1600
3602 13:38:43.440029 ============ PULL DRAM RESETB DOWN ============
3603 13:38:43.446662 ========== PULL DRAM RESETB DOWN end =========
3604 13:38:43.449762 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3605 13:38:43.453263 ===================================
3606 13:38:43.456752 LPDDR4 DRAM CONFIGURATION
3607 13:38:43.460322 ===================================
3608 13:38:43.460745 EX_ROW_EN[0] = 0x0
3609 13:38:43.463315 EX_ROW_EN[1] = 0x0
3610 13:38:43.463733 LP4Y_EN = 0x0
3611 13:38:43.466417 WORK_FSP = 0x0
3612 13:38:43.466868 WL = 0x2
3613 13:38:43.470176 RL = 0x2
3614 13:38:43.470597 BL = 0x2
3615 13:38:43.473135 RPST = 0x0
3616 13:38:43.473581 RD_PRE = 0x0
3617 13:38:43.476786 WR_PRE = 0x1
3618 13:38:43.477207 WR_PST = 0x0
3619 13:38:43.479797 DBI_WR = 0x0
3620 13:38:43.480323 DBI_RD = 0x0
3621 13:38:43.482915 OTF = 0x1
3622 13:38:43.486581 ===================================
3623 13:38:43.489444 ===================================
3624 13:38:43.489864 ANA top config
3625 13:38:43.492889 ===================================
3626 13:38:43.496176 DLL_ASYNC_EN = 0
3627 13:38:43.499762 ALL_SLAVE_EN = 1
3628 13:38:43.502839 NEW_RANK_MODE = 1
3629 13:38:43.503280 DLL_IDLE_MODE = 1
3630 13:38:43.506518 LP45_APHY_COMB_EN = 1
3631 13:38:43.509624 TX_ODT_DIS = 1
3632 13:38:43.513125 NEW_8X_MODE = 1
3633 13:38:43.515908 ===================================
3634 13:38:43.519837 ===================================
3635 13:38:43.522524 data_rate = 1200
3636 13:38:43.525739 CKR = 1
3637 13:38:43.526204 DQ_P2S_RATIO = 8
3638 13:38:43.529440 ===================================
3639 13:38:43.532808 CA_P2S_RATIO = 8
3640 13:38:43.535674 DQ_CA_OPEN = 0
3641 13:38:43.539686 DQ_SEMI_OPEN = 0
3642 13:38:43.542658 CA_SEMI_OPEN = 0
3643 13:38:43.546299 CA_FULL_RATE = 0
3644 13:38:43.546750 DQ_CKDIV4_EN = 1
3645 13:38:43.549270 CA_CKDIV4_EN = 1
3646 13:38:43.552912 CA_PREDIV_EN = 0
3647 13:38:43.555916 PH8_DLY = 0
3648 13:38:43.558858 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3649 13:38:43.562293 DQ_AAMCK_DIV = 4
3650 13:38:43.562724 CA_AAMCK_DIV = 4
3651 13:38:43.565828 CA_ADMCK_DIV = 4
3652 13:38:43.568893 DQ_TRACK_CA_EN = 0
3653 13:38:43.572584 CA_PICK = 600
3654 13:38:43.575878 CA_MCKIO = 600
3655 13:38:43.578937 MCKIO_SEMI = 0
3656 13:38:43.582145 PLL_FREQ = 2288
3657 13:38:43.582714 DQ_UI_PI_RATIO = 32
3658 13:38:43.585633 CA_UI_PI_RATIO = 0
3659 13:38:43.588768 ===================================
3660 13:38:43.591628 ===================================
3661 13:38:43.595129 memory_type:LPDDR4
3662 13:38:43.598603 GP_NUM : 10
3663 13:38:43.599023 SRAM_EN : 1
3664 13:38:43.601931 MD32_EN : 0
3665 13:38:43.605019 ===================================
3666 13:38:43.608668 [ANA_INIT] >>>>>>>>>>>>>>
3667 13:38:43.609085 <<<<<< [CONFIGURE PHASE]: ANA_TX
3668 13:38:43.614999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3669 13:38:43.618589 ===================================
3670 13:38:43.619102 data_rate = 1200,PCW = 0X5800
3671 13:38:43.621748 ===================================
3672 13:38:43.624781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3673 13:38:43.631336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3674 13:38:43.637931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3675 13:38:43.641491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3676 13:38:43.644619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3677 13:38:43.648220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3678 13:38:43.651652 [ANA_INIT] flow start
3679 13:38:43.654629 [ANA_INIT] PLL >>>>>>>>
3680 13:38:43.655156 [ANA_INIT] PLL <<<<<<<<
3681 13:38:43.657826 [ANA_INIT] MIDPI >>>>>>>>
3682 13:38:43.661149 [ANA_INIT] MIDPI <<<<<<<<
3683 13:38:43.661602 [ANA_INIT] DLL >>>>>>>>
3684 13:38:43.664809 [ANA_INIT] flow end
3685 13:38:43.667727 ============ LP4 DIFF to SE enter ============
3686 13:38:43.671190 ============ LP4 DIFF to SE exit ============
3687 13:38:43.674815 [ANA_INIT] <<<<<<<<<<<<<
3688 13:38:43.677855 [Flow] Enable top DCM control >>>>>
3689 13:38:43.680872 [Flow] Enable top DCM control <<<<<
3690 13:38:43.684660 Enable DLL master slave shuffle
3691 13:38:43.690800 ==============================================================
3692 13:38:43.691243 Gating Mode config
3693 13:38:43.697651 ==============================================================
3694 13:38:43.698076 Config description:
3695 13:38:43.707173 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3696 13:38:43.713810 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3697 13:38:43.720642 SELPH_MODE 0: By rank 1: By Phase
3698 13:38:43.727203 ==============================================================
3699 13:38:43.727813 GAT_TRACK_EN = 1
3700 13:38:43.730934 RX_GATING_MODE = 2
3701 13:38:43.733984 RX_GATING_TRACK_MODE = 2
3702 13:38:43.737061 SELPH_MODE = 1
3703 13:38:43.740590 PICG_EARLY_EN = 1
3704 13:38:43.743812 VALID_LAT_VALUE = 1
3705 13:38:43.750550 ==============================================================
3706 13:38:43.753954 Enter into Gating configuration >>>>
3707 13:38:43.757193 Exit from Gating configuration <<<<
3708 13:38:43.760395 Enter into DVFS_PRE_config >>>>>
3709 13:38:43.770589 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3710 13:38:43.773613 Exit from DVFS_PRE_config <<<<<
3711 13:38:43.777172 Enter into PICG configuration >>>>
3712 13:38:43.780285 Exit from PICG configuration <<<<
3713 13:38:43.783601 [RX_INPUT] configuration >>>>>
3714 13:38:43.784022 [RX_INPUT] configuration <<<<<
3715 13:38:43.790440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3716 13:38:43.797210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3717 13:38:43.800277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3718 13:38:43.806783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3719 13:38:43.813973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3720 13:38:43.820104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3721 13:38:43.823735 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3722 13:38:43.826776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3723 13:38:43.833416 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3724 13:38:43.836595 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3725 13:38:43.840268 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3726 13:38:43.847081 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 13:38:43.849832 ===================================
3728 13:38:43.850127 LPDDR4 DRAM CONFIGURATION
3729 13:38:43.852820 ===================================
3730 13:38:43.856661 EX_ROW_EN[0] = 0x0
3731 13:38:43.857215 EX_ROW_EN[1] = 0x0
3732 13:38:43.859957 LP4Y_EN = 0x0
3733 13:38:43.863018 WORK_FSP = 0x0
3734 13:38:43.863423 WL = 0x2
3735 13:38:43.866534 RL = 0x2
3736 13:38:43.866938 BL = 0x2
3737 13:38:43.869927 RPST = 0x0
3738 13:38:43.870449 RD_PRE = 0x0
3739 13:38:43.873141 WR_PRE = 0x1
3740 13:38:43.873680 WR_PST = 0x0
3741 13:38:43.876607 DBI_WR = 0x0
3742 13:38:43.877035 DBI_RD = 0x0
3743 13:38:43.879925 OTF = 0x1
3744 13:38:43.883299 ===================================
3745 13:38:43.886517 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3746 13:38:43.889713 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3747 13:38:43.896445 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 13:38:43.899569 ===================================
3749 13:38:43.899989 LPDDR4 DRAM CONFIGURATION
3750 13:38:43.903148 ===================================
3751 13:38:43.906305 EX_ROW_EN[0] = 0x10
3752 13:38:43.906720 EX_ROW_EN[1] = 0x0
3753 13:38:43.909812 LP4Y_EN = 0x0
3754 13:38:43.910230 WORK_FSP = 0x0
3755 13:38:43.912910 WL = 0x2
3756 13:38:43.916043 RL = 0x2
3757 13:38:43.916628 BL = 0x2
3758 13:38:43.919690 RPST = 0x0
3759 13:38:43.920135 RD_PRE = 0x0
3760 13:38:43.922752 WR_PRE = 0x1
3761 13:38:43.923165 WR_PST = 0x0
3762 13:38:43.926373 DBI_WR = 0x0
3763 13:38:43.926784 DBI_RD = 0x0
3764 13:38:43.929555 OTF = 0x1
3765 13:38:43.932535 ===================================
3766 13:38:43.939044 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3767 13:38:43.942061 nWR fixed to 30
3768 13:38:43.942480 [ModeRegInit_LP4] CH0 RK0
3769 13:38:43.945699 [ModeRegInit_LP4] CH0 RK1
3770 13:38:43.948718 [ModeRegInit_LP4] CH1 RK0
3771 13:38:43.952401 [ModeRegInit_LP4] CH1 RK1
3772 13:38:43.952818 match AC timing 16
3773 13:38:43.955641 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3774 13:38:43.962241 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3775 13:38:43.965987 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3776 13:38:43.971895 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3777 13:38:43.975295 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3778 13:38:43.975717 ==
3779 13:38:43.978651 Dram Type= 6, Freq= 0, CH_0, rank 0
3780 13:38:43.982037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3781 13:38:43.982386 ==
3782 13:38:43.988673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3783 13:38:43.995061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3784 13:38:43.998405 [CA 0] Center 35 (5~66) winsize 62
3785 13:38:44.001695 [CA 1] Center 35 (5~66) winsize 62
3786 13:38:44.005138 [CA 2] Center 34 (4~65) winsize 62
3787 13:38:44.008702 [CA 3] Center 34 (4~65) winsize 62
3788 13:38:44.011609 [CA 4] Center 33 (3~64) winsize 62
3789 13:38:44.015033 [CA 5] Center 33 (3~64) winsize 62
3790 13:38:44.015332
3791 13:38:44.018032 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3792 13:38:44.018332
3793 13:38:44.021837 [CATrainingPosCal] consider 1 rank data
3794 13:38:44.025366 u2DelayCellTimex100 = 270/100 ps
3795 13:38:44.028504 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3796 13:38:44.031636 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3797 13:38:44.035190 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3798 13:38:44.038223 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3799 13:38:44.041279 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3800 13:38:44.044989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3801 13:38:44.045336
3802 13:38:44.051159 CA PerBit enable=1, Macro0, CA PI delay=33
3803 13:38:44.051570
3804 13:38:44.054754 [CBTSetCACLKResult] CA Dly = 33
3805 13:38:44.055053 CS Dly: 5 (0~36)
3806 13:38:44.055311 ==
3807 13:38:44.057761 Dram Type= 6, Freq= 0, CH_0, rank 1
3808 13:38:44.061436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3809 13:38:44.061767 ==
3810 13:38:44.067981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3811 13:38:44.074273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3812 13:38:44.077951 [CA 0] Center 35 (5~66) winsize 62
3813 13:38:44.080964 [CA 1] Center 35 (5~66) winsize 62
3814 13:38:44.084502 [CA 2] Center 34 (4~65) winsize 62
3815 13:38:44.087808 [CA 3] Center 34 (4~65) winsize 62
3816 13:38:44.091106 [CA 4] Center 33 (3~64) winsize 62
3817 13:38:44.094718 [CA 5] Center 33 (3~64) winsize 62
3818 13:38:44.095133
3819 13:38:44.097563 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3820 13:38:44.097971
3821 13:38:44.101101 [CATrainingPosCal] consider 2 rank data
3822 13:38:44.104751 u2DelayCellTimex100 = 270/100 ps
3823 13:38:44.107543 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3824 13:38:44.110835 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3825 13:38:44.114196 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3826 13:38:44.117407 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3827 13:38:44.121150 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3828 13:38:44.127902 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3829 13:38:44.128361
3830 13:38:44.130844 CA PerBit enable=1, Macro0, CA PI delay=33
3831 13:38:44.131234
3832 13:38:44.134610 [CBTSetCACLKResult] CA Dly = 33
3833 13:38:44.135053 CS Dly: 5 (0~37)
3834 13:38:44.135363
3835 13:38:44.137516 ----->DramcWriteLeveling(PI) begin...
3836 13:38:44.137994 ==
3837 13:38:44.140518 Dram Type= 6, Freq= 0, CH_0, rank 0
3838 13:38:44.147809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3839 13:38:44.148199 ==
3840 13:38:44.151072 Write leveling (Byte 0): 30 => 30
3841 13:38:44.153982 Write leveling (Byte 1): 30 => 30
3842 13:38:44.154381 DramcWriteLeveling(PI) end<-----
3843 13:38:44.154708
3844 13:38:44.157107 ==
3845 13:38:44.160789 Dram Type= 6, Freq= 0, CH_0, rank 0
3846 13:38:44.163871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3847 13:38:44.164258 ==
3848 13:38:44.167577 [Gating] SW mode calibration
3849 13:38:44.174209 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3850 13:38:44.177246 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3851 13:38:44.183819 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3852 13:38:44.186860 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3853 13:38:44.190485 0 5 8 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
3854 13:38:44.196986 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3855 13:38:44.200541 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 13:38:44.203447 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 13:38:44.210718 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 13:38:44.213416 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3859 13:38:44.216933 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 13:38:44.223531 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 13:38:44.226819 0 6 8 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
3862 13:38:44.230241 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3863 13:38:44.236906 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 13:38:44.240385 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 13:38:44.243447 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 13:38:44.250093 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 13:38:44.253158 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 13:38:44.256841 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 13:38:44.263094 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3870 13:38:44.266261 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 13:38:44.269909 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 13:38:44.276526 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 13:38:44.279693 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 13:38:44.282588 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 13:38:44.289628 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 13:38:44.292630 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 13:38:44.296492 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 13:38:44.302938 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 13:38:44.306408 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 13:38:44.309332 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 13:38:44.316203 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 13:38:44.319118 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 13:38:44.322502 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 13:38:44.329179 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 13:38:44.332847 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3886 13:38:44.335857 Total UI for P1: 0, mck2ui 16
3887 13:38:44.339483 best dqsien dly found for B0: ( 0, 9, 6)
3888 13:38:44.342830 Total UI for P1: 0, mck2ui 16
3889 13:38:44.345705 best dqsien dly found for B1: ( 0, 9, 6)
3890 13:38:44.349148 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3891 13:38:44.352834 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
3892 13:38:44.353375
3893 13:38:44.355928 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3894 13:38:44.359065 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
3895 13:38:44.362717 [Gating] SW calibration Done
3896 13:38:44.363255 ==
3897 13:38:44.365707 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 13:38:44.368815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3899 13:38:44.369194 ==
3900 13:38:44.372599 RX Vref Scan: 0
3901 13:38:44.373131
3902 13:38:44.375512 RX Vref 0 -> 0, step: 1
3903 13:38:44.375893
3904 13:38:44.376203 RX Delay -230 -> 252, step: 16
3905 13:38:44.382227 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3906 13:38:44.385270 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3907 13:38:44.388923 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3908 13:38:44.392402 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3909 13:38:44.398633 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3910 13:38:44.402056 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3911 13:38:44.405031 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3912 13:38:44.408547 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3913 13:38:44.415274 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
3914 13:38:44.418241 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3915 13:38:44.421786 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3916 13:38:44.425155 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3917 13:38:44.428350 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3918 13:38:44.434903 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3919 13:38:44.438406 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3920 13:38:44.441773 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3921 13:38:44.442157 ==
3922 13:38:44.444884 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 13:38:44.451843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3924 13:38:44.452291 ==
3925 13:38:44.452605 DQS Delay:
3926 13:38:44.452883 DQS0 = 0, DQS1 = 0
3927 13:38:44.454715 DQM Delay:
3928 13:38:44.455167 DQM0 = 38, DQM1 = 32
3929 13:38:44.458054 DQ Delay:
3930 13:38:44.461641 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3931 13:38:44.464756 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3932 13:38:44.467841 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
3933 13:38:44.471489 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3934 13:38:44.471882
3935 13:38:44.472182
3936 13:38:44.472462 ==
3937 13:38:44.474420 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 13:38:44.478160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3939 13:38:44.478551 ==
3940 13:38:44.478929
3941 13:38:44.479383
3942 13:38:44.481265 TX Vref Scan disable
3943 13:38:44.481938 == TX Byte 0 ==
3944 13:38:44.487913 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3945 13:38:44.490903 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3946 13:38:44.494481 == TX Byte 1 ==
3947 13:38:44.497479 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3948 13:38:44.501120 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3949 13:38:44.501652 ==
3950 13:38:44.504180 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 13:38:44.507807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3952 13:38:44.508312 ==
3953 13:38:44.510774
3954 13:38:44.511153
3955 13:38:44.511451 TX Vref Scan disable
3956 13:38:44.514935 == TX Byte 0 ==
3957 13:38:44.518133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3958 13:38:44.524622 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3959 13:38:44.524835 == TX Byte 1 ==
3960 13:38:44.527741 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3961 13:38:44.534592 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3962 13:38:44.534852
3963 13:38:44.535021 [DATLAT]
3964 13:38:44.535177 Freq=600, CH0 RK0
3965 13:38:44.535324
3966 13:38:44.537396 DATLAT Default: 0x9
3967 13:38:44.537616 0, 0xFFFF, sum = 0
3968 13:38:44.540843 1, 0xFFFF, sum = 0
3969 13:38:44.541055 2, 0xFFFF, sum = 0
3970 13:38:44.544090 3, 0xFFFF, sum = 0
3971 13:38:44.547694 4, 0xFFFF, sum = 0
3972 13:38:44.547804 5, 0xFFFF, sum = 0
3973 13:38:44.550943 6, 0xFFFF, sum = 0
3974 13:38:44.551025 7, 0x0, sum = 1
3975 13:38:44.551089 8, 0x0, sum = 2
3976 13:38:44.553918 9, 0x0, sum = 3
3977 13:38:44.554008 10, 0x0, sum = 4
3978 13:38:44.557877 best_step = 8
3979 13:38:44.557958
3980 13:38:44.558021 ==
3981 13:38:44.560596 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 13:38:44.563948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3983 13:38:44.564034 ==
3984 13:38:44.567445 RX Vref Scan: 1
3985 13:38:44.567538
3986 13:38:44.567606 RX Vref 0 -> 0, step: 1
3987 13:38:44.567696
3988 13:38:44.570660 RX Delay -195 -> 252, step: 8
3989 13:38:44.570742
3990 13:38:44.573743 Set Vref, RX VrefLevel [Byte0]: 50
3991 13:38:44.577470 [Byte1]: 55
3992 13:38:44.581109
3993 13:38:44.581185 Final RX Vref Byte 0 = 50 to rank0
3994 13:38:44.584756 Final RX Vref Byte 1 = 55 to rank0
3995 13:38:44.587778 Final RX Vref Byte 0 = 50 to rank1
3996 13:38:44.591020 Final RX Vref Byte 1 = 55 to rank1==
3997 13:38:44.594629 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 13:38:44.601157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 13:38:44.601249 ==
4000 13:38:44.601351 DQS Delay:
4001 13:38:44.604211 DQS0 = 0, DQS1 = 0
4002 13:38:44.604291 DQM Delay:
4003 13:38:44.604354 DQM0 = 40, DQM1 = 30
4004 13:38:44.608062 DQ Delay:
4005 13:38:44.611069 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =40
4006 13:38:44.614594 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4007 13:38:44.617552 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4008 13:38:44.621257 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4009 13:38:44.621379
4010 13:38:44.621443
4011 13:38:44.627486 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4012 13:38:44.631330 CH0 RK0: MR19=808, MR18=5C5C
4013 13:38:44.637371 CH0_RK0: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4014 13:38:44.637456
4015 13:38:44.641047 ----->DramcWriteLeveling(PI) begin...
4016 13:38:44.641135 ==
4017 13:38:44.644026 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 13:38:44.647580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4019 13:38:44.647678 ==
4020 13:38:44.650537 Write leveling (Byte 0): 32 => 32
4021 13:38:44.654491 Write leveling (Byte 1): 29 => 29
4022 13:38:44.657506 DramcWriteLeveling(PI) end<-----
4023 13:38:44.657587
4024 13:38:44.657651 ==
4025 13:38:44.660462 Dram Type= 6, Freq= 0, CH_0, rank 1
4026 13:38:44.664185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4027 13:38:44.664267 ==
4028 13:38:44.667280 [Gating] SW mode calibration
4029 13:38:44.673595 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 13:38:44.680575 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4031 13:38:44.683801 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 13:38:44.690655 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 13:38:44.693810 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 0)
4034 13:38:44.696837 0 5 12 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
4035 13:38:44.703536 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 13:38:44.707090 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 13:38:44.710271 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 13:38:44.716787 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 13:38:44.720154 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 13:38:44.723869 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 13:38:44.730502 0 6 8 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
4042 13:38:44.733600 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 13:38:44.736715 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 13:38:44.740257 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 13:38:44.746962 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 13:38:44.750583 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 13:38:44.753704 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 13:38:44.760369 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 13:38:44.763257 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4050 13:38:44.767086 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4051 13:38:44.773483 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 13:38:44.776772 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:38:44.779833 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:38:44.786693 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:38:44.789912 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:38:44.793612 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 13:38:44.799806 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 13:38:44.803381 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 13:38:44.806420 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 13:38:44.813188 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 13:38:44.816699 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:38:44.819717 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:38:44.826793 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:38:44.829771 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:38:44.832845 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4066 13:38:44.840084 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 13:38:44.840192 Total UI for P1: 0, mck2ui 16
4068 13:38:44.846266 best dqsien dly found for B0: ( 0, 9, 10)
4069 13:38:44.846348 Total UI for P1: 0, mck2ui 16
4070 13:38:44.853019 best dqsien dly found for B1: ( 0, 9, 8)
4071 13:38:44.856081 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4072 13:38:44.859689 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4073 13:38:44.859770
4074 13:38:44.863249 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4075 13:38:44.866375 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4076 13:38:44.869329 [Gating] SW calibration Done
4077 13:38:44.869423 ==
4078 13:38:44.873027 Dram Type= 6, Freq= 0, CH_0, rank 1
4079 13:38:44.876041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4080 13:38:44.876121 ==
4081 13:38:44.879055 RX Vref Scan: 0
4082 13:38:44.879135
4083 13:38:44.879198 RX Vref 0 -> 0, step: 1
4084 13:38:44.879256
4085 13:38:44.882775 RX Delay -230 -> 252, step: 16
4086 13:38:44.889444 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4087 13:38:44.892383 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4088 13:38:44.895595 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4089 13:38:44.898949 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4090 13:38:44.905609 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4091 13:38:44.909339 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4092 13:38:44.912445 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4093 13:38:44.915610 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4094 13:38:44.919246 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4095 13:38:44.925863 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4096 13:38:44.928834 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4097 13:38:44.932427 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4098 13:38:44.935735 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4099 13:38:44.942474 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4100 13:38:44.945588 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4101 13:38:44.949129 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4102 13:38:44.949212 ==
4103 13:38:44.952620 Dram Type= 6, Freq= 0, CH_0, rank 1
4104 13:38:44.955732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4105 13:38:44.955813 ==
4106 13:38:44.958797 DQS Delay:
4107 13:38:44.958900 DQS0 = 0, DQS1 = 0
4108 13:38:44.962338 DQM Delay:
4109 13:38:44.962419 DQM0 = 40, DQM1 = 33
4110 13:38:44.962482 DQ Delay:
4111 13:38:44.965860 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4112 13:38:44.968827 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4113 13:38:44.972557 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4114 13:38:44.975693 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4115 13:38:44.975800
4116 13:38:44.975891
4117 13:38:44.979141 ==
4118 13:38:44.982339 Dram Type= 6, Freq= 0, CH_0, rank 1
4119 13:38:44.985238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4120 13:38:44.985358 ==
4121 13:38:44.985424
4122 13:38:44.985483
4123 13:38:44.989004 TX Vref Scan disable
4124 13:38:44.989084 == TX Byte 0 ==
4125 13:38:44.995175 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4126 13:38:44.998958 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4127 13:38:44.999042 == TX Byte 1 ==
4128 13:38:45.005048 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4129 13:38:45.008722 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4130 13:38:45.008803 ==
4131 13:38:45.012089 Dram Type= 6, Freq= 0, CH_0, rank 1
4132 13:38:45.015406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4133 13:38:45.015488 ==
4134 13:38:45.015551
4135 13:38:45.015610
4136 13:38:45.018456 TX Vref Scan disable
4137 13:38:45.022092 == TX Byte 0 ==
4138 13:38:45.025511 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4139 13:38:45.028637 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4140 13:38:45.032040 == TX Byte 1 ==
4141 13:38:45.035153 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4142 13:38:45.038287 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4143 13:38:45.038368
4144 13:38:45.041811 [DATLAT]
4145 13:38:45.041892 Freq=600, CH0 RK1
4146 13:38:45.041956
4147 13:38:45.044977 DATLAT Default: 0x8
4148 13:38:45.045058 0, 0xFFFF, sum = 0
4149 13:38:45.048592 1, 0xFFFF, sum = 0
4150 13:38:45.048674 2, 0xFFFF, sum = 0
4151 13:38:45.051512 3, 0xFFFF, sum = 0
4152 13:38:45.051594 4, 0xFFFF, sum = 0
4153 13:38:45.055314 5, 0xFFFF, sum = 0
4154 13:38:45.055396 6, 0xFFFF, sum = 0
4155 13:38:45.058126 7, 0x0, sum = 1
4156 13:38:45.058208 8, 0x0, sum = 2
4157 13:38:45.061614 9, 0x0, sum = 3
4158 13:38:45.061695 10, 0x0, sum = 4
4159 13:38:45.064646 best_step = 8
4160 13:38:45.064726
4161 13:38:45.064788 ==
4162 13:38:45.068431 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 13:38:45.071451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4164 13:38:45.071532 ==
4165 13:38:45.075095 RX Vref Scan: 0
4166 13:38:45.075176
4167 13:38:45.075238 RX Vref 0 -> 0, step: 1
4168 13:38:45.075297
4169 13:38:45.078366 RX Delay -195 -> 252, step: 8
4170 13:38:45.085211 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4171 13:38:45.088290 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4172 13:38:45.091918 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4173 13:38:45.095033 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4174 13:38:45.101274 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4175 13:38:45.105176 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4176 13:38:45.108256 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4177 13:38:45.111383 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4178 13:38:45.117892 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4179 13:38:45.121512 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4180 13:38:45.124633 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4181 13:38:45.128047 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4182 13:38:45.131411 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4183 13:38:45.138175 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4184 13:38:45.141477 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4185 13:38:45.144419 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4186 13:38:45.144500 ==
4187 13:38:45.147687 Dram Type= 6, Freq= 0, CH_0, rank 1
4188 13:38:45.154680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4189 13:38:45.154763 ==
4190 13:38:45.154843 DQS Delay:
4191 13:38:45.157711 DQS0 = 0, DQS1 = 0
4192 13:38:45.157791 DQM Delay:
4193 13:38:45.157855 DQM0 = 41, DQM1 = 32
4194 13:38:45.160776 DQ Delay:
4195 13:38:45.164385 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4196 13:38:45.167822 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4197 13:38:45.170809 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4198 13:38:45.174452 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4199 13:38:45.174533
4200 13:38:45.174595
4201 13:38:45.181405 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4202 13:38:45.184501 CH0 RK1: MR19=808, MR18=6C6C
4203 13:38:45.191128 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4204 13:38:45.194301 [RxdqsGatingPostProcess] freq 600
4205 13:38:45.197269 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4206 13:38:45.200980 Pre-setting of DQS Precalculation
4207 13:38:45.207075 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4208 13:38:45.207184 ==
4209 13:38:45.210695 Dram Type= 6, Freq= 0, CH_1, rank 0
4210 13:38:45.213756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4211 13:38:45.213840 ==
4212 13:38:45.220469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4213 13:38:45.227082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4214 13:38:45.230723 [CA 0] Center 35 (5~66) winsize 62
4215 13:38:45.233752 [CA 1] Center 35 (5~66) winsize 62
4216 13:38:45.237130 [CA 2] Center 33 (3~64) winsize 62
4217 13:38:45.240139 [CA 3] Center 33 (3~64) winsize 62
4218 13:38:45.243558 [CA 4] Center 33 (2~64) winsize 63
4219 13:38:45.246814 [CA 5] Center 33 (2~64) winsize 63
4220 13:38:45.246915
4221 13:38:45.250455 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4222 13:38:45.250556
4223 13:38:45.253369 [CATrainingPosCal] consider 1 rank data
4224 13:38:45.256854 u2DelayCellTimex100 = 270/100 ps
4225 13:38:45.260174 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4226 13:38:45.263314 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4227 13:38:45.266944 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4228 13:38:45.270362 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4229 13:38:45.273518 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4230 13:38:45.276734 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4231 13:38:45.276817
4232 13:38:45.283801 CA PerBit enable=1, Macro0, CA PI delay=33
4233 13:38:45.283887
4234 13:38:45.283950 [CBTSetCACLKResult] CA Dly = 33
4235 13:38:45.286836 CS Dly: 3 (0~34)
4236 13:38:45.286918 ==
4237 13:38:45.289898 Dram Type= 6, Freq= 0, CH_1, rank 1
4238 13:38:45.293147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4239 13:38:45.293259 ==
4240 13:38:45.299969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4241 13:38:45.306652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4242 13:38:45.309641 [CA 0] Center 35 (5~66) winsize 62
4243 13:38:45.313338 [CA 1] Center 34 (4~65) winsize 62
4244 13:38:45.316148 [CA 2] Center 33 (3~64) winsize 62
4245 13:38:45.319783 [CA 3] Center 33 (3~64) winsize 62
4246 13:38:45.323514 [CA 4] Center 32 (2~63) winsize 62
4247 13:38:45.326388 [CA 5] Center 32 (2~63) winsize 62
4248 13:38:45.326489
4249 13:38:45.330229 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4250 13:38:45.330328
4251 13:38:45.333154 [CATrainingPosCal] consider 2 rank data
4252 13:38:45.336262 u2DelayCellTimex100 = 270/100 ps
4253 13:38:45.339837 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4254 13:38:45.343322 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4255 13:38:45.346259 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4256 13:38:45.349798 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4257 13:38:45.353556 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4258 13:38:45.356231 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4259 13:38:45.359919
4260 13:38:45.362822 CA PerBit enable=1, Macro0, CA PI delay=32
4261 13:38:45.362896
4262 13:38:45.366589 [CBTSetCACLKResult] CA Dly = 32
4263 13:38:45.366675 CS Dly: 3 (0~35)
4264 13:38:45.366739
4265 13:38:45.369444 ----->DramcWriteLeveling(PI) begin...
4266 13:38:45.369527 ==
4267 13:38:45.372920 Dram Type= 6, Freq= 0, CH_1, rank 0
4268 13:38:45.376467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4269 13:38:45.379481 ==
4270 13:38:45.379563 Write leveling (Byte 0): 25 => 25
4271 13:38:45.382980 Write leveling (Byte 1): 29 => 29
4272 13:38:45.386237 DramcWriteLeveling(PI) end<-----
4273 13:38:45.386318
4274 13:38:45.386381 ==
4275 13:38:45.389491 Dram Type= 6, Freq= 0, CH_1, rank 0
4276 13:38:45.396537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4277 13:38:45.396624 ==
4278 13:38:45.396689 [Gating] SW mode calibration
4279 13:38:45.405788 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4280 13:38:45.409453 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4281 13:38:45.416248 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4282 13:38:45.419188 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4283 13:38:45.422904 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4284 13:38:45.426094 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 13:38:45.432672 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 13:38:45.435771 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 13:38:45.439489 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 13:38:45.445562 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 13:38:45.448868 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 13:38:45.452512 0 6 4 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4291 13:38:45.459001 0 6 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4292 13:38:45.462337 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 13:38:45.468607 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 13:38:45.472461 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 13:38:45.475444 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 13:38:45.478915 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 13:38:45.485503 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 13:38:45.488910 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 13:38:45.492098 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4300 13:38:45.498924 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 13:38:45.502246 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 13:38:45.505323 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 13:38:45.511908 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 13:38:45.515117 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 13:38:45.518750 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 13:38:45.525406 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 13:38:45.528505 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 13:38:45.532078 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 13:38:45.538610 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 13:38:45.541623 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 13:38:45.545229 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 13:38:45.552034 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 13:38:45.554983 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 13:38:45.558088 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4315 13:38:45.564758 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4316 13:38:45.564842 Total UI for P1: 0, mck2ui 16
4317 13:38:45.571443 best dqsien dly found for B0: ( 0, 9, 4)
4318 13:38:45.574440 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 13:38:45.578150 Total UI for P1: 0, mck2ui 16
4320 13:38:45.581296 best dqsien dly found for B1: ( 0, 9, 8)
4321 13:38:45.584911 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4322 13:38:45.588326 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4323 13:38:45.588408
4324 13:38:45.591514 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4325 13:38:45.594488 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4326 13:38:45.598098 [Gating] SW calibration Done
4327 13:38:45.598210 ==
4328 13:38:45.600963 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 13:38:45.604469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4330 13:38:45.608001 ==
4331 13:38:45.608082 RX Vref Scan: 0
4332 13:38:45.608147
4333 13:38:45.610898 RX Vref 0 -> 0, step: 1
4334 13:38:45.610979
4335 13:38:45.614175 RX Delay -230 -> 252, step: 16
4336 13:38:45.617407 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4337 13:38:45.621144 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4338 13:38:45.624172 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4339 13:38:45.630998 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4340 13:38:45.634047 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4341 13:38:45.637706 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4342 13:38:45.640574 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4343 13:38:45.644330 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4344 13:38:45.650467 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4345 13:38:45.654114 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4346 13:38:45.657030 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4347 13:38:45.660547 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4348 13:38:45.667201 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4349 13:38:45.670366 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4350 13:38:45.673924 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4351 13:38:45.676917 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4352 13:38:45.680306 ==
4353 13:38:45.680388 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 13:38:45.686894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4355 13:38:45.686984 ==
4356 13:38:45.687049 DQS Delay:
4357 13:38:45.690482 DQS0 = 0, DQS1 = 0
4358 13:38:45.690563 DQM Delay:
4359 13:38:45.694056 DQM0 = 39, DQM1 = 30
4360 13:38:45.694137 DQ Delay:
4361 13:38:45.696847 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4362 13:38:45.700379 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4363 13:38:45.703555 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4364 13:38:45.707009 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4365 13:38:45.707092
4366 13:38:45.707155
4367 13:38:45.707214 ==
4368 13:38:45.710124 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 13:38:45.713691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 13:38:45.713772 ==
4371 13:38:45.713835
4372 13:38:45.713893
4373 13:38:45.716680 TX Vref Scan disable
4374 13:38:45.720220 == TX Byte 0 ==
4375 13:38:45.723653 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4376 13:38:45.727009 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4377 13:38:45.729890 == TX Byte 1 ==
4378 13:38:45.733553 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4379 13:38:45.736684 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4380 13:38:45.736765 ==
4381 13:38:45.739796 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 13:38:45.747010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4383 13:38:45.747091 ==
4384 13:38:45.747154
4385 13:38:45.747212
4386 13:38:45.747268 TX Vref Scan disable
4387 13:38:45.750734 == TX Byte 0 ==
4388 13:38:45.754519 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4389 13:38:45.761216 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4390 13:38:45.761323 == TX Byte 1 ==
4391 13:38:45.764353 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4392 13:38:45.770778 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4393 13:38:45.770859
4394 13:38:45.770922 [DATLAT]
4395 13:38:45.770995 Freq=600, CH1 RK0
4396 13:38:45.771056
4397 13:38:45.774405 DATLAT Default: 0x9
4398 13:38:45.774484 0, 0xFFFF, sum = 0
4399 13:38:45.777420 1, 0xFFFF, sum = 0
4400 13:38:45.777502 2, 0xFFFF, sum = 0
4401 13:38:45.780939 3, 0xFFFF, sum = 0
4402 13:38:45.784051 4, 0xFFFF, sum = 0
4403 13:38:45.784132 5, 0xFFFF, sum = 0
4404 13:38:45.787585 6, 0xFFFF, sum = 0
4405 13:38:45.787666 7, 0x0, sum = 1
4406 13:38:45.787730 8, 0x0, sum = 2
4407 13:38:45.790893 9, 0x0, sum = 3
4408 13:38:45.790975 10, 0x0, sum = 4
4409 13:38:45.793942 best_step = 8
4410 13:38:45.794021
4411 13:38:45.794084 ==
4412 13:38:45.797623 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 13:38:45.800601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4414 13:38:45.800683 ==
4415 13:38:45.804160 RX Vref Scan: 1
4416 13:38:45.804240
4417 13:38:45.804309 RX Vref 0 -> 0, step: 1
4418 13:38:45.804406
4419 13:38:45.807320 RX Delay -195 -> 252, step: 8
4420 13:38:45.807401
4421 13:38:45.810794 Set Vref, RX VrefLevel [Byte0]: 55
4422 13:38:45.813914 [Byte1]: 48
4423 13:38:45.818032
4424 13:38:45.818112 Final RX Vref Byte 0 = 55 to rank0
4425 13:38:45.821195 Final RX Vref Byte 1 = 48 to rank0
4426 13:38:45.824657 Final RX Vref Byte 0 = 55 to rank1
4427 13:38:45.827773 Final RX Vref Byte 1 = 48 to rank1==
4428 13:38:45.831337 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 13:38:45.838099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4430 13:38:45.838227 ==
4431 13:38:45.838291 DQS Delay:
4432 13:38:45.838349 DQS0 = 0, DQS1 = 0
4433 13:38:45.841110 DQM Delay:
4434 13:38:45.841189 DQM0 = 38, DQM1 = 31
4435 13:38:45.844291 DQ Delay:
4436 13:38:45.848094 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4437 13:38:45.848175 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4438 13:38:45.850965 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4439 13:38:45.857644 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4440 13:38:45.857725
4441 13:38:45.857788
4442 13:38:45.864315 [DQSOSCAuto] RK0, (LSB)MR18= 0x7878, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4443 13:38:45.867986 CH1 RK0: MR19=808, MR18=7878
4444 13:38:45.874209 CH1_RK0: MR19=0x808, MR18=0x7878, DQSOSC=387, MR23=63, INC=175, DEC=116
4445 13:38:45.874291
4446 13:38:45.877658 ----->DramcWriteLeveling(PI) begin...
4447 13:38:45.877744 ==
4448 13:38:45.880731 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 13:38:45.884457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4450 13:38:45.884539 ==
4451 13:38:45.887481 Write leveling (Byte 0): 27 => 27
4452 13:38:45.891201 Write leveling (Byte 1): 27 => 27
4453 13:38:45.894164 DramcWriteLeveling(PI) end<-----
4454 13:38:45.894243
4455 13:38:45.894306 ==
4456 13:38:45.897542 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 13:38:45.901115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4458 13:38:45.901197 ==
4459 13:38:45.904153 [Gating] SW mode calibration
4460 13:38:45.910775 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 13:38:45.917365 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4462 13:38:45.920760 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 13:38:45.927282 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4464 13:38:45.930789 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
4465 13:38:45.933744 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 13:38:45.940472 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 13:38:45.944029 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 13:38:45.947388 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 13:38:45.953968 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 13:38:45.956816 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 13:38:45.960432 0 6 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4472 13:38:45.967137 0 6 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4473 13:38:45.970257 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:38:45.973298 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 13:38:45.980374 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 13:38:45.983167 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 13:38:45.986733 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 13:38:45.993501 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 13:38:45.996473 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4480 13:38:46.000074 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 13:38:46.006356 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 13:38:46.010067 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 13:38:46.013150 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 13:38:46.019906 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 13:38:46.022833 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 13:38:46.026202 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 13:38:46.032963 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 13:38:46.036234 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:38:46.039577 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:38:46.046380 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:38:46.049247 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:38:46.052685 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:38:46.056204 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:38:46.062822 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:38:46.066068 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4496 13:38:46.069017 Total UI for P1: 0, mck2ui 16
4497 13:38:46.072635 best dqsien dly found for B0: ( 0, 9, 2)
4498 13:38:46.075731 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4499 13:38:46.082415 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 13:38:46.085806 Total UI for P1: 0, mck2ui 16
4501 13:38:46.089222 best dqsien dly found for B1: ( 0, 9, 10)
4502 13:38:46.092177 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4503 13:38:46.095765 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4504 13:38:46.095850
4505 13:38:46.098948 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4506 13:38:46.102621 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4507 13:38:46.105577 [Gating] SW calibration Done
4508 13:38:46.105661 ==
4509 13:38:46.109068 Dram Type= 6, Freq= 0, CH_1, rank 1
4510 13:38:46.112378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4511 13:38:46.112464 ==
4512 13:38:46.115571 RX Vref Scan: 0
4513 13:38:46.115653
4514 13:38:46.118614 RX Vref 0 -> 0, step: 1
4515 13:38:46.118698
4516 13:38:46.118762 RX Delay -230 -> 252, step: 16
4517 13:38:46.125466 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4518 13:38:46.129012 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4519 13:38:46.131989 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4520 13:38:46.135327 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4521 13:38:46.142181 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4522 13:38:46.145582 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4523 13:38:46.148619 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4524 13:38:46.151790 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4525 13:38:46.158430 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4526 13:38:46.162122 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4527 13:38:46.165115 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 13:38:46.168582 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4529 13:38:46.175071 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4530 13:38:46.178262 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4531 13:38:46.181921 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4532 13:38:46.185130 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4533 13:38:46.185232 ==
4534 13:38:46.188189 Dram Type= 6, Freq= 0, CH_1, rank 1
4535 13:38:46.194934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4536 13:38:46.195018 ==
4537 13:38:46.195083 DQS Delay:
4538 13:38:46.195142 DQS0 = 0, DQS1 = 0
4539 13:38:46.197839 DQM Delay:
4540 13:38:46.197945 DQM0 = 39, DQM1 = 35
4541 13:38:46.201455 DQ Delay:
4542 13:38:46.204952 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4543 13:38:46.207876 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4544 13:38:46.211234 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4545 13:38:46.214997 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4546 13:38:46.215098
4547 13:38:46.215226
4548 13:38:46.215315 ==
4549 13:38:46.218055 Dram Type= 6, Freq= 0, CH_1, rank 1
4550 13:38:46.221525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4551 13:38:46.221636 ==
4552 13:38:46.221734
4553 13:38:46.221826
4554 13:38:46.224937 TX Vref Scan disable
4555 13:38:46.225037 == TX Byte 0 ==
4556 13:38:46.231255 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4557 13:38:46.234427 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4558 13:38:46.234510 == TX Byte 1 ==
4559 13:38:46.241069 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4560 13:38:46.244555 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4561 13:38:46.244639 ==
4562 13:38:46.248011 Dram Type= 6, Freq= 0, CH_1, rank 1
4563 13:38:46.251430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4564 13:38:46.251541 ==
4565 13:38:46.251632
4566 13:38:46.254259
4567 13:38:46.254340 TX Vref Scan disable
4568 13:38:46.257711 == TX Byte 0 ==
4569 13:38:46.261215 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4570 13:38:46.267725 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4571 13:38:46.267809 == TX Byte 1 ==
4572 13:38:46.271492 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4573 13:38:46.277754 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4574 13:38:46.277837
4575 13:38:46.277937 [DATLAT]
4576 13:38:46.277997 Freq=600, CH1 RK1
4577 13:38:46.278055
4578 13:38:46.281035 DATLAT Default: 0x8
4579 13:38:46.281116 0, 0xFFFF, sum = 0
4580 13:38:46.284329 1, 0xFFFF, sum = 0
4581 13:38:46.287942 2, 0xFFFF, sum = 0
4582 13:38:46.288024 3, 0xFFFF, sum = 0
4583 13:38:46.290973 4, 0xFFFF, sum = 0
4584 13:38:46.291055 5, 0xFFFF, sum = 0
4585 13:38:46.294394 6, 0xFFFF, sum = 0
4586 13:38:46.294477 7, 0x0, sum = 1
4587 13:38:46.294542 8, 0x0, sum = 2
4588 13:38:46.297451 9, 0x0, sum = 3
4589 13:38:46.297533 10, 0x0, sum = 4
4590 13:38:46.301152 best_step = 8
4591 13:38:46.301235
4592 13:38:46.301324 ==
4593 13:38:46.304020 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 13:38:46.307455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4595 13:38:46.307537 ==
4596 13:38:46.311140 RX Vref Scan: 0
4597 13:38:46.311221
4598 13:38:46.311285 RX Vref 0 -> 0, step: 1
4599 13:38:46.311344
4600 13:38:46.314385 RX Delay -195 -> 252, step: 8
4601 13:38:46.321706 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4602 13:38:46.324796 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4603 13:38:46.328467 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4604 13:38:46.331196 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4605 13:38:46.338241 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4606 13:38:46.341445 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4607 13:38:46.344426 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4608 13:38:46.348050 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4609 13:38:46.354668 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4610 13:38:46.357572 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4611 13:38:46.361148 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4612 13:38:46.364746 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4613 13:38:46.371000 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4614 13:38:46.374507 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4615 13:38:46.377616 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4616 13:38:46.381075 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4617 13:38:46.381158 ==
4618 13:38:46.384090 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 13:38:46.390623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4620 13:38:46.390707 ==
4621 13:38:46.390772 DQS Delay:
4622 13:38:46.394338 DQS0 = 0, DQS1 = 0
4623 13:38:46.394418 DQM Delay:
4624 13:38:46.394482 DQM0 = 37, DQM1 = 30
4625 13:38:46.397435 DQ Delay:
4626 13:38:46.401097 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4627 13:38:46.404241 DQ4 =40, DQ5 =44, DQ6 =44, DQ7 =36
4628 13:38:46.407161 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4629 13:38:46.410730 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4630 13:38:46.410827
4631 13:38:46.410904
4632 13:38:46.417604 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4633 13:38:46.420726 CH1 RK1: MR19=808, MR18=5D5D
4634 13:38:46.427517 CH1_RK1: MR19=0x808, MR18=0x5D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4635 13:38:46.430591 [RxdqsGatingPostProcess] freq 600
4636 13:38:46.434321 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4637 13:38:46.437192 Pre-setting of DQS Precalculation
4638 13:38:46.444049 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4639 13:38:46.450673 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4640 13:38:46.457218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4641 13:38:46.457323
4642 13:38:46.457400
4643 13:38:46.460210 [Calibration Summary] 1200 Mbps
4644 13:38:46.460292 CH 0, Rank 0
4645 13:38:46.463804 SW Impedance : PASS
4646 13:38:46.467066 DUTY Scan : NO K
4647 13:38:46.467147 ZQ Calibration : PASS
4648 13:38:46.470575 Jitter Meter : NO K
4649 13:38:46.473405 CBT Training : PASS
4650 13:38:46.473486 Write leveling : PASS
4651 13:38:46.476777 RX DQS gating : PASS
4652 13:38:46.480133 RX DQ/DQS(RDDQC) : PASS
4653 13:38:46.480214 TX DQ/DQS : PASS
4654 13:38:46.483693 RX DATLAT : PASS
4655 13:38:46.486702 RX DQ/DQS(Engine): PASS
4656 13:38:46.486783 TX OE : NO K
4657 13:38:46.490334 All Pass.
4658 13:38:46.490415
4659 13:38:46.490479 CH 0, Rank 1
4660 13:38:46.493699 SW Impedance : PASS
4661 13:38:46.493780 DUTY Scan : NO K
4662 13:38:46.496845 ZQ Calibration : PASS
4663 13:38:46.499827 Jitter Meter : NO K
4664 13:38:46.499911 CBT Training : PASS
4665 13:38:46.503527 Write leveling : PASS
4666 13:38:46.506703 RX DQS gating : PASS
4667 13:38:46.506786 RX DQ/DQS(RDDQC) : PASS
4668 13:38:46.509868 TX DQ/DQS : PASS
4669 13:38:46.509950 RX DATLAT : PASS
4670 13:38:46.513483 RX DQ/DQS(Engine): PASS
4671 13:38:46.516535 TX OE : NO K
4672 13:38:46.516616 All Pass.
4673 13:38:46.516681
4674 13:38:46.516740 CH 1, Rank 0
4675 13:38:46.520067 SW Impedance : PASS
4676 13:38:46.523506 DUTY Scan : NO K
4677 13:38:46.523588 ZQ Calibration : PASS
4678 13:38:46.526453 Jitter Meter : NO K
4679 13:38:46.530105 CBT Training : PASS
4680 13:38:46.530187 Write leveling : PASS
4681 13:38:46.533335 RX DQS gating : PASS
4682 13:38:46.536494 RX DQ/DQS(RDDQC) : PASS
4683 13:38:46.536575 TX DQ/DQS : PASS
4684 13:38:46.540124 RX DATLAT : PASS
4685 13:38:46.543041 RX DQ/DQS(Engine): PASS
4686 13:38:46.543123 TX OE : NO K
4687 13:38:46.546568 All Pass.
4688 13:38:46.546653
4689 13:38:46.546723 CH 1, Rank 1
4690 13:38:46.549526 SW Impedance : PASS
4691 13:38:46.549608 DUTY Scan : NO K
4692 13:38:46.552831 ZQ Calibration : PASS
4693 13:38:46.556539 Jitter Meter : NO K
4694 13:38:46.556621 CBT Training : PASS
4695 13:38:46.559502 Write leveling : PASS
4696 13:38:46.562988 RX DQS gating : PASS
4697 13:38:46.563069 RX DQ/DQS(RDDQC) : PASS
4698 13:38:46.566311 TX DQ/DQS : PASS
4699 13:38:46.566394 RX DATLAT : PASS
4700 13:38:46.569859 RX DQ/DQS(Engine): PASS
4701 13:38:46.572957 TX OE : NO K
4702 13:38:46.573039 All Pass.
4703 13:38:46.573103
4704 13:38:46.576774 DramC Write-DBI off
4705 13:38:46.576861 PER_BANK_REFRESH: Hybrid Mode
4706 13:38:46.579777 TX_TRACKING: ON
4707 13:38:46.589442 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4708 13:38:46.592908 [FAST_K] Save calibration result to emmc
4709 13:38:46.596460 dramc_set_vcore_voltage set vcore to 662500
4710 13:38:46.596582 Read voltage for 933, 3
4711 13:38:46.599833 Vio18 = 0
4712 13:38:46.599971 Vcore = 662500
4713 13:38:46.600076 Vdram = 0
4714 13:38:46.602616 Vddq = 0
4715 13:38:46.602750 Vmddr = 0
4716 13:38:46.609494 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4717 13:38:46.612596 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4718 13:38:46.616242 MEM_TYPE=3, freq_sel=17
4719 13:38:46.619311 sv_algorithm_assistance_LP4_1600
4720 13:38:46.622936 ============ PULL DRAM RESETB DOWN ============
4721 13:38:46.626197 ========== PULL DRAM RESETB DOWN end =========
4722 13:38:46.633104 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4723 13:38:46.636516 ===================================
4724 13:38:46.636943 LPDDR4 DRAM CONFIGURATION
4725 13:38:46.639601 ===================================
4726 13:38:46.642786 EX_ROW_EN[0] = 0x0
4727 13:38:46.646470 EX_ROW_EN[1] = 0x0
4728 13:38:46.646895 LP4Y_EN = 0x0
4729 13:38:46.649621 WORK_FSP = 0x0
4730 13:38:46.650111 WL = 0x3
4731 13:38:46.652685 RL = 0x3
4732 13:38:46.653172 BL = 0x2
4733 13:38:46.656146 RPST = 0x0
4734 13:38:46.656615 RD_PRE = 0x0
4735 13:38:46.659571 WR_PRE = 0x1
4736 13:38:46.660076 WR_PST = 0x0
4737 13:38:46.662516 DBI_WR = 0x0
4738 13:38:46.662951 DBI_RD = 0x0
4739 13:38:46.665987 OTF = 0x1
4740 13:38:46.669382 ===================================
4741 13:38:46.672771 ===================================
4742 13:38:46.673256 ANA top config
4743 13:38:46.675794 ===================================
4744 13:38:46.679563 DLL_ASYNC_EN = 0
4745 13:38:46.682658 ALL_SLAVE_EN = 1
4746 13:38:46.683177 NEW_RANK_MODE = 1
4747 13:38:46.685775 DLL_IDLE_MODE = 1
4748 13:38:46.689428 LP45_APHY_COMB_EN = 1
4749 13:38:46.692290 TX_ODT_DIS = 1
4750 13:38:46.695931 NEW_8X_MODE = 1
4751 13:38:46.699284 ===================================
4752 13:38:46.702475 ===================================
4753 13:38:46.702965 data_rate = 1866
4754 13:38:46.705681 CKR = 1
4755 13:38:46.709075 DQ_P2S_RATIO = 8
4756 13:38:46.712455 ===================================
4757 13:38:46.715603 CA_P2S_RATIO = 8
4758 13:38:46.719287 DQ_CA_OPEN = 0
4759 13:38:46.722245 DQ_SEMI_OPEN = 0
4760 13:38:46.722740 CA_SEMI_OPEN = 0
4761 13:38:46.725213 CA_FULL_RATE = 0
4762 13:38:46.728812 DQ_CKDIV4_EN = 1
4763 13:38:46.732039 CA_CKDIV4_EN = 1
4764 13:38:46.735613 CA_PREDIV_EN = 0
4765 13:38:46.739294 PH8_DLY = 0
4766 13:38:46.739717 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4767 13:38:46.742139 DQ_AAMCK_DIV = 4
4768 13:38:46.745536 CA_AAMCK_DIV = 4
4769 13:38:46.748633 CA_ADMCK_DIV = 4
4770 13:38:46.752272 DQ_TRACK_CA_EN = 0
4771 13:38:46.755408 CA_PICK = 933
4772 13:38:46.758609 CA_MCKIO = 933
4773 13:38:46.759188 MCKIO_SEMI = 0
4774 13:38:46.762318 PLL_FREQ = 3732
4775 13:38:46.765240 DQ_UI_PI_RATIO = 32
4776 13:38:46.768742 CA_UI_PI_RATIO = 0
4777 13:38:46.772018 ===================================
4778 13:38:46.775385 ===================================
4779 13:38:46.778745 memory_type:LPDDR4
4780 13:38:46.779166 GP_NUM : 10
4781 13:38:46.781916 SRAM_EN : 1
4782 13:38:46.784916 MD32_EN : 0
4783 13:38:46.788763 ===================================
4784 13:38:46.789185 [ANA_INIT] >>>>>>>>>>>>>>
4785 13:38:46.791911 <<<<<< [CONFIGURE PHASE]: ANA_TX
4786 13:38:46.794812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4787 13:38:46.798501 ===================================
4788 13:38:46.801516 data_rate = 1866,PCW = 0X8f00
4789 13:38:46.805116 ===================================
4790 13:38:46.808620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4791 13:38:46.815023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4792 13:38:46.817950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4793 13:38:46.824901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4794 13:38:46.827880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4795 13:38:46.831617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4796 13:38:46.832043 [ANA_INIT] flow start
4797 13:38:46.834730 [ANA_INIT] PLL >>>>>>>>
4798 13:38:46.838353 [ANA_INIT] PLL <<<<<<<<
4799 13:38:46.841440 [ANA_INIT] MIDPI >>>>>>>>
4800 13:38:46.841739 [ANA_INIT] MIDPI <<<<<<<<
4801 13:38:46.844464 [ANA_INIT] DLL >>>>>>>>
4802 13:38:46.847928 [ANA_INIT] flow end
4803 13:38:46.851496 ============ LP4 DIFF to SE enter ============
4804 13:38:46.854379 ============ LP4 DIFF to SE exit ============
4805 13:38:46.858048 [ANA_INIT] <<<<<<<<<<<<<
4806 13:38:46.860992 [Flow] Enable top DCM control >>>>>
4807 13:38:46.864175 [Flow] Enable top DCM control <<<<<
4808 13:38:46.867937 Enable DLL master slave shuffle
4809 13:38:46.871436 ==============================================================
4810 13:38:46.874441 Gating Mode config
4811 13:38:46.877898 ==============================================================
4812 13:38:46.881497 Config description:
4813 13:38:46.891464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4814 13:38:46.897971 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4815 13:38:46.900854 SELPH_MODE 0: By rank 1: By Phase
4816 13:38:46.907744 ==============================================================
4817 13:38:46.910835 GAT_TRACK_EN = 1
4818 13:38:46.914608 RX_GATING_MODE = 2
4819 13:38:46.917569 RX_GATING_TRACK_MODE = 2
4820 13:38:46.920956 SELPH_MODE = 1
4821 13:38:46.924295 PICG_EARLY_EN = 1
4822 13:38:46.927340 VALID_LAT_VALUE = 1
4823 13:38:46.930445 ==============================================================
4824 13:38:46.933885 Enter into Gating configuration >>>>
4825 13:38:46.936903 Exit from Gating configuration <<<<
4826 13:38:46.940560 Enter into DVFS_PRE_config >>>>>
4827 13:38:46.953560 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4828 13:38:46.953650 Exit from DVFS_PRE_config <<<<<
4829 13:38:46.957036 Enter into PICG configuration >>>>
4830 13:38:46.960414 Exit from PICG configuration <<<<
4831 13:38:46.963567 [RX_INPUT] configuration >>>>>
4832 13:38:46.966581 [RX_INPUT] configuration <<<<<
4833 13:38:46.973426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4834 13:38:46.977034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4835 13:38:46.983359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4836 13:38:46.989888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4837 13:38:46.996909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4838 13:38:47.003802 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4839 13:38:47.006829 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4840 13:38:47.009864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4841 13:38:47.013547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4842 13:38:47.020173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4843 13:38:47.023244 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4844 13:38:47.026923 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 13:38:47.030109 ===================================
4846 13:38:47.033069 LPDDR4 DRAM CONFIGURATION
4847 13:38:47.036686 ===================================
4848 13:38:47.036798 EX_ROW_EN[0] = 0x0
4849 13:38:47.040028 EX_ROW_EN[1] = 0x0
4850 13:38:47.043177 LP4Y_EN = 0x0
4851 13:38:47.043260 WORK_FSP = 0x0
4852 13:38:47.046677 WL = 0x3
4853 13:38:47.046758 RL = 0x3
4854 13:38:47.049786 BL = 0x2
4855 13:38:47.049867 RPST = 0x0
4856 13:38:47.053559 RD_PRE = 0x0
4857 13:38:47.053641 WR_PRE = 0x1
4858 13:38:47.056635 WR_PST = 0x0
4859 13:38:47.056716 DBI_WR = 0x0
4860 13:38:47.059636 DBI_RD = 0x0
4861 13:38:47.059718 OTF = 0x1
4862 13:38:47.063295 ===================================
4863 13:38:47.066730 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4864 13:38:47.073127 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4865 13:38:47.076233 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4866 13:38:47.079898 ===================================
4867 13:38:47.083078 LPDDR4 DRAM CONFIGURATION
4868 13:38:47.085998 ===================================
4869 13:38:47.086092 EX_ROW_EN[0] = 0x10
4870 13:38:47.089545 EX_ROW_EN[1] = 0x0
4871 13:38:47.092934 LP4Y_EN = 0x0
4872 13:38:47.093015 WORK_FSP = 0x0
4873 13:38:47.096364 WL = 0x3
4874 13:38:47.096445 RL = 0x3
4875 13:38:47.099433 BL = 0x2
4876 13:38:47.099513 RPST = 0x0
4877 13:38:47.103054 RD_PRE = 0x0
4878 13:38:47.103137 WR_PRE = 0x1
4879 13:38:47.106271 WR_PST = 0x0
4880 13:38:47.106352 DBI_WR = 0x0
4881 13:38:47.109562 DBI_RD = 0x0
4882 13:38:47.109643 OTF = 0x1
4883 13:38:47.112528 ===================================
4884 13:38:47.119261 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4885 13:38:47.123542 nWR fixed to 30
4886 13:38:47.127070 [ModeRegInit_LP4] CH0 RK0
4887 13:38:47.127152 [ModeRegInit_LP4] CH0 RK1
4888 13:38:47.130247 [ModeRegInit_LP4] CH1 RK0
4889 13:38:47.133329 [ModeRegInit_LP4] CH1 RK1
4890 13:38:47.133408 match AC timing 8
4891 13:38:47.140190 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4892 13:38:47.143696 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4893 13:38:47.147091 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4894 13:38:47.153545 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4895 13:38:47.156462 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4896 13:38:47.156540 ==
4897 13:38:47.159998 Dram Type= 6, Freq= 0, CH_0, rank 0
4898 13:38:47.163143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4899 13:38:47.163219 ==
4900 13:38:47.170023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4901 13:38:47.176458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4902 13:38:47.180046 [CA 0] Center 38 (8~69) winsize 62
4903 13:38:47.183080 [CA 1] Center 38 (8~69) winsize 62
4904 13:38:47.186112 [CA 2] Center 36 (5~67) winsize 63
4905 13:38:47.189873 [CA 3] Center 36 (5~67) winsize 63
4906 13:38:47.192907 [CA 4] Center 34 (4~65) winsize 62
4907 13:38:47.196557 [CA 5] Center 34 (4~65) winsize 62
4908 13:38:47.196634
4909 13:38:47.199505 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4910 13:38:47.199580
4911 13:38:47.202781 [CATrainingPosCal] consider 1 rank data
4912 13:38:47.206522 u2DelayCellTimex100 = 270/100 ps
4913 13:38:47.209617 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4914 13:38:47.212991 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4915 13:38:47.216204 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4916 13:38:47.219530 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4917 13:38:47.223123 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4918 13:38:47.229988 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4919 13:38:47.230069
4920 13:38:47.232893 CA PerBit enable=1, Macro0, CA PI delay=34
4921 13:38:47.232993
4922 13:38:47.235981 [CBTSetCACLKResult] CA Dly = 34
4923 13:38:47.236080 CS Dly: 7 (0~38)
4924 13:38:47.236171 ==
4925 13:38:47.239662 Dram Type= 6, Freq= 0, CH_0, rank 1
4926 13:38:47.242732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4927 13:38:47.246351 ==
4928 13:38:47.249535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4929 13:38:47.256019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4930 13:38:47.259464 [CA 0] Center 38 (8~69) winsize 62
4931 13:38:47.262795 [CA 1] Center 38 (7~69) winsize 63
4932 13:38:47.265723 [CA 2] Center 36 (5~67) winsize 63
4933 13:38:47.269228 [CA 3] Center 35 (5~66) winsize 62
4934 13:38:47.272676 [CA 4] Center 34 (4~65) winsize 62
4935 13:38:47.275605 [CA 5] Center 34 (4~65) winsize 62
4936 13:38:47.275683
4937 13:38:47.279345 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4938 13:38:47.279423
4939 13:38:47.282213 [CATrainingPosCal] consider 2 rank data
4940 13:38:47.285657 u2DelayCellTimex100 = 270/100 ps
4941 13:38:47.288865 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4942 13:38:47.292038 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4943 13:38:47.295557 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4944 13:38:47.302279 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4945 13:38:47.305822 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4946 13:38:47.308650 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4947 13:38:47.308735
4948 13:38:47.312379 CA PerBit enable=1, Macro0, CA PI delay=34
4949 13:38:47.312485
4950 13:38:47.315210 [CBTSetCACLKResult] CA Dly = 34
4951 13:38:47.315315 CS Dly: 7 (0~39)
4952 13:38:47.315405
4953 13:38:47.318900 ----->DramcWriteLeveling(PI) begin...
4954 13:38:47.322343 ==
4955 13:38:47.322423 Dram Type= 6, Freq= 0, CH_0, rank 0
4956 13:38:47.328419 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4957 13:38:47.328579 ==
4958 13:38:47.332214 Write leveling (Byte 0): 28 => 28
4959 13:38:47.335174 Write leveling (Byte 1): 27 => 27
4960 13:38:47.338859 DramcWriteLeveling(PI) end<-----
4961 13:38:47.338943
4962 13:38:47.339035 ==
4963 13:38:47.342100 Dram Type= 6, Freq= 0, CH_0, rank 0
4964 13:38:47.345123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4965 13:38:47.345197 ==
4966 13:38:47.348756 [Gating] SW mode calibration
4967 13:38:47.355344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4968 13:38:47.358505 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4969 13:38:47.365164 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 13:38:47.368271 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4971 13:38:47.371855 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4972 13:38:47.378504 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4973 13:38:47.381613 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4974 13:38:47.385186 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4975 13:38:47.391525 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
4976 13:38:47.395075 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 13:38:47.398469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 13:38:47.405144 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4979 13:38:47.408146 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4980 13:38:47.411568 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 13:38:47.418200 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 13:38:47.421173 0 11 20 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4983 13:38:47.425013 0 11 24 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4984 13:38:47.431940 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 13:38:47.434772 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 13:38:47.438104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4987 13:38:47.444578 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 13:38:47.448069 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 13:38:47.451366 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 13:38:47.457959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4991 13:38:47.461124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 13:38:47.464659 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 13:38:47.471084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 13:38:47.474615 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 13:38:47.477781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 13:38:47.484614 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 13:38:47.487581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 13:38:47.491220 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 13:38:47.497233 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 13:38:47.500884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 13:38:47.504476 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 13:38:47.510752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 13:38:47.514277 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 13:38:47.517809 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 13:38:47.524304 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 13:38:47.527297 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5007 13:38:47.531048 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5008 13:38:47.534098 Total UI for P1: 0, mck2ui 16
5009 13:38:47.537334 best dqsien dly found for B0: ( 0, 14, 20)
5010 13:38:47.540411 Total UI for P1: 0, mck2ui 16
5011 13:38:47.544109 best dqsien dly found for B1: ( 0, 14, 20)
5012 13:38:47.546918 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5013 13:38:47.550286 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5014 13:38:47.550367
5015 13:38:47.557091 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5016 13:38:47.560124 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5017 13:38:47.560205 [Gating] SW calibration Done
5018 13:38:47.563672 ==
5019 13:38:47.566771 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 13:38:47.570291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5021 13:38:47.570395 ==
5022 13:38:47.570481 RX Vref Scan: 0
5023 13:38:47.570558
5024 13:38:47.573648 RX Vref 0 -> 0, step: 1
5025 13:38:47.573727
5026 13:38:47.577046 RX Delay -80 -> 252, step: 8
5027 13:38:47.580399 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5028 13:38:47.583340 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5029 13:38:47.586839 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5030 13:38:47.593470 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5031 13:38:47.596510 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5032 13:38:47.600121 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5033 13:38:47.603162 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5034 13:38:47.606714 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5035 13:38:47.613236 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5036 13:38:47.616595 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5037 13:38:47.620152 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5038 13:38:47.623198 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5039 13:38:47.626554 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5040 13:38:47.630061 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5041 13:38:47.636703 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5042 13:38:47.639748 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5043 13:38:47.639834 ==
5044 13:38:47.643254 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 13:38:47.646816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5046 13:38:47.646908 ==
5047 13:38:47.649859 DQS Delay:
5048 13:38:47.649936 DQS0 = 0, DQS1 = 0
5049 13:38:47.650011 DQM Delay:
5050 13:38:47.653400 DQM0 = 96, DQM1 = 86
5051 13:38:47.653481 DQ Delay:
5052 13:38:47.656276 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5053 13:38:47.659707 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5054 13:38:47.662933 DQ8 =83, DQ9 =71, DQ10 =87, DQ11 =83
5055 13:38:47.666396 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5056 13:38:47.666493
5057 13:38:47.666591
5058 13:38:47.666685 ==
5059 13:38:47.670008 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 13:38:47.676197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 13:38:47.676291 ==
5062 13:38:47.676392
5063 13:38:47.676482
5064 13:38:47.676570 TX Vref Scan disable
5065 13:38:47.680062 == TX Byte 0 ==
5066 13:38:47.683244 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5067 13:38:47.686378 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5068 13:38:47.690056 == TX Byte 1 ==
5069 13:38:47.693653 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5070 13:38:47.699804 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5071 13:38:47.699915 ==
5072 13:38:47.703480 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 13:38:47.706578 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 13:38:47.706686 ==
5075 13:38:47.706780
5076 13:38:47.706862
5077 13:38:47.709624 TX Vref Scan disable
5078 13:38:47.709706 == TX Byte 0 ==
5079 13:38:47.716240 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5080 13:38:47.719868 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5081 13:38:47.719977 == TX Byte 1 ==
5082 13:38:47.726212 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5083 13:38:47.729700 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5084 13:38:47.729800
5085 13:38:47.729864 [DATLAT]
5086 13:38:47.733069 Freq=933, CH0 RK0
5087 13:38:47.733197
5088 13:38:47.733320 DATLAT Default: 0xd
5089 13:38:47.736054 0, 0xFFFF, sum = 0
5090 13:38:47.736164 1, 0xFFFF, sum = 0
5091 13:38:47.739839 2, 0xFFFF, sum = 0
5092 13:38:47.739925 3, 0xFFFF, sum = 0
5093 13:38:47.742875 4, 0xFFFF, sum = 0
5094 13:38:47.746460 5, 0xFFFF, sum = 0
5095 13:38:47.746547 6, 0xFFFF, sum = 0
5096 13:38:47.749243 7, 0xFFFF, sum = 0
5097 13:38:47.749390 8, 0xFFFF, sum = 0
5098 13:38:47.752824 9, 0xFFFF, sum = 0
5099 13:38:47.752931 10, 0x0, sum = 1
5100 13:38:47.755911 11, 0x0, sum = 2
5101 13:38:47.755998 12, 0x0, sum = 3
5102 13:38:47.756084 13, 0x0, sum = 4
5103 13:38:47.759627 best_step = 11
5104 13:38:47.759711
5105 13:38:47.759794 ==
5106 13:38:47.762549 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 13:38:47.766407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5108 13:38:47.766494 ==
5109 13:38:47.769478 RX Vref Scan: 1
5110 13:38:47.769562
5111 13:38:47.769648 RX Vref 0 -> 0, step: 1
5112 13:38:47.773012
5113 13:38:47.773093 RX Delay -69 -> 252, step: 4
5114 13:38:47.773194
5115 13:38:47.776129 Set Vref, RX VrefLevel [Byte0]: 50
5116 13:38:47.779220 [Byte1]: 55
5117 13:38:47.783977
5118 13:38:47.787317 Final RX Vref Byte 0 = 50 to rank0
5119 13:38:47.787398 Final RX Vref Byte 1 = 55 to rank0
5120 13:38:47.790268 Final RX Vref Byte 0 = 50 to rank1
5121 13:38:47.793602 Final RX Vref Byte 1 = 55 to rank1==
5122 13:38:47.796996 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 13:38:47.803757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5124 13:38:47.803851 ==
5125 13:38:47.803951 DQS Delay:
5126 13:38:47.806732 DQS0 = 0, DQS1 = 0
5127 13:38:47.806835 DQM Delay:
5128 13:38:47.806934 DQM0 = 97, DQM1 = 88
5129 13:38:47.810405 DQ Delay:
5130 13:38:47.813433 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5131 13:38:47.817001 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =104
5132 13:38:47.820052 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5133 13:38:47.823051 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =98
5134 13:38:47.823154
5135 13:38:47.823253
5136 13:38:47.830209 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5137 13:38:47.833456 CH0 RK0: MR19=505, MR18=2626
5138 13:38:47.839786 CH0_RK0: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5139 13:38:47.839874
5140 13:38:47.843244 ----->DramcWriteLeveling(PI) begin...
5141 13:38:47.843332 ==
5142 13:38:47.846790 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 13:38:47.849936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5144 13:38:47.850026 ==
5145 13:38:47.853132 Write leveling (Byte 0): 28 => 28
5146 13:38:47.856358 Write leveling (Byte 1): 27 => 27
5147 13:38:47.859901 DramcWriteLeveling(PI) end<-----
5148 13:38:47.859986
5149 13:38:47.860072 ==
5150 13:38:47.863100 Dram Type= 6, Freq= 0, CH_0, rank 1
5151 13:38:47.869700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5152 13:38:47.869786 ==
5153 13:38:47.869872 [Gating] SW mode calibration
5154 13:38:47.879593 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 13:38:47.882604 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5156 13:38:47.885851 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 13:38:47.892514 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 13:38:47.896147 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 13:38:47.899124 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 13:38:47.905655 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5161 13:38:47.909132 0 10 20 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (1 1)
5162 13:38:47.912832 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5163 13:38:47.918989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 13:38:47.922596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 13:38:47.925622 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 13:38:47.932581 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 13:38:47.935573 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 13:38:47.939118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 13:38:47.945464 0 11 20 | B1->B0 | 3030 3838 | 0 0 | (1 1) (0 0)
5170 13:38:47.948882 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5171 13:38:47.951890 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 13:38:47.958850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 13:38:47.961809 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 13:38:47.965264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 13:38:47.972143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 13:38:47.975258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 13:38:47.978304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5178 13:38:47.985150 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5179 13:38:47.988234 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 13:38:47.991891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 13:38:47.998785 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 13:38:48.001831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 13:38:48.004888 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 13:38:48.011397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 13:38:48.014792 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 13:38:48.018217 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 13:38:48.024808 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 13:38:48.028557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 13:38:48.031741 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 13:38:48.037941 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 13:38:48.041569 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 13:38:48.044577 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 13:38:48.051325 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5194 13:38:48.054595 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5195 13:38:48.057897 Total UI for P1: 0, mck2ui 16
5196 13:38:48.061160 best dqsien dly found for B0: ( 0, 14, 20)
5197 13:38:48.064523 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 13:38:48.068172 Total UI for P1: 0, mck2ui 16
5199 13:38:48.071206 best dqsien dly found for B1: ( 0, 14, 22)
5200 13:38:48.074390 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5201 13:38:48.077972 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5202 13:38:48.078051
5203 13:38:48.084192 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5204 13:38:48.087824 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5205 13:38:48.091310 [Gating] SW calibration Done
5206 13:38:48.091390 ==
5207 13:38:48.094164 Dram Type= 6, Freq= 0, CH_0, rank 1
5208 13:38:48.097588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5209 13:38:48.097670 ==
5210 13:38:48.097755 RX Vref Scan: 0
5211 13:38:48.097835
5212 13:38:48.101085 RX Vref 0 -> 0, step: 1
5213 13:38:48.101186
5214 13:38:48.104140 RX Delay -80 -> 252, step: 8
5215 13:38:48.107244 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5216 13:38:48.111060 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5217 13:38:48.117670 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5218 13:38:48.120654 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5219 13:38:48.124012 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5220 13:38:48.127084 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5221 13:38:48.130832 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5222 13:38:48.133855 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5223 13:38:48.140679 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5224 13:38:48.143690 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5225 13:38:48.147516 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5226 13:38:48.150381 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5227 13:38:48.154061 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5228 13:38:48.160216 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5229 13:38:48.163724 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5230 13:38:48.167082 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5231 13:38:48.167166 ==
5232 13:38:48.170593 Dram Type= 6, Freq= 0, CH_0, rank 1
5233 13:38:48.173587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5234 13:38:48.173668 ==
5235 13:38:48.176660 DQS Delay:
5236 13:38:48.176736 DQS0 = 0, DQS1 = 0
5237 13:38:48.176815 DQM Delay:
5238 13:38:48.180450 DQM0 = 94, DQM1 = 86
5239 13:38:48.180523 DQ Delay:
5240 13:38:48.183455 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5241 13:38:48.186679 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5242 13:38:48.190171 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5243 13:38:48.193346 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5244 13:38:48.193456
5245 13:38:48.193548
5246 13:38:48.196337 ==
5247 13:38:48.196419 Dram Type= 6, Freq= 0, CH_0, rank 1
5248 13:38:48.203317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5249 13:38:48.203406 ==
5250 13:38:48.203508
5251 13:38:48.203596
5252 13:38:48.206754 TX Vref Scan disable
5253 13:38:48.206835 == TX Byte 0 ==
5254 13:38:48.210162 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5255 13:38:48.216805 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5256 13:38:48.216893 == TX Byte 1 ==
5257 13:38:48.219775 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5258 13:38:48.226369 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5259 13:38:48.226458 ==
5260 13:38:48.230028 Dram Type= 6, Freq= 0, CH_0, rank 1
5261 13:38:48.232836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5262 13:38:48.232918 ==
5263 13:38:48.232983
5264 13:38:48.233043
5265 13:38:48.236418 TX Vref Scan disable
5266 13:38:48.239455 == TX Byte 0 ==
5267 13:38:48.243231 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5268 13:38:48.246229 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5269 13:38:48.249859 == TX Byte 1 ==
5270 13:38:48.252861 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5271 13:38:48.256403 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5272 13:38:48.256486
5273 13:38:48.259356 [DATLAT]
5274 13:38:48.259438 Freq=933, CH0 RK1
5275 13:38:48.259503
5276 13:38:48.263029 DATLAT Default: 0xb
5277 13:38:48.263111 0, 0xFFFF, sum = 0
5278 13:38:48.266140 1, 0xFFFF, sum = 0
5279 13:38:48.266224 2, 0xFFFF, sum = 0
5280 13:38:48.269107 3, 0xFFFF, sum = 0
5281 13:38:48.269222 4, 0xFFFF, sum = 0
5282 13:38:48.272498 5, 0xFFFF, sum = 0
5283 13:38:48.272580 6, 0xFFFF, sum = 0
5284 13:38:48.275800 7, 0xFFFF, sum = 0
5285 13:38:48.275882 8, 0xFFFF, sum = 0
5286 13:38:48.279578 9, 0xFFFF, sum = 0
5287 13:38:48.279695 10, 0x0, sum = 1
5288 13:38:48.282677 11, 0x0, sum = 2
5289 13:38:48.282766 12, 0x0, sum = 3
5290 13:38:48.285857 13, 0x0, sum = 4
5291 13:38:48.285940 best_step = 11
5292 13:38:48.286004
5293 13:38:48.286093 ==
5294 13:38:48.289160 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 13:38:48.295921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5296 13:38:48.296003 ==
5297 13:38:48.296068 RX Vref Scan: 0
5298 13:38:48.296128
5299 13:38:48.298925 RX Vref 0 -> 0, step: 1
5300 13:38:48.299006
5301 13:38:48.302806 RX Delay -69 -> 252, step: 4
5302 13:38:48.305679 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5303 13:38:48.308742 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5304 13:38:48.315684 iDelay=203, Bit 2, Center 94 (-1 ~ 190) 192
5305 13:38:48.318732 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5306 13:38:48.322151 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5307 13:38:48.325312 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5308 13:38:48.328977 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5309 13:38:48.335459 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5310 13:38:48.338788 iDelay=203, Bit 8, Center 78 (-9 ~ 166) 176
5311 13:38:48.342270 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5312 13:38:48.345461 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5313 13:38:48.348696 iDelay=203, Bit 11, Center 80 (-9 ~ 170) 180
5314 13:38:48.351767 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5315 13:38:48.358690 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5316 13:38:48.361682 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5317 13:38:48.365311 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5318 13:38:48.365410 ==
5319 13:38:48.368542 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 13:38:48.372172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5321 13:38:48.372257 ==
5322 13:38:48.375122 DQS Delay:
5323 13:38:48.375205 DQS0 = 0, DQS1 = 0
5324 13:38:48.378206 DQM Delay:
5325 13:38:48.378288 DQM0 = 97, DQM1 = 87
5326 13:38:48.378353 DQ Delay:
5327 13:38:48.381827 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5328 13:38:48.385213 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5329 13:38:48.388571 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5330 13:38:48.391791 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5331 13:38:48.391875
5332 13:38:48.391939
5333 13:38:48.401561 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5334 13:38:48.404625 CH0 RK1: MR19=505, MR18=2B2B
5335 13:38:48.411278 CH0_RK1: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5336 13:38:48.411370 [RxdqsGatingPostProcess] freq 933
5337 13:38:48.418126 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5338 13:38:48.421712 Pre-setting of DQS Precalculation
5339 13:38:48.427904 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5340 13:38:48.427998 ==
5341 13:38:48.431472 Dram Type= 6, Freq= 0, CH_1, rank 0
5342 13:38:48.434259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5343 13:38:48.434371 ==
5344 13:38:48.440894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5345 13:38:48.444401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5346 13:38:48.448468 [CA 0] Center 37 (6~68) winsize 63
5347 13:38:48.451634 [CA 1] Center 37 (6~68) winsize 63
5348 13:38:48.455275 [CA 2] Center 34 (4~65) winsize 62
5349 13:38:48.458328 [CA 3] Center 34 (4~65) winsize 62
5350 13:38:48.461925 [CA 4] Center 33 (2~64) winsize 63
5351 13:38:48.465008 [CA 5] Center 33 (2~64) winsize 63
5352 13:38:48.465094
5353 13:38:48.468619 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5354 13:38:48.468705
5355 13:38:48.471865 [CATrainingPosCal] consider 1 rank data
5356 13:38:48.474813 u2DelayCellTimex100 = 270/100 ps
5357 13:38:48.478457 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5358 13:38:48.484692 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5359 13:38:48.488653 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5360 13:38:48.491577 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5361 13:38:48.495263 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5362 13:38:48.497951 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5363 13:38:48.498034
5364 13:38:48.501342 CA PerBit enable=1, Macro0, CA PI delay=33
5365 13:38:48.501424
5366 13:38:48.504678 [CBTSetCACLKResult] CA Dly = 33
5367 13:38:48.504763 CS Dly: 5 (0~36)
5368 13:38:48.508085 ==
5369 13:38:48.511641 Dram Type= 6, Freq= 0, CH_1, rank 1
5370 13:38:48.514673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5371 13:38:48.514777 ==
5372 13:38:48.518259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5373 13:38:48.524366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5374 13:38:48.528573 [CA 0] Center 37 (6~68) winsize 63
5375 13:38:48.531913 [CA 1] Center 37 (6~68) winsize 63
5376 13:38:48.535123 [CA 2] Center 34 (4~65) winsize 62
5377 13:38:48.538034 [CA 3] Center 34 (4~64) winsize 61
5378 13:38:48.541713 [CA 4] Center 33 (2~64) winsize 63
5379 13:38:48.544676 [CA 5] Center 32 (2~63) winsize 62
5380 13:38:48.544751
5381 13:38:48.548096 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5382 13:38:48.548170
5383 13:38:48.551408 [CATrainingPosCal] consider 2 rank data
5384 13:38:48.554635 u2DelayCellTimex100 = 270/100 ps
5385 13:38:48.558435 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5386 13:38:48.564755 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5387 13:38:48.568351 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5388 13:38:48.571336 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5389 13:38:48.574916 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5390 13:38:48.578176 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5391 13:38:48.578258
5392 13:38:48.581767 CA PerBit enable=1, Macro0, CA PI delay=32
5393 13:38:48.581849
5394 13:38:48.584878 [CBTSetCACLKResult] CA Dly = 32
5395 13:38:48.588166 CS Dly: 5 (0~37)
5396 13:38:48.588247
5397 13:38:48.591194 ----->DramcWriteLeveling(PI) begin...
5398 13:38:48.591277 ==
5399 13:38:48.594817 Dram Type= 6, Freq= 0, CH_1, rank 0
5400 13:38:48.597975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5401 13:38:48.598059 ==
5402 13:38:48.600874 Write leveling (Byte 0): 25 => 25
5403 13:38:48.604687 Write leveling (Byte 1): 24 => 24
5404 13:38:48.607506 DramcWriteLeveling(PI) end<-----
5405 13:38:48.607589
5406 13:38:48.607653 ==
5407 13:38:48.610958 Dram Type= 6, Freq= 0, CH_1, rank 0
5408 13:38:48.614251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5409 13:38:48.614361 ==
5410 13:38:48.617471 [Gating] SW mode calibration
5411 13:38:48.624039 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5412 13:38:48.631166 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5413 13:38:48.634266 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 13:38:48.637318 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 13:38:48.644015 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 13:38:48.647730 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 13:38:48.650864 0 10 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
5418 13:38:48.657746 0 10 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5419 13:38:48.660566 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5420 13:38:48.663980 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 13:38:48.671046 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 13:38:48.673766 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 13:38:48.677083 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 13:38:48.683967 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 13:38:48.687589 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5426 13:38:48.690738 0 11 20 | B1->B0 | 2828 4545 | 1 0 | (0 0) (0 0)
5427 13:38:48.697464 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5428 13:38:48.700488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 13:38:48.704159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 13:38:48.710346 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 13:38:48.714043 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 13:38:48.717057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 13:38:48.724115 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5434 13:38:48.727425 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 13:38:48.730676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 13:38:48.737052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 13:38:48.740417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 13:38:48.743956 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 13:38:48.746945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 13:38:48.753642 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 13:38:48.757411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 13:38:48.760285 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 13:38:48.766920 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 13:38:48.770022 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 13:38:48.773321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 13:38:48.780425 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 13:38:48.783769 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 13:38:48.786898 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 13:38:48.793728 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5450 13:38:48.796741 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5451 13:38:48.799934 Total UI for P1: 0, mck2ui 16
5452 13:38:48.803626 best dqsien dly found for B0: ( 0, 14, 16)
5453 13:38:48.806734 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5454 13:38:48.813580 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5455 13:38:48.813666 Total UI for P1: 0, mck2ui 16
5456 13:38:48.819828 best dqsien dly found for B1: ( 0, 14, 22)
5457 13:38:48.823445 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5458 13:38:48.826455 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5459 13:38:48.826537
5460 13:38:48.830000 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5461 13:38:48.832947 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5462 13:38:48.836737 [Gating] SW calibration Done
5463 13:38:48.836818 ==
5464 13:38:48.840408 Dram Type= 6, Freq= 0, CH_1, rank 0
5465 13:38:48.843012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5466 13:38:48.843095 ==
5467 13:38:48.846602 RX Vref Scan: 0
5468 13:38:48.846682
5469 13:38:48.846745 RX Vref 0 -> 0, step: 1
5470 13:38:48.849750
5471 13:38:48.849830 RX Delay -80 -> 252, step: 8
5472 13:38:48.856574 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5473 13:38:48.859719 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5474 13:38:48.862912 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5475 13:38:48.866497 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5476 13:38:48.869930 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5477 13:38:48.872948 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5478 13:38:48.879501 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5479 13:38:48.883145 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5480 13:38:48.886314 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5481 13:38:48.889819 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5482 13:38:48.893200 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5483 13:38:48.899599 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5484 13:38:48.902927 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5485 13:38:48.906080 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5486 13:38:48.909120 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5487 13:38:48.912840 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5488 13:38:48.912923 ==
5489 13:38:48.915915 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 13:38:48.922434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5491 13:38:48.922521 ==
5492 13:38:48.922584 DQS Delay:
5493 13:38:48.926025 DQS0 = 0, DQS1 = 0
5494 13:38:48.926107 DQM Delay:
5495 13:38:48.929174 DQM0 = 94, DQM1 = 86
5496 13:38:48.929255 DQ Delay:
5497 13:38:48.932686 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5498 13:38:48.935742 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5499 13:38:48.939439 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5500 13:38:48.942340 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =95
5501 13:38:48.942421
5502 13:38:48.942485
5503 13:38:48.942543 ==
5504 13:38:48.945894 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 13:38:48.949078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 13:38:48.949159 ==
5507 13:38:48.949222
5508 13:38:48.949281
5509 13:38:48.952573 TX Vref Scan disable
5510 13:38:48.955942 == TX Byte 0 ==
5511 13:38:48.958878 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5512 13:38:48.962798 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5513 13:38:48.965581 == TX Byte 1 ==
5514 13:38:48.969321 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5515 13:38:48.972395 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5516 13:38:48.972476 ==
5517 13:38:48.975894 Dram Type= 6, Freq= 0, CH_1, rank 0
5518 13:38:48.979378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5519 13:38:48.982423 ==
5520 13:38:48.982504
5521 13:38:48.982567
5522 13:38:48.982625 TX Vref Scan disable
5523 13:38:48.986030 == TX Byte 0 ==
5524 13:38:48.989164 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5525 13:38:48.996193 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5526 13:38:48.996301 == TX Byte 1 ==
5527 13:38:48.999145 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5528 13:38:49.005830 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5529 13:38:49.005930
5530 13:38:49.005993 [DATLAT]
5531 13:38:49.006054 Freq=933, CH1 RK0
5532 13:38:49.006111
5533 13:38:49.009047 DATLAT Default: 0xd
5534 13:38:49.009152 0, 0xFFFF, sum = 0
5535 13:38:49.012291 1, 0xFFFF, sum = 0
5536 13:38:49.012394 2, 0xFFFF, sum = 0
5537 13:38:49.015481 3, 0xFFFF, sum = 0
5538 13:38:49.019325 4, 0xFFFF, sum = 0
5539 13:38:49.019437 5, 0xFFFF, sum = 0
5540 13:38:49.022271 6, 0xFFFF, sum = 0
5541 13:38:49.022350 7, 0xFFFF, sum = 0
5542 13:38:49.025807 8, 0xFFFF, sum = 0
5543 13:38:49.025882 9, 0xFFFF, sum = 0
5544 13:38:49.028854 10, 0x0, sum = 1
5545 13:38:49.028931 11, 0x0, sum = 2
5546 13:38:49.031940 12, 0x0, sum = 3
5547 13:38:49.032015 13, 0x0, sum = 4
5548 13:38:49.032075 best_step = 11
5549 13:38:49.032133
5550 13:38:49.035636 ==
5551 13:38:49.038617 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 13:38:49.042164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5553 13:38:49.042240 ==
5554 13:38:49.042303 RX Vref Scan: 1
5555 13:38:49.042361
5556 13:38:49.045260 RX Vref 0 -> 0, step: 1
5557 13:38:49.045347
5558 13:38:49.048793 RX Delay -69 -> 252, step: 4
5559 13:38:49.048868
5560 13:38:49.051850 Set Vref, RX VrefLevel [Byte0]: 55
5561 13:38:49.055502 [Byte1]: 48
5562 13:38:49.055583
5563 13:38:49.058568 Final RX Vref Byte 0 = 55 to rank0
5564 13:38:49.062159 Final RX Vref Byte 1 = 48 to rank0
5565 13:38:49.065198 Final RX Vref Byte 0 = 55 to rank1
5566 13:38:49.068383 Final RX Vref Byte 1 = 48 to rank1==
5567 13:38:49.072050 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 13:38:49.078540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5569 13:38:49.078621 ==
5570 13:38:49.078684 DQS Delay:
5571 13:38:49.078743 DQS0 = 0, DQS1 = 0
5572 13:38:49.081731 DQM Delay:
5573 13:38:49.081811 DQM0 = 94, DQM1 = 88
5574 13:38:49.085182 DQ Delay:
5575 13:38:49.088241 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5576 13:38:49.091508 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5577 13:38:49.094901 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5578 13:38:49.098613 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5579 13:38:49.098695
5580 13:38:49.098757
5581 13:38:49.104820 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5582 13:38:49.107863 CH1 RK0: MR19=505, MR18=3737
5583 13:38:49.114503 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5584 13:38:49.114588
5585 13:38:49.117781 ----->DramcWriteLeveling(PI) begin...
5586 13:38:49.117864 ==
5587 13:38:49.120978 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 13:38:49.124496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5589 13:38:49.124577 ==
5590 13:38:49.127858 Write leveling (Byte 0): 25 => 25
5591 13:38:49.130928 Write leveling (Byte 1): 26 => 26
5592 13:38:49.134540 DramcWriteLeveling(PI) end<-----
5593 13:38:49.134620
5594 13:38:49.134683 ==
5595 13:38:49.137707 Dram Type= 6, Freq= 0, CH_1, rank 1
5596 13:38:49.141270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5597 13:38:49.141392 ==
5598 13:38:49.144355 [Gating] SW mode calibration
5599 13:38:49.151034 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5600 13:38:49.157436 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5601 13:38:49.160993 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 13:38:49.167727 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 13:38:49.170616 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 13:38:49.174231 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5605 13:38:49.181057 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
5606 13:38:49.184063 0 10 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5607 13:38:49.187577 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 13:38:49.194153 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 13:38:49.197359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 13:38:49.200463 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 13:38:49.207446 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 13:38:49.210435 0 11 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5613 13:38:49.213526 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5614 13:38:49.220463 0 11 20 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
5615 13:38:49.223373 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5616 13:38:49.227007 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 13:38:49.233521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 13:38:49.236916 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 13:38:49.240185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 13:38:49.246842 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 13:38:49.250357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5622 13:38:49.253509 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5623 13:38:49.260191 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5624 13:38:49.263315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 13:38:49.266934 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 13:38:49.272905 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 13:38:49.276155 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 13:38:49.279915 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 13:38:49.286894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 13:38:49.289926 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 13:38:49.292978 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 13:38:49.299548 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 13:38:49.302612 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 13:38:49.306160 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 13:38:49.313049 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 13:38:49.316027 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 13:38:49.319329 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5638 13:38:49.322927 Total UI for P1: 0, mck2ui 16
5639 13:38:49.326221 best dqsien dly found for B0: ( 0, 14, 14)
5640 13:38:49.329597 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 13:38:49.333001 Total UI for P1: 0, mck2ui 16
5642 13:38:49.336035 best dqsien dly found for B1: ( 0, 14, 16)
5643 13:38:49.342878 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5644 13:38:49.345754 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5645 13:38:49.345836
5646 13:38:49.349467 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5647 13:38:49.352442 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5648 13:38:49.356045 [Gating] SW calibration Done
5649 13:38:49.356126 ==
5650 13:38:49.359053 Dram Type= 6, Freq= 0, CH_1, rank 1
5651 13:38:49.362458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5652 13:38:49.362540 ==
5653 13:38:49.366187 RX Vref Scan: 0
5654 13:38:49.366269
5655 13:38:49.366333 RX Vref 0 -> 0, step: 1
5656 13:38:49.366392
5657 13:38:49.369069 RX Delay -80 -> 252, step: 8
5658 13:38:49.372703 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5659 13:38:49.379428 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5660 13:38:49.382472 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5661 13:38:49.386073 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5662 13:38:49.389229 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5663 13:38:49.392998 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5664 13:38:49.396066 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5665 13:38:49.399012 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5666 13:38:49.405693 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5667 13:38:49.409358 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5668 13:38:49.412418 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5669 13:38:49.416043 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5670 13:38:49.418964 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5671 13:38:49.425613 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5672 13:38:49.429046 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5673 13:38:49.432170 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5674 13:38:49.432252 ==
5675 13:38:49.435577 Dram Type= 6, Freq= 0, CH_1, rank 1
5676 13:38:49.439016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5677 13:38:49.439099 ==
5678 13:38:49.442235 DQS Delay:
5679 13:38:49.442316 DQS0 = 0, DQS1 = 0
5680 13:38:49.445606 DQM Delay:
5681 13:38:49.445688 DQM0 = 97, DQM1 = 88
5682 13:38:49.445752 DQ Delay:
5683 13:38:49.448935 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5684 13:38:49.452298 DQ4 =99, DQ5 =107, DQ6 =103, DQ7 =91
5685 13:38:49.455311 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5686 13:38:49.458951 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =99
5687 13:38:49.459033
5688 13:38:49.462142
5689 13:38:49.462222 ==
5690 13:38:49.465576 Dram Type= 6, Freq= 0, CH_1, rank 1
5691 13:38:49.468693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5692 13:38:49.468775 ==
5693 13:38:49.468838
5694 13:38:49.468897
5695 13:38:49.472217 TX Vref Scan disable
5696 13:38:49.472298 == TX Byte 0 ==
5697 13:38:49.478932 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5698 13:38:49.482036 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5699 13:38:49.482118 == TX Byte 1 ==
5700 13:38:49.488597 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5701 13:38:49.491670 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5702 13:38:49.491748 ==
5703 13:38:49.495339 Dram Type= 6, Freq= 0, CH_1, rank 1
5704 13:38:49.498515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5705 13:38:49.498597 ==
5706 13:38:49.498661
5707 13:38:49.498721
5708 13:38:49.501584 TX Vref Scan disable
5709 13:38:49.505177 == TX Byte 0 ==
5710 13:38:49.508847 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5711 13:38:49.511917 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5712 13:38:49.515163 == TX Byte 1 ==
5713 13:38:49.518193 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 13:38:49.521860 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 13:38:49.521942
5716 13:38:49.524875 [DATLAT]
5717 13:38:49.524955 Freq=933, CH1 RK1
5718 13:38:49.525019
5719 13:38:49.528644 DATLAT Default: 0xb
5720 13:38:49.528725 0, 0xFFFF, sum = 0
5721 13:38:49.531608 1, 0xFFFF, sum = 0
5722 13:38:49.531697 2, 0xFFFF, sum = 0
5723 13:38:49.535226 3, 0xFFFF, sum = 0
5724 13:38:49.535312 4, 0xFFFF, sum = 0
5725 13:38:49.538198 5, 0xFFFF, sum = 0
5726 13:38:49.538280 6, 0xFFFF, sum = 0
5727 13:38:49.541815 7, 0xFFFF, sum = 0
5728 13:38:49.541901 8, 0xFFFF, sum = 0
5729 13:38:49.545346 9, 0xFFFF, sum = 0
5730 13:38:49.545428 10, 0x0, sum = 1
5731 13:38:49.548569 11, 0x0, sum = 2
5732 13:38:49.548651 12, 0x0, sum = 3
5733 13:38:49.552116 13, 0x0, sum = 4
5734 13:38:49.552198 best_step = 11
5735 13:38:49.552261
5736 13:38:49.552319 ==
5737 13:38:49.555291 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 13:38:49.561359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5739 13:38:49.561441 ==
5740 13:38:49.561505 RX Vref Scan: 0
5741 13:38:49.561565
5742 13:38:49.564871 RX Vref 0 -> 0, step: 1
5743 13:38:49.564951
5744 13:38:49.568003 RX Delay -69 -> 252, step: 4
5745 13:38:49.571458 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5746 13:38:49.574551 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5747 13:38:49.581059 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5748 13:38:49.584783 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5749 13:38:49.587801 iDelay=203, Bit 4, Center 98 (3 ~ 194) 192
5750 13:38:49.591446 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5751 13:38:49.594530 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5752 13:38:49.598095 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5753 13:38:49.604724 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5754 13:38:49.607781 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5755 13:38:49.611350 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5756 13:38:49.614781 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5757 13:38:49.618051 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5758 13:38:49.624752 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5759 13:38:49.627803 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5760 13:38:49.631318 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5761 13:38:49.631430 ==
5762 13:38:49.634326 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 13:38:49.637521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5764 13:38:49.637603 ==
5765 13:38:49.641073 DQS Delay:
5766 13:38:49.641154 DQS0 = 0, DQS1 = 0
5767 13:38:49.641217 DQM Delay:
5768 13:38:49.644144 DQM0 = 96, DQM1 = 87
5769 13:38:49.644225 DQ Delay:
5770 13:38:49.647573 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5771 13:38:49.650700 DQ4 =98, DQ5 =108, DQ6 =104, DQ7 =96
5772 13:38:49.654548 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5773 13:38:49.657433 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5774 13:38:49.657514
5775 13:38:49.657577
5776 13:38:49.667520 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5777 13:38:49.671047 CH1 RK1: MR19=505, MR18=1E1E
5778 13:38:49.674192 CH1_RK1: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5779 13:38:49.677284 [RxdqsGatingPostProcess] freq 933
5780 13:38:49.683803 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5781 13:38:49.687099 Pre-setting of DQS Precalculation
5782 13:38:49.690471 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5783 13:38:49.700360 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5784 13:38:49.707066 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5785 13:38:49.707155
5786 13:38:49.707219
5787 13:38:49.710353 [Calibration Summary] 1866 Mbps
5788 13:38:49.710434 CH 0, Rank 0
5789 13:38:49.713973 SW Impedance : PASS
5790 13:38:49.716819 DUTY Scan : NO K
5791 13:38:49.716900 ZQ Calibration : PASS
5792 13:38:49.720468 Jitter Meter : NO K
5793 13:38:49.720549 CBT Training : PASS
5794 13:38:49.723573 Write leveling : PASS
5795 13:38:49.727149 RX DQS gating : PASS
5796 13:38:49.727258 RX DQ/DQS(RDDQC) : PASS
5797 13:38:49.730316 TX DQ/DQS : PASS
5798 13:38:49.733325 RX DATLAT : PASS
5799 13:38:49.733415 RX DQ/DQS(Engine): PASS
5800 13:38:49.737001 TX OE : NO K
5801 13:38:49.737077 All Pass.
5802 13:38:49.737149
5803 13:38:49.740159 CH 0, Rank 1
5804 13:38:49.740262 SW Impedance : PASS
5805 13:38:49.743544 DUTY Scan : NO K
5806 13:38:49.746581 ZQ Calibration : PASS
5807 13:38:49.746681 Jitter Meter : NO K
5808 13:38:49.749656 CBT Training : PASS
5809 13:38:49.753284 Write leveling : PASS
5810 13:38:49.753426 RX DQS gating : PASS
5811 13:38:49.756426 RX DQ/DQS(RDDQC) : PASS
5812 13:38:49.760165 TX DQ/DQS : PASS
5813 13:38:49.760265 RX DATLAT : PASS
5814 13:38:49.763476 RX DQ/DQS(Engine): PASS
5815 13:38:49.766408 TX OE : NO K
5816 13:38:49.766508 All Pass.
5817 13:38:49.766597
5818 13:38:49.766686 CH 1, Rank 0
5819 13:38:49.769782 SW Impedance : PASS
5820 13:38:49.772873 DUTY Scan : NO K
5821 13:38:49.772971 ZQ Calibration : PASS
5822 13:38:49.776653 Jitter Meter : NO K
5823 13:38:49.779658 CBT Training : PASS
5824 13:38:49.779761 Write leveling : PASS
5825 13:38:49.783503 RX DQS gating : PASS
5826 13:38:49.783584 RX DQ/DQS(RDDQC) : PASS
5827 13:38:49.786339 TX DQ/DQS : PASS
5828 13:38:49.789442 RX DATLAT : PASS
5829 13:38:49.789517 RX DQ/DQS(Engine): PASS
5830 13:38:49.792915 TX OE : NO K
5831 13:38:49.792989 All Pass.
5832 13:38:49.793059
5833 13:38:49.796218 CH 1, Rank 1
5834 13:38:49.796318 SW Impedance : PASS
5835 13:38:49.799677 DUTY Scan : NO K
5836 13:38:49.802852 ZQ Calibration : PASS
5837 13:38:49.802922 Jitter Meter : NO K
5838 13:38:49.806438 CBT Training : PASS
5839 13:38:49.809151 Write leveling : PASS
5840 13:38:49.809255 RX DQS gating : PASS
5841 13:38:49.812708 RX DQ/DQS(RDDQC) : PASS
5842 13:38:49.815835 TX DQ/DQS : PASS
5843 13:38:49.815911 RX DATLAT : PASS
5844 13:38:49.819416 RX DQ/DQS(Engine): PASS
5845 13:38:49.822992 TX OE : NO K
5846 13:38:49.823069 All Pass.
5847 13:38:49.823136
5848 13:38:49.826157 DramC Write-DBI off
5849 13:38:49.826231 PER_BANK_REFRESH: Hybrid Mode
5850 13:38:49.829273 TX_TRACKING: ON
5851 13:38:49.836228 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5852 13:38:49.842326 [FAST_K] Save calibration result to emmc
5853 13:38:49.845978 dramc_set_vcore_voltage set vcore to 650000
5854 13:38:49.846063 Read voltage for 400, 6
5855 13:38:49.849033 Vio18 = 0
5856 13:38:49.849110 Vcore = 650000
5857 13:38:49.849173 Vdram = 0
5858 13:38:49.852763 Vddq = 0
5859 13:38:49.852849 Vmddr = 0
5860 13:38:49.855701 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5861 13:38:49.862404 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5862 13:38:49.865513 MEM_TYPE=3, freq_sel=20
5863 13:38:49.869302 sv_algorithm_assistance_LP4_800
5864 13:38:49.872223 ============ PULL DRAM RESETB DOWN ============
5865 13:38:49.875392 ========== PULL DRAM RESETB DOWN end =========
5866 13:38:49.882227 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5867 13:38:49.885324 ===================================
5868 13:38:49.885427 LPDDR4 DRAM CONFIGURATION
5869 13:38:49.888823 ===================================
5870 13:38:49.891998 EX_ROW_EN[0] = 0x0
5871 13:38:49.892076 EX_ROW_EN[1] = 0x0
5872 13:38:49.895562 LP4Y_EN = 0x0
5873 13:38:49.895636 WORK_FSP = 0x0
5874 13:38:49.898546 WL = 0x2
5875 13:38:49.898621 RL = 0x2
5876 13:38:49.902160 BL = 0x2
5877 13:38:49.905558 RPST = 0x0
5878 13:38:49.905660 RD_PRE = 0x0
5879 13:38:49.908473 WR_PRE = 0x1
5880 13:38:49.908576 WR_PST = 0x0
5881 13:38:49.911838 DBI_WR = 0x0
5882 13:38:49.911936 DBI_RD = 0x0
5883 13:38:49.915449 OTF = 0x1
5884 13:38:49.918555 ===================================
5885 13:38:49.921924 ===================================
5886 13:38:49.922005 ANA top config
5887 13:38:49.925113 ===================================
5888 13:38:49.928514 DLL_ASYNC_EN = 0
5889 13:38:49.931645 ALL_SLAVE_EN = 1
5890 13:38:49.931747 NEW_RANK_MODE = 1
5891 13:38:49.935310 DLL_IDLE_MODE = 1
5892 13:38:49.938330 LP45_APHY_COMB_EN = 1
5893 13:38:49.941893 TX_ODT_DIS = 1
5894 13:38:49.942012 NEW_8X_MODE = 1
5895 13:38:49.945106 ===================================
5896 13:38:49.948987 ===================================
5897 13:38:49.951712 data_rate = 800
5898 13:38:49.954840 CKR = 1
5899 13:38:49.958692 DQ_P2S_RATIO = 4
5900 13:38:49.961736 ===================================
5901 13:38:49.964699 CA_P2S_RATIO = 4
5902 13:38:49.968493 DQ_CA_OPEN = 0
5903 13:38:49.971511 DQ_SEMI_OPEN = 1
5904 13:38:49.971614 CA_SEMI_OPEN = 1
5905 13:38:49.975143 CA_FULL_RATE = 0
5906 13:38:49.978163 DQ_CKDIV4_EN = 0
5907 13:38:49.981731 CA_CKDIV4_EN = 1
5908 13:38:49.984814 CA_PREDIV_EN = 0
5909 13:38:49.988061 PH8_DLY = 0
5910 13:38:49.988140 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5911 13:38:49.991573 DQ_AAMCK_DIV = 0
5912 13:38:49.994571 CA_AAMCK_DIV = 0
5913 13:38:49.998193 CA_ADMCK_DIV = 4
5914 13:38:50.001235 DQ_TRACK_CA_EN = 0
5915 13:38:50.004873 CA_PICK = 800
5916 13:38:50.004975 CA_MCKIO = 400
5917 13:38:50.008035 MCKIO_SEMI = 400
5918 13:38:50.011011 PLL_FREQ = 3016
5919 13:38:50.014796 DQ_UI_PI_RATIO = 32
5920 13:38:50.018334 CA_UI_PI_RATIO = 32
5921 13:38:50.021276 ===================================
5922 13:38:50.024398 ===================================
5923 13:38:50.027808 memory_type:LPDDR4
5924 13:38:50.027893 GP_NUM : 10
5925 13:38:50.031174 SRAM_EN : 1
5926 13:38:50.034715 MD32_EN : 0
5927 13:38:50.037957 ===================================
5928 13:38:50.038044 [ANA_INIT] >>>>>>>>>>>>>>
5929 13:38:50.041162 <<<<<< [CONFIGURE PHASE]: ANA_TX
5930 13:38:50.044123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5931 13:38:50.047705 ===================================
5932 13:38:50.050749 data_rate = 800,PCW = 0X7400
5933 13:38:50.054369 ===================================
5934 13:38:50.057479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5935 13:38:50.064192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5936 13:38:50.073757 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5937 13:38:50.080486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5938 13:38:50.084013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5939 13:38:50.087041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5940 13:38:50.087128 [ANA_INIT] flow start
5941 13:38:50.090619 [ANA_INIT] PLL >>>>>>>>
5942 13:38:50.093722 [ANA_INIT] PLL <<<<<<<<
5943 13:38:50.093808 [ANA_INIT] MIDPI >>>>>>>>
5944 13:38:50.097381 [ANA_INIT] MIDPI <<<<<<<<
5945 13:38:50.100380 [ANA_INIT] DLL >>>>>>>>
5946 13:38:50.100491 [ANA_INIT] flow end
5947 13:38:50.107215 ============ LP4 DIFF to SE enter ============
5948 13:38:50.110257 ============ LP4 DIFF to SE exit ============
5949 13:38:50.113509 [ANA_INIT] <<<<<<<<<<<<<
5950 13:38:50.116673 [Flow] Enable top DCM control >>>>>
5951 13:38:50.120240 [Flow] Enable top DCM control <<<<<
5952 13:38:50.120345 Enable DLL master slave shuffle
5953 13:38:50.126814 ==============================================================
5954 13:38:50.130324 Gating Mode config
5955 13:38:50.133498 ==============================================================
5956 13:38:50.136496 Config description:
5957 13:38:50.147091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5958 13:38:50.153536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5959 13:38:50.156917 SELPH_MODE 0: By rank 1: By Phase
5960 13:38:50.163073 ==============================================================
5961 13:38:50.166704 GAT_TRACK_EN = 0
5962 13:38:50.169710 RX_GATING_MODE = 2
5963 13:38:50.173469 RX_GATING_TRACK_MODE = 2
5964 13:38:50.176695 SELPH_MODE = 1
5965 13:38:50.176772 PICG_EARLY_EN = 1
5966 13:38:50.179783 VALID_LAT_VALUE = 1
5967 13:38:50.186416 ==============================================================
5968 13:38:50.189848 Enter into Gating configuration >>>>
5969 13:38:50.192963 Exit from Gating configuration <<<<
5970 13:38:50.196786 Enter into DVFS_PRE_config >>>>>
5971 13:38:50.206549 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5972 13:38:50.209751 Exit from DVFS_PRE_config <<<<<
5973 13:38:50.212780 Enter into PICG configuration >>>>
5974 13:38:50.216466 Exit from PICG configuration <<<<
5975 13:38:50.219456 [RX_INPUT] configuration >>>>>
5976 13:38:50.223093 [RX_INPUT] configuration <<<<<
5977 13:38:50.226151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5978 13:38:50.232643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5979 13:38:50.239386 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5980 13:38:50.246137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5981 13:38:50.252738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5982 13:38:50.259222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5983 13:38:50.262666 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5984 13:38:50.265663 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5985 13:38:50.269094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5986 13:38:50.275773 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5987 13:38:50.278859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5988 13:38:50.282012 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5989 13:38:50.285727 ===================================
5990 13:38:50.289145 LPDDR4 DRAM CONFIGURATION
5991 13:38:50.292227 ===================================
5992 13:38:50.292330 EX_ROW_EN[0] = 0x0
5993 13:38:50.295359 EX_ROW_EN[1] = 0x0
5994 13:38:50.295460 LP4Y_EN = 0x0
5995 13:38:50.299130 WORK_FSP = 0x0
5996 13:38:50.301986 WL = 0x2
5997 13:38:50.302088 RL = 0x2
5998 13:38:50.305688 BL = 0x2
5999 13:38:50.305790 RPST = 0x0
6000 13:38:50.308555 RD_PRE = 0x0
6001 13:38:50.308649 WR_PRE = 0x1
6002 13:38:50.312284 WR_PST = 0x0
6003 13:38:50.312390 DBI_WR = 0x0
6004 13:38:50.315348 DBI_RD = 0x0
6005 13:38:50.315428 OTF = 0x1
6006 13:38:50.318959 ===================================
6007 13:38:50.321991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6008 13:38:50.328620 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6009 13:38:50.332243 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6010 13:38:50.335088 ===================================
6011 13:38:50.338571 LPDDR4 DRAM CONFIGURATION
6012 13:38:50.341790 ===================================
6013 13:38:50.341869 EX_ROW_EN[0] = 0x10
6014 13:38:50.345392 EX_ROW_EN[1] = 0x0
6015 13:38:50.345473 LP4Y_EN = 0x0
6016 13:38:50.348483 WORK_FSP = 0x0
6017 13:38:50.348564 WL = 0x2
6018 13:38:50.351862 RL = 0x2
6019 13:38:50.355505 BL = 0x2
6020 13:38:50.355587 RPST = 0x0
6021 13:38:50.358610 RD_PRE = 0x0
6022 13:38:50.358692 WR_PRE = 0x1
6023 13:38:50.361613 WR_PST = 0x0
6024 13:38:50.361694 DBI_WR = 0x0
6025 13:38:50.364945 DBI_RD = 0x0
6026 13:38:50.365031 OTF = 0x1
6027 13:38:50.368516 ===================================
6028 13:38:50.375084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6029 13:38:50.378876 nWR fixed to 30
6030 13:38:50.382423 [ModeRegInit_LP4] CH0 RK0
6031 13:38:50.382509 [ModeRegInit_LP4] CH0 RK1
6032 13:38:50.385694 [ModeRegInit_LP4] CH1 RK0
6033 13:38:50.388936 [ModeRegInit_LP4] CH1 RK1
6034 13:38:50.389019 match AC timing 18
6035 13:38:50.395498 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6036 13:38:50.399067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6037 13:38:50.402017 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6038 13:38:50.408869 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6039 13:38:50.412352 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6040 13:38:50.412438 ==
6041 13:38:50.415501 Dram Type= 6, Freq= 0, CH_0, rank 0
6042 13:38:50.418499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6043 13:38:50.418582 ==
6044 13:38:50.425226 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6045 13:38:50.431767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6046 13:38:50.434988 [CA 0] Center 36 (8~64) winsize 57
6047 13:38:50.438513 [CA 1] Center 36 (8~64) winsize 57
6048 13:38:50.441669 [CA 2] Center 36 (8~64) winsize 57
6049 13:38:50.444887 [CA 3] Center 36 (8~64) winsize 57
6050 13:38:50.448494 [CA 4] Center 36 (8~64) winsize 57
6051 13:38:50.451593 [CA 5] Center 36 (8~64) winsize 57
6052 13:38:50.451676
6053 13:38:50.455096 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6054 13:38:50.455179
6055 13:38:50.458189 [CATrainingPosCal] consider 1 rank data
6056 13:38:50.461257 u2DelayCellTimex100 = 270/100 ps
6057 13:38:50.464865 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 13:38:50.467825 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 13:38:50.471218 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6060 13:38:50.474824 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 13:38:50.478358 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 13:38:50.481223 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 13:38:50.481360
6064 13:38:50.484467 CA PerBit enable=1, Macro0, CA PI delay=36
6065 13:38:50.484575
6066 13:38:50.488124 [CBTSetCACLKResult] CA Dly = 36
6067 13:38:50.497143 CS Dly: 1 (0~32)
6068 13:38:50.497260 ==
6069 13:38:50.497378 Dram Type= 6, Freq= 0, CH_0, rank 1
6070 13:38:50.498151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6071 13:38:50.498225 ==
6072 13:38:50.504814 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6073 13:38:50.511395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6074 13:38:50.514319 [CA 0] Center 36 (8~64) winsize 57
6075 13:38:50.517627 [CA 1] Center 36 (8~64) winsize 57
6076 13:38:50.517702 [CA 2] Center 36 (8~64) winsize 57
6077 13:38:50.521637 [CA 3] Center 36 (8~64) winsize 57
6078 13:38:50.524512 [CA 4] Center 36 (8~64) winsize 57
6079 13:38:50.527621 [CA 5] Center 36 (8~64) winsize 57
6080 13:38:50.527697
6081 13:38:50.531048 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6082 13:38:50.534155
6083 13:38:50.537692 [CATrainingPosCal] consider 2 rank data
6084 13:38:50.537766 u2DelayCellTimex100 = 270/100 ps
6085 13:38:50.544449 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 13:38:50.547289 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6087 13:38:50.550931 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6088 13:38:50.554087 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 13:38:50.557571 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 13:38:50.560582 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 13:38:50.560658
6092 13:38:50.564234 CA PerBit enable=1, Macro0, CA PI delay=36
6093 13:38:50.564308
6094 13:38:50.567228 [CBTSetCACLKResult] CA Dly = 36
6095 13:38:50.570973 CS Dly: 1 (0~32)
6096 13:38:50.571068
6097 13:38:50.573787 ----->DramcWriteLeveling(PI) begin...
6098 13:38:50.573862 ==
6099 13:38:50.577208 Dram Type= 6, Freq= 0, CH_0, rank 0
6100 13:38:50.580736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6101 13:38:50.580819 ==
6102 13:38:50.583543 Write leveling (Byte 0): 32 => 0
6103 13:38:50.587250 Write leveling (Byte 1): 32 => 0
6104 13:38:50.590187 DramcWriteLeveling(PI) end<-----
6105 13:38:50.590268
6106 13:38:50.590332 ==
6107 13:38:50.593773 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 13:38:50.596880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 13:38:50.596967 ==
6110 13:38:50.600425 [Gating] SW mode calibration
6111 13:38:50.606931 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6112 13:38:50.613572 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6113 13:38:50.617178 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6114 13:38:50.620022 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6115 13:38:50.626528 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6116 13:38:50.629935 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6117 13:38:50.633015 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6118 13:38:50.639637 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6119 13:38:50.643290 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6120 13:38:50.646221 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6121 13:38:50.652872 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6122 13:38:50.656516 Total UI for P1: 0, mck2ui 16
6123 13:38:50.659564 best dqsien dly found for B0: ( 0, 10, 16)
6124 13:38:50.663261 Total UI for P1: 0, mck2ui 16
6125 13:38:50.666117 best dqsien dly found for B1: ( 0, 10, 16)
6126 13:38:50.669751 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6127 13:38:50.672823 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6128 13:38:50.672901
6129 13:38:50.675915 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6130 13:38:50.679582 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6131 13:38:50.683016 [Gating] SW calibration Done
6132 13:38:50.683094 ==
6133 13:38:50.686278 Dram Type= 6, Freq= 0, CH_0, rank 0
6134 13:38:50.689590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6135 13:38:50.689677 ==
6136 13:38:50.692659 RX Vref Scan: 0
6137 13:38:50.692734
6138 13:38:50.695723 RX Vref 0 -> 0, step: 1
6139 13:38:50.695800
6140 13:38:50.695892 RX Delay -410 -> 252, step: 16
6141 13:38:50.703046 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6142 13:38:50.706046 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6143 13:38:50.709962 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6144 13:38:50.713184 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6145 13:38:50.719502 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6146 13:38:50.722575 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6147 13:38:50.726391 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6148 13:38:50.732486 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6149 13:38:50.735857 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6150 13:38:50.739218 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6151 13:38:50.742685 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6152 13:38:50.749367 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6153 13:38:50.752401 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6154 13:38:50.755447 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6155 13:38:50.758997 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6156 13:38:50.765690 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6157 13:38:50.765774 ==
6158 13:38:50.769265 Dram Type= 6, Freq= 0, CH_0, rank 0
6159 13:38:50.772303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6160 13:38:50.772386 ==
6161 13:38:50.772451 DQS Delay:
6162 13:38:50.775297 DQS0 = 51, DQS1 = 59
6163 13:38:50.775383 DQM Delay:
6164 13:38:50.778775 DQM0 = 12, DQM1 = 12
6165 13:38:50.778855 DQ Delay:
6166 13:38:50.782044 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6167 13:38:50.785608 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6168 13:38:50.788820 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6169 13:38:50.791784 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6170 13:38:50.791866
6171 13:38:50.791933
6172 13:38:50.792011 ==
6173 13:38:50.795160 Dram Type= 6, Freq= 0, CH_0, rank 0
6174 13:38:50.798561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6175 13:38:50.798644 ==
6176 13:38:50.798707
6177 13:38:50.802095
6178 13:38:50.802177 TX Vref Scan disable
6179 13:38:50.805076 == TX Byte 0 ==
6180 13:38:50.808651 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6181 13:38:50.811664 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6182 13:38:50.815282 == TX Byte 1 ==
6183 13:38:50.818260 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6184 13:38:50.821935 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6185 13:38:50.822018 ==
6186 13:38:50.824837 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 13:38:50.831306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6188 13:38:50.831393 ==
6189 13:38:50.831457
6190 13:38:50.831516
6191 13:38:50.831574 TX Vref Scan disable
6192 13:38:50.834730 == TX Byte 0 ==
6193 13:38:50.838291 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6194 13:38:50.841951 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6195 13:38:50.844667 == TX Byte 1 ==
6196 13:38:50.848005 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 13:38:50.851804 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 13:38:50.851911
6199 13:38:50.854851 [DATLAT]
6200 13:38:50.854931 Freq=400, CH0 RK0
6201 13:38:50.854995
6202 13:38:50.858307 DATLAT Default: 0xf
6203 13:38:50.858388 0, 0xFFFF, sum = 0
6204 13:38:50.861263 1, 0xFFFF, sum = 0
6205 13:38:50.861401 2, 0xFFFF, sum = 0
6206 13:38:50.864935 3, 0xFFFF, sum = 0
6207 13:38:50.865018 4, 0xFFFF, sum = 0
6208 13:38:50.868048 5, 0xFFFF, sum = 0
6209 13:38:50.868131 6, 0xFFFF, sum = 0
6210 13:38:50.871647 7, 0xFFFF, sum = 0
6211 13:38:50.871730 8, 0xFFFF, sum = 0
6212 13:38:50.874732 9, 0xFFFF, sum = 0
6213 13:38:50.878419 10, 0xFFFF, sum = 0
6214 13:38:50.878502 11, 0xFFFF, sum = 0
6215 13:38:50.881467 12, 0x0, sum = 1
6216 13:38:50.881550 13, 0x0, sum = 2
6217 13:38:50.881614 14, 0x0, sum = 3
6218 13:38:50.884534 15, 0x0, sum = 4
6219 13:38:50.884616 best_step = 13
6220 13:38:50.884686
6221 13:38:50.888105 ==
6222 13:38:50.891060 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 13:38:50.894523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6224 13:38:50.894605 ==
6225 13:38:50.894713 RX Vref Scan: 1
6226 13:38:50.894778
6227 13:38:50.897931 RX Vref 0 -> 0, step: 1
6228 13:38:50.898037
6229 13:38:50.901242 RX Delay -359 -> 252, step: 8
6230 13:38:50.901373
6231 13:38:50.904752 Set Vref, RX VrefLevel [Byte0]: 50
6232 13:38:50.907676 [Byte1]: 55
6233 13:38:50.911205
6234 13:38:50.911315 Final RX Vref Byte 0 = 50 to rank0
6235 13:38:50.914936 Final RX Vref Byte 1 = 55 to rank0
6236 13:38:50.917814 Final RX Vref Byte 0 = 50 to rank1
6237 13:38:50.921409 Final RX Vref Byte 1 = 55 to rank1==
6238 13:38:50.924926 Dram Type= 6, Freq= 0, CH_0, rank 0
6239 13:38:50.931203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6240 13:38:50.931287 ==
6241 13:38:50.931352 DQS Delay:
6242 13:38:50.934276 DQS0 = 52, DQS1 = 64
6243 13:38:50.934382 DQM Delay:
6244 13:38:50.934474 DQM0 = 9, DQM1 = 13
6245 13:38:50.937831 DQ Delay:
6246 13:38:50.941259 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6247 13:38:50.941381 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6248 13:38:50.944284 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6249 13:38:50.947918 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6250 13:38:50.948030
6251 13:38:50.951032
6252 13:38:50.957774 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b9b, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6253 13:38:50.960908 CH0 RK0: MR19=C0C, MR18=9B9B
6254 13:38:50.967266 CH0_RK0: MR19=0xC0C, MR18=0x9B9B, DQSOSC=390, MR23=63, INC=388, DEC=258
6255 13:38:50.967374 ==
6256 13:38:50.971110 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 13:38:50.973917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 13:38:50.974000 ==
6259 13:38:50.977429 [Gating] SW mode calibration
6260 13:38:50.984178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6261 13:38:50.990432 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6262 13:38:50.994116 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 13:38:50.997055 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 13:38:51.004076 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 13:38:51.006924 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6266 13:38:51.010328 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 13:38:51.017271 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 13:38:51.020237 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 13:38:51.023677 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6270 13:38:51.030060 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 13:38:51.030144 Total UI for P1: 0, mck2ui 16
6272 13:38:51.036513 best dqsien dly found for B0: ( 0, 10, 16)
6273 13:38:51.036622 Total UI for P1: 0, mck2ui 16
6274 13:38:51.043072 best dqsien dly found for B1: ( 0, 10, 16)
6275 13:38:51.046439 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6276 13:38:51.049922 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6277 13:38:51.050004
6278 13:38:51.053060 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6279 13:38:51.056772 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6280 13:38:51.059658 [Gating] SW calibration Done
6281 13:38:51.059740 ==
6282 13:38:51.063071 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 13:38:51.066477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6284 13:38:51.066560 ==
6285 13:38:51.069684 RX Vref Scan: 0
6286 13:38:51.069789
6287 13:38:51.069881 RX Vref 0 -> 0, step: 1
6288 13:38:51.073194
6289 13:38:51.073329 RX Delay -410 -> 252, step: 16
6290 13:38:51.079741 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6291 13:38:51.083264 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6292 13:38:51.086332 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6293 13:38:51.089399 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6294 13:38:51.096135 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6295 13:38:51.099664 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6296 13:38:51.103149 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6297 13:38:51.106079 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6298 13:38:51.112806 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6299 13:38:51.116204 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6300 13:38:51.119096 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6301 13:38:51.125785 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6302 13:38:51.129452 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6303 13:38:51.132277 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6304 13:38:51.135805 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6305 13:38:51.142274 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6306 13:38:51.142360 ==
6307 13:38:51.145848 Dram Type= 6, Freq= 0, CH_0, rank 1
6308 13:38:51.149374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6309 13:38:51.149460 ==
6310 13:38:51.149526 DQS Delay:
6311 13:38:51.152248 DQS0 = 43, DQS1 = 59
6312 13:38:51.152386 DQM Delay:
6313 13:38:51.155886 DQM0 = 7, DQM1 = 14
6314 13:38:51.155967 DQ Delay:
6315 13:38:51.158897 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6316 13:38:51.162032 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6317 13:38:51.165633 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6318 13:38:51.169113 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6319 13:38:51.169213
6320 13:38:51.169330
6321 13:38:51.169408 ==
6322 13:38:51.172428 Dram Type= 6, Freq= 0, CH_0, rank 1
6323 13:38:51.175732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6324 13:38:51.175821 ==
6325 13:38:51.175886
6326 13:38:51.175946
6327 13:38:51.178904 TX Vref Scan disable
6328 13:38:51.179013 == TX Byte 0 ==
6329 13:38:51.185474 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6330 13:38:51.189088 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6331 13:38:51.189199 == TX Byte 1 ==
6332 13:38:51.195798 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6333 13:38:51.198835 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6334 13:38:51.198916 ==
6335 13:38:51.201877 Dram Type= 6, Freq= 0, CH_0, rank 1
6336 13:38:51.205487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6337 13:38:51.205563 ==
6338 13:38:51.205627
6339 13:38:51.205686
6340 13:38:51.208428 TX Vref Scan disable
6341 13:38:51.211845 == TX Byte 0 ==
6342 13:38:51.215558 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6343 13:38:51.218506 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6344 13:38:51.218582 == TX Byte 1 ==
6345 13:38:51.225163 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6346 13:38:51.228624 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6347 13:38:51.228710
6348 13:38:51.228809 [DATLAT]
6349 13:38:51.231644 Freq=400, CH0 RK1
6350 13:38:51.231730
6351 13:38:51.231814 DATLAT Default: 0xd
6352 13:38:51.235243 0, 0xFFFF, sum = 0
6353 13:38:51.235328 1, 0xFFFF, sum = 0
6354 13:38:51.238704 2, 0xFFFF, sum = 0
6355 13:38:51.238821 3, 0xFFFF, sum = 0
6356 13:38:51.241802 4, 0xFFFF, sum = 0
6357 13:38:51.241887 5, 0xFFFF, sum = 0
6358 13:38:51.245257 6, 0xFFFF, sum = 0
6359 13:38:51.248430 7, 0xFFFF, sum = 0
6360 13:38:51.248514 8, 0xFFFF, sum = 0
6361 13:38:51.252063 9, 0xFFFF, sum = 0
6362 13:38:51.252171 10, 0xFFFF, sum = 0
6363 13:38:51.255105 11, 0xFFFF, sum = 0
6364 13:38:51.255187 12, 0x0, sum = 1
6365 13:38:51.258687 13, 0x0, sum = 2
6366 13:38:51.258830 14, 0x0, sum = 3
6367 13:38:51.262107 15, 0x0, sum = 4
6368 13:38:51.262189 best_step = 13
6369 13:38:51.262252
6370 13:38:51.262311 ==
6371 13:38:51.264904 Dram Type= 6, Freq= 0, CH_0, rank 1
6372 13:38:51.268644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6373 13:38:51.268726 ==
6374 13:38:51.271556 RX Vref Scan: 0
6375 13:38:51.271645
6376 13:38:51.275100 RX Vref 0 -> 0, step: 1
6377 13:38:51.275180
6378 13:38:51.275244 RX Delay -359 -> 252, step: 8
6379 13:38:51.283835 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6380 13:38:51.286823 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6381 13:38:51.290136 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6382 13:38:51.293900 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6383 13:38:51.300522 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6384 13:38:51.303598 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6385 13:38:51.306672 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6386 13:38:51.310272 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6387 13:38:51.316520 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6388 13:38:51.319869 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6389 13:38:51.323330 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6390 13:38:51.330250 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6391 13:38:51.333538 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6392 13:38:51.336671 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6393 13:38:51.339673 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6394 13:38:51.346629 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6395 13:38:51.346749 ==
6396 13:38:51.350249 Dram Type= 6, Freq= 0, CH_0, rank 1
6397 13:38:51.353159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6398 13:38:51.353242 ==
6399 13:38:51.353343 DQS Delay:
6400 13:38:51.356805 DQS0 = 52, DQS1 = 64
6401 13:38:51.356887 DQM Delay:
6402 13:38:51.359811 DQM0 = 11, DQM1 = 15
6403 13:38:51.359891 DQ Delay:
6404 13:38:51.363093 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6405 13:38:51.366352 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6406 13:38:51.369839 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =4
6407 13:38:51.373558 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6408 13:38:51.373655
6409 13:38:51.373720
6410 13:38:51.380218 [DQSOSCAuto] RK1, (LSB)MR18= 0xc3c3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6411 13:38:51.382968 CH0 RK1: MR19=C0C, MR18=C3C3
6412 13:38:51.389921 CH0_RK1: MR19=0xC0C, MR18=0xC3C3, DQSOSC=385, MR23=63, INC=398, DEC=265
6413 13:38:51.392851 [RxdqsGatingPostProcess] freq 400
6414 13:38:51.399825 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6415 13:38:51.403197 Pre-setting of DQS Precalculation
6416 13:38:51.406233 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6417 13:38:51.406306 ==
6418 13:38:51.409743 Dram Type= 6, Freq= 0, CH_1, rank 0
6419 13:38:51.412698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6420 13:38:51.412780 ==
6421 13:38:51.419251 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6422 13:38:51.426075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6423 13:38:51.429473 [CA 0] Center 36 (8~64) winsize 57
6424 13:38:51.432381 [CA 1] Center 36 (8~64) winsize 57
6425 13:38:51.436107 [CA 2] Center 36 (8~64) winsize 57
6426 13:38:51.439190 [CA 3] Center 36 (8~64) winsize 57
6427 13:38:51.442578 [CA 4] Center 36 (8~64) winsize 57
6428 13:38:51.445818 [CA 5] Center 36 (8~64) winsize 57
6429 13:38:51.445899
6430 13:38:51.448895 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6431 13:38:51.448976
6432 13:38:51.452063 [CATrainingPosCal] consider 1 rank data
6433 13:38:51.455433 u2DelayCellTimex100 = 270/100 ps
6434 13:38:51.459058 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 13:38:51.462048 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6436 13:38:51.465837 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6437 13:38:51.468903 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 13:38:51.472353 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 13:38:51.475505 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 13:38:51.475585
6441 13:38:51.482295 CA PerBit enable=1, Macro0, CA PI delay=36
6442 13:38:51.482381
6443 13:38:51.482465 [CBTSetCACLKResult] CA Dly = 36
6444 13:38:51.485506 CS Dly: 1 (0~32)
6445 13:38:51.485591 ==
6446 13:38:51.488969 Dram Type= 6, Freq= 0, CH_1, rank 1
6447 13:38:51.491864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6448 13:38:51.491950 ==
6449 13:38:51.499054 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6450 13:38:51.505472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6451 13:38:51.508566 [CA 0] Center 36 (8~64) winsize 57
6452 13:38:51.512169 [CA 1] Center 36 (8~64) winsize 57
6453 13:38:51.515081 [CA 2] Center 36 (8~64) winsize 57
6454 13:38:51.515161 [CA 3] Center 36 (8~64) winsize 57
6455 13:38:51.518763 [CA 4] Center 36 (8~64) winsize 57
6456 13:38:51.521797 [CA 5] Center 36 (8~64) winsize 57
6457 13:38:51.521872
6458 13:38:51.525446 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6459 13:38:51.528551
6460 13:38:51.532068 [CATrainingPosCal] consider 2 rank data
6461 13:38:51.532168 u2DelayCellTimex100 = 270/100 ps
6462 13:38:51.538655 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 13:38:51.541719 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6464 13:38:51.545242 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6465 13:38:51.548252 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6466 13:38:51.551748 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 13:38:51.554717 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 13:38:51.554798
6469 13:38:51.558062 CA PerBit enable=1, Macro0, CA PI delay=36
6470 13:38:51.558140
6471 13:38:51.561254 [CBTSetCACLKResult] CA Dly = 36
6472 13:38:51.564815 CS Dly: 1 (0~32)
6473 13:38:51.564894
6474 13:38:51.567836 ----->DramcWriteLeveling(PI) begin...
6475 13:38:51.567928 ==
6476 13:38:51.571386 Dram Type= 6, Freq= 0, CH_1, rank 0
6477 13:38:51.574897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6478 13:38:51.575003 ==
6479 13:38:51.578041 Write leveling (Byte 0): 32 => 0
6480 13:38:51.581399 Write leveling (Byte 1): 32 => 0
6481 13:38:51.584554 DramcWriteLeveling(PI) end<-----
6482 13:38:51.584628
6483 13:38:51.584689 ==
6484 13:38:51.588160 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 13:38:51.591288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 13:38:51.591373 ==
6487 13:38:51.594845 [Gating] SW mode calibration
6488 13:38:51.601280 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6489 13:38:51.607868 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6490 13:38:51.611442 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 13:38:51.614327 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 13:38:51.620826 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 13:38:51.624595 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6494 13:38:51.627461 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 13:38:51.634037 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 13:38:51.637572 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 13:38:51.640942 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6498 13:38:51.647496 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 13:38:51.651055 Total UI for P1: 0, mck2ui 16
6500 13:38:51.653914 best dqsien dly found for B0: ( 0, 10, 16)
6501 13:38:51.653999 Total UI for P1: 0, mck2ui 16
6502 13:38:51.660582 best dqsien dly found for B1: ( 0, 10, 16)
6503 13:38:51.664202 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6504 13:38:51.667170 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6505 13:38:51.667250
6506 13:38:51.670539 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6507 13:38:51.673730 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6508 13:38:51.677028 [Gating] SW calibration Done
6509 13:38:51.677125 ==
6510 13:38:51.680722 Dram Type= 6, Freq= 0, CH_1, rank 0
6511 13:38:51.683737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6512 13:38:51.683821 ==
6513 13:38:51.687599 RX Vref Scan: 0
6514 13:38:51.687682
6515 13:38:51.690381 RX Vref 0 -> 0, step: 1
6516 13:38:51.690464
6517 13:38:51.690548 RX Delay -410 -> 252, step: 16
6518 13:38:51.697148 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6519 13:38:51.700708 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6520 13:38:51.704069 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6521 13:38:51.707064 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6522 13:38:51.713726 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6523 13:38:51.717140 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6524 13:38:51.720688 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6525 13:38:51.723967 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6526 13:38:51.730311 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6527 13:38:51.733408 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6528 13:38:51.736942 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6529 13:38:51.743640 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6530 13:38:51.746640 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6531 13:38:51.750168 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6532 13:38:51.753677 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6533 13:38:51.759885 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6534 13:38:51.759999 ==
6535 13:38:51.763319 Dram Type= 6, Freq= 0, CH_1, rank 0
6536 13:38:51.766866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6537 13:38:51.766954 ==
6538 13:38:51.767039 DQS Delay:
6539 13:38:51.769840 DQS0 = 43, DQS1 = 59
6540 13:38:51.769920 DQM Delay:
6541 13:38:51.773339 DQM0 = 6, DQM1 = 15
6542 13:38:51.773423 DQ Delay:
6543 13:38:51.776379 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6544 13:38:51.779835 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6545 13:38:51.783247 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6546 13:38:51.786377 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6547 13:38:51.786453
6548 13:38:51.786526
6549 13:38:51.786587 ==
6550 13:38:51.790114 Dram Type= 6, Freq= 0, CH_1, rank 0
6551 13:38:51.793194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6552 13:38:51.793302 ==
6553 13:38:51.793430
6554 13:38:51.793504
6555 13:38:51.796129 TX Vref Scan disable
6556 13:38:51.799889 == TX Byte 0 ==
6557 13:38:51.803409 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6558 13:38:51.806337 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6559 13:38:51.809748 == TX Byte 1 ==
6560 13:38:51.812760 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6561 13:38:51.816402 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6562 13:38:51.816481 ==
6563 13:38:51.819887 Dram Type= 6, Freq= 0, CH_1, rank 0
6564 13:38:51.822848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6565 13:38:51.826384 ==
6566 13:38:51.826501
6567 13:38:51.826615
6568 13:38:51.826719 TX Vref Scan disable
6569 13:38:51.829665 == TX Byte 0 ==
6570 13:38:51.832641 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6571 13:38:51.836137 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6572 13:38:51.839817 == TX Byte 1 ==
6573 13:38:51.842752 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 13:38:51.845858 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 13:38:51.845999
6576 13:38:51.849446 [DATLAT]
6577 13:38:51.849613 Freq=400, CH1 RK0
6578 13:38:51.849751
6579 13:38:51.852603 DATLAT Default: 0xf
6580 13:38:51.852780 0, 0xFFFF, sum = 0
6581 13:38:51.856386 1, 0xFFFF, sum = 0
6582 13:38:51.856549 2, 0xFFFF, sum = 0
6583 13:38:51.859154 3, 0xFFFF, sum = 0
6584 13:38:51.859346 4, 0xFFFF, sum = 0
6585 13:38:51.862488 5, 0xFFFF, sum = 0
6586 13:38:51.862662 6, 0xFFFF, sum = 0
6587 13:38:51.866435 7, 0xFFFF, sum = 0
6588 13:38:51.866664 8, 0xFFFF, sum = 0
6589 13:38:51.869273 9, 0xFFFF, sum = 0
6590 13:38:51.869578 10, 0xFFFF, sum = 0
6591 13:38:51.872927 11, 0xFFFF, sum = 0
6592 13:38:51.876006 12, 0x0, sum = 1
6593 13:38:51.876429 13, 0x0, sum = 2
6594 13:38:51.876685 14, 0x0, sum = 3
6595 13:38:51.879018 15, 0x0, sum = 4
6596 13:38:51.879336 best_step = 13
6597 13:38:51.879577
6598 13:38:51.882674 ==
6599 13:38:51.882975 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 13:38:51.889430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6601 13:38:51.889735 ==
6602 13:38:51.889974 RX Vref Scan: 1
6603 13:38:51.890216
6604 13:38:51.892409 RX Vref 0 -> 0, step: 1
6605 13:38:51.892723
6606 13:38:51.895711 RX Delay -359 -> 252, step: 8
6607 13:38:51.896010
6608 13:38:51.898871 Set Vref, RX VrefLevel [Byte0]: 55
6609 13:38:51.902255 [Byte1]: 48
6610 13:38:51.906282
6611 13:38:51.906581 Final RX Vref Byte 0 = 55 to rank0
6612 13:38:51.909092 Final RX Vref Byte 1 = 48 to rank0
6613 13:38:51.912639 Final RX Vref Byte 0 = 55 to rank1
6614 13:38:51.915996 Final RX Vref Byte 1 = 48 to rank1==
6615 13:38:51.919372 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 13:38:51.925941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6617 13:38:51.926250 ==
6618 13:38:51.926493 DQS Delay:
6619 13:38:51.929282 DQS0 = 48, DQS1 = 64
6620 13:38:51.929610 DQM Delay:
6621 13:38:51.929849 DQM0 = 8, DQM1 = 16
6622 13:38:51.932620 DQ Delay:
6623 13:38:51.935700 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6624 13:38:51.935997 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6625 13:38:51.939074 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6626 13:38:51.942592 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6627 13:38:51.942892
6628 13:38:51.943126
6629 13:38:51.952235 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e1, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6630 13:38:51.955950 CH1 RK0: MR19=C0C, MR18=E1E1
6631 13:38:51.962551 CH1_RK0: MR19=0xC0C, MR18=0xE1E1, DQSOSC=382, MR23=63, INC=404, DEC=269
6632 13:38:51.962856 ==
6633 13:38:51.965245 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 13:38:51.968785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 13:38:51.968866 ==
6636 13:38:51.972075 [Gating] SW mode calibration
6637 13:38:51.979045 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6638 13:38:51.981865 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6639 13:38:51.988541 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6640 13:38:51.992071 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6641 13:38:51.995063 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6642 13:38:52.001759 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6643 13:38:52.005247 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 13:38:52.008694 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 13:38:52.014998 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 13:38:52.018166 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6647 13:38:52.021601 Total UI for P1: 0, mck2ui 16
6648 13:38:52.025100 best dqsien dly found for B0: ( 0, 10, 8)
6649 13:38:52.028744 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 13:38:52.031462 Total UI for P1: 0, mck2ui 16
6651 13:38:52.035175 best dqsien dly found for B1: ( 0, 10, 16)
6652 13:38:52.038263 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6653 13:38:52.041588 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6654 13:38:52.041667
6655 13:38:52.048091 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6656 13:38:52.051694 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6657 13:38:52.055179 [Gating] SW calibration Done
6658 13:38:52.055255 ==
6659 13:38:52.058228 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 13:38:52.061807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6661 13:38:52.061885 ==
6662 13:38:52.061948 RX Vref Scan: 0
6663 13:38:52.062011
6664 13:38:52.064836 RX Vref 0 -> 0, step: 1
6665 13:38:52.064910
6666 13:38:52.068438 RX Delay -410 -> 252, step: 16
6667 13:38:52.071477 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6668 13:38:52.078088 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6669 13:38:52.081632 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6670 13:38:52.084781 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6671 13:38:52.088060 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6672 13:38:52.094879 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6673 13:38:52.097910 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6674 13:38:52.101606 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6675 13:38:52.104428 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6676 13:38:52.111037 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6677 13:38:52.114770 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6678 13:38:52.117662 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6679 13:38:52.121162 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6680 13:38:52.127832 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6681 13:38:52.131002 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6682 13:38:52.134218 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6683 13:38:52.134300 ==
6684 13:38:52.137262 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 13:38:52.144295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6686 13:38:52.144380 ==
6687 13:38:52.144476 DQS Delay:
6688 13:38:52.147539 DQS0 = 43, DQS1 = 59
6689 13:38:52.147636 DQM Delay:
6690 13:38:52.147716 DQM0 = 10, DQM1 = 18
6691 13:38:52.150861 DQ Delay:
6692 13:38:52.153924 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6693 13:38:52.154006 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6694 13:38:52.157447 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6695 13:38:52.160667 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6696 13:38:52.160749
6697 13:38:52.164023
6698 13:38:52.164104 ==
6699 13:38:52.167656 Dram Type= 6, Freq= 0, CH_1, rank 1
6700 13:38:52.170692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6701 13:38:52.170784 ==
6702 13:38:52.170851
6703 13:38:52.170910
6704 13:38:52.173796 TX Vref Scan disable
6705 13:38:52.173877 == TX Byte 0 ==
6706 13:38:52.177253 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6707 13:38:52.184063 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6708 13:38:52.184144 == TX Byte 1 ==
6709 13:38:52.187483 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6710 13:38:52.193761 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6711 13:38:52.193844 ==
6712 13:38:52.197198 Dram Type= 6, Freq= 0, CH_1, rank 1
6713 13:38:52.200830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6714 13:38:52.200913 ==
6715 13:38:52.200977
6716 13:38:52.201095
6717 13:38:52.203823 TX Vref Scan disable
6718 13:38:52.203904 == TX Byte 0 ==
6719 13:38:52.207471 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6720 13:38:52.214092 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6721 13:38:52.214177 == TX Byte 1 ==
6722 13:38:52.217172 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6723 13:38:52.223841 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6724 13:38:52.223950
6725 13:38:52.224042 [DATLAT]
6726 13:38:52.224131 Freq=400, CH1 RK1
6727 13:38:52.224226
6728 13:38:52.226828 DATLAT Default: 0xd
6729 13:38:52.230397 0, 0xFFFF, sum = 0
6730 13:38:52.230481 1, 0xFFFF, sum = 0
6731 13:38:52.233997 2, 0xFFFF, sum = 0
6732 13:38:52.234079 3, 0xFFFF, sum = 0
6733 13:38:52.237220 4, 0xFFFF, sum = 0
6734 13:38:52.237371 5, 0xFFFF, sum = 0
6735 13:38:52.240507 6, 0xFFFF, sum = 0
6736 13:38:52.240615 7, 0xFFFF, sum = 0
6737 13:38:52.243960 8, 0xFFFF, sum = 0
6738 13:38:52.244037 9, 0xFFFF, sum = 0
6739 13:38:52.247273 10, 0xFFFF, sum = 0
6740 13:38:52.247349 11, 0xFFFF, sum = 0
6741 13:38:52.250224 12, 0x0, sum = 1
6742 13:38:52.250300 13, 0x0, sum = 2
6743 13:38:52.254107 14, 0x0, sum = 3
6744 13:38:52.254183 15, 0x0, sum = 4
6745 13:38:52.257053 best_step = 13
6746 13:38:52.257124
6747 13:38:52.257184 ==
6748 13:38:52.260571 Dram Type= 6, Freq= 0, CH_1, rank 1
6749 13:38:52.263422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6750 13:38:52.263498 ==
6751 13:38:52.263587 RX Vref Scan: 0
6752 13:38:52.267095
6753 13:38:52.267176 RX Vref 0 -> 0, step: 1
6754 13:38:52.267240
6755 13:38:52.270068 RX Delay -359 -> 252, step: 8
6756 13:38:52.277769 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6757 13:38:52.281207 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6758 13:38:52.284364 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6759 13:38:52.288004 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6760 13:38:52.294696 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6761 13:38:52.297584 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6762 13:38:52.300835 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6763 13:38:52.304191 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6764 13:38:52.310689 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6765 13:38:52.314246 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6766 13:38:52.317838 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6767 13:38:52.324448 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6768 13:38:52.327514 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6769 13:38:52.330634 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6770 13:38:52.334223 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6771 13:38:52.340745 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6772 13:38:52.340829 ==
6773 13:38:52.344216 Dram Type= 6, Freq= 0, CH_1, rank 1
6774 13:38:52.347220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6775 13:38:52.347302 ==
6776 13:38:52.347366 DQS Delay:
6777 13:38:52.350714 DQS0 = 48, DQS1 = 64
6778 13:38:52.350796 DQM Delay:
6779 13:38:52.354205 DQM0 = 9, DQM1 = 15
6780 13:38:52.354287 DQ Delay:
6781 13:38:52.357650 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6782 13:38:52.360796 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6783 13:38:52.363957 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6784 13:38:52.367455 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6785 13:38:52.367546
6786 13:38:52.367610
6787 13:38:52.374025 [DQSOSCAuto] RK1, (LSB)MR18= 0xb2b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6788 13:38:52.376886 CH1 RK1: MR19=C0C, MR18=B2B2
6789 13:38:52.383469 CH1_RK1: MR19=0xC0C, MR18=0xB2B2, DQSOSC=387, MR23=63, INC=394, DEC=262
6790 13:38:52.386877 [RxdqsGatingPostProcess] freq 400
6791 13:38:52.393890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6792 13:38:52.396811 Pre-setting of DQS Precalculation
6793 13:38:52.400539 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6794 13:38:52.407046 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6795 13:38:52.413655 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6796 13:38:52.413765
6797 13:38:52.413831
6798 13:38:52.416593 [Calibration Summary] 800 Mbps
6799 13:38:52.420282 CH 0, Rank 0
6800 13:38:52.420364 SW Impedance : PASS
6801 13:38:52.423342 DUTY Scan : NO K
6802 13:38:52.426486 ZQ Calibration : PASS
6803 13:38:52.426568 Jitter Meter : NO K
6804 13:38:52.430036 CBT Training : PASS
6805 13:38:52.433810 Write leveling : PASS
6806 13:38:52.433891 RX DQS gating : PASS
6807 13:38:52.436608 RX DQ/DQS(RDDQC) : PASS
6808 13:38:52.436690 TX DQ/DQS : PASS
6809 13:38:52.440234 RX DATLAT : PASS
6810 13:38:52.443303 RX DQ/DQS(Engine): PASS
6811 13:38:52.443385 TX OE : NO K
6812 13:38:52.446661 All Pass.
6813 13:38:52.446757
6814 13:38:52.446822 CH 0, Rank 1
6815 13:38:52.450266 SW Impedance : PASS
6816 13:38:52.450348 DUTY Scan : NO K
6817 13:38:52.453185 ZQ Calibration : PASS
6818 13:38:52.456866 Jitter Meter : NO K
6819 13:38:52.456948 CBT Training : PASS
6820 13:38:52.460414 Write leveling : NO K
6821 13:38:52.463273 RX DQS gating : PASS
6822 13:38:52.463355 RX DQ/DQS(RDDQC) : PASS
6823 13:38:52.466700 TX DQ/DQS : PASS
6824 13:38:52.470048 RX DATLAT : PASS
6825 13:38:52.470129 RX DQ/DQS(Engine): PASS
6826 13:38:52.473177 TX OE : NO K
6827 13:38:52.473258 All Pass.
6828 13:38:52.473360
6829 13:38:52.476789 CH 1, Rank 0
6830 13:38:52.476870 SW Impedance : PASS
6831 13:38:52.479874 DUTY Scan : NO K
6832 13:38:52.483448 ZQ Calibration : PASS
6833 13:38:52.483528 Jitter Meter : NO K
6834 13:38:52.486901 CBT Training : PASS
6835 13:38:52.489857 Write leveling : PASS
6836 13:38:52.489947 RX DQS gating : PASS
6837 13:38:52.493586 RX DQ/DQS(RDDQC) : PASS
6838 13:38:52.493668 TX DQ/DQS : PASS
6839 13:38:52.496789 RX DATLAT : PASS
6840 13:38:52.499865 RX DQ/DQS(Engine): PASS
6841 13:38:52.499946 TX OE : NO K
6842 13:38:52.503064 All Pass.
6843 13:38:52.503173
6844 13:38:52.503244 CH 1, Rank 1
6845 13:38:52.506175 SW Impedance : PASS
6846 13:38:52.506265 DUTY Scan : NO K
6847 13:38:52.509852 ZQ Calibration : PASS
6848 13:38:52.513328 Jitter Meter : NO K
6849 13:38:52.513451 CBT Training : PASS
6850 13:38:52.516634 Write leveling : NO K
6851 13:38:52.519997 RX DQS gating : PASS
6852 13:38:52.520079 RX DQ/DQS(RDDQC) : PASS
6853 13:38:52.522744 TX DQ/DQS : PASS
6854 13:38:52.526485 RX DATLAT : PASS
6855 13:38:52.526565 RX DQ/DQS(Engine): PASS
6856 13:38:52.529519 TX OE : NO K
6857 13:38:52.529625 All Pass.
6858 13:38:52.529692
6859 13:38:52.533047 DramC Write-DBI off
6860 13:38:52.536062 PER_BANK_REFRESH: Hybrid Mode
6861 13:38:52.536165 TX_TRACKING: ON
6862 13:38:52.546099 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6863 13:38:52.549673 [FAST_K] Save calibration result to emmc
6864 13:38:52.552521 dramc_set_vcore_voltage set vcore to 725000
6865 13:38:52.556172 Read voltage for 1600, 0
6866 13:38:52.556268 Vio18 = 0
6867 13:38:52.556332 Vcore = 725000
6868 13:38:52.559153 Vdram = 0
6869 13:38:52.559243 Vddq = 0
6870 13:38:52.559306 Vmddr = 0
6871 13:38:52.566494 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6872 13:38:52.569525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6873 13:38:52.572592 MEM_TYPE=3, freq_sel=13
6874 13:38:52.575554 sv_algorithm_assistance_LP4_3733
6875 13:38:52.579160 ============ PULL DRAM RESETB DOWN ============
6876 13:38:52.582418 ========== PULL DRAM RESETB DOWN end =========
6877 13:38:52.589450 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6878 13:38:52.592495 ===================================
6879 13:38:52.595931 LPDDR4 DRAM CONFIGURATION
6880 13:38:52.599074 ===================================
6881 13:38:52.599156 EX_ROW_EN[0] = 0x0
6882 13:38:52.602234 EX_ROW_EN[1] = 0x0
6883 13:38:52.602315 LP4Y_EN = 0x0
6884 13:38:52.605661 WORK_FSP = 0x1
6885 13:38:52.605742 WL = 0x5
6886 13:38:52.608838 RL = 0x5
6887 13:38:52.608919 BL = 0x2
6888 13:38:52.612155 RPST = 0x0
6889 13:38:52.612239 RD_PRE = 0x0
6890 13:38:52.615591 WR_PRE = 0x1
6891 13:38:52.615673 WR_PST = 0x1
6892 13:38:52.619157 DBI_WR = 0x0
6893 13:38:52.619238 DBI_RD = 0x0
6894 13:38:52.621948 OTF = 0x1
6895 13:38:52.625446 ===================================
6896 13:38:52.629160 ===================================
6897 13:38:52.629284 ANA top config
6898 13:38:52.632433 ===================================
6899 13:38:52.635478 DLL_ASYNC_EN = 0
6900 13:38:52.639013 ALL_SLAVE_EN = 0
6901 13:38:52.642038 NEW_RANK_MODE = 1
6902 13:38:52.642153 DLL_IDLE_MODE = 1
6903 13:38:52.645734 LP45_APHY_COMB_EN = 1
6904 13:38:52.648718 TX_ODT_DIS = 0
6905 13:38:52.651850 NEW_8X_MODE = 1
6906 13:38:52.655278 ===================================
6907 13:38:52.658828 ===================================
6908 13:38:52.661803 data_rate = 3200
6909 13:38:52.665445 CKR = 1
6910 13:38:52.665548 DQ_P2S_RATIO = 8
6911 13:38:52.668404 ===================================
6912 13:38:52.672189 CA_P2S_RATIO = 8
6913 13:38:52.675289 DQ_CA_OPEN = 0
6914 13:38:52.678272 DQ_SEMI_OPEN = 0
6915 13:38:52.681975 CA_SEMI_OPEN = 0
6916 13:38:52.684854 CA_FULL_RATE = 0
6917 13:38:52.684935 DQ_CKDIV4_EN = 0
6918 13:38:52.688447 CA_CKDIV4_EN = 0
6919 13:38:52.691988 CA_PREDIV_EN = 0
6920 13:38:52.695280 PH8_DLY = 12
6921 13:38:52.698472 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6922 13:38:52.701618 DQ_AAMCK_DIV = 4
6923 13:38:52.701699 CA_AAMCK_DIV = 4
6924 13:38:52.704951 CA_ADMCK_DIV = 4
6925 13:38:52.708205 DQ_TRACK_CA_EN = 0
6926 13:38:52.711337 CA_PICK = 1600
6927 13:38:52.714559 CA_MCKIO = 1600
6928 13:38:52.717851 MCKIO_SEMI = 0
6929 13:38:52.721239 PLL_FREQ = 3068
6930 13:38:52.724837 DQ_UI_PI_RATIO = 32
6931 13:38:52.724918 CA_UI_PI_RATIO = 0
6932 13:38:52.728301 ===================================
6933 13:38:52.731408 ===================================
6934 13:38:52.734727 memory_type:LPDDR4
6935 13:38:52.738207 GP_NUM : 10
6936 13:38:52.738293 SRAM_EN : 1
6937 13:38:52.741328 MD32_EN : 0
6938 13:38:52.744815 ===================================
6939 13:38:52.747733 [ANA_INIT] >>>>>>>>>>>>>>
6940 13:38:52.751415 <<<<<< [CONFIGURE PHASE]: ANA_TX
6941 13:38:52.754414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6942 13:38:52.758031 ===================================
6943 13:38:52.758112 data_rate = 3200,PCW = 0X7600
6944 13:38:52.761601 ===================================
6945 13:38:52.764605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6946 13:38:52.771316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6947 13:38:52.777917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6948 13:38:52.781508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6949 13:38:52.784534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6950 13:38:52.787551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6951 13:38:52.791248 [ANA_INIT] flow start
6952 13:38:52.791326 [ANA_INIT] PLL >>>>>>>>
6953 13:38:52.794785 [ANA_INIT] PLL <<<<<<<<
6954 13:38:52.797882 [ANA_INIT] MIDPI >>>>>>>>
6955 13:38:52.800838 [ANA_INIT] MIDPI <<<<<<<<
6956 13:38:52.800919 [ANA_INIT] DLL >>>>>>>>
6957 13:38:52.804408 [ANA_INIT] DLL <<<<<<<<
6958 13:38:52.804490 [ANA_INIT] flow end
6959 13:38:52.811167 ============ LP4 DIFF to SE enter ============
6960 13:38:52.814492 ============ LP4 DIFF to SE exit ============
6961 13:38:52.817687 [ANA_INIT] <<<<<<<<<<<<<
6962 13:38:52.821070 [Flow] Enable top DCM control >>>>>
6963 13:38:52.824394 [Flow] Enable top DCM control <<<<<
6964 13:38:52.827488 Enable DLL master slave shuffle
6965 13:38:52.830896 ==============================================================
6966 13:38:52.834248 Gating Mode config
6967 13:38:52.837746 ==============================================================
6968 13:38:52.840760 Config description:
6969 13:38:52.850784 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6970 13:38:52.857701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6971 13:38:52.860673 SELPH_MODE 0: By rank 1: By Phase
6972 13:38:52.867120 ==============================================================
6973 13:38:52.870758 GAT_TRACK_EN = 1
6974 13:38:52.873788 RX_GATING_MODE = 2
6975 13:38:52.876891 RX_GATING_TRACK_MODE = 2
6976 13:38:52.880542 SELPH_MODE = 1
6977 13:38:52.884165 PICG_EARLY_EN = 1
6978 13:38:52.887243 VALID_LAT_VALUE = 1
6979 13:38:52.890288 ==============================================================
6980 13:38:52.893363 Enter into Gating configuration >>>>
6981 13:38:52.897018 Exit from Gating configuration <<<<
6982 13:38:52.900693 Enter into DVFS_PRE_config >>>>>
6983 13:38:52.910195 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6984 13:38:52.913753 Exit from DVFS_PRE_config <<<<<
6985 13:38:52.917187 Enter into PICG configuration >>>>
6986 13:38:52.920252 Exit from PICG configuration <<<<
6987 13:38:52.923809 [RX_INPUT] configuration >>>>>
6988 13:38:52.926933 [RX_INPUT] configuration <<<<<
6989 13:38:52.933639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6990 13:38:52.936810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6991 13:38:52.943220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6992 13:38:52.950096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6993 13:38:52.956618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6994 13:38:52.963016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6995 13:38:52.966293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6996 13:38:52.969731 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6997 13:38:52.973389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6998 13:38:52.979545 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6999 13:38:52.983099 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7000 13:38:52.986592 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7001 13:38:52.989744 ===================================
7002 13:38:52.992792 LPDDR4 DRAM CONFIGURATION
7003 13:38:52.996458 ===================================
7004 13:38:52.999448 EX_ROW_EN[0] = 0x0
7005 13:38:52.999528 EX_ROW_EN[1] = 0x0
7006 13:38:53.003185 LP4Y_EN = 0x0
7007 13:38:53.003265 WORK_FSP = 0x1
7008 13:38:53.006220 WL = 0x5
7009 13:38:53.006301 RL = 0x5
7010 13:38:53.009770 BL = 0x2
7011 13:38:53.009850 RPST = 0x0
7012 13:38:53.013135 RD_PRE = 0x0
7013 13:38:53.013217 WR_PRE = 0x1
7014 13:38:53.016267 WR_PST = 0x1
7015 13:38:53.016373 DBI_WR = 0x0
7016 13:38:53.019791 DBI_RD = 0x0
7017 13:38:53.019872 OTF = 0x1
7018 13:38:53.022724 ===================================
7019 13:38:53.026430 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7020 13:38:53.032753 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7021 13:38:53.036225 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7022 13:38:53.039733 ===================================
7023 13:38:53.042545 LPDDR4 DRAM CONFIGURATION
7024 13:38:53.045993 ===================================
7025 13:38:53.046096 EX_ROW_EN[0] = 0x10
7026 13:38:53.049145 EX_ROW_EN[1] = 0x0
7027 13:38:53.052482 LP4Y_EN = 0x0
7028 13:38:53.052604 WORK_FSP = 0x1
7029 13:38:53.056198 WL = 0x5
7030 13:38:53.056270 RL = 0x5
7031 13:38:53.059480 BL = 0x2
7032 13:38:53.059580 RPST = 0x0
7033 13:38:53.062473 RD_PRE = 0x0
7034 13:38:53.062554 WR_PRE = 0x1
7035 13:38:53.065881 WR_PST = 0x1
7036 13:38:53.065961 DBI_WR = 0x0
7037 13:38:53.069553 DBI_RD = 0x0
7038 13:38:53.069633 OTF = 0x1
7039 13:38:53.072702 ===================================
7040 13:38:53.079218 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7041 13:38:53.079301 ==
7042 13:38:53.082332 Dram Type= 6, Freq= 0, CH_0, rank 0
7043 13:38:53.085441 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7044 13:38:53.088994 ==
7045 13:38:53.089074 [Duty_Offset_Calibration]
7046 13:38:53.092091 B0:0 B1:2 CA:1
7047 13:38:53.092171
7048 13:38:53.095708 [DutyScan_Calibration_Flow] k_type=0
7049 13:38:53.104631
7050 13:38:53.104707 ==CLK 0==
7051 13:38:53.107625 Final CLK duty delay cell = 0
7052 13:38:53.111144 [0] MAX Duty = 5156%(X100), DQS PI = 22
7053 13:38:53.114706 [0] MIN Duty = 4938%(X100), DQS PI = 52
7054 13:38:53.118046 [0] AVG Duty = 5047%(X100)
7055 13:38:53.118127
7056 13:38:53.121106 CH0 CLK Duty spec in!! Max-Min= 218%
7057 13:38:53.124115 [DutyScan_Calibration_Flow] ====Done====
7058 13:38:53.124188
7059 13:38:53.127653 [DutyScan_Calibration_Flow] k_type=1
7060 13:38:53.144642
7061 13:38:53.144760 ==DQS 0 ==
7062 13:38:53.147604 Final DQS duty delay cell = 0
7063 13:38:53.151569 [0] MAX Duty = 5156%(X100), DQS PI = 32
7064 13:38:53.154401 [0] MIN Duty = 5031%(X100), DQS PI = 8
7065 13:38:53.157800 [0] AVG Duty = 5093%(X100)
7066 13:38:53.157881
7067 13:38:53.157944 ==DQS 1 ==
7068 13:38:53.160917 Final DQS duty delay cell = 0
7069 13:38:53.164132 [0] MAX Duty = 5031%(X100), DQS PI = 6
7070 13:38:53.167494 [0] MIN Duty = 4876%(X100), DQS PI = 18
7071 13:38:53.171006 [0] AVG Duty = 4953%(X100)
7072 13:38:53.171087
7073 13:38:53.174677 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7074 13:38:53.174758
7075 13:38:53.177635 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7076 13:38:53.181180 [DutyScan_Calibration_Flow] ====Done====
7077 13:38:53.181283
7078 13:38:53.184316 [DutyScan_Calibration_Flow] k_type=3
7079 13:38:53.201407
7080 13:38:53.201495 ==DQM 0 ==
7081 13:38:53.205047 Final DQM duty delay cell = 0
7082 13:38:53.208043 [0] MAX Duty = 5187%(X100), DQS PI = 24
7083 13:38:53.211569 [0] MIN Duty = 4907%(X100), DQS PI = 56
7084 13:38:53.214590 [0] AVG Duty = 5047%(X100)
7085 13:38:53.214673
7086 13:38:53.214737 ==DQM 1 ==
7087 13:38:53.218166 Final DQM duty delay cell = 0
7088 13:38:53.221734 [0] MAX Duty = 5031%(X100), DQS PI = 52
7089 13:38:53.224640 [0] MIN Duty = 4782%(X100), DQS PI = 14
7090 13:38:53.227702 [0] AVG Duty = 4906%(X100)
7091 13:38:53.227817
7092 13:38:53.231211 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7093 13:38:53.231307
7094 13:38:53.234872 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7095 13:38:53.237946 [DutyScan_Calibration_Flow] ====Done====
7096 13:38:53.238049
7097 13:38:53.240860 [DutyScan_Calibration_Flow] k_type=2
7098 13:38:53.257794
7099 13:38:53.257877 ==DQ 0 ==
7100 13:38:53.261715 Final DQ duty delay cell = 0
7101 13:38:53.264675 [0] MAX Duty = 5218%(X100), DQS PI = 18
7102 13:38:53.268155 [0] MIN Duty = 4938%(X100), DQS PI = 56
7103 13:38:53.268236 [0] AVG Duty = 5078%(X100)
7104 13:38:53.270984
7105 13:38:53.271064 ==DQ 1 ==
7106 13:38:53.274593 Final DQ duty delay cell = -4
7107 13:38:53.278068 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7108 13:38:53.281111 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7109 13:38:53.284792 [-4] AVG Duty = 4969%(X100)
7110 13:38:53.284898
7111 13:38:53.287903 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7112 13:38:53.287983
7113 13:38:53.290860 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7114 13:38:53.294344 [DutyScan_Calibration_Flow] ====Done====
7115 13:38:53.294420 ==
7116 13:38:53.297601 Dram Type= 6, Freq= 0, CH_1, rank 0
7117 13:38:53.301257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7118 13:38:53.301373 ==
7119 13:38:53.304721 [Duty_Offset_Calibration]
7120 13:38:53.304802 B0:0 B1:4 CA:-5
7121 13:38:53.304866
7122 13:38:53.307907 [DutyScan_Calibration_Flow] k_type=0
7123 13:38:53.318933
7124 13:38:53.319029 ==CLK 0==
7125 13:38:53.322016 Final CLK duty delay cell = 0
7126 13:38:53.325476 [0] MAX Duty = 5156%(X100), DQS PI = 20
7127 13:38:53.328545 [0] MIN Duty = 4906%(X100), DQS PI = 50
7128 13:38:53.331992 [0] AVG Duty = 5031%(X100)
7129 13:38:53.332078
7130 13:38:53.335042 CH1 CLK Duty spec in!! Max-Min= 250%
7131 13:38:53.338047 [DutyScan_Calibration_Flow] ====Done====
7132 13:38:53.338128
7133 13:38:53.341468 [DutyScan_Calibration_Flow] k_type=1
7134 13:38:53.357232
7135 13:38:53.357370 ==DQS 0 ==
7136 13:38:53.360846 Final DQS duty delay cell = 0
7137 13:38:53.364475 [0] MAX Duty = 5156%(X100), DQS PI = 18
7138 13:38:53.367811 [0] MIN Duty = 4907%(X100), DQS PI = 42
7139 13:38:53.367892 [0] AVG Duty = 5031%(X100)
7140 13:38:53.371310
7141 13:38:53.371390 ==DQS 1 ==
7142 13:38:53.374126 Final DQS duty delay cell = -4
7143 13:38:53.377660 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7144 13:38:53.381148 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7145 13:38:53.384429 [-4] AVG Duty = 4922%(X100)
7146 13:38:53.384510
7147 13:38:53.387905 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7148 13:38:53.387985
7149 13:38:53.390939 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7150 13:38:53.394108 [DutyScan_Calibration_Flow] ====Done====
7151 13:38:53.394189
7152 13:38:53.397651 [DutyScan_Calibration_Flow] k_type=3
7153 13:38:53.413230
7154 13:38:53.413382 ==DQM 0 ==
7155 13:38:53.416323 Final DQM duty delay cell = -4
7156 13:38:53.419987 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7157 13:38:53.423102 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7158 13:38:53.426136 [-4] AVG Duty = 4953%(X100)
7159 13:38:53.426240
7160 13:38:53.426305 ==DQM 1 ==
7161 13:38:53.429821 Final DQM duty delay cell = -4
7162 13:38:53.432729 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7163 13:38:53.436389 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7164 13:38:53.439291 [-4] AVG Duty = 4984%(X100)
7165 13:38:53.439387
7166 13:38:53.442900 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7167 13:38:53.442982
7168 13:38:53.445987 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7169 13:38:53.449662 [DutyScan_Calibration_Flow] ====Done====
7170 13:38:53.449741
7171 13:38:53.452588 [DutyScan_Calibration_Flow] k_type=2
7172 13:38:53.470487
7173 13:38:53.470634 ==DQ 0 ==
7174 13:38:53.474141 Final DQ duty delay cell = 0
7175 13:38:53.477567 [0] MAX Duty = 5093%(X100), DQS PI = 20
7176 13:38:53.480879 [0] MIN Duty = 4969%(X100), DQS PI = 44
7177 13:38:53.480961 [0] AVG Duty = 5031%(X100)
7178 13:38:53.484387
7179 13:38:53.484468 ==DQ 1 ==
7180 13:38:53.487219 Final DQ duty delay cell = 0
7181 13:38:53.490699 [0] MAX Duty = 5062%(X100), DQS PI = 6
7182 13:38:53.493735 [0] MIN Duty = 4876%(X100), DQS PI = 30
7183 13:38:53.493824 [0] AVG Duty = 4969%(X100)
7184 13:38:53.497222
7185 13:38:53.500298 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7186 13:38:53.500378
7187 13:38:53.503929 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7188 13:38:53.507042 [DutyScan_Calibration_Flow] ====Done====
7189 13:38:53.510547 nWR fixed to 30
7190 13:38:53.510628 [ModeRegInit_LP4] CH0 RK0
7191 13:38:53.514087 [ModeRegInit_LP4] CH0 RK1
7192 13:38:53.516821 [ModeRegInit_LP4] CH1 RK0
7193 13:38:53.520152 [ModeRegInit_LP4] CH1 RK1
7194 13:38:53.520239 match AC timing 4
7195 13:38:53.527133 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7196 13:38:53.530057 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7197 13:38:53.533726 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7198 13:38:53.540351 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7199 13:38:53.543387 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7200 13:38:53.543463 [MiockJmeterHQA]
7201 13:38:53.543525
7202 13:38:53.546998 [DramcMiockJmeter] u1RxGatingPI = 0
7203 13:38:53.550022 0 : 4252, 4027
7204 13:38:53.550096 4 : 4253, 4026
7205 13:38:53.553638 8 : 4362, 4137
7206 13:38:53.553710 12 : 4363, 4138
7207 13:38:53.553772 16 : 4363, 4137
7208 13:38:53.556654 20 : 4253, 4027
7209 13:38:53.556752 24 : 4253, 4026
7210 13:38:53.560172 28 : 4252, 4027
7211 13:38:53.560244 32 : 4363, 4137
7212 13:38:53.563561 36 : 4253, 4026
7213 13:38:53.563633 40 : 4363, 4138
7214 13:38:53.563694 44 : 4252, 4026
7215 13:38:53.566593 48 : 4252, 4027
7216 13:38:53.566679 52 : 4253, 4027
7217 13:38:53.570280 56 : 4253, 4029
7218 13:38:53.570353 60 : 4250, 4027
7219 13:38:53.573367 64 : 4252, 4026
7220 13:38:53.573438 68 : 4363, 4140
7221 13:38:53.577093 72 : 4252, 4027
7222 13:38:53.577165 76 : 4252, 4029
7223 13:38:53.577224 80 : 4250, 4027
7224 13:38:53.579824 84 : 4362, 4137
7225 13:38:53.579898 88 : 4250, 4026
7226 13:38:53.583438 92 : 4360, 4138
7227 13:38:53.583509 96 : 4252, 4026
7228 13:38:53.586959 100 : 4250, 1573
7229 13:38:53.587032 104 : 4360, 0
7230 13:38:53.587092 108 : 4250, 0
7231 13:38:53.590158 112 : 4250, 0
7232 13:38:53.590239 116 : 4250, 0
7233 13:38:53.593525 120 : 4363, 0
7234 13:38:53.593607 124 : 4250, 0
7235 13:38:53.593672 128 : 4250, 0
7236 13:38:53.597100 132 : 4250, 0
7237 13:38:53.597172 136 : 4252, 0
7238 13:38:53.599754 140 : 4250, 0
7239 13:38:53.599827 144 : 4250, 0
7240 13:38:53.599887 148 : 4252, 0
7241 13:38:53.603301 152 : 4361, 0
7242 13:38:53.603399 156 : 4360, 0
7243 13:38:53.606337 160 : 4363, 0
7244 13:38:53.606409 164 : 4250, 0
7245 13:38:53.606469 168 : 4250, 0
7246 13:38:53.610297 172 : 4250, 0
7247 13:38:53.610371 176 : 4250, 0
7248 13:38:53.613066 180 : 4250, 0
7249 13:38:53.613148 184 : 4250, 0
7250 13:38:53.613212 188 : 4253, 0
7251 13:38:53.616646 192 : 4361, 0
7252 13:38:53.616728 196 : 4249, 0
7253 13:38:53.616791 200 : 4250, 0
7254 13:38:53.620061 204 : 4250, 0
7255 13:38:53.620143 208 : 4360, 0
7256 13:38:53.622965 212 : 4360, 0
7257 13:38:53.623062 216 : 4250, 0
7258 13:38:53.623127 220 : 4360, 891
7259 13:38:53.626575 224 : 4250, 4023
7260 13:38:53.626684 228 : 4363, 4140
7261 13:38:53.629617 232 : 4253, 4029
7262 13:38:53.629698 236 : 4250, 4027
7263 13:38:53.633142 240 : 4250, 4027
7264 13:38:53.633252 244 : 4252, 4029
7265 13:38:53.636129 248 : 4250, 4027
7266 13:38:53.636210 252 : 4249, 4027
7267 13:38:53.639638 256 : 4360, 4138
7268 13:38:53.639721 260 : 4250, 4026
7269 13:38:53.643231 264 : 4250, 4027
7270 13:38:53.643316 268 : 4361, 4137
7271 13:38:53.646235 272 : 4361, 4137
7272 13:38:53.646316 276 : 4250, 4026
7273 13:38:53.649831 280 : 4363, 4140
7274 13:38:53.649913 284 : 4361, 4137
7275 13:38:53.649978 288 : 4250, 4027
7276 13:38:53.652810 292 : 4250, 4026
7277 13:38:53.652892 296 : 4253, 4029
7278 13:38:53.656439 300 : 4250, 4027
7279 13:38:53.656531 304 : 4249, 4027
7280 13:38:53.659419 308 : 4250, 4026
7281 13:38:53.659500 312 : 4253, 4029
7282 13:38:53.663044 316 : 4250, 4027
7283 13:38:53.663126 320 : 4361, 4137
7284 13:38:53.666071 324 : 4361, 4137
7285 13:38:53.666156 328 : 4250, 4026
7286 13:38:53.669484 332 : 4363, 4140
7287 13:38:53.669565 336 : 4361, 3773
7288 13:38:53.672957 340 : 4249, 1584
7289 13:38:53.673039
7290 13:38:53.673102 MIOCK jitter meter ch=0
7291 13:38:53.673161
7292 13:38:53.676048 1T = (340-100) = 240 dly cells
7293 13:38:53.683081 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7294 13:38:53.683188 ==
7295 13:38:53.686124 Dram Type= 6, Freq= 0, CH_0, rank 0
7296 13:38:53.689236 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7297 13:38:53.689362 ==
7298 13:38:53.695995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7299 13:38:53.699186 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7300 13:38:53.702586 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7301 13:38:53.708997 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7302 13:38:53.718270 [CA 0] Center 42 (12~73) winsize 62
7303 13:38:53.721255 [CA 1] Center 42 (12~73) winsize 62
7304 13:38:53.724769 [CA 2] Center 39 (9~69) winsize 61
7305 13:38:53.727767 [CA 3] Center 38 (9~68) winsize 60
7306 13:38:53.731405 [CA 4] Center 37 (7~67) winsize 61
7307 13:38:53.734295 [CA 5] Center 36 (6~66) winsize 61
7308 13:38:53.734376
7309 13:38:53.737619 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7310 13:38:53.737700
7311 13:38:53.740898 [CATrainingPosCal] consider 1 rank data
7312 13:38:53.744814 u2DelayCellTimex100 = 271/100 ps
7313 13:38:53.750984 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7314 13:38:53.754388 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7315 13:38:53.757491 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7316 13:38:53.760612 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7317 13:38:53.764287 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7318 13:38:53.767323 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7319 13:38:53.767403
7320 13:38:53.771000 CA PerBit enable=1, Macro0, CA PI delay=36
7321 13:38:53.771081
7322 13:38:53.774416 [CBTSetCACLKResult] CA Dly = 36
7323 13:38:53.777270 CS Dly: 10 (0~41)
7324 13:38:53.780677 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7325 13:38:53.784346 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7326 13:38:53.784456 ==
7327 13:38:53.787248 Dram Type= 6, Freq= 0, CH_0, rank 1
7328 13:38:53.793824 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7329 13:38:53.793912 ==
7330 13:38:53.797491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7331 13:38:53.804040 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7332 13:38:53.807447 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7333 13:38:53.813923 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7334 13:38:53.820501 [CA 0] Center 42 (12~73) winsize 62
7335 13:38:53.823905 [CA 1] Center 41 (11~72) winsize 62
7336 13:38:53.827185 [CA 2] Center 38 (9~68) winsize 60
7337 13:38:53.830791 [CA 3] Center 37 (7~67) winsize 61
7338 13:38:53.833988 [CA 4] Center 35 (5~65) winsize 61
7339 13:38:53.837819 [CA 5] Center 35 (5~65) winsize 61
7340 13:38:53.837899
7341 13:38:53.840634 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7342 13:38:53.840717
7343 13:38:53.844135 [CATrainingPosCal] consider 2 rank data
7344 13:38:53.847436 u2DelayCellTimex100 = 271/100 ps
7345 13:38:53.850538 CA0 delay=42 (12~73),Diff = 7 PI (25 cell)
7346 13:38:53.857170 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7347 13:38:53.860837 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7348 13:38:53.863770 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7349 13:38:53.867393 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7350 13:38:53.870497 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7351 13:38:53.870578
7352 13:38:53.873562 CA PerBit enable=1, Macro0, CA PI delay=35
7353 13:38:53.873643
7354 13:38:53.877159 [CBTSetCACLKResult] CA Dly = 35
7355 13:38:53.880143 CS Dly: 11 (0~43)
7356 13:38:53.883364 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7357 13:38:53.886723 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7358 13:38:53.886805
7359 13:38:53.890250 ----->DramcWriteLeveling(PI) begin...
7360 13:38:53.890331 ==
7361 13:38:53.893699 Dram Type= 6, Freq= 0, CH_0, rank 0
7362 13:38:53.900305 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7363 13:38:53.900389 ==
7364 13:38:53.903441 Write leveling (Byte 0): 31 => 31
7365 13:38:53.906979 Write leveling (Byte 1): 26 => 26
7366 13:38:53.907062 DramcWriteLeveling(PI) end<-----
7367 13:38:53.907129
7368 13:38:53.910039 ==
7369 13:38:53.913709 Dram Type= 6, Freq= 0, CH_0, rank 0
7370 13:38:53.916709 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7371 13:38:53.916785 ==
7372 13:38:53.920197 [Gating] SW mode calibration
7373 13:38:53.926419 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7374 13:38:53.929828 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7375 13:38:53.936563 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7376 13:38:53.940022 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7377 13:38:53.943054 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7378 13:38:53.949701 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7379 13:38:53.953067 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7380 13:38:53.956401 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7381 13:38:53.963102 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 13:38:53.966410 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7383 13:38:53.970068 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7384 13:38:53.976150 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7385 13:38:53.979751 0 13 8 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
7386 13:38:53.982750 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7387 13:38:53.989858 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7388 13:38:53.992907 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7389 13:38:53.996092 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 13:38:54.002641 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 13:38:54.006210 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7392 13:38:54.009704 0 14 4 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7393 13:38:54.016371 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 13:38:54.019430 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7395 13:38:54.023068 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7396 13:38:54.029484 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 13:38:54.032908 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 13:38:54.036193 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 13:38:54.043017 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 13:38:54.045772 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7401 13:38:54.049282 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7402 13:38:54.052878 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 13:38:54.059577 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 13:38:54.062353 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 13:38:54.065891 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 13:38:54.072446 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 13:38:54.075724 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 13:38:54.079247 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 13:38:54.085969 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 13:38:54.089033 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 13:38:54.092623 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 13:38:54.098832 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 13:38:54.102680 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7414 13:38:54.105470 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7415 13:38:54.112170 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7416 13:38:54.115515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7417 13:38:54.118557 Total UI for P1: 0, mck2ui 16
7418 13:38:54.122250 best dqsien dly found for B0: ( 1, 0, 28)
7419 13:38:54.125339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7420 13:38:54.128926 Total UI for P1: 0, mck2ui 16
7421 13:38:54.132011 best dqsien dly found for B1: ( 1, 1, 4)
7422 13:38:54.135020 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7423 13:38:54.138758 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7424 13:38:54.138840
7425 13:38:54.145405 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7426 13:38:54.148400 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7427 13:38:54.151731 [Gating] SW calibration Done
7428 13:38:54.151815 ==
7429 13:38:54.155129 Dram Type= 6, Freq= 0, CH_0, rank 0
7430 13:38:54.158615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7431 13:38:54.158723 ==
7432 13:38:54.158813 RX Vref Scan: 0
7433 13:38:54.158901
7434 13:38:54.162338 RX Vref 0 -> 0, step: 1
7435 13:38:54.162437
7436 13:38:54.165125 RX Delay 0 -> 252, step: 8
7437 13:38:54.168156 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7438 13:38:54.171775 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7439 13:38:54.178245 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7440 13:38:54.181611 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7441 13:38:54.185042 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7442 13:38:54.188360 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7443 13:38:54.191530 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7444 13:38:54.198045 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7445 13:38:54.201567 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7446 13:38:54.205027 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7447 13:38:54.207820 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7448 13:38:54.211587 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7449 13:38:54.217975 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7450 13:38:54.221130 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7451 13:38:54.224706 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7452 13:38:54.228253 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7453 13:38:54.228333 ==
7454 13:38:54.231462 Dram Type= 6, Freq= 0, CH_0, rank 0
7455 13:38:54.237679 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7456 13:38:54.237765 ==
7457 13:38:54.237828 DQS Delay:
7458 13:38:54.237887 DQS0 = 0, DQS1 = 0
7459 13:38:54.241403 DQM Delay:
7460 13:38:54.241482 DQM0 = 130, DQM1 = 124
7461 13:38:54.244415 DQ Delay:
7462 13:38:54.248099 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7463 13:38:54.251380 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7464 13:38:54.254804 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7465 13:38:54.258153 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7466 13:38:54.258234
7467 13:38:54.258296
7468 13:38:54.258354 ==
7469 13:38:54.261521 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 13:38:54.264542 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7471 13:38:54.268094 ==
7472 13:38:54.268175
7473 13:38:54.268239
7474 13:38:54.268297 TX Vref Scan disable
7475 13:38:54.270957 == TX Byte 0 ==
7476 13:38:54.274513 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7477 13:38:54.277615 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7478 13:38:54.281277 == TX Byte 1 ==
7479 13:38:54.284329 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7480 13:38:54.287697 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7481 13:38:54.290926 ==
7482 13:38:54.291006 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 13:38:54.297550 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7484 13:38:54.297632 ==
7485 13:38:54.310157
7486 13:38:54.313044 TX Vref early break, caculate TX vref
7487 13:38:54.316494 TX Vref=16, minBit 8, minWin=22, winSum=371
7488 13:38:54.319735 TX Vref=18, minBit 8, minWin=23, winSum=381
7489 13:38:54.323083 TX Vref=20, minBit 8, minWin=23, winSum=388
7490 13:38:54.326279 TX Vref=22, minBit 8, minWin=23, winSum=398
7491 13:38:54.329919 TX Vref=24, minBit 9, minWin=23, winSum=402
7492 13:38:54.336603 TX Vref=26, minBit 7, minWin=25, winSum=416
7493 13:38:54.339638 TX Vref=28, minBit 8, minWin=24, winSum=413
7494 13:38:54.343222 TX Vref=30, minBit 0, minWin=25, winSum=410
7495 13:38:54.346233 TX Vref=32, minBit 6, minWin=24, winSum=400
7496 13:38:54.349873 TX Vref=34, minBit 6, minWin=23, winSum=390
7497 13:38:54.355979 [TxChooseVref] Worse bit 7, Min win 25, Win sum 416, Final Vref 26
7498 13:38:54.356082
7499 13:38:54.359371 Final TX Range 0 Vref 26
7500 13:38:54.359451
7501 13:38:54.359514 ==
7502 13:38:54.362544 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 13:38:54.365849 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7504 13:38:54.365929 ==
7505 13:38:54.365993
7506 13:38:54.366052
7507 13:38:54.369216 TX Vref Scan disable
7508 13:38:54.375940 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7509 13:38:54.376020 == TX Byte 0 ==
7510 13:38:54.379149 u2DelayCellOfst[0]=10 cells (3 PI)
7511 13:38:54.382848 u2DelayCellOfst[1]=18 cells (5 PI)
7512 13:38:54.385845 u2DelayCellOfst[2]=14 cells (4 PI)
7513 13:38:54.389005 u2DelayCellOfst[3]=10 cells (3 PI)
7514 13:38:54.392538 u2DelayCellOfst[4]=7 cells (2 PI)
7515 13:38:54.395854 u2DelayCellOfst[5]=0 cells (0 PI)
7516 13:38:54.398903 u2DelayCellOfst[6]=18 cells (5 PI)
7517 13:38:54.402720 u2DelayCellOfst[7]=14 cells (4 PI)
7518 13:38:54.405744 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7519 13:38:54.409412 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7520 13:38:54.412388 == TX Byte 1 ==
7521 13:38:54.415931 u2DelayCellOfst[8]=3 cells (1 PI)
7522 13:38:54.416010 u2DelayCellOfst[9]=0 cells (0 PI)
7523 13:38:54.419008 u2DelayCellOfst[10]=10 cells (3 PI)
7524 13:38:54.422220 u2DelayCellOfst[11]=7 cells (2 PI)
7525 13:38:54.425815 u2DelayCellOfst[12]=14 cells (4 PI)
7526 13:38:54.429251 u2DelayCellOfst[13]=14 cells (4 PI)
7527 13:38:54.432560 u2DelayCellOfst[14]=18 cells (5 PI)
7528 13:38:54.435641 u2DelayCellOfst[15]=14 cells (4 PI)
7529 13:38:54.439058 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7530 13:38:54.445731 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7531 13:38:54.445814 DramC Write-DBI on
7532 13:38:54.445877 ==
7533 13:38:54.448864 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 13:38:54.455467 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7535 13:38:54.455548 ==
7536 13:38:54.455611
7537 13:38:54.455673
7538 13:38:54.455741 TX Vref Scan disable
7539 13:38:54.459348 == TX Byte 0 ==
7540 13:38:54.462876 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7541 13:38:54.465933 == TX Byte 1 ==
7542 13:38:54.469465 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7543 13:38:54.472387 DramC Write-DBI off
7544 13:38:54.472466
7545 13:38:54.472528 [DATLAT]
7546 13:38:54.472585 Freq=1600, CH0 RK0
7547 13:38:54.472642
7548 13:38:54.476010 DATLAT Default: 0xf
7549 13:38:54.476090 0, 0xFFFF, sum = 0
7550 13:38:54.479506 1, 0xFFFF, sum = 0
7551 13:38:54.482454 2, 0xFFFF, sum = 0
7552 13:38:54.482535 3, 0xFFFF, sum = 0
7553 13:38:54.485710 4, 0xFFFF, sum = 0
7554 13:38:54.485793 5, 0xFFFF, sum = 0
7555 13:38:54.489105 6, 0xFFFF, sum = 0
7556 13:38:54.489187 7, 0xFFFF, sum = 0
7557 13:38:54.492651 8, 0xFFFF, sum = 0
7558 13:38:54.492732 9, 0xFFFF, sum = 0
7559 13:38:54.495603 10, 0xFFFF, sum = 0
7560 13:38:54.495687 11, 0xFFFF, sum = 0
7561 13:38:54.499028 12, 0xCFFF, sum = 0
7562 13:38:54.499110 13, 0x0, sum = 1
7563 13:38:54.502116 14, 0x0, sum = 2
7564 13:38:54.502197 15, 0x0, sum = 3
7565 13:38:54.505651 16, 0x0, sum = 4
7566 13:38:54.505732 best_step = 14
7567 13:38:54.505795
7568 13:38:54.505854 ==
7569 13:38:54.509032 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 13:38:54.515335 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7571 13:38:54.515422 ==
7572 13:38:54.515486 RX Vref Scan: 1
7573 13:38:54.515544
7574 13:38:54.519032 Set Vref Range= 24 -> 127
7575 13:38:54.519113
7576 13:38:54.522125 RX Vref 24 -> 127, step: 1
7577 13:38:54.522204
7578 13:38:54.522267 RX Delay 11 -> 252, step: 4
7579 13:38:54.522327
7580 13:38:54.525602 Set Vref, RX VrefLevel [Byte0]: 24
7581 13:38:54.528511 [Byte1]: 24
7582 13:38:54.533017
7583 13:38:54.533098 Set Vref, RX VrefLevel [Byte0]: 25
7584 13:38:54.535782 [Byte1]: 25
7585 13:38:54.540530
7586 13:38:54.540610 Set Vref, RX VrefLevel [Byte0]: 26
7587 13:38:54.543779 [Byte1]: 26
7588 13:38:54.547692
7589 13:38:54.547774 Set Vref, RX VrefLevel [Byte0]: 27
7590 13:38:54.551274 [Byte1]: 27
7591 13:38:54.555562
7592 13:38:54.555657 Set Vref, RX VrefLevel [Byte0]: 28
7593 13:38:54.559256 [Byte1]: 28
7594 13:38:54.563145
7595 13:38:54.563225 Set Vref, RX VrefLevel [Byte0]: 29
7596 13:38:54.566226 [Byte1]: 29
7597 13:38:54.571071
7598 13:38:54.571152 Set Vref, RX VrefLevel [Byte0]: 30
7599 13:38:54.574066 [Byte1]: 30
7600 13:38:54.578630
7601 13:38:54.578716 Set Vref, RX VrefLevel [Byte0]: 31
7602 13:38:54.581554 [Byte1]: 31
7603 13:38:54.585736
7604 13:38:54.585816 Set Vref, RX VrefLevel [Byte0]: 32
7605 13:38:54.589328 [Byte1]: 32
7606 13:38:54.593647
7607 13:38:54.593728 Set Vref, RX VrefLevel [Byte0]: 33
7608 13:38:54.597106 [Byte1]: 33
7609 13:38:54.601275
7610 13:38:54.601391 Set Vref, RX VrefLevel [Byte0]: 34
7611 13:38:54.604730 [Byte1]: 34
7612 13:38:54.608930
7613 13:38:54.609018 Set Vref, RX VrefLevel [Byte0]: 35
7614 13:38:54.612167 [Byte1]: 35
7615 13:38:54.616614
7616 13:38:54.616723 Set Vref, RX VrefLevel [Byte0]: 36
7617 13:38:54.620080 [Byte1]: 36
7618 13:38:54.624061
7619 13:38:54.624140 Set Vref, RX VrefLevel [Byte0]: 37
7620 13:38:54.627115 [Byte1]: 37
7621 13:38:54.631861
7622 13:38:54.631941 Set Vref, RX VrefLevel [Byte0]: 38
7623 13:38:54.634874 [Byte1]: 38
7624 13:38:54.639057
7625 13:38:54.639137 Set Vref, RX VrefLevel [Byte0]: 39
7626 13:38:54.642691 [Byte1]: 39
7627 13:38:54.646868
7628 13:38:54.646950 Set Vref, RX VrefLevel [Byte0]: 40
7629 13:38:54.650391 [Byte1]: 40
7630 13:38:54.654788
7631 13:38:54.654868 Set Vref, RX VrefLevel [Byte0]: 41
7632 13:38:54.657819 [Byte1]: 41
7633 13:38:54.662040
7634 13:38:54.662120 Set Vref, RX VrefLevel [Byte0]: 42
7635 13:38:54.665787 [Byte1]: 42
7636 13:38:54.669648
7637 13:38:54.669730 Set Vref, RX VrefLevel [Byte0]: 43
7638 13:38:54.673044 [Byte1]: 43
7639 13:38:54.677129
7640 13:38:54.677208 Set Vref, RX VrefLevel [Byte0]: 44
7641 13:38:54.680770 [Byte1]: 44
7642 13:38:54.685157
7643 13:38:54.685275 Set Vref, RX VrefLevel [Byte0]: 45
7644 13:38:54.688613 [Byte1]: 45
7645 13:38:54.692785
7646 13:38:54.692865 Set Vref, RX VrefLevel [Byte0]: 46
7647 13:38:54.695841 [Byte1]: 46
7648 13:38:54.700309
7649 13:38:54.700400 Set Vref, RX VrefLevel [Byte0]: 47
7650 13:38:54.703780 [Byte1]: 47
7651 13:38:54.707591
7652 13:38:54.707671 Set Vref, RX VrefLevel [Byte0]: 48
7653 13:38:54.711020 [Byte1]: 48
7654 13:38:54.715274
7655 13:38:54.715380 Set Vref, RX VrefLevel [Byte0]: 49
7656 13:38:54.718770 [Byte1]: 49
7657 13:38:54.723220
7658 13:38:54.723324 Set Vref, RX VrefLevel [Byte0]: 50
7659 13:38:54.726118 [Byte1]: 50
7660 13:38:54.730960
7661 13:38:54.731082 Set Vref, RX VrefLevel [Byte0]: 51
7662 13:38:54.733958 [Byte1]: 51
7663 13:38:54.738009
7664 13:38:54.738108 Set Vref, RX VrefLevel [Byte0]: 52
7665 13:38:54.741614 [Byte1]: 52
7666 13:38:54.745744
7667 13:38:54.745824 Set Vref, RX VrefLevel [Byte0]: 53
7668 13:38:54.749326 [Byte1]: 53
7669 13:38:54.753667
7670 13:38:54.753748 Set Vref, RX VrefLevel [Byte0]: 54
7671 13:38:54.756553 [Byte1]: 54
7672 13:38:54.761193
7673 13:38:54.761273 Set Vref, RX VrefLevel [Byte0]: 55
7674 13:38:54.764767 [Byte1]: 55
7675 13:38:54.768877
7676 13:38:54.768956 Set Vref, RX VrefLevel [Byte0]: 56
7677 13:38:54.772419 [Byte1]: 56
7678 13:38:54.776383
7679 13:38:54.776464 Set Vref, RX VrefLevel [Byte0]: 57
7680 13:38:54.779873 [Byte1]: 57
7681 13:38:54.784343
7682 13:38:54.784423 Set Vref, RX VrefLevel [Byte0]: 58
7683 13:38:54.787317 [Byte1]: 58
7684 13:38:54.791867
7685 13:38:54.791946 Set Vref, RX VrefLevel [Byte0]: 59
7686 13:38:54.794845 [Byte1]: 59
7687 13:38:54.799163
7688 13:38:54.799242 Set Vref, RX VrefLevel [Byte0]: 60
7689 13:38:54.802746 [Byte1]: 60
7690 13:38:54.806900
7691 13:38:54.806992 Set Vref, RX VrefLevel [Byte0]: 61
7692 13:38:54.809891 [Byte1]: 61
7693 13:38:54.814731
7694 13:38:54.814836 Set Vref, RX VrefLevel [Byte0]: 62
7695 13:38:54.817767 [Byte1]: 62
7696 13:38:54.821745
7697 13:38:54.821850 Set Vref, RX VrefLevel [Byte0]: 63
7698 13:38:54.825180 [Byte1]: 63
7699 13:38:54.829839
7700 13:38:54.829941 Set Vref, RX VrefLevel [Byte0]: 64
7701 13:38:54.832692 [Byte1]: 64
7702 13:38:54.837541
7703 13:38:54.837643 Set Vref, RX VrefLevel [Byte0]: 65
7704 13:38:54.840306 [Byte1]: 65
7705 13:38:54.844578
7706 13:38:54.844660 Set Vref, RX VrefLevel [Byte0]: 66
7707 13:38:54.848135 [Byte1]: 66
7708 13:38:54.852432
7709 13:38:54.852507 Set Vref, RX VrefLevel [Byte0]: 67
7710 13:38:54.855608 [Byte1]: 67
7711 13:38:54.860017
7712 13:38:54.860097 Set Vref, RX VrefLevel [Byte0]: 68
7713 13:38:54.863593 [Byte1]: 68
7714 13:38:54.867527
7715 13:38:54.867633 Set Vref, RX VrefLevel [Byte0]: 69
7716 13:38:54.870760 [Byte1]: 69
7717 13:38:54.875531
7718 13:38:54.875606 Set Vref, RX VrefLevel [Byte0]: 70
7719 13:38:54.878546 [Byte1]: 70
7720 13:38:54.883175
7721 13:38:54.883281 Set Vref, RX VrefLevel [Byte0]: 71
7722 13:38:54.886266 [Byte1]: 71
7723 13:38:54.890466
7724 13:38:54.890574 Set Vref, RX VrefLevel [Byte0]: 72
7725 13:38:54.894006 [Byte1]: 72
7726 13:38:54.898013
7727 13:38:54.898097 Final RX Vref Byte 0 = 53 to rank0
7728 13:38:54.901419 Final RX Vref Byte 1 = 55 to rank0
7729 13:38:54.904445 Final RX Vref Byte 0 = 53 to rank1
7730 13:38:54.908041 Final RX Vref Byte 1 = 55 to rank1==
7731 13:38:54.911537 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 13:38:54.917785 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7733 13:38:54.917881 ==
7734 13:38:54.917947 DQS Delay:
7735 13:38:54.921246 DQS0 = 0, DQS1 = 0
7736 13:38:54.921342 DQM Delay:
7737 13:38:54.921402 DQM0 = 126, DQM1 = 121
7738 13:38:54.924724 DQ Delay:
7739 13:38:54.927894 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7740 13:38:54.931181 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7741 13:38:54.934519 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7742 13:38:54.938043 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7743 13:38:54.938152
7744 13:38:54.938244
7745 13:38:54.938335
7746 13:38:54.941104 [DramC_TX_OE_Calibration] TA2
7747 13:38:54.944503 Original DQ_B0 (3 6) =30, OEN = 27
7748 13:38:54.947772 Original DQ_B1 (3 6) =30, OEN = 27
7749 13:38:54.951150 24, 0x0, End_B0=24 End_B1=24
7750 13:38:54.951237 25, 0x0, End_B0=25 End_B1=25
7751 13:38:54.954239 26, 0x0, End_B0=26 End_B1=26
7752 13:38:54.957433 27, 0x0, End_B0=27 End_B1=27
7753 13:38:54.961070 28, 0x0, End_B0=28 End_B1=28
7754 13:38:54.964109 29, 0x0, End_B0=29 End_B1=29
7755 13:38:54.964184 30, 0x0, End_B0=30 End_B1=30
7756 13:38:54.967826 31, 0x4141, End_B0=30 End_B1=30
7757 13:38:54.970787 Byte0 end_step=30 best_step=27
7758 13:38:54.974231 Byte1 end_step=30 best_step=27
7759 13:38:54.977576 Byte0 TX OE(2T, 0.5T) = (3, 3)
7760 13:38:54.980958 Byte1 TX OE(2T, 0.5T) = (3, 3)
7761 13:38:54.981035
7762 13:38:54.981097
7763 13:38:54.987525 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7764 13:38:54.991152 CH0 RK0: MR19=303, MR18=1919
7765 13:38:54.997587 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7766 13:38:54.997703
7767 13:38:55.000475 ----->DramcWriteLeveling(PI) begin...
7768 13:38:55.000549 ==
7769 13:38:55.003892 Dram Type= 6, Freq= 0, CH_0, rank 1
7770 13:38:55.007432 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7771 13:38:55.007526 ==
7772 13:38:55.010476 Write leveling (Byte 0): 29 => 29
7773 13:38:55.014043 Write leveling (Byte 1): 26 => 26
7774 13:38:55.017645 DramcWriteLeveling(PI) end<-----
7775 13:38:55.017730
7776 13:38:55.017794 ==
7777 13:38:55.020549 Dram Type= 6, Freq= 0, CH_0, rank 1
7778 13:38:55.024264 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7779 13:38:55.024342 ==
7780 13:38:55.027237 [Gating] SW mode calibration
7781 13:38:55.033739 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7782 13:38:55.040941 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7783 13:38:55.044324 0 12 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7784 13:38:55.050760 0 12 4 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
7785 13:38:55.053577 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7786 13:38:55.056838 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7787 13:38:55.063956 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7788 13:38:55.066979 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7789 13:38:55.070495 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 13:38:55.076615 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7791 13:38:55.080254 0 13 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 1)
7792 13:38:55.083713 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7793 13:38:55.090452 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 13:38:55.093661 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7795 13:38:55.097139 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7796 13:38:55.100295 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7797 13:38:55.106725 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7798 13:38:55.110308 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 13:38:55.113411 0 14 0 | B1->B0 | 2323 4040 | 0 0 | (0 0) (1 1)
7800 13:38:55.119812 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
7801 13:38:55.123321 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 13:38:55.126982 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7803 13:38:55.133126 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7804 13:38:55.136865 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 13:38:55.139820 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 13:38:55.146299 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7807 13:38:55.149589 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7808 13:38:55.152827 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7809 13:38:55.159973 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 13:38:55.163230 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 13:38:55.166403 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 13:38:55.172726 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 13:38:55.176443 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 13:38:55.179501 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 13:38:55.186184 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 13:38:55.189749 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 13:38:55.192574 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 13:38:55.199688 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 13:38:55.202805 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 13:38:55.205865 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 13:38:55.212935 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7822 13:38:55.215831 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7823 13:38:55.219347 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7824 13:38:55.225714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7825 13:38:55.225803 Total UI for P1: 0, mck2ui 16
7826 13:38:55.232587 best dqsien dly found for B0: ( 1, 0, 28)
7827 13:38:55.235657 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7828 13:38:55.238765 Total UI for P1: 0, mck2ui 16
7829 13:38:55.242436 best dqsien dly found for B1: ( 1, 1, 2)
7830 13:38:55.246028 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7831 13:38:55.248894 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7832 13:38:55.248976
7833 13:38:55.252512 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7834 13:38:55.255604 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7835 13:38:55.259026 [Gating] SW calibration Done
7836 13:38:55.259102 ==
7837 13:38:55.262423 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 13:38:55.265700 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 13:38:55.265774 ==
7840 13:38:55.269186 RX Vref Scan: 0
7841 13:38:55.269309
7842 13:38:55.272291 RX Vref 0 -> 0, step: 1
7843 13:38:55.272369
7844 13:38:55.272432 RX Delay 0 -> 252, step: 8
7845 13:38:55.278871 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7846 13:38:55.282481 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7847 13:38:55.285575 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7848 13:38:55.289218 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7849 13:38:55.292237 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7850 13:38:55.298855 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7851 13:38:55.302662 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7852 13:38:55.305410 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7853 13:38:55.309089 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7854 13:38:55.312054 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7855 13:38:55.318557 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7856 13:38:55.322111 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7857 13:38:55.325545 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7858 13:38:55.328332 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7859 13:38:55.334907 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7860 13:38:55.338503 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7861 13:38:55.338584 ==
7862 13:38:55.342015 Dram Type= 6, Freq= 0, CH_0, rank 1
7863 13:38:55.345017 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7864 13:38:55.345104 ==
7865 13:38:55.348094 DQS Delay:
7866 13:38:55.348174 DQS0 = 0, DQS1 = 0
7867 13:38:55.348237 DQM Delay:
7868 13:38:55.351567 DQM0 = 131, DQM1 = 124
7869 13:38:55.351648 DQ Delay:
7870 13:38:55.354606 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
7871 13:38:55.358255 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7872 13:38:55.364749 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7873 13:38:55.368302 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7874 13:38:55.368404
7875 13:38:55.368499
7876 13:38:55.368588 ==
7877 13:38:55.371153 Dram Type= 6, Freq= 0, CH_0, rank 1
7878 13:38:55.374672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7879 13:38:55.374779 ==
7880 13:38:55.374869
7881 13:38:55.374956
7882 13:38:55.378092 TX Vref Scan disable
7883 13:38:55.378197 == TX Byte 0 ==
7884 13:38:55.384575 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7885 13:38:55.387857 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7886 13:38:55.387964 == TX Byte 1 ==
7887 13:38:55.394697 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7888 13:38:55.398290 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7889 13:38:55.398371 ==
7890 13:38:55.401217 Dram Type= 6, Freq= 0, CH_0, rank 1
7891 13:38:55.404847 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7892 13:38:55.404928 ==
7893 13:38:55.420074
7894 13:38:55.423209 TX Vref early break, caculate TX vref
7895 13:38:55.426377 TX Vref=16, minBit 9, minWin=21, winSum=374
7896 13:38:55.429912 TX Vref=18, minBit 1, minWin=23, winSum=380
7897 13:38:55.433201 TX Vref=20, minBit 1, minWin=23, winSum=389
7898 13:38:55.436403 TX Vref=22, minBit 1, minWin=24, winSum=398
7899 13:38:55.439879 TX Vref=24, minBit 8, minWin=24, winSum=405
7900 13:38:55.446368 TX Vref=26, minBit 8, minWin=24, winSum=412
7901 13:38:55.449599 TX Vref=28, minBit 8, minWin=24, winSum=413
7902 13:38:55.452625 TX Vref=30, minBit 1, minWin=24, winSum=409
7903 13:38:55.456110 TX Vref=32, minBit 8, minWin=24, winSum=403
7904 13:38:55.459584 TX Vref=34, minBit 8, minWin=22, winSum=396
7905 13:38:55.463146 TX Vref=36, minBit 8, minWin=22, winSum=383
7906 13:38:55.469702 [TxChooseVref] Worse bit 8, Min win 24, Win sum 413, Final Vref 28
7907 13:38:55.469806
7908 13:38:55.472686 Final TX Range 0 Vref 28
7909 13:38:55.472786
7910 13:38:55.472874 ==
7911 13:38:55.476167 Dram Type= 6, Freq= 0, CH_0, rank 1
7912 13:38:55.479816 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7913 13:38:55.479947 ==
7914 13:38:55.480062
7915 13:38:55.480169
7916 13:38:55.482900 TX Vref Scan disable
7917 13:38:55.489106 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7918 13:38:55.489251 == TX Byte 0 ==
7919 13:38:55.492473 u2DelayCellOfst[0]=10 cells (3 PI)
7920 13:38:55.496121 u2DelayCellOfst[1]=18 cells (5 PI)
7921 13:38:55.498947 u2DelayCellOfst[2]=10 cells (3 PI)
7922 13:38:55.502495 u2DelayCellOfst[3]=10 cells (3 PI)
7923 13:38:55.506185 u2DelayCellOfst[4]=7 cells (2 PI)
7924 13:38:55.509297 u2DelayCellOfst[5]=0 cells (0 PI)
7925 13:38:55.512401 u2DelayCellOfst[6]=14 cells (4 PI)
7926 13:38:55.515949 u2DelayCellOfst[7]=14 cells (4 PI)
7927 13:38:55.519547 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7928 13:38:55.522523 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7929 13:38:55.526074 == TX Byte 1 ==
7930 13:38:55.529202 u2DelayCellOfst[8]=3 cells (1 PI)
7931 13:38:55.532533 u2DelayCellOfst[9]=0 cells (0 PI)
7932 13:38:55.535889 u2DelayCellOfst[10]=14 cells (4 PI)
7933 13:38:55.535980 u2DelayCellOfst[11]=7 cells (2 PI)
7934 13:38:55.539012 u2DelayCellOfst[12]=18 cells (5 PI)
7935 13:38:55.542324 u2DelayCellOfst[13]=18 cells (5 PI)
7936 13:38:55.545547 u2DelayCellOfst[14]=21 cells (6 PI)
7937 13:38:55.548925 u2DelayCellOfst[15]=18 cells (5 PI)
7938 13:38:55.555587 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7939 13:38:55.559226 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7940 13:38:55.559305 DramC Write-DBI on
7941 13:38:55.559381 ==
7942 13:38:55.562635 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 13:38:55.569023 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7944 13:38:55.569136 ==
7945 13:38:55.569234
7946 13:38:55.569364
7947 13:38:55.569451 TX Vref Scan disable
7948 13:38:55.573225 == TX Byte 0 ==
7949 13:38:55.576239 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7950 13:38:55.579722 == TX Byte 1 ==
7951 13:38:55.583224 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7952 13:38:55.586246 DramC Write-DBI off
7953 13:38:55.586329
7954 13:38:55.586400 [DATLAT]
7955 13:38:55.586459 Freq=1600, CH0 RK1
7956 13:38:55.586516
7957 13:38:55.589943 DATLAT Default: 0xe
7958 13:38:55.590055 0, 0xFFFF, sum = 0
7959 13:38:55.592974 1, 0xFFFF, sum = 0
7960 13:38:55.595993 2, 0xFFFF, sum = 0
7961 13:38:55.596067 3, 0xFFFF, sum = 0
7962 13:38:55.599533 4, 0xFFFF, sum = 0
7963 13:38:55.599614 5, 0xFFFF, sum = 0
7964 13:38:55.602905 6, 0xFFFF, sum = 0
7965 13:38:55.603012 7, 0xFFFF, sum = 0
7966 13:38:55.606404 8, 0xFFFF, sum = 0
7967 13:38:55.606506 9, 0xFFFF, sum = 0
7968 13:38:55.609460 10, 0xFFFF, sum = 0
7969 13:38:55.609563 11, 0xFFFF, sum = 0
7970 13:38:55.612973 12, 0x8FFF, sum = 0
7971 13:38:55.613100 13, 0x0, sum = 1
7972 13:38:55.615918 14, 0x0, sum = 2
7973 13:38:55.616041 15, 0x0, sum = 3
7974 13:38:55.619633 16, 0x0, sum = 4
7975 13:38:55.619712 best_step = 14
7976 13:38:55.619774
7977 13:38:55.619832 ==
7978 13:38:55.622507 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 13:38:55.629014 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7980 13:38:55.629091 ==
7981 13:38:55.629154 RX Vref Scan: 0
7982 13:38:55.629212
7983 13:38:55.632859 RX Vref 0 -> 0, step: 1
7984 13:38:55.632951
7985 13:38:55.635657 RX Delay 11 -> 252, step: 4
7986 13:38:55.639422 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7987 13:38:55.642323 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7988 13:38:55.645609 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7989 13:38:55.652310 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7990 13:38:55.655625 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7991 13:38:55.659151 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7992 13:38:55.662083 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7993 13:38:55.665642 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7994 13:38:55.672149 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7995 13:38:55.675766 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7996 13:38:55.678723 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7997 13:38:55.682352 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7998 13:38:55.685160 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7999 13:38:55.691827 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8000 13:38:59.977079 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8001 13:38:59.977346 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8002 13:38:59.977506 ==
8003 13:38:59.977649 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 13:38:59.977723 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8005 13:38:59.977784 ==
8006 13:38:59.977843 DQS Delay:
8007 13:38:59.977900 DQS0 = 0, DQS1 = 0
8008 13:38:59.977956 DQM Delay:
8009 13:38:59.978020 DQM0 = 128, DQM1 = 120
8010 13:38:59.978076 DQ Delay:
8011 13:38:59.978132 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8012 13:38:59.978188 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8013 13:38:59.978242 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8014 13:38:59.978318 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8015 13:38:59.978375
8016 13:38:59.978430
8017 13:38:59.978518
8018 13:38:59.978588 [DramC_TX_OE_Calibration] TA2
8019 13:38:59.978674 Original DQ_B0 (3 6) =30, OEN = 27
8020 13:38:59.978731 Original DQ_B1 (3 6) =30, OEN = 27
8021 13:38:59.978786 24, 0x0, End_B0=24 End_B1=24
8022 13:38:59.978841 25, 0x0, End_B0=25 End_B1=25
8023 13:38:59.978895 26, 0x0, End_B0=26 End_B1=26
8024 13:38:59.978949 27, 0x0, End_B0=27 End_B1=27
8025 13:38:59.979040 28, 0x0, End_B0=28 End_B1=28
8026 13:38:59.979094 29, 0x0, End_B0=29 End_B1=29
8027 13:38:59.979148 30, 0x0, End_B0=30 End_B1=30
8028 13:38:59.979202 31, 0x4141, End_B0=30 End_B1=30
8029 13:38:59.979272 Byte0 end_step=30 best_step=27
8030 13:38:59.979339 Byte1 end_step=30 best_step=27
8031 13:38:59.979391 Byte0 TX OE(2T, 0.5T) = (3, 3)
8032 13:38:59.979444 Byte1 TX OE(2T, 0.5T) = (3, 3)
8033 13:38:59.979496
8034 13:38:59.979571
8035 13:38:59.979638 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8036 13:38:59.979692 CH0 RK1: MR19=303, MR18=2020
8037 13:38:59.979745 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8038 13:38:59.979798 [RxdqsGatingPostProcess] freq 1600
8039 13:38:59.979851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8040 13:38:59.979903 Pre-setting of DQS Precalculation
8041 13:38:59.979956 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8042 13:38:59.980028 ==
8043 13:38:59.980131 Dram Type= 6, Freq= 0, CH_1, rank 0
8044 13:38:59.980184 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8045 13:38:59.980237 ==
8046 13:38:59.980290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8047 13:38:59.980342 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8048 13:38:59.980395 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8049 13:38:59.980447 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8050 13:38:59.980501 [CA 0] Center 41 (11~71) winsize 61
8051 13:38:59.980553 [CA 1] Center 41 (11~72) winsize 62
8052 13:38:59.980612 [CA 2] Center 37 (8~67) winsize 60
8053 13:38:59.980665 [CA 3] Center 36 (6~66) winsize 61
8054 13:38:59.980717 [CA 4] Center 34 (4~64) winsize 61
8055 13:38:59.980770 [CA 5] Center 34 (5~64) winsize 60
8056 13:38:59.980823
8057 13:38:59.980874 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8058 13:38:59.980927
8059 13:38:59.980979 [CATrainingPosCal] consider 1 rank data
8060 13:38:59.981032 u2DelayCellTimex100 = 271/100 ps
8061 13:38:59.981084 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8062 13:38:59.981142 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8063 13:38:59.981196 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8064 13:38:59.981248 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8065 13:38:59.981324 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8066 13:38:59.981391 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8067 13:38:59.981443
8068 13:38:59.981496 CA PerBit enable=1, Macro0, CA PI delay=34
8069 13:38:59.981548
8070 13:38:59.981600 [CBTSetCACLKResult] CA Dly = 34
8071 13:38:59.981652 CS Dly: 8 (0~39)
8072 13:38:59.981712 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8073 13:38:59.981765 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8074 13:38:59.981817 ==
8075 13:38:59.981885 Dram Type= 6, Freq= 0, CH_1, rank 1
8076 13:38:59.981952 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8077 13:38:59.982021 ==
8078 13:38:59.982075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8079 13:38:59.982146 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8080 13:38:59.982199 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8081 13:38:59.982290 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8082 13:38:59.982343 [CA 0] Center 40 (10~70) winsize 61
8083 13:38:59.982395 [CA 1] Center 39 (9~70) winsize 62
8084 13:38:59.982447 [CA 2] Center 35 (6~65) winsize 60
8085 13:38:59.982520 [CA 3] Center 35 (6~64) winsize 59
8086 13:38:59.982574 [CA 4] Center 33 (3~63) winsize 61
8087 13:38:59.982626 [CA 5] Center 33 (3~63) winsize 61
8088 13:38:59.982678
8089 13:38:59.982737 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8090 13:38:59.982820
8091 13:38:59.982871 [CATrainingPosCal] consider 2 rank data
8092 13:38:59.982923 u2DelayCellTimex100 = 271/100 ps
8093 13:38:59.982975 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8094 13:38:59.983028 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8095 13:38:59.983080 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8096 13:38:59.983132 CA3 delay=35 (6~64),Diff = 2 PI (7 cell)
8097 13:38:59.983184 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8098 13:38:59.983236 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8099 13:38:59.983294
8100 13:38:59.983346 CA PerBit enable=1, Macro0, CA PI delay=33
8101 13:38:59.983398
8102 13:38:59.983450 [CBTSetCACLKResult] CA Dly = 33
8103 13:38:59.983503 CS Dly: 9 (0~41)
8104 13:38:59.983555 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8105 13:38:59.983608 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8106 13:38:59.983661
8107 13:38:59.983713 ----->DramcWriteLeveling(PI) begin...
8108 13:38:59.983767 ==
8109 13:38:59.983820 Dram Type= 6, Freq= 0, CH_1, rank 0
8110 13:38:59.983878 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8111 13:38:59.983932 ==
8112 13:38:59.983984 Write leveling (Byte 0): 22 => 22
8113 13:38:59.984037 Write leveling (Byte 1): 21 => 21
8114 13:38:59.984089 DramcWriteLeveling(PI) end<-----
8115 13:38:59.984141
8116 13:38:59.984193 ==
8117 13:38:59.984245 Dram Type= 6, Freq= 0, CH_1, rank 0
8118 13:38:59.984297 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8119 13:38:59.984356 ==
8120 13:38:59.984409 [Gating] SW mode calibration
8121 13:38:59.984462 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8122 13:38:59.984515 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8123 13:38:59.984597 0 12 0 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
8124 13:38:59.984856 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 13:38:59.984939 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 13:38:59.985008 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 13:38:59.985061 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 13:38:59.985114 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8129 13:38:59.985166 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 13:38:59.985219 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8131 13:38:59.985272 0 13 0 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
8132 13:38:59.985364 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8133 13:38:59.985423 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 13:38:59.985477 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 13:38:59.985530 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8136 13:38:59.985582 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 13:38:59.985635 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 13:38:59.985688 0 13 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8139 13:38:59.985740 0 14 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8140 13:38:59.985792 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 13:38:59.985845 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 13:38:59.985898 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 13:38:59.985950 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 13:38:59.986029 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 13:38:59.986115 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8146 13:38:59.986170 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8147 13:38:59.986223 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8148 13:38:59.986275 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8149 13:38:59.986328 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 13:38:59.986380 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 13:38:59.986432 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 13:38:59.986485 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 13:38:59.986537 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 13:38:59.986628 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 13:38:59.986681 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 13:38:59.986734 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 13:38:59.986787 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 13:38:59.986840 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 13:38:59.986893 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 13:38:59.986945 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 13:38:59.986998 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8162 13:38:59.987051 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8163 13:38:59.987109 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8164 13:38:59.987163 Total UI for P1: 0, mck2ui 16
8165 13:38:59.987217 best dqsien dly found for B0: ( 1, 0, 26)
8166 13:38:59.987270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8167 13:38:59.987324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8168 13:38:59.987377 Total UI for P1: 0, mck2ui 16
8169 13:38:59.987430 best dqsien dly found for B1: ( 1, 1, 2)
8170 13:38:59.987483 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8171 13:38:59.987536 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8172 13:38:59.987589
8173 13:38:59.987647 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8174 13:38:59.987701 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8175 13:38:59.987753 [Gating] SW calibration Done
8176 13:38:59.987806 ==
8177 13:38:59.987859 Dram Type= 6, Freq= 0, CH_1, rank 0
8178 13:38:59.987911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8179 13:38:59.987964 ==
8180 13:38:59.988016 RX Vref Scan: 0
8181 13:38:59.988069
8182 13:38:59.988121 RX Vref 0 -> 0, step: 1
8183 13:38:59.988180
8184 13:38:59.988233 RX Delay 0 -> 252, step: 8
8185 13:38:59.988286 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8186 13:38:59.988339 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8187 13:38:59.988392 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8188 13:38:59.988444 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8189 13:38:59.988496 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8190 13:38:59.988548 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8191 13:38:59.988601 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8192 13:38:59.988653 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8193 13:38:59.988710 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8194 13:38:59.988764 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8195 13:38:59.988817 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8196 13:38:59.988869 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8197 13:38:59.988922 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8198 13:38:59.988975 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8199 13:38:59.989028 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8200 13:38:59.989080 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8201 13:38:59.989133 ==
8202 13:38:59.989185 Dram Type= 6, Freq= 0, CH_1, rank 0
8203 13:38:59.989238 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8204 13:38:59.989328 ==
8205 13:38:59.989397 DQS Delay:
8206 13:38:59.989449 DQS0 = 0, DQS1 = 0
8207 13:38:59.989502 DQM Delay:
8208 13:38:59.989555 DQM0 = 129, DQM1 = 125
8209 13:38:59.989619 DQ Delay:
8210 13:38:59.989676 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8211 13:38:59.989729 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8212 13:38:59.989782 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8213 13:38:59.989857 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8214 13:38:59.989924
8215 13:38:59.989976
8216 13:38:59.990029 ==
8217 13:38:59.990082 Dram Type= 6, Freq= 0, CH_1, rank 0
8218 13:38:59.990134 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8219 13:38:59.990188 ==
8220 13:38:59.990240
8221 13:38:59.990292
8222 13:38:59.990351 TX Vref Scan disable
8223 13:38:59.990404 == TX Byte 0 ==
8224 13:38:59.990457 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8225 13:38:59.990510 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8226 13:38:59.990563 == TX Byte 1 ==
8227 13:38:59.990615 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8228 13:38:59.990669 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8229 13:38:59.990721 ==
8230 13:38:59.990970 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 13:38:59.991134 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8232 13:38:59.991266 ==
8233 13:38:59.991395
8234 13:38:59.991533 TX Vref early break, caculate TX vref
8235 13:38:59.991665 TX Vref=16, minBit 3, minWin=21, winSum=369
8236 13:38:59.991797 TX Vref=18, minBit 3, minWin=21, winSum=377
8237 13:38:59.991928 TX Vref=20, minBit 1, minWin=22, winSum=383
8238 13:38:59.992068 TX Vref=22, minBit 0, minWin=23, winSum=394
8239 13:38:59.992205 TX Vref=24, minBit 0, minWin=24, winSum=403
8240 13:38:59.992262 TX Vref=26, minBit 3, minWin=24, winSum=414
8241 13:38:59.992318 TX Vref=28, minBit 3, minWin=24, winSum=410
8242 13:38:59.992371 TX Vref=30, minBit 3, minWin=24, winSum=404
8243 13:38:59.992425 TX Vref=32, minBit 3, minWin=23, winSum=397
8244 13:38:59.992484 TX Vref=34, minBit 1, minWin=23, winSum=388
8245 13:38:59.992538 [TxChooseVref] Worse bit 3, Min win 24, Win sum 414, Final Vref 26
8246 13:38:59.992592
8247 13:38:59.992645 Final TX Range 0 Vref 26
8248 13:38:59.992698
8249 13:38:59.992751 ==
8250 13:38:59.992804 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 13:38:59.992856 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8252 13:38:59.992909 ==
8253 13:38:59.992962
8254 13:38:59.993051
8255 13:38:59.993104 TX Vref Scan disable
8256 13:38:59.993157 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8257 13:38:59.993210 == TX Byte 0 ==
8258 13:38:59.993262 u2DelayCellOfst[0]=14 cells (4 PI)
8259 13:38:59.993343 u2DelayCellOfst[1]=10 cells (3 PI)
8260 13:38:59.993411 u2DelayCellOfst[2]=0 cells (0 PI)
8261 13:38:59.993464 u2DelayCellOfst[3]=3 cells (1 PI)
8262 13:38:59.993523 u2DelayCellOfst[4]=7 cells (2 PI)
8263 13:38:59.993575 u2DelayCellOfst[5]=14 cells (4 PI)
8264 13:38:59.993628 u2DelayCellOfst[6]=14 cells (4 PI)
8265 13:38:59.993700 u2DelayCellOfst[7]=3 cells (1 PI)
8266 13:38:59.993755 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8267 13:38:59.993808 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8268 13:38:59.993861 == TX Byte 1 ==
8269 13:38:59.993914 u2DelayCellOfst[8]=0 cells (0 PI)
8270 13:38:59.993967 u2DelayCellOfst[9]=3 cells (1 PI)
8271 13:38:59.994020 u2DelayCellOfst[10]=7 cells (2 PI)
8272 13:38:59.994079 u2DelayCellOfst[11]=0 cells (0 PI)
8273 13:38:59.994161 u2DelayCellOfst[12]=10 cells (3 PI)
8274 13:38:59.994214 u2DelayCellOfst[13]=14 cells (4 PI)
8275 13:38:59.994267 u2DelayCellOfst[14]=14 cells (4 PI)
8276 13:38:59.994320 u2DelayCellOfst[15]=14 cells (4 PI)
8277 13:38:59.994373 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8278 13:38:59.994426 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8279 13:38:59.994479 DramC Write-DBI on
8280 13:38:59.994532 ==
8281 13:38:59.994585 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 13:38:59.994644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8283 13:38:59.994698 ==
8284 13:38:59.994750
8285 13:38:59.994802
8286 13:38:59.994854 TX Vref Scan disable
8287 13:38:59.994907 == TX Byte 0 ==
8288 13:38:59.994959 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8289 13:38:59.995012 == TX Byte 1 ==
8290 13:38:59.995065 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8291 13:38:59.995122 DramC Write-DBI off
8292 13:38:59.995177
8293 13:38:59.995230 [DATLAT]
8294 13:38:59.995283 Freq=1600, CH1 RK0
8295 13:38:59.995335
8296 13:38:59.995388 DATLAT Default: 0xf
8297 13:38:59.995442 0, 0xFFFF, sum = 0
8298 13:38:59.995496 1, 0xFFFF, sum = 0
8299 13:38:59.995550 2, 0xFFFF, sum = 0
8300 13:38:59.995603 3, 0xFFFF, sum = 0
8301 13:38:59.995694 4, 0xFFFF, sum = 0
8302 13:38:59.995747 5, 0xFFFF, sum = 0
8303 13:38:59.995801 6, 0xFFFF, sum = 0
8304 13:38:59.995855 7, 0xFFFF, sum = 0
8305 13:38:59.995908 8, 0xFFFF, sum = 0
8306 13:38:59.995961 9, 0xFFFF, sum = 0
8307 13:38:59.996014 10, 0xFFFF, sum = 0
8308 13:38:59.996068 11, 0xFFFF, sum = 0
8309 13:38:59.996122 12, 0xFFF, sum = 0
8310 13:38:59.996181 13, 0x0, sum = 1
8311 13:38:59.996237 14, 0x0, sum = 2
8312 13:38:59.996290 15, 0x0, sum = 3
8313 13:38:59.996344 16, 0x0, sum = 4
8314 13:38:59.996397 best_step = 14
8315 13:38:59.996449
8316 13:38:59.996502 ==
8317 13:38:59.996555 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 13:38:59.996607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8319 13:38:59.996660 ==
8320 13:38:59.996713 RX Vref Scan: 1
8321 13:38:59.996772
8322 13:38:59.996825 Set Vref Range= 24 -> 127
8323 13:38:59.996877
8324 13:38:59.996930 RX Vref 24 -> 127, step: 1
8325 13:38:59.996983
8326 13:38:59.997035 RX Delay 3 -> 252, step: 4
8327 13:38:59.997087
8328 13:38:59.997139 Set Vref, RX VrefLevel [Byte0]: 24
8329 13:38:59.997192 [Byte1]: 24
8330 13:38:59.997245
8331 13:38:59.997326 Set Vref, RX VrefLevel [Byte0]: 25
8332 13:38:59.997401 [Byte1]: 25
8333 13:38:59.997464
8334 13:38:59.997517 Set Vref, RX VrefLevel [Byte0]: 26
8335 13:38:59.997570 [Byte1]: 26
8336 13:38:59.997623
8337 13:38:59.997675 Set Vref, RX VrefLevel [Byte0]: 27
8338 13:38:59.997728 [Byte1]: 27
8339 13:38:59.997781
8340 13:38:59.997840 Set Vref, RX VrefLevel [Byte0]: 28
8341 13:38:59.997893 [Byte1]: 28
8342 13:38:59.997945
8343 13:38:59.997997 Set Vref, RX VrefLevel [Byte0]: 29
8344 13:38:59.998050 [Byte1]: 29
8345 13:38:59.998103
8346 13:38:59.998155 Set Vref, RX VrefLevel [Byte0]: 30
8347 13:38:59.998207 [Byte1]: 30
8348 13:38:59.998260
8349 13:38:59.998312 Set Vref, RX VrefLevel [Byte0]: 31
8350 13:38:59.998369 [Byte1]: 31
8351 13:38:59.998423
8352 13:38:59.998475 Set Vref, RX VrefLevel [Byte0]: 32
8353 13:38:59.998528 [Byte1]: 32
8354 13:38:59.998580
8355 13:38:59.998632 Set Vref, RX VrefLevel [Byte0]: 33
8356 13:38:59.998684 [Byte1]: 33
8357 13:38:59.998736
8358 13:38:59.998788 Set Vref, RX VrefLevel [Byte0]: 34
8359 13:38:59.998840 [Byte1]: 34
8360 13:38:59.998893
8361 13:38:59.998951 Set Vref, RX VrefLevel [Byte0]: 35
8362 13:38:59.999003 [Byte1]: 35
8363 13:38:59.999055
8364 13:38:59.999107 Set Vref, RX VrefLevel [Byte0]: 36
8365 13:38:59.999159 [Byte1]: 36
8366 13:38:59.999211
8367 13:38:59.999263 Set Vref, RX VrefLevel [Byte0]: 37
8368 13:38:59.999315 [Byte1]: 37
8369 13:38:59.999366
8370 13:38:59.999418 Set Vref, RX VrefLevel [Byte0]: 38
8371 13:38:59.999476 [Byte1]: 38
8372 13:38:59.999529
8373 13:38:59.999581 Set Vref, RX VrefLevel [Byte0]: 39
8374 13:38:59.999633 [Byte1]: 39
8375 13:38:59.999685
8376 13:38:59.999737 Set Vref, RX VrefLevel [Byte0]: 40
8377 13:38:59.999789 [Byte1]: 40
8378 13:38:59.999841
8379 13:38:59.999893 Set Vref, RX VrefLevel [Byte0]: 41
8380 13:38:59.999945 [Byte1]: 41
8381 13:39:00.000019
8382 13:39:00.000086 Set Vref, RX VrefLevel [Byte0]: 42
8383 13:39:00.000155 [Byte1]: 42
8384 13:39:00.000253
8385 13:39:00.000304 Set Vref, RX VrefLevel [Byte0]: 43
8386 13:39:00.000356 [Byte1]: 43
8387 13:39:00.000408
8388 13:39:00.000657 Set Vref, RX VrefLevel [Byte0]: 44
8389 13:39:00.000798 [Byte1]: 44
8390 13:39:00.000928
8391 13:39:00.001077 Set Vref, RX VrefLevel [Byte0]: 45
8392 13:39:00.001251 [Byte1]: 45
8393 13:39:00.001356
8394 13:39:00.001421 Set Vref, RX VrefLevel [Byte0]: 46
8395 13:39:00.001477 [Byte1]: 46
8396 13:39:00.001530
8397 13:39:00.001583 Set Vref, RX VrefLevel [Byte0]: 47
8398 13:39:00.001645 [Byte1]: 47
8399 13:39:00.001699
8400 13:39:00.001751 Set Vref, RX VrefLevel [Byte0]: 48
8401 13:39:00.001804 [Byte1]: 48
8402 13:39:00.001859
8403 13:39:00.001912 Set Vref, RX VrefLevel [Byte0]: 49
8404 13:39:00.001967 [Byte1]: 49
8405 13:39:00.002020
8406 13:39:00.002073 Set Vref, RX VrefLevel [Byte0]: 50
8407 13:39:00.002132 [Byte1]: 50
8408 13:39:00.002185
8409 13:39:00.002237 Set Vref, RX VrefLevel [Byte0]: 51
8410 13:39:00.002289 [Byte1]: 51
8411 13:39:00.002342
8412 13:39:00.002394 Set Vref, RX VrefLevel [Byte0]: 52
8413 13:39:00.002446 [Byte1]: 52
8414 13:39:00.002498
8415 13:39:00.002550 Set Vref, RX VrefLevel [Byte0]: 53
8416 13:39:00.002602 [Byte1]: 53
8417 13:39:00.002660
8418 13:39:00.002713 Set Vref, RX VrefLevel [Byte0]: 54
8419 13:39:00.002765 [Byte1]: 54
8420 13:39:00.002818
8421 13:39:00.002870 Set Vref, RX VrefLevel [Byte0]: 55
8422 13:39:00.002922 [Byte1]: 55
8423 13:39:00.002975
8424 13:39:00.003027 Set Vref, RX VrefLevel [Byte0]: 56
8425 13:39:00.003080 [Byte1]: 56
8426 13:39:00.003132
8427 13:39:00.003183 Set Vref, RX VrefLevel [Byte0]: 57
8428 13:39:00.003243 [Byte1]: 57
8429 13:39:00.003296
8430 13:39:00.003347 Set Vref, RX VrefLevel [Byte0]: 58
8431 13:39:00.003399 [Byte1]: 58
8432 13:39:00.003452
8433 13:39:00.003503 Set Vref, RX VrefLevel [Byte0]: 59
8434 13:39:00.003555 [Byte1]: 59
8435 13:39:00.003608
8436 13:39:00.003660 Set Vref, RX VrefLevel [Byte0]: 60
8437 13:39:00.003712 [Byte1]: 60
8438 13:39:00.003771
8439 13:39:00.003824 Set Vref, RX VrefLevel [Byte0]: 61
8440 13:39:00.003876 [Byte1]: 61
8441 13:39:00.003928
8442 13:39:00.003980 Set Vref, RX VrefLevel [Byte0]: 62
8443 13:39:00.004033 [Byte1]: 62
8444 13:39:00.004085
8445 13:39:00.004136 Set Vref, RX VrefLevel [Byte0]: 63
8446 13:39:00.004190 [Byte1]: 63
8447 13:39:00.004243
8448 13:39:00.004312 Set Vref, RX VrefLevel [Byte0]: 64
8449 13:39:00.004378 [Byte1]: 64
8450 13:39:00.004435
8451 13:39:00.004488 Set Vref, RX VrefLevel [Byte0]: 65
8452 13:39:00.004540 [Byte1]: 65
8453 13:39:00.004593
8454 13:39:00.004645 Set Vref, RX VrefLevel [Byte0]: 66
8455 13:39:00.004697 [Byte1]: 66
8456 13:39:00.004750
8457 13:39:00.004801 Set Vref, RX VrefLevel [Byte0]: 67
8458 13:39:00.004854 [Byte1]: 67
8459 13:39:00.004906
8460 13:39:00.004959 Set Vref, RX VrefLevel [Byte0]: 68
8461 13:39:00.005017 [Byte1]: 68
8462 13:39:00.005070
8463 13:39:00.005122 Set Vref, RX VrefLevel [Byte0]: 69
8464 13:39:00.005175 [Byte1]: 69
8465 13:39:00.005226
8466 13:39:00.005335 Set Vref, RX VrefLevel [Byte0]: 70
8467 13:39:00.005406 [Byte1]: 70
8468 13:39:00.005459
8469 13:39:00.005511 Set Vref, RX VrefLevel [Byte0]: 71
8470 13:39:00.005571 [Byte1]: 71
8471 13:39:00.005624
8472 13:39:00.005676 Set Vref, RX VrefLevel [Byte0]: 72
8473 13:39:00.005729 [Byte1]: 72
8474 13:39:00.005781
8475 13:39:00.005833 Set Vref, RX VrefLevel [Byte0]: 73
8476 13:39:00.005886 [Byte1]: 73
8477 13:39:00.005938
8478 13:39:00.005990 Set Vref, RX VrefLevel [Byte0]: 74
8479 13:39:00.006043 [Byte1]: 74
8480 13:39:00.006100
8481 13:39:00.006154 Final RX Vref Byte 0 = 58 to rank0
8482 13:39:00.006207 Final RX Vref Byte 1 = 53 to rank0
8483 13:39:00.006260 Final RX Vref Byte 0 = 58 to rank1
8484 13:39:00.006313 Final RX Vref Byte 1 = 53 to rank1==
8485 13:39:00.006366 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 13:39:00.006419 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8487 13:39:00.006472 ==
8488 13:39:00.006526 DQS Delay:
8489 13:39:00.006578 DQS0 = 0, DQS1 = 0
8490 13:39:00.006637 DQM Delay:
8491 13:39:00.006690 DQM0 = 128, DQM1 = 124
8492 13:39:00.006743 DQ Delay:
8493 13:39:00.006795 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =126
8494 13:39:00.006847 DQ4 =128, DQ5 =140, DQ6 =134, DQ7 =126
8495 13:39:00.006900 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8496 13:39:00.006955 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8497 13:39:00.007008
8498 13:39:00.007060
8499 13:39:00.007113
8500 13:39:00.007170 [DramC_TX_OE_Calibration] TA2
8501 13:39:00.007224 Original DQ_B0 (3 6) =30, OEN = 27
8502 13:39:00.007277 Original DQ_B1 (3 6) =30, OEN = 27
8503 13:39:00.007330 24, 0x0, End_B0=24 End_B1=24
8504 13:39:00.007384 25, 0x0, End_B0=25 End_B1=25
8505 13:39:00.007437 26, 0x0, End_B0=26 End_B1=26
8506 13:39:00.007491 27, 0x0, End_B0=27 End_B1=27
8507 13:39:00.007544 28, 0x0, End_B0=28 End_B1=28
8508 13:39:00.007597 29, 0x0, End_B0=29 End_B1=29
8509 13:39:00.007650 30, 0x0, End_B0=30 End_B1=30
8510 13:39:00.007703 31, 0x4141, End_B0=30 End_B1=30
8511 13:39:00.007763 Byte0 end_step=30 best_step=27
8512 13:39:00.007815 Byte1 end_step=30 best_step=27
8513 13:39:00.007867 Byte0 TX OE(2T, 0.5T) = (3, 3)
8514 13:39:00.007920 Byte1 TX OE(2T, 0.5T) = (3, 3)
8515 13:39:00.007972
8516 13:39:00.008023
8517 13:39:00.008075 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8518 13:39:00.008128 CH1 RK0: MR19=303, MR18=2424
8519 13:39:00.008180 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8520 13:39:00.008233
8521 13:39:00.008291 ----->DramcWriteLeveling(PI) begin...
8522 13:39:00.008345 ==
8523 13:39:00.008397 Dram Type= 6, Freq= 0, CH_1, rank 1
8524 13:39:00.008450 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8525 13:39:00.008502 ==
8526 13:39:00.008554 Write leveling (Byte 0): 21 => 21
8527 13:39:00.008606 Write leveling (Byte 1): 18 => 18
8528 13:39:00.008658 DramcWriteLeveling(PI) end<-----
8529 13:39:00.008712
8530 13:39:00.008764 ==
8531 13:39:00.008822 Dram Type= 6, Freq= 0, CH_1, rank 1
8532 13:39:00.008875 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8533 13:39:00.008927 ==
8534 13:39:00.008979 [Gating] SW mode calibration
8535 13:39:00.009043 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8536 13:39:00.009098 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8537 13:39:00.009151 0 12 0 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
8538 13:39:00.009412 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8539 13:39:00.009551 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8540 13:39:00.009682 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8541 13:39:00.009812 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8542 13:39:00.010016 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8543 13:39:00.010076 0 12 24 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
8544 13:39:00.010131 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8545 13:39:00.010185 0 13 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
8546 13:39:00.010239 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8547 13:39:00.010292 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8548 13:39:00.010345 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8549 13:39:00.010406 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8550 13:39:00.010458 0 13 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8551 13:39:00.010511 0 13 24 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8552 13:39:00.010564 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8553 13:39:00.010616 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8554 13:39:00.010668 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8555 13:39:00.010721 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8556 13:39:00.010774 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8557 13:39:00.010826 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8558 13:39:00.010878 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8559 13:39:00.010971 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8560 13:39:00.011024 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8561 13:39:00.011076 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8562 13:39:00.011128 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 13:39:00.011180 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 13:39:00.011234 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 13:39:00.011286 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 13:39:00.011339 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 13:39:00.011391 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 13:39:00.011450 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 13:39:00.011503 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 13:39:00.011555 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 13:39:00.011608 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 13:39:00.011660 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 13:39:00.011713 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 13:39:00.011765 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8575 13:39:00.011817 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8576 13:39:00.011869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8577 13:39:00.011922 Total UI for P1: 0, mck2ui 16
8578 13:39:00.011981 best dqsien dly found for B0: ( 1, 0, 22)
8579 13:39:00.012034 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8580 13:39:00.012087 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8581 13:39:00.012140 Total UI for P1: 0, mck2ui 16
8582 13:39:00.012192 best dqsien dly found for B1: ( 1, 0, 30)
8583 13:39:00.012245 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8584 13:39:00.012298 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8585 13:39:00.012351
8586 13:39:00.012403 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8587 13:39:00.012456 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8588 13:39:00.012508 [Gating] SW calibration Done
8589 13:39:00.012590 ==
8590 13:39:00.012657 Dram Type= 6, Freq= 0, CH_1, rank 1
8591 13:39:00.012709 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8592 13:39:00.012762 ==
8593 13:39:00.012814 RX Vref Scan: 0
8594 13:39:00.012867
8595 13:39:00.012919 RX Vref 0 -> 0, step: 1
8596 13:39:00.012970
8597 13:39:00.013022 RX Delay 0 -> 252, step: 8
8598 13:39:00.013144 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8599 13:39:00.013197 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8600 13:39:00.013249 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8601 13:39:00.013327 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8602 13:39:00.013395 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8603 13:39:00.013448 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8604 13:39:00.013501 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8605 13:39:00.013553 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8606 13:39:00.013612 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8607 13:39:00.013665 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8608 13:39:00.013738 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8609 13:39:00.013792 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8610 13:39:00.013845 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8611 13:39:00.013914 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8612 13:39:00.013981 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8613 13:39:00.014033 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8614 13:39:00.014090 ==
8615 13:39:00.014145 Dram Type= 6, Freq= 0, CH_1, rank 1
8616 13:39:00.014197 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8617 13:39:00.014250 ==
8618 13:39:00.014302 DQS Delay:
8619 13:39:00.014355 DQS0 = 0, DQS1 = 0
8620 13:39:00.014407 DQM Delay:
8621 13:39:00.014460 DQM0 = 130, DQM1 = 125
8622 13:39:00.014512 DQ Delay:
8623 13:39:00.014565 DQ0 =131, DQ1 =123, DQ2 =115, DQ3 =131
8624 13:39:00.014624 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8625 13:39:00.014677 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8626 13:39:00.014729 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8627 13:39:00.014782
8628 13:39:00.014834
8629 13:39:00.014886 ==
8630 13:39:00.014939 Dram Type= 6, Freq= 0, CH_1, rank 1
8631 13:39:00.014992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8632 13:39:00.015045 ==
8633 13:39:00.015097
8634 13:39:00.015155
8635 13:39:00.015207 TX Vref Scan disable
8636 13:39:00.015260 == TX Byte 0 ==
8637 13:39:00.015312 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8638 13:39:00.015365 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8639 13:39:00.015418 == TX Byte 1 ==
8640 13:39:00.015470 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8641 13:39:00.015524 Update DQM dly =972 (3 ,6, 12) DQM OEN =(3 ,3)
8642 13:39:00.015577 ==
8643 13:39:00.015629 Dram Type= 6, Freq= 0, CH_1, rank 1
8644 13:39:00.015681 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8645 13:39:00.015740 ==
8646 13:39:00.015792
8647 13:39:00.016038 TX Vref early break, caculate TX vref
8648 13:39:00.016098 TX Vref=16, minBit 3, minWin=22, winSum=383
8649 13:39:00.016152 TX Vref=18, minBit 2, minWin=23, winSum=391
8650 13:39:00.016205 TX Vref=20, minBit 3, minWin=23, winSum=397
8651 13:39:00.016265 TX Vref=22, minBit 0, minWin=24, winSum=403
8652 13:39:00.016318 TX Vref=24, minBit 4, minWin=24, winSum=415
8653 13:39:00.016371 TX Vref=26, minBit 5, minWin=25, winSum=423
8654 13:39:00.016424 TX Vref=28, minBit 0, minWin=25, winSum=421
8655 13:39:00.016476 TX Vref=30, minBit 0, minWin=25, winSum=419
8656 13:39:00.016529 TX Vref=32, minBit 3, minWin=24, winSum=414
8657 13:39:00.016582 TX Vref=34, minBit 0, minWin=23, winSum=405
8658 13:39:00.016634 TX Vref=36, minBit 0, minWin=23, winSum=397
8659 13:39:00.016687 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 26
8660 13:39:00.016740
8661 13:39:00.016792 Final TX Range 0 Vref 26
8662 13:39:00.016845
8663 13:39:00.016903 ==
8664 13:39:00.016956 Dram Type= 6, Freq= 0, CH_1, rank 1
8665 13:39:00.017009 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8666 13:39:00.017062 ==
8667 13:39:00.017115
8668 13:39:00.017167
8669 13:39:00.017219 TX Vref Scan disable
8670 13:39:00.017272 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8671 13:39:00.017366 == TX Byte 0 ==
8672 13:39:00.017420 u2DelayCellOfst[0]=18 cells (5 PI)
8673 13:39:00.017479 u2DelayCellOfst[1]=10 cells (3 PI)
8674 13:39:00.017532 u2DelayCellOfst[2]=0 cells (0 PI)
8675 13:39:00.017584 u2DelayCellOfst[3]=7 cells (2 PI)
8676 13:39:00.017637 u2DelayCellOfst[4]=10 cells (3 PI)
8677 13:39:00.017705 u2DelayCellOfst[5]=18 cells (5 PI)
8678 13:39:00.017771 u2DelayCellOfst[6]=18 cells (5 PI)
8679 13:39:00.017823 u2DelayCellOfst[7]=7 cells (2 PI)
8680 13:39:00.017896 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8681 13:39:00.017958 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8682 13:39:00.018013 == TX Byte 1 ==
8683 13:39:00.018066 u2DelayCellOfst[8]=0 cells (0 PI)
8684 13:39:00.018118 u2DelayCellOfst[9]=7 cells (2 PI)
8685 13:39:00.018170 u2DelayCellOfst[10]=10 cells (3 PI)
8686 13:39:00.018222 u2DelayCellOfst[11]=3 cells (1 PI)
8687 13:39:00.018274 u2DelayCellOfst[12]=14 cells (4 PI)
8688 13:39:00.018326 u2DelayCellOfst[13]=18 cells (5 PI)
8689 13:39:00.018378 u2DelayCellOfst[14]=18 cells (5 PI)
8690 13:39:00.018431 u2DelayCellOfst[15]=18 cells (5 PI)
8691 13:39:00.018488 Update DQ dly =970 (3 ,6, 10) DQ OEN =(3 ,3)
8692 13:39:00.018542 Update DQM dly =972 (3 ,6, 12) DQM OEN =(3 ,3)
8693 13:39:00.018595 DramC Write-DBI on
8694 13:39:00.018647 ==
8695 13:39:00.018699 Dram Type= 6, Freq= 0, CH_1, rank 1
8696 13:39:00.018752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8697 13:39:00.018804 ==
8698 13:39:00.018856
8699 13:39:00.018908
8700 13:39:00.018960 TX Vref Scan disable
8701 13:39:00.019012 == TX Byte 0 ==
8702 13:39:00.019072 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8703 13:39:00.019124 == TX Byte 1 ==
8704 13:39:00.019176 Update DQM dly =714 (2 ,6, 10) DQM OEN =(3 ,3)
8705 13:39:00.019229 DramC Write-DBI off
8706 13:39:00.019281
8707 13:39:00.019333 [DATLAT]
8708 13:39:00.019385 Freq=1600, CH1 RK1
8709 13:39:00.019438
8710 13:39:00.019490 DATLAT Default: 0xe
8711 13:39:00.019542 0, 0xFFFF, sum = 0
8712 13:39:00.019602 1, 0xFFFF, sum = 0
8713 13:39:00.019656 2, 0xFFFF, sum = 0
8714 13:39:00.019709 3, 0xFFFF, sum = 0
8715 13:39:00.019763 4, 0xFFFF, sum = 0
8716 13:39:00.019816 5, 0xFFFF, sum = 0
8717 13:39:00.019869 6, 0xFFFF, sum = 0
8718 13:39:00.019922 7, 0xFFFF, sum = 0
8719 13:39:00.019976 8, 0xFFFF, sum = 0
8720 13:39:00.020028 9, 0xFFFF, sum = 0
8721 13:39:00.020082 10, 0xFFFF, sum = 0
8722 13:39:00.020142 11, 0xFFFF, sum = 0
8723 13:39:00.020197 12, 0xF7F, sum = 0
8724 13:39:00.020251 13, 0x0, sum = 1
8725 13:39:00.020305 14, 0x0, sum = 2
8726 13:39:00.020358 15, 0x0, sum = 3
8727 13:39:00.020411 16, 0x0, sum = 4
8728 13:39:00.020465 best_step = 14
8729 13:39:00.020517
8730 13:39:00.020569 ==
8731 13:39:00.020622 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 13:39:00.020681 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8733 13:39:00.020734 ==
8734 13:39:00.020787 RX Vref Scan: 0
8735 13:39:00.020842
8736 13:39:00.020895 RX Vref 0 -> 0, step: 1
8737 13:39:00.020948
8738 13:39:00.021001 RX Delay 3 -> 252, step: 4
8739 13:39:00.021053 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8740 13:39:00.021106 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8741 13:39:00.021159 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8742 13:39:00.021218 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8743 13:39:00.021271 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8744 13:39:00.021364 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8745 13:39:00.021417 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8746 13:39:00.021469 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8747 13:39:00.021522 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8748 13:39:00.021574 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8749 13:39:00.021626 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8750 13:39:00.021679 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8751 13:39:00.021738 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8752 13:39:00.021791 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8753 13:39:00.021843 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8754 13:39:00.021896 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8755 13:39:00.021948 ==
8756 13:39:00.022001 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 13:39:00.022068 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8758 13:39:00.022125 ==
8759 13:39:00.022177 DQS Delay:
8760 13:39:00.022229 DQS0 = 0, DQS1 = 0
8761 13:39:00.022289 DQM Delay:
8762 13:39:00.022342 DQM0 = 127, DQM1 = 122
8763 13:39:00.022395 DQ Delay:
8764 13:39:00.022448 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8765 13:39:00.022500 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8766 13:39:00.022553 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8767 13:39:00.022605 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8768 13:39:00.022657
8769 13:39:00.022709
8770 13:39:00.022761
8771 13:39:00.022820 [DramC_TX_OE_Calibration] TA2
8772 13:39:00.022873 Original DQ_B0 (3 6) =30, OEN = 27
8773 13:39:00.022927 Original DQ_B1 (3 6) =30, OEN = 27
8774 13:39:00.022979 24, 0x0, End_B0=24 End_B1=24
8775 13:39:00.023033 25, 0x0, End_B0=25 End_B1=25
8776 13:39:00.023087 26, 0x0, End_B0=26 End_B1=26
8777 13:39:00.023141 27, 0x0, End_B0=27 End_B1=27
8778 13:39:00.023194 28, 0x0, End_B0=28 End_B1=28
8779 13:39:00.023247 29, 0x0, End_B0=29 End_B1=29
8780 13:39:00.023335 30, 0x0, End_B0=30 End_B1=30
8781 13:39:00.023390 31, 0x4141, End_B0=30 End_B1=30
8782 13:39:00.023443 Byte0 end_step=30 best_step=27
8783 13:39:00.023496 Byte1 end_step=30 best_step=27
8784 13:39:00.023548 Byte0 TX OE(2T, 0.5T) = (3, 3)
8785 13:39:00.023600 Byte1 TX OE(2T, 0.5T) = (3, 3)
8786 13:39:00.023652
8787 13:39:00.023704
8788 13:39:00.023952 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8789 13:39:00.024168 CH1 RK1: MR19=303, MR18=1C1C
8790 13:39:00.024343 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8791 13:39:00.024542 [RxdqsGatingPostProcess] freq 1600
8792 13:39:00.024688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8793 13:39:00.024818 Pre-setting of DQS Precalculation
8794 13:39:00.024924 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8795 13:39:00.025039 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8796 13:39:00.025128 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8797 13:39:00.025212
8798 13:39:00.025319
8799 13:39:00.025392 [Calibration Summary] 3200 Mbps
8800 13:39:00.025453 CH 0, Rank 0
8801 13:39:00.025507 SW Impedance : PASS
8802 13:39:00.025562 DUTY Scan : NO K
8803 13:39:00.025616 ZQ Calibration : PASS
8804 13:39:00.025669 Jitter Meter : NO K
8805 13:39:00.025721 CBT Training : PASS
8806 13:39:00.025783 Write leveling : PASS
8807 13:39:00.025844 RX DQS gating : PASS
8808 13:39:00.025897 RX DQ/DQS(RDDQC) : PASS
8809 13:39:00.025974 TX DQ/DQS : PASS
8810 13:39:00.026058 RX DATLAT : PASS
8811 13:39:00.026113 RX DQ/DQS(Engine): PASS
8812 13:39:00.026167 TX OE : PASS
8813 13:39:00.026250 All Pass.
8814 13:39:00.026334
8815 13:39:00.026400 CH 0, Rank 1
8816 13:39:00.026458 SW Impedance : PASS
8817 13:39:00.026528 DUTY Scan : NO K
8818 13:39:00.026596 ZQ Calibration : PASS
8819 13:39:00.026648 Jitter Meter : NO K
8820 13:39:00.026701 CBT Training : PASS
8821 13:39:00.026754 Write leveling : PASS
8822 13:39:00.026806 RX DQS gating : PASS
8823 13:39:00.026858 RX DQ/DQS(RDDQC) : PASS
8824 13:39:00.026911 TX DQ/DQS : PASS
8825 13:39:00.026963 RX DATLAT : PASS
8826 13:39:00.027022 RX DQ/DQS(Engine): PASS
8827 13:39:00.027075 TX OE : PASS
8828 13:39:00.027128 All Pass.
8829 13:39:00.027180
8830 13:39:00.027292 CH 1, Rank 0
8831 13:39:00.027359 SW Impedance : PASS
8832 13:39:00.027412 DUTY Scan : NO K
8833 13:39:00.027464 ZQ Calibration : PASS
8834 13:39:00.027517 Jitter Meter : NO K
8835 13:39:00.027600 CBT Training : PASS
8836 13:39:00.027667 Write leveling : PASS
8837 13:39:00.027724 RX DQS gating : PASS
8838 13:39:00.027788 RX DQ/DQS(RDDQC) : PASS
8839 13:39:00.027841 TX DQ/DQS : PASS
8840 13:39:00.027893 RX DATLAT : PASS
8841 13:39:00.027946 RX DQ/DQS(Engine): PASS
8842 13:39:00.027997 TX OE : PASS
8843 13:39:00.028050 All Pass.
8844 13:39:00.028108
8845 13:39:00.028191 CH 1, Rank 1
8846 13:39:00.028245 SW Impedance : PASS
8847 13:39:00.028298 DUTY Scan : NO K
8848 13:39:00.028351 ZQ Calibration : PASS
8849 13:39:00.028403 Jitter Meter : NO K
8850 13:39:00.028455 CBT Training : PASS
8851 13:39:00.028507 Write leveling : PASS
8852 13:39:00.028560 RX DQS gating : PASS
8853 13:39:00.028611 RX DQ/DQS(RDDQC) : PASS
8854 13:39:00.028670 TX DQ/DQS : PASS
8855 13:39:00.028723 RX DATLAT : PASS
8856 13:39:00.028776 RX DQ/DQS(Engine): PASS
8857 13:39:00.028828 TX OE : PASS
8858 13:39:00.028880 All Pass.
8859 13:39:00.028933
8860 13:39:00.028985 DramC Write-DBI on
8861 13:39:00.029054 PER_BANK_REFRESH: Hybrid Mode
8862 13:39:00.029107 TX_TRACKING: ON
8863 13:39:00.029161 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8864 13:39:00.029223 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8865 13:39:00.029279 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8866 13:39:00.029355 [FAST_K] Save calibration result to emmc
8867 13:39:00.029408 sync common calibartion params.
8868 13:39:00.029461 sync cbt_mode0:0, 1:0
8869 13:39:00.029513 dram_init: ddr_geometry: 0
8870 13:39:00.029565 dram_init: ddr_geometry: 0
8871 13:39:00.029655 dram_init: ddr_geometry: 0
8872 13:39:00.029714 0:dram_rank_size:80000000
8873 13:39:00.029788 1:dram_rank_size:80000000
8874 13:39:00.029844 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8875 13:39:00.029898 DFS_SHUFFLE_HW_MODE: ON
8876 13:39:00.029950 dramc_set_vcore_voltage set vcore to 725000
8877 13:39:00.030003 Read voltage for 1600, 0
8878 13:39:00.030055 Vio18 = 0
8879 13:39:00.030107 Vcore = 725000
8880 13:39:00.030158 Vdram = 0
8881 13:39:00.030218 Vddq = 0
8882 13:39:00.030270 Vmddr = 0
8883 13:39:00.030323 switch to 3200 Mbps bootup
8884 13:39:00.030375 [DramcRunTimeConfig]
8885 13:39:00.030428 PHYPLL
8886 13:39:00.030480 DPM_CONTROL_AFTERK: ON
8887 13:39:00.030533 PER_BANK_REFRESH: ON
8888 13:39:00.030586 REFRESH_OVERHEAD_REDUCTION: ON
8889 13:39:00.030639 CMD_PICG_NEW_MODE: OFF
8890 13:39:00.030691 XRTWTW_NEW_MODE: ON
8891 13:39:00.030750 XRTRTR_NEW_MODE: ON
8892 13:39:00.030802 TX_TRACKING: ON
8893 13:39:00.030855 RDSEL_TRACKING: OFF
8894 13:39:00.030907 DQS Precalculation for DVFS: ON
8895 13:39:00.030960 RX_TRACKING: OFF
8896 13:39:00.031011 HW_GATING DBG: ON
8897 13:39:00.031064 ZQCS_ENABLE_LP4: ON
8898 13:39:00.031116 RX_PICG_NEW_MODE: ON
8899 13:39:00.031177 TX_PICG_NEW_MODE: ON
8900 13:39:00.031242 ENABLE_RX_DCM_DPHY: ON
8901 13:39:00.031296 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8902 13:39:00.031349 DUMMY_READ_FOR_TRACKING: OFF
8903 13:39:00.031401 !!! SPM_CONTROL_AFTERK: OFF
8904 13:39:00.031462 !!! SPM could not control APHY
8905 13:39:00.031515 IMPEDANCE_TRACKING: ON
8906 13:39:00.031567 TEMP_SENSOR: ON
8907 13:39:00.031619 HW_SAVE_FOR_SR: OFF
8908 13:39:00.031672 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8909 13:39:00.031723 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8910 13:39:00.031776 Read ODT Tracking: ON
8911 13:39:00.031835 Refresh Rate DeBounce: ON
8912 13:39:00.031888 DFS_NO_QUEUE_FLUSH: ON
8913 13:39:00.031940 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8914 13:39:00.031992 ENABLE_DFS_RUNTIME_MRW: OFF
8915 13:39:00.032045 DDR_RESERVE_NEW_MODE: ON
8916 13:39:00.032097 MR_CBT_SWITCH_FREQ: ON
8917 13:39:00.032149 =========================
8918 13:39:00.032202 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8919 13:39:00.032256 dram_init: ddr_geometry: 0
8920 13:39:00.032313 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8921 13:39:00.032368 dram_init: dram init end (result: 0)
8922 13:39:00.032421 DRAM-K: Full calibration passed in 23406 msecs
8923 13:39:00.032474 MRC: failed to locate region type 0.
8924 13:39:00.032527 DRAM rank0 size:0x80000000,
8925 13:39:00.032580 DRAM rank1 size=0x80000000
8926 13:39:00.032633 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8927 13:39:00.032747 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8928 13:39:00.033016 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8929 13:39:00.033090 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8930 13:39:00.033144 DRAM rank0 size:0x80000000,
8931 13:39:00.033197 DRAM rank1 size=0x80000000
8932 13:39:00.033250 CBMEM:
8933 13:39:00.033326 IMD: root @ 0xfffff000 254 entries.
8934 13:39:00.033419 IMD: root @ 0xffffec00 62 entries.
8935 13:39:00.033487 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8936 13:39:00.033540 WARNING: RO_VPD is uninitialized or empty.
8937 13:39:00.033593 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8938 13:39:00.033646 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8939 13:39:00.033699 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8940 13:39:00.033752 BS: romstage times (exec / console): total (unknown) / 22946 ms
8941 13:39:00.033805
8942 13:39:00.033857
8943 13:39:00.033915 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8944 13:39:00.033970 ARM64: Exception handlers installed.
8945 13:39:00.034022 ARM64: Testing exception
8946 13:39:00.034075 ARM64: Done test exception
8947 13:39:00.034128 Enumerating buses...
8948 13:39:00.034181 Show all devs... Before device enumeration.
8949 13:39:00.034233 Root Device: enabled 1
8950 13:39:00.034286 CPU_CLUSTER: 0: enabled 1
8951 13:39:00.034338 CPU: 00: enabled 1
8952 13:39:00.034390 Compare with tree...
8953 13:39:00.034448 Root Device: enabled 1
8954 13:39:00.034534 CPU_CLUSTER: 0: enabled 1
8955 13:39:00.034586 CPU: 00: enabled 1
8956 13:39:00.034658 Root Device scanning...
8957 13:39:00.034713 scan_static_bus for Root Device
8958 13:39:00.034784 CPU_CLUSTER: 0 enabled
8959 13:39:00.034838 scan_static_bus for Root Device done
8960 13:39:00.034890 scan_bus: bus Root Device finished in 8 msecs
8961 13:39:00.034943 done
8962 13:39:00.035003 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8963 13:39:00.035058 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8964 13:39:00.035111 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8965 13:39:00.035165 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8966 13:39:00.035218 Allocating resources...
8967 13:39:00.035271 Reading resources...
8968 13:39:00.035323 Root Device read_resources bus 0 link: 0
8969 13:39:00.035376 DRAM rank0 size:0x80000000,
8970 13:39:00.035428 DRAM rank1 size=0x80000000
8971 13:39:00.035487 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8972 13:39:00.035540 CPU: 00 missing read_resources
8973 13:39:00.035592 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8974 13:39:00.035645 Root Device read_resources bus 0 link: 0 done
8975 13:39:00.035698 Done reading resources.
8976 13:39:00.035749 Show resources in subtree (Root Device)...After reading.
8977 13:39:00.035802 Root Device child on link 0 CPU_CLUSTER: 0
8978 13:39:00.035855 CPU_CLUSTER: 0 child on link 0 CPU: 00
8979 13:39:00.035908 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8980 13:39:00.035962 CPU: 00
8981 13:39:00.036021 Root Device assign_resources, bus 0 link: 0
8982 13:39:00.036074 CPU_CLUSTER: 0 missing set_resources
8983 13:39:00.036127 Root Device assign_resources, bus 0 link: 0 done
8984 13:39:00.036179 Done setting resources.
8985 13:39:00.036232 Show resources in subtree (Root Device)...After assigning values.
8986 13:39:00.036285 Root Device child on link 0 CPU_CLUSTER: 0
8987 13:39:00.036337 CPU_CLUSTER: 0 child on link 0 CPU: 00
8988 13:39:00.036390 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8989 13:39:00.036443 CPU: 00
8990 13:39:00.036496 Done allocating resources.
8991 13:39:00.036554 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8992 13:39:00.036607 Enabling resources...
8993 13:39:00.036659 done.
8994 13:39:00.036711 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8995 13:39:00.036764 Initializing devices...
8996 13:39:00.036817 Root Device init
8997 13:39:00.036869 init hardware done!
8998 13:39:00.036921 0x00000018: ctrlr->caps
8999 13:39:00.376495 52.000 MHz: ctrlr->f_max
9000 13:39:00.376658 0.400 MHz: ctrlr->f_min
9001 13:39:00.376767 0x40ff8080: ctrlr->voltages
9002 13:39:00.376851 sclk: 390625
9003 13:39:00.376910 Bus Width = 1
9004 13:39:00.376996 sclk: 390625
9005 13:39:00.377051 Bus Width = 1
9006 13:39:00.377107 Early init status = 3
9007 13:39:00.377163 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9008 13:39:00.377219 in-header: 03 fc 00 00 01 00 00 00
9009 13:39:00.377274 in-data: 00
9010 13:39:00.377374 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9011 13:39:00.377431 in-header: 03 fd 00 00 00 00 00 00
9012 13:39:00.377484 in-data:
9013 13:39:00.377538 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9014 13:39:00.377592 in-header: 03 fc 00 00 01 00 00 00
9015 13:39:00.377645 in-data: 00
9016 13:39:00.377719 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9017 13:39:00.377775 in-header: 03 fd 00 00 00 00 00 00
9018 13:39:00.377835 in-data:
9019 13:39:00.377890 [SSUSB] Setting up USB HOST controller...
9020 13:39:00.377943 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9021 13:39:00.377997 [SSUSB] phy power-on done.
9022 13:39:00.378050 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9023 13:39:00.378104 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9024 13:39:00.378157 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9025 13:39:00.378210 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9026 13:39:00.378263 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9027 13:39:00.378317 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9028 13:39:00.378370 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9029 13:39:00.378429 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9030 13:39:00.378482 SPM: binary array size = 0x9dc
9031 13:39:00.378536 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9032 13:39:00.378806 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9033 13:39:00.378908 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9034 13:39:00.379028 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9035 13:39:00.379119 configure_display: Starting display init
9036 13:39:00.379195 anx7625_power_on_init: Init interface.
9037 13:39:00.379266 anx7625_disable_pd_protocol: Disabled PD feature.
9038 13:39:00.379335 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9039 13:39:00.379436 anx7625_start_dp_work: Secure OCM version=00
9040 13:39:00.379564 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9041 13:39:00.379638 sp_tx_get_edid_block: EDID Block = 1
9042 13:39:00.379695 Extracted contents:
9043 13:39:00.379750 header: 00 ff ff ff ff ff ff 00
9044 13:39:00.379806 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9045 13:39:00.379860 version: 01 04
9046 13:39:00.379916 basic params: 95 1f 11 78 0a
9047 13:39:00.379971 chroma info: 76 90 94 55 54 90 27 21 50 54
9048 13:39:00.380024 established: 00 00 00
9049 13:39:00.380090 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9050 13:39:00.380143 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9051 13:39:00.380196 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9052 13:39:00.380248 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9053 13:39:00.380301 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9054 13:39:00.380352 extensions: 00
9055 13:39:00.380405 checksum: fb
9056 13:39:00.380457
9057 13:39:00.380509 Manufacturer: IVO Model 57d Serial Number 0
9058 13:39:00.380589 Made week 0 of 2020
9059 13:39:00.380641 EDID version: 1.4
9060 13:39:00.380693 Digital display
9061 13:39:00.380761 6 bits per primary color channel
9062 13:39:00.380828 DisplayPort interface
9063 13:39:00.380881 Maximum image size: 31 cm x 17 cm
9064 13:39:00.380933 Gamma: 220%
9065 13:39:00.380985 Check DPMS levels
9066 13:39:00.381036 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9067 13:39:00.381105 First detailed timing is preferred timing
9068 13:39:00.381187 Established timings supported:
9069 13:39:00.381241 Standard timings supported:
9070 13:39:00.381302 Detailed timings
9071 13:39:00.381357 Hex of detail: 383680a07038204018303c0035ae10000019
9072 13:39:00.381411 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9073 13:39:00.381464 0780 0798 07c8 0820 hborder 0
9074 13:39:00.381531 0438 043b 0447 0458 vborder 0
9075 13:39:00.381614 -hsync -vsync
9076 13:39:00.381666 Did detailed timing
9077 13:39:00.381718 Hex of detail: 000000000000000000000000000000000000
9078 13:39:00.381770 Manufacturer-specified data, tag 0
9079 13:39:00.381821 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9080 13:39:00.381873 ASCII string: InfoVision
9081 13:39:00.381925 Hex of detail: 000000fe00523134304e574635205248200a
9082 13:39:00.381976 ASCII string: R140NWF5 RH
9083 13:39:00.382028 Checksum
9084 13:39:00.382079 Checksum: 0xfb (valid)
9085 13:39:00.382161 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9086 13:39:00.382214 DSI data_rate: 832800000 bps
9087 13:39:00.382266 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9088 13:39:00.382318 anx7625_parse_edid: pixelclock(138800).
9089 13:39:00.382370 hactive(1920), hsync(48), hfp(24), hbp(88)
9090 13:39:00.382422 vactive(1080), vsync(12), vfp(3), vbp(17)
9091 13:39:00.382474 anx7625_dsi_config: config dsi.
9092 13:39:00.382525 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9093 13:39:00.382577 anx7625_dsi_config: success to config DSI
9094 13:39:00.382648 anx7625_dp_start: MIPI phy setup OK.
9095 13:39:00.382713 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9096 13:39:00.382765 mtk_ddp_mode_set invalid vrefresh 60
9097 13:39:00.382817 main_disp_path_setup
9098 13:39:00.382872 ovl_layer_smi_id_en
9099 13:39:00.382960 ovl_layer_smi_id_en
9100 13:39:00.383053 ccorr_config
9101 13:39:00.383137 aal_config
9102 13:39:00.383257 gamma_config
9103 13:39:00.383313 postmask_config
9104 13:39:00.383367 dither_config
9105 13:39:00.383421 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9106 13:39:00.383474 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9107 13:39:00.383527 Root Device init finished in 552 msecs
9108 13:39:00.383580 CPU_CLUSTER: 0 init
9109 13:39:00.383633 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9110 13:39:00.383703 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9111 13:39:00.383769 APU_MBOX 0x190000b0 = 0x10001
9112 13:39:00.383822 APU_MBOX 0x190001b0 = 0x10001
9113 13:39:00.383874 APU_MBOX 0x190005b0 = 0x10001
9114 13:39:00.383926 APU_MBOX 0x190006b0 = 0x10001
9115 13:39:00.383978 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9116 13:39:00.384031 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9117 13:39:00.384084 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9118 13:39:00.384136 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9119 13:39:00.384205 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9120 13:39:00.384289 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9121 13:39:00.384343 CPU_CLUSTER: 0 init finished in 81 msecs
9122 13:39:00.384414 Devices initialized
9123 13:39:00.384479 Show all devs... After init.
9124 13:39:00.384541 Root Device: enabled 1
9125 13:39:00.384595 CPU_CLUSTER: 0: enabled 1
9126 13:39:00.384648 CPU: 00: enabled 1
9127 13:39:00.384715 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9128 13:39:00.384769 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9129 13:39:00.384821 ELOG: NV offset 0x57f000 size 0x1000
9130 13:39:00.384874 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9131 13:39:00.384927 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9132 13:39:00.385193 ELOG: Event(17) added with size 13 at 2024-05-28 13:38:59 UTC
9133 13:39:00.385256 out: cmd=0x121: 03 db 21 01 00 00 00 00
9134 13:39:00.385337 in-header: 03 07 00 00 2c 00 00 00
9135 13:39:00.385392 in-data: 5c 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9136 13:39:00.385448 ELOG: Event(A1) added with size 10 at 2024-05-28 13:38:59 UTC
9137 13:39:00.385502 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9138 13:39:00.385555 ELOG: Event(A0) added with size 9 at 2024-05-28 13:38:59 UTC
9139 13:39:00.385608 elog_add_boot_reason: Logged dev mode boot
9140 13:39:00.385660 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9141 13:39:00.385742 Finalize devices...
9142 13:39:00.385795 Devices finalized
9143 13:39:00.385847 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9144 13:39:00.385899 Writing coreboot table at 0xffe64000
9145 13:39:00.385978 0. 000000000010a000-0000000000113fff: RAMSTAGE
9146 13:39:00.386061 1. 0000000040000000-00000000400fffff: RAM
9147 13:39:00.386147 2. 0000000040100000-000000004032afff: RAMSTAGE
9148 13:39:00.386220 3. 000000004032b000-00000000545fffff: RAM
9149 13:39:00.386287 4. 0000000054600000-000000005465ffff: BL31
9150 13:39:00.386340 5. 0000000054660000-00000000ffe63fff: RAM
9151 13:39:00.386392 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9152 13:39:00.386445 7. 0000000100000000-000000013fffffff: RAM
9153 13:39:00.386497 Passing 5 GPIOs to payload:
9154 13:39:00.386550 NAME | PORT | POLARITY | VALUE
9155 13:39:00.386620 EC in RW | 0x000000aa | low | undefined
9156 13:39:00.386703 EC interrupt | 0x00000005 | low | undefined
9157 13:39:00.386757 TPM interrupt | 0x000000ab | high | undefined
9158 13:39:00.386810 SD card detect | 0x00000011 | high | undefined
9159 13:39:00.386864 speaker enable | 0x00000093 | high | undefined
9160 13:39:00.386918 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9161 13:39:00.386972 in-header: 03 f4 00 00 02 00 00 00
9162 13:39:00.387038 in-data: 07 00
9163 13:39:00.387090 ADC[4]: Raw value=669327 ID=5
9164 13:39:00.387142 ADC[3]: Raw value=212549 ID=1
9165 13:39:00.387194 RAM Code: 0x51
9166 13:39:00.387261 ADC[6]: Raw value=74410 ID=0
9167 13:39:00.387326 ADC[5]: Raw value=211444 ID=1
9168 13:39:00.387378 SKU Code: 0x1
9169 13:39:00.387430 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4152
9170 13:39:00.387495 coreboot table: 964 bytes.
9171 13:39:00.387552 IMD ROOT 0. 0xfffff000 0x00001000
9172 13:39:00.387605 IMD SMALL 1. 0xffffe000 0x00001000
9173 13:39:00.387657 RO MCACHE 2. 0xffffc000 0x00001104
9174 13:39:00.387709 CONSOLE 3. 0xfff7c000 0x00080000
9175 13:39:00.387776 FMAP 4. 0xfff7b000 0x00000452
9176 13:39:00.387843 TIME STAMP 5. 0xfff7a000 0x00000910
9177 13:39:00.387915 VBOOT WORK 6. 0xfff66000 0x00014000
9178 13:39:00.388008 RAMOOPS 7. 0xffe66000 0x00100000
9179 13:39:00.388061 COREBOOT 8. 0xffe64000 0x00002000
9180 13:39:00.388114 IMD small region:
9181 13:39:00.388167 IMD ROOT 0. 0xffffec00 0x00000400
9182 13:39:00.388221 VPD 1. 0xffffeb80 0x0000006c
9183 13:39:00.388300 MMC STATUS 2. 0xffffeb60 0x00000004
9184 13:39:00.388366 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9185 13:39:00.388419 Probing TPM: done!
9186 13:39:00.388471 Connected to device vid:did:rid of 1ae0:0028:00
9187 13:39:00.388523 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9188 13:39:00.388606 Initialized TPM device CR50 revision 0
9189 13:39:00.388659 Checking cr50 for pending updates
9190 13:39:00.388710 Reading cr50 TPM mode
9191 13:39:00.388762 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9192 13:39:00.388830 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9193 13:39:00.388896 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9194 13:39:00.388949 Checking segment from ROM address 0x40100000
9195 13:39:00.389001 Checking segment from ROM address 0x4010001c
9196 13:39:00.389052 Loading segment from ROM address 0x40100000
9197 13:39:00.389104 code (compression=0)
9198 13:39:00.389156 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9199 13:39:00.389209 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9200 13:39:00.389261 it's not compressed!
9201 13:39:00.389339 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9202 13:39:00.389414 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9203 13:39:00.389504 Loading segment from ROM address 0x4010001c
9204 13:39:00.389593 Entry Point 0x80000000
9205 13:39:00.389684 Loaded segments
9206 13:39:00.389752 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9207 13:39:00.389809 Jumping to boot code at 0x80000000(0xffe64000)
9208 13:39:00.389864 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9209 13:39:00.389920 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9210 13:39:00.389974 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9211 13:39:00.390029 Checking segment from ROM address 0x40100000
9212 13:39:00.390083 Checking segment from ROM address 0x4010001c
9213 13:39:00.390137 Loading segment from ROM address 0x40100000
9214 13:39:00.390190 code (compression=1)
9215 13:39:00.390244 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9216 13:39:00.390298 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9217 13:39:00.390352 using LZMA
9218 13:39:00.390418 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9219 13:39:00.390661 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9220 13:39:00.390721 Loading segment from ROM address 0x4010001c
9221 13:39:00.390775 Entry Point 0x54601000
9222 13:39:00.390827 Loaded segments
9223 13:39:00.390893 NOTICE: MT8192 bl31_setup
9224 13:39:00.390979 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9225 13:39:00.391035 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9226 13:39:00.391088 WARNING: region 0:
9227 13:39:00.391141 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9228 13:39:00.391194 WARNING: region 1:
9229 13:39:00.391247 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9230 13:39:00.391299 WARNING: region 2:
9231 13:39:00.391352 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9232 13:39:00.391418 WARNING: region 3:
9233 13:39:00.391483 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9234 13:39:00.391559 WARNING: region 4:
9235 13:39:00.391652 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9236 13:39:00.391706 WARNING: region 5:
9237 13:39:00.391759 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9238 13:39:00.391813 WARNING: region 6:
9239 13:39:00.391866 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9240 13:39:00.391948 WARNING: region 7:
9241 13:39:00.392015 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9242 13:39:00.392067 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9243 13:39:00.392119 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9244 13:39:00.392172 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9245 13:39:00.392224 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9246 13:39:00.392276 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9247 13:39:00.392328 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9248 13:39:00.392381 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9249 13:39:00.392433 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9250 13:39:00.392514 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9251 13:39:00.392566 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9252 13:39:00.392635 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9253 13:39:00.392718 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9254 13:39:00.392772 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9255 13:39:00.392825 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9256 13:39:00.392878 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9257 13:39:00.392945 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9258 13:39:00.393014 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9259 13:39:00.393080 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9260 13:39:00.393132 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9261 13:39:00.393206 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9262 13:39:00.393312 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9263 13:39:00.393404 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9264 13:39:00.393459 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9265 13:39:00.393512 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9266 13:39:00.393595 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9267 13:39:00.393648 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9268 13:39:00.393700 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9269 13:39:00.393752 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9270 13:39:00.393804 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9271 13:39:00.393857 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9272 13:39:00.393909 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9273 13:39:00.393981 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9274 13:39:00.394049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9275 13:39:00.394116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9276 13:39:00.394168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9277 13:39:00.394220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9278 13:39:00.394272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9279 13:39:00.394325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9280 13:39:00.394377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9281 13:39:00.394430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9282 13:39:00.394482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9283 13:39:00.394534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9284 13:39:00.394615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9285 13:39:00.394667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9286 13:39:00.394719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9287 13:39:00.394771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9288 13:39:00.394824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9289 13:39:00.394892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9290 13:39:00.394959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9291 13:39:00.395027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9292 13:39:00.395080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9293 13:39:00.395133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9294 13:39:00.395204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9295 13:39:00.395260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9296 13:39:00.395328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9297 13:39:00.395380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9298 13:39:00.395433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9299 13:39:00.395524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9300 13:39:00.395596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9301 13:39:00.395651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9302 13:39:00.395705 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9303 13:39:00.395758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9304 13:39:00.396008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9305 13:39:00.396133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9306 13:39:00.396226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9307 13:39:00.396314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9308 13:39:00.396385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9309 13:39:00.396442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9310 13:39:00.396496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9311 13:39:00.396549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9312 13:39:00.396617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9313 13:39:00.396684 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9314 13:39:00.396737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9315 13:39:00.396789 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9316 13:39:00.396842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9317 13:39:00.396894 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9318 13:39:00.396946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9319 13:39:00.396999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9320 13:39:00.397050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9321 13:39:00.397103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9322 13:39:00.397170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9323 13:39:00.397223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9324 13:39:00.397277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9325 13:39:00.397352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9326 13:39:00.397406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9327 13:39:00.397458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9328 13:39:00.397509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9329 13:39:00.397562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9330 13:39:00.397661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9331 13:39:00.397716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9332 13:39:00.397768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9333 13:39:00.397821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9334 13:39:00.397889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9335 13:39:00.397956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9336 13:39:00.398023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9337 13:39:00.398076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9338 13:39:00.398129 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9339 13:39:00.398183 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9340 13:39:00.398248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9341 13:39:00.398301 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9342 13:39:00.398353 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9343 13:39:00.398405 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9344 13:39:00.398457 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9345 13:39:00.398509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9346 13:39:00.398561 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9347 13:39:00.398628 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9348 13:39:00.398694 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9349 13:39:00.398746 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9350 13:39:00.398797 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9351 13:39:00.398850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9352 13:39:00.398902 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9353 13:39:00.398953 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9354 13:39:00.399006 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9355 13:39:00.399058 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9356 13:39:00.399159 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9357 13:39:00.399231 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9358 13:39:00.399285 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9359 13:39:00.399339 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9360 13:39:00.399395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9361 13:39:00.399499 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9362 13:39:00.399585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9363 13:39:00.399671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9364 13:39:00.399726 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9365 13:39:00.399779 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9366 13:39:00.399833 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9367 13:39:00.399886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9368 13:39:00.399939 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9369 13:39:00.399993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9370 13:39:00.400046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9371 13:39:00.400099 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9372 13:39:00.400165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9373 13:39:00.400217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9374 13:39:00.400269 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9375 13:39:00.400320 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9376 13:39:00.400372 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9377 13:39:00.400423 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9378 13:39:00.400476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9379 13:39:00.400527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9380 13:39:00.400769 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9381 13:39:00.400830 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9382 13:39:00.400885 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9383 13:39:00.400959 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9384 13:39:00.401015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9385 13:39:00.401069 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9386 13:39:00.401157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9387 13:39:00.401253 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9388 13:39:00.401345 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9389 13:39:00.401401 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9390 13:39:00.401455 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9391 13:39:00.401523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9392 13:39:00.404558 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9393 13:39:00.407579 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9394 13:39:00.414166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9395 13:39:00.417627 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9396 13:39:00.424173 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9397 13:39:00.427929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9398 13:39:00.431111 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9399 13:39:00.437582 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9400 13:39:00.440898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9401 13:39:00.444426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9402 13:39:00.450950 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9403 13:39:00.454467 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9404 13:39:00.460696 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9405 13:39:00.464202 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9406 13:39:00.467607 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9407 13:39:00.474036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9408 13:39:00.477676 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9409 13:39:00.484202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9410 13:39:00.487152 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9411 13:39:00.490885 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9412 13:39:00.497595 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9413 13:39:00.500577 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9414 13:39:00.507113 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9415 13:39:00.510104 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9416 13:39:00.513647 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9417 13:39:00.520468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9418 13:39:00.524034 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9419 13:39:00.530581 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9420 13:39:00.533682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9421 13:39:00.536998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9422 13:39:00.543540 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9423 13:39:00.546798 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9424 13:39:00.553897 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9425 13:39:00.557053 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9426 13:39:00.559993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9427 13:39:00.567099 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9428 13:39:00.570688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9429 13:39:00.573175 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9430 13:39:00.579938 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9431 13:39:00.583544 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9432 13:39:00.589787 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9433 13:39:00.593389 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9434 13:39:00.599947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9435 13:39:00.602901 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9436 13:39:00.606467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9437 13:39:00.612896 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9438 13:39:00.616633 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9439 13:39:00.622801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9440 13:39:00.626386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9441 13:39:00.632828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9442 13:39:00.636416 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9443 13:39:00.639351 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9444 13:39:00.646369 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9445 13:39:00.649412 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9446 13:39:00.656404 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9447 13:39:00.659206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9448 13:39:00.666203 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9449 13:39:00.669171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9450 13:39:00.672589 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9451 13:39:00.679714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9452 13:39:00.682457 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9453 13:39:00.689165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9454 13:39:00.692796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9455 13:39:00.695763 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9456 13:39:00.702658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9457 13:39:00.705634 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9458 13:39:00.712840 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9459 13:39:00.715621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9460 13:39:00.722322 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9461 13:39:00.725907 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9462 13:39:00.729069 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9463 13:39:00.735472 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9464 13:39:00.739046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9465 13:39:00.745698 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9466 13:39:00.748550 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9467 13:39:00.755528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9468 13:39:00.758688 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9469 13:39:00.762248 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9470 13:39:00.768687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9471 13:39:00.772128 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9472 13:39:00.775510 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9473 13:39:00.778749 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9474 13:39:00.785144 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9475 13:39:00.788479 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9476 13:39:00.792388 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9477 13:39:00.798999 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9478 13:39:00.802191 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9479 13:39:00.805154 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9480 13:39:00.812373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9481 13:39:00.815386 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9482 13:39:00.818409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9483 13:39:00.825264 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9484 13:39:00.828357 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9485 13:39:00.832005 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9486 13:39:00.838427 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9487 13:39:00.841842 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9488 13:39:00.848826 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9489 13:39:00.851635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9490 13:39:00.855231 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9491 13:39:00.861746 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9492 13:39:00.864818 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9493 13:39:00.868332 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9494 13:39:00.874991 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9495 13:39:00.878616 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9496 13:39:00.881542 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9497 13:39:00.888388 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9498 13:39:00.891615 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9499 13:39:00.898337 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9500 13:39:00.901463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9501 13:39:00.904818 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9502 13:39:00.911230 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9503 13:39:00.914796 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9504 13:39:00.920902 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9505 13:39:00.924376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9506 13:39:00.928037 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9507 13:39:00.934088 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9508 13:39:00.937712 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9509 13:39:00.941172 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9510 13:39:00.948058 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9511 13:39:00.951026 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9512 13:39:00.954102 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9513 13:39:00.957590 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9514 13:39:00.964071 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9515 13:39:00.967710 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9516 13:39:00.970713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9517 13:39:00.974278 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9518 13:39:00.981148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9519 13:39:00.983977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9520 13:39:00.987056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9521 13:39:00.990690 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9522 13:39:00.997008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9523 13:39:01.000239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9524 13:39:01.003625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9525 13:39:01.010230 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9526 13:39:01.013762 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9527 13:39:01.020444 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9528 13:39:01.023820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9529 13:39:01.030269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9530 13:39:01.033820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9531 13:39:01.036854 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9532 13:39:01.043796 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9533 13:39:01.046738 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9534 13:39:01.053433 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9535 13:39:01.056993 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9536 13:39:01.059993 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9537 13:39:01.066562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9538 13:39:01.069950 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9539 13:39:01.076514 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9540 13:39:01.080207 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9541 13:39:01.083312 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9542 13:39:01.089784 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9543 13:39:01.092922 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9544 13:39:01.099957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9545 13:39:01.103366 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9546 13:39:01.109538 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9547 13:39:01.113115 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9548 13:39:01.116536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9549 13:39:01.123065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9550 13:39:01.125727 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9551 13:39:01.132570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9552 13:39:01.136252 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9553 13:39:01.142296 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9554 13:39:01.146070 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9555 13:39:01.149139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9556 13:39:01.156908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9557 13:39:01.159018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9558 13:39:01.165588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9559 13:39:01.168609 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9560 13:39:01.172093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9561 13:39:01.178707 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9562 13:39:01.182238 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9563 13:39:01.188972 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9564 13:39:01.192032 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9565 13:39:01.195572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9566 13:39:01.202070 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9567 13:39:01.205152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9568 13:39:01.211972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9569 13:39:01.215421 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9570 13:39:01.221678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9571 13:39:01.225018 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9572 13:39:01.228901 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9573 13:39:01.235509 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9574 13:39:01.238272 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9575 13:39:01.245220 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9576 13:39:01.248322 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9577 13:39:01.251840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9578 13:39:01.258395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9579 13:39:01.262084 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9580 13:39:01.268443 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9581 13:39:01.271827 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9582 13:39:01.274839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9583 13:39:01.281840 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9584 13:39:01.284718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9585 13:39:01.291185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9586 13:39:01.294804 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9587 13:39:01.300934 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9588 13:39:01.304500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9589 13:39:01.307561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9590 13:39:01.314743 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9591 13:39:01.317703 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9592 13:39:01.324432 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9593 13:39:01.327437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9594 13:39:01.334666 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9595 13:39:01.337545 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9596 13:39:01.340719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9597 13:39:01.347655 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9598 13:39:01.350858 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9599 13:39:01.357647 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9600 13:39:01.360630 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9601 13:39:01.367194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9602 13:39:01.370697 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9603 13:39:01.374201 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9604 13:39:01.380644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9605 13:39:01.384146 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9606 13:39:01.390531 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9607 13:39:01.393953 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9608 13:39:01.400602 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9609 13:39:01.403534 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9610 13:39:01.410141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9611 13:39:01.413775 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9612 13:39:01.416703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9613 13:39:01.423678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9614 13:39:01.426922 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9615 13:39:01.433543 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9616 13:39:01.437165 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9617 13:39:01.443248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9618 13:39:01.446729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9619 13:39:01.450085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9620 13:39:01.456451 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9621 13:39:01.460265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9622 13:39:01.466828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9623 13:39:01.469675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9624 13:39:01.476447 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9625 13:39:01.480112 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9626 13:39:01.486438 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9627 13:39:01.489552 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9628 13:39:01.493048 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9629 13:39:01.499638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9630 13:39:01.502697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9631 13:39:01.509793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9632 13:39:01.512649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9633 13:39:01.519265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9634 13:39:01.522620 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9635 13:39:01.526162 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9636 13:39:01.532366 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9637 13:39:01.535869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9638 13:39:01.542392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9639 13:39:01.545513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9640 13:39:01.552279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9641 13:39:01.555856 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9642 13:39:01.562411 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9643 13:39:01.565960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9644 13:39:01.569255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9645 13:39:01.575329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9646 13:39:01.578967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9647 13:39:01.585270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9648 13:39:01.589032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9649 13:39:01.595757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9650 13:39:01.598481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9651 13:39:01.605012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9652 13:39:01.608589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9653 13:39:01.615206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9654 13:39:01.618836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9655 13:39:01.624875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9656 13:39:01.628360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9657 13:39:01.634964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9658 13:39:01.638540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9659 13:39:01.644871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9660 13:39:01.648579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9661 13:39:01.651539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9662 13:39:01.658029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9663 13:39:01.661275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9664 13:39:01.668480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9665 13:39:01.671337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9666 13:39:01.678271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9667 13:39:01.681707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9668 13:39:01.688191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9669 13:39:01.694702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9670 13:39:01.697806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9671 13:39:01.704714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9672 13:39:01.708174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9673 13:39:01.714349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9674 13:39:01.717993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9675 13:39:01.724673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9676 13:39:01.727609 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9677 13:39:01.727703 INFO: [APUAPC] vio 0
9678 13:39:01.735277 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9679 13:39:01.738353 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9680 13:39:01.742025 INFO: [APUAPC] D0_APC_0: 0x400510
9681 13:39:01.744911 INFO: [APUAPC] D0_APC_1: 0x0
9682 13:39:01.748225 INFO: [APUAPC] D0_APC_2: 0x1540
9683 13:39:01.751746 INFO: [APUAPC] D0_APC_3: 0x0
9684 13:39:01.755358 INFO: [APUAPC] D1_APC_0: 0xffffffff
9685 13:39:01.758361 INFO: [APUAPC] D1_APC_1: 0xffffffff
9686 13:39:01.762102 INFO: [APUAPC] D1_APC_2: 0x3fffff
9687 13:39:01.764821 INFO: [APUAPC] D1_APC_3: 0x0
9688 13:39:01.768170 INFO: [APUAPC] D2_APC_0: 0xffffffff
9689 13:39:01.771824 INFO: [APUAPC] D2_APC_1: 0xffffffff
9690 13:39:01.774849 INFO: [APUAPC] D2_APC_2: 0x3fffff
9691 13:39:01.778276 INFO: [APUAPC] D2_APC_3: 0x0
9692 13:39:01.781816 INFO: [APUAPC] D3_APC_0: 0xffffffff
9693 13:39:01.784678 INFO: [APUAPC] D3_APC_1: 0xffffffff
9694 13:39:01.788296 INFO: [APUAPC] D3_APC_2: 0x3fffff
9695 13:39:01.791781 INFO: [APUAPC] D3_APC_3: 0x0
9696 13:39:01.795073 INFO: [APUAPC] D4_APC_0: 0xffffffff
9697 13:39:01.798149 INFO: [APUAPC] D4_APC_1: 0xffffffff
9698 13:39:01.801200 INFO: [APUAPC] D4_APC_2: 0x3fffff
9699 13:39:01.801284 INFO: [APUAPC] D4_APC_3: 0x0
9700 13:39:01.805050 INFO: [APUAPC] D5_APC_0: 0xffffffff
9701 13:39:01.811366 INFO: [APUAPC] D5_APC_1: 0xffffffff
9702 13:39:01.815107 INFO: [APUAPC] D5_APC_2: 0x3fffff
9703 13:39:01.815210 INFO: [APUAPC] D5_APC_3: 0x0
9704 13:39:01.818053 INFO: [APUAPC] D6_APC_0: 0xffffffff
9705 13:39:01.821679 INFO: [APUAPC] D6_APC_1: 0xffffffff
9706 13:39:01.824685 INFO: [APUAPC] D6_APC_2: 0x3fffff
9707 13:39:01.828210 INFO: [APUAPC] D6_APC_3: 0x0
9708 13:39:01.831358 INFO: [APUAPC] D7_APC_0: 0xffffffff
9709 13:39:01.834770 INFO: [APUAPC] D7_APC_1: 0xffffffff
9710 13:39:01.838237 INFO: [APUAPC] D7_APC_2: 0x3fffff
9711 13:39:01.841235 INFO: [APUAPC] D7_APC_3: 0x0
9712 13:39:01.844789 INFO: [APUAPC] D8_APC_0: 0xffffffff
9713 13:39:01.847977 INFO: [APUAPC] D8_APC_1: 0xffffffff
9714 13:39:01.851032 INFO: [APUAPC] D8_APC_2: 0x3fffff
9715 13:39:01.854371 INFO: [APUAPC] D8_APC_3: 0x0
9716 13:39:01.857819 INFO: [APUAPC] D9_APC_0: 0xffffffff
9717 13:39:01.861481 INFO: [APUAPC] D9_APC_1: 0xffffffff
9718 13:39:01.864473 INFO: [APUAPC] D9_APC_2: 0x3fffff
9719 13:39:01.867638 INFO: [APUAPC] D9_APC_3: 0x0
9720 13:39:01.871122 INFO: [APUAPC] D10_APC_0: 0xffffffff
9721 13:39:01.874719 INFO: [APUAPC] D10_APC_1: 0xffffffff
9722 13:39:01.878290 INFO: [APUAPC] D10_APC_2: 0x3fffff
9723 13:39:01.881622 INFO: [APUAPC] D10_APC_3: 0x0
9724 13:39:01.884635 INFO: [APUAPC] D11_APC_0: 0xffffffff
9725 13:39:01.887991 INFO: [APUAPC] D11_APC_1: 0xffffffff
9726 13:39:01.890947 INFO: [APUAPC] D11_APC_2: 0x3fffff
9727 13:39:01.894635 INFO: [APUAPC] D11_APC_3: 0x0
9728 13:39:01.898085 INFO: [APUAPC] D12_APC_0: 0xffffffff
9729 13:39:01.901079 INFO: [APUAPC] D12_APC_1: 0xffffffff
9730 13:39:01.904559 INFO: [APUAPC] D12_APC_2: 0x3fffff
9731 13:39:01.908193 INFO: [APUAPC] D12_APC_3: 0x0
9732 13:39:01.911251 INFO: [APUAPC] D13_APC_0: 0xffffffff
9733 13:39:01.914604 INFO: [APUAPC] D13_APC_1: 0xffffffff
9734 13:39:01.917484 INFO: [APUAPC] D13_APC_2: 0x3fffff
9735 13:39:01.920658 INFO: [APUAPC] D13_APC_3: 0x0
9736 13:39:01.923961 INFO: [APUAPC] D14_APC_0: 0xffffffff
9737 13:39:01.927579 INFO: [APUAPC] D14_APC_1: 0xffffffff
9738 13:39:01.930622 INFO: [APUAPC] D14_APC_2: 0x3fffff
9739 13:39:01.934255 INFO: [APUAPC] D14_APC_3: 0x0
9740 13:39:01.937257 INFO: [APUAPC] D15_APC_0: 0xffffffff
9741 13:39:01.940896 INFO: [APUAPC] D15_APC_1: 0xffffffff
9742 13:39:01.944332 INFO: [APUAPC] D15_APC_2: 0x3fffff
9743 13:39:01.947439 INFO: [APUAPC] D15_APC_3: 0x0
9744 13:39:01.951039 INFO: [APUAPC] APC_CON: 0x4
9745 13:39:01.954055 INFO: [NOCDAPC] D0_APC_0: 0x0
9746 13:39:01.957732 INFO: [NOCDAPC] D0_APC_1: 0x0
9747 13:39:01.960672 INFO: [NOCDAPC] D1_APC_0: 0x0
9748 13:39:01.964124 INFO: [NOCDAPC] D1_APC_1: 0xfff
9749 13:39:01.967164 INFO: [NOCDAPC] D2_APC_0: 0x0
9750 13:39:01.967251 INFO: [NOCDAPC] D2_APC_1: 0xfff
9751 13:39:01.970803 INFO: [NOCDAPC] D3_APC_0: 0x0
9752 13:39:01.973825 INFO: [NOCDAPC] D3_APC_1: 0xfff
9753 13:39:01.977339 INFO: [NOCDAPC] D4_APC_0: 0x0
9754 13:39:01.980422 INFO: [NOCDAPC] D4_APC_1: 0xfff
9755 13:39:01.984022 INFO: [NOCDAPC] D5_APC_0: 0x0
9756 13:39:01.987183 INFO: [NOCDAPC] D5_APC_1: 0xfff
9757 13:39:01.990688 INFO: [NOCDAPC] D6_APC_0: 0x0
9758 13:39:01.993830 INFO: [NOCDAPC] D6_APC_1: 0xfff
9759 13:39:01.997068 INFO: [NOCDAPC] D7_APC_0: 0x0
9760 13:39:02.000412 INFO: [NOCDAPC] D7_APC_1: 0xfff
9761 13:39:02.000523 INFO: [NOCDAPC] D8_APC_0: 0x0
9762 13:39:02.003906 INFO: [NOCDAPC] D8_APC_1: 0xfff
9763 13:39:02.007494 INFO: [NOCDAPC] D9_APC_0: 0x0
9764 13:39:02.010558 INFO: [NOCDAPC] D9_APC_1: 0xfff
9765 13:39:02.013519 INFO: [NOCDAPC] D10_APC_0: 0x0
9766 13:39:02.016953 INFO: [NOCDAPC] D10_APC_1: 0xfff
9767 13:39:02.020501 INFO: [NOCDAPC] D11_APC_0: 0x0
9768 13:39:02.023462 INFO: [NOCDAPC] D11_APC_1: 0xfff
9769 13:39:02.026879 INFO: [NOCDAPC] D12_APC_0: 0x0
9770 13:39:02.030137 INFO: [NOCDAPC] D12_APC_1: 0xfff
9771 13:39:02.033259 INFO: [NOCDAPC] D13_APC_0: 0x0
9772 13:39:02.036716 INFO: [NOCDAPC] D13_APC_1: 0xfff
9773 13:39:02.039830 INFO: [NOCDAPC] D14_APC_0: 0x0
9774 13:39:02.043333 INFO: [NOCDAPC] D14_APC_1: 0xfff
9775 13:39:02.046905 INFO: [NOCDAPC] D15_APC_0: 0x0
9776 13:39:02.046992 INFO: [NOCDAPC] D15_APC_1: 0xfff
9777 13:39:02.050030 INFO: [NOCDAPC] APC_CON: 0x4
9778 13:39:02.053637 INFO: [APUAPC] set_apusys_apc done
9779 13:39:02.056645 INFO: [DEVAPC] devapc_init done
9780 13:39:02.063182 INFO: GICv3 without legacy support detected.
9781 13:39:02.066679 INFO: ARM GICv3 driver initialized in EL3
9782 13:39:02.070156 INFO: Maximum SPI INTID supported: 639
9783 13:39:02.073074 INFO: BL31: Initializing runtime services
9784 13:39:02.079730 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9785 13:39:02.083172 INFO: SPM: enable CPC mode
9786 13:39:02.086326 INFO: mcdi ready for mcusys-off-idle and system suspend
9787 13:39:02.092724 INFO: BL31: Preparing for EL3 exit to normal world
9788 13:39:02.096241 INFO: Entry point address = 0x80000000
9789 13:39:02.096325 INFO: SPSR = 0x8
9790 13:39:02.103165
9791 13:39:02.103249
9792 13:39:02.103313
9793 13:39:02.106720 Starting depthcharge on Spherion...
9794 13:39:02.106805
9795 13:39:02.106871 Wipe memory regions:
9796 13:39:02.106932
9797 13:39:02.107567 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9798 13:39:02.107706 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9799 13:39:02.107825 Setting prompt string to ['asurada:']
9800 13:39:02.107930 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9801 13:39:02.109707 [0x00000040000000, 0x00000054600000)
9802 13:39:02.231905
9803 13:39:02.232040 [0x00000054660000, 0x00000080000000)
9804 13:39:02.492467
9805 13:39:02.492608 [0x000000821a7280, 0x000000ffe64000)
9806 13:39:03.237212
9807 13:39:03.237375 [0x00000100000000, 0x00000140000000)
9808 13:39:03.618110
9809 13:39:03.621549 Initializing XHCI USB controller at 0x11200000.
9810 13:39:04.659127
9811 13:39:04.662458 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9812 13:39:04.662549
9813 13:39:04.662635
9814 13:39:04.662936 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9816 13:39:04.763333 asurada: tftpboot 192.168.201.1 14063009/tftp-deploy-umrz_1vp/kernel/image.itb 14063009/tftp-deploy-umrz_1vp/kernel/cmdline
9817 13:39:04.763496 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9818 13:39:04.763603 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9819 13:39:04.768021 tftpboot 192.168.201.1 14063009/tftp-deploy-umrz_1vp/kernel/image.itp-deploy-umrz_1vp/kernel/cmdline
9820 13:39:04.768109
9821 13:39:04.768195 Waiting for link
9822 13:39:04.928215
9823 13:39:04.928367 R8152: Initializing
9824 13:39:04.928462
9825 13:39:04.931263 Version 9 (ocp_data = 6010)
9826 13:39:04.931349
9827 13:39:04.934800 R8152: Done initializing
9828 13:39:04.934887
9829 13:39:04.934972 Adding net device
9830 13:39:06.967612
9831 13:39:06.967754 done.
9832 13:39:06.967852
9833 13:39:06.967946 MAC: 00:e0:4c:68:03:bd
9834 13:39:06.968039
9835 13:39:06.970999 Sending DHCP discover... done.
9836 13:39:06.971117
9837 13:39:06.974308 Waiting for reply... done.
9838 13:39:06.974400
9839 13:39:06.977525 Sending DHCP request... done.
9840 13:39:06.977606
9841 13:39:06.981205 Waiting for reply... done.
9842 13:39:06.981281
9843 13:39:06.981395 My ip is 192.168.201.16
9844 13:39:06.981455
9845 13:39:06.984704 The DHCP server ip is 192.168.201.1
9846 13:39:06.984792
9847 13:39:06.991353 TFTP server IP predefined by user: 192.168.201.1
9848 13:39:06.991431
9849 13:39:06.998043 Bootfile predefined by user: 14063009/tftp-deploy-umrz_1vp/kernel/image.itb
9850 13:39:06.998121
9851 13:39:07.001027 Sending tftp read request... done.
9852 13:39:07.001101
9853 13:39:07.005029 Waiting for the transfer...
9854 13:39:07.005104
9855 13:39:07.253719 00000000 ################################################################
9856 13:39:07.253852
9857 13:39:07.502606 00080000 ################################################################
9858 13:39:07.502739
9859 13:39:07.753673 00100000 ################################################################
9860 13:39:07.753842
9861 13:39:08.001916 00180000 ################################################################
9862 13:39:08.002051
9863 13:39:08.252692 00200000 ################################################################
9864 13:39:08.252839
9865 13:39:08.502289 00280000 ################################################################
9866 13:39:08.502451
9867 13:39:08.751662 00300000 ################################################################
9868 13:39:08.751796
9869 13:39:09.003624 00380000 ################################################################
9870 13:39:09.003759
9871 13:39:09.267207 00400000 ################################################################
9872 13:39:09.267344
9873 13:39:09.519695 00480000 ################################################################
9874 13:39:09.519843
9875 13:39:09.767396 00500000 ################################################################
9876 13:39:09.767531
9877 13:39:10.015508 00580000 ################################################################
9878 13:39:10.015644
9879 13:39:10.263760 00600000 ################################################################
9880 13:39:10.263888
9881 13:39:10.513605 00680000 ################################################################
9882 13:39:10.513744
9883 13:39:10.762786 00700000 ################################################################
9884 13:39:10.762917
9885 13:39:11.015568 00780000 ################################################################
9886 13:39:11.015705
9887 13:39:11.264116 00800000 ################################################################
9888 13:39:11.264251
9889 13:39:11.513071 00880000 ################################################################
9890 13:39:11.513235
9891 13:39:11.763364 00900000 ################################################################
9892 13:39:11.763528
9893 13:39:12.014603 00980000 ################################################################
9894 13:39:12.014770
9895 13:39:12.271612 00a00000 ################################################################
9896 13:39:12.271762
9897 13:39:12.522965 00a80000 ################################################################
9898 13:39:12.523107
9899 13:39:12.783282 00b00000 ################################################################
9900 13:39:12.783456
9901 13:39:13.052968 00b80000 ################################################################
9902 13:39:13.053144
9903 13:39:13.326968 00c00000 ################################################################
9904 13:39:13.327142
9905 13:39:13.594484 00c80000 ################################################################
9906 13:39:13.594657
9907 13:39:13.857212 00d00000 ################################################################
9908 13:39:13.857410
9909 13:39:14.120131 00d80000 ################################################################
9910 13:39:14.120298
9911 13:39:14.380739 00e00000 ################################################################
9912 13:39:14.380911
9913 13:39:14.640508 00e80000 ################################################################
9914 13:39:14.640645
9915 13:39:14.893229 00f00000 ################################################################
9916 13:39:14.893409
9917 13:39:15.140997 00f80000 ################################################################
9918 13:39:15.141135
9919 13:39:15.394257 01000000 ################################################################
9920 13:39:15.394392
9921 13:39:15.650444 01080000 ################################################################
9922 13:39:15.650613
9923 13:39:15.907499 01100000 ################################################################
9924 13:39:15.907676
9925 13:39:16.159485 01180000 ################################################################
9926 13:39:16.159621
9927 13:39:16.409666 01200000 ################################################################
9928 13:39:16.409804
9929 13:39:16.676099 01280000 ################################################################
9930 13:39:16.676280
9931 13:39:16.936575 01300000 ################################################################
9932 13:39:16.936732
9933 13:39:17.189922 01380000 ################################################################
9934 13:39:17.190064
9935 13:39:17.446864 01400000 ################################################################
9936 13:39:17.447020
9937 13:39:17.719004 01480000 ################################################################
9938 13:39:17.719136
9939 13:39:17.981622 01500000 ################################################################
9940 13:39:17.981786
9941 13:39:18.243586 01580000 ################################################################
9942 13:39:18.243748
9943 13:39:18.509742 01600000 ################################################################
9944 13:39:18.509919
9945 13:39:18.777786 01680000 ################################################################
9946 13:39:18.777995
9947 13:39:19.051393 01700000 ################################################################
9948 13:39:19.051554
9949 13:39:19.314322 01780000 ################################################################
9950 13:39:19.314501
9951 13:39:19.573070 01800000 ################################################################
9952 13:39:19.573241
9953 13:39:19.820621 01880000 ################################################################
9954 13:39:19.820781
9955 13:39:20.076137 01900000 ################################################################
9956 13:39:20.076302
9957 13:39:20.336503 01980000 ################################################################
9958 13:39:20.336661
9959 13:39:20.596603 01a00000 ################################################################
9960 13:39:20.596738
9961 13:39:20.863548 01a80000 ################################################################
9962 13:39:20.863678
9963 13:39:21.143747 01b00000 ################################################################
9964 13:39:21.143914
9965 13:39:21.422519 01b80000 ################################################################
9966 13:39:21.422676
9967 13:39:21.701911 01c00000 ################################################################
9968 13:39:21.702052
9969 13:39:21.980829 01c80000 ################################################################
9970 13:39:21.980990
9971 13:39:22.258823 01d00000 ################################################################
9972 13:39:22.258986
9973 13:39:22.514181 01d80000 ################################################################
9974 13:39:22.514311
9975 13:39:22.702366 01e00000 ############################################### done.
9976 13:39:22.702499
9977 13:39:22.706010 The bootfile was 31840490 bytes long.
9978 13:39:22.706097
9979 13:39:22.708595 Sending tftp read request... done.
9980 13:39:22.708677
9981 13:39:22.708748 Waiting for the transfer...
9982 13:39:22.708809
9983 13:39:22.711964 00000000 # done.
9984 13:39:22.712046
9985 13:39:22.718567 Command line loaded dynamically from TFTP file: 14063009/tftp-deploy-umrz_1vp/kernel/cmdline
9986 13:39:22.718649
9987 13:39:22.741415 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9988 13:39:22.741535
9989 13:39:22.741671 Loading FIT.
9990 13:39:22.741774
9991 13:39:22.745035 Image ramdisk-1 has 18729896 bytes.
9992 13:39:22.745159
9993 13:39:22.748575 Image fdt-1 has 47258 bytes.
9994 13:39:22.748657
9995 13:39:22.751336 Image kernel-1 has 13061303 bytes.
9996 13:39:22.751418
9997 13:39:22.761152 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
9998 13:39:22.761284
9999 13:39:22.778142 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10000 13:39:22.778274
10001 13:39:22.784607 Choosing best match conf-1 for compat google,spherion.
10002 13:39:22.784688
10003 13:39:22.792272 Connected to device vid:did:rid of 1ae0:0028:00
10004 13:39:22.798816
10005 13:39:22.802434 tpm_get_response: command 0x17b, return code 0x0
10006 13:39:22.802516
10007 13:39:22.805531 ec_init: CrosEC protocol v3 supported (256, 248)
10008 13:39:22.810847
10009 13:39:22.813773 tpm_cleanup: add release locality here.
10010 13:39:22.813855
10011 13:39:22.813933 Shutting down all USB controllers.
10012 13:39:22.816937
10013 13:39:22.817018 Removing current net device
10014 13:39:22.817080
10015 13:39:22.823985 Exiting depthcharge with code 4 at timestamp: 48929419
10016 13:39:22.824067
10017 13:39:22.827214 LZMA decompressing kernel-1 to 0x821a6718
10018 13:39:22.827296
10019 13:39:22.830459 LZMA decompressing kernel-1 to 0x40000000
10020 13:39:24.440722
10021 13:39:24.441205 jumping to kernel
10022 13:39:24.442921 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10023 13:39:24.443454 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10024 13:39:24.443838 Setting prompt string to ['Linux version [0-9]']
10025 13:39:24.444184 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 13:39:24.444535 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10027 13:39:24.491182
10028 13:39:24.494368 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10029 13:39:24.498393 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10030 13:39:24.498869 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10031 13:39:24.499247 Setting prompt string to []
10032 13:39:24.499650 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10033 13:39:24.500047 Using line separator: #'\n'#
10034 13:39:24.500455 No login prompt set.
10035 13:39:24.500828 Parsing kernel messages
10036 13:39:24.501271 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10037 13:39:24.501844 [login-action] Waiting for messages, (timeout 00:04:04)
10038 13:39:24.502189 Waiting using forced prompt support (timeout 00:02:02)
10039 13:39:24.517859 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10040 13:39:24.520888 [ 0.000000] random: crng init done
10041 13:39:24.527478 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10042 13:39:24.530900 [ 0.000000] efi: UEFI not found.
10043 13:39:24.537527 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10044 13:39:24.544401 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10045 13:39:24.553695 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10046 13:39:24.563823 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10047 13:39:24.570287 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10048 13:39:24.576950 [ 0.000000] printk: bootconsole [mtk8250] enabled
10049 13:39:24.583369 [ 0.000000] NUMA: No NUMA configuration found
10050 13:39:24.589968 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10051 13:39:24.593385 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10052 13:39:24.596747 [ 0.000000] Zone ranges:
10053 13:39:24.603722 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10054 13:39:24.606842 [ 0.000000] DMA32 empty
10055 13:39:24.613593 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10056 13:39:24.617082 [ 0.000000] Movable zone start for each node
10057 13:39:24.620118 [ 0.000000] Early memory node ranges
10058 13:39:24.626698 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10059 13:39:24.633245 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10060 13:39:24.639906 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10061 13:39:24.646360 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10062 13:39:24.652955 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10063 13:39:24.659514 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10064 13:39:24.689962 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10065 13:39:24.696530 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10066 13:39:24.702881 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10067 13:39:24.706422 [ 0.000000] psci: probing for conduit method from DT.
10068 13:39:24.713283 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10069 13:39:24.716487 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10070 13:39:24.723167 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10071 13:39:24.726186 [ 0.000000] psci: SMC Calling Convention v1.2
10072 13:39:24.732773 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10073 13:39:24.736209 [ 0.000000] Detected VIPT I-cache on CPU0
10074 13:39:24.742832 [ 0.000000] CPU features: detected: GIC system register CPU interface
10075 13:39:24.749387 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10076 13:39:24.756424 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10077 13:39:24.762534 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10078 13:39:24.769600 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10079 13:39:24.779360 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10080 13:39:24.782390 [ 0.000000] alternatives: applying boot alternatives
10081 13:39:24.789345 [ 0.000000] Fallback order for Node 0: 0
10082 13:39:24.796095 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10083 13:39:24.798951 [ 0.000000] Policy zone: Normal
10084 13:39:24.822100 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10085 13:39:24.832376 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10086 13:39:24.841825 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10087 13:39:24.848439 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10088 13:39:24.855429 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10089 13:39:24.861761 <6>[ 0.000000] software IO TLB: area num 8.
10090 13:39:24.917003 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10091 13:39:24.997683 <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved)
10092 13:39:25.004777 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10093 13:39:25.011016 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10094 13:39:25.014280 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10095 13:39:25.021226 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10096 13:39:25.027637 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10097 13:39:25.031021 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10098 13:39:25.040575 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10099 13:39:25.047332 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10100 13:39:25.053842 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10101 13:39:25.060573 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10102 13:39:25.063463 <6>[ 0.000000] GICv3: 608 SPIs implemented
10103 13:39:25.067285 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10104 13:39:25.073427 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10105 13:39:25.076695 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10106 13:39:25.083170 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10107 13:39:25.096614 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10108 13:39:25.109885 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10109 13:39:25.116285 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10110 13:39:25.124246 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10111 13:39:25.137340 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10112 13:39:25.143995 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10113 13:39:25.151001 <6>[ 0.009172] Console: colour dummy device 80x25
10114 13:39:25.161069 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10115 13:39:25.167557 <6>[ 0.024340] pid_max: default: 32768 minimum: 301
10116 13:39:25.170586 <6>[ 0.029212] LSM: Security Framework initializing
10117 13:39:25.177734 <6>[ 0.034154] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10118 13:39:25.187472 <6>[ 0.041762] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10119 13:39:25.193668 <6>[ 0.051041] cblist_init_generic: Setting adjustable number of callback queues.
10120 13:39:25.200235 <6>[ 0.058484] cblist_init_generic: Setting shift to 3 and lim to 1.
10121 13:39:25.210103 <6>[ 0.064823] cblist_init_generic: Setting adjustable number of callback queues.
10122 13:39:25.213688 <6>[ 0.072296] cblist_init_generic: Setting shift to 3 and lim to 1.
10123 13:39:25.220356 <6>[ 0.078736] rcu: Hierarchical SRCU implementation.
10124 13:39:25.226927 <6>[ 0.083751] rcu: Max phase no-delay instances is 1000.
10125 13:39:25.233325 <6>[ 0.090775] EFI services will not be available.
10126 13:39:25.236730 <6>[ 0.095734] smp: Bringing up secondary CPUs ...
10127 13:39:25.244525 <6>[ 0.100785] Detected VIPT I-cache on CPU1
10128 13:39:25.250974 <6>[ 0.100854] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10129 13:39:25.257650 <6>[ 0.100884] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10130 13:39:25.261083 <6>[ 0.101219] Detected VIPT I-cache on CPU2
10131 13:39:25.267513 <6>[ 0.101266] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10132 13:39:25.277253 <6>[ 0.101282] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10133 13:39:25.280902 <6>[ 0.101542] Detected VIPT I-cache on CPU3
10134 13:39:25.287448 <6>[ 0.101590] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10135 13:39:25.294121 <6>[ 0.101603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10136 13:39:25.297548 <6>[ 0.101910] CPU features: detected: Spectre-v4
10137 13:39:25.303771 <6>[ 0.101916] CPU features: detected: Spectre-BHB
10138 13:39:25.307186 <6>[ 0.101921] Detected PIPT I-cache on CPU4
10139 13:39:25.313719 <6>[ 0.101977] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10140 13:39:25.320419 <6>[ 0.101993] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10141 13:39:25.326957 <6>[ 0.102289] Detected PIPT I-cache on CPU5
10142 13:39:25.333604 <6>[ 0.102351] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10143 13:39:25.340112 <6>[ 0.102367] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10144 13:39:25.343327 <6>[ 0.102649] Detected PIPT I-cache on CPU6
10145 13:39:25.349971 <6>[ 0.102710] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10146 13:39:25.356782 <6>[ 0.102726] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10147 13:39:25.363297 <6>[ 0.103025] Detected PIPT I-cache on CPU7
10148 13:39:25.369794 <6>[ 0.103091] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10149 13:39:25.376783 <6>[ 0.103106] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10150 13:39:25.379763 <6>[ 0.103153] smp: Brought up 1 node, 8 CPUs
10151 13:39:25.386720 <6>[ 0.244433] SMP: Total of 8 processors activated.
10152 13:39:25.389846 <6>[ 0.249354] CPU features: detected: 32-bit EL0 Support
10153 13:39:25.399536 <6>[ 0.254749] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10154 13:39:25.406386 <6>[ 0.263549] CPU features: detected: Common not Private translations
10155 13:39:25.413123 <6>[ 0.270065] CPU features: detected: CRC32 instructions
10156 13:39:25.415910 <6>[ 0.275450] CPU features: detected: RCpc load-acquire (LDAPR)
10157 13:39:25.422675 <6>[ 0.281410] CPU features: detected: LSE atomic instructions
10158 13:39:25.429280 <6>[ 0.287191] CPU features: detected: Privileged Access Never
10159 13:39:25.435939 <6>[ 0.292971] CPU features: detected: RAS Extension Support
10160 13:39:25.442693 <6>[ 0.298614] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10161 13:39:25.446222 <6>[ 0.305833] CPU: All CPU(s) started at EL2
10162 13:39:25.452382 <6>[ 0.310149] alternatives: applying system-wide alternatives
10163 13:39:25.461500 <6>[ 0.320179] devtmpfs: initialized
10164 13:39:25.476180 <6>[ 0.328490] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10165 13:39:25.483112 <6>[ 0.338443] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10166 13:39:25.489484 <6>[ 0.346473] pinctrl core: initialized pinctrl subsystem
10167 13:39:25.492969 <6>[ 0.353147] DMI not present or invalid.
10168 13:39:25.499563 <6>[ 0.357546] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10169 13:39:25.509783 <6>[ 0.364402] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10170 13:39:25.516278 <6>[ 0.371844] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10171 13:39:25.526103 <6>[ 0.379932] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10172 13:39:25.529300 <6>[ 0.388088] audit: initializing netlink subsys (disabled)
10173 13:39:25.539416 <5>[ 0.393783] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10174 13:39:25.546127 <6>[ 0.394489] thermal_sys: Registered thermal governor 'step_wise'
10175 13:39:25.552302 <6>[ 0.401749] thermal_sys: Registered thermal governor 'power_allocator'
10176 13:39:25.555897 <6>[ 0.408006] cpuidle: using governor menu
10177 13:39:25.562472 <6>[ 0.418967] NET: Registered PF_QIPCRTR protocol family
10178 13:39:25.569172 <6>[ 0.424447] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10179 13:39:25.572029 <6>[ 0.431548] ASID allocator initialised with 32768 entries
10180 13:39:25.579191 <6>[ 0.438117] Serial: AMBA PL011 UART driver
10181 13:39:25.588455 <4>[ 0.446958] Trying to register duplicate clock ID: 134
10182 13:39:25.647240 <6>[ 0.508764] KASLR enabled
10183 13:39:25.661844 <6>[ 0.516521] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10184 13:39:25.668376 <6>[ 0.523538] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10185 13:39:25.674577 <6>[ 0.530030] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10186 13:39:25.681186 <6>[ 0.537034] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10187 13:39:25.687817 <6>[ 0.543519] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10188 13:39:25.694869 <6>[ 0.550523] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10189 13:39:25.701033 <6>[ 0.557007] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10190 13:39:25.707616 <6>[ 0.564010] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10191 13:39:25.710815 <6>[ 0.571520] ACPI: Interpreter disabled.
10192 13:39:25.719349 <6>[ 0.577930] iommu: Default domain type: Translated
10193 13:39:25.726332 <6>[ 0.583043] iommu: DMA domain TLB invalidation policy: strict mode
10194 13:39:25.729266 <5>[ 0.589694] SCSI subsystem initialized
10195 13:39:25.736059 <6>[ 0.593859] usbcore: registered new interface driver usbfs
10196 13:39:25.742644 <6>[ 0.599592] usbcore: registered new interface driver hub
10197 13:39:25.745979 <6>[ 0.605145] usbcore: registered new device driver usb
10198 13:39:25.752937 <6>[ 0.611243] pps_core: LinuxPPS API ver. 1 registered
10199 13:39:25.762822 <6>[ 0.616434] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10200 13:39:25.766359 <6>[ 0.625777] PTP clock support registered
10201 13:39:25.769392 <6>[ 0.630018] EDAC MC: Ver: 3.0.0
10202 13:39:25.777105 <6>[ 0.635175] FPGA manager framework
10203 13:39:25.783628 <6>[ 0.638862] Advanced Linux Sound Architecture Driver Initialized.
10204 13:39:25.786665 <6>[ 0.645635] vgaarb: loaded
10205 13:39:25.793439 <6>[ 0.648795] clocksource: Switched to clocksource arch_sys_counter
10206 13:39:25.796582 <5>[ 0.655230] VFS: Disk quotas dquot_6.6.0
10207 13:39:25.803033 <6>[ 0.659413] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10208 13:39:25.806319 <6>[ 0.666605] pnp: PnP ACPI: disabled
10209 13:39:25.815067 <6>[ 0.673314] NET: Registered PF_INET protocol family
10210 13:39:25.821395 <6>[ 0.678694] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10211 13:39:25.833807 <6>[ 0.688699] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10212 13:39:25.843560 <6>[ 0.697488] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10213 13:39:25.849995 <6>[ 0.705456] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10214 13:39:25.856796 <6>[ 0.713858] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10215 13:39:25.867289 <6>[ 0.722509] TCP: Hash tables configured (established 32768 bind 32768)
10216 13:39:25.874495 <6>[ 0.729372] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10217 13:39:25.880554 <6>[ 0.736393] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10218 13:39:25.887122 <6>[ 0.743914] NET: Registered PF_UNIX/PF_LOCAL protocol family
10219 13:39:25.893586 <6>[ 0.750041] RPC: Registered named UNIX socket transport module.
10220 13:39:25.897336 <6>[ 0.756195] RPC: Registered udp transport module.
10221 13:39:25.903807 <6>[ 0.761129] RPC: Registered tcp transport module.
10222 13:39:25.910546 <6>[ 0.766061] RPC: Registered tcp NFSv4.1 backchannel transport module.
10223 13:39:25.913493 <6>[ 0.772728] PCI: CLS 0 bytes, default 64
10224 13:39:25.916767 <6>[ 0.777022] Unpacking initramfs...
10225 13:39:25.946438 <6>[ 0.801377] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10226 13:39:25.956039 <6>[ 0.810019] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10227 13:39:25.959779 <6>[ 0.818854] kvm [1]: IPA Size Limit: 40 bits
10228 13:39:25.966077 <6>[ 0.823377] kvm [1]: GICv3: no GICV resource entry
10229 13:39:25.969385 <6>[ 0.828399] kvm [1]: disabling GICv2 emulation
10230 13:39:25.976240 <6>[ 0.833084] kvm [1]: GIC system register CPU interface enabled
10231 13:39:25.979486 <6>[ 0.839249] kvm [1]: vgic interrupt IRQ18
10232 13:39:25.985935 <6>[ 0.843602] kvm [1]: VHE mode initialized successfully
10233 13:39:25.992238 <5>[ 0.850076] Initialise system trusted keyrings
10234 13:39:25.998903 <6>[ 0.854864] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10235 13:39:26.006890 <6>[ 0.864947] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10236 13:39:26.013486 <5>[ 0.871340] NFS: Registering the id_resolver key type
10237 13:39:26.016665 <5>[ 0.876658] Key type id_resolver registered
10238 13:39:26.022735 <5>[ 0.881073] Key type id_legacy registered
10239 13:39:26.029441 <6>[ 0.885350] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10240 13:39:26.035867 <6>[ 0.892273] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10241 13:39:26.042421 <6>[ 0.900001] 9p: Installing v9fs 9p2000 file system support
10242 13:39:26.079446 <5>[ 0.937803] Key type asymmetric registered
10243 13:39:26.082645 <5>[ 0.942132] Asymmetric key parser 'x509' registered
10244 13:39:26.092736 <6>[ 0.947293] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10245 13:39:26.095443 <6>[ 0.954936] io scheduler mq-deadline registered
10246 13:39:26.099056 <6>[ 0.959698] io scheduler kyber registered
10247 13:39:26.118225 <6>[ 0.976550] EINJ: ACPI disabled.
10248 13:39:26.150961 <4>[ 1.002718] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10249 13:39:26.160351 <4>[ 1.013369] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10250 13:39:26.175438 <6>[ 1.034212] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10251 13:39:26.183400 <6>[ 1.042256] printk: console [ttyS0] disabled
10252 13:39:26.211572 <6>[ 1.066890] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10253 13:39:26.218291 <6>[ 1.076359] printk: console [ttyS0] enabled
10254 13:39:26.221190 <6>[ 1.076359] printk: console [ttyS0] enabled
10255 13:39:26.227847 <6>[ 1.085255] printk: bootconsole [mtk8250] disabled
10256 13:39:26.231457 <6>[ 1.085255] printk: bootconsole [mtk8250] disabled
10257 13:39:26.237774 <6>[ 1.096277] SuperH (H)SCI(F) driver initialized
10258 13:39:26.241142 <6>[ 1.101533] msm_serial: driver initialized
10259 13:39:26.255236 <6>[ 1.110475] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10260 13:39:26.264862 <6>[ 1.119020] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10261 13:39:26.271578 <6>[ 1.127561] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10262 13:39:26.281614 <6>[ 1.136192] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10263 13:39:26.291359 <6>[ 1.144899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10264 13:39:26.297935 <6>[ 1.153618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10265 13:39:26.307937 <6>[ 1.162158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10266 13:39:26.314590 <6>[ 1.170953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10267 13:39:26.324791 <6>[ 1.179494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10268 13:39:26.336111 <6>[ 1.194799] loop: module loaded
10269 13:39:26.342996 <6>[ 1.200821] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10270 13:39:26.365263 <4>[ 1.224154] mtk-pmic-keys: Failed to locate of_node [id: -1]
10271 13:39:26.372557 <6>[ 1.230978] megasas: 07.719.03.00-rc1
10272 13:39:26.382306 <6>[ 1.240721] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10273 13:39:26.389883 <6>[ 1.248193] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10274 13:39:26.406737 <6>[ 1.264869] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10275 13:39:26.462777 <6>[ 1.314871] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10276 13:39:26.700593 <6>[ 1.559566] Freeing initrd memory: 18288K
10277 13:39:26.712449 <6>[ 1.570970] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10278 13:39:26.723421 <6>[ 1.582065] tun: Universal TUN/TAP device driver, 1.6
10279 13:39:26.726618 <6>[ 1.588134] thunder_xcv, ver 1.0
10280 13:39:26.730091 <6>[ 1.591641] thunder_bgx, ver 1.0
10281 13:39:26.733125 <6>[ 1.595136] nicpf, ver 1.0
10282 13:39:26.744064 <6>[ 1.599167] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10283 13:39:26.747107 <6>[ 1.606642] hns3: Copyright (c) 2017 Huawei Corporation.
10284 13:39:26.753655 <6>[ 1.612230] hclge is initializing
10285 13:39:26.757242 <6>[ 1.615812] e1000: Intel(R) PRO/1000 Network Driver
10286 13:39:26.763879 <6>[ 1.620941] e1000: Copyright (c) 1999-2006 Intel Corporation.
10287 13:39:26.766836 <6>[ 1.626953] e1000e: Intel(R) PRO/1000 Network Driver
10288 13:39:26.773504 <6>[ 1.632168] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10289 13:39:26.780542 <6>[ 1.638353] igb: Intel(R) Gigabit Ethernet Network Driver
10290 13:39:26.787180 <6>[ 1.644002] igb: Copyright (c) 2007-2014 Intel Corporation.
10291 13:39:26.793749 <6>[ 1.649840] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10292 13:39:26.800352 <6>[ 1.656359] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10293 13:39:26.803770 <6>[ 1.662819] sky2: driver version 1.30
10294 13:39:26.810329 <6>[ 1.667754] usbcore: registered new device driver r8152-cfgselector
10295 13:39:26.817139 <6>[ 1.674290] usbcore: registered new interface driver r8152
10296 13:39:26.820383 <6>[ 1.680115] VFIO - User Level meta-driver version: 0.3
10297 13:39:26.829519 <6>[ 1.688352] usbcore: registered new interface driver usb-storage
10298 13:39:26.836107 <6>[ 1.694803] usbcore: registered new device driver onboard-usb-hub
10299 13:39:26.845230 <6>[ 1.703975] mt6397-rtc mt6359-rtc: registered as rtc0
10300 13:39:26.855544 <6>[ 1.709435] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:39:27 UTC (1716903567)
10301 13:39:26.858597 <6>[ 1.719002] i2c_dev: i2c /dev entries driver
10302 13:39:26.875508 <6>[ 1.730821] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10303 13:39:26.882220 <4>[ 1.739557] cpu cpu0: supply cpu not found, using dummy regulator
10304 13:39:26.888882 <4>[ 1.745981] cpu cpu1: supply cpu not found, using dummy regulator
10305 13:39:26.895517 <4>[ 1.752381] cpu cpu2: supply cpu not found, using dummy regulator
10306 13:39:26.902141 <4>[ 1.758779] cpu cpu3: supply cpu not found, using dummy regulator
10307 13:39:26.908926 <4>[ 1.765200] cpu cpu4: supply cpu not found, using dummy regulator
10308 13:39:26.915225 <4>[ 1.771595] cpu cpu5: supply cpu not found, using dummy regulator
10309 13:39:26.921775 <4>[ 1.777991] cpu cpu6: supply cpu not found, using dummy regulator
10310 13:39:26.925312 <4>[ 1.784385] cpu cpu7: supply cpu not found, using dummy regulator
10311 13:39:26.946567 <6>[ 1.805005] cpu cpu0: EM: created perf domain
10312 13:39:26.949544 <6>[ 1.809919] cpu cpu4: EM: created perf domain
10313 13:39:26.956932 <6>[ 1.815487] sdhci: Secure Digital Host Controller Interface driver
10314 13:39:26.963154 <6>[ 1.821918] sdhci: Copyright(c) Pierre Ossman
10315 13:39:26.970267 <6>[ 1.826826] Synopsys Designware Multimedia Card Interface Driver
10316 13:39:26.976248 <6>[ 1.833424] sdhci-pltfm: SDHCI platform and OF driver helper
10317 13:39:26.979931 <6>[ 1.833450] mmc0: CQHCI version 5.10
10318 13:39:26.986323 <6>[ 1.843410] ledtrig-cpu: registered to indicate activity on CPUs
10319 13:39:26.993022 <6>[ 1.850404] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10320 13:39:26.999605 <6>[ 1.857429] usbcore: registered new interface driver usbhid
10321 13:39:27.003011 <6>[ 1.863250] usbhid: USB HID core driver
10322 13:39:27.009649 <6>[ 1.867450] spi_master spi0: will run message pump with realtime priority
10323 13:39:27.054958 <6>[ 1.907330] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10324 13:39:27.074812 <6>[ 1.923157] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10325 13:39:27.081609 <6>[ 1.938005] cros-ec-spi spi0.0: Chrome EC device registered
10326 13:39:27.085182 <6>[ 1.944137] mmc0: Command Queue Engine enabled
10327 13:39:27.091321 <6>[ 1.948922] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10328 13:39:27.097881 <6>[ 1.956207] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10329 13:39:27.107827 <6>[ 1.958372] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10330 13:39:27.111241 <6>[ 1.964717] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10331 13:39:27.117845 <6>[ 1.971249] NET: Registered PF_PACKET protocol family
10332 13:39:27.124314 <6>[ 1.977805] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10333 13:39:27.128053 <6>[ 1.981617] 9pnet: Installing 9P2000 support
10334 13:39:27.131252 <6>[ 1.987447] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10335 13:39:27.137617 <5>[ 1.991315] Key type dns_resolver registered
10336 13:39:27.144437 <6>[ 1.997198] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10337 13:39:27.147793 <6>[ 2.001551] registered taskstats version 1
10338 13:39:27.154311 <5>[ 2.011937] Loading compiled-in X.509 certificates
10339 13:39:27.182641 <4>[ 2.034558] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10340 13:39:27.192244 <4>[ 2.045276] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10341 13:39:27.206221 <6>[ 2.065271] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10342 13:39:27.213572 <6>[ 2.072172] xhci-mtk 11200000.usb: xHCI Host Controller
10343 13:39:27.220322 <6>[ 2.077686] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10344 13:39:27.229922 <6>[ 2.085530] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10345 13:39:27.237161 <6>[ 2.094947] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10346 13:39:27.243204 <6>[ 2.101005] xhci-mtk 11200000.usb: xHCI Host Controller
10347 13:39:27.249948 <6>[ 2.106483] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10348 13:39:27.256322 <6>[ 2.114130] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10349 13:39:27.263474 <6>[ 2.121762] hub 1-0:1.0: USB hub found
10350 13:39:27.266240 <6>[ 2.125778] hub 1-0:1.0: 1 port detected
10351 13:39:27.272869 <6>[ 2.130045] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10352 13:39:27.279978 <6>[ 2.138571] hub 2-0:1.0: USB hub found
10353 13:39:27.282971 <6>[ 2.142581] hub 2-0:1.0: 1 port detected
10354 13:39:27.290638 <6>[ 2.149415] mtk-msdc 11f70000.mmc: Got CD GPIO
10355 13:39:27.302738 <6>[ 2.158145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10356 13:39:27.309394 <6>[ 2.166210] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10357 13:39:27.319428 <4>[ 2.174104] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10358 13:39:27.329563 <6>[ 2.183638] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10359 13:39:27.336433 <6>[ 2.191715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10360 13:39:27.343085 <6>[ 2.199740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10361 13:39:27.352898 <6>[ 2.207660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10362 13:39:27.359406 <6>[ 2.215476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10363 13:39:27.369586 <6>[ 2.223291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10364 13:39:27.379581 <6>[ 2.233441] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10365 13:39:27.386434 <6>[ 2.241823] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10366 13:39:27.395926 <6>[ 2.250168] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10367 13:39:27.402743 <6>[ 2.258507] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10368 13:39:27.412730 <6>[ 2.266844] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10369 13:39:27.419420 <6>[ 2.275182] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10370 13:39:27.429562 <6>[ 2.283519] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10371 13:39:27.436142 <6>[ 2.291856] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10372 13:39:27.446263 <6>[ 2.300193] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10373 13:39:27.452811 <6>[ 2.308530] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10374 13:39:27.462531 <6>[ 2.316867] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10375 13:39:27.469451 <6>[ 2.325205] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10376 13:39:27.479251 <6>[ 2.333542] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10377 13:39:27.485618 <6>[ 2.341881] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10378 13:39:27.495662 <6>[ 2.350219] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10379 13:39:27.501998 <6>[ 2.358912] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10380 13:39:27.508584 <6>[ 2.366024] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10381 13:39:27.515195 <6>[ 2.372766] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10382 13:39:27.521764 <6>[ 2.379504] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10383 13:39:27.528335 <6>[ 2.386408] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10384 13:39:27.538353 <6>[ 2.393253] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10385 13:39:27.548285 <6>[ 2.402391] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10386 13:39:27.558435 <6>[ 2.411509] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10387 13:39:27.568514 <6>[ 2.420804] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10388 13:39:27.574867 <6>[ 2.430271] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10389 13:39:27.584762 <6>[ 2.439738] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10390 13:39:27.595176 <6>[ 2.448857] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10391 13:39:27.604380 <6>[ 2.458323] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10392 13:39:27.614236 <6>[ 2.467440] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10393 13:39:27.624175 <6>[ 2.476732] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10394 13:39:27.634534 <6>[ 2.486892] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10395 13:39:27.643895 <6>[ 2.498455] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10396 13:39:27.650494 <6>[ 2.507973] Trying to probe devices needed for running init ...
10397 13:39:27.697601 <6>[ 2.553062] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10398 13:39:27.852213 <6>[ 2.711030] hub 1-1:1.0: USB hub found
10399 13:39:27.855189 <6>[ 2.715512] hub 1-1:1.0: 4 ports detected
10400 13:39:27.865222 <6>[ 2.724152] hub 1-1:1.0: USB hub found
10401 13:39:27.868517 <6>[ 2.728490] hub 1-1:1.0: 4 ports detected
10402 13:39:27.978411 <6>[ 2.833401] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10403 13:39:28.004618 <6>[ 2.862974] hub 2-1:1.0: USB hub found
10404 13:39:28.007668 <6>[ 2.867467] hub 2-1:1.0: 3 ports detected
10405 13:39:28.017030 <6>[ 2.875533] hub 2-1:1.0: USB hub found
10406 13:39:28.020094 <6>[ 2.879983] hub 2-1:1.0: 3 ports detected
10407 13:39:28.193542 <6>[ 3.049093] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10408 13:39:28.326521 <6>[ 3.184592] hub 1-1.4:1.0: USB hub found
10409 13:39:28.329602 <6>[ 3.189237] hub 1-1.4:1.0: 2 ports detected
10410 13:39:28.338096 <6>[ 3.196326] hub 1-1.4:1.0: USB hub found
10411 13:39:28.341049 <6>[ 3.200920] hub 1-1.4:1.0: 2 ports detected
10412 13:39:28.406164 <6>[ 3.261230] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10413 13:39:28.514356 <6>[ 3.369621] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10414 13:39:28.550061 <4>[ 3.405023] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10415 13:39:28.559577 <4>[ 3.414112] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10416 13:39:28.603420 <6>[ 3.462649] r8152 2-1.3:1.0 eth0: v1.12.13
10417 13:39:28.637530 <6>[ 3.493107] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10418 13:39:28.829393 <6>[ 3.685125] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10419 13:39:30.210898 <6>[ 5.069579] r8152 2-1.3:1.0 eth0: carrier on
10420 13:39:32.421985 <5>[ 5.096879] Sending DHCP requests .., OK
10421 13:39:32.428666 <6>[ 7.285242] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10422 13:39:32.432199 <6>[ 7.293536] IP-Config: Complete:
10423 13:39:32.445276 <6>[ 7.297030] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10424 13:39:32.451939 <6>[ 7.307738] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10425 13:39:32.458409 <6>[ 7.316355] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10426 13:39:32.464805 <6>[ 7.316364] nameserver0=192.168.201.1
10427 13:39:32.467928 <6>[ 7.328495] clk: Disabling unused clocks
10428 13:39:32.471719 <6>[ 7.333990] ALSA device list:
10429 13:39:32.478466 <6>[ 7.337261] No soundcards found.
10430 13:39:32.485829 <6>[ 7.344623] Freeing unused kernel memory: 8512K
10431 13:39:32.488835 <6>[ 7.349655] Run /init as init process
10432 13:39:32.498405 Loading, please wait...
10433 13:39:32.526761 Starting systemd-udevd version 252.22-1~deb12u1
10434 13:39:32.784334 <6>[ 7.639974] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10435 13:39:32.797079 <6>[ 7.652542] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10436 13:39:32.807094 <6>[ 7.660473] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10437 13:39:32.813210 <6>[ 7.669427] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10438 13:39:32.826963 <4>[ 7.682209] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10439 13:39:32.829722 <6>[ 7.687649] mc: Linux media interface: v0.10
10440 13:39:32.837084 <6>[ 7.688193] remoteproc remoteproc0: scp is available
10441 13:39:32.839949 <6>[ 7.688252] remoteproc remoteproc0: powering up scp
10442 13:39:32.849767 <6>[ 7.688256] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10443 13:39:32.856401 <6>[ 7.688275] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10444 13:39:32.862895 <4>[ 7.693188] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10445 13:39:32.869494 <6>[ 7.714261] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10446 13:39:32.876096 <6>[ 7.714319] videodev: Linux video capture interface: v2.00
10447 13:39:32.883146 <3>[ 7.722046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10448 13:39:32.892852 <4>[ 7.740549] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10449 13:39:32.899488 <4>[ 7.740549] Fallback method does not support PEC.
10450 13:39:32.905848 <3>[ 7.748277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10451 13:39:32.916929 <6>[ 7.757540] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10452 13:39:32.926621 <6>[ 7.757940] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10453 13:39:32.933082 <3>[ 7.776741] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10454 13:39:32.943486 <3>[ 7.780145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10455 13:39:32.950110 <3>[ 7.806294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10456 13:39:32.956977 <6>[ 7.806404] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10457 13:39:32.966738 <3>[ 7.809797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10458 13:39:32.972986 <6>[ 7.814280] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10459 13:39:32.983037 <6>[ 7.814395] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10460 13:39:32.989669 <6>[ 7.814404] remoteproc remoteproc0: remote processor scp is now up
10461 13:39:32.996267 <3>[ 7.814417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10462 13:39:33.002692 <3>[ 7.814421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 13:39:33.012998 <3>[ 7.814428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10464 13:39:33.019122 <3>[ 7.814431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10465 13:39:33.028995 <3>[ 7.814463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10466 13:39:33.035753 <3>[ 7.814500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10467 13:39:33.045694 <3>[ 7.814503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10468 13:39:33.052439 <3>[ 7.814506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10469 13:39:33.062116 <3>[ 7.814528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10470 13:39:33.064912 <6>[ 7.821541] pci_bus 0000:00: root bus resource [bus 00-ff]
10471 13:39:33.075396 <3>[ 7.830288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 13:39:33.084991 <6>[ 7.832626] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10473 13:39:33.091620 <6>[ 7.837219] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10474 13:39:33.098424 <3>[ 7.845717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10475 13:39:33.107929 <3>[ 7.845727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 13:39:33.115204 <6>[ 7.847511] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10477 13:39:33.124612 <6>[ 7.849542] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10478 13:39:33.134460 <6>[ 7.852157] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10479 13:39:33.141129 <3>[ 7.860226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10480 13:39:33.147812 <3>[ 7.860256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10481 13:39:33.154453 <6>[ 7.868376] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10482 13:39:33.161022 <6>[ 7.877336] Bluetooth: Core ver 2.22
10483 13:39:33.167755 <6>[ 7.884576] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10484 13:39:33.171123 <6>[ 7.892896] NET: Registered PF_BLUETOOTH protocol family
10485 13:39:33.177928 <6>[ 7.900723] pci 0000:00:00.0: supports D1 D2
10486 13:39:33.184210 <6>[ 7.908732] Bluetooth: HCI device and connection manager initialized
10487 13:39:33.190922 <6>[ 7.909908] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10488 13:39:33.204442 <6>[ 7.911224] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10489 13:39:33.211045 <6>[ 7.911312] usbcore: registered new interface driver uvcvideo
10490 13:39:33.217673 <6>[ 7.916800] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10491 13:39:33.223943 <6>[ 7.917639] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10492 13:39:33.230362 <6>[ 7.924914] Bluetooth: HCI socket layer initialized
10493 13:39:33.236955 <6>[ 7.930751] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10494 13:39:33.240488 <6>[ 7.938749] Bluetooth: L2CAP socket layer initialized
10495 13:39:33.247227 <6>[ 7.948011] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10496 13:39:33.253449 <6>[ 7.948391] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10497 13:39:33.260064 <6>[ 7.955128] Bluetooth: SCO socket layer initialized
10498 13:39:33.266780 <6>[ 7.963200] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10499 13:39:33.273539 <6>[ 8.041968] usbcore: registered new interface driver btusb
10500 13:39:33.283067 <4>[ 8.042990] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10501 13:39:33.289904 <3>[ 8.043000] Bluetooth: hci0: Failed to load firmware file (-2)
10502 13:39:33.296528 <3>[ 8.043004] Bluetooth: hci0: Failed to set up firmware (-2)
10503 13:39:33.306698 <4>[ 8.043008] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10504 13:39:33.313369 <6>[ 8.048045] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10505 13:39:33.319902 <6>[ 8.177961] pci 0000:01:00.0: supports D1 D2
10506 13:39:33.326613 <6>[ 8.182480] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10507 13:39:33.345380 <6>[ 8.200941] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10508 13:39:33.351778 <6>[ 8.207842] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10509 13:39:33.358433 <6>[ 8.215923] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10510 13:39:33.368440 <6>[ 8.223921] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10511 13:39:33.375130 <6>[ 8.231921] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10512 13:39:33.384812 <6>[ 8.239921] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10513 13:39:33.387976 <6>[ 8.247920] pci 0000:00:00.0: PCI bridge to [bus 01]
10514 13:39:33.397938 <6>[ 8.253135] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10515 13:39:33.404480 <6>[ 8.261257] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10516 13:39:33.411460 <6>[ 8.268043] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10517 13:39:33.417824 <6>[ 8.274765] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10518 13:39:33.432769 <5>[ 8.288052] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10519 13:39:33.456360 <5>[ 8.312438] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10520 13:39:33.462914 <5>[ 8.319880] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10521 13:39:33.473396 <4>[ 8.328409] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10522 13:39:33.479321 <6>[ 8.337311] cfg80211: failed to load regulatory.db
10523 13:39:33.523426 <6>[ 8.379586] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10524 13:39:33.530134 <6>[ 8.387080] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10525 13:39:33.554569 <6>[ 8.413751] mt7921e 0000:01:00.0: ASIC revision: 79610010
10526 13:39:33.656376 <6>[ 8.512464] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10527 13:39:33.660054 <6>[ 8.512464]
10528 13:39:33.674650 Begin: Loading essential drivers ... done.
10529 13:39:33.677363 Begin: Running /scripts/init-premount ... done.
10530 13:39:33.684491 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10531 13:39:33.694481 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10532 13:39:33.697338 Device /sys/class/net/eth0 found
10533 13:39:33.697703 done.
10534 13:39:33.717983 Begin: Waiting up to 180 secs for any network device to become available ... done.
10535 13:39:33.769828 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10536 13:39:33.776742 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10537 13:39:33.783217 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10538 13:39:33.789414 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10539 13:39:33.796327 host : mt8192-asurada-spherion-r0-cbg-4
10540 13:39:33.802883 domain : lava-rack
10541 13:39:33.806298 rootserver: 192.168.201.1 rootpath:
10542 13:39:33.809279 filename :
10543 13:39:33.911033 done.
10544 13:39:33.917670 Begin: Running /scripts/nfs-bottom ... done.
10545 13:39:33.927714 Begin: Running /scripts/init-botto<6>[ 8.782979] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10546 13:39:33.933874 m ... done.
10547 13:39:35.232435 <6>[ 10.091969] NET: Registered PF_INET6 protocol family
10548 13:39:35.239616 <6>[ 10.099355] Segment Routing with IPv6
10549 13:39:35.242759 <6>[ 10.103325] In-situ OAM (IOAM) with IPv6
10550 13:39:35.405659 <30>[ 10.238886] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10551 13:39:35.412244 <30>[ 10.272047] systemd[1]: Detected architecture arm64.
10552 13:39:35.420199
10553 13:39:35.423635 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10554 13:39:35.423785
10555 13:39:35.450462 <30>[ 10.310085] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10556 13:39:36.494035 <30>[ 11.350164] systemd[1]: Queued start job for default target graphical.target.
10557 13:39:36.545944 <30>[ 11.402297] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10558 13:39:36.552247 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10559 13:39:36.574922 <30>[ 11.430846] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10560 13:39:36.584272 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10561 13:39:36.602589 <30>[ 11.458790] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10562 13:39:36.612084 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10563 13:39:36.630071 <30>[ 11.486479] systemd[1]: Created slice user.slice - User and Session Slice.
10564 13:39:36.636773 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10565 13:39:36.661255 <30>[ 11.513972] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10566 13:39:36.671012 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10567 13:39:36.688425 <30>[ 11.541319] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10568 13:39:36.694734 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10569 13:39:36.723401 <30>[ 11.569736] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10570 13:39:36.733652 <30>[ 11.589642] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10571 13:39:36.740063 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10572 13:39:36.757364 <30>[ 11.613469] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10573 13:39:36.767440 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10574 13:39:36.785566 <30>[ 11.641593] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10575 13:39:36.795264 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10576 13:39:36.809942 <30>[ 11.669611] systemd[1]: Reached target paths.target - Path Units.
10577 13:39:36.819851 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10578 13:39:36.837027 <30>[ 11.693458] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10579 13:39:36.843525 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10580 13:39:36.857410 <30>[ 11.717067] systemd[1]: Reached target slices.target - Slice Units.
10581 13:39:36.867427 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10582 13:39:36.881861 <30>[ 11.741574] systemd[1]: Reached target swap.target - Swaps.
10583 13:39:36.888222 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10584 13:39:36.909155 <30>[ 11.765596] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10585 13:39:36.919094 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10586 13:39:36.937274 <30>[ 11.793612] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10587 13:39:36.947359 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10588 13:39:36.968277 <30>[ 11.824735] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10589 13:39:36.978345 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10590 13:39:36.994252 <30>[ 11.850677] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10591 13:39:37.004252 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10592 13:39:37.021772 <30>[ 11.877829] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10593 13:39:37.028409 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10594 13:39:37.046629 <30>[ 11.902578] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10595 13:39:37.055995 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10596 13:39:37.075437 <30>[ 11.931965] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10597 13:39:37.085678 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10598 13:39:37.101907 <30>[ 11.958277] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10599 13:39:37.111881 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10600 13:39:37.161481 <30>[ 12.017443] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10601 13:39:37.167854 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10602 13:39:37.189266 <30>[ 12.045980] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10603 13:39:37.195790 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10604 13:39:37.244775 <30>[ 12.101514] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10605 13:39:37.251388 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10606 13:39:37.279973 <30>[ 12.129737] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10607 13:39:37.295497 <30>[ 12.151704] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10608 13:39:37.305203 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10609 13:39:37.326589 <30>[ 12.182650] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10610 13:39:37.332662 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10611 13:39:37.358815 <30>[ 12.215050] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10612 13:39:37.365257 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10613 13:39:37.390658 <30>[ 12.247070] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10614 13:39:37.400472 Startin<6>[ 12.256558] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10615 13:39:37.406995 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10616 13:39:37.461467 <30>[ 12.317896] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10617 13:39:37.471038 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10618 13:39:37.494643 <30>[ 12.351084] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10619 13:39:37.500991 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10620 13:39:37.526544 <30>[ 12.382820] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10621 13:39:37.533262 Startin<6>[ 12.391741] fuse: init (API version 7.37)
10622 13:39:37.539870 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10623 13:39:37.585830 <30>[ 12.442063] systemd[1]: Starting systemd-journald.service - Journal Service...
10624 13:39:37.592150 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10625 13:39:37.624127 <30>[ 12.480721] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10626 13:39:37.630535 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10627 13:39:37.656986 <30>[ 12.510583] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10628 13:39:37.663713 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10629 13:39:37.689839 <30>[ 12.546426] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10630 13:39:37.699506 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10631 13:39:37.722458 <30>[ 12.578809] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10632 13:39:37.732571 <3>[ 12.581576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 13:39:37.738788 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10634 13:39:37.761367 <3>[ 12.618160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10635 13:39:37.768718 <30>[ 12.621784] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10636 13:39:37.778615 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10637 13:39:37.797943 <30>[ 12.653821] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10638 13:39:37.804573 <3>[ 12.656724] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 13:39:37.814893 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10640 13:39:37.833711 <30>[ 12.689376] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10641 13:39:37.840198 <3>[ 12.689436] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 13:39:37.850089 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10643 13:39:37.868904 <3>[ 12.724607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10644 13:39:37.879052 <30>[ 12.734354] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10645 13:39:37.885691 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10646 13:39:37.897021 <3>[ 12.753509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 13:39:37.907528 <30>[ 12.763412] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10648 13:39:37.914059 <30>[ 12.771608] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10649 13:39:37.928276 [[0;32m OK [0m] Finished [0<3>[ 12.782814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 13:39:37.933702 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10651 13:39:37.947785 <30>[ 12.807250] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10652 13:39:37.958025 <3>[ 12.812457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 13:39:37.968297 <30>[ 12.815407] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10654 13:39:37.974330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10655 13:39:37.990780 <3>[ 12.847371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 13:39:38.002648 <30>[ 12.859076] systemd[1]: modprobe@drm.service: Deactivated successfully.
10657 13:39:38.009663 <30>[ 12.867001] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10658 13:39:38.026735 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 12.881251] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 13:39:38.027234 ule drm.
10660 13:39:38.047411 <30>[ 12.903679] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10661 13:39:38.058072 <30>[ 12.912455] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10662 13:39:38.064619 <3>[ 12.920407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 13:39:38.074024 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10664 13:39:38.095174 <30>[ 12.951256] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10665 13:39:38.101792 <30>[ 12.959224] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10666 13:39:38.112384 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10667 13:39:38.122306 <3>[ 12.976404] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10668 13:39:38.128512 <3>[ 12.977366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10669 13:39:38.145928 <4>[ 12.993981] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10670 13:39:38.152835 <30>[ 12.995545] systemd[1]: modprobe@loop.service: Deactivated successfully.
10671 13:39:38.159432 <3>[ 13.008608] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 13:39:38.170047 <3>[ 13.009607] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10673 13:39:38.179912 <3>[ 13.034616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10674 13:39:38.186609 <30>[ 13.034635] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10675 13:39:38.196255 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10676 13:39:38.216254 <30>[ 13.071317] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10677 13:39:38.222400 <3>[ 13.078381] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10678 13:39:38.232489 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10679 13:39:38.250835 <30>[ 13.106208] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10680 13:39:38.260946 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10681 13:39:38.278096 <30>[ 13.134591] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10682 13:39:38.288017 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10683 13:39:38.306171 <30>[ 13.162544] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10684 13:39:38.316138 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10685 13:39:38.334883 <30>[ 13.190911] systemd[1]: Reached target network-pre.target - Preparation for Network.
10686 13:39:38.340942 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10687 13:39:38.381340 <30>[ 13.237455] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10688 13:39:38.387526 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10689 13:39:38.413606 <30>[ 13.269893] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10690 13:39:38.423256 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10691 13:39:38.444525 <30>[ 13.297367] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10692 13:39:38.461328 <30>[ 13.311025] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10693 13:39:38.497371 <30>[ 13.353737] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10694 13:39:38.503819 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10695 13:39:38.531763 <30>[ 13.384639] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10696 13:39:38.545852 <30>[ 13.402321] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10697 13:39:38.552592 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10698 13:39:38.579557 <30>[ 13.436086] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10699 13:39:38.586350 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10700 13:39:38.617387 <30>[ 13.473491] systemd[1]: Started systemd-journald.service - Journal Service.
10701 13:39:38.623488 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10702 13:39:38.645895 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10703 13:39:38.669764 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10704 13:39:38.694510 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10705 13:39:38.718112 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10706 13:39:38.737937 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10707 13:39:38.781716 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10708 13:39:38.806375 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10709 13:39:38.841508 <46>[ 13.698023] systemd-journald[302]: Received client request to flush runtime journal.
10710 13:39:39.624649 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10711 13:39:39.640700 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10712 13:39:39.660123 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10713 13:39:39.969196 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10714 13:39:40.305923 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10715 13:39:40.330586 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10716 13:39:40.476294 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10717 13:39:40.543206 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10718 13:39:40.630703 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10719 13:39:40.913079 <6>[ 15.773490] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10720 13:39:40.930837 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10721 13:39:40.949285 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10722 13:39:41.018121 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10723 13:39:41.038892 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10724 13:39:41.082220 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10725 13:39:41.141035 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10726 13:39:41.165345 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10727 13:39:41.190408 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10728 13:39:41.210943 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10729 13:39:41.253228 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10730 13:39:41.306801 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10731 13:39:41.336745 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10732 13:39:41.361926 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10733 13:39:41.407802 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10734 13:39:41.425841 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10735 13:39:41.437937 <46>[ 16.294695] systemd-journald[302]: Time jumped backwards, rotating.
10736 13:39:41.447608 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10737 13:39:41.464463 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10738 13:39:41.488978 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10739 13:39:41.854658 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10740 13:39:41.872277 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10741 13:39:42.212304 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10742 13:39:42.540649 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10743 13:39:42.560231 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10744 13:39:42.825685 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10745 13:39:42.843856 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10746 13:39:42.860177 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10747 13:39:42.937671 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10748 13:39:42.971887 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10749 13:39:43.031909 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10750 13:39:43.057198 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10751 13:39:43.247357 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10752 13:39:43.292819 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10753 13:39:43.361933 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10754 13:39:43.381564 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10755 13:39:43.401911 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10756 13:39:43.439759 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10757 13:39:43.460890 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10758 13:39:43.483177 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10759 13:39:43.501538 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10760 13:39:43.553744 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10761 13:39:43.656407 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10762 13:39:43.739526
10763 13:39:43.743069 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10764 13:39:43.743596
10765 13:39:43.745893 debian-bookworm-arm64 login: root (automatic login)
10766 13:39:43.746414
10767 13:39:44.042646 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
10768 13:39:44.043246
10769 13:39:44.048986 The programs included with the Debian GNU/Linux system are free software;
10770 13:39:44.055981 the exact distribution terms for each program are described in the
10771 13:39:44.059386 individual files in /usr/share/doc/*/copyright.
10772 13:39:44.059951
10773 13:39:44.065953 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10774 13:39:44.069248 permitted by applicable law.
10775 13:39:45.040981 Matched prompt #10: / #
10777 13:39:45.041389 Setting prompt string to ['/ #']
10778 13:39:45.041490 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10780 13:39:45.041692 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10781 13:39:45.041790 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10782 13:39:45.041863 Setting prompt string to ['/ #']
10783 13:39:45.041923 Forcing a shell prompt, looking for ['/ #']
10785 13:39:45.092121 / #
10786 13:39:45.092243 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10787 13:39:45.092320 Waiting using forced prompt support (timeout 00:02:30)
10788 13:39:45.096755
10789 13:39:45.097016 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10790 13:39:45.097108 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10792 13:39:45.197458 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx'
10793 13:39:45.202554 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063009/extract-nfsrootfs-lt9sivnx'
10795 13:39:45.303104 / # export NFS_SERVER_IP='192.168.201.1'
10796 13:39:45.308401 export NFS_SERVER_IP='192.168.201.1'
10797 13:39:45.308691 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10798 13:39:45.308791 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10799 13:39:45.308880 end: 2 depthcharge-action (duration 00:01:17) [common]
10800 13:39:45.308968 start: 3 lava-test-retry (timeout 00:08:01) [common]
10801 13:39:45.309053 start: 3.1 lava-test-shell (timeout 00:08:01) [common]
10802 13:39:45.309130 Using namespace: common
10804 13:39:45.409452 / # #
10805 13:39:45.409612 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10806 13:39:45.415012 #
10807 13:39:45.415282 Using /lava-14063009
10809 13:39:45.515590 / # export SHELL=/bin/bash
10810 13:39:45.521091 export SHELL=/bin/bash
10812 13:39:45.621619 / # . /lava-14063009/environment
10813 13:39:45.627367 . /lava-14063009/environment
10815 13:39:45.732568 / # /lava-14063009/bin/lava-test-runner /lava-14063009/0
10816 13:39:45.732722 Test shell timeout: 10s (minimum of the action and connection timeout)
10817 13:39:45.738328 /lava-14063009/bin/lava-test-runner /lava-14063009/0
10818 13:39:45.968232 + export TESTRUN_ID=0_timesync-off
10819 13:39:45.971428 + TESTRUN_ID=0_timesync-off
10820 13:39:45.975333 + cd /lava-14063009/0/tests/0_timesync-off
10821 13:39:45.978422 ++ cat uuid
10822 13:39:45.981606 + UUID=14063009_1.6.2.3.1
10823 13:39:45.982042 + set +x
10824 13:39:45.988021 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14063009_1.6.2.3.1>
10825 13:39:45.988946 Received signal: <STARTRUN> 0_timesync-off 14063009_1.6.2.3.1
10826 13:39:45.989306 Starting test lava.0_timesync-off (14063009_1.6.2.3.1)
10827 13:39:45.989436 Skipping test definition patterns.
10828 13:39:45.991130 + systemctl stop systemd-timesyncd
10829 13:39:46.050346 + set +x
10830 13:39:46.053843 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14063009_1.6.2.3.1>
10831 13:39:46.054110 Received signal: <ENDRUN> 0_timesync-off 14063009_1.6.2.3.1
10832 13:39:46.054200 Ending use of test pattern.
10833 13:39:46.054263 Ending test lava.0_timesync-off (14063009_1.6.2.3.1), duration 0.06
10835 13:39:46.104971 + export TESTRUN_ID=1_kselftest-arm64
10836 13:39:46.105091 + TESTRUN_ID=1_kselftest-arm64
10837 13:39:46.111882 + cd /lava-14063009/0/tests/1_kselftest-arm64
10838 13:39:46.111992 ++ cat uuid
10839 13:39:46.114803 + UUID=14063009_1.6.2.3.5
10840 13:39:46.114911 + set +x
10841 13:39:46.118439 Received signal: <STARTRUN> 1_kselftest-arm64 14063009_1.6.2.3.5
10842 13:39:46.118538 Starting test lava.1_kselftest-arm64 (14063009_1.6.2.3.5)
10843 13:39:46.118656 Skipping test definition patterns.
10844 13:39:46.121910 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14063009_1.6.2.3.5>
10845 13:39:46.121987 + cd ./automated/linux/kselftest/
10846 13:39:46.147829 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10847 13:39:46.175967 INFO: install_deps skipped
10848 13:39:46.664909 --2024-05-28 13:39:46-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10849 13:39:46.683229 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10850 13:39:46.814635 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10851 13:39:46.943514 HTTP request sent, awaiting response... 200 OK
10852 13:39:46.946921 Length: 1642660 (1.6M) [application/octet-stream]
10853 13:39:46.950400 Saving to: 'kselftest_armhf.tar.gz'
10854 13:39:46.950476
10855 13:39:46.950540
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10858 13:39:47.894417 kselftest_armhf.tar 13%[=> ] 218.91K 425KB/s
10859 13:39:48.013215 kselftest_armhf.tar 49%[========> ] 786.88K 828KB/s
10860 13:39:48.019664 kselftest_armhf.tar 100%[===================>] 1.57M 1.46MB/s in 1.1s
10861 13:39:48.019751
10862 13:39:48.164577 2024-05-28 13:39:48 (1.46 MB/s) - 'kselftest_armhf.tar.gz' saved [1642660/1642660]
10863 13:39:48.164726
10864 13:39:51.904346 skiplist:
10865 13:39:51.907264 ========================================
10866 13:39:51.910791 ========================================
10867 13:39:51.950435 arm64:tags_test
10868 13:39:51.953839 arm64:run_tags_test.sh
10869 13:39:51.953924 arm64:fake_sigreturn_bad_magic
10870 13:39:51.957197 arm64:fake_sigreturn_bad_size
10871 13:39:51.960186 arm64:fake_sigreturn_bad_size_for_magic0
10872 13:39:51.963843 arm64:fake_sigreturn_duplicated_fpsimd
10873 13:39:51.966774 arm64:fake_sigreturn_misaligned_sp
10874 13:39:51.970203 arm64:fake_sigreturn_missing_fpsimd
10875 13:39:51.973820 arm64:fake_sigreturn_sme_change_vl
10876 13:39:51.976739 arm64:fake_sigreturn_sve_change_vl
10877 13:39:51.979931 arm64:mangle_pstate_invalid_compat_toggle
10878 13:39:51.983505 arm64:mangle_pstate_invalid_daif_bits
10879 13:39:51.986703 arm64:mangle_pstate_invalid_mode_el1h
10880 13:39:51.990094 arm64:mangle_pstate_invalid_mode_el1t
10881 13:39:51.993483 arm64:mangle_pstate_invalid_mode_el2h
10882 13:39:51.996505 arm64:mangle_pstate_invalid_mode_el2t
10883 13:39:51.999989 arm64:mangle_pstate_invalid_mode_el3h
10884 13:39:52.003292 arm64:mangle_pstate_invalid_mode_el3t
10885 13:39:52.006865 arm64:sme_trap_no_sm
10886 13:39:52.009830 arm64:sme_trap_non_streaming
10887 13:39:52.009925 arm64:sme_trap_za
10888 13:39:52.012872 arm64:sme_vl
10889 13:39:52.012954 arm64:ssve_regs
10890 13:39:52.016259 arm64:sve_regs
10891 13:39:52.016410 arm64:sve_vl
10892 13:39:52.016516 arm64:za_no_regs
10893 13:39:52.019794 arm64:za_regs
10894 13:39:52.019881 arm64:pac
10895 13:39:52.022828 arm64:fp-stress
10896 13:39:52.022911 arm64:sve-ptrace
10897 13:39:52.026410 arm64:sve-probe-vls
10898 13:39:52.026506 arm64:vec-syscfg
10899 13:39:52.026574 arm64:za-fork
10900 13:39:52.029500 arm64:za-ptrace
10901 13:39:52.033005 arm64:check_buffer_fill
10902 13:39:52.033087 arm64:check_child_memory
10903 13:39:52.036101 arm64:check_gcr_el1_cswitch
10904 13:39:52.039700 arm64:check_ksm_options
10905 13:39:52.039782 arm64:check_mmap_options
10906 13:39:52.042761 arm64:check_prctl
10907 13:39:52.046336 arm64:check_tags_inclusion
10908 13:39:52.046419 arm64:check_user_mem
10909 13:39:52.049842 arm64:btitest
10910 13:39:52.049960 arm64:nobtitest
10911 13:39:52.050041 arm64:hwcap
10912 13:39:52.052585 arm64:ptrace
10913 13:39:52.052706 arm64:syscall-abi
10914 13:39:52.056186 arm64:tpidr2
10915 13:39:52.059594 ============== Tests to run ===============
10916 13:39:52.059678 arm64:tags_test
10917 13:39:52.062880 arm64:run_tags_test.sh
10918 13:39:52.065721 arm64:fake_sigreturn_bad_magic
10919 13:39:52.069321 arm64:fake_sigreturn_bad_size
10920 13:39:52.072351 arm64:fake_sigreturn_bad_size_for_magic0
10921 13:39:52.075849 arm64:fake_sigreturn_duplicated_fpsimd
10922 13:39:52.079012 arm64:fake_sigreturn_misaligned_sp
10923 13:39:52.082607 arm64:fake_sigreturn_missing_fpsimd
10924 13:39:52.085434 arm64:fake_sigreturn_sme_change_vl
10925 13:39:52.085518 arm64:fake_sigreturn_sve_change_vl
10926 13:39:52.092187 arm64:mangle_pstate_invalid_compat_toggle
10927 13:39:52.095292 arm64:mangle_pstate_invalid_daif_bits
10928 13:39:52.099054 arm64:mangle_pstate_invalid_mode_el1h
10929 13:39:52.102261 arm64:mangle_pstate_invalid_mode_el1t
10930 13:39:52.105655 arm64:mangle_pstate_invalid_mode_el2h
10931 13:39:52.109019 arm64:mangle_pstate_invalid_mode_el2t
10932 13:39:52.112451 arm64:mangle_pstate_invalid_mode_el3h
10933 13:39:52.115340 arm64:mangle_pstate_invalid_mode_el3t
10934 13:39:52.115422 arm64:sme_trap_no_sm
10935 13:39:52.118867 arm64:sme_trap_non_streaming
10936 13:39:52.122053 arm64:sme_trap_za
10937 13:39:52.122135 arm64:sme_vl
10938 13:39:52.122201 arm64:ssve_regs
10939 13:39:52.125431 arm64:sve_regs
10940 13:39:52.125513 arm64:sve_vl
10941 13:39:52.128449 arm64:za_no_regs
10942 13:39:52.128531 arm64:za_regs
10943 13:39:52.128595 arm64:pac
10944 13:39:52.132172 arm64:fp-stress
10945 13:39:52.132253 arm64:sve-ptrace
10946 13:39:52.135114 arm64:sve-probe-vls
10947 13:39:52.135196 arm64:vec-syscfg
10948 13:39:52.138784 arm64:za-fork
10949 13:39:52.138866 arm64:za-ptrace
10950 13:39:52.141752 arm64:check_buffer_fill
10951 13:39:52.145422 arm64:check_child_memory
10952 13:39:52.145504 arm64:check_gcr_el1_cswitch
10953 13:39:52.148363 arm64:check_ksm_options
10954 13:39:52.152033 arm64:check_mmap_options
10955 13:39:52.152172 arm64:check_prctl
10956 13:39:52.155094 arm64:check_tags_inclusion
10957 13:39:52.155181 arm64:check_user_mem
10958 13:39:52.158405 arm64:btitest
10959 13:39:52.158519 arm64:nobtitest
10960 13:39:52.161460 arm64:hwcap
10961 13:39:52.161542 arm64:ptrace
10962 13:39:52.164990 arm64:syscall-abi
10963 13:39:52.165072 arm64:tpidr2
10964 13:39:52.168294 ===========End Tests to run ===============
10965 13:39:52.171801 shardfile-arm64 pass
10966 13:39:52.308940 <12>[ 27.170735] kselftest: Running tests in arm64
10967 13:39:52.317662 TAP version 13
10968 13:39:52.330087 1..48
10969 13:39:52.344967 # selftests: arm64: tags_test
10970 13:39:52.776682 ok 1 selftests: arm64: tags_test
10971 13:39:52.793441 # selftests: arm64: run_tags_test.sh
10972 13:39:52.832366 # --------------------
10973 13:39:52.835668 # running tags test
10974 13:39:52.835761 # --------------------
10975 13:39:52.839023 # [PASS]
10976 13:39:52.842387 ok 2 selftests: arm64: run_tags_test.sh
10977 13:39:52.853525 # selftests: arm64: fake_sigreturn_bad_magic
10978 13:39:52.911790 # Registered handlers for all signals.
10979 13:39:52.911896 # Detected MINSTKSIGSZ:4720
10980 13:39:52.914866 # Testcase initialized.
10981 13:39:52.917793 # uc context validated.
10982 13:39:52.921617 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10983 13:39:52.924801 # Handled SIG_COPYCTX
10984 13:39:52.924883 # Available space:3568
10985 13:39:52.931201 # Using badly built context - ERR: BAD MAGIC !
10986 13:39:52.938249 # SIG_OK -- SP:0xFFFFCE92EC90 si_addr@:0xffffce92ec90 si_code:2 token@:0xffffce92da30 offset:-4704
10987 13:39:52.941132 # ==>> completed. PASS(1)
10988 13:39:52.948131 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
10989 13:39:52.954876 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCE92DA30
10990 13:39:52.958139 ok 3 selftests: arm64: fake_sigreturn_bad_magic
10991 13:39:52.964522 # selftests: arm64: fake_sigreturn_bad_size
10992 13:39:52.989987 # Registered handlers for all signals.
10993 13:39:52.990085 # Detected MINSTKSIGSZ:4720
10994 13:39:52.992851 # Testcase initialized.
10995 13:39:52.996500 # uc context validated.
10996 13:39:52.999551 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10997 13:39:53.003213 # Handled SIG_COPYCTX
10998 13:39:53.003290 # Available space:3568
10999 13:39:53.006273 # uc context validated.
11000 13:39:53.013068 # Using badly built context - ERR: Bad size for esr_context
11001 13:39:53.019268 # SIG_OK -- SP:0xFFFFF0FA6B90 si_addr@:0xfffff0fa6b90 si_code:2 token@:0xfffff0fa5930 offset:-4704
11002 13:39:53.022826 # ==>> completed. PASS(1)
11003 13:39:53.029225 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11004 13:39:53.036276 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF0FA5930
11005 13:39:53.039774 ok 4 selftests: arm64: fake_sigreturn_bad_size
11006 13:39:53.045941 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11007 13:39:53.060899 # Registered handlers for all signals.
11008 13:39:53.061016 # Detected MINSTKSIGSZ:4720
11009 13:39:53.064389 # Testcase initialized.
11010 13:39:53.067358 # uc context validated.
11011 13:39:53.071195 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11012 13:39:53.074026 # Handled SIG_COPYCTX
11013 13:39:53.074108 # Available space:3568
11014 13:39:53.081196 # Using badly built context - ERR: Bad size for terminator
11015 13:39:53.090520 # SIG_OK -- SP:0xFFFFDB45A150 si_addr@:0xffffdb45a150 si_code:2 token@:0xffffdb458ef0 offset:-4704
11016 13:39:53.090605 # ==>> completed. PASS(1)
11017 13:39:53.100569 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11018 13:39:53.107153 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB458EF0
11019 13:39:53.110714 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11020 13:39:53.116805 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11021 13:39:53.132393 # Registered handlers for all signals.
11022 13:39:53.132472 # Detected MINSTKSIGSZ:4720
11023 13:39:53.135375 # Testcase initialized.
11024 13:39:53.138575 # uc context validated.
11025 13:39:53.141881 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11026 13:39:53.145128 # Handled SIG_COPYCTX
11027 13:39:53.145222 # Available space:3568
11028 13:39:53.152043 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11029 13:39:53.162076 # SIG_OK -- SP:0xFFFFF112E950 si_addr@:0xfffff112e950 si_code:2 token@:0xfffff112d6f0 offset:-4704
11030 13:39:53.162164 # ==>> completed. PASS(1)
11031 13:39:53.171775 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11032 13:39:53.178646 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF112D6F0
11033 13:39:53.181883 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11034 13:39:53.185240 # selftests: arm64: fake_sigreturn_misaligned_sp
11035 13:39:53.198900 # Registered handlers for all signals.
11036 13:39:53.198986 # Detected MINSTKSIGSZ:4720
11037 13:39:53.202136 # Testcase initialized.
11038 13:39:53.205126 # uc context validated.
11039 13:39:53.208259 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11040 13:39:53.211764 # Handled SIG_COPYCTX
11041 13:39:53.218548 # SIG_OK -- SP:0xFFFFE0CE7EE3 si_addr@:0xffffe0ce7ee3 si_code:2 token@:0xffffe0ce7ee3 offset:0
11042 13:39:53.221581 # ==>> completed. PASS(1)
11043 13:39:53.228140 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11044 13:39:53.234901 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0CE7EE3
11045 13:39:53.241431 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11046 13:39:53.244755 # selftests: arm64: fake_sigreturn_missing_fpsimd
11047 13:39:53.272691 # Registered handlers for all signals.
11048 13:39:53.272794 # Detected MINSTKSIGSZ:4720
11049 13:39:53.275662 # Testcase initialized.
11050 13:39:53.279255 # uc context validated.
11051 13:39:53.282223 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11052 13:39:53.285585 # Handled SIG_COPYCTX
11053 13:39:53.289179 # Mangling template header. Spare space:4096
11054 13:39:53.292141 # Using badly built context - ERR: Missing FPSIMD
11055 13:39:53.302353 # SIG_OK -- SP:0xFFFFF7781AC0 si_addr@:0xfffff7781ac0 si_code:2 token@:0xfffff7780860 offset:-4704
11056 13:39:53.305412 # ==>> completed. PASS(1)
11057 13:39:53.312084 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11058 13:39:53.318582 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF7780860
11059 13:39:53.322290 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11060 13:39:53.328827 # selftests: arm64: fake_sigreturn_sme_change_vl
11061 13:39:53.340202 # Registered handlers for all signals.
11062 13:39:53.340284 # Detected MINSTKSIGSZ:4720
11063 13:39:53.343775 # ==>> completed. SKIP.
11064 13:39:53.350324 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11065 13:39:53.353621 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11066 13:39:53.360175 # selftests: arm64: fake_sigreturn_sve_change_vl
11067 13:39:53.417454 # Registered handlers for all signals.
11068 13:39:53.417574 # Detected MINSTKSIGSZ:4720
11069 13:39:53.420950 # ==>> completed. SKIP.
11070 13:39:53.427507 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11071 13:39:53.430606 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11072 13:39:53.437277 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11073 13:39:53.479721 # Registered handlers for all signals.
11074 13:39:53.479822 # Detected MINSTKSIGSZ:4720
11075 13:39:53.483140 # Testcase initialized.
11076 13:39:53.486140 # uc context validated.
11077 13:39:53.486221 # Handled SIG_TRIG
11078 13:39:53.496105 # SIG_OK -- SP:0xFFFFFF9C5EC0 si_addr@:0xffffff9c5ec0 si_code:2 token@:(nil) offset:-281474970181312
11079 13:39:53.499249 # ==>> completed. PASS(1)
11080 13:39:53.505818 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11081 13:39:53.512707 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11082 13:39:53.515926 # selftests: arm64: mangle_pstate_invalid_daif_bits
11083 13:39:53.545747 # Registered handlers for all signals.
11084 13:39:53.545840 # Detected MINSTKSIGSZ:4720
11085 13:39:53.548824 # Testcase initialized.
11086 13:39:53.552422 # uc context validated.
11087 13:39:53.552513 # Handled SIG_TRIG
11088 13:39:53.562251 # SIG_OK -- SP:0xFFFFE66E1490 si_addr@:0xffffe66e1490 si_code:2 token@:(nil) offset:-281474547717264
11089 13:39:53.565793 # ==>> completed. PASS(1)
11090 13:39:53.571832 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11091 13:39:53.575393 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11092 13:39:53.581805 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11093 13:39:53.614835 # Registered handlers for all signals.
11094 13:39:53.614936 # Detected MINSTKSIGSZ:4720
11095 13:39:53.618225 # Testcase initialized.
11096 13:39:53.621672 # uc context validated.
11097 13:39:53.621745 # Handled SIG_TRIG
11098 13:39:53.631354 # SIG_OK -- SP:0xFFFFCB8A77E0 si_addr@:0xffffcb8a77e0 si_code:2 token@:(nil) offset:-281474096592864
11099 13:39:53.634738 # ==>> completed. PASS(1)
11100 13:39:53.641283 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11101 13:39:53.644931 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11102 13:39:53.650933 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11103 13:39:53.684509 # Registered handlers for all signals.
11104 13:39:53.684602 # Detected MINSTKSIGSZ:4720
11105 13:39:53.687988 # Testcase initialized.
11106 13:39:53.691478 # uc context validated.
11107 13:39:53.691560 # Handled SIG_TRIG
11108 13:39:53.701339 # SIG_OK -- SP:0xFFFFCE376910 si_addr@:0xffffce376910 si_code:2 token@:(nil) offset:-281474141481232
11109 13:39:53.704441 # ==>> completed. PASS(1)
11110 13:39:53.711419 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11111 13:39:53.714786 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11112 13:39:53.721295 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11113 13:39:53.751944 # Registered handlers for all signals.
11114 13:39:53.752042 # Detected MINSTKSIGSZ:4720
11115 13:39:53.755468 # Testcase initialized.
11116 13:39:53.758376 # uc context validated.
11117 13:39:53.758458 # Handled SIG_TRIG
11118 13:39:53.768155 # SIG_OK -- SP:0xFFFFD54DC900 si_addr@:0xffffd54dc900 si_code:2 token@:(nil) offset:-281474260388096
11119 13:39:53.771685 # ==>> completed. PASS(1)
11120 13:39:53.778177 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11121 13:39:53.781670 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11122 13:39:53.788206 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11123 13:39:53.814291 # Registered handlers for all signals.
11124 13:39:53.814393 # Detected MINSTKSIGSZ:4720
11125 13:39:53.817258 # Testcase initialized.
11126 13:39:53.820893 # uc context validated.
11127 13:39:53.820974 # Handled SIG_TRIG
11128 13:39:53.830708 # SIG_OK -- SP:0xFFFFD056A400 si_addr@:0xffffd056a400 si_code:2 token@:(nil) offset:-281474177082368
11129 13:39:53.833801 # ==>> completed. PASS(1)
11130 13:39:53.840527 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11131 13:39:53.844024 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11132 13:39:53.850142 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11133 13:39:53.887064 # Registered handlers for all signals.
11134 13:39:53.887157 # Detected MINSTKSIGSZ:4720
11135 13:39:53.890078 # Testcase initialized.
11136 13:39:53.893307 # uc context validated.
11137 13:39:53.893402 # Handled SIG_TRIG
11138 13:39:53.903248 # SIG_OK -- SP:0xFFFFCC816990 si_addr@:0xffffcc816990 si_code:2 token@:(nil) offset:-281474112776592
11139 13:39:53.906721 # ==>> completed. PASS(1)
11140 13:39:53.913331 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11141 13:39:53.916458 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11142 13:39:53.923010 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11143 13:39:53.952263 # Registered handlers for all signals.
11144 13:39:53.952488 # Detected MINSTKSIGSZ:4720
11145 13:39:53.955672 # Testcase initialized.
11146 13:39:53.959406 # uc context validated.
11147 13:39:53.959566 # Handled SIG_TRIG
11148 13:39:53.969278 # SIG_OK -- SP:0xFFFFDF1536E0 si_addr@:0xffffdf1536e0 si_code:2 token@:(nil) offset:-281474424452832
11149 13:39:53.972334 # ==>> completed. PASS(1)
11150 13:39:53.978958 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11151 13:39:53.982631 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11152 13:39:53.986012 # selftests: arm64: sme_trap_no_sm
11153 13:39:54.031021 # Registered handlers for all signals.
11154 13:39:54.031469 # Detected MINSTKSIGSZ:4720
11155 13:39:54.034590 # ==>> completed. SKIP.
11156 13:39:54.044236 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11157 13:39:54.047455 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11158 13:39:54.050790 # selftests: arm64: sme_trap_non_streaming
11159 13:39:54.097668 # Registered handlers for all signals.
11160 13:39:54.098160 # Detected MINSTKSIGSZ:4720
11161 13:39:54.101365 # ==>> completed. SKIP.
11162 13:39:54.110945 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11163 13:39:54.117946 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11164 13:39:54.120721 # selftests: arm64: sme_trap_za
11165 13:39:54.174347 # Registered handlers for all signals.
11166 13:39:54.174794 # Detected MINSTKSIGSZ:4720
11167 13:39:54.177168 # Testcase initialized.
11168 13:39:54.187342 # SIG_OK -- SP:0xFFFFC0858C10 si_addr@:0xaaaaca892510 si_code:1 token@:(nil) offset:-187650519147792
11169 13:39:54.187766 # ==>> completed. PASS(1)
11170 13:39:54.197179 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11171 13:39:54.200351 ok 21 selftests: arm64: sme_trap_za
11172 13:39:54.200781 # selftests: arm64: sme_vl
11173 13:39:54.241498 # Registered handlers for all signals.
11174 13:39:54.241971 # Detected MINSTKSIGSZ:4720
11175 13:39:54.245012 # ==>> completed. SKIP.
11176 13:39:54.251563 # # SME VL :: Check that we get the right SME VL reported
11177 13:39:54.254668 ok 22 selftests: arm64: sme_vl # SKIP
11178 13:39:54.259323 # selftests: arm64: ssve_regs
11179 13:39:54.316232 # Registered handlers for all signals.
11180 13:39:54.316717 # Detected MINSTKSIGSZ:4720
11181 13:39:54.319431 # ==>> completed. SKIP.
11182 13:39:54.325971 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11183 13:39:54.332798 ok 23 selftests: arm64: ssve_regs # SKIP
11184 13:39:54.335811 # selftests: arm64: sve_regs
11185 13:39:54.374604 # Registered handlers for all signals.
11186 13:39:54.375089 # Detected MINSTKSIGSZ:4720
11187 13:39:54.378087 # ==>> completed. SKIP.
11188 13:39:54.384219 # # SVE registers :: Check that we get the right SVE registers reported
11189 13:39:54.387604 ok 24 selftests: arm64: sve_regs # SKIP
11190 13:39:54.391530 # selftests: arm64: sve_vl
11191 13:39:54.455487 # Registered handlers for all signals.
11192 13:39:54.456217 # Detected MINSTKSIGSZ:4720
11193 13:39:54.458458 # ==>> completed. SKIP.
11194 13:39:54.464973 # # SVE VL :: Check that we get the right SVE VL reported
11195 13:39:54.467896 ok 25 selftests: arm64: sve_vl # SKIP
11196 13:39:54.471444 # selftests: arm64: za_no_regs
11197 13:39:54.546123 # Registered handlers for all signals.
11198 13:39:54.546605 # Detected MINSTKSIGSZ:4720
11199 13:39:54.549224 # ==>> completed. SKIP.
11200 13:39:54.555939 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11201 13:39:54.559565 ok 26 selftests: arm64: za_no_regs # SKIP
11202 13:39:54.562667 # selftests: arm64: za_regs
11203 13:39:54.621689 # Registered handlers for all signals.
11204 13:39:54.622224 # Detected MINSTKSIGSZ:4720
11205 13:39:54.625272 # ==>> completed. SKIP.
11206 13:39:54.631645 # # ZA register :: Check that we get the right ZA registers reported
11207 13:39:54.634574 ok 27 selftests: arm64: za_regs # SKIP
11208 13:39:54.638208 # selftests: arm64: pac
11209 13:39:54.692378 # TAP version 13
11210 13:39:54.692888 # 1..7
11211 13:39:54.695887 # # Starting 7 tests from 1 test cases.
11212 13:39:54.698954 # # RUN global.corrupt_pac ...
11213 13:39:54.702537 # # SKIP PAUTH not enabled
11214 13:39:54.706130 # # OK global.corrupt_pac
11215 13:39:54.709031 # ok 1 # SKIP PAUTH not enabled
11216 13:39:54.715983 # # RUN global.pac_instructions_not_nop ...
11217 13:39:54.719338 # # SKIP PAUTH not enabled
11218 13:39:54.722573 # # OK global.pac_instructions_not_nop
11219 13:39:54.725270 # ok 2 # SKIP PAUTH not enabled
11220 13:39:54.732423 # # RUN global.pac_instructions_not_nop_generic ...
11221 13:39:54.735183 # # SKIP Generic PAUTH not enabled
11222 13:39:54.738735 # # OK global.pac_instructions_not_nop_generic
11223 13:39:54.742344 # ok 3 # SKIP Generic PAUTH not enabled
11224 13:39:54.748978 # # RUN global.single_thread_different_keys ...
11225 13:39:54.751882 # # SKIP PAUTH not enabled
11226 13:39:54.758470 # # OK global.single_thread_different_keys
11227 13:39:54.758902 # ok 4 # SKIP PAUTH not enabled
11228 13:39:54.765391 # # RUN global.exec_changed_keys ...
11229 13:39:54.768187 # # SKIP PAUTH not enabled
11230 13:39:54.771766 # # OK global.exec_changed_keys
11231 13:39:54.774825 # ok 5 # SKIP PAUTH not enabled
11232 13:39:54.778422 # # RUN global.context_switch_keep_keys ...
11233 13:39:54.781650 # # SKIP PAUTH not enabled
11234 13:39:54.788595 # # OK global.context_switch_keep_keys
11235 13:39:54.789123 # ok 6 # SKIP PAUTH not enabled
11236 13:39:54.794859 # # RUN global.context_switch_keep_keys_generic ...
11237 13:39:54.797811 # # SKIP Generic PAUTH not enabled
11238 13:39:54.804943 # # OK global.context_switch_keep_keys_generic
11239 13:39:54.808384 # ok 7 # SKIP Generic PAUTH not enabled
11240 13:39:54.811477 # # PASSED: 7 / 7 tests passed.
11241 13:39:54.814924 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11242 13:39:54.818057 ok 28 selftests: arm64: pac
11243 13:39:54.821569 # selftests: arm64: fp-stress
11244 13:40:03.098909 <6>[ 37.964883] vpu: disabling
11245 13:40:03.102181 <6>[ 37.967936] vproc2: disabling
11246 13:40:03.105827 <6>[ 37.971210] vproc1: disabling
11247 13:40:03.108834 <6>[ 37.974483] vaud18: disabling
11248 13:40:03.115320 <6>[ 37.977911] vsram_others: disabling
11249 13:40:03.118803 <6>[ 37.981803] va09: disabling
11250 13:40:03.122137 <6>[ 37.984921] vsram_md: disabling
11251 13:40:03.125506 <6>[ 37.988419] Vgpu: disabling
11252 13:40:04.769249 # TAP version 13
11253 13:40:04.770025 # 1..16
11254 13:40:04.772208 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11255 13:40:04.775547 # # Will run for 10s
11256 13:40:04.776290 # # Started FPSIMD-0-0
11257 13:40:04.778781 # # Started FPSIMD-0-1
11258 13:40:04.782451 # # Started FPSIMD-1-0
11259 13:40:04.783105 # # Started FPSIMD-1-1
11260 13:40:04.785741 # # Started FPSIMD-2-0
11261 13:40:04.788676 # # Started FPSIMD-2-1
11262 13:40:04.789144 # # Started FPSIMD-3-0
11263 13:40:04.792151 # # Started FPSIMD-3-1
11264 13:40:04.792732 # # Started FPSIMD-4-0
11265 13:40:04.795152 # # Started FPSIMD-4-1
11266 13:40:04.798860 # # Started FPSIMD-5-0
11267 13:40:04.799275 # # Started FPSIMD-5-1
11268 13:40:04.801876 # # Started FPSIMD-6-0
11269 13:40:04.805417 # # Started FPSIMD-6-1
11270 13:40:04.805847 # # Started FPSIMD-7-0
11271 13:40:04.808715 # # Started FPSIMD-7-1
11272 13:40:04.811909 # # FPSIMD-1-0: Vector length: 128 bits
11273 13:40:04.814981 # # FPSIMD-1-0: PID: 1162
11274 13:40:04.818511 # # FPSIMD-0-0: Vector length: 128 bits
11275 13:40:04.818931 # # FPSIMD-0-0: PID: 1160
11276 13:40:04.825175 # # FPSIMD-0-1: Vector length: 128 bits
11277 13:40:04.825704 # # FPSIMD-0-1: PID: 1161
11278 13:40:04.828583 # # FPSIMD-2-0: Vector length: 128 bits
11279 13:40:04.831549 # # FPSIMD-2-0: PID: 1164
11280 13:40:04.835005 # # FPSIMD-2-1: Vector length: 128 bits
11281 13:40:04.838382 # # FPSIMD-2-1: PID: 1165
11282 13:40:04.841218 # # FPSIMD-6-1: Vector length: 128 bits
11283 13:40:04.844692 # # FPSIMD-6-1: PID: 1173
11284 13:40:04.847913 # # FPSIMD-4-1: Vector length: 128 bits
11285 13:40:04.848460 # # FPSIMD-4-1: PID: 1169
11286 13:40:04.851344 # # FPSIMD-5-1: Vector length: 128 bits
11287 13:40:04.854943 # # FPSIMD-5-1: PID: 1171
11288 13:40:04.858295 # # FPSIMD-6-0: Vector length: 128 bits
11289 13:40:04.861153 # # FPSIMD-6-0: PID: 1172
11290 13:40:04.864945 # # FPSIMD-4-0: Vector length: 128 bits
11291 13:40:04.867957 # # FPSIMD-5-0: Vector length: 128 bits
11292 13:40:04.871326 # # FPSIMD-5-0: PID: 1170
11293 13:40:04.874390 # # FPSIMD-4-0: PID: 1168
11294 13:40:04.877550 # # FPSIMD-7-0: Vector length: 128 bits
11295 13:40:04.877963 # # FPSIMD-7-0: PID: 1174
11296 13:40:04.881139 # # FPSIMD-1-1: Vector length: 128 bits
11297 13:40:04.884542 # # FPSIMD-1-1: PID: 1163
11298 13:40:04.887777 # # FPSIMD-3-1: Vector length: 128 bits
11299 13:40:04.890905 # # FPSIMD-3-1: PID: 1167
11300 13:40:04.894151 # # FPSIMD-3-0: Vector length: 128 bits
11301 13:40:04.897441 # # FPSIMD-3-0: PID: 1166
11302 13:40:04.901248 # # FPSIMD-7-1: Vector length: 128 bits
11303 13:40:04.904153 # # FPSIMD-7-1: PID: 1175
11304 13:40:04.904659 # # Finishing up...
11305 13:40:04.911000 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1033099, signals=10
11306 13:40:04.917565 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1052493, signals=10
11307 13:40:04.927372 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1008616, signals=10
11308 13:40:04.934191 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2187686, signals=10
11309 13:40:04.940822 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=2092739, signals=10
11310 13:40:04.947295 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=2190764, signals=10
11311 13:40:04.953828 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=2143140, signals=10
11312 13:40:04.957358 # ok 1 FPSIMD-0-0
11313 13:40:04.957874 # ok 2 FPSIMD-0-1
11314 13:40:04.960589 # ok 3 FPSIMD-1-0
11315 13:40:04.961004 # ok 4 FPSIMD-1-1
11316 13:40:04.963512 # ok 5 FPSIMD-2-0
11317 13:40:04.963921 # ok 6 FPSIMD-2-1
11318 13:40:04.966962 # ok 7 FPSIMD-3-0
11319 13:40:04.967508 # ok 8 FPSIMD-3-1
11320 13:40:04.970661 # ok 9 FPSIMD-4-0
11321 13:40:04.971127 # ok 10 FPSIMD-4-1
11322 13:40:04.973577 # ok 11 FPSIMD-5-0
11323 13:40:04.973988 # ok 12 FPSIMD-5-1
11324 13:40:04.977137 # ok 13 FPSIMD-6-0
11325 13:40:04.977599 # ok 14 FPSIMD-6-1
11326 13:40:04.980120 # ok 15 FPSIMD-7-0
11327 13:40:04.983746 # ok 16 FPSIMD-7-1
11328 13:40:04.990352 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1261484, signals=9
11329 13:40:04.996648 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1002490, signals=10
11330 13:40:05.003662 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1028573, signals=10
11331 13:40:05.009969 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1025128, signals=10
11332 13:40:05.016605 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=977291, signals=9
11333 13:40:05.023108 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1005446, signals=10
11334 13:40:05.033360 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1060449, signals=10
11335 13:40:05.039975 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=982418, signals=10
11336 13:40:05.046007 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=993428, signals=9
11337 13:40:05.053266 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11338 13:40:05.053756 ok 29 selftests: arm64: fp-stress
11339 13:40:05.056185 # selftests: arm64: sve-ptrace
11340 13:40:05.059596 # TAP version 13
11341 13:40:05.060015 # 1..4104
11342 13:40:05.062678 # ok 2 # SKIP SVE not available
11343 13:40:05.066338 # # Planned tests != run tests (4104 != 1)
11344 13:40:05.072754 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11345 13:40:05.075897 ok 30 selftests: arm64: sve-ptrace # SKIP
11346 13:40:05.079470 # selftests: arm64: sve-probe-vls
11347 13:40:05.079931 # TAP version 13
11348 13:40:05.080276 # 1..2
11349 13:40:05.082669 # ok 2 # SKIP SVE not available
11350 13:40:05.086286 # # Planned tests != run tests (2 != 1)
11351 13:40:05.092741 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11352 13:40:05.095710 ok 31 selftests: arm64: sve-probe-vls # SKIP
11353 13:40:05.099236 # selftests: arm64: vec-syscfg
11354 13:40:05.099903 # TAP version 13
11355 13:40:05.102079 # 1..20
11356 13:40:05.102546 # ok 1 # SKIP SVE not supported
11357 13:40:05.105749 # ok 2 # SKIP SVE not supported
11358 13:40:05.109025 # ok 3 # SKIP SVE not supported
11359 13:40:05.112144 # ok 4 # SKIP SVE not supported
11360 13:40:05.115501 # ok 5 # SKIP SVE not supported
11361 13:40:05.118701 # ok 6 # SKIP SVE not supported
11362 13:40:05.122245 # ok 7 # SKIP SVE not supported
11363 13:40:05.122826 # ok 8 # SKIP SVE not supported
11364 13:40:05.125202 # ok 9 # SKIP SVE not supported
11365 13:40:05.128953 # ok 10 # SKIP SVE not supported
11366 13:40:05.132399 # ok 11 # SKIP SME not supported
11367 13:40:05.135303 # ok 12 # SKIP SME not supported
11368 13:40:05.138666 # ok 13 # SKIP SME not supported
11369 13:40:05.142337 # ok 14 # SKIP SME not supported
11370 13:40:05.145351 # ok 15 # SKIP SME not supported
11371 13:40:05.148444 # ok 16 # SKIP SME not supported
11372 13:40:05.148866 # ok 17 # SKIP SME not supported
11373 13:40:05.152238 # ok 18 # SKIP SME not supported
11374 13:40:05.155210 # ok 19 # SKIP SME not supported
11375 13:40:05.158389 # ok 20 # SKIP SME not supported
11376 13:40:05.164991 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11377 13:40:05.168582 ok 32 selftests: arm64: vec-syscfg
11378 13:40:05.168877 # selftests: arm64: za-fork
11379 13:40:05.171626 # TAP version 13
11380 13:40:05.171847 # 1..1
11381 13:40:05.175118 # # PID: 1252
11382 13:40:05.175340 # # SME support not present
11383 13:40:05.177966 # ok 0 skipped
11384 13:40:05.181310 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11385 13:40:05.185118 ok 33 selftests: arm64: za-fork
11386 13:40:05.188176 # selftests: arm64: za-ptrace
11387 13:40:05.188397 # TAP version 13
11388 13:40:05.191669 # 1..1
11389 13:40:05.191890 # ok 2 # SKIP SME not available
11390 13:40:05.198223 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11391 13:40:05.201252 ok 34 selftests: arm64: za-ptrace # SKIP
11392 13:40:05.204453 # selftests: arm64: check_buffer_fill
11393 13:40:05.226725 # # SKIP: MTE features unavailable
11394 13:40:05.234403 ok 35 selftests: arm64: check_buffer_fill # SKIP
11395 13:40:05.250840 # selftests: arm64: check_child_memory
11396 13:40:05.307064 # # SKIP: MTE features unavailable
11397 13:40:05.314396 ok 36 selftests: arm64: check_child_memory # SKIP
11398 13:40:05.331123 # selftests: arm64: check_gcr_el1_cswitch
11399 13:40:05.398842 # # SKIP: MTE features unavailable
11400 13:40:05.406364 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11401 13:40:05.423315 # selftests: arm64: check_ksm_options
11402 13:40:05.463333 # # SKIP: MTE features unavailable
11403 13:40:05.470088 ok 38 selftests: arm64: check_ksm_options # SKIP
11404 13:40:05.486141 # selftests: arm64: check_mmap_options
11405 13:40:05.547048 # # SKIP: MTE features unavailable
11406 13:40:05.554088 ok 39 selftests: arm64: check_mmap_options # SKIP
11407 13:40:05.568283 # selftests: arm64: check_prctl
11408 13:40:05.620328 # TAP version 13
11409 13:40:05.620800 # 1..5
11410 13:40:05.623837 # ok 1 check_basic_read
11411 13:40:05.624393 # ok 2 NONE
11412 13:40:05.626687 # ok 3 # SKIP SYNC
11413 13:40:05.627105 # ok 4 # SKIP ASYNC
11414 13:40:05.630384 # ok 5 # SKIP SYNC+ASYNC
11415 13:40:05.633355 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11416 13:40:05.636823 ok 40 selftests: arm64: check_prctl
11417 13:40:05.643304 # selftests: arm64: check_tags_inclusion
11418 13:40:05.689861 # # SKIP: MTE features unavailable
11419 13:40:05.697729 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11420 13:40:05.709412 # selftests: arm64: check_user_mem
11421 13:40:05.763178 # # SKIP: MTE features unavailable
11422 13:40:05.770510 ok 42 selftests: arm64: check_user_mem # SKIP
11423 13:40:05.783965 # selftests: arm64: btitest
11424 13:40:05.835908 # TAP version 13
11425 13:40:05.836447 # 1..18
11426 13:40:05.838721 # # HWCAP_PACA not present
11427 13:40:05.842395 # # HWCAP2_BTI not present
11428 13:40:05.842860 # # Test binary built for BTI
11429 13:40:05.849091 # ok 1 nohint_func/call_using_br_x0 # SKIP
11430 13:40:05.852110 # ok 1 nohint_func/call_using_br_x16 # SKIP
11431 13:40:05.855156 # ok 1 nohint_func/call_using_blr # SKIP
11432 13:40:05.858980 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11433 13:40:05.862284 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11434 13:40:05.868494 # ok 1 bti_none_func/call_using_blr # SKIP
11435 13:40:05.872146 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11436 13:40:05.875135 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11437 13:40:05.878906 # ok 1 bti_c_func/call_using_blr # SKIP
11438 13:40:05.881733 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11439 13:40:05.884763 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11440 13:40:05.888452 # ok 1 bti_j_func/call_using_blr # SKIP
11441 13:40:05.891941 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11442 13:40:05.898345 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11443 13:40:05.901695 # ok 1 bti_jc_func/call_using_blr # SKIP
11444 13:40:05.904927 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11445 13:40:05.908118 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11446 13:40:05.911493 # ok 1 paciasp_func/call_using_blr # SKIP
11447 13:40:05.917945 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11448 13:40:05.920969 # # WARNING - EXPECTED TEST COUNT WRONG
11449 13:40:05.924323 ok 43 selftests: arm64: btitest
11450 13:40:05.927930 # selftests: arm64: nobtitest
11451 13:40:05.928347 # TAP version 13
11452 13:40:05.928672 # 1..18
11453 13:40:05.931080 # # HWCAP_PACA not present
11454 13:40:05.934793 # # HWCAP2_BTI not present
11455 13:40:05.937670 # # Test binary not built for BTI
11456 13:40:05.941136 # ok 1 nohint_func/call_using_br_x0 # SKIP
11457 13:40:05.944176 # ok 1 nohint_func/call_using_br_x16 # SKIP
11458 13:40:05.947844 # ok 1 nohint_func/call_using_blr # SKIP
11459 13:40:05.950820 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11460 13:40:05.957463 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11461 13:40:05.960469 # ok 1 bti_none_func/call_using_blr # SKIP
11462 13:40:05.963956 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11463 13:40:05.967573 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11464 13:40:05.970886 # ok 1 bti_c_func/call_using_blr # SKIP
11465 13:40:05.973694 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11466 13:40:05.977225 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11467 13:40:05.983791 # ok 1 bti_j_func/call_using_blr # SKIP
11468 13:40:05.987234 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11469 13:40:05.990214 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11470 13:40:05.993650 # ok 1 bti_jc_func/call_using_blr # SKIP
11471 13:40:05.997204 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11472 13:40:06.000425 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11473 13:40:06.003741 # ok 1 paciasp_func/call_using_blr # SKIP
11474 13:40:06.009937 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11475 13:40:06.013206 # # WARNING - EXPECTED TEST COUNT WRONG
11476 13:40:06.016923 ok 44 selftests: arm64: nobtitest
11477 13:40:06.020090 # selftests: arm64: hwcap
11478 13:40:06.020510 # TAP version 13
11479 13:40:06.021000 # 1..28
11480 13:40:06.023345 # ok 1 cpuinfo_match_RNG
11481 13:40:06.026413 # # SIGILL reported for RNG
11482 13:40:06.030018 # ok 2 # SKIP sigill_RNG
11483 13:40:06.030474 # ok 3 cpuinfo_match_SME
11484 13:40:06.033372 # ok 4 sigill_SME
11485 13:40:06.033869 # ok 5 cpuinfo_match_SVE
11486 13:40:06.036169 # ok 6 sigill_SVE
11487 13:40:06.039684 # ok 7 cpuinfo_match_SVE 2
11488 13:40:06.043001 # # SIGILL reported for SVE 2
11489 13:40:06.043431 # ok 8 # SKIP sigill_SVE 2
11490 13:40:06.046201 # ok 9 cpuinfo_match_SVE AES
11491 13:40:06.049625 # # SIGILL reported for SVE AES
11492 13:40:06.052821 # ok 10 # SKIP sigill_SVE AES
11493 13:40:06.056416 # ok 11 cpuinfo_match_SVE2 PMULL
11494 13:40:06.059474 # # SIGILL reported for SVE2 PMULL
11495 13:40:06.059891 # ok 12 # SKIP sigill_SVE2 PMULL
11496 13:40:06.063149 # ok 13 cpuinfo_match_SVE2 BITPERM
11497 13:40:06.065935 # # SIGILL reported for SVE2 BITPERM
11498 13:40:06.069645 # ok 14 # SKIP sigill_SVE2 BITPERM
11499 13:40:06.072519 # ok 15 cpuinfo_match_SVE2 SHA3
11500 13:40:06.075940 # # SIGILL reported for SVE2 SHA3
11501 13:40:06.079380 # ok 16 # SKIP sigill_SVE2 SHA3
11502 13:40:06.082997 # ok 17 cpuinfo_match_SVE2 SM4
11503 13:40:06.086066 # # SIGILL reported for SVE2 SM4
11504 13:40:06.089469 # ok 18 # SKIP sigill_SVE2 SM4
11505 13:40:06.089928 # ok 19 cpuinfo_match_SVE2 I8MM
11506 13:40:06.092495 # # SIGILL reported for SVE2 I8MM
11507 13:40:06.096045 # ok 20 # SKIP sigill_SVE2 I8MM
11508 13:40:06.098990 # ok 21 cpuinfo_match_SVE2 F32MM
11509 13:40:06.102390 # # SIGILL reported for SVE2 F32MM
11510 13:40:06.105959 # ok 22 # SKIP sigill_SVE2 F32MM
11511 13:40:06.109035 # ok 23 cpuinfo_match_SVE2 F64MM
11512 13:40:06.111965 # # SIGILL reported for SVE2 F64MM
11513 13:40:06.115640 # ok 24 # SKIP sigill_SVE2 F64MM
11514 13:40:06.119310 # ok 25 cpuinfo_match_SVE2 BF16
11515 13:40:06.122053 # # SIGILL reported for SVE2 BF16
11516 13:40:06.122588 # ok 26 # SKIP sigill_SVE2 BF16
11517 13:40:06.125280 # ok 27 cpuinfo_match_SVE2 EBF16
11518 13:40:06.128485 # ok 28 # SKIP sigill_SVE2 EBF16
11519 13:40:06.135520 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11520 13:40:06.138729 ok 45 selftests: arm64: hwcap
11521 13:40:06.139154 # selftests: arm64: ptrace
11522 13:40:06.141895 # TAP version 13
11523 13:40:06.142593 # 1..7
11524 13:40:06.145183 # # Parent is 1494, child is 1495
11525 13:40:06.148537 # ok 1 read_tpidr_one
11526 13:40:06.148980 # ok 2 write_tpidr_one
11527 13:40:06.152228 # ok 3 verify_tpidr_one
11528 13:40:06.152646 # ok 4 count_tpidrs
11529 13:40:06.155188 # ok 5 tpidr2_write
11530 13:40:06.155785 # ok 6 tpidr2_read
11531 13:40:06.158713 # ok 7 write_tpidr_only
11532 13:40:06.165225 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11533 13:40:06.165810 ok 46 selftests: arm64: ptrace
11534 13:40:06.168661 # selftests: arm64: syscall-abi
11535 13:40:06.171612 # TAP version 13
11536 13:40:06.172028 # 1..2
11537 13:40:06.175248 # ok 1 getpid() FPSIMD
11538 13:40:06.175683 # ok 2 sched_yield() FPSIMD
11539 13:40:06.181744 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11540 13:40:06.184923 ok 47 selftests: arm64: syscall-abi
11541 13:40:06.187934 # selftests: arm64: tpidr2
11542 13:40:06.238596 # TAP version 13
11543 13:40:06.238957 # 1..5
11544 13:40:06.241685 # # PID: 1531
11545 13:40:06.241983 # # SME support not present
11546 13:40:06.244962 # ok 0 skipped, TPIDR2 not supported
11547 13:40:06.248149 # ok 1 skipped, TPIDR2 not supported
11548 13:40:06.251823 # ok 2 skipped, TPIDR2 not supported
11549 13:40:06.254940 # ok 3 skipped, TPIDR2 not supported
11550 13:40:06.258339 # ok 4 skipped, TPIDR2 not supported
11551 13:40:06.265162 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11552 13:40:06.268126 ok 48 selftests: arm64: tpidr2
11553 13:40:07.756197 arm64_tags_test pass
11554 13:40:07.759818 arm64_run_tags_test_sh pass
11555 13:40:07.762722 arm64_fake_sigreturn_bad_magic pass
11556 13:40:07.765983 arm64_fake_sigreturn_bad_size pass
11557 13:40:07.769345 arm64_fake_sigreturn_bad_size_for_magic0 pass
11558 13:40:07.773036 arm64_fake_sigreturn_duplicated_fpsimd pass
11559 13:40:07.776135 arm64_fake_sigreturn_misaligned_sp pass
11560 13:40:07.779495 arm64_fake_sigreturn_missing_fpsimd pass
11561 13:40:07.782634 arm64_fake_sigreturn_sme_change_vl skip
11562 13:40:07.789639 arm64_fake_sigreturn_sve_change_vl skip
11563 13:40:07.792654 arm64_mangle_pstate_invalid_compat_toggle pass
11564 13:40:07.796223 arm64_mangle_pstate_invalid_daif_bits pass
11565 13:40:07.799462 arm64_mangle_pstate_invalid_mode_el1h pass
11566 13:40:07.802534 arm64_mangle_pstate_invalid_mode_el1t pass
11567 13:40:07.805941 arm64_mangle_pstate_invalid_mode_el2h pass
11568 13:40:07.812132 arm64_mangle_pstate_invalid_mode_el2t pass
11569 13:40:07.815629 arm64_mangle_pstate_invalid_mode_el3h pass
11570 13:40:07.819124 arm64_mangle_pstate_invalid_mode_el3t pass
11571 13:40:07.822219 arm64_sme_trap_no_sm skip
11572 13:40:07.825616 arm64_sme_trap_non_streaming skip
11573 13:40:07.826212 arm64_sme_trap_za pass
11574 13:40:07.828982 arm64_sme_vl skip
11575 13:40:07.829608 arm64_ssve_regs skip
11576 13:40:07.832521 arm64_sve_regs skip
11577 13:40:07.833047 arm64_sve_vl skip
11578 13:40:07.835346 arm64_za_no_regs skip
11579 13:40:07.835931 arm64_za_regs skip
11580 13:40:07.838895 arm64_pac_PAUTH_not_enabled skip
11581 13:40:07.841886 arm64_pac_PAUTH_not_enabled_dup2 skip
11582 13:40:07.845104 arm64_pac_Generic_PAUTH_not_enabled skip
11583 13:40:07.848720 arm64_pac_PAUTH_not_enabled_dup3 skip
11584 13:40:07.851778 arm64_pac_PAUTH_not_enabled_dup4 skip
11585 13:40:07.858346 arm64_pac_PAUTH_not_enabled_dup5 skip
11586 13:40:07.861806 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11587 13:40:07.861997 arm64_pac pass
11588 13:40:07.864803 arm64_fp-stress_FPSIMD-0-0 pass
11589 13:40:07.868407 arm64_fp-stress_FPSIMD-0-1 pass
11590 13:40:07.871528 arm64_fp-stress_FPSIMD-1-0 pass
11591 13:40:07.875123 arm64_fp-stress_FPSIMD-1-1 pass
11592 13:40:07.878028 arm64_fp-stress_FPSIMD-2-0 pass
11593 13:40:07.878218 arm64_fp-stress_FPSIMD-2-1 pass
11594 13:40:07.881254 arm64_fp-stress_FPSIMD-3-0 pass
11595 13:40:07.884673 arm64_fp-stress_FPSIMD-3-1 pass
11596 13:40:07.888028 arm64_fp-stress_FPSIMD-4-0 pass
11597 13:40:07.891835 arm64_fp-stress_FPSIMD-4-1 pass
11598 13:40:07.895252 arm64_fp-stress_FPSIMD-5-0 pass
11599 13:40:07.898488 arm64_fp-stress_FPSIMD-5-1 pass
11600 13:40:07.898961 arm64_fp-stress_FPSIMD-6-0 pass
11601 13:40:07.901468 arm64_fp-stress_FPSIMD-6-1 pass
11602 13:40:07.905389 arm64_fp-stress_FPSIMD-7-0 pass
11603 13:40:07.908094 arm64_fp-stress_FPSIMD-7-1 pass
11604 13:40:07.911564 arm64_fp-stress pass
11605 13:40:07.914647 arm64_sve-ptrace_SVE_not_available skip
11606 13:40:07.915106 arm64_sve-ptrace skip
11607 13:40:07.921664 arm64_sve-probe-vls_SVE_not_available skip
11608 13:40:07.922131 arm64_sve-probe-vls skip
11609 13:40:07.924983 arm64_vec-syscfg_SVE_not_supported skip
11610 13:40:07.927700 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11611 13:40:07.934619 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11612 13:40:07.937796 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11613 13:40:07.941373 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11614 13:40:07.944128 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11615 13:40:07.951410 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11616 13:40:07.954416 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11617 13:40:07.957893 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11618 13:40:07.960768 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11619 13:40:07.964417 arm64_vec-syscfg_SME_not_supported skip
11620 13:40:07.967390 arm64_vec-syscfg_SME_not_supported_dup2 skip
11621 13:40:07.973884 arm64_vec-syscfg_SME_not_supported_dup3 skip
11622 13:40:07.977448 arm64_vec-syscfg_SME_not_supported_dup4 skip
11623 13:40:07.980612 arm64_vec-syscfg_SME_not_supported_dup5 skip
11624 13:40:07.984229 arm64_vec-syscfg_SME_not_supported_dup6 skip
11625 13:40:07.990462 arm64_vec-syscfg_SME_not_supported_dup7 skip
11626 13:40:07.994037 arm64_vec-syscfg_SME_not_supported_dup8 skip
11627 13:40:07.997252 arm64_vec-syscfg_SME_not_supported_dup9 skip
11628 13:40:08.000118 arm64_vec-syscfg_SME_not_supported_dup10 skip
11629 13:40:08.003579 arm64_vec-syscfg pass
11630 13:40:08.006654 arm64_za-fork_skipped pass
11631 13:40:08.006899 arm64_za-fork pass
11632 13:40:08.010301 arm64_za-ptrace_SME_not_available skip
11633 13:40:08.013350 arm64_za-ptrace skip
11634 13:40:08.013646 arm64_check_buffer_fill skip
11635 13:40:08.016991 arm64_check_child_memory skip
11636 13:40:08.020203 arm64_check_gcr_el1_cswitch skip
11637 13:40:08.023202 arm64_check_ksm_options skip
11638 13:40:08.026754 arm64_check_mmap_options skip
11639 13:40:08.030067 arm64_check_prctl_check_basic_read pass
11640 13:40:08.032982 arm64_check_prctl_NONE pass
11641 13:40:08.033208 arm64_check_prctl_SYNC skip
11642 13:40:08.036637 arm64_check_prctl_ASYNC skip
11643 13:40:08.040398 arm64_check_prctl_SYNC_ASYNC skip
11644 13:40:08.043270 arm64_check_prctl pass
11645 13:40:08.046215 arm64_check_tags_inclusion skip
11646 13:40:08.046439 arm64_check_user_mem skip
11647 13:40:08.053279 arm64_btitest_nohint_func_call_using_br_x0 skip
11648 13:40:08.056368 arm64_btitest_nohint_func_call_using_br_x16 skip
11649 13:40:08.059557 arm64_btitest_nohint_func_call_using_blr skip
11650 13:40:08.066333 arm64_btitest_bti_none_func_call_using_br_x0 skip
11651 13:40:08.069398 arm64_btitest_bti_none_func_call_using_br_x16 skip
11652 13:40:08.072876 arm64_btitest_bti_none_func_call_using_blr skip
11653 13:40:08.076807 arm64_btitest_bti_c_func_call_using_br_x0 skip
11654 13:40:08.082984 arm64_btitest_bti_c_func_call_using_br_x16 skip
11655 13:40:08.086559 arm64_btitest_bti_c_func_call_using_blr skip
11656 13:40:08.089402 arm64_btitest_bti_j_func_call_using_br_x0 skip
11657 13:40:08.092461 arm64_btitest_bti_j_func_call_using_br_x16 skip
11658 13:40:08.099580 arm64_btitest_bti_j_func_call_using_blr skip
11659 13:40:08.102469 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11660 13:40:08.105917 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11661 13:40:08.112548 arm64_btitest_bti_jc_func_call_using_blr skip
11662 13:40:08.115846 arm64_btitest_paciasp_func_call_using_br_x0 skip
11663 13:40:08.118746 arm64_btitest_paciasp_func_call_using_br_x16 skip
11664 13:40:08.122204 arm64_btitest_paciasp_func_call_using_blr skip
11665 13:40:08.125913 arm64_btitest pass
11666 13:40:08.128689 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11667 13:40:08.135749 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11668 13:40:08.138707 arm64_nobtitest_nohint_func_call_using_blr skip
11669 13:40:08.142209 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11670 13:40:08.148798 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11671 13:40:08.152226 arm64_nobtitest_bti_none_func_call_using_blr skip
11672 13:40:08.155575 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11673 13:40:08.161846 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11674 13:40:08.165193 arm64_nobtitest_bti_c_func_call_using_blr skip
11675 13:40:08.168421 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11676 13:40:08.175104 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11677 13:40:08.178742 arm64_nobtitest_bti_j_func_call_using_blr skip
11678 13:40:08.181733 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11679 13:40:08.188502 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11680 13:40:08.191909 arm64_nobtitest_bti_jc_func_call_using_blr skip
11681 13:40:08.194961 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11682 13:40:08.201579 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11683 13:40:08.205097 arm64_nobtitest_paciasp_func_call_using_blr skip
11684 13:40:08.208039 arm64_nobtitest pass
11685 13:40:08.211652 arm64_hwcap_cpuinfo_match_RNG pass
11686 13:40:08.212069 arm64_hwcap_sigill_RNG skip
11687 13:40:08.215010 arm64_hwcap_cpuinfo_match_SME pass
11688 13:40:08.217826 arm64_hwcap_sigill_SME pass
11689 13:40:08.221589 arm64_hwcap_cpuinfo_match_SVE pass
11690 13:40:08.224740 arm64_hwcap_sigill_SVE pass
11691 13:40:08.228269 arm64_hwcap_cpuinfo_match_SVE_2 pass
11692 13:40:08.231259 arm64_hwcap_sigill_SVE_2 skip
11693 13:40:08.234380 arm64_hwcap_cpuinfo_match_SVE_AES pass
11694 13:40:08.237869 arm64_hwcap_sigill_SVE_AES skip
11695 13:40:08.241388 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11696 13:40:08.244752 arm64_hwcap_sigill_SVE2_PMULL skip
11697 13:40:08.247770 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11698 13:40:08.250748 arm64_hwcap_sigill_SVE2_BITPERM skip
11699 13:40:08.254383 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11700 13:40:08.257815 arm64_hwcap_sigill_SVE2_SHA3 skip
11701 13:40:08.260887 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11702 13:40:08.264303 arm64_hwcap_sigill_SVE2_SM4 skip
11703 13:40:08.267801 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11704 13:40:08.270804 arm64_hwcap_sigill_SVE2_I8MM skip
11705 13:40:08.274227 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11706 13:40:08.277246 arm64_hwcap_sigill_SVE2_F32MM skip
11707 13:40:08.280463 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11708 13:40:08.284130 arm64_hwcap_sigill_SVE2_F64MM skip
11709 13:40:08.287293 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11710 13:40:08.290754 arm64_hwcap_sigill_SVE2_BF16 skip
11711 13:40:08.293860 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11712 13:40:08.297440 arm64_hwcap_sigill_SVE2_EBF16 skip
11713 13:40:08.300524 arm64_hwcap pass
11714 13:40:08.300941 arm64_ptrace_read_tpidr_one pass
11715 13:40:08.303998 arm64_ptrace_write_tpidr_one pass
11716 13:40:08.307174 arm64_ptrace_verify_tpidr_one pass
11717 13:40:08.310534 arm64_ptrace_count_tpidrs pass
11718 13:40:08.314044 arm64_ptrace_tpidr2_write pass
11719 13:40:08.316995 arm64_ptrace_tpidr2_read pass
11720 13:40:08.320518 arm64_ptrace_write_tpidr_only pass
11721 13:40:08.321088 arm64_ptrace pass
11722 13:40:08.323496 arm64_syscall-abi_getpid_FPSIMD pass
11723 13:40:08.326868 arm64_syscall-abi_sched_yield_FPSIMD pass
11724 13:40:08.330071 arm64_syscall-abi pass
11725 13:40:08.333935 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11726 13:40:08.340384 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11727 13:40:08.343395 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11728 13:40:08.346832 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11729 13:40:08.353648 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11730 13:40:08.354070 arm64_tpidr2 pass
11731 13:40:08.360307 + ../../utils/send-to-lava.sh ./output/result.txt
11732 13:40:08.363453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11733 13:40:08.364218 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11735 13:40:08.369875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11736 13:40:08.370549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11738 13:40:08.376687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11739 13:40:08.377396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11741 13:40:08.383258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11742 13:40:08.383963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11744 13:40:08.389741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11745 13:40:08.390420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11747 13:40:08.426756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11748 13:40:08.427526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11750 13:40:08.476515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11751 13:40:08.477475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11753 13:40:08.525161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11754 13:40:08.525885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11756 13:40:08.564411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11757 13:40:08.564716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11759 13:40:08.599798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11760 13:40:08.600088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11762 13:40:08.642420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11763 13:40:08.642715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11765 13:40:08.679897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11766 13:40:08.680175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11768 13:40:08.711113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11769 13:40:08.711409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11771 13:40:08.747691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11772 13:40:08.747995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11774 13:40:08.794502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11775 13:40:08.794790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11777 13:40:08.834322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11778 13:40:08.834647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11780 13:40:08.874124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11781 13:40:08.874415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11783 13:40:08.912069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11784 13:40:08.912575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11786 13:40:08.955212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11787 13:40:08.955504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11789 13:40:08.992236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11790 13:40:08.992507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11792 13:40:09.030017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11793 13:40:09.030312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11795 13:40:09.065272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11796 13:40:09.065555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11798 13:40:09.106072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11799 13:40:09.106355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11801 13:40:09.144503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11802 13:40:09.144796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11804 13:40:09.191216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11805 13:40:09.191491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11807 13:40:09.237959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11808 13:40:09.238246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11810 13:40:09.288868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11811 13:40:09.289590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11813 13:40:09.334409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11814 13:40:09.335139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11816 13:40:09.379140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
11818 13:40:09.381931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
11819 13:40:09.423499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
11820 13:40:09.423795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
11822 13:40:09.464681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
11823 13:40:09.465450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
11825 13:40:09.514882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
11826 13:40:09.515606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
11828 13:40:09.568536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
11829 13:40:09.569260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
11831 13:40:09.614051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
11832 13:40:09.614931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
11834 13:40:09.663180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
11835 13:40:09.663484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
11837 13:40:09.701039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11838 13:40:09.701321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11840 13:40:09.745129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11841 13:40:09.745644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11843 13:40:09.793584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11844 13:40:09.794339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11846 13:40:09.844487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11847 13:40:09.845210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11849 13:40:09.888182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11850 13:40:09.888916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11852 13:40:09.936496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11853 13:40:09.937205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11855 13:40:09.981903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11857 13:40:09.984971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11858 13:40:10.020339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11859 13:40:10.020608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11861 13:40:10.054512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11862 13:40:10.054797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11864 13:40:10.092077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
11865 13:40:10.092370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
11867 13:40:10.128793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
11868 13:40:10.129076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
11870 13:40:10.167586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
11871 13:40:10.167876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
11873 13:40:10.206860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
11874 13:40:10.207148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
11876 13:40:10.244125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
11877 13:40:10.244431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
11879 13:40:10.286839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
11880 13:40:10.287108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
11882 13:40:10.330479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
11883 13:40:10.330779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
11885 13:40:10.368945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
11886 13:40:10.369232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
11888 13:40:10.408506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
11889 13:40:10.408800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
11891 13:40:10.455910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
11892 13:40:10.456192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
11894 13:40:10.496694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
11895 13:40:10.496968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
11897 13:40:10.542534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
11898 13:40:10.542838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
11900 13:40:10.582147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
11901 13:40:10.582427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
11903 13:40:10.628761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
11904 13:40:10.629055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
11906 13:40:10.667808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
11907 13:40:10.668085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
11909 13:40:10.702760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
11910 13:40:10.703056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
11912 13:40:10.737274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
11913 13:40:10.737615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
11915 13:40:10.773858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
11916 13:40:10.774140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
11918 13:40:10.809385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
11919 13:40:10.810066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
11921 13:40:10.858095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
11922 13:40:10.858803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
11924 13:40:10.908142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
11925 13:40:10.908830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
11927 13:40:10.951532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
11928 13:40:10.951816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
11930 13:40:10.987962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
11931 13:40:10.988249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
11933 13:40:11.022643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
11934 13:40:11.022911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
11936 13:40:11.064426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
11937 13:40:11.064723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
11939 13:40:11.101268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
11940 13:40:11.101590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
11942 13:40:11.141005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
11943 13:40:11.141332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
11945 13:40:11.177189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
11946 13:40:11.177506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
11948 13:40:11.217562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
11949 13:40:11.218055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
11951 13:40:11.258980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
11952 13:40:11.259263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
11954 13:40:11.295795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
11955 13:40:11.296065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
11957 13:40:11.335617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
11958 13:40:11.335905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
11960 13:40:11.376036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
11961 13:40:11.376303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
11963 13:40:11.409716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
11964 13:40:11.409985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
11966 13:40:11.449883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
11967 13:40:11.450167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
11969 13:40:11.488717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
11970 13:40:11.489009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
11972 13:40:11.535778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
11973 13:40:11.536069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
11975 13:40:11.569503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
11976 13:40:11.569776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
11978 13:40:11.608129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
11979 13:40:11.608393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
11981 13:40:11.641051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
11982 13:40:11.641340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
11984 13:40:11.672667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
11986 13:40:11.675702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
11987 13:40:11.714636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
11988 13:40:11.714948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
11990 13:40:11.762265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
11991 13:40:11.762994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
11993 13:40:11.813024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
11994 13:40:11.813340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
11996 13:40:11.843302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
11997 13:40:11.843575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
11999 13:40:11.879471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12000 13:40:11.879795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12002 13:40:11.909535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12003 13:40:11.909808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12005 13:40:11.950063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12007 13:40:11.953207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12008 13:40:11.992668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12009 13:40:11.993484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12011 13:40:12.036456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12012 13:40:12.037178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12014 13:40:12.082067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12015 13:40:12.082791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12017 13:40:12.132538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12018 13:40:12.133391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12020 13:40:12.181789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12021 13:40:12.182549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12023 13:40:12.230590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12024 13:40:12.231352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12026 13:40:12.280230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12027 13:40:12.281029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12029 13:40:12.332065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12030 13:40:12.332832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12032 13:40:12.382339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12033 13:40:12.383045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12035 13:40:12.435202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12036 13:40:12.436164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12038 13:40:12.482297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12039 13:40:12.483044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12041 13:40:12.530518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12042 13:40:12.531344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12044 13:40:12.576618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12045 13:40:12.577501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12047 13:40:12.623127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12048 13:40:12.624059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12050 13:40:12.671870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12051 13:40:12.672645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12053 13:40:12.718809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12054 13:40:12.719890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12056 13:40:12.763999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12057 13:40:12.764772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12059 13:40:12.812440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12060 13:40:12.813254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12062 13:40:12.864355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12063 13:40:12.865138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12065 13:40:12.913087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12066 13:40:12.913897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12068 13:40:12.957336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12069 13:40:12.958181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12071 13:40:13.004975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12072 13:40:13.005756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12074 13:40:13.055952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12075 13:40:13.056777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12077 13:40:13.101896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12078 13:40:13.102639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12080 13:40:13.141049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12081 13:40:13.141331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12083 13:40:13.174769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12084 13:40:13.175041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12086 13:40:13.215193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12087 13:40:13.215493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12089 13:40:13.256171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12090 13:40:13.256459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12092 13:40:13.299843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12093 13:40:13.300602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12095 13:40:13.346576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12096 13:40:13.347369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12098 13:40:13.392541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12099 13:40:13.392807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12101 13:40:13.431430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12102 13:40:13.431703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12104 13:40:13.466010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12105 13:40:13.466306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12107 13:40:13.500367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12108 13:40:13.500656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12110 13:40:13.534769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12111 13:40:13.535059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12113 13:40:13.563936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12114 13:40:13.564219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12116 13:40:13.602375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12117 13:40:13.602648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12119 13:40:13.643416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12120 13:40:13.643696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12122 13:40:13.683133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12123 13:40:13.683399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12125 13:40:13.714922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12126 13:40:13.715182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12128 13:40:13.747876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12129 13:40:13.748265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12131 13:40:13.794118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12132 13:40:13.794898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12134 13:40:13.835782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12135 13:40:13.836539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12137 13:40:13.880741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12138 13:40:13.881641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12140 13:40:13.924259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12141 13:40:13.925010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12143 13:40:13.973241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12144 13:40:13.973999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12146 13:40:14.018678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12147 13:40:14.019374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12149 13:40:14.070688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12150 13:40:14.071404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12152 13:40:14.112807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12153 13:40:14.113506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12155 13:40:14.163913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12156 13:40:14.164636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12158 13:40:14.207837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12159 13:40:14.208557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12161 13:40:14.259062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12162 13:40:14.259798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12164 13:40:14.307665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12165 13:40:14.308371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12167 13:40:14.354371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12168 13:40:14.355101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12170 13:40:14.395397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12171 13:40:14.396124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12173 13:40:14.442791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12174 13:40:14.443607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12176 13:40:14.488286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12177 13:40:14.489082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12179 13:40:14.541439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12180 13:40:14.542207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12182 13:40:14.586673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12183 13:40:14.587715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12185 13:40:14.629223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12186 13:40:14.629545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12188 13:40:14.664874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12190 13:40:14.668308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12191 13:40:14.706418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12192 13:40:14.706688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12194 13:40:14.744065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12195 13:40:14.744351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12197 13:40:14.776780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12198 13:40:14.777052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12200 13:40:14.816748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12201 13:40:14.817015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12203 13:40:14.856607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12204 13:40:14.856896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12206 13:40:14.894049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12208 13:40:14.897100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12209 13:40:14.935163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12210 13:40:14.935446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12212 13:40:14.968916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12213 13:40:14.969194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12215 13:40:15.000667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12216 13:40:15.000957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12218 13:40:15.044426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12220 13:40:15.047117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12221 13:40:15.094662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12223 13:40:15.097440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12224 13:40:15.143051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12225 13:40:15.143331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12227 13:40:15.180306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12228 13:40:15.180592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12230 13:40:15.213743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12231 13:40:15.214041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12233 13:40:15.248678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12234 13:40:15.248970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12236 13:40:15.298366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12237 13:40:15.298639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12239 13:40:15.336814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12240 13:40:15.337109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12242 13:40:15.375294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12243 13:40:15.375577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12245 13:40:15.410534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12246 13:40:15.410819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12248 13:40:15.443715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12249 13:40:15.444018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12251 13:40:15.484449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12252 13:40:15.484748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12254 13:40:15.519317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12255 13:40:15.519581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12257 13:40:15.554308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12258 13:40:15.554638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12260 13:40:15.590708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12261 13:40:15.590977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12263 13:40:15.624830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12264 13:40:15.625135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12266 13:40:15.660682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12267 13:40:15.660785 + set +x
12268 13:40:15.661061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12270 13:40:15.667620 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14063009_1.6.2.3.5>
12271 13:40:15.667884 Received signal: <ENDRUN> 1_kselftest-arm64 14063009_1.6.2.3.5
12272 13:40:15.667970 Ending use of test pattern.
12273 13:40:15.668050 Ending test lava.1_kselftest-arm64 (14063009_1.6.2.3.5), duration 29.55
12275 13:40:15.670976 <LAVA_TEST_RUNNER EXIT>
12276 13:40:15.671341 ok: lava_test_shell seems to have completed
12277 13:40:15.672639 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12278 13:40:15.672841 end: 3.1 lava-test-shell (duration 00:00:30) [common]
12279 13:40:15.672985 end: 3 lava-test-retry (duration 00:00:30) [common]
12280 13:40:15.673120 start: 4 finalize (timeout 00:07:30) [common]
12281 13:40:15.673266 start: 4.1 power-off (timeout 00:00:30) [common]
12282 13:40:15.673479 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
12283 13:40:15.757010 >> Command sent successfully.
12284 13:40:15.767606 Returned 0 in 0 seconds
12285 13:40:15.869005 end: 4.1 power-off (duration 00:00:00) [common]
12287 13:40:15.870555 start: 4.2 read-feedback (timeout 00:07:30) [common]
12288 13:40:15.872022 Listened to connection for namespace 'common' for up to 1s
12289 13:40:16.872568 Finalising connection for namespace 'common'
12290 13:40:16.873204 Disconnecting from shell: Finalise
12291 13:40:16.873680 / #
12292 13:40:16.974660 end: 4.2 read-feedback (duration 00:00:01) [common]
12293 13:40:16.975416 end: 4 finalize (duration 00:00:01) [common]
12294 13:40:16.976115 Cleaning after the job
12295 13:40:16.976814 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/ramdisk
12296 13:40:16.986912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/kernel
12297 13:40:17.016485 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/dtb
12298 13:40:17.016806 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/nfsrootfs
12299 13:40:17.084532 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063009/tftp-deploy-umrz_1vp/modules
12300 13:40:17.090216 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063009
12301 13:40:17.646080 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063009
12302 13:40:17.646255 Job finished correctly